diff options
Diffstat (limited to 'contrib/gcc/config/i386/i386.md')
-rw-r--r-- | contrib/gcc/config/i386/i386.md | 419 |
1 files changed, 299 insertions, 120 deletions
diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md index 0c0cf5f..c2cca61 100644 --- a/contrib/gcc/config/i386/i386.md +++ b/contrib/gcc/config/i386/i386.md @@ -1735,9 +1735,14 @@ (set_attr "mode" "SI") (set_attr "length_immediate" "1")]) +; The first alternative is used only to compute proper length of instruction. +; Reload's algorithm does not take into account the cost of spill instructions +; needed to free register in given class, so avoid it from choosing the first +; alternative when eax is not available. + (define_insn "*movsi_1" - [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!rm,!*Y,!rm,!*Y") - (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,rm,*Y,*Y"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=*?a,r,*?a,m,!*y,!rm,!*y,!*Y,!rm,!*Y") + (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,rm,*y,*y,rm,*Y,*Y"))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" { switch (get_attr_type (insn)) @@ -1748,6 +1753,8 @@ return "movd\t{%1, %0|%0, %1}"; case TYPE_MMX: + if (get_attr_mode (insn) == DImode) + return "movq\t{%1, %0|%0, %1}"; return "movd\t{%1, %0|%0, %1}"; case TYPE_LEA: @@ -1760,17 +1767,17 @@ } } [(set (attr "type") - (cond [(eq_attr "alternative" "4,5") + (cond [(eq_attr "alternative" "4,5,6") (const_string "mmx") - (eq_attr "alternative" "6,7,8") + (eq_attr "alternative" "7,8,9") (const_string "sse") (and (ne (symbol_ref "flag_pic") (const_int 0)) (match_operand:SI 1 "symbolic_operand" "")) (const_string "lea") ] (const_string "imov"))) - (set_attr "modrm" "0,*,0,*,*,*,*,*,*") - (set_attr "mode" "SI,SI,SI,SI,SI,SI,TI,SI,SI")]) + (set_attr "modrm" "0,*,0,*,*,*,*,*,*,*") + (set_attr "mode" "SI,SI,SI,SI,SI,SI,DI,TI,SI,SI")]) ;; Stores and loads of ax to arbitary constant address. ;; We fake an second form of instruction to force reload to load address @@ -1843,8 +1850,13 @@ [(set_attr "type" "push") (set_attr "mode" "QI")]) +; The first alternative is used only to compute proper length of instruction. +; Reload's algorithm does not take into account the cost of spill instructions +; needed to free register in given class, so avoid it from choosing the first +; alternative when eax is not available. + (define_insn "*movhi_1" - [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m") + [(set (match_operand:HI 0 "nonimmediate_operand" "=*?a,r,r,*?a,r,m") (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))] "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" { @@ -2462,7 +2474,7 @@ (set_attr "length_immediate" "1")]) (define_insn "*movdi_2" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,*Y,!*Y") + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y") (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))] "!TARGET_64BIT && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" @@ -2715,8 +2727,8 @@ (set (mem:SF (reg:DI 7)) (match_dup 1))]) (define_insn "*movsf_1" - [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m") - (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y") + (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf,rm,*y,*y"))] "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) && (reload_in_progress || reload_completed || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE) @@ -2754,7 +2766,10 @@ case 4: return "mov{l}\t{%1, %0|%0, %1}"; case 5: - return "pxor\t%0, %0"; + if (TARGET_SSE2) + return "pxor\t%0, %0"; + else + return "xorps\t%0, %0"; case 6: if (TARGET_PARTIAL_REG_DEPENDENCY) return "movaps\t{%1, %0|%0, %1}"; @@ -2764,12 +2779,19 @@ case 8: return "movss\t{%1, %0|%0, %1}"; + case 9: + case 10: + return "movd\t{%1, %0|%0, %1}"; + + case 11: + return "movq\t{%1, %0|%0, %1}"; + default: abort(); } } - [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse") - (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")]) + [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse,mmx,mmx,mmx") + (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI,DI")]) (define_insn "*swapsf" [(set (match_operand:SF 0 "register_operand" "+f") @@ -5129,7 +5151,7 @@ (define_expand "floatsidf2" [(set (match_operand:DF 0 "register_operand" "") (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))] - "" + "TARGET_80387 || TARGET_SSE2" "") (define_insn "*floatsidf2_i387" @@ -7332,45 +7354,85 @@ (set_attr "prefix_0f" "0,0,1") (set_attr "mode" "HI")]) -(define_insn "mulqi3" +(define_expand "mulqi3" + [(parallel [(set (match_operand:QI 0 "register_operand" "") + (mult:QI (match_operand:QI 1 "nonimmediate_operand" "") + (match_operand:QI 2 "register_operand" ""))) + (clobber (reg:CC 17))])] + "TARGET_QIMODE_MATH" + "") + +(define_insn "*mulqi3_1" [(set (match_operand:QI 0 "register_operand" "=a") - (mult:QI (match_operand:QI 1 "register_operand" "%0") + (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0") (match_operand:QI 2 "nonimmediate_operand" "qm"))) (clobber (reg:CC 17))] - "TARGET_QIMODE_MATH" + "TARGET_QIMODE_MATH + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{b}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) -(define_insn "umulqihi3" +(define_expand "umulqihi3" + [(parallel [(set (match_operand:HI 0 "register_operand" "") + (mult:HI (zero_extend:HI + (match_operand:QI 1 "nonimmediate_operand" "")) + (zero_extend:HI + (match_operand:QI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "TARGET_QIMODE_MATH" + "") + +(define_insn "*umulqihi3_1" [(set (match_operand:HI 0 "register_operand" "=a") - (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0")) + (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) (clobber (reg:CC 17))] - "TARGET_QIMODE_MATH" + "TARGET_QIMODE_MATH + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{b}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) -(define_insn "mulqihi3" +(define_expand "mulqihi3" + [(parallel [(set (match_operand:HI 0 "register_operand" "") + (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")) + (sign_extend:HI (match_operand:QI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "TARGET_QIMODE_MATH" + "") + +(define_insn "*mulqihi3_insn" [(set (match_operand:HI 0 "register_operand" "=a") - (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0")) + (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) (clobber (reg:CC 17))] - "TARGET_QIMODE_MATH" + "TARGET_QIMODE_MATH + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{b}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) -(define_insn "umulditi3" +(define_expand "umulditi3" + [(parallel [(set (match_operand:TI 0 "register_operand" "") + (mult:TI (zero_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "")) + (zero_extend:TI + (match_operand:DI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "TARGET_64BIT" + "") + +(define_insn "*umulditi3_insn" [(set (match_operand:TI 0 "register_operand" "=A") - (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0")) + (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{q}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") @@ -7378,70 +7440,132 @@ (set_attr "mode" "DI")]) ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers -(define_insn "umulsidi3" +(define_expand "umulsidi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (zero_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "")) + (zero_extend:DI + (match_operand:SI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "!TARGET_64BIT" + "") + +(define_insn "*umulsidi3_insn" [(set (match_operand:DI 0 "register_operand" "=A") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) + (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) (clobber (reg:CC 17))] - "!TARGET_64BIT" + "!TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") (set_attr "length_immediate" "0") (set_attr "mode" "SI")]) -(define_insn "mulditi3" +(define_expand "mulditi3" + [(parallel [(set (match_operand:TI 0 "register_operand" "") + (mult:TI (sign_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "")) + (sign_extend:TI + (match_operand:DI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "TARGET_64BIT" + "") + +(define_insn "*mulditi3_insn" [(set (match_operand:TI 0 "register_operand" "=A") - (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0")) + (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{q}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "DI")]) -(define_insn "mulsidi3" +(define_expand "mulsidi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (sign_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "")) + (sign_extend:DI + (match_operand:SI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "!TARGET_64BIT" + "") + +(define_insn "*mulsidi3_insn" [(set (match_operand:DI 0 "register_operand" "=A") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) + (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) (clobber (reg:CC 17))] - "!TARGET_64BIT" + "!TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{l}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "SI")]) +(define_expand "umuldi3_highpart" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (truncate:DI + (lshiftrt:TI + (mult:TI (zero_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "")) + (zero_extend:TI + (match_operand:DI 2 "register_operand" ""))) + (const_int 64)))) + (clobber (match_scratch:DI 3 "")) + (clobber (reg:CC 17))])] + "TARGET_64BIT" + "") + (define_insn "*umuldi3_highpart_rex64" [(set (match_operand:DI 0 "register_operand" "=d") (truncate:DI (lshiftrt:TI (mult:TI (zero_extend:TI - (match_operand:DI 1 "register_operand" "%a")) + (match_operand:DI 1 "nonimmediate_operand" "%a")) (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))) (const_int 64)))) - (clobber (match_scratch:DI 3 "=a")) + (clobber (match_scratch:DI 3 "=1")) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{q}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") (set_attr "length_immediate" "0") (set_attr "mode" "DI")]) -(define_insn "umulsi3_highpart" +(define_expand "umulsi3_highpart" + [(parallel [(set (match_operand:SI 0 "register_operand" "") + (truncate:SI + (lshiftrt:DI + (mult:DI (zero_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "")) + (zero_extend:DI + (match_operand:SI 2 "register_operand" ""))) + (const_int 32)))) + (clobber (match_scratch:SI 3 "")) + (clobber (reg:CC 17))])] + "" + "") + +(define_insn "*umulsi3_highpart_insn" [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI - (match_operand:SI 1 "register_operand" "%a")) + (match_operand:SI 1 "nonimmediate_operand" "%a")) (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=a")) + (clobber (match_scratch:SI 3 "=1")) (clobber (reg:CC 17))] - "" + "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "mul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") @@ -7453,48 +7577,78 @@ (zero_extend:DI (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI - (match_operand:SI 1 "register_operand" "%a")) + (match_operand:SI 1 "nonimmediate_operand" "%a")) (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32))))) - (clobber (match_scratch:SI 3 "=a")) + (clobber (match_scratch:SI 3 "=1")) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") (set_attr "length_immediate" "0") (set_attr "mode" "SI")]) +(define_expand "smuldi3_highpart" + [(parallel [(set (match_operand:DI 0 "register_operand" "=d") + (truncate:DI + (lshiftrt:TI + (mult:TI (sign_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "")) + (sign_extend:TI + (match_operand:DI 2 "register_operand" ""))) + (const_int 64)))) + (clobber (match_scratch:DI 3 "")) + (clobber (reg:CC 17))])] + "TARGET_64BIT" + "") + (define_insn "*smuldi3_highpart_rex64" [(set (match_operand:DI 0 "register_operand" "=d") (truncate:DI (lshiftrt:TI (mult:TI (sign_extend:TI - (match_operand:DI 1 "register_operand" "%a")) + (match_operand:DI 1 "nonimmediate_operand" "%a")) (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))) (const_int 64)))) - (clobber (match_scratch:DI 3 "=a")) + (clobber (match_scratch:DI 3 "=1")) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{q}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") (set_attr "mode" "DI")]) -(define_insn "smulsi3_highpart" +(define_expand "smulsi3_highpart" + [(parallel [(set (match_operand:SI 0 "register_operand" "") + (truncate:SI + (lshiftrt:DI + (mult:DI (sign_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "")) + (sign_extend:DI + (match_operand:SI 2 "register_operand" ""))) + (const_int 32)))) + (clobber (match_scratch:SI 3 "")) + (clobber (reg:CC 17))])] + "" + "") + +(define_insn "*smulsi3_highpart_insn" [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI - (match_operand:SI 1 "register_operand" "%a")) + (match_operand:SI 1 "nonimmediate_operand" "%a")) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=a")) + (clobber (match_scratch:SI 3 "=1")) (clobber (reg:CC 17))] - "" + "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "imul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") @@ -7505,13 +7659,14 @@ (zero_extend:DI (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI - (match_operand:SI 1 "register_operand" "%a")) + (match_operand:SI 1 "nonimmediate_operand" "%a")) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32))))) - (clobber (match_scratch:SI 3 "=a")) + (clobber (match_scratch:SI 3 "=1")) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") @@ -13541,7 +13696,7 @@ simply pretend the untyped call returns a complex long double value. */ - emit_call_insn (TARGET_80387 + emit_call_insn (TARGET_FLOAT_RETURNS_IN_80387 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG), operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1)) @@ -13856,10 +14011,11 @@ (define_insn "*fop_sf_comm_nosse" [(set (match_operand:SF 0 "register_operand" "=f") (match_operator:SF 3 "binary_fp_operator" - [(match_operand:SF 1 "register_operand" "%0") + [(match_operand:SF 1 "nonimmediate_operand" "%0") (match_operand:SF 2 "nonimmediate_operand" "fm")]))] "TARGET_80387 && !TARGET_SSE_MATH - && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" + && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "* return output_387_binary_op (insn, operands);" [(set (attr "type") (if_then_else (match_operand:SF 3 "mult_operator" "") @@ -13870,10 +14026,11 @@ (define_insn "*fop_sf_comm" [(set (match_operand:SF 0 "register_operand" "=f#x,x#f") (match_operator:SF 3 "binary_fp_operator" - [(match_operand:SF 1 "register_operand" "%0,0") + [(match_operand:SF 1 "nonimmediate_operand" "%0,0") (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))] "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387 - && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" + && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "* return output_387_binary_op (insn, operands);" [(set (attr "type") (if_then_else (eq_attr "alternative" "1") @@ -13886,9 +14043,10 @@ (define_insn "*fop_sf_comm_sse" [(set (match_operand:SF 0 "register_operand" "=x") (match_operator:SF 3 "binary_fp_operator" - [(match_operand:SF 1 "register_operand" "%0") + [(match_operand:SF 1 "nonimmediate_operand" "%0") (match_operand:SF 2 "nonimmediate_operand" "xm")]))] - "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" + "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "* return output_387_binary_op (insn, operands);" [(set_attr "type" "sse") (set_attr "mode" "SF")]) @@ -13896,10 +14054,11 @@ (define_insn "*fop_df_comm_nosse" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 3 "binary_fp_operator" - [(match_operand:DF 1 "register_operand" "%0") + [(match_operand:DF 1 "nonimmediate_operand" "%0") (match_operand:DF 2 "nonimmediate_operand" "fm")]))] "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH) - && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" + && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "* return output_387_binary_op (insn, operands);" [(set (attr "type") (if_then_else (match_operand:SF 3 "mult_operator" "") @@ -13910,10 +14069,11 @@ (define_insn "*fop_df_comm" [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f") (match_operator:DF 3 "binary_fp_operator" - [(match_operand:DF 1 "register_operand" "%0,0") + [(match_operand:DF 1 "nonimmediate_operand" "%0,0") (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))] "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387 - && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" + && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "* return output_387_binary_op (insn, operands);" [(set (attr "type") (if_then_else (eq_attr "alternative" "1") @@ -13926,10 +14086,11 @@ (define_insn "*fop_df_comm_sse" [(set (match_operand:DF 0 "register_operand" "=Y") (match_operator:DF 3 "binary_fp_operator" - [(match_operand:DF 1 "register_operand" "%0") + [(match_operand:DF 1 "nonimmediate_operand" "%0") (match_operand:DF 2 "nonimmediate_operand" "Ym")]))] "TARGET_SSE2 && TARGET_SSE_MATH - && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'" + && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c' + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "* return output_387_binary_op (insn, operands);" [(set_attr "type" "sse") (set_attr "mode" "DF")]) @@ -14563,7 +14724,7 @@ [(set (match_operand:XF 0 "register_operand" "=f") (sqrt:XF (float_extend:XF (match_operand:DF 1 "register_operand" "0"))))] - "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387" + "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" "fsqrt" [(set_attr "type" "fpspc") (set_attr "mode" "XF") @@ -14583,7 +14744,7 @@ [(set (match_operand:XF 0 "register_operand" "=f") (sqrt:XF (float_extend:XF (match_operand:SF 1 "register_operand" "0"))))] - "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387" + "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387" "fsqrt" [(set_attr "type" "fpspc") (set_attr "mode" "XF") @@ -14630,7 +14791,7 @@ (define_insn "sinxf2" [(set (match_operand:XF 0 "register_operand" "=f") (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))] - "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387 + "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 && flag_unsafe_math_optimizations" "fsin" [(set_attr "type" "fpspc") @@ -15750,8 +15911,8 @@ "TARGET_64BIT && TARGET_CMOVE && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" "@ - cmov%C1\t{%2, %0|%0, %2} - cmov%c1\t{%3, %0|%0, %3}" + cmov%O2%C1\t{%2, %0|%0, %2} + cmov%O2%c1\t{%3, %0|%0, %3}" [(set_attr "type" "icmov") (set_attr "mode" "DI")]) @@ -15792,8 +15953,8 @@ "TARGET_CMOVE && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" "@ - cmov%C1\t{%2, %0|%0, %2} - cmov%c1\t{%3, %0|%0, %3}" + cmov%O2%C1\t{%2, %0|%0, %2} + cmov%O2%c1\t{%3, %0|%0, %3}" [(set_attr "type" "icmov") (set_attr "mode" "SI")]) @@ -15814,8 +15975,8 @@ "TARGET_CMOVE && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" "@ - cmov%C1\t{%2, %0|%0, %2} - cmov%c1\t{%3, %0|%0, %3}" + cmov%O2%C1\t{%2, %0|%0, %2} + cmov%O2%c1\t{%3, %0|%0, %3}" [(set_attr "type" "icmov") (set_attr "mode" "HI")]) @@ -15838,8 +15999,8 @@ "@ fcmov%F1\t{%2, %0|%0, %2} fcmov%f1\t{%3, %0|%0, %3} - cmov%C1\t{%2, %0|%0, %2} - cmov%c1\t{%3, %0|%0, %3}" + cmov%O2%C1\t{%2, %0|%0, %2} + cmov%O2%c1\t{%3, %0|%0, %3}" [(set_attr "type" "fcmov,fcmov,icmov,icmov") (set_attr "mode" "SF,SF,SI,SI")]) @@ -15878,8 +16039,8 @@ "@ fcmov%F1\t{%2, %0|%0, %2} fcmov%f1\t{%3, %0|%0, %3} - cmov%C1\t{%2, %0|%0, %2} - cmov%c1\t{%3, %0|%0, %3}" + cmov%O2%C1\t{%2, %0|%0, %2} + cmov%O2%c1\t{%3, %0|%0, %3}" [(set_attr "type" "fcmov,fcmov,icmov,icmov") (set_attr "mode" "DF")]) @@ -15967,12 +16128,13 @@ (define_insn "*minsf_nonieee" [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") - (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0") + (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0") (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) (match_dup 1) (match_dup 2))) (clobber (reg:CC 17))] - "TARGET_SSE && !TARGET_IEEE_FP" + "TARGET_SSE && !TARGET_IEEE_FP + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") (define_split @@ -16049,12 +16211,13 @@ (define_insn "*mindf_nonieee" [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") - (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0") + (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0") (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) (match_dup 1) (match_dup 2))) (clobber (reg:CC 17))] - "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP" + "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") (define_split @@ -16130,12 +16293,13 @@ (define_insn "*maxsf_nonieee" [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") - (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0") + (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0") (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) (match_dup 1) (match_dup 2))) (clobber (reg:CC 17))] - "TARGET_SSE && !TARGET_IEEE_FP" + "TARGET_SSE && !TARGET_IEEE_FP + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") (define_split @@ -16210,12 +16374,13 @@ (define_insn "*maxdf_nonieee" [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") - (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0") + (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0") (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) (match_dup 1) (match_dup 2))) (clobber (reg:CC 17))] - "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP" + "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") (define_split @@ -17947,7 +18112,16 @@ [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D")) (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") (match_operand:V8QI 2 "register_operand" "y")] 32))] - "TARGET_SSE || TARGET_3DNOW_A" + "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT" + ;; @@@ check ordering of operands in intel/nonintel syntax + "maskmovq\t{%2, %1|%1, %2}" + [(set_attr "type" "sse")]) + +(define_insn "mmx_maskmovq_rex" + [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D")) + (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")] 32))] + "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT" ;; @@@ check ordering of operands in intel/nonintel syntax "maskmovq\t{%2, %1|%1, %2}" [(set_attr "type" "sse")]) @@ -18231,17 +18405,19 @@ (define_insn "sse_andti3" [(set (match_operand:TI 0 "register_operand" "=x") - (and:TI (match_operand:TI 1 "register_operand" "%0") + (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE && !TARGET_SSE2" + "TARGET_SSE && !TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "andps\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) (define_insn "*sse_andti3_sse2" [(set (match_operand:TI 0 "register_operand" "=x") - (and:TI (match_operand:TI 1 "register_operand" "%0") + (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" + "TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "pand\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) @@ -18311,17 +18487,19 @@ (define_insn "sse_iorti3" [(set (match_operand:TI 0 "register_operand" "=x") - (ior:TI (match_operand:TI 1 "register_operand" "%0") + (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE && !TARGET_SSE2" + "TARGET_SSE && !TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "orps\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) (define_insn "*sse_iorti3_sse2" [(set (match_operand:TI 0 "register_operand" "=x") - (ior:TI (match_operand:TI 1 "register_operand" "%0") + (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" + "TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "por\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) @@ -18359,17 +18537,19 @@ (define_insn "sse_xorti3" [(set (match_operand:TI 0 "register_operand" "=x") - (xor:TI (match_operand:TI 1 "register_operand" "%0") + (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE && !TARGET_SSE2" + "TARGET_SSE && !TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "xorps\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) (define_insn "*sse_xorti3_sse2" [(set (match_operand:TI 0 "register_operand" "=x") - (xor:TI (match_operand:TI 1 "register_operand" "%0") + (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" + "TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "pxor\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) @@ -18839,14 +19019,14 @@ (plus:V8QI (plus:V8QI (match_operand:V8QI 1 "register_operand" "0") (match_operand:V8QI 2 "nonimmediate_operand" "ym")) - (vec_const:V8QI (parallel [(const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1) - (const_int 1)]))) + (const_vector:V8QI [(const_int 1) + (const_int 1) + (const_int 1) + (const_int 1) + (const_int 1) + (const_int 1) + (const_int 1) + (const_int 1)])) (const_int 1)))] "TARGET_SSE || TARGET_3DNOW_A" "pavgb\t{%2, %0|%0, %2}" @@ -18858,10 +19038,10 @@ (plus:V4HI (plus:V4HI (match_operand:V4HI 1 "register_operand" "0") (match_operand:V4HI 2 "nonimmediate_operand" "ym")) - (vec_const:V4HI (parallel [(const_int 1) - (const_int 1) - (const_int 1) - (const_int 1)]))) + (const_vector:V4HI [(const_int 1) + (const_int 1) + (const_int 1) + (const_int 1)])) (const_int 1)))] "TARGET_SSE || TARGET_3DNOW_A" "pavgw\t{%2, %0|%0, %2}" @@ -19575,12 +19755,11 @@ (match_operand:V4HI 1 "register_operand" "0")) (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) - (vec_const:V4SI - (parallel [(const_int 32768) - (const_int 32768) - (const_int 32768) - (const_int 32768)]))) - (const_int 16))))] + (const_vector:V4SI [(const_int 32768) + (const_int 32768) + (const_int 32768) + (const_int 32768)])) + (const_int 16))))] "TARGET_3DNOW" "pmulhrw\\t{%2, %0|%0, %2}" [(set_attr "type" "mmx")]) |