diff options
Diffstat (limited to 'contrib/gcc/config/frv/frv.c')
| -rw-r--r-- | contrib/gcc/config/frv/frv.c | 1736 |
1 files changed, 757 insertions, 979 deletions
diff --git a/contrib/gcc/config/frv/frv.c b/contrib/gcc/config/frv/frv.c index d09533a..1a75042 100644 --- a/contrib/gcc/config/frv/frv.c +++ b/contrib/gcc/config/frv/frv.c @@ -1,25 +1,28 @@ -/* Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. +/* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2004 + Free Software Foundation, Inc. Contributed by Red Hat, Inc. -This file is part of GNU CC. +This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify +GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. -GNU CC is distributed in the hope that it will be useful, +GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to +along with GCC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "config.h" #include "system.h" +#include "coretypes.h" +#include "tm.h" #include "rtl.h" #include "tree.h" #include "regs.h" @@ -72,7 +75,7 @@ frv_tmp_reg_t; /* conditional expression used */ #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE) -/* the following is not sure in the reg_state bytes, so can have a larger value +/* The following is not sure in the reg_state bytes, so can have a larger value than 0xff. */ #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */ @@ -108,7 +111,7 @@ typedef struct rtx frv_compare_op0; rtx frv_compare_op1; -/* Conditional execution support gathered together in one structure */ +/* Conditional execution support gathered together in one structure. */ typedef struct { /* Linked list of insns to add if the conditional execution conversion was @@ -136,20 +139,20 @@ typedef struct /* Current number of temp registers available. */ int cur_scratch_regs; - /* Number of nested conditional execution blocks */ + /* Number of nested conditional execution blocks. */ int num_nested_cond_exec; /* Map of insns that set up constants in scratch registers. */ bitmap scratch_insns_bitmap; - /* Conditional execution test register (CC0..CC7) */ + /* Conditional execution test register (CC0..CC7). */ rtx cr_reg; /* Conditional execution compare register that is paired with cr_reg, so that nested compares can be done. The csubcc and caddcc instructions don't have enough bits to specify both a CC register to be set and a CR register to do the test on, so the same bit number is used for both. Needless to - say, this is rather inconvient for GCC. */ + say, this is rather inconvenient for GCC. */ rtx nested_cc_reg; /* Extra CR registers used for &&, ||. */ @@ -157,7 +160,7 @@ typedef struct rtx extra_fp_cr; /* Previous CR used in nested if, to make sure we are dealing with the same - nested if as the previous statement. */ + nested if as the previous statement. */ rtx last_nested_if_cr; } frv_ifcvt_t; @@ -167,10 +170,10 @@ static /* GTY(()) */ frv_ifcvt_t frv_ifcvt; /* Map register number to smallest register class. */ enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; -/* Map class letter into register class */ +/* Map class letter into register class. */ enum reg_class reg_class_from_letter[256]; -/* Cached value of frv_stack_info */ +/* Cached value of frv_stack_info. */ static frv_stack_t *frv_stack_cache = (frv_stack_t *)0; /* -mbranch-cost= support */ @@ -194,93 +197,75 @@ const char *frv_sched_lookahead_str; /* -msched-lookahead=n */ int frv_sched_lookahead = 4; /* -msched-lookahead=n */ /* Forward references */ -static int frv_default_flags_for_cpu PARAMS ((void)); -static int frv_string_begins_with PARAMS ((tree, const char *)); -static FRV_INLINE int symbol_ref_small_data_p PARAMS ((rtx)); -static FRV_INLINE int const_small_data_p PARAMS ((rtx)); -static FRV_INLINE int plus_small_data_p PARAMS ((rtx, rtx)); +static int frv_default_flags_for_cpu (void); +static int frv_string_begins_with (tree, const char *); +static FRV_INLINE int const_small_data_p (rtx); +static FRV_INLINE int plus_small_data_p (rtx, rtx); static void frv_print_operand_memory_reference_reg - PARAMS ((FILE *, rtx)); -static void frv_print_operand_memory_reference PARAMS ((FILE *, rtx, int)); -static int frv_print_operand_jump_hint PARAMS ((rtx)); -static FRV_INLINE int frv_regno_ok_for_base_p PARAMS ((int, int)); -static rtx single_set_pattern PARAMS ((rtx)); -static int frv_function_contains_far_jump PARAMS ((void)); -static rtx frv_alloc_temp_reg PARAMS ((frv_tmp_reg_t *, - enum reg_class, - enum machine_mode, - int, int)); -static rtx frv_frame_offset_rtx PARAMS ((int)); -static rtx frv_frame_mem PARAMS ((enum machine_mode, - rtx, int)); -static rtx frv_dwarf_store PARAMS ((rtx, int)); -static void frv_frame_insn PARAMS ((rtx, rtx)); -static void frv_frame_access PARAMS ((frv_frame_accessor_t*, - rtx, int)); -static void frv_frame_access_multi PARAMS ((frv_frame_accessor_t*, - frv_stack_t *, int)); -static void frv_frame_access_standard_regs PARAMS ((enum frv_stack_op, - frv_stack_t *)); -static struct machine_function *frv_init_machine_status PARAMS ((void)); -static int frv_legitimate_memory_operand PARAMS ((rtx, - enum machine_mode, - int)); -static rtx frv_int_to_acc PARAMS ((enum insn_code, - int, rtx)); -static enum machine_mode frv_matching_accg_mode PARAMS ((enum machine_mode)); -static rtx frv_read_argument PARAMS ((tree *)); -static int frv_check_constant_argument PARAMS ((enum insn_code, - int, rtx)); -static rtx frv_legitimize_target PARAMS ((enum insn_code, rtx)); -static rtx frv_legitimize_argument PARAMS ((enum insn_code, - int, rtx)); -static rtx frv_expand_set_builtin PARAMS ((enum insn_code, - tree, rtx)); -static rtx frv_expand_unop_builtin PARAMS ((enum insn_code, - tree, rtx)); -static rtx frv_expand_binop_builtin PARAMS ((enum insn_code, - tree, rtx)); -static rtx frv_expand_cut_builtin PARAMS ((enum insn_code, - tree, rtx)); -static rtx frv_expand_binopimm_builtin PARAMS ((enum insn_code, - tree, rtx)); -static rtx frv_expand_voidbinop_builtin PARAMS ((enum insn_code, - tree)); -static rtx frv_expand_voidtriop_builtin PARAMS ((enum insn_code, - tree)); -static rtx frv_expand_voidaccop_builtin PARAMS ((enum insn_code, - tree)); -static rtx frv_expand_mclracc_builtin PARAMS ((tree)); -static rtx frv_expand_mrdacc_builtin PARAMS ((enum insn_code, - tree)); -static rtx frv_expand_mwtacc_builtin PARAMS ((enum insn_code, - tree)); -static rtx frv_expand_noargs_builtin PARAMS ((enum insn_code)); -static rtx frv_emit_comparison PARAMS ((enum rtx_code, rtx, - rtx)); -static int frv_clear_registers_used PARAMS ((rtx *, void *)); -static void frv_ifcvt_add_insn PARAMS ((rtx, rtx, int)); -static rtx frv_ifcvt_rewrite_mem PARAMS ((rtx, - enum machine_mode, - rtx)); -static rtx frv_ifcvt_load_value PARAMS ((rtx, rtx)); -static void frv_registers_update PARAMS ((rtx, unsigned char [], - int [], int *, int)); -static int frv_registers_used_p PARAMS ((rtx, unsigned char [], - int)); -static int frv_registers_set_p PARAMS ((rtx, unsigned char [], - int)); -static void frv_pack_insns PARAMS ((void)); -static void frv_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); -static void frv_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); -static bool frv_assemble_integer PARAMS ((rtx, unsigned, int)); -static const char * frv_strip_name_encoding PARAMS ((const char *)); -static void frv_encode_section_info PARAMS ((tree, int)); -static void frv_init_builtins PARAMS ((void)); -static rtx frv_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int)); -static bool frv_in_small_data_p PARAMS ((tree)); + (FILE *, rtx); +static void frv_print_operand_memory_reference (FILE *, rtx, int); +static int frv_print_operand_jump_hint (rtx); +static FRV_INLINE int frv_regno_ok_for_base_p (int, int); +static rtx single_set_pattern (rtx); +static int frv_function_contains_far_jump (void); +static rtx frv_alloc_temp_reg (frv_tmp_reg_t *, + enum reg_class, + enum machine_mode, + int, int); +static rtx frv_frame_offset_rtx (int); +static rtx frv_frame_mem (enum machine_mode, rtx, int); +static rtx frv_dwarf_store (rtx, int); +static void frv_frame_insn (rtx, rtx); +static void frv_frame_access (frv_frame_accessor_t*, + rtx, int); +static void frv_frame_access_multi (frv_frame_accessor_t*, + frv_stack_t *, int); +static void frv_frame_access_standard_regs (enum frv_stack_op, + frv_stack_t *); +static struct machine_function *frv_init_machine_status (void); +static int frv_legitimate_memory_operand (rtx, enum machine_mode, int); +static rtx frv_int_to_acc (enum insn_code, int, rtx); +static enum machine_mode frv_matching_accg_mode (enum machine_mode); +static rtx frv_read_argument (tree *); +static int frv_check_constant_argument (enum insn_code, int, rtx); +static rtx frv_legitimize_target (enum insn_code, rtx); +static rtx frv_legitimize_argument (enum insn_code, int, rtx); +static rtx frv_expand_set_builtin (enum insn_code, tree, rtx); +static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx); +static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx); +static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx); +static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx); +static rtx frv_expand_voidbinop_builtin (enum insn_code, tree); +static rtx frv_expand_voidtriop_builtin (enum insn_code, tree); +static rtx frv_expand_voidaccop_builtin (enum insn_code, tree); +static rtx frv_expand_mclracc_builtin (tree); +static rtx frv_expand_mrdacc_builtin (enum insn_code, tree); +static rtx frv_expand_mwtacc_builtin (enum insn_code, tree); +static rtx frv_expand_noargs_builtin (enum insn_code); +static rtx frv_emit_comparison (enum rtx_code, rtx, rtx); +static int frv_clear_registers_used (rtx *, void *); +static void frv_ifcvt_add_insn (rtx, rtx, int); +static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx); +static rtx frv_ifcvt_load_value (rtx, rtx); +static void frv_registers_update (rtx, unsigned char [], + int [], int *, int); +static int frv_registers_used_p (rtx, unsigned char [], int); +static int frv_registers_set_p (rtx, unsigned char [], int); +static int frv_issue_rate (void); +static int frv_use_dfa_pipeline_interface (void); +static void frv_pack_insns (void); +static void frv_function_prologue (FILE *, HOST_WIDE_INT); +static void frv_function_epilogue (FILE *, HOST_WIDE_INT); +static bool frv_assemble_integer (rtx, unsigned, int); +static void frv_init_builtins (void); +static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int); +static void frv_init_libfuncs (void); +static bool frv_in_small_data_p (tree); static void frv_asm_output_mi_thunk - PARAMS ((FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree)); + (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); +static bool frv_rtx_costs (rtx, int, int, int*); +static void frv_asm_out_constructor (rtx, int); +static void frv_asm_out_destructor (rtx, int); /* Initialize the GCC target structure. */ #undef TARGET_ASM_FUNCTION_PROLOGUE @@ -289,38 +274,37 @@ static void frv_asm_output_mi_thunk #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue #undef TARGET_ASM_INTEGER #define TARGET_ASM_INTEGER frv_assemble_integer -#undef TARGET_STRIP_NAME_ENCODING -#define TARGET_STRIP_NAME_ENCODING frv_strip_name_encoding -#undef TARGET_ENCODE_SECTION_INFO -#define TARGET_ENCODE_SECTION_INFO frv_encode_section_info #undef TARGET_INIT_BUILTINS #define TARGET_INIT_BUILTINS frv_init_builtins #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN frv_expand_builtin +#undef TARGET_INIT_LIBFUNCS +#define TARGET_INIT_LIBFUNCS frv_init_libfuncs #undef TARGET_IN_SMALL_DATA_P #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p +#undef TARGET_RTX_COSTS +#define TARGET_RTX_COSTS frv_rtx_costs +#undef TARGET_ASM_CONSTRUCTOR +#define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor +#undef TARGET_ASM_DESTRUCTOR +#define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor #undef TARGET_ASM_OUTPUT_MI_THUNK #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall +#undef TARGET_SCHED_ISSUE_RATE +#define TARGET_SCHED_ISSUE_RATE frv_issue_rate +#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE +#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE frv_use_dfa_pipeline_interface + struct gcc_target targetm = TARGET_INITIALIZER; -/* Given a SYMBOL_REF, return true if it points to small data. */ - -static FRV_INLINE int -symbol_ref_small_data_p (x) - rtx x; -{ - return SDATA_NAME_P (XSTR (x, 0)); -} - /* Given a CONST, return true if the symbol_ref points to small data. */ static FRV_INLINE int -const_small_data_p (x) - rtx x; +const_small_data_p (rtx x) { rtx x0, x1; @@ -328,7 +312,7 @@ const_small_data_p (x) return FALSE; x0 = XEXP (XEXP (x, 0), 0); - if (GET_CODE (x0) != SYMBOL_REF || !SDATA_NAME_P (XSTR (x0, 0))) + if (GET_CODE (x0) != SYMBOL_REF || !SYMBOL_REF_SMALL_P (x0)) return FALSE; x1 = XEXP (XEXP (x, 0), 1); @@ -342,16 +326,14 @@ const_small_data_p (x) /* Given a PLUS, return true if this is a small data reference. */ static FRV_INLINE int -plus_small_data_p (op0, op1) - rtx op0; - rtx op1; +plus_small_data_p (rtx op0, rtx op1) { if (GET_MODE (op0) == SImode && GET_CODE (op0) == REG && REGNO (op0) == SDA_BASE_REG) { if (GET_CODE (op1) == SYMBOL_REF) - return symbol_ref_small_data_p (op1); + return SYMBOL_REF_SMALL_P (op1); if (GET_CODE (op1) == CONST) return const_small_data_p (op1); @@ -362,7 +344,7 @@ plus_small_data_p (op0, op1) static int -frv_default_flags_for_cpu () +frv_default_flags_for_cpu (void) { switch (frv_cpu_type) { @@ -393,11 +375,11 @@ frv_default_flags_for_cpu () `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ void -frv_override_options () +frv_override_options (void) { int regno, i; - /* Set the cpu type */ + /* Set the cpu type. */ if (frv_cpu_string) { if (strcmp (frv_cpu_string, "simple") == 0) @@ -450,26 +432,26 @@ frv_override_options () if (write_symbols == DWARF_DEBUG && flag_pic) error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)"); - /* Change the branch cost value */ + /* Change the branch cost value. */ if (frv_branch_cost_string) frv_branch_cost_int = atoi (frv_branch_cost_string); - /* Change the # of insns to be converted to conditional execution */ + /* Change the # of insns to be converted to conditional execution. */ if (frv_condexec_insns_str) frv_condexec_insns = atoi (frv_condexec_insns_str); - /* Change # of temporary registers used to hold integer constants */ + /* Change # of temporary registers used to hold integer constants. */ if (frv_condexec_temps_str) frv_condexec_temps = atoi (frv_condexec_temps_str); - /* Change scheduling look ahead. */ + /* Change scheduling look ahead. */ if (frv_sched_lookahead_str) frv_sched_lookahead = atoi (frv_sched_lookahead_str); /* A C expression whose value is a register class containing hard register REGNO. In general there is more than one such class; choose a class which is "minimal", meaning that no smaller class - also contains the register. */ + also contains the register. */ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) { @@ -615,9 +597,7 @@ frv_override_options () /* On the FRV, possibly disable VLIW packing which is done by the 2nd scheduling pass at the current time. */ void -frv_optimization_options (level, size) - int level; - int size ATTRIBUTE_UNUSED; +frv_optimization_options (int level, int size ATTRIBUTE_UNUSED) { if (level >= 2) { @@ -634,9 +614,7 @@ frv_optimization_options (level, size) /* Return true if NAME (a STRING_CST node) begins with PREFIX. */ static int -frv_string_begins_with (name, prefix) - tree name; - const char *prefix; +frv_string_begins_with (tree name, const char *prefix) { int prefix_len = strlen (prefix); @@ -644,64 +622,6 @@ frv_string_begins_with (name, prefix) return (TREE_STRING_LENGTH (name) > prefix_len && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0); } - -/* Encode section information of DECL, which is either a VAR_DECL, - FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???. - - For the FRV we want to record: - - - whether the object lives in .sdata/.sbss. - objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR - -*/ - -static void -frv_encode_section_info (decl, first) - tree decl; - int first; -{ - if (! first) - return; - if (TREE_CODE (decl) == VAR_DECL) - { - int size = int_size_in_bytes (TREE_TYPE (decl)); - tree section_name = DECL_SECTION_NAME (decl); - int is_small = 0; - - /* Don't apply the -G flag to internal compiler structures. We - should leave such structures in the main data section, partly - for efficiency and partly because the size of some of them - (such as C++ typeinfos) is not known until later. */ - if (!DECL_ARTIFICIAL (decl) && size > 0 && size <= g_switch_value) - is_small = 1; - - /* If we already know which section the decl should be in, see if - it's a small data section. */ - if (section_name) - { - if (TREE_CODE (section_name) == STRING_CST) - { - if (frv_string_begins_with (section_name, ".sdata")) - is_small = 1; - if (frv_string_begins_with (section_name, ".sbss")) - is_small = 1; - } - else - abort (); - } - - if (is_small) - { - rtx sym_ref = XEXP (DECL_RTL (decl), 0); - char * str = xmalloc (2 + strlen (XSTR (sym_ref, 0))); - - str[0] = SDATA_FLAG_CHAR; - strcpy (&str[1], XSTR (sym_ref, 0)); - XSTR (sym_ref, 0) = str; - } - } -} - /* Zero or more C statements that may conditionally modify two variables `fixed_regs' and `call_used_regs' (both of type `char []') after they have @@ -724,7 +644,7 @@ frv_encode_section_info (decl, first) target switches are opposed to them.) */ void -frv_conditional_register_usage () +frv_conditional_register_usage (void) { int i; @@ -931,7 +851,7 @@ frv_conditional_register_usage () */ frv_stack_t * -frv_stack_info () +frv_stack_info (void) { static frv_stack_t info, zero_info; frv_stack_t *info_ptr = &info; @@ -943,14 +863,15 @@ frv_stack_info () int alignment; int offset; - /* If we've already calculated the values and reload is complete, just return now */ + /* If we've already calculated the values and reload is complete, + just return now. */ if (frv_stack_cache) return frv_stack_cache; - /* Zero all fields */ + /* Zero all fields. */ info = zero_info; - /* Set up the register range information */ + /* Set up the register range information. */ info_ptr->regs[STACK_REGS_GPR].name = "gpr"; info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1; info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST; @@ -1013,7 +934,7 @@ frv_stack_info () } } - /* Iterate over all of the register ranges */ + /* Iterate over all of the register ranges. */ for (range = 0; range < STACK_REGS_MAX; range++) { frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); @@ -1023,7 +944,7 @@ frv_stack_info () int size_2words = 0; int regno; - /* Calculate which registers need to be saved & save area size */ + /* Calculate which registers need to be saved & save area size. */ switch (range) { default: @@ -1059,9 +980,9 @@ frv_stack_info () case STACK_REGS_STDARG: if (varargs_p) { - /* If this is a stdarg function with an non varardic argument split - between registers and the stack, adjust the saved registers - downward */ + /* If this is a stdarg function with a non varardic + argument split between registers and the stack, + adjust the saved registers downward. */ last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD) / UNITS_PER_WORD); @@ -1087,11 +1008,11 @@ frv_stack_info () if (size_1word) { - /* If this is a field, it only takes one word */ + /* If this is a field, it only takes one word. */ if (reg_ptr->field_p) size_1word = UNITS_PER_WORD; - /* Determine which register pairs can be saved together */ + /* Determine which register pairs can be saved together. */ else if (reg_ptr->dword_p && TARGET_DWORD) { for (regno = first; regno < last; regno += 2) @@ -1150,7 +1071,7 @@ frv_stack_info () info_ptr->header_size = 4 * UNITS_PER_WORD; info_ptr->total_size += 4 * UNITS_PER_WORD; - /* Calculate the offsets to save normal register pairs */ + /* Calculate the offsets to save normal register pairs. */ for (range = 0; range < STACK_REGS_MAX; range++) { frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); @@ -1172,7 +1093,7 @@ frv_stack_info () } } - /* Calculate the offsets to save normal single registers */ + /* Calculate the offsets to save normal single registers. */ for (range = 0; range < STACK_REGS_MAX; range++) { frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]); @@ -1256,11 +1177,10 @@ frv_stack_info () } -/* Print the information about the frv stack offsets, etc. when debugging. */ +/* Print the information about the frv stack offsets, etc. when debugging. */ void -frv_debug_stack (info) - frv_stack_t *info; +frv_debug_stack (frv_stack_t *info) { int range; @@ -1319,14 +1239,14 @@ frv_debug_stack (info) /* The following variable value is TRUE if the next output insn should finish cpu cycle. In order words the insn will have packing bit - (which means absence of asm code suffix `.p' on assembler. */ + (which means absence of asm code suffix `.p' on assembler. */ static int frv_insn_packing_flag; /* True if the current function contains a far jump. */ static int -frv_function_contains_far_jump () +frv_function_contains_far_jump (void) { rtx insn = get_insns (); while (insn != NULL @@ -1343,9 +1263,7 @@ frv_function_contains_far_jump () will return correctly. It also does the VLIW packing. */ static void -frv_function_prologue (file, size) - FILE *file; - HOST_WIDE_INT size ATTRIBUTE_UNUSED; +frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { /* If no frame was created, check whether the function uses a call instruction to implement a far jump. If so, save the link in gr3 and @@ -1392,12 +1310,12 @@ frv_function_prologue (file, size) /* Return the next available temporary register in a given class. */ static rtx -frv_alloc_temp_reg (info, class, mode, mark_as_used, no_abort) - frv_tmp_reg_t *info; /* which registers are available */ - enum reg_class class; /* register class desired */ - enum machine_mode mode; /* mode to allocate register with */ - int mark_as_used; /* register not available after allocation */ - int no_abort; /* return NULL instead of aborting */ +frv_alloc_temp_reg ( + frv_tmp_reg_t *info, /* which registers are available */ + enum reg_class class, /* register class desired */ + enum machine_mode mode, /* mode to allocate register with */ + int mark_as_used, /* register not available after allocation */ + int no_abort) /* return NULL instead of aborting */ { int regno = info->next_reg[ (int)class ]; int orig_regno = regno; @@ -1439,8 +1357,7 @@ frv_alloc_temp_reg (info, class, mode, mark_as_used, no_abort) The function returns a constant rtx if OFFSET is small enough, otherwise it loads the constant into register OFFSET_REGNO and returns that. */ static rtx -frv_frame_offset_rtx (offset) - int offset; +frv_frame_offset_rtx (int offset) { rtx offset_rtx = GEN_INT (offset); if (IN_RANGE_P (offset, -2048, 2047)) @@ -1462,10 +1379,7 @@ frv_frame_offset_rtx (offset) /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The prologue and epilogue uses such expressions to access the stack. */ static rtx -frv_frame_mem (mode, base, offset) - enum machine_mode mode; - rtx base; - int offset; +frv_frame_mem (enum machine_mode mode, rtx base, int offset) { return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, base, @@ -1482,9 +1396,7 @@ frv_frame_mem (mode, base, offset) or SEQUENCE that has several sets, each set must be individually marked as frame-related. */ static rtx -frv_dwarf_store (reg, offset) - rtx reg; - int offset; +frv_dwarf_store (rtx reg, int offset) { rtx set = gen_rtx_SET (VOIDmode, gen_rtx_MEM (GET_MODE (reg), @@ -1501,9 +1413,7 @@ frv_dwarf_store (reg, offset) frame-related and has a REG_FRAME_RELATED_EXPR note containing DWARF_PATTERN. */ static void -frv_frame_insn (pattern, dwarf_pattern) - rtx pattern; - rtx dwarf_pattern; +frv_frame_insn (rtx pattern, rtx dwarf_pattern) { rtx insn = emit_insn (pattern); RTX_FRAME_RELATED_P (insn) = 1; @@ -1522,7 +1432,7 @@ frv_frame_insn (pattern, dwarf_pattern) simply be the stack pointer, but if several accesses are being made to a region far away from the stack pointer, it may be more efficient to set up a temporary instead. - + Store instructions will be frame-related and will be annotated with the overall effect of the store. Load instructions will be followed by a (use) to prevent later optimizations from zapping them. @@ -1530,10 +1440,7 @@ frv_frame_insn (pattern, dwarf_pattern) The function takes care of the moves to and from SPRs, using TEMP_REGNO as a temporary in such cases. */ static void -frv_frame_access (accessor, reg, stack_offset) - frv_frame_accessor_t *accessor; - rtx reg; - int stack_offset; +frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset) { enum machine_mode mode = GET_MODE (reg); rtx mem = frv_frame_mem (mode, @@ -1584,10 +1491,9 @@ frv_frame_access (accessor, reg, stack_offset) is the stack information generated by frv_stack_info, and REG_SET is the number of the register set to transfer. */ static void -frv_frame_access_multi (accessor, info, reg_set) - frv_frame_accessor_t *accessor; - frv_stack_t *info; - int reg_set; +frv_frame_access_multi (frv_frame_accessor_t *accessor, + frv_stack_t *info, + int reg_set) { frv_stack_regs_t *regs_info; int regno; @@ -1607,9 +1513,7 @@ frv_frame_access_multi (accessor, info, reg_set) them if OP is FRV_LOAD. INFO is the stack information generated by frv_stack_info. */ static void -frv_frame_access_standard_regs (op, info) - enum frv_stack_op op; - frv_stack_t *info; +frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info) { frv_frame_accessor_t accessor; @@ -1619,7 +1523,7 @@ frv_frame_access_standard_regs (op, info) frv_frame_access_multi (&accessor, info, STACK_REGS_GPR); frv_frame_access_multi (&accessor, info, STACK_REGS_FPR); frv_frame_access_multi (&accessor, info, STACK_REGS_LCR); -} +} /* Called after register allocation to add any instructions needed for the @@ -1632,7 +1536,7 @@ frv_frame_access_standard_regs (op, info) Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 so that the debug info generation code can handle them properly. */ void -frv_expand_prologue () +frv_expand_prologue (void) { frv_stack_t *info = frv_stack_info (); rtx sp = stack_pointer_rtx; @@ -1733,7 +1637,7 @@ frv_expand_prologue () if (info->stdarg_size > 0) emit_insn (gen_blockage ()); - /* Set up pic register/small data register for this function. */ + /* Set up pic register/small data register for this function. */ if (flag_pic && cfun->uses_pic_offset_table) emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO), gen_rtx_REG (Pmode, LR_REGNO), @@ -1742,19 +1646,18 @@ frv_expand_prologue () /* Under frv, all of the work is done via frv_expand_epilogue, but - this function provides a convient place to do cleanup. */ + this function provides a convenient place to do cleanup. */ static void -frv_function_epilogue (file, size) - FILE *file ATTRIBUTE_UNUSED; - HOST_WIDE_INT size ATTRIBUTE_UNUSED; +frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED, + HOST_WIDE_INT size ATTRIBUTE_UNUSED) { frv_stack_cache = (frv_stack_t *)0; - /* zap last used registers for conditional execution. */ - memset ((PTR) &frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg)); + /* Zap last used registers for conditional execution. */ + memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg)); - /* release the bitmap of created insns. */ + /* Release the bitmap of created insns. */ BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap); } @@ -1772,8 +1675,7 @@ frv_function_epilogue (file, size) slots for arguments passed to the current function. */ void -frv_expand_epilogue (sibcall_p) - int sibcall_p; +frv_expand_epilogue (int sibcall_p) { frv_stack_t *info = frv_stack_info (); rtx fp = frame_pointer_rtx; @@ -1874,30 +1776,27 @@ frv_expand_epilogue (sibcall_p) varargs. */ static void -frv_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) - FILE *file; - tree thunk_fndecl ATTRIBUTE_UNUSED; - HOST_WIDE_INT delta; - HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED; - tree function; +frv_asm_output_mi_thunk (FILE *file, + tree thunk_fndecl ATTRIBUTE_UNUSED, + HOST_WIDE_INT delta, + HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, + tree function) { const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0); const char *name_arg0 = reg_names[FIRST_ARG_REGNUM]; const char *name_jmp = reg_names[JUMP_REGNO]; const char *parallel = ((PACKING_FLAG_USED_P ()) ? ".p" : ""); - /* Do the add using an addi if possible */ + /* Do the add using an addi if possible. */ if (IN_RANGE_P (delta, -2048, 2047)) fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0); else { - const char *name_add = reg_names[TEMP_REGNO]; - fprintf (file, "\tsethi%s #hi(", parallel); - fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); - fprintf (file, "),%s\n", name_add); - fprintf (file, "\tsetlo #lo("); - fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); - fprintf (file, "),%s\n", name_add); + const char *const name_add = reg_names[TEMP_REGNO]; + fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n", + parallel, delta, name_add); + fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n", + delta, name_add); fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0); } @@ -1937,7 +1836,7 @@ frv_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp); } - /* Jump to the function address */ + /* Jump to the function address. */ fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]); } @@ -1961,10 +1860,10 @@ frv_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) register can be allocated for ordinary usage, unless you mark it as a fixed register. See `FIXED_REGISTERS' for more information. */ -/* On frv, create a frame whenever we need to create stack */ +/* On frv, create a frame whenever we need to create stack. */ int -frv_frame_pointer_required () +frv_frame_pointer_required (void) { if (! current_function_is_leaf) return TRUE; @@ -1998,9 +1897,7 @@ frv_frame_pointer_required () /* See frv_stack_info for more details on the frv stack frame. */ int -frv_initial_elimination_offset (from, to) - int from; - int to; +frv_initial_elimination_offset (int from, int to) { frv_stack_t *info = frv_stack_info (); int ret = 0; @@ -2009,7 +1906,7 @@ frv_initial_elimination_offset (from, to) ret = info->total_size - info->pretend_size; else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM) - ret = - info->reg_offset[FRAME_POINTER_REGNUM]; + ret = info->reg_offset[FRAME_POINTER_REGNUM]; else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) ret = (info->total_size @@ -2057,12 +1954,11 @@ frv_initial_elimination_offset (from, to) this case. */ void -frv_setup_incoming_varargs (cum, mode, type, pretend_size, second_time) - CUMULATIVE_ARGS *cum; - enum machine_mode mode; - tree type ATTRIBUTE_UNUSED; - int *pretend_size; - int second_time; +frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum, + enum machine_mode mode, + tree type ATTRIBUTE_UNUSED, + int *pretend_size, + int second_time) { if (TARGET_DEBUG_ARG) fprintf (stderr, @@ -2081,7 +1977,7 @@ frv_setup_incoming_varargs (cum, mode, type, pretend_size, second_time) the library function `__builtin_saveregs'. */ rtx -frv_expand_builtin_saveregs () +frv_expand_builtin_saveregs (void) { int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS; @@ -2096,9 +1992,7 @@ frv_expand_builtin_saveregs () /* Expand __builtin_va_start to do the va_start macro. */ void -frv_expand_builtin_va_start (valist, nextarg) - tree valist; - rtx nextarg; +frv_expand_builtin_va_start (tree valist, rtx nextarg) { tree t; int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS; @@ -2125,9 +2019,7 @@ frv_expand_builtin_va_start (valist, nextarg) /* Expand __builtin_va_arg to do the va_arg macro. */ rtx -frv_expand_builtin_va_arg(valist, type) - tree valist; - tree type; +frv_expand_builtin_va_arg (tree valist, tree type) { rtx addr; rtx mem; @@ -2172,8 +2064,7 @@ frv_expand_builtin_va_arg(valist, type) #endif int -frv_expand_block_move (operands) - rtx operands[]; +frv_expand_block_move (rtx operands[]) { rtx orig_dest = operands[0]; rtx orig_src = operands[1]; @@ -2196,11 +2087,11 @@ frv_expand_block_move (operands) int move_bytes; enum machine_mode mode; - /* If this is not a fixed size move, just call memcpy */ + /* If this is not a fixed size move, just call memcpy. */ if (! constp) return FALSE; - /* If this is not a fixed size alignment, abort */ + /* If this is not a fixed size alignment, abort. */ if (GET_CODE (align_rtx) != CONST_INT) abort (); @@ -2222,7 +2113,7 @@ frv_expand_block_move (operands) num_reg = offset = 0; for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) { - /* Calculate the correct offset for src/dest */ + /* Calculate the correct offset for src/dest. */ if (offset == 0) { src_addr = src_reg; @@ -2273,8 +2164,7 @@ frv_expand_block_move (operands) operands[2] is the alignment */ int -frv_expand_block_clear (operands) - rtx operands[]; +frv_expand_block_clear (rtx operands[]) { rtx orig_dest = operands[0]; rtx bytes_rtx = operands[1]; @@ -2290,11 +2180,11 @@ frv_expand_block_clear (operands) int clear_bytes; enum machine_mode mode; - /* If this is not a fixed size move, just call memcpy */ + /* If this is not a fixed size move, just call memcpy. */ if (! constp) return FALSE; - /* If this is not a fixed size alignment, abort */ + /* If this is not a fixed size alignment, abort. */ if (GET_CODE (align_rtx) != CONST_INT) abort (); @@ -2315,12 +2205,12 @@ frv_expand_block_clear (operands) num_reg = offset = 0; for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes)) { - /* Calculate the correct offset for src/dest */ + /* Calculate the correct offset for src/dest. */ dest_addr = ((offset == 0) ? dest_reg : plus_constant (dest_reg, offset)); - /* Generate the appropriate store of gr0 */ + /* Generate the appropriate store of gr0. */ if (bytes >= 4 && align >= 4) mode = SImode; else if (bytes >= 2 && align >= 2) @@ -2338,17 +2228,15 @@ frv_expand_block_clear (operands) /* The following variable is used to output modifiers of assembler - code of the current output insn.. */ + code of the current output insn. */ static rtx *frv_insn_operands; /* The following function is used to add assembler insn code suffix .p - if it is necessary. */ + if it is necessary. */ const char * -frv_asm_output_opcode (f, ptr) - FILE *f; - const char *ptr; +frv_asm_output_opcode (FILE *f, const char *ptr) { int c; @@ -2380,18 +2268,15 @@ frv_asm_output_opcode (f, ptr) /* The following function sets up the packing bit for the current output insn. Remember that the function is not called for asm - insns. */ + insns. */ void -frv_final_prescan_insn (insn, opvec, noperands) - rtx insn; - rtx *opvec; - int noperands ATTRIBUTE_UNUSED; +frv_final_prescan_insn (rtx insn, rtx *opvec, int noperands ATTRIBUTE_UNUSED) { if (! PACKING_FLAG_USED_P()) return; - if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') + if (!INSN_P (insn)) return; frv_insn_operands = opvec; @@ -2403,8 +2288,8 @@ frv_final_prescan_insn (insn, opvec, noperands) Printable instructions will be asm_operands or match one of the .md patterns. Since asm instructions cannot be packed -- and will - therefore have TImode -- this loop terminates on any recognisable - instruction, and on any unrecognisable instruction with TImode. */ + therefore have TImode -- this loop terminates on any recognizable + instruction, and on any unrecognizable instruction with TImode. */ for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn)) { if (NOTE_P (insn)) @@ -2417,7 +2302,7 @@ frv_final_prescan_insn (insn, opvec, noperands) /* Set frv_insn_packing_flag to FALSE if the next instruction should be packed with this one. Set it to TRUE otherwise. If the next - instruction is an asm insntruction, this statement will set the + instruction is an asm instruction, this statement will set the flag to TRUE, and that value will still hold when the asm operands themselves are printed. */ frv_insn_packing_flag = ! (insn && INSN_P (insn) @@ -2436,8 +2321,7 @@ frv_final_prescan_insn (insn, opvec, noperands) /* The default is correct, but we need to make sure the frame gets created. */ rtx -frv_dynamic_chain_address (frame) - rtx frame; +frv_dynamic_chain_address (rtx frame) { cfun->machine->frame_needed = 1; return frame; @@ -2455,9 +2339,7 @@ frv_dynamic_chain_address (frame) address of other frames. */ rtx -frv_return_addr_rtx (count, frame) - int count ATTRIBUTE_UNUSED; - rtx frame; +frv_return_addr_rtx (int count ATTRIBUTE_UNUSED, rtx frame) { cfun->machine->frame_needed = 1; return gen_rtx_MEM (Pmode, plus_constant (frame, 8)); @@ -2472,10 +2354,7 @@ frv_return_addr_rtx (count, frame) GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which this function cannot handle. */ rtx -frv_index_memory (memref, mode, index) - rtx memref; - enum machine_mode mode; - int index; +frv_index_memory (rtx memref, enum machine_mode mode, int index) { rtx base = XEXP (memref, 0); if (GET_CODE (base) == PRE_MODIFY) @@ -2487,9 +2366,7 @@ frv_index_memory (memref, mode, index) /* Print a memory address as an operand to reference that memory location. */ void -frv_print_operand_address (stream, x) - FILE * stream; - rtx x; +frv_print_operand_address (FILE * stream, rtx x) { if (GET_CODE (x) == MEM) x = XEXP (x, 0); @@ -2522,9 +2399,7 @@ frv_print_operand_address (stream, x) static void -frv_print_operand_memory_reference_reg (stream, x) - FILE *stream; - rtx x; +frv_print_operand_memory_reference_reg (FILE * stream, rtx x) { int regno = true_regnum (x); if (GPR_P (regno)) @@ -2536,10 +2411,7 @@ frv_print_operand_memory_reference_reg (stream, x) /* Print a memory reference suitable for the ld/st instructions. */ static void -frv_print_operand_memory_reference (stream, x, addr_offset) - FILE *stream; - rtx x; - int addr_offset; +frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset) { rtx x0 = NULL_RTX; rtx x1 = NULL_RTX; @@ -2611,7 +2483,7 @@ frv_print_operand_memory_reference (stream, x, addr_offset) case SYMBOL_REF: if (x0 && GET_CODE (x0) == REG && REGNO (x0) == SDA_BASE_REG - && symbol_ref_small_data_p (x1)) + && SYMBOL_REF_SMALL_P (x1)) { fputs ("#gprel12(", stream); assemble_name (stream, XSTR (x1, 0)); @@ -2627,7 +2499,8 @@ frv_print_operand_memory_reference (stream, x, addr_offset) { fputs ("#gprel12(", stream); assemble_name (stream, XSTR (XEXP (XEXP (x1, 0), 0), 0)); - fprintf (stream, "+%d)", INTVAL (XEXP (XEXP (x1, 0), 1))); + fprintf (stream, "+"HOST_WIDE_INT_PRINT_DEC")", + INTVAL (XEXP (XEXP (x1, 0), 1))); } else fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x); @@ -2648,8 +2521,7 @@ frv_print_operand_memory_reference (stream, x, addr_offset) #define FRV_JUMP_NOT_LIKELY 0 static int -frv_print_operand_jump_hint (insn) - rtx insn; +frv_print_operand_jump_hint (rtx insn) { rtx note; rtx labelref; @@ -2746,10 +2618,7 @@ frv_print_operand_jump_hint (insn) are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */ void -frv_print_operand (file, x, code) - FILE * file; - rtx x; - int code; +frv_print_operand (FILE * file, rtx x, int code) { HOST_WIDE_INT value; int offset; @@ -2786,7 +2655,7 @@ frv_print_operand (file, x, code) { case '.': - /* Output r0 */ + /* Output r0. */ fputs (reg_names[GPR_R0], file); break; @@ -2794,30 +2663,30 @@ frv_print_operand (file, x, code) fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn)); break; - case SDATA_FLAG_CHAR: - /* Output small data area base register (gr16). */ + case '@': + /* Output small data area base register (gr16). */ fputs (reg_names[SDA_BASE_REG], file); break; case '~': - /* Output pic register (gr17). */ + /* Output pic register (gr17). */ fputs (reg_names[PIC_REGNO], file); break; case '*': - /* Output the temporary integer CCR register */ + /* Output the temporary integer CCR register. */ fputs (reg_names[ICR_TEMP], file); break; case '&': - /* Output the temporary integer CC register */ + /* Output the temporary integer CC register. */ fputs (reg_names[ICC_TEMP], file); break; - /* case 'a': print an address */ + /* case 'a': print an address. */ case 'C': - /* Print appropriate test for integer branch false operation */ + /* Print appropriate test for integer branch false operation. */ switch (GET_CODE (x)) { default: @@ -2840,7 +2709,7 @@ frv_print_operand (file, x, code) CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */ case 'c': - /* Print appropriate test for integer branch true operation */ + /* Print appropriate test for integer branch true operation. */ switch (GET_CODE (x)) { default: @@ -2873,7 +2742,7 @@ frv_print_operand (file, x, code) break; case 'F': - /* Print appropriate test for floating point branch false operation */ + /* Print appropriate test for floating point branch false operation. */ switch (GET_CODE (x)) { default: @@ -2889,7 +2758,7 @@ frv_print_operand (file, x, code) break; case 'f': - /* Print appropriate test for floating point branch true operation */ + /* Print appropriate test for floating point branch true operation. */ switch (GET_CODE (x)) { default: @@ -2906,7 +2775,7 @@ frv_print_operand (file, x, code) case 'I': /* Print 'i' if the operand is a constant, or is a memory reference that - adds a constant */ + adds a constant. */ if (GET_CODE (x) == MEM) x = ((GET_CODE (XEXP (x, 0)) == PLUS) ? XEXP (XEXP (x, 0), 1) @@ -2927,7 +2796,7 @@ frv_print_operand (file, x, code) case 'i': /* For jump instructions, print 'i' if the operand is a constant or - is an expression that adds a constant */ + is an expression that adds a constant. */ if (GET_CODE (x) == CONST_INT) fputs ("i", file); @@ -2949,7 +2818,7 @@ frv_print_operand (file, x, code) fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x); break; - /* case 'l': print a LABEL_REF */ + /* case 'l': print a LABEL_REF. */ case 'M': case 'N': @@ -2993,7 +2862,7 @@ frv_print_operand (file, x, code) } break; - /* case 'n': negate and print a constant int */ + /* case 'n': negate and print a constant int. */ case 'P': /* Print PIC label using operand as the number. */ @@ -3004,13 +2873,13 @@ frv_print_operand (file, x, code) break; case 'U': - /* Print 'u' if the operand is a update load/store */ + /* Print 'u' if the operand is a update load/store. */ if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY) fputs ("u", file); break; case 'z': - /* If value is 0, print gr0, otherwise it must be a register */ + /* If value is 0, print gr0, otherwise it must be a register. */ if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0) fputs (reg_names[GPR_R0], file); @@ -3022,14 +2891,14 @@ frv_print_operand (file, x, code) break; case 'x': - /* Print constant in hex */ + /* Print constant in hex. */ if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) { fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value); break; } - /* fall through */ + /* Fall through. */ case '\0': if (GET_CODE (x) == REG) @@ -3076,19 +2945,18 @@ frv_print_operand (file, x, code) FNTYPE is nonzero, but never both of them at once. */ void -frv_init_cumulative_args (cum, fntype, libname, indirect, incoming) - CUMULATIVE_ARGS *cum; - tree fntype; - rtx libname; - int indirect; - int incoming; +frv_init_cumulative_args (CUMULATIVE_ARGS *cum, + tree fntype, + rtx libname, + tree fndecl, + int incoming) { *cum = FIRST_ARG_REGNUM; if (TARGET_DEBUG_ARG) { fprintf (stderr, "\ninit_cumulative_args:"); - if (indirect) + if (!fndecl && fntype) fputs (" indirect", stderr); if (incoming) @@ -3117,9 +2985,8 @@ frv_init_cumulative_args (cum, fntype, libname, indirect, incoming) `PARM_BOUNDARY' is used for all arguments. */ int -frv_function_arg_boundary (mode, type) - enum machine_mode mode ATTRIBUTE_UNUSED; - tree type ATTRIBUTE_UNUSED; +frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED, + tree type ATTRIBUTE_UNUSED) { return BITS_PER_WORD; } @@ -3156,12 +3023,11 @@ frv_function_arg_boundary (mode, type) stack and then loaded into a register. */ rtx -frv_function_arg (cum, mode, type, named, incoming) - CUMULATIVE_ARGS *cum; - enum machine_mode mode; - tree type ATTRIBUTE_UNUSED; - int named; - int incoming ATTRIBUTE_UNUSED; +frv_function_arg (CUMULATIVE_ARGS *cum, + enum machine_mode mode, + tree type ATTRIBUTE_UNUSED, + int named, + int incoming ATTRIBUTE_UNUSED) { enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; int arg_num = *cum; @@ -3206,11 +3072,10 @@ frv_function_arg (cum, mode, type, named, incoming) for arguments without any special help. */ void -frv_function_arg_advance (cum, mode, type, named) - CUMULATIVE_ARGS *cum; - enum machine_mode mode; - tree type ATTRIBUTE_UNUSED; - int named; +frv_function_arg_advance (CUMULATIVE_ARGS *cum, + enum machine_mode mode, + tree type ATTRIBUTE_UNUSED, + int named) { enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; int bytes = GET_MODE_SIZE (xmode); @@ -3243,11 +3108,10 @@ frv_function_arg_advance (cum, mode, type, named) the called function. */ int -frv_function_arg_partial_nregs (cum, mode, type, named) - CUMULATIVE_ARGS *cum; - enum machine_mode mode; - tree type ATTRIBUTE_UNUSED; - int named ATTRIBUTE_UNUSED; +frv_function_arg_partial_nregs (CUMULATIVE_ARGS *cum, + enum machine_mode mode, + tree type ATTRIBUTE_UNUSED, + int named ATTRIBUTE_UNUSED) { enum machine_mode xmode = (mode == BLKmode) ? SImode : mode; int bytes = GET_MODE_SIZE (xmode); @@ -3280,11 +3144,10 @@ frv_function_arg_partial_nregs (cum, mode, type, named) MUST_PASS_IN_STACK (MODE, TYPE) */ int -frv_function_arg_pass_by_reference (cum, mode, type, named) - CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; - enum machine_mode mode; - tree type; - int named ATTRIBUTE_UNUSED; +frv_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, + enum machine_mode mode, + tree type, + int named ATTRIBUTE_UNUSED) { return MUST_PASS_IN_STACK (mode, type); } @@ -3299,11 +3162,10 @@ frv_function_arg_pass_by_reference (cum, mode, type, named) otherwise a copy must be made. */ int -frv_function_arg_callee_copies (cum, mode, type, named) - CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; - enum machine_mode mode ATTRIBUTE_UNUSED; - tree type ATTRIBUTE_UNUSED; - int named ATTRIBUTE_UNUSED; +frv_function_arg_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, + tree type ATTRIBUTE_UNUSED, + int named ATTRIBUTE_UNUSED) { return 0; } @@ -3313,11 +3175,10 @@ frv_function_arg_callee_copies (cum, mode, type, named) copying it to a pseudo register. */ int -frv_function_arg_keep_as_reference (cum, mode, type, named) - CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; - enum machine_mode mode ATTRIBUTE_UNUSED; - tree type ATTRIBUTE_UNUSED; - int named ATTRIBUTE_UNUSED; +frv_function_arg_keep_as_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, + tree type ATTRIBUTE_UNUSED, + int named ATTRIBUTE_UNUSED) { return 0; } @@ -3326,9 +3187,7 @@ frv_function_arg_keep_as_reference (cum, mode, type, named) /* Return true if a register is ok to use as a base or index register. */ static FRV_INLINE int -frv_regno_ok_for_base_p (regno, strict_p) - int regno; - int strict_p; +frv_regno_ok_for_base_p (int regno, int strict_p) { if (GPR_P (regno)) return TRUE; @@ -3400,11 +3259,10 @@ frv_regno_ok_for_base_p (regno, strict_p) `PRINT_OPERAND_ADDRESS'. */ int -frv_legitimate_address_p (mode, x, strict_p, condexec_p) - enum machine_mode mode; - rtx x; - int strict_p; - int condexec_p; +frv_legitimate_address_p (enum machine_mode mode, + rtx x, + int strict_p, + int condexec_p) { rtx x0, x1; int ret = 0; @@ -3421,7 +3279,7 @@ frv_legitimate_address_p (mode, x, strict_p, condexec_p) if (GET_CODE (x) != REG) break; - /* fall through */ + /* Fall through. */ case REG: ret = frv_regno_ok_for_base_p (REGNO (x), strict_p); @@ -3481,11 +3339,11 @@ frv_legitimate_address_p (mode, x, strict_p, condexec_p) if (GET_CODE (x1) != REG) break; - /* fall through */ + /* Fall through. */ case REG: - /* Do not allow reg+reg addressing for modes > 1 word if we can't depend - on having move double instructions */ + /* Do not allow reg+reg addressing for modes > 1 word if we + can't depend on having move double instructions. */ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) ret = FALSE; else @@ -3511,7 +3369,7 @@ frv_legitimate_address_p (mode, x, strict_p, condexec_p) case SYMBOL_REF: if (!condexec_p && regno0 == SDA_BASE_REG - && symbol_ref_small_data_p (x1)) + && SYMBOL_REF_SMALL_P (x1)) ret = TRUE; break; @@ -3557,10 +3415,9 @@ frv_legitimate_address_p (mode, x, strict_p, condexec_p) can generate better code. */ rtx -frv_legitimize_address (x, oldx, mode) - rtx x; - rtx oldx ATTRIBUTE_UNUSED; - enum machine_mode mode ATTRIBUTE_UNUSED; +frv_legitimize_address (rtx x, + rtx oldx ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED) { rtx ret = NULL_RTX; @@ -3569,7 +3426,7 @@ frv_legitimize_address (x, oldx, mode) things up when force_reg is called to try and put it in a register because we aren't optimizing. */ if (optimize - && ((GET_CODE (x) == SYMBOL_REF && symbol_ref_small_data_p (x)) + && ((GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x)) || (GET_CODE (x) == CONST && const_small_data_p (x)))) { ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, SDA_BASE_REG), x); @@ -3591,10 +3448,7 @@ frv_legitimize_address (x, oldx, mode) the operand is used by a predicated instruction. */ static int -frv_legitimate_memory_operand (op, mode, condexec_p) - rtx op; - enum machine_mode mode; - int condexec_p; +frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p) { return ((GET_MODE (op) == mode || mode == VOIDmode) && GET_CODE (op) == MEM @@ -3606,9 +3460,8 @@ frv_legitimate_memory_operand (op, mode, condexec_p) /* Return 1 is OP is a memory operand, or will be turned into one by reload. */ -int frv_load_operand (op, mode) - rtx op; - enum machine_mode mode; +int +frv_load_operand (rtx op, enum machine_mode mode) { if (GET_MODE (op) != mode && mode != VOIDmode) return FALSE; @@ -3629,9 +3482,8 @@ int frv_load_operand (op, mode) /* Return 1 if operand is a GPR register or a FPR register. */ -int gpr_or_fpr_operand (op, mode) - rtx op; - enum machine_mode mode; +int +gpr_or_fpr_operand (rtx op, enum machine_mode mode) { int regno; @@ -3658,9 +3510,8 @@ int gpr_or_fpr_operand (op, mode) /* Return 1 if operand is a GPR register or 12 bit signed immediate. */ -int gpr_or_int12_operand (op, mode) - rtx op; - enum machine_mode mode; +int +gpr_or_int12_operand (rtx op, enum machine_mode mode) { if (GET_CODE (op) == CONST_INT) return IN_RANGE_P (INTVAL (op), -2048, 2047); @@ -3685,9 +3536,8 @@ int gpr_or_int12_operand (op, mode) /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit signed immediate. */ -int gpr_fpr_or_int12_operand (op, mode) - rtx op; - enum machine_mode mode; +int +gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode) { int regno; @@ -3717,9 +3567,8 @@ int gpr_fpr_or_int12_operand (op, mode) /* Return 1 if operand is a register or 6 bit signed immediate. */ -int fpr_or_int6_operand (op, mode) - rtx op; - enum machine_mode mode; +int +fpr_or_int6_operand (rtx op, enum machine_mode mode) { if (GET_CODE (op) == CONST_INT) return IN_RANGE_P (INTVAL (op), -32, 31); @@ -3743,9 +3592,8 @@ int fpr_or_int6_operand (op, mode) /* Return 1 if operand is a register or 10 bit signed immediate. */ -int gpr_or_int10_operand (op, mode) - rtx op; - enum machine_mode mode; +int +gpr_or_int10_operand (rtx op, enum machine_mode mode) { if (GET_CODE (op) == CONST_INT) return IN_RANGE_P (INTVAL (op), -512, 511); @@ -3769,9 +3617,8 @@ int gpr_or_int10_operand (op, mode) /* Return 1 if operand is a register or an integer immediate. */ -int gpr_or_int_operand (op, mode) - rtx op; - enum machine_mode mode; +int +gpr_or_int_operand (rtx op, enum machine_mode mode) { if (GET_CODE (op) == CONST_INT) return TRUE; @@ -3795,9 +3642,8 @@ int gpr_or_int_operand (op, mode) /* Return 1 if operand is a 12 bit signed immediate. */ -int int12_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { if (GET_CODE (op) != CONST_INT) return FALSE; @@ -3807,9 +3653,8 @@ int int12_operand (op, mode) /* Return 1 if operand is a 6 bit signed immediate. */ -int int6_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { if (GET_CODE (op) != CONST_INT) return FALSE; @@ -3819,36 +3664,32 @@ int int6_operand (op, mode) /* Return 1 if operand is a 5 bit signed immediate. */ -int int5_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15); } /* Return 1 if operand is a 5 bit unsigned immediate. */ -int uint5_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31); } /* Return 1 if operand is a 4 bit unsigned immediate. */ -int uint4_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15); } /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */ -int uint1_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1); } @@ -3856,9 +3697,8 @@ int uint1_operand (op, mode) /* Return 1 if operand is an integer constant that takes 2 instructions to load up and can be split into sethi/setlo instructions.. */ -int int_2word_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +int_2word_operand(rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { HOST_WIDE_INT value; REAL_VALUE_TYPE rv; @@ -3878,7 +3718,7 @@ int int_2word_operand (op, mode) case SYMBOL_REF: /* small data references are already 1 word */ - return (flag_pic == 0) && (! symbol_ref_small_data_p (op)); + return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op)); case CONST_INT: return ! IN_RANGE_P (INTVAL (op), -32768, 32767); @@ -3904,9 +3744,7 @@ int int_2word_operand (op, mode) /* Return 1 if operand is the pic address register. */ int -pic_register_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +pic_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { if (! flag_pic) return FALSE; @@ -3921,11 +3759,10 @@ pic_register_operand (op, mode) } /* Return 1 if operand is a symbolic reference when a PIC option is specified - that takes 3 seperate instructions to form. */ + that takes 3 separate instructions to form. */ -int pic_symbolic_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +pic_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { if (! flag_pic) return FALSE; @@ -3940,7 +3777,7 @@ int pic_symbolic_operand (op, mode) case SYMBOL_REF: /* small data references are already 1 word */ - return ! symbol_ref_small_data_p (op); + return ! SYMBOL_REF_SMALL_P (op); case CONST: /* small data references are already 1 word */ @@ -3952,9 +3789,7 @@ int pic_symbolic_operand (op, mode) /* Return 1 if operand is the small data register. */ int -small_data_register_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +small_data_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { if (GET_CODE (op) != REG) return FALSE; @@ -3968,9 +3803,8 @@ small_data_register_operand (op, mode) /* Return 1 if operand is a symbolic reference to a small data area static or global object. */ -int small_data_symbolic_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +small_data_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { switch (GET_CODE (op)) { @@ -3981,17 +3815,16 @@ int small_data_symbolic_operand (op, mode) return const_small_data_p (op); case SYMBOL_REF: - return symbol_ref_small_data_p (op); + return SYMBOL_REF_SMALL_P (op); } return FALSE; } -/* Return 1 if operand is a 16 bit unsigned immediate */ +/* Return 1 if operand is a 16 bit unsigned immediate. */ -int uint16_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { if (GET_CODE (op) != CONST_INT) return FALSE; @@ -3999,11 +3832,11 @@ int uint16_operand (op, mode) return IN_RANGE_P (INTVAL (op), 0, 0xffff); } -/* Return 1 if operand is an integer constant with the bottom 16 bits clear */ +/* Return 1 if operand is an integer constant with the bottom 16 bits + clear. */ -int upper_int16_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +int +upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { if (GET_CODE (op) != CONST_INT) return FALSE; @@ -4011,12 +3844,10 @@ int upper_int16_operand (op, mode) return ((INTVAL (op) & 0xffff) == 0); } -/* Return true if operand is a GPR register. */ +/* Return true if operand is a GPR register. */ int -integer_register_operand (op, mode) - rtx op; - enum machine_mode mode; +integer_register_operand (rtx op, enum machine_mode mode) { if (GET_MODE (op) != mode && mode != VOIDmode) return FALSE; @@ -4039,9 +3870,7 @@ integer_register_operand (op, mode) here, in order to prevent a combine bug. */ int -gpr_no_subreg_operand (op, mode) - rtx op; - enum machine_mode mode; +gpr_no_subreg_operand (rtx op, enum machine_mode mode) { if (GET_MODE (op) != mode && mode != VOIDmode) return FALSE; @@ -4052,12 +3881,10 @@ gpr_no_subreg_operand (op, mode) return GPR_OR_PSEUDO_P (REGNO (op)); } -/* Return true if operand is a FPR register. */ +/* Return true if operand is a FPR register. */ int -fpr_operand (op, mode) - rtx op; - enum machine_mode mode; +fpr_operand (rtx op, enum machine_mode mode) { if (GET_MODE (op) != mode && mode != VOIDmode) return FALSE; @@ -4076,12 +3903,10 @@ fpr_operand (op, mode) return FPR_OR_PSEUDO_P (REGNO (op)); } -/* Return true if operand is an even GPR or FPR register. */ +/* Return true if operand is an even GPR or FPR register. */ int -even_reg_operand (op, mode) - rtx op; - enum machine_mode mode; +even_reg_operand (rtx op, enum machine_mode mode) { int regno; @@ -4112,12 +3937,10 @@ even_reg_operand (op, mode) return FALSE; } -/* Return true if operand is an odd GPR register. */ +/* Return true if operand is an odd GPR register. */ int -odd_reg_operand (op, mode) - rtx op; - enum machine_mode mode; +odd_reg_operand (rtx op, enum machine_mode mode) { int regno; @@ -4136,7 +3959,7 @@ odd_reg_operand (op, mode) return FALSE; regno = REGNO (op); - /* assume that reload will give us an even register */ + /* Assume that reload will give us an even register. */ if (regno >= FIRST_PSEUDO_REGISTER) return FALSE; @@ -4149,12 +3972,10 @@ odd_reg_operand (op, mode) return FALSE; } -/* Return true if operand is an even GPR register. */ +/* Return true if operand is an even GPR register. */ int -even_gpr_operand (op, mode) - rtx op; - enum machine_mode mode; +even_gpr_operand (rtx op, enum machine_mode mode) { int regno; @@ -4182,12 +4003,10 @@ even_gpr_operand (op, mode) return (((regno - GPR_FIRST) & 1) == 0); } -/* Return true if operand is an odd GPR register. */ +/* Return true if operand is an odd GPR register. */ int -odd_gpr_operand (op, mode) - rtx op; - enum machine_mode mode; +odd_gpr_operand (rtx op, enum machine_mode mode) { int regno; @@ -4206,7 +4025,7 @@ odd_gpr_operand (op, mode) return FALSE; regno = REGNO (op); - /* assume that reload will give us an even register */ + /* Assume that reload will give us an even register. */ if (regno >= FIRST_PSEUDO_REGISTER) return FALSE; @@ -4216,12 +4035,10 @@ odd_gpr_operand (op, mode) return (((regno - GPR_FIRST) & 1) != 0); } -/* Return true if operand is a quad aligned FPR register. */ +/* Return true if operand is a quad aligned FPR register. */ int -quad_fpr_operand (op, mode) - rtx op; - enum machine_mode mode; +quad_fpr_operand (rtx op, enum machine_mode mode) { int regno; @@ -4249,12 +4066,10 @@ quad_fpr_operand (op, mode) return (((regno - FPR_FIRST) & 3) == 0); } -/* Return true if operand is an even FPR register. */ +/* Return true if operand is an even FPR register. */ int -even_fpr_operand (op, mode) - rtx op; - enum machine_mode mode; +even_fpr_operand (rtx op, enum machine_mode mode) { int regno; @@ -4282,12 +4097,10 @@ even_fpr_operand (op, mode) return (((regno - FPR_FIRST) & 1) == 0); } -/* Return true if operand is an odd FPR register. */ +/* Return true if operand is an odd FPR register. */ int -odd_fpr_operand (op, mode) - rtx op; - enum machine_mode mode; +odd_fpr_operand (rtx op, enum machine_mode mode) { int regno; @@ -4306,7 +4119,7 @@ odd_fpr_operand (op, mode) return FALSE; regno = REGNO (op); - /* assume that reload will give us an even register */ + /* Assume that reload will give us an even register. */ if (regno >= FIRST_PSEUDO_REGISTER) return FALSE; @@ -4324,9 +4137,7 @@ odd_fpr_operand (op, mode) the stack and the address taken and passed through to another function. */ int -dbl_memory_one_insn_operand (op, mode) - rtx op; - enum machine_mode mode; +dbl_memory_one_insn_operand (rtx op, enum machine_mode mode) { rtx addr; rtx addr_reg; @@ -4377,9 +4188,7 @@ dbl_memory_one_insn_operand (op, mode) use two instructions to load or store. */ int -dbl_memory_two_insn_operand (op, mode) - rtx op; - enum machine_mode mode; +dbl_memory_two_insn_operand (rtx op, enum machine_mode mode) { if (GET_CODE (op) != MEM) return FALSE; @@ -4397,9 +4206,7 @@ dbl_memory_two_insn_operand (op, mode) operation. */ int -move_destination_operand (op, mode) - rtx op; - enum machine_mode mode; +move_destination_operand (rtx op, enum machine_mode mode) { rtx subreg; enum rtx_code code; @@ -4441,9 +4248,7 @@ move_destination_operand (op, mode) operation. */ int -move_source_operand (op, mode) - rtx op; - enum machine_mode mode; +move_source_operand (rtx op, enum machine_mode mode) { rtx subreg; enum rtx_code code; @@ -4492,9 +4297,7 @@ move_source_operand (op, mode) move operation. */ int -condexec_dest_operand (op, mode) - rtx op; - enum machine_mode mode; +condexec_dest_operand (rtx op, enum machine_mode mode) { rtx subreg; enum rtx_code code; @@ -4536,9 +4339,7 @@ condexec_dest_operand (op, mode) move operation. */ int -condexec_source_operand (op, mode) - rtx op; - enum machine_mode mode; +condexec_source_operand (rtx op, enum machine_mode mode) { rtx subreg; enum rtx_code code; @@ -4584,9 +4385,7 @@ condexec_source_operand (op, mode) appropriate type. */ int -reg_or_0_operand (op, mode) - rtx op; - enum machine_mode mode; +reg_or_0_operand (rtx op, enum machine_mode mode) { switch (GET_CODE (op)) { @@ -4608,12 +4407,10 @@ reg_or_0_operand (op, mode) return FALSE; } -/* Return true if operand is the link register */ +/* Return true if operand is the link register. */ int -lr_operand (op, mode) - rtx op; - enum machine_mode mode; +lr_operand (rtx op, enum machine_mode mode) { if (GET_CODE (op) != REG) return FALSE; @@ -4630,9 +4427,7 @@ lr_operand (op, mode) /* Return true if operand is a gpr register or a valid memory operation. */ int -gpr_or_memory_operand (op, mode) - rtx op; - enum machine_mode mode; +gpr_or_memory_operand (rtx op, enum machine_mode mode) { return (integer_register_operand (op, mode) || frv_legitimate_memory_operand (op, mode, FALSE)); @@ -4641,20 +4436,16 @@ gpr_or_memory_operand (op, mode) /* Return true if operand is a fpr register or a valid memory operation. */ int -fpr_or_memory_operand (op, mode) - rtx op; - enum machine_mode mode; +fpr_or_memory_operand (rtx op, enum machine_mode mode) { return (fpr_operand (op, mode) || frv_legitimate_memory_operand (op, mode, FALSE)); } -/* Return true if operand is an icc register */ +/* Return true if operand is an icc register. */ int -icc_operand (op, mode) - rtx op; - enum machine_mode mode; +icc_operand (rtx op, enum machine_mode mode) { int regno; @@ -4668,12 +4459,10 @@ icc_operand (op, mode) return ICC_OR_PSEUDO_P (regno); } -/* Return true if operand is an fcc register */ +/* Return true if operand is an fcc register. */ int -fcc_operand (op, mode) - rtx op; - enum machine_mode mode; +fcc_operand (rtx op, enum machine_mode mode) { int regno; @@ -4687,12 +4476,10 @@ fcc_operand (op, mode) return FCC_OR_PSEUDO_P (regno); } -/* Return true if operand is either an fcc or icc register */ +/* Return true if operand is either an fcc or icc register. */ int -cc_operand (op, mode) - rtx op; - enum machine_mode mode; +cc_operand (rtx op, enum machine_mode mode) { int regno; @@ -4709,12 +4496,10 @@ cc_operand (op, mode) return FALSE; } -/* Return true if operand is an integer CCR register */ +/* Return true if operand is an integer CCR register. */ int -icr_operand (op, mode) - rtx op; - enum machine_mode mode; +icr_operand (rtx op, enum machine_mode mode) { int regno; @@ -4728,12 +4513,10 @@ icr_operand (op, mode) return ICR_OR_PSEUDO_P (regno); } -/* Return true if operand is an fcc register */ +/* Return true if operand is an fcc register. */ int -fcr_operand (op, mode) - rtx op; - enum machine_mode mode; +fcr_operand (rtx op, enum machine_mode mode) { int regno; @@ -4747,12 +4530,10 @@ fcr_operand (op, mode) return FCR_OR_PSEUDO_P (regno); } -/* Return true if operand is either an fcc or icc register */ +/* Return true if operand is either an fcc or icc register. */ int -cr_operand (op, mode) - rtx op; - enum machine_mode mode; +cr_operand (rtx op, enum machine_mode mode) { int regno; @@ -4772,9 +4553,7 @@ cr_operand (op, mode) /* Return true if operand is a memory reference suitable for a call. */ int -call_operand (op, mode) - rtx op; - enum machine_mode mode; +call_operand (rtx op, enum machine_mode mode) { if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT) return FALSE; @@ -4789,12 +4568,10 @@ call_operand (op, mode) return gpr_or_int12_operand (op, mode); } -/* Return true if operator is an kind of relational operator */ +/* Return true if operator is a kind of relational operator. */ int -relational_operator (op, mode) - rtx op; - enum machine_mode mode; +relational_operator (rtx op, enum machine_mode mode) { rtx op0; rtx op1; @@ -4849,12 +4626,10 @@ relational_operator (op, mode) return FALSE; } -/* Return true if operator is a signed integer relational operator */ +/* Return true if operator is a signed integer relational operator. */ int -signed_relational_operator (op, mode) - rtx op; - enum machine_mode mode; +signed_relational_operator (rtx op, enum machine_mode mode) { rtx op0; rtx op1; @@ -4895,12 +4670,10 @@ signed_relational_operator (op, mode) return FALSE; } -/* Return true if operator is a signed integer relational operator */ +/* Return true if operator is a signed integer relational operator. */ int -unsigned_relational_operator (op, mode) - rtx op; - enum machine_mode mode; +unsigned_relational_operator (rtx op, enum machine_mode mode) { rtx op0; rtx op1; @@ -4939,12 +4712,10 @@ unsigned_relational_operator (op, mode) return FALSE; } -/* Return true if operator is a floating point relational operator */ +/* Return true if operator is a floating point relational operator. */ int -float_relational_operator (op, mode) - rtx op; - enum machine_mode mode; +float_relational_operator (rtx op, enum machine_mode mode) { rtx op0; rtx op1; @@ -4992,9 +4763,7 @@ float_relational_operator (op, mode) /* Return true if operator is EQ/NE of a conditional execution register. */ int -ccr_eqne_operator (op, mode) - rtx op; - enum machine_mode mode; +ccr_eqne_operator (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); rtx op0; @@ -5033,9 +4802,7 @@ ccr_eqne_operator (op, mode) unsigned). */ int -minmax_operator (op, mode) - rtx op; - enum machine_mode mode; +minmax_operator (rtx op, enum machine_mode mode) { if (mode != VOIDmode && mode != GET_MODE (op)) return FALSE; @@ -5065,9 +4832,7 @@ minmax_operator (op, mode) conditionally and takes 1 cycle. */ int -condexec_si_binary_operator (op, mode) - rtx op; - enum machine_mode mode; +condexec_si_binary_operator (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); @@ -5095,9 +4860,7 @@ condexec_si_binary_operator (op, mode) executed conditionally by a media instruction. */ int -condexec_si_media_operator (op, mode) - rtx op; - enum machine_mode mode; +condexec_si_media_operator (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); @@ -5120,9 +4883,7 @@ condexec_si_media_operator (op, mode) conditionally. */ int -condexec_si_divide_operator (op, mode) - rtx op; - enum machine_mode mode; +condexec_si_divide_operator (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); @@ -5144,9 +4905,7 @@ condexec_si_divide_operator (op, mode) conditionally. */ int -condexec_si_unary_operator (op, mode) - rtx op; - enum machine_mode mode; +condexec_si_unary_operator (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); @@ -5168,9 +4927,7 @@ condexec_si_unary_operator (op, mode) evaluated conditionally by floating-point instructions. */ int -condexec_sf_conv_operator (op, mode) - rtx op; - enum machine_mode mode; +condexec_sf_conv_operator (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); @@ -5193,9 +4950,7 @@ condexec_sf_conv_operator (op, mode) instructions. */ int -condexec_sf_add_operator (op, mode) - rtx op; - enum machine_mode mode; +condexec_sf_add_operator (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); @@ -5217,9 +4972,7 @@ condexec_sf_add_operator (op, mode) executed. */ int -condexec_memory_operand (op, mode) - rtx op; - enum machine_mode mode; +condexec_memory_operand (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); rtx addr; @@ -5256,9 +5009,7 @@ condexec_memory_operand (op, mode) register. */ int -intop_compare_operator (op, mode) - rtx op; - enum machine_mode mode; +intop_compare_operator (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); @@ -5291,9 +5042,7 @@ intop_compare_operator (op, mode) with a setcc operation inside of a conditional execution. */ int -condexec_intop_cmp_operator (op, mode) - rtx op; - enum machine_mode mode; +condexec_intop_cmp_operator (rtx op, enum machine_mode mode) { enum machine_mode op_mode = GET_MODE (op); @@ -5322,12 +5071,10 @@ condexec_intop_cmp_operator (op, mode) return TRUE; } -/* Return 1 if operand is a valid ACC register number */ +/* Return 1 if operand is a valid ACC register number. */ int -acc_operand (op, mode) - rtx op; - enum machine_mode mode; +acc_operand (rtx op, enum machine_mode mode) { int regno; @@ -5349,12 +5096,10 @@ acc_operand (op, mode) return ACC_OR_PSEUDO_P (regno); } -/* Return 1 if operand is a valid even ACC register number */ +/* Return 1 if operand is a valid even ACC register number. */ int -even_acc_operand (op, mode) - rtx op; - enum machine_mode mode; +even_acc_operand (rtx op, enum machine_mode mode) { int regno; @@ -5376,12 +5121,10 @@ even_acc_operand (op, mode) return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 1) == 0); } -/* Return 1 if operand is zero or four */ +/* Return 1 if operand is zero or four. */ int -quad_acc_operand (op, mode) - rtx op; - enum machine_mode mode; +quad_acc_operand (rtx op, enum machine_mode mode) { int regno; @@ -5403,12 +5146,10 @@ quad_acc_operand (op, mode) return (ACC_OR_PSEUDO_P (regno) && ((regno - ACC_FIRST) & 3) == 0); } -/* Return 1 if operand is a valid ACCG register number */ +/* Return 1 if operand is a valid ACCG register number. */ int -accg_operand (op, mode) - rtx op; - enum machine_mode mode; +accg_operand (rtx op, enum machine_mode mode) { if (GET_MODE (op) != mode && mode != VOIDmode) return FALSE; @@ -5432,7 +5173,7 @@ accg_operand (op, mode) epilog code. For frv, we only do it if there was no stack allocation. */ int -direct_return_p () +direct_return_p (void) { frv_stack_t *info; @@ -5449,9 +5190,7 @@ direct_return_p () instructions are emitted. */ int -frv_emit_movsi (dest, src) - rtx dest; - rtx src; +frv_emit_movsi (rtx dest, rtx src) { int base_regno = -1; @@ -5461,7 +5200,7 @@ frv_emit_movsi (dest, src) && (!reg_or_0_operand (src, SImode) /* Virtual registers will almost always be replaced by an add instruction, so expose this to CSE by copying to - an intermediate register */ + an intermediate register. */ || (GET_CODE (src) == REG && IN_RANGE_P (REGNO (src), FIRST_VIRTUAL_REGISTER, @@ -5493,7 +5232,7 @@ frv_emit_movsi (dest, src) break; case SYMBOL_REF: - if (symbol_ref_small_data_p (src)) + if (SYMBOL_REF_SMALL_P (src)) base_regno = SDA_BASE_REG; else if (flag_pic) @@ -5522,9 +5261,7 @@ frv_emit_movsi (dest, src) /* Return a string to output a single word move. */ const char * -output_move_single (operands, insn) - rtx operands[]; - rtx insn; +output_move_single (rtx operands[], rtx insn) { rtx dest = operands[0]; rtx src = operands[1]; @@ -5742,9 +5479,7 @@ output_move_single (operands, insn) /* Return a string to output a double word move. */ const char * -output_move_double (operands, insn) - rtx operands[]; - rtx insn; +output_move_double (rtx operands[], rtx insn) { rtx dest = operands[0]; rtx src = operands[1]; @@ -5875,9 +5610,7 @@ output_move_double (operands, insn) Operand3 -- source */ const char * -output_condmove_single (operands, insn) - rtx operands[]; - rtx insn; +output_condmove_single (rtx operands[], rtx insn) { rtx dest = operands[2]; rtx src = operands[3]; @@ -6016,15 +5749,12 @@ output_condmove_single (operands, insn) comparison was done it. */ static rtx -frv_emit_comparison (test, op0, op1) - enum rtx_code test; - rtx op0; - rtx op1; +frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1) { enum machine_mode cc_mode; rtx cc_reg; - /* Floating point doesn't have comparison against a constant */ + /* Floating point doesn't have comparison against a constant. */ if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG) op1 = force_reg (GET_MODE (op0), op1); @@ -6050,9 +5780,7 @@ frv_emit_comparison (test, op0, op1) conditional execution, but that confuses the rest of the compiler. */ int -frv_emit_cond_branch (test, label) - enum rtx_code test; - rtx label; +frv_emit_cond_branch (enum rtx_code test, rtx label) { rtx test_rtx; rtx label_ref; @@ -6077,9 +5805,7 @@ frv_emit_cond_branch (test, label) operands were previously stored in frv_compare_op0 and frv_compare_op1. */ int -frv_emit_scc (test, target) - enum rtx_code test; - rtx target; +frv_emit_scc (enum rtx_code test, rtx target) { rtx set; rtx test_rtx; @@ -6107,15 +5833,10 @@ frv_emit_scc (test, target) /* Split a SCC instruction into component parts, returning a SEQUENCE to hold - the seperate insns. */ + the separate insns. */ rtx -frv_split_scc (dest, test, cc_reg, cr_reg, value) - rtx dest; - rtx test; - rtx cc_reg; - rtx cr_reg; - HOST_WIDE_INT value; +frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value) { rtx ret; @@ -6150,11 +5871,7 @@ frv_split_scc (dest, test, cc_reg, cr_reg, value) move. */ int -frv_emit_cond_move (dest, test_rtx, src1, src2) - rtx dest; - rtx test_rtx; - rtx src1; - rtx src2; +frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2) { rtx set; rtx clobber_cc; @@ -6178,7 +5895,7 @@ frv_emit_cond_move (dest, test_rtx, src1, src2) HOST_WIDE_INT value1 = INTVAL (src1); HOST_WIDE_INT value2 = INTVAL (src2); - /* having 0 as one of the constants can be done by loading the other + /* Having 0 as one of the constants can be done by loading the other constant, and optionally moving in gr0. */ if (value1 == 0 || value2 == 0) ; @@ -6227,12 +5944,11 @@ frv_emit_cond_move (dest, test_rtx, src1, src2) } -/* Split a conditonal move into constituent parts, returning a SEQUENCE +/* Split a conditional move into constituent parts, returning a SEQUENCE containing all of the insns. */ rtx -frv_split_cond_move (operands) - rtx operands[]; +frv_split_cond_move (rtx operands[]) { rtx dest = operands[0]; rtx test = operands[1]; @@ -6259,7 +5975,7 @@ frv_split_cond_move (operands) HOST_WIDE_INT value1 = INTVAL (src1); HOST_WIDE_INT value2 = INTVAL (src2); - /* having 0 as one of the constants can be done by loading the other + /* Having 0 as one of the constants can be done by loading the other constant, and optionally moving in gr0. */ if (value1 == 0) { @@ -6327,9 +6043,7 @@ frv_split_cond_move (operands) /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a memory location that is not known to be dword-aligned. */ void -frv_split_double_load (dest, source) - rtx dest; - rtx source; +frv_split_double_load (rtx dest, rtx source) { int regno = REGNO (dest); rtx dest1 = gen_highpart (SImode, dest); @@ -6365,9 +6079,7 @@ frv_split_double_load (dest, source) /* Split (set DEST SOURCE), where DEST refers to a dword memory location and SOURCE is either a double register or the constant zero. */ void -frv_split_double_store (dest, source) - rtx dest; - rtx source; +frv_split_double_store (rtx dest, rtx source) { rtx dest1 = change_address (dest, SImode, NULL); rtx dest2 = frv_index_memory (dest, SImode, 1); @@ -6388,8 +6100,7 @@ frv_split_double_store (dest, source) insns. */ rtx -frv_split_minmax (operands) - rtx operands[]; +frv_split_minmax (rtx operands[]) { rtx dest = operands[0]; rtx minmax = operands[1]; @@ -6403,7 +6114,7 @@ frv_split_minmax (operands) start_sequence (); - /* Figure out which test to use */ + /* Figure out which test to use. */ switch (GET_CODE (minmax)) { default: @@ -6469,8 +6180,7 @@ frv_split_minmax (operands) insns. */ rtx -frv_split_abs (operands) - rtx operands[]; +frv_split_abs (rtx operands[]) { rtx dest = operands[0]; rtx src = operands[1]; @@ -6490,7 +6200,7 @@ frv_split_abs (operands) cr_reg, gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx))); - /* Emit the conditional negate if the value is negative */ + /* Emit the conditional negate if the value is negative. */ emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx), gen_negsi2 (dest, src))); @@ -6512,9 +6222,7 @@ frv_split_abs (operands) register used in an insn. */ static int -frv_clear_registers_used (ptr, data) - rtx *ptr; - void *data; +frv_clear_registers_used (rtx *ptr, void *data) { if (GET_CODE (*ptr) == REG) { @@ -6542,8 +6250,7 @@ frv_clear_registers_used (ptr, data) /* On the FR-V, we don't have any extra fields per se, but it is useful hook to initialize the static storage. */ void -frv_ifcvt_init_extra_fields (ce_info) - ce_if_block_t *ce_info ATTRIBUTE_UNUSED; +frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) { frv_ifcvt.added_insns_list = NULL_RTX; frv_ifcvt.cur_scratch_regs = 0; @@ -6560,14 +6267,11 @@ frv_ifcvt_init_extra_fields (ce_info) if the conditional execution conversion is successful. */ static void -frv_ifcvt_add_insn (pattern, insn, before_p) - rtx pattern; - rtx insn; - int before_p; +frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p) { rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn); - link->jump = before_p; /* mark to add this before or after insn */ + link->jump = before_p; /* Mark to add this before or after insn. */ frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link, frv_ifcvt.added_insns_list); @@ -6590,10 +6294,7 @@ frv_ifcvt_add_insn (pattern, insn, before_p) tests cannot be converted. */ void -frv_ifcvt_modify_tests (ce_info, p_true, p_false) - ce_if_block_t *ce_info; - rtx *p_true; - rtx *p_false; +frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false) { basic_block test_bb = ce_info->test_bb; /* test basic block */ basic_block then_bb = ce_info->then_bb; /* THEN */ @@ -6628,8 +6329,8 @@ frv_ifcvt_modify_tests (ce_info, p_true, p_false) /* Figure out which registers we can allocate for our own purposes. Only consider registers that are not preserved across function calls and are not fixed. However, allow the ICC/ICR temporary registers to be allocated - if we did not need to use them in reloading other registers. */ - memset ((PTR) &tmp_reg->regs, 0, sizeof (tmp_reg->regs)); + if we did not need to use them in reloading other registers. */ + memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs)); COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set); AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set); SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP); @@ -6704,16 +6405,16 @@ frv_ifcvt_modify_tests (ce_info, p_true, p_false) /* Scan all of the blocks for registers that must not be allocated. */ for (j = 0; j < num_bb; j++) { - rtx last_insn = bb[j]->end; - rtx insn = bb[j]->head; + rtx last_insn = BB_END (bb[j]); + rtx insn = BB_HEAD (bb[j]); int regno; if (rtl_dump_file) fprintf (rtl_dump_file, "Scanning %s block %d, start %d, end %d\n", (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"), (int) bb[j]->index, - (int) INSN_UID (bb[j]->head), - (int) INSN_UID (bb[j]->end)); + (int) INSN_UID (BB_HEAD (bb[j])), + (int) INSN_UID (BB_END (bb[j]))); /* Anything live at the beginning of the block is obviously unavailable for allocation. */ @@ -6723,7 +6424,7 @@ frv_ifcvt_modify_tests (ce_info, p_true, p_false) CLEAR_HARD_REG_BIT (tmp_reg->regs, regno); }); - /* loop through the insns in the block. */ + /* Loop through the insns in the block. */ for (;;) { /* Mark any new registers that are created as being unavailable for @@ -6913,7 +6614,7 @@ frv_ifcvt_modify_tests (ce_info, p_true, p_false) gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx)); /* Record the check insn to be inserted later. */ - frv_ifcvt_add_insn (check_insn, test_bb->end, TRUE); + frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE); /* Update the tests. */ frv_ifcvt.cr_reg = cr; @@ -6947,11 +6648,10 @@ frv_ifcvt_modify_tests (ce_info, p_true, p_false) (const_int 0))) */ void -frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false) - ce_if_block_t *ce_info; - basic_block bb; - rtx *p_true; - rtx *p_false; +frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info, + basic_block bb, + rtx *p_true, + rtx *p_false) { rtx old_true = XEXP (*p_true, 0); rtx old_false = XEXP (*p_false, 0); @@ -6987,7 +6687,7 @@ frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false) if (GET_CODE (cr) != REG) goto fail; - + if (mode == CCmode || mode == CC_UNSmode) { cr_class = ICR_REGS; @@ -7032,7 +6732,7 @@ frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false) /* First add the andcr/andncr/orcr/orncr, which will be added after the conditional check instruction, due to frv_ifcvt_add_insn being a LIFO stack. */ - frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), bb->end, TRUE); + frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE); /* Now add the conditional check insn. */ cc = XEXP (test_expr, 0); @@ -7041,9 +6741,9 @@ frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false) check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else); - /* add the new check insn to the list of check insns that need to be + /* Add the new check insn to the list of check insns that need to be inserted. */ - frv_ifcvt_add_insn (check_insn, bb->end, TRUE); + frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE); if (TARGET_DEBUG_COND_EXEC) { @@ -7061,7 +6761,7 @@ frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false) fail: *p_true = *p_false = NULL_RTX; - /* If we allocated a CR register, release it. */ + /* If we allocated a CR register, release it. */ if (new_cr) { CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr)); @@ -7080,9 +6780,7 @@ frv_ifcvt_modify_multiple_tests (ce_info, bb, p_true, p_false) that use constants to ones that just use registers. */ static rtx -frv_ifcvt_load_value (value, insn) - rtx value; - rtx insn ATTRIBUTE_UNUSED; +frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED) { int num_alloc = frv_ifcvt.cur_scratch_regs; int i; @@ -7104,7 +6802,7 @@ frv_ifcvt_load_value (value, insn) } } - /* Have we exhausted the number of registers available? */ + /* Have we exhausted the number of registers available? */ if (num_alloc >= GPR_TEMP_NUM) { if (rtl_dump_file) @@ -7152,10 +6850,7 @@ frv_ifcvt_load_value (value, insn) into a temporary register, or the new MEM if we were successful. */ static rtx -frv_ifcvt_rewrite_mem (mem, mode, insn) - rtx mem; - enum machine_mode mode; - rtx insn; +frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn) { rtx addr = XEXP (mem, 0); @@ -7203,8 +6898,7 @@ frv_ifcvt_rewrite_mem (mem, mode, insn) SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */ static rtx -single_set_pattern (pattern) - rtx pattern; +single_set_pattern (rtx pattern) { rtx set; int i; @@ -7251,10 +6945,9 @@ single_set_pattern (pattern) insn cannot be converted to be executed conditionally. */ rtx -frv_ifcvt_modify_insn (ce_info, pattern, insn) - ce_if_block_t *ce_info ATTRIBUTE_UNUSED; - rtx pattern; - rtx insn; +frv_ifcvt_modify_insn (ce_if_block_t *ce_info, + rtx pattern, + rtx insn) { rtx orig_ce_pattern = pattern; rtx set; @@ -7316,7 +7009,7 @@ frv_ifcvt_modify_insn (ce_info, pattern, insn) rtx src = SET_SRC (set); enum machine_mode mode = GET_MODE (dest); - /* Check for normal binary operators */ + /* Check for normal binary operators. */ if (mode == SImode && (GET_RTX_CLASS (GET_CODE (src)) == '2' || GET_RTX_CLASS (GET_CODE (src)) == 'c')) @@ -7378,7 +7071,16 @@ frv_ifcvt_modify_insn (ce_info, pattern, insn) other registers. */ else if (frv_ifcvt.scratch_insns_bitmap && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap, - INSN_UID (insn))) + INSN_UID (insn)) + /* We must not unconditionally set a reg set used as + scratch in the THEN branch if the same reg is live + in the ELSE branch. */ + && REG_P (SET_DEST (set)) + && (! ce_info->else_bb + || BLOCK_FOR_INSN (insn) == ce_info->else_bb + || ! (REGNO_REG_SET_P + (ce_info->else_bb->global_live_at_start, + REGNO (SET_DEST (set)))))) pattern = set; else if (mode == QImode || mode == HImode || mode == SImode @@ -7506,8 +7208,7 @@ frv_ifcvt_modify_insn (ce_info, pattern, insn) conditional if information CE_INFO. */ void -frv_ifcvt_modify_final (ce_info) - ce_if_block_t *ce_info ATTRIBUTE_UNUSED; +frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) { rtx existing_insn; rtx check_insn; @@ -7563,8 +7264,7 @@ frv_ifcvt_modify_final (ce_info) information CE_INFO. */ void -frv_ifcvt_modify_cancel (ce_info) - ce_if_block_t *ce_info ATTRIBUTE_UNUSED; +frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED) { int i; rtx p = frv_ifcvt.added_insns_list; @@ -7599,7 +7299,7 @@ frv_ifcvt_modify_cancel (ce_info) jmpl @(gr0,<jmp_reg>) */ int -frv_trampoline_size () +frv_trampoline_size (void) { return 5 /* instructions */ * 4 /* instruction size */; } @@ -7619,10 +7319,7 @@ frv_trampoline_size () jmpl @(gr0,<jmp_reg>) */ void -frv_initialize_trampoline (addr, fnaddr, static_chain) - rtx addr; - rtx fnaddr; - rtx static_chain; +frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain) { rtx sc_reg = force_reg (Pmode, static_chain); @@ -7688,11 +7385,10 @@ frv_initialize_trampoline (addr, fnaddr, static_chain) This case often occurs between floating-point and general registers. */ enum reg_class -frv_secondary_reload_class (class, mode, x, in_p) - enum reg_class class; - enum machine_mode mode ATTRIBUTE_UNUSED; - rtx x; - int in_p ATTRIBUTE_UNUSED; +frv_secondary_reload_class (enum reg_class class, + enum machine_mode mode ATTRIBUTE_UNUSED, + rtx x, + int in_p ATTRIBUTE_UNUSED) { enum reg_class ret; @@ -7768,8 +7464,7 @@ frv_secondary_reload_class (class, mode, x, in_p) register allocation. */ int -frv_class_likely_spilled_p (class) - enum reg_class class; +frv_class_likely_spilled_p (enum reg_class class) { switch (class) { @@ -7797,7 +7492,7 @@ frv_class_likely_spilled_p (class) /* An expression for the alignment of a structure field FIELD if the - alignment computed in the usual way is COMPUTED. GNU CC uses this + alignment computed in the usual way is COMPUTED. GCC uses this value instead of the value in `BIGGEST_ALIGNMENT' or `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ @@ -7844,19 +7539,16 @@ frv_class_likely_spilled_p (class) */ int -frv_adjust_field_align (field, computed) - tree field; - int computed; +frv_adjust_field_align (tree field, int computed) { - /* C++ provides a null DECL_CONTEXT if the bit field is wider than its - type. */ - if (DECL_BIT_FIELD (field) && DECL_CONTEXT (field)) + /* Make sure that the bitfield is not wider than the type. */ + if (DECL_BIT_FIELD (field) + && !DECL_ARTIFICIAL (field)) { tree parent = DECL_CONTEXT (field); tree prev = NULL_TREE; tree cur; - /* Loop finding the previous field to the current one */ for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur)) { if (TREE_CODE (cur) != FIELD_DECL) @@ -7870,7 +7562,7 @@ frv_adjust_field_align (field, computed) /* If this isn't a :0 field and if the previous element is a bitfield also, see if the type is different, if so, we will need to align the - bit-field to the next boundary */ + bit-field to the next boundary. */ if (prev && ! DECL_PACKED (field) && ! integer_zerop (DECL_SIZE (field)) @@ -7941,9 +7633,7 @@ frv_adjust_field_align (field, computed) pattern's constraint asks for one. */ int -frv_hard_regno_mode_ok (regno, mode) - int regno; - enum machine_mode mode; +frv_hard_regno_mode_ok (int regno, enum machine_mode mode) { int base; int mask; @@ -7979,8 +7669,8 @@ frv_hard_regno_mode_ok (regno, mode) } else { - /* The other registers store one word. */ - if (GPR_P (regno)) + /* The other registers store one word. */ + if (GPR_P (regno) || regno == AP_FIRST) base = GPR_FIRST; else if (FPR_P (regno)) @@ -7989,6 +7679,10 @@ frv_hard_regno_mode_ok (regno, mode) else if (ACC_P (regno)) base = ACC_FIRST; + else if (SPR_P (regno)) + return mode == SImode; + + /* Fill in the table. */ else return 0; @@ -8021,9 +7715,7 @@ frv_hard_regno_mode_ok (regno, mode) for each byte. */ int -frv_hard_regno_nregs (regno, mode) - int regno; - enum machine_mode mode; +frv_hard_regno_nregs (int regno, enum machine_mode mode) { if (ACCG_P (regno)) return GET_MODE_SIZE (mode); @@ -8045,9 +7737,7 @@ frv_hard_regno_nregs (regno, mode) This declaration is required. */ int -frv_class_max_nregs (class, mode) - enum reg_class class; - enum machine_mode mode; +frv_class_max_nregs (enum reg_class class, enum machine_mode mode) { if (class == ACCG_REGS) /* An N-byte value requires N accumulator guards. */ @@ -8063,25 +7753,24 @@ frv_class_max_nregs (class, mode) definition for this macro on machines where anything `CONSTANT_P' is valid. */ int -frv_legitimate_constant_p (x) - rtx x; +frv_legitimate_constant_p (rtx x) { enum machine_mode mode = GET_MODE (x); - /* All of the integer constants are ok */ + /* All of the integer constants are ok. */ if (GET_CODE (x) != CONST_DOUBLE) return TRUE; - /* double integer constants are ok */ + /* double integer constants are ok. */ if (mode == VOIDmode || mode == DImode) return TRUE; - /* 0 is always ok */ + /* 0 is always ok. */ if (x == CONST0_RTX (mode)) return TRUE; /* If floating point is just emulated, allow any constant, since it will be - constructed in the GPRs */ + constructed in the GPRs. */ if (!TARGET_HAS_FPRS) return TRUE; @@ -8113,9 +7802,7 @@ frv_legitimate_constant_p (x) #define LOW_COST 1 int -frv_register_move_cost (from, to) - enum reg_class from; - enum reg_class to; +frv_register_move_cost (enum reg_class from, enum reg_class to) { switch (from) { @@ -8204,10 +7891,7 @@ frv_register_move_cost (from, to) need a fixup entry for aligned (non-debugging) code. */ static bool -frv_assemble_integer (value, size, aligned_p) - rtx value; - unsigned int size; - int aligned_p; +frv_assemble_integer (rtx value, unsigned int size, int aligned_p) { if (flag_pic && size == UNITS_PER_WORD) { @@ -8246,22 +7930,54 @@ frv_assemble_integer (value, size, aligned_p) /* Function to set up the backend function structure. */ static struct machine_function * -frv_init_machine_status () +frv_init_machine_status (void) { return ggc_alloc_cleared (sizeof (struct machine_function)); } + +/* Implement TARGET_SCHED_ISSUE_RATE. */ + +static int +frv_issue_rate (void) +{ + if (!TARGET_PACK) + return 1; + + switch (frv_cpu_type) + { + default: + case FRV_CPU_FR300: + case FRV_CPU_SIMPLE: + return 1; + + case FRV_CPU_FR400: + return 2; + + case FRV_CPU_GENERIC: + case FRV_CPU_FR500: + case FRV_CPU_TOMCAT: + return 4; + } +} + +/* Implement TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. */ + +static int +frv_use_dfa_pipeline_interface (void) +{ + return true; +} /* Update the register state information, to know about which registers are set or clobbered. */ static void -frv_registers_update (x, reg_state, modified, p_num_mod, flag) - rtx x; - unsigned char reg_state[]; - int modified[]; - int *p_num_mod; - int flag; +frv_registers_update (rtx x, + unsigned char reg_state[], + int modified[], + int *p_num_mod, + int flag) { int regno, reg_max; rtx reg; @@ -8333,7 +8049,7 @@ frv_registers_update (x, reg_state, modified, p_num_mod, flag) case REG: regno = REGNO (x); reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); - /* fall through */ + /* Fall through. */ reg_common: if (flag & REGSTATE_MODIFIED) @@ -8404,10 +8120,7 @@ frv_registers_update (x, reg_state, modified, p_num_mod, flag) /* Return if any registers in a hard register set were used an insn. */ static int -frv_registers_used_p (x, reg_state, flag) - rtx x; - unsigned char reg_state[]; - int flag; +frv_registers_used_p (rtx x, unsigned char reg_state[], int flag) { int regno, reg_max; rtx reg; @@ -8423,7 +8136,7 @@ frv_registers_used_p (x, reg_state, flag) default: break; - /* Skip clobber, that doesn't use the previous value */ + /* Skip clobber, that doesn't use the previous value. */ case CLOBBER: return FALSE; @@ -8488,7 +8201,7 @@ frv_registers_used_p (x, reg_state, flag) case REG: regno = REGNO (x); reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); - /* fall through */ + /* Fall through. */ reg_common: while (regno < reg_max) @@ -8509,7 +8222,7 @@ frv_registers_used_p (x, reg_state, flag) expression that governs this expression (ie, true vs. false for the same CC register). If this isn't two halves of the same conditional expression, consider the register - modified. */ + modified. */ if (((rs_if == REGSTATE_IF_TRUE && flag_if == REGSTATE_IF_FALSE) || (rs_if == REGSTATE_IF_FALSE && flag_if == REGSTATE_IF_TRUE)) && ((rs & REGSTATE_CC_MASK) == (flag & REGSTATE_CC_MASK))) @@ -8564,10 +8277,7 @@ frv_registers_used_p (x, reg_state, flag) /* Return if any registers in a hard register set were set in an insn. */ static int -frv_registers_set_p (x, reg_state, modify_p) - rtx x; - unsigned char reg_state[]; - int modify_p; +frv_registers_set_p (rtx x, unsigned char reg_state[], int modify_p) { int regno, reg_max; rtx reg; @@ -8591,7 +8301,7 @@ frv_registers_set_p (x, reg_state, modify_p) case COND_EXEC: cond = XEXP (x, 0); - /* just to be sure, make sure it is the type of cond_exec we + /* Just to be sure, make sure it is the type of cond_exec we expect. */ if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) && GET_CODE (XEXP (cond, 0)) == REG @@ -8622,7 +8332,7 @@ frv_registers_set_p (x, reg_state, modify_p) case REG: regno = REGNO (x); reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); - /* fall through */ + /* Fall through. */ reg_common: if (modify_p) @@ -8672,18 +8382,13 @@ frv_registers_set_p (x, reg_state, modify_p) } -/* In rare cases, correct code generation requires extra machine dependent - processing between the second jump optimization pass and delayed branch - scheduling. On those machines, define this macro as a C statement to act on - the code starting at INSN. */ - /* On the FR-V, this pass is used to rescan the insn chain, and pack conditional branches/calls/jumps, etc. with previous insns where it can. It does not reorder the instructions. We assume the scheduler left the flow information in a reasonable state. */ static void -frv_pack_insns () +frv_pack_insns (void) { state_t frv_state; /* frv state machine */ int cur_start_vliw_p; /* current insn starts a VLIW insn */ @@ -8699,27 +8404,16 @@ frv_pack_insns () unsigned char reg_state[FIRST_PSEUDO_REGISTER]; /* If we weren't going to pack the insns, don't bother with this pass. */ - if (!optimize || !flag_schedule_insns_after_reload || TARGET_NO_VLIW_BRANCH) + if (!optimize + || !flag_schedule_insns_after_reload + || TARGET_NO_VLIW_BRANCH + || frv_issue_rate () == 1) return; - switch (frv_cpu_type) - { - default: - case FRV_CPU_FR300: /* FR300/simple are single issue */ - case FRV_CPU_SIMPLE: - return; - - case FRV_CPU_GENERIC: /* FR-V and FR500 are multi-issue */ - case FRV_CPU_FR400: - case FRV_CPU_FR500: - case FRV_CPU_TOMCAT: - break; - } - /* Set up the instruction and register states. */ dfa_start (); frv_state = (state_t) xmalloc (state_size ()); - memset ((PTR) reg_state, REGSTATE_DEAD, sizeof (reg_state)); + memset (reg_state, REGSTATE_DEAD, sizeof (reg_state)); /* Go through the insns, and repack the insns. */ state_reset (frv_state); @@ -8754,7 +8448,7 @@ frv_pack_insns () continue; } - /* things like labels reset everything. */ + /* Things like labels reset everything. */ if (GET_RTX_CLASS (code) != 'i') { next_start_vliw_p = TRUE; @@ -8762,7 +8456,7 @@ frv_pack_insns () } /* Clear the VLIW start flag on random USE and CLOBBER insns, which is - set on the USE insn that preceeds the return, and potentially on + set on the USE insn that precedes the return, and potentially on CLOBBERs for setting multiword variables. Also skip the ADDR_VEC holding the case table labels. */ pattern_code = GET_CODE (PATTERN (insn)); @@ -8808,7 +8502,7 @@ frv_pack_insns () partnering sethi instruction, with which it can be packed. Although output dependencies are rare they are still - possible. So check output dependencies in VLIW insn. */ + possible. So check output dependencies in VLIW insn. */ || (get_attr_type (insn) != TYPE_SETLO && (frv_registers_used_p (PATTERN (insn), reg_state, @@ -8835,7 +8529,7 @@ frv_pack_insns () /* Record which registers are modified. */ frv_registers_update (PATTERN (insn), reg_state, modified, &num_mod, 0); - /* Process the death notices */ + /* Process the death notices. */ for (link = REG_NOTES (insn); link != NULL_RTX; link = XEXP (link, 1)) @@ -8852,7 +8546,7 @@ frv_pack_insns () } } - free ((PTR) frv_state); + free (frv_state); dfa_finish (); return; } @@ -8877,7 +8571,7 @@ static struct builtin_description bdesc_set[] = { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 } }; -/* Media intrinsics that take just one argument. */ +/* Media intrinsics that take just one argument. */ static struct builtin_description bdesc_1arg[] = { @@ -8888,7 +8582,7 @@ static struct builtin_description bdesc_1arg[] = { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 } }; -/* Media intrinsics that take two arguments. */ +/* Media intrinsics that take two arguments. */ static struct builtin_description bdesc_2arg[] = { @@ -8923,7 +8617,7 @@ static struct builtin_description bdesc_cut[] = { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 } }; -/* Two-argument media intrinsics with an immediate second argument. */ +/* Two-argument media intrinsics with an immediate second argument. */ static struct builtin_description bdesc_2argimm[] = { @@ -8945,7 +8639,7 @@ static struct builtin_description bdesc_2argimm[] = }; /* Media intrinsics that take two arguments and return void, the first argument - being a pointer to 4 words in memory. */ + being a pointer to 4 words in memory. */ static struct builtin_description bdesc_void2arg[] = { @@ -8954,7 +8648,7 @@ static struct builtin_description bdesc_void2arg[] = }; /* Media intrinsics that take three arguments, the first being a const_int that - denotes an accumulator, and that return void. */ + denotes an accumulator, and that return void. */ static struct builtin_description bdesc_void3arg[] = { @@ -8998,10 +8692,10 @@ static struct builtin_description bdesc_voidacc[] = { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 } }; -/* Initialize media builtins. */ +/* Initialize media builtins. */ static void -frv_init_builtins () +frv_init_builtins (void) { tree endlink = void_list_node; tree accumulator = integer_type_node; @@ -9112,7 +8806,7 @@ frv_init_builtins () def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH); def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH); def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH); - def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH); + def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH); def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH); def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB); def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE); @@ -9152,6 +8846,54 @@ frv_init_builtins () #undef TRINARY } +/* Set the names for various arithmetic operations according to the + FRV ABI. */ +static void +frv_init_libfuncs (void) +{ + set_optab_libfunc (smod_optab, SImode, "__modi"); + set_optab_libfunc (umod_optab, SImode, "__umodi"); + + set_optab_libfunc (add_optab, DImode, "__addll"); + set_optab_libfunc (sub_optab, DImode, "__subll"); + set_optab_libfunc (smul_optab, DImode, "__mulll"); + set_optab_libfunc (sdiv_optab, DImode, "__divll"); + set_optab_libfunc (smod_optab, DImode, "__modll"); + set_optab_libfunc (umod_optab, DImode, "__umodll"); + set_optab_libfunc (and_optab, DImode, "__andll"); + set_optab_libfunc (ior_optab, DImode, "__orll"); + set_optab_libfunc (xor_optab, DImode, "__xorll"); + set_optab_libfunc (one_cmpl_optab, DImode, "__notll"); + + set_optab_libfunc (add_optab, SFmode, "__addf"); + set_optab_libfunc (sub_optab, SFmode, "__subf"); + set_optab_libfunc (smul_optab, SFmode, "__mulf"); + set_optab_libfunc (sdiv_optab, SFmode, "__divf"); + + set_optab_libfunc (add_optab, DFmode, "__addd"); + set_optab_libfunc (sub_optab, DFmode, "__subd"); + set_optab_libfunc (smul_optab, DFmode, "__muld"); + set_optab_libfunc (sdiv_optab, DFmode, "__divd"); + + set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod"); + set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof"); + + set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi"); + set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); + set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi"); + set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); + + set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui"); + set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); + set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui"); + set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); + + set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof"); + set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof"); + set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod"); + set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod"); +} + /* Convert an integer constant to an accumulator register. ICODE is the code of the target instruction, OPNUM is the number of the accumulator operand and OPVAL is the constant integer. Try both @@ -9159,10 +8901,7 @@ frv_init_builtins () instruction. */ static rtx -frv_int_to_acc (icode, opnum, opval) - enum insn_code icode; - int opnum; - rtx opval; +frv_int_to_acc (enum insn_code icode, int opnum, rtx opval) { rtx reg; @@ -9194,8 +8933,7 @@ frv_int_to_acc (icode, opnum, opval) should have. */ static enum machine_mode -frv_matching_accg_mode (mode) - enum machine_mode mode; +frv_matching_accg_mode (enum machine_mode mode) { switch (mode) { @@ -9218,8 +8956,7 @@ frv_matching_accg_mode (mode) class as ACC, but is four times smaller. */ rtx -frv_matching_accg_for_acc (acc) - rtx acc; +frv_matching_accg_for_acc (rtx acc) { return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)), REGNO (acc) - ACC_FIRST + ACCG_FIRST); @@ -9230,8 +8967,7 @@ frv_matching_accg_for_acc (acc) list. */ static rtx -frv_read_argument (arglistptr) - tree *arglistptr; +frv_read_argument (tree *arglistptr) { tree next = TREE_VALUE (*arglistptr); *arglistptr = TREE_CHAIN (*arglistptr); @@ -9243,10 +8979,7 @@ frv_read_argument (arglistptr) function prints an error if OPVAL is not valid. */ static int -frv_check_constant_argument (icode, opnum, opval) - enum insn_code icode; - int opnum; - rtx opval; +frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval) { if (GET_CODE (opval) != CONST_INT) { @@ -9266,9 +8999,7 @@ frv_check_constant_argument (icode, opnum, opval) predicate. */ static rtx -frv_legitimize_target (icode, target) - enum insn_code icode; - rtx target; +frv_legitimize_target (enum insn_code icode, rtx target) { enum machine_mode mode = insn_data[icode].operand[0].mode; @@ -9281,15 +9012,12 @@ frv_legitimize_target (icode, target) } /* Given that ARG is being passed as operand OPNUM to instruction ICODE, - check whether ARG satisfies the operand's contraints. If it doesn't, + check whether ARG satisfies the operand's constraints. If it doesn't, copy ARG to a temporary register and return that. Otherwise return ARG itself. */ static rtx -frv_legitimize_argument (icode, opnum, arg) - enum insn_code icode; - int opnum; - rtx arg; +frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg) { enum machine_mode mode = insn_data[icode].operand[opnum].mode; @@ -9303,10 +9031,7 @@ frv_legitimize_argument (icode, opnum, arg) only MHDSETS falls into this category. */ static rtx -frv_expand_set_builtin (icode, arglist, target) - enum insn_code icode; - tree arglist; - rtx target; +frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target) { rtx pat; rtx op0 = frv_read_argument (&arglist); @@ -9323,13 +9048,10 @@ frv_expand_set_builtin (icode, arglist, target) return target; } -/* Expand builtins that take one operand. */ +/* Expand builtins that take one operand. */ static rtx -frv_expand_unop_builtin (icode, arglist, target) - enum insn_code icode; - tree arglist; - rtx target; +frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) { rtx pat; rtx op0 = frv_read_argument (&arglist); @@ -9344,13 +9066,10 @@ frv_expand_unop_builtin (icode, arglist, target) return target; } -/* Expand builtins that take two operands. */ +/* Expand builtins that take two operands. */ static rtx -frv_expand_binop_builtin (icode, arglist, target) - enum insn_code icode; - tree arglist; - rtx target; +frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) { rtx pat; rtx op0 = frv_read_argument (&arglist); @@ -9368,13 +9087,10 @@ frv_expand_binop_builtin (icode, arglist, target) } /* Expand cut-style builtins, which take two operands and an implicit ACCG - one. */ + one. */ static rtx -frv_expand_cut_builtin (icode, arglist, target) - enum insn_code icode; - tree arglist; - rtx target; +frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target) { rtx pat; rtx op0 = frv_read_argument (&arglist); @@ -9403,13 +9119,10 @@ frv_expand_cut_builtin (icode, arglist, target) return target; } -/* Expand builtins that take two operands and the second is immediate. */ +/* Expand builtins that take two operands and the second is immediate. */ static rtx -frv_expand_binopimm_builtin (icode, arglist, target) - enum insn_code icode; - tree arglist; - rtx target; +frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target) { rtx pat; rtx op0 = frv_read_argument (&arglist); @@ -9429,12 +9142,10 @@ frv_expand_binopimm_builtin (icode, arglist, target) } /* Expand builtins that take two operands, the first operand being a pointer to - ints and return void. */ + ints and return void. */ static rtx -frv_expand_voidbinop_builtin (icode, arglist) - enum insn_code icode; - tree arglist; +frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist) { rtx pat; rtx op0 = frv_read_argument (&arglist); @@ -9475,9 +9186,7 @@ frv_expand_voidbinop_builtin (icode, arglist) corresponds to the accumulator. */ static rtx -frv_expand_voidtriop_builtin (icode, arglist) - enum insn_code icode; - tree arglist; +frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist) { rtx pat; rtx op0 = frv_read_argument (&arglist); @@ -9505,9 +9214,7 @@ frv_expand_voidtriop_builtin (icode, arglist) void. */ static rtx -frv_expand_voidaccop_builtin (icode, arglist) - enum insn_code icode; - tree arglist; +frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist) { rtx pat; rtx op0 = frv_read_argument (&arglist); @@ -9537,8 +9244,7 @@ frv_expand_voidaccop_builtin (icode, arglist) number as argument. */ static rtx -frv_expand_mclracc_builtin (arglist) - tree arglist; +frv_expand_mclracc_builtin (tree arglist) { enum insn_code icode = CODE_FOR_mclracc; rtx pat; @@ -9558,8 +9264,7 @@ frv_expand_mclracc_builtin (arglist) /* Expand builtins that take no arguments. */ static rtx -frv_expand_noargs_builtin (icode) - enum insn_code icode; +frv_expand_noargs_builtin (enum insn_code icode) { rtx pat = GEN_FCN (icode) (GEN_INT (0)); if (pat) @@ -9572,9 +9277,7 @@ frv_expand_noargs_builtin (icode) number or accumulator guard number as argument and return an SI integer. */ static rtx -frv_expand_mrdacc_builtin (icode, arglist) - enum insn_code icode; - tree arglist; +frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist) { rtx pat; rtx target = gen_reg_rtx (SImode); @@ -9597,9 +9300,7 @@ frv_expand_mrdacc_builtin (icode, arglist) second. */ static rtx -frv_expand_mwtacc_builtin (icode, arglist) - enum insn_code icode; - tree arglist; +frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist) { rtx pat; rtx op0 = frv_read_argument (&arglist); @@ -9617,15 +9318,14 @@ frv_expand_mwtacc_builtin (icode, arglist) return NULL_RTX; } -/* Expand builtins. */ +/* Expand builtins. */ static rtx -frv_expand_builtin (exp, target, subtarget, mode, ignore) - tree exp; - rtx target; - rtx subtarget ATTRIBUTE_UNUSED; - enum machine_mode mode ATTRIBUTE_UNUSED; - int ignore ATTRIBUTE_UNUSED; +frv_expand_builtin (tree exp, + rtx target, + rtx subtarget ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, + int ignore ATTRIBUTE_UNUSED) { tree arglist = TREE_OPERAND (exp, 1); tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); @@ -9684,7 +9384,7 @@ frv_expand_builtin (exp, target, subtarget, mode, ignore) break; } - /* Expand unique builtins. */ + /* Expand unique builtins. */ switch (fcode) { @@ -9716,73 +9416,151 @@ frv_expand_builtin (exp, target, subtarget, mode, ignore) break; } - /* Expand groups of builtins. */ + /* Expand groups of builtins. */ - for (i = 0, d = bdesc_set; i < sizeof (bdesc_set) / sizeof *d; i++, d++) + for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++) if (d->code == fcode) return frv_expand_set_builtin (d->icode, arglist, target); - for (i = 0, d = bdesc_1arg; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++) + for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) if (d->code == fcode) return frv_expand_unop_builtin (d->icode, arglist, target); - for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) if (d->code == fcode) return frv_expand_binop_builtin (d->icode, arglist, target); - for (i = 0, d = bdesc_cut; i < sizeof (bdesc_cut) / sizeof *d; i++, d++) + for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++) if (d->code == fcode) return frv_expand_cut_builtin (d->icode, arglist, target); - for (i = 0, d = bdesc_2argimm; - i < sizeof (bdesc_2argimm) / sizeof *d; - i++, d++) - { - if (d->code == fcode) - return frv_expand_binopimm_builtin (d->icode, arglist, target); - } + for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++) + if (d->code == fcode) + return frv_expand_binopimm_builtin (d->icode, arglist, target); - for (i = 0, d = bdesc_void2arg; - i < sizeof (bdesc_void2arg) / sizeof *d; - i++, d++) - { - if (d->code == fcode) - return frv_expand_voidbinop_builtin (d->icode, arglist); - } + for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++) + if (d->code == fcode) + return frv_expand_voidbinop_builtin (d->icode, arglist); + + for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++) + if (d->code == fcode) + return frv_expand_voidtriop_builtin (d->icode, arglist); + + for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++) + if (d->code == fcode) + return frv_expand_voidaccop_builtin (d->icode, arglist); + + return 0; +} - for (i = 0, d = bdesc_void3arg; - i < sizeof (bdesc_void3arg) / sizeof *d; - i++, d++) +static bool +frv_in_small_data_p (tree decl) +{ + HOST_WIDE_INT size; + tree section_name; + + /* Don't apply the -G flag to internal compiler structures. We + should leave such structures in the main data section, partly + for efficiency and partly because the size of some of them + (such as C++ typeinfos) is not known until later. */ + if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl)) + return false; + + /* If we already know which section the decl should be in, see if + it's a small data section. */ + section_name = DECL_SECTION_NAME (decl); + if (section_name) { - if (d->code == fcode) - return frv_expand_voidtriop_builtin (d->icode, arglist); + if (TREE_CODE (section_name) != STRING_CST) + abort (); + if (frv_string_begins_with (section_name, ".sdata")) + return true; + if (frv_string_begins_with (section_name, ".sbss")) + return true; + return false; } - for (i = 0, d = bdesc_voidacc; - i < sizeof (bdesc_voidacc) / sizeof *d; - i++, d++) + size = int_size_in_bytes (TREE_TYPE (decl)); + if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) + return true; + + return false; +} + +static bool +frv_rtx_costs (rtx x, + int code ATTRIBUTE_UNUSED, + int outer_code ATTRIBUTE_UNUSED, + int *total) +{ + switch (code) { - if (d->code == fcode) - return frv_expand_voidaccop_builtin (d->icode, arglist); + case CONST_INT: + /* Make 12 bit integers really cheap. */ + if (IN_RANGE_P (INTVAL (x), -2048, 2047)) + { + *total = 0; + return true; + } + /* Fall through. */ + + case CONST: + case LABEL_REF: + case SYMBOL_REF: + case CONST_DOUBLE: + *total = COSTS_N_INSNS (2); + return true; + + case PLUS: + case MINUS: + case AND: + case IOR: + case XOR: + case ASHIFT: + case ASHIFTRT: + case LSHIFTRT: + case NOT: + case NEG: + case COMPARE: + if (GET_MODE (x) == SImode) + *total = COSTS_N_INSNS (1); + else if (GET_MODE (x) == DImode) + *total = COSTS_N_INSNS (2); + else + *total = COSTS_N_INSNS (3); + return true; + + case MULT: + if (GET_MODE (x) == SImode) + *total = COSTS_N_INSNS (2); + else + *total = COSTS_N_INSNS (6); /* guess */ + return true; + + case DIV: + case UDIV: + case MOD: + case UMOD: + *total = COSTS_N_INSNS (18); + return true; + + default: + return false; } - return 0; } - -static const char * -frv_strip_name_encoding (str) - const char *str; + +static void +frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) { - while (*str == '*' || *str == SDATA_FLAG_CHAR) - str++; - return str; + ctors_section (); + assemble_align (POINTER_SIZE); + assemble_integer_with_op ("\t.picptr\t", symbol); } -static bool -frv_in_small_data_p (decl) - tree decl; +static void +frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) { - HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); - - return symbol_ref_small_data_p (XEXP (DECL_RTL (decl), 0)) - && size > 0 && size <= g_switch_value; + dtors_section (); + assemble_align (POINTER_SIZE); + assemble_integer_with_op ("\t.picptr\t", symbol); } |
