diff options
Diffstat (limited to 'contrib/binutils/opcodes')
71 files changed, 0 insertions, 64338 deletions
diff --git a/contrib/binutils/opcodes/ChangeLog b/contrib/binutils/opcodes/ChangeLog deleted file mode 100644 index 88c6b3e..0000000 --- a/contrib/binutils/opcodes/ChangeLog +++ /dev/null @@ -1,191 +0,0 @@ -2004-05-13 Nick Clifton <nickc@redhat.com> - - * po/fr.po: Updated French translation. - -2004-05-05 Alan Modra <amodra@bigpond.net.au> - - PR 146. - * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC. - -2004-04-09 Daniel Jacobowitz <drow@mvista.com> - - Merge from mainline: - 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> - * m32r-asm.c: Regenerate. - - 2004-03-08 Nick Clifton <nickc@redhat.com> - * po/de.po: Updated German translation. - - 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com> - * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4. - Also correct mistake in the comment. - - 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com> - * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to - ensure that double registers have even numbers. - Add REG_N_B01 for nn01 (binary 01) nibble to ensure - that reserved instruction 0xfffd does not decode the same - as 0xfdfd (ftrv). - * sh-opc.h: Add REG_N_D nibble type and use it whereever - REG_N refers to a double register. - Add REG_N_B01 nibble type and use it instead of REG_NM - in ftrv. - Adjust the bit patterns in a few comments. - -2004-04-08 Alan Modra <amodra@bigpond.net.au> - - Apply from mainline. - 2004-02-25 Aldy Hernandez <aldyh@redhat.com> - * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst. - - 2004-02-20 Aldy Hernandez <aldyh@redhat.com> - * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat. - - 2004-02-20 Aldy Hernandez <aldyh@redhat.com> - * ppc-opc.c (powerpc_opcodes): Add m*ivor35. - - 2004-02-20 Aldy Hernandez <aldyh@redhat.com> - * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34, - mtivor32, mtivor33, mtivor34. - - 2004-02-19 Aldy Hernandez <aldyh@redhat.com> - * ppc-opc.c (powerpc_opcodes): Add mfmcar. - -2004-03-15 Aldy Hernandez <aldyh@redhat.com> - - * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg. - -2004-03-16 Alan Modra <amodra@bigpond.net.au> - - * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle - PPC_OPERANDS_GPR_0. - * ppc-opc.c (RA0): Define. - (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0. - (RAOPT): Rename from RAO. Update all uses. - (powerpc_opcodes): Use RA0 as appropriate. - -2004-03-15 Alan Modra <amodra@bigpond.net.au> - - * sparc-dis.c (print_insn_sparc): Update getword prototype. - -2004-03-13 Alan Modra <amodra@bigpond.net.au> - - Apply the following patches from mainline - 2004-03-12 Michal Ludvig <mludvig@suse.cz> - * i386-dis.c (GRPPLOCK): Delete. - (grps): Delete GRPPLOCK entry. - - 2004-03-12 Alan Modra <amodra@bigpond.net.au> - * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions. - (M, Mp): Use OP_M. - (None, PADLOCK_SPECIAL, PADLOCK_0): Delete. - (GRPPADLCK): Define. - (dis386): Use NOP_Fixup on "nop". - (dis386_twobyte): Use GRPPADLCK on opcode 0xa7. - (twobyte_has_modrm): Set for 0xa7. - (padlock_table): Delete. Move to.. - (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence - and clflush. - (print_insn): Revert PADLOCK_SPECIAL code. - (OP_E): Delete sfence, lfence, mfence checks. - - 2004-03-12 Jakub Jelinek <jakub@redhat.com> - * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg. - (INVLPG_Fixup): New function. - (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag. - - 2004-03-12 Alan Modra <amodra@bigpond.net.au> - * i386-dis.c (grps): Use clflush by default for 0x0fae/7. - (OP_E): Twiddle clflush to sfence here. - -2004-03-12 Michal Ludvig <mludvig@suse.cz> - - * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines. - (dis386_twobyte): Opcode 0xa7 is PADLOCK_0. - (padlock_table): New struct with PadLock instructions. - (print_insn): Handle PADLOCK_SPECIAL. - -2004-02-10 Petko Manolov <petkan@nucleusys.com> - - * arm-opc.h Maverick accumulator register opcode fixes. - -2004-02-13 Ben Elliston <bje@wasabisystems.com> - - * m32r-dis.c: Regenerate. - -2004-01-27 Michael Snyder <msnyder@redhat.com> - - * sh-opc.h (sh_table): "fsrra", not "fssra". - -2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au> - - * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten - contraints. - -2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au> - - * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args. - -2004-01-19 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c (OP_E): Print scale factor on intel mode sib when not - 1. Don't print scale factor on AT&T mode when index missing. - -2004-01-16 Alexandre Oliva <aoliva@redhat.com> - - * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended - when loaded into XR registers. - -2004-01-14 Richard Sandiford <rsandifo@redhat.com> - - * frv-desc.h: Regenerate. - * frv-desc.c: Regenerate. - * frv-opc.c: Regenerate. - -2004-01-13 Michael Snyder <msnyder@redhat.com> - - * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn. - -2004-01-09 Paul Brook <paul@codesourcery.com> - - * arm-opc.h (arm_opcodes): Move generic mcrr after known - specific opcodes. - -2004-01-07 Daniel Jacobowitz <drow@mvista.com> - - * Makefile.am (libopcodes_la_DEPENDENCIES) - (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory - comment about the problem. - * Makefile.in: Regenerate. - -2004-01-06 Alexandre Oliva <aoliva@redhat.com> - - 2003-12-19 Alexandre Oliva <aoliva@redhat.com> - * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some - cut&paste errors in shifting/truncating numerical operands. - 2003-08-04 Alexandre Oliva <aoliva@redhat.com> - * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo. - (parse_uslo16): Likewise. - (parse_uhi16): Parse gotoffhi and gotofffuncdeschi. - (parse_d12): Parse gotoff12 and gotofffuncdesc12. - (parse_s12): Likewise. - 2003-08-04 Alexandre Oliva <aoliva@redhat.com> - * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo. - (parse_uslo16): Likewise. - (parse_uhi16): Parse gothi and gotfuncdeschi. - (parse_d12): Parse got12 and gotfuncdesc12. - (parse_s12): Likewise. - -2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl> - - * msp430-dis.c (msp430_doubleoperand): Check for an 'add' - instruction which looks similar to an 'rla' instruction. - -For older changes see ChangeLog-0203 - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/contrib/binutils/opcodes/ChangeLog-0001 b/contrib/binutils/opcodes/ChangeLog-0001 deleted file mode 100644 index 085453a..0000000 --- a/contrib/binutils/opcodes/ChangeLog-0001 +++ /dev/null @@ -1,2224 +0,0 @@ -2001-12-31 Jeffrey A Law (law@redhat.com) - - * hppa-dis.c (print_insn_hppa): Handle new 'c' mode completers, - 'X', 'M', and 'A'. No longer emit a space after 'x' or 's'. - Always emit a space after 'H'. - -2001-12-18 matthew green <mrg@redhat.com> - - * ppc-opc.c (PPCVEC): Include PPC_OPCODE_ANY. - -2001-12-17 Richard Henderson <rth@redhat.com> - - * alpha-opc.c (unop): Encode with RB as $sp. - -2001-12-07 Geoffrey Keating <geoffk@redhat.com> - - * Makefile.am: Add support for xstormy16. - * Makefile.in: Regenerate. - * configure.in: Add support for xstormy16. - * configure: Regenerate. - * disassemble.c: Add support for xstormy16. - * xstormy16-asm.c: New generated file. - * xstormy16-desc.c: New generated file. - * xstormy16-desc.h: New generated file. - * xstormy16-dis.c: New generated file. - * xstormy16-ibld.c: New generated file. - * xstormy16-opc.c: New generated file. - * xstormy16-opc.h: New generated file. - -2001-12-06 Richard Henderson <rth@redhat.com> - - * alpha-opc.c (alpha_opcodes): Add wh64en. - -2001-12-04 Alexandre Oliva <aoliva@redhat.com> - - * d10v-opc.c (d10v_predefined_registers): Remove warnings - introduced in Nov 29's patch. - - * d10v-dis.c (print_operand): Apply REGISTER_MASK to `num' of - unmatched register. - - * d10v-dis.c (print_operand): Disregard OPERAND_SP in register - predefined value. - - * d10v-opc.c (RSRC_NOSP): New macro. - (d10v_operands): Add it. - (d10v_opcodes): Use RSRC_NOSP in post-decrement "st" and "st2w". - -2001-11-29 Alexandre Oliva <aoliva@redhat.com> - - * d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP. - (RSRC_SP): New macro. - (d10v_operands): Add it. - (d10v_opcodes): Adjust "st" and "st2w" to use RSRC_SP. - -2001-11-23 Lars Brinkhoff <lars@nocrew.org> - - * pdp11-dis.c (print_insn_pdp11): Handle illegal instructions. - Also, break out of the loop as soon as an instruction has been - printed. - -2001-11-17 matthew green <mrg@redhat.com> - - * ppc-opc.c (mfvrsave, mtvrsave): New instructions. - -2001-11-15 Alan Modra <amodra@bigpond.net.au> - - * po/POTFILES.in: Regenerate. - - * ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC. - (insert_bat, extract_bat, insert_bba, extract_bba, - insert_bd, extract_bd, insert_bdm, extract_bdm, - insert_bdp, extract_bdp, valid_bo, - insert_bo, extract_bo, insert_boe, extract_boe, - insert_ds, extract_ds, insert_de, extract_de, - insert_des, extract_des, insert_li, extract_li, - insert_mbe, extract_mbe, insert_mb6, extract_mb6, - insert_nb, extract_nb, insert_nsi, extract_nsi, - insert_ral, insert_ram, insert_ras, - insert_rbs, extract_rbs, insert_sh6, extract_sh6, - insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param. - (extract_bd, extract_bdm, extract_bdp, - extract_ds, extract_des, - extract_li, extract_nsi): Implement sign extension without conditional. - (insert_bdm, extract_bdm, - insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints. - (extract_bdm, extract_bdp): Correct 32 bit validation. - (AT1_MASK, AT2_MASK): Define. - (BBOAT_MASK): Define. - (BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define. - (BOFM64, BOFP64, BOTM64, BOTP64): Define. - (BODNZM64, BODNZP64, BODZM64, BODZP64): Define. - (PPCCOM32, PPCCOM64): Define. - (powerpc_opcodes): Modify existing 32 bit insns with branch hints - and add new patterns to implement 64 bit branches with hints. Move - booke instructions so they match before ppc64. - - * ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for - 64 bit default targets, and parse "32" and "64" in options. - Formatting fixes. - (print_insn_powerpc): Pass dialect to operand->extract. - -2001-11-14 Dave Brolley <brolley@redhat.com> - - * cgen-dis.c (count_decodable_bits): New function. - (add_insn_to_hash_chain): New function. - (hash_insn_array): Call add_insn_to_hash_chain. - (hash_insn_list): Call add_insn_to_hash_chain. - * m32r-dis.c: Regenerated. - * fr30-dis.c: Regenerated. - -2001-11-14 Andreas Jaeger <aj@suse.de> - - * i386-dis.c (print_insn): Use x86-64 as option. - -2001-11-14 Alan Modra <amodra@bigpond.net.au> - - * disassemble.c (disassembler): Call print_insn_i386. - * i386-dis.c (SUFFIX_ALWAYS): Define. - (struct dis_private): Add orig_sizeflag. - (print_insn_i386): Make it a wrapper, calling.. - (print_insn): ..The old body of print_insn_i386. Avoid longjmp - warning without using volatile by moving orig_sizeflag to priv, - and removing inbuf. Parse disassembler_options. - (print_insn_i386_att, print_insn_i386_intel): Move initialisation - code to print_insn. - (putop): Remove #ifdef SUFFIX_ALWAYS. - -2001-11-11 Timothy Wall <twall@alum.mit.edu> - - * tic54x-dis.c: Use revised opcode structure. Export opcode - template lookup. - (has_lkaddr): Don't forget about Lmem insns. - * tic54x-opc.c: Add emulation trap. Parallel table now uses - standard opcode templates. - -2001-11-13 Zack Weinberg <zack@codesourcery.com> - - * i386-dis.c (grps): Change "sldt", "str", and "smsw" entries - to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand - category instead of Ew. - -2001-11-12 Niraj Gupta <ngupta@zumanetworks.com> - - * m68k-opc.c: Fix definitions of wddata[bwl]. - -2001-11-09 Richard Sandiford <rsandifo@redhat.com> - - * cgen-asm.c (cgen_parse_keyword): If the keyword is too big to - fit in the buffer, try to match the empty keyword. - -2001-11-09 Nick Clifton <nickc@cambridge.redhat.com> - - * cgen-ibld.in (extract_1): Fix badly placed #if 0. - * fr30-ibld.c: Regenerate. - * m32r-ibld.c: Regenerate. - * openrisc-ibld.c: Regenerate. - -2001-11-04 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (print_insn_mips): Remove spaces at end of line. - -2001-11-02 Nick Clifton <nickc@cambridge.redhat.com> - - * configure.in (ALL_LINGUAS): Add "fr", "sv" and "tr". - * configure: Regernate. - * po/fr.po: New file. - * po/sv.po: New file. - * po/tr.po: New file. - -2001-11-01 Stephane Carrez <Stephane.Carrez@worldnet.fr> - - * m68hc11-dis.c (print_insn): Fix disassembly of movb with a - constant as source. - -2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> - - * Makefile.am (CFILES): Add mmix-dis.c and mmix-opc.c. Regenerate - dependencies. - * Makefile.in: Regenerate. - * mmix-dis.c, mmix-opc.c: New files. - -2001-10-29 Kazu Hirata <kazu@hxi.com> - - * d30v-dis.c: Fix a comment typo. - -2001-10-23 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and - "bltzall" as writing GPR 31 (since they do). - - * mips-dis.c (print_insn_arg): Calculate info->target - where appropriate. - (print_insn_mips): Fill in instruction info. - (print_mips16_insn_arg): Remove unneded variable 'val'. - Removed duplicated instruction target calculations, - calculate once and print that result. Use same idiom for - masking the jump segment bits as is used in print_insn_arg. - -2001-10-20 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c (CT): Make it an optional operand. - -2001-10-17 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (mips_isa_type): Make the ISA used to disassemble - SB-1 binaries include instructions specific to the SB-1. - * mips-opc.c (SB1): New definition. - (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps", - "recip.ps", "rsqrt.ps", and "sqrt.ps". - -2001-10-17 matthew green <mrg@redhat.com> - - * ppc-opc.c (STRM): New AltiVec operand. - (XDSS): New AltiVec instruction form. - (mtvscr): Correct operand list. - (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions. - -2001-10-17 Alan Modra <amodra@bigpond.net.au> - - * po/POTFILES.in: Regenerate. - -2001-10-13 matthew green <mrg@redhat.com> - - * ppc-opc.c (MO): New macro for MO field of mbar instruction. - (powerpc_opcodes): Add rfci, wrtee, wrteei, mfdcrx, mfdcr, - mtdcrx, mtdcr, msync, dcba and mbar as BookE instructions. - -2001-10-13 Nick Clifton <nickc@cambridge.redhat.com> - - * cgen-ibld.in: Include safe-ctype.h in preference to - ctype.h. - * cgen-asm.in: Include safe-ctype.h in preference to - ctype.h. Fix formatting. Use ISSPACE instead of isspace and - TOLOWER instead of tolower. - (@arch@_cgen_build_insn_regex): Remove duplication of syntax - string elements in constructed regular expression. - * fr30-asm.c: Regenerate. - * fr30-desc.c: Regenerate. - * fr30-ibld.c: Regenerate. - * m32r-asm.c: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-ibld.c: Regenerate. - * openrisc-asm.c: Regenerate. - * openrisc-desc.c: Regenerate. - * openrisc-ibld.c: Regenerate. - * po/opcodes.pot: Regenerate. - -2001-10-12 matthew green <mrg@redhat.com> - - * ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New - instruction field instruction/extraction functions for new BookE - DE form instructions. - (CT): New macro for CT field in an X form instruction. - (DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form - instructions. - (PPC64): Don't include PPC_OPCODE_PPC. - (403): New opcode macro for PPC403 processors. - (BOOKE): New opcode macro for BookE processors. - (bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions. - (bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise. - (dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise. - (stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise. - (mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise. - (subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise. - (subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise. - (addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise. - (lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise. - (stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise. - (tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise. - (lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise. - (stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise. - (lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise. - - * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look - for a disassembler option of `booke', `booke32' or `booke64' to enable - BookE support in the disassembler. - -2001-10-12 John Healy <jhealy@redhat.com> - - * cgen-dis.in (print_insn): Use min (cd->base_insn_bitsize, buflen*8) - for the length when extracting the base part of the insn. - -2001-10-09 Bruno Haible <haible@clisp.cons.org> - - * cgen-asm.in (*_cgen_build_insn_regex): Generate a case sensitive - regular expression. Fix some formatting problems. - * fr30-asm.c: Regenerate. - * openrisc-asm.c: Regenerate. - * m32r-asm.c: Regenerate. - -2001-10-09 Christian Groessler <cpg@aladdin.de> - - * z8k-dis.c (unparse_instr): Fixed formatting. Change disassembly - of indirect register memory accesses to be same format the - assembler accepts. - -2001-10-09 Nick Clifton <nickc@cambridge.redhat.com> - - * sh-opc.h: Fix encoding of least significant nibble of the - DSP single data transfer instructions. - - * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP - instructions. - -2001-10-08 Nick Clifton <nickc@cambridge.redhat.com> - - * cgen-asm.in: Fix compile time warning messages in generated - C files. - * cgen-dis.in: The same. - * cgen-ibld.in: The same. - * fr30-asm.c: Regenerate. - * fr30-desc.c: Regenerate. - * fr30-dis.c: Regenerate. - * fr30-ibld.c: Regenerate. - * fr30-opc.c: Regenerate. - * m32r-asm.c: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-dis.c: Regenerate. - * m32r-ibld.c: Regenerate. - * m32r-opc.c: Regenerate. - * m32r-opinst.c Regenerate. - * openrisc-asm.c: Regenerate. - * openrisc-desc.c: Regenerate. - * openrisc-dis.c: Regenerate. - * openrisc-ibld.c: Regenerate. - * openrisc-opc.c: Regenerate. - * openrisc-opc.h: Regenerate. - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - * po/opcodes.pot: Regenerate. - -2001-10-08 Aldy Hernandez <aldyh@redhat.com> - - * arm-opc.h (arm_opcodes): Add cirrus insns. - - * arm-dis.c (print_insn_arm): Add 'I' case. - -2001-10-03 Alan Modra <amodra@bigpond.net.au> - - * po/POTFILES.in: Regenerate. - * configure: Regenerate. - -2001-10-02 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am (Makefile): Depend on bfd/configure.in. - Run "make dep-am". - * Makefile.in: Regenerate. - -2001-09-30 John Healy <jhealy@redhat.com> - - * cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits - calls to cgen_get_insn_value and cgen_put_insn_value calls. - (extract_1): Switched bfd_get_bits call to cgen_get_insn_value call. - -2001-09-30 Hans-Peter Nilsson <hp@bitrange.com> - - * Makefile.am: Update dependencies with "make dep-am". - * Makefile.in: Regenerate. - -2001-09-26 Alan Modra <amodra@bigpond.net.au> - - * arc-dis.c: Formatting fixes. - (my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE. - -2001-09-21 Bruno Haible <haible@clisp.cons.org> - - * arc-dis.c: Don't include <ctype.h>. - * openrisc-desc.c: Likewise. - * openrisc-ibld.c: Likewise. - -2001-09-20 Nick Clifton <nickc@cambridge.redhat.com> - - * fr30-opc.c: Fix compile time warning messages. - * i370-opc.c: Fix compile time warning messages. - * i960-dis.c: Fix compile time warning messages. - * m32r-asm.c: Fix compile time warning messages. - * m32r-desc.c: Fix compile time warning messages. - * m32r-dis.c: Fix compile time warning messages. - * m32r-ibld.c: Fix compile time warning messages. - * m32r-opc.c: Fix compile time warning messages. - * m32r-opinst.c: Fix compile time warning messages. - * ns32k-dis.c: Fix compile time warning messages. - * openrisc-asm.c: Fix compile time warning messages. - * openrisc-desc.c: Fix compile time warning messages. - * openrisc-dis.c: Fix compile time warning messages. - * openrisc-ibld.c: Fix compile time warning messages. - * openrisc-opc.c: Fix compile time warning messages. - * pdp11-dis.c: Fix compile time warning messages. - * tic54x-dis.c: Fix compile time warning messages. - * v850-opc.c: Fix compile time warning messages. - * vax-dis.c: Fix compile time warning messages. - * w65-opc.h: Fix compile time warning messages. - * z8k-opc.h: Fix compile time warning messages. - * z8kgen.c: Fix compile time warning messages. - -2001-09-19 Nick Clifton <nickc@cambridge.redhat.com> - - * arm-dis.c: Fix compile time warning messages. - * cgen-asm.c: Fix compile time warning messages. - * cgen-dis.c: Fix compile time warning messages. - * cris-dis.c: Fix compile time warning messages. - * d10v-dis.c: Fix compile time warning messages. - * fr30-asm.c: Fix compile time warning messages. - * fr30-desc.c: Fix compile time warning messages. - * fr30-dis.c: Fix compile time warning messages. - * fr30-ibld.c: Fix compile time warning messages. - -2001-09-18 Bruno Haible <haible@clisp.cons.org> - - * cgen-asm.c: Include "safe-ctype.h" instead of <ctype.h>. - (cgen_parse_keyword): Use ISALNUM instead of isalnum. - * cgen-opc.c: Include "safe-ctype.h" instead of <ctype.h>. - (cgen_keyword_lookup_name): Use ISALPHA/TOLOWER instead of - isalpha/tolower. - (cgen_keyword_add): Use ISALNUM instead of isalnum. - (hash_keyword_name): Use TOLOWER instead of tolower. - * fr30-asm.c: Include "safe-ctype.h" instead of <ctype.h>. - (parse_insn_normal): Use TOLOWER/ISSPACE instead of - tolower/isspace. - (fr30_cgen_assemble_insn): Use ISSPACE instead of isspace. - * fr30-desc.c: Don't include <ctype.h>. - * fr30-ibld.c: Likewise. - * ia64-gen.c: Include "safe-ctype.h" instead of <ctype.h>. - (load_insn_classes, parse_resource_users, load_depfile): Use - ISSPACE instead of isspace. - * m32r-asm.c: Include "safe-ctype.h" instead of <ctype.h>. - (parse_insn_normal): Use TOLOWER/ISSPACE instead of - tolower/isspace. - (m32r_cgen_assemble_insn): Use ISSPACE instead of isspace. - * m32r-desc.c: Don't include <ctype.h>. - * m32r-ibld.c: Likewise. - * openrisc-asm.c: Include "safe-ctype.h" instead of <ctype.h>. - (parse_insn_normal): Use TOLOWER/ISSPACE instead of - tolower/isspace. - (openrisc_cgen_assemble_insn): Use ISSPACE instead of isspace. - -2001-09-18 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * Makefile.am: Add rules and dependencies to create the s/390 opcode - table out of s390-opc.txt automatically. - * configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used. - * s390-mkopc.c (dumpTable): Change output to create a complete file. - * s390-opc.c: New improved opcode format macros and remove the - pregenerated opcode table. - * s390-opc.txt: Adapt to new improved opcode format macros. - -2001-09-14 David Schleef <ds@schleef.org> - - * ppc-opc.c (VXA, VXA_MASK): Fix mask bits. - -2001-09-04 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c (grps): Don't print the implicit al/ax/eax register - for opcode 0xf6 or 0xf7 forms of mul, imul, div, idiv insns. - -2001-08-31 Eric Christopher <echristo@redhat.com> - Jason Eckhardt <jle@redhat.com> - - * mips-dis.c: Add support for bfd_mach_mipsisa32 and - bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k, - bfd_mach_mips64. - -2001-08-31 Andreas Jaeger <aj@suse.de> - - * tic54x-opc.c: Add default initializers to avoid warnings. - - * arc-opc.c: Include "sysdep.h" to get stdio.h as include file. - * arc-ext.c: Likewise. - -2001-08-28 matthew green <mrg@redhat.com> - - * ppc-opc.c (icbt): Order correctly. - -2001-08-27 David Edelsohn <dje@watson.ibm.com> - Torbjorn Granlund <tege@swox.com> - - * ppc-opc.c (DS): Add PPC_OPERAND_DS flag. - (LS): Define. - (insert_ds): Complain if not a multiple of 4. - (XSYNC): Define. - (XSYNC_MASK): Define. - (powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev", - "slbmfee". Modify "sync" to use XSYNC_MASK and LS. - -2001-08-26 Andreas Jaeger <aj@suse.de> - - * h8500-opc.h: Add default initializers to h8500_table to shut up - GCC warnings. - -2001-08-25 Andreas Jaeger <aj@suse.de> - - * tic54x-dis.c: Add unused attributes where needed. - - * z8k-dis.c (output_instr): Add unused attribute. - - * h8300-dis.c: Add missing prototypes. - (bfd_h8_disassemble): Make static. - - * cris-dis.c: Add missing prototype. - * h8500-dis.c: Likewise. - * m68hc11-dis.c: Likewise. - * pj-dis.c: Likewise. - * tic54x-dis.c: Likewise. - * v850-dis.c: Likewise. - * vax-dis.c: Likewise. - * w65-dis.c: Likewise. - * z8k-dis.c: Likewise. - - * d10v-dis.c: Add missing prototype. - (dis_long): Remove unused variable. - (dis_2_short): Likewise. - - * sh-dis.c: Add missing prototypes. - * v850-opc.c: Likewise. - Add unused attributes where needed. - - * ns32k-dis.c: Add missing prototypes. - (bit_extract_simple): Remove unused variable. - -2001-08-23 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-opc.c: Add "low or high" and "not low or high" - branch instructions for gcc 3.0. - * s390-opc.txt: Likewise. - -2001-08-21 Andreas Jaeger <aj@suse.de> - - * i960-dis.c: Add parameters for prototypes - (ctrl): Add unused attributes. - (cobr): Likewise. - (put_abs): Likewise. - - * mips-dis.c: Add missing prototypes. - * a29k-dis.c: Likewise. - * arc-dis.c: Likewise. - * ia64-opc.c: Likewise. - - * s390-dis.c: Add missing prototypes. - (init_disasm): Remove unused attribute since the parameter is - used. - -2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-opc.c (M1): Define. Reformatted Code. - (mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps, - mtps, mtps. Typo. - -2001-08-16 Jonathan Larmour <jlarmour@redhat.com> - - * mips-opc.c: R3900s can support all branch likely INSN_MACROs where - the corresponding non-likely insn is in MIPS I. - -2001-08-13 Kazu Hirata <kazu@hxi.com> - - * mcore-dis.c: Fix formatting. - * mips-dis.c: Likewise. - * pj-dis.c: Likewise. - * z8k-dis.c: Likewise. - -2001-08-12 Richard Henderson <rth@redhat.com> - - * cgen-ibld.in (extract_normal): Match type of VALUE and MASK - to *VALUEP. Regenerate all cgen files. - -2001-08-10 Richard Sandiford <rsandifo@redhat.com> - - * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32 - argument. - * mips-opc.c (G6): Undefine. - (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro - as the first "move" alternative. - -2001-08-10 Andreas Jaeger <aj@suse.de> - - * configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes - to build warnings. - * configure: Regenerate. - -2001-08-10 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c: Revert 2001-08-08. - -2001-08-09 Alan Modra <amodra@bigpond.net.au> - - * dis-buf.c (generic_strcat_address): Add missing prototype. - #if 0 the functions as it is unused. - -2001-08-08 Alan Modra <amodra@bigpond.net.au> - - 1999-10-25 Torbjorn Granlund <tege@swox.com> - * ppc-opc.c: Include "bfd.h". - (powerpc_operands): Add new field for reloc type. - -2001-07-21 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (print_insn_arg): Don't use software integer registers - for coprocessor registers. - (get_mips_isa): Removed. - (is_newabi): New function, checks if NewABI is used. - (_print_insn_mips): Get distinction between old ABI and new ABI right. - -2001-08-01 Christian Groessler <cpg@aladdin.de> - - * z8kgen.c: Fixed indentation of opt[] array. Include stdio.h to - get stderr definition. - (internal, gas): Removed warnings. - (gas): Create a correct final entry for created array. - * z8k-opc.h: Recreated with new z8kgen. - -2001-07-28 Kazu Hirata <kazu@hxi.com> - - * i386-dis.c: Fix formatting. - -2001-07-28 Matthias Kramm <kramm@quiss.org> - - * i386-dis.c: Change formatting conventions for architecture - i386:intel to better match the format of various intel i386 - assemblers, like nasm, tasm or masm. - -2001-07-24 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Update dependencies with "make dep-am". - * Makefile.in: Regenerate - -2001-07-24 Kazu Hirata <kazu@hxi.com> - - * alpha-dis.c: Fix formatting. - * cris-dis.c: Likewise. - * d10v-dis.c: Likewise. - * d30v-dis.c: Likewise. - * m10300-dis.c: Likewise. - * tic54x-dis.c: Likewise. - -2001-07-23 Kazu Hirata <kazu@hxi.com> - - * m68k-dis.c: Fix formatting. - * pj-dis.c: Likewise. - * s390-dis.c: Likewise. - * z8k-dis.c: Likewise. - -2001-07-21 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s - into the rest of the surrounding definitions. - -2001-07-18 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c (grps): Print l or w suffix, and require mem modrm - for lgdt, lidt, sgdt, sidt. - -2001-07-13 Philip Blundell <philb@gnu.org> - - * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR. - -2001-07-12 Jeff Johnston <jjohnstn@redhat.com> - - * cgen-asm.in: Include "xregex.h" always to enable the libiberty - regex support. - (@arch@_cgen_build_insn_regex): New routine from Graydon. - (@arch@_cgen_assemble_insn): Add Graydon's code to use regex - to verify if it is worth parsing the insn as insn "x". Also update - error message when insn is not a recognized format of the insn vs - when the insn is completely unrecognized. - -2001-07-11 Frank Ch. Eigler <fche@redhat.com> - - * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of - bfd_get_bits. - * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect - non-zero CGEN_CPU_DESC->insn_chunk_bitsize. - -2001-07-09 Andreas Jaeger <aj@suse.de>, Karsten Keil <kkeil@suse.de> - - * i386-dis.c (set_op): Handle 64 bit and 32 bit mode. - (OP_J): Use bfd_vma for mask to work properly with 64 bits. - (op_address,op_riprel): Use bfd_vma to handle 64 bits. - -2001-07-05 Ben Elliston <bje@redhat.com> - - * Makefile.am (CPUDIR): Define. - (stamp-m32r): Update dependencies. - (stamp-fr30): Ditto. - (stamp-openrisc): Ditto. - * Makefile.in: Regenerate. - -2001-07-03 Zoltan Hidvegi <hzoli@hzoli.2y.net> - - * ppc-opc.c: Fix encoding of 'clf' instruction. - -2001-06-30 Geoffrey Keating <geoffk@redhat.com> - - * cgen-ibld.in (insert_normal): Support CGEN_IFLD_SIGN_OPT. - -2001-06-28 Geoffrey Keating <geoffk@redhat.com> - - * cgen-asm.c (cgen_parse_keyword): Allow any first character. - * cgen-opc.c (cgen_keyword_add): Ignore special first - character when building nonalpha_chars field. - -2001-06-24 Ben Elliston <bje@redhat.com> - - * m88k-dis.c: Format to conform to GNU coding standards. - -2001-06-23 Andreas Jaeger <aj@suse.de> - - * disassemble.c (disassembler_usage): Add unused attribute. - -2001-06-22 Eric Christopher <echristo@redhat.com> - - * mips-opc.c: Move prefx to start of the table. - -2001-06-22 Stacey Sheldon <ssheldon@Catena.com> - - * arc-opc.c (insert_st_syntax): Fix over-optimisation of ST - instruction. - -2001-06-22 Pauli <pauli@moreton.com.au> - - * m68k-opc.c: Add wdebug instruction. - -2001-06-15 Aldy Hernandez <aldyh@redhat.com> - - * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc. - -2001-06-14 Geoffrey Keating <geoffk@redhat.com> - - * cgen-asm.c (cgen_parse_keyword): When looking for the - boundaries of a keyword, allow any special characters - that are actually in one of the allowed keyword. - * cgen-opc.c (cgen_keyword_add): Add any special characters - to the nonalpha_chars field. - -2001-06-12 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-opc.c: Add lgh instruction. - * s390-opc.txt: Likewise. - -2001-06-11 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c: Group function prototypes in one place. - (FLOATCODE): Redefine as 1. - (USE_GROUPS): Redefine as 2. - (USE_PREFIX_USER_TABLE): Redefine as 3. - (X86_64_SPECIAL): Define as 4. - (GRP1b..GRPAMD): Move USE_GROUPS to bytecode1, index to bytecode2. - (PREGRP0..PREGRP26): Similarly with USE_PREFIX_USER_TABLE. - (dis386_att, dis386_intel, disx86_64_att, disx86_64_intel): Delete. - (dis386): New table combining above four tables. - (dis386_twobyte_att, dis386_twobyte_intel): Delete. - (dis386_twobyte): New table combining above two tables. - (x86_64_table): New table to handle x86_64. - (X86_64_0): Define. - (float_mem_att, float_mem_intel): Delet. - (float_mem): New table combining above two tables. - (print_insn_i386): Modify for above. - (dofloat): Likewise. - (putop): Handle '{', '|' and '}' to select alternative mnemonics. - Return 0 on success, 1 if no valid alternative. - (putop <case 'F'>, <case 'H'>): Print nothing for intel_syntax. - (putop <case 'T'>): Move to case 'U', and share case 'Q' code. - (putop <case 'I'>): Move to case 'T', and share case 'P' code. - (OP_REG <case rAX_reg .. rDI_reg>): Handle as for eAX_reg .. eDI_reg - if not 64-bit mode. - (OP_I <case q_mode>): Handle as for v_mode if not 64-bit mode. - (OP_I64): If not 64-bit mode, call OP_I. - OP_OFF64): If not 64-bit mode, call OP_OFF. - (OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename - 'ignore'/'ignored' to 'bytemode'. - -2001-06-10 Alan Modra <amodra@bigpond.net.au> - - * configure.in: Sort 'ta' case statement. - * configure: Regenerate. - - * i386-dis.c (dis386_att): Add 'H' to conditional branch and - loop,jcxz insns. - (disx86_64_att): Likewise. - (dis386_twobyte_att): Likewise. - (print_insn_i386): Don't print branch hints as a prefix. - (putop): 'H' macro prints branch hints. - (get64): Kill compile warnings. - -2001-06-09 Alexandre Oliva <aoliva@redhat.com> - - * sh-opc.h (sh_table): Don't use empty initializers. - -2001-06-06 Christian Groessler <cpg@aladdin.de> - - * z8k-dis.c: Fix formatting. - (unpack_instr): Remove unused cases in switch statement. Add - safety abort() in default case. - (unparse_instr): Add safety abort() in default case. - -2001-06-06 Peter Jakubek <pjak@snafu.de> - - * m68k-dis.c (print_insn_m68k): Fix typo. - * m68k-opc.c (m68k_opcodes): Correct allowed operands for - mcf (ColdFire) div, rem and moveb instructions. - -2001-06-06 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define. - (cond_jump_mode, loop_jcxz_mode): Define. - (dis386_att): Add cond_jump_flag and loop_jcxz_flag as - appropriate, and 'F' suffix to loop insns. - (disx86_64_att): Likewise. - (dis386_twobyte_att): Likewise. - (print_insn_i386): Don't output addr prefix for loop, jcxz insns. - Output data size prefix for long conditional jumps. Output cs and - ds branch hints. - (putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'. - (OP_J): Don't make PREFIX_DATA used. - -2001-06-04 Alexandre Oliva <aoliva@redhat.com> - - * sh-opc.h (sh_table): Complete last element entry to avoid - compiler warning. - -2001-05-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (mips_isa_type): Add MIPS r12k support. - -2001-05-23 Alan Modra <amodra@one.net.au> - - * arc-opc.c: Whitespace changes. - -2001-05-18 Hans-Peter Nilsson <hp@axis.com> - - * cris-opc.c (cris_spec_regs): Add missing initializer field for - last element. - -2001-05-15 Frank Ch. Eigler <fche@redhat.com> - - * cgen-dis.in (extract_normal): Complete support for min<base case. - -2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (INSNLEN): Rename MAXLEN. - (std_reg_names): Replace by mips32_reg_names and mips64_reg_names. - (print_insn_arg): Remove $ prefix of register names. - (set_mips_isa_type): Remove. - (mips_isa_type): New function. - (get_mips_isa): New Function. - (print_insn_mips): Rename _print_insn_mips. - (_print_insn_mips): New function, contains code which was - duplicated in print_insn_big_mips and print_insn_little_mips. - (print_insn_big_mips): Moved code to _print_insn_mips. - (print_insn_little_mips): Likewise. - (print_mips16_insn_arg): Remove $ prefix of register names. - Print error message before abort. - -2001-05-14 J.T. Conklin <jtc@redback.com> - - * ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of - simplified mnemonics used for setting PPC750-specific special - purpose registers. - -2001-05-12 H.J. Lu <hjl@gnu.org> - - * i386-dis.c (print_insn_i386): Always set `mod', `reg' and - `rm'. - -2001-05-12 Peter Targett <peter.targett@arccores.com> - - * arc-opc.c (arc_reg_names): Correct attribute for lp_count - register to r/w. Formatting fixes throughout file. - -2001-05-12 Alan Modra <amodra@one.net.au> - - * i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and - movq operands. - (twobyte_has_modrm): Update table. - (need_modrm): Give it file scope. - (MODRM_CHECK): Define. - (dofloat): Use MODRM_CHECK. - (OP_E): Likewise. - (OP_EM): Likewise. - (OP_EX): Likewise. - -2001-05-07 Frank Ch. Eigler <fche@redhat.com> - - * cgen-dis.in (default_print_insn): Tolerate min<base instructions - even at end of a section. - * cgen-ibld.in (extract_normal): Tolerate min!=base!=max instructions - by ignoring precariously-unpacked insn_value in favor of raw buffer. - -2001-05-03 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * disassemble.c (disassembler_usage): Remove unused attribute. - -2001-05-04 Frank Ch. Eigler <fche@redhat.com> - - * m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes. - -2001-05-04 Frank Ch. Eigler <fche@redhat.com> - - * cgen-dis.in (print_insn): Remove call to read_insn. Instead, - assume incoming buffer already has the base insn loaded. Handle - smaller-than-base instructions for variable-length case. - -2001-05-04 Alan Modra <amodra@one.net.au> - - * i386-dis.c (Ev, Ed): Remove duplicate define. - (Gd): Define. - (XS): Define. - (OP_XS): New function. - (dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and - movmskp operands. - (dis386_twobyte_intel): Likewise. - (prefix_user_table): Use MS for maskmovq operand. - -2001-04-27 Johan Rydberg <jrydberg@opencores.org> - - * Makefile.am: Add OpenRISC target. - * Makefile.in: Regenerated. - - * disassemble.c (disassembler): Recognize the OpenRISC disassembly. - - * configure.in (bfd_openrisc_arch): Add target. - * configure: Regenerated. - - * openrisc-asm.c: New file. - * openrisc-desc.c: Likewise. - * openrisc-desc.h: Likewise. - * openrisc-dis.c: Likewise. - * openrisc-ibld.c: Likewise. - * openrisc-opc.c: Likewise. - * openrisc-opc.h: Likewise. - -2001-04-24 Christian Groessler <cpg@aladdin.de> - - * z8k-dis.c: add names of control registers (ctrl_names); - (seg_length): provides instruction length fixup for segmented - mode; (unpack_instr): correctly handle ARG_DISP16, ARG_DISP12, - CLASS_0DISP7, CLASS_1DISP7, CLASS_DISP8 and CLASS_PR cases; - (unparse_intr): handle CLASS_PR, print addresses without '#' - * z8k-opc.h: re-created with new z8kgen - * z8kgen.c: merged in fixes which were in existing z8k-opc.h; new - entries for ldctl/ldctlb instruction - -2001-04-06 Andreas Jaeger <aj@suse.de> - - * i386-dis.c: Add ffreep instruction. - -2001-03-30 Alexandre Oliva <aoliva@redhat.com> - - * ppc-opc.c (insert_mbe): Shift mask initializer as long. - -2001-03-24 Alan Modra <alan@linuxcare.com.au> - - * i386-dis.c (PREGRP25): Define. - (dis386_twobyte_att): Use here in place of "movntq" entry. - (dis386_twobyte_intel): Likewise. - (prefix_user_table): Add PREGRP25 entry for "movntq" and "movntdq". - (PREGRP26): Define. - (dis386_twobyte_att): Use here. - (dis386_twobyte_intel): Likewise. - (prefix_user_table): Add PREGRP26 entry for "punpcklqdq". - (prefix_user_table <maskmovdqu>): XM operand, not MX. - (prefix_user_table): Cosmetic changes to "bad" entries. - -2001-03-23 Nick Clifton <nickc@redhat.com> - - * mips-opc.c: Remove extraneous whitespace. - * mips-dis.c: Remove extraneous whitespace. - -2001-03-22 Ben Elliston <bje@redhat.com> - - * cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg - declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional. - * cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused - to allay a compiler warning. - -2001-03-22 Alan Modra <alan@linuxcare.com.au> - - * i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq. - (dis386_twobyte_intel): Likewise. - (twobyte_has_modrm): Set entry for paddq, psubq. - -2001-03-20 Patrick Macdonald <patrickm@redhat.com> - - * cgen-dis.in (print_insn_@arch@): Add support for target machine - determination via CGEN_COMPUTE_MACH. - * fr30-desc.c: Regenerate. - * fr30-dis.c: Regenerate. - * fr30-opc.h: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-dis.c: Regenerate. - * m32r-opc.h: Regenerate. - * m32r-opinst.c: Regenerate. - -2001-03-20 H.J. Lu <hjl@gnu.org> - - * configure.in: Remove the redundent AC_ARG_PROGRAM. - * configure: Rebuild. - -2001-03-19 Jim Wilson <wilson@redhat.com> - - * ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and - notestr if larger than xsect. - (in_class): Handle format M5. - * ia64-asmtab.c: Regnerate. - -2001-03-19 John David Anglin <dave@hiauly1.hia.nrc.ca> - - * vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer - has more than one byte left to read. - -2001-03-16 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-opc.c: Add new opcodes. Smooth out formatting. - * s390-opc.txt: Add new opcodes. - -2001-03-06 Nick Clifton <nickc@redhat.com> - - * arm-dis.c (print_insn_thumb): Compute destination address - of BLX(1) instruction by taking bit 1 from PC and not from bit - 0 of the offset. - -2001-03-06 Igor Shevlyakov <igor@windriver.com> - - * m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs - so command line switches will work. - -2001-03-05 Dave Brolley <brolley@redhat.com> - - * fr30-asm.c: Regenerate. - * fr30-desc.c: Regenerate. - * fr30-desc.h: Regenerate. - * fr30-dis.c: Regenerate. - * fr30-ibld.c: Regenerate. - * fr30-opc.c: Regenerate. - * fr30-opc.h: Regenerate. - * m32r-asm.c: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-desc.h: Regenerate. - * m32r-dis.c: Regenerate. - * m32r-ibld.c: Regenerate. - * m32r-opc.c: Regenerate. - * m32r-opc.h: Regenerate. - * m32r-opinst.c: Regenerate. - -2001-02-28 Igor Shevlyakov <igor@windriver.com> - - * m68k-opc.c: fix cpushl according to Motorola. Enable - bunch of instructions for Coldfire 5407 and add all new. - -2001-02-27 Alan Modra <alan@linuxcare.com.au> - - * configure.in (BFD_VERSION): Do without grep. - * configure: Regenerate. - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - -2001-02-23 David Mosberger <davidm@hpl.hp.com> - - * ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4". - * ia64-asmtab.c: Regenerate. - -2001-02-21 David Mosberger <davidm@hpl.hp.com> - - * ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two - separate variants: one for IMM22 and the other for IMM14. - * ia64-asmtab.c: Regenerate. - -2001-02-21 Greg McGary <greg@mcgary.org> - - * cgen-opc.c (cgen_get_insn_value): Add missing `return'. - -2001-02-20 H.J. Lu <hjl@gnu.org> - - * Makefile.am (ia64-ic.tbl): Remove the target. - (ia64-raw.tbl): Likewise. - (ia64-waw.tbl): Likewise. - (ia64-war.tbl): Likewise. - (ia64-asmtab.c): Generate it in the source directory. - * Makefile.in: Regenerated. - -2001-02-18 lars brinkhoff <lars@nocrew.org> - - * Makefile.am: Add PDP-11 target. - * configure.in: Likewise. - * disassemble.c: Likewise. - * pdp11-dis.c: New file. - * pdp11-opc.c: New file. - -2001-02-14 Jim Wilson <wilson@redhat.com> - - * ia64-ic.tbl: Update from Intel. Add setf to fr-writers. - * ia64-asmtab.c: Regenerate. - -2001-02-12 Jan Hubicka <jh@suse.cz> - - * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison - instructions. - (putop): Handle 'Y' - -2001-02-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * mips-dis.c (print_insn_arg): Use top four bits of the address of - the following instruction not of the jump itself for the jump - target. - (print_mips16_insn_arg): Likewise. - -2001-02-11 Michael Sokolov <msokolov@ivan.Harhan.ORG> - - * Makefile.am (stamp-lib): ranlib the libopcodes.a in the build - directory. - * Makefile.in: Regenerate. - -2001-02-09 Schwidefsky <schwidefsky@de.ibm.com> - - * Makefile.am: Add linux target for S/390. - * Makefile.in: Likewise. - * configure.in: Likewise. - * disassemble.c: Likewise. - * s390-dis.c: New file. - * s390-mkopc.c: New file. - * s390-opc.c: New file. - * s390-opc.txt: New file. - -2001-02-05 Jim Wilson <wilson@redhat.com> - - * ia64-asmtab.c: Revert 2000-12-16 change. - -2001-02-02 Patrick Macdonald <patrickm@redhat.com> - - * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS. - * m32r-desc.h: Regenerate. - -2001-02-01 Jan Hubicka <jh@suse.cz> - - * i386-dis.c (dis386_att, grps): Use 'T' for push/pop - (putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax - -2001-01-14 Alan Modra <alan@linuxcare.com.au> - - * hppa-dis.c (print_insn_hppa): Handle '>' and '<' arg types. - -2001-01-13 Nick Clifton <nickc@redhat.com> - - * disassemble.c: Remove spurious white space. - -2001-01-13 Jan Hubicka <jh@suse.cz> - - * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret - templates. - -2001-01-11 Peter Targett <peter.targett@arccores.com> - - * configure.in: Add arc-ext.lo for bfd_arc_arch selection. - * Makefile.am (C_FILES): Add arc-ext.c. - (ALL_MACHINES) Add arc-ext.lo. - (INCLUDES) Add opcode directory to list. - New dependency entry for arc-ext.lo. - * disassemble.c (disassembler): Correct call to - arc_get_disassembler. - * arc-opc.c: New update for ARC, including full base - instructions for ARC variants. - * arc-dis.h, arc-dis.c: New update for ARC, including - extensibility functionality. - * arc-ext.h, arc-ext.c: New files for handling extensibility. - -2001-01-10 Jan Hubicka <jh@suse.cz> - - * i386-dis.c (PREGRP15 - PREGRP24): New. - (dis386_twobyt): Add SSE2 instructions. - (twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions. - (twobyte_uses_f3_prefix): ... this one. - (grps): Add SSE instructions. - (prefix_user_table): Add two new slots; add SSE2 instructions. - (print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix; - Handle the REPNZ and Data16 prefixes as well; do proper lookup - to prefix_user_table. - (OP_E): Accept mfence and lfence as well. - (OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions. - (OP_XMM): Support REX extensions. - (OP_EM): Likewise. - (OP_EX): Likewise. - -2001-01-09 Nick Clifton <nickc@redhat.com> - - * arm-dis.c (print_insn): Set pc to zero for instructions with - a reloc associated with them. - -2001-01-09 Jeff Johnston <jjohnstn@redhat.com> - - * cgen-asm.in (parse_insn_normal): Changed syn to be - CGEN_SYNTAX_CHAR_TYPE. Changed all references to *syn - as character to use CGEN_SYNTAX_CHAR macro and all comparisons - to '\0' to use 0 instead. - * cgen-dis.in (print_insn_normal): Ditto. - * cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto. - -2001-01-05 Jan Hubicka <jh@suse.cz> - - * i386-dis.c: Add x86_64 support. - (rex): New static variable. - (REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants. - (USED_REX): New macro. - (Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros. - (OP_I64, OP_OFF64, OP_IMREG): New functions. - (OP_REG, OP_OFF): Declare. - (get64, get32, get32s): New functions. - (r??_reg): New constants. - (dis386_att): Change templates of instruction implicitly promoted - to 64bit; change e?? to RMe?? for unwind RM byte instructions. - (grps): Likewise. - (dis386_intel): Likewise. - (dixx86_64_att): New table based on dis386_att. - (dixx86_64_intel): New table based on dis386_intel. - (names64, names8rex): New global variable. - (names32, names16): Add extended registers. - (prefix_user_t): Recognize rex prefixes. - (prefix_name): Print REX prefixes nicely. - (op_riprel): New global variable. - (start_pc): Set type to bfd_vma. - (print_insn_i386): Detect the 64bit mode and use proper table; - move ckprefix after initializing the buffer; output unused rex prefixes; - output information about target of RIP relative addresses. - (putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S'; - (print_operand_value): New function. - (OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for - REX prefix and new modes. - (get64, get32s): New. - (get32): Return bfd_signed_vma type. - (set_op): Initialize the op_riprel. - * disassemble.c (disassembler): Recognize the x86-64 disassembly. - -2001-01-03 Richard Sandiford <r.sandiford@redhat.com> - - cgen-dis.in (read_insn): Use bfd_get_bits() - -2001-01-02 Richard Sandiford <rsandifo@redhat.com> - - * cgen-dis.c (hash_insn_array): Use bfd_put_bits(). - (hash_insn_list): Likewise - * cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits(). - (extract_1): Use bfd_get_bits(). - (extract_normal): Apply sign extension to both extraction - methods. - * cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits() - (cgen_put_insn_value): Use bfd_put_bits() - -2000-12-28 Frank Ch. Eigler <fche@redhat.com> - - * cgen-asm.in (parse_insn_normal): Print better error message for - instructions with missing operands. - -2000-12-21 Santeri Paavolainen <santtu@ssh.com> - - * cgen-opc.c: Include alloca.h if HAVE_ALLOCA_H is defined. - -2000-12-16 Nick Clifton <nickc@redhat.com> - - * Makefile.in: Regenerate. - * aclocal.m4: Regenerate. - * config.in: Regenerate. - * configure.in: Add spacing. - * configure: Regenerate. - * ia64-asmtab.c: Regenerate. - * po/opcodes.pot: Regenerate. - -2000-12-12 Frank Ch. Eigler <fche@redhat.com> - - * cgen-asm.in (@arch@_cgen_assemble_insn): Prefer printing insert-time - error messages over later parse-time ones. - -2000-12-12 Jim Wilson <wilson@redhat.com> - - * ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode - argument. - * ia64-gen.c (insert_deplist): Cast sizeof result to int. - (print_dependency_table): Print NULL if semantics field not set. - (insert_opcode_dependencies): Mark cmp parameter as unused. - (print_main_table): Use fprintf_vma to print long long fields. - (main): Mark argv paramter as unused. Convert to old style definition. - * ia64-opc.c (ia64_find_dependency): Cast sizeof result to int. - * ia64-asmtab.c: Regnerate. - -2000-12-09 Nick Clifton <nickc@redhat.com> - - * m32r-dis.c (print_insn): Prevent re-read of instruction from - wrong address. - - * fr30-dis.c: Regenerate. - -2000-12-08 Peter Targett <peter.targett@arccores.com> - - * configure.in: Add arc-ext.lo for bfd_arc_arch selection. - * Makefile.am (C_FILES): Add arc-ext.c. - (ALL_MACHINES) Add arc-ext.lo. - (INCLUDES) Add opcode directory to list. - New dependency entry for arc-ext.lo. - * disassemble.c (disassembler): Correct call to - arc_get_disassembler. - * arc-opc.c: New update for ARC, including full base - instructions for ARC variants. - * arc-dis.h, arc-dis.c: New update for ARC, including - extensibility functionality. - * arc-ext.h, arc-ext.c: New files for handling extensibility. - -2000-12-03 Chris Demetriou cgd@sibyte.com - - * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO, - MOD_HILO, and MOD_LO macros. - - * mips-opc.c (M1, M2): Delete. - (mips_builtin_opcodes): Remove all uses of M1. - - * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2 - instructions take "G" format second operands and use the - correct flags. - There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to - match. - Delete "sel" code operands from mfc1 and mtc1. - Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants - for dm[ft]c[023]. - -2000-12-03 Ed Satterthwaite ehs@sibyte.com and - Chris Demetriou cgd@sibyte.com - - * mips-opc.c (mips_builtin_opcodes): Finish additions - for MIPS32 support, and clean up existing entries for - aesthetics, consistency with the MIPS32 ISA, and - with consistency the rest of the table. - -2000-12-01 Nick Clifton <nickc@redhat.com> - - * mips16-opc.c (mips16_opcodes): Add initialiser for membership - field. - -2000-12-01 Chris Demetriou <cgd@sibyte.com> - - mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument - specifiers. Update 'B' for new constant names, and remove - 'm'. - mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop" - near the top of the array, so they are disassembled properly. - Enable "ssnop" for MIPS32. Add "break" variant with 20 bit - code for MIPS32. Update "clo" and "clz" to use 'U' operand - specifier. Add 'H' format specifier variants for "mfc1," - "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update - MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32 - "wait" variant which uses 'J' operand specifier. - - * mips-dis.c (set_mips_isa_type): Update to use - CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case. - Replace bfd_mach_mips4K with bfd_mach_mips32_4k case. - * mips-opc.c (I32): New constant for instructions added in - MIPS32. - (P4): Delete. - (mips_builtin_opcodes) Replace all uses of P4 with I32. - - * mips-dis.c (set_mips_isa_type): Add cases for - bfd_mach_mips5 and bfd_mach_mips64. - * mips-opc.c (I64): New definitions. - - * mips-dis.c (set_mips_isa_type): Add case for - bfd_mach_mips_sb1. - -2000-11-28 Hans-Peter Nilsson <hp@bitrange.com> - - * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned. - (print_insn_ppi): Make nib1, nib2, nib3 unsigned. - Initialize variable dc to NULL. - (print_insn_shx): Remove unused label d_reg_n. - -2000-11-24 Nick Clifton <nickc@redhat.com> - - * arm-opc.h: Add new opcode formatting parameter 'B'. - (arm_opcodes): Add XScale, v5, and v5te instructions. - (thumb_opcodes): Add v5t instructions. - - * arm-dis.c (print_insn_arm): Handle new 'B' format - parameter. - (print_insn_thumb): Decode BLX(1) instruction. - -2000-11-21 Chris Demetriou <cgd@sibyte.com> - - * mips-opc.c: Fix file header comment. - -2000-11-14 Hans-Peter Nilsson <hp@axis.com> - - * cris-dis.c (cris_get_disassembler): If abfd is NULL, return - print_insn_cris_with_register_prefix. - -2000-11-11 Alexandre Oliva <aoliva@redhat.com> - - * sh-opc.h: The operand of `mov.w r0, (<disp>,GBR)' is IMM1, not 0. - -2000-11-07 Matthew Green <mrg@redhat.com> - - * cgen-dis.in (print_insn): All insns which can fit into insn_value - must be loaded there in their entirety. - -2000-10-20 Jakub Jelinek <jakub@redhat.com> - - * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs. - (compute_arch_mask): Add v8plusb and v9b machines. - (print_insn_sparc): siam mode decoding, accept ASRs up to 25. - * sparc-opc.c: Support for Cheetah instruction set. - (prefetch_table): Add #invalidate. - -2000-10-16 Nick Clifton <nickc@redhat.com> - - * mcore-dis.c (imsk): Change mask for OC to 0xFE00. - -2000-10-06 Dave Brolley <brolley@redhat.com> - - * fr30-desc.h: Regenerate. - * m32r-desc.h: Regenerate. - * m32r-ibld.c: Regenerate. - -2000-10-05 Jim Wilson <wilson@redhat.com> - - * ia64-ic.tbl: Update from Intel. - * ia64-asmtab.c: Regenerate. - -2000-10-04 Kazu Hirata <kazu@hxi.com> - - * ia64-gen.c: Convert C++-style comments to C-style comments. - * tic54x-dis.c: Likewise. - -2000-09-29 Hans-Peter Nilsson <hp@axis.com> - - Changes to add dollar prefix to registers for files where user symbols - don't have a leading underscore. Fix formatting. - * cris-dis.c (REGISTER_PREFIX_CHAR): New. - (format_reg): Add parameter with_reg_prefix. All callers changed. - (print_with_operands): Ditto. - (print_insn_cris_generic): Renamed from print_insn_cris, add - parameter with_reg_prefix. - (print_insn_cris_with_register_prefix, - print_insn_cris_without_register_prefix, cris_get_disassembler): - New. - * disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler. - -2000-09-22 Jim Wilson <wilson@redhat.com> - - * ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for - gt, ge, ngt, and nge. - * ia64-asmtab.c: Regenerate. - - * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change. - * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP. - (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62". - * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update. - * ia64-asmtab.c: Regnerate. - -2000-09-13 Anders Norlander <anorland@acc.umu.se> - - * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores. - Add mfc0 and mtc0 with sub-selection values. - Add clo and clz opcodes. - Add msub and msubu instructions for MIPS32. - Add madd/maddu aliases for mad/madu for MIPS32. - Support wait, deret, eret, movn, pref for MIPS32. - Support tlbp, tlbr, tlbwi, tlbwr. - (P4): New define. - - * mips-dis.c (print_insn_arg): Print sdbbp 'm' args. - (print_insn_arg): Handle 'H' args. - (set_mips_isa_type): Recognize 4K. - Use CPU_* defines instead of hardcoded numbers. - -2000-09-11 Catherine Moore <clm@redhat.com> - - * d30v-opc.c (d30v_operand_t): New operand type Rb2. - (d30v_format_tab): Use Rb2 for modinc and moddec. - -2000-09-07 Catherine Moore <clm@redhat.com> - - * d30v-opc.c (d30v_format_tab): Use format Ra for - modinc and moddec. - -2000-09-06 Alexandre Oliva <aoliva@redhat.com> - - * configure: Rebuilt with new libtool.m4. - -2000-09-05 Nick Clifton <nickc@redhat.com> - - * configure: Regenerate. - * po/opcodes.pot: Regenerate. - -2000-08-31 Alexandre Oliva <aoliva@redhat.com> - - * acinclude.m4: Include libtool and gettext macros from the - top level. - * aclocal.m4, configure: Rebuilt. - -2000-08-30 Kazu Hirata <kazu@hxi.com> - - * tic80-dis.c: Fix formatting. - -2000-08-29 Kazu Hirata <kazu@hxi.com> - - * w65-dis.c: Fix formatting. - -2000-08-28 Mark Hatle <mhatle@mvista.com> - - * ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics. - (powerpc_opcodes): Add table entries for PPC 405 instructions. - Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403 - instructions. Added extended mnemonic mftbl as defined in the - 405GP manual for all PPCs. - -2000-08-28 Jim Wilson <wilson@redhat.com> - - * ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode - call. Change last goto to use failed instead of done. - -2000-08-28 Dave Brolley <brolley@redhat.com> - - * cgen-ibld.in (cgen_put_insn_int_value): New function. - (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. - (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P. - (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. - * cgen-dis.in (read_insn): New static function. - (print_insn): Use read_insn to read the insn into the buffer and set - up for disassembly. - (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is - in the buffer. - * fr30-asm.c: Regenerated. - * fr30-desc.c: Regenerated. - * fr30-desc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-ibld.c: Regenerated. - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * m32r-asm.c: Regenerated. - * m32r-desc.c: Regenerated. - * m32r-desc.h: Regenerated. - * m32r-dis.c: Regenerated. - * m32r-ibld.c: Regenerated. - * m32r-opc.c: Regenerated. - -2000-08-28 Kazu Hirata <kazu@hxi.com> - - * tic30-dis.c: Fix formatting. - -2000-08-27 Kazu Hirata <kazu@hxi.com> - - * sh-dis.c: Fix formatting. - -2000-08-24 David Edelsohn <dje@watson.ibm.com> - - * ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd. - -2000-08-24 Kazu Hirata <kazu@hxi.com> - - * z8k-dis.c: Fix formatting. - -2000-08-16 Jim Wilson <wilson@redhat.com> - - * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete - break, mov-immediate, nop. - * ia64-opc-f.c: Delete fpsub instructions. - * ia64-opc-m.c: Add POSTINC to all instructions with postincrement - address operand. Rewrite using macros to avoid long lines. - * ia64-opc.h (POSTINC): Define. - * ia64-asmtab.c: Regenerate. - -2000-08-15 Jim Wilson <wilson@redhat.com> - - * ia64-ic.tbl: Add missing entries. - -2000-08-08 Jason Eckhardt <jle@redhat.com> - - * i860-dis.c (print_br_address): Change third argument from int - to long. - -2000-08-07 Richard Henderson <rth@redhat.com> - - * ia64-dis.c (print_insn_ia64): Get byte skip count correct - for MLI templates. Handle IA64_OPND_TGT64. - -2000-08-04 Ben Elliston <bje@redhat.com> - - * cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files. - * cgen.sh: Likewise. - -2000-08-02 Jim Wilson <wilson@redhat.com> - - * ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end. - -2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr-dis.c (avr_operand): Use PARAMS macro in declaration. - Change return type from void to int. Check the combination - of operands, return 1 if valid. Fix to avoid BUF overflow. - Report undefined combinations of operands in COMMENT. - Report internal errors to stderr. Output the adiw/sbiw - constant operand in both decimal and hex. - (print_insn_avr): Disassemble ldd/std with displacement of 0 - as ld/st. Check avr_operand () return value, handle invalid - combinations of operands like unknown opcodes. - -2000-07-28 Ben Elliston <bje@redhat.com> - - * Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New. - (run-cgen, stamp-m32r, stamp-fr30): New targets. - * Makefile.in: Regenerate. - * configure.in: Add --enable-cgen-maint option. - * configure: Regenerate. - -2000-07-26 Dave Brolley <brolley@redhat.com> - - * cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned. - (cgen_hw_lookup_by_num): Ditto. - (cgen_operand_lookup_by_name): Ditto. - (print_address): Ditto. - (print_keyword): Ditto. - * cgen-dis.c (hash_insn_array): Mark unused parameters with - ATTRIBUTE_UNUSED. - * cgen-asm.c (hash_insn_array): Mark unused parameters with - ATTRIBUTE_UNUSED. - (cgen_parse_keyword): Ditto. - -2000-07-22 Jason Eckhardt <jle@redhat.com> - - * i860-dis.c: New file. - (print_insn_i860): New function. - (print_br_address): New function. - (sign_extend): New function. - (BITWISE_OP): New macro. - (I860_REG_PREFIX): New macro. - (grnames, frnames, crnames): New structures. - - * disassemble.c (ARCH_i860): Define. - (disassembler): Add check for bfd_arch_i860 to set disassemble - function to print_insn_i860. - - * Makefile.in (CFILES): Added i860-dis.c. - (ALL_MACHINES): Added i860-dis.lo. - (i860-dis.lo): New dependences. - - * configure.in: New bits for bfd_i860_arch. - - * configure: Regenerated. - -2000-07-20 Hans-Peter Nilsson <hp@axis.com> - - * Makefile.am (CFILES): Add cris-dis.c and cris-opc.c. - (ALL_MACHINES): Add cris-dis.lo and cris-opc.lo. - (cris-dis.lo, cris-opc.lo): New rules. - * Makefile.in: Rebuild. - * configure.in (bfd_cris_arch): New target. - * configure: Rebuild. - * disassemble.c (ARCH_cris): Define. - (disassembler): Support ARCH_cris. - * cris-dis.c, cris-opc.c: New files. - * po/POTFILES.in, po/opcodes.pot: Regenerate. - -2000-07-11 Jakub Jelinek <jakub@redhat.com> - - * sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2. - Reported by Bill Clarke <llib@computer.org>. - -2000-07-09 Geoffrey Keating <geoffk@redhat.com> - - * ppc-opc.c (powerpc_opcodes): Correct suffix for vslw. - Patch by Randall J Fisher <rfisher@ecn.purdue.edu>. - -2000-07-09 Alan Modra <alan@linuxcare.com.au> - - * hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg, - fput_const, extract_3, extract_5_load, extract_5_store, - extract_5r_store, extract_5R_store, extract_10U_store, - extract_5Q_store, extract_11, extract_14, extract_16, extract_21, - extract_12, extract_17, extract_22): Prototype. - (print_insn_hppa): Rename inner block opcode -> opc to avoid - shadowing outer block. - (GET_BIT): Define. - -2000-07-05 DJ Delorie <dj@redhat.com> - - * MAINTAINERS: new - -2000-07-04 Alexandre Oliva <aoliva@redhat.com> - - * arm-dis.c (print_insn_arm): Output combinations of PSR flags. - -2000-07-03 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr-dis.c (avr_operand): Change _ () to _() around all strings - marked for translation (exception from the usual coding style). - (print_insn_avr): Initialize insn2 to avoid warnings. - -2000-07-03 Kazu Hirata <kazu@hxi.com> - - * h8300-dis.c (bfd_h8_disassemble): Improve readability. - * h8500-dis.c: Fix formatting. - -2000-07-01 Alan Modra <alan@linuxcare.com.au> - - * Makefile.am (DEP): Fix 2000-06-22. grep after running dep.sed - (CLEANFILES): Add DEPA. - * Makefile.in: Regenerate. - -2000-06-26 Scott Bambrough <scottb@netwinder.org> - - * arm-dis.c (regnames): Add an additional register set to match - the set used by GCC. Make it the default. - -2000-06-22 Alan Modra <alan@linuxcare.com.au> - - * Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we - find one. - * Makefile.in: Regenerate. - -2000-06-20 H.J. Lu <hjl@gnu.org> - - * Makefile.am: Rebuild dependency. - * Makefile.in: Rebuild. - -2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> - - * Makefile.in, configure: regenerate - * disassemble.c (disassembler): Recognize ARCH_m68hc12, - ARCH_m68hc11. - * m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12): - New functions. - * configure.in: Recognize m68hc12 and m68hc11. - * m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x - * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly - and opcode generation for m68hc11 and m68hc12. - -2000-06-16 Nick Duffek <nsd@redhat.com> - - * disassemble.c (disassembler): Refer to the PowerPC 620 using - bfd_mach_ppc_620 instead of 620. - -2000-06-12 Kazu Hirata <kazu@hxi.com> - - * h8300-dis.c: Fix formatting. - (bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl] - correctly. - -2000-06-09 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c (avr_operand): Bugfix for jmp/call address. - -2000-06-07 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c: completely rewritten. - -2000-06-02 Kazu Hirata <kazu@hxi.com> - - * h8300-dis.c: Follow the GNU coding style. - (bfd_h8_disassemble) Fix a typo. - -2000-06-01 Kazu Hirata <kazu@hxi.com> - - * h8300-dis.c (bfd_h8_disassemble_init): Fix a typo. - (bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl] - correctly. Fix a typo. - -2000-05-31 Nick Clifton <nickc@redhat.com> - - * opintl.h (_(String)): Explain why dgettext is used instead of - gettext. - -2000-05-30 Nick Clifton <nickc@redhat.com> - - * opintl.h (gettext, dgettext, dcgettext, textdomain, - bindtextdomain): Replace defines with those from intl/libgettext.h - to quieten gcc warnings. - -2000-05-26 Alan Modra <alan@linuxcare.com.au> - - * Makefile.am: Update dependencies with "make dep-am" - * Makefile.in: Regenerate. - -2000-05-25 Alexandre Oliva <aoliva@redhat.com> - - * m10300-dis.c (disassemble): Don't assume 32-bit longs when - sign-extending operands. - -2000-05-15 Donald Lindsay <dlindsay@redhat.com> - - * d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches - except brf's. - -2000-05-21 Nick Clifton <nickc@redhat.com> - - * Makefile.am (LIBIBERTY): Define. - -2000-05-19 Diego Novillo <dnovillo@redhat.com> - - * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES. - (STD_REGISTER_NAMES): New name for REGISTER_NAMES. - (reg_names): Rename to std_reg_names. Change it to a char ** - static variable. - (std_reg_names): New name for reg_names. - (set_mips_isa_type): Set reg_names to point to std_reg_names by - default. - -2000-05-16 Frank Ch. Eigler <fche@redhat.com> - - * fr30-desc.h: Partially regenerated to account for changed - CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros. - * m32r-desc.h: Ditto. - -2000-05-15 Nick Clifton <nickc@redhat.com> - - * arm-opc.h: Use upper case for flasg in MSR and MRS - instructions. Allow any bit to be set in the field_mask of - the MSR instruction. - - * arm-dis.c (print_insn_arm): Decode _x and _s bits of the - field_mask of an MSR instruction. - -2000-05-11 Thomas de Lellis <tdel@windriver.com> - - * arm-opc.h: Disassembly of thumb ldsb/ldsh - instructions changed to ldrsb/ldrsh. - -2000-05-11 Ulf Carlsson <ulfc@engr.sgi.com> - - * mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit - target addresses for 'jal' and 'j'. - -2000-05-10 Geoff Keating <geoffk@redhat.com> - - * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes - also available in common mode when powerpc syntax is being used. - -2000-05-08 Alan Modra <alan@linuxcare.com.au> - - * m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args. - (dummy_print_address): Ditto. - -2000-05-04 Timothy Wall <twall@redhat.com> - - * tic54x-opc.c: New. - * tic54x-dis.c: New. - * disassemble.c (disassembler): Add ARCH_tic54x. - * configure.in: Added tic54x target. - * configure: Ditto. - * Makefile.am: Add tic54x dependencies. - * Makefile.in: Ditto. - -2000-05-03 J.T. Conklin <jtc@redback.com> - - * ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for - vector unit operands. - (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector - unit instruction formats. - (PPCVEC): New macro, mask for vector instructions. - (powerpc_operands): Add table entries for above operand types. - (powerpc_opcodes): Add table entries for vector instructions. - - * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask. - (print_insn_little_powerpc): Likewise. - (print_insn_powerpc): Prepend 'v' when printing vector registers. - -2000-04-24 Clinton Popetz <cpopetz@redhat.com> - - * configure.in: Add bfd_powerpc_64_arch. - * disassemble.c (disassembler): Use print_insn_big_powerpc for - 64 bit code. - -2000-04-24 Nick Clifton <nickc@redhat.com> - - * fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow - field. - -2000-04-23 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c (reg_fmul_d): New. Extract destination register from - FMUL instruction. - (reg_fmul_r): New. Extract source register from FMUL instruction. - (reg_muls_d): New. Extract destination register from MULS instruction. - (reg_muls_r): New. Extract source register from MULS instruction. - (reg_movw_d): New. Extract destination register from MOVW instruction. - (reg_movw_r): New. Extract source register from MOVW instruction. - (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU, - EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions. - -2000-04-22 Timothy Wall <twall@redhat.com> - - * ia64-gen.c (general): Add an ordered table of primary - opcode names, as well as priority fields to disassembly data - structures to enforce a preferred disassembly format based on the - ordering of the opcode tables. - (load_insn_classes): Show a useful message if IC tables are missing. - (load_depfile): Ditto. - * ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to - distinguish preferred disassembly. - * ia64-opc-f.c: Reorder some insn for preferred disassembly - format. Fix incorrect flag on fma.s/fma.s.s0. - * ia64-opc.c: Scan *all* disassembly matches and use the one with - the highest priority. - * ia64-opc-b.c: Use more abbreviations. - * ia64-asmtab.c: Regenerate. - -2000-04-21 Jason Eckhardt <jle@redhat.com> - - * hppa-dis.c (extract_16): New function. - (print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of - new operand types l,y,&,fe,fE,fx. - -2000-04-21 Richard Henderson <rth@redhat.com> - David Mosberger <davidm@hpl.hp.com> - Timothy Wall <twall@redhat.com> - Bob Manson <manson@charmed.cygnus.com> - Jim Wilson <wilson@redhat.com> - - * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h. - (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c, - ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c, - ia64-asmtab.c. - (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo. - (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen, - ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules. - * Makefile.in: Rebuild. - * configure Rebuild. - * configure.in (bfd_ia64_arch): New target. - * disassemble.c (ARCH_ia64): Define. - (disassembler): Support ARCH_ia64. - * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl, - ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c, - ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl, - ia64-war.tbl, ia64-waw.tbl: New files. - -2000-04-20 Alexandre Oliva <aoliva@redhat.com> - - * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define. - (disassemble): Use them. - -2000-04-14 Alan Modra <alan@linuxcare.com.au> - - * sysdep.h: Include "ansidecl.h" not <ansidecl.h> - * Makefile.am: Update dependencies. - * Makefile.in: Regenerate. - -2000-04-14 Michael Sokolov <msokolov@ivan.Harhan.ORG> - - * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c, - avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c, - disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c, - i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c, - m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c, - mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c, - ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c, - tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c, - w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove - ansidecl.h as sysdep.h includes it. - -2000-04-7 Andrew Cagney <cagney@b1.redhat.com> - - * configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add - --enable-build-warnings option. - * Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions. - * Makefile.in, configure: Re-generate. - -2000-04-05 J"orn Rennecke <amylaar@redhat.com> - - * sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs. - stc GBR,@-<REG_N> is available for arch_sh1_up. - Group parallel processing insn with identical mnemonics together. - Make three-operand psha / pshl come first. - -2000-04-05 J"orn Rennecke <amylaar@redhat.co.uk> - - * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4. - Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. - (sh_arg_type): Add A_PC. - (sh_table): Update entries using immediates. Add repeat. - * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4. - Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. - -2000-04-04 Alan Modra <alan@linuxcare.com.au> - - * po/opcodes.pot: Regenerate. - - * Makefile.am (MKDEP): Use gcc -MM rather than mkdep. - (DEP): Quote when passing vars to sub-make. Add warning message - to end. - (DEP1): Rewrite for "gcc -MM". - (CLEANFILES): Add DEP2. - Update dependencies. - * Makefile.in: Regenerate. - -2000-04-03 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c: Syntax cleanup. - (add0fff): Print the pc relative address as a signed number. - (add03f8): Likewise. - -2000-04-01 Ian Lance Taylor <ian@zembu.com> - - * disassemble.c (disassembler_usage): Don't use a prototype. Mark - the parameter ATTRIBUTE_UNUSED. - * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed. - -2000-04-01 Alexandre Oliva <aoliva@redhat.com> - - * m10300-opc.c: SP-based offsets are always unsigned. - -2000-03-29 Thomas de Lellis <tdel@windriver.com> - - * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal" - [branch always] instead of "undefined". - -2000-03-27 Nick Clifton <nickc@redhat.com> - - * d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of - short instructions, from end of list of long instructions. - -2000-03-27 Ian Lance Taylor <ian@zembu.com> - - * Makefile.am (CFILES): Add avr-dis.c. - (ALL_MACHINES): Add avr-dis.lo. - -2000-03-27 Alan Modra <alan@linuxcare.com> - - * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to - truncate integers. - (print_insn_avr): Call function via pointer in K&R compatible way. - (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204, - add0fff, add03f8): Convert to old style function declaration and - add prototype. - (avrdis_opcode): Add prototype. - -2000-03-27 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c: New file. AVR disassembler. - * configure.in (bfd_avr_arch): New architecture support. - * disassemble.c: Likewise. - * configure: Regenerate. - -2000-03-06 J"oern Rennecke <amylaar@redhat.com> - - * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement. - -2000-03-02 J"orn Rennecke <amylaar@redhat.co.uk> - - * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand - flag to determine if operand is pc-relative. - * d30v-opc.c: - (d30v_format_table): - (REL6S3): Renamed from IMM6S3. - Added flag OPERAND_PCREL. - (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with - added flag OPERAND_PCREL. - (IMM12S3U): Replaced with REL12S3. - (SHORT_D2, LONG_D): Delay target is pc-relative. - (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r): - Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r, - using the REL* operands. - (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D. - (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B, - LONG_Db, using REL* operands. - (SHORT_U, SHORT_A5S): Removed stray alternatives. - (d30v_opcode_table): Use new *r formats. - -2000-02-28 Nick Clifton <nickc@redhat.com> - - * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with - 'signed_overflow_ok_p'. - -2000-02-27 Eli Zaretskii <eliz@is.elta.co.il> - - * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the - name of the libtool directory. - * Makefile.in: Rebuild. - -2000-02-24 Nick Clifton <nickc@redhat.com> - - * cgen-opc.c (cgen_set_signed_overflow_ok): New function. - (cgen_clear_signed_overflow_ok): New function. - (cgen_signed_overflow_ok_p): New function. - -2000-02-23 Andrew Haley <aph@redhat.com> - - * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, - m32r-ibld.c, m32r-opc.h: Rebuild. - -2000-02-23 Linas Vepstas <linas@linas.org> - - * i370-dis.c, i370-opc.c: New. - - * disassemble.c (ARCH_i370): Define. - (disassembler): Handle it. - - * Makefile.am: Add support for Linux/IBM 370. - * configure.in: Likewise. - - * Makefile.in: Regenerate. - * configure: Likewise. - -2000-02-22 Chandra Chavva <cchavva@redhat.com> - - * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to - ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel - procedure. - -2000-02-22 Andrew Haley <aph@redhat.com> - - * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER: - force gp32 to zero. - * mips-opc.c (G6): New define. - (mips_builtin_op): Add "move" definition for -gp32. - -2000-02-22 Ian Lance Taylor <ian@zembu.com> - - From Grant Erickson <gerickso@Brocade.COM>: - * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2. - -2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au> - - * dis-buf.c (buffer_read_memory): Change `length' param and all int - vars to unsigned. - -2000-02-17 J"orn Rennecke <amylaar@redhat.co.uk> - - * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. - (print_insn_ppi): Likewise. - (print_insn_shx): Use info->mach to select appropriate insn set. - Add support for sh-dsp. Remove FD_REG_N support. - * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. - (sh_arg_type): Likewise. Remove FD_REG_N. - (sh_dsp_reg_nums): New enum. - (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. - (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. - (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. - (arch_sh3_dsp_up): Likewise. - (sh_opcode_info): New field: arch. - (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and - D_REG_N. Fill in arch field. Add sh-dsp insns. - -2000-02-14 Fernando Nasser <fnasser@totem.to.redhat.com> - - * arm-dis.c: Change flavor name from atpcs-special to - special-atpcs to prevent name conflict in gdb. - (get_arm_regname_num_options, set_arm_regname_option, - get_arm_regnames): New functions. API to access the several - flavor of register names. Note: Used by gdb. - (print_insn_thumb): Use the register name entry from the currently - selected flavor for LR and PC. - -2000-02-10 Nick Clifton <nickc@redhat.com> - - * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR - classes. - (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and - "mulsh.h" instructions. - * mcore-dis.c (imsk array): Add masks for MULSH and OPSR - classes. - (print_insn_mcore): Add support for little endian targets. - Add support for MULSH and OPSR classes. - -2000-02-07 Nick Clifton <nickc@redhat.com> - - * arm-dis.c (parse_arm_diassembler_option): Rename again. - Previous delat did not take. - -2000-02-03 Timothy Wall <twall@redhat.com> - - * dis-buf.c (buffer_read_memory): Use octets_per_byte field - to adjust target address bounds checking and calculate the - appropriate octet offset into data. - -2000-01-27 Nick Clifton <nickc@redhat.com> - - * arm-dis.c: (parse_disassembler_option): Rename to - parse_arm_disassembler_option and allow to be exported. - - * disassemble.c (disassembler_usage): New function: Print out any - target specific disassembler options. - Call arm_disassembler_options() if the ARM architecture is being - supported. - - * arm-dis.c (NUM_ELEM): Define this macro if not already - defined. - (arm_regname): New struct type for ARM register names. - (arm_toggle_regnames): Delete. - (parse_disassembler_option): Use register name structure. - (print_insn): New function: Combines duplicate code found in - print_insn_big_arm and print_insn_little_arm. - (print_insn_big_arm): Call print_insn. - (print_insn_little_arm): Call print_insn. - (print_arm_disassembler_options): Display list of supported, - ARM specific disassembler options. - -2000-01-27 Thomas de Lellis <tdel@windriver.com> - - * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the - ARM_STT_16BIT flag as Thumb code symbols. - - * arm-dis.c (printf_insn_little_arm): Ditto. - -2000-01-25 Thomas de Lellis <tdel@windriver.com> - - * arm-dis.c (printf_insn_thumb): Prevent double dumping - of raw thumb instructions. - -2000-01-20 Nick Clifton <nickc@redhat.com> - - * mcore-opc.h (mcore_table): Add "add" as an alias for "addu". - -2000-01-03 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (streq): New macro. - (strneq): New macro. - (force_thumb): ew local variable. - (parse_disassembler_option): New function: Parse a single, ARM - specific disassembler command line switch. - (parse_disassembler_option): Call parse_disassembler_option to - parse individual command line switches. - (print_insn_big_arm): Check force_thumb. - (print_insn_little_arm): Check force_thumb. - -For older changes see ChangeLog-9899 - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/contrib/binutils/opcodes/ChangeLog-0203 b/contrib/binutils/opcodes/ChangeLog-0203 deleted file mode 100644 index 25ed8b5..0000000 --- a/contrib/binutils/opcodes/ChangeLog-0203 +++ /dev/null @@ -1,2110 +0,0 @@ -2003-12-15 Christian Groessler <chris@groessler.org> - - * z8k-dis.c (intr_names): Removed. - (print_intr, print_flags): New functions. - (unparse_instr): Use new functions. - -2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> - - * m32r-opc.c: Regenerate. - -2003-12-14 Mark Mitchell <mark@codesourcery.com> - - * arm-opc.h (arm_opcodes): Put V6 instructions before XScale - instructions. - -2003-12-13 Hans-Peter Nilsson <hp@bitrange.com> - - * mmix-opc.c (mmix_opcodes): Use GO_INSN_BYTE, PUSHGO_INSN_BYTE, - SETL_INSN_BYTE, INCH_INSN_BYTE, INCMH_INSN_BYTE, INCML_INSN_BYTE - and SWYM_INSN_BYTE instead of raw numbers. - -2003-12-10 Zack Weinberg <zack@codesourcery.com> - - * ppc-opc.c (MO): Make optional. - (RAO, RSO, SHO): New optional forms of RA, RS, SH operands. - (tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional. - -2003-12-05 Ricardo Anguiano <anguiano@codesourcery.com> - Mark Mitchell <mark@codesourcery.com> - Richard Earnshaw <rearnsha@arm.com> - - * arm-dis.c (print_arm_insn): Add 'W' macro. - * arm-opc.h (arm_opcodes): Add V6 instructions. - (thumb_opcodes): Likewise. - -2003-12-04 Alan Modra <amodra@bigpond.net.au> - - * openrisc-asm.c: Regenerate. - * pj-opc.c: Update copyright date. - -2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> - - * m32r-asm.c: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-desc.h: Regenerate. - * m32r-dis.c: Regenerate. - * m32r-ibld.c: Regenerate. - * m32r-opc.c: Regenerate. - * m32r-opc.h: Regenerate. - * m32r-opinst.c: Regenerate. - -2003-12-02 Alexandre Oliva <aoliva@redhat.com> - - * sh-opc.h: Add support for sh4a and no-fpu variants. - * sh-dis.c: Ditto. - -2003-12-02 Kazu Hirata <kazu@cs.umass.edu> - - * alpha-opc.c: Remove ARGSUSED. - * i370-opc.c: Likewise. - * ppc-opc.c: Likewise. - -2003-12-02 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - -2003-11-28 Christian Groessler <chris@groessler.org> - - * z8k-dis.c: Convert to ISO C90. - * z8kgen.c: Convert to ISO C90. - (opt): Move long opcode for "ldb rdb,imm8" after short one, now - the short one is created when assembling. - * z8k-opc.h: Regenerate with new z8kgen.c. - -2003-11-19 Kazu Hirata <kazu@cs.umass.edu> - - * h8300-dis.c (print_colon_thingie): Remove. - -2003-11-18 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * mips-opc.c (mips_builtin_opcodes): Handle new macros: "lca" and - "dlca". - -2003-11-14 Nick Clifton <nickc@redhat.com> - - * dis-init.c (init_disassemble_info): Initialise - symbol_is_valid field. - * dis-buf.c (generic_symbol_is_valid): New function. Always - returns TRUE. - * arm-dis.c (arm_symbol_is_valid): New function. Return FALSE - for ARM ELF mapping symbols. - * disassemble.c (disassemble_init_for_target): Set - symbol_is_valid field to arm_symbol_is_valid of the target is - an ARM. - -2003-11-05 H.J. Lu <hongjiu.lu@intel.com> - - * m68k-opc.c (m68k_opcodes): Reorder "fmovel". - -2003-11-03 Daniel Jacobowitz <drow@mvista.com> - - * arm-dis.c (print_arm_insn): Print "-" after "#". - -2003-10-30 Falk Hueffner <falk.hueffner@student.uni-tuebingen.de> - - * alpha-opc.c: Add support for a second argument to RPCC. - -2003-10-27 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11-dis.c: Convert to ISO C90 prototypes. - -2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com> - Bernardo Innocenti <bernie@develer.com> - - * m68k-dis.c: Add MCFv4/MCF5528x support. - * m68k-opc.c: Likewise. - -2003-10-10 Dave Brolley <brolley@redhat.com> - - * frv-asm.c,frv-desc.c,frv-opc.c: Regenerated. - -2003-10-08 Dave Brolley <brolley@redhat.com> - - * frv-desc.[ch], frv-opc.[ch]: Regenerated. - -2003-09-30 Bob Wilson <bob.wilson@acm.org> - - * xtensa-dis.c (fetch_data): Remove numBytes parameter. - (print_insn_xtensa): Fix call to fetch_data. - -2003-09-30 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" - (print_insn_args): Add handing for +E, +F, +G, and +H. - * mips-opc.c (I65): New define for MIPS64r2. - (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", - "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", - and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to - be supported on MIPS64r2. - -2003-09-24 Dave Brolley <brolley@redhat.com> - - * frv-desc.c, frv-opc.c, frv-opc.h: Regenerated. - -2003-09-14 Andreas Jaeger <aj@suse.de> - - * i386-dis.c: Convert to ISO C90 prototypes. - * i370-dis.c: Likewise. - * i370-opc.c: Likewiwse. - * i960-dis.c: Likewise. - * ia64-opc.c: Likewise. - -2003-09-09 Dave Brolley <brolley@redhat.com> - - * frv-desc.c: Regenerated. - -2003-09-08 Dave Brolley <brolley@redhat.com> - - On behalf of Doug Evans <dje@sebabeach.org> - * Makefile.am (run-cgen): Pass new args archfile and opcfile - to cgen.sh. - (stamp-ip2k,stamp-m32r,stamp-fr30,stamp-frv,stamp-openrisc, - stamp-iq2000,stamp-xstormy16): Pass paths of .cpu and .opc files - to cgen.sh. - (stamp-frv): Delete hardcoded path spec workaround. - * Makefile.in: Regenerate. - * cgen.sh: New args archfile and opcfile. Pass on to cgen. - -2003-09-04 Nick Clifton <nickc@redhat.com> - - * v850-dis.c (disassemble): Accept bfd_mach_v850e1. - * v850-opc.c (v850_opcodes): Add DBTRAP and DBRET instructions. - -2003-09-04 Alan Modra <amodra@bigpond.net.au> - - * ppc-dis.c (struct dis_private): New. - (powerpc_dialect): Make static. Accept -Many in addition to existing - options. Save dialect in dis_private. - (print_insn_big_powerpc): Retrieve dialect from dis_private. - (print_insn_little_powerpc): Likewise. - (print_insn_powerpc): Call powpc_dialect here. Remove unnecessary - efs/altivec check. Try harder to disassemble if given -Many. - * ppc-opc.c (insert_fxm): Expand comment. - (PPC, PPCCOM, PPC32, PPC64, PPCVEC): Remove PPC_OPCODE_ANY. - (POWER, POWER2, PPCPWR2, POWER32, COM, COM32, M601, PWRCOM): Likewise. - (POWER4): Remove PPCCOM. - (PPCONLY): Don't define. Update all occurrences to PPC. - -2003-09-03 Andrew Cagney <cagney@redhat.com> - - * dis-init.c (init_disassemble_info): New file and function. - * Makefile.am (CFILES): Add "dis-init.c". - (libopcodes_la_SOURCES): Add "dis-init.c". - (dis-init.lo): Specify dependencies. - * Makefile.in: Regenerate. - -2003-09-03 Dave Brolley <brolley@redhat.com> - - * frv-*: Regenerated. - -2003-09-02 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c (powerpc_opcodes): Combine identical PPC403/BOOKE entries. - Move duplicate mnemonic entries together. Use RS instead of RT on - all mt*. - * ppc-dis.c: Convert to ISO C. - -2003-08-29 Dave Brolley <brolley@redhat.com> - - * Makefile.am (stamp-frv): Copy frv.cpu and frv.opc from - $(srcdir)/../cpu temporarily when regenerating source files. - * Makefile.in: Regenerated. - -2003-08-19 Nick Clifton <nickc@redhat.com> - - * arm-dis.c (print_insn_arm: case 'A'): Add code to - disassemble unindexed form of Addressing Mode 5. - -2003-08-19 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c (PPC440): Define. - (powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci, - icread instructions when PPC440. Add dlmzb instruction. - -2003-08-14 Alan Modra <amodra@bigpond.net.au> - - * dep-in.sed: Remove libintl.h. - * Makefile.am (POTFILES.in): Unset LC_COLLATE. - Run "make dep-am". - * Makefile.in: Regenerate. - -2003-08-07 Michael Meissner <gnu@the-meissners.org> - - * cgen-asm.c (hash_insn_array): Remove PARAMS macro. - (hash_insn_list): Ditto. - (build_asm_hash_table): Ditto. - (cgen_set_parse_operand_fn): Prototype definition. - (cgen_init_parse_operand): Ditto. - (hash_insn_array): Ditto. - (hash_insn_list): Ditto. - (build_asm_hash_table): Ditto. - (cgen_asm_lookup_insn): Ditto. - (cgen_parse_keyword): Ditto. - (cgen_parse_signed_integer): Ditto. - (cgen_parse_unsigned_integer): Ditto. - (cgen_parse_address): Ditto. - (cgen_validate_signed_integer): Ditto. - (cgen_validate_unsigned_integer): Ditto. - - * cgen-opc.c (hash_keyword_name): Remove PARAMS macro. - (hash_keyword_value): Ditto. - (build_keyword_hash_tables): Ditto. - (cgen_keyword_lookup_name): Prototype definition. - (cgen_keyword_lookup_value): Ditto. - (cgen_keyword_add): Ditto. - (cgen_keyword_search_init): Ditto. - (cgen_keyword_search_next): Ditto. - (hash_keyword_name): Ditto. - (hash_keyword_value): Ditto. - (build_keyword_hash_tables): Ditto. - (cgen_hw_lookup_by_name): Ditto. - (cgen_hw_lookup_by_num): Ditto. - (cgen_operand_lookup_by_name): Ditto. - (cgen_operand_lookup_by_num): Ditto. - (cgen_insn_count): Ditto. - (cgen_macro_insn_count): Ditto. - (cgen_get_insn_value): Ditto. - (cgen_put_insn_value): Ditto. - (cgen_lookup_insn): Ditto. - (cgen_get_insn_operands): Ditto. - (cgen_lookup_get_insn_operands): Ditto. - (cgen_set_signed_overflow_ok): Ditto. - (cgen_clear_signed_overflow_ok): Ditto. - (cgen_signed_overflow_ok_p): Ditto. - - * cgen-dis.c (hash_insn_array): Remove PARAMS macro. - (hash_insn_list): Ditto. - (build_dis_hash_table): Ditto. - (count_decodable_bits): Ditto. - (add_insn_to_hash_chain): Ditto. - (count_decodable_bits): Prototype definition. - (add_insn_to_hash_chain): Ditto. - (hash_insn_array): Ditto. - (hash_insn_list): Ditto. - (build_dis_hash_table): Ditto. - (cgen_dis_lookup_insn): Ditto. - - * cgen-asm.in (parse_insn_normal): Remove PARAMS macro. - (@arch@_cgen_build_insn_regex): Prototype definition. - (parse_insn_normal): Ditto. - (@arch@_cgen_assemble_insn): Ditto. - (@arch@_cgen_asm_hash_keywords): Ditto. - - * cgen-dis.in (print_normal): Remove PARAMS macro. Use void * - instead of PTR. - (print_address): Ditto. - (print_keyword): Ditto. - (print_insn_normal): Ditto. - (print_insn): Ditto. - (default_print_insn): Ditto. - (read_insn): Ditto. - (print_normal): Prototype definition. Use void * instead of PTR. - (print_address): Ditto. - (print_keyword): Ditto. - (print_insn_normal): Ditto. - (read_insn): Ditto. - (print_insn): Ditto. - (default_print_insn): Ditto. - (print_insn_@arch@): Ditto. - - * cgen-ibld.in (insert_normal): Remove PARAMS macro. - (insn_insn_normal): Ditto. - (extract_normal): Ditto. - (extract_insn_normal): Ditto. - (put_insn_int_value): Ditto. - (insert_1): Ditto. - (fill_cache): Ditto. - (extract_1): Ditto. - (insert_1): Prototype definition. - (insert_normal): Ditto. - (insert_insn_normal): Ditto. - (put_insn_int_value): Ditto. - (fill_cache): Ditto. - (extract_1): Ditto. - (extract_normal): Ditto. - (extract_insn_normal): Ditto. - - * fr30-asm.c: Regenerate. - * fr30-dis.c: Ditto. - * fr30-ibld.c: Ditto. - * frv-asm.c: Ditto. - * frv-dis.c: Ditto. - * frv-ibld.c: Ditto. - * ip2k-asm.c: Ditto. - * ip2k-dis.c: Ditto. - * ip2k-ibld.c: Ditto. - * iq2000-asm.c: Ditto. - * iq2000-dis.c: Ditto. - * iq2000-ibld.c: Ditto. - * m32r-asm.c: Ditto. - * m32r-dis.c: Ditto. - * m32r-ibld.c: Ditto. - * openrisc-asm.c: Ditto. - * openrisc-dis.c: Ditto. - * openrisc-ibld.c: Ditto. - * xstormy16-asm.c: Ditto. - * xstormy16-dis.c: Ditto. - * xstormy16-ibld.c: Ditto. - -2003-08-06 Nick Clifton <nickc@redhat.com> - - * po/fr.po: Updated French translation. - -2003-08-05 Nick Clifton <nickc@redhat.com> - - * configure.in (ALL_LINGUAS): Add nl. - * configure: Regenerate. - * po/nl.po: New Dutch translation. - -2003-07-30 Jason Eckhardt <jle@rice.edu> - - * i860-dis.c: Convert to ISO C90. Remove superflous prototypes. - -2003-07-30 Nick Clifton <nickc@redhat.com> - - * po/ro.po: Updated Romanian translation. - -2003-07-29 Jakub Jelinek <jakub@redhat.com> - - * ppc-opc.c (insert_mbe, extract_mbe): Shift 1L instead of 1 up. - -2003-07-24 Nick Clifton <nickc@redhat.com> - - * po/fr.po: Updated French translation. - -2003-07-18 Nick Clifton <nickc@redhat.com> - - * arm-dis.c (parse_arm_disassembler_option): Do not expect - option string to be NUL terminated. - (parse_disassembler_options): Allow options to be space or - comma separated. - -2003-07-17 Nick Clifton <nickc@redhat.com> - - * po/es.po: New Spanish translation. - * po/sv.po: New Swedish translation. - * po/opcodes.pot: Regenerate. - -2003-07-15 Richard Sandiford <rsandifo@redhat.com> - - * mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries. - -2003-07-14 Nick Clifton <nickc@redhat.com> - - * po/tr.po: Update with latest version. - * po/POTFILES.in: Regenerate. - * Makefile.in: Regenerate. - -2003-07-11 Alan Modra <amodra@bigpond.net.au> - - * po/opcodes.pot: Regenerate. - -2003-07-09 Alexandre Oliva <aoliva@redhat.com> - - 2000-05-25 Alexandre Oliva <aoliva@cygnus.com> - * m10300-dis.c (disassemble): Negate negative accumulator's shift. - 2000-05-24 Alexandre Oliva <aoliva@cygnus.com> - * m10300-dis.c (disassemble, case FSREG, FDREG): Don't assume - 32-bit longs when sign-extending operands. - 2000-04-20 Alexandre Oliva <aoliva@cygnus.com> - * m10300-opc.c: Remove MN10300_OPERAND_RELAX from all FSREGs. - * m10300-dis.c (HAVE_AM33_2): Define. - (disassemble): Use it. - (HAVE_AM33): Redefine. - (print_insn_mn10300): Fix mask for 5-byte extended insns. - 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> - * m10300-opc.c: Renamed AM332 to AM33_2. - 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> - * m10300-opc.c: Defined AM33 2.0 register operands. Added support - for AM33 2.0 `imm8,(abs16)' addressing mode for btst, bset and - bclr. Implemented `fbCC', `flCC', `dcpf' and all FP insns. - * m10300-dis.c (print_insn_mn10300): Recognize 5byte extended - insn code of AM33 2.0. - (disassemble): Recognize FMT_D3. Print out FP register names. - -2003-07-09 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (set_default_mips_dis_options): Get BFD from - the disassembler_info's section, rather than from the - disassembler_info's symbols pointer. - -2003-07-07 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c: Remove NULL pointer checks. Formatting. Remove - extraneous ATTRIBUTE_UNUSED. - * ppc-dis.c (print_insn_powerpc): Always pass a valid address to - operand->extract. - -2003-07-04 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c: Convert to C90, removing unnecessary prototypes and - casts. Formatting. - - * ppc-opc.c: Remove PARAMS from prototypes. - (FXM4): Define. - (insert_fxm): New function, used by both FXM and FXM4. - (extract_fxm): Likewise. - (XFXFXM_MASK): Remove 1 << 20 term. - (powerpc_opcodes): Add Power4 version of "mfcr". Simplify "mtcr" mask. - -2003-07-01 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-dis.c (s390_extract_operand): Add support for long displacements. - * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z990. - * s390-opc.c (D20_20): Add define for 20 bit displacements. - (INSTR_RRF_R0RR, INSTR_RSL_R0RD, INSTR_RSY_RRRD, INSTR_RSY_RURD, - INSTR_RSY_AARD, INSTR_RXY_RRRD, INSTR_RXY_FRRD, INSTR_SIY_URD): Add - new instruction formats. - (MASK_RRF_R0RR, MASK_RSL_R0RD, MASK_RSY_RRRD, MASK_RSY_RURD, - MASK_RSY_AARD, MASK_RXY_RRRD, MASK_RXY_FRRD, MASK_SIY_URD): Likewise. - (s390_opformats): Likewise. - * s390-opc.txt: Add new instructions for cpu type z990. Add missing - hfp instructions. Add missing instructions pgin, pgout and xsch. - -2003-06-23 H.J. Lu <hongjiu.lu@intel.com> - - * i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in - Intel Precott New Instructions. - (PREGRP27): New. Added for "addsubpd" and "addsubps". - (PREGRP28): New. Added for "haddpd" and "haddps". - (PREGRP29): New. Added for "hsubpd" and "hsubps". - (PREGRP30): New. Added for "movsldup" and "movddup". - (PREGRP31): New. Added for "movshdup" and "movhpd". - (PREGRP32): New. Added for "lddqu". - (dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry. - Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for - entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for - entry 0xd0. Use PREGRP32 for entry 0xf0. - (twobyte_has_modrm): Updated. - (twobyte_uses_SSE_prefix): Likewise. - (grps): Use PNI_Fixup in the "sidtQ" entry. - (prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30, - PREGRP31 and PREGRP32. - (float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb. - Use "fisttpll" in entry 1 in opcode 0xdd. - Use "fisttp" in entry 1 in opcode 0xdf. - -2003-06-19 Christian Groessler <chris@groessler.org> - - * z8k-dis.c (instr_data_s): Change tabl_index from long to int. - (print_insn_z8k): Correctly check return value from - z8k_lookup_instr call. - (unparse_instr): Handle CLASS_IRO case. - * z8kgen.c: Fix function definitions. Fix formatting. - (opt): Add brk opcode alias for non-simulator breakpoint. Add - missing and fix existing in/out and sin/sout opcode definitions. - (args): "@ri", "@ro" - add CLASS_IRO register usage for in/out - opcodes. - (internal): Check p->flags for non-zero before dereferencing it. - (gas): Add CLASS_IRO line. Insert new OPC_xxx lines for the added - opcodes and renumber the remaining lines repectively. - (main): Remove "-d" command line switch. - * z8k-opc.h: Regenerate with new z8kgen.c. - -2003-06-11 H.J. Lu <hongjiu.lu@intel.com> - - * po/Make-in (DESTDIR): New. - (install-data-yes): Support $(DESTDIR). - (uninstall): Likewise. - -2003-06-11 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - -2003-06-10 Doug Evans <dje@sebabeach.org> - - * cgen-asm.in (@arch@_cgen_assemble_insn): CGEN_INSN_RELAX renamed to - CGEN_INSN_RELAXED. - * fr30-asm.c,fr30-desc.c,fr30-desc.h: Regenerate. - * frv-asm.c,frv-desc.c,frv-desc.h: Regenerate. - * ip2k-asm.c,ip2k-desc.c,ip2k-desc.h: Regenerate. - * iq2000-asm.c,iq2000-desc.c,iq2000-desc.h: Regenerate. - * m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-opc.c: Regenerate. - * openrisc-asm.c,openrisc-desc.c,openrisc-desc.h: Regenerate. - * xstormy16-asm.c,xstormy16-desc.c,xstormy16-desc.h: Regenerate. - -2003-06-10 Gary Hade <garyhade@us.ibm.com> - Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define. - (insert_dq, extract_dq, insert_raq, insert_rtq, insert_rsq): New. - (powerpc_opcodes): Add "attn", "lq" and "stq". - -2003-06-10 Richard Sandiford <rsandifo@redhat.com> - - * h8300-dis.c (bfd_h8_disassemble): Don't print brackets round - rts/l and rte/l register lists. - -2003-06-03 Nick Clifton <nickc@redhat.com> - - * frv-desc.c: Regenerate. - * frv-opc.c: Regenerate. - * frv-asm.c: Regenerate. - * frv-desc.h: Regenerate. - * frv-dis.c: Regenerate. - * frv-ibld.c: Regenerate. - * frv-opc.h: Regenerate. - * po/opcodes.pot: Regenerate. - -2003-06-03 Michael Snyder <msnyder@redhat.com> - and Bernd Schmidt <bernds@redhat.com> - and Alexandre Oliva <aoliva@redhat.com> - - * disassemble.c (disassembler): Add support for h8300sx. - * h8300-dis.c: Ditto. - -2003-06-03 Nick Clifton <nickc@redhat.com> - - * frv-desc.c: Regenerate. - * frv-opc.c: Regenerate. - - * aclocal.m4: Regenerate. - * config.in: Regenerate. - * configure: Regenerate. - * iq2000-asm.c: Regenerate. - * iq2000-desc.c: Regenerate. - * iq2000-desc.h: Regenerate. - * iq2000-dis.c: Regenerate. - * iq2000-ibld.c: Regenerate. - * iq2000-opc.c: Regenerate. - * iq2000-opc.h: Regenerate. - * po/POTFILES.in: Regenerate. - * po/opcodes.pot: Regenerate. - -2003-05-23 Jason Eckhardt <jle@rice.edu> - - * i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3. - (print_insn_i860): Grab 4 bits of the control register field - instead of 3. - -2003-05-18 Jason Eckhardt <jle@rice.edu> - - * i860-dis.c (print_insn_i860): Instruction shrd has a dual bit, - print it. - -2003-05-17 Andreas Jaeger <aj@suse.de> - - * Makefile.am (libopcodes_la_LIBADD): Add libbfd.la. - (libopcodes_la_DEPENDENCIES): Add libbfd.la. - * Makefile.in: Regenerated. - -2003-05-16 Nick Clifton <nickc@redhat.com> - - * configure.in (ALL_LINGUAS): Add Romanian translation. - * configure: Regenerate. - * po/ro.po: New file: Romanian translation. - -2003-05-12 Dhananjay Deshpande <dhananjayd@kpitcummins.com> - - * disassemble.c (disassembler): Add support for h8300hn and h8300sn. - -2003-05-09 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c (print_insn): Test intel_syntax against (char) -1 in - case char is unsigned. - -2003-05-01 Christian Groessler <chris@groessler.org> - - * z8k-dis.c (z8k_lookup_instr): Optimize FETCH_DATA calls. - (unpack_instr): Fix representation of segmented addresses. - (intr_name): Added, contains names of the parameters to the EI/DI - instructions. - (unparse_instr): Fix display of EI/DI parameters. - -2003-04-22 Doug Evans <dje@sebabeach.org> - - * fr30-desc.c,fr30-desc.h,fr30-opc.c,fr30-opc.h: Regenerate. - * frv-desc.c,frv-desc.h,frv-opc.c,frv-opc.h: Regenerate. - * ip2k-desc.c,ip2k-desc.h,ip2k-opc.c,ip2k-opc.h: Regenerate. - * m32r-desc.c,m32r-desc.h,m32r-opc.c,m32r-opc.h: Regenerate. - * m32r-opinst.c: Regenerate. - * openrisc-desc.c,openrisc-desc.h,openrisc-opc.c,openrisc-opc.h: Regenerate. - * xstormy16-desc.c,xstormy16-desc.h,xstormy16-opc.c,xstormy16-opc.h: Regenerate. - -2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com> - - * h8500-opc.c: Replace occurrances of 'Hitachi' with 'Renesas'. - -2003-04-07 James E Wilson <wilson@tuliptree.org> - - * ia64-ic.tbl (fr-readers): Add mem-writers-fp. - * ia64-asmtab.c: Regenerate. - -2003-04-08 Alexandre Oliva <aoliva@redhat.com> - - * mips-dis.c (mips_gpr_names_newabi): Reverted previous patch. - -2003-04-07 Alexandre Oliva <aoliva@redhat.com> - - * mips-dis.c (mips_gpr_names_newabi): $12-$15 are named $t4-$t7. - -2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x-dis.c: Namespace cleanup. Replace s/c4x/tic4x and - s/c3x/tic3x/ - -2003-04-01 Nick Clifton <nickc@redhat.com> - - * arm-dis.c: Remove presence of (r) and (tm) symbols. - * arm-opc.h: Remove presence of (r) and (tm) symbols. - -2003-03-25 Stan Cox <scox@redhat.com> - Nick Clifton <nickc@redhat.com> - - Contribute support for Intel's iWMMXt chip - an ARM variant: - - * arm-dis.c (regnames): Add iWMMXt register names. - (set_iwmmxt_regnames): New function. - (print_insn_arm): Handle iWMMXt formatters. - * arm-opc.h: Document iWMMXt formatters. - (arm_opcod): Add iWMMXt instructions. - -2003-03-22 Doug Evans <dje@sebabeach.org> - - * i386-dis.c (dis386): Recognize icebp (0xf1). - -2003-03-21 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-dis.c (init_disasm): Rename S390_OPCODE_ESAME to - S390_OPCODE_ZARCH. - (print_insn_s390): Use new modes field of s390_opcodes. - * s390-mkopc.c (ARCHBITS_ESAONLY, ARCHBITS_ESA, ARCHBITS_ESAME): Remove. - (s390_opcode_mode_val, s390_opcode_cpu_val): New enums. - (struct op_struct): Remove archbits. Add mode_bits and min_cpu. - (insertOpcode): Replace archbits by min_cpu and mode_bits. - (dumpTable): Write mode_bits and min_cpu instead of archbits. - (main): Adapt to new format in s390-opcode.txt. - * s390-opc.c (s390_opformats): Replace archbits by min_cpu and - mode_bits. - * s390-opc.txt: Replace archbits by min_cpu and mode_bits. - -2003-03-17 Nick Clifton <nickc@redhat.com> - - * ppc-opc.c: Fix formatting. Update copyright date. - -2003-03-14 Daniel Jacobowitz <drow@mvista.com> - - * ppc-opc.c (powerpc_opcodes): Readd tlbre for PPC403. - -2003-02-25 Alan Modra <amodra@bigpond.net.au> - - * hppa-dis.c: Formatting. - -2003-02-25 Matthew Wilcox <willy@debian.org> - - * hppa-dis.c (print_insn_hppa): Implement fcnv instruction modifiers. - - * hppa-dis.c (print_insn_hppa <2 bit space register>): Do not print - the space register when the value is zero. - -2003-02-23 Elias Athanasopoulos <elathan@phys.uoa.gr> - - * mips-dis.c (print_mips_disassembler_options): Make 'i' unsigned, - use ARRAY_SIZE in loops. - -2003-02-12 Dave Brolley <brolley@redhat.com> - - * fr30-desc.c: Regenerate. - -2003-02-06 Gwenole Beauchesne <gbeauchesne@mandrakesoft.com> - - * i386-dis.c (dq_mode, Edq): Define. - (dis386_twobyte): Correct movd operands. - (OP_E): Handle dq_mode case. - -2003-01-29 Henric Jungheim <henric@attbi.com> - - * sparc-dis.c (print_insn_sparc): When examining values added in - to rs1, make sure that there are previous instructions. - -2003-01-23 Nick Clifton <nickc@redhat.com> - - * Add sh2e support: - - 2002-04-02 Alexandre Oliva <aoliva@redhat.com> - - * sh-dis.c (print_insn_shx): Handle bfd_mach_sh2e. - * sh-opc.h (arch_sh2e, arch_sh2e_up): New. - (arch_sh2_up): Added sh2e. - (sh_table): Replaced all occurrences of arch_sh3e_up with - arch_sh2e_up, except in fsqrt. - -2003-01-23 Alan Modra <amodra@bigpond.net.au> - - * sh64-dis.c: Include elf32-sh64.h. - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - -2003-01-17 Richard Henderson <rth@redhat.com> - - * alpha-opc.c (alpha_opcodes): Add bugchk, rduniq, wruniq, gentrap - PAL entry points. - -2003-01-16 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - -2003-01-08 Klee Dienes <kdienes@apple.com> - - * Makefile.am (ALL_MACHINES): Add msp430-dis.lo. - * Makefile.in: Regenerate. - -2003-01-08 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c (powerpc_macros <extrwi>): Accept a shift of 32. - -2002-01-02 Ben Elliston <bje@redhat.com> - Jeff Johnston <jjohnstn@redhat.com> - - * iq2000-asm.c: New file. - * iq2000-desc.c: Likewise. - * iq2000-desc.h: Likewise. - * iq2000-dis.c: Likewise. - * iq2000-ibld.c: Likewise. - * iq2000-opc.c: Likewise. - * iq2000-opc.h: Likewise. - * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h. - (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c, - iq2000-ibld.c, iq2000-opc.c. - (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo, - iq2000-ibld.lo, iq2000-opc.lo. - (CLEANFILES): Add stamp-iq2000. - (IQ2000_DEPS): New macro. - (stamp-iq2000): New target. - * Makefile.in: Regenerate. - * configure.in: Handle bfd_iq2000_arch. - * configure: Regenerate. - -2003-01-02 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (print_insn_args): Use position extracted by "+A" - to calculate size for "+B". Redo code for "+C" so it shares - the same style as "+A" and "+B" now do. - -2003-01-02 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c: Update copyright years. - (print_insn_arg): Rename to... - (print_insn_args): This, returning void. Process the whole - string of args rather than a single one. Reindent. - (print_insn_mips): Update to match the above. - -2002-12-31 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Move "di" into the - right order alphabetically, and make all hex constants use - lower-case letters. - -2002-12-31 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (mips_cp0sel_name): New structure. - (mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2) - (mips_cp0sel_names_sb1): New arrays. - (mips_arch_choice): New structure members "cp0sel_names" and - "cp0sel_names_len". - (mips_arch_choices): Add references to new cp0sel_names arrays - as appropriate, and make all existing entries reference - appropriate mips_XXX_names_numeric arrays rather than simply - using NULL. - (mips_cp0sel_names, mips_cp0sel_names_len): New variables. - (lookup_mips_cp0sel_name): New function. - (set_default_mips_dis_options): Set mips_cp0sel_names and - mips_cp0sel_names_len as appropriate. Remove now-unnecessary - checks for NULL register name arrays. - (parse_mips_dis_option): Likewise. - (print_insn_arg): Handle "+D" operand type. - * mips-opc.c (mips_builtin_opcodes): Add new "+D" variants - of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register - names symbolically. - -2002-12-30 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric) - (mips_hwr_names_mips3264r2): New arrays. - (mips_arch_choice): New "hwr_names" member. - (mips_arch_choices): Adjust for structure change, and add a new - entry for "mips32r2" ISA. - (mips_hwr_names): New variable. - (set_default_mips_dis_options): Set mips_hwr_names. - (parse_mips_dis_option): New "hwr-names" option which sets - mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names. - (print_insn_arg): Change return type to "int" - and use that to indicate number of characters consumed. - Add support for "+" operand extension character, "+A", "+B", - "+C", and "K" operands. - (print_insn_mips): Adjust for changes to print_insn_arg. - (print_mips_disassembler_options): Adjust for "hwr-names" - addition and "reg-names" change. - * mips-opc (I33): New define (shorthand for INSN_ISA32R2). - (mips_builtin_opcodes): Note that "nop" and "ssnop" are special - forms of "sll". Add new MIPS32 Release 2 instructions: ehb, - di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2, - rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh. - Note that hardware rotate instructions (ror, rorv) can be - used on MIPS32 Release 2, and add the official mnemonics - for them (rotr, rotrv) and the similar "rotl" mnemonic for - left-rotate. - -2002-12-30 Dmitry Diky <diwil@mail.ru> - - * configure.in: Add msp430 target. - * configure: Regenerate. - * disassemble.c: Add entry for msp430 disassembly. - * msp430-dis.c: New file: msp430 disassembler. - -2002-12-27 Chris Demetriou <cgd@broadcom.com> - - * disassemble.c (disassembler_usage): Add invocation of - print_mips_disassembler_options. - * mips-dis.c: Include libiberty.h. - (print_mips_disassembler_options, set_default_mips_dis_options) - (parse_mips_dis_option, parse_mips_dis_options, choose_abi_by_name) - (choose_arch_by_name, choose_arch_by_number): New functions. - (mips_abi_choice, mips_arch_choice): New structures. - (mips32_reg_names, mips64_reg_names, reg_names): Remove. - (mips_gpr_names_numeric, mips_gpr_names_oldabi) - (mips_gpr_names_newabi, mips_fpr_names_numeric) - (mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64) - (mips_cp0_names_numeric, mips_cp0_names_mips3264) - (mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices) - (mips_processor, mips_isa, mips_gpr_names, mips_fpr_names) - (mips_cp0_names): New variables. - (print_insn_args): Use new variables to print GPR, FPR, and CP0 - register names. - (mips_isa_type): Remove. - (print_insn_mips): Remove ISA and CPU setup since it is now done... - (_print_insn_mips): Here. Remove register setup code, and - call set_default_mips_dis_options and parse_mips_dis_options - instead. - (print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names. - -2002-12-23 Alan Modra <amodra@bigpond.net.au> - - * Makefile.in: Regenerate. - -2002-12-19 Nick Kelsey <nickk@ubicom.com> - - * cgen-asm.c (cgen_parse_keyword): Added underscore to symbol character - check to fix false keyword trigger with names such as <keyword>_foo. - -2002-12-19 Doug Evans <dje@sebabeach.org> - - * Makefile.am (CGEN_CPUS): New variable. - (run-cgen-all): New rule. - * Makefile.in: Regenerate. - -2002-12-18 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two - "dror" entries, and reorder the remaining "dror" and "ror" entries. - -2002-12-16 DJ Delorie <dj@delorie.com> - - * xstormy16-asm.c (parse_immediate16): Add prototype. - -2002-12-16 Andrew MacLeod <amacleod@redhat.com> - - * xstormy16-asm.c: Regenerate. - -2002-12-16 Alan Modra <amodra@bigpond.net.au> - - * ns32k-dis.c (print_insn_ns32k): Constify "d", remove register - keyword. - -2002-12-13 Alan Modra <amodra@bigpond.net.au> - - * h8500-opc.h (h8500_table): Add missing initializers to quiet - warnings. - * pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change. - * pj-opc.c (pj_opc_info): Add braces around union initializer. - * z8kgen.c: Include "libiberty.h". - (opt, args, toks): Fix initializer warnings. - (chewname): Make "name" a char **. Return mnemonic trimmed of - operands. - (gas): Improve emitted "DO NOT EDIT" warning. Format emitted - opcode_entry_type, and make "nicename" and "name" const. Make - z8k_table const too. Formatting. Generate idx as gas needs it. - * z8k-opc.h: Regenerate. - -2002-12-08 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11-dis.c (print_indexed_operand): Fix PC-relative address - for 9 and 16-bit PC-relative addressing mode. - -2002-12-05 Aldy Hernandez <aldyh@redhat.com> - - * ppc-opc.c: Delete evsabs, evsnabs, evsneg, evsadd, evssub, - evsmul, evsdiv, evscmpgt, evsgmplt, evststgt, evtstlt, evststeq, - evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi, - evsctsiz, evsctuf, evsctsf, evmwhssfaa, evmwhssmaa, evmwhsmfaa, - evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, - evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, - evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, - evmwhgsmian, evmwhgumian. - (mftb): Add to opcode table. - (mtspefscr): Change RT to RS in opcode table. - -2002-12-05 Aldy Hernandez <aldyh@redhat.com> - - * ppc-opc.c: Move mbar and msync up. Change mask for mbar and - msync. - -2002-12-04 David Mosberger <davidm@hpl.hp.com> - - * ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction. - * ia64-opc-b.c: Add "hint.b" instruction. - * ia64-opc-f.c: Add "hint.f" instruction. - * ia64-opc-i.c: Add "hint.i" instruction. - * ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and - "cmp8xchg16" instructions. - * ia64-opc-x.c: Add "hint.x" instruction. - - * ia64-opc.h (AR_CSD): New macro. - - * ia64-ic.tbl: Update according to SDM2.1. - * ia64-raw.tbl: Ditto. - * ia64-waw.tbl: Ditto. - - * ia64-gen.c (in_iclass): Handle "hint" like "nop". - (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD], - AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR]. - * ia64-asmtab.c: Regenerate. - -2002-11-25 Aldy Hernandez <aldyh@redhat.com> - - * ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa, - evmwlssfaaw, evmwlsmfaaw, evmwlssfanw, evmwlsfanw. - -2002-12-04 Aldy Hernandez <aldyh@redhat.com> - - * ppc-opc.c (PMRN): Remove. - (RA): Set to NB + 1. - (powerpc_opcodes): Change PMRN to SPR. - Change all RD to RS. - Change mftb to look like mftbl. - Move mftb before mftbl. - Add mfbbtar. - Add mtbbtar. - Change mfpmr to use PMR. - Change mtpmr to use PMR. - (RD): Remove. - (insert_ev2): Fix mask and shift. - (extract_ev2): Same. - (insert_ev4): Same. - (extract_ev4): Same. - (PMR): Define. - (extract_pmrn): Remove. - (insert_pmrn): Remove. - -2002-12-03 Richard Henderson <rth@redhat.com> - - * ia64-opc-m.c: Add ld8.mov. - * ia64-asmtab.c: Regenerate. - -2002-12-02 Alan Modra <amodra@bigpond.net.au> - - * arm-dis.c (print_insn_arm): Constify "insn". Formatting. - (print_insn_thumb): Likewise. - * h8500-dis.c (print_insn_h8500): Constify "opcode". - * mcore-dis.c (print_insn_mcore): Constify "op". Formatting. - * ns32k-dis.c (print_insn_arg <case 'F'>): Use a union to avoid - type-punned pointer warnings. - <case 'L'>: Likewise. Fix error message too. - * pdp11-dis.c (print_reg): Warning fix. - * sh-dis.c (print_movxy): Constify "op" param. - (print_insn_ddt): Constify sh_opcode_info vars. - (print_insn_ppi): Likewise. - (print_insn_sh): Likewise. - * tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid - type-punned pointer warnings. - * w65-dis.c (print_insn_w65): Constify "op". - -2002-12-01 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11-dis.c (PC_REGNUM): Define. - (print_indexed_operand): Need an adjustment for some PC-relative - operand modes; print the final address of PC-relative modes. - (print_insn): Take into account movw/movb to adjust the PC-relative - operand addresses. - -2002-11-30 Alan Modra <amodra@bigpond.net.au> - - *arm-dis.c, cris-dis.c, h8300-dis.c, mips-dis.c, mmix-dis.c, sh-dis.c, - sh64-dis.c, v850-dis.c: Replace boolean with bfd_boolean, true with - TRUE, false with FALSE. Simplify comparisons of bfd_boolean vars - with TRUE/FALSE. Formatting. - -2002-11-25 DJ Delorie <dj@redhat.com> - - * xstormy16-opc.c: Regenerate. - -2002-11-25 Jim Wilson <wilson@redhat.com> - - * ia64-dis.c (print_insn_ia64): Correct handling of IA64_OPND_TGT64. - -2002-11-15 DJ Delorie <dj@redhat.com> - - * xstormy16-desc.c: Regenerate. - * xstormy16-opc.c: Regenerate. - * xstormy16-opc.h: Regenerate. - -2002-11-18 Klee Dienes <kdienes@apple.com> - - * avr-dis.c: Include libiberty.h (for xmalloc). - (struct avr_opcodes_s): Remove 'bin_mask' field (it's - automatically computed in the init routine). - (AVR_INSN): No longer provide bin_mask field in initializer. - (avr_opcodes_s): Declare as const. - (print_insn_avr): Store the bin_mask field in a separate table - (allocated with xmalloc); iterate through it at the same time as - we iterate through the opcodes. - -2002-11-18 Klee Dienes <kdienes@apple.com> - - * h8300-dis.c: Include libiberty.h (for xmalloc). - (struct h8_instruction): New type, used to wrap h8_opcodes with a - length field (computed at run-time). - (h8_instructions): New variable. - (bfd_h8_disassemble_init): Allocate the storage for - h8_instructions. Fill h8_instructions with pointers to the - appropriate opcode and the correct value for the length field. - (bfd_h8_disassemble): Iterate through h8_instructions instead of - h8_opcodes. - -2002-11-18 Klee Dienes <kdienes@apple.com> - - * arc-opc.c (arc_ext_opcodes): Define. - (arc_ext_operands): Define. - * i386-dis.c (Suffix3DNow): Declare as const. - * arm-opc.h (arm_opcodes): Declare as const. - (thumb_opcodes): Declare as const. - * h8500-opc.h (h8500_table): Declare as const. - (h8500_table): Use a NULL for the opcode in the terminator, so - that code testing (opcode->name) behaves correctly. - * mcore-opc.h (mcore_table): Declare as const. - * sh-opc.h (sh_table): Declare as const. - * w65-opc.h (optable): Declare as const. - * z8k-opc.h (z8k_table): Declare as const. - -2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x-dis.c: Added support for enhanced and special insn. - (c4x_print_op): Added insn class 'i' and 'j' - (c4x_hash_opcode_special): Add to support special insn - (c4x_hash_opcode): Update to support the new opcode-list - format. Add support for the new special insns. - (c4x_disassemble): New opcode-list support. - -2002-11-16 Klee Dienes <kdienes@apple.com> - - * m88k-dis.c: Include libiberty.h (for xmalloc). - (HASHTAB): New type, used to build instruction hash tables. - Contains a pointer to an INSTAB and a pointer to the next hash - chain entry. - (instructions): Move definition from m88k.h; remove initialization - of 'next' field. - (hashtable): Now an aray of pointer-to-HASHTAB, not INSTAB. - (printop): Mark pointer to OPSPEC as const. - (install): Remove; fold into init_disasm. - (m88kdis): Update to ihashtab_initialized to 1 after calling - init_disasm. entry_ptr now iterates through HASHTABs, not - INSTABs. - (init_disasm): Iterate through the instructions and add to - hashtable[]. - -2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x-dis.c: (c4x_print_op): Add support for the new argument - format. Fix bug in 'N' register printer. - -2002-11-12 Segher Boessenkool <segher@koffie.nl> - - * ppc-dis.c (print_insn_powerpc): Correct condition register display. - -2002-11-07 Aldy Hernandez <aldyh@redhat.com> - - * ppc-opc.c (EVUIMM_4): Change bit size to 32. - (EVUIMM_2): Same. - (EVUIMM_8): Same. - -2002-11-07 Klee Dienes <kdienes@apple.com> - - * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir' - argument to ia64-gen. - Regenerate dependencies for ia64-len.lo. - * Makefile.in: Regenerate. - * ia64-gen.c: Convert to use getopt(). Add the standard GNU - options, as well as '--srcdir', which controls the directory in - which ia64-gen looks for the sources it uses to generate the - output table. Add a 'const' to the declaration of the final - output table. Call xmalloc_set_program_name to set the program - name. - * ia64-asmtab.c: Regenerate. - -2002-11-07 Nick Clifton <nickc@redhat.com> - - * ia64-gen.c: Fix comment formatting and compile time warnings. - * ia64-opc-a.c: Fix compile time warnings. - * ia64-opc-b.c: Likewise. - * ia64-opc-d.c: Likewise. - * ia64-opc-f.c: Likewise. - * ia64-opc-i.c: Likewise. - * ia64-opc-m.c: Likewise. - * ia64-opc-x.c: Likewise. - -2002-11-06 Aldy Hernandez <aldyh@redhat.com> - - * ppc-opc.c: Change RD to RS for evmerge*. - -2002-10-07 Nathan Tallent <eraxxon@alumni.rice.edu> - - * sparc-opc.c (sparc_opcodes) <fb, fba, fbe, fbz, fbg, fbge, - fbl, fble, fblg, fbn, fbne, fbnz, fbo, fbu, fbue, fbug, fbuge, - fbul, fbule>: Add conditional/unconditional branch - classification. - -2002-10-13 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11-dis.c (print_insn): Treat bitmask and branch operands - at the end. - -2002-09-30 Gavin Romig-Koch <gavin@redhat.com> - Ken Raeburn <raeburn@cygnus.com> - Aldy Hernandez <aldyh@redhat.com> - Eric Christopher <echristo@redhat.com> - Richard Sandiford <rsandifo@redhat.com> - - * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'. - (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400 - and bfd_mach_mips5500. - * mips-opc.c (V1): Include INSN_4111 and INSN_4120. - (N411, N412, N5, N54, N55): New convenience defines. - (mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes. - Change dmadd16 and madd16 from V1 to N411. - -2002-09-26 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (print_insn_mips): Always allow disassembly of - 32-bit jalx opcode. - -2002-09-24 Nick Clifton <nickc@redhat.com> - - * po/de.po: Updated German translation. - -2002-09-21 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - -2002-09-20 Nick Clifton <nickc@redhat.com> - - * ppc-opc.c (CRFD, CRFS): Add PPC_OPERAND_CR flag so that cr - register names are accepted. - -2002-09-17 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x-dis.c: Add function declarations and ATTRIBUTE_UNUSED. - Convert functions to K&R format. - -2002-09-13 Nick Clifton <nickc@redhat.com> - - * ppc-opc.c (MFDEC2): Include Book-E. - (PPCCHLK64): New opcode mask. - (evsubw, evsubiw, evmr, evnot, isellt, iselgt, iseleq, mfpid, - mfcsrr0, mfcsrr1, mfdear, mfesr, mfivpr, mfusprg0, mftbl, - mftbu, mfpir, mfdbsr, mfdbcr0, mfdbcr1, mfdbcr2, mfiac1, - mfiac2, mfiac3, mfiac4, mfdac1, mfdac2, mfdvc1, mfdvc2, mftsr, - mftcr, mfivor0, mfivor1, mfivor2, mfivor3, mfivor4, mfivor5, - mfivor6, mfivor7, mfivor8, mfivor9, mfivor10, mfivor11, - mfivor12, mfivor13, mfivor14, mfivor15, mfbbear, mfmcsrr0, - mfmcsrr1, mfmcsr, mtpid, mtdecar, mtcsrr0, mtcsrr1, mtdear, - mtesr, mtivpr, mtusprg0, mtsprg4, mtsprg5, mtsprg6, mtsprg7, - mtdbsr, mtdbcr0, mtdbcr1, mtdbcr2, mtiac1, mtiac2, mtiac3, - mtiac4, mtdac1, mtdac2, mtdvc1, mtdvc2, mttsr, mttcr, mtivor0, - mtivor1, mtivor2, mtivor3, mtivor4, mtivor5, mtivor6, mtivor7, - mtivor8, mtivor9, mtivor10, mtivor11, mtivor12, mtivor13, - mtivor14, mtivor15, mtbbear, mtmcsrr0, mtmcsrr1, mtmcsr): New - Book-E instructions. - (evfsneg): Fix opcode value. - (dcbtstlse, dcbtlse, icblce, dcblce, icbtsle): Use PPCCHLK64 - mask. - (mcrxr64, tlbivaxe, tlbsxe, tlbsxe.): Restrict to 64-bit - Book-E. - (extsw): Restrict to 64-bit PPC instruction sets. - (extsw.): Does not exist in 64-bit Book-E. - (powerpc_macro): Remove mftbl, mftbu and mftb Book-E macros as - they are no longer needed. - -2002-09-12 Gary Hade <garyhade@us.ibm.com> - - * ppc-dis.c (powerpc_dialect): Add missing PPC_OPCODE_CLASSIC. - -2002-09-11 Nick Clifton <nickc@redhat.com> - - * po/da.po: Updated Danish translation file. - -2002-09-04 Nick Clifton <nickc@redhat.com> - - * ppc-opc.c (extsw, extsw.): Do not allow for the BookE32. - -2002-09-04 Nick Clifton <nickc@redhat.com> - - * disassemble.c (disassembler_usage): Add invocation of - print_ppc_disassembler_options. - * ppc-dis.c (print_ppc_disassembler_options): New function. - -2002-09-04 Nick Clifton <nickc@redhat.com> - - * ppc-opc.c: The BookE implementations of the TLBWE and TLBRE - instructions do not take any arguments. - -2002-09-02 Nick Clifton <nickc@redhat.com> - - * v850-opc.c: Remove redundant references to V850EA architecture. - -2002-09-02 Alan Modra <amodra@bigpond.net.au> - - * arc-opc.c: Include bfd.h. - (arc_get_opcode_mach): Subtract off base bfd_mach value. - -2002-08-30 Alan Modra <amodra@bigpond.net.au> - - * v850-dis.c (disassemble): Remove bfd_mach_v850ea case. - - * mips-dis.c (_print_insn_mips): Don't use hard-coded mach constants. - -2002-08-28 Svein E. Seldal <Svein.Seldal@solidas.com> - - * configure.in: Added bfd_tic4x_arch. - * configure: Regenerate. - * Makefile.am: Added tic4x-dis.o target. - * Makefile.in: Regenerate. - -2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> - - * disassemble.c: Added tic4x target and c4x - disassembler routine. - * tic4x-dis.c: New file. - -2002-08-16 Christian Groessler <chris@groessler.org> - - * z8k-dis.c (unparse_instr): case CLASS_BA: Designate hex - values as those. - * z8kgen.c (opt): Fix definition of "in rd,imm16" opcode. - * z8k-opc.h: Regenerated with new z8kgen.c. - -2002-08-19 Elena Zannoni <ezannoni@redhat.com> - - From matthew green <mrg@redhat.com> - - * ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and - `-mefs'. Turn off AltiVec for E500 and efs. - (print_insn_powerpc): Don't print an AltiVec instruction if the - dialect is not efs. - - * ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2, - insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions - for extracting pmrn/evld/evstd/etc operands. - (CRB, CRFD, CRFS, DC, RD): New instruction fields. - (CT): Make this equal to RD + 1. - (PMRN): New operand. - (RA): Update. - (EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands. - (WS): Update. - (EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL. - (ISEL, ISEL_MASK): New instruction form and mask for ISEL. - (XISEL, XISEL_MASK): New instruction form and mask for ISEL. - (CTX, CTX_MASK): New instruction form and mask for context cache - instructions. - (UCTX, UCTX_MASK): New instruction form and mask for user context - cache instructions. - (XC, XC_MASK, XUC, XUC_MASK): New instruction forms. - (CLASSIC): New define. - (PPCESPE): New define. - (PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New - defines for integer select, cache control, branch - locking, power management, cache locking and machine check - APU instructions, respectively. - (efsabs, efsnabs, efsneg, efsadd, efssub, efsmul, - efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt, - efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf, - efsctui, efsctsi, efsctsiz, efsctuf, efsctsf, - evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb, - evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor, - evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi, - evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi, - evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts, - evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh, - evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx, - evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat, - evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx, - evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe, - evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox, - evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv, - evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq, - evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui, - evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg, - evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq, - evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf, - evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf, - evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi, - evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi, - evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw, - evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw, - evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw, - evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw, - evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw, - evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa, - evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian, - evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf, - evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa, - evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan, - evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa, - evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian, - evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi, - evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi, - evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw, - evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw, - evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa, - evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia, - evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan, - evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw, - evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw, - evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex - instructions. - (rfmci): New machine check APU instruction. - (isel): New integer select APU instructino. - (icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls, - dcbtstlse, dcblc, dcblce): New cache control APU instructions. - (mtspefscr, mfspefscr): New instructions. - (mfpmr, mtpmr): New performance monitor APU instructions. - (savecontext): New context cache APU instructions. - (bblels, bbelr): New branch locking APU instructions. - (bblels, bbelr): New instructions. - (mftbl, mftbu, mftb): Set as CLASSIC instructions. Add BOOKE alias. - -2002-08-13 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11-opc.c: Update call operand to accept the page definition. - Identify instructions that are branches and calls to generate a - RL_JUMP relocation. - -2002-08-13 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11-dis.c (print_insn): Take into account 68HC12 memory - banks and fix disassembling of call instruction. - (print_indexed_operand): New param to tell whether - it was an indirect addressing operand (for disassembling call). - -2002-08-09 Nick Clifton <nickc@redhat.com> - - * po/sv.po: Updated Swedish translation. - -2002-08-08 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as - aliases to "daddiu" and "addiu". - -2002-07-30 Nick Clifton <nickc@redhat.com> - - * po/sv.po: Updated Swedish translation. - -2002-07-25 Nick Clifton <nickc@redhat.com> - - * po/sv.po: Updated Swedish translation. - * po/es.po: Updated Spanish translation. - * po/pr_BR.po: Updated Brazilian Portuguese translation. - * po/tr.po: Updated Turkish translation. - * po/fr.po: Updated French translation. - -2002-07-24 Nick Clifton <nickc@redhat.com> - - * po/sv.po: Updated Swedish translation. - * po/es.po: Updated Spanish translation. - * po/pr_BR.po: Updated Brazilian Portuguese translation. - -2002-07-23 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - -2002-07-23 Nick Clifton <nickc@redhat.com> - - * po/fr.po: Updated French translation. - * po/pr_BR.po: New Brazilian Portuguese translation. - * po/id.po: Updated Indonesian translation. - * configure.in (LINGUAS): Add pr_BR. - * configure: Regenerate. - -2002-07-18 Denis Chertykov <denisc@overta.ru> - Frank Ch. Eigler <fche@redhat.com> - Alan Lehotsky <alehotsky@cygnus.com> - matthew green <mrg@redhat.com> - - * configure.in: Add support for ip2k. - * configure: Regenerate. - * Makefile.am: Add support for ip2k. - * Makefile.in: Regenerate. - * disassemble.c: Add support for ip2k. - * ip2k-asm.c: New generated file. - * ip2k-desc.c: New generated file. - * ip2k-desc.h: New generated file. - * ip2k-dis.c: New generated file. - * ip2k-ibld.c: New generated file. - * ip2k-opc.c: New generated file. - * ip2k-opc.h: New generated file. - -2002-07-17 David Mosberger <davidm@hpl.hp.com> - - * ia64-opc-b.c (bWhc): New macro. - (mWhc): Ditto. - (OpPaWhcD): Ditto. - (ia64_opcodes_b): Correct patterns for indirect call - instructions to use 3-bit "wh" field. - * ia64-asmtab.c: Regnerate. - -2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. - * mips-opc.c (I16): New define. - (mips_builtin_opcodes): Make jalx an I16 insn. - -2002-06-18 Dave Brolley <brolley@redhat.com> - - * po/POTFILES.in: Add frv-*.[ch]. - * disassemble.c (ARCH_frv): New macro. - (disassembler): Handle bfd_arch_frv. - * configure.in: Support frv_bfd_arch. - * Makefile.am (HFILES): Add frv-*.h. - (CFILES): Add frv-*.c - (ALL_MACHINES): Add frv-*.lo. - (CLEANFILES): Add stamp-frv. - (FRV_DEPS): New variable. - (stamp-frv): New target. - (frv-asm.lo): New target. - (frv-desc.lo): New target. - (frv-dis.lo): New target. - (frv-ibld.lo): New target. - (frv-opc.lo): New target. - (frv-*.[ch]): New files. - -2002-06-18 Ben Elliston <bje@redhat.com> - - * Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen. - * Makefile.in: Regenerate. - -2002-06-08 Alan Modra <amodra@bigpond.net.au> - - * a29k-dis.c: Replace CONST with const. - * h8300-dis.c: Likewise. - * m68k-dis.c: Likewise. - * or32-dis.c: Likewise. - * sparc-dis.c: Likewise. - -2002-06-04 Jason Thorpe <thorpej@wasabisystems.com> - - * configure.in: Add "sh5*-*" to list of targets which include - sh64 support. - * configure: Regenerate. - -2002-05-31 Chris G. Demetriou <cgd@broadcom.com> - - * mips-opc.c: Clean up a few whitespace issues, and sort a - few entries understanding that 'x' follows 'w' in the alphabet. - -2002-05-31 Chris G. Demetriou <cgd@broadcom.com> - Ed Satterthwaite <ehs@broadcom.com> - - * mips-opc.c: Add support for SB-1 MDMX subset and extensions. - -2002-05-31 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - -2002-05-30 Chris G. Demetriou <cgd@broadcom.com> - Ed Satterthwaite <ehs@broadcom.com> - - * mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y', - and 'Z' formats, for MDMX. - (mips_isa_type): Add MDMX instructions to the ISA - bit mask for bfd_mach_mipsisa64. - * mips-opc.c: Add support for MDMX instructions. - (MX): New definition. - - * mips-dis.c: Update copyright years to include 2002. - -2002-05-30 Diego Novillo <dnovillo@redhat.com> - - * d10v-opc.c (d10v_opcodes): `btsti' does not modify its - arguments. - -2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> - - * configure.in: Add DLX configuraton support. - * configure: Regenerate. - * Makefile.am: Add DLX configuraton support. - * Makefile.in: Regenerate. - * disassemble.c: Add DLX support. - * dlx-dis.c: New file. - -2002-05-25 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am (sh-dis.lo): Don't put make commands in deps. - * Makefile.in: Regenerate. - * arc-dis.c: Use #include "" instead of <> for local header files. - * m68k-dis.c: Likewise. - -2002-05-22 J"orn Rennecke <joern.rennecke@superh.com> - - * Makefile.am (sh-dis.lo): Compile with @archdefs@. - * Makefile.in: regenerate. - - * sh-dis.c (print_insn_sh): If coff and bfd_mach_sh, use arch_sh4 - for disassembly. - -2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros. - -2002-05-17 J"orn Rennecke <joern.rennecke@superh.com> - - * disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh. - * sh-dis.c (LITTLE_BIT): Delete. - (print_insn_sh, print_insn_shl): Deleted. - (print_insn_shx): Renamed to - (print_insn_sh). No longer static. Handle SHmedia instructions. - Use info->endian to determine endianness. - * sh64-dis.c (print_insn_sh64, print_insn_sh64l): Delete. - (print_insn_sh64x): No longer static. Renamed to - (print_insn_sh64). Removed pfun_compact and endian arguments. - If we got an uneven address to indicate SHmedia, adjust it. - Return -2 for SHcompact instructions. - -2002-05-17 Alan Modra <amodra@bigpond.net.au> - - * acinclude.m4 (AM_INSTALL_LIBBFD): Fake to fool autotools. - * configure.in: Invoke AM_INSTALL_LIBBFD. - * Makefile.am (install-data-local): Move to.. - (install_libopcodes): .. New target. - (uninstall_libopcodes): Likewise. - (install-bfdlibLTLIBRARIES): Likewise. - (uninstall-bfdlibLTLIBRARIES): Likewise. - (bfdlibdir): New. - (bfdincludedir): New. - (lib_LTLIBRARIES): Rename to bfdlib_LTLIBRARIES. - * aclocal.m4: Regenerate. - * configure: Regenerate. - * Makefile.in: Regenerate. - -2002-05-15 Nick Clifton <nickc@cambridge.redhat.com> - - * fr30-asm.c: Regenerate. - * fr30-desc.c: Regenerate. - * fr30-dis.c: Regenerate. - * m32r-asm.c: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-dis.c: Regenerate. - * openrisc-asm.c: Regenerate. - * openrisc-desc.c: Regenerate. - * openrisc-dis.c: Regenerate. - * xstormy16-asm.c: Regenerate. - * xstormy16-desc.c: Regenerate. - * xstormy16-dis.c: Regenerate. - -2002-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (is_newabi): EABI is not a NewABI. - -2002-05-13 Jason Thorpe <thorpej@wasabisystems.com> - - * configure.in (shle-*-*elf*): Include sh64 support. - * configure: Regenerate. - -2002-04-28 Jason Thorpe <thorpej@wasabisystems.com> - - * vax-dis.c (print_insn_arg): Pass the insn info to print_insn_mode. - (print_insn_mode): Print some basic info about floating point values. - -2002-05-09 Anton Blanchard <anton@samba.org> - - * ppc-opc.c: Add "tlbiel" for POWER4. - -2002-05-07 Graydon Hoare <graydon@redhat.com> - - * cgen-dis.in: (print_insn_@arch@): Cache list of opened CPUs rather - than just most-recently-opened. - -2002-05-01 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c: Add "tlbsx." and "tlbsxe." for booke. - -2002-04-24 Christian Groessler <chris@groessler.org> - - * z8k-dis.c (print_insn_z8k): Set disassemble_info to 2 - bytes_per_chunk, 6 bytes_per_line for nicer display of the hex - codes. - (z8k_lookup_instr): CLASS_IGNORE case added. - (output_instr): Don't print hex codes, they are already - printed. - (unpack_instr): ARG_NIM4 case added. ARG_NIM8 case - fixed. Support CLASS_BIT_1OR2 and CLASS_IGNORE cases. - (unparse_instr): Fix base and indexed addressing disassembly: - The index is inside the brackets. - * z8kgen.c (gas): Add ARG_NIM4 and CLASS_IGNORE defines. - (opt): Fix shift left/right arithmetic/logical byte defines: - The high byte of the immediate word is ignored by the - processor. - Fix n parameter of ldm opcodes: The opcode contains (n-1). - (args): Fix "n" entry. - (toks): Add "nim4" and "iiii" entries. - * z8k-opc.h: Regenerated with new z8kgen.c. - -2002-04-24 Nick Clifton <nickc@cambridge.redhat.com> - - * po/id.po: New Indonesian translation. - * configure.in (ALL_LIGUAS): Add id.po - * configure: Regenerate. - -2002-04-17 matthew green <mrg@redhat.com> - - * ppc-opc.c (powerpc_opcode): Fix dssall operand list. - -2002-04-04 Alan Modra <amodra@bigpond.net.au> - - * dep-in.sed: Cope with absolute paths. - * Makefile.am (dep.sed): Subst TOPDIR. - Run "make dep-am". - * Makefile.in: Regenerate. - * ppc-opc.c: Whitespace. - * s390-dis.c: Fix copyright date. - -2002-03-23 matthew green <mrg@redhat.com> - - * ppc-opc.c (vmaddfp): Fix operand order. - -2002-03-21 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - -2002-03-21 Anton Blanchard <anton@samba.org> - - * ppc-opc.c: Add optional field to mtmsrd. - (MTMSRD_L, XRLARB_MASK): Define. - -2002-03-18 Jan Hubicka <jh@suse.cz> - - * i386-dis.c (prefix_name): Fix handling of 32bit address prefix - in 64bit mode. - (print_insn) Likewise. - (putop): Fix handling of 'E' - (OP_E, OP_OFF): handle 32bit addressing mode in 64bit. - (ptr_reg): Likewise. - -2002-03-18 Nick Clifton <nickc@cambridge.redhat.com> - - * po/fr.po: Updated version. - -2002-03-16 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (M3D): Tweak comment. - (mips_builtin_op): Add comment indicating that opcodes of the - same name must be placed together in the table, and sort - the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt", - "rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name. - -2002-03-16 Nick Clifton <nickc@cambridge.redhat.com> - - * Makefile.am: Tidy up sh64 rules. - * Makefile.in: Regenerate. - -2002-03-15 Chris G. Demetriou <cgd@broadcom.com> - - * mips-dis.c: Update copyright years. - -2002-03-15 Chris G. Demetriou <cgd@broadcom.com> - - * mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA - bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add - comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that - indicate that they should dissassemble all applicable - MIPS-specified ASEs. - * mips-opc.c: Add support for MIPS-3D instructions. - (M3D): New definition. - - * mips-opc.c: Update copyright years. - -2002-03-15 Chris G. Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Sort bc<N> opcodes by name. - -2002-03-15 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (is_newabi): Fix ABI decoding. - -2002-03-14 Chris G. Demetriou <cgd@broadcom.com> - - * mips-dis.c (mips_isa_type): Fix formatting of bfd_mach_mipsisa32 - and bfd_mach_mipsisa64 cases to match the rest. - -2002-03-13 Nick Clifton <nickc@cambridge.redhat.com> - - * po/fr.po: Updated version. - -2002-03-13 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c: Add optional `L' field to tlbie. - (XRTLRA_MASK): Define. - -2002-03-06 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Mark "pref" as being - present on I4. - - * mips-opc.c (mips_builtin_opcodes): Add "movn.ps" and "movz.ps". - -2002-03-05 Paul Koning <pkoning@equallogic.com> - - * pdp11-opc.c: Fix "mark" operand type. Fix operand types - for float opcodes that take float operands. Add alternate - names (xxxD vs. xxxF) for float opcodes. - * pdp11-dis.c (print_operand): Clean up formatting for mode 67. - (print_foperand): New function to handle float opcode operands. - (print_insn_pdp11): Use print_foperand to disassemble float ops. - -2002-02-27 Nick Clifton <nickc@cambridge.redhat.com> - - * po/de.po: Updated. - -2002-02-26 Brian Gaeke <brg@dgate.org> - - * Makefile.am (install-data-local): Install dis-asm.h. - -2002-02-26 Nick Clifton <nickc@cambridge.redhat.com> - - * configure.in (LINGUAS): Add de.po. - * configure: Regenerate. - * po/de.po: New file. - -2002-02-25 Alan Modra <amodra@bigpond.net.au> - - * ppc-dis.c (powerpc_dialect): Handle power4 option. - * ppc-opc.c (insert_bdm): Correct description of "at" branch - hints. Test PPC_OPCODE_POWER4 to determine branch hint flavour. - (extract_bdm, insert_bdp, extract_bdp, valid_bo): Likewise. - (BOFM64, BOFP64, BOTM64, BOFP64): Rename to BOFM4, BOFP4 etc. - (BODNZM64, BODNZP64, BODZM64, BODZP64): Likewise. - (PPCCOM32, PPCCOM64): Delete. - (NOPOWER4, POWER4): Define. - (powerpc_opcodes): Replace occurences of PPCCOM32 with NOPOWER4, - and PPCCOM4 with POWER4 so that "at" style branch hint opcodes - are enabled for power4 rather than ppc64. - -2002-02-20 Tom Rix <trix@redhat.com> - - * ppc-opc.c (powerpc_operands): Add WS field. Use for tlbre, tlbwe. - -2002-02-19 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-dis.c (init_disasm): Use renamed architecture defines. - -2002-02-19 matthew green <mrg@redhat.com> - - * ppc-opc.c (powerpc_dialect): Fix comment; BookE is not Motorola - specific. - -2002-02-18 Nick Clifton <nickc@cambridge.redhat.com> - - * po/tr.po: Updated translation. - -2002-02-15 Richard Henderson <rth@redhat.com> - - * alpha-opc.c (alpha_opcodes): Fix thinko in ret pseudo - disassembly mask. - -2002-02-15 Richard Henderson <rth@redhat.com> - - * alpha-opc.c (alpha_opcodes): Add simple pseudos for - lda, ldah, jmp, ret. - -2002-02-14 Nick Clifton <nickc@cambridge.redhat.com> - - * po/da.po: Updated translation. - -2002-02-12 Graydon Hoare <graydon@redhat.com> - - * cgen-asm.in (parse_insn_normal): Change call from - @arch@_cgen_parse_operand to cd->parse_operand, to - facilitate CGEN_ASM_INIT_HOOK doing useful work. - -2002-02-11 Alexandre Oliva <aoliva@redhat.com> - - * sparc-dis.c (print_insn_sparc): Make sure 0xFFFFFFFF is not - sign-extended. - -2002-02-11 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: "make dep-am". - * Makefile.in: Regenerate. - * aclocal.m4: Regenerate. - * config.in: Regenerate. - * configure: Regenerate. - -2002-02-10 Hans-Peter Nilsson <hp@bitrange.com> - - * configure.in <bfd_sh_arc>: For sh-* and shl-*, enable sh64 - support only for sh-*-*elf*, shl-*-*elf*, sh-*-linux* and - shl-*-linux*. - * configure: Regenerate. - -2002-02-10 Daniel Jacobowitz <drow@mvista.com> - - * cgen-dis.c: Add prototypes for count_decodable_bits - and add_insn_to_hash_chain. - -2002-02-08 Alexandre Oliva <aoliva@redhat.com> - - * configure.in <bfd_sh_arc>: Enable sh64 support on sh-*. - * configure: Rebuilt. - -2002-02-08 Ivan Guzvinec <ivang@opencores.org> - - * or32-opc.c: Fix compile time warning messages. - * or32-dis.c: Fix compile time warning messages. - -2002-02-08 Alexandre Oliva <aoliva@redhat.com> - - Contribute sh64-elf. - 2001-10-08 Nick Clifton <nickc@cambridge.redhat.com> - * sh64-opc.c: Regenerate. - 2001-03-13 DJ Delorie <dj@redhat.com> - * sh64-opc.h: Rename A_RESV_Fx to A_REUSE_PREV so that its - purpose is more obvious. - * sh64-opc.c (shmedia_table): Ditto. - * sh64-dis.c (initialize_shmedia_opcode_mask_table): Ditto. - (print_insn_shmedia): Ditto. - 2001-03-12 DJ Delorie <dj@redhat.com> - * sh64-opc.c: Adjust comments to reflect reality: replace bits - 3:0 with zeros (not "reserved"), replace "rrrrrr" with - "gggggg" for two-operand floating point opcodes. Remove - "fsina". - 2001-01-08 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-dis.c (print_insn_shmedia) <failing read_memory_func>: - Correct printing of .byte:s. Return number of printed bytes or - -1; never 0. - (print_insn_sh64x) <not CRT_SH5_ISA16>: Ditto. Print as .byte:s - to next four-byte-alignment if insn or data is not aligned. - 2001-01-06 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-dis.c: Update comments and fix comment formatting. - (initialize_shmedia_opcode_mask_table) <case A_IMMM>: - Abort instead of setting length to 0. - (crange_qsort_cmpb, crange_qsort_cmpl, crange_bsearch_cmpb, - crange_bsearch_cmpl, sh64_get_contents_type, - sh64_address_in_cranges): Move to bfd/elf32-sh64.c. - 2001-01-05 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-opc.c: Remove #if 0:d entries for instructions not found in - SH-5/ST50-023-04: fcosa.s, fsrra.s and prefo. - 2000-12-30 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-dis.c (print_insn_shmedia): Display MOVI/SHORI-formed - address with same prefix as SHcompact. - In the disassembler, use a .cranges section for linked executables. - * sh64-dis.c (SAVED_MOVI_R, SAVED_MOVI_IMM): Move to head of file - and update for using structure in info->private_data. - (struct sh64_disassemble_info): New. - (is_shmedia_p): Delete. - (crange_qsort_cmpb): New function. - (crange_qsort_cmpl, crange_bsearch_cmpb): New functions. - (crange_bsearch_cmpl, sh64_address_in_cranges): New functions. - (init_sh64_disasm_info, sh64_get_contents_type_disasm): New functions. - (sh64_get_contents_type, sh64_address_is_shmedia): New functions. - (print_insn_shmedia): Correct displaying of address after MOVI/SHORI - pair. Display addresses for linked executables only. - (print_insn_sh64x_media): Initialize info->private_data by calling - init_sh64_disasm_info. - (print_insn_sh64x): Ditto. Find out type of contents by calling - sh64_contents_type_disasm. Display data regions using ".long" and - ".byte" similar to unrecognized opcodes. - 2000-12-19 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-dis.c (is_shmedia_p): Check info->section and look for ISA - information in section flags before considering symbols. Don't - assume an info->mach setting of bfd_mach_sh5 means SHmedia code. - * configure.in (bfd_sh_arch): Check presence of sh64 insns by - matching $target $canon_targets instead of looking at the - now-removed -DINCLUDE_SHMEDIA in $targ_cflags. - * configure: Regenerate. - 2000-11-25 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-opc.c (shmedia_creg_table): New. - * sh64-opc.h (shmedia_creg_info): New type. - (shmedia_creg_table): Declare. - * sh64-dis.c (creg_name): New function. - (print_insn_shmedia): Use it. - * disassemble.c (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map - bfd_mach_sh5 to print_insn_sh64 if big-endian and to - print_insn_sh64l if little-endian. - * sh64-dis.c (print_insn_shmedia): Make r unsigned. - (print_insn_sh64l): New. - (print_insn_sh64x): New. - (print_insn_sh64x_media): New. - (print_insn_sh64): Break out code to print_insn_sh64x and - print_insn_sh64x_media. - 2000-11-24 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-opc.h: New file - * sh64-opc.c: New file - * sh64-dis.c: New file - * Makefile.am: Add sh64 targets. - (HFILES): Add sh64-opc.h. - (CFILES): Add sh64-opc.c and sh64-dis.c. - (ALL_MACHINES): Add sh64 files. - * Makefile.in: Regenerate. - * configure.in: Add support for sh64 to bfd_sh_arch. - * configure: Regenerate. - * disassemble.c [ARCH_all] (INCLUDE_SHMEDIA): Define. - (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map bfd_mach_sh5 to - print_insn_sh64. - * sh-dis.c (print_insn_shx): Handle bfd_mach_sh5 as arch_sh4. - * po/POTFILES.in: Regenerate. - * po/opcodes.pot: Regenerate. - -2002-02-04 Frank Ch. Eigler <fche@redhat.com> - - * cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets. - -2002-02-04 Alexandre Oliva <aoliva@redhat.com> - - * sh-opc.h (sh_arg_type): Added A_DISP_PC_ABS. - -2002-02-01 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am" - * Makefile.in: Regenerate. - -2002-01-31 Ivan Guzvinec <ivang@opencores.org> - - * or32-dis.c: New file. - * or32-opc.c: New file. - * configure.in: Add support for or32. - * configure: Regenerate. - * Makefile.am: Add support for or32. - * Makefile.in: Regenerate. - * disassemble.c: Add support for or32. - * po/POTFILES.in: Regenerate. - * po/opcodes.pot: Regenerate. - -2002-01-27 Daniel Jacobowitz <drow@mvista.com> - - * configure: Regenerated. - -2002-01-26 Nick Clifton <nickc@cambridge.redhat.com> - - * po/fr.po: Updated version. - -2002-01-25 Nick Clifton <nickc@cambridge.redhat.com> - - * po/es.po: Updated version. - -2002-01-24 Nick Clifton <nickc@cambridge.redhat.com> - - * po/da.po: New version. - -2002-01-23 Nick Clifton <nickc@cambridge.redhat.com> - - * po/da.po: New file: Spanish translation. - * configure.in (ALL_LINGUAS): Add da. - * configure: Regenerate. - -2002-01-22 Graydon Hoare <graydon@redhat.com> - - * fr30-asm.c: Regenerate. - * fr30-desc.c: Likewise. - * fr30-desc.h: Likewise. - * fr30-dis.c: Likewise. - * fr30-ibld.c: Likewise. - * fr30-opc.c: Likewise. - * fr30-opc.h: Likewise. - * m32r-asm.c: Likewise. - * m32r-desc.c: Likewise. - * m32r-desc.h: Likewise. - * m32r-dis.c: Likewise. - * m32r-ibld.c: Likewise. - * m32r-opc.c: Likewise. - * m32r-opc.h: Likewise. - * m32r-opinst.c: Likewise. - * openrisc-asm.c: Likewise. - * openrisc-desc.c: Likewise. - * openrisc-desc.h: Likewise. - * openrisc-dis.c: Likewise. - * openrisc-ibld.c: Likewise. - * openrisc-opc.c: Likewise. - * openrisc-opc.h: Likewise. - * xstormy16-desc.c: Likewise. - -2002-01-22 Richard Henderson <rth@redhat.com> - - * alpha-dis.c (print_insn_alpha): Also mask the base opcode for - comparison. - -2002-01-22 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - -2002-01-19 Richard Earnshaw <rearnsha@arm.com> - - * arm-opc.h (arm_opcodes): Use generic rule %5?hb instead of %h. - * arm-dis.c (print_insn_arm): Don't handle 'h' case. - -2002-01-18 Keith Walker <keith.walker@arm.com> - - * arm-opc.h (arm_opcodes): Add bxj instruction. - -2002-01-17 Nick Clifton <nickc@cambridge.redhat.com> - - * po/opcodes.pot: Regenerate. - * po/fr.po: Regenerate. - * po/sv.po: Regenerate. - * po/tr.po: Regenerate. - -2002-01-16 Nick Clifton <nickc@cambridge.redhat.com> - - * po/tr.po: Import new version. - -2002-01-15 Richard Earnshaw <rearnsha@arm.com> - - * arm-opc.h (arm_opcodes): Add patterns for VFP instructions. - * arm-dis.c (print_insn_arm): Support new disassembly qualifiers for - VFP bitfields. - -2002-01-10 matthew green <mrg@redhat.com> - - * xstormy16-asm.c: Regenerate. - * xstormy16-desc.c: Likewise. - * xstormy16-desc.h: Likewise. - * xstormy16-dis.c: Likewise. - * xstormy16-opc.c: Likewise. - * xstormy16-opc.h: Likewise. - -2002-01-07 Nick Clifton <nickc@cambridge.redhat.com> - - * po/es.po: New file: Spanish translation. - * configure.in (ALL_LINGUAS): Add es. - * configure: Regenerate. - -For older changes see ChangeLog-0001 - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/contrib/binutils/opcodes/ChangeLog-9297 b/contrib/binutils/opcodes/ChangeLog-9297 deleted file mode 100644 index 799457e..0000000 --- a/contrib/binutils/opcodes/ChangeLog-9297 +++ /dev/null @@ -1,3797 +0,0 @@ -Mon Dec 22 12:37:06 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add FP_D to s.d instruction flags. - -Wed Dec 17 11:38:29 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (halt, pulse): Enable them on the 68060. - -Tue Dec 16 15:22:53 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit - PC relative offset forms before the 15 bit forms. An assembler command - line option now chooses the default. - -Tue Dec 16 15:22:51 1997 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Set new flags bits - FLAG_{2WORD,MUL{16,32},ADDSUBppp}, in appropriate instructions. - -1997-12-15 Brendan Kehoe <brendan@lisa.cygnus.com> - - * configure: Only build libopcodes shared if --enable-shared's value - was `yes', or was set to `*opcodes*'. - * aclocal.m4: Likewise. - * NOTE: this really needs to be fixed in libtool/libtool.m4, the - original source of this bit of code. It's not clear what the best fix - would be, though. - -Fri Dec 12 11:57:04 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change. - (tic80_opcodes): Reorder table entries to put the 32 bit PC relative - offset forms before the 15 bit forms, to default to the long forms. - -Fri Dec 12 01:32:30 1997 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid. - -Wed Dec 10 17:42:35 1997 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_little_arm): Prevent examination of stored - symbol if none is present. - (print_insn_big_arm): Prevent examination of stored symbol if - none is present. - -Thu Oct 23 21:13:37 1997 Fred Fish <fnf@cygnus.com> - - * d10v-opc.c (d10v_opcodes): Correct entry for RTE. - -Mon Dec 8 11:21:07 1997 Nick Clifton <nickc@cygnus.com> - - * disassemble.c: Remove disasm_symaddr() function. - - * arm-dis.c: Use info->symbol instead of info->flags to determine - if disassmbly should be in Thumb or Arm mode. - -Tue Dec 2 09:54:27 1997 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c: Add support for disassembling Thumb opcodes. - (print_insn_thumb): New function. - - * disassemble.c (disasm_symaddr): New function. - - * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly. - (thumb_opcodes): Table of Thumb opcodes. - -Mon Dec 1 12:25:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (btst): Change Dd@s to Dd;b. - - * m68k-dis.c (print_insn_arg): Recognize 'm', 'n', 'o', 'p', 'q', - and 'v' as operand types. - -Mon Dec 1 11:56:50 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Add argument for lpstop. From Olivier Carmona - <olivier.carmona@di.epfl.ch>. - * m68k-dis.c (print_insn_m68k): Handle special case of lpstop, - which has a two word opcode with a one word argument. - -Sun Nov 23 22:25:21 1997 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is - unsigned, not signed. - (d30v_format_table): Add SHORT_CMPU cases for cmpu. - -Tue Nov 18 23:10:03 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d10v-dis.c (print_operand): - Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG. - -Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d10v-opc.c (OPERAND_FLAG): Split into: - (OPERAND_FFLAG, OPERAND_CFLAG) . - (FSRC): Split into: - (FFSRC, CFSRC). - -Thu Nov 13 11:05:33 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Move the INSN_MACRO ISA value to the membership - field for all INSN_MACRO's. - * mips16-opc.c: same - -Wed Nov 12 10:16:57 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (sync,cache): These are 3900 insns. - -Tue Nov 11 23:53:41 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - sh-opc.h (sh_table): Remove ftst/nan. - -Tue Oct 28 17:59:32 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c (ffc, ffs): Fix mask. - -Tue Oct 28 16:34:54 1997 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m - control registers. - -Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. - (WR_HILO, RD_HILO, MOD_HILO): New macros. - -Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips-opc.c: Fix bug in mask for "not" pseudo-instruction. - (WR_HILO, RD_HILO, MOD_HILO): New macros. - -Thu Oct 23 14:57:58 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Replace // with /* ... */ - -Wed Oct 22 17:33:21 1997 Richard Henderson <rth@cygnus.com> - - * sparc-opc.c: Add wr & rd for v9a asr's. - * sparc-dis.c (print_insn_sparc): Recognize '_' and '/' for v9a asr's. - (v9a_asr_reg_names): New variable. - Patch from David Miller <davem@vger.rutgers.edu>. - -Wed Oct 22 17:18:02 1997 Richard Henderson <rth@cygnus.com> - - * sparc-opc.c (v9notv9a): New insn type. - (IMPDEP): Move to the end to not conflict with edge8 et al. - Patch from David Miller <davem@vger.rutgers.edu>. - -Fri Oct 17 13:18:53 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (bnezl,beqzl): Mark these as also tx39. - -Thu Oct 16 11:55:20 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1. - -Tue Oct 14 16:10:31 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Use new symbol_at_address_func() field - of disassemble_info structure to determine if an overlay address - has a matching symbol in low memory. - - * dis-buf.c (generic_symbol_at_address): New (dummy) function for - new symbol_at_address_func field in disassemble_info structure. - -Fri Oct 10 16:44:52 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (extract_d22): Use signed arithmatic. - -Tue Oct 7 23:40:43 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Three op mult is not an ISA insn. - -Tue Oct 7 23:37:21 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Fix formatting. - -Fri Oct 3 17:26:54 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (OP_E): Explicitly sign extend 8 bit values, rather - than assuming that char is signed. Explicitly sign extend 16 bit - values, rather than assuming that short is 16 bits. - (OP_sI, OP_J, OP_DIR): Likewise. - -Thu Oct 2 13:36:45 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (v850_sreg_names): Use symbolic names for higher - system registers. - -Wed Oct 1 16:58:54 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c: Fix typo in comment. - - * v850-dis.c (disassemble): Add test of processor type when - determining opcodes. - -Wed Oct 1 14:10:20 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Use a diversion to set enable_shared before the - arguments are parsed. - * configure: Rebuild. - -Thu Sep 25 13:04:59 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (TBL1): Use ! rather than `. - * m68k-dis.c (print_insn_arg): Remove ` operand specifier. - -Wed Sep 24 11:29:35 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire. - - * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32. - - * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr - for mcf5200. - - * configure.in: Call AC_CHECK_TOOL before AM_PROG_LIBTOOL. - * aclocal.m4: Rebuild with new libtool. - * configure: Rebuild. - -Fri Sep 19 11:45:49 1997 Andrew Cagney <cagney@b1.cygnus.com> - - * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2. - -Thu Sep 18 11:21:43 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr. - -Tue Sep 16 15:18:20 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes): Further rearrangements. - -Tue Sep 16 16:12:11 1997 Ken Raeburn <raeburn@cygnus.com> - - * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change. - -Tue Sep 16 09:48:50 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes): Fields reordered to allow assembler - parser to work. - -Tue Sep 16 10:01:00 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret. - -Mon Sep 15 18:31:52 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c: Initialise processors field of v850_opcode structure. - -Wed Aug 27 21:42:39 1997 Ken Raeburn <raeburn@cygnus.com> - - Merge changes from Martin Hunt: - - * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values. - - * d30v-opc.c (pre_defined_registers): Add control registers from 0-63. - (d30v_opcode_tabel): Add dbt, rtd, srah, and srlh instructions. Fix - rot2h, sra2h, and srl2h to use new SHORT_A5S format. - - * d30v-dis.c (print_insn): Fix disassembly of SHORT_D2 opcodes. - - * d30v-dis.c (print_insn): First operand of d*i (delayed - branch) instructions is relative. - - * d30v-opc.c (d30v_opcode_table): Change form for repeati. - (d30v_operand_table): Add IMM6S3 type. - (d30v_format_table): Change SHORT_D2. Add LONG_Db. - - * d30v-dis.c: Fix bug with ".s" and ".l" extensions - and cmp instructions. - - * d30v-opc.c: Correct entries for repeat*, and sat*. - Make IMM5 unsigned. Create IMM6U and IMM12S3U operand - types. Correct several formats. - - * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc. - - * d30v-opc.c (pre_defined_registers): Change control registers. - - * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and - SHORT_C2. Manual was incorrect. - - * d30v-dis.c (lookup_opcode): Return value now indicates - if an opcode has a short and a long form. Used for deciding - to append a ".s" or ".l". - (print_insn): Append a ".s" to an instruction if it is - the short form and ".l" if it is a long form. Do not append - anything if the instruction has only one possible size. - - * d30v-opc.c: Change mulx2h to require an even register. - New form: SHORT_A2; a SHORT_A form that needs an even - register as the first operand. - - * d30v-dis.c (print_insn_d30v): Fix problem where the last - instruction was not being disassembled if there were an odd - number of instructions. - - * d30v-opc.c (SHORT_M2, LONG_M2): Two new forms. - -Fri Sep 12 11:43:54 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Improved display of register lists. - -Thu Sep 11 17:35:10 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Fix assembler args to - fzeros, fones, fsrc1, fsrc1s, fsrc2s, fnot1, fnot1s, fnot2s, - fors, fnors, fands, fnands, fxors, fxnors, fornot1s, fornot2s, - fandnot1s, fandnot2s. - -Tue Sep 9 10:03:49 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq. - -Mon Sep 8 14:06:59 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-asm.c (cgen_parse_address): New argument resultp. - All callers updated. - * m32r-asm.c (parse_h_hi16): Right shift numbers by 16. - -Tue Sep 2 18:39:08 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-dis.c (disassemble): PC relative instructions are - relative to the next instruction, not the current instruction. - -Tue Sep 2 15:41:55 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Only signed extend values that are not - returned by extract functions. - Remove use of V850_OPERAND_ADJUST_SHORT_MEMORY flag. - -Tue Sep 2 15:39:40 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c: Update comments. Remove use of - V850_OPERAND_ADJUST_SHORT_MEMORY. Fix several operand patterns. - -Tue Aug 26 09:42:28 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (MOVHI): Immediate parameter is unsigned. - -Mon Aug 25 15:58:07 1997 Christopher Provenzano <proven@cygnus.com> - - * configure: Rebuilt with latest devo autoconf for NT support. - -Fri Aug 22 10:35:15 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Use curly brace syntax for register - lists. - - * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases - where r0 is being used as a destination register. - -Thu Aug 21 11:09:09 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other. - -Tue Aug 19 10:59:59 1997 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage. - -Mon Aug 18 11:10:03 1997 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (v850_opcodes[]): Remove use of flag field. - * v850-opc.c (v850_opcodes[]): Add support for reversed short load - opcodes.. - -Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com> - - * configure (cgen_files): Add support for v850e target. - * configure.in (cgen_files): Add support for v850e target. - -Mon Aug 18 11:08:25 1997 Nick Clifton <nickc@cygnus.com> - - * configure (cgen_files): Add support for v850ea target. - * configure.in (cgen_files): Add support for v850ea target. - -Fri Aug 15 05:17:48 1997 Doug Evans <dje@canuck.cygnus.com> - - * configure.in (bfd_arc_arch): Add. - * configure: Rebuild. - * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo. - * Makefile.in: Rebuild. - * arc-dis.c, arc-opc.c: New files. - * disassemble.c (ARCH_all): Define ARCH_arc. - (disassembler): Add ARC support. - -Wed Aug 13 18:52:11 1997 Nick Clifton <nickc@cygnus.com> - - * v850-dis.c (disassemble): Add support for v850EA instructions. - - * v850-opc.c (insert_i5div, extract_i5div): New Functions. - (v850_opcodes): Add v850EA instructions. - - * v850-dis.c (disassemble): Add support for v850E instructions. - - * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16, - extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9, - insert_spe, extract_spe): New Functions. - (v850_opcodes): Add v850E instructions. - - * v850-opc.c: Reorganised and re-layed out to improve readability - and portability. - -Tue Aug 5 23:09:31 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.12.1. - -Mon Aug 4 12:02:16 1997 Ian Lance Taylor <ian@cygnus.com> - - * aclocal.m4, configure: Rebuild with new automake patches. - -Fri Aug 1 13:02:04 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Set enable_shared before AM_PROG_LIBTOOL. - * acinclude.m4: Just include acinclude.m4 from BFD. - * aclocal.m4, configure: Rebuild. - -Thu Jul 31 21:44:42 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am: New file, based on old Makefile.in. - * acconfig.h: New file. - * acinclude.m4: New file. - * stamp-h.in: New file. - * configure.in: Call AM_INIT_AUTOMAKE and AM_PROG_LIBTOOL. - Removed shared library handling; now handled by libtool. Replace - AC_CONFIG_HEADER with AM_CONFIG_HEADER. Call AM_MAINTAINER_MODE, - AM_CYGWIN32, and AM_EXEEXT. Replace AC_PROG_INSTALL with - AM_PROG_INSTALL. Change all .o files to .lo. Remove stamp-h - handling in AC_OUTPUT. - * dep-in.sed: Change .o to .lo. - * Makefile.in: Now built with automake. - * aclocal.m4: Now built with aclocal. - * config.in, configure: Rebuild. - -Mon Jul 28 21:52:24 1997 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c: Fix typo/thinko in "eret" instruction. - -Thu Jul 24 13:03:26 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns. - Make array const. - * sparc-dis.c (sorted_opcodes): New static local. - (struct opcode_hash): `opcode' is pointer to const element. - (build_hash): First arg is now table of sorted pointers. - (print_insn_sparc): Sort opcodes by sorting table of pointers. - (compare_opcodes): Update. - -Tue Jul 15 12:05:23 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-opc.c: #include <ctype.h>. - (hash_keyword_name): New arg `case_sensitive_p'. Callers updated. - Handle case insensitive hashing. - (hash_keyword_value): Change type of `value' to unsigned int. - -Thu Jul 10 12:56:10 1997 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c (mips_builtin_opcodes): If an insn uses single - precision FP, mark it as such. Likewise for double precision - FP. Mark ISA1 insns. Consolidate duplicate opcodes where - possible. - -Wed Jun 25 15:25:57 1997 Felix Lee <flee@cirdan.cygnus.com> - - * ppc-opc.c (extract_nsi): make unsigned expression signed before - negating it. - (UNUSED): remove one level of parens, so MSVC doesn't choke on - nesting depth when all the macros are expanded. - -Tue Jun 17 17:02:17 1997 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: The fcmp v9a instructions take an integer register - as a destination, not a floating point register. From Christian - Kuehnke <Christian.Kuehnke@arbi.Informatik.Uni-Oldenburg.DE>. - -Mon Jun 16 14:13:18 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-dis.c (print_insn_arg): Print case 7.2 using %pc@() - syntax. From Roman Hodek - <rnhodek@faui22c.informatik.uni-erlangen.de>. - - * i386-dis.c (twobyte_has_modrm): Fix pand. - -Mon Jun 16 14:08:38 1997 Michael Taylor <mbt@mit.edu> - - * i386-dis.c (dis386_twobyte): Fix pand and pandn. - -Tue Jun 10 11:26:47 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * arm-dis.c: Add prototypes for arm_decode_shift and - print_insn_arm. - -Mon Jun 2 11:39:04 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c: Add r3900 insns. - -Tue May 27 15:55:44 1997 Ian Lance Taylor <ian@cygnus.com> - - * sh-dis.c (print_insn_shx): Change relmask to bfd_vma. Don't - print delay slot instructions on the same line. When using a PC - relative load, add a comment with the value being loaded if it can - be obtained. - -Tue May 27 11:02:08 1997 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl - to pushS/popS for segment regs and byte constant so that - pushw/popw printed when in 16 bit data mode. - - * i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to - print cbtw, cwtd in 16 bit data mode. - * i386-dis.c (putop): extra case W to support above. - - * i386-dis.c (print_insn_x86): print addr32 prefix when given - address size prefix in 16 bit address mode. - -Fri May 23 16:47:23 1997 Ian Lance Taylor <ian@cygnus.com> - - * sh-dis.c: Reindent. Rename local variable fprintf to - fprintf_fn. - -Thu May 22 14:06:02 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2. - -Tue May 20 11:26:27 1997 Gavin Koch <gavin@cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new - field membership. - * mips16-opc.c (mip16_opcodes): same. - -Mon May 12 15:10:53 1997 Jim Wilson <wilson@cygnus.com> - - * m68k-opc.c (moveb): Change $d to %d. - -Mon May 5 14:28:41 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c: (dis386_twobyte): Add MMX instructions. - (twobyte_has_modrm): Likewise. - (grps): Likewise. - (OP_MMX, OP_EM, OP_MS): New static functions. - - * i386-dis.c: Revert patch of April 4. The output now matches - what gcc generates. - -Fri May 2 12:48:37 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead - of $simm16. - -Thu May 1 15:34:15 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU. - -Tue Apr 15 12:40:08 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (install): Depend upon installdirs. - (installdirs): New target. - -Mon Apr 14 12:13:51 1997 Ian Lance Taylor <ian@cygnus.com> - - From Thomas Graichen <graichen@rzpd.de>: - * configure.in: Use ${CONFIG_SHELL} when running $ac_config_sub. - * configure: Rebuild. - -Sun Apr 13 17:50:41 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-*.c, m32r-*.c: #include sysdep.h instead of config.h. - Delete string{,s}.h support. - -Thu Apr 10 14:44:56 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-asm.c (cgen_parse_operand_fn): New global. - (cgen_parse_{{,un}signed_integer,address}): Update call to - cgen_parse_operand_fn. - (cgen_init_parse_operand): New function. - * m32r-asm.c (parse_insn_normal): cgen_init_parse_operand renamed - from cgen_asm_init_parse. - (m32r_cgen_assemble_insn): New operand `errmsg'. - Delete call to as_bad, return error message to caller. - (m32r_cgen_asm_hash_keywords): #if 0 out. - -Wed Apr 9 12:05:25 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_arg) [case 'd']: Print as address register, - not data register. - [case 'J']: Fix typo in register name. - -Mon Apr 7 16:48:22 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Substitute SHLIB_LIBS. - * configure: Rebuild. - * Makefile.in (SHLIB_LIBS): New variable. - ($(SHLIB)): Use $(SHLIB_LIBS). - -Mon Apr 7 11:45:44 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen-dis.c (build_dis_hash_table): Fix xmalloc size computation. - - * cgen-opc.c (hash_keyword_name): Improve algorithm. - - * disassemble.c (disassembler): Handle m32r. - -Fri Apr 4 12:29:38 1997 Doug Evans <dje@canuck.cygnus.com> - - * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files. - * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files. - * Makefile.in (CFILES): Add them. - (ALL_MACHINES): Add them. - (dependencies): Regenerate. - * configure.in (cgen_files): New variable. - (bfd_m32r_arch): Add entry. - * configure: Regenerate. - -Fri Apr 4 14:04:16 1997 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Correct file names for bfd_mn10[23]00_arch. - * configure: Rebuild. - - * Makefile.in: Rebuild dependencies. - - * d10v-dis.c: Include "ansidecl.h" before "opcode/d10v.h". - - * i386-dis.c (float_reg): Swap fsubrp and fsubp. Swap fdivrp and - fdivp. - -Thu Apr 3 13:22:45 1997 Ian Lance Taylor <ian@cygnus.com> - - * Branched binutils 2.8. - -Wed Apr 2 12:23:53 1997 Ian Lance Taylor <ian@cygnus.com> - - * m10200-dis.c: Rename from mn10200-dis.c. - * m10200-opc.c: Rename from mn10200-opc.c. - * m10300-dis.c: Rename from mn10300-dis.c - * m10300-opc.c: Rename from mn10300-opc.c. - * Makefile.in: Update accordingly. - - * mips16-opc.c: Add mul and dmul macros. - -Tue Apr 1 16:27:45 1997 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Update CFLAGS, add clean target. - -Fri Mar 28 12:10:09 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add "wait". From Ralf Baechle - <ralf@gnu.ai.mit.edu>. - - * configure.in: Add stdlib.h to AC_CHECK_HEADERS list. - * configure, config.in: Rebuild. - * sysdep.h: Include <stdlib.h> if it exists. - * sparc-dis.c: Include <stdio.h> and "sysdep.h". Don't include - <string.h>. - * Makefile.in: Rebuild dependencies. - -Thu Mar 27 14:24:43 1997 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c: Add PPC 403 instructions and extended opcodes. From - Andrew Bray <andy@madhouse.demon.co.uk>. - - * mips-opc.c: Add cast when setting mips_opcodes. - -Tue Mar 25 23:04:00 1997 Stu Grossman (grossman@critters.cygnus.com) - - * v850-dis.c (disassemble): Fix sign extension problem. - * v850-opc.c (extract_d*): Fix sign extension problems to make - disassembly calculate branch offsets correctly. - -Mon Mar 24 13:22:13 1997 Ian Lance Taylor <ian@cygnus.com> - - * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s. - - * mips-opc.c: Add dctr and dctw. - -Sun Mar 23 18:08:10 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v-dis.c (print_insn): Change the way signed constants - are displayed. - -Fri Mar 21 14:37:52 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (BFD_H): New variable. - (HFILES): New variable. - (CFILES): Add all C files. - (.dep, .dep1, dep.sed, dep, dep-in): New targets. - Delete old dependencies, and build new ones. - * dep-in.sed: New file. - -Thu Mar 20 19:03:30 1997 Philippe De Muyter <phdm@info.ucl.ac.be> - - * m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}. - -Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c: Change "trap" to "syscall". - * mn10300-opc.c: Add new "syscall" instruction. - -Mon Mar 17 08:48:03 1997 J.T. Conklin <jtc@beauty.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and - mulul insns on the coldfire. - -Sat Mar 15 17:13:05 1997 Ian Lance Taylor <ian@cygnus.com> - - * arm-dis.c (print_insn_arm): Don't print instruction bytes. - (print_insn_big_arm): Set bytes_per_chunk and display_endian. - (print_insn_little_arm): Likewise. - -Fri Mar 14 15:08:59 1997 Ian Lance Taylor <ian@cygnus.com> - - Based on patches from H.J. Lu <hjl@lucon.org>: - * i386-dis.c (fetch_data): Add prototype. - * m68k-dis.c (fetch_data): Add prototype. - (dummy_print_address): Add prototype. Make static. - * ppc-opc.c (valid_bo): Add prototype. - * sparc-dis.c (build_hash_table): Add prototype. - (is_delayed_branch, compute_arch_mask): Add prototypes. - (print_insn_sparc): Make several local variables const. - (compare_opcodes): Change arguments to const PTR. Add prototype. - * sparc-opc.c (arg): Change name field to be const. - (lookup_name, lookup_value): Add prototypes. Change table and - name parameters to be const. - (sparc_encode_asi): Change name parameter to be const. - (sparc_encode_membar, sparc_encode_prefetch): Likewise. - (sparc_encode_sparclet_cpreg): Likewise. - (sparc_decode_asi): Change return type to be const. - (sparc_decode_membar, sparc_decode_prefetch): Likewise. - (sparc_decode_sparclet_cpreg): Likewise. - -Fri Mar 7 10:51:49 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in ($(SHLINK)): Just use ln -s, not ln -sf, since - Solaris doesn't like the combined options, and the -f is - unnecessary. - (stamp-tshlink, install): Likewise. - -Thu Mar 6 16:51:11 1997 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these - as relaxable. - -Tue Mar 4 06:10:36 1997 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010. - -Mon Mar 3 07:45:20 1997 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on - the mc68000. - -Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be> - - * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction. - -Thu Feb 27 11:36:41 1997 Michael Meissner <meissner@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8. - -Wed Feb 26 15:34:48 1997 Michael Meissner <meissner@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Define r25 properly. - -Wed Feb 26 13:38:30 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use - floatformat_to_double to make portable. - (print_insn_arg): Use NEXTEXTEND macro when extracting extended - precision float. - -Mon Feb 24 19:26:12 1997 Dawn Perchik <dawn@cygnus.com> - - * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes, - and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes. - -Mon Feb 24 15:19:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to - d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. - -Mon Feb 24 14:33:26 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (LSI_SCALED): Renamed from this ... - (OFF_SL_BR_SCALED): ... to this, and added the flag - TIC80_OPERAND_BASEREL to the flags word. - (tic80_opcodes): Replace all occurances of LSI_SCALED with - OFF_SL_BR_SCALED. - -Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com> - - * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. - Change mips_opcodes from const array to a pointer, - and change bfd_mips_num_opcodes from const int to int, - so that we can increase the size of the mips opcodes table - dynamically. - -Sat Feb 22 21:03:47 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Revert change to - store BITNUM values in the table in one's complement form - to match behavior when assembler is given a raw numeric - value for a BITNUM operand. - * tic80-dis.c (print_operand_bitnum): Ditto. - -Fri Feb 21 16:31:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v-opc.c: Removed references to FLAG_X. - -Wed Feb 19 14:51:20 1997 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in: Add dependencies on ../bfd/bfd.h as required. - -Tue Feb 18 17:43:43 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * Makefile.in: Added d30v object files. - * configure: (bfd_d30v_arch) Rebuilt. - * configure.in: (bfd_d30v_arch) Added new case. - * d30v-dis.c: New file. - * d30v-opc.c: New file. - * disassemble.c (disassembler) Add entry for d30v. - -Tue Feb 18 16:32:08 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Add symbolic - representations for the floating point BITNUM values. - -Fri Feb 14 12:14:05 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values - in the table in one's complement form, as they appear in the - actual instruction. - (tic80_symbol_to_value): Use macros to access predefined - symbol fields. - (tic80_value_to_symbol): Ditto. - (tic80_next_predefined_symbol): New function. - * tic80-dis.c (print_operand_bitnum): Remove code that did - one's complement for BITNUM values. - -Thu Feb 13 21:56:51 1997 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Remove 8 bit characters. Update to latest - gcc release. - -Thu Feb 13 20:41:22 1997 Philippe De Muyter <phdm@info.ucl.ac.be> - - * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction. - -Thu Feb 13 16:30:02 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (IMM16_PCREL): This is a signed operand. - (IMM24_PCREL): Likewise. - -Thu Feb 13 13:28:43 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base - address for an extended PC relative instruction that is not a - branch. - -Wed Feb 12 12:27:40 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and - bytes_per_line. - -Tue Feb 11 16:36:31 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'. - (tic80_opcodes): Sort entries so that long immediate forms - come after short immediate forms, making it easier for - assembler to select the right one for a given operand. - -Tue Feb 11 15:26:47 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and - display_endian. - (print_insn_mips16): Likewise. - -Mon Feb 10 10:12:41 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_symbol_to_value): Changed to accept - a symbol class that restricts translation to just that - class (general register, condition code, etc). - -Thu Feb 6 17:34:09 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E, - and REG_DEST_E for register operands that have to be - an even numbered register. Add REG_FPA for operands that - are one of the floating point accumulator registers. - Add TIC80_OPERAND_MASK to flags for ENDMASK operand. - (tic80_opcodes): Change entries that need even numbered - register operands to use the new operand table entries. - Add "or" entries that are identical to "or.tt" entries. - -Wed Feb 5 11:12:44 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips16-opc.c: Add new cases of exit instruction for - disassembler. - * mips-dis.c (print_mips16_insn_arg): Display floating point - registers in operands of exit instruction. Print `$' before - register names in operands of entry and exit instructions. - -Thu Jan 30 14:09:03 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_predefined_symbols): Table of name/value - pairs for all predefined symbols recognized by the assembler. - Also used by the disassembling routines. - (tic80_symbol_to_value): New function. - (tic80_value_to_symbol): New function. - * tic80-dis.c (print_operand_control_register, - print_operand_condition_code, print_operand_bitnum): - Remove private tables and use tic80_value_to_symbol function. - -Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c (print_operand): Change address printing - to correctly handle PC wrapping. Fixes PR11490. - -Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative - branches relaxable. - -Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_mips16): Set insn_info information. - (print_mips16_insn_arg): Likewise. - - * mips-dis.c (print_insn_mips16): Better handling of an extend - opcode followed by an instruction which can not be extended. - -Fri Jan 24 12:08:21 1997 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Changed operand specifier for the - coldfire moveb instruction to not allow an address register as - destination. Although the documentation does not indicate that - this is invalid, experiments uncovered unexpected behavior. - Added a comment explaining the situation. Thanks to Andreas - Schwab for pointing this out to me. - -Wed Jan 22 20:13:51 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_opcodes): Expand comment to note that the - entries are presorted so that entries with the same mnemonic are - adjacent to each other in the table. Sort the entries for each - instruction so that this is true. - -Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c: Include <libiberty.h>. - (print_insn_m68k): Sort the opcode table on the most significant - nibble of the opcode. - -Sat Jan 18 15:15:05 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd", - "vsub", "vst", "xnor", and "xor" instructions. - (V_a1): Renamed from V_a, msb of accumulator reg number. - (V_a0): Add macro, lsb of accumulator reg number. - -Fri Jan 17 18:24:31 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Broke excessively long - function up into several smaller ones and arranged for - the instruction printing function to be callable recursively - to print vector instructions that have both a load and a - math instruction packed into a single opcode. - * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode - to explain why it comes after the other vector opcodes. - -Fri Jan 17 16:19:15 1997 J.T. Conklin <jtc@beauty.cygnus.com> - - * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire - move insns to handle immediate operands. - -Thu Jan 17 16:19:00 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil". - fix operand mask in the "moveml" entries for the coldfire. - -Thu Jan 16 20:54:40 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V): - New macros for building vector instruction opcodes. - (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and - FMT_LI, which were unused. The field is now a flags field. - Remove some opcodes that are possible, but illegal, such - as long immediate instructions with doubles for immediate - values. Add "vadd" and "vld" instructions. - -Wed Jan 15 18:59:51 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (tic80_operands): Reorder some table entries to make - the order more logical. Move the shift alias instructions ("rotl", - "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be - interspersed with the regular sr.x and sl.x instructions. Add - and test new instruction opcodes for "sl", "sli", "sr", "sri", "st", - "sub", "subu", "swcr", and "trap". - -Tue Jan 14 19:42:50 1997 Fred Fish <fnf@cygnus.com> - - * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS. - (OFF_SL_PC): Renamed from OFF_SL. - (OFF_SS_BR): New operand type for base relative operand. - (OFF_SL_BR): New operand type for base relative operand. - (REG_BASE): New operand type for base register operand. - (tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp", - "frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr", - "ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr" - instructions. - * tic80-dis.c (print_insn_tic80): Print opcode name with fixed width - 10 char field, padded with spaces on rhs, rather than a string - followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather - than old TIC80_OPERAND_RELATIVE. Add support for new - TIC80_OPERAND_BASEREL flag bit. - -Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Print floating point operands - as floats. - * tic80-opc.c (SPFI): Add single precision floating point - immediate operand type. - (ROTATE): Add rotate operand type for shifts. - (ENDMASK): Add for shifts. - (n): Macro for the 'n' bit. - (i): Macro for the 'i' bit. - (PD): Macro for the 'PD' field. - (P2): Macro for the 'P2' field. - (P1): Macro for the 'P1' field. - (tic80_opcodes): Add entries for "exts", "extu", "fadd", - "fcmp", and "fdiv". - -Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200-dis.c (disassemble): Mask off unwanted bits after - adding in current address for pc-relative operands. - -Mon Jan 6 10:56:25 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit. - (print_insn_tic80): If R_SCALED then print ":s" modifier for operand. - * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names - changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively. - (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI, - REG_BASE_M_SI, REG_BASE_M_LI respectively. - (REG_SCALED, LSI_SCALED): New operand types. - (E): New macro for 'E' bit at bit 27. - (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap - opcodes, including the various size flavors (b,h,w,d) for - the direct load and store instructions. - -Sun Jan 5 12:18:14 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit - in an instruction. - * tic80-dis.c (print_insn_tic80): Change comma and paren handling. - Use M_SI and M_LI macros to check for ":m" modifier for GPR operands. - * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands. - (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers. - (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode - masks with "MASK_* & ~M_*" to get the M bit reset. - (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef. - -Sat Jan 4 19:05:05 1997 Fred Fish <fnf@cygnus.com> - - * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE - correctly. Add support for printing TIC80_OPERAND_BITNUM and - TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic - form. - * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM, - CC, SICR, and LICR table entries. - (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz", - "bcnd", and "brcr" opcodes. - -Fri Jan 3 18:32:11 1997 Fred Fish <fnf@cygnus.com> - - * ppc-opc.c (powerpc_operands): Make comment match the - actual fields (no shift field). - * sparc-opc.c (sparc_opcodes): Document why this cannot be "const". - * tic80-dis.c (print_insn_tic80): Replace abort stub with a - partial implementation, work in progress. - * tic80-opc.c (tic80_operands): Begin construction operands table. - (tic80_opcodes): Continue populating opcodes table and start - filling in the operand indices. - (tic80_num_opcodes): Add this. - -Fri Jan 3 12:13:52 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Add #B case for moveq. - -Thu Jan 2 12:14:29 1997 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disassemble): Make sure all variables are initialized - before they are used. - -Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Put curly-braces around operands - for "breakpoint" instruction. - -Tue Dec 31 15:38:13 1996 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE. - (dep): Use ALL_CFLAGS rather than CFLAGS. - -Tue Dec 31 15:09:16 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY - flag. - -Mon Dec 30 17:02:11 1996 Fred Fish <fnf@cygnus.com> - - * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency. - (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in. - -Mon Dec 30 11:38:01 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips16-opc.c: Add "abs". - -Sun Dec 29 10:58:22 1996 Fred Fish <fnf@cygnus.com> - - * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o. - * disassemble.c (ARCH_tic80): Define if ARCH_all is defined. - (disassembler): Add bfd_arch_tic80 support to set disassemble - to print_insn_tic80. - * tic80-dis.c (print_insn_tic80): Add stub. - -Fri Dec 27 22:30:57 1996 Fred Fish <fnf@cygnus.com> - - * configure.in (arch in $selarchs): Add bfd_tic80_arch entry. - * configure: Regenerate with autoconf. - * tic80-dis.c: Add file. - * tic80-opc.c: Add file. - -Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link. - -Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (mn10200_operands): Add SIMM16N. - (mn10200_opcodes): Use it for some logicals and btst insns. - Add "break" and "trap" instructions. - - * mn10300-opc.c (mn10300_opcodes): Add "break" instruction. - - * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". - -Sat Dec 14 22:36:20 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_mips16_insn_arg): The base address of a PC - relative load or add now depends upon whether the instruction is - in a delay slot. - -Wed Dec 11 09:23:46 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-dis.c: Finish writing disassembler. - * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn". - Fix mask for "jmp (an)". - - * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently - handle endianness issues for mn10300. - - * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)". - -Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 - instruction. Fix opcode field for "movb (imm24),dn". - - * mn10200-opc.c (mn10200_operands): Fix insertion position - for DI operand. - -Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c: Create mn10200 opcode table. - * mn10200-dis.c: Flesh out mn10200 disassembler. Not ready, - but moving along nicely. - -Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * Makefile.in (ALL_MACHINES): Add mips16-opc.o. - -Fri Dec 6 16:47:40 1996 J.T. Conklin <jtc@rhino.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Revert change to use < and > - specifiers for fmovem* instructions. - -Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disassemble): Remove '$' register prefixing. - -Fri Dec 6 17:34:39 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips16-opc.c: Change opcode for entry/exit to avoid conflicting - with dsrl. - -Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c: Add some comments explaining the various - operands and such. - - * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings. - -Thu Dec 5 12:09:48 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-dis.c (print_insn_arg): Handle new < and > operand - specifiers. - - * m68k-opc.c (m68k_opcodes): Simplify table by using < and > - operand specifiers in fmovm* instructions. - -Wed Dec 4 14:52:18 1996 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c (insert_li): Give an error if the offset has the two - least significant bits set. - -Wed Nov 27 13:09:01 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_mips16): Separate the instruction from - the arguments with a tab, not a space. - -Tue Nov 26 13:24:17 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disasemble): Finish conversion to '$' as - register prefix. - - * mn10300-opc.c (mn10300_opcodes): Fix mask field for - mov am,(imm32,sp). - -Tue Nov 26 10:53:21 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.12. - - Add support for mips16 (16 bit MIPS implementation): - * mips16-opc.c: New file. - * mips-dis.c: Include "elf-bfd.h" and "elf/mips.h". - (mips16_reg_names): New static array. - (print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or - after seeing a 16 bit symbol. - (print_insn_little_mips): Likewise. - (print_insn_mips16): New static function. - (print_mips16_insn_arg): New static function. - * mips-opc.c: Add jalx instruction. - * Makefile.in (mips16-opc.o): New target. - * configure.in: Use mips16-opc.o for bfd_mips_arch. - * configure: Rebuild. - -Mon Nov 25 16:15:17 1996 J.T. Conklin <jtc@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Simplify table by using < and > - operand specifiers in *save, *restore and movem* instructions. - - * m68k-opc.c (m68k_opcodes): Fix move and movem instructions for - the coldfire. - - * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use - register operands for immediate arithmetic, not, neg, negx, and - set according to condition instructions. - - * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage - specifier of the effective-address operand in immediate forms of - arithmetic instructions. The specifier for the immediate operand - notes how and where the constant will be stored. - -Mon Nov 25 11:17:01 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" - opcode. - - * mn10300-dis.c (disassemble): Use '$' instead of '%' for - register prefix. - - * mn10300-dis.c (disassemble): Prefix registers with '%'. - -Wed Nov 20 10:37:13 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c (disassemble): Handle register lists. - - * mn10300-opc.c: Fix handling of register list operand for - "call", "ret", and "rets" instructions. - - * mn10300-dis.c (disassemble): Print PC-relative and memory - addresses symbolically if possible. - * mn10300-opc.c: Distinguish between absolute memory addresses, - pc-relative offsets & random immediates. - - * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte - in 7 byte insns. - (disassemble): Handle SPLIT and EXTENDED operands. - -Tue Nov 19 13:33:01 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-dis.c: Rough cut at printing some operands. - - * mn10300-dis.c: Start working on disassembler support. - * mn10300-opc.c (mn10300_opcodes): Fix masks on several insns. - - * mn10300-opc.c (mn10300_operands): Add "REGS" for a register - list. - (mn10300_opcodes): Use REGS for register list in "movm" instructions. - -Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Add3 sets the carry. - -Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Demand parens around - register argument is calls and jmp instructions. - -Thu Nov 7 00:26:05 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and - getx operand. Fix opcode for mulqu imm,dn. - -Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Hijack "bits" field - in MN10300_OPERAND_SPLIT operands for how many bits - appear in the basic insn word. Add IMM32_HIGH24, - IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. - (mn10300_opcodes): Use new operands as needed. - - * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 - for bset, bclr, btst instructions. - (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed. - - * mn10300-opc.c (mn10300_operands): Remove many redundant - operands. Update opcode table as appropriate. - (IMM32): Add MN10300_OPERAND_SPLIT flag. - (mn10300_opcodes): Fix single bit error in mov imm32,dn insn. - -Tue Nov 5 13:26:58 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2 - operands (for indexed load/stores). Fix bitpos for DI - operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the - few instructions that insert immediates/displacements in the - middle of the instruction. Add IMM8E for 8 bit immediate in - the extended part of an instruction. - (mn10300_operands): Use new opcodes as appropriate. - -Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Declare the trap instruction - sequential so the assembler never parallelizes it with - other instructions. - -Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for - a data/address register that appears in register field 0 - and register field 1. - (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN - -Fri Nov 1 10:29:11 1996 Richard Henderson <rth@tamu.edu> - - * alpha-dis.c (print_insn_alpha): Use new NOPAL mask for - standard disassembly. - - * alpha-opc.c (alpha_operands): Rearrange flags slot. - (alpha_opcodes): Add new BWX, CIX, and MAX instructions. - Recategorize PALcode instructions. - -Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Add relaxing "jbr". - -Tue Oct 29 16:30:28 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (_print_insn_mips): Don't print a trailing tab if - there are no operand types. - -Tue Oct 29 12:22:21 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (D9_RELAX): Renamed from D9, all references - changed. - (v850_operands): Make sure D22 immediately follows D9_RELAX. - -Fri Oct 25 12:12:53 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5. - -Thu Oct 24 17:53:52 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w - and sst.w instructions. - - * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for - "bCC"instructions). - -Thu Oct 24 17:21:20 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (_print_insn_mips): Use a tab between the instruction - and the arguments. - -Tue Oct 22 23:32:56 1996 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c (PPCPWR2): Define. - (powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating - it. - -Fri Oct 11 16:03:49 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode - field for movhu instruction. - - * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, - cast value to "long" not "signed long" to keep hpux10 - compiler quiet. - -Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field - for mov (abs16),DN. - - * mn10300-opc.c (FMT*): Remove definitions. - - * mn10300-opc.c (mn10300_opcodes): Fix destination register - for shift-by-register opcodes. - - * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM - into [AD][MN][01] for encoding the position of the register - in the opcode. - -Wed Oct 9 11:19:26 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, - "putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". - -Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. - Fix various typos. Add "PAREN" operand. - (MEM, MEM2): Define. - (mn10300_opcodes): Surround all memory addresses with "PAREN" - operands. Fix several typos. - - * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's - changes. - -Mon Oct 7 16:48:45 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300-opc.c (FMT_XX): Renumber starting at one. - (mn10300_operands): Rough cut. Enough to parse "mov" instructions - at this time. - (mn10300_opcodes): Break opcode format out into its own field. - Update many operand fields to deal with signed vs unsigned - issues. Fix one or two typos in the "mov" instruction - opcode, mask and/or operand fields. - -Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (plusha): Prefer encoding for m68040up, in case - m68851 wasn't reset. - -Thu Oct 3 17:17:02 1996 Ian Lance Taylor <ian@cygnus.com> - - * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for - all opcodes. Very rough cut at operands for all opcodes. - - * mn10300-opc.c (mn10300_opcodes): Start fleshing out the - opcode table. - -Thu Oct 3 10:06:07 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200-opc.c, mn10300-opc.c: New files. - * mn10200-dis.c, mn10300-dis.c: New files. - * mn10x00-opc.c, mn10x00-dis.c: Deleted. - * disassemble.c: Break mn10x00 support into 10200 and 10300 - support. - * configure.in: Likewise. - * configure: Rebuilt. - -Thu Oct 3 15:59:12 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) - - * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. - -Wed Oct 2 23:28:42 1996 Jeffrey A Law (law@cygnus.com) - - * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita - MN10x00 processors. - * disassemble.c (ARCH_mn10x00): Define. - (disassembler): Handle bfd_arch_mn10x00. - * configure.in: Recognize bfd_mn10x00_arch. - * configure: Rebuilt. - -Tue Oct 1 10:49:11 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses - accordingly. Don't declare functions using op_rtn. - -Fri Sep 27 18:28:59 1996 Stu Grossman (grossman@critters.cygnus.com) - - * v850-dis.c (disassemble): Add memaddr argument. Re-arrange - params to be more standard. - * (disassemble): Print absolute addresses and symbolic names for - branch and jump targets. - * v850-opc.c (v850_operand): Add displacement flag to 9 and 22 - bit operands. - * (v850_opcodes): Add breakpoint insn. - -Mon Sep 23 12:32:26 1996 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Move the fmovemx data register cases before the - other cases, so that they get recognized before the data register - does gets treated as a degenerate register list. - -Tue Sep 17 12:06:51 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add a case for "div" and "divu" with two registers - and a destination of $0. - -Tue Sep 10 16:12:39 1996 Fred Fish <fnf@rtl.cygnus.com> - - * mips-dis.c (print_insn_arg): Add prototype. - (_print_insn_mips): Ditto. - -Mon Sep 9 14:26:26 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_arg): Print condition code registers as - $fccN. - -Tue Sep 3 12:09:46 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx. - -Tue Sep 3 12:05:25 1996 Jeffrey A Law (law@cygnus.com) - - * v850-dis.c (disassemble): Make static. Provide prototype. - -Sun Sep 1 22:30:40 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (insert_d9, insert_d22): Fix boundary case - in range checks. - -Sat Aug 31 01:27:26 1996 Jeffrey A Law (law@cygnus.com) - - * v850-dis.c (disassemble): Handle insertion of ',', '[' and - ']' characters into the output stream. - * v850-opc.c (v850_opcodes: Remove size field from all opcodes. - Add "memop" field to all opcodes (for the disassembler). - Reorder opcodes so that "nop" comes before "mov" and "jr" - comes before "jarl". - - * v850-dis.c (print_insn_v850): Fix typo in last change. - - * v850-dis.c (print_insn_v850): Properly handle disassembling - a two byte insn at the end of a memory region when the memory - region's size is only two byte aligned. - - * v850-dis.c (v850_cc_names): Fix stupid thinkos. - - * v850-dis.c (v850_reg_names): Define. - (v850_sreg_names, v850_cc_names): Likewise. - (disassemble): Very rough cut at printing operands (unformatted). - - * v850-opc.c (BOP_MASK): Fix. - (v850_opcodes): Fix mask for jarl and jr. - - * v850-dis.c: New file. Skeleton for disassembler support. - * Makefile.in Remove v850 references, they're not needed here. - * configure.in: Add v850-dis.o when building v850 toolchains. - * configure: Rebuilt. - * disassemble.c (disassembler): Call v850 disassembler. - - * v850-opc.c (insert_d8_7, extract_d8_7): New functions. - (insert_d8_6, extract_d8_6): New functions. - (v850_operands): Rename D7S to D7; operand for D7 is unsigned. - Rename D8 to D8_7, use {insert,extract}_d8_7 routines. - Add D8_6. - (IF4A, IF4B): Use "D7" instead of "D7S". - (IF4C, IF4D): Use "D8_7" instead of "D8". - (IF4E, IF4F): New. Use "D8_6". - (v850_opcodes): Use IF4A/IF4B for sld.b/sst.b. Use IF4C/IF4D for - sld.h/sst.h. Use IF4E/IF4F for sld.w/sst.w. - - * v850-opc.c (insert_d16_15, extract_d16_15): New functions. - (v850_operands): Change D16 to D16_15, use special insert/extract - routines. New new D16 that uses the generic insert/extract code. - (IF7A, IF7B): Use D16_15. - (IF7C, IF7D): New. Use D16. - (v850_opcodes): Use IF7C and IF7D for ld.b and st.b. - - * v850-opc.c (insert_d9, insert_d22): Slightly improve error - message. Issue an error if the branch offset is odd. - - * v850-opc.c: Add notes about needing special insert/extract - for all the load/store insns, except "ld.b" and "st.b". - - * v850-opc.c (insert_d22, extract_d22): New functions. - (v850_operands): Use insert_d22 and extract_d22 for - D22 operands. - (insert_d9): Fix range check. - -Fri Aug 30 18:01:02 1996 J.T. Conklin <jtc@hippo.cygnus.com> - - * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag - and set bits field to D9 and D22 operands. - -Thu Aug 29 11:10:46 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_operands): Define SR2 operand. - (v850_opcodes): "ldsr" uses R1,SR2. - - * v850-opc.c (v850_opcodes): Fix opcode specs for - sld.w, sst.b, sst.h, sst.w, and nop. - -Wed Aug 28 15:55:43 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Add null opcode to mark the - end of the opcode table. - -Mon Aug 26 13:35:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (pre_defined_registers): Added register pairs, - "r0-r1", "r2-r3", etc. - -Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_operands): Make I16 be a signed operand. - Create I16U for an unsigned 16bit mmediate operand. - (v850_opcodes): Use I16U for "ori", "andi" and "xori". - - * v850-opc.c (v850_operands): Define EP operand. - (IF4A, IF4B, IF4C, IF4D): Use EP. - - * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov" - with immediate operand, "movhi". Tweak "ldsr". - - * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw] - correct. Get sld.[bhw] and sst.[bhw] closer. - - * v850-opc.c (v850_operands): "not" is a two byte insn - - * v850-opc.c (v850_opcodes): Correct bit pattern for setf. - - * v850-opc.c (v850_operands): D16 inserts at offset 16! - - * v850-opc.c (two): Get order of words correct. - - * v850-opc.c (v850_operands): I16 inserts at offset 16! - - * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system - register source and destination operands. - (v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr". - - * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix - same thinko in "trap" opcode. - - * v850-opc.c (v850_opcodes): Add initializer for size field - on all opcodes. - - * v850-opc.c (v850_operands): D6 -> DS7. References changed. - Add D8 for 8-bit unsigned field in short load/store insns. - (IF4A, IF4D): These both need two registers. - (IF4C, IF4D): Define. Use 8-bit unsigned field. - (v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use - IF4C & IF4D. For "trap" use I5U, not I5. Add IF1 operand - for "ldsr" and "stsr". - * v850-opc.c (v850_operands): 3-bit immediate for bit insns - is unsigned. - - * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and - short store word (sst.w). - -Thu Aug 22 16:57:27 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850-opc.c (v850_operands): Added insert and extract fields, - pointers to functions that handle unusual operand encodings. - -Thu Aug 22 01:05:24 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_opcodes): Enable "trap". - - * v850-opc.c (v850_opcodes): Fix order of displacement - and register for "set1", "clr1", "not1", and "tst1". - -Wed Aug 21 18:46:26 1996 Jeffrey A Law (law@cygnus.com) - - * v850-opc.c (v850_operands): Add "B3" support. - (v850_opcodes): Fix and enable "set1", "clr1", "not1" - and "tst1". - - * v850-opc.c (v850_opcodes): "jmp" has only an R1 operand. - - * v850-opc.c: Close unterminated comment. - -Wed Aug 21 17:31:26 1996 J.T. Conklin <jtc@hippo.cygnus.com> - - * v850-opc.c (v850_operands): Add flags field. - (v850_opcodes): add move opcodes. - -Tue Aug 20 14:41:03 1996 J.T. Conklin <jtc@hippo.cygnus.com> - - * Makefile.in (ALL_MACHINES): Add v850-opc.o. - * configure: (bfd_v850v_arch) Add new case. - * configure.in: (bfd_v850_arch) Add new case. - * v850-opc.c: New file. - -Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Handle little endian sparcs. - -Thu Aug 15 13:14:43 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c: Add additional information to the opcode - table to help determinine which instructions can be done - in parallel. - -Thu Aug 15 13:11:13 1996 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-make.sed: Update editing of include pathnames to be - more general. - -Thu Aug 15 16:28:41 1996 James G. Smith <jsmith@cygnus.co.uk> - - * arm-opc.h: Added "bx" instruction definition. - -Wed Aug 14 17:00:04 1996 Richard Henderson <rth@tamu.edu> - - * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5. - -Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l. - -Fri Aug 9 13:21:59 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER. - -Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Update for alpha-opc changes. - -Wed Aug 7 11:55:10 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (print_insn_i386): Actually return the correct value. - (ONE, OP_ONE): #ifdef out; not used. - -Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions. - Changed subi operand type to treat 0 as 16. - -Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose - <rose@netcom.com>. - -Wed Jul 31 14:39:27 1996 James G. Smith <jsmith@cygnus.co.uk> - - * arm-opc.h: (arm_opcodes): Added halfword and sign-extension - memory transfer instructions. Add new format string entries %h and %s. - * arm-dis.c: (print_insn_arm): Provide decoding of the new - formats %h and %s. - -Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift. - (d10v_opcodes): Modified accumulator shift instructions to use UNUM4S. - -Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com> - - * alpha-dis.c (print_insn_alpha_osf): Remove. - (print_insn_alpha_vms): Remove. - (print_insn_alpha): Make globally visible. Chose the register - names based on info->flavour. - * disassemble.c: Always return print_insn_alpha for the alpha. - -Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c (dis_long): Handle unknown opcodes. - -Thu Jul 25 12:08:09 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-opc.c: Changes to support signed and unsigned numbers. - All instructions with the same name that have long and short forms - now end in ".l" or ".s". Divs added. - * d10v-dis.c: Changes to support signed and unsigned numbers. - -Tue Jul 23 11:02:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v-dis.c: Change all functions to use info->print_address_func. - -Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire - move ccr/sr insns more strict so that the disassembler only - selects them when the addressing mode is data register. - -Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - * d10v-opc.c (pre_defined_registers): Declare. - * d10v-dis.c (print_operand): Now uses pre_defined_registers - to pick a better name for the registers. - -Mon Jul 22 13:47:23 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix - operands for fexpand and fpmerge. From Christian Kuehnke - <Christian.Kuehnke@arbi.informatik.uni-oldenburg.de>. - -Mon Jul 22 13:17:06 1996 Richard Henderson <rth@tamu.edu> - - * alpha-dis.c (print_insn_alpha): No longer the user-visible - print routine. Take new regnames and cpumask arguments. - Kill the environment variable nonsense. - (print_insn_alpha_osf): New function. Do OSF/1 style regnames. - (print_insn_alpha_vms): New function. Do VMS style regnames. - * disassemble.c (disassembler): Test bfd flavour to pick - between OSF and VMS routines. Default to OSF. - -Thu Jul 18 17:19:34 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_SUBST (INSTALL_SHLIB). - * configure: Rebuild. - * Makefile.in (install): Use @INSTALL_SHLIB@. - -Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * configure: (bfd_d10v_arch) Add new case. - * configure.in: (bfd_d10v_arch) Add new case. - * d10v-dis.c: New file. - * d10v-opc.c: New file. - * disassemble.c (disassembler) Add entry for d10v. - -Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating - to bcc, trapfl, subxl, and wddata discovered by Andreas Schwab. - -Mon Jul 15 16:59:55 1996 Stu Grossman (grossman@critters.cygnus.com) - - * i386-dis.c: Get rid of print_insn_i8086. Use info.mach to - distinguish between variants of the instruction set. - * sparc-dis.c: Get rid of print_insn_sparclite. Use info.mach to - distinguish between variants of the instruction set. - -Fri Jul 12 10:12:01 1996 Stu Grossman (grossman@critters.cygnus.com) - - * i386-dis.c (print_insn_i8086): New routine to disassemble using - the 8086 instruction set. - * i386-dis.c: General cleanups. Make most things static. Add - prototypes. Get rid of static variables aflags and dflags. Pass - them as args (to almost everything). - -Thu Jul 11 11:58:44 1996 Jeffrey A Law (law@cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Handle macregs in ldmac insns. - - * h8300-dis.c (bfd_h8_disassemble): Handle "ldm.l" and "stm.l". - - * h8300-dis.c (bfd_h8_disassemble): "abs" is implicitly two - if the next arg is marked with SRC_IN_DST. Gross. - - * h8300-dis.c (bfd_h8_disassemble): Print "exr" when - we're looking for and find EXR. - - * h8300-dis.c (bfd_h8_disassemble): We don't have a match - if we're looking for KBIT and we don't find it. - - * h8300-dis.c (bfd_h8_disassemble): Mask off unwanted bits - for L_3 and L_2. - - * h8300-dis.c (bfd_h8_disassemble): Don't set plen for - 3bit immediate operands. - -Tue Jul 9 10:55:20 1996 Ian Lance Taylor <ian@cygnus.com> - - * Released binutils 2.7. - - * alpha-opc.c: Add new case of "mov". From Klaus Kaempf - <kkaempf@progis.ac-net.de>. - -Thu Jul 4 11:42:51 1996 Ian Lance Taylor <ian@cygnus.com> - - * alpha-opc.c: Correct second case of "mov" to use OPRL. - -Wed Jul 3 16:03:47 1996 Stu Grossman (grossman@critters.cygnus.com) - - * sparc-dis.c (print_insn_sparclite): New routine to print - sparclite instructions. - -Wed Jul 3 14:21:18 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k-opc.c (m68k_opcodes): Add coldfire support. - -Fri Jun 28 15:53:51 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS, - #ASI_NUCLEUS_LITTLE. Rename #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_L - to #ASI_AS_IF_USER_{PRIMARY,SECONDARY}_LITTLE. - -Tue Jun 25 22:58:31 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) - - * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir): - Use autoconf-set values. - (docdir, oldincludedir): Removed. - * configure.in (AC_PREREQ): autoconf 2.5 or higher. - -Fri Jun 21 13:53:36 1996 Richard Henderson <rth@tamu.edu> - - * alpha-opc.c: New file. - * alpha-opc.h: Remove. - * alpha-dis.c: Complete rewrite to use new opcode table. - * configure.in: For bfd_alpha_arch, use alpha-opc.o. - * configure: Rebuild with autoconf 2.10. - * Makefile.in (ALL_MACHINES): Add alpha-opc.o. - (alpha-dis.o): Depend upon $(INCDIR)/opcode/alpha.h, not - alpha-opc.h. - (alpha-opc.o): New target. - -Wed Jun 19 15:55:12 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-dis.c (print_insn_sparc): Remove unused local variable i. - Set imm_added_to_rs1 even if the source and destination register - are not the same. - - * sparc-opc.c: Add some two operand forms of the wr instruction. - -Tue Jun 18 15:58:27 1996 Jeffrey A. Law <law@rtl.cygnus.com> - - * h8300-dis.c (bfd_h8_disassemble): Rename "hmode" argument - to just "mode". - - * disassemble.c (disassembler): Handle H8/S. - * h8300-dis.c (print_insn_h8300s): New function for H8/S. - -Tue Jun 18 18:06:50 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: Add beq/teq as aliases for be/te. - - * ppc-opc.c: Fix fcmpo opcode. From Sergei Steshenko - <sergei@msil.sps.mot.com>. - -Tue Jun 18 15:08:54 1996 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: New file. - - * alpha-dis.c (print_insn_alpha): Print lda ra,lit(rz) as mov. - -Mon Jun 10 18:50:38 1996 Ian Lance Taylor <ian@cygnus.com> - - * h8300-dis.c (bfd_h8_disassemble): Always print ABS8MEM with :8, - regardless of plen. - -Tue Jun 4 09:15:53 1996 Doug Evans <dje@canuck.cygnus.com> - - * i386-dis.c (OP_OFF): Call append_prefix. - -Thu May 23 15:18:23 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (instruction encoding macros): Add explicit casts to - unsigned long to silence a warning from the Solaris PowerPC - compiler. - -Thu Apr 25 19:33:32 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Add ultrasparc vis extensions. - -Mon Apr 22 17:12:35 1996 Doug Evans <dje@blues.cygnus.com> - - * sparc-dis.c (X_IMM,X_SIMM): New macros. - (X_IMM13): Delete. - (print_insn_sparc): Merge cases i,I,j together. New cases X,Y. - * sparc-opc.c (sparc_opcodes): Use X for 5 bit shift constants, - Y for 6 bit shift constants. Rewrite entries for crdcxt, cwrcxt, - cpush, cpusha, cpull sparclet insns. - -Wed Apr 17 14:20:22 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (compute_arch_mask): Replace ANSI style def with K&R. - -Thu Apr 11 17:30:02 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc-opc.c: Set F_FBR on floating point branch instructions. - Set F_FLOAT on other floating point instructions. - -Mon Apr 8 17:02:48 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (PPC860): Macro for 860/821 specific instructions and - registers. - (powerpc_opcodes): Add 860/821 specific SPRs. - -Mon Apr 8 14:00:44 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Permit --enable-shared to specify a list of - directories. Set and substitute BFD_PICLIST. - * configure: Rebuild. - * Makefile.in (BFD_PICLIST): Rename from BFD_LIST. Change all - uses. Set to @BFD_PICLIST@. - -Fri Apr 5 17:12:27 1996 Jeffrey A Law (law@cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Use "bit" for L_3 immediates, - not "abs", which may be needed for the absolute in something - like btst #0,@10:8. Print L_3 immediates separately from other - immediates. Change ABSMOV reference to ABS8MEM. - -Wed Apr 3 10:40:45 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (opcodes_initialized): Move inside print_insn_sparc. - (current_arch_mask): New static global. - (compute_arch_mask): New static function. - (print_insn_sparc): Delete sparc_v9_p. New static local - current_mach. Resort opcode table if current_mach changes. - Generalize "insn not supported" test. - (compare_opcodes): Prefer supported opcodes to nonsupported ones. - Delete test for v9/!v9. - * sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK. - (v6notlet): Define. - (brfc): Split into CBR and FBR for coprocessor/fp branches. - (brfcx): Renamed to FBRX. - (condfc): Renamed to CONDFC. Pass v6notlet to CBR (standard - coprocessor mnemonics are not supported on the sparclet). - (condf): Renamed to CONDF. - (SLCBCC2): Delete F_ALIAS flag. - -Sat Mar 30 21:45:59 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): rd must be 0 for - mov foo,{%y,%psr,%wim,%tbr}. Support mov foo,%asrX. - -Fri Mar 29 13:02:40 1996 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (config.status): Depend upon BFD VERSION file, so - that the shared library version number is set correctly. - -Tue Mar 26 15:47:14 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Use AC_CHECK_TOOL to find ar and ranlib. From - Miles Bader <miles@gnu.ai.mit.edu>. - * configure: Rebuild. - -Sat Mar 16 13:04:07 1996 Fred Fish <fnf@cygnus.com> - - * z8kgen.c (internal, gas): Call xmalloc rather than unchecked - malloc. - -Tue Mar 12 12:14:10 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.8. - -Thu Mar 7 15:11:10 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Handle 'O' operand char like 'r'. - * sparc-opc.c (sparc_opcodes): Use 'O' operand char for `neg reg'. - -Tue Mar 5 15:51:57 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Don't set SHLIB or SHLINK to an empty string, - since they appear as targets in Makefile.in. - * configure: Rebuild. - -Mon Feb 26 13:03:40 1996 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-make.sed: Edit out shared library support bits. - -Tue Feb 20 20:48:28 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-opc.c (v8,v6notv9): Add MASK_SPARCLET. - (sparc_opcode_archs): Add MASK_V8 to sparclet entry. - (sparc_opcodes): Add sparclet insns. - (sparclet_cpreg_table): New static local. - (sparc_{encode,decode}_sparclet_cpreg): New functions. - * sparc-dis.c (print_insn_sparc): Handle sparclet cpregs. - -Tue Feb 20 11:02:44 1996 Alan Modra <alan@mullet.Levels.UniSA.Edu.Au> - - * i386-dis.c (index16): New static variable. - (putop): Print jecxz for 32 bit case, jcxz for 16 bit, not the - other way around. - (OP_indirE): Return result of OP_E. - (OP_E): Check for 16 bit addressing mode, and disassemble - correctly. Optimised 32 bit case a little. Don't print - "(base,index,scale)" when sib specifies only an offset. - -Mon Feb 19 12:32:17 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Set and substitute SHLIB_DEP. - * configure: Rebuild. - * Makefile.in (SHLIB_DEP): New variable. - (LIBIBERTY_LISTS, BFD_LIST): New variables. - (stamp-piclist): Depend upon LIBIBERTY_LISTS and BFD_LIST. If - COMMON_SHLIB, add them to piclist with appropriate modifications. - ($(SHLIB)): Depend upon $(SHLIB_DEP). Don't check COMMON_SHLIB - here: just use piclist. - -Mon Feb 19 02:03:50 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (MASK_V9,V9_ONLY_P,V9_P): Define. - (print_insn_sparc): Rewrite v9/not-v9 tests. - (compare_opcodes): Likewise. - * sparc-opc.c (MASK_<ARCH>): Define. - (v6,v7,v8,sparclite,v9,v9a): Redefine. - (sparclet,v6notv9): Define. - (sparc_opcode_archs): Delete member `conflicts'. Add `supported'. - (sparc_opcodes): Delete F_NOTV9, use v6notv9 instead. - -Thu Feb 15 14:45:05 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_PROG_CC before configure.host. - * configure: Rebuild. - - * Makefile.in (SONAME): Remove leading ../bfd/ from $(SHLIB). - -Wed Feb 14 19:01:27 1996 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (onebyte_has_modrm): New static array. - (twobyte_has_modrm): New static array. - (print_insn_i386): Only fetch the mod/reg/rm byte if it is needed. - -Tue Feb 13 15:15:01 1996 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in ($(SHLINK)): Check ts against $(SHLIB), not - $(SHLINK). - -Mon Feb 12 16:26:06 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (PPC): Undef, so default defination on Windows NT - doesn't conflict. - -Wed Feb 7 13:59:54 1996 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcodes): The bkpt instruction is supported on - m68010up, not just m68020up | cpu32. - - * Makefile.in (SONAME): New variable. - ($(SHLINK)): Make a link to the transformed name, as well. - (stamp-tshlink): New target. - (install): Skip stamp-tshlink during install. - -Tue Feb 6 12:28:54 1996 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_ARG_PROGRAM. - * configure: Rebuild. - * Makefile.in (program_transform_name): New variable. - (install): Transform library name before installing it. - -Mon Feb 5 16:14:42 1996 Ian Lance Taylor <ian@cygnus.com> - - * i960-dis.c (mem): Add HX dcinva instruction. - - Support for building as a shared library, based on patches from - Alan Modra <alan@spri.levels.unisa.edu.au>: - * configure.in: Add AC_ARG_ENABLE for shared and commonbfdlib. - New substitutions: ALLLIBS, PICFLAG, SHLIB, SHLIB_CC, - SHLIB_CFLAGS, COMMON_SHLIB, SHLINK. - * configure: Rebuild. - * Makefile.in (ALLLIBS): New variable. - (PICFLAG, SHLIB, SHLIB_CC, SHLIB_CFLAGS): New variables. - (COMMON_SHLIB, SHLINK): New variables. - (.c.o): If PICFLAG is set, compile twice, once PIC, once normal. - (STAGESTUFF): Remove variable. - (all): Depend upon $(ALLLIBS) rather than $(TARGETLIB). - (stamp-piclist, piclist): New targets. - ($(SHLIB), $(SHLINK)): New targets. - ($(OFILES)): Depend upon stamp-picdir. - (disassemble.o): Build twice if PICFLAG is set. - (MOSTLYCLEAN): Add pic/*.o. - (clean): Remove $(SHLIB), $(SHLINK), piclist, and stamp-piclist. - (distclean): Remove pic and stamp-picdir. - (install): Install shared libraries. - (stamp-picdir): New target. - -Fri Feb 2 17:15:25 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Delete DISASM_RAW_INSN support. - Print unknown instruction as "unknown", rather than in hex. - -Tue Jan 30 14:06:08 1996 Ian Lance Taylor <ian@cygnus.com> - - * dis-buf.c: Include "sysdep.h" before "dis-asm.h". - -Thu Jan 25 20:24:07 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-opc.c (sparc_opcode_archs): Mark v8/sparclite as conflicting. - -Thu Jan 25 11:56:49 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386-dis.c (print_insn_i386): Only fetch the mod/reg/rm byte - when necessary. From Ulrich Drepper - <drepper@myware.rz.uni-karlsruhe.de>. - -Thu Jan 25 03:39:10 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): NUMOPCODES replaced with - sparc_num_opcodes. Update architecture enum values. - * sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname. - (sparc_opcode_lookup_arch): New function. - (sparc_num_opcodes): Renamed from bfd_sparc_num_opcodes. - (sparc_opcodes): Add v9a shutdown insn. - -Mon Jan 22 08:29:59 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc-dis.c (print_insn_sparc): Renamed from print_insn. - If DISASM_RAW_INSN, print insn in hex. Handle v9a as opcode - architecture. - (print_insn_sparc64): Deleted. - * disassemble.c (disassembler, case bfd_arch_sparc): Always use - print_insn_sparc. - - * sparc-opc.c (architecture_pname): Add v9a. - -Fri Jan 12 14:35:58 1996 David Mosberger-Tang <davidm@AZStarNet.com> - - * alpha-opc.h (alpha_insn_set): VAX floating point opcode was - incorrectly defined as 0x16 when it should be 0x15. - (FLOAT_FORMAT_MASK): function code is 11 bits, not just 7 bits! - (alpha_insn_set): added cvtst and cvttq float ops. Also added - excb (exception barrier) which is defined in the Alpha - Architecture Handbook version 2. - * alpha-dis.c (print_insn_alpha): Fixed special-case decoding for - OPERATE_FORMAT_CODE type instructions. The bug caused mulq to be - disassembled as or, for example. - -Wed Jan 10 12:37:22 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_insn_arg): Print cases 'i' and 'u' in hex. - (_print_insn_mips): Change i from int to unsigned int. - -Thu Jan 4 17:21:10 1996 David Edelsohn <edelsohn@mhpcc.edu> - - * ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different - from tlbie PowerPC opcode. Add PPC603 tlbld and tlbli. - -Thu Dec 28 13:29:19 1995 John Hassey <hassey@rtp.dg.com> - - * i386-dis.c: Added Pentium Pro instructions. - -Tue Dec 19 22:56:35 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (fsqrt{,.}): Duplicate for PowerPC in addition to - being for Power2. - -Fri Dec 15 14:14:15 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * sh-opc.h (sh_nibble_type): Added REG_B. - (sh_arg_type): Added A_REG_B. - (sh_table): Added pref and bank reg versions of ldc, ldc.l, stc - and stc.l opcodes. - * sh-dis.c (print_insn_shx): Added cases for REG_B and A_REG_B. - -Fri Dec 15 16:44:31 1995 Ian Lance Taylor <ian@cygnus.com> - - * disassemble.c (disassembler): Use new bfd_big_endian macro. - -Tue Dec 12 12:22:24 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (distclean): Remove stamp-h. From Ronald - F. Guilmette <rfg@monkeys.com>. - -Tue Dec 5 13:42:44 1995 Stan Shebs <shebs@andros.cygnus.com> - - From David Mosberger-Tang <davidm@azstarnet.com>: - * alpha-dis.c (print_insn_alpha): fixed decoding of cpys - instruction. - -Mon Dec 4 12:29:05 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * sh-opc.h (sh_arg_type): Added A_SSR and A_SPC. - (sh_table): Added many SH3 opcodes. - * sh-dis.c (print_insn_shx): Added cases for A_SSR and A_SPC. - -Fri Dec 1 07:42:18 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (subfc., subfco): Mark this PPCCOM, not PPC. - (subco,subco.): Mark this PPC, not PPCCOM. - -Mon Nov 27 13:09:52 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.7. - -Tue Nov 21 18:28:06 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure: Rebuild with autoconf 2.6. - -Wed Nov 15 19:02:53 1995 Ken Raeburn <raeburn@cygnus.com> - - * configure.in: Sort list of architectures. Accept but do nothing - for alliant, convex, pyramid, romp, and tahoe. - -Wed Nov 8 20:18:59 1995 Ian Lance Taylor <ian@cygnus.com> - - * a29k-dis.c (print_special): Change num to unsigned int. - -Wed Nov 8 20:10:35 1995 Eric Freudenthal <freudenthal@nyu.edu> - - * a29k-dis.c (print_insn): Cast insn24 to unsigned long when - shifting it. - -Tue Nov 7 15:21:06 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_CHECK_PROG to find and cache AR. - * configure: Rebuilt. - -Mon Nov 6 17:39:47 1995 Harry Dolan <dolan@ssd.intel.com> - - * configure.in: Add case for bfd_i860_arch. - * configure: Rebuild. - -Fri Nov 3 12:45:31 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcodes): Correct fmoveml operands. - * m68k-dis.c (NEXTSINGLE): Change i to unsigned int. - (NEXTDOUBLE): Likewise. - (print_insn_m68k): Don't match fmoveml if there is more than one - register in the list. - (print_insn_arg): Handle a place of '8' for a type of 'L'. - -Thu Nov 2 23:06:33 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Use #W rather than #w. - * m68k-dis.c (print_insn_arg): Handle new 'W' place. - -Wed Nov 1 13:30:24 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcode_aliases): Add dbfw as an alias for dbf, - and likewise for all the dbxx opcodes. - -Mon Oct 30 20:50:40 1995 Fred Fish <fnf@cygnus.com> - - * arc-dis.c: Include elf-bfd.h rather than libelf.h. - -Mon Oct 23 11:11:34 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> - - * mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added - the VR4100 specific instructions to the mips_opcodes structure. - -Thu Oct 19 11:05:23 1995 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-config.in, mpw-make.sed: Remove ugly workaround for - ugly Metrowerks bug in CW6, is fixed in CW7. - -Mon Oct 16 12:59:01 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (whole file): Add flags for common/any support. - -Tue Oct 10 11:06:07 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (BISON): Remove macro. - (FLAGS_TO_PASS): Remove BISON. - -Fri Oct 6 16:26:45 1995 Ken Raeburn <raeburn@cygnus.com> - - Mon Sep 25 22:49:32 1995 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_m68k): Recognize all two-word - instructions that take no args by looking at the match mask. - (print_insn_arg): Always print "%" before register names. - [case 'c']: Use "nc" for the no-cache case, as recognized by gas. - [case '_']: Don't print "@#" before address. - [case 'J']: Use "%s" as format string, not register name. - [case 'B']: Treat place == 'C' like 'l' and 'L'. - -Thu Oct 5 22:16:20 1995 Ken Raeburn <raeburn@cygnus.com> - - * i386-dis.c: Describe cmpxchg8b operand, and spell the opcode - name correctly. - -Tue Oct 3 08:30:20 1995 steve chamberlain <sac@slash.cygnus.com> - - From David Mosberger-Tang <davidm@azstarnet.com> - - * alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added. - (alpha_insn_set): added definitions for VAX floating point - instructions (Unix compilers don't generate these, but handcoded - assembly might still use them). - - * alpha-dis.c (print_insn_alpha): added support for disassembling - the miscellaneous instructions in the Alpha instruction set. - -Tue Sep 26 18:47:20 1995 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-config.in: Add m68k-opc.c.o to BFD_MACHINES for m68k, - no longer create sysdep.h, sed ppc-opc.c to work around a - serious Metrowerks C bug. - * mpw-make.in: Remove. - * mpw-make.sed: New file, used by mpw-configure to edit - Makefile.in into an MPW makefile. - -Wed Sep 20 12:55:28 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (maintainer-clean): New synonym for realclean. - -Tue Sep 19 15:28:36 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Split pmove patterns which use 'P' into patterns - which use '0', '1', and '2' instead. Specify the proper size for - a pmove immediate operand. Correct the pmovefd patterns to be - moves to a register, not from a register. - * m68k-dis.c (print_insn_arg): Replace 'P' with '0', '1', '2'. - -Thu Sep 14 11:58:22 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Mark all insns that reference - %psr, %wim, %tbr as F_NOTV9. - -Fri Sep 8 01:07:38 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (Makefile): Just rebuild Makefile when running - config.status. - (config.h, stamp-h): New targets. - * configure.in: Call AC_CONFIG_HEADER and AC_CANONICAL_SYSTEM - earlier. Don't bother to call AC_ARG_PROGRAM. Touch stamp-h when - rebuilding config.h. - * configure: Rebuild. - - * mips-opc.c: Change unaligned loads and stores with "t,A" - operands to use "t,A(b)". - -Thu Sep 7 19:02:46 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-dis.c (print_insn_shx): Add F_FR0 support. - -Thu Sep 7 19:02:46 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-dis.c (print_insn_shx): Change loop over op->arg[n] to iterate - until 3 instead of until 2. - -Wed Sep 6 21:21:33 1995 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.in (ALL_CFLAGS): Define. - (.c.o, disassemble.o): Use $(ALL_CFLAGS). - (MOSTLYCLEAN): Add config.log. - (distclean): Don't remove config.log. - * configure.in: Substitute HDEFINES. - * configure: Rebuild. - -Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (sh_arg_type): Add F_FR0. - (sh_table, case fmac): Add F_FR0 as first argument. - -Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (sh_opcode_info): Increase arg array size to 4. - -Tue Sep 5 18:28:10 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c: Remove all references to NO_V9. - -Tue Sep 5 20:03:26 1995 Ian Lance Taylor <ian@cygnus.com> - - * aclocal.m4: Just include ../bfd/aclocal.m4. - * configure: Rebuild. - -Tue Sep 5 16:09:59 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (X_DISP19): Define. - (print_insn, case 'G'): Use it. - (print_insn, case 'L'): Sign extend displacement. - -Mon Sep 4 14:28:46 1995 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Run ../bfd/configure.host before AC_PROG_CC. - Subsitute CFLAGS and AR. Call AC_PROG_INSTALL. Don't substitute - host_makefile_frag or frags. - * aclocal.m4: New file. - * configure: Rebuild. - * Makefile.in (INSTALL): Set to @INSTALL@. - (INSTALL_PROGRAM): Set to @INSTALL_PROGRAM@. - (INSTALL_DATA): Set to @INSTALL_DATA@. - (AR): Set to @AR@. - (AR_FLAGS): Set to rc rather than qc. - (CC): Define as @CC@. - (CFLAGS): Set to @CFLAGS@. - (@host_makefile_frag@): Remove. - (config.status): Remove dependency upon @frags@. - - * configure.in: ../bfd/config.bfd now just sets shell variables. - Use them rather than looking through target Makefile fragments. - * configure: Rebuild. - -Thu Aug 31 12:35:32 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (ftrc): Change FPUL_N to FPUL_M. - -Wed Aug 30 13:52:28 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sparc_opcodes): Delete duplicate wr %y insn. - Add clrx, iprefetch, signx, clruw, cas, casl, casx, casxl synthetic - sparc64 insns. - - * sparc-opc.c (sparc_opcodes): Fix prefetcha insn. - (lookup_{name,value}): New functions. - (prefetch_table): New static local. - (sparc_{encode,decode}_prefetch): New functions. - * sparc-dis.c (print_insn): Handle '*' arg (prefetch function). - -Wed Aug 30 11:11:58 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h: Add blank lines to improve readabililty of sh3e - instructions. - -Wed Aug 30 11:09:38 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-dis.c: Correct comment on first line of file. - -Tue Aug 29 15:37:18 1995 Doug Evans <dje@canuck.cygnus.com> - - * disassemble.c (disassembler): Handle bfd_mach_sparc64. - - * sparc-opc.c (asi, membar): New static locals. - (sparc_{encode,decode}_{asi,membar}): New functions. - (sparc_opcodes, membar insn): Fix. - * sparc-dis.c (print_insn): Call sparc_decode_asi. - Support decoding of membar masks. - (X_MEMBAR): Define. - -Sat Aug 26 21:22:48 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcode_aliases): Add br, brs, brb, brw, brl. - -Mon Aug 21 17:33:36 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c (m68k_opcode_aliases): Add bhib as an alias for bhis, - and likewise for the other branches. Add bhs as an alias for bcc, - and likewise for the size variants. Add dbhs as an alias for - dbcc. - -Fri Aug 11 13:40:24 1995 Jeff Law (law@snake.cs.utah.edu) - - * sh-opc.h (FP sts instructions): Update to match reality. - -Mon Aug 7 16:12:58 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-dis.c: (fpcr_names): Add % before all register names. - (reg_names): Likewise. - (print_insn_arg): Don't explicitly print % before register names. - Add % before register names in static array names. In case 'r', - print data registers as `@(Dn)', not `Dn@'. When printing a - memory address, don't print @# before it. - (print_indexed): Change base_disp and outer_disp from int to - bfd_vma. Print using MIT syntax, not mutant invalid Motorola - syntax. Sign extend 8 byte displacement correctly. - (print_base): Print using MIT syntax. Print zpc when appropriate. - Change parameter disp from int to bfd_vma. - - * m68k-opc.c (m68k_opcode_aliases): Add jsrl and jsrs as aliases - for jsr. - -Mon Aug 7 02:21:40 1995 Jeff Law (law@snake.cs.utah.edu) - - * sh-dis.c (print_insn_shx): Handle new operand types F_REG_N, - F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N. - * sh-opc.h (sh_arg_type): Add new operand types. - (sh_table): Add new opcodes from SH3E Floating Point ISA. - -Sat Aug 5 16:50:14 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (distclean): Remove generated file config.h. - -Sat Aug 5 16:50:14 1995 Fred Fish <fnf@cygnus.com> - - * Makefile.in (distclean): Remove generated file config.h. - -Wed Aug 2 18:33:40 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: New file, holding tables from include/opcode/m68k.h. - Clean up tables. - * m68k-dis.c: Remove BREAK_UP_BIG_DECL stuff. - (opcode): Remove. - (print_insn_m68k): Change d to be const. Use m68k_numopcodes - rather than numopcodes. Use m68k_opcodes rather than removed - opcode function. Don't check F_ALIAS. - (print_insn_arg): Change first parameter to be const char *. - * Makefile.in (ALL_MACHINES): Add m68k-opc.o. - (m68k-opc.o): New target. - * configure.in: Build m68k-opc.o for bfd_m68k_arch. - * configure: Rebuild. - -Wed Aug 2 08:23:38 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-dis.c (HASH_SIZE, HASH_INSN): Define. - (opcode_bits, opcode_hash_table): New variables. - (opcodes_initialized): Renamed from opcodes_sorted. - (build_hash_table): New function. - (is_delayed_branch): Use hash table. - (print_insn): Renamed from print_insn_sparc, made static. - Build and use hash table. If !sparc64, ignore sparc64 insns, - and vice-versa if sparc64. - (print_insn_sparc, print_insn_sparc64): New functions. - (compare_opcodes): Move sparc64 opcodes to end. - Print commutative insns with constant second. - * sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS. - -Tue Aug 1 00:12:49 1995 Ian Lance Taylor <ian@cygnus.com> - - * sh-dis.c (print_insn_shx): Remove unused local dslot. Use - print_address_func for A_BDISP12 and A_BDISP8. Correct test which - avoids printing a delay slot in a delay slot. - * sh-opc.h (sh_table): Fully bracket last entry. - -Mon Jul 31 12:04:47 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc-opc.c (sllx, srax, srlx): Fix disassembly. - -Wed Jul 12 00:59:34 1995 Ken Raeburn <raeburn@kr-pc.cygnus.com> - - * configure.in: Get host_makefile_frag from ${srcdir}. - - * configure.in: Autoconfiscated. Check for string[s].h. Create - config.h from config.in. Don't set up sysdep.h link. - * sysdep.h: New file. - * configure, config.in: New files, generated from configure.in. - * Makefile.in: Updated to be processed autoconf-style. - (distclean): Keep sysdep.h. Remove config.log and config.cache. - (Makefile): Depend on config.status. - (config.status): New rule. - * configure.bat: Update Makefile substitutions. - -Tue Jul 11 14:23:37 1995 Jeff Spiegel <jeffs@lsil.com> - - * mips-opc.c (L1): Define. - (mips_opcodes): Add R4010 instructions: flushi, flushd, flushid, - addciu, madd, maddu, ffc, ffs, msub, msubu, selsi, selsr, waiti, - and wb. - -Tue Jul 11 11:49:49 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu - if ISA 3 and addu otherwise, replacing or, since some MIPS chips - have multiple add units but only a single logical unit. - - * ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3, - shifted by 18, without any insertion or extraction function. - (insert_cr, extract_cr): Remove. - -Wed Jun 21 20:05:39 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k-dis.c (print_insn_arg, print_indexed): Print "%" before - register names. - -Thu Jun 15 17:23:31 1995 Stan Shebs <shebs@andros.cygnus.com> - - * mpw-config.in: Add sh and i386 configs, remove sparc config. - * sh-opc.h: Add copyright. - -Mon Jun 5 03:30:43 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com> - - * Makefile.in (crunch-m68k): Delete extra target accidentally - checked in a while ago. - -Wed May 24 16:22:13 1995 Jim Wilson <wilson@chestnut.cygnus.com> - - * sh-opc.h (sh_table): Add SH3 support. - -Wed May 24 14:16:08 1995 Steve Chamberlain <sac@slash.cygnus.com> - - * sh-opc.h: Added bsrf and braf. - -Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) - - * arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete - bogus [ls]fm{ea,fd} patterns. - - * arm-opc.h (arm_opcodes): Correct typos in stm, ldm, std, and ldc. - * arm-dis.c (print_insn_arm): Make GIVEN a parameter, don't try and - initialize it from memory. Make function static. - (print_insn_{big,little}_arm): New functions. - * disassemble.c (disassembler, case bfd_arch_arm): Disassemble for - the correct endianness. - -Mon Apr 24 14:18:05 1995 Jason Molenda (crash@phydeaux.cygnus.com> - - * sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from - enum list. - -Wed Apr 19 14:07:03 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * m68k-dis.c (opcode): Finish change made by Kung Hsu on April - 17th, so that it builds again using GCC as the compiler. - -Tue Apr 18 12:14:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * mips-dis.c (print_insn_little_mips): Cast return value from - bfd_getl32 from bfd_vma to unsigned long, because _print_insn_mips - expects an unsigned long, and that might be fewer words of - argument storage (e.g., if bfd_vma is long long on a 32-bit - machine). - (print_insn_big_mips): Likewise with bfd_getb32 value. - (_print_insn_mips): Now static. - -Mon Apr 17 12:23:28 1995 Kung Hsu <kung@rtl.cygnus.com> - - * m68k-dis.c: Take out #define BREAK_UP_BIG_DECL kludge, because - gcc memory hog problem with initializer is fixed. - -Mon Apr 10 15:55:01 1995 Stan Shebs <shebs@andros.cygnus.com> - - Merge in support for Mac MPW as a host. - (Old change descriptions retained for informational value.) - - * mpw-config.in (archname): Compute from the config. - (BFD_MACHINES, ARCHDEFS): Put into mk.tmp. - - * mpw-config.in (target_arch): Compute from canonical target. - (m68k, mips, powerpc, sparc): Add architectures. - * mpw-make.in (disassemble.c.o): Add. - (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far). - - * mpw-config.in (BFD_MACHINES): Set to a default value. - * mpw-make.in (BFD_MACHINES): Remove wired-in value. - - * mpw-make.in (CSEARCH): Add extra-include to search path. - - * mpw-config.in (varargs.h): Don't create. - (sysdep.h): Create using forward-include. - * mpw-make.in (CSEARCH): Add include/mpw to search path. - - * mpw-config.in: New file, MPW version of configure.in. - * mpw-make.in: New file, MPW version of Makefile.in. - -Fri Mar 31 14:23:38 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * alpha-dis.c (print_insn_alpha): Put empty statement after - default label. - -Tue Mar 21 10:51:40 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa-dis.c (sign_extend): Delete, redundant with libhppa.h version. - (low_sign_extend): Likewise. - (get_field): Delete unused function. - (set_field, deposit_14, deposit_21): Likewise. - -Fri Mar 17 15:55:53 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * i386-dis.c: Support for more pentium opcodes. From Guy Harris - (guy@netapp.com). - -Tue Mar 14 00:52:57 1995 Ken Raeburn (raeburn@kr-pc.cygnus.com) - - Sat Feb 11 17:22:41 1995 Klaus Kaempf (kkaempf@didymus.rmi.de) - - * alpha-opc.h (OSF_ASMCODE): define - print pal-code names as defined in App C of the - Alpha Architecture Reference Manual - - * alpha-dis.c: cleaned up output - print stylized code forms as defined in App A.4.3 of the - Alpha Architecture Reference Manual - -Wed Mar 8 15:21:14 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add new mips4 instructions. Don't set INSN_RFE for - `rfe'. - * mips-dis.c (print_insn_arg): Handle new argument types 'h', 'R', - 'N', and 'M'. - -Wed Mar 8 02:54:05 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k-dis.c (opcode): New function. Returns address of opcode - table entry given index, even if the opcode table was split to - work around gcc bugs. - (print_insn_m68k): Call opcode instead of referencing m68k_opcodes - directly. - (BREAK_UP_BIG_DECL): Make secondary array static and const. - (reg_names): Now const. - (print_insn_arg): Arrays cacheFieldName and names now const. - (print_indexed): Array scales now const. - -Tue Mar 7 16:41:21 1995 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c: Sort recently added instructions by minor opcode - number within major opcode number. - -Mon Mar 6 10:04:36 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa-dis.c: Include libhppa.h. - -Fri Feb 24 19:15:36 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Change dli to use M_DLI, and add dla. - -Mon Feb 20 23:54:38 1995 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * Makefile.in (ALL_MACHINES): Add w65-dis.o. - -Thu Feb 16 17:34:41 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add r4650 mul instruction. - -Wed Feb 15 15:45:20 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c: Add uld and usd macros for unaligned double load and - store. - -Tue Feb 14 13:17:37 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci, - mfdcr, mtdcr, icbt, iccci. - -Thu Feb 9 12:28:13 1995 Stan Shebs <shebs@andros.cygnus.com> - - * i960-dis.c (struct tabent, struct sparse_tabent): Change the - signed char fields to shorts, more portable. - -Wed Feb 8 17:29:29 1995 Stan Shebs <shebs@andros.cygnus.com> - - * i960-dis.c (struct tabent, struct sparse_tabent): Declare the - char fields as signed chars, since they may have negative values. - -Mon Feb 6 10:52:06 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * i386-dis.c (dis386_twobyte): Add cpuid, From Charles Hannum - (mycroft@netbsd.org). - -Mon Jan 30 12:38:00 1995 Ian Lance Taylor <ian@cygnus.com> - - From "Logg, Ed" <elogg@ea.com>: - * ppc-opc.c (extract_bdm): Correct parenthezisation. - * ppc-dis.c (print_insn_powerpc): Print .long before unrecognized - value. - -Thu Jan 26 18:32:08 1995 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c: Changes based on patch from David Edelsohn - <edelsohn@mhpcc.edu>. - (powerpc_operands): Add operands SPRBAT and SPRG. Split TBR out of - SPR. - (FXM_MASK): Define. - (insert_tbr): New static function. - (extract_tbr): New static function. - (XFXFXM_MASK, XFXM): Define. - (XSPRBAT_MASK, XSPRG_MASK): Define. - (powerpc_opcodes): Add instructions to access special registers by - name. Add mtcr and mftbu. - -Tue Jan 17 10:56:43 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips-opc.c (P3): Define. - (mips_opcodes): Add mad and madu. - -Sun Jan 15 16:32:59 1995 Steve Chamberlain <sac@splat> - - * configure.in: Add W65 support. - * disassemble.c: Likewise. - * w65-opc.h, w65-dis.c: New files. - -Wed Dec 28 22:15:33 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Add support for 2 bit - immediates. - -Tue Dec 20 11:25:12 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips-opc.c: Add dli as a synonym for li. - -Thu Dec 8 18:23:31 1994 Ken Raeburn <raeburn@cujo.cygnus.com> - - * alpha-dis.c (print_insn_alpha): Handle call_pal instruction, and - print something for reserved opcode values, even if it won't - assemble again. - - * mips-dis.c (_print_insn_mips): When initializing, shift right - and mask, to avoid sign extension problems on the Alpha. - - * m68k-dis.c (print_insn_arg, case 'J'): Handle buscr and pcr - control registers. - -Wed Nov 23 22:34:51 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * sh-opc.h (mov.l gbr): Get direction right. - * sh-dis.c (print_insn_shx): New function. - (print_insn_shl, print_insn_sh): Call print_insn_shx to - print opcodes with right byte order. - -Thu Nov 3 19:32:22 1994 Ken Raeburn <raeburn@cujo.cygnus.com> - - * ns32k-dis.c (struct ns32k_option): Renamed from struct option, - to avoid conflicts with getopt. - -Mon Oct 31 18:48:10 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * hppa-dis.c (print_insn_hppa): Read the instruction using - bfd_getb32, so that it works on a little endian or 64 bit host. - Remove unused local variable op. - -Tue Oct 25 17:07:57 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips-opc.c: Use or instead of addu for pseudo-op move, since - addu does not work correctly if -mips3. - -Wed Oct 19 13:40:16 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * a29k-dis.c (print_special): Add special register names defined - on 29030, 29040 and 29050. - (print_insn): Handle new operand type 'I'. - -Wed Oct 12 11:59:55 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * Makefile.in (INSTALL): Use top level install.sh script. - -Wed Oct 5 19:16:29 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * sparc-dis.c: Rewrite to use bitfields, rather than a union, so - that it works on a little endian host. - -Tue Oct 4 12:14:21 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * configure.in: Use ${config_shell} when running config.bfd. - -Wed Sep 21 18:49:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-opc.c (mips_opcodes): "dabs" is only available with -mips3. - -Thu Sep 15 16:30:22 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * a29k-dis.c (print_insn): Print the opcode. - -Wed Sep 14 17:52:14 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-opc.c (mips_opcodes): Set WR_t for sc and scd. - -Sun Sep 11 22:32:17 1994 Jeff Law (law@snake.cs.utah.edu) - - * hppa-dis.c (reg_names): Use r26-r23 for arg0-arg3. - -Tue Sep 6 11:37:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions - which store a value into memory. - -Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) - - * configure.in, Makefile.in, disassemble.c: Add support for the ARM. - * arm-dis.c, arm-opc.h: New files. - -Fri Aug 5 14:00:05 1994 Stan Shebs (shebs@andros.cygnus.com) - - * Makefile.in (ns32k-dis.o): Add dependency. - * ns32k-dis.c (print_insn_arg): Declare initialized local as - string, not as array of chars. - -Thu Jul 28 18:14:16 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * sparc-dis.c (print_insn_sparc): Handle new operand type 'x'. - - * sparc-opc.c: Added sparclite extended FP operations, and - versions of v9 impdep* instructions permitting specification of - the OPF field. - -Tue Jul 26 16:36:03 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i960-dis.c (reg_names): Now const. - (struct sparse_tabent): New type, copied from array type in mem - function. - (ctrl): Local static array ctrl_tab now const. - (cobr): Local static array cobr_tab now const. - (mem): Local variables reg1, reg2, reg3 now point to const. Local - static variable mem_tab no longer explicitly initialized. Changed - mem_init to const array of struct sparse_tabent. - (reg): Local static variable reg_tab no longer explicitly - initialized. Changed reg_init to const array of struct - sparse_tabent. - (ea): Local static array scale_tab now const. - - * i960-dis.c (reg): Added i960JX instructions to reg_init table. - (REG_MAX): Updated. - -Tue Jul 19 21:00:00 1994 DJ Delorie (dj@ctron.com) - - * configure.bat: the disassember needs to be enabled for - "objdump -d" to work in djgpp. - -Wed Jul 13 18:01:58 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * ns32k-dis.c: Deleted all code in "#ifdef GDB". - (invalid_float): Enabled general version, doesn't require running - on ns32k host. Changed to take char* argument, and test for - explicitly specified sizes, instead of using sizeof() on host CPU - types. - (INVALID_FLOAT): Cast first argument. - (opt_u, opt_U, opt_O, opt_C, opt_S, list_P532, list_M532, - list_P032, list_M032): Now const. - (optlist, list_search): Made appropriate arguments now point to - const. - (print_insn_arg): Changed static array of one-character-string - pointers into a static const array of characters; fixed sprintf - statement accordingly. - -Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au) - - * ns32k-dis.c: Semi-new file. Had apparently been dropped - from distribution. A ns32k-dis.c from a previous distribution has - been brought up to date and supports the new interface. - - * disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k. - - * configure.in: add bfd_ns32k_arch target support. - - * Makefile.in: add ns32k-dis.o to ALL_MACHINES. - Add ns32k-dis.c to CFILES. Add dependencies for ns32k-dis.o. - -Wed Jun 29 22:10:37 1994 Steve Chamberlain (sac@cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Get 16bit branch - disassembly right. - -Tue Jun 28 13:22:06 1994 Stan Shebs (shebs@andros.cygnus.com) - - * h8300-dis.c, mips-dis.c: Don't use true and false. - -Thu Jun 23 12:53:19 1994 David J. Mackenzie (djm@rtl.cygnus.com) - - * configure.in: Change --with-targets to --enable-targets. - -Wed Jun 22 13:38:32 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips-dis.c (_print_insn_mips): Build a static hash table mapping - opcodes to the first instruction with that opcode, to speed - disassembly of large files. From ralphc@pyramid.com (Ralph - Campbell). - -Tue Jun 7 12:49:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * Makefile.in (mostlyclean): Fix typo (was mostyclean). - -Wed May 11 22:32:00 1994 DJ Delorie (dj@ctron.com) - - * configure.bat: update to latest makefile.in - -Sat May 7 17:13:21 1994 Steve Chamberlain (sac@cygnus.com) - - * a29k-dis.c (print_insn): Print 'x' type operand in hex. - * h8300-dis.c (bfd_h8_disassemble): Print 16bit rels correctly. - * sh-dis.c (print_insn_sh): Don't recur endlessly if delay - slot insn is in a delay slot. - * z8k-opc.h: (resflg): Fix patterns. - * h8500-opc.h Fix CR insn patterns. - -Fri May 6 14:34:46 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and - "cmpl" before POWER versions, so that gas -many uses them. - -Thu Apr 28 18:32:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * disassemble.c: New file. - * Makefile.in (OFILES): Add disassemble.o. - (disassemble.o): Provide dependencies; compile with $(ARCHDEFS). - * configure.in: Define ARCHDEFS in Makefile. Code taken from - binutils/configure.in. - - * m68k-dis.c (print_insn_m68k): If F_ALIAS flag is set, skip the - opcode being examined. - -Thu Apr 21 17:08:40 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS. - (insert_ral, insert_ram, insert_ras): New functions. - (powerpc_opcodes): Use RAL for load with update, RAM for lmw, and - RAS for store with update. - -Sat Apr 16 23:41:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn - (edelsohn@npac.syr.edu). - -Wed Apr 6 17:11:45 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c (mips_opcodes): Correct operands of "nor" with an - immediate argument. - -Mon Apr 4 16:30:46 1994 Doug Evans (dje@canuck.cygnus.com) - - * sparc-opc.c (sparc_opcodes): Fix "rd %fprs,%l0". - -Mon Apr 4 13:22:00 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_operands): The signedp field has been - removed, so don't initialize it. Set the PPC_OPERAND_SIGNED flag - instead. Add new operand SISIGNOPT. - (powerpc_opcodes): For lis, liu, addis, and cau use SISIGNOPT. - Based on patch from David Edelsohn (edelsohn@npac.syr.edu). - * ppc-dis.c (print_insn_powerpc): Check PPC_OPERAND_SIGNED rather - than signedp field. - -Wed Mar 30 00:31:49 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * i386-dis.c (struct private): Renamed to dis_private. `private' - is a reserved word for dynix cc. - -Mon Mar 28 13:00:15 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * configure.in: Change error message to refer to bfd/config.bfd - rather than bfd/configure.in. - -Mon Mar 28 12:28:30 1994 David Edelsohn (edelsohn@npac.syr.edu) - - * ppc-opc.c: Define POWER2 as short alias flag. - (powerpc_opcodes): Add POWER/2 opcodes lfq*, stfq*, fcir[z], and - fsqrt. - -Wed Mar 23 12:23:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i960-dis.c (print_insn_i960): Don't read a second word for - opcodes 0, 1, 2 and 3. - -Wed Mar 16 15:37:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * configure.in: Don't build m68881-ext.o for bfd_m68k_arch. - -Mon Mar 14 14:53:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m68881-ext.c: Removed; no longer used. - * Makefile.in: Changed accordingly. - - * m68k-dis.c (ext_format_68881): Don't declare. - (print_insn_m68k): If an instruction uses place 'i', it uses at - least four fixed bytes. - (print_insn_arg): Don't bump p by 2 for case 'I', place 'i'. For - extended float, convert to double using floatformat_to_double, not - ieee_extended_to_double, and fetch the data before converting it. - -Tue Mar 8 18:12:25 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: It's sqrt.s, not sqrt.w. From - davidj@ICSI.Berkeley.EDU (David Johnson). - -Tue Feb 8 16:55:27 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_opcodes): The POWER uses bdn[l][a] where the - PowerPC uses bdnz[l][a]. - -Tue Feb 8 00:32:28 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * dis-buf.c, i386-dis.c: Include sysdep.h. - -Mon Feb 7 19:22:23 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * configure.in (bfd_powerpc_arch): Use ppc-dis.o and ppc-opc.o. - - * ppc-opc.c (powerpc_opcodes): Mark POWER instructions supported - by Motorola PowerPC 601 with PPC_OPCODE_601. - * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): - Disassemble Motorola PowerPC 601 instructions as well as normal - PowerPC instructions. - -Sun Feb 6 07:45:17 1994 Jim Kingdon (kingdon@lioth.cygnus.com) - - * i960-dis.c (reg, mem): Just use a static array instead of - calling xmalloc. - -Sat Feb 5 00:04:02 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): For '?' and '@' only adjust the - condition name index if this is for a negated condition. - - * hppa-dis.c (print_insn_hppa): No space before 'H' operand. - Floating point format for 'H' operand is backwards from normal - case (0 == double, 1 == single). For '4', '6', '7', '9', and '8' - operands (fmpyadd and fmpysub), handle bizarre register - translation correctly for single precision format. - - * hppa-dis.c (print_insn_hppa): Do not emit a space after 'F' - or 'I' operands if the next format specifier is 'M' (fcmp - condition completer). - -Feb 4 23:38:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c (powerpc_operands): New operand type MBE to handle a - single number giving a bitmask for the MB and ME fields of an M - form instruction. Change NB to accept 32, and turn it into 0; - also turn 0 into 32 when disassembling. Seperated SH from NB. - (insert_mbe, extract_mbe): New functions. - (insert_nb, extract_nb): New functions. - (SC_MASK): Mask out SA and LK bits. - (powerpc_opcodes): Change "cal" to use RT, D, RA rather than RT, - RA, SI. Change "liu" and "cau" to use UI rather than SI. Mark - "bctr" and "bctrl" as accepted by POWER. Change "rlwimi", - "rlimi", "rlwimi.", "rlimi.", "rlwinm", "rlinm", "rlwinm.", - "rlinm.", "rlmi", "rlmi.", "rlwnm", "rlnm", "rlwnm.", "rlnm." to - use MBE rather than MB. Add "mfmq" and "mtmq" POWER instructions. - (powerpc_macros): Define table of macro definitions. - (powerpc_num_macros): Define. - - * ppc-dis.c (print_insn_powerpc): Don't skip optional operands - if PPC_OPERAND_NEXT is set. - -Sat Jan 22 23:10:07 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i960-dis.c (print_insn_i960): Make buffer bfd_byte instead of - char. Retrieve contents using bfd_getl32 instead of shifting. - -Fri Jan 21 19:01:39 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc-opc.c: New file. Opcode table for PowerPC, including - opcodes for POWER (RS/6000). - * ppc-dis.c: New file. PowerPC and Power (RS/6000) disassembler. - * Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o. - (CFILES): Add ppc-dis.c. - (ppc-dis.o, ppc-opc.o): New targets. - * configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch. - -Mon Jan 17 20:05:49 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template. - No space before 'u', 'f', or 'N'. - -Sun Jan 16 14:20:16 1994 Jim Kingdon (kingdon@deneb.cygnus.com) - - * i386-dis.c (print_insn_i386): Add FIXME comment regarding reading - farther than we should. - - * i386-dis.c (dis386): Use Yb and Yv for scasb and scasS. - -Thu Jan 6 12:38:05 1994 David J. Mackenzie (djm@thepub.cygnus.com) - - * sparc-dis.c m68k-dis.c alpha-dis.c a29k-dis.c: Fix comments. - -Wed Jan 5 11:56:21 1994 David J. Mackenzie (djm@thepub.cygnus.com) - - * i960-dis.c (print_insn_i960): Only read word2 if the instruction - needs it, to prevent reading past the end of a section. - -Wed Nov 17 17:20:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Use macro for j instruction, to support SVR4 PIC. - Removed t,A case for la; always use t,A(b) case. - -Mon Nov 8 12:37:36 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - From Ted Lemen <mellon@pepper.ncd.com> - * mips-dis.c (print_insn_arg): Handle 'k'. - * mips-opc.c: Make cache use k, not t. - -Sun Nov 7 23:52:34 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * alpha-opc.h, alpha-dis.c (print_insn_alpha): Add - FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct - FLOAT_FORMAT_CODE to put out floating point register names. - -Mon Nov 1 18:17:51 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Use macros for jal variants, to support SVR4 PIC. - -Thu Oct 28 17:42:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * a29k-dis.c (print_insn): Use 0x%08x, not 0x%8x. - -Wed Oct 27 11:48:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c (dsll, dsra, dsrl): Added '>' cases for shift counts - larger than 32. Moved dsxx32 variants first for disassembler. - -Mon Oct 25 11:33:14 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * z8kgen.c, z8k-opc.h: Add full lda information. - -Tue Oct 19 12:39:25 1993 Jeffrey A Law (law@cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): Do not emit a space after - movb instructions. Any necessary space will be emitted by - the code to handle nullification completers. - -Wed Oct 13 16:19:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Moved l.d down so that it disassembles as ldc1. - -Fri Oct 8 02:34:21 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * alpha-opc.h: Add ldl_l, fix typo for ldq_u. - * alpha-dis.c (print_insn_alpha): Add code for PAL_FORMAT_CODE. - -Tue Oct 5 17:47:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Correct lwu opcode value (book had it wrong). - -Thu Sep 30 11:26:18 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * z8k-dis.c (FETCH_DATA): get just the right amount of data. - (unpack_instr): Cope with ARG_IMM4M1 type instructions. - -Wed Sep 29 16:24:49 1993 K. Richard Pixley (rich@sendai.cygnus.com) - - * m88k-dis.c (m88kdis): comment change. Remove space after - printing mnemonic. - (printop): handle new arg types DEC and XREG for m88110. - -Tue Sep 28 19:20:16 1993 Jeffrey A Law (law@snake.cs.utah.edu) - - * hppa-dis.c (print_insn_hppa): Handle 'z' operand - type for absolute branch addresses. Delete special - "ble" and "be" code in 'W' operand code. - -Fri Sep 24 14:08:33 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Set hazard information correctly for branch - likely instructions. - -Fri Sep 17 04:41:17 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * alpha-dis.c (print_insn_alpha), alpha-opc.h: Fix bugs, use - info->fprintf_func for printing and info->print_address_func for - address output. - -Wed Sep 15 12:12:07 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Set INSN_TRAP for tXX instructions. - -Thu Sep 9 10:11:27 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): - Corrected second case of "b" for disassembler. - -Tue Sep 7 14:25:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-dis.c, m88k-dis.c: Don't include libbfd.h. Changed calls - to BFD swapping routines to correspond to BFD name changes. - -Thu Sep 2 10:35:25 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Change div machine instruction to be z,s,t rather - than s,t. Change div macro to be d,v,t rather than d,s,t. - Likewise for divu, ddiv, ddivu. Added z,s,t case for drem, dremu, - rem and remu which generates only the corresponding div - instruction. This is for compatibility with the MIPS assembler, - which only generates the simple machine instruction when an - explicit destination of $0 is used. - * mips-dis.c (print_insn_arg): Handle 'z' (always register zero). - -Thu Aug 26 17:41:44 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set - WR_31 hazard for bal, bgezal, bltzal. - -Thu Aug 26 17:20:02 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * hppa-dis.c (print_insn_hppa): Use print function - from within the disassemble_info, not fprintf_filtered. - -Wed Aug 25 13:51:40 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa-dis.c (print_insn_hppa): Handle '|' like '>'. (From Jeff - Law, law@cs.utah.edu.) - -Mon Aug 23 12:44:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c ("absu"): Removed. - ("dabs"): Added. - -Fri Aug 20 10:52:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Added r6000 and r4000 instructions and macros. - Changed hazard information to distinguish between memory load - delays and coprocessor load delays. - -Wed Aug 18 15:39:23 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. - -Tue Aug 17 09:44:42 1993 David J. Mackenzie (djm@thepub.cygnus.com) - - * configure.in: Don't pass cpu to config.bfd. - -Tue Aug 17 12:23:52 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m88k-dis.c (m88kdis): Make class unsigned. - -Thu Aug 12 15:08:18 1993 Ian Lance Taylor (ian@cygnus.com) - - * alpha-dis.c (print_insn_alpha): One branch format case was - missing the instruction name. - -Wed Aug 11 19:29:39 1993 David J. Mackenzie (djm@thepub.cygnus.com) - - * Makefile.in (ALL_MACHINES): Renamed from DIS_LIBS. - Add the arch-specific auxiliary files. - (OFILES): Remove the arch-specific auxiliary files - and use BFD_MACHINES instead of DIS_LIBS. - * configure.in: Set BFD_MACHINES based on --with-targets option. - -Thu Aug 12 12:04:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: Added lwc1 E,A(b) to go with lwc1 T,A(b). Similarly - for swc1. - -Sun Aug 8 15:09:30 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * sparc-opc.c: Change CONST to const to deal with gcc - -Dconst=__const -traditional. - -Fri Aug 6 10:58:55 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Took - coprocessor instructions out of #if 0, and made them use new - argument type "C". - -Thu Aug 5 17:11:06 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * sparc-dis.c: Include ansidecl.h before opcodes/sparc.h. - -Fri Jul 30 18:48:15 1993 John Gilmore (gnu@cygnus.com) - - * sparc-opc.c: Add F_JSR, F_UNBR, or F_CONDBR flags to each branch - instruction, for use by the disassembler. - - * sparc-dis.c (SEX): Add sign extension macro. Replace many - hand-coded sign extensions that depended on 32-bit host ints. - FIXME, we still depend on big-endian host bitfield ordering. - (sparc_print_insn): Set the insn_info_valid field, and the - other fields that describe the instruction being printed. - -Tue Jul 27 17:04:58 1993 Jim Wilson (wilson@sphagnum.cygnus.com) - - * sparc-opc.c (call): Accept all 6 addressing modes valid for - `jmp' instead of just one of them. - -Wed Jul 21 11:43:32 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa-dis.c: Move floating registers from reg_names to fp_reg_names. - (fput_fp_reg_r): Renamed from fput_reg_r. - (fput_fp_reg): New function. - (print_insn_hppa): Use fput_fp_reg{,_r} where appropriate. - - * hppa-dis.c (print_insn_hppa, cases 'a', 'd'): Print space afterwards. - - * hppa-dis.c (print_insn_hppa, case 'd'): Use GET_COND not GET_FIELD. - -Mon Jul 19 13:52:21 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa-dis.c (print_insn_hppa): Use extract_5r_store for 'r'. - - * hppa-dis.c (print_insn_hppa, case '>'): If next character is 'n', - don't output a space. - - * hppa-dis.c (float_format_names): 10 is undefined, and 11 is quad. - -Sun Jul 18 16:30:02 1993 Jim Kingdon (kingdon@rtl.cygnus.com) - - * mips-opc.c: New file, containing opcode table from - ../include/opcode/mips.h. - * Makefile.in: Add it. - -Thu Jul 15 12:37:05 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m88k-dis.c: New file, moved in from gdb and changed to use the - new dis-asm.h disassembler interface. - * Makefile.in (DIS_LIBS): Added m88k-dis.o. - (m88k-dis.o): New target. - -Tue Jul 13 10:04:16 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips-dis.c (print_insn_arg, _print_insn_mips): Made pointer to - argument string const char * to correspond to opcode/mips.h. - -Tue Jul 6 15:18:37 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips-dis.c: Updated to account for name changes in new version - of opcode/mips.h. - * Makefile.in: Added header file dependencies. - -Sat Jul 3 23:47:56 1993 Doug Evans (dje@canuck.cygnus.com) - - * h8300-dis.c (bfd_h8_disassemble): Correct fetching of instruction. - -Thu Jul 1 12:23:38 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * m68k-dis.c (NEXTWORD, NEXTLONG): Use ((x) ^ 0x8000) - 0x8000 to sign - extend, rather than shifts. - -Sun Jun 20 20:56:56 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) - - * Makefile.in: Undo 15 June change. - -Fri Jun 18 14:15:15 1993 Per Bothner (bothner@deneb.cygnus.com) - - * m68k-dis.c (print_insn_arg): Change return value to byte count - or error code. - * m68k-dis.c: Re-write to detect invalid operands before - printing anything, so we can handle this the same way we - handle invalid opcodes. - -Thu Jun 17 15:01:36 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * sh-dis.c, sh-opc.h: Understand some more opcodes. - -Wed Jun 16 13:48:05 1993 Ian Lance Taylor (ian@cygnus.com) - - * hppa-dis.c: Include <ansidecl.h> and sysdep.h before other - header files. - -Tue Jun 15 21:45:26 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * sparc-dis.c: Don't declare qsort, since sysdep.h might. - - * configure.in: Do make sysdep.h link. - * Makefile.in: Search ../include. Don't search ../bfd. - -Tue Jun 15 13:36:10 1993 Stu Grossman (grossman@cygnus.com) - - Changes from Jeff Law, law@cs.utah.edu: - * hppa-dis.c: Fix typo. 'a' and 'd' were reversed. - Do not print a space before the completers specified by - 'a' and 'd'. - -Fri Jun 11 18:40:21 1993 Ken Raeburn (raeburn@cygnus.com) - - * mips-dis.c: No longer need to bomb out if HOST_64_BIT is - defined, since gdb has been fixed. - - Changes from Jeff Law, law@cs.utah.edu: - * hppa-dis.c (print_insn_hppa): Last argument to fput_reg, - fput_reg_r, fput_creg, fput_const, and fputs_filtered should - be a *disassemble_info, not a *FILE. - * hppa-dis.c: Support 'd', '!', and 'a'. - * hppa-dis.c: Support 's' to extract a 2 bit space register. - * hppa-dis.c: Delete cases which are no longer needed. - -Fri Jun 11 07:53:48 1993 Jim Kingdon (kingdon@cygnus.com) - - * m68k-dis.c (print_insn_{m68k,arg}): Add MMU codes. - -Tue Jun 8 12:25:01 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * h8300-dis.c: New file, removed from bfd/cpu-h8300.c, with - H8/300-H opcodes. - -Mon Jun 7 12:58:49 1993 Per Bothner (bothner@rtl.cygnus.com) - - * Makefile.in (CSEARCH): Add -I../bfd for sysdep.h and bfd.h. - * configure.in: No longer need to configure to get sysdep.h. - -Thu Jun 3 15:56:49 1993 Stu Grossman (grossman@cygnus.com) - - * Patches from Jeffrey Law <law@cs.utah.edu>. - * hppa-dis.c: Support 'I', 'J', and 'K' in output - templates for 1.1 FP computational instructions. - -Tue May 25 13:05:48 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * h8500-dis.c (print_insn_h8500): Address argument is type - bfd_vma. - * z8k-dis.c (print_insn_z8k, print_insn_z8001, print_insn_z8002): - Ditto. - - * h8500-opc.h (addr_class_type): No comma at end of enumerator. - * sh-opc.h (sh_nibble_type, sh_arg_type): Ditto. - - * sparc-dis.c (compare_opcodes): Move static declaration to - top-level. - -Fri May 21 14:17:37 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * sparc-dis.c (print_insn_sparc): Implement 'n' argument for unimp - instruction, remove unimp hack from 'l' argument. - -Wed May 19 15:35:54 1993 Stu Grossman (grossman@cygnus.com) - - * z8k-dis.c (fetch_data): Use unsigned char to make ancient gcc's - happy. - -Fri May 14 15:22:46 1993 Ian Lance Taylor (ian@cygnus.com) - - * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): - * mips-dis.c (print_insn_arg): Handle 'C' for general coprocessor - instructions. - -Fri May 14 00:09:14 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa-dis.c: Include dis-asm.h before sysdep.h. Changed some - arrays of string pointers to 2-d arrays of chars, to save - space. - -Thu May 6 20:51:17 1993 Fred Fish (fnf@cygnus.com) - - * a29k-dis.c, alpha-dis.c, i960-dis.c, sparc-dis.c, z8k-dis.c: - Cast second arg to read_memory_func to "bfd_byte *", as necessary. - -Tue May 4 20:31:10 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa-dis.c: New file from Utah, adapted to new disassembler - calling interface. - * Makefile.in: Include it. - -Mon Apr 26 18:17:42 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * sh-dis.c, sh-opc.h: New files. - -Fri Apr 23 18:51:22 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * alpha-dis.c, alpha-opc.h: New files. - -Tue Apr 6 12:54:08 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) - - * mips-dis.c: Sign extend 'j' and 'b' arguments, delta is a signed - value. - -Mon Apr 5 17:37:37 1993 John Gilmore (gnu@cygnus.com) - - * sparc-dis.c: Make "ta" the default trap instruction, "t" the alias. - -Fri Apr 2 07:24:27 1993 Ian Lance Taylor (ian@cygnus.com) - - * a29k-dis.c, sparc-dis.c, sparc-opc.c: Use CONST rather than - const. - -Thu Apr 1 11:20:43 1993 Jim Kingdon (kingdon@cygnus.com) - - * sparc-dis.c: Use fprintf_func a few places where I forgot, - and double percent signs a few places. - - * a29k-dis.c, i960-dis.c: New, merged from gdb and binutils. - - * i386-dis.c, m68k-dis.c, mips-dis.c, sparc-dis.c: - Use info->print_address_func not print_address. - - * dis-buf.c (generic_print_address): New function. - -Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * Makefile.in: Add sparc-dis.c. - sparc-dis.c: New file, merges binutils and gdb versions as follows: - From GDB: - Add `add' instruction to the set that get checked - for a preceding `sethi' in order to print an absolute address. - * (print_insn): Disassembly prefers real instructions. - (is_delayed_branch): Speed up. - * sparc-opc.c: Add ALIAS bit to aliases. Fix up opcode tables. - Still missing some float ops, and needs testing. - * sparc-pinsn.c (print_insn): Eliminate 'set' test, subsumed by - F_ALIAS. Use printf, not fprintf, when not passing a file - pointer... - (compare_opcodes): Check that identical instructions have - identical opcodes, complain otherwise. - From binutils: - * New 'm' arg. - * Include reg_names. - From neither: - Use dis-asm.h/read_memory_func interface. - -Wed Mar 31 20:49:06 1993 K. Richard Pixley (rich@rtl.cygnus.com) - - * h8500-dis.c, i386-dis.c, m68k-dis.c, z8k-dis.c (fetch_data): - deliberately return non-zero to setjmp from longjmp. Otherwise - this code fails to compile. - -Wed Mar 31 17:04:31 1993 Stu Grossman (grossman@cygnus.com) - - * m68k-dis.c: Fix prototype for fetch_arg(). - -Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * dis-buf.c: New file, for new read_memory_func interface. - Makefile.in (OFILES): Include it. - m68k-dis.c, i386-dis.c, h8500-dis.c, mips-dis.c, z8k-dis.c: - Use new read_memory_func interface. - -Mon Mar 29 14:02:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8500-dis.c (print_insn_h8500): Get sign of fp offsets right. - * h8500-opc.h: Fix couple of opcodes. - -Wed Mar 24 02:03:36 1993 david d `zoo' zuhn (zoo at poseidon.cygnus.com) - - * Makefile.in: add dvi & installcheck targets - -Mon Mar 22 18:55:04 1993 John Gilmore (gnu@cygnus.com) - - * Makefile.in: Update for h8500-dis.c. - -Fri Mar 19 14:27:17 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8500-dis.c, h8500-opc.h: New files - -Thu Mar 18 14:12:37 1993 Per Bothner (bothner@rtl.cygnus.com) - - * mips-dis.c, z8k-dis.c: Converted to use interface defined in - ../include/dis-asm.h. - * m68k-dis.c: New file (merge of ../binutils/m68k-pinsn.c - and ../gdb/m68k-pinsn.c). - * i386-dis.c: New file (merge of ../binutils/i386-pinsn.c - and ../gdb/i386-pinsn.c). - * m68881-ext.c: New file. Moved definition of - ext_format ext_format_68881 from ../gdb/m68k-tdep.c. - * Makefile.in: Adjust for new files. - * i386-dis.c: Patches from John Hassey (hassey@dg-rtp.dg.com). - * m68k-dis.c: Recognize '9' placement code, so (say) pflush - can be dis-assembled. - -Wed Feb 17 09:19:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * mips-dis.c (print_insn_arg): Now returns void. - -Mon Jan 11 16:09:16 1993 Fred Fish (fnf@cygnus.com) - - * mips-dis.c (ansidecl.h): Include for benefit of sysdep.h - files that use the macros. - -Thu Jan 7 13:15:17 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips-dis.c: New file, from gdb/mips-pinsn.c. - * Makefile.in (DIS_LIBS): Added mips-dis.o. - (CFILES): Added mips-dis.c. - -Thu Jan 7 07:36:33 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c (print_insn_z8001, print_insn_z8002): new routines - * z8kgen.c, z8k-opc.h: fix sizes of some shifts. - -Tue Dec 22 15:42:44 1992 Per Bothner (bothner@rtl.cygnus.com) - - * Makefile.in: Improve *clean rules. - * configure.in: Allow a default host. - -Tue Nov 17 19:53:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) - - * Makefile.in: also use -I$(srcdir)/../bfd, since some sysdep - files include other sysdep files - -Thu Nov 12 16:10:37 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c z8k-opc.h z8kgen.c: checkpoint - -Fri Oct 9 04:56:05 1992 John Gilmore (gnu@cygnus.com) - - * configure.in: For host support, use ../bfd/configure.host - so it stays in sync with the ../bfd/hosts database. - -Thu Oct 1 23:38:54 1992 david d `zoo' zuhn (zoo at cirdan.cygnus.com) - - * configure.in: use cpu-vendor-os triple instead of nested cases - -Wed Sep 30 16:09:20 1992 Michael Werner (mtw@cygnus.com) - - * z8k-dis.c (unparse_instr): fix bug where opcode returned was - *always* the wrong one. - -Wed Sep 30 07:42:17 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8kgen.c: added copyright info - -Tue Sep 29 12:20:21 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c (unparse_instr): prettier tabs - * z8kgen.c z8k-opc.h: bug fixes in tables - -Fri Sep 25 12:50:32 1992 Stu Grossman (grossman at cygnus.com) - - * configure.in: Add ncr* configuration. - * z8k-dis.c (struct instr_data_s): Make instr_asmsrc char to make - picayune ANSI compilers happy. - -Sep 20 08:50:55 1992 Fred Fish (fnf@cygnus.com) - - * configure.in (i386): Make i386 and i486 synonymous for now. - * configure.in (i[34]86-*-sysv4): Add my_host definition. - -Fri Sep 18 17:01:23 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * Makefile.in (install): Fix typo. - -Fri Sep 18 02:04:24 1992 John Gilmore (gnu@cygnus.com) - - * Makefile.in (make): Remove obsolete crud. - (sparc-opc.o): Avoid Sun Make VPATH bug. - -Tue Sep 8 17:29:27 1992 K. Richard Pixley (rich@sendai.cygnus.com) - - * Makefile.in: since there are no SUBDIRS, remove rule and - references of subdir_do. - -Tue Sep 8 17:02:58 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * Makefile.in (install): Get the library name right here too. - Don't install bfd.h, since it's unrelated to this library. No - subdirs to recurse into, either. - (CFILES): The source file has a .c suffix, not .o. - - * sparc-opc.c: New file, moved from BFD. - * Makefile.in (OFILES): Build it. - -Thu Sep 3 16:59:20 1992 Michael Werner (mtw@cygnus.com) - - * z8k-dis.c: fixed forward refferences of some declarations. - -Mon Aug 31 16:09:45 1992 Michael Werner (mtw@cygnus.com) - - * Makefile.in: get the name of the library right - -Mon Aug 31 13:47:35 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * z8k-dis.c: knows how to disassemble z8k stuff - * z8k-opc.h: new file full of z8000 opcodes - -Fri Aug 28 15:38:03 1992 Ken Raeburn (raeburn@cygnus.com) - - * Renamed opc-sparc.c to sparc-opc.c for systems with short - filename constraints. - * Makefile.in: Updated to reflect change. - - -Local Variables: -version-control: never -End: diff --git a/contrib/binutils/opcodes/ChangeLog-9899 b/contrib/binutils/opcodes/ChangeLog-9899 deleted file mode 100644 index 3f8bf77..0000000 --- a/contrib/binutils/opcodes/ChangeLog-9899 +++ /dev/null @@ -1,1669 +0,0 @@ -1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (grps[]): Correct GRP5 FF/3 from "call" to "lcall". - -Wed Dec 1 03:34:53 1999 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c, m10300-dis.c: Add am33 support. - -Wed Nov 24 20:29:58 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c (unit_cond_names): Add PA2.0 unit condition names. - (print_insn_hppa): Handle 'B' operand. - -1999-11-22 Nick Clifton <nickc@cygnus.com> - - * d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction. - -1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-opc.c (I5): New. - (abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s - madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps, - pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New. - -Mon Nov 15 19:34:58 1999 Donald Lindsay <dlindsay@cygnus.com> - - * arm-dis.c (print_insn_arm): Added general purpose 'X' format. - * arm-opc.h (print_insn_arm): Added comment documenting - the 'X' format just added to arm-dis.c. - -1999-11-15 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-opc.c (la): Create a version that just uses addiu directly. - (dla): Expand to daddiu if possible. - -1999-11-11 Nick Clifton <nickc@cygnus.com> - - * mips-opc.c: Add ssnop pattern. - -1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER. - -1999-10-29 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c (mvtacc): Use format SHORT_AR not SHORT_AA - (d30v_format_tab): Define the SHORT_AR format. - -1999-10-28 Nick Clifton <nickc@cygnus.com> - - * mcore-dis.c: Remove spurious code introduced in previous delta. - -1999-10-27 Scott Bambrough <scottb@netwinder.org> - - * arm-dis.c: Include sysdep.h to prevent compile time warnings. - -1999-10-18 Michael Meissner <meissner@cygnus.com> - - * alpha-opc.c (alpha_operands): Fill in missing initializer. - (alpha_num_operands): Convert to unsigned. - (alpha_num_opcodes): Ditto. - (insert_rba): Declare unused arguments ATTRIBUTE_UNUSED. - (insert_rca): Ditto. - (insert_za): Ditto. - (insert_zb): Ditto. - (insert_zc): Ditto. - (extract_bdisp): Ditto. - (extract_jhint): Ditto. - (extract_ev6hwjhint): Ditto. - -Sun Oct 10 01:48:01 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> - - * hppa-dis.c (print_insn_hppa): Add new codes 'cc', 'cd', 'cC', - 'co', '@'. - - * hppa-dis.c (print_insn_hppa): Removed unused args. Fix '?W'. - - * hppa-dis.c (print_insn_hppa): Implement codes "?N", "?Q". - -Thu Oct 7 00:12:43 MDT 1999 Diego Novillo <dnovillo@cygnus.com> - - * d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for - rac/rachi instructions. - (d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi, - slae, st and st2w. - -1999-10-04 Doug Evans <devans@casey.cygnus.com> - - * fr30-asm.c, fr30-desc.h: Rebuild. - * m32r-asm.c, m32r-desc.c, m32r-desc.h: Rebuild. Add m32rx support. - * m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c: Ditto. - -1999-09-29 Nick Clifton <nickc@cygnus.com> - - * sh-opc.h: Fix bit patterns for several load and store - instructions. - -Thu Sep 23 08:27:20 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org - - * hppa-dis.c (print_insn_hppa): Replace 'B', 'M', 'g' and 'l' with - cleaner code using completer prefixes. Add 'Y'. - -Sun Sep 19 10:41:27 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c: (print_insn_hppa): Correct 'cJ', 'cc'. - - * hppa-dis.c (extract_22): New function. - - * hppa-dis.c (print_insn_hppa): Handle 'J', 'K', and 'cc'. - - * hppa-dis.c (print_insn_hppa): Handle 'fe' and 'cJ'. - - * hppa-dis.c (print_insn_hppa): Handle '#', 'd', and 'cq'. - - * hppa-dis.c (print_insn_hppa): Handle 'm', 'h', '='. - - * hppa-dis.c (print_insn_hppa): Handle 'X' operand. - - * hppa-dis.c (print_insn_hppa): Handle 'B' operand. - - * hppa-dis.c (print_insn_hppa): Handle 'M' and 'L' operands. - - * hppa-dis.c (print_insn_hppa): Handle 'l' operand. - - * hppa-dis.c (print_insn_hppa): Handle 'g' operand. - -Sat Sep 18 11:36:12 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c (print_insn_hppa): Output a space after 'X' completer. - - * hppa-dis.c: (print_insn_hppa): Do output a space before a 'v' - operand. - - * hppa-dis.c: (print_insn_hppa): Handle 'fX'. - - * hppa-dis.c: (print_insn_hppa): Add missing break after - FP register case. - - * hppa-dis.c: Finish constifying various completers, register - names, etc etc. - -1999-09-14 Michael Meissner <meissner@cygnus.com> - - * configure.in (Canonicalization of target names): Remove adding - ${CONFIG_SHELL} in front of $ac_config_sub, since autoconfig 2.14 - generates $ac_config_sub with a ${CONFIG_SHELL} already. - * configure: Regenerate. - -Tue Sep 7 13:50:32 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c (print_insn_hppa): Escape '%' in output strings. - - * hppa-dis.c (print_insn_hppa): Handle 'Z' argument. - -1999-09-07 Nick Clifton <nickc@cygnus.com> - - * sh-opc.h: Add mulu.w and muls.w patterns. These are the correct - names for the mulu and muls patterns. - -1999-09-04 Steve Chamberlain <sac@pobox.com> - - * pj-opc.c: New file. - * pj-dis.c: New file. - * disassemble.c (disassembler): Handle bfd_arch_pj. - * configure.in: Handle bfd_pj_arch. - * Makefile.am: Rebuild dependencies. - (CFILES): Add pj-dis.c and pj-opc.c. - (ALL_MACHINES): Add pj-dis.lo and pj-opc.lo. - * configure, Makefile.in: Rebuild. - -1999-09-04 H.J. Lu <hjl@gnu.org> - - * i386-dis.c (print_insn_i386): Set bytes_per_line to 7. - -Mon Aug 30 18:56:14 1999 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (fetch, fetch_m, ecb, wh64): RA must be R31. - -1999-08-04 Doug Evans <devans@casey.cygnus.com> - - * fr30-asm.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. - * m32r-asm.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. - * m32r-opinst.c: Rebuild. - -Sat Aug 28 00:27:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'. Prefix float - register args by 'f'. - - * hppa-dis.c (print_insn_hppa): Add args q, %, !, and |. - - * hppa-dis.c (MASK_10, read_write_names, add_compl_names, - extract_10U_store): New. - (print_insn_hppa): Add new completers. - - * hppa-dis.c (signed_unsigned_names,mix_half_names, - saturation_names): New. - (print_insn_hppa): Add completer codes 'a', 'ch', 'cH', 'cS', and 'c*'. - - * hppa-dis.c (print_insn_hppa): Place completers behind prefix 'c'. - - * hppa-dis.c (print_insn_hppa): Add cases for '.', '~'. '$'. and '!' - - * hppa-dis.c (print_insn_hppa): Look at next arg instead of bits - to decide to print a space. - -1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Add AMD athlon instruction support. - -1999-08-10 Ian Lance Taylor <ian@zembu.com> - - From Wally Iimura <iimura@microunity.com>: - * dis-buf.c (buffer_read_memory): Rewrite expression to avoid - overflow at end of address space. - (generic_print_address): Use sprintf_vma. - -1999-08-08 Ian Lance Taylor <ian@zembu.com> - - * Makefile.am: Rename .dep* files to DEP*. Change DEP variable to - MKDEP. Rebuild dependencies. - * Makefile.in: Rebuild. - -Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa-dis.c (compare_cond_64_names, cmpib_cond_64_names, - add_cond_64_names, wide_add_cond_names, logical_cond_64_names, - unit_cond_64_names, shift_cond_64_names, bb_cond_64_names): New. - (print_insn_hppa): Add 64 bit condition completers. - -Thu Aug 5 16:59:58 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa-dis.c (print_insn_hppa): Change condition args to use - '?' prefix. - -Wed Jul 28 04:33:58 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa-dis.c (print_insn_hppa): Remove unnecessary test in 'E' - code. - -1999-07-21 Ian Lance Taylor <ian@zembu.com> - - From Mark Elbrecht: - * configure.bat: Remove; obsolete. - -1999-07-11 Ian Lance Taylor <ian@zembu.com> - - * dis-buf.c: Add ATTRIBUTE_UNUSED as appropriate. - (generic_strcat_address): Add cast to avoid warning. - * i386-dis.c: Initialize all structure fields to avoid warnings. - Add ATTRIBUTE_UNUSED as appropriate. - -1999-07-08 Jakub Jelinek <jj@ultra.linux.cz> - - * sparc-dis.c (print_insn_sparc): Differentiate between - addition and oring when guessing symbol for comment. - -1999-07-05 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Display hex equivalent of rotated - constant. - -1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Mention intel mode specials in macro char comment. - -1999-06-21 Ian Lance Taylor <ian@zembu.com> - - * alpha-dis.c: Don't include <stdlib.h>. - * arm-dis.c: Include "sysdep.h". - * tic30-dis.c: Don't include <stdlib.h> or <string.h>. Include - "sysdep.h". - * Makefile.am: Rebuild dependencies. - * Makefile.in: Rebuild. - -1999-06-16 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Add detection of IMB and IMBRange - SWIs. - -1999-06-14 Nick Clifton <nickc@cygnus.com> & Drew Mosley <dmoseley@cygnus.com> - - * arm-dis.c (arm_regnames): Turn into a pointer to a register - name set. - (arm_regnames_standard): New variable: Array of ARM register - names according to ARM instruction set nomenclature. - (arm_regnames_apcs): New variable: Array of ARM register names - according to ARM Procedure Call Standard. - (arm_regnames_raw): New variable: Array of ARM register names - using just 'r' and the register number. - (arm_toggle_regnames): New function: Toggle the chosen register set - naming scheme. - (parse_disassembler_options): New function: Parse any target - disassembler command line options. - (print_insn_big_arm): Call parse_disassembler_options if any - are defined. - (print_insn_little_arm): Call parse_disassembler_options if any - are defined. - -1999-06-13 Ian Lance Taylor <ian@zembu.com> - - * i386-dis.c (FWAIT_OPCODE): Define. - (used_prefixes): New static variable. - (fetch_data): Don't print an error message if we have already - fetched some bytes successfully. - (ckprefix): Clear used_prefixes. Use FWAIT_OPCODE, not 0x9b. - (prefix_name): New static function. - (print_insn_i386): If setjmp fails, indicating a data error, but - we have managed to fetch some bytes, print the first one as a - prefix or a .byte pseudo-op. If fwait is followed by a non - floating point instruction, print the first prefix. Set - used_prefixes when prefixes are used. If any prefixes were not - used after disassembling the instruction, print the first prefix - instead of printing the instruction. - (putop): Set used_prefixes when prefixes are used. - (append_seg, OP_E, OP_G, OP_REG, OP_I, OP_sI, OP_J): Likewise. - (OP_DIR, OP_SIMD_Suffix): Likewise. - -1999-06-07 Jakub Jelinek <jj@ultra.linux.cz> - - * sparc-opc.c: Fix up set, setsw, setuw operand kinds. - Support signx %reg, clruw %reg. - -1999-06-07 Jakub Jelinek <jj@ultra.linux.cz> - - * sparc-opc.c: Add aliases Solaris as supports. - -Mon Jun 7 12:04:52 1999 Andreas Schwab <schwab@issan.cs.uni-dortmund.de> - - * Makefile.am (CFILES): Add arc-{dis,opc}.c and v850-{dis,opc}.c. - * Makefile.in: Regenerated. - -1999-06-03 Philip Blundell <philb@gnu.org> - - * arm-dis.c (print_insn_arm): Make LDRH/LDRB consistent with LDR - when target is PC-relative. - -1999-05-28 Linus Nordberg <linus.nordberg@canit.se> - - * m68k-opc.c: Rename MACL/MSACL to MAC/MSAC. Add MACM/MSACM. Add - MOVE MACSR,CCR. - - * m68k-dis.c (fetch_arg): Add places `n', `o'. - - * m68k-opc.c: Add MSAC, MACL, MOVE to/from ACC, MACSR, MASK. - Add mcf5206e to appropriate instructions. - Add alias for MAC, MSAC. - - * m68k-dis.c (print_insn_arg): Add formats `E', `G', `H' and place - `N'. - - * m68k-opc.c (m68k_opcodes): Add divsw, divsl, divuw, divul, macl, - macw, remsl, remul for mcf5307. Change mcf5200 --> mcf. - - * m68k-dis.c: Add format `u' and places `h', `m', `M'. - -1999-05-18 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (Ed): Define. - (dis386_twobyte_att, dis386_twobyte_intel): Use Ed for movd. - (Rw): Remove. - (OP_rm): Rename to OP_Rd. - (ONE): Remove. - (OP_ONE): Remove. - (putop): Add const to template and p. - (print_insn_x86): Delete. - (print_insn_i386): Merge old function print_insn_x86. Add const - to dp. - (struct dis386): Add const to name. - (dis386_att, dis386_intel): Add const. - (dis386_twobyte_att, dis386_twobyte_intel): Add const. - (names32, names16, names8, names_seg, index16): Add const. - (grps, prefix_user_table, float_reg): Add const. - (float_mem_att, float_mem_intel): Add const. - (oappend): Add const to s. - (OP_REG): Add const to s. - (ptr_reg): Add const to s. - (dofloat): Add const to dp. - (OP_C): Don't skip modrm, it's now done in OP_Rd. - (OP_D): Ditto. - (OP_T): Ditto. - (OP_Rd): Check for valid mod. Call Op_E to print. - (OP_E): Handle d_mode arg. Check for bad sfence,lea,lds etc. - (OP_MS): Check for valid mod. Call Op_EM to print. - (OP_3DNowSuffix): Set obufp and use oappend rather than - strcat. Call BadOp() for errors. - (OP_SIMD_Suffix): Likewise. - (BadOp): New function. - -1999-05-12 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (dis386_intel): Remove macro chars, except for - jEcxz. Change cWtR and cRtd to cW and cR. - (dis386_twobyte_intel): Remove macro chars here too. - (putop): Handle R and W macros for intel mode. - - * i386-dis.c (SIMD_Fixup): New function. - (dis386_twobyte_att): Use it on movlps and movhps, and change - Ev to EX on these insns. Change movmskps Ev, XM to Gv, EX. - (dis386_twobyte_intel): Same here. - - * i386-dis.c (Av): Remove. - (Ap): remove lptr. - (lptr): Remove. - (OPSIMD): Define. - (OP_SIMD_Suffix): New function. - (OP_DIR): Remove dead code. - (eAX_reg..eDI_reg): Renumber. - (onebyte_has_modrm): Table numbering comments. - (INTERNAL_DISASSEMBLER_ERROR): Move to before print_insn_x86. - (print_insn_x86): Move all prefix oappends to after uses_f3_prefix - checks. Print error on invalid dp->bytemode2. Remove simd_cmp, - and handle SIMD cmp insns in OP_SIMD_Suffix. - (info->bytes_per_line): Bump from 5 to 6. - (OP_None): Remove. - (OP_E): Use INTERNAL_DISASSEMBLER_ERROR. Handle sfence. - (OP_3DNowSuffix): Ensure mnemonic index unsigned. - - PIII SIMD support from Doug Ledford <dledford@redhat.com> - * i386-dis.c (XM, EX, None): Define. - (OP_XMM, OP_EX, OP_None): New functions. - (USE_GROUPS, USE_PREFIX_USER_TABLE): Define. - (GRP14): Rename to GRPAMD. - (GRP*): Add USE_GROUPS flag. - (PREGRP*): Define. - (dis386_twobyte_att, dis386_twobyte_intel): Add SIMD insns. - (twobyte_has_modrm): Add SIMD entries. - (twobyte_uses_f3_prefix, simd_cmp_op, prefix_user_table): New. - (grps): Add SIMD insns. - (print_insn_x86): New vars uses_f3_prefix and simd_cmp. Don't - oappend repz if uses_f3_prefix. Add code to handle new groups for - SIMD insns. - - From Maciej W. Rozycki <macro@ds2.pg.gda.pl> - * i386-dis.c (dis386_att, dis386_intel): Change 0xE8 call insn - operand from Av to Jv. - -1999-05-07 Nick Clifton <nickc@cygnus.com> - - * mcore-dis.c (print_insn_mcore): Use .short to display - unidentified instructions, not .word. - -1999-04-26 Tom Tromey <tromey@cygnus.com> - - * aclocal.m4, configure: Updated for new version of libtool. - -1999-04-14 Doug Evans <devans@casey.cygnus.com> - - * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. - * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. - -Mon Apr 12 23:46:17 1999 Jeffrey A Law (law@cygnus.com) - - * hppa-dis.c (print_insn_hppa, case '3'): New case for PA2.0 - instructions. - -1999-04-10 Doug Evans <devans@casey.cygnus.com> - - * fr30-desc.c, fr30-desc.h, fr30-ibld.c: Rebuild. - * m32r-desc.c, m32r-desc.h, m32r-opinst.c: Rebuild. - -1999-04-06 Ian Lance Taylor <ian@zembu.com> - - * opintl.h (LC_MESSAGES): Never define. - -1999-04-04 Ian Lance Taylor <ian@zembu.com> - - * i386-dis.c (intel_syntax, open_char, close_char): Make static. - (separator_char, scale_char): Likewise. - (print_insn_x86): Likewise. - (print_insn_i386): Likewise. Add declaration. - -1999-03-26 Doug Evans <devans@casey.cygnus.com> - - * fr30-dis.c: Rebuild. - * m32r-dis.c: Rebuild. - -1999-03-23 Ian Lance Taylor <ian@zembu.com> - - * m68k-opc.c: Change compare instructions to use "@s" rather than - ";s" when used with an immediate operand. - -1999-03-22 Doug Evans <devans@casey.cygnus.com> - - * cgen-opc.c (cgen_set_cpu): Delete. - (cgen_lookup_insn): max_insn_size renamed to max_insn_bitsize. - * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c, - fr30-opc.h: Rebuild. - * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c, - m32r-opc.h: Rebuild. - * po/opcodes.pot: Rebuild. - -1999-03-16 Martin Hunt <hunt@cygnus.com> - - * d30v-opc.c (mvtsys): Remove FLAG_LKR. - -1999-03-11 Doug Evans <devans@casey.cygnus.com> - - * cgen-opc.c (cgen_set_cpu): New arg `isa'. All callers updated. - (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): New fns. - (cgen_get_insn_operands): Rewrite test for hardcoded/operand index. - * fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c: Rebuild. - * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c: Rebuild. - * m32r-opinst.c: Rebuild. - -1999-02-25 Doug Evans <devans@casey.cygnus.com> - - * cgen-opc.c (cgen_hw_lookup_by_name): Rewrite. - (cgen_hw_lookup_by_num): Rewrite. - * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. - * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. - * m32r-opinst.c: Rebuild. - -Sat Feb 13 14:06:19 1999 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c: Add sqrt+flags patterns. Add EV6 PALcode insns. - (insert_jhint): Fix insertion mask. - * alpha-dis.c (print_insn_alpha): Disassemble EV6 PALcode insns. - -1999-02-10 Doug Evans <devans@casey.cygnus.com> - - * Makefile.in: Rebuild. - -1999-02-09 Doug Evans <devans@casey.cygnus.com> - - * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: Delete. - * i960-dis.c (print_insn_i960): Rename from print_insn_i960_orig. - * Makefile.am: Remove references to them. - (HFILES): Add fr30-desc.h, m32r-desc.h. - (CFILES): Add fr30-desc.c, fr30-ibld.c, m32r-desc.c, m32r-ibld.c, - m32r-opinst.c. - (ALL_MACHINES): Update. - * configure.in: Redo handling of cgen_files. - (bfd_i960_arch): Delete i960c-*.lo files. - * configure: Regenerate. - * cgen-asm.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. - (hash_insn_array): Rewrite. - * cgen-dis.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. - (hash_insn_array): Rewrite. - * cgen-opc.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. - (cgen_lookup_insn,cgen_get_insn_operands): Define here. - (cgen_lookup_get_insn_operands): Ditto. - * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerate. - * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. - * po/POTFILES.in: Rebuild. - * po/opcodes.pot: Rebuild. - -Fri Feb 5 00:04:24 1999 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am: Rebuild dependencies. - (HFILES): Add fr30-opc.h. - (CFILES): Add fr30-asm.c, fr30-dis.c, fr30-opc.c. - * Makefile.in: Rebuild. - - * configure.in: Change AC_PREREQ to 2.13. Remove AM_CYGWIN32. - Change AM_EXEEXT to AC_EXEEXT and AM_PROG_INSTALL to - AC_PROG_INSTALL. - * acconfig.h: Remove. - * configure: Rebuild with current autoconf/automake. - * aclocal.m4: Likewise. - * config.in: Likewise. - * Makefile.in: Likewise. - -Thu Feb 4 13:48:52 1999 Ian Lance Taylor <ian@cygnus.com> - - * m68k-opc.c: Correct move (not movew) to status word on 5200. - -Mon Feb 1 20:54:36 1999 Catherine Moore <clm@cygnus.com> - - * disassemble.c (disassembler): Handle bfd_mach_i386_i386_intel_syntax. - * i386-dis.c (x_mode): Define. - (dis386): Remove. - (dis386_att): New. - (dis386_intel): New. - (dis386_twobyte): Remove. - (dis386_twobyte_att): New. - (dis386_twobyte_intel): New. - (print_insn_x86): Use new arrays. - (float_mem): Remove. - (float_mem_intel): New. - (float_mem_att): New. - (dofloat): Use new float_mem arrays. - (print_insn_i386_att): New. - (print_insn_i386_intel): New. - (print_insn_i386): Handle bfd_mach_i386_i386_intel_syntax. - (putop): Handle intel syntax. - (OP_indirE): Handle intel syntax. - (OP_E): Handle intel syntax. - (OP_I): Handle intel syntax. - (OP_sI): Handle intel syntax. - (OP_OFF): Handle intel syntax. - -1999-01-27 Doug Evans <devans@casey.cygnus.com> - - * fr30-opc.h, fr30-opc.c: Rebuild. - * i960c-opc.h, i960c-opc.c: Rebuild. - * m32r-opc.c: Rebuild. - -Tue Jan 19 18:01:54 1999 David Taylor <taylor@texas.cygnus.com> - - * hppa-dis.c: revert HP merge changes until HP gives us - an updated file. - -1999-01-19 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Display ARM syntax for PC relative - offsets as well as symbloic address. - -Tue Jan 19 10:51:01 1999 David Taylor <taylor@texas.cygnus.com> - - * hppa-dis.c: fix comments and some indentation. - -1999-01-12 Doug Evans <devans@casey.cygnus.com> - - * fr30-opc.c, i960c-opc.c: Regenerate. - -1999-01-11 Doug Evans <devans@casey.cygnus.com> - - * fr30-opc.c: Regenerate. - -1999-01-06 Doug Evans <devans@casey.cygnus.com> - - * m32r-dis.c: Regenerate. - -1999-01-05 Doug Evans <devans@casey.cygnus.com> - - * fr30-asm.c, fr30-dis.c, fr30-opc.h, fr30-opc.c: Regenerate. - * i960c-asm.c, i960c-dis.c, i960c-opc.h, i960c-opc.c: Regenerate. - * m32r-asm.c, m32r-dis.c, m32r-opc.h, m32r-opc.c: Regenerate. - -1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) - - * configure.in: Require autoconf 2.12.1 or higher. - -1998-12-30 Gavin Romig-Koch <gavin@cygnus.com> - - * mips16-opc.c: Mark branch insns with MIPS16_INSN_BRANCH. - -Wed Dec 16 16:17:49 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - -1998-12-16 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-dis.c (set_mips_isa_type): Handle bfd_mach_mips4111. - -1998-12-15 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c, fr30-opc.h: Regenerated. - -1998-12-14 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c, fr30-opc.h: Regenerated. - -Thu Dec 10 18:39:46 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c, fr30-opc.h: Regenerated. - -Thu Dec 10 12:49:24 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Tue Dec 8 13:56:18 1998 David Taylor <taylor@texas.cygnus.com> - - * dis-buf.c (generic_strcat_address): reformat to GNU coding - conventions. change sprintf call to an sprintf_vma call. - -Tue Dec 8 13:12:44 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. - -Tue Dec 8 10:50:46 1998 David Taylor <taylor@texas.cygnus.com> - - The following changes were made by - Elena Zannoni <ezannoni@kwikemart.cygnus.com>, - David Taylor <taylor@texas.cygnus.com>, and - Edith Epstein <eepstein@sophia.cygnus.com> as part of a project to - merge in changes by HP; HP did not create ChangeLog entries. - - * dis-buf.c (generic_strcat_address): new function. - - * hppa-dis.c: Changes to improve hppa disassembly. - Changed formatting in : reg_names, fp_reg_names,control_reg, - New variables : sign_extension_names, deposit_names, conversion_names - float_test_names, compare_cond_names_double, add_cond_names_double, - logical_cond_names_double, unit_cond_names_double, - branch_push_pop_names, saturation_names, shift_names, mix_names, - New Macros : GET_COMPL_O, GET_PUSH_POP,MERGED_REG - Move some definitions to libhppa.h: GET_FIELD, GET_BIT - (fput_const): renamed as fput_hex_const - (print_insn_hppa): - - use the macros fputs_filtered and - fput_decimal_const whenever possible; calls to sign_extend require - 2 params -- add a missing second param of 0. - - Some new code ifdefed for LOCAL_ONLY, all related to figuring out - architecture version number of current machine. HP folks are - trying to handle situation where the target program was compiled - for PA 1.x (32-bit), but is running on a PA 2.0 machine and - visa versa. - - added new cases : 'g', 'B', 'm' - - added cases specifically for PA 2.0 - - changed the following cases : '"', 'n', 'N', 'p', 'Z', - - calls to fput_const become calls to fput_hex_const - -1998-12-07 James E Wilson <wilson@wilson-pc.cygnus.com> - - * Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c. - (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo. - (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules. - * Makefile.in: Rebuilt. - * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o, - i960-dis.c to ta. - * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig. - * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files. - -Mon Dec 7 14:33:44 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. - -Sun Dec 6 14:06:48 1998 Ian Lance Taylor <ian@cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Add dmfc2 and dmtc2. - - * ppc-opc.c (powerpc_opcodes): Add PowerPC403 GC[X] instructions. - From Saitoh Masanobu <msaitoh@spa.is.uec.ac.jp>. - -Fri Dec 4 17:45:51 1998 Doug Evans <devans@canuck.cygnus.com> - - * fr30-opc.c: Regenerate. - -Fri Dec 4 17:08:08 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. - -Thu Dec 3 14:26:20 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. - -Thu Dec 3 00:09:17 1998 Doug Evans <devans@canuck.cygnus.com> - - * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerate. - -1998-11-30 Doug Evans <devans@casey.cygnus.com> - - * cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE -> - CGEN_INSN_BASE_VALUE. - * m32r-opc.c, m32r-opc.h, m32r-asm.c, m32r-dis.c: Regenerate. - * fr30-opc.c, fr30-opc.h, fr30-asm.c, fr30-dis.c: Regenerate. - -Thu Nov 26 11:26:32 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c, fr30-dis.c, fr30-opc.c: Regenerated. - -Tue Nov 24 11:20:54 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c, fr30-dis.c: Regenerated. - -Mon Nov 23 18:28:48 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. - -1998-11-20 Doug Evans <devans@tobor.to.cygnus.com> - - * fr30-opc.c: Regenerated. - -Thu Nov 19 16:02:46 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-asm.c: Regenerated. - -Thu Nov 19 07:54:15 1998 Doug Evans <devans@charmed.cygnus.com> - - * mips-opc.c (sync.p,sync.l): Swap insn values. - -1998-11-19 Doug Evans <devans@tobor.to.cygnus.com> - - * fr30-opc.c: Regenerate. - -Wed Nov 18 21:36:37 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - -1998-11-18 Doug Evans <devans@casey.cygnus.com> - - * m32r-asm.c, m32r-dis.c, m32r-opc.c: Rebuild. - * fr30-asm.c, fr30-dis.c, fr30-opc.c: Rebuild. - -Wed Nov 18 11:30:04 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - -Mon Nov 16 19:21:48 1998 Dave Brolley <brolley@cygnus.com> - - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-asm.c: Regenerated. - -Thu Nov 12 19:24:18 1998 Dave Brolley <brolley@cygnus.com> - - * po/opcodes.pot: Regenerated. - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-asm.c: Regenerated. - -Tue Nov 10 15:26:27 1998 Nick Clifton <nickc@cygnus.com> - - * disassemble.c (disassembler): Add support for FR30 target. - -Tue Nov 10 11:00:04 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-dis.c, m32r-opc.c, m32r-opc.h: Rebuild. - * fr30-dis.c, fr30-opc.c, fr30-opc.h: Rebuild. - -Mon Nov 9 18:22:55 1998 Dave Brolley <brolley@cygnus.com> - - * po/opcodes.pot: Regenerate. - * po/POTFILES.in: Regenerate. - * fr30-opc.c: Regenerate. - * fr30-opc.h: Regenerate. - -Fri Nov 6 17:21:38 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c: Regenerate. - -Wed Nov 4 18:46:47 1998 Dave Brolley <brolley@cygnus.com> - - * configure.in: Added case for bfd_fr30_arch. - * Makefile.am (CFILES): Added fr30-asm.c, fr30-dis.c, fr30-opc.c. - (ALL_MACHINES): Added fr30-asm.lo, fr30-dis.lo, fr30-opc.lo. - (CLEANFILES): Added stamp-fr30. - (FR30_DEPS): Added. - * fr30-asm.c: New file. - * fr30-dis.c: New file. - * fr30-opc.c: New file. - * fr30-opc.h: New file. - * po/POTFILES.in: Regenerated - * po/opcodes.pot: Regenerated - -Mon Nov 2 15:05:33 1998 Geoffrey Noer <noer@cygnus.com> - - * configure.in: detect cygwin* instead of cygwin32* - * configure: regenerate - -Tue Oct 27 08:58:37 1998 Gavin Romig-Koch <gavin@cygnus.com> - - * mips-opc.c (IS_M): Added. - -Mon Oct 19 13:03:19 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.c, m32r-opc.h, m32r-asm.c, m32r-dis.c: Regenerate. - -Fri Oct 9 14:01:56 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h, m32r-opc.c: Regenerate. - -Sun Oct 4 21:01:44 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (OP_3DNowSuffix): New static function. - (OPSUF): Define. - (GRP14): Define. - (dis386_twobyte): Add GRP14, femms, and 3DNow entries. - (twobyte_has_modrm): Set entries corresponding to GRP14, 3DNow. - (insn_codep): New static variable. - (print_insn_x86): Init insn_codep after prefixes. - (grps): Add GRP14 entries for prefetch, prefetchw. - (OP_REG): Reformat. - - From Jeff B Epler <jepler@usgs.gov> - * i386-dis.c (Suffix3DNow): New table. - -Wed Sep 30 10:17:50 1998 Nick Clifton <nickc@cygnus.com> - - * d10v-opc.c: Treat TRAP as if it were a branch type instruction. - -Mon Sep 28 14:35:43 1998 Martin M. Hunt <hunt@cygnus.com> - - * d10v-dis.c (print_operand): If num is nonzero, then - add OPERAND_ACC1, not OPERAND_ACC0. - -Thu Sep 24 09:20:03 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Add FLAG_JSR attribute to DBT, REIT, RTD, and TRAP - insns. - -Tue Sep 22 17:55:14 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Add use of EITHER_BUT_PREFER_MU execution unit - class. - -Tue Sep 15 15:14:45 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.h, m32r-opc.c: Add bbpc,bbpsw support. - -1998-09-09 Michael Meissner <meissner@cygnus.com> - - * ppc-opc.c (powerpc_opcodes): Add support for PowerPC 750 move - to/from SPRs. - -Fri Sep 4 19:42:59 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_big_arm): Detect Thumb symbols in elf - object files. - (print_insn_little_arm): Detect Thumb symbols in elf object - files. - -Sat Aug 29 22:24:09 1998 Richard Henderson <rth@cygnus.com> - - * alpha-dis.c (print_insn_alpha): Use the machine type to - decide which PALcode set to include. - -Sun Aug 23 02:16:18 1998 Richard Henderson <rth@cygnus.com> - - * sparc-opc.c (FBRX): Fix typo in ",a,pn %fcc3" case. - -Fri Aug 21 16:07:52 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Add FLAG_MUL32 to MAC, MACS, - MSUB and MSUBS instructions. - -Thu Aug 13 16:23:04 1998 Ian Lance Taylor <ian@cygnus.com> - - * ppc-opc.c (powerpc_operands): Omit parens around additions in - operand name macros. - -Wed Aug 12 14:00:38 1998 Ian Lance Taylor <ian@cygnus.com> - - From Peter Jeremy <peter.jeremy@auss2.alcatel.com.au>: - * m68k-opc.c: Correct mulsl and mulul to use q rather than D, a, - +, -, and d for ColdFire. - - From Peter Thiemann <thiemann@informatik.uni-tuebingen.de>: - * ppc-opc.c (insert_mbe): Handle wrapping bitmasks. - (extract_mbe): Likewise. - -Wed Aug 12 11:11:34 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Fix typo in udf20 .. udf25 instruction opcodes. - - * m10300-opc.c: First cut at UDF instructions. - -Mon Aug 10 14:08:22 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate (remove semantic descriptions). - -Mon Aug 10 12:51:12 1998 Catherine Moore <clm@cygnus.com> - - * arm-dis.c (print_insn_big_arm): Fix indentation. - (print_insn_little_arm): Likewise. - -Sun Aug 9 20:17:28 1998 Catherine Moore <clm@cygnus.com> - - * arm-dis.c (print_insn_big_arm): Check for thumb symbol - attributes. - (print_insn_little_arm): Likewise. - -Mon Aug 3 12:43:16 1998 Doug Evans <devans@seba.cygnus.com> - - Move all global state data into opcode table struct, and treat - opcode table as something that is "opened/closed". - * cgen-asm.c (all fns): New first arg of opcode table descriptor. - (cgen_asm_init): Delete. - (cgen_set_parse_operand_fn): New function. - * cgen-dis.c (all fns): New first arg of opcode table descriptor. - (cgen_dis_init): Delete. - * cgen-opc.c (all fns): New first arg of opcode table descriptor. - (cgen_current_{opcode_table_mach,endian}): Delete. - * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. - -Thu Jul 30 21:41:10 1998 Frank Ch. Eigler <fche@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Add new "LKR" flag to some - instructions. - -Tue Jul 28 11:00:09 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Add entries for "no_match_operands" field in - the opcode table. - -Fri Jul 24 11:41:37 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c, m32r-opc.c: Regenerate (-Wall cleanups). - -Tue Jul 21 13:41:07 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. - -Mon Jul 13 14:53:59 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (ckprefix): Handle fwait specially only when it isn't - the first prefix. - (dofloat): Correct test for fnstsw. Print `fnstsw %ax' rather - than `fnstsw %eax'. - (OP_J): Remove unnecessary subtraction when 16-bit displacement - will be masked later. - -Thu Jul 2 17:11:27 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define. - -Wed Jul 1 16:11:16 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. - -Fri Jun 26 11:08:55 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-dis.c: Only recognize instructions from the currently - selected machine. - * m10300-opc.c: Add field indicating the particular variant of - the mn10300 each instruction is available on. - -Fri Jun 26 12:04:21 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: For bfd_vax_arch, build vax-dis.lo. - * Makefile.am: Rebuild dependencies. - (CFILES): Add vax-dis.c. - (ALL_MACHINES): Add vax-dis.lo. - * aclocal.m4: Rebuild with current libtool. - * configure, Makefile.in: Rebuild. - -Fri Jun 26 12:03:20 1998 Klaus Kaempf <kkaempf@progis.de> - - * vax-dis.c: New file, from work by Pauline Middelink - <middelin@polyware.iaf.nl>. - * disassemble.c (ARCH_vax): Define if ARCH_all. - (disassembler): Add case for ARCH_vax. - * makefile.vms: Support compilation on vms/vax. - -Tue Jun 23 19:42:18 1998 Mark Alexander <marka@cygnus.com> - - * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities - related to sign extension and the size of ints. - -Tue Jun 23 10:59:26 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c: Support one operand "asr", "lsr" and "asl" - instructions. Support (sp) addressing mode by expanding it into - (0,sp). - -Sat Jun 20 14:46:20 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-dis.c (_print_insn_mips): Fix argument interchange typo. - -Fri Jun 19 09:16:42 1998 Mark Alexander <marka@cygnus.com> - - * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op. - -1998-06-18 Ulrich Drepper <drepper@cygnus.com> - - * i386-dis.c: Add support for fxsave, fxrstor, sysenter and - sysexit. - -Thu Jun 18 10:22:24 1998 John Metzler <jmetzler@cygnus.com> - - * mips-dis.c (print_insn_little_mips): Previously, instruction - printing references the symbol table to determine whether the - instruction resides in a block regular instructions or mips16 - instructions. However, when the disassembler gets used in other - environments where the symbol table is not present, we no longer - rely in the symbol table, rather, use the low bit of the - instructions address to guess. There should be no change for usage - of the disassembler in host based programs, gdb, objdump. - (print_insn_big_mips): ditto. - (print_insn_mips): ditto - -Wed Jun 17 21:19:01 1998 Mark Alexander <marka@cygnus.com> - - * m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes. - -Wed Jun 17 17:49:23 1998 Jeffrey A Law (law@cygnus.com) - - * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall". - -Tue Jun 16 13:10:51 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (index16): Add '%' to register names. Use ',' - instead of '+'. - -Sat Jun 13 11:33:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Don't print opcode suffix when we can figure out the - size (and gas can!) by register operands, or from the default - size. - (putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C' - macro to 'E'. - (dis386, dis386_twobyte, grps): Use new suffix macros. - (dis386): Correct imul Ib to imul sIb. Change jnl to jge to be - consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse - order of cmps operands to agree with Intel docs. Correct operand - of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to - agree with Intel docs. - (print_insn_x86): Print orphan fwait before other prefixes. - Return correct byte count for orphan fwait with prefixes. Don't - print `bound' operands in reverse order. - (ckprefix): Stop accumulating prefixes if we get fwait. - (OP_DIR): Print `$' before Ap operands of ljmp, lcall. - -Fri Jun 12 13:40:38 1998 Tom Tromey <tromey@cygnus.com> - - * po/Make-in (all-yes): If maintainer mode, depend on .pot file. - ($(PACKAGE).pot): Unconditionally depend on POTFILES. - -Fri Jun 12 11:04:06 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - Fix problems when bfd_vma is wider than long. - * i386-dis.c: Make op_address and start_pc unsigned. - (set_op): Make parameter unsigned. - (print_insn_x86): Cast to bfd_vma when passing a value to - print_address_func. - * ns32k-dis.c (CORE_ADDR): Don't define. - (print_insn_ns32k): Change type of addr to bfd_vma. Use - bfd_scan_vma to read back address. - (print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma - to format it. - * m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow. - (NEXTULONG): New definition. - (print_insn_m68k): Avoid overflow when computing third argument of - print_insn_arg. - (print_insn_arg): Use NEXTULONG to fetch 32 bit address values. - Use disp instead of val to store offset values. - (print_indexed): Use base_disp instead of word to store base - displacement, to avoid overflow. - * m10300-dis.c (disassemble): Cast value to long when computing - pc-relative address, to get correct sign extension. - -Wed Jun 10 15:58:37 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Tue Jun 9 14:27:57 1998 Nick Clifton <nickc@cygnus.com> - - * arm-opc.h (thumb_opcodes): Display 'add rx, rY, #0' insns as - 'mov rX, rY'. Patch courtesy of Tony Thompson <Tony.Thompson@arm.com> - -Mon Jun 8 18:17:21 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Remove FALG_MUL32 attribyte from MULX2H insn. - -Fri Jun 5 23:47:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_* - functions to void. - (OP_DSreg): Rename from OP_DSSI. - (OP_ESreg): Rename from OP_ESDI. - (Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode. - (DSBX): Define. - (append_seg): Rename from append_prefix. - (ptr_reg): New function. - (dis386): Add S suffix to pushf, popf, ret, lret, enter, leave. - Add DSBX for xlat. - (PREFIX_ADDR): Rename from PREFIX_ADR. - (float_reg): Add non-broken opcodes for people who don't want - UNIXWARE_COMPAT. - -Fri Jun 5 19:15:04 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on - 68000/68008/68010. - -Wed Jun 3 18:56:22 1998 H.J. Lu <hjl@gnu.org> - - * i386-dis.c (dis386): Change 0x60 to "pushaS", 0x61 to "popaS". - -Tue Jun 2 15:06:46 1998 Geoff Keating <geoffk@ozemail.com.au> - - * ppc-opc.c (powerpc_macros): Support shifts and rotates of size - 0; produce error message for shifts of size 32 (or 64 for 64-bit - shifts), because the hardware doesn't support them. - -Wed May 27 15:29:13 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b, - LONG_2, LONG_2b formats to use this new operand. - -Tue May 26 20:47:48 1998 Stan Cox <scox@cygnus.com> - - * sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le. - -Tue May 26 20:45:33 1998 Mark Alexander <marka@cygnus.com> - - * sparc-dis.c (print_insn_sparc): big endian instruction / little - endian data support. - -Tue May 26 16:14:39 1998 Nick Clifton <nickc@cygnus.com> - - * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3 - and SHORT_B3b formats to use Rb instead of Ra. - - Add FLAG_MUL16 to MUL2XH opcode. - - Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension - to existing 1.1.1 parallelisation prohibition procedure. - -Fri May 22 16:00:00 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c, m32r-dis.c: Regenerate. - -Tue May 19 17:36:08 1998 Ian Lance Taylor <ian@cygnus.com> - - * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly - with a shift count of 0. - -Fri May 15 14:58:31 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-opc.c (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. - (cgen_hw_lookup_by_num): New function. - -Wed May 13 17:03:59 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-asm.c: Regenerate (handle uppercase HIGH/SHIGH/LOW/SDA). - -Wed May 13 14:34:31 1998 Mark Alexander <marka@cygnus.com> - - * sparc-dis.c (print_insn_sparc): Always fetch instructions - as big-endian on SPARClite. - -Tue May 12 11:46:31 1998 Richard Henderson <rth@cygnus.com> - - * d30v-opc.c (pre_defined_register): Remove alias for r0. - -Sun May 10 22:37:22 1998 Jeffrey A Law (law@cygnus.com) - - * po/Make-in (install-info): New target. - -Thu May 7 17:15:59 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in (WIN32LIBADD): Add -lintl on cygwin32. - * configure: Rebuild. - -Thu May 7 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand - variety of ISA2 instructions to set bottom ten bits of trap code. - -Thu May 7 11:54:25 1998 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am (config.status): Add explicit target so that - config.status depends upon bfd/configure.in. - * Makefile.in: Rebuild. - -Thu May 7 09:33:02 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips-opc.c (break, sdbbp): Added two-operand variety of ISA1 - instructions to set bottom ten bits of break code. - * mips-dis.c (print_insn_arg): Implement 'q' operand format used - for above optional argument. - -Wed May 6 15:30:06 1998 Klaus Kaempf <kkaempf@progis.de> - - * makefile.vms: Run dec c with /nodebug. - -Mon May 4 10:19:57 1998 Tom Tromey <tromey@cygnus.com> - - * Makefile.in: Rebuilt. - * Makefile.am: Regenerated dependencies with mkdep. - - * opintl.h (_): Define as dgettext. - -Tue Apr 28 14:12:12 1998 Nick Clifton <nickc@cygnus.com> - - * cgen-asm.c: Internationalised. - * m32r-asm.c: Internationalised. - * m32r-dis.c: Internationalised. - * m32r-opc.c: Internationalised. - - * aclocal.m4: Regenerated. - * configure: Regenerated. - * Makefile.am (POTFILES): Remove inclusion of BFD_H. - * Makefile.in: Rebuild. - * po/POTFILES.in: Rebuilt using rule in Makefile.in. - * po/opcodes.pot: Rebuilt after changing POTFILES.in. - -Tue Apr 28 13:13:13 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Call AC_ISC_POSIX near start. Move CY_GNU_GETTEXT - after AC_PROG_CC. - * aclocal.m4, configure: Rebuild with current tools. - -Mon Apr 27 14:31:00 1998 Nick Clifton <nickc@cygnus.com> - - * opintl.h: New file - contains internationalisation macros used - by source files in this directory. - * po/: New subdirectory - contains internationalisation files. - * po/Make-in: New file - Makefile constructor. - * po/POTFILES.in: New file - list of files in opcodes directory - that should be scan for internationalisation macros. - * po/opcodes.pot: New file - list of internationisation strings - found in files mentioned in po/POTFILES.in. - * Makefile.am: Add rule to build po/POTFILES.in. Add SUBDIRS - entry. Add intl directory to include paths. - * acconfig.h: Add ENABLE_NLS, HAVE_CATGETS, HAVE_GETEXT, - HAVE_STRCPY, HAVE_LC_MESSAGES - * configure.in: Add rule to build Makefile in po subdirectory. - * Makefile.in: Rebuilt. - * aclocal.m4: Rebuilt. - * config.in: Rebuilt. - * configure: Rebuilt. - * alpha-opc.c: Internationalised. - * arc-dis.c: Internationalised. - * arc-opc.c: Internationalised. - * arm-dis.c: Internationalised. - * cgen-asm.c: Internationalised. - * d30v-dis.c: Internationalised. - * dis-buf.c: Internationalised. - * h8300-dis.c: Internationalised. - * h8500-dis.c: Internationalised. - * i386-dis.c: Internationalised. - * m10200-dis.c: Internationalised. - * m10300-dis.c: Internationalised. - * m68k-dis.c: Internationalised. - * m88k-dis.c: Internationalised. - * mips-dis.c: Internationalised. - * ns32k-dis.c: Internationalised. - * opintl.h: Internationalised. - * ppc-opc.c: Internationalised. - * sparc-dis.c: Internationalised. - * v850-dis.c: Internationalised. - * v850-opc.c: Internationalised. - -Mon Apr 27 10:33:56 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c (cgen_current_opcode_table): Renamed from ..._data. - (asm_hash_table_entries): New variable. - (cgen_asm_init): Free asm_hash_table_entries. - (hash_insn_array,hash_insn_list): New functions. - (build_asm_hash_table): Use them. Hash macro insns as well. - (cgen_asm_lookup_insn): Update. - * cgen-dis.c (cgen_current_opcode_table): Renamed from ..._data. - (dis_hash_table_entries): New variable. - (cgen_dis_init): Free dis_hash_table_entries. - (hash_insn_array,hash_insn_list): New functions. - (build_dis_hash_table): Use them. Hash macro insns as well. - (cgen_dis_lookup_insn): Update. - * cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data. - (cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update. - (cgen_macro_insn_count): New function. - * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. - -Fri Apr 24 16:07:57 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386-dis.c (OP_DSSI): Print segment override. - -Mon Apr 13 16:59:39 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_arm): Add "_all" extension to 'C' - operator. - -Mon Apr 13 16:50:27 1998 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am (libopcodes_la_LIBADD): Add @WIN32LIBADD@. - (libopcodes_la_LDFLAGS): Add @WIN32LDFLAGS@. - * configure.in: Define and substitute WIN32LDFLAGS and - WIN32LIBADD. - * aclocal.m4: Rebuild with new libtool. - * configure, Makefile.in: Rebuild. - -Fri Apr 10 18:14:31 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Sun Apr 5 16:04:39 1998 H.J. Lu <hjl@gnu.org> - - * Makefile.am (stamp-lib): Check that .libs/libopcodes.a exists - before trying to copy it. - * Makefile.in: Rebuild. - -Thu Apr 2 17:25:49 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c: Use signed immediate values for CMPUI instruction. - -Wed Apr 1 16:20:27 1998 Ian Dall <Ian.Dall@dsto.defence.gov.au> - - * ns32k-dis.c (bit_extract_simple): New function to extract bits - from an arbitrary valid buffer instead of fetching them on demand - using fetch_data(). - (invalid_float): use bit_extract_simple() instead of bit_extract(). - -Tue Mar 31 11:09:08 1998 Ian Lance Taylor <ian@cygnus.com> - - From H.J. Lu <hjl@gnu.org>: - * i386-dis.c (dis386): Change 0x8c and 0x8e to movS, and change Ew - to Ev for both. - -Mon Mar 30 17:32:03 1998 Ian Lance Taylor <ian@cygnus.com> - - * Branched binutils 2.9. - -Mon Mar 30 15:18:00 1998 Ken Raeburn <raeburn@cygnus.com> - - * d30v-dis.c (print_insn_d30v): Don't use uninitialized "num" when - disassembling last 4 bytes of a section. - -Fri Mar 27 18:08:13 1998 Ian Lance Taylor <ian@cygnus.com> - - Fix some gcc -Wall warnings: - * arc-dis.c (print_insn): Add casts to avoid warnings. - * cgen-opc.c (cgen_keyword_lookup_name): Likewise. - * d10v-dis.c (dis_long, dis_2_short): Likewise. - * m10200-dis.c (disassemble): Likewise. - * m10300-dis.c (disassemble): Likewise. - * ns32k-dis.c (print_insn_ns32k): Likewise. - * ppc-opc.c (insert_ral, insert_ram): Likewise. - * cgen-dis.c (build_dis_hash_table): Remove used local variables. - * cgen-opc.c (cgen_keyword_search_next): Likewise. - * d10v-dis.c (dis_long, dis_2_short): Likewise. - * d30v-dis.c (print_insn_d30v, lookup_opcode): Likewise. - * ns32k-dis.c (bit_extract, print_insn_ns32k): Likewise. - * tic80-dis.c (print_one_instruction): Likewise. - * w65-dis.c (print_operand): Likewise. - * z8k-dis.c (fetch_data): Likewise. - * a29k-dis.c: Add return type for find_byte_func_type. - * arc-opc.c: Include <stdio.h>. Remove declarations of - insert_multshift and extract_multshift. - * d30v-dis.c (lookup_opcode): Parenthesize assignments in - conditionals. - (extract_value): Fully parenthesize expression. - * h8500-dis.c (print_insn_h8500): Initialize local variables. - * h8500-opc.h (h8500_table): Fully bracket initializer. - * w65-opc.h (optable): Likewise. - * i386-dis.c (print_insn_x86): Declare aflag and flag parameters. - * i386-dis.c (OP_E): Initialize local variables. - * m10200-dis.c (print_insn_mn10200): Likewise. - * mips-dis.c (print_insn_mips16): Likewise. - * sh-dis.c (print_insn_shx): Likewise. - * v850-dis.c (print_insn_v850): Likewise. - * ns32k-dis.c (print_insn_arg): Declare. - (get_displacement, invalid_float): Declare. - (list_search, sign_extend, flip_bytes): Declare return type. - (get_displacement): Likewise. - (print_insn_arg): Likewise. Make d int. Fix sprintf format - string. - (print_insn_ns32k): Make i unsigned. - (invalid_float): Make static. Declare type of val. - * tic30-dis.c (print_par_insn): Make i size_t. Don't check strlen - on each for iteration. - * tic30-dis.c (get_indirect_operand): Likewise. - * z8k-dis.c (print_insn_z8001): Declare return type. - (print_insn_z8002): Likewise. - (unparse_instr): Fix sprintf format strings. - -Fri Mar 27 00:05:23 1998 Jeffrey A Law (law@cygnus.com) - - * mips-opc.c: Add "sync.l" and "sync.p". - -Wed Mar 25 14:32:48 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k-dis.c (print_insn_m68k): Use info->mach to select the - default m68k variant to recognize. - - * i960-dis.c (pinsn): Change type of first argument to bfd_vma. - (ctrl, cobr, mem, ea): Likewise. - (print_addr): Likewise. Remove cast. - (ea): Cast argument of print_addr to bfd_vma. - - * cgen-asm.c (cgen_parse_signed_integer): Fix type of local - variable value. - (cgen_parse_unsigned_integer): Likewise. - (cgen_parse_address): Likewise. - -Wed Mar 25 14:31:31 1998 Ian Lance Taylor <ian@cygnus.com> - - * i960-dis.c (ctrl): Add full braces to structure initialization. - (cobr, mem, reg): Likewise. - (ea): Correct parenthesization in expression. - - * cgen-asm.c: Include <ctype.h>. - (build_asm_hash_table): Remove unused local variable i. - (cgen_parse_keyword): Add casts to avoid warnings. - - * arm-dis.c (print_insn_big_arm): Only call coffsymbol for a COFF - symbol. Fix indentation. - (print_insn_little_arm): Likewise. - -Fri Mar 20 18:55:18 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Use AM_DISABLE_SHARED. - * aclocal.m4, configure: Rebuild with libtool 1.2. - -Thu Mar 19 15:46:53 1998 Nick Clifton <nickc@cygnus.com> - - These patches are courtesy of Jonathan Walton and Tony Thompson - (athompso@cambridge.arm.com). - - * arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC - relative addresses. - - * arm-opc.h (thumb_opcodes): Annotate PC relative addresses with - both the offset and the label closest to the destination. - -Sat Mar 14 23:47:14 1998 Doug Evans <devans@seba.cygnus.com> - - * m32r-opc.h: Regenerate. - -Wed Mar 4 12:08:14 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. - -Sat Feb 28 16:02:34 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Do not - assume that info->symbols is non-empty. - -Sat Feb 28 12:19:05 1998 Richard Henderson <rth@cygnus.com> - - * alpha-opc.c (cvtqs) There is no such thing. - (cvttq): Missing most of the /*d variants. - -Thu Feb 26 15:53:09 1998 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (d30v_opcode_table): Indicate which instructions are - delayed branches or jumps. - -Tue Feb 24 10:46:44 1998 Doug Evans <devans@canuck.cygnus.com> - - * arm-dis.c (print_insn_{big,little}_arm): info->symbol changed - to *info->symbols. - * mips-dis.c (print_insn_{big,little}_mips): Likewise. - * tic30-dis.c (print_branch): Likewise. - -Tue Feb 24 11:06:18 1998 Nick Clifton <nickc@cygnus.com> - - * arm-dis.c (print_insn_big_arm, print_insn_little_arm): Remove - saved_symbol code as it is no longer needed. - -Mon Feb 23 13:16:17 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c: Include symcat.h. - * cgen-dis.c, cgen-opc.c: Ditto. - * m32r-asm.c, m32r-dis.c, m32r-opc.h, m32r-opc.c: Regenerate. - -Mon Feb 23 10:34:58 1998 Jeffrey A Law (law@cygnus.com) - - * mips-dis.c (print_insn_arg): Do not prefix 'P' arguments with '$'. - -Thu Feb 19 16:51:13 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.[ch]: Regenerate. - -Tue Feb 17 17:14:50 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max - arguments. Don't perform validation here. - * m32r-asm.c, m32r-dis.c, m32r-opc.c: Regenerate. - -Fri Feb 13 14:26:06 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Fri Feb 13 14:53:02 1998 Ian Lance Taylor <ian@cygnus.com> - - * Makefile.am (AUTOMAKE_OPTIONS): Define. - * configure, Makefile.in, aclocal.m4: Rebuild with automake 1.2e. - -Fri Feb 13 10:21:09 1998 Mark Alexander <marka@cygnus.com> - - * m10300-dis.c (print_insn_mn10300): Recognize break instruction. - -Fri Feb 13 13:12:14 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Get the version number from BFD. - * configure: Rebuild. - - From H.J. Lu <hjl@gnu.org>: - * Makefile.am (libopcodes_la_LDFLAGS): Define. - * Makefile.in: Rebuild. - -Fri Feb 13 09:50:32 1998 Nick Clifton <nickc@cygnus.com> - - * m32r-opc.c: Regenerate. - * m32r-opc.h: Regenerate. - -Thu Feb 12 11:01:40 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.c: Regenerate. - -Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk> - - Fix rac to accept only a0: - * d10v-opc.c (d10v_predefined_registers, d10v_operands, d10v_opcodes): - Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1. - Introduce OPERAND_GPR. - * d10v-dis.c (print_operand): Likewise. - -Wed Feb 11 18:58:34 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-opc.c (cgen_set_cpu): Delete init of hw list `next' chain. - (cgen_hw_lookup): Make result const. - * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. - -Sat Feb 7 15:30:27 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure, aclocal.m4: Rebuild with new libtool. - -Thu Feb 5 17:56:10 1998 Michael Meissner <meissner@cygnus.com> - - * d30v-opc.c (repeat{,i} instructions): Repeat/repeati - instructions use a PC relative branch, not absolute. - -Wed Feb 4 19:17:37 1998 Ian Lance Taylor <ian@cygnus.com> - - * configure.in: Set libtool_enable_shared rather than - libtool_shared. Remove diversion hack. - * configure, Makefile.in, aclocal.m4: Rebuild with new libtool. - -Tue Feb 3 17:19:40 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-opc.c (cgen_set_cpu): Initialize hardware table. - * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. - -Mon Feb 2 19:22:15 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> - - * tic30-dis.c: New file. - * disassemble.c (disassembler): Add bfd_arch_tic30 case. - * configure.in: Handle bfd_tic30_arch. - * Makefile.am: Rebuild dependencies. - (CFILES): Add tic30-dis.c - (ALL_MACHINES): Add tic30-dis.lo. - * configure, Makefile.in: Rebuild. - -Thu Jan 29 13:02:56 1998 Doug Evans <devans@canuck.cygnus.com> - - * m32r-opc.h (HAVE_CPU_M32R): Define. - -Wed Jan 28 09:55:03 1998 Nick Clifton <nickc@cygnus.com> - - * v850-opc.c (insertion routines): If both alignment and size is - wrong then report this. - -Tue Jan 27 21:52:59 1998 Jeffrey A Law (law@cygnus.com) - - * mips-dis.c (_print_insn_mips): Set target_processor as appropriate. - Only recognize instructions for the current target_processor. - -Thu Jan 22 16:20:17 1998 Fred Fish <fnf@cygnus.com> - - * d10v-dis.c (PC_MASK): Correct value. - (print_operand): If there's a reloc, don't calculate the - address because they could be in different sections. - -Fri Jan 16 15:29:11 1998 Jim Blandy <jimb@zwingli.cygnus.com> - - * mips-opc.c (mips_builtin_opcodes): Move 4010's "addciu" - instruction after the 4650's "mul" instruction; nobody's using the - 4010 these days. If object files someday indicate which processor - variant they're intended for, we can do a better job at this. - -Mon Jan 12 14:43:54 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen-asm.c (build_asm_hash_table): Traverse compiled in table using - table provided entry size. Use CGEN_INSN_MNEMONIC. - (cgen_parse_keyword): Rewrite. - * cgen-dis.c (build_dis_hash_table): Traverse compiled in table using - table provided entry size. Use CGEN_INSN_MASK_BITSIZE. - * cgen-opc.c: Clean up pass over `struct foo' usage. - (cgen_keyword_lookup_value): Handle "" entry. - (cgen_keyword_add): Likewise. - -For older changes see ChangeLog-9297 - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/contrib/binutils/opcodes/MAINTAINERS b/contrib/binutils/opcodes/MAINTAINERS deleted file mode 100644 index d59a3bd..0000000 --- a/contrib/binutils/opcodes/MAINTAINERS +++ /dev/null @@ -1 +0,0 @@ -See ../binutils/MAINTAINERS diff --git a/contrib/binutils/opcodes/Makefile.am b/contrib/binutils/opcodes/Makefile.am deleted file mode 100644 index ea621f2..0000000 --- a/contrib/binutils/opcodes/Makefile.am +++ /dev/null @@ -1,848 +0,0 @@ -## Process this file with automake to generate Makefile.in - -AUTOMAKE_OPTIONS = cygnus - -SUBDIRS = po - -INCDIR = $(srcdir)/../include -BFDDIR = $(srcdir)/../bfd -MKDEP = gcc -MM - -WARN_CFLAGS = @WARN_CFLAGS@ -AM_CFLAGS = $(WARN_CFLAGS) - -bfdlibdir = @bfdlibdir@ -bfdincludedir = @bfdincludedir@ - -bfdlib_LTLIBRARIES = libopcodes.la - -# This is where bfd.h lives. -BFD_H = ../bfd/bfd.h - -# This is where libiberty lives. -LIBIBERTY = ../libiberty/libiberty.a - -# Header files. -HFILES = \ - arm-opc.h \ - fr30-desc.h fr30-opc.h \ - frv-desc.h frv-opc.h \ - h8500-opc.h \ - ia64-asmtab.h \ - ia64-opc.h \ - ip2k-desc.h ip2k-opc.h \ - iq2000-desc.h iq2000-opc.h \ - m32r-desc.h m32r-opc.h \ - mcore-opc.h \ - openrisc-desc.h openrisc-opc.h \ - sh-opc.h \ - sh64-opc.h \ - sysdep.h \ - w65-opc.h \ - xstormy16-desc.h xstormy16-opc.h \ - z8k-opc.h - -# C source files that correspond to .o's. -CFILES = \ - a29k-dis.c \ - alpha-dis.c \ - alpha-opc.c \ - arc-dis.c \ - arc-opc.c \ - arc-ext.c \ - arm-dis.c \ - avr-dis.c \ - cgen-asm.c \ - cgen-dis.c \ - cgen-opc.c \ - cris-dis.c \ - cris-opc.c \ - d10v-dis.c \ - d10v-opc.c \ - d30v-dis.c \ - d30v-opc.c \ - dlx-dis.c \ - dis-buf.c \ - dis-init.c \ - disassemble.c \ - fr30-asm.c \ - fr30-desc.c \ - fr30-dis.c \ - fr30-ibld.c \ - fr30-opc.c \ - frv-asm.c \ - frv-desc.c \ - frv-dis.c \ - frv-ibld.c \ - frv-opc.c \ - h8300-dis.c \ - h8500-dis.c \ - hppa-dis.c \ - i370-dis.c \ - i370-opc.c \ - i386-dis.c \ - i860-dis.c \ - i960-dis.c \ - ia64-dis.c \ - ia64-opc-a.c \ - ia64-opc-b.c \ - ia64-opc-f.c \ - ia64-opc-i.c \ - ia64-opc-m.c \ - ia64-opc-d.c \ - ia64-opc.c \ - ia64-gen.c \ - ia64-asmtab.c \ - ip2k-asm.c \ - ip2k-desc.c \ - ip2k-dis.c \ - ip2k-ibld.c \ - ip2k-opc.c \ - iq2000-asm.c \ - iq2000-desc.c \ - iq2000-dis.c \ - iq2000-ibld.c \ - iq2000-opc.c \ - m32r-asm.c \ - m32r-desc.c \ - m32r-dis.c \ - m32r-ibld.c \ - m32r-opc.c \ - m32r-opinst.c \ - m68hc11-dis.c \ - m68hc11-opc.c \ - m68k-dis.c \ - m68k-opc.c \ - m88k-dis.c \ - mcore-dis.c \ - mips-dis.c \ - mips-opc.c \ - mips16-opc.c \ - m10200-dis.c \ - m10200-opc.c \ - m10300-dis.c \ - m10300-opc.c \ - mmix-dis.c \ - mmix-opc.c \ - ns32k-dis.c \ - openrisc-asm.c \ - openrisc-desc.c \ - openrisc-dis.c \ - openrisc-ibld.c \ - openrisc-opc.c \ - or32-dis.c \ - or32-opc.c \ - pdp11-dis.c \ - pdp11-opc.c \ - pj-dis.c \ - pj-opc.c \ - ppc-dis.c \ - ppc-opc.c \ - s390-mkopc.c \ - s390-opc.c \ - s390-dis.c \ - sh-dis.c \ - sh64-dis.c \ - sh64-opc.c \ - sparc-dis.c \ - sparc-opc.c \ - tic30-dis.c \ - tic4x-dis.c \ - tic54x-dis.c \ - tic54x-opc.c \ - tic80-dis.c \ - tic80-opc.c \ - v850-dis.c \ - v850-opc.c \ - vax-dis.c \ - w65-dis.c \ - xstormy16-asm.c \ - xstormy16-desc.c \ - xstormy16-dis.c \ - xstormy16-ibld.c \ - xstormy16-opc.c \ - xtensa-dis.c \ - z8k-dis.c \ - z8kgen.c - -ALL_MACHINES = \ - a29k-dis.lo \ - alpha-dis.lo \ - alpha-opc.lo \ - arc-dis.lo \ - arc-opc.lo \ - arc-ext.lo \ - arm-dis.lo \ - avr-dis.lo \ - cgen-asm.lo \ - cgen-dis.lo \ - cgen-opc.lo \ - cris-dis.lo \ - cris-opc.lo \ - d10v-dis.lo \ - d10v-opc.lo \ - d30v-dis.lo \ - d30v-opc.lo \ - dlx-dis.lo \ - fr30-asm.lo \ - fr30-desc.lo \ - fr30-dis.lo \ - fr30-ibld.lo \ - fr30-opc.lo \ - frv-asm.lo \ - frv-desc.lo \ - frv-dis.lo \ - frv-ibld.lo \ - frv-opc.lo \ - h8300-dis.lo \ - h8500-dis.lo \ - hppa-dis.lo \ - i386-dis.lo \ - i370-dis.lo \ - i370-opc.lo \ - i860-dis.lo \ - i960-dis.lo \ - ia64-dis.lo \ - ia64-opc.lo \ - ip2k-asm.lo \ - ip2k-desc.lo \ - ip2k-dis.lo \ - ip2k-ibld.lo \ - ip2k-opc.lo \ - iq2000-asm.lo \ - iq2000-desc.lo \ - iq2000-dis.lo \ - iq2000-ibld.lo \ - iq2000-opc.lo \ - m32r-asm.lo \ - m32r-desc.lo \ - m32r-dis.lo \ - m32r-ibld.lo \ - m32r-opc.lo \ - m32r-opinst.lo \ - m68hc11-dis.lo \ - m68hc11-opc.lo \ - m68k-dis.lo \ - m68k-opc.lo \ - m88k-dis.lo \ - m10200-dis.lo \ - m10200-opc.lo \ - m10300-dis.lo \ - m10300-opc.lo \ - mcore-dis.lo \ - mips-dis.lo \ - mips-opc.lo \ - mips16-opc.lo \ - mmix-dis.lo \ - mmix-opc.lo \ - msp430-dis.lo \ - ns32k-dis.lo \ - openrisc-asm.lo \ - openrisc-desc.lo \ - openrisc-dis.lo \ - openrisc-ibld.lo \ - openrisc-opc.lo \ - or32-dis.lo \ - or32-opc.lo \ - pdp11-dis.lo \ - pdp11-opc.lo \ - pj-dis.lo \ - pj-opc.lo \ - ppc-dis.lo \ - ppc-opc.lo \ - s390-dis.lo \ - s390-opc.lo \ - sh-dis.lo \ - sh64-dis.lo \ - sh64-opc.lo \ - sparc-dis.lo \ - sparc-opc.lo \ - tic30-dis.lo \ - tic4x-dis.lo \ - tic54x-dis.lo \ - tic54x-opc.lo \ - tic80-dis.lo \ - tic80-opc.lo \ - v850-dis.lo \ - v850-opc.lo \ - vax-dis.lo \ - w65-dis.lo \ - xstormy16-asm.lo \ - xstormy16-desc.lo \ - xstormy16-dis.lo \ - xstormy16-ibld.lo \ - xstormy16-opc.lo \ - xtensa-dis.lo \ - z8k-dis.lo - -OFILES = @BFD_MACHINES@ - -INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ -I$(srcdir)/../intl -I../intl - -disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h - $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c - -libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c -# It's desirable to list ../bfd/libbfd.la in DEPENDENCIES and LIBADD. -# Unfortunately this causes libtool to add -L$(libdir), referring to the -# planned install directory of libbfd. This can cause us to pick up an -# old version of libbfd, or to pick up libbfd for the wrong architecture -# if host != build. -libopcodes_la_DEPENDENCIES = $(OFILES) -libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ -libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ - -# libtool will build .libs/libopcodes.a. We create libopcodes.a in -# the build directory so that we don't have to convert all the -# programs that use libopcodes.a simultaneously. This is a hack which -# should be removed if everything else starts using libtool. FIXME. - -noinst_LIBRARIES = libopcodes.a - -stamp-lib: libopcodes.la - libtooldir=`$(LIBTOOL) --config | sed -n -e 's/^objdir=//p'`; \ - if [ -f $$libtooldir/libopcodes.a ]; then \ - cp $$libtooldir/libopcodes.a libopcodes.tmp; \ - $(RANLIB) libopcodes.tmp; \ - $(SHELL) $(srcdir)/../move-if-change libopcodes.tmp libopcodes.a; \ - else true; fi - touch stamp-lib - -libopcodes.a: stamp-lib ; @true - -POTFILES = $(HFILES) $(CFILES) -po/POTFILES.in: @MAINT@ Makefile - for f in $(POTFILES); do echo $$f; done | LC_COLLATE= sort > tmp \ - && mv tmp $(srcdir)/po/POTFILES.in - -# We should reconfigure whenever bfd/configure.in changes, because -# that's where the version number comes from. -config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in - $(SHELL) ./config.status --recheck - -install-bfdlibLTLIBRARIES: @INSTALL_LIBBFD_TRUE@install_libopcodes - @$(NORMAL_INSTALL) - -uninstall-bfdlibLTLIBRARIES: @INSTALL_LIBBFD_TRUE@uninstall_libopcodes - @$(NORMAL_UNINSTALL) - -.PHONY: install_libopcodes uninstall_libopcodes -install_libopcodes: $(bfdlib_LTLIBRARIES) - $(mkinstalldirs) $(DESTDIR)$(bfdlibdir) - $(mkinstalldirs) $(DESTDIR)$(bfdincludedir) - @list='$(bfdlib_LTLIBRARIES)'; for p in $$list; do \ - if test -f $$p; then \ - echo "$(LIBTOOL) --mode=install $(INSTALL) $$p $(DESTDIR)$(bfdlibdir)/$$p"; \ - $(LIBTOOL) --mode=install $(INSTALL) $$p $(DESTDIR)$(bfdlibdir)/$$p; \ - else :; fi; \ - done - $(INSTALL_DATA) $(INCDIR)/dis-asm.h $(DESTDIR)$(bfdincludedir)/dis-asm.h - -uninstall_libopcodes: - list='$(bfdlib_LTLIBRARIES)'; for p in $$list; do \ - $(LIBTOOL) --mode=uninstall rm -f $(DESTDIR)$(bfdlibdir)/$$p; \ - done - rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h - -CLEANFILES = \ - stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ - stamp-iq2000 stamp-xstormy16 \ - libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 - - -CGENDIR = @cgendir@ -CPUDIR = $(CGENDIR)/cpu -CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` -CGENFLAGS = -v - -CGENDEPS = \ - $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ - $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ - $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ - $(CGENDIR)/opc-opinst.scm \ - cgen-asm.in cgen-dis.in cgen-ibld.in - -CGEN_CPUS = fr30 frv ip2k m32r openrisc xstormy16 - -if CGEN_MAINT -IP2K_DEPS = stamp-ip2k -M32R_DEPS = stamp-m32r -FR30_DEPS = stamp-fr30 -FRV_DEPS = stamp-frv -OPENRISC_DEPS = stamp-openrisc -IQ2000_DEPS = stamp-iq2000 -XSTORMY16_DEPS = stamp-xstormy16 -else -IP2K_DEPS = -M32R_DEPS = -FR30_DEPS = -FRV_DEPS = -OPENRISC_DEPS = -IQ2000_DEPS = -XSTORMY16_DEPS = -endif - -run-cgen: - $(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) \ - $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) $(archfile) $(opcfile) \ - "$(options)" "$(extrafiles)" - touch stamp-${prefix} -.PHONY: run-cgen - -# Maintainer utility rule to regenerate all cgen files. -run-cgen-all: - for c in $(CGEN_CPUS) ; \ - do \ - $(MAKE) stamp-$$c || exit 1 ; \ - done -.PHONY: run-cgen-all - -# For now, require developers to configure with --enable-cgen-maint. -$(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) - @true -stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc - $(MAKE) run-cgen arch=ip2k prefix=ip2k options= \ - archfile=$(CPUDIR)/ip2k.cpu opcfile=$(CPUDIR)/ip2k.opc extrafiles= - -$(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) - @true -stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc - $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst \ - archfile=$(CPUDIR)/m32r.cpu opcfile=$(CPUDIR)/m32r.opc extrafiles=opinst - -$(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) - @true -stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc - $(MAKE) run-cgen arch=fr30 prefix=fr30 options= \ - archfile=$(CPUDIR)/fr30.cpu opcfile=$(CPUDIR)/fr30.opc extrafiles= - -$(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) - 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$(INCDIR)/libiberty.h -# IF YOU PUT ANYTHING HERE IT WILL GO AWAY diff --git a/contrib/binutils/opcodes/Makefile.in b/contrib/binutils/opcodes/Makefile.in deleted file mode 100644 index 559194d..0000000 --- a/contrib/binutils/opcodes/Makefile.in +++ /dev/null @@ -1,1348 +0,0 @@ -# Makefile.in generated automatically by automake 1.4 from Makefile.am - -# Copyright (C) 1994, 1995-8, 1999 Free Software Foundation, Inc. -# This Makefile.in is free software; the Free Software Foundation -# gives unlimited permission to copy and/or distribute it, -# with or without modifications, as long as this notice is preserved. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY, to the extent permitted by law; without -# even the implied warranty of MERCHANTABILITY or FITNESS FOR A -# PARTICULAR PURPOSE. - - -SHELL = @SHELL@ - -srcdir = @srcdir@ -top_srcdir = @top_srcdir@ -VPATH = @srcdir@ -prefix = @prefix@ -exec_prefix = @exec_prefix@ - -bindir = @bindir@ -sbindir = @sbindir@ -libexecdir = @libexecdir@ -datadir = @datadir@ -sysconfdir = @sysconfdir@ -sharedstatedir = @sharedstatedir@ -localstatedir = @localstatedir@ -libdir = @libdir@ -infodir = @infodir@ -mandir = @mandir@ -includedir = @includedir@ -oldincludedir = /usr/include - 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-/* Name of package. */ -#undef PACKAGE - -/* Version of package. */ -#undef VERSION diff --git a/contrib/binutils/opcodes/acinclude.m4 b/contrib/binutils/opcodes/acinclude.m4 deleted file mode 100644 index 3a47b1b..0000000 --- a/contrib/binutils/opcodes/acinclude.m4 +++ /dev/null @@ -1,24 +0,0 @@ -sinclude(../bfd/acinclude.m4) - -dnl sinclude(../libtool.m4) already included in bfd/acinclude.m4 -dnl The lines below arrange for aclocal not to bring libtool.m4 -dnl AM_PROG_LIBTOOL into aclocal.m4, while still arranging for automake -dnl to add a definition of LIBTOOL to Makefile.in. -ifelse(yes,no,[ -AC_DEFUN([AM_PROG_LIBTOOL],) -AC_DEFUN([AM_DISABLE_SHARED],) -AC_SUBST(LIBTOOL) -]) - -dnl sinclude(../gettext.m4) already included in bfd/acinclude.m4 -ifelse(yes,no,[ -AC_DEFUN([CY_WITH_NLS],) -AC_SUBST(INTLLIBS) -]) - -dnl AM_INSTALL_LIBBFD already included in bfd/acinclude.m4 -ifelse(yes,no,[ -AC_DEFUN([AM_INSTALL_LIBBFD],) -AC_SUBST(bfdlibdir) -AC_SUBST(bfdincludedir) -]) diff --git a/contrib/binutils/opcodes/aclocal.m4 b/contrib/binutils/opcodes/aclocal.m4 deleted file mode 100644 index 92732d3..0000000 --- a/contrib/binutils/opcodes/aclocal.m4 +++ /dev/null @@ -1,203 +0,0 @@ -dnl aclocal.m4 generated automatically by aclocal 1.4-p5 - -dnl Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc. -dnl This file is free software; the Free Software Foundation -dnl gives unlimited permission to copy and/or distribute it, -dnl with or without modifications, as long as this notice is preserved. - -dnl This program is distributed in the hope that it will be useful, -dnl but WITHOUT ANY WARRANTY, to the extent permitted by law; without -dnl even the implied warranty of MERCHANTABILITY or FITNESS FOR A -dnl PARTICULAR PURPOSE. - -sinclude(../bfd/acinclude.m4) - -dnl sinclude(../libtool.m4) already included in bfd/acinclude.m4 -dnl The lines below arrange for aclocal not to bring libtool.m4 -dnl AM_PROG_LIBTOOL into aclocal.m4, while still arranging for automake -dnl to add a definition of LIBTOOL to Makefile.in. -ifelse(yes,no,[ -AC_DEFUN([AM_PROG_LIBTOOL],) -AC_DEFUN([AM_DISABLE_SHARED],) -AC_SUBST(LIBTOOL) -]) - -dnl sinclude(../gettext.m4) already included in bfd/acinclude.m4 -ifelse(yes,no,[ -AC_DEFUN([CY_WITH_NLS],) -AC_SUBST(INTLLIBS) -]) - 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See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/alpha.h" - -/* OSF register names. */ - -static const char * const osf_regnames[64] = { - "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", - "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", - "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", - "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", - "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", - "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", - "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", - "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" -}; - -/* VMS register names. */ - -static const char * const vms_regnames[64] = { - "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", - "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", - "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", - "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ", - "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", - "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", - "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", - "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ" -}; - -/* Disassemble Alpha instructions. */ - -int -print_insn_alpha (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - static const struct alpha_opcode *opcode_index[AXP_NOPS+1]; - const char * const * regnames; - const struct alpha_opcode *opcode, *opcode_end; - const unsigned char *opindex; - unsigned insn, op, isa_mask; - int need_comma; - - /* Initialize the majorop table the first time through */ - if (!opcode_index[0]) - { - opcode = alpha_opcodes; - opcode_end = opcode + alpha_num_opcodes; - - for (op = 0; op < AXP_NOPS; ++op) - { - opcode_index[op] = opcode; - while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) - ++opcode; - } - opcode_index[op] = opcode; - } - - if (info->flavour == bfd_target_evax_flavour) - regnames = vms_regnames; - else - regnames = osf_regnames; - - isa_mask = AXP_OPCODE_NOPAL; - switch (info->mach) - { - case bfd_mach_alpha_ev4: - isa_mask |= AXP_OPCODE_EV4; - break; - case bfd_mach_alpha_ev5: - isa_mask |= AXP_OPCODE_EV5; - break; - case bfd_mach_alpha_ev6: - isa_mask |= AXP_OPCODE_EV6; - break; - } - - /* Read the insn into a host word */ - { - bfd_byte buffer[4]; - int status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getl32 (buffer); - } - - /* Get the major opcode of the instruction. */ - op = AXP_OP (insn); - - /* Find the first match in the opcode table. */ - opcode_end = opcode_index[op + 1]; - for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode) - { - if ((insn ^ opcode->opcode) & opcode->mask) - continue; - - if (!(opcode->flags & isa_mask)) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - { - int invalid = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - const struct alpha_operand *operand = alpha_operands + *opindex; - if (operand->extract) - (*operand->extract) (insn, &invalid); - } - if (invalid) - continue; - } - - /* The instruction is valid. */ - goto found; - } - - /* No instruction found */ - (*info->fprintf_func) (info->stream, ".long %#08x", insn); - - return 4; - -found: - (*info->fprintf_func) (info->stream, "%s", opcode->name); - if (opcode->operands[0] != 0) - (*info->fprintf_func) (info->stream, "\t"); - - /* Now extract and print the operands. */ - need_comma = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - const struct alpha_operand *operand = alpha_operands + *opindex; - int value; - - /* Operands that are marked FAKE are simply ignored. We - already made sure that the extract function considered - the instruction to be valid. */ - if ((operand->flags & AXP_OPERAND_FAKE) != 0) - continue; - - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, (int *) NULL); - else - { - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - if (operand->flags & AXP_OPERAND_SIGNED) - { - int signbit = 1 << (operand->bits - 1); - value = (value ^ signbit) - signbit; - } - } - - if (need_comma && - ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA)) - != AXP_OPERAND_PARENS)) - { - (*info->fprintf_func) (info->stream, ","); - } - if (operand->flags & AXP_OPERAND_PARENS) - (*info->fprintf_func) (info->stream, "("); - - /* Print the operand as directed by the flags. */ - if (operand->flags & AXP_OPERAND_IR) - (*info->fprintf_func) (info->stream, "%s", regnames[value]); - else if (operand->flags & AXP_OPERAND_FPR) - (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]); - else if (operand->flags & AXP_OPERAND_RELATIVE) - (*info->print_address_func) (memaddr + 4 + value, info); - else if (operand->flags & AXP_OPERAND_SIGNED) - (*info->fprintf_func) (info->stream, "%d", value); - else - (*info->fprintf_func) (info->stream, "%#x", value); - - if (operand->flags & AXP_OPERAND_PARENS) - (*info->fprintf_func) (info->stream, ")"); - need_comma = 1; - } - - return 4; -} diff --git a/contrib/binutils/opcodes/alpha-opc.c b/contrib/binutils/opcodes/alpha-opc.c deleted file mode 100644 index 5371597..0000000 --- a/contrib/binutils/opcodes/alpha-opc.c +++ /dev/null @@ -1,1551 +0,0 @@ -/* alpha-opc.c -- Alpha AXP opcode list - Copyright 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. - Contributed by Richard Henderson <rth@cygnus.com>, - patterned after the PPC opcode handling written by Ian Lance Taylor. - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/alpha.h" -#include "bfd.h" -#include "opintl.h" - -/* This file holds the Alpha AXP opcode table. The opcode table includes - almost all of the extended instruction mnemonics. This permits the - disassembler to use them, and simplifies the assembler logic, at the - cost of increasing the table size. The table is strictly constant - data, so the compiler should be able to put it in the text segment. - - This file also holds the operand table. All knowledge about inserting - and extracting operands from instructions is kept in this file. - - The information for the base instruction set was compiled from the - _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, - version 2. - - The information for the post-ev5 architecture extensions BWX, CIX and - MAX came from version 3 of this same document, which is also available - on-line at http://ftp.digital.com/pub/Digital/info/semiconductor - /literature/alphahb2.pdf - - The information for the EV4 PALcode instructions was compiled from - _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware - Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary - revision dated June 1994. - - The information for the EV5 PALcode instructions was compiled from - _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital - Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ - -/* Local insertion and extraction functions */ - -static unsigned insert_rba PARAMS((unsigned, int, const char **)); -static unsigned insert_rca PARAMS((unsigned, int, const char **)); -static unsigned insert_za PARAMS((unsigned, int, const char **)); -static unsigned insert_zb PARAMS((unsigned, int, const char **)); -static unsigned insert_zc PARAMS((unsigned, int, const char **)); -static unsigned insert_bdisp PARAMS((unsigned, int, const char **)); -static unsigned insert_jhint PARAMS((unsigned, int, const char **)); -static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **)); - -static int extract_rba PARAMS((unsigned, int *)); -static int extract_rca PARAMS((unsigned, int *)); -static int extract_za PARAMS((unsigned, int *)); -static int extract_zb PARAMS((unsigned, int *)); -static int extract_zc PARAMS((unsigned, int *)); -static int extract_bdisp PARAMS((unsigned, int *)); -static int extract_jhint PARAMS((unsigned, int *)); -static int extract_ev6hwjhint PARAMS((unsigned, int *)); - - -/* The operands table */ - -const struct alpha_operand alpha_operands[] = -{ - /* The fields are bits, shift, insert, extract, flags */ - /* The zero index is used to indicate end-of-list */ -#define UNUSED 0 - { 0, 0, 0, 0, 0, 0 }, - - /* The plain integer register fields */ -#define RA (UNUSED + 1) - { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, -#define RB (RA + 1) - { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, -#define RC (RB + 1) - { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, - - /* The plain fp register fields */ -#define FA (RC + 1) - { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, -#define FB (FA + 1) - { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, -#define FC (FB + 1) - { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, - - /* The integer registers when they are ZERO */ -#define ZA (FC + 1) - { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, -#define ZB (ZA + 1) - { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, -#define ZC (ZB + 1) - { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, - - /* The RB field when it needs parentheses */ -#define PRB (ZC + 1) - { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, - - /* The RB field when it needs parentheses _and_ a preceding comma */ -#define CPRB (PRB + 1) - { 5, 16, 0, - AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, - - /* The RB field when it must be the same as the RA field */ -#define RBA (CPRB + 1) - { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, - - /* The RC field when it must be the same as the RB field */ -#define RCA (RBA + 1) - { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, - - /* The RC field when it can *default* to RA */ -#define DRC1 (RCA + 1) - { 5, 0, 0, - AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, - - /* The RC field when it can *default* to RB */ -#define DRC2 (DRC1 + 1) - { 5, 0, 0, - AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, - - /* The FC field when it can *default* to RA */ -#define DFC1 (DRC2 + 1) - { 5, 0, 0, - AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, - - /* The FC field when it can *default* to RB */ -#define DFC2 (DFC1 + 1) - { 5, 0, 0, - AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, - - /* The unsigned 8-bit literal of Operate format insns */ -#define LIT (DFC2 + 1) - { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The signed 16-bit displacement of Memory format insns. From here - we can't tell what relocation should be used, so don't use a default. */ -#define MDISP (LIT + 1) - { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, - - /* The signed "23-bit" aligned displacement of Branch format insns */ -#define BDISP (MDISP + 1) - { 21, 0, BFD_RELOC_23_PCREL_S2, - AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, - - /* The 26-bit PALcode function */ -#define PALFN (BDISP + 1) - { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */ -#define JMPHINT (PALFN + 1) - { 14, 0, BFD_RELOC_ALPHA_HINT, - AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, - insert_jhint, extract_jhint }, - - /* The optional hint to RET/JSR_COROUTINE */ -#define RETHINT (JMPHINT + 1) - { 14, 0, -RETHINT, - AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, - - /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */ -#define EV4HWDISP (RETHINT + 1) -#define EV6HWDISP (EV4HWDISP) - { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, - - /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */ -#define EV4HWINDEX (EV4HWDISP + 1) - { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns - that occur in DEC PALcode. */ -#define EV4EXTHWINDEX (EV4HWINDEX + 1) - { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */ -#define EV5HWDISP (EV4EXTHWINDEX + 1) - { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, - - /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */ -#define EV5HWINDEX (EV5HWDISP + 1) - { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The 16-bit combined index/scoreboard mask for the ev6 - hw_m[ft]pr (pal19/pal1d) insns */ -#define EV6HWINDEX (EV5HWINDEX + 1) - { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - - /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */ -#define EV6HWJMPHINT (EV6HWINDEX+ 1) - { 8, 0, -EV6HWJMPHINT, - AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, - insert_ev6hwjhint, extract_ev6hwjhint } -}; - -const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); - -/* The RB field when it is the same as the RA field in the same insn. - This operand is marked fake. The insertion function just copies - the RA field into the RB field, and the extraction function just - checks that the fields are the same. */ - -static unsigned -insert_rba(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (((insn >> 21) & 0x1f) << 16); -} - -static int -extract_rba(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) - *invalid = 1; - return 0; -} - - -/* The same for the RC field */ - -static unsigned -insert_rca(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | ((insn >> 21) & 0x1f); -} - -static int -extract_rca(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != (insn & 0x1f)) - *invalid = 1; - return 0; -} - - -/* Fake arguments in which the registers must be set to ZERO */ - -static unsigned -insert_za(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (31 << 21); -} - -static int -extract_za(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) - *invalid = 1; - return 0; -} - -static unsigned -insert_zb(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (31 << 16); -} - -static int -extract_zb(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) - *invalid = 1; - return 0; -} - -static unsigned -insert_zc(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | 31; -} - -static int -extract_zc(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && (insn & 0x1f) != 31) - *invalid = 1; - return 0; -} - - -/* The displacement field of a Branch format insn. */ - -static unsigned -insert_bdisp(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = _("branch operand unaligned"); - return insn | ((value / 4) & 0x1FFFFF); -} - -static int -extract_bdisp(insn, invalid) - unsigned insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); -} - - -/* The hint field of a JMP/JSR insn. */ - -static unsigned -insert_jhint(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = _("jump hint unaligned"); - return insn | ((value / 4) & 0x3FFF); -} - -static int -extract_jhint(insn, invalid) - unsigned insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); -} - -/* The hint field of an EV6 HW_JMP/JSR insn. */ - -static unsigned -insert_ev6hwjhint(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = _("jump hint unaligned"); - return insn | ((value / 4) & 0x1FFF); -} - -static int -extract_ev6hwjhint(insn, invalid) - unsigned insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); -} - - -/* Macros used to form opcodes */ - -/* The main opcode */ -#define OP(x) (((x) & 0x3F) << 26) -#define OP_MASK 0xFC000000 - -/* Branch format instructions */ -#define BRA_(oo) OP(oo) -#define BRA_MASK OP_MASK -#define BRA(oo) BRA_(oo), BRA_MASK - -/* Floating point format instructions */ -#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) -#define FP_MASK (OP_MASK | 0xFFE0) -#define FP(oo,fff) FP_(oo,fff), FP_MASK - -/* Memory format instructions */ -#define MEM_(oo) OP(oo) -#define MEM_MASK OP_MASK -#define MEM(oo) MEM_(oo), MEM_MASK - -/* Memory/Func Code format instructions */ -#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) -#define MFC_MASK (OP_MASK | 0xFFFF) -#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK - -/* Memory/Branch format instructions */ -#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) -#define MBR_MASK (OP_MASK | 0xC000) -#define MBR(oo,h) MBR_(oo,h), MBR_MASK - -/* Operate format instructions. The OPRL variant specifies a - literal second argument. */ -#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) -#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) -#define OPR_MASK (OP_MASK | 0x1FE0) -#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK -#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK - -/* Generic PALcode format instructions */ -#define PCD_(oo) OP(oo) -#define PCD_MASK OP_MASK -#define PCD(oo) PCD_(oo), PCD_MASK - -/* Specific PALcode instructions */ -#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) -#define SPCD_MASK 0xFFFFFFFF -#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK - -/* Hardware memory (hw_{ld,st}) instructions */ -#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) -#define EV4HWMEM_MASK (OP_MASK | 0xF000) -#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK - -#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) -#define EV5HWMEM_MASK (OP_MASK | 0xF800) -#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK - -#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) -#define EV6HWMEM_MASK (OP_MASK | 0xF000) -#define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK - -#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13)) -#define EV6HWMBR_MASK (OP_MASK | 0xE000) -#define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK - -/* Abbreviations for instruction subsets. */ -#define BASE AXP_OPCODE_BASE -#define EV4 AXP_OPCODE_EV4 -#define EV5 AXP_OPCODE_EV5 -#define EV6 AXP_OPCODE_EV6 -#define BWX AXP_OPCODE_BWX -#define CIX AXP_OPCODE_CIX -#define MAX AXP_OPCODE_MAX - -/* Common combinations of arguments */ -#define ARG_NONE { 0 } -#define ARG_BRA { RA, BDISP } -#define ARG_FBRA { FA, BDISP } -#define ARG_FP { FA, FB, DFC1 } -#define ARG_FPZ1 { ZA, FB, DFC1 } -#define ARG_MEM { RA, MDISP, PRB } -#define ARG_FMEM { FA, MDISP, PRB } -#define ARG_OPR { RA, RB, DRC1 } -#define ARG_OPRL { RA, LIT, DRC1 } -#define ARG_OPRZ1 { ZA, RB, DRC1 } -#define ARG_OPRLZ1 { ZA, LIT, RC } -#define ARG_PCD { PALFN } -#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } -#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } -#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } -#define ARG_EV6HWMEM { RA, EV6HWDISP, PRB } - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK { OPERANDS } - - NAME is the name of the instruction. - - OPCODE is the instruction opcode. - - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - - OPERANDS is the list of operands. - - The preceding macros merge the text of the OPCODE and MASK fields. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. - - Otherwise, it is sorted by major opcode and minor function code. - - There are three classes of not-really-instructions in this table: - - ALIAS is another name for another instruction. Some of - these come from the Architecture Handbook, some - come from the original gas opcode tables. In all - cases, the functionality of the opcode is unchanged. - - PSEUDO a stylized code form endorsed by Chapter A.4 of the - Architecture Handbook. - - EXTRA a stylized code form found in the original gas tables. - - And two annotations: - - EV56 BUT opcodes that are officially introduced as of the ev56, - but with defined results on previous implementations. - - EV56 UNA opcodes that were introduced as of the ev56 with - presumably undefined results on previous implementations - that were not assigned to a particular extension. -*/ - -const struct alpha_opcode alpha_opcodes[] = { - { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, - { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, - { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, - { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE }, - { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, - { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, - { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, - { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE }, - { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE }, - { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE }, - { "call_pal", PCD(0x00), BASE, ARG_PCD }, - { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ - - { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */ - { "lda", MEM(0x08), BASE, ARG_MEM }, - { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */ - { "ldah", MEM(0x09), BASE, ARG_MEM }, - { "ldbu", MEM(0x0A), BWX, ARG_MEM }, - { "unop", MEM_(0x0B) | (30 << 16), - MEM_MASK, BASE, { ZA } }, /* pseudo */ - { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, - { "ldwu", MEM(0x0C), BWX, ARG_MEM }, - { "stw", MEM(0x0D), BWX, ARG_MEM }, - { "stb", MEM(0x0E), BWX, ARG_MEM }, - { "stq_u", MEM(0x0F), BASE, ARG_MEM }, - - { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ - { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, - { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, - { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, - { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, - { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ - { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, - { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, - { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, - { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, - { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, - { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, - { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, - { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, - { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, - { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, - { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, - { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, - { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, - { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, - { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, - { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, - { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ - { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, - { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, - { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, - { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, - { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, - { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, - { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, - { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, - { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, - { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, - { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, - { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, - { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, - { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, - { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ - { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, - { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, - { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, - { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, - { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, - { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, - { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ - { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, - { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, - { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, - { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, - - { "and", OPR(0x11,0x00), BASE, ARG_OPR }, - { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, - { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ - { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ - { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, - { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, - { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, - { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, - { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, - { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, - { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ - { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ - { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ - { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ - { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ - { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ - { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ - { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, - { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, - { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, - { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, - { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, - { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, - { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ - { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ - { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, - { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, - { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, - { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, - { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, - { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, - { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, - { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, - { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, - { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, - { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ - { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ - { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ - { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ - { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, - { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, - { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, - { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, - { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), - 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ - - { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, - { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, - { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, - { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, - { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, - { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, - { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, - { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, - { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, - { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, - { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, - { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, - { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, - { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, - { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, - { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, - { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, - { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, - { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, - { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, - { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, - { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, - { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, - { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, - { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, - { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, - { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, - { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, - { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, - { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, - { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, - { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, - { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, - { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, - { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, - { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, - { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, - { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, - { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, - { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, - { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, - { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, - { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, - { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, - { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, - { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, - { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, - { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, - { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, - { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, - { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, - { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, - - { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, - { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, - { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, - { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, - { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, - { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, - { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, - { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, - { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, - { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, - - { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, - { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, - { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, - { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, - { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, - { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, - { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, - { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, - { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 }, - { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, - { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, - { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, - { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, - { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 }, - { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 }, - { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 }, - { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 }, - { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 }, - { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 }, - { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 }, - { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 }, - { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 }, - { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 }, - { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 }, - { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 }, - { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 }, - { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 }, - { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 }, - { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 }, - { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 }, - { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 }, - { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 }, - { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 }, - { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 }, - { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 }, - { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 }, - { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 }, - { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 }, - { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 }, - { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 }, - { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 }, - { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 }, - { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 }, - { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 }, - { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 }, - { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 }, - { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 }, - { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 }, - { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 }, - { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 }, - { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 }, - - { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, - { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, - { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, - { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, - { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, - { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, - { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, - { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, - { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, - { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, - { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, - { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, - { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, - { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, - { "addf", FP(0x15,0x080), BASE, ARG_FP }, - { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ - { "subf", FP(0x15,0x081), BASE, ARG_FP }, - { "mulf", FP(0x15,0x082), BASE, ARG_FP }, - { "divf", FP(0x15,0x083), BASE, ARG_FP }, - { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, - { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, - { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, - { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, - { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, - { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, - { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, - { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, - { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, - { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, - { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, - { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, - { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, - { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, - { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, - { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, - { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, - { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, - { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, - { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, - { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, - { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, - { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, - { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, - { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, - { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, - { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, - { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, - { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, - { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, - { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, - { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, - { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, - { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, - { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, - { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, - { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, - { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, - { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, - { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, - { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, - { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, - { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, - { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, - { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, - { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, - { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, - { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, - { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, - { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, - { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ - { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, - { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, - { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, - { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, - { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, - { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, - { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, - { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, - { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, - { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, - { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, - { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, - { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, - { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, - { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, - { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, - { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, - { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, - { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, - { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, - { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, - { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, - { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, - { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, - { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, - { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, - { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, - { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, - { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, - { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, - { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, - { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, - { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, - { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, - { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, - { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, - { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, - { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, - - { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, - { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, - { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, - { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, - { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, - { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, - { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, - { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, - { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, - { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, - { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, - { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, - { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, - { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, - { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, - { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, - { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, - { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, - { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, - { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, - { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, - { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, - { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, - { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, - { "adds", FP(0x16,0x080), BASE, ARG_FP }, - { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ - { "subs", FP(0x16,0x081), BASE, ARG_FP }, - { "muls", FP(0x16,0x082), BASE, ARG_FP }, - { "divs", FP(0x16,0x083), BASE, ARG_FP }, - { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, - { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, - { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, - { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, - { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, - { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, - { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, - { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, - { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, - { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, - { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, - { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, - { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, - { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, - { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, - { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, - { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, - { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, - { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, - { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, - { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, - { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, - { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, - { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, - { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, - { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, - { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, - { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, - { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, - { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, - { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, - { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, - { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, - { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, - { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, - { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, - { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, - { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, - { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, - { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, - { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, - { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, - { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, - { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, - { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, - { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, - { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, - { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, - { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, - { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, - { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, - { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, - { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, - { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, - { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, - { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, - { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, - { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, - { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, - { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, - { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, - { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, - { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, - { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, - { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, - { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, - { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, - { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, - { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, - { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, - { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, - { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, - { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, - { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, - { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, - { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, - { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, - { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, - { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, - { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, - { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, - { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, - { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, - { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, - { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, - { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, - { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ - { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, - { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, - { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, - { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, - { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, - { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, - { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, - { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, - { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, - { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, - { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, - { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, - { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, - { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, - { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, - { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, - { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, - { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, - { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, - { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, - { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, - { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, - { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, - { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, - { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, - { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, - { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, - { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, - { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, - { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, - { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, - { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, - { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, - { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, - { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, - { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, - { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, - { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, - { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, - { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, - { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, - { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, - { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, - { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, - { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, - { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, - { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, - { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, - { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, - { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ - { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, - { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, - { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, - { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, - { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ - { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, - { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, - { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, - { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, - { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, - { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, - { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, - { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, - { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, - { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, - { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, - { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, - { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, - { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, - { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, - { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, - { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, - { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, - { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, - - { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, - { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ - { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ - { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ - { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ - { "cpys", FP(0x17,0x020), BASE, ARG_FP }, - { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ - { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, - { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, - { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, - { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, - { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, - { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, - { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, - { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, - { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, - { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, - { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, - { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, - { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, - - { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, - { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ - { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, - { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, - { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, - { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, - { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, - { "rpcc", MFC(0x18,0xC000), BASE, { RA, ZB } }, - { "rpcc", MFC(0x18,0xC000), BASE, { RA, RB } }, /* ev6 una */ - { "rc", MFC(0x18,0xE000), BASE, { RA } }, - { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ - { "rs", MFC(0x18,0xF000), BASE, { RA } }, - { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ - { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */ - - { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, - { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, - { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } }, - { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, - { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, - { "pal19", PCD(0x19), BASE, ARG_PCD }, - - { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */ - BASE, { ZA, CPRB } }, - { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, - { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, - { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */ - 0xFFFFFFFF, BASE, { 0 } }, - { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, - { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ - { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, - - { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, - { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, - { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM }, - { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, - { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, - { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM }, - { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, - { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, - { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, - { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, - { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, - { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, - { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, - { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, - { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, - { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, - { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, - { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM }, - { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, - { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, - { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, - { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, - { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, - { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, - { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, - { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, - { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, - { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM }, - { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, - { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, - { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM }, - { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM }, - { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, - { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, - { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM }, - { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, - { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, - { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, - { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, - { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM }, - { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, - { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, - { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM }, - { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, - { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, - { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, - { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, - { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, - { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, - { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, - { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, - { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, - { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, - { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, - { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM }, - { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, - { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, - { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, - { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, - { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, - { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, - { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, - { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, - { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, - { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM }, - { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, - { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, - { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM }, - { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM }, - { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, - { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, - { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM }, - { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, - { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, - { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, - { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, - { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, - { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, - { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, - { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, - { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, - { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, - { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, - { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, - { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, - { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, - { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, - { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, - { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, - { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, - { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, - { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, - { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, - { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, - { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, - { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, - { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, - { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, - { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, - { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, - { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, - { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, - { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, - { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, - { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, - { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, - { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, - { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, - { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, - { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, - { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, - { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, - { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, - { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, - { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, - { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, - { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, - { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, - { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, - { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, - { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, - { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, - { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, - { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, - { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, - { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, - { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, - { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, - { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, - { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, - { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, - { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, - { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, - { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, - { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, - { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, - { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, - { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, - { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, - { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, - { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, - { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, - { "pal1b", PCD(0x1B), BASE, ARG_PCD }, - - { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, - { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, - { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, - { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, - { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, - { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, - { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, - { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, - { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, - { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, - { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, - { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, - { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, - { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, - { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, - { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, - { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, - { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, - { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, - { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, - { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, - { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, - { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, - { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, - { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, - { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, - { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, - { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, - - { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, - { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, - { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } }, - { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, - { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, - { "pal1d", PCD(0x1D), BASE, ARG_PCD }, - - { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, - { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, - { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } }, - { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } }, - { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } }, - { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, - { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */ - { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } }, - { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } }, - { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } }, - { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, - { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */ - { "pal1e", PCD(0x1E), BASE, ARG_PCD }, - - { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, - { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, - { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */ - { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, - { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, - { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM }, - { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, - { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, - { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, - { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, - { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, - { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, - { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, - { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM }, - { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, - { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, - { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, - { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, - { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, - { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, - { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, - { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, - { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, - { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, - { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, - { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, - { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM }, - { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, - { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, - { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, - { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, - { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */ - { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, - { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, - { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM }, - { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, - { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, - { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, - { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, - { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, - { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, - { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, - { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM }, - { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, - { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, - { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, - { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, - { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, - { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, - { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, - { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, - { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, - { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, - { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, - { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, - { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, - { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, - { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM }, - { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, - { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, - { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, - { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, - { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, - { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, - { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, - { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, - { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, - { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, - { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, - { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, - { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, - { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, - { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, - { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, - { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, - { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, - { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, - { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, - { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, - { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, - { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, - { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, - { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, - { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, - { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, - { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, - { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, - { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, - { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, - { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, - { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, - { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, - { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, - { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, - { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, - { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, - { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, - { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, - { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, - { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, - { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, - { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, - { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, - { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, - { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, - { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, - { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, - { "pal1f", PCD(0x1F), BASE, ARG_PCD }, - - { "ldf", MEM(0x20), BASE, ARG_FMEM }, - { "ldg", MEM(0x21), BASE, ARG_FMEM }, - { "lds", MEM(0x22), BASE, ARG_FMEM }, - { "ldt", MEM(0x23), BASE, ARG_FMEM }, - { "stf", MEM(0x24), BASE, ARG_FMEM }, - { "stg", MEM(0x25), BASE, ARG_FMEM }, - { "sts", MEM(0x26), BASE, ARG_FMEM }, - { "stt", MEM(0x27), BASE, ARG_FMEM }, - - { "ldl", MEM(0x28), BASE, ARG_MEM }, - { "ldq", MEM(0x29), BASE, ARG_MEM }, - { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, - { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, - { "stl", MEM(0x2C), BASE, ARG_MEM }, - { "stq", MEM(0x2D), BASE, ARG_MEM }, - { "stl_c", MEM(0x2E), BASE, ARG_MEM }, - { "stq_c", MEM(0x2F), BASE, ARG_MEM }, - - { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ - { "br", BRA(0x30), BASE, ARG_BRA }, - { "fbeq", BRA(0x31), BASE, ARG_FBRA }, - { "fblt", BRA(0x32), BASE, ARG_FBRA }, - { "fble", BRA(0x33), BASE, ARG_FBRA }, - { "bsr", BRA(0x34), BASE, ARG_BRA }, - { "fbne", BRA(0x35), BASE, ARG_FBRA }, - { "fbge", BRA(0x36), BASE, ARG_FBRA }, - { "fbgt", BRA(0x37), BASE, ARG_FBRA }, - { "blbc", BRA(0x38), BASE, ARG_BRA }, - { "beq", BRA(0x39), BASE, ARG_BRA }, - { "blt", BRA(0x3A), BASE, ARG_BRA }, - { "ble", BRA(0x3B), BASE, ARG_BRA }, - { "blbs", BRA(0x3C), BASE, ARG_BRA }, - { "bne", BRA(0x3D), BASE, ARG_BRA }, - { "bge", BRA(0x3E), BASE, ARG_BRA }, - { "bgt", BRA(0x3F), BASE, ARG_BRA }, -}; - -const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); diff --git a/contrib/binutils/opcodes/arc-dis.c b/contrib/binutils/opcodes/arc-dis.c deleted file mode 100644 index 194a75a..0000000 --- a/contrib/binutils/opcodes/arc-dis.c +++ /dev/null @@ -1,1246 +0,0 @@ -/* Instruction printing code for the ARC. - Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002 - Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "ansidecl.h" -#include "libiberty.h" -#include "dis-asm.h" -#include "opcode/arc.h" -#include "elf-bfd.h" -#include "elf/arc.h" -#include <string.h> -#include "opintl.h" - -#include <stdarg.h> -#include "arc-dis.h" -#include "arc-ext.h" - -#ifndef dbg -#define dbg (0) -#endif - -#define BIT(word,n) ((word) & (1 << n)) -#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) -#define OPCODE(word) (BITS ((word), 27, 31)) -#define FIELDA(word) (BITS ((word), 21, 26)) -#define FIELDB(word) (BITS ((word), 15, 20)) -#define FIELDC(word) (BITS ((word), 9, 14)) - -/* FIELD D is signed in all of its uses, so we make sure argument is - treated as signed for bit shifting purposes: */ -#define FIELDD(word) (BITS (((signed int)word), 0, 8)) - -#define PUT_NEXT_WORD_IN(a) \ - do \ - { \ - if (is_limm == 1 && !NEXT_WORD (1)) \ - mwerror (state, _("Illegal limm reference in last instruction!\n")); \ - a = state->words[1]; \ - } \ - while (0) - -#define CHECK_FLAG_COND_NULLIFY() \ - do \ - { \ - if (is_shimm == 0) \ - { \ - flag = BIT (state->words[0], 8); \ - state->nullifyMode = BITS (state->words[0], 5, 6); \ - cond = BITS (state->words[0], 0, 4); \ - } \ - } \ - while (0) - -#define CHECK_COND() \ - do \ - { \ - if (is_shimm == 0) \ - cond = BITS (state->words[0], 0, 4); \ - } \ - while (0) - -#define CHECK_FIELD(field) \ - do \ - { \ - if (field == 62) \ - { \ - is_limm++; \ - field##isReg = 0; \ - PUT_NEXT_WORD_IN (field); \ - limm_value = field; \ - } \ - else if (field > 60) \ - { \ - field##isReg = 0; \ - is_shimm++; \ - flag = (field == 61); \ - field = FIELDD (state->words[0]); \ - } \ - } \ - while (0) - -#define CHECK_FIELD_A() \ - do \ - { \ - fieldA = FIELDA (state->words[0]); \ - if (fieldA > 60) \ - { \ - fieldAisReg = 0; \ - fieldA = 0; \ - } \ - } \ - while (0) - -#define CHECK_FIELD_B() \ - do \ - { \ - fieldB = FIELDB (state->words[0]); \ - CHECK_FIELD (fieldB); \ - } \ - while (0) - -#define CHECK_FIELD_C() \ - do \ - { \ - fieldC = FIELDC (state->words[0]); \ - CHECK_FIELD (fieldC); \ - } \ - while (0) - -#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) -#define IS_REG(x) (field##x##isReg) -#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","") -#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[") -#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]") -#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]") -#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","") -#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",") -#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","") -#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \ - (IS_REG (x) ? cb1"%r"ca1 : \ - usesAuxReg ? cb"%a"ca : \ - IS_SMALL (x) ? cb"%d"ca : cb"%h"ca)) -#define WRITE_FORMAT_RB() strcat (formatString, "]") -#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str)) -#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop"); - -#define NEXT_WORD(x) (offset += 4, state->words[x]) - -#define add_target(x) (state->targets[state->tcnt++] = (x)) - -static char comment_prefix[] = "\t; "; - -static const char *core_reg_name PARAMS ((struct arcDisState *, int)); -static const char *aux_reg_name PARAMS ((struct arcDisState *, int)); -static const char *cond_code_name PARAMS ((struct arcDisState *, int)); -static const char *instruction_name - PARAMS ((struct arcDisState *, int, int, int *)); -static void mwerror PARAMS ((struct arcDisState *, const char *)); -static const char *post_address PARAMS ((struct arcDisState *, int)); -static void write_comments_ - PARAMS ((struct arcDisState *, int, int, long int)); -static void write_instr_name_ - PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int)); -static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *)); -static const char *_coreRegName PARAMS ((void *, int)); -static int decodeInstr PARAMS ((bfd_vma, disassemble_info *)); - -static const char * -core_reg_name (state, val) - struct arcDisState * state; - int val; -{ - if (state->coreRegName) - return (*state->coreRegName)(state->_this, val); - return 0; -} - -static const char * -aux_reg_name (state, val) - struct arcDisState * state; - int val; -{ - if (state->auxRegName) - return (*state->auxRegName)(state->_this, val); - return 0; -} - -static const char * -cond_code_name (state, val) - struct arcDisState * state; - int val; -{ - if (state->condCodeName) - return (*state->condCodeName)(state->_this, val); - return 0; -} - -static const char * -instruction_name (state, op1, op2, flags) - struct arcDisState * state; - int op1; - int op2; - int * flags; -{ - if (state->instName) - return (*state->instName)(state->_this, op1, op2, flags); - return 0; -} - -static void -mwerror (state, msg) - struct arcDisState * state; - const char * msg; -{ - if (state->err != 0) - (*state->err)(state->_this, (msg)); -} - -static const char * -post_address (state, addr) - struct arcDisState * state; - int addr; -{ - static char id[3 * ARRAY_SIZE (state->addresses)]; - int j, i = state->acnt; - - if (i < ((int) ARRAY_SIZE (state->addresses))) - { - state->addresses[i] = addr; - ++state->acnt; - j = i*3; - id[j+0] = '@'; - id[j+1] = '0'+i; - id[j+2] = 0; - - return id + j; - } - return ""; -} - -static void my_sprintf PARAMS ((struct arcDisState *, char *, const char *, - ...)); - -static void -my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format, - ...)) -{ - char *bp; - const char *p; - int size, leading_zero, regMap[2]; - long auxNum; - - VA_OPEN (ap, format); - VA_FIXEDARG (ap, struct arcDisState *, state); - VA_FIXEDARG (ap, char *, buf); - VA_FIXEDARG (ap, const char *, format); - - bp = buf; - *bp = 0; - p = format; - auxNum = -1; - regMap[0] = 0; - regMap[1] = 0; - - while (1) - switch (*p++) - { - case 0: - goto DOCOMM; /* (return) */ - default: - *bp++ = p[-1]; - break; - case '%': - size = 0; - leading_zero = 0; - RETRY: ; - switch (*p++) - { - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - { - /* size. */ - size = p[-1] - '0'; - if (size == 0) - leading_zero = 1; /* e.g. %08x */ - while (*p >= '0' && *p <= '9') - { - size = size * 10 + *p - '0'; - p++; - } - goto RETRY; - } -#define inc_bp() bp = bp + strlen (bp) - - case 'h': - { - unsigned u = va_arg (ap, int); - - /* Hex. We can change the format to 0x%08x in - one place, here, if we wish. - We add underscores for easy reading. */ - if (u > 65536) - sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff); - else - sprintf (bp, "0x%x", u); - inc_bp (); - } - break; - case 'X': case 'x': - { - int val = va_arg (ap, int); - - if (size != 0) - if (leading_zero) - sprintf (bp, "%0*x", size, val); - else - sprintf (bp, "%*x", size, val); - else - sprintf (bp, "%x", val); - inc_bp (); - } - break; - case 'd': - { - int val = va_arg (ap, int); - - if (size != 0) - sprintf (bp, "%*d", size, val); - else - sprintf (bp, "%d", val); - inc_bp (); - } - break; - case 'r': - { - /* Register. */ - int val = va_arg (ap, int); - -#define REG2NAME(num, name) case num: sprintf (bp, ""name); \ - regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break; - - switch (val) - { - REG2NAME (26, "gp"); - REG2NAME (27, "fp"); - REG2NAME (28, "sp"); - REG2NAME (29, "ilink1"); - REG2NAME (30, "ilink2"); - REG2NAME (31, "blink"); - REG2NAME (60, "lp_count"); - default: - { - const char * ext; - - ext = core_reg_name (state, val); - if (ext) - sprintf (bp, "%s", ext); - else - sprintf (bp,"r%d",val); - } - break; - } - inc_bp (); - } break; - - case 'a': - { - /* Aux Register. */ - int val = va_arg (ap, int); - -#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break; - - switch (val) - { - AUXREG2NAME (0x0, "status"); - AUXREG2NAME (0x1, "semaphore"); - AUXREG2NAME (0x2, "lp_start"); - AUXREG2NAME (0x3, "lp_end"); - AUXREG2NAME (0x4, "identity"); - AUXREG2NAME (0x5, "debug"); - default: - { - const char *ext; - - ext = aux_reg_name (state, val); - if (ext) - sprintf (bp, "%s", ext); - else - my_sprintf (state, bp, "%h", val); - } - break; - } - inc_bp (); - } - break; - - case 's': - { - sprintf (bp, "%s", va_arg (ap, char *)); - inc_bp (); - } - break; - - default: - fprintf (stderr, "?? format %c\n", p[-1]); - break; - } - } - - DOCOMM: *bp = 0; - VA_CLOSE (ap); -} - -static void -write_comments_(state, shimm, is_limm, limm_value) - struct arcDisState * state; - int shimm; - int is_limm; - long limm_value; -{ - if (state->commentBuffer != 0) - { - int i; - - if (is_limm) - { - const char *name = post_address (state, limm_value + shimm); - - if (*name != 0) - WRITE_COMMENT (name); - } - for (i = 0; i < state->commNum; i++) - { - if (i == 0) - strcpy (state->commentBuffer, comment_prefix); - else - strcat (state->commentBuffer, ", "); - strncat (state->commentBuffer, state->comm[i], - sizeof (state->commentBuffer)); - } - } -} - -#define write_comments2(x) write_comments_(state, x, is_limm, limm_value) -#define write_comments() write_comments2(0) - -static const char *condName[] = { - /* 0..15. */ - "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , - "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" -}; - -static void -write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem) - struct arcDisState * state; - const char * instrName; - int cond; - int condCodeIsPartOfName; - int flag; - int signExtend; - int addrWriteBack; - int directMem; -{ - strcpy (state->instrBuffer, instrName); - - if (cond > 0) - { - const char *cc = 0; - - if (!condCodeIsPartOfName) - strcat (state->instrBuffer, "."); - - if (cond < 16) - cc = condName[cond]; - else - cc = cond_code_name (state, cond); - - if (!cc) - cc = "???"; - - strcat (state->instrBuffer, cc); - } - - if (flag) - strcat (state->instrBuffer, ".f"); - - switch (state->nullifyMode) - { - case BR_exec_always: - strcat (state->instrBuffer, ".d"); - break; - case BR_exec_when_jump: - strcat (state->instrBuffer, ".jd"); - break; - } - - if (signExtend) - strcat (state->instrBuffer, ".x"); - - if (addrWriteBack) - strcat (state->instrBuffer, ".a"); - - if (directMem) - strcat (state->instrBuffer, ".di"); -} - -#define write_instr_name() \ - do \ - { \ - write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \ - flag, signExtend, addrWriteBack, directMem); \ - formatString[0] = '\0'; \ - } \ - while (0) - -enum { - op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, - op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, - op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, - op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15 -}; - -extern disassemble_info tm_print_insn_info; - -static int -dsmOneArcInst (addr, state) - bfd_vma addr; - struct arcDisState * state; -{ - int condCodeIsPartOfName = 0; - int decodingClass; - const char * instrName; - int repeatsOp = 0; - int fieldAisReg = 1; - int fieldBisReg = 1; - int fieldCisReg = 1; - int fieldA; - int fieldB; - int fieldC = 0; - int flag = 0; - int cond = 0; - int is_shimm = 0; - int is_limm = 0; - long limm_value = 0; - int signExtend = 0; - int addrWriteBack = 0; - int directMem = 0; - int is_linked = 0; - int offset = 0; - int usesAuxReg = 0; - int flags; - int ignoreFirstOpd; - char formatString[60]; - - state->instructionLen = 4; - state->nullifyMode = BR_exec_when_no_jump; - state->opWidth = 12; - state->isBranch = 0; - - state->_mem_load = 0; - state->_ea_present = 0; - state->_load_len = 0; - state->ea_reg1 = no_reg; - state->ea_reg2 = no_reg; - state->_offset = 0; - - if (! NEXT_WORD (0)) - return 0; - - state->_opcode = OPCODE (state->words[0]); - instrName = 0; - decodingClass = 0; /* default! */ - repeatsOp = 0; - condCodeIsPartOfName=0; - state->commNum = 0; - state->tcnt = 0; - state->acnt = 0; - state->flow = noflow; - ignoreFirstOpd = 0; - - if (state->commentBuffer) - state->commentBuffer[0] = '\0'; - - switch (state->_opcode) - { - case op_LD0: - switch (BITS (state->words[0],1,2)) - { - case 0: - instrName = "ld"; - state->_load_len = 4; - break; - case 1: - instrName = "ldb"; - state->_load_len = 1; - break; - case 2: - instrName = "ldw"; - state->_load_len = 2; - break; - default: - instrName = "??? (0[3])"; - state->flow = invalid_instr; - break; - } - decodingClass = 5; - break; - - case op_LD1: - if (BIT (state->words[0],13)) - { - instrName = "lr"; - decodingClass = 10; - } - else - { - switch (BITS (state->words[0],10,11)) - { - case 0: - instrName = "ld"; - state->_load_len = 4; - break; - case 1: - instrName = "ldb"; - state->_load_len = 1; - break; - case 2: - instrName = "ldw"; - state->_load_len = 2; - break; - default: - instrName = "??? (1[3])"; - state->flow = invalid_instr; - break; - } - decodingClass = 6; - } - break; - - case op_ST: - if (BIT (state->words[0],25)) - { - instrName = "sr"; - decodingClass = 8; - } - else - { - switch (BITS (state->words[0],22,23)) - { - case 0: - instrName = "st"; - break; - case 1: - instrName = "stb"; - break; - case 2: - instrName = "stw"; - break; - default: - instrName = "??? (2[3])"; - state->flow = invalid_instr; - break; - } - decodingClass = 7; - } - break; - - case op_3: - decodingClass = 1; /* default for opcode 3... */ - switch (FIELDC (state->words[0])) - { - case 0: - instrName = "flag"; - decodingClass = 2; - break; - case 1: - instrName = "asr"; - break; - case 2: - instrName = "lsr"; - break; - case 3: - instrName = "ror"; - break; - case 4: - instrName = "rrc"; - break; - case 5: - instrName = "sexb"; - break; - case 6: - instrName = "sexw"; - break; - case 7: - instrName = "extb"; - break; - case 8: - instrName = "extw"; - break; - case 0x3f: - { - decodingClass = 9; - switch( FIELDD (state->words[0]) ) - { - case 0: - instrName = "brk"; - break; - case 1: - instrName = "sleep"; - break; - case 2: - instrName = "swi"; - break; - default: - instrName = "???"; - state->flow=invalid_instr; - break; - } - } - break; - - /* ARC Extension Library Instructions - NOTE: We assume that extension codes are these instrs. */ - default: - instrName = instruction_name (state, - state->_opcode, - FIELDC (state->words[0]), - &flags); - if (!instrName) - { - instrName = "???"; - state->flow = invalid_instr; - } - if (flags & IGNORE_FIRST_OPD) - ignoreFirstOpd = 1; - break; - } - break; - - case op_BC: - instrName = "b"; - case op_BLC: - if (!instrName) - instrName = "bl"; - case op_LPC: - if (!instrName) - instrName = "lp"; - case op_JC: - if (!instrName) - { - if (BITS (state->words[0],9,9)) - { - instrName = "jl"; - is_linked = 1; - } - else - { - instrName = "j"; - is_linked = 0; - } - } - condCodeIsPartOfName = 1; - decodingClass = ((state->_opcode == op_JC) ? 4 : 3); - state->isBranch = 1; - break; - - case op_ADD: - case op_ADC: - case op_AND: - repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0])); - decodingClass = 0; - - switch (state->_opcode) - { - case op_ADD: - instrName = (repeatsOp ? "asl" : "add"); - break; - case op_ADC: - instrName = (repeatsOp ? "rlc" : "adc"); - break; - case op_AND: - instrName = (repeatsOp ? "mov" : "and"); - break; - } - break; - - case op_SUB: instrName = "sub"; - break; - case op_SBC: instrName = "sbc"; - break; - case op_OR: instrName = "or"; - break; - case op_BIC: instrName = "bic"; - break; - - case op_XOR: - if (state->words[0] == 0x7fffffff) - { - /* nop encoded as xor -1, -1, -1 */ - instrName = "nop"; - decodingClass = 9; - } - else - instrName = "xor"; - break; - - default: - instrName = instruction_name (state,state->_opcode,0,&flags); - /* if (instrName) printf("FLAGS=0x%x\n", flags); */ - if (!instrName) - { - instrName = "???"; - state->flow=invalid_instr; - } - if (flags & IGNORE_FIRST_OPD) - ignoreFirstOpd = 1; - break; - } - - fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */ - flag = cond = is_shimm = is_limm = 0; - state->nullifyMode = BR_exec_when_no_jump; /* 0 */ - signExtend = addrWriteBack = directMem = 0; - usesAuxReg = 0; - - switch (decodingClass) - { - case 0: - CHECK_FIELD_A (); - CHECK_FIELD_B (); - if (!repeatsOp) - CHECK_FIELD_C (); - CHECK_FLAG_COND_NULLIFY (); - - write_instr_name (); - if (!ignoreFirstOpd) - { - WRITE_FORMAT_x (A); - WRITE_FORMAT_COMMA_x (B); - if (!repeatsOp) - WRITE_FORMAT_COMMA_x (C); - WRITE_NOP_COMMENT (); - my_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB, fieldC); - } - else - { - WRITE_FORMAT_x (B); - if (!repeatsOp) - WRITE_FORMAT_COMMA_x (C); - my_sprintf (state, state->operandBuffer, formatString, - fieldB, fieldC); - } - write_comments (); - break; - - case 1: - CHECK_FIELD_A (); - CHECK_FIELD_B (); - CHECK_FLAG_COND_NULLIFY (); - - write_instr_name (); - if (!ignoreFirstOpd) - { - WRITE_FORMAT_x (A); - WRITE_FORMAT_COMMA_x (B); - WRITE_NOP_COMMENT (); - my_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB); - } - else - { - WRITE_FORMAT_x (B); - my_sprintf (state, state->operandBuffer, formatString, fieldB); - } - write_comments (); - break; - - case 2: - CHECK_FIELD_B (); - CHECK_FLAG_COND_NULLIFY (); - flag = 0; /* this is the FLAG instruction -- it's redundant */ - - write_instr_name (); - WRITE_FORMAT_x (B); - my_sprintf (state, state->operandBuffer, formatString, fieldB); - write_comments (); - break; - - case 3: - fieldA = BITS (state->words[0],7,26) << 2; - fieldA = (fieldA << 10) >> 10; /* make it signed */ - fieldA += addr + 4; - CHECK_FLAG_COND_NULLIFY (); - flag = 0; - - write_instr_name (); - /* This address could be a label we know. Convert it. */ - if (state->_opcode != op_LPC /* LP */) - { - add_target (fieldA); /* For debugger. */ - state->flow = state->_opcode == op_BLC /* BL */ - ? direct_call - : direct_jump; - /* indirect calls are achieved by "lr blink,[status]; - lr dest<- func addr; j [dest]" */ - } - - strcat (formatString, "%s"); /* address/label name */ - my_sprintf (state, state->operandBuffer, formatString, - post_address (state, fieldA)); - write_comments (); - break; - - case 4: - /* For op_JC -- jump to address specified. - Also covers jump and link--bit 9 of the instr. word - selects whether linked, thus "is_linked" is set above. */ - fieldA = 0; - CHECK_FIELD_B (); - CHECK_FLAG_COND_NULLIFY (); - - if (!fieldBisReg) - { - fieldAisReg = 0; - fieldA = (fieldB >> 25) & 0x7F; /* flags */ - fieldB = (fieldB & 0xFFFFFF) << 2; - state->flow = is_linked ? direct_call : direct_jump; - add_target (fieldB); - /* screwy JLcc requires .jd mode to execute correctly - * but we pretend it is .nd (no delay slot). */ - if (is_linked && state->nullifyMode == BR_exec_when_jump) - state->nullifyMode = BR_exec_when_no_jump; - } - else - { - state->flow = is_linked ? indirect_call : indirect_jump; - /* We should also treat this as indirect call if NOT linked - * but the preceding instruction was a "lr blink,[status]" - * and we have a delay slot with "add blink,blink,2". - * For now we can't detect such. */ - state->register_for_indirect_jump = fieldB; - } - - write_instr_name (); - strcat (formatString, - IS_REG (B) ? "[%r]" : "%s"); /* address/label name */ - if (fieldA != 0) - { - fieldAisReg = 0; - WRITE_FORMAT_COMMA_x (A); - } - if (IS_REG (B)) - my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); - else - my_sprintf (state, state->operandBuffer, formatString, - post_address (state, fieldB), fieldA); - write_comments (); - break; - - case 5: - /* LD instruction. - B and C can be regs, or one (both?) can be limm. */ - CHECK_FIELD_A (); - CHECK_FIELD_B (); - CHECK_FIELD_C (); - if (dbg) - printf ("5:b reg %d %d c reg %d %d \n", - fieldBisReg,fieldB,fieldCisReg,fieldC); - state->_offset = 0; - state->_ea_present = 1; - if (fieldBisReg) - state->ea_reg1 = fieldB; - else - state->_offset += fieldB; - if (fieldCisReg) - state->ea_reg2 = fieldC; - else - state->_offset += fieldC; - state->_mem_load = 1; - - directMem = BIT (state->words[0],5); - addrWriteBack = BIT (state->words[0],3); - signExtend = BIT (state->words[0],0); - - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB(A); - if (fieldBisReg || fieldB != 0) - WRITE_FORMAT_x_COMMA (B); - else - fieldB = fieldC; - - WRITE_FORMAT_x_RB (C); - my_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB, fieldC); - write_comments (); - break; - - case 6: - /* LD instruction. */ - CHECK_FIELD_B (); - CHECK_FIELD_A (); - fieldC = FIELDD (state->words[0]); - - if (dbg) - printf ("6:b reg %d %d c 0x%x \n", - fieldBisReg, fieldB, fieldC); - state->_ea_present = 1; - state->_offset = fieldC; - state->_mem_load = 1; - if (fieldBisReg) - state->ea_reg1 = fieldB; - /* field B is either a shimm (same as fieldC) or limm (different!) - Say ea is not present, so only one of us will do the name lookup. */ - else - state->_offset += fieldB, state->_ea_present = 0; - - directMem = BIT (state->words[0],14); - addrWriteBack = BIT (state->words[0],12); - signExtend = BIT (state->words[0],9); - - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB (A); - if (!fieldBisReg) - { - fieldB = state->_offset; - WRITE_FORMAT_x_RB (B); - } - else - { - WRITE_FORMAT_x (B); - if (fieldC != 0 && !BIT (state->words[0],13)) - { - fieldCisReg = 0; - WRITE_FORMAT_COMMA_x_RB (C); - } - else - WRITE_FORMAT_RB (); - } - my_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB, fieldC); - write_comments (); - break; - - case 7: - /* ST instruction. */ - CHECK_FIELD_B(); - CHECK_FIELD_C(); - fieldA = FIELDD(state->words[0]); /* shimm */ - - /* [B,A offset] */ - if (dbg) printf("7:b reg %d %x off %x\n", - fieldBisReg,fieldB,fieldA); - state->_ea_present = 1; - state->_offset = fieldA; - if (fieldBisReg) - state->ea_reg1 = fieldB; - /* field B is either a shimm (same as fieldA) or limm (different!) - Say ea is not present, so only one of us will do the name lookup. - (for is_limm we do the name translation here). */ - else - state->_offset += fieldB, state->_ea_present = 0; - - directMem = BIT(state->words[0],26); - addrWriteBack = BIT(state->words[0],24); - - write_instr_name(); - WRITE_FORMAT_x_COMMA_LB(C); - - if (!fieldBisReg) - { - fieldB = state->_offset; - WRITE_FORMAT_x_RB(B); - } - else - { - WRITE_FORMAT_x(B); - if (fieldBisReg && fieldA != 0) - { - fieldAisReg = 0; - WRITE_FORMAT_COMMA_x_RB(A); - } - else - WRITE_FORMAT_RB(); - } - my_sprintf (state, state->operandBuffer, formatString, - fieldC, fieldB, fieldA); - write_comments2(fieldA); - break; - case 8: - /* SR instruction */ - CHECK_FIELD_B(); - CHECK_FIELD_C(); - - write_instr_name(); - WRITE_FORMAT_x_COMMA_LB(C); - /* Try to print B as an aux reg if it is not a core reg. */ - usesAuxReg = 1; - WRITE_FORMAT_x(B); - WRITE_FORMAT_RB(); - my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); - write_comments(); - break; - - case 9: - write_instr_name(); - state->operandBuffer[0] = '\0'; - break; - - case 10: - /* LR instruction */ - CHECK_FIELD_A(); - CHECK_FIELD_B(); - - write_instr_name(); - WRITE_FORMAT_x_COMMA_LB(A); - /* Try to print B as an aux reg if it is not a core reg. */ - usesAuxReg = 1; - WRITE_FORMAT_x(B); - WRITE_FORMAT_RB(); - my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); - write_comments(); - break; - - case 11: - CHECK_COND(); - write_instr_name(); - state->operandBuffer[0] = '\0'; - break; - - default: - mwerror (state, "Bad decoding class in ARC disassembler"); - break; - } - - state->_cond = cond; - return state->instructionLen = offset; -} - - -/* Returns the name the user specified core extension register. */ -static const char * -_coreRegName(arg, regval) - void * arg ATTRIBUTE_UNUSED; - int regval; -{ - return arcExtMap_coreRegName (regval); -} - -/* Returns the name the user specified AUX extension register. */ -static const char * -_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) -{ - return arcExtMap_auxRegName(regval); -} - - -/* Returns the name the user specified condition code name. */ -static const char * -_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) -{ - return arcExtMap_condCodeName(regval); -} - -/* Returns the name the user specified extension instruction. */ -static const char * -_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) -{ - return arcExtMap_instName(majop, minop, flags); -} - -/* Decode an instruction returning the size of the instruction - in bytes or zero if unrecognized. */ -static int -decodeInstr (address, info) - bfd_vma address; /* Address of this instruction. */ - disassemble_info * info; -{ - int status; - bfd_byte buffer[4]; - struct arcDisState s; /* ARC Disassembler state */ - void *stream = info->stream; /* output stream */ - fprintf_ftype func = info->fprintf_func; - int bytes; - - memset (&s, 0, sizeof(struct arcDisState)); - - /* read first instruction */ - status = (*info->read_memory_func) (address, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, address, info); - return 0; - } - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[0] = bfd_getl32(buffer); - else - s.words[0] = bfd_getb32(buffer); - /* always read second word in case of limm */ - - /* we ignore the result since last insn may not have a limm */ - status = (*info->read_memory_func) (address + 4, buffer, 4, info); - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[1] = bfd_getl32(buffer); - else - s.words[1] = bfd_getb32(buffer); - - s._this = &s; - s.coreRegName = _coreRegName; - s.auxRegName = _auxRegName; - s.condCodeName = _condCodeName; - s.instName = _instName; - - /* disassemble */ - bytes = dsmOneArcInst(address, (void *)&s); - - /* display the disassembly instruction */ - (*func) (stream, "%08x ", s.words[0]); - (*func) (stream, " "); - - (*func) (stream, "%-10s ", s.instrBuffer); - - if (__TRANSLATION_REQUIRED(s)) - { - bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; - (*info->print_address_func) ((bfd_vma) addr, info); - (*func) (stream, "\n"); - } - else - (*func) (stream, "%s",s.operandBuffer); - return s.instructionLen; -} - -/* Return the print_insn function to use. - Side effect: load (possibly empty) extension section */ - -disassembler_ftype -arc_get_disassembler (void *ptr) -{ - if (ptr) - build_ARC_extmap (ptr); - return decodeInstr; -} diff --git a/contrib/binutils/opcodes/arc-dis.h b/contrib/binutils/opcodes/arc-dis.h deleted file mode 100644 index 04bfbbb..0000000 --- a/contrib/binutils/opcodes/arc-dis.h +++ /dev/null @@ -1,81 +0,0 @@ -/* Disassembler structures definitions for the ARC. - Copyright 1994, 1995, 1997, 1998, 2000, 2001 - Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#ifndef ARCDIS_H -#define ARCDIS_H - -enum -{ - BR_exec_when_no_jump, - BR_exec_always, - BR_exec_when_jump -}; - -enum Flow -{ - noflow, - direct_jump, - direct_call, - indirect_jump, - indirect_call, - invalid_instr -}; - -enum { no_reg = 99 }; -enum { allOperandsSize = 256 }; - -struct arcDisState -{ - void *_this; - int instructionLen; - void (*err)(void*, const char*); - const char *(*coreRegName)(void*, int); - const char *(*auxRegName)(void*, int); - const char *(*condCodeName)(void*, int); - const char *(*instName)(void*, int, int, int*); - - unsigned char* instruction; - unsigned index; - const char *comm[6]; /* instr name, cond, NOP, 3 operands */ - int opWidth; - int targets[4]; - int addresses[4]; - /* Set as a side-effect of calling the disassembler. - Used only by the debugger. */ - enum Flow flow; - int register_for_indirect_jump; - int ea_reg1, ea_reg2, _offset; - int _cond, _opcode; - unsigned long words[2]; - char *commentBuffer; - char instrBuffer[40]; - char operandBuffer[allOperandsSize]; - char _ea_present; - char _mem_load; - char _load_len; - char nullifyMode; - unsigned char commNum; - unsigned char isBranch; - unsigned char tcnt; - unsigned char acnt; -}; - -#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0) - -#endif diff --git a/contrib/binutils/opcodes/arc-ext.c b/contrib/binutils/opcodes/arc-ext.c deleted file mode 100644 index fd43d29..0000000 --- a/contrib/binutils/opcodes/arc-ext.c +++ /dev/null @@ -1,260 +0,0 @@ -/* ARC target-dependent stuff. Extension structure access functions - Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc. - - This file is part of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdlib.h> -#include <stdio.h> -#include "bfd.h" -#include "arc-ext.h" -#include "libiberty.h" - -/* Extension structure */ -static struct arcExtMap arc_extension_map; - -/* Get the name of an extension instruction. */ - -const char * -arcExtMap_instName(int opcode, int minor, int *flags) -{ - if (opcode == 3) - { - /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */ - if (minor < 0x09 || minor == 0x3f) - return 0; - else - opcode = 0x1f - 0x10 + minor - 0x09 + 1; - } - else - if (opcode < 0x10) - return 0; - else - opcode -= 0x10; - if (!arc_extension_map.instructions[opcode]) - return 0; - *flags = arc_extension_map.instructions[opcode]->flags; - return arc_extension_map.instructions[opcode]->name; -} - -/* Get the name of an extension core register. */ - -const char * -arcExtMap_coreRegName(int value) -{ - if (value < 32) - return 0; - return (const char *) arc_extension_map.coreRegisters[value-32]; -} - -/* Get the name of an extension condition code. */ - -const char * -arcExtMap_condCodeName(int value) -{ - if (value < 16) - return 0; - return (const char *) arc_extension_map.condCodes[value-16]; -} - -/* Get the name of an extension aux register. */ - -const char * -arcExtMap_auxRegName(long address) -{ - /* walk the list of aux reg names and find the name */ - struct ExtAuxRegister *r; - - for (r = arc_extension_map.auxRegisters; r; r = r->next) { - if (r->address == address) - return (const char *) r->name; - } - return 0; -} - -/* Recursively free auxilliary register strcture pointers until - the list is empty. */ - -static void -clean_aux_registers(struct ExtAuxRegister *r) -{ - if (r -> next) - { - clean_aux_registers( r->next); - free(r -> name); - free(r -> next); - r ->next = NULL; - } - else - free(r -> name); -} - -/* Free memory that has been allocated for the extensions. */ - -static void -cleanup_ext_map(void) -{ - struct ExtAuxRegister *r; - struct ExtInstruction *insn; - int i; - - /* clean aux reg structure */ - r = arc_extension_map.auxRegisters; - if (r) - { - (clean_aux_registers(r)); - free(r); - } - - /* clean instructions */ - for (i = 0; i < NUM_EXT_INST; i++) - { - insn = arc_extension_map.instructions[i]; - if (insn) - free(insn->name); - } - - /* clean core reg struct */ - for (i = 0; i < NUM_EXT_CORE; i++) - { - if (arc_extension_map.coreRegisters[i]) - free(arc_extension_map.coreRegisters[i]); - } - - for (i = 0; i < NUM_EXT_COND; i++) { - if (arc_extension_map.condCodes[i]) - free(arc_extension_map.condCodes[i]); - } - - memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); -} - -int -arcExtMap_add(void *base, unsigned long length) -{ - unsigned char *block = base; - unsigned char *p = block; - - /* Clean up and reset everything if needed. */ - cleanup_ext_map(); - - while (p && p < (block + length)) - { - /* p[0] == length of record - p[1] == type of record - For instructions: - p[2] = opcode - p[3] = minor opcode (if opcode == 3) - p[4] = flags - p[5]+ = name - For core regs and condition codes: - p[2] = value - p[3]+ = name - For aux regs: - p[2..5] = value - p[6]+ = name - (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */ - - if (p[0] == 0) - return -1; - - switch (p[1]) - { - case EXT_INSTRUCTION: - { - char opcode = p[2]; - char minor = p[3]; - char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char)); - struct ExtInstruction * insn = - (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction)); - - if (opcode==3) - opcode = 0x1f - 0x10 + minor - 0x09 + 1; - else - opcode -= 0x10; - insn -> flags = (char) *(p+4); - strcpy(insn_name, (p+5)); - insn -> name = insn_name; - arc_extension_map.instructions[(int) opcode] = insn; - } - break; - - case EXT_CORE_REGISTER: - { - char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char)); - - strcpy(core_name, (p+3)); - arc_extension_map.coreRegisters[p[2]-32] = core_name; - } - break; - - case EXT_COND_CODE: - { - char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char)); - strcpy(cc_name, (p+3)); - arc_extension_map.condCodes[p[2]-16] = cc_name; - } - break; - - case EXT_AUX_REGISTER: - { - /* trickier -- need to store linked list to these */ - struct ExtAuxRegister *newAuxRegister = - (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister)); - char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char)); - - strcpy (aux_name, (p+6)); - newAuxRegister->name = aux_name; - newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5]; - newAuxRegister->next = arc_extension_map.auxRegisters; - arc_extension_map.auxRegisters = newAuxRegister; - } - break; - - default: - return -1; - - } - p += p[0]; /* move to next record */ - } - - return 0; -} - -/* Load hw extension descibed in .extArcMap ELF section. */ - -void -build_ARC_extmap (text_bfd) - bfd *text_bfd; -{ - char *arcExtMap; - bfd_size_type count; - asection *p; - - for (p = text_bfd->sections; p != NULL; p = p->next) - if (!strcmp (p->name, ".arcextmap")) - { - count = p->_raw_size; - arcExtMap = (char *) xmalloc (count); - if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count)) - { - arcExtMap_add ((PTR) arcExtMap, count); - break; - } - free ((PTR) arcExtMap); - } -} diff --git a/contrib/binutils/opcodes/arc-ext.h b/contrib/binutils/opcodes/arc-ext.h deleted file mode 100644 index bfe9750b..0000000 --- a/contrib/binutils/opcodes/arc-ext.h +++ /dev/null @@ -1,62 +0,0 @@ -/* ARC target-dependent stuff. Extension data structures. - Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#ifndef ARCEXT_H -#define ARCEXT_H - -enum {EXT_INSTRUCTION = 0}; -enum {EXT_CORE_REGISTER = 1}; -enum {EXT_AUX_REGISTER = 2}; -enum {EXT_COND_CODE = 3}; - -enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)}; -enum {NUM_EXT_CORE = 59-32+1}; -enum {NUM_EXT_COND = 0x1f-0x10+1}; - -struct ExtInstruction -{ - char flags; - char *name; -}; - -struct ExtAuxRegister -{ - long address; - char *name; - struct ExtAuxRegister *next; -}; - -struct arcExtMap -{ - struct ExtAuxRegister *auxRegisters; - struct ExtInstruction *instructions[NUM_EXT_INST]; - unsigned char *coreRegisters[NUM_EXT_CORE]; - unsigned char *condCodes[NUM_EXT_COND]; -}; - -extern int arcExtMap_add(void*, unsigned long); -extern const char *arcExtMap_coreRegName(int); -extern const char *arcExtMap_auxRegName(long); -extern const char *arcExtMap_condCodeName(int); -extern const char *arcExtMap_instName(int, int, int*); -extern void build_ARC_extmap(bfd *); - -#define IGNORE_FIRST_OPD 1 - -#endif diff --git a/contrib/binutils/opcodes/arc-opc.c b/contrib/binutils/opcodes/arc-opc.c deleted file mode 100644 index 614fff0..0000000 --- a/contrib/binutils/opcodes/arc-opc.c +++ /dev/null @@ -1,1822 +0,0 @@ -/* Opcode table for the ARC. - Copyright 1994, 1995, 1997, 1998, 2000, 2001 - Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "bfd.h" -#include "opcode/arc.h" - -#define INSERT_FN(fn) \ -static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \ - int, const struct arc_operand_value *, long, \ - const char **)) -#define EXTRACT_FN(fn) \ -static long fn PARAMS ((arc_insn *, const struct arc_operand *, \ - int, const struct arc_operand_value **, int *)) - -INSERT_FN (insert_reg); -INSERT_FN (insert_shimmfinish); -INSERT_FN (insert_limmfinish); -INSERT_FN (insert_offset); -INSERT_FN (insert_base); -INSERT_FN (insert_st_syntax); -INSERT_FN (insert_ld_syntax); -INSERT_FN (insert_addr_wb); -INSERT_FN (insert_flag); -INSERT_FN (insert_nullify); -INSERT_FN (insert_flagfinish); -INSERT_FN (insert_cond); -INSERT_FN (insert_forcelimm); -INSERT_FN (insert_reladdr); -INSERT_FN (insert_absaddr); -INSERT_FN (insert_jumpflags); -INSERT_FN (insert_unopmacro); - -EXTRACT_FN (extract_reg); -EXTRACT_FN (extract_ld_offset); -EXTRACT_FN (extract_ld_syntax); -EXTRACT_FN (extract_st_offset); -EXTRACT_FN (extract_st_syntax); -EXTRACT_FN (extract_flag); -EXTRACT_FN (extract_cond); -EXTRACT_FN (extract_reladdr); -EXTRACT_FN (extract_jumpflags); -EXTRACT_FN (extract_unopmacro); - -enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; - -#define OPERANDS 3 - -enum operand ls_operand[OPERANDS]; - -struct arc_opcode *arc_ext_opcodes; -struct arc_ext_operand_value *arc_ext_operands; - -#define LS_VALUE 0 -#define LS_DEST 0 -#define LS_BASE 1 -#define LS_OFFSET 2 - -/* Various types of ARC operands, including insn suffixes. */ - -/* Insn format values: - - 'a' REGA register A field - 'b' REGB register B field - 'c' REGC register C field - 'S' SHIMMFINISH finish inserting a shimm value - 'L' LIMMFINISH finish inserting a limm value - 'o' OFFSET offset in st insns - 'O' OFFSET offset in ld insns - '0' SYNTAX_ST_NE enforce store insn syntax, no errors - '1' SYNTAX_LD_NE enforce load insn syntax, no errors - '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only - '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only - 's' BASE base in st insn - 'f' FLAG F flag - 'F' FLAGFINISH finish inserting the F flag - 'G' FLAGINSN insert F flag in "flag" insn - 'n' DELAY N field (nullify field) - 'q' COND condition code field - 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm - 'B' BRANCH branch address (22 bit pc relative) - 'J' JUMP jump address (26 bit absolute) - 'j' JUMPFLAGS optional high order bits of 'J' - 'z' SIZE1 size field in ld a,[b,c] - 'Z' SIZE10 size field in ld a,[b,shimm] - 'y' SIZE22 size field in st c,[b,shimm] - 'x' SIGN0 sign extend field ld a,[b,c] - 'X' SIGN9 sign extend field ld a,[b,shimm] - 'w' ADDRESS3 write-back field in ld a,[b,c] - 'W' ADDRESS12 write-back field in ld a,[b,shimm] - 'v' ADDRESS24 write-back field in st c,[b,shimm] - 'e' CACHEBYPASS5 cache bypass in ld a,[b,c] - 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm] - 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm] - 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros - - The following modifiers may appear between the % and char (eg: %.f): - - '.' MODDOT '.' prefix must be present - 'r' REG generic register value, for register table - 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] - - Fields are: - - CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */ - -const struct arc_operand arc_operands[] = -{ -/* place holder (??? not sure if needed). */ -#define UNUSED 0 - { 0, 0, 0, 0, 0, 0 }, - -/* register A or shimm/limm indicator. */ -#define REGA (UNUSED + 1) - { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, - -/* register B or shimm/limm indicator. */ -#define REGB (REGA + 1) - { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, - -/* register C or shimm/limm indicator. */ -#define REGC (REGB + 1) - { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, - -/* fake operand used to insert shimm value into most instructions. */ -#define SHIMMFINISH (REGC + 1) - { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, - -/* fake operand used to insert limm value into most instructions. */ -#define LIMMFINISH (SHIMMFINISH + 1) - { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, - -/* shimm operand when there is no reg indicator (st). */ -#define ST_OFFSET (LIMMFINISH + 1) - { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset }, - -/* shimm operand when there is no reg indicator (ld). */ -#define LD_OFFSET (ST_OFFSET + 1) - { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset }, - -/* operand for base. */ -#define BASE (LD_OFFSET + 1) - { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg}, - -/* 0 enforce syntax for st insns. */ -#define SYNTAX_ST_NE (BASE + 1) - { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax }, - -/* 1 enforce syntax for ld insns. */ -#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1) - { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax }, - -/* 0 enforce syntax for st insns. */ -#define SYNTAX_ST (SYNTAX_LD_NE + 1) - { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax }, - -/* 0 enforce syntax for ld insns. */ -#define SYNTAX_LD (SYNTAX_ST + 1) - { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax }, - -/* flag update bit (insertion is defered until we know how). */ -#define FLAG (SYNTAX_LD + 1) - { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, - -/* fake utility operand to finish 'f' suffix handling. */ -#define FLAGFINISH (FLAG + 1) - { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, - -/* fake utility operand to set the 'f' flag for the "flag" insn. */ -#define FLAGINSN (FLAGFINISH + 1) - { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, - -/* branch delay types. */ -#define DELAY (FLAGINSN + 1) - { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 }, - -/* conditions. */ -#define COND (DELAY + 1) - { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, - -/* set `cond_p' to 1 to ensure a constant is treated as a limm. */ -#define FORCELIMM (COND + 1) - { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 }, - -/* branch address; b, bl, and lp insns. */ -#define BRANCH (FORCELIMM + 1) - { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr }, - -/* jump address; j insn (this is basically the same as 'L' except that the - value is right shifted by 2). */ -#define JUMP (BRANCH + 1) - { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 }, - -/* jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */ -#define JUMPFLAGS (JUMP + 1) - { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags }, - -/* size field, stored in bit 1,2. */ -#define SIZE1 (JUMPFLAGS + 1) - { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* size field, stored in bit 10,11. */ -#define SIZE10 (SIZE1 + 1) - { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* size field, stored in bit 22,23. */ -#define SIZE22 (SIZE10 + 1) - { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* sign extend field, stored in bit 0. */ -#define SIGN0 (SIZE22 + 1) - { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* sign extend field, stored in bit 9. */ -#define SIGN9 (SIGN0 + 1) - { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* address write back, stored in bit 3. */ -#define ADDRESS3 (SIGN9 + 1) - { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, - -/* address write back, stored in bit 12. */ -#define ADDRESS12 (ADDRESS3 + 1) - { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, - -/* address write back, stored in bit 24. */ -#define ADDRESS24 (ADDRESS12 + 1) - { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, - -/* cache bypass, stored in bit 5. */ -#define CACHEBYPASS5 (ADDRESS24 + 1) - { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* cache bypass, stored in bit 14. */ -#define CACHEBYPASS14 (CACHEBYPASS5 + 1) - { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* cache bypass, stored in bit 26. */ -#define CACHEBYPASS26 (CACHEBYPASS14 + 1) - { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* unop macro, used to copy REGB to REGC. */ -#define UNOPMACRO (CACHEBYPASS26 + 1) - { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, - -/* '.' modifier ('.' required). */ -#define MODDOT (UNOPMACRO + 1) - { '.', 1, 0, ARC_MOD_DOT, 0, 0 }, - -/* Dummy 'r' modifier for the register table. - It's called a "dummy" because there's no point in inserting an 'r' into all - the %a/%b/%c occurrences in the insn table. */ -#define REG (MODDOT + 1) - { 'r', 6, 0, ARC_MOD_REG, 0, 0 }, - -/* Known auxiliary register modifier (stored in shimm field). */ -#define AUXREG (REG + 1) - { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 }, - -/* end of list place holder. */ - { 0, 0, 0, 0, 0, 0 } -}; - -/* Given a format letter, yields the index into `arc_operands'. - eg: arc_operand_map['a'] = REGA. */ -unsigned char arc_operand_map[256]; - -/* ARC instructions. - - Longer versions of insns must appear before shorter ones (if gas sees - "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is - junk). This isn't necessary for `ld' because of the trailing ']'. - - Instructions that are really macros based on other insns must appear - before the real insn so they're chosen when disassembling. Eg: The `mov' - insn is really the `and' insn. */ - -struct arc_opcode arc_opcodes[] = -{ - /* Base case instruction set (core versions 5-8) */ - - /* "mov" is really an "and". */ - { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 }, - /* "asl" is really an "add". */ - { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, - /* "lsl" is really an "add". */ - { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, - /* "nop" is really an "xor". */ - { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 }, - /* "rlc" is really an "adc". */ - { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 }, - { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 }, - { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 }, - { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 }, - { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 }, - { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 }, - { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 }, - { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 }, - { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 }, - { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 }, - { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 }, - { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 }, - /* %Q: force cond_p=1 -> no shimm values. This insn allows an - optional flags spec. */ - { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - /* This insn allows an optional flags spec. */ - { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - /* Put opcode 1 ld insns first so shimm gets prefered over limm. - "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ - { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 }, - { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, - { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, - { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 }, - { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 }, - { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 }, - { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 }, - { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 }, - { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 }, - { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 }, - { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 }, - { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 }, - { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 }, - { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 }, - /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ - { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, - { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, - { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 }, - { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 } -}; - -const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); - -const struct arc_operand_value arc_reg_names[] = -{ - /* Core register set r0-r63. */ - - /* r0-r28 - general purpose registers. */ - { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 }, - { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 }, - { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 }, - { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 }, - { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 }, - { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 }, - { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 }, - { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 }, - { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 }, - { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 }, - /* Maskable interrupt link register. */ - { "ilink1", 29, REG, 0 }, - /* Maskable interrupt link register. */ - { "ilink2", 30, REG, 0 }, - /* Branch-link register. */ - { "blink", 31, REG, 0 }, - - /* r32-r59 reserved for extensions. */ - { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 }, - { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 }, - { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 }, - { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 }, - { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 }, - { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 }, - { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 }, - { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 }, - { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 }, - { "r59", 59, REG, 0 }, - - /* Loop count register (24 bits). */ - { "lp_count", 60, REG, 0 }, - /* Short immediate data indicator setting flags. */ - { "r61", 61, REG, ARC_REGISTER_READONLY }, - /* Long immediate data indicator setting flags. */ - { "r62", 62, REG, ARC_REGISTER_READONLY }, - /* Short immediate data indicator not setting flags. */ - { "r63", 63, REG, ARC_REGISTER_READONLY }, - - /* Small-data base register. */ - { "gp", 26, REG, 0 }, - /* Frame pointer. */ - { "fp", 27, REG, 0 }, - /* Stack pointer. */ - { "sp", 28, REG, 0 }, - - { "r29", 29, REG, 0 }, - { "r30", 30, REG, 0 }, - { "r31", 31, REG, 0 }, - { "r60", 60, REG, 0 }, - - /* Auxiliary register set. */ - - /* Auxiliary register address map: - 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation - 0xfffffeff-0x80000000 - customer limm allocation - 0x7fffffff-0x00000100 - ARC limm allocation - 0x000000ff-0x00000000 - ARC shimm allocation */ - - /* Base case auxiliary registers (shimm address). */ - { "status", 0x00, AUXREG, 0 }, - { "semaphore", 0x01, AUXREG, 0 }, - { "lp_start", 0x02, AUXREG, 0 }, - { "lp_end", 0x03, AUXREG, 0 }, - { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY }, - { "debug", 0x05, AUXREG, 0 }, -}; - -const int arc_reg_names_count = - sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); - -/* The suffix table. - Operands with the same name must be stored together. */ - -const struct arc_operand_value arc_suffixes[] = -{ - /* Entry 0 is special, default values aren't printed by the disassembler. */ - { "", 0, -1, 0 }, - - /* Base case condition codes. */ - { "al", 0, COND, 0 }, - { "ra", 0, COND, 0 }, - { "eq", 1, COND, 0 }, - { "z", 1, COND, 0 }, - { "ne", 2, COND, 0 }, - { "nz", 2, COND, 0 }, - { "pl", 3, COND, 0 }, - { "p", 3, COND, 0 }, - { "mi", 4, COND, 0 }, - { "n", 4, COND, 0 }, - { "cs", 5, COND, 0 }, - { "c", 5, COND, 0 }, - { "lo", 5, COND, 0 }, - { "cc", 6, COND, 0 }, - { "nc", 6, COND, 0 }, - { "hs", 6, COND, 0 }, - { "vs", 7, COND, 0 }, - { "v", 7, COND, 0 }, - { "vc", 8, COND, 0 }, - { "nv", 8, COND, 0 }, - { "gt", 9, COND, 0 }, - { "ge", 10, COND, 0 }, - { "lt", 11, COND, 0 }, - { "le", 12, COND, 0 }, - { "hi", 13, COND, 0 }, - { "ls", 14, COND, 0 }, - { "pnz", 15, COND, 0 }, - - /* Condition codes 16-31 reserved for extensions. */ - - { "f", 1, FLAG, 0 }, - - { "nd", ARC_DELAY_NONE, DELAY, 0 }, - { "d", ARC_DELAY_NORMAL, DELAY, 0 }, - { "jd", ARC_DELAY_JUMP, DELAY, 0 }, - - { "b", 1, SIZE1, 0 }, - { "b", 1, SIZE10, 0 }, - { "b", 1, SIZE22, 0 }, - { "w", 2, SIZE1, 0 }, - { "w", 2, SIZE10, 0 }, - { "w", 2, SIZE22, 0 }, - { "x", 1, SIGN0, 0 }, - { "x", 1, SIGN9, 0 }, - { "a", 1, ADDRESS3, 0 }, - { "a", 1, ADDRESS12, 0 }, - { "a", 1, ADDRESS24, 0 }, - - { "di", 1, CACHEBYPASS5, 0 }, - { "di", 1, CACHEBYPASS14, 0 }, - { "di", 1, CACHEBYPASS26, 0 }, -}; - -const int arc_suffixes_count = - sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); - -/* Indexed by first letter of opcode. Points to chain of opcodes with same - first letter. */ -static struct arc_opcode *opcode_map[26 + 1]; - -/* Indexed by insn code. Points to chain of opcodes with same insn code. */ -static struct arc_opcode *icode_map[32]; - -/* Configuration flags. */ - -/* Various ARC_HAVE_XXX bits. */ -static int cpu_type; - -/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ - -int -arc_get_opcode_mach (bfd_mach, big_p) - int bfd_mach, big_p; -{ - static int mach_type_map[] = - { - ARC_MACH_5, - ARC_MACH_6, - ARC_MACH_7, - ARC_MACH_8 - }; - return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0); -} - -/* Initialize any tables that need it. - Must be called once at start up (or when first needed). - - FLAGS is a set of bits that say what version of the cpu we have, - and in particular at least (one of) ARC_MACH_XXX. */ - -void -arc_opcode_init_tables (flags) - int flags; -{ - static int init_p = 0; - - cpu_type = flags; - - /* We may be intentionally called more than once (for example gdb will call - us each time the user switches cpu). These tables only need to be init'd - once though. */ - if (!init_p) - { - register int i,n; - - memset (arc_operand_map, 0, sizeof (arc_operand_map)); - n = sizeof (arc_operands) / sizeof (arc_operands[0]); - for (i = 0; i < n; ++i) - arc_operand_map[arc_operands[i].fmt] = i; - - memset (opcode_map, 0, sizeof (opcode_map)); - memset (icode_map, 0, sizeof (icode_map)); - /* Scan the table backwards so macros appear at the front. */ - for (i = arc_opcodes_count - 1; i >= 0; --i) - { - int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); - int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); - - arc_opcodes[i].next_asm = opcode_map[opcode_hash]; - opcode_map[opcode_hash] = &arc_opcodes[i]; - - arc_opcodes[i].next_dis = icode_map[icode_hash]; - icode_map[icode_hash] = &arc_opcodes[i]; - } - - init_p = 1; - } -} - -/* Return non-zero if OPCODE is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opcode_supported (opcode) - const struct arc_opcode *opcode; -{ - if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type) - return 1; - return 0; -} - -/* Return the first insn in the chain for assembling INSN. */ - -const struct arc_opcode * -arc_opcode_lookup_asm (insn) - const char *insn; -{ - return opcode_map[ARC_HASH_OPCODE (insn)]; -} - -/* Return the first insn in the chain for disassembling INSN. */ - -const struct arc_opcode * -arc_opcode_lookup_dis (insn) - unsigned int insn; -{ - return icode_map[ARC_HASH_ICODE (insn)]; -} - -/* Nonzero if we've seen an 'f' suffix (in certain insns). */ -static int flag_p; - -/* Nonzero if we've finished processing the 'f' suffix. */ -static int flagshimm_handled_p; - -/* Nonzero if we've seen a 'a' suffix (address writeback). */ -static int addrwb_p; - -/* Nonzero if we've seen a 'q' suffix (condition code). */ -static int cond_p; - -/* Nonzero if we've inserted a nullify condition. */ -static int nullify_p; - -/* The value of the a nullify condition we inserted. */ -static int nullify; - -/* Nonzero if we've inserted jumpflags. */ -static int jumpflags_p; - -/* Nonzero if we've inserted a shimm. */ -static int shimm_p; - -/* The value of the shimm we inserted (each insn only gets one but it can - appear multiple times). */ -static int shimm; - -/* Nonzero if we've inserted a limm (during assembly) or seen a limm - (during disassembly). */ -static int limm_p; - -/* The value of the limm we inserted. Each insn only gets one but it can - appear multiple times. */ -static long limm; - -/* Insertion functions. */ - -/* Called by the assembler before parsing an instruction. */ - -void -arc_opcode_init_insert () -{ - int i; - - for(i = 0; i < OPERANDS; i++) - ls_operand[i] = OP_NONE; - - flag_p = 0; - flagshimm_handled_p = 0; - cond_p = 0; - addrwb_p = 0; - shimm_p = 0; - limm_p = 0; - jumpflags_p = 0; - nullify_p = 0; - nullify = 0; /* the default is important. */ -} - -/* Called by the assembler to see if the insn has a limm operand. - Also called by the disassembler to see if the insn contains a limm. */ - -int -arc_opcode_limm_p (limmp) - long *limmp; -{ - if (limmp) - *limmp = limm; - return limm_p; -} - -/* Insert a value into a register field. - If REG is NULL, then this is actually a constant. - - We must also handle auxiliary registers for lr/sr insns. */ - -static arc_insn -insert_reg (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - static char buf[100]; - enum operand op_type = OP_NONE; - - if (reg == NULL) - { - /* We have a constant that also requires a value stored in a register - field. Handle these by updating the register field and saving the - value for later handling by either %S (shimm) or %L (limm). */ - - /* Try to use a shimm value before a limm one. */ - if (ARC_SHIMM_CONST_P (value) - /* If we've seen a conditional suffix we have to use a limm. */ - && !cond_p - /* If we already have a shimm value that is different than ours - we have to use a limm. */ - && (!shimm_p || shimm == value)) - { - int marker; - - op_type = OP_SHIMM; - /* forget about shimm as dest mlm. */ - - if ('a' != operand->fmt) - { - shimm_p = 1; - shimm = value; - flagshimm_handled_p = 1; - marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; - } - else - { - /* don't request flag setting on shimm as dest. */ - marker = ARC_REG_SHIMM; - } - insn |= marker << operand->shift; - /* insn |= value & 511; - done later. */ - } - /* We have to use a limm. If we've already seen one they must match. */ - else if (!limm_p || limm == value) - { - op_type = OP_LIMM; - limm_p = 1; - limm = value; - insn |= ARC_REG_LIMM << operand->shift; - /* The constant is stored later. */ - } - else - { - *errmsg = "unable to fit different valued constants into instruction"; - } - } - else - { - /* We have to handle both normal and auxiliary registers. */ - - if (reg->type == AUXREG) - { - if (!(mods & ARC_MOD_AUXREG)) - *errmsg = "auxiliary register not allowed here"; - else - { - if ((insn & I(-1)) == I(2)) /* check for use validity. */ - { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = "attempt to set readonly register"; - } - else - { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = "attempt to read writeonly register"; - } - insn |= ARC_REG_SHIMM << operand->shift; - insn |= reg->value << arc_operands[reg->type].shift; - } - } - else - { - /* check for use validity. */ - if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) - { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = "attempt to set readonly register"; - } - if ('a' != operand->fmt) - { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = "attempt to read writeonly register"; - } - /* We should never get an invalid register number here. */ - if ((unsigned int) reg->value > 60) - { - sprintf (buf, "invalid register number `%d'", reg->value); - *errmsg = buf; - } - insn |= reg->value << operand->shift; - op_type = OP_REG; - } - } - - switch (operand->fmt) - { - case 'a': - ls_operand[LS_DEST] = op_type; - break; - case 's': - ls_operand[LS_BASE] = op_type; - break; - case 'c': - if ((insn & I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; - case 'o': case 'O': - ls_operand[LS_OFFSET] = op_type; - break; - } - - return insn; -} - -/* Called when we see an 'f' flag. */ - -static arc_insn -insert_flag (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - /* We can't store anything in the insn until we've parsed the registers. - Just record the fact that we've got this flag. `insert_reg' will use it - to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ - flag_p = 1; - return insn; -} - -/* Called when we see an nullify condition. */ - -static arc_insn -insert_nullify (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - nullify_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - nullify = value; - return insn; -} - -/* Called after completely building an insn to ensure the 'f' flag gets set - properly. This is needed because we don't know how to set this flag until - we've parsed the registers. */ - -static arc_insn -insert_flagfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - if (flag_p && !flagshimm_handled_p) - { - if (shimm_p) - abort (); - flagshimm_handled_p = 1; - insn |= (1 << operand->shift); - } - return insn; -} - -/* Called when we see a conditional flag (eg: .eq). */ - -static arc_insn -insert_cond (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - cond_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Used in the "j" instruction to prevent constants from being interpreted as - shimm values (which the jump insn doesn't accept). This can also be used - to force the use of limm values in other situations (eg: ld r0,[foo] uses - this). - ??? The mechanism is sound. Access to it is a bit klunky right now. */ - -static arc_insn -insert_forcelimm (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - cond_p = 1; - return insn; -} - -static arc_insn -insert_addr_wb (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - addrwb_p = 1 << operand->shift; - return insn; -} - -static arc_insn -insert_base (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (reg != NULL) - { - arc_insn myinsn; - myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift; - insn |= B(myinsn); - ls_operand[LS_BASE] = OP_REG; - } - else if (ARC_SHIMM_CONST_P (value) && !cond_p) - { - if (shimm_p && value != shimm) - { - /* convert the previous shimm operand to a limm. */ - limm_p = 1; - limm = shimm; - insn &= ~C(-1); /* we know where the value is in insn. */ - insn |= C(ARC_REG_LIMM); - ls_operand[LS_VALUE] = OP_LIMM; - } - insn |= ARC_REG_SHIMM << operand->shift; - shimm_p = 1; - shimm = value; - ls_operand[LS_BASE] = OP_SHIMM; - } - else - { - if (limm_p && value != limm) - { - *errmsg = "too many long constants"; - return insn; - } - limm_p = 1; - limm = value; - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } - - return insn; -} - -/* Used in ld/st insns to handle the offset field. We don't try to - match operand syntax here. we catch bad combinations later. */ - -static arc_insn -insert_offset (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - long minval, maxval; - - if (reg != NULL) - { - arc_insn myinsn; - myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift; - ls_operand[LS_OFFSET] = OP_REG; - if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later. */ - if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later. */ - insn |= C(myinsn); - } - else - { - /* This is *way* more general than necessary, but maybe some day it'll - be useful. */ - if (operand->flags & ARC_OPERAND_SIGNED) - { - minval = -(1 << (operand->bits - 1)); - maxval = (1 << (operand->bits - 1)) - 1; - } - else - { - minval = 0; - maxval = (1 << operand->bits) - 1; - } - if ((cond_p && !limm_p) || (value < minval || value > maxval)) - { - if (limm_p && value != limm) - { - *errmsg = "too many long constants"; - } - else - { - limm_p = 1; - limm = value; - if (operand->flags & ARC_OPERAND_STORE) - insn |= B(ARC_REG_LIMM); - if (operand->flags & ARC_OPERAND_LOAD) - insn |= C(ARC_REG_LIMM); - ls_operand[LS_OFFSET] = OP_LIMM; - } - } - else - { - if ((value < minval || value > maxval)) - *errmsg = "need too many limms"; - else if (shimm_p && value != shimm) - { - /* check for bad operand combinations before we lose info about them. */ - if ((insn & I(-1)) == I(1)) - { - *errmsg = "to many shimms in load"; - goto out; - } - if (limm_p && operand->flags & ARC_OPERAND_LOAD) - { - *errmsg = "too many long constants"; - goto out; - } - /* convert what we thought was a shimm to a limm. */ - limm_p = 1; - limm = shimm; - if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) - { - insn &= ~C(-1); - insn |= C(ARC_REG_LIMM); - ls_operand[LS_VALUE] = OP_LIMM; - } - if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) - { - insn &= ~B(-1); - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } - } - shimm = value; - shimm_p = 1; - ls_operand[LS_OFFSET] = OP_SHIMM; - } - } - out: - return insn; -} - -/* Used in st insns to do final disasemble syntax check. */ - -static long -extract_st_syntax (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; -{ -#define ST_SYNTAX(V,B,O) \ -((ls_operand[LS_VALUE] == (V) && \ - ls_operand[LS_BASE] == (B) && \ - ls_operand[LS_OFFSET] == (O))) - - if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) - || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) - || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE) - || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) - *invalid = 1; - return 0; -} - -int -arc_limm_fixup_adjust(insn) - arc_insn insn; -{ - int retval = 0; - - /* check for st shimm,[limm]. */ - if ((insn & (I(-1) | C(-1) | B(-1))) == - (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM))) - { - retval = insn & 0x1ff; - if (retval & 0x100) /* sign extend 9 bit offset. */ - retval |= ~0x1ff; - } - return -retval; /* negate offset for return. */ -} - -/* Used in st insns to do final syntax check. */ - -static arc_insn -insert_st_syntax (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg; -{ - if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0) - { - /* change an illegal insn into a legal one, it's easier to - do it here than to try to handle it during operand scan. */ - limm_p = 1; - limm = shimm; - shimm_p = 0; - shimm = 0; - insn = insn & ~(C(-1) | 511); - insn |= ARC_REG_LIMM << ARC_SHIFT_REGC; - ls_operand[LS_VALUE] = OP_LIMM; - } - - if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)) - { - /* try to salvage this syntax. */ - if (shimm & 0x1) /* odd shimms won't work. */ - { - if (limm_p) /* do we have a limm already? */ - { - *errmsg = "impossible store"; - } - limm_p = 1; - limm = shimm; - shimm = 0; - shimm_p = 0; - insn = insn & ~(B(-1) | 511); - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } - else - { - shimm >>= 1; - insn = insn & ~511; - insn |= shimm; - ls_operand[LS_OFFSET] = OP_SHIMM; - } - } - if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)) - { - limm += arc_limm_fixup_adjust(insn); - } - if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE) - || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) - || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) - || ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) - || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) - || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) - *errmsg = "st operand error"; - if (addrwb_p) - { - if (ls_operand[LS_BASE] != OP_REG) - *errmsg = "address writeback not allowed"; - insn |= addrwb_p; - } - if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm) - *errmsg = "store value must be zero"; - return insn; -} - -/* Used in ld insns to do final syntax check. */ - -static arc_insn -insert_ld_syntax (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg; -{ -#define LD_SYNTAX(D,B,O) \ -((ls_operand[LS_DEST] == (D) && \ - ls_operand[LS_BASE] == (B) && \ - ls_operand[LS_OFFSET] == (O))) - - int test = insn & I(-1); - - if (!(test == I(1))) - { - if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM - || ls_operand[LS_OFFSET] == OP_SHIMM)) - *errmsg = "invalid load/shimm insn"; - } - if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE) - || LD_SYNTAX(OP_REG,OP_REG,OP_REG) - || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) - || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) - || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) - *errmsg = "ld operand error"; - if (addrwb_p) - { - if (ls_operand[LS_BASE] != OP_REG) - *errmsg = "address writeback not allowed"; - insn |= addrwb_p; - } - return insn; -} - -/* Used in ld insns to do final syntax check. */ - -static long -extract_ld_syntax (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; -{ - int test = insn[0] & I(-1); - - if (!(test == I(1))) - { - if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM - || ls_operand[LS_OFFSET] == OP_SHIMM)) - *invalid = 1; - } - if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1))) - || LD_SYNTAX(OP_REG,OP_REG,OP_REG) - || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) - || (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0)) - || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) - *invalid = 1; - return 0; -} - -/* Called at the end of processing normal insns (eg: add) to insert a shimm - value (if present) into the insn. */ - -static arc_insn -insert_shimmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - if (shimm_p) - insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Called at the end of processing normal insns (eg: add) to insert a limm - value (if present) into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ - -static arc_insn -insert_limmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ -#if 0 - if (limm_p) - ; /* nothing to do, gas does it. */ -#endif - return insn; -} - -static arc_insn -insert_jumpflags (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value; - const char **errmsg; -{ - if (!flag_p) - { - *errmsg = "jump flags, but no .f seen"; - } - if (!limm_p) - { - *errmsg = "jump flags, but no limm addr"; - } - if (limm & 0xfc000000) - { - *errmsg = "flag bits of jump address limm lost"; - } - if (limm & 0x03000000) - { - *errmsg = "attempt to set HR bits"; - } - if ((value & ((1 << operand->bits) - 1)) != value) - { - *errmsg = "bad jump flags value"; - } - jumpflags_p = 1; - limm = ((limm & ((1 << operand->shift) - 1)) - | ((value & ((1 << operand->bits) - 1)) << operand->shift)); - return insn; -} - -/* Called at the end of unary operand macros to copy the B field to C. */ - -static arc_insn -insert_unopmacro (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; - return insn; -} - -/* Insert a relative address for a branch insn (b, bl, or lp). */ - -static arc_insn -insert_reladdr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value; - const char **errmsg; -{ - if (value & 3) - *errmsg = "branch address not on 4 byte boundary"; - insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Insert a limm value as a 26 bit address right shifted 2 into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's little for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. - - We do check for correct usage of the nullify suffix, or we - set the default correctly, though. */ - -static arc_insn -insert_absaddr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg; -{ - if (limm_p) - { - /* if it is a jump and link, .jd must be specified. */ - if (insn & R(-1,9,1)) - { - if (!nullify_p) - { - insn |= 0x02 << 5; /* default nullify to .jd. */ - } - else - { - if (nullify != 0x02) - { - *errmsg = "must specify .jd or no nullify suffix"; - } - } - } - } - return insn; -} - -/* Extraction functions. - - The suffix extraction functions' return value is redundant since it can be - obtained from (*OPVAL)->value. However, the boolean suffixes don't have - a suffix table entry for the "false" case, so values of zero must be - obtained from the return value (*OPVAL == NULL). */ - -static const struct arc_operand_value *lookup_register (int type, long regno); - -/* Called by the disassembler before printing an instruction. */ - -void -arc_opcode_init_extract () -{ - arc_opcode_init_insert(); -} - -/* As we're extracting registers, keep an eye out for the 'f' indicator - (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, - like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. - - We must also handle auxiliary registers for lr/sr insns. They are just - constants with special names. */ - -static long -extract_reg (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid ATTRIBUTE_UNUSED; -{ - int regno; - long value; - enum operand op_type; - - /* Get the register number. */ - regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - - /* Is it a constant marker? */ - if (regno == ARC_REG_SHIMM) - { - op_type = OP_SHIMM; - /* always return zero if dest is a shimm mlm. */ - - if ('a' != operand->fmt) - { - value = *insn & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - if (!flagshimm_handled_p) - flag_p = 0; - flagshimm_handled_p = 1; - } - else - { - value = 0; - } - } - else if (regno == ARC_REG_SHIMM_UPDATE) - { - op_type = OP_SHIMM; - - /* always return zero if dest is a shimm mlm. */ - - if ('a' != operand->fmt) - { - value = *insn & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - } - else - { - value = 0; - } - flag_p = 1; - flagshimm_handled_p = 1; - } - else if (regno == ARC_REG_LIMM) - { - op_type = OP_LIMM; - value = insn[1]; - limm_p = 1; - /* if this is a jump instruction (j,jl), show new pc correctly. */ - if (0x07 == ((*insn & I(-1)) >> 27)) - { - value = (value & 0xffffff); - } - } - /* It's a register, set OPVAL (that's the only way we distinguish registers - from constants here). */ - else - { - const struct arc_operand_value *reg = lookup_register (REG, regno); - op_type = OP_REG; - - if (reg == NULL) - abort (); - if (opval != NULL) - *opval = reg; - value = regno; - } - - /* If this field takes an auxiliary register, see if it's a known one. */ - if ((mods & ARC_MOD_AUXREG) - && ARC_REG_CONSTANT_P (regno)) - { - const struct arc_operand_value *reg = lookup_register (AUXREG, value); - - /* This is really a constant, but tell the caller it has a special - name. */ - if (reg != NULL && opval != NULL) - *opval = reg; - } - switch(operand->fmt) - { - case 'a': - ls_operand[LS_DEST] = op_type; - break; - case 's': - ls_operand[LS_BASE] = op_type; - break; - case 'c': - if ((insn[0]& I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; - case 'o': case 'O': - ls_operand[LS_OFFSET] = op_type; - break; - } - - return value; -} - -/* Return the value of the "flag update" field for shimm insns. - This value is actually stored in the register field. */ - -static long -extract_flag (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval; - int *invalid ATTRIBUTE_UNUSED; -{ - int f; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - f = flag_p != 0; - else - f = (*insn & (1 << operand->shift)) != 0; - - /* There is no text for zero values. */ - if (f == 0) - return 0; - flag_p = 1; - val = arc_opcode_lookup_suffix (operand, 1); - if (opval != NULL && val != NULL) - *opval = val; - return val->value; -} - -/* Extract the condition code (if it exists). - If we've seen a shimm value in this insn (meaning that the insn can't have - a condition code field), then we don't store anything in OPVAL and return - zero. */ - -static long -extract_cond (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval; - int *invalid ATTRIBUTE_UNUSED; -{ - long cond; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - return 0; - - cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - val = arc_opcode_lookup_suffix (operand, cond); - - /* Ignore NULL values of `val'. Several condition code values are - reserved for extensions. */ - if (opval != NULL && val != NULL) - *opval = val; - return cond; -} - -/* Extract a branch address. - We return the value as a real address (not right shifted by 2). */ - -static long -extract_reladdr (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; -{ - long addr; - - addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (addr & (1 << (operand->bits - 1)))) - addr -= 1 << operand->bits; - return addr << 2; -} - -/* extract the flags bits from a j or jl long immediate. */ -static long -extract_jumpflags(insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; -{ - if (!flag_p || !limm_p) - *invalid = 1; - return ((flag_p && limm_p) - ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); -} - -/* extract st insn's offset. */ - -static long -extract_st_offset (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; -{ - int value = 0; - - if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; - } - else - { - *invalid = 1; - } - return(value); -} - -/* extract ld insn's offset. */ - -static long -extract_ld_offset (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - int test = insn[0] & I(-1); - int value; - - if (test) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; - return(value); - } - /* if it isn't in the insn, it's concealed behind reg 'c'. */ - return extract_reg (insn, &arc_operands[arc_operand_map['c']], - mods, opval, invalid); -} - -/* The only thing this does is set the `invalid' flag if B != C. - This is needed because the "mov" macro appears before it's real insn "and" - and we don't want the disassembler to confuse them. */ - -static long -extract_unopmacro (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; -{ - /* This misses the case where B == ARC_REG_SHIMM_UPDATE && - C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get - printed as "and"s. */ - if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) - != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) - if (invalid != NULL) - *invalid = 1; - return 0; -} - -/* Utility for the extraction functions to return the index into - `arc_suffixes'. */ - -const struct arc_operand_value * -arc_opcode_lookup_suffix (type, value) - const struct arc_operand *type; - int value; -{ - register const struct arc_operand_value *v,*end; - struct arc_ext_operand_value *ext_oper = arc_ext_operands; - - while (ext_oper) - { - if (type == &arc_operands[ext_oper->operand.type] - && value == ext_oper->operand.value) - return (&ext_oper->operand); - ext_oper = ext_oper->next; - } - - /* ??? This is a little slow and can be speeded up. */ - - for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) - if (type == &arc_operands[v->type] - && value == v->value) - return v; - return 0; -} - -static const struct arc_operand_value * -lookup_register (type, regno) - int type; - long regno; -{ - register const struct arc_operand_value *r,*end; - struct arc_ext_operand_value *ext_oper = arc_ext_operands; - - while (ext_oper) - { - if (ext_oper->operand.type == type && ext_oper->operand.value == regno) - return (&ext_oper->operand); - ext_oper = ext_oper->next; - } - - if (type == REG) - return &arc_reg_names[regno]; - - /* ??? This is a little slow and can be speeded up. */ - - for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; - r < end; ++r) - if (type == r->type && regno == r->value) - return r; - return 0; -} - -int -arc_insn_is_j(insn) - arc_insn insn; -{ - return (insn & (I(-1))) == I(0x7); -} - -int -arc_insn_not_jl(insn) - arc_insn insn; -{ - return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) - != (I(0x7) | R(-1,9,1))); -} - -int -arc_operand_type(int opertype) -{ - switch (opertype) - { - case 0: - return(COND); - break; - case 1: - return(REG); - break; - case 2: - return(AUXREG); - break; - } - return -1; -} - -struct arc_operand_value * -get_ext_suffix(s) - char *s; -{ - struct arc_ext_operand_value *suffix = arc_ext_operands; - - while (suffix) - { - if ((COND == suffix->operand.type) - && !strcmp(s,suffix->operand.name)) - return(&suffix->operand); - suffix = suffix->next; - } - return NULL; -} - -int -arc_get_noshortcut_flag() -{ - return ARC_REGISTER_NOSHORT_CUT; -} diff --git a/contrib/binutils/opcodes/arm-dis.c b/contrib/binutils/opcodes/arm-dis.c deleted file mode 100644 index e918daf..0000000 --- a/contrib/binutils/opcodes/arm-dis.c +++ /dev/null @@ -1,1388 +0,0 @@ -/* Instruction printing code for the ARM - Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 - Free Software Foundation, Inc. - Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) - Modification by James G. Smith (jsmith@cygnus.co.uk) - - This file is part of libopcodes. - - This program is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License as published by the Free - Software Foundation; either version 2 of the License, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" -#define DEFINE_TABLE -#include "arm-opc.h" -#include "coff/internal.h" -#include "libcoff.h" -#include "opintl.h" -#include "safe-ctype.h" - -/* FIXME: This shouldn't be done here. */ -#include "elf-bfd.h" -#include "elf/internal.h" -#include "elf/arm.h" - -#ifndef streq -#define streq(a,b) (strcmp ((a), (b)) == 0) -#endif - -#ifndef strneq -#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) -#endif - -#ifndef NUM_ELEM -#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) -#endif - -static char * arm_conditional[] = -{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", "gt", "le", "", "nv"}; - -typedef struct -{ - const char * name; - const char * description; - const char * reg_names[16]; -} -arm_regname; - -static arm_regname regnames[] = -{ - { "raw" , "Select raw register names", - { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, - { "gcc", "Select register names used by GCC", - { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, - { "std", "Select register names used in ARM's ISA documentation", - { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, - { "apcs", "Select register names used in the APCS", - { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, - { "atpcs", "Select register names used in the ATPCS", - { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, - { "special-atpcs", "Select special register names used in the ATPCS", - { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, - { "iwmmxt_regnames", "Select register names used on the Intel Wireless MMX technology coprocessor", - { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"}}, - { "iwmmxt_Cregnames", "Select control register names used on the Intel Wireless MMX technology coprocessor", - {"wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"}} -}; - -static char * iwmmxt_wwnames[] = -{"b", "h", "w", "d"}; - -static char * iwmmxt_wwssnames[] = -{"b", "bus", "b", "bss", - "h", "hus", "h", "hss", - "w", "wus", "w", "wss", - "d", "dus", "d", "dss" -}; - -/* Default to GCC register name set. */ -static unsigned int regname_selected = 1; - -#define NUM_ARM_REGNAMES NUM_ELEM (regnames) -#define arm_regnames regnames[regname_selected].reg_names - -static bfd_boolean force_thumb = FALSE; - -static char * arm_fp_const[] = -{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; - -static char * arm_shift[] = -{"lsl", "lsr", "asr", "ror"}; - -/* Forward declarations. */ -static void arm_decode_shift - PARAMS ((long, fprintf_ftype, void *)); -static int print_insn_arm - PARAMS ((bfd_vma, struct disassemble_info *, long)); -static int print_insn_thumb - PARAMS ((bfd_vma, struct disassemble_info *, long)); -static void parse_disassembler_options - PARAMS ((char *)); -static int print_insn - PARAMS ((bfd_vma, struct disassemble_info *, bfd_boolean)); -static int set_iwmmxt_regnames - PARAMS ((void)); - -int get_arm_regname_num_options - PARAMS ((void)); -int set_arm_regname_option - PARAMS ((int)); -int get_arm_regnames - PARAMS ((int, const char **, const char **, const char ***)); - -/* Functions. */ -int -get_arm_regname_num_options () -{ - return NUM_ARM_REGNAMES; -} - -int -set_arm_regname_option (option) - int option; -{ - int old = regname_selected; - regname_selected = option; - return old; -} - -int -get_arm_regnames (option, setname, setdescription, register_names) - int option; - const char **setname; - const char **setdescription; - const char ***register_names; -{ - *setname = regnames[option].name; - *setdescription = regnames[option].description; - *register_names = regnames[option].reg_names; - return 16; -} - -static void -arm_decode_shift (given, func, stream) - long given; - fprintf_ftype func; - void * stream; -{ - func (stream, "%s", arm_regnames[given & 0xf]); - - if ((given & 0xff0) != 0) - { - if ((given & 0x10) == 0) - { - int amount = (given & 0xf80) >> 7; - int shift = (given & 0x60) >> 5; - - if (amount == 0) - { - if (shift == 3) - { - func (stream, ", rrx"); - return; - } - - amount = 32; - } - - func (stream, ", %s #%d", arm_shift[shift], amount); - } - else - func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], - arm_regnames[(given & 0xf00) >> 8]); - } -} - -static int -set_iwmmxt_regnames () -{ - const char * setname; - const char * setdesc; - const char ** regnames; - int iwmmxt_regnames = 0; - int num_regnames = get_arm_regname_num_options (); - - get_arm_regnames (iwmmxt_regnames, &setname, - &setdesc, ®names); - while ((strcmp ("iwmmxt_regnames", setname)) - && (iwmmxt_regnames < num_regnames)) - get_arm_regnames (++iwmmxt_regnames, &setname, &setdesc, ®names); - - return iwmmxt_regnames; -} - -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (always 4 on ARM). */ - -static int -print_insn_arm (pc, info, given) - bfd_vma pc; - struct disassemble_info *info; - long given; -{ - const struct arm_opcode *insn; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - static int iwmmxt_regnames = 0; - - for (insn = arm_opcodes; insn->assembler; insn++) - { - if (insn->value == FIRST_IWMMXT_INSN - && info->mach != bfd_mach_arm_XScale - && info->mach != bfd_mach_arm_iWMMXt) - insn = insn + IWMMXT_INSN_COUNT; - - if ((given & insn->mask) == insn->value) - { - char * c; - - for (c = insn->assembler; *c; c++) - { - if (*c == '%') - { - switch (*++c) - { - case '%': - func (stream, "%%"); - break; - - case 'a': - if (((given & 0x000f0000) == 0x000f0000) - && ((given & 0x02000000) == 0)) - { - int offset = given & 0xfff; - - func (stream, "[pc"); - - if (given & 0x01000000) - { - if ((given & 0x00800000) == 0) - offset = - offset; - - /* Pre-indexed. */ - func (stream, ", #%d]", offset); - - offset += pc + 8; - - /* Cope with the possibility of write-back - being used. Probably a very dangerous thing - for the programmer to do, but who are we to - argue ? */ - if (given & 0x00200000) - func (stream, "!"); - } - else - { - /* Post indexed. */ - func (stream, "], #%d", offset); - - /* ie ignore the offset. */ - offset = pc + 8; - } - - func (stream, "\t; "); - info->print_address_func (offset, info); - } - else - { - func (stream, "[%s", - arm_regnames[(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) - { - if ((given & 0x02000000) == 0) - { - int offset = given & 0xfff; - if (offset) - func (stream, ", #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - } - else - { - func (stream, ", %s", - (((given & 0x00800000) == 0) - ? "-" : "")); - arm_decode_shift (given, func, stream); - } - - func (stream, "]%s", - ((given & 0x00200000) != 0) ? "!" : ""); - } - else - { - if ((given & 0x02000000) == 0) - { - int offset = given & 0xfff; - if (offset) - func (stream, "], #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - else - func (stream, "]"); - } - else - { - func (stream, "], %s", - (((given & 0x00800000) == 0) - ? "-" : "")); - arm_decode_shift (given, func, stream); - } - } - } - break; - - case 's': - if ((given & 0x004f0000) == 0x004f0000) - { - /* PC relative with immediate offset. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - - if ((given & 0x00800000) == 0) - offset = -offset; - - func (stream, "[pc, #%d]\t; ", offset); - - (*info->print_address_func) - (offset + pc + 8, info); - } - else - { - func (stream, "[%s", - arm_regnames[(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) - { - /* Pre-indexed. */ - if ((given & 0x00400000) == 0x00400000) - { - /* Immediate. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) - func (stream, ", #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - } - else - { - /* Register. */ - func (stream, ", %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), - arm_regnames[given & 0xf]); - } - - func (stream, "]%s", - ((given & 0x00200000) != 0) ? "!" : ""); - } - else - { - /* Post-indexed. */ - if ((given & 0x00400000) == 0x00400000) - { - /* Immediate. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (offset) - func (stream, "], #%s%d", - (((given & 0x00800000) == 0) - ? "-" : ""), offset); - else - func (stream, "]"); - } - else - { - /* Register. */ - func (stream, "], %s%s", - (((given & 0x00800000) == 0) - ? "-" : ""), - arm_regnames[given & 0xf]); - } - } - } - break; - - case 'b': - (*info->print_address_func) - (BDISP (given) * 4 + pc + 8, info); - break; - - case 'c': - func (stream, "%s", - arm_conditional [(given >> 28) & 0xf]); - break; - - case 'm': - { - int started = 0; - int reg; - - func (stream, "{"); - for (reg = 0; reg < 16; reg++) - if ((given & (1 << reg)) != 0) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, "%s", arm_regnames[reg]); - } - func (stream, "}"); - } - break; - - case 'o': - if ((given & 0x02000000) != 0) - { - int rotate = (given & 0xf00) >> 7; - int immed = (given & 0xff); - immed = (((immed << (32 - rotate)) - | (immed >> rotate)) & 0xffffffff); - func (stream, "#%d\t; 0x%x", immed, immed); - } - else - arm_decode_shift (given, func, stream); - break; - - case 'p': - if ((given & 0x0000f000) == 0x0000f000) - func (stream, "p"); - break; - - case 't': - if ((given & 0x01200000) == 0x00200000) - func (stream, "t"); - break; - - case 'A': - func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - - if ((given & (1 << 24)) != 0) - { - int offset = given & 0xff; - - if (offset) - func (stream, ", #%s%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4, - ((given & 0x00200000) != 0 ? "!" : "")); - else - func (stream, "]"); - } - else - { - int offset = given & 0xff; - - func (stream, "]"); - - if (given & (1 << 21)) - { - if (offset) - func (stream, ", #%s%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); - } - else - func (stream, ", {%d}", offset); - } - break; - - case 'B': - /* Print ARM V5 BLX(1) address: pc+25 bits. */ - { - bfd_vma address; - bfd_vma offset = 0; - - if (given & 0x00800000) - /* Is signed, hi bits should be ones. */ - offset = (-1) ^ 0x00ffffff; - - /* Offset is (SignExtend(offset field)<<2). */ - offset += given & 0x00ffffff; - offset <<= 2; - address = offset + pc + 8; - - if (given & 0x01000000) - /* H bit allows addressing to 2-byte boundaries. */ - address += 2; - - info->print_address_func (address, info); - } - break; - - case 'I': - /* Print a Cirrus/DSP shift immediate. */ - /* Immediates are 7bit signed ints with bits 0..3 in - bits 0..3 of opcode and bits 4..6 in bits 5..7 - of opcode. */ - { - int imm; - - imm = (given & 0xf) | ((given & 0xe0) >> 1); - - /* Is ``imm'' a negative number? */ - if (imm & 0x40) - imm |= (-1 << 7); - - func (stream, "%d", imm); - } - - break; - - case 'C': - func (stream, "_"); - if (given & 0x80000) - func (stream, "f"); - if (given & 0x40000) - func (stream, "s"); - if (given & 0x20000) - func (stream, "x"); - if (given & 0x10000) - func (stream, "c"); - break; - - case 'F': - switch (given & 0x00408000) - { - case 0: - func (stream, "4"); - break; - case 0x8000: - func (stream, "1"); - break; - case 0x00400000: - func (stream, "2"); - break; - default: - func (stream, "3"); - } - break; - - case 'P': - switch (given & 0x00080080) - { - case 0: - func (stream, "s"); - break; - case 0x80: - func (stream, "d"); - break; - case 0x00080000: - func (stream, "e"); - break; - default: - func (stream, _("<illegal precision>")); - break; - } - break; - case 'Q': - switch (given & 0x00408000) - { - case 0: - func (stream, "s"); - break; - case 0x8000: - func (stream, "d"); - break; - case 0x00400000: - func (stream, "e"); - break; - default: - func (stream, "p"); - break; - } - break; - case 'R': - switch (given & 0x60) - { - case 0: - break; - case 0x20: - func (stream, "p"); - break; - case 0x40: - func (stream, "m"); - break; - default: - func (stream, "z"); - break; - } - break; - - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': - { - int bitstart = *c++ - '0'; - int bitend = 0; - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - switch (*c) - { - case '-': - c++; - - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - - if (!bitend) - abort (); - - switch (*c) - { - case 'r': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%s", arm_regnames[reg]); - } - break; - case 'd': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%d", reg); - } - break; - case 'W': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%d", reg + 1); - } - break; - case 'x': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "0x%08x", reg); - - /* Some SWI instructions have special - meanings. */ - if ((given & 0x0fffffff) == 0x0FF00000) - func (stream, "\t; IMB"); - else if ((given & 0x0fffffff) == 0x0FF00001) - func (stream, "\t; IMBRange"); - } - break; - case 'X': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%01x", reg & 0xf); - } - break; - case 'f': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - if (reg > 7) - func (stream, "#%s", - arm_fp_const[reg & 7]); - else - func (stream, "f%d", reg); - } - break; - - case 'w': - { - long reg; - - if (bitstart != bitend) - { - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - if (bitend - bitstart == 1) - func (stream, "%s", iwmmxt_wwnames[reg]); - else - func (stream, "%s", iwmmxt_wwssnames[reg]); - } - else - { - reg = (((given >> 8) & 0x1) | - ((given >> 22) & 0x1)); - func (stream, "%s", iwmmxt_wwnames[reg]); - } - } - break; - - case 'g': - { - long reg; - int current_regnames; - - if (! iwmmxt_regnames) - iwmmxt_regnames = set_iwmmxt_regnames (); - current_regnames = set_arm_regname_option - (iwmmxt_regnames); - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%s", arm_regnames[reg]); - set_arm_regname_option (current_regnames); - } - break; - - case 'G': - { - long reg; - int current_regnames; - - if (! iwmmxt_regnames) - iwmmxt_regnames = set_iwmmxt_regnames (); - current_regnames = set_arm_regname_option - (iwmmxt_regnames + 1); - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%s", arm_regnames[reg]); - set_arm_regname_option (current_regnames); - } - break; - - default: - abort (); - } - break; - - case 'y': - case 'z': - { - int single = *c == 'y'; - int regno; - - switch (bitstart) - { - case 4: /* Sm pair */ - func (stream, "{"); - /* Fall through. */ - case 0: /* Sm, Dm */ - regno = given & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 5) & 1; - } - break; - - case 1: /* Sd, Dd */ - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - break; - - case 2: /* Sn, Dn */ - regno = (given >> 16) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 7) & 1; - } - break; - - case 3: /* List */ - func (stream, "{"); - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - break; - - - default: - abort (); - } - - func (stream, "%c%d", single ? 's' : 'd', regno); - - if (bitstart == 3) - { - int count = given & 0xff; - - if (single == 0) - count >>= 1; - - if (--count) - { - func (stream, "-%c%d", - single ? 's' : 'd', - regno + count); - } - - func (stream, "}"); - } - else if (bitstart == 4) - func (stream, ", %c%d}", single ? 's' : 'd', - regno + 1); - - break; - } - - case '`': - c++; - if ((given & (1 << bitstart)) == 0) - func (stream, "%c", *c); - break; - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - case '?': - ++c; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c++); - else - func (stream, "%c", *++c); - break; - default: - abort (); - } - break; - - case 'L': - switch (given & 0x00400100) - { - case 0x00000000: func (stream, "b"); break; - case 0x00400000: func (stream, "h"); break; - case 0x00000100: func (stream, "w"); break; - case 0x00400100: func (stream, "d"); break; - default: - break; - } - break; - - case 'Z': - { - int value; - /* given (20, 23) | given (0, 3) */ - value = ((given >> 16) & 0xf0) | (given & 0xf); - func (stream, "%d", value); - } - break; - - case 'l': - /* This is like the 'A' operator, except that if - the width field "M" is zero, then the offset is - *not* multiplied by four. */ - { - int offset = given & 0xff; - int multiplier = (given & 0x00000100) ? 4 : 1; - - func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - - if (offset) - { - if ((given & 0x01000000) != 0) - func (stream, ", #%s%d]%s", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * multiplier, - ((given & 0x00200000) != 0 ? "!" : "")); - else - func (stream, "], #%s%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * multiplier); - } - else - func (stream, "]"); - } - break; - - default: - abort (); - } - } - } - else - func (stream, "%c", *c); - } - return 4; - } - } - abort (); -} - -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction. */ - -static int -print_insn_thumb (pc, info, given) - bfd_vma pc; - struct disassemble_info *info; - long given; -{ - const struct thumb_opcode *insn; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - - for (insn = thumb_opcodes; insn->assembler; insn++) - { - if ((given & insn->mask) == insn->value) - { - char * c = insn->assembler; - - /* Special processing for Thumb 2 instruction BL sequence: */ - if (!*c) /* Check for empty (not NULL) assembler string. */ - { - long offset; - - info->bytes_per_chunk = 4; - info->bytes_per_line = 4; - - offset = BDISP23 (given); - offset = offset * 2 + pc + 4; - - if ((given & 0x10000000) == 0) - { - func (stream, "blx\t"); - offset &= 0xfffffffc; - } - else - func (stream, "bl\t"); - - info->print_address_func (offset, info); - return 4; - } - else - { - info->bytes_per_chunk = 2; - info->bytes_per_line = 4; - - given &= 0xffff; - - for (; *c; c++) - { - if (*c == '%') - { - int domaskpc = 0; - int domasklr = 0; - - switch (*++c) - { - case '%': - func (stream, "%%"); - break; - - case 'S': - { - long reg; - - reg = (given >> 3) & 0x7; - if (given & (1 << 6)) - reg += 8; - - func (stream, "%s", arm_regnames[reg]); - } - break; - - case 'D': - { - long reg; - - reg = given & 0x7; - if (given & (1 << 7)) - reg += 8; - - func (stream, "%s", arm_regnames[reg]); - } - break; - - case 'T': - func (stream, "%s", - arm_conditional [(given >> 8) & 0xf]); - break; - - case 'N': - if (given & (1 << 8)) - domasklr = 1; - /* Fall through. */ - case 'O': - if (*c == 'O' && (given & (1 << 8))) - domaskpc = 1; - /* Fall through. */ - case 'M': - { - int started = 0; - int reg; - - func (stream, "{"); - - /* It would be nice if we could spot - ranges, and generate the rS-rE format: */ - for (reg = 0; (reg < 8); reg++) - if ((given & (1 << reg)) != 0) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, "%s", arm_regnames[reg]); - } - - if (domasklr) - { - if (started) - func (stream, ", "); - started = 1; - func (stream, arm_regnames[14] /* "lr" */); - } - - if (domaskpc) - { - if (started) - func (stream, ", "); - func (stream, arm_regnames[15] /* "pc" */); - } - - func (stream, "}"); - } - break; - - - case '0': case '1': case '2': case '3': case '4': - case '5': case '6': case '7': case '8': case '9': - { - int bitstart = *c++ - '0'; - int bitend = 0; - - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - switch (*c) - { - case '-': - { - long reg; - - c++; - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - if (!bitend) - abort (); - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - switch (*c) - { - case 'r': - func (stream, "%s", arm_regnames[reg]); - break; - - case 'd': - func (stream, "%d", reg); - break; - - case 'H': - func (stream, "%d", reg << 1); - break; - - case 'W': - func (stream, "%d", reg << 2); - break; - - case 'a': - /* PC-relative address -- the bottom two - bits of the address are dropped - before the calculation. */ - info->print_address_func - (((pc + 4) & ~3) + (reg << 2), info); - break; - - case 'x': - func (stream, "0x%04x", reg); - break; - - case 'I': - reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - func (stream, "%d", reg); - break; - - case 'B': - reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - (*info->print_address_func) - (reg * 2 + pc + 4, info); - break; - - default: - abort (); - } - } - break; - - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - - case '?': - ++c; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c++); - else - func (stream, "%c", *++c); - break; - - default: - abort (); - } - } - break; - - default: - abort (); - } - } - else - func (stream, "%c", *c); - } - } - return 2; - } - } - - /* No match. */ - abort (); -} - -/* Disallow mapping symbols ($a, $b, $d, $t etc) from - being displayed in symbol relative addresses. */ - -bfd_boolean -arm_symbol_is_valid (asymbol * sym, - struct disassemble_info * info ATTRIBUTE_UNUSED) -{ - const char * name; - - if (sym == NULL) - return FALSE; - - name = bfd_asymbol_name (sym); - - return (name && *name != '$'); -} - -/* Parse an individual disassembler option. */ - -void -parse_arm_disassembler_option (option) - char * option; -{ - if (option == NULL) - return; - - if (strneq (option, "reg-names-", 10)) - { - int i; - - option += 10; - - for (i = NUM_ARM_REGNAMES; i--;) - if (strneq (option, regnames[i].name, strlen (regnames[i].name))) - { - regname_selected = i; - break; - } - - if (i < 0) - /* XXX - should break 'option' at following delimiter. */ - fprintf (stderr, _("Unrecognised register name set: %s\n"), option); - } - else if (strneq (option, "force-thumb", 11)) - force_thumb = 1; - else if (strneq (option, "no-force-thumb", 14)) - force_thumb = 0; - else - /* XXX - should break 'option' at following delimiter. */ - fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); - - return; -} - -/* Parse the string of disassembler options, spliting it at whitespaces - or commas. (Whitespace separators supported for backwards compatibility). */ - -static void -parse_disassembler_options (options) - char * options; -{ - if (options == NULL) - return; - - while (*options) - { - parse_arm_disassembler_option (options); - - /* Skip forward to next seperator. */ - while ((*options) && (! ISSPACE (*options)) && (*options != ',')) - ++ options; - /* Skip forward past seperators. */ - while (ISSPACE (*options) || (*options == ',')) - ++ options; - } -} - -/* NOTE: There are no checks in these routines that - the relevant number of data bytes exist. */ - -static int -print_insn (pc, info, little) - bfd_vma pc; - struct disassemble_info * info; - bfd_boolean little; -{ - unsigned char b[4]; - long given; - int status; - int is_thumb; - - if (info->disassembler_options) - { - parse_disassembler_options (info->disassembler_options); - - /* To avoid repeated parsing of these options, we remove them here. */ - info->disassembler_options = NULL; - } - - is_thumb = force_thumb; - - if (!is_thumb && info->symbols != NULL) - { - if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) - { - coff_symbol_type * cs; - - cs = coffsymbol (*info->symbols); - is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT - || cs->native->u.syment.n_sclass == C_THUMBSTAT - || cs->native->u.syment.n_sclass == C_THUMBLABEL - || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC - || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); - } - else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour) - { - elf_symbol_type * es; - unsigned int type; - - es = *(elf_symbol_type **)(info->symbols); - type = ELF_ST_TYPE (es->internal_elf_sym.st_info); - - is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); - } - } - - info->bytes_per_chunk = 4; - info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; - - if (little) - { - status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info); - if (status != 0 && is_thumb) - { - info->bytes_per_chunk = 2; - - status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); - b[3] = b[2] = 0; - } - - if (status != 0) - { - info->memory_error_func (status, pc, info); - return -1; - } - - given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); - } - else - { - status = info->read_memory_func - (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info); - if (status != 0) - { - info->memory_error_func (status, pc, info); - return -1; - } - - if (is_thumb) - { - if (pc & 0x2) - { - given = (b[2] << 8) | b[3]; - - status = info->read_memory_func - ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); - if (status != 0) - { - info->memory_error_func (status, pc + 4, info); - return -1; - } - - given |= (b[0] << 24) | (b[1] << 16); - } - else - given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16); - } - else - given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); - } - - if (info->flags & INSN_HAS_RELOC) - /* If the instruction has a reloc associated with it, then - the offset field in the instruction will actually be the - addend for the reloc. (We are using REL type relocs). - In such cases, we can ignore the pc when computing - addresses, since the addend is not currently pc-relative. */ - pc = 0; - - if (is_thumb) - status = print_insn_thumb (pc, info, given); - else - status = print_insn_arm (pc, info, given); - - return status; -} - -int -print_insn_big_arm (pc, info) - bfd_vma pc; - struct disassemble_info * info; -{ - return print_insn (pc, info, FALSE); -} - -int -print_insn_little_arm (pc, info) - bfd_vma pc; - struct disassemble_info * info; -{ - return print_insn (pc, info, TRUE); -} - -void -print_arm_disassembler_options (FILE * stream) -{ - int i; - - fprintf (stream, _("\n\ -The following ARM specific disassembler options are supported for use with\n\ -the -M switch:\n")); - - for (i = NUM_ARM_REGNAMES; i--;) - fprintf (stream, " reg-names-%s %*c%s\n", - regnames[i].name, - (int)(14 - strlen (regnames[i].name)), ' ', - regnames[i].description); - - fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); - fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); -} diff --git a/contrib/binutils/opcodes/arm-opc.h b/contrib/binutils/opcodes/arm-opc.h deleted file mode 100644 index 574bc1f..0000000 --- a/contrib/binutils/opcodes/arm-opc.h +++ /dev/null @@ -1,717 +0,0 @@ -/* Opcode table for the ARM. - - Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003 - Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -struct arm_opcode { - unsigned long value, mask; /* recognise instruction if (op&mask)==value */ - char *assembler; /* how to disassemble this instruction */ -}; - -struct thumb_opcode -{ - unsigned short value, mask; /* recognise instruction if (op&mask)==value */ - char * assembler; /* how to disassemble this instruction */ -}; - -/* format of the assembler string : - - %% % - %<bitfield>d print the bitfield in decimal - %<bitfield>x print the bitfield in hex - %<bitfield>X print the bitfield as 1 hex digit without leading "0x" - %<bitfield>w print the bitfield plus one in decimal - %<bitfield>r print as an ARM register - %<bitfield>f print a floating point constant if >7 else a - floating point register - %<code>y print a single precision VFP reg. - Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair - %<code>z print a double precision VFP reg - Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list - %c print condition code (always bits 28-31) - %P print floating point precision in arithmetic insn - %Q print floating point precision in ldf/stf insn - %R print floating point rounding mode - %<bitnum>'c print specified char iff bit is one - %<bitnum>`c print specified char iff bit is zero - %<bitnum>?ab print a if bit is one else print b - %p print 'p' iff bits 12-15 are 15 - %t print 't' iff bit 21 set and bit 24 clear - %o print operand2 (immediate or register + shift) - %a print address for ldr/str instruction - %s print address for ldr/str halfword/signextend instruction - %b print branch destination - %B print arm BLX(1) destination - %A print address for ldc/stc/ldf/stf instruction - %m print register mask for ldm/stm instruction - %C print the PSR sub type. - %F print the COUNT field of a LFM/SFM instruction. -IWMMXT specific format options: - %<bitfield>g print as an iWMMXt 64-bit register - %<bitfield>G print as an iWMMXt general purpose or control register - %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us - %Z print the Immediate of a WSHUFH instruction. - %L print as an iWMMXt N/M width field. - %l like 'A' except use byte offsets for 'B' & 'H' versions -Thumb specific format options: - %D print Thumb register (bits 0..2 as high number if bit 7 set) - %S print Thumb register (bits 3..5 as high number if bit 6 set) - %<bitfield>I print bitfield as a signed decimal - (top bit of range being the sign bit) - %M print Thumb register mask - %N print Thumb register mask (with LR) - %O print Thumb register mask (with PC) - %T print Thumb condition code (always bits 8-11) - %I print cirrus signed shift immediate: bits 0..3|4..6 - %<bitfield>B print Thumb branch destination (signed displacement) - %<bitfield>W print (bitfield * 4) as a decimal - %<bitfield>H print (bitfield * 2) as a decimal - %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol -*/ - -/* Note: There is a partial ordering in this table - it must be searched from - the top to obtain a correct match. */ - -static const struct arm_opcode arm_opcodes[] = -{ - /* ARM instructions. */ - {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, - {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, - {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, - {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, - {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, - - /* ARM V6 instructions. */ - {0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"}, - {0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, - {0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"}, - {0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, - {0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, - {0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, - {0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"}, - {0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"}, - {0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"}, - {0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, - {0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"}, - {0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"}, - {0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"}, - {0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"}, - {0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"}, - {0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"}, - {0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"}, - {0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"}, - {0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"}, - {0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"}, - {0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"}, - {0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"}, - {0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"}, - {0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"}, - {0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"}, - {0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"}, - {0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"}, - {0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"}, - {0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"}, - {0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"}, - {0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"}, - {0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"}, - {0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"}, - {0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"}, - {0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"}, - {0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"}, - {0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"}, - {0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"}, - {0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"}, - {0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"}, - {0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, - {0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, - {0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, - {0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, - {0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, - {0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, - {0xf1010000, 0xfffffc00, "setend\t%9?ble"}, - {0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, - {0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, - {0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, - {0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"}, - {0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, - {0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"}, - {0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"}, - {0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, - {0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, - {0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, - {0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, - {0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"}, - {0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"}, - {0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, - - /* V5J instruction. */ - {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, - - /* XScale instructions. */ - {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, - {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, - {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, - {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, - {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, - {0xf450f000, 0xfc70f000, "pld\t%a"}, - - /* Intel Wireless MMX technology instructions. */ -#define FIRST_IWMMXT_INSN 0x0e130130 -#define IWMMXT_INSN_COUNT 47 - {0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, - {0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, - {0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, - {0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, - {0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, - {0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, - {0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, - {0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, - {0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, - {0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, - {0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, - {0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, - {0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, - {0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, - {0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, - {0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, - {0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, - {0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, - {0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, - {0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, - {0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, - {0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"}, - {0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, - {0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, - - /* V5 Instructions. */ - {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, - {0xfa000000, 0xfe000000, "blx\t%B"}, - {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, - {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, - {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"}, - {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"}, - {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - - /* V5E "El Segundo" Instructions. */ - {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"}, - {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"}, - {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - - {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - - {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - - {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, - {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, - {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, - {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, - - {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, - {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, - - {0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, - {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, - {0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, - {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, - - /* ARM Instructions. */ - {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, - {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, - {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, - {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, - {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, - {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, - {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, - {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, - {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, - {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, - {0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, - {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, - {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, - {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, - {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, - {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, - {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, - {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, - {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, - {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, - {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"}, - {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"}, - {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"}, - {0x06000010, 0x0e000010, "undefined"}, - {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, - {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, - {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, - {0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, - {0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, - - /* Floating point coprocessor (FPA) instructions */ - {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, - {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, - {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, - {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, - {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, - {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, - {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, - {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, - {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, - {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, - {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, - {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, - {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, - {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, - {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, - {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, - {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, - {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, - {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, - {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, - {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, - {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, - {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, - {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, - {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, - {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, - {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, - {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, - {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, - {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, - - /* Floating point coprocessor (VFP) instructions */ - {0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"}, - {0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"}, - {0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"}, - {0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %1y"}, - {0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"}, - {0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"}, - {0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"}, - {0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%1y"}, - {0x0eb00b40, 0x0fff0ff0, "fcpyd%c\t%1z, %0z"}, - {0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%1y, %0y"}, - {0x0eb70ac0, 0x0fff0fd0, "fcvtds%c\t%1z, %0y"}, - {0x0eb70bc0, 0x0fbf0ff0, "fcvtsd%c\t%1y, %0z"}, - {0x0e800b00, 0x0ff00ff0, "fdivd%c\t%1z, %2z, %0z"}, - {0x0e800a00, 0x0fb00f50, "fdivs%c\t%1y, %2y, %0y"}, - {0x0d100b00, 0x0f700f00, "fldd%c\t%1z, %A"}, - {0x0c900b00, 0x0fd00f00, "fldmia%0?xd%c\t%16-19r%21'!, %3z"}, - {0x0d300b00, 0x0ff00f00, "fldmdb%0?xd%c\t%16-19r!, %3z"}, - {0x0d100a00, 0x0f300f00, "flds%c\t%1y, %A"}, - {0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %3y"}, - {0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %3y"}, - {0x0e000b00, 0x0ff00ff0, "fmacd%c\t%1z, %2z, %0z"}, - {0x0e000a00, 0x0fb00f50, "fmacs%c\t%1y, %2y, %0y"}, - {0x0e200b10, 0x0ff00fff, "fmdhr%c\t%2z, %12-15r"}, - {0x0e000b10, 0x0ff00fff, "fmdlr%c\t%2z, %12-15r"}, - {0x0c400b10, 0x0ff00ff0, "fmdrr%c\t%0z, %12-15r, %16-19r"}, - {0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %2z"}, - {0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %2z"}, - {0x0c500b10, 0x0ff00ff0, "fmrrd%c\t%12-15r, %16-19r, %0z"}, - {0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %4y"}, - {0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %2y"}, - {0x0ef1fa10, 0x0fffffff, "fmstat%c"}, - {0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, - {0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, - {0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, - {0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, - {0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, - {0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"}, - {0x0e100b00, 0x0ff00ff0, "fmscd%c\t%1z, %2z, %0z"}, - {0x0e100a00, 0x0fb00f50, "fmscs%c\t%1y, %2y, %0y"}, - {0x0e000a10, 0x0ff00f7f, "fmsr%c\t%2y, %12-15r"}, - {0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %4y"}, - {0x0e200b00, 0x0ff00ff0, "fmuld%c\t%1z, %2z, %0z"}, - {0x0e200a00, 0x0fb00f50, "fmuls%c\t%1y, %2y, %0y"}, - {0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"}, - {0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"}, - {0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"}, - {0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"}, - {0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"}, - {0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"}, - {0x0eb10b40, 0x0fff0ff0, "fnegd%c\t%1z, %0z"}, - {0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%1y, %0y"}, - {0x0e000b40, 0x0ff00ff0, "fnmacd%c\t%1z, %2z, %0z"}, - {0x0e000a40, 0x0fb00f50, "fnmacs%c\t%1y, %2y, %0y"}, - {0x0e100b40, 0x0ff00ff0, "fnmscd%c\t%1z, %2z, %0z"}, - {0x0e100a40, 0x0fb00f50, "fnmscs%c\t%1y, %2y, %0y"}, - {0x0e200b40, 0x0ff00ff0, "fnmuld%c\t%1z, %2z, %0z"}, - {0x0e200a40, 0x0fb00f50, "fnmuls%c\t%1y, %2y, %0y"}, - {0x0eb80bc0, 0x0fff0fd0, "fsitod%c\t%1z, %0y"}, - {0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%1y, %0y"}, - {0x0eb10bc0, 0x0fff0ff0, "fsqrtd%c\t%1z, %0z"}, - {0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%1y, %0y"}, - {0x0d000b00, 0x0f700f00, "fstd%c\t%1z, %A"}, - {0x0c800b00, 0x0fd00f00, "fstmia%0?xd%c\t%16-19r%21'!, %3z"}, - {0x0d200b00, 0x0ff00f00, "fstmdb%0?xd%c\t%16-19r!, %3z"}, - {0x0d000a00, 0x0f300f00, "fsts%c\t%1y, %A"}, - {0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %3y"}, - {0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %3y"}, - {0x0e300b40, 0x0ff00ff0, "fsubd%c\t%1z, %2z, %0z"}, - {0x0e300a40, 0x0fb00f50, "fsubs%c\t%1y, %2y, %0y"}, - {0x0ebc0b40, 0x0fbe0f70, "fto%16?sui%7'zd%c\t%1y, %0z"}, - {0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%1y, %0y"}, - {0x0eb80b40, 0x0fff0fd0, "fuitod%c\t%1z, %0y"}, - {0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%1y, %0y"}, - - /* Cirrus coprocessor instructions. */ - {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, - {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, - {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, - {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, - {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, - {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, - {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, - {0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, - {0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, - {0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, - {0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, - {0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, - {0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, - {0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, - {0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, - {0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, - {0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, - {0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, - {0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, - {0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, - {0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, - {0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, - {0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, - {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, - {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, - {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, - {0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, - {0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, - {0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, - {0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, - {0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, - {0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, - {0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, - {0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, - {0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, - {0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, - {0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, - {0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, - {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, - {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, - {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, - {0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, - {0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, - {0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, - {0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, - {0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, - {0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, - {0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, - {0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, - {0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, - {0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, - {0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, - {0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, - {0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, - {0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, - {0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, - {0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, - {0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, - {0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, - {0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, - {0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, - {0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, - {0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, - {0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, - {0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, - {0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, - {0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, - {0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, - {0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, - {0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, - {0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, - {0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, - {0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, - {0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, - {0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, - {0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, - - /* Generic coprocessor instructions */ - {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"}, - {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"}, - - /* The rest. */ - {0x00000000, 0x00000000, "undefined instruction %0-31x"}, - {0x00000000, 0x00000000, 0} -}; - -#define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */ - -static const struct thumb_opcode thumb_opcodes[] = -{ - /* Thumb instructions. */ - - /* ARM V6. */ - {0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"}, - {0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"}, - {0x4600, 0xffc0, "cpy\t%0-2r, %3-5r"}, - {0xba00, 0xffc0, "rev\t%0-2r, %3-5r"}, - {0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"}, - {0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"}, - {0xb650, 0xfff7, "setend\t%3?ble\t"}, - {0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"}, - {0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"}, - {0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"}, - {0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"}, - - /* ARM V5 ISA extends Thumb. */ - {0xbe00, 0xff00, "bkpt\t%0-7x"}, - {0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */ - /* Note: this is BLX(2). BLX(1) is done in arm-dis.c/print_insn_thumb() - as an extension of the special processing there for Thumb BL. - BL and BLX(1) involve 2 successive 16-bit instructions, which must - always appear together in the correct order. So, the empty - string is put in this table, and the string interpreter takes <empty> - to mean it has a pair of BL-ish instructions. */ - {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"}, - /* Format 5 instructions do not update the PSR. */ - {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"}, - /* Format 4. */ - {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"}, - {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"}, - {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"}, - {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"}, - {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"}, - {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"}, - {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"}, - {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"}, - {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"}, - {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"}, - {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"}, - {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"}, - {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"}, - {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"}, - {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"}, - {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"}, - /* format 13 */ - {0xB000, 0xFF80, "add\tsp, #%0-6W"}, - {0xB080, 0xFF80, "sub\tsp, #%0-6W"}, - /* format 5 */ - {0x4700, 0xFF80, "bx\t%S"}, - {0x4400, 0xFF00, "add\t%D, %S"}, - {0x4500, 0xFF00, "cmp\t%D, %S"}, - {0x4600, 0xFF00, "mov\t%D, %S"}, - /* format 14 */ - {0xB400, 0xFE00, "push\t%N"}, - {0xBC00, 0xFE00, "pop\t%O"}, - /* format 2 */ - {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"}, - {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"}, - {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"}, - {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"}, - /* format 8 */ - {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"}, - {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"}, - {0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"}, - /* format 7 */ - {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"}, - {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"}, - /* format 1 */ - {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"}, - {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"}, - {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"}, - /* format 3 */ - {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"}, - {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"}, - {0x3000, 0xF800, "add\t%8-10r, #%0-7d"}, - {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"}, - /* format 6 */ - {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ - /* format 9 */ - {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, - {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, - {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, - {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, - /* format 10 */ - {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"}, - {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"}, - /* format 11 */ - {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"}, - {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"}, - /* format 12 */ - {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"}, - {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"}, - /* format 15 */ - {0xC000, 0xF800, "stmia\t%8-10r!,%M"}, - {0xC800, 0xF800, "ldmia\t%8-10r!,%M"}, - /* format 18 */ - {0xE000, 0xF800, "b\t%0-10B"}, - {0xE800, 0xF800, "undefined"}, - /* format 19 */ - {0xF000, 0xF800, ""}, /* special processing required in disassembler */ - {0xF800, 0xF800, "second half of BL instruction %0-15x"}, - /* format 16 */ - {0xD000, 0xFF00, "beq\t%0-7B"}, - {0xD100, 0xFF00, "bne\t%0-7B"}, - {0xD200, 0xFF00, "bcs\t%0-7B"}, - {0xD300, 0xFF00, "bcc\t%0-7B"}, - {0xD400, 0xFF00, "bmi\t%0-7B"}, - {0xD500, 0xFF00, "bpl\t%0-7B"}, - {0xD600, 0xFF00, "bvs\t%0-7B"}, - {0xD700, 0xFF00, "bvc\t%0-7B"}, - {0xD800, 0xFF00, "bhi\t%0-7B"}, - {0xD900, 0xFF00, "bls\t%0-7B"}, - {0xDA00, 0xFF00, "bge\t%0-7B"}, - {0xDB00, 0xFF00, "blt\t%0-7B"}, - {0xDC00, 0xFF00, "bgt\t%0-7B"}, - {0xDD00, 0xFF00, "ble\t%0-7B"}, - /* format 17 */ - {0xDE00, 0xFF00, "bal\t%0-7B"}, - {0xDF00, 0xFF00, "swi\t%0-7d"}, - /* format 9 */ - {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, - {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, - {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, - {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, - /* the rest */ - {0x0000, 0x0000, "undefined instruction %0-15x"}, - {0x0000, 0x0000, 0} -}; - -#define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \ - ^ 0x200000) - 0x200000) /* 23bit */ - diff --git a/contrib/binutils/opcodes/cgen-asm.c b/contrib/binutils/opcodes/cgen-asm.c deleted file mode 100644 index 7231e2d..0000000 --- a/contrib/binutils/opcodes/cgen-asm.c +++ /dev/null @@ -1,363 +0,0 @@ -/* CGEN generic assembler support code. - - Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "safe-ctype.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" -#include "opintl.h" - -static CGEN_INSN_LIST * hash_insn_array (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *); -static CGEN_INSN_LIST * hash_insn_list (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *); -static void build_asm_hash_table (CGEN_CPU_DESC); - -/* Set the cgen_parse_operand_fn callback. */ - -void -cgen_set_parse_operand_fn (CGEN_CPU_DESC cd, cgen_parse_operand_fn fn) -{ - cd->parse_operand_fn = fn; -} - -/* Called whenever starting to parse an insn. */ - -void -cgen_init_parse_operand (CGEN_CPU_DESC cd) -{ - /* This tells the callback to re-initialize. */ - (void) (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INIT, NULL, 0, 0, NULL, NULL); -} - -/* Subroutine of build_asm_hash_table to add INSNS to the hash table. - - COUNT is the number of elements in INSNS. - ENTSIZE is sizeof (CGEN_IBASE) for the target. - ??? No longer used but leave in for now. - HTABLE points to the hash table. - HENTBUF is a pointer to sufficiently large buffer of hash entries. - The result is a pointer to the next entry to use. - - The table is scanned backwards as additions are made to the front of the - list and we want earlier ones to be prefered. */ - -static CGEN_INSN_LIST * -hash_insn_array (CGEN_CPU_DESC cd, - const CGEN_INSN *insns, - int count, - int entsize ATTRIBUTE_UNUSED, - CGEN_INSN_LIST **htable, - CGEN_INSN_LIST *hentbuf) -{ - int i; - - for (i = count - 1; i >= 0; --i, ++hentbuf) - { - unsigned int hash; - const CGEN_INSN *insn = &insns[i]; - - if (! (* cd->asm_hash_p) (insn)) - continue; - hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (insn)); - hentbuf->next = htable[hash]; - hentbuf->insn = insn; - htable[hash] = hentbuf; - } - - return hentbuf; -} - -/* Subroutine of build_asm_hash_table to add INSNS to the hash table. - This function is identical to hash_insn_array except the insns are - in a list. */ - -static CGEN_INSN_LIST * -hash_insn_list (CGEN_CPU_DESC cd, - const CGEN_INSN_LIST *insns, - CGEN_INSN_LIST **htable, - CGEN_INSN_LIST *hentbuf) -{ - const CGEN_INSN_LIST *ilist; - - for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) - { - unsigned int hash; - - if (! (* cd->asm_hash_p) (ilist->insn)) - continue; - hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (ilist->insn)); - hentbuf->next = htable[hash]; - hentbuf->insn = ilist->insn; - htable[hash] = hentbuf; - } - - return hentbuf; -} - -/* Build the assembler instruction hash table. */ - -static void -build_asm_hash_table (CGEN_CPU_DESC cd) -{ - int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); - CGEN_INSN_TABLE *insn_table = &cd->insn_table; - CGEN_INSN_TABLE *macro_insn_table = &cd->macro_insn_table; - unsigned int hash_size = cd->asm_hash_size; - CGEN_INSN_LIST *hash_entry_buf; - CGEN_INSN_LIST **asm_hash_table; - CGEN_INSN_LIST *asm_hash_table_entries; - - /* The space allocated for the hash table consists of two parts: - the hash table and the hash lists. */ - - asm_hash_table = (CGEN_INSN_LIST **) - xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); - memset (asm_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); - asm_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) - xmalloc (count * sizeof (CGEN_INSN_LIST)); - - /* Add compiled in insns. - Don't include the first one as it is a reserved entry. */ - /* ??? It was the end of all hash chains, and also the special - "invalid insn" marker. May be able to do it differently now. */ - - hash_entry_buf = hash_insn_array (cd, - insn_table->init_entries + 1, - insn_table->num_init_entries - 1, - insn_table->entry_size, - asm_hash_table, hash_entry_buf); - - /* Add compiled in macro-insns. */ - - hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, - macro_insn_table->num_init_entries, - macro_insn_table->entry_size, - asm_hash_table, hash_entry_buf); - - /* Add runtime added insns. - Later added insns will be prefered over earlier ones. */ - - hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, - asm_hash_table, hash_entry_buf); - - /* Add runtime added macro-insns. */ - - hash_insn_list (cd, macro_insn_table->new_entries, - asm_hash_table, hash_entry_buf); - - cd->asm_hash_table = asm_hash_table; - cd->asm_hash_table_entries = asm_hash_table_entries; -} - -/* Return the first entry in the hash list for INSN. */ - -CGEN_INSN_LIST * -cgen_asm_lookup_insn (CGEN_CPU_DESC cd, const char *insn) -{ - unsigned int hash; - - if (cd->asm_hash_table == NULL) - build_asm_hash_table (cd); - - hash = (* cd->asm_hash) (insn); - return cd->asm_hash_table[hash]; -} - -/* Keyword parser. - The result is NULL upon success or an error message. - If successful, *STRP is updated to point passed the keyword. - - ??? At present we have a static notion of how to pick out a keyword. - Later we can allow a target to customize this if necessary [say by - recording something in the keyword table]. */ - -const char * -cgen_parse_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - CGEN_KEYWORD *keyword_table, - long *valuep) -{ - const CGEN_KEYWORD_ENTRY *ke; - char buf[256]; - const char *p,*start; - - if (keyword_table->name_hash_table == NULL) - (void) cgen_keyword_search_init (keyword_table, NULL); - - p = start = *strp; - - /* Allow any first character. This is to make life easier for - the fairly common case of suffixes, eg. 'ld.b.w', where the first - character of the suffix ('.') is special. */ - if (*p) - ++p; - - /* Allow letters, digits, and any special characters. */ - while (((p - start) < (int) sizeof (buf)) - && *p - && (ISALNUM (*p) - || *p == '_' - || strchr (keyword_table->nonalpha_chars, *p))) - ++p; - - if (p - start >= (int) sizeof (buf)) - { - /* All non-empty CGEN keywords can fit into BUF. The only thing - we can match here is the empty keyword. */ - buf[0] = 0; - } - else - { - memcpy (buf, start, p - start); - buf[p - start] = 0; - } - - ke = cgen_keyword_lookup_name (keyword_table, buf); - - if (ke != NULL) - { - *valuep = ke->value; - /* Don't advance pointer if we recognized the null keyword. */ - if (ke->name[0] != 0) - *strp = p; - return NULL; - } - - return "unrecognized keyword/register name"; -} - -/* Parse a small signed integer parser. - ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. - Note that if the caller expects a bfd_vma result, it should call - cgen_parse_address. */ - -const char * -cgen_parse_signed_integer (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, - &result, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - *valuep = value; - return errmsg; -} - -/* Parse a small unsigned integer parser. - ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. - Note that if the caller expects a bfd_vma result, it should call - cgen_parse_address. */ - -const char * -cgen_parse_unsigned_integer (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, - &result, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - *valuep = value; - return errmsg; -} - -/* Address parser. */ - -const char * -cgen_parse_address (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - int opinfo, - enum cgen_parse_operand_result *resultp, - bfd_vma *valuep) -{ - bfd_vma value; - enum cgen_parse_operand_result result_type; - const char *errmsg; - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_ADDRESS, strp, opindex, opinfo, - &result_type, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - { - if (resultp != NULL) - *resultp = result_type; - *valuep = value; - } - return errmsg; -} - -/* Signed integer validation routine. */ - -const char * -cgen_validate_signed_integer (long value, long min, long max) -{ - if (value < min || value > max) - { - static char buf[100]; - - /* xgettext:c-format */ - sprintf (buf, _("operand out of range (%ld not between %ld and %ld)"), - value, min, max); - return buf; - } - - return NULL; -} - -/* Unsigned integer validation routine. - Supplying `min' here may seem unnecessary, but we also want to handle - cases where min != 0 (and max > LONG_MAX). */ - -const char * -cgen_validate_unsigned_integer (unsigned long value, - unsigned long min, - unsigned long max) -{ - if (value < min || value > max) - { - static char buf[100]; - - /* xgettext:c-format */ - sprintf (buf, _("operand out of range (%lu not between %lu and %lu)"), - value, min, max); - return buf; - } - - return NULL; -} diff --git a/contrib/binutils/opcodes/cgen-asm.in b/contrib/binutils/opcodes/cgen-asm.in deleted file mode 100644 index 420f640..0000000 --- a/contrib/binutils/opcodes/cgen-asm.in +++ /dev/null @@ -1,450 +0,0 @@ -/* Assembler interface for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't - -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* ??? Eventually more and more of this stuff can go to cpu-independent files. - Keep that in mind. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "bfd.h" -#include "symcat.h" -#include "@prefix@-desc.h" -#include "@prefix@-opc.h" -#include "opintl.h" -#include "xregex.h" -#include "libiberty.h" -#include "safe-ctype.h" - -#undef min -#define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max -#define max(a,b) ((a) > (b) ? (a) : (b)) - -static const char * parse_insn_normal - (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); - -/* -- assembler routines inserted here. */ - - -/* Regex construction routine. - - This translates an opcode syntax string into a regex string, - by replacing any non-character syntax element (such as an - opcode) with the pattern '.*' - - It then compiles the regex and stores it in the opcode, for - later use by @arch@_cgen_assemble_insn - - Returns NULL for success, an error message for failure. */ - -char * -@arch@_cgen_build_insn_regex (CGEN_INSN *insn) -{ - CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); - const char *mnem = CGEN_INSN_MNEMONIC (insn); - char rxbuf[CGEN_MAX_RX_ELEMENTS]; - char *rx = rxbuf; - const CGEN_SYNTAX_CHAR_TYPE *syn; - int reg_err; - - syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); - - /* Mnemonics come first in the syntax string. */ - if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) - return _("missing mnemonic in syntax string"); - ++syn; - - /* Generate a case sensitive regular expression that emulates case - insensitive matching in the "C" locale. We cannot generate a case - insensitive regular expression because in Turkish locales, 'i' and 'I' - are not equal modulo case conversion. */ - - /* Copy the literal mnemonic out of the insn. */ - for (; *mnem; mnem++) - { - char c = *mnem; - - if (ISALPHA (c)) - { - *rx++ = '['; - *rx++ = TOLOWER (c); - *rx++ = TOUPPER (c); - *rx++ = ']'; - } - else - *rx++ = c; - } - - /* Copy any remaining literals from the syntax string into the rx. */ - for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) - { - if (CGEN_SYNTAX_CHAR_P (* syn)) - { - char c = CGEN_SYNTAX_CHAR (* syn); - - switch (c) - { - /* Escape any regex metacharacters in the syntax. */ - case '.': case '[': case '\\': - case '*': case '^': case '$': - -#ifdef CGEN_ESCAPE_EXTENDED_REGEX - case '?': case '{': case '}': - case '(': case ')': case '*': - case '|': case '+': case ']': -#endif - *rx++ = '\\'; - *rx++ = c; - break; - - default: - if (ISALPHA (c)) - { - *rx++ = '['; - *rx++ = TOLOWER (c); - *rx++ = TOUPPER (c); - *rx++ = ']'; - } - else - *rx++ = c; - break; - } - } - else - { - /* Replace non-syntax fields with globs. */ - *rx++ = '.'; - *rx++ = '*'; - } - } - - /* Trailing whitespace ok. */ - * rx++ = '['; - * rx++ = ' '; - * rx++ = '\t'; - * rx++ = ']'; - * rx++ = '*'; - - /* But anchor it after that. */ - * rx++ = '$'; - * rx = '\0'; - - CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); - reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); - - if (reg_err == 0) - return NULL; - else - { - static char msg[80]; - - regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); - regfree ((regex_t *) CGEN_INSN_RX (insn)); - free (CGEN_INSN_RX (insn)); - (CGEN_INSN_RX (insn)) = NULL; - return msg; - } -} - - -/* Default insn parser. - - The syntax string is scanned and operands are parsed and stored in FIELDS. - Relocs are queued as we go via other callbacks. - - ??? Note that this is currently an all-or-nothing parser. If we fail to - parse the instruction, we return 0 and the caller will start over from - the beginning. Backtracking will be necessary in parsing subexpressions, - but that can be handled there. Not handling backtracking here may get - expensive in the case of the m68k. Deal with later. - - Returns NULL for success, an error message for failure. */ - -static const char * -parse_insn_normal (CGEN_CPU_DESC cd, - const CGEN_INSN *insn, - const char **strp, - CGEN_FIELDS *fields) -{ - /* ??? Runtime added insns not handled yet. */ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - const char *str = *strp; - const char *errmsg; - const char *p; - const CGEN_SYNTAX_CHAR_TYPE * syn; -#ifdef CGEN_MNEMONIC_OPERANDS - /* FIXME: wip */ - int past_opcode_p; -#endif - - /* For now we assume the mnemonic is first (there are no leading operands). - We can parse it without needing to set up operand parsing. - GAS's input scrubber will ensure mnemonics are lowercase, but we may - not be called from GAS. */ - p = CGEN_INSN_MNEMONIC (insn); - while (*p && TOLOWER (*p) == TOLOWER (*str)) - ++p, ++str; - - if (* p) - return _("unrecognized instruction"); - -#ifndef CGEN_MNEMONIC_OPERANDS - if (* str && ! ISSPACE (* str)) - return _("unrecognized instruction"); -#endif - - CGEN_INIT_PARSE (cd); - cgen_init_parse_operand (cd); -#ifdef CGEN_MNEMONIC_OPERANDS - past_opcode_p = 0; -#endif - - /* We don't check for (*str != '\0') here because we want to parse - any trailing fake arguments in the syntax string. */ - syn = CGEN_SYNTAX_STRING (syntax); - - /* Mnemonics come first for now, ensure valid string. */ - if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) - abort (); - - ++syn; - - while (* syn != 0) - { - /* Non operand chars must match exactly. */ - if (CGEN_SYNTAX_CHAR_P (* syn)) - { - /* FIXME: While we allow for non-GAS callers above, we assume the - first char after the mnemonic part is a space. */ - /* FIXME: We also take inappropriate advantage of the fact that - GAS's input scrubber will remove extraneous blanks. */ - if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) - { -#ifdef CGEN_MNEMONIC_OPERANDS - if (CGEN_SYNTAX_CHAR(* syn) == ' ') - past_opcode_p = 1; -#endif - ++ syn; - ++ str; - } - else if (*str) - { - /* Syntax char didn't match. Can't be this insn. */ - static char msg [80]; - - /* xgettext:c-format */ - sprintf (msg, _("syntax error (expected char `%c', found `%c')"), - CGEN_SYNTAX_CHAR(*syn), *str); - return msg; - } - else - { - /* Ran out of input. */ - static char msg [80]; - - /* xgettext:c-format */ - sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), - CGEN_SYNTAX_CHAR(*syn)); - return msg; - } - continue; - } - - /* We have an operand of some sort. */ - errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), - &str, fields); - if (errmsg) - return errmsg; - - /* Done with this operand, continue with next one. */ - ++ syn; - } - - /* If we're at the end of the syntax string, we're done. */ - if (* syn == 0) - { - /* FIXME: For the moment we assume a valid `str' can only contain - blanks now. IE: We needn't try again with a longer version of - the insn and it is assumed that longer versions of insns appear - before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (ISSPACE (* str)) - ++ str; - - if (* str != '\0') - return _("junk at end of line"); /* FIXME: would like to include `str' */ - - return NULL; - } - - /* We couldn't parse it. */ - return _("unrecognized instruction"); -} - -/* Main entry point. - This routine is called for each instruction to be assembled. - STR points to the insn to be assembled. - We assume all necessary tables have been initialized. - The assembled instruction, less any fixups, is stored in BUF. - Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value - still needs to be converted to target byte order, otherwise BUF is an array - of bytes in target byte order. - The result is a pointer to the insn's entry in the opcode table, - or NULL if an error occured (an error message will have already been - printed). - - Note that when processing (non-alias) macro-insns, - this function recurses. - - ??? It's possible to make this cpu-independent. - One would have to deal with a few minor things. - At this point in time doing so would be more of a curiosity than useful - [for example this file isn't _that_ big], but keeping the possibility in - mind helps keep the design clean. */ - -const CGEN_INSN * -@arch@_cgen_assemble_insn (CGEN_CPU_DESC cd, - const char *str, - CGEN_FIELDS *fields, - CGEN_INSN_BYTES_PTR buf, - char **errmsg) -{ - const char *start; - CGEN_INSN_LIST *ilist; - const char *parse_errmsg = NULL; - const char *insert_errmsg = NULL; - int recognized_mnemonic = 0; - - /* Skip leading white space. */ - while (ISSPACE (* str)) - ++ str; - - /* The instructions are stored in hashed lists. - Get the first in the list. */ - ilist = CGEN_ASM_LOOKUP_INSN (cd, str); - - /* Keep looking until we find a match. */ - start = str; - for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) - { - const CGEN_INSN *insn = ilist->insn; - recognized_mnemonic = 1; - -#ifdef CGEN_VALIDATE_INSN_SUPPORTED - /* Not usually needed as unsupported opcodes - shouldn't be in the hash lists. */ - /* Is this insn supported by the selected cpu? */ - if (! @arch@_cgen_insn_supported (cd, insn)) - continue; -#endif - /* If the RELAXED attribute is set, this is an insn that shouldn't be - chosen immediately. Instead, it is used during assembler/linker - relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) - continue; - - str = start; - - /* Skip this insn if str doesn't look right lexically. */ - if (CGEN_INSN_RX (insn) != NULL && - regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) - continue; - - /* Allow parse/insert handlers to obtain length of insn. */ - CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - - parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); - if (parse_errmsg != NULL) - continue; - - /* ??? 0 is passed for `pc'. */ - insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, - (bfd_vma) 0); - if (insert_errmsg != NULL) - continue; - - /* It is up to the caller to actually output the insn and any - queued relocs. */ - return insn; - } - - { - static char errbuf[150]; -#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS - const char *tmp_errmsg; - - /* If requesting verbose error messages, use insert_errmsg. - Failing that, use parse_errmsg. */ - tmp_errmsg = (insert_errmsg ? insert_errmsg : - parse_errmsg ? parse_errmsg : - recognized_mnemonic ? - _("unrecognized form of instruction") : - _("unrecognized instruction")); - - if (strlen (start) > 50) - /* xgettext:c-format */ - sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); - else - /* xgettext:c-format */ - sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); -#else - if (strlen (start) > 50) - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s...'"), start); - else - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s'"), start); -#endif - - *errmsg = errbuf; - return NULL; - } -} - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -@arch@_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! @arch@_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff --git a/contrib/binutils/opcodes/cgen-dis.c b/contrib/binutils/opcodes/cgen-dis.c deleted file mode 100644 index ca621de..0000000 --- a/contrib/binutils/opcodes/cgen-dis.c +++ /dev/null @@ -1,241 +0,0 @@ -/* CGEN generic disassembler support code. - - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 - Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" - -static CGEN_INSN_LIST * hash_insn_array (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *); -static CGEN_INSN_LIST * hash_insn_list (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *); -static void build_dis_hash_table (CGEN_CPU_DESC); -static int count_decodable_bits (const CGEN_INSN *); -static void add_insn_to_hash_chain (CGEN_INSN_LIST *, - const CGEN_INSN *, - CGEN_INSN_LIST **, - unsigned int); - -/* Return the number of decodable bits in this insn. */ -static int -count_decodable_bits (const CGEN_INSN *insn) -{ - unsigned mask = CGEN_INSN_BASE_MASK (insn); - int bits = 0; - int m; - for (m = 1; m != 0; m <<= 1) - { - if (mask & m) - ++bits; - } - return bits; -} - -/* Add an instruction to the hash chain. */ -static void -add_insn_to_hash_chain (CGEN_INSN_LIST *hentbuf, - const CGEN_INSN *insn, - CGEN_INSN_LIST **htable, - unsigned int hash) -{ - CGEN_INSN_LIST *current_buf; - CGEN_INSN_LIST *previous_buf; - int insn_decodable_bits; - - /* Add insns sorted by the number of decodable bits, in decreasing order. - This ensures that any insn which is a special case of another will be - checked first. */ - insn_decodable_bits = count_decodable_bits (insn); - previous_buf = NULL; - for (current_buf = htable[hash]; current_buf != NULL; - current_buf = current_buf->next) - { - int current_decodable_bits = count_decodable_bits (current_buf->insn); - if (insn_decodable_bits >= current_decodable_bits) - break; - previous_buf = current_buf; - } - - /* Now insert the new insn. */ - hentbuf->insn = insn; - hentbuf->next = current_buf; - if (previous_buf == NULL) - htable[hash] = hentbuf; - else - previous_buf->next = hentbuf; -} - -/* Subroutine of build_dis_hash_table to add INSNS to the hash table. - - COUNT is the number of elements in INSNS. - ENTSIZE is sizeof (CGEN_IBASE) for the target. - ??? No longer used but leave in for now. - HTABLE points to the hash table. - HENTBUF is a pointer to sufficiently large buffer of hash entries. - The result is a pointer to the next entry to use. - - The table is scanned backwards as additions are made to the front of the - list and we want earlier ones to be prefered. */ - -static CGEN_INSN_LIST * -hash_insn_array (CGEN_CPU_DESC cd, - const CGEN_INSN * insns, - int count, - int entsize ATTRIBUTE_UNUSED, - CGEN_INSN_LIST ** htable, - CGEN_INSN_LIST * hentbuf) -{ - int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; - int i; - - for (i = count - 1; i >= 0; --i, ++hentbuf) - { - unsigned int hash; - char buf [4]; - unsigned long value; - const CGEN_INSN *insn = &insns[i]; - - if (! (* cd->dis_hash_p) (insn)) - continue; - - /* We don't know whether the target uses the buffer or the base insn - to hash on, so set both up. */ - - value = CGEN_INSN_BASE_VALUE (insn); - bfd_put_bits ((bfd_vma) value, - buf, - CGEN_INSN_MASK_BITSIZE (insn), - big_p); - hash = (* cd->dis_hash) (buf, value); - add_insn_to_hash_chain (hentbuf, insn, htable, hash); - } - - return hentbuf; -} - -/* Subroutine of build_dis_hash_table to add INSNS to the hash table. - This function is identical to hash_insn_array except the insns are - in a list. */ - -static CGEN_INSN_LIST * -hash_insn_list (CGEN_CPU_DESC cd, - const CGEN_INSN_LIST *insns, - CGEN_INSN_LIST **htable, - CGEN_INSN_LIST *hentbuf) -{ - int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; - const CGEN_INSN_LIST *ilist; - - for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) - { - unsigned int hash; - char buf[4]; - unsigned long value; - - if (! (* cd->dis_hash_p) (ilist->insn)) - continue; - - /* We don't know whether the target uses the buffer or the base insn - to hash on, so set both up. */ - - value = CGEN_INSN_BASE_VALUE (ilist->insn); - bfd_put_bits((bfd_vma) value, - buf, - CGEN_INSN_MASK_BITSIZE (ilist->insn), - big_p); - hash = (* cd->dis_hash) (buf, value); - add_insn_to_hash_chain (hentbuf, ilist->insn, htable, hash); - } - - return hentbuf; -} - -/* Build the disassembler instruction hash table. */ - -static void -build_dis_hash_table (CGEN_CPU_DESC cd) -{ - int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); - CGEN_INSN_TABLE *insn_table = & cd->insn_table; - CGEN_INSN_TABLE *macro_insn_table = & cd->macro_insn_table; - unsigned int hash_size = cd->dis_hash_size; - CGEN_INSN_LIST *hash_entry_buf; - CGEN_INSN_LIST **dis_hash_table; - CGEN_INSN_LIST *dis_hash_table_entries; - - /* The space allocated for the hash table consists of two parts: - the hash table and the hash lists. */ - - dis_hash_table = (CGEN_INSN_LIST **) - xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); - memset (dis_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); - dis_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) - xmalloc (count * sizeof (CGEN_INSN_LIST)); - - /* Add compiled in insns. - Don't include the first one as it is a reserved entry. */ - /* ??? It was the end of all hash chains, and also the special - "invalid insn" marker. May be able to do it differently now. */ - - hash_entry_buf = hash_insn_array (cd, - insn_table->init_entries + 1, - insn_table->num_init_entries - 1, - insn_table->entry_size, - dis_hash_table, hash_entry_buf); - - /* Add compiled in macro-insns. */ - - hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, - macro_insn_table->num_init_entries, - macro_insn_table->entry_size, - dis_hash_table, hash_entry_buf); - - /* Add runtime added insns. - Later added insns will be prefered over earlier ones. */ - - hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, - dis_hash_table, hash_entry_buf); - - /* Add runtime added macro-insns. */ - - hash_insn_list (cd, macro_insn_table->new_entries, - dis_hash_table, hash_entry_buf); - - cd->dis_hash_table = dis_hash_table; - cd->dis_hash_table_entries = dis_hash_table_entries; -} - -/* Return the first entry in the hash list for INSN. */ - -CGEN_INSN_LIST * -cgen_dis_lookup_insn (CGEN_CPU_DESC cd, const char * buf, CGEN_INSN_INT value) -{ - unsigned int hash; - - if (cd->dis_hash_table == NULL) - build_dis_hash_table (cd); - - hash = (* cd->dis_hash) (buf, value); - - return cd->dis_hash_table[hash]; -} diff --git a/contrib/binutils/opcodes/cgen-dis.in b/contrib/binutils/opcodes/cgen-dis.in deleted file mode 100644 index 1a3c0fa..0000000 --- a/contrib/binutils/opcodes/cgen-dis.in +++ /dev/null @@ -1,456 +0,0 @@ -/* Disassembler interface for targets using CGEN. -*- C -*- - CGEN: Cpu tools GENerator - -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't - -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 -Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* ??? Eventually more and more of this stuff can go to cpu-independent files. - Keep that in mind. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "dis-asm.h" -#include "bfd.h" -#include "symcat.h" -#include "libiberty.h" -#include "@prefix@-desc.h" -#include "@prefix@-opc.h" -#include "opintl.h" - -/* Default text to print if an instruction isn't recognized. */ -#define UNKNOWN_INSN_MSG _("*unknown*") - -static void print_normal - (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); -static void print_address - (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); -static void print_keyword - (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); -static void print_insn_normal - (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); -static int print_insn - (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); -static int default_print_insn - (CGEN_CPU_DESC, bfd_vma, disassemble_info *); -static int read_insn - (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, - unsigned long *); - -/* -- disassembler routines inserted here */ - -/* Default print handler. */ - -static void -print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void *dis_info, - long value, - unsigned int attrs, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - -#ifdef CGEN_PRINT_NORMAL - CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); -#endif - - /* Print the operand as directed by the attributes. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) - (*info->fprintf_func) (info->stream, "%ld", value); - else - (*info->fprintf_func) (info->stream, "0x%lx", value); -} - -/* Default address handler. */ - -static void -print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void *dis_info, - bfd_vma value, - unsigned int attrs, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - -#ifdef CGEN_PRINT_ADDRESS - CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); -#endif - - /* Print the operand as directed by the attributes. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) - (*info->print_address_func) (value, info); - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) - (*info->print_address_func) (value, info); - else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) - (*info->fprintf_func) (info->stream, "%ld", (long) value); - else - (*info->fprintf_func) (info->stream, "0x%lx", (long) value); -} - -/* Keyword print handler. */ - -static void -print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void *dis_info, - CGEN_KEYWORD *keyword_table, - long value, - unsigned int attrs ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - const CGEN_KEYWORD_ENTRY *ke; - - ke = cgen_keyword_lookup_value (keyword_table, value); - if (ke != NULL) - (*info->fprintf_func) (info->stream, "%s", ke->name); - else - (*info->fprintf_func) (info->stream, "???"); -} - -/* Default insn printer. - - DIS_INFO is defined as `void *' so the disassembler needn't know anything - about disassemble_info. */ - -static void -print_insn_normal (CGEN_CPU_DESC cd, - void *dis_info, - const CGEN_INSN *insn, - CGEN_FIELDS *fields, - bfd_vma pc, - int length) -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - disassemble_info *info = (disassemble_info *) dis_info; - const CGEN_SYNTAX_CHAR_TYPE *syn; - - CGEN_INIT_PRINT (cd); - - for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) - { - if (CGEN_SYNTAX_MNEMONIC_P (*syn)) - { - (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); - continue; - } - if (CGEN_SYNTAX_CHAR_P (*syn)) - { - (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); - continue; - } - - /* We have an operand. */ - @arch@_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, - fields, CGEN_INSN_ATTRS (insn), pc, length); - } -} - -/* Subroutine of print_insn. Reads an insn into the given buffers and updates - the extract info. - Returns 0 if all is well, non-zero otherwise. */ - -static int -read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - bfd_vma pc, - disassemble_info *info, - char *buf, - int buflen, - CGEN_EXTRACT_INFO *ex_info, - unsigned long *insn_value) -{ - int status = (*info->read_memory_func) (pc, buf, buflen, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - ex_info->dis_info = info; - ex_info->valid = (1 << buflen) - 1; - ex_info->insn_bytes = buf; - - *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); - return 0; -} - -/* Utility to print an insn. - BUF is the base part of the insn, target byte order, BUFLEN bytes long. - The result is the size of the insn in bytes or zero for an unknown insn - or -1 if an error occurs fetching data (memory_error_func will have - been called). */ - -static int -print_insn (CGEN_CPU_DESC cd, - bfd_vma pc, - disassemble_info *info, - char *buf, - unsigned int buflen) -{ - CGEN_INSN_INT insn_value; - const CGEN_INSN_LIST *insn_list; - CGEN_EXTRACT_INFO ex_info; - int basesize; - - /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ - basesize = cd->base_insn_bitsize < buflen * 8 ? - cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); - - - /* Fill in ex_info fields like read_insn would. Don't actually call - read_insn, since the incoming buffer is already read (and possibly - modified a la m32r). */ - ex_info.valid = (1 << buflen) - 1; - ex_info.dis_info = info; - ex_info.insn_bytes = buf; - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); - while (insn_list != NULL) - { - const CGEN_INSN *insn = insn_list->insn; - CGEN_FIELDS fields; - int length; - unsigned long insn_value_cropped; - -#ifdef CGEN_VALIDATE_INSN_SUPPORTED - /* Not needed as insn shouldn't be in hash lists if not supported. */ - /* Supported by this cpu? */ - if (! @arch@_cgen_insn_supported (cd, insn)) - { - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - continue; - } -#endif - - /* Basic bit mask must be correct. */ - /* ??? May wish to allow target to defer this check until the extract - handler. */ - - /* Base size may exceed this instruction's size. Extract the - relevant part from the buffer. */ - if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && - (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) - insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), - info->endian == BFD_ENDIAN_BIG); - else - insn_value_cropped = insn_value; - - if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* Printing is handled in two passes. The first pass parses the - machine insn and extracts the fields. The second pass prints - them. */ - - /* Make sure the entire insn is loaded into insn_value, if it - can fit. */ - if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && - (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) - { - unsigned long full_insn_value; - int rc = read_insn (cd, pc, info, buf, - CGEN_INSN_BITSIZE (insn) / 8, - & ex_info, & full_insn_value); - if (rc != 0) - return rc; - length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, &ex_info, full_insn_value, &fields, pc); - } - else - length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - - /* length < 0 -> error */ - if (length < 0) - return length; - if (length > 0) - { - CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ - return length / 8; - } - } - - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - } - - return 0; -} - -/* Default value for CGEN_PRINT_INSN. - The result is the size of the insn in bytes or zero for an unknown insn - or -1 if an error occured fetching bytes. */ - -#ifndef CGEN_PRINT_INSN -#define CGEN_PRINT_INSN default_print_insn -#endif - -static int -default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) -{ - char buf[CGEN_MAX_INSN_SIZE]; - int buflen; - int status; - - /* Attempt to read the base part of the insn. */ - buflen = cd->base_insn_bitsize / 8; - status = (*info->read_memory_func) (pc, buf, buflen, info); - - /* Try again with the minimum part, if min < base. */ - if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) - { - buflen = cd->min_insn_bitsize / 8; - status = (*info->read_memory_func) (pc, buf, buflen, info); - } - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - return print_insn (cd, pc, info, buf, buflen); -} - -/* Main entry point. - Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (in bytes). */ - -typedef struct cpu_desc_list { - struct cpu_desc_list *next; - int isa; - int mach; - int endian; - CGEN_CPU_DESC cd; -} cpu_desc_list; - -int -print_insn_@arch@ (bfd_vma pc, disassemble_info *info) -{ - static cpu_desc_list *cd_list = 0; - cpu_desc_list *cl = 0; - static CGEN_CPU_DESC cd = 0; - static int prev_isa; - static int prev_mach; - static int prev_endian; - int length; - int isa,mach; - int endian = (info->endian == BFD_ENDIAN_BIG - ? CGEN_ENDIAN_BIG - : CGEN_ENDIAN_LITTLE); - enum bfd_architecture arch; - - /* ??? gdb will set mach but leave the architecture as "unknown" */ -#ifndef CGEN_BFD_ARCH -#define CGEN_BFD_ARCH bfd_arch_@arch@ -#endif - arch = info->arch; - if (arch == bfd_arch_unknown) - arch = CGEN_BFD_ARCH; - - /* There's no standard way to compute the machine or isa number - so we leave it to the target. */ -#ifdef CGEN_COMPUTE_MACH - mach = CGEN_COMPUTE_MACH (info); -#else - mach = info->mach; -#endif - -#ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); -#else - isa = info->insn_sets; -#endif - - /* If we've switched cpu's, try to find a handle we've used before */ - if (cd - && (isa != prev_isa - || mach != prev_mach - || endian != prev_endian)) - { - cd = 0; - for (cl = cd_list; cl; cl = cl->next) - { - if (cl->isa == isa && - cl->mach == mach && - cl->endian == endian) - { - cd = cl->cd; - break; - } - } - } - - /* If we haven't initialized yet, initialize the opcode table. */ - if (! cd) - { - const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); - const char *mach_name; - - if (!arch_type) - abort (); - mach_name = arch_type->printable_name; - - prev_isa = isa; - prev_mach = mach; - prev_endian = endian; - cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, - CGEN_CPU_OPEN_BFDMACH, mach_name, - CGEN_CPU_OPEN_ENDIAN, prev_endian, - CGEN_CPU_OPEN_END); - if (!cd) - abort (); - - /* save this away for future reference */ - cl = xmalloc (sizeof (struct cpu_desc_list)); - cl->cd = cd; - cl->isa = isa; - cl->mach = mach; - cl->endian = endian; - cl->next = cd_list; - cd_list = cl; - - @arch@_cgen_init_dis (cd); - } - - /* We try to have as much common code as possible. - But at this point some targets need to take over. */ - /* ??? Some targets may need a hook elsewhere. Try to avoid this, - but if not possible try to move this hook elsewhere rather than - have two hooks. */ - length = CGEN_PRINT_INSN (cd, pc, info); - if (length > 0) - return length; - if (length < 0) - return -1; - - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - return cd->default_insn_bitsize / 8; -} diff --git a/contrib/binutils/opcodes/cgen-ibld.in b/contrib/binutils/opcodes/cgen-ibld.in deleted file mode 100644 index 316f183..0000000 --- a/contrib/binutils/opcodes/cgen-ibld.in +++ /dev/null @@ -1,542 +0,0 @@ -/* Instruction building/extraction support for @arch@. -*- C -*- - -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't - -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. - -This file is part of the GNU Binutils and GDB, the GNU debugger. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* ??? Eventually more and more of this stuff can go to cpu-independent files. - Keep that in mind. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "dis-asm.h" -#include "bfd.h" -#include "symcat.h" -#include "@prefix@-desc.h" -#include "@prefix@-opc.h" -#include "opintl.h" -#include "safe-ctype.h" - -#undef min -#define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max -#define max(a,b) ((a) > (b) ? (a) : (b)) - -/* Used by the ifield rtx function. */ -#define FLD(f) (fields->f) - -static const char * insert_normal - (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); -static const char * insert_insn_normal - (CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); -static int extract_normal - (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *); -static int extract_insn_normal - (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); -#if CGEN_INT_INSN_P -static void put_insn_int_value - (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); -#endif -#if ! CGEN_INT_INSN_P -static CGEN_INLINE void insert_1 - (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); -static CGEN_INLINE int fill_cache - (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); -static CGEN_INLINE long extract_1 - (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); -#endif - -/* Operand insertion. */ - -#if ! CGEN_INT_INSN_P - -/* Subroutine of insert_normal. */ - -static CGEN_INLINE void -insert_1 (CGEN_CPU_DESC cd, - unsigned long value, - int start, - int length, - int word_length, - unsigned char *bufp) -{ - unsigned long x,mask; - int shift; - - x = cgen_get_insn_value (cd, bufp, word_length); - - /* Written this way to avoid undefined behaviour. */ - mask = (((1L << (length - 1)) - 1) << 1) | 1; - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = (word_length - (start + length)); - x = (x & ~(mask << shift)) | ((value & mask) << shift); - - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); -} - -#endif /* ! CGEN_INT_INSN_P */ - -/* Default insertion routine. - - ATTRS is a mask of the boolean attributes. - WORD_OFFSET is the offset in bits from the start of the insn of the value. - WORD_LENGTH is the length of the word in bits in which the value resides. - START is the starting bit number in the word, architecture origin. - LENGTH is the length of VALUE in bits. - TOTAL_LENGTH is the total length of the insn in bits. - - The result is an error message or NULL if success. */ - -/* ??? This duplicates functionality with bfd's howto table and - bfd_install_relocation. */ -/* ??? This doesn't handle bfd_vma's. Create another function when - necessary. */ - -static const char * -insert_normal (CGEN_CPU_DESC cd, - long value, - unsigned int attrs, - unsigned int word_offset, - unsigned int start, - unsigned int length, - unsigned int word_length, - unsigned int total_length, - CGEN_INSN_BYTES_PTR buffer) -{ - static char errbuf[100]; - /* Written this way to avoid undefined behaviour. */ - unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; - - /* If LENGTH is zero, this operand doesn't contribute to the value. */ - if (length == 0) - return NULL; - -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - - if (word_length > 32) - abort (); - - /* For architectures with insns smaller than the base-insn-bitsize, - word_length may be too big. */ - if (cd->min_insn_bitsize < cd->base_insn_bitsize) - { - if (word_offset == 0 - && word_length > total_length) - word_length = total_length; - } - - /* Ensure VALUE will fit. */ - if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) - { - long minval = - (1L << (length - 1)); - unsigned long maxval = mask; - - if ((value > 0 && (unsigned long) value > maxval) - || value < minval) - { - /* xgettext:c-format */ - sprintf (errbuf, - _("operand out of range (%ld not between %ld and %lu)"), - value, minval, maxval); - return errbuf; - } - } - else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) - { - unsigned long maxval = mask; - - if ((unsigned long) value > maxval) - { - /* xgettext:c-format */ - sprintf (errbuf, - _("operand out of range (%lu not between 0 and %lu)"), - value, maxval); - return errbuf; - } - } - else - { - if (! cgen_signed_overflow_ok_p (cd)) - { - long minval = - (1L << (length - 1)); - long maxval = (1L << (length - 1)) - 1; - - if (value < minval || value > maxval) - { - sprintf - /* xgettext:c-format */ - (errbuf, _("operand out of range (%ld not between %ld and %ld)"), - value, minval, maxval); - return errbuf; - } - } - } - -#if CGEN_INT_INSN_P - - { - int shift; - - if (CGEN_INSN_LSB0_P) - shift = (word_offset + start + 1) - length; - else - shift = total_length - (word_offset + start + length); - *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); - } - -#else /* ! CGEN_INT_INSN_P */ - - { - unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; - - insert_1 (cd, value, start, length, word_length, bufp); - } - -#endif /* ! CGEN_INT_INSN_P */ - - return NULL; -} - -/* Default insn builder (insert handler). - The instruction is recorded in CGEN_INT_INSN_P byte order (meaning - that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is - recorded in host byte order, otherwise BUFFER is an array of bytes - and the value is recorded in target byte order). - The result is an error message or NULL if success. */ - -static const char * -insert_insn_normal (CGEN_CPU_DESC cd, - const CGEN_INSN * insn, - CGEN_FIELDS * fields, - CGEN_INSN_BYTES_PTR buffer, - bfd_vma pc) -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - unsigned long value; - const CGEN_SYNTAX_CHAR_TYPE * syn; - - CGEN_INIT_INSERT (cd); - value = CGEN_INSN_BASE_VALUE (insn); - - /* If we're recording insns as numbers (rather than a string of bytes), - target byte order handling is deferred until later. */ - -#if CGEN_INT_INSN_P - - put_insn_int_value (cd, buffer, cd->base_insn_bitsize, - CGEN_FIELDS_BITSIZE (fields), value); - -#else - - cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); - -#endif /* ! CGEN_INT_INSN_P */ - - /* ??? It would be better to scan the format's fields. - Still need to be able to insert a value based on the operand though; - e.g. storing a branch displacement that got resolved later. - Needs more thought first. */ - - for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) - { - const char *errmsg; - - if (CGEN_SYNTAX_CHAR_P (* syn)) - continue; - - errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), - fields, buffer, pc); - if (errmsg) - return errmsg; - } - - return NULL; -} - -#if CGEN_INT_INSN_P -/* Cover function to store an insn value into an integral insn. Must go here - because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ - -static void -put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - CGEN_INSN_BYTES_PTR buf, - int length, - int insn_length, - CGEN_INSN_INT value) -{ - /* For architectures with insns smaller than the base-insn-bitsize, - length may be too big. */ - if (length > insn_length) - *buf = value; - else - { - int shift = insn_length - length; - /* Written this way to avoid undefined behaviour. */ - CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; - *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); - } -} -#endif - -/* Operand extraction. */ - -#if ! CGEN_INT_INSN_P - -/* Subroutine of extract_normal. - Ensure sufficient bytes are cached in EX_INFO. - OFFSET is the offset in bytes from the start of the insn of the value. - BYTES is the length of the needed value. - Returns 1 for success, 0 for failure. */ - -static CGEN_INLINE int -fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - CGEN_EXTRACT_INFO *ex_info, - int offset, - int bytes, - bfd_vma pc) -{ - /* It's doubtful that the middle part has already been fetched so - we don't optimize that case. kiss. */ - unsigned int mask; - disassemble_info *info = (disassemble_info *) ex_info->dis_info; - - /* First do a quick check. */ - mask = (1 << bytes) - 1; - if (((ex_info->valid >> offset) & mask) == mask) - return 1; - - /* Search for the first byte we need to read. */ - for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) - if (! (mask & ex_info->valid)) - break; - - if (bytes) - { - int status; - - pc += offset; - status = (*info->read_memory_func) - (pc, ex_info->insn_bytes + offset, bytes, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return 0; - } - - ex_info->valid |= ((1 << bytes) - 1) << offset; - } - - return 1; -} - -/* Subroutine of extract_normal. */ - -static CGEN_INLINE long -extract_1 (CGEN_CPU_DESC cd, - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, - int start, - int length, - int word_length, - unsigned char *bufp, - bfd_vma pc ATTRIBUTE_UNUSED) -{ - unsigned long x; - int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif - x = cgen_get_insn_value (cd, bufp, word_length); - - if (CGEN_INSN_LSB0_P) - shift = (start + 1) - length; - else - shift = (word_length - (start + length)); - return x >> shift; -} - -#endif /* ! CGEN_INT_INSN_P */ - -/* Default extraction routine. - - INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, - or sometimes less for cases like the m32r where the base insn size is 32 - but some insns are 16 bits. - ATTRS is a mask of the boolean attributes. We only need `SIGNED', - but for generality we take a bitmask of all of them. - WORD_OFFSET is the offset in bits from the start of the insn of the value. - WORD_LENGTH is the length of the word in bits in which the value resides. - START is the starting bit number in the word, architecture origin. - LENGTH is the length of VALUE in bits. - TOTAL_LENGTH is the total length of the insn in bits. - - Returns 1 for success, 0 for failure. */ - -/* ??? The return code isn't properly used. wip. */ - -/* ??? This doesn't handle bfd_vma's. Create another function when - necessary. */ - -static int -extract_normal (CGEN_CPU_DESC cd, -#if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info, -#else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, -#endif - CGEN_INSN_INT insn_value, - unsigned int attrs, - unsigned int word_offset, - unsigned int start, - unsigned int length, - unsigned int word_length, - unsigned int total_length, -#if ! CGEN_INT_INSN_P - bfd_vma pc, -#else - bfd_vma pc ATTRIBUTE_UNUSED, -#endif - long *valuep) -{ - long value, mask; - - /* If LENGTH is zero, this operand doesn't contribute to the value - so give it a standard value of zero. */ - if (length == 0) - { - *valuep = 0; - return 1; - } - -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - - if (word_length > 32) - abort (); - - /* For architectures with insns smaller than the insn-base-bitsize, - word_length may be too big. */ - if (cd->min_insn_bitsize < cd->base_insn_bitsize) - { - if (word_offset == 0 - && word_length > total_length) - word_length = total_length; - } - - /* Does the value reside in INSN_VALUE, and at the right alignment? */ - - if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) - { - if (CGEN_INSN_LSB0_P) - value = insn_value >> ((word_offset + start + 1) - length); - else - value = insn_value >> (total_length - ( word_offset + start + length)); - } - -#if ! CGEN_INT_INSN_P - - else - { - unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; - - if (word_length > 32) - abort (); - - if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) - return 0; - - value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); - } - -#endif /* ! CGEN_INT_INSN_P */ - - /* Written this way to avoid undefined behaviour. */ - mask = (((1L << (length - 1)) - 1) << 1) | 1; - - value &= mask; - /* sign extend? */ - if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) - && (value & (1L << (length - 1)))) - value |= ~mask; - - *valuep = value; - - return 1; -} - -/* Default insn extractor. - - INSN_VALUE is the first base_insn_bitsize bits, translated to host order. - The extracted fields are stored in FIELDS. - EX_INFO is used to handle reading variable length insns. - Return the length of the insn in bits, or 0 if no match, - or -1 if an error occurs fetching data (memory_error_func will have - been called). */ - -static int -extract_insn_normal (CGEN_CPU_DESC cd, - const CGEN_INSN *insn, - CGEN_EXTRACT_INFO *ex_info, - CGEN_INSN_INT insn_value, - CGEN_FIELDS *fields, - bfd_vma pc) -{ - const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); - const CGEN_SYNTAX_CHAR_TYPE *syn; - - CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - - CGEN_INIT_EXTRACT (cd); - - for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) - { - int length; - - if (CGEN_SYNTAX_CHAR_P (*syn)) - continue; - - length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), - ex_info, insn_value, fields, pc); - if (length <= 0) - return length; - } - - /* We recognized and successfully extracted this insn. */ - return CGEN_INSN_BITSIZE (insn); -} - -/* machine generated code added here */ diff --git a/contrib/binutils/opcodes/cgen-opc.c b/contrib/binutils/opcodes/cgen-opc.c deleted file mode 100644 index 882b348..0000000 --- a/contrib/binutils/opcodes/cgen-opc.c +++ /dev/null @@ -1,615 +0,0 @@ -/* CGEN generic opcode support. - - Copyright 1996, 1997, 1998, 1999, 2000, 2001 - Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "safe-ctype.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" - -#ifdef HAVE_ALLOCA_H -#include <alloca.h> -#endif - -static unsigned int hash_keyword_name - (const CGEN_KEYWORD *, const char *, int); -static unsigned int hash_keyword_value - (const CGEN_KEYWORD *, unsigned int); -static void build_keyword_hash_tables - (CGEN_KEYWORD *); - -/* Return number of hash table entries to use for N elements. */ -#define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31) - -/* Look up *NAMEP in the keyword table KT. - The result is the keyword entry or NULL if not found. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_name (CGEN_KEYWORD *kt, const char *name) -{ - const CGEN_KEYWORD_ENTRY *ke; - const char *p,*n; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - ke = kt->name_hash_table[hash_keyword_name (kt, name, 0)]; - - /* We do case insensitive comparisons. - If that ever becomes a problem, add an attribute that denotes - "do case sensitive comparisons". */ - - while (ke != NULL) - { - n = name; - p = ke->name; - - while (*p - && (*p == *n - || (ISALPHA (*p) && (TOLOWER (*p) == TOLOWER (*n))))) - ++n, ++p; - - if (!*p && !*n) - return ke; - - ke = ke->next_name; - } - - if (kt->null_entry) - return kt->null_entry; - return NULL; -} - -/* Look up VALUE in the keyword table KT. - The result is the keyword entry or NULL if not found. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_value (CGEN_KEYWORD *kt, int value) -{ - const CGEN_KEYWORD_ENTRY *ke; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - ke = kt->value_hash_table[hash_keyword_value (kt, value)]; - - while (ke != NULL) - { - if (value == ke->value) - return ke; - ke = ke->next_value; - } - - return NULL; -} - -/* Add an entry to a keyword table. */ - -void -cgen_keyword_add (CGEN_KEYWORD *kt, CGEN_KEYWORD_ENTRY *ke) -{ - unsigned int hash; - size_t i; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - hash = hash_keyword_name (kt, ke->name, 0); - ke->next_name = kt->name_hash_table[hash]; - kt->name_hash_table[hash] = ke; - - hash = hash_keyword_value (kt, ke->value); - ke->next_value = kt->value_hash_table[hash]; - kt->value_hash_table[hash] = ke; - - if (ke->name[0] == 0) - kt->null_entry = ke; - - for (i = 1; i < strlen (ke->name); i++) - if (! ISALNUM (ke->name[i]) - && ! strchr (kt->nonalpha_chars, ke->name[i])) - { - size_t idx = strlen (kt->nonalpha_chars); - - /* If you hit this limit, please don't just - increase the size of the field, instead - look for a better algorithm. */ - if (idx >= sizeof (kt->nonalpha_chars) - 1) - abort (); - kt->nonalpha_chars[idx] = ke->name[i]; - kt->nonalpha_chars[idx+1] = 0; - } -} - -/* FIXME: Need function to return count of keywords. */ - -/* Initialize a keyword table search. - SPEC is a specification of what to search for. - A value of NULL means to find every keyword. - Currently NULL is the only acceptable value [further specification - deferred]. - The result is an opaque data item used to record the search status. - It is passed to each call to cgen_keyword_search_next. */ - -CGEN_KEYWORD_SEARCH -cgen_keyword_search_init (CGEN_KEYWORD *kt, const char *spec) -{ - CGEN_KEYWORD_SEARCH search; - - /* FIXME: Need to specify format of PARAMS. */ - if (spec != NULL) - abort (); - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - search.table = kt; - search.spec = spec; - search.current_hash = 0; - search.current_entry = NULL; - return search; -} - -/* Return the next keyword specified by SEARCH. - The result is the next entry or NULL if there are no more. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_search_next (CGEN_KEYWORD_SEARCH *search) -{ - /* Has search finished? */ - if (search->current_hash == search->table->hash_table_size) - return NULL; - - /* Search in progress? */ - if (search->current_entry != NULL - /* Anything left on this hash chain? */ - && search->current_entry->next_name != NULL) - { - search->current_entry = search->current_entry->next_name; - return search->current_entry; - } - - /* Move to next hash chain [unless we haven't started yet]. */ - if (search->current_entry != NULL) - ++search->current_hash; - - while (search->current_hash < search->table->hash_table_size) - { - search->current_entry = search->table->name_hash_table[search->current_hash]; - if (search->current_entry != NULL) - return search->current_entry; - ++search->current_hash; - } - - return NULL; -} - -/* Return first entry in hash chain for NAME. - If CASE_SENSITIVE_P is non-zero, return a case sensitive hash. */ - -static unsigned int -hash_keyword_name (const CGEN_KEYWORD *kt, - const char *name, - int case_sensitive_p) -{ - unsigned int hash; - - if (case_sensitive_p) - for (hash = 0; *name; ++name) - hash = (hash * 97) + (unsigned char) *name; - else - for (hash = 0; *name; ++name) - hash = (hash * 97) + (unsigned char) TOLOWER (*name); - return hash % kt->hash_table_size; -} - -/* Return first entry in hash chain for VALUE. */ - -static unsigned int -hash_keyword_value (const CGEN_KEYWORD *kt, unsigned int value) -{ - return value % kt->hash_table_size; -} - -/* Build a keyword table's hash tables. - We probably needn't build the value hash table for the assembler when - we're using the disassembler, but we keep things simple. */ - -static void -build_keyword_hash_tables (CGEN_KEYWORD *kt) -{ - int i; - /* Use the number of compiled in entries as an estimate for the - typical sized table [not too many added at runtime]. */ - unsigned int size = KEYWORD_HASH_SIZE (kt->num_init_entries); - - kt->hash_table_size = size; - kt->name_hash_table = (CGEN_KEYWORD_ENTRY **) - xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); - memset (kt->name_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); - kt->value_hash_table = (CGEN_KEYWORD_ENTRY **) - xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); - memset (kt->value_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); - - /* The table is scanned backwards as we want keywords appearing earlier to - be prefered over later ones. */ - for (i = kt->num_init_entries - 1; i >= 0; --i) - cgen_keyword_add (kt, &kt->init_entries[i]); -} - -/* Hardware support. */ - -/* Lookup a hardware element by its name. - Returns NULL if NAME is not supported by the currently selected - mach/isa. */ - -const CGEN_HW_ENTRY * -cgen_hw_lookup_by_name (CGEN_CPU_DESC cd, const char *name) -{ - unsigned int i; - const CGEN_HW_ENTRY **hw = cd->hw_table.entries; - - for (i = 0; i < cd->hw_table.num_entries; ++i) - if (hw[i] && strcmp (name, hw[i]->name) == 0) - return hw[i]; - - return NULL; -} - -/* Lookup a hardware element by its number. - Hardware elements are enumerated, however it may be possible to add some - at runtime, thus HWNUM is not an enum type but rather an int. - Returns NULL if HWNUM is not supported by the currently selected mach. */ - -const CGEN_HW_ENTRY * -cgen_hw_lookup_by_num (CGEN_CPU_DESC cd, unsigned int hwnum) -{ - unsigned int i; - const CGEN_HW_ENTRY **hw = cd->hw_table.entries; - - /* ??? This can be speeded up. */ - for (i = 0; i < cd->hw_table.num_entries; ++i) - if (hw[i] && hwnum == hw[i]->type) - return hw[i]; - - return NULL; -} - -/* Operand support. */ - -/* Lookup an operand by its name. - Returns NULL if NAME is not supported by the currently selected - mach/isa. */ - -const CGEN_OPERAND * -cgen_operand_lookup_by_name (CGEN_CPU_DESC cd, const char *name) -{ - unsigned int i; - const CGEN_OPERAND **op = cd->operand_table.entries; - - for (i = 0; i < cd->operand_table.num_entries; ++i) - if (op[i] && strcmp (name, op[i]->name) == 0) - return op[i]; - - return NULL; -} - -/* Lookup an operand by its number. - Operands are enumerated, however it may be possible to add some - at runtime, thus OPNUM is not an enum type but rather an int. - Returns NULL if OPNUM is not supported by the currently selected - mach/isa. */ - -const CGEN_OPERAND * -cgen_operand_lookup_by_num (CGEN_CPU_DESC cd, int opnum) -{ - return cd->operand_table.entries[opnum]; -} - -/* Instruction support. */ - -/* Return number of instructions. This includes any added at runtime. */ - -int -cgen_insn_count (CGEN_CPU_DESC cd) -{ - int count = cd->insn_table.num_init_entries; - CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries; - - for ( ; rt_insns != NULL; rt_insns = rt_insns->next) - ++count; - - return count; -} - -/* Return number of macro-instructions. - This includes any added at runtime. */ - -int -cgen_macro_insn_count (CGEN_CPU_DESC cd) -{ - int count = cd->macro_insn_table.num_init_entries; - CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries; - - for ( ; rt_insns != NULL; rt_insns = rt_insns->next) - ++count; - - return count; -} - -/* Cover function to read and properly byteswap an insn value. */ - -CGEN_INSN_INT -cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length) -{ - int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); - int insn_chunk_bitsize = cd->insn_chunk_bitsize; - CGEN_INSN_INT value = 0; - - if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) - { - /* We need to divide up the incoming value into insn_chunk_bitsize-length - segments, and endian-convert them, one at a time. */ - int i; - - /* Enforce divisibility. */ - if ((length % insn_chunk_bitsize) != 0) - abort (); - - for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */ - { - int index; - bfd_vma this_value; - index = i; /* NB: not dependent on endianness; opposite of cgen_put_insn_value! */ - this_value = bfd_get_bits (& buf[index / 8], insn_chunk_bitsize, big_p); - value = (value << insn_chunk_bitsize) | this_value; - } - } - else - { - value = bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG); - } - - return value; -} - -/* Cover function to store an insn value properly byteswapped. */ - -void -cgen_put_insn_value (CGEN_CPU_DESC cd, - unsigned char *buf, - int length, - CGEN_INSN_INT value) -{ - int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); - int insn_chunk_bitsize = cd->insn_chunk_bitsize; - - if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) - { - /* We need to divide up the incoming value into insn_chunk_bitsize-length - segments, and endian-convert them, one at a time. */ - int i; - - /* Enforce divisibility. */ - if ((length % insn_chunk_bitsize) != 0) - abort (); - - for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */ - { - int index; - index = (length - insn_chunk_bitsize - i); /* NB: not dependent on endianness! */ - bfd_put_bits ((bfd_vma) value, & buf[index / 8], insn_chunk_bitsize, big_p); - value >>= insn_chunk_bitsize; - } - } - else - { - bfd_put_bits ((bfd_vma) value, buf, length, big_p); - } -} - -/* Look up instruction INSN_*_VALUE and extract its fields. - INSN_INT_VALUE is used if CGEN_INT_INSN_P. - Otherwise INSN_BYTES_VALUE is used. - INSN, if non-null, is the insn table entry. - Otherwise INSN_*_VALUE is examined to compute it. - LENGTH is the bit length of INSN_*_VALUE if known, otherwise 0. - 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'. - If INSN != NULL, LENGTH must be valid. - ALIAS_P is non-zero if alias insns are to be included in the search. - - The result is a pointer to the insn table entry, or NULL if the instruction - wasn't recognized. */ - -/* ??? Will need to be revisited for VLIW architectures. */ - -const CGEN_INSN * -cgen_lookup_insn (CGEN_CPU_DESC cd, - const CGEN_INSN *insn, - CGEN_INSN_INT insn_int_value, - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value, - int length, - CGEN_FIELDS *fields, - int alias_p) -{ - unsigned char *buf; - CGEN_INSN_INT base_insn; - CGEN_EXTRACT_INFO ex_info; - CGEN_EXTRACT_INFO *info; - - if (cd->int_insn_p) - { - info = NULL; - buf = (unsigned char *) alloca (cd->max_insn_bitsize / 8); - cgen_put_insn_value (cd, buf, length, insn_int_value); - base_insn = insn_int_value; - } - else - { - info = &ex_info; - ex_info.dis_info = NULL; - ex_info.insn_bytes = insn_bytes_value; - ex_info.valid = -1; - buf = insn_bytes_value; - base_insn = cgen_get_insn_value (cd, buf, length); - } - - if (!insn) - { - const CGEN_INSN_LIST *insn_list; - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = cgen_dis_lookup_insn (cd, buf, base_insn); - while (insn_list != NULL) - { - insn = insn_list->insn; - - if (alias_p - /* FIXME: Ensure ALIAS attribute always has same index. */ - || ! CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) - { - /* Basic bit mask must be correct. */ - /* ??? May wish to allow target to defer this check until the - extract handler. */ - if ((base_insn & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* ??? 0 is passed for `pc' */ - int elength = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, info, base_insn, fields, (bfd_vma) 0); - if (elength > 0) - { - /* sanity check */ - if (length != 0 && length != elength) - abort (); - return insn; - } - } - } - - insn_list = insn_list->next; - } - } - else - { - /* Sanity check: can't pass an alias insn if ! alias_p. */ - if (! alias_p - && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) - abort (); - /* Sanity check: length must be correct. */ - if (length != CGEN_INSN_BITSIZE (insn)) - abort (); - - /* ??? 0 is passed for `pc' */ - length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, info, base_insn, fields, (bfd_vma) 0); - /* Sanity check: must succeed. - Could relax this later if it ever proves useful. */ - if (length == 0) - abort (); - return insn; - } - - return NULL; -} - -/* Fill in the operand instances used by INSN whose operands are FIELDS. - INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled - in. */ - -void -cgen_get_insn_operands (CGEN_CPU_DESC cd, - const CGEN_INSN *insn, - const CGEN_FIELDS *fields, - int *indices) -{ - const CGEN_OPINST *opinst; - int i; - - if (insn->opinst == NULL) - abort (); - for (i = 0, opinst = insn->opinst; opinst->type != CGEN_OPINST_END; ++i, ++opinst) - { - enum cgen_operand_type op_type = opinst->op_type; - if (op_type == CGEN_OPERAND_NIL) - indices[i] = opinst->index; - else - indices[i] = (*cd->get_int_operand) (cd, op_type, fields); - } -} - -/* Cover function to cgen_get_insn_operands when either INSN or FIELDS - isn't known. - The INSN, INSN_*_VALUE, and LENGTH arguments are passed to - cgen_lookup_insn unchanged. - INSN_INT_VALUE is used if CGEN_INT_INSN_P. - Otherwise INSN_BYTES_VALUE is used. - - The result is the insn table entry or NULL if the instruction wasn't - recognized. */ - -const CGEN_INSN * -cgen_lookup_get_insn_operands (CGEN_CPU_DESC cd, - const CGEN_INSN *insn, - CGEN_INSN_INT insn_int_value, - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value, - int length, - int *indices, - CGEN_FIELDS *fields) -{ - /* Pass non-zero for ALIAS_P only if INSN != NULL. - If INSN == NULL, we want a real insn. */ - insn = cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, - length, fields, insn != NULL); - if (! insn) - return NULL; - - cgen_get_insn_operands (cd, insn, fields, indices); - return insn; -} - -/* Allow signed overflow of instruction fields. */ -void -cgen_set_signed_overflow_ok (CGEN_CPU_DESC cd) -{ - cd->signed_overflow_ok_p = 1; -} - -/* Generate an error message if a signed field in an instruction overflows. */ -void -cgen_clear_signed_overflow_ok (CGEN_CPU_DESC cd) -{ - cd->signed_overflow_ok_p = 0; -} - -/* Will an error message be generated if a signed field in an instruction overflows ? */ -unsigned int -cgen_signed_overflow_ok_p (CGEN_CPU_DESC cd) -{ - return cd->signed_overflow_ok_p; -} diff --git a/contrib/binutils/opcodes/cgen.sh b/contrib/binutils/opcodes/cgen.sh deleted file mode 100644 index 5a340b6..0000000 --- a/contrib/binutils/opcodes/cgen.sh +++ /dev/null @@ -1,165 +0,0 @@ -#! /bin/sh -# CGEN generic assembler support code. -# -# Copyright 2001 Free Software Foundation, Inc. -# -# This file is part of the GNU Binutils and GDB, the GNU debugger. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -# -# Generate CGEN opcode files: arch-desc.[ch], arch-opc.[ch], -# arch-asm.c, arch-dis.c, arch-opinst.c, arch-ibld.[ch]. -# -# Usage: -# cgen.sh action srcdir cgen cgendir cgenflags arch prefix \ -# arch-file opc-file options [extrafiles] -# -# ACTION is currently always "opcodes". It exists to be consistent with the -# simulator. -# ARCH is the name of the architecture. -# It is substituted into @arch@ and @ARCH@ in the generated files. -# PREFIX is both the generated file prefix and is substituted into -# @prefix@ in the generated files. -# ARCH-FILE is the name of the .cpu file (including path). -# OPC-FILE is the name of the .opc file (including path). -# OPTIONS is comma separated list of options (???). -# EXTRAFILES is a space separated list (1 arg still) of extra files to build: -# - opinst - arch-opinst.c is being made, causes semantic analysis -# -# We store the generated files in the source directory until we decide to -# ship a Scheme interpreter (or other implementation) with gdb/binutils. -# Maybe we never will. - -# We want to behave like make, any error forces us to stop. -set -e - -action=$1 -srcdir=$2 -cgen=$3 -cgendir=$4 -cgenflags=$5 -arch=$6 -prefix=$7 -archfile=$8 -opcfile=$9 -shift ; options=$9 - -# List of extra files to build. -# Values: opinst (only 1 extra file at present) -shift ; extrafiles=$9 - -rootdir=${srcdir}/.. - -# $arch is $6, as passed on the command line. -# $ARCH is the same argument but in all uppercase. -# Both forms are used in this script. - -lowercase='abcdefghijklmnopqrstuvwxyz' -uppercase='ABCDEFGHIJKLMNOPQRSTUVWXYZ' -ARCH=`echo ${arch} | tr "${lowercase}" "${uppercase}"` - -extrafile_args="" -for ef in .. $extrafiles -do - case $ef in - ..) ;; - opinst) extrafile_args="-Q tmp-opinst.c1 $extrafile_args" ;; - esac -done - -case $action in -opcodes) - # Remove residual working files. - rm -f tmp-desc.h tmp-desc.h1 - rm -f tmp-desc.c tmp-desc.c1 - rm -f tmp-opc.h tmp-opc.h1 - rm -f tmp-opc.c tmp-opc.c1 - rm -f tmp-opinst.c tmp-opinst.c1 - rm -f tmp-ibld.h tmp-ibld.h1 - rm -f tmp-ibld.c tmp-ibld.in1 - rm -f tmp-asm.c tmp-asm.in1 - rm -f tmp-dis.c tmp-dis.in1 - - # Run CGEN. - ${cgen} -s ${cgendir}/cgen-opc.scm \ - -s ${cgendir} \ - ${cgenflags} \ - -f "${options}" \ - -m all \ - -a ${archfile} \ - -OPC ${opcfile} \ - -H tmp-desc.h1 \ - -C tmp-desc.c1 \ - -O tmp-opc.h1 \ - -P tmp-opc.c1 \ - -L tmp-ibld.in1 \ - -A tmp-asm.in1 \ - -D tmp-dis.in1 \ - ${extrafile_args} - - # Customise generated files for the particular architecture. - sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-desc.h1 > tmp-desc.h - ${rootdir}/move-if-change tmp-desc.h ${srcdir}/${prefix}-desc.h - - sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ - -e "s/@prefix@/${prefix}/" < tmp-desc.c1 > tmp-desc.c - ${rootdir}/move-if-change tmp-desc.c ${srcdir}/${prefix}-desc.c - - sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-opc.h1 > tmp-opc.h - ${rootdir}/move-if-change tmp-opc.h ${srcdir}/${prefix}-opc.h - - sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ - -e "s/@prefix@/${prefix}/" < tmp-opc.c1 > tmp-opc.c - ${rootdir}/move-if-change tmp-opc.c ${srcdir}/${prefix}-opc.c - - case $extrafiles in - *opinst*) - sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ - -e "s/@prefix@/${prefix}/" < tmp-opinst.c1 >tmp-opinst.c - ${rootdir}/move-if-change tmp-opinst.c ${srcdir}/${prefix}-opinst.c - ;; - esac - - cat ${srcdir}/cgen-ibld.in tmp-ibld.in1 | \ - sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ - -e "s/@prefix@/${prefix}/" > tmp-ibld.c - ${rootdir}/move-if-change tmp-ibld.c ${srcdir}/${prefix}-ibld.c - - sed -e "/ -- assembler routines/ r tmp-asm.in1" ${srcdir}/cgen-asm.in \ - | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ - -e "s/@prefix@/${prefix}/" > tmp-asm.c - ${rootdir}/move-if-change tmp-asm.c ${srcdir}/${prefix}-asm.c - - sed -e "/ -- disassembler routines/ r tmp-dis.in1" ${srcdir}/cgen-dis.in \ - | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \ - -e "s/@prefix@/${prefix}/" > tmp-dis.c - ${rootdir}/move-if-change tmp-dis.c ${srcdir}/${prefix}-dis.c - - # Remove temporary files. - rm -f tmp-desc.h1 tmp-desc.c1 - rm -f tmp-opc.h1 tmp-opc.c1 - rm -f tmp-opinst.c1 - rm -f tmp-ibld.h1 tmp-ibld.in1 - rm -f tmp-asm.in1 tmp-dis.in1 - ;; - -*) - echo "$0: bad action: ${action}" >&2 - exit 1 - ;; - -esac - -exit 0 diff --git a/contrib/binutils/opcodes/config.in b/contrib/binutils/opcodes/config.in deleted file mode 100644 index 5caef55..0000000 --- a/contrib/binutils/opcodes/config.in +++ /dev/null @@ -1,132 +0,0 @@ -/* config.in. Generated automatically from configure.in by autoheader. */ - -/* Define if using alloca.c. */ -#undef C_ALLOCA - -/* Define to empty if the keyword does not work. */ -#undef const - -/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. - This function is required for alloca.c support on those systems. */ -#undef CRAY_STACKSEG_END - -/* Define if you have alloca, as a function or macro. */ -#undef HAVE_ALLOCA - -/* Define if you have <alloca.h> and it should be used (not on Ultrix). */ -#undef HAVE_ALLOCA_H - -/* Define if you have a working `mmap' system call. */ -#undef HAVE_MMAP - -/* Define as __inline if that's what the C compiler calls it. */ -#undef inline - -/* Define to `long' if <sys/types.h> doesn't define. */ -#undef off_t - -/* Define to `unsigned' if <sys/types.h> doesn't define. */ -#undef size_t - -/* If using the C implementation of alloca, define if you know the - direction of stack growth for your system; otherwise it will be - automatically deduced at run-time. - STACK_DIRECTION > 0 => grows toward higher addresses - STACK_DIRECTION < 0 => grows toward lower addresses - STACK_DIRECTION = 0 => direction of growth unknown - */ -#undef STACK_DIRECTION - -/* Define if you have the ANSI C header files. */ -#undef STDC_HEADERS - -/* Define if you have the __argz_count function. */ -#undef HAVE___ARGZ_COUNT - -/* Define if you have the __argz_next function. */ -#undef HAVE___ARGZ_NEXT - -/* Define if you have the __argz_stringify function. */ -#undef HAVE___ARGZ_STRINGIFY - -/* Define if you have the dcgettext function. */ -#undef HAVE_DCGETTEXT - -/* Define if you have the getcwd function. */ -#undef HAVE_GETCWD - -/* Define if you have the getpagesize function. */ -#undef HAVE_GETPAGESIZE - -/* Define if you have the munmap function. */ -#undef HAVE_MUNMAP - -/* Define if you have the putenv function. */ -#undef HAVE_PUTENV - -/* Define if you have the setenv function. */ -#undef HAVE_SETENV - -/* Define if you have the setlocale function. */ -#undef HAVE_SETLOCALE - -/* Define if you have the stpcpy function. */ -#undef HAVE_STPCPY - -/* Define if you have the strcasecmp function. */ -#undef HAVE_STRCASECMP - -/* Define if you have the strchr function. */ -#undef HAVE_STRCHR - -/* Define if you have the <argz.h> header file. */ -#undef HAVE_ARGZ_H - -/* Define if you have the <limits.h> header file. */ -#undef HAVE_LIMITS_H - -/* Define if you have the <locale.h> header file. */ -#undef HAVE_LOCALE_H - -/* Define if you have the <malloc.h> header file. */ -#undef HAVE_MALLOC_H - -/* Define if you have the <nl_types.h> header file. */ -#undef HAVE_NL_TYPES_H - -/* Define if you have the <stdlib.h> header file. */ -#undef HAVE_STDLIB_H - -/* Define if you have the <string.h> header file. */ -#undef HAVE_STRING_H - -/* Define if you have the <strings.h> header file. */ -#undef HAVE_STRINGS_H - -/* Define if you have the <sys/param.h> header file. */ -#undef HAVE_SYS_PARAM_H - -/* Define if you have the <unistd.h> header file. */ -#undef HAVE_UNISTD_H - -/* Define if you have the <values.h> header file. */ -#undef HAVE_VALUES_H - -/* Name of package */ -#undef PACKAGE - -/* Version number of package */ -#undef VERSION - -/* Define if you have the stpcpy function */ -#undef HAVE_STPCPY - -/* Define if your locale.h file contains LC_MESSAGES. */ -#undef HAVE_LC_MESSAGES - -/* Define to 1 if NLS is requested */ -#undef ENABLE_NLS - -/* Define as 1 if you have gettext and don't want to use GNU gettext. */ -#undef HAVE_GETTEXT - diff --git a/contrib/binutils/opcodes/configure b/contrib/binutils/opcodes/configure deleted file mode 100755 index 4a95a9a..0000000 --- a/contrib/binutils/opcodes/configure +++ /dev/null @@ -1,5173 +0,0 @@ -#! /bin/sh - -# Guess values for system-dependent variables and create Makefiles. -# Generated automatically using autoconf version 2.13 -# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. -# -# This configure script is free software; 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This may be overridden by the -dnl configure option --enable-shared. -AM_DISABLE_SHARED - -AM_PROG_LIBTOOL - -AC_ARG_ENABLE(targets, -[ --enable-targets alternative target configurations], -[case "${enableval}" in - yes | "") AC_ERROR(enable-targets option must specify target names or 'all') - ;; - no) enable_targets= ;; - *) enable_targets=$enableval ;; -esac])dnl -AC_ARG_ENABLE(commonbfdlib, -[ --enable-commonbfdlib build shared BFD/opcodes/libiberty library], -[case "${enableval}" in - yes) commonbfdlib=true ;; - no) commonbfdlib=false ;; - *) AC_MSG_ERROR([bad value ${enableval} for opcodes commonbfdlib option]) ;; -esac])dnl - -build_warnings="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" -AC_ARG_ENABLE(build-warnings, -[ --enable-build-warnings Enable build-time compiler warnings if gcc is used], -[case "${enableval}" in - yes) ;; - no) build_warnings="-w";; - ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` - build_warnings="${build_warnings} ${t}";; - *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` - build_warnings="${t} ${build_warnings}";; - *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;; -esac -if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then - echo "Setting warning flags = $build_warnings" 6>&1 -fi])dnl -WARN_CFLAGS="" -if test "x${build_warnings}" != x -a "x$GCC" = xyes ; then - WARN_CFLAGS="${build_warnings}" -fi -AC_SUBST(WARN_CFLAGS) - -AM_CONFIG_HEADER(config.h:config.in) - -if test -z "$target" ; then - AC_MSG_ERROR(Unrecognized target system type; please check config.sub.) -fi - -AM_MAINTAINER_MODE -AM_INSTALL_LIBBFD -AC_EXEEXT - -# host-specific stuff: - -AC_PROG_CC - -ALL_LINGUAS="fr sv tr es da de id pt_BR ro nl" -CY_GNU_GETTEXT - -. ${srcdir}/../bfd/configure.host - -BFD_CC_FOR_BUILD - -AC_SUBST(HDEFINES) -AC_PROG_INSTALL - -AC_CHECK_HEADERS(string.h strings.h stdlib.h) - -cgen_maint=no -cgendir='$(srcdir)/../cgen' - -AC_ARG_ENABLE(cgen-maint, -[ --enable-cgen-maint[=dir] build cgen generated files], -[case "${enableval}" in - yes) cgen_maint=yes ;; - no) cgen_maint=no ;; - *) - # argument is cgen install directory (not implemented yet). - # Having a `share' directory might be more appropriate for the .scm, - # .cpu, etc. files. - cgen_maint=yes - cgendir=${cgen_maint}/lib/cgen - ;; -esac])dnl -AM_CONDITIONAL(CGEN_MAINT, test x${cgen_maint} = xyes) -AC_SUBST(cgendir) - -using_cgen=no - -# Horrible hacks to build DLLs on Windows. -WIN32LDFLAGS= -WIN32LIBADD= -case "${host}" in -*-*-cygwin*) - if test "$enable_shared" = "yes"; then - WIN32LDFLAGS="-no-undefined" - WIN32LIBADD="-L`pwd`/../bfd -lbfd -L`pwd`/../libiberty -liberty -L`pwd`/../intl -lintl -lcygwin" - fi - ;; -esac -AC_SUBST(WIN32LDFLAGS) -AC_SUBST(WIN32LIBADD) - -# target-specific stuff: - -# Canonicalize the secondary target names. -if test -n "$enable_targets" ; then - for targ in `echo $enable_targets | sed 's/,/ /g'` - do - result=`$ac_config_sub $targ 2>/dev/null` - if test -n "$result" ; then - canon_targets="$canon_targets $result" - else - # Allow targets that config.sub doesn't recognize, like "all". - canon_targets="$canon_targets $targ" - fi - done -fi - -all_targets=false -selarchs= -for targ in $target $canon_targets -do - if test "x$targ" = "xall" ; then - all_targets=true - else - . $srcdir/../bfd/config.bfd - selarchs="$selarchs $targ_archs" - fi -done - -# Utility var, documents generic cgen support files. - -cgen_files="cgen-opc.lo cgen-asm.lo cgen-dis.lo" - -# We don't do any links based on the target system, just makefile config. - -if test x${all_targets} = xfalse ; then - - # Target architecture .o files. - ta= - - for arch in $selarchs - do - ad=`echo $arch | sed -e s/bfd_//g -e s/_arch//g` - archdefs="$archdefs -DARCH_$ad" - case "$arch" in - bfd_a29k_arch) ta="$ta a29k-dis.lo" ;; - bfd_alliant_arch) ;; - bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; - bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; - bfd_arm_arch) ta="$ta arm-dis.lo" ;; - bfd_avr_arch) ta="$ta avr-dis.lo" ;; - bfd_convex_arch) ;; - bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo" ;; - bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; - bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; - bfd_dlx_arch) ta="$ta dlx-dis.lo" ;; - bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;; - bfd_h8300_arch) ta="$ta h8300-dis.lo" ;; - bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; - bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; - bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;; - bfd_i386_arch) ta="$ta i386-dis.lo" ;; - bfd_i860_arch) ta="$ta i860-dis.lo" ;; - bfd_i960_arch) ta="$ta i960-dis.lo" ;; - bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; - bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; - bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; - bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; - bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; - bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; - bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; - bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; - bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; - bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; - bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; - bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; - bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; - bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; - bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; - bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; - bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; - bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; - bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; - bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; - bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; - bfd_pyramid_arch) ;; - bfd_romp_arch) ;; - bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; - bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; - bfd_sh_arch) - # We can't decide what we want just from the CPU family. - # We want SH5 support unless a specific version of sh is - # specified, as in sh3-elf, sh3b-linux-gnu, etc. - # Include it just for ELF targets, since the SH5 bfd:s are ELF only. - for t in $target $canon_targets; do - case $t in - all | sh5*-* | sh64*-* | sh-*-*elf* | shl*-*-*elf* | \ - sh-*-linux* | shl-*-linux*) - ta="$ta sh64-dis.lo sh64-opc.lo" - archdefs="$archdefs -DINCLUDE_SHMEDIA" - break;; - esac; - done - ta="$ta sh-dis.lo" ;; - bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; - bfd_tahoe_arch) ;; - bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; - bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; - bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; - bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; - bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850e_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_v850ea_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; - bfd_vax_arch) ta="$ta vax-dis.lo" ;; - bfd_w65_arch) ta="$ta w65-dis.lo" ;; - bfd_we32k_arch) ;; - bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; - bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;; - bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; - bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; - - "") ;; - *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; - esac - done - - if test $using_cgen = yes ; then - ta="$ta $cgen_files" - fi - - # Weed out duplicate .o files. - f="" - for i in $ta ; do - case " $f " in - *" $i "*) ;; - *) f="$f $i" ;; - esac - done - ta="$f" - - # And duplicate -D flags. - f="" - for i in $archdefs ; do - case " $f " in - *" $i "*) ;; - *) f="$f $i" ;; - esac - done - archdefs="$f" - - BFD_MACHINES="$ta" - -else # all_targets is true - archdefs=-DARCH_all - BFD_MACHINES='$(ALL_MACHINES)' -fi - -AC_SUBST(archdefs) -AC_SUBST(BFD_MACHINES) - -AC_OUTPUT(Makefile po/Makefile.in:po/Make-in, -[sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile]) diff --git a/contrib/binutils/opcodes/dep-in.sed b/contrib/binutils/opcodes/dep-in.sed deleted file mode 100644 index 94da2ad..0000000 --- a/contrib/binutils/opcodes/dep-in.sed +++ /dev/null @@ -1,23 +0,0 @@ -:loop -/\\$/N -s/\\\n */ /g -t loop - -s!\.o:!.lo:! -s! @BFD_H@! $(BFD_H)!g -s!@INCDIR@!$(INCDIR)!g -s!@TOPDIR@/include!$(INCDIR)!g -s!@BFDDIR@!$(BFDDIR)!g -s!@TOPDIR@/bfd!$(BFDDIR)!g -s!@SRCDIR@/!!g -s! \.\./intl/libintl\.h!!g - -s/\\\n */ /g - -s/ *$// -s/ */ /g -s/ *:/:/g -/:$/d - -s/\(.\{50\}[^ ]*\) /\1 \\\ - /g diff --git a/contrib/binutils/opcodes/dis-buf.c b/contrib/binutils/opcodes/dis-buf.c deleted file mode 100644 index 83fbfbd..0000000 --- a/contrib/binutils/opcodes/dis-buf.c +++ /dev/null @@ -1,127 +0,0 @@ -/* Disassemble from a buffer, for GNU. - Copyright 1993, 1994, 1996, 1997, 1998, 1999, 2000 - Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" -#include <errno.h> -#include "opintl.h" - -/* Get LENGTH bytes from info's buffer, at target address memaddr. - Transfer them to myaddr. */ -int -buffer_read_memory (memaddr, myaddr, length, info) - bfd_vma memaddr; - bfd_byte *myaddr; - unsigned int length; - struct disassemble_info *info; -{ - unsigned int opb = info->octets_per_byte; - unsigned int end_addr_offset = length / opb; - unsigned int max_addr_offset = info->buffer_length / opb; - unsigned int octets = (memaddr - info->buffer_vma) * opb; - - if (memaddr < info->buffer_vma - || memaddr - info->buffer_vma + end_addr_offset > max_addr_offset) - /* Out of bounds. Use EIO because GDB uses it. */ - return EIO; - memcpy (myaddr, info->buffer + octets, length); - - return 0; -} - -/* Print an error message. We can assume that this is in response to - an error return from buffer_read_memory. */ -void -perror_memory (status, memaddr, info) - int status; - bfd_vma memaddr; - struct disassemble_info *info; -{ - if (status != EIO) - /* Can't happen. */ - info->fprintf_func (info->stream, _("Unknown error %d\n"), status); - else - /* Actually, address between memaddr and memaddr + len was - out of bounds. */ - info->fprintf_func (info->stream, - _("Address 0x%x is out of bounds.\n"), memaddr); -} - -/* This could be in a separate file, to save miniscule amounts of space - in statically linked executables. */ - -/* Just print the address is hex. This is included for completeness even - though both GDB and objdump provide their own (to print symbolic - addresses). */ - -void -generic_print_address (addr, info) - bfd_vma addr; - struct disassemble_info *info; -{ - char buf[30]; - - sprintf_vma (buf, addr); - (*info->fprintf_func) (info->stream, "0x%s", buf); -} - -#if 0 -/* Just concatenate the address as hex. This is included for - completeness even though both GDB and objdump provide their own (to - print symbolic addresses). */ - -void generic_strcat_address PARAMS ((bfd_vma, char *, int)); - -void -generic_strcat_address (addr, buf, len) - bfd_vma addr; - char *buf; - int len; -{ - if (buf != (char *)NULL && len > 0) - { - char tmpBuf[30]; - - sprintf_vma (tmpBuf, addr); - if ((strlen (buf) + strlen (tmpBuf)) <= (unsigned int) len) - strcat (buf, tmpBuf); - else - strncat (buf, tmpBuf, (len - strlen(buf))); - } - return; -} -#endif - -/* Just return true. */ - -int -generic_symbol_at_address (addr, info) - bfd_vma addr ATTRIBUTE_UNUSED; - struct disassemble_info *info ATTRIBUTE_UNUSED; -{ - return 1; -} - -/* Just return TRUE. */ - -bfd_boolean -generic_symbol_is_valid (asymbol * sym ATTRIBUTE_UNUSED, - struct disassemble_info *info ATTRIBUTE_UNUSED) -{ - return TRUE; -} diff --git a/contrib/binutils/opcodes/dis-init.c b/contrib/binutils/opcodes/dis-init.c deleted file mode 100644 index 35a5ee7..0000000 --- a/contrib/binutils/opcodes/dis-init.c +++ /dev/null @@ -1,43 +0,0 @@ -/* Initialize "struct disassemble_info". - - Copyright 2003 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" -#include "bfd.h" - -void -init_disassemble_info (struct disassemble_info *info, void *stream, - fprintf_ftype fprintf_func) -{ - memset (info, 0, sizeof (*info)); - - info->flavour = bfd_target_unknown_flavour; - info->arch = bfd_arch_unknown; - info->endian = BFD_ENDIAN_UNKNOWN; - info->octets_per_byte = 1; - info->fprintf_func = fprintf_func; - info->stream = stream; - info->read_memory_func = buffer_read_memory; - info->memory_error_func = perror_memory; - info->print_address_func = generic_print_address; - info->symbol_at_address_func = generic_symbol_at_address; - info->symbol_is_valid = generic_symbol_is_valid; - info->display_endian = BFD_ENDIAN_UNKNOWN; -} - diff --git a/contrib/binutils/opcodes/disassemble.c b/contrib/binutils/opcodes/disassemble.c deleted file mode 100644 index d5b17be..0000000 --- a/contrib/binutils/opcodes/disassemble.c +++ /dev/null @@ -1,417 +0,0 @@ -/* Select disassembly routine for specified architecture. - Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 - Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" - -#ifdef ARCH_all -#define ARCH_a29k -#define ARCH_alpha -#define ARCH_arc -#define ARCH_arm -#define ARCH_avr -#define ARCH_cris -#define ARCH_d10v -#define ARCH_d30v -#define ARCH_dlx -#define ARCH_h8300 -#define ARCH_h8500 -#define ARCH_hppa -#define ARCH_i370 -#define ARCH_i386 -#define ARCH_i860 -#define ARCH_i960 -#define ARCH_ip2k -#define ARCH_ia64 -#define ARCH_fr30 -#define ARCH_m32r -#define ARCH_m68k -#define ARCH_m68hc11 -#define ARCH_m68hc12 -#define ARCH_m88k -#define ARCH_mcore -#define ARCH_mips -#define ARCH_mmix -#define ARCH_mn10200 -#define ARCH_mn10300 -#define ARCH_msp430 -#define ARCH_ns32k -#define ARCH_openrisc -#define ARCH_or32 -#define ARCH_pdp11 -#define ARCH_pj -#define ARCH_powerpc -#define ARCH_rs6000 -#define ARCH_s390 -#define ARCH_sh -#define ARCH_sparc -#define ARCH_tic30 -#define ARCH_tic4x -#define ARCH_tic54x -#define ARCH_tic80 -#define ARCH_v850 -#define ARCH_vax -#define ARCH_w65 -#define ARCH_xstormy16 -#define ARCH_xtensa -#define ARCH_z8k -#define ARCH_frv -#define ARCH_iq2000 -#define INCLUDE_SHMEDIA -#endif - - -disassembler_ftype -disassembler (abfd) - bfd *abfd; -{ - enum bfd_architecture a = bfd_get_arch (abfd); - disassembler_ftype disassemble; - - switch (a) - { - /* If you add a case to this table, also add it to the - ARCH_all definition right above this function. */ -#ifdef ARCH_a29k - case bfd_arch_a29k: - /* As far as I know we only handle big-endian 29k objects. */ - disassemble = print_insn_big_a29k; - break; -#endif -#ifdef ARCH_alpha - case bfd_arch_alpha: - disassemble = print_insn_alpha; - break; -#endif -#ifdef ARCH_arc - case bfd_arch_arc: - { - disassemble = arc_get_disassembler (abfd); - break; - } -#endif -#ifdef ARCH_arm - case bfd_arch_arm: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_arm; - else - disassemble = print_insn_little_arm; - break; -#endif -#ifdef ARCH_avr - case bfd_arch_avr: - disassemble = print_insn_avr; - break; -#endif -#ifdef ARCH_cris - case bfd_arch_cris: - disassemble = cris_get_disassembler (abfd); - break; -#endif -#ifdef ARCH_d10v - case bfd_arch_d10v: - disassemble = print_insn_d10v; - break; -#endif -#ifdef ARCH_d30v - case bfd_arch_d30v: - disassemble = print_insn_d30v; - break; -#endif -#ifdef ARCH_dlx - case bfd_arch_dlx: - /* As far as I know we only handle big-endian DLX objects. */ - disassemble = print_insn_dlx; - break; -#endif -#ifdef ARCH_h8300 - case bfd_arch_h8300: - if (bfd_get_mach (abfd) == bfd_mach_h8300h - || bfd_get_mach (abfd) == bfd_mach_h8300hn) - disassemble = print_insn_h8300h; - else if (bfd_get_mach (abfd) == bfd_mach_h8300s - || bfd_get_mach (abfd) == bfd_mach_h8300sn - || bfd_get_mach (abfd) == bfd_mach_h8300sx) - disassemble = print_insn_h8300s; - else - disassemble = print_insn_h8300; - break; -#endif -#ifdef ARCH_h8500 - case bfd_arch_h8500: - disassemble = print_insn_h8500; - break; -#endif -#ifdef ARCH_hppa - case bfd_arch_hppa: - disassemble = print_insn_hppa; - break; -#endif -#ifdef ARCH_i370 - case bfd_arch_i370: - disassemble = print_insn_i370; - break; -#endif -#ifdef ARCH_i386 - case bfd_arch_i386: - disassemble = print_insn_i386; - break; -#endif -#ifdef ARCH_i860 - case bfd_arch_i860: - disassemble = print_insn_i860; - break; -#endif -#ifdef ARCH_i960 - case bfd_arch_i960: - disassemble = print_insn_i960; - break; -#endif -#ifdef ARCH_ia64 - case bfd_arch_ia64: - disassemble = print_insn_ia64; - break; -#endif -#ifdef ARCH_ip2k - case bfd_arch_ip2k: - disassemble = print_insn_ip2k; - break; -#endif -#ifdef ARCH_fr30 - case bfd_arch_fr30: - disassemble = print_insn_fr30; - break; -#endif -#ifdef ARCH_m32r - case bfd_arch_m32r: - disassemble = print_insn_m32r; - break; -#endif -#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) - case bfd_arch_m68hc11: - disassemble = print_insn_m68hc11; - break; - case bfd_arch_m68hc12: - disassemble = print_insn_m68hc12; - break; -#endif -#ifdef ARCH_m68k - case bfd_arch_m68k: - disassemble = print_insn_m68k; - break; -#endif -#ifdef ARCH_m88k - case bfd_arch_m88k: - disassemble = print_insn_m88k; - break; -#endif -#ifdef ARCH_msp430 - case bfd_arch_msp430: - disassemble = print_insn_msp430; - break; -#endif -#ifdef ARCH_ns32k - case bfd_arch_ns32k: - disassemble = print_insn_ns32k; - break; -#endif -#ifdef ARCH_mcore - case bfd_arch_mcore: - disassemble = print_insn_mcore; - break; -#endif -#ifdef ARCH_mips - case bfd_arch_mips: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_mips; - else - disassemble = print_insn_little_mips; - break; -#endif -#ifdef ARCH_mmix - case bfd_arch_mmix: - disassemble = print_insn_mmix; - break; -#endif -#ifdef ARCH_mn10200 - case bfd_arch_mn10200: - disassemble = print_insn_mn10200; - break; -#endif -#ifdef ARCH_mn10300 - case bfd_arch_mn10300: - disassemble = print_insn_mn10300; - break; -#endif -#ifdef ARCH_openrisc - case bfd_arch_openrisc: - disassemble = print_insn_openrisc; - break; -#endif -#ifdef ARCH_or32 - case bfd_arch_or32: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_or32; - else - disassemble = print_insn_little_or32; - break; -#endif -#ifdef ARCH_pdp11 - case bfd_arch_pdp11: - disassemble = print_insn_pdp11; - break; -#endif -#ifdef ARCH_pj - case bfd_arch_pj: - disassemble = print_insn_pj; - break; -#endif -#ifdef ARCH_powerpc - case bfd_arch_powerpc: - if (bfd_big_endian (abfd)) - disassemble = print_insn_big_powerpc; - else - disassemble = print_insn_little_powerpc; - break; -#endif -#ifdef ARCH_rs6000 - case bfd_arch_rs6000: - if (bfd_get_mach (abfd) == bfd_mach_ppc_620) - disassemble = print_insn_big_powerpc; - else - disassemble = print_insn_rs6000; - break; -#endif -#ifdef ARCH_s390 - case bfd_arch_s390: - disassemble = print_insn_s390; - break; -#endif -#ifdef ARCH_sh - case bfd_arch_sh: - disassemble = print_insn_sh; - break; -#endif -#ifdef ARCH_sparc - case bfd_arch_sparc: - disassemble = print_insn_sparc; - break; -#endif -#ifdef ARCH_tic30 - case bfd_arch_tic30: - disassemble = print_insn_tic30; - break; -#endif -#ifdef ARCH_tic4x - case bfd_arch_tic4x: - disassemble = print_insn_tic4x; - break; -#endif -#ifdef ARCH_tic54x - case bfd_arch_tic54x: - disassemble = print_insn_tic54x; - break; -#endif -#ifdef ARCH_tic80 - case bfd_arch_tic80: - disassemble = print_insn_tic80; - break; -#endif -#ifdef ARCH_v850 - case bfd_arch_v850: - disassemble = print_insn_v850; - break; -#endif -#ifdef ARCH_w65 - case bfd_arch_w65: - disassemble = print_insn_w65; - break; -#endif -#ifdef ARCH_xstormy16 - case bfd_arch_xstormy16: - disassemble = print_insn_xstormy16; - break; -#endif -#ifdef ARCH_xtensa - case bfd_arch_xtensa: - disassemble = print_insn_xtensa; - break; -#endif -#ifdef ARCH_z8k - case bfd_arch_z8k: - if (bfd_get_mach(abfd) == bfd_mach_z8001) - disassemble = print_insn_z8001; - else - disassemble = print_insn_z8002; - break; -#endif -#ifdef ARCH_vax - case bfd_arch_vax: - disassemble = print_insn_vax; - break; -#endif -#ifdef ARCH_frv - case bfd_arch_frv: - disassemble = print_insn_frv; - break; -#endif -#ifdef ARCH_iq2000 - case bfd_arch_iq2000: - disassemble = print_insn_iq2000; - break; -#endif - default: - return 0; - } - return disassemble; -} - -void -disassembler_usage (stream) - FILE * stream ATTRIBUTE_UNUSED; -{ -#ifdef ARCH_arm - print_arm_disassembler_options (stream); -#endif -#ifdef ARCH_mips - print_mips_disassembler_options (stream); -#endif -#ifdef ARCH_powerpc - print_ppc_disassembler_options (stream); -#endif - - return; -} - -void -disassemble_init_for_target (struct disassemble_info * info) -{ - if (info == NULL) - return; - - switch (info->arch) - { -#ifdef ARCH_arm - case bfd_arch_arm: - info->symbol_is_valid = arm_symbol_is_valid; - break; -#endif - default: - break; - } -} diff --git a/contrib/binutils/opcodes/i386-dis.c b/contrib/binutils/opcodes/i386-dis.c deleted file mode 100644 index a71eb0c..0000000 --- a/contrib/binutils/opcodes/i386-dis.c +++ /dev/null @@ -1,4208 +0,0 @@ -/* Print i386 instructions for GDB, the GNU debugger. - Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2001, 2002, 2003, 2004 Free Software Foundation, Inc. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* - * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) - * July 1988 - * modified by John Hassey (hassey@dg-rtp.dg.com) - * x86-64 support added by Jan Hubicka (jh@suse.cz) - * VIA PadLock support by Michal Ludvig (mludvig@suse.cz) - */ - -/* - * The main tables describing the instructions is essentially a copy - * of the "Opcode Map" chapter (Appendix A) of the Intel 80386 - * Programmers Manual. Usually, there is a capital letter, followed - * by a small letter. The capital letter tell the addressing mode, - * and the small letter tells about the operand size. Refer to - * the Intel manual for details. - */ - -#include "dis-asm.h" -#include "sysdep.h" -#include "opintl.h" - -#define MAXLEN 20 - -#include <setjmp.h> - -#ifndef UNIXWARE_COMPAT -/* Set non-zero for broken, compatible instructions. Set to zero for - non-broken opcodes. */ -#define UNIXWARE_COMPAT 1 -#endif - -static int fetch_data (struct disassemble_info *, bfd_byte *); -static void ckprefix (void); -static const char *prefix_name (int, int); -static int print_insn (bfd_vma, disassemble_info *); -static void dofloat (int); -static void OP_ST (int, int); -static void OP_STi (int, int); -static int putop (const char *, int); -static void oappend (const char *); -static void append_seg (void); -static void OP_indirE (int, int); -static void print_operand_value (char *, int, bfd_vma); -static void OP_E (int, int); -static void OP_G (int, int); -static bfd_vma get64 (void); -static bfd_signed_vma get32 (void); -static bfd_signed_vma get32s (void); -static int get16 (void); -static void set_op (bfd_vma, int); -static void OP_REG (int, int); -static void OP_IMREG (int, int); -static void OP_I (int, int); -static void OP_I64 (int, int); -static void OP_sI (int, int); -static void OP_J (int, int); -static void OP_SEG (int, int); -static void OP_DIR (int, int); -static void OP_OFF (int, int); -static void OP_OFF64 (int, int); -static void ptr_reg (int, int); -static void OP_ESreg (int, int); -static void OP_DSreg (int, int); -static void OP_C (int, int); -static void OP_D (int, int); -static void OP_T (int, int); -static void OP_Rd (int, int); -static void OP_MMX (int, int); -static void OP_XMM (int, int); -static void OP_EM (int, int); -static void OP_EX (int, int); -static void OP_MS (int, int); -static void OP_XS (int, int); -static void OP_M (int, int); -static void OP_0fae (int, int); -static void OP_0f07 (int, int); -static void NOP_Fixup (int, int); -static void OP_3DNowSuffix (int, int); -static void OP_SIMD_Suffix (int, int); -static void SIMD_Fixup (int, int); -static void PNI_Fixup (int, int); -static void INVLPG_Fixup (int, int); -static void BadOp (void); - -struct dis_private { - /* Points to first byte not fetched. */ - bfd_byte *max_fetched; - bfd_byte the_buffer[MAXLEN]; - bfd_vma insn_start; - int orig_sizeflag; - jmp_buf bailout; -}; - -/* The opcode for the fwait instruction, which we treat as a prefix - when we can. */ -#define FWAIT_OPCODE (0x9b) - -/* Set to 1 for 64bit mode disassembly. */ -static int mode_64bit; - -/* Flags for the prefixes for the current instruction. See below. */ -static int prefixes; - -/* REX prefix the current instruction. See below. */ -static int rex; -/* Bits of REX we've already used. */ -static int rex_used; -#define REX_MODE64 8 -#define REX_EXTX 4 -#define REX_EXTY 2 -#define REX_EXTZ 1 -/* Mark parts used in the REX prefix. When we are testing for - empty prefix (for 8bit register REX extension), just mask it - out. Otherwise test for REX bit is excuse for existence of REX - only in case value is nonzero. */ -#define USED_REX(value) \ - { \ - if (value) \ - rex_used |= (rex & value) ? (value) | 0x40 : 0; \ - else \ - rex_used |= 0x40; \ - } - -/* Flags for prefixes which we somehow handled when printing the - current instruction. */ -static int used_prefixes; - -/* Flags stored in PREFIXES. */ -#define PREFIX_REPZ 1 -#define PREFIX_REPNZ 2 -#define PREFIX_LOCK 4 -#define PREFIX_CS 8 -#define PREFIX_SS 0x10 -#define PREFIX_DS 0x20 -#define PREFIX_ES 0x40 -#define PREFIX_FS 0x80 -#define PREFIX_GS 0x100 -#define PREFIX_DATA 0x200 -#define PREFIX_ADDR 0x400 -#define PREFIX_FWAIT 0x800 - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, addr) \ - ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (addr))) - -static int -fetch_data (struct disassemble_info *info, bfd_byte *addr) -{ - int status; - struct dis_private *priv = (struct dis_private *) info->private_data; - bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); - - status = (*info->read_memory_func) (start, - priv->max_fetched, - addr - priv->max_fetched, - info); - if (status != 0) - { - /* If we did manage to read at least one byte, then - print_insn_i386 will do something sensible. Otherwise, print - an error. We do that here because this is where we know - STATUS. */ - if (priv->max_fetched == priv->the_buffer) - (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); - } - else - priv->max_fetched = addr; - return 1; -} - -#define XX NULL, 0 - -#define Eb OP_E, b_mode -#define Ev OP_E, v_mode -#define Ed OP_E, d_mode -#define Edq OP_E, dq_mode -#define indirEb OP_indirE, b_mode -#define indirEv OP_indirE, v_mode -#define Ew OP_E, w_mode -#define Ma OP_E, v_mode -#define M OP_M, 0 /* lea, lgdt, etc. */ -#define Mp OP_M, 0 /* 32 or 48 bit memory operand for LDS, LES etc */ -#define Gb OP_G, b_mode -#define Gv OP_G, v_mode -#define Gd OP_G, d_mode -#define Gw OP_G, w_mode -#define Rd OP_Rd, d_mode -#define Rm OP_Rd, m_mode -#define Ib OP_I, b_mode -#define sIb OP_sI, b_mode /* sign extened byte */ -#define Iv OP_I, v_mode -#define Iq OP_I, q_mode -#define Iv64 OP_I64, v_mode -#define Iw OP_I, w_mode -#define Jb OP_J, b_mode -#define Jv OP_J, v_mode -#define Cm OP_C, m_mode -#define Dm OP_D, m_mode -#define Td OP_T, d_mode - -#define RMeAX OP_REG, eAX_reg -#define RMeBX OP_REG, eBX_reg -#define RMeCX OP_REG, eCX_reg -#define RMeDX OP_REG, eDX_reg -#define RMeSP OP_REG, eSP_reg -#define RMeBP OP_REG, eBP_reg -#define RMeSI OP_REG, eSI_reg -#define RMeDI OP_REG, eDI_reg -#define RMrAX OP_REG, rAX_reg -#define RMrBX OP_REG, rBX_reg -#define RMrCX OP_REG, rCX_reg -#define RMrDX OP_REG, rDX_reg -#define RMrSP OP_REG, rSP_reg -#define RMrBP OP_REG, rBP_reg -#define RMrSI OP_REG, rSI_reg -#define RMrDI OP_REG, rDI_reg -#define RMAL OP_REG, al_reg -#define RMAL OP_REG, al_reg -#define RMCL OP_REG, cl_reg -#define RMDL OP_REG, dl_reg -#define RMBL OP_REG, bl_reg -#define RMAH OP_REG, ah_reg -#define RMCH OP_REG, ch_reg -#define RMDH OP_REG, dh_reg -#define RMBH OP_REG, bh_reg -#define RMAX OP_REG, ax_reg -#define RMDX OP_REG, dx_reg - -#define eAX OP_IMREG, eAX_reg -#define eBX OP_IMREG, eBX_reg -#define eCX OP_IMREG, eCX_reg -#define eDX OP_IMREG, eDX_reg -#define eSP OP_IMREG, eSP_reg -#define eBP OP_IMREG, eBP_reg -#define eSI OP_IMREG, eSI_reg -#define eDI OP_IMREG, eDI_reg -#define AL OP_IMREG, al_reg -#define AL OP_IMREG, al_reg -#define CL OP_IMREG, cl_reg -#define DL OP_IMREG, dl_reg -#define BL OP_IMREG, bl_reg -#define AH OP_IMREG, ah_reg -#define CH OP_IMREG, ch_reg -#define DH OP_IMREG, dh_reg -#define BH OP_IMREG, bh_reg -#define AX OP_IMREG, ax_reg -#define DX OP_IMREG, dx_reg -#define indirDX OP_IMREG, indir_dx_reg - -#define Sw OP_SEG, w_mode -#define Ap OP_DIR, 0 -#define Ob OP_OFF, b_mode -#define Ob64 OP_OFF64, b_mode -#define Ov OP_OFF, v_mode -#define Ov64 OP_OFF64, v_mode -#define Xb OP_DSreg, eSI_reg -#define Xv OP_DSreg, eSI_reg -#define Yb OP_ESreg, eDI_reg -#define Yv OP_ESreg, eDI_reg -#define DSBX OP_DSreg, eBX_reg - -#define es OP_REG, es_reg -#define ss OP_REG, ss_reg -#define cs OP_REG, cs_reg -#define ds OP_REG, ds_reg -#define fs OP_REG, fs_reg -#define gs OP_REG, gs_reg - -#define MX OP_MMX, 0 -#define XM OP_XMM, 0 -#define EM OP_EM, v_mode -#define EX OP_EX, v_mode -#define MS OP_MS, v_mode -#define XS OP_XS, v_mode -#define OPSUF OP_3DNowSuffix, 0 -#define OPSIMD OP_SIMD_Suffix, 0 - -#define cond_jump_flag NULL, cond_jump_mode -#define loop_jcxz_flag NULL, loop_jcxz_mode - -/* bits in sizeflag */ -#define SUFFIX_ALWAYS 4 -#define AFLAG 2 -#define DFLAG 1 - -#define b_mode 1 /* byte operand */ -#define v_mode 2 /* operand size depends on prefixes */ -#define w_mode 3 /* word operand */ -#define d_mode 4 /* double word operand */ -#define q_mode 5 /* quad word operand */ -#define x_mode 6 -#define m_mode 7 /* d_mode in 32bit, q_mode in 64bit mode. */ -#define cond_jump_mode 8 -#define loop_jcxz_mode 9 -#define dq_mode 10 /* operand size depends on REX prefixes. */ - -#define es_reg 100 -#define cs_reg 101 -#define ss_reg 102 -#define ds_reg 103 -#define fs_reg 104 -#define gs_reg 105 - -#define eAX_reg 108 -#define eCX_reg 109 -#define eDX_reg 110 -#define eBX_reg 111 -#define eSP_reg 112 -#define eBP_reg 113 -#define eSI_reg 114 -#define eDI_reg 115 - -#define al_reg 116 -#define cl_reg 117 -#define dl_reg 118 -#define bl_reg 119 -#define ah_reg 120 -#define ch_reg 121 -#define dh_reg 122 -#define bh_reg 123 - -#define ax_reg 124 -#define cx_reg 125 -#define dx_reg 126 -#define bx_reg 127 -#define sp_reg 128 -#define bp_reg 129 -#define si_reg 130 -#define di_reg 131 - -#define rAX_reg 132 -#define rCX_reg 133 -#define rDX_reg 134 -#define rBX_reg 135 -#define rSP_reg 136 -#define rBP_reg 137 -#define rSI_reg 138 -#define rDI_reg 139 - -#define indir_dx_reg 150 - -#define FLOATCODE 1 -#define USE_GROUPS 2 -#define USE_PREFIX_USER_TABLE 3 -#define X86_64_SPECIAL 4 - -#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0 - -#define GRP1b NULL, NULL, USE_GROUPS, NULL, 0, NULL, 0 -#define GRP1S NULL, NULL, USE_GROUPS, NULL, 1, NULL, 0 -#define GRP1Ss NULL, NULL, USE_GROUPS, NULL, 2, NULL, 0 -#define GRP2b NULL, NULL, USE_GROUPS, NULL, 3, NULL, 0 -#define GRP2S NULL, NULL, USE_GROUPS, NULL, 4, NULL, 0 -#define GRP2b_one NULL, NULL, USE_GROUPS, NULL, 5, NULL, 0 -#define GRP2S_one NULL, NULL, USE_GROUPS, NULL, 6, NULL, 0 -#define GRP2b_cl NULL, NULL, USE_GROUPS, NULL, 7, NULL, 0 -#define GRP2S_cl NULL, NULL, USE_GROUPS, NULL, 8, NULL, 0 -#define GRP3b NULL, NULL, USE_GROUPS, NULL, 9, NULL, 0 -#define GRP3S NULL, NULL, USE_GROUPS, NULL, 10, NULL, 0 -#define GRP4 NULL, NULL, USE_GROUPS, NULL, 11, NULL, 0 -#define GRP5 NULL, NULL, USE_GROUPS, NULL, 12, NULL, 0 -#define GRP6 NULL, NULL, USE_GROUPS, NULL, 13, NULL, 0 -#define GRP7 NULL, NULL, USE_GROUPS, NULL, 14, NULL, 0 -#define GRP8 NULL, NULL, USE_GROUPS, NULL, 15, NULL, 0 -#define GRP9 NULL, NULL, USE_GROUPS, NULL, 16, NULL, 0 -#define GRP10 NULL, NULL, USE_GROUPS, NULL, 17, NULL, 0 -#define GRP11 NULL, NULL, USE_GROUPS, NULL, 18, NULL, 0 -#define GRP12 NULL, NULL, USE_GROUPS, NULL, 19, NULL, 0 -#define GRP13 NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0 -#define GRP14 NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0 -#define GRPAMD NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0 -#define GRPPADLCK NULL, NULL, USE_GROUPS, NULL, 23, NULL, 0 - -#define PREGRP0 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 0, NULL, 0 -#define PREGRP1 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 1, NULL, 0 -#define PREGRP2 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 2, NULL, 0 -#define PREGRP3 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 3, NULL, 0 -#define PREGRP4 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 4, NULL, 0 -#define PREGRP5 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 5, NULL, 0 -#define PREGRP6 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 6, NULL, 0 -#define PREGRP7 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 7, NULL, 0 -#define PREGRP8 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 8, NULL, 0 -#define PREGRP9 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 9, NULL, 0 -#define PREGRP10 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 10, NULL, 0 -#define PREGRP11 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 11, NULL, 0 -#define PREGRP12 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 12, NULL, 0 -#define PREGRP13 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 13, NULL, 0 -#define PREGRP14 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 14, NULL, 0 -#define PREGRP15 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 15, NULL, 0 -#define PREGRP16 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 16, NULL, 0 -#define PREGRP17 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 17, NULL, 0 -#define PREGRP18 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 18, NULL, 0 -#define PREGRP19 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 19, NULL, 0 -#define PREGRP20 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 20, NULL, 0 -#define PREGRP21 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 21, NULL, 0 -#define PREGRP22 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 22, NULL, 0 -#define PREGRP23 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 23, NULL, 0 -#define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0 -#define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0 -#define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0 -#define PREGRP27 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 27, NULL, 0 -#define PREGRP28 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 28, NULL, 0 -#define PREGRP29 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 29, NULL, 0 -#define PREGRP30 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 30, NULL, 0 -#define PREGRP31 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 31, NULL, 0 -#define PREGRP32 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 32, NULL, 0 - -#define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0 - -typedef void (*op_rtn) (int bytemode, int sizeflag); - -struct dis386 { - const char *name; - op_rtn op1; - int bytemode1; - op_rtn op2; - int bytemode2; - op_rtn op3; - int bytemode3; -}; - -/* Upper case letters in the instruction names here are macros. - 'A' => print 'b' if no register operands or suffix_always is true - 'B' => print 'b' if suffix_always is true - 'E' => print 'e' if 32-bit form of jcxz - 'F' => print 'w' or 'l' depending on address size prefix (loop insns) - 'H' => print ",pt" or ",pn" branch hint - 'L' => print 'l' if suffix_always is true - 'N' => print 'n' if instruction has no wait "prefix" - 'O' => print 'd', or 'o' - 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, - . or suffix_always is true. print 'q' if rex prefix is present. - 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always - . is true - 'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode) - 'S' => print 'w', 'l' or 'q' if suffix_always is true - 'T' => print 'q' in 64bit mode and behave as 'P' otherwise - 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise - 'X' => print 's', 'd' depending on data16 prefix (for XMM) - 'W' => print 'b' or 'w' ("w" or "de" in intel mode) - 'Y' => 'q' if instruction has an REX 64bit overwrite prefix - - Many of the above letters print nothing in Intel mode. See "putop" - for the details. - - Braces '{' and '}', and vertical bars '|', indicate alternative - mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel - modes. In cases where there are only two alternatives, the X86_64 - instruction is reserved, and "(bad)" is printed. -*/ - -static const struct dis386 dis386[] = { - /* 00 */ - { "addB", Eb, Gb, XX }, - { "addS", Ev, Gv, XX }, - { "addB", Gb, Eb, XX }, - { "addS", Gv, Ev, XX }, - { "addB", AL, Ib, XX }, - { "addS", eAX, Iv, XX }, - { "push{T|}", es, XX, XX }, - { "pop{T|}", es, XX, XX }, - /* 08 */ - { "orB", Eb, Gb, XX }, - { "orS", Ev, Gv, XX }, - { "orB", Gb, Eb, XX }, - { "orS", Gv, Ev, XX }, - { "orB", AL, Ib, XX }, - { "orS", eAX, Iv, XX }, - { "push{T|}", cs, XX, XX }, - { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */ - /* 10 */ - { "adcB", Eb, Gb, XX }, - { "adcS", Ev, Gv, XX }, - { "adcB", Gb, Eb, XX }, - { "adcS", Gv, Ev, XX }, - { "adcB", AL, Ib, XX }, - { "adcS", eAX, Iv, XX }, - { "push{T|}", ss, XX, XX }, - { "popT|}", ss, XX, XX }, - /* 18 */ - { "sbbB", Eb, Gb, XX }, - { "sbbS", Ev, Gv, XX }, - { "sbbB", Gb, Eb, XX }, - { "sbbS", Gv, Ev, XX }, - { "sbbB", AL, Ib, XX }, - { "sbbS", eAX, Iv, XX }, - { "push{T|}", ds, XX, XX }, - { "pop{T|}", ds, XX, XX }, - /* 20 */ - { "andB", Eb, Gb, XX }, - { "andS", Ev, Gv, XX }, - { "andB", Gb, Eb, XX }, - { "andS", Gv, Ev, XX }, - { "andB", AL, Ib, XX }, - { "andS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG ES prefix */ - { "daa{|}", XX, XX, XX }, - /* 28 */ - { "subB", Eb, Gb, XX }, - { "subS", Ev, Gv, XX }, - { "subB", Gb, Eb, XX }, - { "subS", Gv, Ev, XX }, - { "subB", AL, Ib, XX }, - { "subS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG CS prefix */ - { "das{|}", XX, XX, XX }, - /* 30 */ - { "xorB", Eb, Gb, XX }, - { "xorS", Ev, Gv, XX }, - { "xorB", Gb, Eb, XX }, - { "xorS", Gv, Ev, XX }, - { "xorB", AL, Ib, XX }, - { "xorS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG SS prefix */ - { "aaa{|}", XX, XX, XX }, - /* 38 */ - { "cmpB", Eb, Gb, XX }, - { "cmpS", Ev, Gv, XX }, - { "cmpB", Gb, Eb, XX }, - { "cmpS", Gv, Ev, XX }, - { "cmpB", AL, Ib, XX }, - { "cmpS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG DS prefix */ - { "aas{|}", XX, XX, XX }, - /* 40 */ - { "inc{S|}", RMeAX, XX, XX }, - { "inc{S|}", RMeCX, XX, XX }, - { "inc{S|}", RMeDX, XX, XX }, - { "inc{S|}", RMeBX, XX, XX }, - { "inc{S|}", RMeSP, XX, XX }, - { "inc{S|}", RMeBP, XX, XX }, - { "inc{S|}", RMeSI, XX, XX }, - { "inc{S|}", RMeDI, XX, XX }, - /* 48 */ - { "dec{S|}", RMeAX, XX, XX }, - { "dec{S|}", RMeCX, XX, XX }, - { "dec{S|}", RMeDX, XX, XX }, - { "dec{S|}", RMeBX, XX, XX }, - { "dec{S|}", RMeSP, XX, XX }, - { "dec{S|}", RMeBP, XX, XX }, - { "dec{S|}", RMeSI, XX, XX }, - { "dec{S|}", RMeDI, XX, XX }, - /* 50 */ - { "pushS", RMrAX, XX, XX }, - { "pushS", RMrCX, XX, XX }, - { "pushS", RMrDX, XX, XX }, - { "pushS", RMrBX, XX, XX }, - { "pushS", RMrSP, XX, XX }, - { "pushS", RMrBP, XX, XX }, - { "pushS", RMrSI, XX, XX }, - { "pushS", RMrDI, XX, XX }, - /* 58 */ - { "popS", RMrAX, XX, XX }, - { "popS", RMrCX, XX, XX }, - { "popS", RMrDX, XX, XX }, - { "popS", RMrBX, XX, XX }, - { "popS", RMrSP, XX, XX }, - { "popS", RMrBP, XX, XX }, - { "popS", RMrSI, XX, XX }, - { "popS", RMrDI, XX, XX }, - /* 60 */ - { "pusha{P|}", XX, XX, XX }, - { "popa{P|}", XX, XX, XX }, - { "bound{S|}", Gv, Ma, XX }, - { X86_64_0 }, - { "(bad)", XX, XX, XX }, /* seg fs */ - { "(bad)", XX, XX, XX }, /* seg gs */ - { "(bad)", XX, XX, XX }, /* op size prefix */ - { "(bad)", XX, XX, XX }, /* adr size prefix */ - /* 68 */ - { "pushT", Iq, XX, XX }, - { "imulS", Gv, Ev, Iv }, - { "pushT", sIb, XX, XX }, - { "imulS", Gv, Ev, sIb }, - { "ins{b||b|}", Yb, indirDX, XX }, - { "ins{R||R|}", Yv, indirDX, XX }, - { "outs{b||b|}", indirDX, Xb, XX }, - { "outs{R||R|}", indirDX, Xv, XX }, - /* 70 */ - { "joH", Jb, XX, cond_jump_flag }, - { "jnoH", Jb, XX, cond_jump_flag }, - { "jbH", Jb, XX, cond_jump_flag }, - { "jaeH", Jb, XX, cond_jump_flag }, - { "jeH", Jb, XX, cond_jump_flag }, - { "jneH", Jb, XX, cond_jump_flag }, - { "jbeH", Jb, XX, cond_jump_flag }, - { "jaH", Jb, XX, cond_jump_flag }, - /* 78 */ - { "jsH", Jb, XX, cond_jump_flag }, - { "jnsH", Jb, XX, cond_jump_flag }, - { "jpH", Jb, XX, cond_jump_flag }, - { "jnpH", Jb, XX, cond_jump_flag }, - { "jlH", Jb, XX, cond_jump_flag }, - { "jgeH", Jb, XX, cond_jump_flag }, - { "jleH", Jb, XX, cond_jump_flag }, - { "jgH", Jb, XX, cond_jump_flag }, - /* 80 */ - { GRP1b }, - { GRP1S }, - { "(bad)", XX, XX, XX }, - { GRP1Ss }, - { "testB", Eb, Gb, XX }, - { "testS", Ev, Gv, XX }, - { "xchgB", Eb, Gb, XX }, - { "xchgS", Ev, Gv, XX }, - /* 88 */ - { "movB", Eb, Gb, XX }, - { "movS", Ev, Gv, XX }, - { "movB", Gb, Eb, XX }, - { "movS", Gv, Ev, XX }, - { "movQ", Ev, Sw, XX }, - { "leaS", Gv, M, XX }, - { "movQ", Sw, Ev, XX }, - { "popU", Ev, XX, XX }, - /* 90 */ - { "nop", NOP_Fixup, 0, XX, XX }, - { "xchgS", RMeCX, eAX, XX }, - { "xchgS", RMeDX, eAX, XX }, - { "xchgS", RMeBX, eAX, XX }, - { "xchgS", RMeSP, eAX, XX }, - { "xchgS", RMeBP, eAX, XX }, - { "xchgS", RMeSI, eAX, XX }, - { "xchgS", RMeDI, eAX, XX }, - /* 98 */ - { "cW{tR||tR|}", XX, XX, XX }, - { "cR{tO||tO|}", XX, XX, XX }, - { "lcall{T|}", Ap, XX, XX }, - { "(bad)", XX, XX, XX }, /* fwait */ - { "pushfT", XX, XX, XX }, - { "popfT", XX, XX, XX }, - { "sahf{|}", XX, XX, XX }, - { "lahf{|}", XX, XX, XX }, - /* a0 */ - { "movB", AL, Ob64, XX }, - { "movS", eAX, Ov64, XX }, - { "movB", Ob64, AL, XX }, - { "movS", Ov64, eAX, XX }, - { "movs{b||b|}", Yb, Xb, XX }, - { "movs{R||R|}", Yv, Xv, XX }, - { "cmps{b||b|}", Xb, Yb, XX }, - { "cmps{R||R|}", Xv, Yv, XX }, - /* a8 */ - { "testB", AL, Ib, XX }, - { "testS", eAX, Iv, XX }, - { "stosB", Yb, AL, XX }, - { "stosS", Yv, eAX, XX }, - { "lodsB", AL, Xb, XX }, - { "lodsS", eAX, Xv, XX }, - { "scasB", AL, Yb, XX }, - { "scasS", eAX, Yv, XX }, - /* b0 */ - { "movB", RMAL, Ib, XX }, - { "movB", RMCL, Ib, XX }, - { "movB", RMDL, Ib, XX }, - { "movB", RMBL, Ib, XX }, - { "movB", RMAH, Ib, XX }, - { "movB", RMCH, Ib, XX }, - { "movB", RMDH, Ib, XX }, - { "movB", RMBH, Ib, XX }, - /* b8 */ - { "movS", RMeAX, Iv64, XX }, - { "movS", RMeCX, Iv64, XX }, - { "movS", RMeDX, Iv64, XX }, - { "movS", RMeBX, Iv64, XX }, - { "movS", RMeSP, Iv64, XX }, - { "movS", RMeBP, Iv64, XX }, - { "movS", RMeSI, Iv64, XX }, - { "movS", RMeDI, Iv64, XX }, - /* c0 */ - { GRP2b }, - { GRP2S }, - { "retT", Iw, XX, XX }, - { "retT", XX, XX, XX }, - { "les{S|}", Gv, Mp, XX }, - { "ldsS", Gv, Mp, XX }, - { "movA", Eb, Ib, XX }, - { "movQ", Ev, Iv, XX }, - /* c8 */ - { "enterT", Iw, Ib, XX }, - { "leaveT", XX, XX, XX }, - { "lretP", Iw, XX, XX }, - { "lretP", XX, XX, XX }, - { "int3", XX, XX, XX }, - { "int", Ib, XX, XX }, - { "into{|}", XX, XX, XX }, - { "iretP", XX, XX, XX }, - /* d0 */ - { GRP2b_one }, - { GRP2S_one }, - { GRP2b_cl }, - { GRP2S_cl }, - { "aam{|}", sIb, XX, XX }, - { "aad{|}", sIb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "xlat", DSBX, XX, XX }, - /* d8 */ - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - { FLOAT }, - /* e0 */ - { "loopneFH", Jb, XX, loop_jcxz_flag }, - { "loopeFH", Jb, XX, loop_jcxz_flag }, - { "loopFH", Jb, XX, loop_jcxz_flag }, - { "jEcxzH", Jb, XX, loop_jcxz_flag }, - { "inB", AL, Ib, XX }, - { "inS", eAX, Ib, XX }, - { "outB", Ib, AL, XX }, - { "outS", Ib, eAX, XX }, - /* e8 */ - { "callT", Jv, XX, XX }, - { "jmpT", Jv, XX, XX }, - { "ljmp{T|}", Ap, XX, XX }, - { "jmp", Jb, XX, XX }, - { "inB", AL, indirDX, XX }, - { "inS", eAX, indirDX, XX }, - { "outB", indirDX, AL, XX }, - { "outS", indirDX, eAX, XX }, - /* f0 */ - { "(bad)", XX, XX, XX }, /* lock prefix */ - { "icebp", XX, XX, XX }, - { "(bad)", XX, XX, XX }, /* repne */ - { "(bad)", XX, XX, XX }, /* repz */ - { "hlt", XX, XX, XX }, - { "cmc", XX, XX, XX }, - { GRP3b }, - { GRP3S }, - /* f8 */ - { "clc", XX, XX, XX }, - { "stc", XX, XX, XX }, - { "cli", XX, XX, XX }, - { "sti", XX, XX, XX }, - { "cld", XX, XX, XX }, - { "std", XX, XX, XX }, - { GRP4 }, - { GRP5 }, -}; - -static const struct dis386 dis386_twobyte[] = { - /* 00 */ - { GRP6 }, - { GRP7 }, - { "larS", Gv, Ew, XX }, - { "lslS", Gv, Ew, XX }, - { "(bad)", XX, XX, XX }, - { "syscall", XX, XX, XX }, - { "clts", XX, XX, XX }, - { "sysretP", XX, XX, XX }, - /* 08 */ - { "invd", XX, XX, XX }, - { "wbinvd", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "ud2a", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { GRPAMD }, - { "femms", XX, XX, XX }, - { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix. */ - /* 10 */ - { PREGRP8 }, - { PREGRP9 }, - { PREGRP30 }, - { "movlpX", EX, XM, SIMD_Fixup, 'h' }, - { "unpcklpX", XM, EX, XX }, - { "unpckhpX", XM, EX, XX }, - { PREGRP31 }, - { "movhpX", EX, XM, SIMD_Fixup, 'l' }, - /* 18 */ - { GRP14 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 20 */ - { "movL", Rm, Cm, XX }, - { "movL", Rm, Dm, XX }, - { "movL", Cm, Rm, XX }, - { "movL", Dm, Rm, XX }, - { "movL", Rd, Td, XX }, - { "(bad)", XX, XX, XX }, - { "movL", Td, Rd, XX }, - { "(bad)", XX, XX, XX }, - /* 28 */ - { "movapX", XM, EX, XX }, - { "movapX", EX, XM, XX }, - { PREGRP2 }, - { "movntpX", Ev, XM, XX }, - { PREGRP4 }, - { PREGRP3 }, - { "ucomisX", XM,EX, XX }, - { "comisX", XM,EX, XX }, - /* 30 */ - { "wrmsr", XX, XX, XX }, - { "rdtsc", XX, XX, XX }, - { "rdmsr", XX, XX, XX }, - { "rdpmc", XX, XX, XX }, - { "sysenter", XX, XX, XX }, - { "sysexit", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 38 */ - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - /* 40 */ - { "cmovo", Gv, Ev, XX }, - { "cmovno", Gv, Ev, XX }, - { "cmovb", Gv, Ev, XX }, - { "cmovae", Gv, Ev, XX }, - { "cmove", Gv, Ev, XX }, - { "cmovne", Gv, Ev, XX }, - { "cmovbe", Gv, Ev, XX }, - { "cmova", Gv, Ev, XX }, - /* 48 */ - { "cmovs", Gv, Ev, XX }, - { "cmovns", Gv, Ev, XX }, - { "cmovp", Gv, Ev, XX }, - { "cmovnp", Gv, Ev, XX }, - { "cmovl", Gv, Ev, XX }, - { "cmovge", Gv, Ev, XX }, - { "cmovle", Gv, Ev, XX }, - { "cmovg", Gv, Ev, XX }, - /* 50 */ - { "movmskpX", Gd, XS, XX }, - { PREGRP13 }, - { PREGRP12 }, - { PREGRP11 }, - { "andpX", XM, EX, XX }, - { "andnpX", XM, EX, XX }, - { "orpX", XM, EX, XX }, - { "xorpX", XM, EX, XX }, - /* 58 */ - { PREGRP0 }, - { PREGRP10 }, - { PREGRP17 }, - { PREGRP16 }, - { PREGRP14 }, - { PREGRP7 }, - { PREGRP5 }, - { PREGRP6 }, - /* 60 */ - { "punpcklbw", MX, EM, XX }, - { "punpcklwd", MX, EM, XX }, - { "punpckldq", MX, EM, XX }, - { "packsswb", MX, EM, XX }, - { "pcmpgtb", MX, EM, XX }, - { "pcmpgtw", MX, EM, XX }, - { "pcmpgtd", MX, EM, XX }, - { "packuswb", MX, EM, XX }, - /* 68 */ - { "punpckhbw", MX, EM, XX }, - { "punpckhwd", MX, EM, XX }, - { "punpckhdq", MX, EM, XX }, - { "packssdw", MX, EM, XX }, - { PREGRP26 }, - { PREGRP24 }, - { "movd", MX, Edq, XX }, - { PREGRP19 }, - /* 70 */ - { PREGRP22 }, - { GRP10 }, - { GRP11 }, - { GRP12 }, - { "pcmpeqb", MX, EM, XX }, - { "pcmpeqw", MX, EM, XX }, - { "pcmpeqd", MX, EM, XX }, - { "emms", XX, XX, XX }, - /* 78 */ - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { PREGRP28 }, - { PREGRP29 }, - { PREGRP23 }, - { PREGRP20 }, - /* 80 */ - { "joH", Jv, XX, cond_jump_flag }, - { "jnoH", Jv, XX, cond_jump_flag }, - { "jbH", Jv, XX, cond_jump_flag }, - { "jaeH", Jv, XX, cond_jump_flag }, - { "jeH", Jv, XX, cond_jump_flag }, - { "jneH", Jv, XX, cond_jump_flag }, - { "jbeH", Jv, XX, cond_jump_flag }, - { "jaH", Jv, XX, cond_jump_flag }, - /* 88 */ - { "jsH", Jv, XX, cond_jump_flag }, - { "jnsH", Jv, XX, cond_jump_flag }, - { "jpH", Jv, XX, cond_jump_flag }, - { "jnpH", Jv, XX, cond_jump_flag }, - { "jlH", Jv, XX, cond_jump_flag }, - { "jgeH", Jv, XX, cond_jump_flag }, - { "jleH", Jv, XX, cond_jump_flag }, - { "jgH", Jv, XX, cond_jump_flag }, - /* 90 */ - { "seto", Eb, XX, XX }, - { "setno", Eb, XX, XX }, - { "setb", Eb, XX, XX }, - { "setae", Eb, XX, XX }, - { "sete", Eb, XX, XX }, - { "setne", Eb, XX, XX }, - { "setbe", Eb, XX, XX }, - { "seta", Eb, XX, XX }, - /* 98 */ - { "sets", Eb, XX, XX }, - { "setns", Eb, XX, XX }, - { "setp", Eb, XX, XX }, - { "setnp", Eb, XX, XX }, - { "setl", Eb, XX, XX }, - { "setge", Eb, XX, XX }, - { "setle", Eb, XX, XX }, - { "setg", Eb, XX, XX }, - /* a0 */ - { "pushT", fs, XX, XX }, - { "popT", fs, XX, XX }, - { "cpuid", XX, XX, XX }, - { "btS", Ev, Gv, XX }, - { "shldS", Ev, Gv, Ib }, - { "shldS", Ev, Gv, CL }, - { "(bad)", XX, XX, XX }, - { GRPPADLCK }, - /* a8 */ - { "pushT", gs, XX, XX }, - { "popT", gs, XX, XX }, - { "rsm", XX, XX, XX }, - { "btsS", Ev, Gv, XX }, - { "shrdS", Ev, Gv, Ib }, - { "shrdS", Ev, Gv, CL }, - { GRP13 }, - { "imulS", Gv, Ev, XX }, - /* b0 */ - { "cmpxchgB", Eb, Gb, XX }, - { "cmpxchgS", Ev, Gv, XX }, - { "lssS", Gv, Mp, XX }, - { "btrS", Ev, Gv, XX }, - { "lfsS", Gv, Mp, XX }, - { "lgsS", Gv, Mp, XX }, - { "movz{bR|x|bR|x}", Gv, Eb, XX }, - { "movz{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movzww ! */ - /* b8 */ - { "(bad)", XX, XX, XX }, - { "ud2b", XX, XX, XX }, - { GRP8 }, - { "btcS", Ev, Gv, XX }, - { "bsfS", Gv, Ev, XX }, - { "bsrS", Gv, Ev, XX }, - { "movs{bR|x|bR|x}", Gv, Eb, XX }, - { "movs{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movsww ! */ - /* c0 */ - { "xaddB", Eb, Gb, XX }, - { "xaddS", Ev, Gv, XX }, - { PREGRP1 }, - { "movntiS", Ev, Gv, XX }, - { "pinsrw", MX, Ed, Ib }, - { "pextrw", Gd, MS, Ib }, - { "shufpX", XM, EX, Ib }, - { GRP9 }, - /* c8 */ - { "bswap", RMeAX, XX, XX }, - { "bswap", RMeCX, XX, XX }, - { "bswap", RMeDX, XX, XX }, - { "bswap", RMeBX, XX, XX }, - { "bswap", RMeSP, XX, XX }, - { "bswap", RMeBP, XX, XX }, - { "bswap", RMeSI, XX, XX }, - { "bswap", RMeDI, XX, XX }, - /* d0 */ - { PREGRP27 }, - { "psrlw", MX, EM, XX }, - { "psrld", MX, EM, XX }, - { "psrlq", MX, EM, XX }, - { "paddq", MX, EM, XX }, - { "pmullw", MX, EM, XX }, - { PREGRP21 }, - { "pmovmskb", Gd, MS, XX }, - /* d8 */ - { "psubusb", MX, EM, XX }, - { "psubusw", MX, EM, XX }, - { "pminub", MX, EM, XX }, - { "pand", MX, EM, XX }, - { "paddusb", MX, EM, XX }, - { "paddusw", MX, EM, XX }, - { "pmaxub", MX, EM, XX }, - { "pandn", MX, EM, XX }, - /* e0 */ - { "pavgb", MX, EM, XX }, - { "psraw", MX, EM, XX }, - { "psrad", MX, EM, XX }, - { "pavgw", MX, EM, XX }, - { "pmulhuw", MX, EM, XX }, - { "pmulhw", MX, EM, XX }, - { PREGRP15 }, - { PREGRP25 }, - /* e8 */ - { "psubsb", MX, EM, XX }, - { "psubsw", MX, EM, XX }, - { "pminsw", MX, EM, XX }, - { "por", MX, EM, XX }, - { "paddsb", MX, EM, XX }, - { "paddsw", MX, EM, XX }, - { "pmaxsw", MX, EM, XX }, - { "pxor", MX, EM, XX }, - /* f0 */ - { PREGRP32 }, - { "psllw", MX, EM, XX }, - { "pslld", MX, EM, XX }, - { "psllq", MX, EM, XX }, - { "pmuludq", MX, EM, XX }, - { "pmaddwd", MX, EM, XX }, - { "psadbw", MX, EM, XX }, - { PREGRP18 }, - /* f8 */ - { "psubb", MX, EM, XX }, - { "psubw", MX, EM, XX }, - { "psubd", MX, EM, XX }, - { "psubq", MX, EM, XX }, - { "paddb", MX, EM, XX }, - { "paddw", MX, EM, XX }, - { "paddd", MX, EM, XX }, - { "(bad)", XX, XX, XX } -}; - -static const unsigned char onebyte_has_modrm[256] = { - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ - /* ------------------------------- */ - /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ - /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ - /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ - /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ - /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ - /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ - /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ - /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ - /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ - /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ - /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ - /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ - /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ - /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ - /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ - /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ - /* ------------------------------- */ - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ -}; - -static const unsigned char twobyte_has_modrm[256] = { - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ - /* ------------------------------- */ - /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ - /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 1f */ - /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */ - /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ - /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ - /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ - /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ - /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1, /* 7f */ - /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ - /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ - /* a0 */ 0,0,0,1,1,1,0,1,0,0,0,1,1,1,1,1, /* af */ - /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */ - /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ - /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ - /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ - /* ------------------------------- */ - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ -}; - -static const unsigned char twobyte_uses_SSE_prefix[256] = { - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ - /* ------------------------------- */ - /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ - /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */ - /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */ - /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ - /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ - /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */ - /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */ - /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1, /* 7f */ - /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ - /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ - /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ - /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ - /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */ - /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 1,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */ - /* ------------------------------- */ - /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ -}; - -static char obuf[100]; -static char *obufp; -static char scratchbuf[100]; -static unsigned char *start_codep; -static unsigned char *insn_codep; -static unsigned char *codep; -static disassemble_info *the_info; -static int mod; -static int rm; -static int reg; -static unsigned char need_modrm; - -/* If we are accessing mod/rm/reg without need_modrm set, then the - values are stale. Hitting this abort likely indicates that you - need to update onebyte_has_modrm or twobyte_has_modrm. */ -#define MODRM_CHECK if (!need_modrm) abort () - -static const char **names64; -static const char **names32; -static const char **names16; -static const char **names8; -static const char **names8rex; -static const char **names_seg; -static const char **index16; - -static const char *intel_names64[] = { - "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" -}; -static const char *intel_names32[] = { - "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", - "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" -}; -static const char *intel_names16[] = { - "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", - "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" -}; -static const char *intel_names8[] = { - "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", -}; -static const char *intel_names8rex[] = { - "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", - "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" -}; -static const char *intel_names_seg[] = { - "es", "cs", "ss", "ds", "fs", "gs", "?", "?", -}; -static const char *intel_index16[] = { - "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" -}; - -static const char *att_names64[] = { - "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", - "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" -}; -static const char *att_names32[] = { - "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", - "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" -}; -static const char *att_names16[] = { - "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", - "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" -}; -static const char *att_names8[] = { - "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", -}; -static const char *att_names8rex[] = { - "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", - "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" -}; -static const char *att_names_seg[] = { - "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", -}; -static const char *att_index16[] = { - "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" -}; - -static const struct dis386 grps[][8] = { - /* GRP1b */ - { - { "addA", Eb, Ib, XX }, - { "orA", Eb, Ib, XX }, - { "adcA", Eb, Ib, XX }, - { "sbbA", Eb, Ib, XX }, - { "andA", Eb, Ib, XX }, - { "subA", Eb, Ib, XX }, - { "xorA", Eb, Ib, XX }, - { "cmpA", Eb, Ib, XX } - }, - /* GRP1S */ - { - { "addQ", Ev, Iv, XX }, - { "orQ", Ev, Iv, XX }, - { "adcQ", Ev, Iv, XX }, - { "sbbQ", Ev, Iv, XX }, - { "andQ", Ev, Iv, XX }, - { "subQ", Ev, Iv, XX }, - { "xorQ", Ev, Iv, XX }, - { "cmpQ", Ev, Iv, XX } - }, - /* GRP1Ss */ - { - { "addQ", Ev, sIb, XX }, - { "orQ", Ev, sIb, XX }, - { "adcQ", Ev, sIb, XX }, - { "sbbQ", Ev, sIb, XX }, - { "andQ", Ev, sIb, XX }, - { "subQ", Ev, sIb, XX }, - { "xorQ", Ev, sIb, XX }, - { "cmpQ", Ev, sIb, XX } - }, - /* GRP2b */ - { - { "rolA", Eb, Ib, XX }, - { "rorA", Eb, Ib, XX }, - { "rclA", Eb, Ib, XX }, - { "rcrA", Eb, Ib, XX }, - { "shlA", Eb, Ib, XX }, - { "shrA", Eb, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "sarA", Eb, Ib, XX }, - }, - /* GRP2S */ - { - { "rolQ", Ev, Ib, XX }, - { "rorQ", Ev, Ib, XX }, - { "rclQ", Ev, Ib, XX }, - { "rcrQ", Ev, Ib, XX }, - { "shlQ", Ev, Ib, XX }, - { "shrQ", Ev, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "sarQ", Ev, Ib, XX }, - }, - /* GRP2b_one */ - { - { "rolA", Eb, XX, XX }, - { "rorA", Eb, XX, XX }, - { "rclA", Eb, XX, XX }, - { "rcrA", Eb, XX, XX }, - { "shlA", Eb, XX, XX }, - { "shrA", Eb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "sarA", Eb, XX, XX }, - }, - /* GRP2S_one */ - { - { "rolQ", Ev, XX, XX }, - { "rorQ", Ev, XX, XX }, - { "rclQ", Ev, XX, XX }, - { "rcrQ", Ev, XX, XX }, - { "shlQ", Ev, XX, XX }, - { "shrQ", Ev, XX, XX }, - { "(bad)", XX, XX, XX}, - { "sarQ", Ev, XX, XX }, - }, - /* GRP2b_cl */ - { - { "rolA", Eb, CL, XX }, - { "rorA", Eb, CL, XX }, - { "rclA", Eb, CL, XX }, - { "rcrA", Eb, CL, XX }, - { "shlA", Eb, CL, XX }, - { "shrA", Eb, CL, XX }, - { "(bad)", XX, XX, XX }, - { "sarA", Eb, CL, XX }, - }, - /* GRP2S_cl */ - { - { "rolQ", Ev, CL, XX }, - { "rorQ", Ev, CL, XX }, - { "rclQ", Ev, CL, XX }, - { "rcrQ", Ev, CL, XX }, - { "shlQ", Ev, CL, XX }, - { "shrQ", Ev, CL, XX }, - { "(bad)", XX, XX, XX }, - { "sarQ", Ev, CL, XX } - }, - /* GRP3b */ - { - { "testA", Eb, Ib, XX }, - { "(bad)", Eb, XX, XX }, - { "notA", Eb, XX, XX }, - { "negA", Eb, XX, XX }, - { "mulA", Eb, XX, XX }, /* Don't print the implicit %al register, */ - { "imulA", Eb, XX, XX }, /* to distinguish these opcodes from other */ - { "divA", Eb, XX, XX }, /* mul/imul opcodes. Do the same for div */ - { "idivA", Eb, XX, XX } /* and idiv for consistency. */ - }, - /* GRP3S */ - { - { "testQ", Ev, Iv, XX }, - { "(bad)", XX, XX, XX }, - { "notQ", Ev, XX, XX }, - { "negQ", Ev, XX, XX }, - { "mulQ", Ev, XX, XX }, /* Don't print the implicit register. */ - { "imulQ", Ev, XX, XX }, - { "divQ", Ev, XX, XX }, - { "idivQ", Ev, XX, XX }, - }, - /* GRP4 */ - { - { "incA", Eb, XX, XX }, - { "decA", Eb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP5 */ - { - { "incQ", Ev, XX, XX }, - { "decQ", Ev, XX, XX }, - { "callT", indirEv, XX, XX }, - { "lcallT", indirEv, XX, XX }, - { "jmpT", indirEv, XX, XX }, - { "ljmpT", indirEv, XX, XX }, - { "pushU", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP6 */ - { - { "sldtQ", Ev, XX, XX }, - { "strQ", Ev, XX, XX }, - { "lldt", Ew, XX, XX }, - { "ltr", Ew, XX, XX }, - { "verr", Ew, XX, XX }, - { "verw", Ew, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX } - }, - /* GRP7 */ - { - { "sgdtQ", M, XX, XX }, - { "sidtQ", PNI_Fixup, 0, XX, XX }, - { "lgdtQ", M, XX, XX }, - { "lidtQ", M, XX, XX }, - { "smswQ", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "lmsw", Ew, XX, XX }, - { "invlpg", INVLPG_Fixup, w_mode, XX, XX }, - }, - /* GRP8 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "btQ", Ev, Ib, XX }, - { "btsQ", Ev, Ib, XX }, - { "btrQ", Ev, Ib, XX }, - { "btcQ", Ev, Ib, XX }, - }, - /* GRP9 */ - { - { "(bad)", XX, XX, XX }, - { "cmpxchg8b", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP10 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psrlw", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "psraw", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "psllw", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP11 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psrld", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "psrad", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "pslld", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP12 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psrlq", MS, Ib, XX }, - { "psrldq", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psllq", MS, Ib, XX }, - { "pslldq", MS, Ib, XX }, - }, - /* GRP13 */ - { - { "fxsave", Ev, XX, XX }, - { "fxrstor", Ev, XX, XX }, - { "ldmxcsr", Ev, XX, XX }, - { "stmxcsr", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "lfence", OP_0fae, 0, XX, XX }, - { "mfence", OP_0fae, 0, XX, XX }, - { "clflush", OP_0fae, 0, XX, XX }, - }, - /* GRP14 */ - { - { "prefetchnta", Ev, XX, XX }, - { "prefetcht0", Ev, XX, XX }, - { "prefetcht1", Ev, XX, XX }, - { "prefetcht2", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRPAMD */ - { - { "prefetch", Eb, XX, XX }, - { "prefetchw", Eb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRPPADLCK */ - { - { "xstorerng", OP_0f07, 0, XX, XX }, - { "xcryptecb", OP_0f07, 0, XX, XX }, - { "xcryptcbc", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, - { "xcryptcfb", OP_0f07, 0, XX, XX }, - { "xcryptofb", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, - } -}; - -static const struct dis386 prefix_user_table[][4] = { - /* PREGRP0 */ - { - { "addps", XM, EX, XX }, - { "addss", XM, EX, XX }, - { "addpd", XM, EX, XX }, - { "addsd", XM, EX, XX }, - }, - /* PREGRP1 */ - { - { "", XM, EX, OPSIMD }, /* See OP_SIMD_SUFFIX. */ - { "", XM, EX, OPSIMD }, - { "", XM, EX, OPSIMD }, - { "", XM, EX, OPSIMD }, - }, - /* PREGRP2 */ - { - { "cvtpi2ps", XM, EM, XX }, - { "cvtsi2ssY", XM, Ev, XX }, - { "cvtpi2pd", XM, EM, XX }, - { "cvtsi2sdY", XM, Ev, XX }, - }, - /* PREGRP3 */ - { - { "cvtps2pi", MX, EX, XX }, - { "cvtss2siY", Gv, EX, XX }, - { "cvtpd2pi", MX, EX, XX }, - { "cvtsd2siY", Gv, EX, XX }, - }, - /* PREGRP4 */ - { - { "cvttps2pi", MX, EX, XX }, - { "cvttss2siY", Gv, EX, XX }, - { "cvttpd2pi", MX, EX, XX }, - { "cvttsd2siY", Gv, EX, XX }, - }, - /* PREGRP5 */ - { - { "divps", XM, EX, XX }, - { "divss", XM, EX, XX }, - { "divpd", XM, EX, XX }, - { "divsd", XM, EX, XX }, - }, - /* PREGRP6 */ - { - { "maxps", XM, EX, XX }, - { "maxss", XM, EX, XX }, - { "maxpd", XM, EX, XX }, - { "maxsd", XM, EX, XX }, - }, - /* PREGRP7 */ - { - { "minps", XM, EX, XX }, - { "minss", XM, EX, XX }, - { "minpd", XM, EX, XX }, - { "minsd", XM, EX, XX }, - }, - /* PREGRP8 */ - { - { "movups", XM, EX, XX }, - { "movss", XM, EX, XX }, - { "movupd", XM, EX, XX }, - { "movsd", XM, EX, XX }, - }, - /* PREGRP9 */ - { - { "movups", EX, XM, XX }, - { "movss", EX, XM, XX }, - { "movupd", EX, XM, XX }, - { "movsd", EX, XM, XX }, - }, - /* PREGRP10 */ - { - { "mulps", XM, EX, XX }, - { "mulss", XM, EX, XX }, - { "mulpd", XM, EX, XX }, - { "mulsd", XM, EX, XX }, - }, - /* PREGRP11 */ - { - { "rcpps", XM, EX, XX }, - { "rcpss", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - }, - /* PREGRP12 */ - { - { "rsqrtps", XM, EX, XX }, - { "rsqrtss", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - }, - /* PREGRP13 */ - { - { "sqrtps", XM, EX, XX }, - { "sqrtss", XM, EX, XX }, - { "sqrtpd", XM, EX, XX }, - { "sqrtsd", XM, EX, XX }, - }, - /* PREGRP14 */ - { - { "subps", XM, EX, XX }, - { "subss", XM, EX, XX }, - { "subpd", XM, EX, XX }, - { "subsd", XM, EX, XX }, - }, - /* PREGRP15 */ - { - { "(bad)", XM, EX, XX }, - { "cvtdq2pd", XM, EX, XX }, - { "cvttpd2dq", XM, EX, XX }, - { "cvtpd2dq", XM, EX, XX }, - }, - /* PREGRP16 */ - { - { "cvtdq2ps", XM, EX, XX }, - { "cvttps2dq",XM, EX, XX }, - { "cvtps2dq",XM, EX, XX }, - { "(bad)", XM, EX, XX }, - }, - /* PREGRP17 */ - { - { "cvtps2pd", XM, EX, XX }, - { "cvtss2sd", XM, EX, XX }, - { "cvtpd2ps", XM, EX, XX }, - { "cvtsd2ss", XM, EX, XX }, - }, - /* PREGRP18 */ - { - { "maskmovq", MX, MS, XX }, - { "(bad)", XM, EX, XX }, - { "maskmovdqu", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - }, - /* PREGRP19 */ - { - { "movq", MX, EM, XX }, - { "movdqu", XM, EX, XX }, - { "movdqa", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - }, - /* PREGRP20 */ - { - { "movq", EM, MX, XX }, - { "movdqu", EX, XM, XX }, - { "movdqa", EX, XM, XX }, - { "(bad)", EX, XM, XX }, - }, - /* PREGRP21 */ - { - { "(bad)", EX, XM, XX }, - { "movq2dq", XM, MS, XX }, - { "movq", EX, XM, XX }, - { "movdq2q", MX, XS, XX }, - }, - /* PREGRP22 */ - { - { "pshufw", MX, EM, Ib }, - { "pshufhw", XM, EX, Ib }, - { "pshufd", XM, EX, Ib }, - { "pshuflw", XM, EX, Ib }, - }, - /* PREGRP23 */ - { - { "movd", Edq, MX, XX }, - { "movq", XM, EX, XX }, - { "movd", Edq, XM, XX }, - { "(bad)", Ed, XM, XX }, - }, - /* PREGRP24 */ - { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "punpckhqdq", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - }, - /* PREGRP25 */ - { - { "movntq", Ev, MX, XX }, - { "(bad)", Ev, XM, XX }, - { "movntdq", Ev, XM, XX }, - { "(bad)", Ev, XM, XX }, - }, - /* PREGRP26 */ - { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "punpcklqdq", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - }, - /* PREGRP27 */ - { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "addsubpd", XM, EX, XX }, - { "addsubps", XM, EX, XX }, - }, - /* PREGRP28 */ - { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "haddpd", XM, EX, XX }, - { "haddps", XM, EX, XX }, - }, - /* PREGRP29 */ - { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "hsubpd", XM, EX, XX }, - { "hsubps", XM, EX, XX }, - }, - /* PREGRP30 */ - { - { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */ - { "movsldup", XM, EX, XX }, - { "movlpd", XM, EX, XX }, - { "movddup", XM, EX, XX }, - }, - /* PREGRP31 */ - { - { "movhpX", XM, EX, SIMD_Fixup, 'l' }, - { "movshdup", XM, EX, XX }, - { "movhpd", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - }, - /* PREGRP32 */ - { - { "(bad)", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - { "lddqu", XM, M, XX }, - }, -}; - -static const struct dis386 x86_64_table[][2] = { - { - { "arpl", Ew, Gw, XX }, - { "movs{||lq|xd}", Gv, Ed, XX }, - }, -}; - -#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") - -static void -ckprefix (void) -{ - int newrex; - rex = 0; - prefixes = 0; - used_prefixes = 0; - rex_used = 0; - while (1) - { - FETCH_DATA (the_info, codep + 1); - newrex = 0; - switch (*codep) - { - /* REX prefixes family. */ - case 0x40: - case 0x41: - case 0x42: - case 0x43: - case 0x44: - case 0x45: - case 0x46: - case 0x47: - case 0x48: - case 0x49: - case 0x4a: - case 0x4b: - case 0x4c: - case 0x4d: - case 0x4e: - case 0x4f: - if (mode_64bit) - newrex = *codep; - else - return; - break; - case 0xf3: - prefixes |= PREFIX_REPZ; - break; - case 0xf2: - prefixes |= PREFIX_REPNZ; - break; - case 0xf0: - prefixes |= PREFIX_LOCK; - break; - case 0x2e: - prefixes |= PREFIX_CS; - break; - case 0x36: - prefixes |= PREFIX_SS; - break; - case 0x3e: - prefixes |= PREFIX_DS; - break; - case 0x26: - prefixes |= PREFIX_ES; - break; - case 0x64: - prefixes |= PREFIX_FS; - break; - case 0x65: - prefixes |= PREFIX_GS; - break; - case 0x66: - prefixes |= PREFIX_DATA; - break; - case 0x67: - prefixes |= PREFIX_ADDR; - break; - case FWAIT_OPCODE: - /* fwait is really an instruction. If there are prefixes - before the fwait, they belong to the fwait, *not* to the - following instruction. */ - if (prefixes) - { - prefixes |= PREFIX_FWAIT; - codep++; - return; - } - prefixes = PREFIX_FWAIT; - break; - default: - return; - } - /* Rex is ignored when followed by another prefix. */ - if (rex) - { - oappend (prefix_name (rex, 0)); - oappend (" "); - } - rex = newrex; - codep++; - } -} - -/* Return the name of the prefix byte PREF, or NULL if PREF is not a - prefix byte. */ - -static const char * -prefix_name (int pref, int sizeflag) -{ - switch (pref) - { - /* REX prefixes family. */ - case 0x40: - return "rex"; - case 0x41: - return "rexZ"; - case 0x42: - return "rexY"; - case 0x43: - return "rexYZ"; - case 0x44: - return "rexX"; - case 0x45: - return "rexXZ"; - case 0x46: - return "rexXY"; - case 0x47: - return "rexXYZ"; - case 0x48: - return "rex64"; - case 0x49: - return "rex64Z"; - case 0x4a: - return "rex64Y"; - case 0x4b: - return "rex64YZ"; - case 0x4c: - return "rex64X"; - case 0x4d: - return "rex64XZ"; - case 0x4e: - return "rex64XY"; - case 0x4f: - return "rex64XYZ"; - case 0xf3: - return "repz"; - case 0xf2: - return "repnz"; - case 0xf0: - return "lock"; - case 0x2e: - return "cs"; - case 0x36: - return "ss"; - case 0x3e: - return "ds"; - case 0x26: - return "es"; - case 0x64: - return "fs"; - case 0x65: - return "gs"; - case 0x66: - return (sizeflag & DFLAG) ? "data16" : "data32"; - case 0x67: - if (mode_64bit) - return (sizeflag & AFLAG) ? "addr32" : "addr64"; - else - return ((sizeflag & AFLAG) && !mode_64bit) ? "addr16" : "addr32"; - case FWAIT_OPCODE: - return "fwait"; - default: - return NULL; - } -} - -static char op1out[100], op2out[100], op3out[100]; -static int op_ad, op_index[3]; -static bfd_vma op_address[3]; -static bfd_vma op_riprel[3]; -static bfd_vma start_pc; - -/* - * On the 386's of 1988, the maximum length of an instruction is 15 bytes. - * (see topic "Redundant prefixes" in the "Differences from 8086" - * section of the "Virtual 8086 Mode" chapter.) - * 'pc' should be the address of this instruction, it will - * be used to print the target address if this is a relative jump or call - * The function returns the length of this instruction in bytes. - */ - -static char intel_syntax; -static char open_char; -static char close_char; -static char separator_char; -static char scale_char; - -/* Here for backwards compatibility. When gdb stops using - print_insn_i386_att and print_insn_i386_intel these functions can - disappear, and print_insn_i386 be merged into print_insn. */ -int -print_insn_i386_att (bfd_vma pc, disassemble_info *info) -{ - intel_syntax = 0; - - return print_insn (pc, info); -} - -int -print_insn_i386_intel (bfd_vma pc, disassemble_info *info) -{ - intel_syntax = 1; - - return print_insn (pc, info); -} - -int -print_insn_i386 (bfd_vma pc, disassemble_info *info) -{ - intel_syntax = -1; - - return print_insn (pc, info); -} - -static int -print_insn (bfd_vma pc, disassemble_info *info) -{ - const struct dis386 *dp; - int i; - int two_source_ops; - char *first, *second, *third; - int needcomma; - unsigned char uses_SSE_prefix; - int sizeflag; - const char *p; - struct dis_private priv; - - mode_64bit = (info->mach == bfd_mach_x86_64_intel_syntax - || info->mach == bfd_mach_x86_64); - - if (intel_syntax == (char) -1) - intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax - || info->mach == bfd_mach_x86_64_intel_syntax); - - if (info->mach == bfd_mach_i386_i386 - || info->mach == bfd_mach_x86_64 - || info->mach == bfd_mach_i386_i386_intel_syntax - || info->mach == bfd_mach_x86_64_intel_syntax) - priv.orig_sizeflag = AFLAG | DFLAG; - else if (info->mach == bfd_mach_i386_i8086) - priv.orig_sizeflag = 0; - else - abort (); - - for (p = info->disassembler_options; p != NULL; ) - { - if (strncmp (p, "x86-64", 6) == 0) - { - mode_64bit = 1; - priv.orig_sizeflag = AFLAG | DFLAG; - } - else if (strncmp (p, "i386", 4) == 0) - { - mode_64bit = 0; - priv.orig_sizeflag = AFLAG | DFLAG; - } - else if (strncmp (p, "i8086", 5) == 0) - { - mode_64bit = 0; - priv.orig_sizeflag = 0; - } - else if (strncmp (p, "intel", 5) == 0) - { - intel_syntax = 1; - } - else if (strncmp (p, "att", 3) == 0) - { - intel_syntax = 0; - } - else if (strncmp (p, "addr", 4) == 0) - { - if (p[4] == '1' && p[5] == '6') - priv.orig_sizeflag &= ~AFLAG; - else if (p[4] == '3' && p[5] == '2') - priv.orig_sizeflag |= AFLAG; - } - else if (strncmp (p, "data", 4) == 0) - { - if (p[4] == '1' && p[5] == '6') - priv.orig_sizeflag &= ~DFLAG; - else if (p[4] == '3' && p[5] == '2') - priv.orig_sizeflag |= DFLAG; - } - else if (strncmp (p, "suffix", 6) == 0) - priv.orig_sizeflag |= SUFFIX_ALWAYS; - - p = strchr (p, ','); - if (p != NULL) - p++; - } - - if (intel_syntax) - { - names64 = intel_names64; - names32 = intel_names32; - names16 = intel_names16; - names8 = intel_names8; - names8rex = intel_names8rex; - names_seg = intel_names_seg; - index16 = intel_index16; - open_char = '['; - close_char = ']'; - separator_char = '+'; - scale_char = '*'; - } - else - { - names64 = att_names64; - names32 = att_names32; - names16 = att_names16; - names8 = att_names8; - names8rex = att_names8rex; - names_seg = att_names_seg; - index16 = att_index16; - open_char = '('; - close_char = ')'; - separator_char = ','; - scale_char = ','; - } - - /* The output looks better if we put 7 bytes on a line, since that - puts most long word instructions on a single line. */ - info->bytes_per_line = 7; - - info->private_data = &priv; - priv.max_fetched = priv.the_buffer; - priv.insn_start = pc; - - obuf[0] = 0; - op1out[0] = 0; - op2out[0] = 0; - op3out[0] = 0; - - op_index[0] = op_index[1] = op_index[2] = -1; - - the_info = info; - start_pc = pc; - start_codep = priv.the_buffer; - codep = priv.the_buffer; - - if (setjmp (priv.bailout) != 0) - { - const char *name; - - /* Getting here means we tried for data but didn't get it. That - means we have an incomplete instruction of some sort. Just - print the first byte as a prefix or a .byte pseudo-op. */ - if (codep > priv.the_buffer) - { - name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); - if (name != NULL) - (*info->fprintf_func) (info->stream, "%s", name); - else - { - /* Just print the first byte as a .byte instruction. */ - (*info->fprintf_func) (info->stream, ".byte 0x%x", - (unsigned int) priv.the_buffer[0]); - } - - return 1; - } - - return -1; - } - - obufp = obuf; - ckprefix (); - - insn_codep = codep; - sizeflag = priv.orig_sizeflag; - - FETCH_DATA (info, codep + 1); - two_source_ops = (*codep == 0x62) || (*codep == 0xc8); - - if ((prefixes & PREFIX_FWAIT) - && ((*codep < 0xd8) || (*codep > 0xdf))) - { - const char *name; - - /* fwait not followed by floating point instruction. Print the - first prefix, which is probably fwait itself. */ - name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); - if (name == NULL) - name = INTERNAL_DISASSEMBLER_ERROR; - (*info->fprintf_func) (info->stream, "%s", name); - return 1; - } - - if (*codep == 0x0f) - { - FETCH_DATA (info, codep + 2); - dp = &dis386_twobyte[*++codep]; - need_modrm = twobyte_has_modrm[*codep]; - uses_SSE_prefix = twobyte_uses_SSE_prefix[*codep]; - } - else - { - dp = &dis386[*codep]; - need_modrm = onebyte_has_modrm[*codep]; - uses_SSE_prefix = 0; - } - codep++; - - if (!uses_SSE_prefix && (prefixes & PREFIX_REPZ)) - { - oappend ("repz "); - used_prefixes |= PREFIX_REPZ; - } - if (!uses_SSE_prefix && (prefixes & PREFIX_REPNZ)) - { - oappend ("repnz "); - used_prefixes |= PREFIX_REPNZ; - } - if (prefixes & PREFIX_LOCK) - { - oappend ("lock "); - used_prefixes |= PREFIX_LOCK; - } - - if (prefixes & PREFIX_ADDR) - { - sizeflag ^= AFLAG; - if (dp->bytemode3 != loop_jcxz_mode || intel_syntax) - { - if ((sizeflag & AFLAG) || mode_64bit) - oappend ("addr32 "); - else - oappend ("addr16 "); - used_prefixes |= PREFIX_ADDR; - } - } - - if (!uses_SSE_prefix && (prefixes & PREFIX_DATA)) - { - sizeflag ^= DFLAG; - if (dp->bytemode3 == cond_jump_mode - && dp->bytemode1 == v_mode - && !intel_syntax) - { - if (sizeflag & DFLAG) - oappend ("data32 "); - else - oappend ("data16 "); - used_prefixes |= PREFIX_DATA; - } - } - - if (need_modrm) - { - FETCH_DATA (info, codep + 1); - mod = (*codep >> 6) & 3; - reg = (*codep >> 3) & 7; - rm = *codep & 7; - } - - if (dp->name == NULL && dp->bytemode1 == FLOATCODE) - { - dofloat (sizeflag); - } - else - { - int index; - if (dp->name == NULL) - { - switch (dp->bytemode1) - { - case USE_GROUPS: - dp = &grps[dp->bytemode2][reg]; - break; - - case USE_PREFIX_USER_TABLE: - index = 0; - used_prefixes |= (prefixes & PREFIX_REPZ); - if (prefixes & PREFIX_REPZ) - index = 1; - else - { - used_prefixes |= (prefixes & PREFIX_DATA); - if (prefixes & PREFIX_DATA) - index = 2; - else - { - used_prefixes |= (prefixes & PREFIX_REPNZ); - if (prefixes & PREFIX_REPNZ) - index = 3; - } - } - dp = &prefix_user_table[dp->bytemode2][index]; - break; - - case X86_64_SPECIAL: - dp = &x86_64_table[dp->bytemode2][mode_64bit]; - break; - - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - break; - } - } - - if (putop (dp->name, sizeflag) == 0) - { - obufp = op1out; - op_ad = 2; - if (dp->op1) - (*dp->op1) (dp->bytemode1, sizeflag); - - obufp = op2out; - op_ad = 1; - if (dp->op2) - (*dp->op2) (dp->bytemode2, sizeflag); - - obufp = op3out; - op_ad = 0; - if (dp->op3) - (*dp->op3) (dp->bytemode3, sizeflag); - } - } - - /* See if any prefixes were not used. If so, print the first one - separately. If we don't do this, we'll wind up printing an - instruction stream which does not precisely correspond to the - bytes we are disassembling. */ - if ((prefixes & ~used_prefixes) != 0) - { - const char *name; - - name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); - if (name == NULL) - name = INTERNAL_DISASSEMBLER_ERROR; - (*info->fprintf_func) (info->stream, "%s", name); - return 1; - } - if (rex & ~rex_used) - { - const char *name; - name = prefix_name (rex | 0x40, priv.orig_sizeflag); - if (name == NULL) - name = INTERNAL_DISASSEMBLER_ERROR; - (*info->fprintf_func) (info->stream, "%s ", name); - } - - obufp = obuf + strlen (obuf); - for (i = strlen (obuf); i < 6; i++) - oappend (" "); - oappend (" "); - (*info->fprintf_func) (info->stream, "%s", obuf); - - /* The enter and bound instructions are printed with operands in the same - order as the intel book; everything else is printed in reverse order. */ - if (intel_syntax || two_source_ops) - { - first = op1out; - second = op2out; - third = op3out; - op_ad = op_index[0]; - op_index[0] = op_index[2]; - op_index[2] = op_ad; - } - else - { - first = op3out; - second = op2out; - third = op1out; - } - needcomma = 0; - if (*first) - { - if (op_index[0] != -1 && !op_riprel[0]) - (*info->print_address_func) ((bfd_vma) op_address[op_index[0]], info); - else - (*info->fprintf_func) (info->stream, "%s", first); - needcomma = 1; - } - if (*second) - { - if (needcomma) - (*info->fprintf_func) (info->stream, ","); - if (op_index[1] != -1 && !op_riprel[1]) - (*info->print_address_func) ((bfd_vma) op_address[op_index[1]], info); - else - (*info->fprintf_func) (info->stream, "%s", second); - needcomma = 1; - } - if (*third) - { - if (needcomma) - (*info->fprintf_func) (info->stream, ","); - if (op_index[2] != -1 && !op_riprel[2]) - (*info->print_address_func) ((bfd_vma) op_address[op_index[2]], info); - else - (*info->fprintf_func) (info->stream, "%s", third); - } - for (i = 0; i < 3; i++) - if (op_index[i] != -1 && op_riprel[i]) - { - (*info->fprintf_func) (info->stream, " # "); - (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep - + op_address[op_index[i]]), info); - } - return codep - priv.the_buffer; -} - -static const char *float_mem[] = { - /* d8 */ - "fadd{s||s|}", - "fmul{s||s|}", - "fcom{s||s|}", - "fcomp{s||s|}", - "fsub{s||s|}", - "fsubr{s||s|}", - "fdiv{s||s|}", - "fdivr{s||s|}", - /* d9 */ - "fld{s||s|}", - "(bad)", - "fst{s||s|}", - "fstp{s||s|}", - "fldenv", - "fldcw", - "fNstenv", - "fNstcw", - /* da */ - "fiadd{l||l|}", - "fimul{l||l|}", - "ficom{l||l|}", - "ficomp{l||l|}", - "fisub{l||l|}", - "fisubr{l||l|}", - "fidiv{l||l|}", - "fidivr{l||l|}", - /* db */ - "fild{l||l|}", - "fisttp{l||l|}", - "fist{l||l|}", - "fistp{l||l|}", - "(bad)", - "fld{t||t|}", - "(bad)", - "fstp{t||t|}", - /* dc */ - "fadd{l||l|}", - "fmul{l||l|}", - "fcom{l||l|}", - "fcomp{l||l|}", - "fsub{l||l|}", - "fsubr{l||l|}", - "fdiv{l||l|}", - "fdivr{l||l|}", - /* dd */ - "fld{l||l|}", - "fisttpll", - "fst{l||l|}", - "fstp{l||l|}", - "frstor", - "(bad)", - "fNsave", - "fNstsw", - /* de */ - "fiadd", - "fimul", - "ficom", - "ficomp", - "fisub", - "fisubr", - "fidiv", - "fidivr", - /* df */ - "fild", - "fisttp", - "fist", - "fistp", - "fbld", - "fild{ll||ll|}", - "fbstp", - "fistpll", -}; - -#define ST OP_ST, 0 -#define STi OP_STi, 0 - -#define FGRPd9_2 NULL, NULL, 0, NULL, 0, NULL, 0 -#define FGRPd9_4 NULL, NULL, 1, NULL, 0, NULL, 0 -#define FGRPd9_5 NULL, NULL, 2, NULL, 0, NULL, 0 -#define FGRPd9_6 NULL, NULL, 3, NULL, 0, NULL, 0 -#define FGRPd9_7 NULL, NULL, 4, NULL, 0, NULL, 0 -#define FGRPda_5 NULL, NULL, 5, NULL, 0, NULL, 0 -#define FGRPdb_4 NULL, NULL, 6, NULL, 0, NULL, 0 -#define FGRPde_3 NULL, NULL, 7, NULL, 0, NULL, 0 -#define FGRPdf_4 NULL, NULL, 8, NULL, 0, NULL, 0 - -static const struct dis386 float_reg[][8] = { - /* d8 */ - { - { "fadd", ST, STi, XX }, - { "fmul", ST, STi, XX }, - { "fcom", STi, XX, XX }, - { "fcomp", STi, XX, XX }, - { "fsub", ST, STi, XX }, - { "fsubr", ST, STi, XX }, - { "fdiv", ST, STi, XX }, - { "fdivr", ST, STi, XX }, - }, - /* d9 */ - { - { "fld", STi, XX, XX }, - { "fxch", STi, XX, XX }, - { FGRPd9_2 }, - { "(bad)", XX, XX, XX }, - { FGRPd9_4 }, - { FGRPd9_5 }, - { FGRPd9_6 }, - { FGRPd9_7 }, - }, - /* da */ - { - { "fcmovb", ST, STi, XX }, - { "fcmove", ST, STi, XX }, - { "fcmovbe",ST, STi, XX }, - { "fcmovu", ST, STi, XX }, - { "(bad)", XX, XX, XX }, - { FGRPda_5 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* db */ - { - { "fcmovnb",ST, STi, XX }, - { "fcmovne",ST, STi, XX }, - { "fcmovnbe",ST, STi, XX }, - { "fcmovnu",ST, STi, XX }, - { FGRPdb_4 }, - { "fucomi", ST, STi, XX }, - { "fcomi", ST, STi, XX }, - { "(bad)", XX, XX, XX }, - }, - /* dc */ - { - { "fadd", STi, ST, XX }, - { "fmul", STi, ST, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, -#if UNIXWARE_COMPAT - { "fsub", STi, ST, XX }, - { "fsubr", STi, ST, XX }, - { "fdiv", STi, ST, XX }, - { "fdivr", STi, ST, XX }, -#else - { "fsubr", STi, ST, XX }, - { "fsub", STi, ST, XX }, - { "fdivr", STi, ST, XX }, - { "fdiv", STi, ST, XX }, -#endif - }, - /* dd */ - { - { "ffree", STi, XX, XX }, - { "(bad)", XX, XX, XX }, - { "fst", STi, XX, XX }, - { "fstp", STi, XX, XX }, - { "fucom", STi, XX, XX }, - { "fucomp", STi, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - }, - /* de */ - { - { "faddp", STi, ST, XX }, - { "fmulp", STi, ST, XX }, - { "(bad)", XX, XX, XX }, - { FGRPde_3 }, -#if UNIXWARE_COMPAT - { "fsubp", STi, ST, XX }, - { "fsubrp", STi, ST, XX }, - { "fdivp", STi, ST, XX }, - { "fdivrp", STi, ST, XX }, -#else - { "fsubrp", STi, ST, XX }, - { "fsubp", STi, ST, XX }, - { "fdivrp", STi, ST, XX }, - { "fdivp", STi, ST, XX }, -#endif - }, - /* df */ - { - { "ffreep", STi, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { FGRPdf_4 }, - { "fucomip",ST, STi, XX }, - { "fcomip", ST, STi, XX }, - { "(bad)", XX, XX, XX }, - }, -}; - -static char *fgrps[][8] = { - /* d9_2 0 */ - { - "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, - - /* d9_4 1 */ - { - "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", - }, - - /* d9_5 2 */ - { - "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", - }, - - /* d9_6 3 */ - { - "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", - }, - - /* d9_7 4 */ - { - "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", - }, - - /* da_5 5 */ - { - "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, - - /* db_4 6 */ - { - "feni(287 only)","fdisi(287 only)","fNclex","fNinit", - "fNsetpm(287 only)","(bad)","(bad)","(bad)", - }, - - /* de_3 7 */ - { - "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, - - /* df_4 8 */ - { - "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", - }, -}; - -static void -dofloat (int sizeflag) -{ - const struct dis386 *dp; - unsigned char floatop; - - floatop = codep[-1]; - - if (mod != 3) - { - putop (float_mem[(floatop - 0xd8) * 8 + reg], sizeflag); - obufp = op1out; - if (floatop == 0xdb) - OP_E (x_mode, sizeflag); - else if (floatop == 0xdd) - OP_E (d_mode, sizeflag); - else - OP_E (v_mode, sizeflag); - return; - } - /* Skip mod/rm byte. */ - MODRM_CHECK; - codep++; - - dp = &float_reg[floatop - 0xd8][reg]; - if (dp->name == NULL) - { - putop (fgrps[dp->bytemode1][rm], sizeflag); - - /* Instruction fnstsw is only one with strange arg. */ - if (floatop == 0xdf && codep[-1] == 0xe0) - strcpy (op1out, names16[0]); - } - else - { - putop (dp->name, sizeflag); - - obufp = op1out; - if (dp->op1) - (*dp->op1) (dp->bytemode1, sizeflag); - obufp = op2out; - if (dp->op2) - (*dp->op2) (dp->bytemode2, sizeflag); - } -} - -static void -OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - oappend ("%st"); -} - -static void -OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - sprintf (scratchbuf, "%%st(%d)", rm); - oappend (scratchbuf + intel_syntax); -} - -/* Capital letters in template are macros. */ -static int -putop (const char *template, int sizeflag) -{ - const char *p; - int alt; - - for (p = template; *p; p++) - { - switch (*p) - { - default: - *obufp++ = *p; - break; - case '{': - alt = 0; - if (intel_syntax) - alt += 1; - if (mode_64bit) - alt += 2; - while (alt != 0) - { - while (*++p != '|') - { - if (*p == '}') - { - /* Alternative not valid. */ - strcpy (obuf, "(bad)"); - obufp = obuf + 5; - return 1; - } - else if (*p == '\0') - abort (); - } - alt--; - } - break; - case '|': - while (*++p != '}') - { - if (*p == '\0') - abort (); - } - break; - case '}': - break; - case 'A': - if (intel_syntax) - break; - if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) - *obufp++ = 'b'; - break; - case 'B': - if (intel_syntax) - break; - if (sizeflag & SUFFIX_ALWAYS) - *obufp++ = 'b'; - break; - case 'E': /* For jcxz/jecxz */ - if (mode_64bit) - { - if (sizeflag & AFLAG) - *obufp++ = 'r'; - else - *obufp++ = 'e'; - } - else - if (sizeflag & AFLAG) - *obufp++ = 'e'; - used_prefixes |= (prefixes & PREFIX_ADDR); - break; - case 'F': - if (intel_syntax) - break; - if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) - { - if (sizeflag & AFLAG) - *obufp++ = mode_64bit ? 'q' : 'l'; - else - *obufp++ = mode_64bit ? 'l' : 'w'; - used_prefixes |= (prefixes & PREFIX_ADDR); - } - break; - case 'H': - if (intel_syntax) - break; - if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS - || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) - { - used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); - *obufp++ = ','; - *obufp++ = 'p'; - if (prefixes & PREFIX_DS) - *obufp++ = 't'; - else - *obufp++ = 'n'; - } - break; - case 'L': - if (intel_syntax) - break; - if (sizeflag & SUFFIX_ALWAYS) - *obufp++ = 'l'; - break; - case 'N': - if ((prefixes & PREFIX_FWAIT) == 0) - *obufp++ = 'n'; - else - used_prefixes |= PREFIX_FWAIT; - break; - case 'O': - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - *obufp++ = 'o'; - else - *obufp++ = 'd'; - break; - case 'T': - if (intel_syntax) - break; - if (mode_64bit) - { - *obufp++ = 'q'; - break; - } - /* Fall through. */ - case 'P': - if (intel_syntax) - break; - if ((prefixes & PREFIX_DATA) - || (rex & REX_MODE64) - || (sizeflag & SUFFIX_ALWAYS)) - { - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - *obufp++ = 'q'; - else - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); - } - } - break; - case 'U': - if (intel_syntax) - break; - if (mode_64bit) - { - *obufp++ = 'q'; - break; - } - /* Fall through. */ - case 'Q': - if (intel_syntax) - break; - USED_REX (REX_MODE64); - if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) - { - if (rex & REX_MODE64) - *obufp++ = 'q'; - else - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); - } - } - break; - case 'R': - USED_REX (REX_MODE64); - if (intel_syntax) - { - if (rex & REX_MODE64) - { - *obufp++ = 'q'; - *obufp++ = 't'; - } - else if (sizeflag & DFLAG) - { - *obufp++ = 'd'; - *obufp++ = 'q'; - } - else - { - *obufp++ = 'w'; - *obufp++ = 'd'; - } - } - else - { - if (rex & REX_MODE64) - *obufp++ = 'q'; - else if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - } - if (!(rex & REX_MODE64)) - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case 'S': - if (intel_syntax) - break; - if (sizeflag & SUFFIX_ALWAYS) - { - if (rex & REX_MODE64) - *obufp++ = 'q'; - else - { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); - } - } - break; - case 'X': - if (prefixes & PREFIX_DATA) - *obufp++ = 'd'; - else - *obufp++ = 's'; - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case 'Y': - if (intel_syntax) - break; - if (rex & REX_MODE64) - { - USED_REX (REX_MODE64); - *obufp++ = 'q'; - } - break; - /* implicit operand size 'l' for i386 or 'q' for x86-64 */ - case 'W': - /* operand size flag for cwtl, cbtw */ - USED_REX (0); - if (rex) - *obufp++ = 'l'; - else if (sizeflag & DFLAG) - *obufp++ = 'w'; - else - *obufp++ = 'b'; - if (intel_syntax) - { - if (rex) - { - *obufp++ = 'q'; - *obufp++ = 'e'; - } - if (sizeflag & DFLAG) - { - *obufp++ = 'd'; - *obufp++ = 'e'; - } - else - { - *obufp++ = 'w'; - } - } - if (!rex) - used_prefixes |= (prefixes & PREFIX_DATA); - break; - } - } - *obufp = 0; - return 0; -} - -static void -oappend (const char *s) -{ - strcpy (obufp, s); - obufp += strlen (s); -} - -static void -append_seg (void) -{ - if (prefixes & PREFIX_CS) - { - used_prefixes |= PREFIX_CS; - oappend ("%cs:" + intel_syntax); - } - if (prefixes & PREFIX_DS) - { - used_prefixes |= PREFIX_DS; - oappend ("%ds:" + intel_syntax); - } - if (prefixes & PREFIX_SS) - { - used_prefixes |= PREFIX_SS; - oappend ("%ss:" + intel_syntax); - } - if (prefixes & PREFIX_ES) - { - used_prefixes |= PREFIX_ES; - oappend ("%es:" + intel_syntax); - } - if (prefixes & PREFIX_FS) - { - used_prefixes |= PREFIX_FS; - oappend ("%fs:" + intel_syntax); - } - if (prefixes & PREFIX_GS) - { - used_prefixes |= PREFIX_GS; - oappend ("%gs:" + intel_syntax); - } -} - -static void -OP_indirE (int bytemode, int sizeflag) -{ - if (!intel_syntax) - oappend ("*"); - OP_E (bytemode, sizeflag); -} - -static void -print_operand_value (char *buf, int hex, bfd_vma disp) -{ - if (mode_64bit) - { - if (hex) - { - char tmp[30]; - int i; - buf[0] = '0'; - buf[1] = 'x'; - sprintf_vma (tmp, disp); - for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); - strcpy (buf + 2, tmp + i); - } - else - { - bfd_signed_vma v = disp; - char tmp[30]; - int i; - if (v < 0) - { - *(buf++) = '-'; - v = -disp; - /* Check for possible overflow on 0x8000000000000000. */ - if (v < 0) - { - strcpy (buf, "9223372036854775808"); - return; - } - } - if (!v) - { - strcpy (buf, "0"); - return; - } - - i = 0; - tmp[29] = 0; - while (v) - { - tmp[28 - i] = (v % 10) + '0'; - v /= 10; - i++; - } - strcpy (buf, tmp + 29 - i); - } - } - else - { - if (hex) - sprintf (buf, "0x%x", (unsigned int) disp); - else - sprintf (buf, "%d", (int) disp); - } -} - -static void -OP_E (int bytemode, int sizeflag) -{ - bfd_vma disp; - int add = 0; - int riprel = 0; - USED_REX (REX_EXTZ); - if (rex & REX_EXTZ) - add += 8; - - /* Skip mod/rm byte. */ - MODRM_CHECK; - codep++; - - if (mod == 3) - { - switch (bytemode) - { - case b_mode: - USED_REX (0); - if (rex) - oappend (names8rex[rm + add]); - else - oappend (names8[rm + add]); - break; - case w_mode: - oappend (names16[rm + add]); - break; - case d_mode: - oappend (names32[rm + add]); - break; - case q_mode: - oappend (names64[rm + add]); - break; - case m_mode: - if (mode_64bit) - oappend (names64[rm + add]); - else - oappend (names32[rm + add]); - break; - case v_mode: - case dq_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - oappend (names64[rm + add]); - else if ((sizeflag & DFLAG) || bytemode == dq_mode) - oappend (names32[rm + add]); - else - oappend (names16[rm + add]); - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case 0: - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - break; - } - return; - } - - disp = 0; - append_seg (); - - if ((sizeflag & AFLAG) || mode_64bit) /* 32 bit address mode */ - { - int havesib; - int havebase; - int base; - int index = 0; - int scale = 0; - - havesib = 0; - havebase = 1; - base = rm; - - if (base == 4) - { - havesib = 1; - FETCH_DATA (the_info, codep + 1); - scale = (*codep >> 6) & 3; - index = (*codep >> 3) & 7; - base = *codep & 7; - USED_REX (REX_EXTY); - USED_REX (REX_EXTZ); - if (rex & REX_EXTY) - index += 8; - if (rex & REX_EXTZ) - base += 8; - codep++; - } - - switch (mod) - { - case 0: - if ((base & 7) == 5) - { - havebase = 0; - if (mode_64bit && !havesib && (sizeflag & AFLAG)) - riprel = 1; - disp = get32s (); - } - break; - case 1: - FETCH_DATA (the_info, codep + 1); - disp = *codep++; - if ((disp & 0x80) != 0) - disp -= 0x100; - break; - case 2: - disp = get32s (); - break; - } - - if (!intel_syntax) - if (mod != 0 || (base & 7) == 5) - { - print_operand_value (scratchbuf, !riprel, disp); - oappend (scratchbuf); - if (riprel) - { - set_op (disp, 1); - oappend ("(%rip)"); - } - } - - if (havebase || (havesib && (index != 4 || scale != 0))) - { - if (intel_syntax) - { - switch (bytemode) - { - case b_mode: - oappend ("BYTE PTR "); - break; - case w_mode: - oappend ("WORD PTR "); - break; - case v_mode: - oappend ("DWORD PTR "); - break; - case d_mode: - oappend ("QWORD PTR "); - break; - case m_mode: - if (mode_64bit) - oappend ("DWORD PTR "); - else - oappend ("QWORD PTR "); - break; - case x_mode: - oappend ("XWORD PTR "); - break; - default: - break; - } - } - *obufp++ = open_char; - if (intel_syntax && riprel) - oappend ("rip + "); - *obufp = '\0'; - USED_REX (REX_EXTZ); - if (!havesib && (rex & REX_EXTZ)) - base += 8; - if (havebase) - oappend (mode_64bit && (sizeflag & AFLAG) - ? names64[base] : names32[base]); - if (havesib) - { - if (index != 4) - { - if (intel_syntax) - { - if (havebase) - { - *obufp++ = separator_char; - *obufp = '\0'; - } - sprintf (scratchbuf, "%s", - mode_64bit && (sizeflag & AFLAG) - ? names64[index] : names32[index]); - } - else - sprintf (scratchbuf, ",%s", - mode_64bit && (sizeflag & AFLAG) - ? names64[index] : names32[index]); - oappend (scratchbuf); - } - if (scale != 0 || (!intel_syntax && index != 4)) - { - *obufp++ = scale_char; - *obufp = '\0'; - sprintf (scratchbuf, "%d", 1 << scale); - oappend (scratchbuf); - } - } - if (intel_syntax) - if (mod != 0 || (base & 7) == 5) - { - /* Don't print zero displacements. */ - if (disp != 0) - { - if ((bfd_signed_vma) disp > 0) - { - *obufp++ = '+'; - *obufp = '\0'; - } - - print_operand_value (scratchbuf, 0, disp); - oappend (scratchbuf); - } - } - - *obufp++ = close_char; - *obufp = '\0'; - } - else if (intel_syntax) - { - if (mod != 0 || (base & 7) == 5) - { - if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS)) - ; - else - { - oappend (names_seg[ds_reg - es_reg]); - oappend (":"); - } - print_operand_value (scratchbuf, 1, disp); - oappend (scratchbuf); - } - } - } - else - { /* 16 bit address mode */ - switch (mod) - { - case 0: - if ((rm & 7) == 6) - { - disp = get16 (); - if ((disp & 0x8000) != 0) - disp -= 0x10000; - } - break; - case 1: - FETCH_DATA (the_info, codep + 1); - disp = *codep++; - if ((disp & 0x80) != 0) - disp -= 0x100; - break; - case 2: - disp = get16 (); - if ((disp & 0x8000) != 0) - disp -= 0x10000; - break; - } - - if (!intel_syntax) - if (mod != 0 || (rm & 7) == 6) - { - print_operand_value (scratchbuf, 0, disp); - oappend (scratchbuf); - } - - if (mod != 0 || (rm & 7) != 6) - { - *obufp++ = open_char; - *obufp = '\0'; - oappend (index16[rm + add]); - *obufp++ = close_char; - *obufp = '\0'; - } - } -} - -static void -OP_G (int bytemode, int sizeflag) -{ - int add = 0; - USED_REX (REX_EXTX); - if (rex & REX_EXTX) - add += 8; - switch (bytemode) - { - case b_mode: - USED_REX (0); - if (rex) - oappend (names8rex[reg + add]); - else - oappend (names8[reg + add]); - break; - case w_mode: - oappend (names16[reg + add]); - break; - case d_mode: - oappend (names32[reg + add]); - break; - case q_mode: - oappend (names64[reg + add]); - break; - case v_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - oappend (names64[reg + add]); - else if (sizeflag & DFLAG) - oappend (names32[reg + add]); - else - oappend (names16[reg + add]); - used_prefixes |= (prefixes & PREFIX_DATA); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - break; - } -} - -static bfd_vma -get64 (void) -{ - bfd_vma x; -#ifdef BFD64 - unsigned int a; - unsigned int b; - - FETCH_DATA (the_info, codep + 8); - a = *codep++ & 0xff; - a |= (*codep++ & 0xff) << 8; - a |= (*codep++ & 0xff) << 16; - a |= (*codep++ & 0xff) << 24; - b = *codep++ & 0xff; - b |= (*codep++ & 0xff) << 8; - b |= (*codep++ & 0xff) << 16; - b |= (*codep++ & 0xff) << 24; - x = a + ((bfd_vma) b << 32); -#else - abort (); - x = 0; -#endif - return x; -} - -static bfd_signed_vma -get32 (void) -{ - bfd_signed_vma x = 0; - - FETCH_DATA (the_info, codep + 4); - x = *codep++ & (bfd_signed_vma) 0xff; - x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; - x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; - x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; - return x; -} - -static bfd_signed_vma -get32s (void) -{ - bfd_signed_vma x = 0; - - FETCH_DATA (the_info, codep + 4); - x = *codep++ & (bfd_signed_vma) 0xff; - x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; - x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; - x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; - - x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); - - return x; -} - -static int -get16 (void) -{ - int x = 0; - - FETCH_DATA (the_info, codep + 2); - x = *codep++ & 0xff; - x |= (*codep++ & 0xff) << 8; - return x; -} - -static void -set_op (bfd_vma op, int riprel) -{ - op_index[op_ad] = op_ad; - if (mode_64bit) - { - op_address[op_ad] = op; - op_riprel[op_ad] = riprel; - } - else - { - /* Mask to get a 32-bit address. */ - op_address[op_ad] = op & 0xffffffff; - op_riprel[op_ad] = riprel & 0xffffffff; - } -} - -static void -OP_REG (int code, int sizeflag) -{ - const char *s; - int add = 0; - USED_REX (REX_EXTZ); - if (rex & REX_EXTZ) - add = 8; - - switch (code) - { - case indir_dx_reg: - if (intel_syntax) - s = "[dx]"; - else - s = "(%dx)"; - break; - case ax_reg: case cx_reg: case dx_reg: case bx_reg: - case sp_reg: case bp_reg: case si_reg: case di_reg: - s = names16[code - ax_reg + add]; - break; - case es_reg: case ss_reg: case cs_reg: - case ds_reg: case fs_reg: case gs_reg: - s = names_seg[code - es_reg + add]; - break; - case al_reg: case ah_reg: case cl_reg: case ch_reg: - case dl_reg: case dh_reg: case bl_reg: case bh_reg: - USED_REX (0); - if (rex) - s = names8rex[code - al_reg + add]; - else - s = names8[code - al_reg]; - break; - case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: - case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: - if (mode_64bit) - { - s = names64[code - rAX_reg + add]; - break; - } - code += eAX_reg - rAX_reg; - /* Fall through. */ - case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: - case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - s = names64[code - eAX_reg + add]; - else if (sizeflag & DFLAG) - s = names32[code - eAX_reg + add]; - else - s = names16[code - eAX_reg + add]; - used_prefixes |= (prefixes & PREFIX_DATA); - break; - default: - s = INTERNAL_DISASSEMBLER_ERROR; - break; - } - oappend (s); -} - -static void -OP_IMREG (int code, int sizeflag) -{ - const char *s; - - switch (code) - { - case indir_dx_reg: - if (intel_syntax) - s = "[dx]"; - else - s = "(%dx)"; - break; - case ax_reg: case cx_reg: case dx_reg: case bx_reg: - case sp_reg: case bp_reg: case si_reg: case di_reg: - s = names16[code - ax_reg]; - break; - case es_reg: case ss_reg: case cs_reg: - case ds_reg: case fs_reg: case gs_reg: - s = names_seg[code - es_reg]; - break; - case al_reg: case ah_reg: case cl_reg: case ch_reg: - case dl_reg: case dh_reg: case bl_reg: case bh_reg: - USED_REX (0); - if (rex) - s = names8rex[code - al_reg]; - else - s = names8[code - al_reg]; - break; - case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: - case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - s = names64[code - eAX_reg]; - else if (sizeflag & DFLAG) - s = names32[code - eAX_reg]; - else - s = names16[code - eAX_reg]; - used_prefixes |= (prefixes & PREFIX_DATA); - break; - default: - s = INTERNAL_DISASSEMBLER_ERROR; - break; - } - oappend (s); -} - -static void -OP_I (int bytemode, int sizeflag) -{ - bfd_signed_vma op; - bfd_signed_vma mask = -1; - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++; - mask = 0xff; - break; - case q_mode: - if (mode_64bit) - { - op = get32s (); - break; - } - /* Fall through. */ - case v_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - op = get32s (); - else if (sizeflag & DFLAG) - { - op = get32 (); - mask = 0xffffffff; - } - else - { - op = get16 (); - mask = 0xfffff; - } - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case w_mode: - mask = 0xfffff; - op = get16 (); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - - op &= mask; - scratchbuf[0] = '$'; - print_operand_value (scratchbuf + 1, 1, op); - oappend (scratchbuf + intel_syntax); - scratchbuf[0] = '\0'; -} - -static void -OP_I64 (int bytemode, int sizeflag) -{ - bfd_signed_vma op; - bfd_signed_vma mask = -1; - - if (!mode_64bit) - { - OP_I (bytemode, sizeflag); - return; - } - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++; - mask = 0xff; - break; - case v_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - op = get64 (); - else if (sizeflag & DFLAG) - { - op = get32 (); - mask = 0xffffffff; - } - else - { - op = get16 (); - mask = 0xfffff; - } - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case w_mode: - mask = 0xfffff; - op = get16 (); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - - op &= mask; - scratchbuf[0] = '$'; - print_operand_value (scratchbuf + 1, 1, op); - oappend (scratchbuf + intel_syntax); - scratchbuf[0] = '\0'; -} - -static void -OP_sI (int bytemode, int sizeflag) -{ - bfd_signed_vma op; - bfd_signed_vma mask = -1; - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++; - if ((op & 0x80) != 0) - op -= 0x100; - mask = 0xffffffff; - break; - case v_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - op = get32s (); - else if (sizeflag & DFLAG) - { - op = get32s (); - mask = 0xffffffff; - } - else - { - mask = 0xffffffff; - op = get16 (); - if ((op & 0x8000) != 0) - op -= 0x10000; - } - used_prefixes |= (prefixes & PREFIX_DATA); - break; - case w_mode: - op = get16 (); - mask = 0xffffffff; - if ((op & 0x8000) != 0) - op -= 0x10000; - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - - scratchbuf[0] = '$'; - print_operand_value (scratchbuf + 1, 1, op); - oappend (scratchbuf + intel_syntax); -} - -static void -OP_J (int bytemode, int sizeflag) -{ - bfd_vma disp; - bfd_vma mask = -1; - - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - disp = *codep++; - if ((disp & 0x80) != 0) - disp -= 0x100; - break; - case v_mode: - if (sizeflag & DFLAG) - disp = get32s (); - else - { - disp = get16 (); - /* For some reason, a data16 prefix on a jump instruction - means that the pc is masked to 16 bits after the - displacement is added! */ - mask = 0xffff; - } - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } - disp = (start_pc + codep - start_codep + disp) & mask; - set_op (disp, 0); - print_operand_value (scratchbuf, 1, disp); - oappend (scratchbuf); -} - -static void -OP_SEG (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - oappend (names_seg[reg]); -} - -static void -OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) -{ - int seg, offset; - - if (sizeflag & DFLAG) - { - offset = get32 (); - seg = get16 (); - } - else - { - offset = get16 (); - seg = get16 (); - } - used_prefixes |= (prefixes & PREFIX_DATA); - if (intel_syntax) - sprintf (scratchbuf, "0x%x,0x%x", seg, offset); - else - sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); - oappend (scratchbuf); -} - -static void -OP_OFF (int bytemode ATTRIBUTE_UNUSED, int sizeflag) -{ - bfd_vma off; - - append_seg (); - - if ((sizeflag & AFLAG) || mode_64bit) - off = get32 (); - else - off = get16 (); - - if (intel_syntax) - { - if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS))) - { - oappend (names_seg[ds_reg - es_reg]); - oappend (":"); - } - } - print_operand_value (scratchbuf, 1, off); - oappend (scratchbuf); -} - -static void -OP_OFF64 (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - bfd_vma off; - - if (!mode_64bit) - { - OP_OFF (bytemode, sizeflag); - return; - } - - append_seg (); - - off = get64 (); - - if (intel_syntax) - { - if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS))) - { - oappend (names_seg[ds_reg - es_reg]); - oappend (":"); - } - } - print_operand_value (scratchbuf, 1, off); - oappend (scratchbuf); -} - -static void -ptr_reg (int code, int sizeflag) -{ - const char *s; - if (intel_syntax) - oappend ("["); - else - oappend ("("); - - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - { - if (!(sizeflag & AFLAG)) - s = names32[code - eAX_reg]; - else - s = names64[code - eAX_reg]; - } - else if (sizeflag & AFLAG) - s = names32[code - eAX_reg]; - else - s = names16[code - eAX_reg]; - oappend (s); - if (intel_syntax) - oappend ("]"); - else - oappend (")"); -} - -static void -OP_ESreg (int code, int sizeflag) -{ - oappend ("%es:" + intel_syntax); - ptr_reg (code, sizeflag); -} - -static void -OP_DSreg (int code, int sizeflag) -{ - if ((prefixes - & (PREFIX_CS - | PREFIX_DS - | PREFIX_SS - | PREFIX_ES - | PREFIX_FS - | PREFIX_GS)) == 0) - prefixes |= PREFIX_DS; - append_seg (); - ptr_reg (code, sizeflag); -} - -static void -OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - int add = 0; - USED_REX (REX_EXTX); - if (rex & REX_EXTX) - add = 8; - sprintf (scratchbuf, "%%cr%d", reg + add); - oappend (scratchbuf + intel_syntax); -} - -static void -OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - int add = 0; - USED_REX (REX_EXTX); - if (rex & REX_EXTX) - add = 8; - if (intel_syntax) - sprintf (scratchbuf, "db%d", reg + add); - else - sprintf (scratchbuf, "%%db%d", reg + add); - oappend (scratchbuf); -} - -static void -OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - sprintf (scratchbuf, "%%tr%d", reg); - oappend (scratchbuf + intel_syntax); -} - -static void -OP_Rd (int bytemode, int sizeflag) -{ - if (mod == 3) - OP_E (bytemode, sizeflag); - else - BadOp (); -} - -static void -OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - int add = 0; - USED_REX (REX_EXTX); - if (rex & REX_EXTX) - add = 8; - used_prefixes |= (prefixes & PREFIX_DATA); - if (prefixes & PREFIX_DATA) - sprintf (scratchbuf, "%%xmm%d", reg + add); - else - sprintf (scratchbuf, "%%mm%d", reg + add); - oappend (scratchbuf + intel_syntax); -} - -static void -OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - int add = 0; - USED_REX (REX_EXTX); - if (rex & REX_EXTX) - add = 8; - sprintf (scratchbuf, "%%xmm%d", reg + add); - oappend (scratchbuf + intel_syntax); -} - -static void -OP_EM (int bytemode, int sizeflag) -{ - int add = 0; - if (mod != 3) - { - OP_E (bytemode, sizeflag); - return; - } - USED_REX (REX_EXTZ); - if (rex & REX_EXTZ) - add = 8; - - /* Skip mod/rm byte. */ - MODRM_CHECK; - codep++; - used_prefixes |= (prefixes & PREFIX_DATA); - if (prefixes & PREFIX_DATA) - sprintf (scratchbuf, "%%xmm%d", rm + add); - else - sprintf (scratchbuf, "%%mm%d", rm + add); - oappend (scratchbuf + intel_syntax); -} - -static void -OP_EX (int bytemode, int sizeflag) -{ - int add = 0; - if (mod != 3) - { - OP_E (bytemode, sizeflag); - return; - } - USED_REX (REX_EXTZ); - if (rex & REX_EXTZ) - add = 8; - - /* Skip mod/rm byte. */ - MODRM_CHECK; - codep++; - sprintf (scratchbuf, "%%xmm%d", rm + add); - oappend (scratchbuf + intel_syntax); -} - -static void -OP_MS (int bytemode, int sizeflag) -{ - if (mod == 3) - OP_EM (bytemode, sizeflag); - else - BadOp (); -} - -static void -OP_XS (int bytemode, int sizeflag) -{ - if (mod == 3) - OP_EX (bytemode, sizeflag); - else - BadOp (); -} - -static void -OP_M (int bytemode, int sizeflag) -{ - if (mod == 3) - BadOp (); /* bad lea,lds,les,lfs,lgs,lss modrm */ - else - OP_E (bytemode, sizeflag); -} - -static void -OP_0f07 (int bytemode, int sizeflag) -{ - if (mod != 3 || rm != 0) - BadOp (); - else - OP_E (bytemode, sizeflag); -} - -static void -OP_0fae (int bytemode, int sizeflag) -{ - if (mod == 3) - { - if (reg == 7) - strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence"); - - if (reg < 5 || rm != 0) - { - BadOp (); /* bad sfence, mfence, or lfence */ - return; - } - } - else if (reg != 7) - { - BadOp (); /* bad clflush */ - return; - } - - OP_E (bytemode, sizeflag); -} - -static void -NOP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - /* NOP with REPZ prefix is called PAUSE. */ - if (prefixes == PREFIX_REPZ) - strcpy (obuf, "pause"); -} - -static const char *const Suffix3DNow[] = { -/* 00 */ NULL, NULL, NULL, NULL, -/* 04 */ NULL, NULL, NULL, NULL, -/* 08 */ NULL, NULL, NULL, NULL, -/* 0C */ "pi2fw", "pi2fd", NULL, NULL, -/* 10 */ NULL, NULL, NULL, NULL, -/* 14 */ NULL, NULL, NULL, NULL, -/* 18 */ NULL, NULL, NULL, NULL, -/* 1C */ "pf2iw", "pf2id", NULL, NULL, -/* 20 */ NULL, NULL, NULL, NULL, -/* 24 */ NULL, NULL, NULL, NULL, -/* 28 */ NULL, NULL, NULL, NULL, -/* 2C */ NULL, NULL, NULL, NULL, -/* 30 */ NULL, NULL, NULL, NULL, -/* 34 */ NULL, NULL, NULL, NULL, -/* 38 */ NULL, NULL, NULL, NULL, -/* 3C */ NULL, NULL, NULL, NULL, -/* 40 */ NULL, NULL, NULL, NULL, -/* 44 */ NULL, NULL, NULL, NULL, -/* 48 */ NULL, NULL, NULL, NULL, -/* 4C */ NULL, NULL, NULL, NULL, -/* 50 */ NULL, NULL, NULL, NULL, -/* 54 */ NULL, NULL, NULL, NULL, -/* 58 */ NULL, NULL, NULL, NULL, -/* 5C */ NULL, NULL, NULL, NULL, -/* 60 */ NULL, NULL, NULL, NULL, -/* 64 */ NULL, NULL, NULL, NULL, -/* 68 */ NULL, NULL, NULL, NULL, -/* 6C */ NULL, NULL, NULL, NULL, -/* 70 */ NULL, NULL, NULL, NULL, -/* 74 */ NULL, NULL, NULL, NULL, -/* 78 */ NULL, NULL, NULL, NULL, -/* 7C */ NULL, NULL, NULL, NULL, -/* 80 */ NULL, NULL, NULL, NULL, -/* 84 */ NULL, NULL, NULL, NULL, -/* 88 */ NULL, NULL, "pfnacc", NULL, -/* 8C */ NULL, NULL, "pfpnacc", NULL, -/* 90 */ "pfcmpge", NULL, NULL, NULL, -/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", -/* 98 */ NULL, NULL, "pfsub", NULL, -/* 9C */ NULL, NULL, "pfadd", NULL, -/* A0 */ "pfcmpgt", NULL, NULL, NULL, -/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", -/* A8 */ NULL, NULL, "pfsubr", NULL, -/* AC */ NULL, NULL, "pfacc", NULL, -/* B0 */ "pfcmpeq", NULL, NULL, NULL, -/* B4 */ "pfmul", NULL, "pfrcpit2", "pfmulhrw", -/* B8 */ NULL, NULL, NULL, "pswapd", -/* BC */ NULL, NULL, NULL, "pavgusb", -/* C0 */ NULL, NULL, NULL, NULL, -/* C4 */ NULL, NULL, NULL, NULL, -/* C8 */ NULL, NULL, NULL, NULL, -/* CC */ NULL, NULL, NULL, NULL, -/* D0 */ NULL, NULL, NULL, NULL, -/* D4 */ NULL, NULL, NULL, NULL, -/* D8 */ NULL, NULL, NULL, NULL, -/* DC */ NULL, NULL, NULL, NULL, -/* E0 */ NULL, NULL, NULL, NULL, -/* E4 */ NULL, NULL, NULL, NULL, -/* E8 */ NULL, NULL, NULL, NULL, -/* EC */ NULL, NULL, NULL, NULL, -/* F0 */ NULL, NULL, NULL, NULL, -/* F4 */ NULL, NULL, NULL, NULL, -/* F8 */ NULL, NULL, NULL, NULL, -/* FC */ NULL, NULL, NULL, NULL, -}; - -static void -OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - const char *mnemonic; - - FETCH_DATA (the_info, codep + 1); - /* AMD 3DNow! instructions are specified by an opcode suffix in the - place where an 8-bit immediate would normally go. ie. the last - byte of the instruction. */ - obufp = obuf + strlen (obuf); - mnemonic = Suffix3DNow[*codep++ & 0xff]; - if (mnemonic) - oappend (mnemonic); - else - { - /* Since a variable sized modrm/sib chunk is between the start - of the opcode (0x0f0f) and the opcode suffix, we need to do - all the modrm processing first, and don't know until now that - we have a bad opcode. This necessitates some cleaning up. */ - op1out[0] = '\0'; - op2out[0] = '\0'; - BadOp (); - } -} - -static const char *simd_cmp_op[] = { - "eq", - "lt", - "le", - "unord", - "neq", - "nlt", - "nle", - "ord" -}; - -static void -OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - unsigned int cmp_type; - - FETCH_DATA (the_info, codep + 1); - obufp = obuf + strlen (obuf); - cmp_type = *codep++ & 0xff; - if (cmp_type < 8) - { - char suffix1 = 'p', suffix2 = 's'; - used_prefixes |= (prefixes & PREFIX_REPZ); - if (prefixes & PREFIX_REPZ) - suffix1 = 's'; - else - { - used_prefixes |= (prefixes & PREFIX_DATA); - if (prefixes & PREFIX_DATA) - suffix2 = 'd'; - else - { - used_prefixes |= (prefixes & PREFIX_REPNZ); - if (prefixes & PREFIX_REPNZ) - suffix1 = 's', suffix2 = 'd'; - } - } - sprintf (scratchbuf, "cmp%s%c%c", - simd_cmp_op[cmp_type], suffix1, suffix2); - used_prefixes |= (prefixes & PREFIX_REPZ); - oappend (scratchbuf); - } - else - { - /* We have a bad extension byte. Clean up. */ - op1out[0] = '\0'; - op2out[0] = '\0'; - BadOp (); - } -} - -static void -SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED) -{ - /* Change movlps/movhps to movhlps/movlhps for 2 register operand - forms of these instructions. */ - if (mod == 3) - { - char *p = obuf + strlen (obuf); - *(p + 1) = '\0'; - *p = *(p - 1); - *(p - 1) = *(p - 2); - *(p - 2) = *(p - 3); - *(p - 3) = extrachar; - } -} - -static void -PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag) -{ - if (mod == 3 && reg == 1) - { - char *p = obuf + strlen (obuf); - - /* Override "sidt". */ - if (rm) - { - /* mwait %eax,%ecx */ - strcpy (p - 4, "mwait %eax,%ecx"); - } - else - { - /* monitor %eax,%ecx,%edx" */ - strcpy (p - 4, "monitor %eax,%ecx,%edx"); - } - - codep++; - } - else - OP_E (0, sizeflag); -} - -static void -INVLPG_Fixup (int bytemode, int sizeflag) -{ - if (*codep == 0xf8) - { - char *p = obuf + strlen (obuf); - - /* Override "invlpg". */ - strcpy (p - 6, "swapgs"); - codep++; - } - else - OP_E (bytemode, sizeflag); -} - -static void -BadOp (void) -{ - /* Throw away prefixes and 1st. opcode byte. */ - codep = insn_codep + 1; - oappend ("(bad)"); -} diff --git a/contrib/binutils/opcodes/ia64-asmtab.c b/contrib/binutils/opcodes/ia64-asmtab.c deleted file mode 100644 index 2465d39..0000000 --- a/contrib/binutils/opcodes/ia64-asmtab.c +++ /dev/null @@ -1,7562 +0,0 @@ -/* This file is automatically generated by ia64-gen. Do not edit! */ -static const char * const ia64_strings[] = { - "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and", - "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call", - "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16", - "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", - "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", - "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", - "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", - "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", - "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", - "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", - "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", - "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", - "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", - "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia", - "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8", - "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le", - "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many", - "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", - "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", - "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1", - "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1", - "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", - "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", - "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", - "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", - "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig", - "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2", - "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1", - "sxt2", "sxt4", "sync", "tak", "tbit", "thash", "tnat", "tpa", "trunc", - "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4", "uss", - "uus", "uuu", "w", "wexit", "wtop", "x", "xchg1", "xchg2", "xchg4", - "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", "zxt4", -}; - -static const struct ia64_dependency -dependencies[] = { - { "ALAT", 0, 0, 0, -1, NULL, }, - { "AR[BSP]", 26, 0, 2, 17, NULL, }, - { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, }, - { "AR[CFLG]", 26, 0, 2, 27, NULL, }, - { "AR[CCV]", 26, 0, 2, 32, NULL, }, - { "AR[CSD]", 26, 0, 2, 25, NULL, }, - { "AR[EC]", 26, 0, 2, 66, NULL, }, - { "AR[EFLAG]", 26, 0, 2, 24, NULL, }, - { "AR[FCR]", 26, 0, 2, 21, NULL, }, - { "AR[FDR]", 26, 0, 2, 30, NULL, }, - { "AR[FIR]", 26, 0, 2, 29, NULL, }, - { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].traps", 30, 0, 2, -1, NULL, }, - { "AR[FPSR].rv", 30, 0, 2, -1, NULL, }, - { "AR[FSR]", 26, 0, 2, 28, NULL, }, - { "AR[ITC]", 26, 0, 2, 44, NULL, }, - { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, }, - { "AR[LC]", 26, 0, 2, 65, NULL, }, - { "AR[PFS]", 26, 0, 2, 64, NULL, }, - { "AR[PFS]", 26, 0, 2, 64, NULL, }, - { "AR[PFS]", 26, 0, 0, 64, NULL, }, - { "AR[RNAT]", 26, 0, 2, 19, NULL, }, - { "AR[RSC]", 26, 0, 2, 16, NULL, }, - { "AR[SSD]", 26, 0, 2, 26, NULL, }, - { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, }, - { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, }, - { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 0, -1, NULL, }, - { "CPUID#", 7, 0, 5, -1, NULL, }, - { "CR[CMCV]", 27, 0, 3, 74, NULL, }, - { "CR[DCR]", 27, 0, 3, 0, NULL, }, - { "CR[EOI]", 27, 0, 7, 67, "SC Section 10.8.3.4", }, - { "CR[GPTA]", 27, 0, 3, 9, NULL, }, - { "CR[IFA]", 27, 0, 1, 20, NULL, }, - { "CR[IFA]", 27, 0, 3, 20, NULL, }, - { "CR[IFS]", 27, 0, 3, 23, NULL, }, - { "CR[IFS]", 27, 0, 1, 23, NULL, }, - { "CR[IFS]", 27, 0, 1, 23, NULL, }, - { "CR[IHA]", 27, 0, 3, 25, NULL, }, - { "CR[IIM]", 27, 0, 3, 24, NULL, }, - { "CR[IIP]", 27, 0, 3, 19, NULL, }, - { "CR[IIP]", 27, 0, 1, 19, NULL, }, - { "CR[IIPA]", 27, 0, 3, 22, NULL, }, - { "CR[IPSR]", 27, 0, 3, 16, NULL, }, - { "CR[IPSR]", 27, 0, 1, 16, NULL, }, - { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, }, - { "CR[ISR]", 27, 0, 3, 17, NULL, }, - { "CR[ITIR]", 27, 0, 3, 21, NULL, }, - { "CR[ITIR]", 27, 0, 1, 21, NULL, }, - { "CR[ITM]", 27, 0, 3, 1, NULL, }, - { "CR[ITV]", 27, 0, 3, 72, NULL, }, - { "CR[IVA]", 27, 0, 4, 2, NULL, }, - { "CR[IVR]", 27, 0, 7, 65, "SC Section 10.8.3.2", }, - { "CR[LID]", 27, 0, 7, 64, "SC Section 10.8.3.1", }, - { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, }, - { "CR[PMV]", 27, 0, 3, 73, NULL, }, - { "CR[PTA]", 27, 0, 3, 8, NULL, }, - { "CR[TPR]", 27, 0, 3, 66, NULL, }, - { "CR[TPR]", 27, 0, 7, 66, "SC Section 10.8.3.3", }, - { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, }, - { "DBR#", 11, 0, 2, -1, NULL, }, - { "DBR#", 11, 0, 3, -1, NULL, }, - { "DTC", 0, 0, 3, -1, NULL, }, - { "DTC", 0, 0, 2, -1, NULL, }, - { "DTC", 0, 0, 0, -1, NULL, }, - { "DTC", 0, 0, 2, -1, NULL, }, - { "DTC_LIMIT*", 0, 0, 2, -1, NULL, }, - { "DTR", 0, 0, 3, -1, NULL, }, - { "DTR", 0, 0, 2, -1, NULL, }, - { "DTR", 0, 0, 3, -1, NULL, }, - { "DTR", 0, 0, 0, -1, NULL, }, - { "DTR", 0, 0, 2, -1, NULL, }, - { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, }, - { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, }, - { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, }, - { "GR0", 14, 0, 0, -1, NULL, }, - { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, }, - { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, }, - { "IBR#", 16, 0, 2, -1, NULL, }, - { "InService*", 17, 0, 3, -1, NULL, }, - { "InService*", 17, 0, 2, -1, NULL, }, - { "InService*", 17, 0, 2, -1, NULL, }, - { "IP", 0, 0, 0, -1, NULL, }, - { "ITC", 0, 0, 4, -1, NULL, }, - { "ITC", 0, 0, 2, -1, NULL, }, - { "ITC", 0, 0, 0, -1, NULL, }, - { "ITC", 0, 0, 4, -1, NULL, }, - { "ITC", 0, 0, 2, -1, NULL, }, - { "ITC_LIMIT*", 0, 0, 2, -1, NULL, }, - { "ITR", 0, 0, 2, -1, NULL, }, - { "ITR", 0, 0, 4, -1, NULL, }, - { "ITR", 0, 0, 2, -1, NULL, }, - { "ITR", 0, 0, 0, -1, NULL, }, - { "ITR", 0, 0, 4, -1, NULL, }, - { "memory", 0, 0, 0, -1, NULL, }, - { "MSR#", 18, 0, 5, -1, NULL, }, - { "PKR#", 19, 0, 3, -1, NULL, }, - { "PKR#", 19, 0, 0, -1, NULL, }, - { "PKR#", 19, 0, 2, -1, NULL, }, - { "PKR#", 19, 0, 2, -1, NULL, }, - { "PMC#", 20, 0, 2, -1, NULL, }, - { "PMC#", 20, 0, 7, -1, "SC+3 Section 12.1.1", }, - { "PMD#", 21, 0, 2, -1, NULL, }, - { "PR0", 0, 0, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, }, - { "PR63", 24, 0, 2, -1, NULL, }, - { "PR63", 24, 0, 2, -1, NULL, }, - { "PR63", 24, 0, 0, -1, NULL, }, - { "PSR.ac", 28, 0, 1, 3, NULL, }, - { "PSR.ac", 28, 0, 3, 3, NULL, }, - { "PSR.ac", 28, 0, 2, 3, NULL, }, - { "PSR.be", 28, 0, 1, 1, NULL, }, - { "PSR.be", 28, 0, 3, 1, NULL, }, - { "PSR.be", 28, 0, 2, 1, NULL, }, - { "PSR.bn", 28, 0, 2, 44, NULL, }, - { "PSR.cpl", 28, 0, 1, 32, NULL, }, - { "PSR.da", 28, 0, 3, 38, NULL, }, - { "PSR.db", 28, 0, 3, 24, NULL, }, - { "PSR.db", 28, 0, 2, 24, NULL, }, - { "PSR.db", 28, 0, 3, 24, NULL, }, - { "PSR.dd", 28, 0, 3, 39, NULL, }, - { "PSR.dfh", 28, 0, 3, 19, NULL, }, - { "PSR.dfh", 28, 0, 2, 19, NULL, }, - { "PSR.dfl", 28, 0, 3, 18, NULL, }, - { "PSR.dfl", 28, 0, 2, 18, NULL, }, - { "PSR.di", 28, 0, 3, 22, NULL, }, - { "PSR.di", 28, 0, 2, 22, NULL, }, - { "PSR.dt", 28, 0, 3, 17, NULL, }, - { "PSR.dt", 28, 0, 2, 17, NULL, }, - { "PSR.ed", 28, 0, 3, 43, NULL, }, - { "PSR.i", 28, 0, 2, 14, NULL, }, - { "PSR.i", 28, 0, 3, 14, NULL, }, - { "PSR.ia", 28, 0, 0, 14, NULL, }, - { "PSR.ic", 28, 0, 2, 13, NULL, }, - { "PSR.ic", 28, 0, 3, 13, NULL, }, - { "PSR.id", 28, 0, 0, 14, NULL, }, - { "PSR.is", 28, 0, 0, 14, NULL, }, - { "PSR.it", 28, 0, 3, 14, NULL, }, - { "PSR.lp", 28, 0, 2, 25, NULL, }, - { "PSR.lp", 28, 0, 3, 25, NULL, }, - { "PSR.lp", 28, 0, 3, 25, NULL, }, - { "PSR.mc", 28, 0, 0, 35, NULL, }, - { "PSR.mfh", 28, 0, 2, 5, NULL, }, - { "PSR.mfl", 28, 0, 2, 4, NULL, }, - { "PSR.pk", 28, 0, 3, 15, NULL, }, - { "PSR.pk", 28, 0, 2, 15, NULL, }, - { "PSR.pp", 28, 0, 2, 21, NULL, }, - { "PSR.ri", 28, 0, 0, 41, NULL, }, - { "PSR.rt", 28, 0, 2, 27, NULL, }, - { "PSR.rt", 28, 0, 3, 27, NULL, }, - { "PSR.rt", 28, 0, 3, 27, NULL, }, - { "PSR.si", 28, 0, 2, 23, NULL, }, - { "PSR.si", 28, 0, 3, 23, NULL, }, - { "PSR.sp", 28, 0, 2, 20, NULL, }, - { "PSR.sp", 28, 0, 3, 20, NULL, }, - { "PSR.ss", 28, 0, 3, 40, NULL, }, - { "PSR.tb", 28, 0, 3, 26, NULL, }, - { "PSR.tb", 28, 0, 2, 26, NULL, }, - { "PSR.up", 28, 0, 2, 2, NULL, }, - { "RR#", 25, 0, 3, -1, NULL, }, - { "RR#", 25, 0, 2, -1, NULL, }, - { "RSE", 29, 0, 2, -1, NULL, }, - { "ALAT", 0, 1, 0, -1, NULL, }, - { "AR[BSP]", 26, 1, 2, 17, NULL, }, - { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, }, - { "AR[CCV]", 26, 1, 2, 32, NULL, }, - { "AR[CFLG]", 26, 1, 2, 27, NULL, }, - { "AR[CSD]", 26, 1, 2, 25, NULL, }, - { "AR[EC]", 26, 1, 2, 66, NULL, }, - { "AR[EFLAG]", 26, 1, 2, 24, NULL, }, - { "AR[FCR]", 26, 1, 2, 21, NULL, }, - { "AR[FDR]", 26, 1, 2, 30, NULL, }, - { "AR[FIR]", 26, 1, 2, 29, NULL, }, - { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, }, - { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, }, - { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, }, - { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, }, - { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].rv", 30, 1, 2, -1, NULL, }, - { "AR[FPSR].traps", 30, 1, 2, -1, NULL, }, - { "AR[FSR]", 26, 1, 2, 28, NULL, }, - { "AR[ITC]", 26, 1, 2, 44, NULL, }, - { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, }, - { "AR[LC]", 26, 1, 2, 65, NULL, }, - { "AR[PFS]", 26, 1, 0, 64, NULL, }, - { "AR[PFS]", 26, 1, 2, 64, NULL, }, - { "AR[PFS]", 26, 1, 2, 64, NULL, }, - { "AR[RNAT]", 26, 1, 2, 19, NULL, }, - { "AR[RSC]", 26, 1, 2, 16, NULL, }, - { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, }, - { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, }, - { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, }, - { "CFM", 6, 1, 2, -1, NULL, }, - { "CPUID#", 7, 1, 0, -1, NULL, }, - { "CR[CMCV]", 27, 1, 2, 74, NULL, }, - { "CR[DCR]", 27, 1, 2, 0, NULL, }, - { "CR[EOI]", 27, 1, 7, 67, "SC Section 10.8.3.4", }, - { "CR[GPTA]", 27, 1, 2, 9, NULL, }, - { "CR[IFA]", 27, 1, 2, 20, NULL, }, - { "CR[IFS]", 27, 1, 2, 23, NULL, }, - { "CR[IHA]", 27, 1, 2, 25, NULL, }, - { "CR[IIM]", 27, 1, 2, 24, NULL, }, - { "CR[IIP]", 27, 1, 2, 19, NULL, }, - { "CR[IIPA]", 27, 1, 2, 22, NULL, }, - { "CR[IPSR]", 27, 1, 2, 16, NULL, }, - { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, }, - { "CR[ISR]", 27, 1, 2, 17, NULL, }, - { "CR[ITIR]", 27, 1, 2, 21, NULL, }, - { "CR[ITM]", 27, 1, 2, 1, NULL, }, - { "CR[ITV]", 27, 1, 2, 72, NULL, }, - { "CR[IVA]", 27, 1, 2, 2, NULL, }, - { "CR[IVR]", 27, 1, 7, 65, "SC", }, - { "CR[LID]", 27, 1, 7, 64, "SC", }, - { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, }, - { "CR[PMV]", 27, 1, 2, 73, NULL, }, - { "CR[PTA]", 27, 1, 2, 8, NULL, }, - { "CR[TPR]", 27, 1, 2, 66, NULL, }, - { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, }, - { "DBR#", 11, 1, 2, -1, NULL, }, - { "DTC", 0, 1, 0, -1, NULL, }, - { "DTC", 0, 1, 2, -1, NULL, }, - { "DTC", 0, 1, 2, -1, NULL, }, - { "DTC_LIMIT*", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 0, -1, NULL, }, - { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, }, - { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, }, - { "GR0", 14, 1, 0, -1, NULL, }, - { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, }, - { "IBR#", 16, 1, 2, -1, NULL, }, - { "InService*", 17, 1, 7, -1, "SC", }, - { "IP", 0, 1, 0, -1, NULL, }, - { "ITC", 0, 1, 0, -1, NULL, }, - { "ITC", 0, 1, 2, -1, NULL, }, - { "ITC", 0, 1, 2, -1, NULL, }, - { "ITR", 0, 1, 2, -1, NULL, }, - { "ITR", 0, 1, 2, -1, NULL, }, - { "ITR", 0, 1, 0, -1, NULL, }, - { "memory", 0, 1, 0, -1, NULL, }, - { "MSR#", 18, 1, 7, -1, "SC", }, - { "PKR#", 19, 1, 0, -1, NULL, }, - { "PKR#", 19, 1, 0, -1, NULL, }, - { "PKR#", 19, 1, 2, -1, NULL, }, - { "PMC#", 20, 1, 2, -1, NULL, }, - { "PMD#", 21, 1, 2, -1, NULL, }, - { "PR0", 0, 1, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, - { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, - { "PR63", 24, 1, 0, -1, NULL, }, - { "PR63", 24, 1, 0, -1, NULL, }, - { "PR63", 24, 1, 2, -1, NULL, }, - { "PR63", 24, 1, 2, -1, NULL, }, - { "PSR.ac", 28, 1, 2, 3, NULL, }, - { "PSR.be", 28, 1, 2, 1, NULL, }, - { "PSR.bn", 28, 1, 2, 44, NULL, }, - { "PSR.cpl", 28, 1, 2, 32, NULL, }, - { "PSR.da", 28, 1, 2, 38, NULL, }, - { "PSR.db", 28, 1, 2, 24, NULL, }, - { "PSR.dd", 28, 1, 2, 39, NULL, }, - { "PSR.dfh", 28, 1, 2, 19, NULL, }, - { "PSR.dfl", 28, 1, 2, 18, NULL, }, - { "PSR.di", 28, 1, 2, 22, NULL, }, - { "PSR.dt", 28, 1, 2, 17, NULL, }, - { "PSR.ed", 28, 1, 2, 43, NULL, }, - { "PSR.i", 28, 1, 2, 14, NULL, }, - { "PSR.ia", 28, 1, 2, 14, NULL, }, - { "PSR.ic", 28, 1, 2, 13, NULL, }, - { "PSR.id", 28, 1, 2, 14, NULL, }, - { "PSR.is", 28, 1, 2, 14, NULL, }, - { "PSR.it", 28, 1, 2, 14, NULL, }, - { "PSR.lp", 28, 1, 2, 25, NULL, }, - { "PSR.mc", 28, 1, 2, 35, NULL, }, - { "PSR.mfh", 28, 1, 0, 5, NULL, }, - { "PSR.mfh", 28, 1, 2, 5, NULL, }, - { "PSR.mfh", 28, 1, 2, 5, NULL, }, - { "PSR.mfl", 28, 1, 0, 4, NULL, }, - { "PSR.mfl", 28, 1, 2, 4, NULL, }, - { "PSR.mfl", 28, 1, 2, 4, NULL, }, - { "PSR.pk", 28, 1, 2, 15, NULL, }, - { "PSR.pp", 28, 1, 2, 21, NULL, }, - { "PSR.ri", 28, 1, 2, 41, NULL, }, - { "PSR.rt", 28, 1, 2, 27, NULL, }, - { "PSR.si", 28, 1, 2, 23, NULL, }, - { "PSR.sp", 28, 1, 2, 20, NULL, }, - { "PSR.ss", 28, 1, 2, 40, NULL, }, - { "PSR.tb", 28, 1, 2, 26, NULL, }, - { "PSR.up", 28, 1, 2, 2, NULL, }, - { "RR#", 25, 1, 2, -1, NULL, }, - { "RSE", 29, 1, 2, -1, NULL, }, - { "PR63", 24, 2, 6, -1, NULL, }, -}; - -static const short dep0[] = { - 96, 267, 2139, 2312, -}; - -static const short dep1[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, 4135, - 20613, -}; - -static const short dep2[] = { - 96, 267, 2165, 2166, 2168, 2169, 2171, 2172, 2174, 2329, 2332, 2333, 2336, - 2337, 2340, 2341, -}; - -static const short dep3[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2329, 2332, - 2333, 2336, 2337, 2340, 2341, 4135, 20613, -}; - -static const short dep4[] = { - 96, 267, 22645, 22646, 22648, 22649, 22651, 22652, 22654, 22809, 22812, 22813, - 22816, 22817, 22820, 22821, -}; - -static const short dep5[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, - 22809, 22812, 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep6[] = { - 96, 267, 2165, 2166, 2168, 2169, 2171, 2172, 2174, 2329, 2330, 2332, 2334, - 2336, 2338, 2340, -}; - -static const short dep7[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2329, 2330, - 2333, 2334, 2337, 2338, 2341, 4135, 20613, -}; - -static const short dep8[] = { - 96, 267, 2165, 2166, 2168, 2169, 2171, 2172, 2174, 2329, 2331, 2333, 2335, - 2337, 2339, 2341, -}; - -static const short dep9[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2329, 2331, - 2332, 2335, 2336, 2339, 2340, 4135, 20613, -}; - -static const short dep10[] = { - 96, 267, 2165, 2166, 2168, 2169, 2171, 2172, 2174, 2329, 2330, 2331, 2332, - 2333, 2334, 2335, 2336, 2337, 2338, 2339, 2340, 2341, -}; - -static const short dep11[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2329, 2330, - 2331, 2332, 2333, 2334, 2335, 2336, 2337, 2338, 2339, 2340, 2341, 4135, 20613, - -}; - -static const short dep12[] = { - 96, 267, 2379, -}; - -static const short dep13[] = { - 40, 41, 96, 156, 174, 175, 267, 2082, 2083, 2165, 2167, 2168, 2170, 2171, - 2173, 2174, 4135, -}; - -static const short dep14[] = { - 96, 155, 267, 310, 2379, 28852, 29002, -}; - -static const short dep15[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, - 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 40, 41, 96, 144, 156, 174, 175, - 267, 310, 2082, 2083, 2165, 2167, 2168, 2170, 2171, 2173, 2174, 4135, 28852, - 29002, -}; - -static const short dep16[] = { - 1, 6, 40, 96, 134, 182, 187, 226, 267, 297, 2379, 28852, 29002, -}; - -static const short dep17[] = { - 1, 25, 27, 38, 40, 41, 96, 156, 158, 159, 174, 175, 182, 187, 226, 267, 297, - 2082, 2083, 2165, 2167, 2168, 2170, 2171, 2173, 2174, 4135, 28852, 29002, - -}; - -static const short dep18[] = { - 1, 40, 51, 96, 182, 226, 233, 267, 28852, 29002, -}; - -static const short dep19[] = { - 1, 38, 40, 41, 96, 153, 174, 182, 226, 233, 267, 4135, 28852, 29002, -}; - -static const short dep20[] = { - 40, 96, 226, 267, -}; - -static const short dep21[] = { - 96, 174, 226, 267, -}; - -static const short dep22[] = { - 1, 40, 96, 128, 129, 131, 132, 133, 134, 135, 138, 139, 140, 141, 142, 143, - 144, 145, 146, 147, 148, 150, 151, 152, 153, 154, 155, 156, 159, 160, 161, - 162, 163, 164, 165, 166, 169, 170, 171, 172, 173, 174, 175, 176, 177, 182, - 226, 267, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, - 307, 308, 309, 310, 311, 312, 313, 315, 316, 318, 319, 320, 321, 322, 323, - 324, 325, 326, 327, 328, 28852, 29002, -}; - -static const short dep23[] = { - 1, 38, 40, 41, 50, 51, 55, 58, 72, 96, 134, 174, 182, 226, 267, 294, 295, - 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, - 311, 312, 313, 315, 316, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, - 328, 4135, 28852, 29002, -}; - -static const short dep24[] = { - 96, 133, 267, 296, -}; - -static const short dep25[] = { - 96, 134, 174, 267, 296, -}; - -static const short dep26[] = { - 96, 134, 267, 297, -}; - -static const short dep27[] = { - 25, 26, 96, 97, 100, 104, 107, 134, 156, 174, 267, 297, -}; - -static const short dep28[] = { - 40, 41, 96, 174, 267, 2165, 2167, 2168, 2170, 2171, 2173, 2174, 4135, -}; - -static const short dep29[] = { - 1, 25, 40, 96, 182, 214, 215, 226, 267, 2082, 2270, 2273, 2379, 28852, 29002, - -}; - -static const short dep30[] = { - 1, 6, 38, 40, 41, 96, 134, 156, 174, 175, 182, 214, 216, 226, 267, 2082, 2083, - 2165, 2167, 2168, 2170, 2171, 2173, 2174, 2271, 2273, 4135, 28852, 29002, - -}; - -static const short dep31[] = { - 96, 267, -}; - -static const short dep32[] = { - 96, 174, 267, 2082, 2084, -}; - -static const short dep33[] = { - 40, 41, 96, 156, 174, 175, 267, 2165, 2167, 2168, 2170, 2171, 2173, 2174, - 4135, -}; - -static const short dep34[] = { - 6, 37, 38, 39, 96, 124, 125, 187, 226, 267, 292, 293, 2379, -}; - -static const short dep35[] = { - 6, 37, 40, 41, 96, 156, 174, 175, 187, 226, 267, 292, 293, 331, 2165, 2167, - 2168, 2170, 2171, 2173, 2174, 4135, -}; - -static const short dep36[] = { - 24, 96, 213, 267, 2379, -}; - -static const short dep37[] = { - 24, 40, 41, 96, 156, 174, 175, 213, 267, 2165, 2167, 2168, 2170, 2171, 2173, - 2174, 4135, -}; - -static const short dep38[] = { - 6, 24, 37, 38, 39, 96, 124, 125, 187, 213, 226, 267, 292, 293, 2379, -}; - -static const short dep39[] = { - 6, 24, 37, 40, 41, 96, 156, 174, 175, 187, 213, 226, 267, 292, 293, 331, 2165, - 2167, 2168, 2170, 2171, 2173, 2174, 4135, -}; - -static const short dep40[] = { - 1, 6, 38, 40, 41, 96, 134, 156, 174, 175, 182, 214, 216, 226, 267, 2165, 2167, - 2168, 2170, 2171, 2173, 2174, 2271, 2273, 4135, 28852, 29002, -}; - -static const short dep41[] = { - 96, 174, 267, -}; - -static const short dep42[] = { - 15, 96, 196, 197, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, - 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, - 22817, 22820, 22821, -}; - -static const short dep43[] = { - 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 22809, 22812, - 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep44[] = { - 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, 2135, 2310, - 18593, 18594, 18746, 18747, 18749, 18750, 22645, 22646, 22647, 22649, 22650, - 22652, 22653, 22809, 22812, 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep45[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, - 207, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2310, 4135, 16524, 16526, - 18746, 18748, 18749, 18751, 22809, 22812, 22813, 22816, 22817, 22820, 22821, - -}; - -static const short dep46[] = { - 16, 96, 199, 200, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, - 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, - 22817, 22820, 22821, -}; - -static const short dep47[] = { - 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 22809, 22812, - 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep48[] = { - 17, 96, 202, 203, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, - 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, - 22817, 22820, 22821, -}; - -static const short dep49[] = { - 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 22809, 22812, - 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep50[] = { - 18, 96, 205, 206, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, - 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, - 22817, 22820, 22821, -}; - -static const short dep51[] = { - 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 22809, 22812, - 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep52[] = { - 15, 96, 196, 197, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, - -}; - -static const short dep53[] = { - 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, -}; - -static const short dep54[] = { - 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, 2135, 2310, - 18593, 18594, 18746, 18747, 18749, 18750, -}; - -static const short dep55[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, - 207, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2310, 4135, 16524, 16526, - 18746, 18748, 18749, 18751, -}; - -static const short dep56[] = { - 16, 96, 199, 200, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, - -}; - -static const short dep57[] = { - 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, -}; - -static const short dep58[] = { - 17, 96, 202, 203, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, - -}; - -static const short dep59[] = { - 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, -}; - -static const short dep60[] = { - 18, 96, 205, 206, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, - -}; - -static const short dep61[] = { - 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, -}; - -static const short dep62[] = { - 96, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, -}; - -static const short dep63[] = { - 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2310, 4135, - 16524, 16526, 18746, 18748, 18749, 18751, -}; - -static const short dep64[] = { - 11, 96, 192, 267, -}; - -static const short dep65[] = { - 11, 40, 41, 96, 174, 192, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep66[] = { - 11, 40, 41, 96, 174, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep67[] = { - 12, 96, 193, 267, -}; - -static const short dep68[] = { - 11, 40, 41, 96, 174, 193, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep69[] = { - 13, 96, 194, 267, -}; - -static const short dep70[] = { - 11, 40, 41, 96, 174, 194, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep71[] = { - 14, 96, 195, 267, -}; - -static const short dep72[] = { - 11, 40, 41, 96, 174, 195, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep73[] = { - 15, 96, 197, 198, 267, -}; - -static const short dep74[] = { - 40, 41, 96, 174, 197, 198, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep75[] = { - 40, 41, 96, 174, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep76[] = { - 16, 96, 200, 201, 267, -}; - -static const short dep77[] = { - 40, 41, 96, 174, 200, 201, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep78[] = { - 17, 96, 203, 204, 267, -}; - -static const short dep79[] = { - 40, 41, 96, 174, 203, 204, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep80[] = { - 18, 96, 206, 207, 267, -}; - -static const short dep81[] = { - 40, 41, 96, 174, 206, 207, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep82[] = { - 15, 19, 20, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, - -}; - -static const short dep83[] = { - 15, 16, 19, 20, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, - -}; - -static const short dep84[] = { - 15, 17, 19, 20, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, - -}; - -static const short dep85[] = { - 15, 18, 19, 20, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, - -}; - -static const short dep86[] = { - 15, 96, 196, 197, 267, -}; - -static const short dep87[] = { - 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2165, 2166, 2169, 2172, 4135, - -}; - -static const short dep88[] = { - 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, -}; - -static const short dep89[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, - 207, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep90[] = { - 16, 96, 199, 200, 267, -}; - -static const short dep91[] = { - 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2165, 2166, 2169, 2172, 4135, - -}; - -static const short dep92[] = { - 17, 96, 202, 203, 267, -}; - -static const short dep93[] = { - 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2165, 2166, 2169, 2172, 4135, - -}; - -static const short dep94[] = { - 18, 96, 205, 206, 267, -}; - -static const short dep95[] = { - 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2165, 2166, 2169, 2172, 4135, - -}; - -static const short dep96[] = { - 15, 96, 196, 197, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, - 2333, 2336, 2337, 2340, 2341, -}; - -static const short dep97[] = { - 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2329, 2332, 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, - -}; - -static const short dep98[] = { - 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, 2165, 2166, - 2167, 2169, 2170, 2172, 2173, 2329, 2332, 2333, 2336, 2337, 2340, 2341, -}; - -static const short dep99[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, - 207, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2329, 2332, 2333, 2336, - 2337, 2340, 2341, 4135, 16524, 16526, -}; - -static const short dep100[] = { - 16, 96, 199, 200, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, - 2333, 2336, 2337, 2340, 2341, -}; - -static const short dep101[] = { - 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2329, 2332, 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, - -}; - -static const short dep102[] = { - 17, 96, 202, 203, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, - 2333, 2336, 2337, 2340, 2341, -}; - -static const short dep103[] = { - 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2329, 2332, 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, - -}; - -static const short dep104[] = { - 18, 96, 205, 206, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, - 2333, 2336, 2337, 2340, 2341, -}; - -static const short dep105[] = { - 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 2329, 2332, 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, - -}; - -static const short dep106[] = { - 15, 96, 196, 197, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, - 22812, 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep107[] = { - 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 4135, 16524, 16526, 22809, 22812, 22813, 22816, 22817, 22820, - 22821, -}; - -static const short dep108[] = { - 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, 22645, 22646, - 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, 22817, 22820, - 22821, -}; - -static const short dep109[] = { - 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, - 207, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 4135, 16524, 16526, 22809, - 22812, 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep110[] = { - 16, 96, 199, 200, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, - 22812, 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep111[] = { - 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 4135, 16524, 16526, 22809, 22812, 22813, 22816, 22817, 22820, - 22821, -}; - -static const short dep112[] = { - 17, 96, 202, 203, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, - 22812, 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep113[] = { - 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 4135, 16524, 16526, 22809, 22812, 22813, 22816, 22817, 22820, - 22821, -}; - -static const short dep114[] = { - 18, 96, 205, 206, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, - 22812, 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep115[] = { - 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2134, 2135, 2136, 2165, 2166, - 2169, 2172, 4135, 16524, 16526, 22809, 22812, 22813, 22816, 22817, 22820, - 22821, -}; - -static const short dep116[] = { - 96, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, 2333, 2336, - 2337, 2340, 2341, -}; - -static const short dep117[] = { - 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2329, 2332, - 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, -}; - -static const short dep118[] = { - 96, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, - 22816, 22817, 22820, 22821, -}; - -static const short dep119[] = { - 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 4135, 16524, - 16526, 22809, 22812, 22813, 22816, 22817, 22820, 22821, -}; - -static const short dep120[] = { - 19, 20, 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2310, - 4135, 16524, 16526, 18746, 18748, 18749, 18751, -}; - -static const short dep121[] = { - 40, 41, 96, 156, 174, 175, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, - 4135, 20613, -}; - -static const short dep122[] = { - 96, 267, 2083, 2084, 2271, 2272, -}; - -static const short dep123[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2270, 2272, - 4135, 20613, -}; - -static const short dep124[] = { - 40, 41, 96, 174, 267, 2082, 2084, 2165, 2166, 2169, 2172, 2312, 4135, 20613, - -}; - -static const short dep125[] = { - 96, 267, 14454, 14456, 14457, 14459, 14460, 14462, 14620, 14621, 14624, 14625, - 14628, 14629, -}; - -static const short dep126[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 4135, 14620, 14621, 14624, 14625, - 14628, 14629, 20613, 24693, 24694, 24697, 24700, -}; - -static const short dep127[] = { - 96, 121, 123, 124, 126, 267, 288, 289, 292, 293, -}; - -static const short dep128[] = { - 40, 41, 96, 174, 267, 288, 289, 292, 293, 4135, 24693, 24694, 24697, 24700, - -}; - -static const short dep129[] = { - 40, 41, 96, 174, 267, 2165, 2166, 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep130[] = { - 40, 41, 96, 118, 121, 124, 174, 267, 2312, 4135, 20613, 24693, -}; - -static const short dep131[] = { - 6, 24, 26, 27, 96, 187, 213, 216, 267, 2081, 2269, -}; - -static const short dep132[] = { - 40, 41, 96, 174, 187, 213, 215, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, - 2269, 4135, 20613, -}; - -static const short dep133[] = { - 6, 24, 25, 26, 40, 41, 96, 174, 267, 2081, 2165, 2166, 2169, 2172, 2312, 4135, - 20613, -}; - -static const short dep134[] = { - 0, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep135[] = { - 0, 96, 181, 267, -}; - -static const short dep136[] = { - 0, 40, 41, 96, 156, 174, 175, 181, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep137[] = { - 40, 41, 96, 174, 181, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep138[] = { - 2, 28, 96, 183, 217, 267, 28852, 29002, -}; - -static const short dep139[] = { - 1, 2, 28, 29, 96, 168, 169, 174, 183, 217, 267, 28852, 29002, -}; - -static const short dep140[] = { - 1, 28, 29, 38, 40, 41, 96, 168, 169, 174, 183, 217, 267, 4135, 28852, 29002, - -}; - -static const short dep141[] = { - 0, 40, 41, 96, 174, 181, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep142[] = { - 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, - 28, 29, 30, 31, 96, 182, 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, - 194, 195, 197, 198, 200, 201, 203, 204, 206, 207, 208, 209, 210, 211, 217, - 218, 219, 267, 2071, 2081, 2260, 2269, 28852, 29002, -}; - -static const short dep143[] = { - 29, 40, 41, 96, 134, 174, 182, 183, 184, 185, 186, 188, 189, 190, 191, 192, - 193, 194, 195, 197, 198, 200, 201, 203, 204, 206, 207, 208, 209, 210, 211, - 217, 218, 219, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2260, 2269, - 4135, 20613, 28852, 29002, -}; - -static const short dep144[] = { - 96, 267, 14463, 14465, 14466, 14468, 14497, 14498, 14513, 14630, 14631, 14651, - 14652, 14654, 14655, 14664, -}; - -static const short dep145[] = { - 40, 41, 96, 173, 174, 267, 2165, 2166, 2169, 2172, 4135, 14630, 14631, 14651, - 14652, 14654, 14655, 14664, -}; - -static const short dep146[] = { - 14463, 14465, 14466, 14468, 14497, 14498, 14513, 14630, 14631, 14651, 14652, - 14654, 14655, 14664, -}; - -static const short dep147[] = { - 173, 14630, 14631, 14651, 14652, 14654, 14655, 14664, -}; - -static const short dep148[] = { - 96, 267, 14464, 14465, 14467, 14468, 14476, 14477, 14478, 14479, 14480, 14481, - 14482, 14483, 14485, 14488, 14489, 14497, 14498, 14499, 14500, 14501, 14506, - 14507, 14508, 14509, 14513, 14630, 14631, 14637, 14638, 14639, 14640, 14642, - 14644, 14651, 14652, 14654, 14655, 14656, 14657, 14660, 14661, 14664, -}; - -static const short dep149[] = { - 40, 41, 72, 96, 134, 174, 267, 2165, 2166, 2169, 2172, 4135, 14630, 14631, - 14637, 14638, 14639, 14640, 14642, 14644, 14651, 14652, 14654, 14655, 14656, - 14657, 14660, 14661, 14664, -}; - -static const short dep150[] = { - 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, - 28, 29, 30, 31, 40, 41, 96, 134, 171, 174, 267, 2071, 2081, 2165, 2166, 2169, - 2172, 2312, 4135, 20613, 28852, -}; - -static const short dep151[] = { - 43, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, 56, 57, 58, 60, 61, 62, 63, - 64, 65, 67, 69, 70, 71, 72, 93, 95, 96, 228, 229, 230, 231, 232, 233, 234, - 235, 236, 237, 238, 240, 241, 242, 243, 244, 246, 248, 249, 250, 266, 267, - 2116, 2295, -}; - -static const short dep152[] = { - 40, 41, 95, 96, 134, 153, 174, 228, 229, 230, 231, 232, 233, 234, 235, 236, - 237, 238, 240, 241, 242, 243, 244, 246, 248, 249, 250, 266, 267, 2137, 2138, - 2139, 2165, 2166, 2169, 2172, 2295, 4135, 20613, -}; - -static const short dep153[] = { - 59, 94, 96, 239, 266, 267, 2139, 2312, -}; - -static const short dep154[] = { - 40, 41, 43, 44, 46, 48, 49, 51, 52, 53, 54, 56, 57, 60, 61, 63, 64, 65, 66, - 67, 69, 70, 71, 93, 94, 96, 134, 153, 174, 239, 266, 267, 2107, 2116, 2165, - 2166, 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep155[] = { - 2, 28, 41, 96, 183, 217, 226, 267, 2139, 2312, 28852, 29002, -}; - -static const short dep156[] = { - 2, 25, 26, 28, 29, 38, 40, 41, 96, 168, 169, 174, 183, 217, 226, 267, 2312, - 4135, 20613, 28852, 29002, -}; - -static const short dep157[] = { - 96, 128, 129, 131, 132, 136, 137, 140, 141, 142, 143, 144, 145, 146, 147, - 149, 152, 153, 157, 158, 161, 162, 163, 164, 165, 167, 168, 170, 171, 172, - 173, 175, 176, 177, 267, 294, 295, 299, 301, 302, 303, 304, 306, 308, 312, - 315, 316, 318, 319, 320, 321, 323, 324, 325, 327, 328, -}; - -static const short dep158[] = { - 40, 41, 72, 96, 134, 174, 267, 294, 295, 299, 301, 302, 303, 304, 306, 308, - 312, 315, 316, 318, 319, 320, 321, 323, 324, 325, 327, 328, 2137, 2138, 2139, - 2165, 2166, 2169, 2172, 4135, 20613, -}; - -static const short dep159[] = { - 96, 127, 129, 130, 132, 161, 162, 177, 267, 294, 295, 315, 316, 318, 319, - 328, -}; - -static const short dep160[] = { - 40, 41, 96, 173, 174, 267, 294, 295, 315, 316, 318, 319, 328, 2137, 2138, - 2139, 2165, 2166, 2169, 2172, 4135, 20613, -}; - -static const short dep161[] = { - 40, 41, 96, 129, 132, 134, 137, 138, 141, 143, 145, 147, 149, 150, 152, 156, - 157, 159, 160, 161, 162, 164, 165, 167, 169, 170, 172, 174, 176, 177, 267, - 2165, 2166, 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep162[] = { - 40, 41, 96, 129, 132, 161, 162, 174, 177, 267, 2165, 2166, 2169, 2172, 2312, - 4135, 20613, -}; - -static const short dep163[] = { - 40, 41, 75, 76, 81, 83, 96, 110, 134, 163, 174, 178, 267, 2137, 2138, 2139, - 2165, 2166, 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep164[] = { - 40, 41, 75, 76, 81, 83, 96, 110, 134, 135, 136, 138, 139, 163, 174, 178, 267, - 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, -}; - -static const short dep165[] = { - 76, 77, 96, 100, 101, 254, 255, 267, 269, 270, -}; - -static const short dep166[] = { - 40, 41, 47, 62, 77, 79, 85, 96, 98, 101, 134, 153, 174, 178, 254, 255, 267, - 269, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, -}; - -static const short dep167[] = { - 40, 41, 47, 62, 77, 79, 96, 98, 101, 103, 105, 134, 153, 174, 178, 254, 255, - 267, 269, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, -}; - -static const short dep168[] = { - 96, 267, 12466, 12467, 12617, -}; - -static const short dep169[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, - 12617, 20613, -}; - -static const short dep170[] = { - 96, 267, 6218, 6219, 6396, -}; - -static const short dep171[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, - 6396, 20613, -}; - -static const short dep172[] = { - 96, 267, 6236, 6409, -}; - -static const short dep173[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, - 6409, 20613, -}; - -static const short dep174[] = { - 96, 267, 6254, 6255, 6256, 6257, 6420, 6422, 8469, -}; - -static const short dep175[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, - 6257, 6421, 6422, 8303, 8468, 20613, -}; - -static const short dep176[] = { - 96, 267, 6258, 6259, 6423, -}; - -static const short dep177[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, - 6423, 20613, -}; - -static const short dep178[] = { - 96, 267, 6260, 6424, -}; - -static const short dep179[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, - 6424, 20613, -}; - -static const short dep180[] = { - 96, 267, 10349, 10515, -}; - -static const short dep181[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, - 10515, 20613, -}; - -static const short dep182[] = { - 76, 77, 81, 82, 96, 100, 101, 254, 255, 257, 258, 267, 269, 270, -}; - -static const short dep183[] = { - 40, 41, 47, 62, 77, 79, 82, 85, 96, 98, 101, 134, 153, 174, 178, 254, 255, - 257, 259, 267, 269, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, - -}; - -static const short dep184[] = { - 76, 77, 96, 100, 101, 103, 104, 254, 255, 267, 269, 270, 271, 272, -}; - -static const short dep185[] = { - 40, 41, 47, 62, 77, 79, 96, 98, 101, 103, 105, 134, 153, 174, 178, 254, 255, - 267, 269, 270, 271, 272, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, - -}; - -static const short dep186[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, - 4135, 12467, 20613, -}; - -static const short dep187[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, - 4135, 6218, 20613, -}; - -static const short dep188[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, - 4135, 6236, 20613, -}; - -static const short dep189[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, - 4135, 6256, 8302, 20613, -}; - -static const short dep190[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, - 4135, 6258, 20613, -}; - -static const short dep191[] = { - 40, 41, 96, 134, 173, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, - 2312, 4135, 6259, 6260, 20613, -}; - -static const short dep192[] = { - 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, - 4135, 10349, 20613, -}; - -static const short dep193[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, 4135, - 6186, 20613, -}; - -static const short dep194[] = { - 76, 78, 79, 96, 97, 98, 99, 253, 254, 267, 268, 269, -}; - -static const short dep195[] = { - 40, 41, 77, 78, 82, 84, 96, 99, 101, 103, 106, 134, 174, 178, 253, 255, 267, - 268, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, -}; - -static const short dep196[] = { - 76, 78, 79, 80, 96, 97, 98, 99, 102, 253, 254, 256, 267, 268, 269, -}; - -static const short dep197[] = { - 40, 41, 77, 78, 80, 82, 84, 96, 99, 101, 102, 103, 106, 134, 174, 178, 253, - 255, 256, 267, 268, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, - -}; - -static const short dep198[] = { - 76, 78, 79, 83, 84, 85, 96, 97, 98, 99, 253, 254, 259, 260, 267, 268, 269, - -}; - -static const short dep199[] = { - 40, 41, 77, 78, 82, 84, 96, 99, 101, 134, 174, 178, 253, 255, 258, 260, 267, - 268, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, -}; - -static const short dep200[] = { - 76, 78, 79, 96, 97, 98, 99, 105, 106, 107, 253, 254, 267, 268, 269, 272, 273, - -}; - -static const short dep201[] = { - 40, 41, 77, 78, 96, 99, 101, 103, 106, 134, 174, 178, 253, 255, 267, 268, - 270, 271, 273, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, -}; - -static const short dep202[] = { - 40, 41, 46, 70, 96, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, - 2312, 4135, 20613, -}; - -static const short dep203[] = { - 40, 41, 96, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, - 4135, 20613, -}; - -static const short dep204[] = { - 40, 41, 76, 81, 83, 96, 134, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, - 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep205[] = { - 40, 41, 96, 156, 174, 175, 267, 2134, 2135, 2136, 2137, 2138, 2139, 2165, - 2166, 2169, 2172, 4135, 16524, 16526, 20613, -}; - -static const short dep206[] = { - 40, 41, 76, 81, 83, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, - 4135, 20613, -}; - -static const short dep207[] = { - 40, 41, 77, 78, 96, 99, 134, 174, 253, 255, 267, 268, 270, 2137, 2138, 2139, - 2165, 2166, 2169, 2172, 4135, 20613, -}; - -static const short dep208[] = { - 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, 138, - 139, 146, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, - 4135, 20613, -}; - -static const short dep209[] = { - 5, 96, 186, 267, 2139, 2312, -}; - -static const short dep210[] = { - 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, 138, - 139, 146, 163, 174, 178, 186, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, - 2312, 4135, 20613, -}; - -static const short dep211[] = { - 40, 41, 44, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, - 138, 139, 146, 148, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, - 2172, 2312, 4135, 20613, -}; - -static const short dep212[] = { - 0, 96, 181, 267, 2139, 2312, -}; - -static const short dep213[] = { - 0, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, - 138, 139, 146, 163, 174, 178, 181, 267, 2137, 2138, 2139, 2165, 2166, 2169, - 2172, 2312, 4135, 20613, -}; - -static const short dep214[] = { - 0, 40, 41, 44, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, - 136, 138, 139, 146, 148, 163, 174, 178, 181, 267, 2137, 2138, 2139, 2165, - 2166, 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep215[] = { - 31, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, - 138, 139, 146, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, - 2312, 4135, 20613, -}; - -static const short dep216[] = { - 0, 96, 181, 267, 2312, 26714, -}; - -static const short dep217[] = { - 0, 96, 108, 181, 267, 274, -}; - -static const short dep218[] = { - 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, - 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, 2166, 2169, - 2172, 4135, 20613, -}; - -static const short dep219[] = { - 0, 5, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, - 138, 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, 2166, - 2169, 2172, 4135, 20613, -}; - -static const short dep220[] = { - 0, 31, 96, 108, 181, 219, 267, 274, -}; - -static const short dep221[] = { - 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, - 139, 146, 163, 174, 178, 181, 219, 267, 274, 2137, 2138, 2139, 2165, 2166, - 2169, 2172, 4135, 20613, -}; - -static const short dep222[] = { - 0, 96, 108, 181, 267, 274, 2139, 2312, -}; - -static const short dep223[] = { - 0, 4, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, - 136, 138, 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, - 2166, 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep224[] = { - 0, 4, 5, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, - 136, 138, 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, - 2166, 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep225[] = { - 0, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, - 138, 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, 2166, - 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep226[] = { - 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2312, 4135, - 16524, 16526, 20613, -}; - -static const short dep227[] = { - 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, - 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, 2166, 2169, - 2172, 2312, 4135, 20613, -}; - -static const short dep228[] = { - 0, 31, 96, 108, 181, 219, 267, 274, 2139, 2312, -}; - -static const short dep229[] = { - 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, - 139, 146, 163, 174, 178, 181, 219, 267, 274, 2137, 2138, 2139, 2165, 2166, - 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep230[] = { - 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, 138, - 139, 146, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2310, - 4135, 16524, 16526, 18746, 18748, 18749, 18751, 20613, -}; - -static const short dep231[] = { - 40, 41, 44, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, - 138, 139, 146, 148, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, - 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 20613, -}; - -static const short dep232[] = { - 0, 96, 181, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, -}; - -static const short dep233[] = { - 0, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, - 138, 139, 146, 163, 174, 178, 181, 267, 2137, 2138, 2139, 2165, 2166, 2169, - 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 20613, -}; - -static const short dep234[] = { - 0, 40, 41, 44, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, - 136, 138, 139, 146, 148, 163, 174, 178, 181, 267, 2137, 2138, 2139, 2165, - 2166, 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 20613, - -}; - -static const short dep235[] = { - 0, 96, 181, 267, 2136, 2310, 18593, 18594, 18746, 18747, 18749, 18750, -}; - -static const short dep236[] = { - 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, - 139, 146, 163, 174, 178, 181, 267, 274, 2134, 2135, 2136, 2137, 2138, 2139, - 2165, 2166, 2169, 2172, 4135, 16524, 16526, 20613, -}; - -static const short dep237[] = { - 40, 41, 75, 96, 134, 148, 174, 267, 2165, 2166, 2169, 2172, 4135, -}; - -static const short dep238[] = { - 40, 41, 75, 96, 134, 135, 139, 148, 174, 267, 2165, 2166, 2169, 2172, 4135, - -}; - -static const short dep239[] = { - 40, 41, 75, 96, 134, 148, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, - 2312, 4135, 20613, -}; - -static const short dep240[] = { - 40, 41, 75, 96, 134, 135, 139, 148, 174, 267, 2137, 2138, 2139, 2165, 2166, - 2169, 2172, 2312, 4135, 20613, -}; - -static const short dep241[] = { - 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2310, 4135, - 16524, 16526, 18746, 18748, 18749, 18751, 20613, -}; - -static const short dep242[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, - 22, 24, 26, 27, 28, 29, 30, 31, 96, 182, 183, 184, 185, 186, 187, 188, 189, - 190, 191, 192, 193, 194, 195, 197, 198, 200, 201, 203, 204, 206, 207, 208, - 209, 210, 211, 213, 216, 217, 218, 219, 267, 2071, 2081, 2139, 2260, 2269, - 2312, 28852, 29002, -}; - -static const short dep243[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, - 22, 24, 25, 26, 28, 29, 30, 31, 40, 41, 96, 134, 171, 174, 182, 183, 184, - 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 197, 198, 200, 201, - 203, 204, 206, 207, 208, 209, 210, 211, 213, 215, 217, 218, 219, 267, 2071, - 2081, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2260, 2269, 2312, 4135, 20613, - 28852, 29002, -}; - -#define NELS(X) (sizeof(X)/sizeof(X[0])) -static const struct ia64_opcode_dependency -op_dependencies[] = { - { NELS(dep1), dep1, NELS(dep0), dep0, }, - { NELS(dep3), dep3, NELS(dep2), dep2, }, - { NELS(dep5), dep5, NELS(dep4), dep4, }, - { NELS(dep7), dep7, NELS(dep6), dep6, }, - { NELS(dep9), dep9, NELS(dep8), dep8, }, - { NELS(dep11), dep11, NELS(dep10), dep10, }, - { NELS(dep13), dep13, NELS(dep12), dep12, }, - { NELS(dep15), dep15, NELS(dep14), dep14, }, - { NELS(dep17), dep17, NELS(dep16), dep16, }, - { NELS(dep19), dep19, NELS(dep18), dep18, }, - { NELS(dep21), dep21, NELS(dep20), dep20, }, - { NELS(dep23), dep23, NELS(dep22), dep22, }, - { NELS(dep25), dep25, NELS(dep24), dep24, }, - { NELS(dep27), dep27, NELS(dep26), dep26, }, - { NELS(dep28), dep28, NELS(dep12), dep12, }, - { NELS(dep30), dep30, NELS(dep29), dep29, }, - { NELS(dep32), dep32, NELS(dep31), dep31, }, - { NELS(dep33), dep33, NELS(dep12), dep12, }, - { NELS(dep35), dep35, NELS(dep34), dep34, }, - { NELS(dep37), dep37, NELS(dep36), dep36, }, - { NELS(dep39), dep39, NELS(dep38), dep38, }, - { NELS(dep40), dep40, NELS(dep29), dep29, }, - { NELS(dep41), dep41, NELS(dep31), dep31, }, - { NELS(dep43), dep43, NELS(dep42), dep42, }, - { NELS(dep45), dep45, NELS(dep44), dep44, }, - { NELS(dep47), dep47, NELS(dep46), dep46, }, - { NELS(dep49), dep49, NELS(dep48), dep48, }, - { NELS(dep51), dep51, NELS(dep50), dep50, }, - { NELS(dep53), dep53, NELS(dep52), dep52, }, - { NELS(dep55), dep55, NELS(dep54), dep54, }, - { NELS(dep57), dep57, NELS(dep56), dep56, }, - { NELS(dep59), dep59, NELS(dep58), dep58, }, - { NELS(dep61), dep61, NELS(dep60), dep60, }, - { NELS(dep63), dep63, NELS(dep62), dep62, }, - { NELS(dep65), dep65, NELS(dep64), dep64, }, - { NELS(dep66), dep66, NELS(dep31), dep31, }, - { NELS(dep68), dep68, NELS(dep67), dep67, }, - { NELS(dep70), dep70, NELS(dep69), dep69, }, - { NELS(dep72), dep72, NELS(dep71), dep71, }, - { NELS(dep74), dep74, NELS(dep73), dep73, }, - { NELS(dep75), dep75, NELS(dep31), dep31, }, - { NELS(dep77), dep77, NELS(dep76), dep76, }, - { NELS(dep79), dep79, NELS(dep78), dep78, }, - { NELS(dep81), dep81, NELS(dep80), dep80, }, - { NELS(dep82), dep82, NELS(dep31), dep31, }, - { NELS(dep83), dep83, NELS(dep31), dep31, }, - { NELS(dep84), dep84, NELS(dep31), dep31, }, - { NELS(dep85), dep85, NELS(dep31), dep31, }, - { NELS(dep87), dep87, NELS(dep86), dep86, }, - { NELS(dep89), dep89, NELS(dep88), dep88, }, - { NELS(dep91), dep91, NELS(dep90), dep90, }, - { NELS(dep93), dep93, NELS(dep92), dep92, }, - { NELS(dep95), dep95, NELS(dep94), dep94, }, - { NELS(dep97), dep97, NELS(dep96), dep96, }, - { NELS(dep99), dep99, NELS(dep98), dep98, }, - { NELS(dep101), dep101, NELS(dep100), dep100, }, - { NELS(dep103), dep103, NELS(dep102), dep102, }, - { NELS(dep105), dep105, NELS(dep104), dep104, }, - { NELS(dep107), dep107, NELS(dep106), dep106, }, - { NELS(dep109), dep109, NELS(dep108), dep108, }, - { NELS(dep111), dep111, NELS(dep110), dep110, }, - { NELS(dep113), dep113, NELS(dep112), dep112, }, - { NELS(dep115), dep115, NELS(dep114), dep114, }, - { NELS(dep117), dep117, NELS(dep116), dep116, }, - { NELS(dep119), dep119, NELS(dep118), dep118, }, - { NELS(dep120), dep120, NELS(dep62), dep62, }, - { NELS(dep121), dep121, NELS(dep31), dep31, }, - { NELS(dep123), dep123, NELS(dep122), dep122, }, - { NELS(dep124), dep124, NELS(dep0), dep0, }, - { NELS(dep126), dep126, NELS(dep125), dep125, }, - { NELS(dep128), dep128, NELS(dep127), dep127, }, - { NELS(dep129), dep129, NELS(dep0), dep0, }, - { NELS(dep130), dep130, NELS(dep0), dep0, }, - { NELS(dep132), dep132, NELS(dep131), dep131, }, - { NELS(dep133), dep133, NELS(dep0), dep0, }, - { NELS(dep134), dep134, NELS(dep31), dep31, }, - { NELS(dep136), dep136, NELS(dep135), dep135, }, - { NELS(dep137), dep137, NELS(dep135), dep135, }, - { NELS(dep139), dep139, NELS(dep138), dep138, }, - { NELS(dep140), dep140, NELS(dep138), dep138, }, - { NELS(dep141), dep141, NELS(dep135), dep135, }, - { NELS(dep143), dep143, NELS(dep142), dep142, }, - { NELS(dep145), dep145, NELS(dep144), dep144, }, - { NELS(dep147), dep147, NELS(dep146), dep146, }, - { NELS(dep149), dep149, NELS(dep148), dep148, }, - { NELS(dep150), dep150, NELS(dep0), dep0, }, - { NELS(dep152), dep152, NELS(dep151), dep151, }, - { NELS(dep154), dep154, NELS(dep153), dep153, }, - { NELS(dep156), dep156, NELS(dep155), dep155, }, - { NELS(dep158), dep158, NELS(dep157), dep157, }, - { NELS(dep160), dep160, NELS(dep159), dep159, }, - { NELS(dep161), dep161, NELS(dep0), dep0, }, - { NELS(dep162), dep162, NELS(dep0), dep0, }, - { NELS(dep163), dep163, NELS(dep0), dep0, }, - { NELS(dep164), dep164, NELS(dep31), dep31, }, - { NELS(dep166), dep166, NELS(dep165), dep165, }, - { NELS(dep167), dep167, NELS(dep165), dep165, }, - { NELS(dep169), dep169, NELS(dep168), dep168, }, - { NELS(dep171), dep171, NELS(dep170), dep170, }, - { NELS(dep173), dep173, NELS(dep172), dep172, }, - { NELS(dep175), dep175, NELS(dep174), dep174, }, - { NELS(dep177), dep177, NELS(dep176), dep176, }, - { NELS(dep179), dep179, NELS(dep178), dep178, }, - { NELS(dep181), dep181, NELS(dep180), dep180, }, - { NELS(dep183), dep183, NELS(dep182), dep182, }, - { NELS(dep185), dep185, NELS(dep184), dep184, }, - { NELS(dep186), dep186, NELS(dep0), dep0, }, - { NELS(dep187), dep187, NELS(dep0), dep0, }, - { NELS(dep188), dep188, NELS(dep0), dep0, }, - { NELS(dep189), dep189, NELS(dep0), dep0, }, - { NELS(dep190), dep190, NELS(dep0), dep0, }, - { NELS(dep191), dep191, NELS(dep0), dep0, }, - { NELS(dep192), dep192, NELS(dep0), dep0, }, - { NELS(dep193), dep193, NELS(dep0), dep0, }, - { NELS(dep195), dep195, NELS(dep194), dep194, }, - { NELS(dep197), dep197, NELS(dep196), dep196, }, - { NELS(dep199), dep199, NELS(dep198), dep198, }, - { NELS(dep201), dep201, NELS(dep200), dep200, }, - { NELS(dep202), dep202, NELS(dep0), dep0, }, - { NELS(dep203), dep203, NELS(dep0), dep0, }, - { NELS(dep204), dep204, NELS(dep0), dep0, }, - { NELS(dep205), dep205, NELS(dep31), dep31, }, - { NELS(dep206), dep206, NELS(dep31), dep31, }, - { NELS(dep207), dep207, NELS(dep194), dep194, }, - { NELS(dep208), dep208, NELS(dep0), dep0, }, - { NELS(dep210), dep210, NELS(dep209), dep209, }, - { NELS(dep211), dep211, NELS(dep0), dep0, }, - { NELS(dep213), dep213, NELS(dep212), dep212, }, - { NELS(dep214), dep214, NELS(dep212), dep212, }, - { NELS(dep215), dep215, NELS(dep0), dep0, }, - { NELS(dep213), dep213, NELS(dep216), dep216, }, - { NELS(dep218), dep218, NELS(dep217), dep217, }, - { NELS(dep219), dep219, NELS(dep217), dep217, }, - { NELS(dep221), dep221, NELS(dep220), dep220, }, - { NELS(dep223), dep223, NELS(dep222), dep222, }, - { NELS(dep224), dep224, NELS(dep222), dep222, }, - { NELS(dep225), dep225, NELS(dep222), dep222, }, - { NELS(dep226), dep226, NELS(dep0), dep0, }, - { NELS(dep227), dep227, NELS(dep222), dep222, }, - { NELS(dep229), dep229, NELS(dep228), dep228, }, - { NELS(dep230), dep230, NELS(dep62), dep62, }, - { NELS(dep231), dep231, NELS(dep62), dep62, }, - { NELS(dep233), dep233, NELS(dep232), dep232, }, - { NELS(dep234), dep234, NELS(dep232), dep232, }, - { NELS(dep233), dep233, NELS(dep235), dep235, }, - { NELS(dep236), dep236, NELS(dep217), dep217, }, - { NELS(dep237), dep237, NELS(dep31), dep31, }, - { NELS(dep238), dep238, NELS(dep31), dep31, }, - { NELS(dep239), dep239, NELS(dep0), dep0, }, - { NELS(dep240), dep240, NELS(dep0), dep0, }, - { NELS(dep241), dep241, NELS(dep62), dep62, }, - { 0, NULL, 0, NULL, }, - { NELS(dep243), dep243, NELS(dep242), dep242, }, -}; - -static const struct ia64_completer_table -completer_table[] = { - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 88 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 455, -1, 0, 1, 6 }, - { 0x0, 0x0, 0, 518, -1, 0, 1, 17 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 151 }, - { 0x0, 0x0, 0, 617, -1, 0, 1, 17 }, - { 0x0, 0x0, 0, 1836, -1, 0, 1, 10 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 9 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 13 }, - { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, 2014, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, 958, -1, 0, 1, 122 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 44 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 40 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 78 }, - { 0x0, 0x0, 0, 1878, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2057, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 1882, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, 1884, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2066, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2069, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2091, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2094, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 35 }, - { 0x0, 0x0, 0, 2102, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 1181, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 40 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 151 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 77 }, - { 0x0, 0x0, 0, 1216, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1225, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1234, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1236, -1, 0, 1, 125 }, - { 0x0, 0x0, 0, 1245, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1254, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1263, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1272, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1281, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1290, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1300, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1310, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1320, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1329, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1335, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1341, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1347, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1353, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1359, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1365, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1371, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1377, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1383, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1389, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1395, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1401, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1407, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1413, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1419, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1425, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1431, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 1435, -1, 0, 1, 146 }, - { 0x0, 0x0, 0, 1439, -1, 0, 1, 148 }, - { 0x0, 0x0, 0, 1443, -1, 0, 1, 148 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 79 }, - { 0x0, 0x0, 0, 253, -1, 0, 1, 40 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 67 }, - { 0x1, 0x1, 0, 984, -1, 20, 1, 67 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 68 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 69 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 71 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 72 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 86 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 87 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 89 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 90 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 91 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 92 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 97 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 98 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 99 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 100 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 101 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 102 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 103 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 106 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 107 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 108 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 109 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 110 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 111 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 112 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 113 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 152 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 152 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 152 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 71 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 151 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2394, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2395, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 1848, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 1849, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2409, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, 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234, 771, 881, 0, 0, -1 }, - { 0x1, 0x1, 234, 772, 635, 33, 1, 17 }, - { 0x1, 0x1, 234, 773, 639, 33, 1, 17 }, - { 0x0, 0x0, 234, 774, 885, 0, 0, -1 }, - { 0x1, 0x1, 234, 775, 651, 33, 1, 21 }, - { 0x0, 0x0, 235, 2323, 822, 0, 0, -1 }, - { 0x0, 0x0, 235, 2324, 830, 0, 0, -1 }, - { 0x0, 0x0, 235, 2325, 826, 0, 0, -1 }, - { 0x0, 0x0, 235, 2326, 480, 0, 1, 6 }, - { 0x1, 0x1, 235, 2327, 488, 6, 1, 7 }, - { 0x0, 0x0, 235, 2328, 484, 0, 1, 6 }, - { 0x0, 0x0, 235, 2329, 834, 0, 0, -1 }, - { 0x0, 0x0, 235, 2330, 500, 0, 1, 8 }, - { 0x0, 0x0, 235, 2331, 838, 0, 0, -1 }, - { 0x0, 0x0, 235, 2332, 512, 0, 1, 15 }, - { 0x0, 0x0, 235, 2333, 843, 0, 0, -1 }, - { 0x0, 0x0, 235, 2334, 847, 0, 0, -1 }, - { 0x0, 0x0, 235, 2335, 535, 0, 1, 17 }, - { 0x0, 0x0, 235, 2336, 539, 0, 1, 17 }, - { 0x0, 0x0, 235, 2337, 851, 0, 0, -1 }, - { 0x0, 0x0, 235, 2338, 855, 0, 0, -1 }, - { 0x0, 0x0, 235, 2339, 559, 0, 1, 18 }, - { 0x1, 0x1, 235, 2340, 563, 6, 1, 18 }, - { 0x0, 0x0, 235, 2341, 859, 0, 0, -1 }, - { 0x0, 0x0, 235, 2342, 575, 0, 1, 19 }, - { 0x0, 0x0, 235, 2343, 863, 0, 0, -1 }, - { 0x0, 0x0, 235, 2344, 867, 0, 0, -1 }, - { 0x0, 0x0, 235, 2345, 595, 0, 1, 20 }, - { 0x1, 0x1, 235, 2346, 599, 6, 1, 20 }, - { 0x0, 0x0, 235, 2347, 871, 0, 0, -1 }, - { 0x0, 0x0, 235, 2348, 611, 0, 1, 21 }, - { 0x0, 0x0, 235, 2349, 876, 0, 0, -1 }, - { 0x0, 0x0, 235, 2350, 880, 0, 0, -1 }, - { 0x0, 0x0, 235, 2351, 634, 0, 1, 17 }, - { 0x0, 0x0, 235, 2352, 638, 0, 1, 17 }, - { 0x0, 0x0, 235, 2353, 884, 0, 0, -1 }, - { 0x0, 0x0, 235, 2354, 650, 0, 1, 21 }, - { 0x1, 0x1, 235, 776, 973, 27, 1, 16 }, - { 0x0, 0x0, 235, 777, 971, 0, 1, 16 }, - { 0x0, 0x0, 235, 1021, 975, 0, 1, 22 }, - { 0x0, 0x1, 235, 983, 981, 20, 1, 67 }, - { 0x0, 0x0, 235, 110, 979, 0, 1, 67 }, - { 0x1, 0x1, 238, -1, -1, 29, 1, 0 }, - { 0x0, 0x0, 238, -1, -1, 0, 1, 0 }, - { 0x1, 0x1, 238, 2495, -1, 27, 1, 0 }, - { 0x1, 0x1, 238, 2496, -1, 27, 1, 0 }, - { 0x1, 0x1, 238, 2497, -1, 27, 1, 0 }, - { 0x1, 0x1, 238, 2498, -1, 27, 1, 0 }, - { 0x0, 0x0, 260, -1, 1952, 0, 0, -1 }, - { 0x0, 0x0, 260, -1, 1954, 0, 0, -1 }, - { 0x1, 0x1, 260, -1, -1, 28, 1, 29 }, - { 0x1, 0x1, 260, -1, -1, 28, 1, 29 }, - { 0x0, 0x0, 260, -1, 1993, 0, 0, -1 }, - { 0x0, 0x0, 260, -1, 1995, 0, 0, -1 }, - { 0x1, 0x1, 260, -1, -1, 28, 1, 29 }, - { 0x1, 0x1, 260, -1, -1, 28, 1, 29 }, - { 0x0, 0x0, 262, 22, -1, 0, 1, 0 }, - { 0x0, 0x0, 262, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 262, -1, -1, 0, 1, 0 }, - { 0x0, 0x1, 262, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 262, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 262, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 262, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 262, -1, -1, 29, 1, 0 }, - { 0x0, 0x0, 262, 178, -1, 0, 1, 0 }, - { 0x0, 0x1, 262, -1, -1, 29, 1, 0 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 64 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 64 }, - { 0x0, 0x0, 263, -1, 1928, 0, 0, -1 }, - { 0x0, 0x0, 263, -1, 1930, 0, 0, -1 }, - { 0x0, 0x0, 263, -1, 1932, 0, 0, -1 }, - { 0x0, 0x0, 263, -1, 1934, 0, 0, -1 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 49 }, - { 0x0, 0x0, 263, -1, 1936, 0, 0, -1 }, - { 0x0, 0x0, 263, -1, 1938, 0, 0, -1 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x0, 0x0, 263, -1, 1940, 0, 0, -1 }, - { 0x0, 0x0, 263, -1, 1942, 0, 0, -1 }, - { 0x0, 0x0, 263, -1, 1944, 0, 0, -1 }, - { 0x0, 0x0, 263, -1, 1946, 0, 0, -1 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 49 }, - { 0x0, 0x0, 263, -1, 1948, 0, 0, -1 }, - { 0x0, 0x0, 263, -1, 1950, 0, 0, -1 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, - { 0x1, 0x1, 263, 334, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, 392, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, 338, -1, 12, 1, 2 }, - { 0x1, 0x1, 263, 396, -1, 12, 1, 2 }, - { 0x0, 0x0, 264, -1, 1935, 0, 0, -1 }, - { 0x9, 0x9, 264, -1, 2465, 33, 1, 49 }, - { 0x0, 0x0, 264, 1173, 1984, 0, 0, -1 }, - { 0x3, 0x3, 264, 1174, -1, 27, 1, 49 }, - { 0x0, 0x0, 268, 2392, -1, 0, 1, 0 }, - { 0x3, 0x3, 269, -1, -1, 27, 1, 0 }, - { 0x3, 0x3, 269, -1, -1, 27, 1, 0 }, - { 0x3, 0x3, 269, -1, -1, 27, 1, 0 }, - { 0x3, 0x3, 269, -1, -1, 27, 1, 0 }, - { 0x1, 0x1, 270, 2491, -1, 28, 1, 0 }, - { 0x1, 0x1, 270, 2492, -1, 28, 1, 0 }, - { 0x1, 0x1, 270, 2493, -1, 28, 1, 0 }, - { 0x1, 0x1, 270, 2494, -1, 28, 1, 0 }, - { 0x1, 0x1, 271, -1, -1, 27, 1, 93 }, - { 0x1, 0x1, 271, -1, -1, 27, 1, 93 }, - { 0x0, 0x0, 271, -1, 820, 0, 0, -1 }, - { 0x0, 0x0, 272, 2504, 2369, 0, 0, -1 }, - { 0x0, 0x0, 272, 2505, 2371, 0, 0, -1 }, - { 0x0, 0x0, 273, -1, 2370, 0, 0, -1 }, - { 0x0, 0x0, 273, -1, 2372, 0, 0, -1 }, - { 0x0, 0x0, 274, -1, -1, 0, 1, 40 }, - { 0x0, 0x0, 274, -1, -1, 0, 1, 40 }, - { 0x0, 0x0, 274, -1, -1, 0, 1, 40 }, - { 0x0, 0x0, 279, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 283, -1, 1958, 0, 1, 29 }, - { 0x0, 0x0, 284, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 284, -1, -1, 0, 1, 71 }, - { 0x0, 0x0, 284, 1744, 2482, 0, 1, 1 }, - { 0x0, 0x0, 284, -1, 393, 0, 0, -1 }, - { 0x0, 0x0, 284, 1746, 2484, 0, 1, 1 }, - { 0x0, 0x0, 284, -1, 397, 0, 0, -1 }, -}; - -static const struct ia64_main_table -main_table[] = { - { 5, 1, 1, 0x0000010000000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 0, }, - { 5, 1, 1, 0x0000010008000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 1, }, - { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 66, 27, 0, 0 }, 0x0, 2, }, - { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 63, 26, 0, 0 }, 0x0, 3, }, - { 6, 1, 1, 0x0000012000000000ull, 0x000001e000000000ull, { 24, 66, 27, 0, 0 }, 0x0, 4, }, - { 7, 1, 1, 0x0000010040000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 5, }, - { 7, 1, 1, 0x0000010c00000000ull, 0x000001ee00000000ull, { 24, 63, 26, 0, 0 }, 0x0, 6, }, - { 8, 1, 1, 0x0000010800000000ull, 0x000001ee00000000ull, { 24, 63, 26, 0, 0 }, 0x0, 7, }, - { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 3, 52, 53, 54 }, 0x221, 8, }, - { 10, 1, 1, 0x0000010060000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 9, }, - { 10, 1, 1, 0x0000010160000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 10, }, - { 11, 1, 1, 0x0000010068000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 11, }, - { 11, 1, 1, 0x0000010168000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 12, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011ffull, { 16, 0, 0, 0, 0 }, 0x40, 821, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x0, 686, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x40, 687, }, - { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x200, 1866, }, - { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x240, 1867, }, - { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x0, 443, }, - { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x40, 444, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011ffull, { 81, 0, 0, 0, 0 }, 0x40, 842, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x0, 688, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x40, 689, }, - { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x210, 2502, }, - { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x250, 2503, }, - { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x30, 451, }, - { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x70, 452, }, - { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x230, 449, }, - { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x270, 450, }, - { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 81, 0, 0, 0 }, 0x0, 445, }, - { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 81, 0, 0, 0 }, 0x40, 446, }, - { 15, 4, 0, 0x0000000000000000ull, 0x000001e1f8000000ull, { 65, 0, 0, 0, 0 }, 0x0, 398, }, - { 15, 5, 0, 0x0000000000000000ull, 0x000001e3f8000000ull, { 65, 0, 0, 0, 0 }, 0x0, 812, }, - { 15, 2, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 65, 0, 0, 0, 0 }, 0x2, 956, }, - { 15, 3, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 65, 0, 0, 0, 0 }, 0x0, 1047, }, - { 15, 6, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 69, 0, 0, 0, 0 }, 0x0, 2506, }, - { 15, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 65, 0, 0, 0, 0 }, 0x0, 15, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011ffull, { 82, 0, 0, 0, 0 }, 0x40, 875, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x0, 690, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x40, 691, }, - { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x0, 447, }, - { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x40, 448, }, - { 17, 4, 0, 0x0000004080000000ull, 0x000001e9f8000018ull, { 16, 77, 0, 0, 0 }, 0x20, 2388, }, - { 17, 4, 0, 0x000000e000000000ull, 0x000001e800000018ull, { 81, 77, 0, 0, 0 }, 0x20, 2389, }, - { 18, 4, 0, 0x0000000060000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 219, }, - { 22, 2, 0, 0x0000000200000000ull, 0x000001ee00000000ull, { 25, 80, 0, 0, 0 }, 0x0, 1871, }, - { 22, 3, 0, 0x0000000800000000ull, 0x000001ee00000000ull, { 24, 81, 0, 0, 0 }, 0x0, 221, }, - { 22, 3, 0, 0x0000000c00000000ull, 0x000001ee00000000ull, { 18, 81, 0, 0, 0 }, 0x0, 222, }, - { 22, 3, 0, 0x0000002200000000ull, 0x000001ee00000000ull, { 25, 80, 0, 0, 0 }, 0x0, 1872, }, - { 22, 3, 0, 0x0000002600000000ull, 0x000001ee00000000ull, { 19, 80, 0, 0, 0 }, 0x0, 1873, }, - { 22, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 25, 80, 0, 0, 0 }, 0x0, 1874, }, - { 25, 4, 0, 0x0000000020000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 17, }, - { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x0, 1023, }, - { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 22, 26, 25, 0 }, 0x0, 999, }, - { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 23, 26, 25, 0 }, 0x0, 925, }, - { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 22, 25, 26, 0 }, 0x0, 904, }, - { 26, 1, 2, 0x0000018200000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x40, 1157, }, - { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x0, 926, }, - { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 26, 7, 0 }, 0x40, 1025, }, - { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x40, 1002, }, - { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 23, 55, 26, 0 }, 0x0, 1027, }, - { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 23, 57, 26, 0 }, 0x0, 1003, }, - { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 22, 57, 26, 0 }, 0x0, 929, }, - { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 22, 55, 26, 0 }, 0x0, 908, }, - { 26, 1, 2, 0x0000018a00000000ull, 0x000001ee00001000ull, { 22, 23, 55, 26, 0 }, 0x40, 1160, }, - { 26, 1, 2, 0x000001a800000000ull, 0x000001ee00001000ull, { 22, 23, 59, 26, 0 }, 0x0, 1018, }, - { 26, 1, 2, 0x000001a800000000ull, 0x000001ee00001000ull, { 23, 22, 59, 26, 0 }, 0x0, 946, }, - { 26, 1, 2, 0x000001c200000000ull, 0x000001fe00001000ull, { 23, 22, 25, 26, 0 }, 0x40, 1161, }, - { 26, 1, 2, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 22, 7, 26, 0 }, 0x40, 1004, }, - { 26, 1, 2, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 22, 26, 7, 0 }, 0x40, 910, }, - { 26, 1, 2, 0x000001ca00000000ull, 0x000001ee00001000ull, { 23, 22, 55, 26, 0 }, 0x40, 1162, }, - { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x0, 1030, }, - { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 22, 26, 25, 0 }, 0x0, 1006, }, - { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 23, 26, 25, 0 }, 0x0, 932, }, - { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 22, 25, 26, 0 }, 0x0, 911, }, - { 27, 1, 2, 0x0000018600000000ull, 0x000001fe00001000ull, { 22, 23, 25, 26, 0 }, 0x40, 1165, }, - { 27, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x0, 933, }, - { 27, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 23, 26, 7, 0 }, 0x40, 1032, }, - { 27, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 23, 7, 26, 0 }, 0x40, 1009, }, - { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 23, 55, 26, 0 }, 0x0, 1034, }, - { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 23, 57, 26, 0 }, 0x0, 1010, }, - { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 22, 57, 26, 0 }, 0x0, 936, }, - { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 22, 55, 26, 0 }, 0x0, 915, }, - { 27, 1, 2, 0x0000018e00000000ull, 0x000001ee00001000ull, { 22, 23, 55, 26, 0 }, 0x40, 1168, }, - { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 23, 56, 26, 0 }, 0x0, 1044, }, - { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 23, 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{ 24, 9, 0, 0, 0 }, 0x0, 115, }, - { 155, 2, 1, 0x0000000150000000ull, 0x000001eff8000000ull, { 14, 25, 0, 0, 0 }, 0x0, 962, }, - { 155, 2, 1, 0x0000000050000000ull, 0x000001eff8000000ull, { 14, 55, 0, 0, 0 }, 0x0, 963, }, - { 155, 2, 1, 0x0000000190000000ull, 0x000001eff8000000ull, { 24, 14, 0, 0, 0 }, 0x0, 964, }, - { 155, 3, 1, 0x0000000140000000ull, 0x000001eff8000000ull, { 14, 55, 0, 0, 0 }, 0x0, 1051, }, - { 155, 3, 1, 0x0000002150000000ull, 0x000001eff8000000ull, { 14, 25, 0, 0, 0 }, 0x0, 1052, }, - { 155, 3, 1, 0x0000002110000000ull, 0x000001eff8000000ull, { 24, 14, 0, 0, 0 }, 0x0, 1053, }, - { 155, 3, 1, 0x0000002160000000ull, 0x000001eff8000000ull, { 17, 25, 0, 0, 0 }, 0x8, 116, }, - { 155, 3, 1, 0x0000002120000000ull, 0x000001eff8000000ull, { 24, 17, 0, 0, 0 }, 0x8, 117, }, - { 155, 3, 1, 0x0000002168000000ull, 0x000001eff8000000ull, { 12, 25, 0, 0, 0 }, 0x8, 118, }, - { 155, 3, 1, 0x0000002148000000ull, 0x000001eff8000000ull, { 13, 25, 0, 0, 0 }, 0x0, 119, }, - { 155, 3, 1, 0x0000002128000000ull, 0x000001eff8000000ull, { 24, 11, 0, 0, 0 }, 0x8, 120, }, - { 155, 3, 1, 0x0000002108000000ull, 0x000001eff8000000ull, { 24, 13, 0, 0, 0 }, 0x0, 121, }, - { 155, 3, 1, 0x0000002000000000ull, 0x000001eff8000000ull, { 38, 25, 0, 0, 0 }, 0x8, 122, }, - { 155, 3, 1, 0x0000002008000000ull, 0x000001eff8000000ull, { 29, 25, 0, 0, 0 }, 0x8, 123, }, - { 155, 3, 1, 0x0000002010000000ull, 0x000001eff8000000ull, { 32, 25, 0, 0, 0 }, 0x8, 124, }, - { 155, 3, 1, 0x0000002018000000ull, 0x000001eff8000000ull, { 35, 25, 0, 0, 0 }, 0x8, 125, }, - { 155, 3, 1, 0x0000002020000000ull, 0x000001eff8000000ull, { 36, 25, 0, 0, 0 }, 0x8, 126, }, - { 155, 3, 1, 0x0000002028000000ull, 0x000001eff8000000ull, { 37, 25, 0, 0, 0 }, 0x8, 127, }, - { 155, 3, 1, 0x0000002030000000ull, 0x000001eff8000000ull, { 34, 25, 0, 0, 0 }, 0x8, 128, }, - { 155, 3, 1, 0x0000002080000000ull, 0x000001eff8000000ull, { 24, 38, 0, 0, 0 }, 0x8, 129, }, - { 155, 3, 1, 0x0000002088000000ull, 0x000001eff8000000ull, { 24, 29, 0, 0, 0 }, 0x8, 130, }, - { 155, 3, 1, 0x0000002090000000ull, 0x000001eff8000000ull, { 24, 32, 0, 0, 0 }, 0x8, 131, }, - { 155, 3, 1, 0x0000002098000000ull, 0x000001eff8000000ull, { 24, 35, 0, 0, 0 }, 0x8, 132, }, - { 155, 3, 1, 0x00000020a0000000ull, 0x000001eff8000000ull, { 24, 36, 0, 0, 0 }, 0x8, 133, }, - { 155, 3, 1, 0x00000020a8000000ull, 0x000001eff8000000ull, { 24, 37, 0, 0, 0 }, 0x0, 134, }, - { 155, 3, 1, 0x00000020b0000000ull, 0x000001eff8000000ull, { 24, 34, 0, 0, 0 }, 0x8, 135, }, - { 155, 3, 1, 0x00000020b8000000ull, 0x000001eff8000000ull, { 24, 28, 0, 0, 0 }, 0x0, 136, }, - { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 14, 0, 0, 0 }, 0x0, 137, }, - { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 14, 55, 0, 0, 0 }, 0x0, 138, }, - { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 14, 25, 0, 0, 0 }, 0x0, 139, }, - { 156, 6, 1, 0x000000c000000000ull, 0x000001e000100000ull, { 24, 70, 0, 0, 0 }, 0x0, 140, }, - { 157, 2, 1, 0x000000eca0000000ull, 0x000001fff0000000ull, { 24, 25, 74, 0, 0 }, 0x0, 141, }, - { 158, 2, 1, 0x000000eea0000000ull, 0x000001fff0000000ull, { 24, 25, 75, 0, 0 }, 0x0, 142, }, - { 168, 4, 0, 0x0000004000000000ull, 0x000001e1f8000000ull, { 65, 0, 0, 0, 0 }, 0x0, 400, }, - { 168, 5, 0, 0x0000000008000000ull, 0x000001e3fc000000ull, { 65, 0, 0, 0, 0 }, 0x0, 814, }, - { 168, 2, 0, 0x0000000008000000ull, 0x000001effc000000ull, { 65, 0, 0, 0, 0 }, 0x2, 965, }, - { 168, 3, 0, 0x0000000008000000ull, 0x000001effc000000ull, { 65, 0, 0, 0, 0 }, 0x0, 1054, }, - { 168, 6, 0, 0x0000000008000000ull, 0x000001effc000000ull, { 69, 0, 0, 0, 0 }, 0x0, 2508, }, - { 168, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 65, 0, 0, 0, 0 }, 0x0, 143, }, - { 175, 1, 1, 0x0000010070000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 144, }, - { 175, 1, 1, 0x0000010170000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 145, }, - { 178, 2, 1, 0x000000ea00000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2490, }, - { 179, 2, 1, 0x000000f820000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2393, }, - { 180, 1, 1, 0x0000010400000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 146, }, - { 181, 1, 1, 0x0000010600000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 147, }, - { 182, 1, 1, 0x0000011400000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 148, }, - { 183, 1, 1, 0x0000010450000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 149, }, - { 184, 1, 1, 0x0000010650000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 150, }, - { 185, 1, 1, 0x0000010470000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 151, }, - { 186, 1, 1, 0x0000010670000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 152, }, - { 187, 1, 1, 0x0000010520000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 800, }, - { 188, 1, 1, 0x0000010720000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 801, }, - { 189, 1, 1, 0x0000011520000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 802, }, - { 190, 2, 1, 0x000000e850000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2407, }, - { 191, 2, 1, 0x000000ea70000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 153, }, - { 192, 2, 1, 0x000000e810000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2408, }, - { 193, 2, 1, 0x000000ea30000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 154, }, - { 194, 2, 1, 0x000000ead0000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1844, }, - { 195, 2, 1, 0x000000e230000000ull, 0x000001ff30000000ull, { 24, 25, 26, 42, 0 }, 0x0, 155, }, - { 196, 2, 1, 0x000000e690000000ull, 0x000001fff0000000ull, { 24, 26, 0, 0, 0 }, 0x0, 156, }, - { 198, 3, 1, 0x00000021c0000000ull, 0x000001eff8000000ull, { 24, 26, 25, 0, 0 }, 0x0, 1845, }, - { 198, 3, 1, 0x00000020c0000000ull, 0x000001eff8000000ull, { 24, 26, 49, 0, 0 }, 0x0, 1846, }, - { 198, 3, 0, 0x0000002188000000ull, 0x000001eff8000000ull, { 26, 49, 0, 0, 0 }, 0x0, 1870, }, - { 199, 2, 1, 0x000000e8b0000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 157, }, - { 200, 2, 1, 0x000000e240000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 158, }, - { 200, 2, 1, 0x000000ee50000000ull, 0x000001fff0000000ull, { 24, 25, 39, 0, 0 }, 0x0, 159, }, - { 201, 2, 1, 0x000000f040000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 160, }, - { 201, 2, 1, 0x000000fc50000000ull, 0x000001fff0000000ull, { 24, 25, 39, 0, 0 }, 0x0, 161, }, - { 202, 1, 1, 0x0000010680000000ull, 0x000001ffe0000000ull, { 24, 25, 41, 26, 0 }, 0x0, 162, }, - { 203, 2, 1, 0x000000e220000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 163, }, - { 203, 2, 1, 0x000000e630000000ull, 0x000001fff0000000ull, { 24, 26, 43, 0, 0 }, 0x0, 164, }, - { 204, 2, 1, 0x000000f020000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 165, }, - { 204, 2, 1, 0x000000f430000000ull, 0x000001fff0000000ull, { 24, 26, 43, 0, 0 }, 0x0, 166, }, - { 205, 1, 1, 0x00000106c0000000ull, 0x000001ffe0000000ull, { 24, 25, 41, 26, 0 }, 0x0, 167, }, - { 206, 1, 1, 0x0000010420000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 168, }, - { 207, 1, 1, 0x0000010620000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 169, }, - { 208, 1, 1, 0x0000011420000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 170, }, - { 209, 3, 0, 0x0000002048000000ull, 0x000001eff8000000ull, { 26, 25, 0, 0, 0 }, 0x8, 993, }, - { 209, 3, 0, 0x0000002050000000ull, 0x000001eff8000000ull, { 26, 25, 0, 0, 0 }, 0xc, 902, }, - { 209, 3, 0, 0x00000021a0000000ull, 0x000001eff8000000ull, { 26, 0, 0, 0, 0 }, 0x8, 783, }, - { 210, 3, 0, 0x0000002060000000ull, 0x000001eff8000000ull, { 26, 25, 0, 0, 0 }, 0x8, 709, }, - { 215, 4, 0, 0x0000000040000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x22c, 171, }, - { 216, 3, 0, 0x0000000038000000ull, 0x000001ee78000000ull, { 67, 0, 0, 0, 0 }, 0x8, 172, }, - { 217, 3, 0, 0x0000000028000000ull, 0x000001ee78000000ull, { 67, 0, 0, 0, 0 }, 0x0, 173, }, - { 226, 3, 1, 0x000000c708000000ull, 0x000001ffc8000000ull, { 18, 25, 0, 0, 0 }, 0x0, 2318, }, - { 227, 2, 1, 0x000000a600000000ull, 0x000001ee04000000ull, { 24, 25, 45, 0, 0 }, 0x140, 174, }, - { 227, 2, 1, 0x000000f240000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 175, }, - { 228, 1, 1, 0x0000010080000000ull, 0x000001efe0000000ull, { 24, 25, 40, 26, 0 }, 0x0, 176, }, - { 229, 1, 1, 0x00000100c0000000ull, 0x000001efe0000000ull, { 24, 25, 40, 26, 0 }, 0x0, 177, }, - { 230, 2, 1, 0x000000a400000000ull, 0x000001ee00002000ull, { 24, 26, 76, 0, 0 }, 0x140, 2414, }, - { 230, 2, 1, 0x000000f220000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 179, }, - { 231, 2, 1, 0x000000ac00000000ull, 0x000001ee00000000ull, { 24, 25, 26, 44, 0 }, 0x0, 180, }, - { 236, 3, 0, 0x0000000180000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 711, }, - { 237, 3, 0, 0x0000000030000000ull, 0x000001ee78000000ull, { 67, 0, 0, 0, 0 }, 0x8, 181, }, - { 239, 3, 1, 0x0000008c00000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 182, }, - { 239, 3, 1, 0x000000ac00000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 183, }, - { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 33, 25, 1, 0, 0 }, 0x0, 184, }, - { 241, 3, 1, 0x0000008c40000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 185, }, - { 241, 3, 1, 0x000000ac40000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 186, }, - { 242, 3, 1, 0x0000008c80000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 187, }, - { 242, 3, 1, 0x000000ac80000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 188, }, - { 243, 3, 1, 0x0000008cc0000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 189, }, - { 243, 3, 1, 0x000000acc0000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 190, }, - { 244, 3, 1, 0x000000cec0000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 2321, }, - { 244, 3, 1, 0x000000eec0000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 2322, }, - { 245, 3, 1, 0x000000cc40000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 191, }, - { 245, 3, 1, 0x000000ec40000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 192, }, - { 246, 3, 1, 0x000000ccc0000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 193, }, - { 246, 3, 1, 0x000000ecc0000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 194, }, - { 247, 3, 1, 0x000000cc00000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 195, }, - { 247, 3, 1, 0x000000ec00000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 196, }, - { 248, 3, 1, 0x000000cc80000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 197, }, - { 248, 3, 1, 0x000000ec80000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 198, }, - { 249, 1, 1, 0x0000010028000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 199, }, - { 249, 1, 1, 0x0000010020000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 200, }, - { 249, 1, 1, 0x0000010128000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 201, }, - { 250, 3, 0, 0x0000000020000000ull, 0x000001ee78000000ull, { 67, 0, 0, 0, 0 }, 0x0, 202, }, - { 251, 2, 1, 0x00000000a0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 203, }, - { 252, 2, 1, 0x00000000a8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 204, }, - { 253, 2, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 205, }, - { 254, 3, 0, 0x0000000198000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 968, }, - { 255, 3, 1, 0x00000020f8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 206, }, - { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 23, 26, 76, 0 }, 0x0, 2513, }, - { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 23, 22, 26, 76, 0 }, 0x40, 1745, }, - { 257, 3, 1, 0x00000020d0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 207, }, - { 258, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 23, 26, 0, 0 }, 0x0, 2515, }, - { 258, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 23, 22, 26, 0, 0 }, 0x40, 1747, }, - { 259, 3, 1, 0x00000020f0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 208, }, - { 261, 3, 1, 0x00000020d8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 209, }, - { 265, 2, 1, 0x000000e840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 949, }, - { 266, 2, 1, 0x000000ea40000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 950, }, - { 267, 2, 1, 0x000000f840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 951, }, - { 275, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 210, }, - { 276, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 211, }, - { 277, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 212, }, - { 278, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 213, }, - { 280, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x0, 997, }, - { 280, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x40, 1045, }, - { 281, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 18, 20, 21, 0, 0 }, 0x40, 998, }, - { 282, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 214, }, - { 282, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 215, }, - { 285, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 216, }, - { 286, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 217, }, - { 287, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 218, }, -}; - -static const char dis_table[] = { -0xa0, 0xc4, 0xd8, 0xa0, 0x2d, 0x88, 0xa0, 0x2b, 0x70, 0xa0, 0x1a, 0xb0, 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0xe5, 0x22, 0x02, 0xc0, -0x38, 0x17, 0xe5, 0x21, 0xfc, 0xc0, 0x37, 0xff, 0xcb, 0x61, 0x16, 0x40, -0x85, 0x34, 0x68, 0x90, 0x48, 0xcb, 0xa1, 0x16, 0x00, 0x85, 0x34, 0x67, -0xcb, 0xa1, 0x15, 0xc0, 0x85, 0x34, 0x66, 0x92, 0x20, 0x91, 0x30, 0x90, -0xb8, 0xd5, 0x03, 0x00, 0xc0, 0xc0, 0x81, 0x8c, 0x01, 0xa0, 0x84, 0x30, -0x3e, 0xc0, 0xc0, 0x81, 0x8c, 0x01, 0x80, 0x84, 0x30, 0x3c, 0xd5, 0x02, -0x00, 0xc0, 0xc0, 0x81, 0x30, 0x28, 0xc0, 0xc0, 0x81, 0x30, 0x24, 0x90, -0x78, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x1c, 0xc0, 0xc0, 0x81, -0x30, 0x18, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x10, 0xc0, 0xc0, -0x81, 0x30, 0x0c, 0x91, 0x70, 0x90, 0xd8, 0xd5, 0x03, 0x80, 0xc8, 0xe1, -0xf8, 0xc0, 0x81, 0x8c, 0x01, 0xc0, 0x84, 0x30, 0x40, 0xc8, 0xe1, 0xf9, -0xc0, 0x81, 0x8c, 0x01, 0x90, 0x84, 0x30, 0x3d, 0xd5, 0x02, 0x80, 0xc8, -0xe1, 0xf8, 0x40, 0x81, 0x30, 0x2c, 0xc8, 0xe1, 0xf5, 0x40, 0x81, 0x30, -0x26, 0x90, 0x98, 0xd5, 0x02, 0x80, 0xc8, 0xe1, 0xef, 0x40, 0x81, 0x30, -0x20, 0xc8, 0xe1, 0xf0, 0x40, 0x81, 0x30, 0x1a, 0xd5, 0x02, 0x80, 0xc8, -0xe1, 0xee, 0xc0, 0x81, 0x30, 0x14, 0xc8, 0xe1, 0xeb, 0xc0, 0x81, 0x30, -0x0e, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, -0x80, 0xe5, 0x22, 0x1b, 0xc0, 0x38, 0x6b, 0xe5, 0x22, 0x1c, 0xc0, 0x38, -0x7d, 0xcb, 0x61, 0x15, 0x40, 0x85, 0x34, 0x64, 0x98, 0x50, 0x00, 0x80, -0xe5, 0x22, 0x13, 0xc0, 0x38, 0x4b, 0xe5, 0x22, 0x14, 0xc0, 0x38, 0x5d, -0xcb, 0x61, 0x15, 0x00, 0x85, 0x34, 0x63, 0x90, 0x48, 0xcb, 0xa1, 0x14, -0xc0, 0x85, 0x34, 0x62, 0xcb, 0xa1, 0x14, 0x80, 0x85, 0x34, 0x61, 0x91, -0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x0c, 0xc0, 0x38, -0x3f, 0xe5, 0x22, 0x06, 0xc0, 0x38, 0x27, 0xcb, 0x61, 0x12, 0xc0, 0x85, -0x34, 0x50, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x00, 0xc0, 0x38, 0x0f, -0xe5, 0x21, 0xfa, 0xc0, 0x37, 0xf7, 0xcb, 0x61, 0x12, 0x80, 0x85, 0x34, -0x4f, 0x90, 0x48, 0xcb, 0xa1, 0x12, 0x40, 0x85, 0x34, 0x4e, 0xcb, 0xa1, -0x12, 0x00, 0x85, 0x34, 0x4d, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40, 0xe5, -0x20, 0x02, 0x40, 0x30, 0x0a, 0xe5, 0x20, 0x01, 0x80, 0x30, 0x07, 0x90, -0x40, 0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, 0xe5, 0x20, 0x00, 0x00, 0x30, -0x01, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 0xf2, 0xc0, 0x37, 0xc5, 0xe5, -0x21, 0xf4, 0x00, 0x37, 0xdb, 0x90, 0x40, 0xe5, 0x21, 0xe9, 0x40, 0x37, -0x9f, 0xe5, 0x21, 0xea, 0x80, 0x37, 0xb5, 0x80, 0x99, 0x28, 0x02, 0xf0, -0x8c, 0x21, 0xf8, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, 0x1e, 0xc0, 0x38, -0x79, 0xe5, 0x22, 0x1d, 0x40, 0x38, 0x7f, 0x90, 0x40, 0xe5, 0x22, 0x16, -0xc0, 0x38, 0x59, 0xe5, 0x22, 0x15, 0x40, 0x38, 0x5f, 0x91, 0x48, 0x90, -0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x0d, 0xc0, 0x38, 0x43, 0xe5, -0x22, 0x07, 0xc0, 0x38, 0x2b, 0xcb, 0x61, 0x10, 0x80, 0x85, 0x34, 0x46, -0x90, 0x40, 0xe5, 0x22, 0x01, 0xc0, 0x38, 0x13, 0xe5, 0x21, 0xfb, 0xc0, -0x37, 0xfb, 0x90, 0x48, 0xcb, 0xa1, 0x10, 0x00, 0x85, 0x34, 0x44, 0xcb, -0xa1, 0x10, 0x40, 0x85, 0x34, 0x45, 0x10, 0x10, 0x90, 0x80, 0x90, 0x40, -0xe5, 0x21, 0xf6, 0x40, 0x37, 0xd7, 0xe5, 0x21, 0xf4, 0xc0, 0x37, 0xdf, -0x90, 0x40, 0xe5, 0x21, 0xec, 0xc0, 0x37, 0xb1, 0xe5, 0x21, 0xeb, 0x40, -0x37, 0xb9, -}; - -static const struct ia64_dis_names ia64_dis_names[] = { -{ 0x51, 40, 0, 10 }, -{ 0x31, 40, 1, 20 }, -{ 0x11, 41, 0, 19 }, -{ 0x29, 40, 0, 12 }, -{ 0x19, 40, 1, 24 }, -{ 0x9, 41, 0, 23 }, -{ 0x15, 40, 0, 14 }, -{ 0xd, 40, 1, 28 }, -{ 0x5, 41, 0, 27 }, -{ 0xb, 40, 0, 16 }, -{ 0x7, 40, 1, 32 }, -{ 0x3, 41, 0, 31 }, -{ 0x51, 38, 1, 58 }, -{ 0x50, 38, 0, 34 }, -{ 0xd1, 38, 1, 57 }, -{ 0xd0, 38, 0, 33 }, -{ 0x31, 38, 1, 68 }, -{ 0x30, 38, 1, 44 }, -{ 0x11, 39, 1, 67 }, -{ 0x10, 39, 0, 43 }, -{ 0x71, 38, 1, 66 }, -{ 0x70, 38, 1, 42 }, -{ 0x31, 39, 1, 65 }, -{ 0x30, 39, 0, 41 }, -{ 0x29, 38, 1, 60 }, -{ 0x28, 38, 0, 36 }, -{ 0x69, 38, 1, 59 }, -{ 0x68, 38, 0, 35 }, -{ 0x19, 38, 1, 72 }, -{ 0x18, 38, 1, 48 }, -{ 0x9, 39, 1, 71 }, -{ 0x8, 39, 0, 47 }, -{ 0x39, 38, 1, 70 }, -{ 0x38, 38, 1, 46 }, -{ 0x19, 39, 1, 69 }, -{ 0x18, 39, 0, 45 }, -{ 0x15, 38, 1, 62 }, -{ 0x14, 38, 0, 38 }, -{ 0x35, 38, 1, 61 }, -{ 0x34, 38, 0, 37 }, -{ 0xd, 38, 1, 76 }, -{ 0xc, 38, 1, 52 }, -{ 0x5, 39, 1, 75 }, -{ 0x4, 39, 0, 51 }, -{ 0x1d, 38, 1, 74 }, -{ 0x1c, 38, 1, 50 }, -{ 0xd, 39, 1, 73 }, -{ 0xc, 39, 0, 49 }, -{ 0xb, 38, 1, 64 }, -{ 0xa, 38, 0, 40 }, -{ 0x1b, 38, 1, 63 }, -{ 0x1a, 38, 0, 39 }, -{ 0x7, 38, 1, 80 }, -{ 0x6, 38, 1, 56 }, -{ 0x3, 39, 1, 79 }, -{ 0x2, 39, 0, 55 }, -{ 0xf, 38, 1, 78 }, -{ 0xe, 38, 1, 54 }, -{ 0x7, 39, 1, 77 }, -{ 0x6, 39, 0, 53 }, -{ 0x8, 37, 0, 82 }, -{ 0x18, 37, 0, 81 }, -{ 0x1, 37, 1, 86 }, -{ 0x2, 37, 0, 85 }, -{ 0x3, 37, 1, 84 }, -{ 0x4, 37, 0, 83 }, -{ 0x1, 293, 0, 87 }, -{ 0x20, 246, 0, 98 }, -{ 0x220, 246, 0, 94 }, -{ 0x1220, 246, 0, 91 }, -{ 0xa20, 246, 0, 92 }, -{ 0x620, 246, 0, 93 }, -{ 0x120, 246, 0, 95 }, -{ 0xa0, 246, 0, 96 }, -{ 0x60, 246, 0, 97 }, -{ 0x10, 246, 0, 102 }, -{ 0x90, 246, 0, 99 }, -{ 0x50, 246, 0, 100 }, -{ 0x30, 246, 0, 101 }, -{ 0x8, 246, 0, 103 }, -{ 0x4, 246, 0, 104 }, -{ 0x2, 246, 0, 105 }, -{ 0x1, 246, 0, 106 }, -{ 0x1, 367, 0, 108 }, -{ 0x3, 367, 0, 107 }, -{ 0x2, 373, 0, 109 }, -{ 0x1, 373, 0, 110 }, -{ 0x2, 369, 0, 111 }, -{ 0x1, 369, 0, 112 }, -{ 0x2, 371, 0, 113 }, -{ 0x1, 371, 0, 114 }, -{ 0x2, 375, 0, 115 }, -{ 0x1, 375, 0, 116 }, -{ 0x1, 225, 0, 143 }, -{ 0x5, 225, 0, 141 }, -{ 0x3, 225, 0, 142 }, -{ 0x140, 234, 0, 119 }, -{ 0x540, 234, 0, 117 }, -{ 0x340, 234, 0, 118 }, -{ 0xc0, 234, 0, 131 }, -{ 0x2c0, 234, 0, 129 }, -{ 0x1c0, 234, 0, 130 }, -{ 0x20, 234, 0, 146 }, -{ 0xa0, 234, 0, 144 }, -{ 0x60, 234, 0, 145 }, -{ 0x10, 234, 0, 158 }, -{ 0x50, 234, 0, 156 }, -{ 0x30, 234, 0, 157 }, -{ 0x8, 234, 0, 170 }, -{ 0x28, 234, 0, 168 }, -{ 0x18, 234, 0, 169 }, -{ 0x4, 234, 0, 180 }, -{ 0x2, 234, 0, 181 }, -{ 0x1, 234, 0, 182 }, -{ 0x140, 228, 0, 122 }, -{ 0x540, 228, 0, 120 }, -{ 0x340, 228, 0, 121 }, -{ 0xc0, 228, 0, 134 }, -{ 0x2c0, 228, 0, 132 }, -{ 0x1c0, 228, 0, 133 }, -{ 0x20, 228, 0, 149 }, -{ 0xa0, 228, 0, 147 }, -{ 0x60, 228, 0, 148 }, -{ 0x10, 228, 0, 161 }, -{ 0x50, 228, 0, 159 }, -{ 0x30, 228, 0, 160 }, -{ 0x8, 228, 0, 173 }, -{ 0x28, 228, 0, 171 }, -{ 0x18, 228, 0, 172 }, -{ 0x4, 228, 0, 183 }, -{ 0x2, 228, 0, 184 }, -{ 0x1, 228, 0, 185 }, -{ 0x140, 231, 0, 125 }, -{ 0x540, 231, 0, 123 }, -{ 0x340, 231, 0, 124 }, -{ 0xc0, 231, 0, 137 }, -{ 0x2c0, 231, 0, 135 }, -{ 0x1c0, 231, 0, 136 }, -{ 0x20, 231, 0, 152 }, -{ 0xa0, 231, 0, 150 }, -{ 0x60, 231, 0, 151 }, -{ 0x10, 231, 0, 164 }, -{ 0x50, 231, 0, 162 }, -{ 0x30, 231, 0, 163 }, -{ 0x8, 231, 0, 176 }, -{ 0x28, 231, 0, 174 }, -{ 0x18, 231, 0, 175 }, -{ 0x4, 231, 0, 186 }, -{ 0x2, 231, 0, 187 }, -{ 0x1, 231, 0, 188 }, -{ 0x140, 243, 0, 128 }, -{ 0x540, 243, 0, 126 }, -{ 0x340, 243, 0, 127 }, -{ 0xc0, 243, 0, 140 }, -{ 0x2c0, 243, 0, 138 }, -{ 0x1c0, 243, 0, 139 }, -{ 0x20, 243, 0, 155 }, -{ 0xa0, 243, 0, 153 }, -{ 0x60, 243, 0, 154 }, -{ 0x10, 243, 0, 167 }, -{ 0x50, 243, 0, 165 }, -{ 0x30, 243, 0, 166 }, -{ 0x8, 243, 0, 179 }, -{ 0x28, 243, 0, 177 }, -{ 0x18, 243, 0, 178 }, -{ 0x4, 243, 0, 189 }, -{ 0x2, 243, 0, 190 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1, 1818 }, -{ 0xc, 21, 1, 1794 }, -{ 0x5, 22, 1, 1817 }, -{ 0x4, 22, 0, 1793 }, -{ 0x1d, 21, 1, 1816 }, -{ 0x1c, 21, 1, 1792 }, -{ 0xd, 22, 1, 1815 }, -{ 0xc, 22, 0, 1791 }, -{ 0xb, 21, 1, 1806 }, -{ 0xa, 21, 0, 1782 }, -{ 0x1b, 21, 1, 1805 }, -{ 0x1a, 21, 0, 1781 }, -{ 0x7, 21, 1, 1822 }, -{ 0x6, 21, 1, 1798 }, -{ 0x3, 22, 1, 1821 }, -{ 0x2, 22, 0, 1797 }, -{ 0xf, 21, 1, 1820 }, -{ 0xe, 21, 1, 1796 }, -{ 0x7, 22, 1, 1819 }, -{ 0x6, 22, 0, 1795 }, -{ 0x8, 20, 0, 1824 }, -{ 0x18, 20, 0, 1823 }, -{ 0x1, 20, 1, 1828 }, -{ 0x2, 20, 0, 1827 }, -{ 0x3, 20, 1, 1826 }, -{ 0x4, 20, 0, 1825 }, -{ 0x1, 197, 0, 1829 }, -{ 0x1, 296, 0, 1830 }, -{ 0x14, 42, 0, 1833 }, -{ 0x34, 42, 0, 1831 }, -{ 0xc, 42, 0, 1834 }, -{ 0x1c, 42, 0, 1832 }, -{ 0x2, 42, 0, 1837 }, -{ 0x6, 42, 0, 1835 }, -{ 0x1, 42, 0, 1838 }, -{ 0x3, 42, 0, 1836 }, -{ 0x51, 18, 0, 1840 }, -{ 0xd1, 18, 0, 1839 }, -{ 0x31, 18, 1, 1850 }, -{ 0x11, 19, 0, 1849 }, -{ 0x71, 18, 1, 1848 }, -{ 0x31, 19, 0, 1847 }, -{ 0x29, 18, 0, 1842 }, -{ 0x69, 18, 0, 1841 }, -{ 0x19, 18, 1, 1854 }, -{ 0x9, 19, 0, 1853 }, -{ 0x39, 18, 1, 1852 }, -{ 0x19, 19, 0, 1851 }, -{ 0x15, 18, 0, 1844 }, -{ 0x35, 18, 0, 1843 }, -{ 0xd, 18, 1, 1858 }, -{ 0x5, 19, 0, 1857 }, -{ 0x1d, 18, 1, 1856 }, -{ 0xd, 19, 0, 1855 }, -{ 0xb, 18, 0, 1846 }, -{ 0x1b, 18, 0, 1845 }, -{ 0x7, 18, 1, 1862 }, -{ 0x3, 19, 0, 1861 }, -{ 0xf, 18, 1, 1860 }, -{ 0x7, 19, 0, 1859 }, -{ 0x1, 31, 0, 1863 }, -{ 0x1, 104, 0, 1864 }, -{ 0x2, 44, 0, 1865 }, -{ 0x1, 44, 0, 1866 }, -{ 0x1, 344, 0, 1867 }, -{ 0x2, 51, 0, 1868 }, -{ 0x1, 51, 0, 1869 }, -{ 0x1, 97, 0, 1870 }, -{ 0x51, 16, 0, 1872 }, -{ 0xd1, 16, 0, 1871 }, -{ 0x31, 16, 1, 1882 }, -{ 0x11, 17, 0, 1881 }, -{ 0x71, 16, 1, 1880 }, -{ 0x31, 17, 0, 1879 }, -{ 0x29, 16, 0, 1874 }, -{ 0x69, 16, 0, 1873 }, -{ 0x19, 16, 1, 1886 }, -{ 0x9, 17, 0, 1885 }, -{ 0x39, 16, 1, 1884 }, -{ 0x19, 17, 0, 1883 }, -{ 0x15, 16, 0, 1876 }, -{ 0x35, 16, 0, 1875 }, -{ 0xd, 16, 1, 1890 }, -{ 0x5, 17, 0, 1889 }, -{ 0x1d, 16, 1, 1888 }, -{ 0xd, 17, 0, 1887 }, -{ 0xb, 16, 0, 1878 }, -{ 0x1b, 16, 0, 1877 }, -{ 0x7, 16, 1, 1894 }, -{ 0x3, 17, 0, 1893 }, -{ 0xf, 16, 1, 1892 }, -{ 0x7, 17, 0, 1891 }, -{ 0xa20, 14, 0, 1896 }, -{ 0x1a20, 14, 0, 1895 }, -{ 0x620, 14, 1, 1906 }, -{ 0x220, 15, 0, 1905 }, -{ 0xe20, 14, 1, 1904 }, -{ 0x620, 15, 0, 1903 }, -{ 0x520, 14, 0, 1898 }, -{ 0xd20, 14, 0, 1897 }, -{ 0x320, 14, 1, 1910 }, -{ 0x120, 15, 0, 1909 }, -{ 0x720, 14, 1, 1908 }, -{ 0x320, 15, 0, 1907 }, -{ 0x2a0, 14, 0, 1900 }, -{ 0x6a0, 14, 0, 1899 }, -{ 0x1a0, 14, 1, 1914 }, -{ 0xa0, 15, 0, 1913 }, -{ 0x3a0, 14, 1, 1912 }, -{ 0x1a0, 15, 0, 1911 }, -{ 0x160, 14, 0, 1902 }, -{ 0x360, 14, 0, 1901 }, -{ 0xe0, 14, 1, 1918 }, -{ 0x60, 15, 0, 1917 }, -{ 0x1e0, 14, 1, 1916 }, -{ 0xe0, 15, 0, 1915 }, -{ 0x51, 14, 1, 1944 }, -{ 0x50, 14, 0, 1920 }, -{ 0xd1, 14, 1, 1943 }, -{ 0xd0, 14, 0, 1919 }, -{ 0x31, 14, 1, 1954 }, -{ 0x30, 14, 1, 1930 }, -{ 0x11, 15, 1, 1953 }, -{ 0x10, 15, 0, 1929 }, -{ 0x71, 14, 1, 1952 }, -{ 0x70, 14, 1, 1928 }, -{ 0x31, 15, 1, 1951 }, -{ 0x30, 15, 0, 1927 }, -{ 0x29, 14, 1, 1946 }, -{ 0x28, 14, 0, 1922 }, -{ 0x69, 14, 1, 1945 }, -{ 0x68, 14, 0, 1921 }, -{ 0x19, 14, 1, 1958 }, -{ 0x18, 14, 1, 1934 }, -{ 0x9, 15, 1, 1957 }, -{ 0x8, 15, 0, 1933 }, -{ 0x39, 14, 1, 1956 }, -{ 0x38, 14, 1, 1932 }, -{ 0x19, 15, 1, 1955 }, -{ 0x18, 15, 0, 1931 }, -{ 0x15, 14, 1, 1948 }, -{ 0x14, 14, 0, 1924 }, -{ 0x35, 14, 1, 1947 }, -{ 0x34, 14, 0, 1923 }, -{ 0xd, 14, 1, 1962 }, -{ 0xc, 14, 1, 1938 }, -{ 0x5, 15, 1, 1961 }, -{ 0x4, 15, 0, 1937 }, -{ 0x1d, 14, 1, 1960 }, -{ 0x1c, 14, 1, 1936 }, -{ 0xd, 15, 1, 1959 }, -{ 0xc, 15, 0, 1935 }, -{ 0xb, 14, 1, 1950 }, -{ 0xa, 14, 0, 1926 }, -{ 0x1b, 14, 1, 1949 }, -{ 0x1a, 14, 0, 1925 }, -{ 0x7, 14, 1, 1966 }, -{ 0x6, 14, 1, 1942 }, -{ 0x3, 15, 1, 1965 }, -{ 0x2, 15, 0, 1941 }, -{ 0xf, 14, 1, 1964 }, -{ 0xe, 14, 1, 1940 }, -{ 0x7, 15, 1, 1963 }, -{ 0x6, 15, 0, 1939 }, -{ 0x8, 13, 0, 1968 }, -{ 0x18, 13, 0, 1967 }, -{ 0x1, 13, 1, 1972 }, -{ 0x2, 13, 0, 1971 }, -{ 0x3, 13, 1, 1970 }, -{ 0x4, 13, 0, 1969 }, -{ 0x1, 84, 1, 2048 }, -{ 0x1, 85, 1, 2047 }, -{ 0x1, 86, 1, 2046 }, -{ 0x1, 87, 1, 2045 }, -{ 0x39, 40, 1, 22 }, -{ 0x19, 41, 0, 21 }, -{ 0x3, 84, 1, 2044 }, -{ 0x3, 85, 1, 2043 }, -{ 0x3, 86, 1, 2042 }, -{ 0x3, 87, 1, 2041 }, -{ 0x69, 40, 0, 11 }, -{ 0x14, 79, 1, 2038 }, -{ 0xa, 83, 1, 2037 }, -{ 0xd1, 40, 0, 9 }, -{ 0x34, 79, 1, 1974 }, -{ 0xe, 91, 0, 1973 }, -{ 0xc, 79, 1, 2118 }, -{ 0x6, 83, 0, 2117 }, -{ 0x2, 79, 1, 1980 }, -{ 0x2, 82, 0, 1979 }, -{ 0x12, 79, 1, 1978 }, -{ 0x6, 82, 0, 1977 }, -{ 0xa, 79, 1, 2040 }, -{ 0x5, 83, 1, 2039 }, -{ 0x71, 40, 1, 18 }, -{ 0x31, 41, 0, 17 }, -{ 0x1a, 79, 1, 1976 }, -{ 0x7, 91, 0, 1975 }, -{ 0x6, 79, 1, 2120 }, -{ 0x3, 83, 0, 2119 }, -{ 0x1, 79, 1, 2128 }, -{ 0x1, 80, 1, 2127 }, -{ 0x1, 81, 1, 2126 }, -{ 0x1, 82, 0, 2125 }, -{ 0x3, 79, 1, 2124 }, -{ 0x3, 80, 1, 2123 }, -{ 0x3, 81, 1, 2122 }, -{ 0x3, 82, 0, 2121 }, -{ 0x8, 60, 1, 2060 }, -{ 0x2, 63, 1, 2057 }, -{ 0x1, 65, 1, 2059 }, -{ 0x1, 66, 1, 2058 }, -{ 0xf, 40, 1, 30 }, -{ 0x7, 41, 0, 29 }, -{ 0x18, 60, 1, 2056 }, -{ 0x6, 63, 1, 2053 }, -{ 0x3, 65, 1, 2055 }, -{ 0x3, 66, 1, 2054 }, -{ 0x1b, 40, 0, 15 }, -{ 0x14, 60, 1, 2050 }, -{ 0xa, 64, 1, 2049 }, -{ 0x35, 40, 0, 13 }, -{ 0x34, 60, 1, 1982 }, -{ 0xe, 70, 0, 1981 }, -{ 0xc, 60, 1, 2130 }, -{ 0x6, 64, 0, 2129 }, -{ 0x2, 60, 1, 1988 }, -{ 0x4, 63, 0, 1987 }, -{ 0x12, 60, 1, 1986 }, -{ 0xc, 63, 0, 1985 }, -{ 0xa, 60, 1, 2052 }, -{ 0x5, 64, 1, 2051 }, -{ 0x1d, 40, 1, 26 }, -{ 0xd, 41, 0, 25 }, -{ 0x1a, 60, 1, 1984 }, -{ 0x7, 70, 0, 1983 }, -{ 0x6, 60, 1, 2132 }, -{ 0x3, 64, 0, 2131 }, -{ 0x1, 60, 1, 2140 }, -{ 0x1, 61, 1, 2139 }, -{ 0x1, 62, 1, 2138 }, -{ 0x1, 63, 0, 2137 }, -{ 0x3, 60, 1, 2136 }, -{ 0x3, 61, 1, 2135 }, -{ 0x3, 62, 1, 2134 }, -{ 0x3, 63, 0, 2133 }, -{ 0x28, 76, 1, 2064 }, -{ 0x44, 77, 1, 2061 }, -{ 0x88, 77, 1, 2063 }, -{ 0x28, 78, 0, 2062 }, -{ 0x68, 76, 1, 1992 }, -{ 0x188, 77, 1, 1991 }, -{ 0x38, 89, 1, 1990 }, -{ 0x38, 90, 0, 1989 }, -{ 0x18, 76, 1, 2144 }, -{ 0x14, 77, 1, 2141 }, -{ 0x28, 77, 1, 2143 }, -{ 0x18, 78, 0, 2142 }, -{ 0x14, 76, 1, 2068 }, -{ 0x24, 77, 1, 2067 }, -{ 0x48, 77, 1, 2065 }, -{ 0x14, 78, 0, 2066 }, -{ 0x34, 76, 1, 1996 }, -{ 0x64, 77, 1, 1995 }, -{ 0x1c, 89, 1, 1994 }, -{ 0x1c, 90, 0, 1993 }, -{ 0xc, 76, 1, 2148 }, -{ 0xc, 77, 1, 2147 }, -{ 0x18, 77, 1, 2145 }, -{ 0xc, 78, 0, 2146 }, -{ 0xa, 76, 1, 2072 }, -{ 0x11, 77, 1, 2069 }, -{ 0x22, 77, 1, 2071 }, -{ 0xa, 78, 0, 2070 }, -{ 0x1a, 76, 1, 2000 }, -{ 0x62, 77, 1, 1999 }, -{ 0xe, 89, 1, 1998 }, -{ 0xe, 90, 0, 1997 }, -{ 0x6, 76, 1, 2152 }, -{ 0x5, 77, 1, 2149 }, -{ 0xa, 77, 1, 2151 }, -{ 0x6, 78, 0, 2150 }, -{ 0x5, 76, 1, 2076 }, -{ 0x9, 77, 1, 2075 }, -{ 0x12, 77, 1, 2073 }, -{ 0x5, 78, 0, 2074 }, -{ 0xd, 76, 1, 2004 }, -{ 0x19, 77, 1, 2003 }, -{ 0x7, 89, 1, 2002 }, -{ 0x7, 90, 0, 2001 }, -{ 0x3, 76, 1, 2156 }, -{ 0x3, 77, 1, 2155 }, -{ 0x6, 77, 1, 2153 }, -{ 0x3, 78, 0, 2154 }, -{ 0x28, 57, 1, 2080 }, -{ 0x44, 58, 1, 2077 }, -{ 0x88, 58, 1, 2079 }, -{ 0x28, 59, 0, 2078 }, -{ 0x68, 57, 1, 2008 }, -{ 0x188, 58, 1, 2007 }, -{ 0x38, 68, 1, 2006 }, -{ 0x38, 69, 0, 2005 }, -{ 0x18, 57, 1, 2160 }, -{ 0x14, 58, 1, 2157 }, -{ 0x28, 58, 1, 2159 }, -{ 0x18, 59, 0, 2158 }, -{ 0x14, 57, 1, 2084 }, -{ 0x24, 58, 1, 2083 }, -{ 0x48, 58, 1, 2081 }, -{ 0x14, 59, 0, 2082 }, -{ 0x34, 57, 1, 2012 }, -{ 0x64, 58, 1, 2011 }, -{ 0x1c, 68, 1, 2010 }, -{ 0x1c, 69, 0, 2009 }, -{ 0xc, 57, 1, 2164 }, -{ 0xc, 58, 1, 2163 }, -{ 0x18, 58, 1, 2161 }, -{ 0xc, 59, 0, 2162 }, -{ 0xa, 57, 1, 2088 }, -{ 0x11, 58, 1, 2085 }, -{ 0x22, 58, 1, 2087 }, -{ 0xa, 59, 0, 2086 }, -{ 0x1a, 57, 1, 2016 }, -{ 0x62, 58, 1, 2015 }, -{ 0xe, 68, 1, 2014 }, -{ 0xe, 69, 0, 2013 }, -{ 0x6, 57, 1, 2168 }, -{ 0x5, 58, 1, 2165 }, -{ 0xa, 58, 1, 2167 }, -{ 0x6, 59, 0, 2166 }, -{ 0x5, 57, 1, 2092 }, -{ 0x9, 58, 1, 2091 }, -{ 0x12, 58, 1, 2089 }, -{ 0x5, 59, 0, 2090 }, -{ 0xd, 57, 1, 2020 }, -{ 0x19, 58, 1, 2019 }, -{ 0x7, 68, 1, 2018 }, -{ 0x7, 69, 0, 2017 }, -{ 0x3, 57, 1, 2172 }, -{ 0x3, 58, 1, 2171 }, -{ 0x6, 58, 1, 2169 }, -{ 0x3, 59, 0, 2170 }, -{ 0x8, 71, 1, 2104 }, -{ 0x2, 72, 1, 2103 }, -{ 0x2, 73, 1, 2102 }, -{ 0x2, 74, 0, 2101 }, -{ 0x18, 71, 1, 2100 }, -{ 0x6, 72, 1, 2099 }, -{ 0x6, 73, 1, 2098 }, -{ 0x6, 74, 0, 2097 }, -{ 0x14, 71, 1, 2094 }, -{ 0xa, 75, 0, 2093 }, -{ 0x34, 71, 1, 2022 }, -{ 0xe, 88, 0, 2021 }, -{ 0xc, 71, 1, 2174 }, -{ 0x6, 75, 0, 2173 }, -{ 0x2, 71, 1, 2028 }, -{ 0x4, 74, 0, 2027 }, -{ 0x12, 71, 1, 2026 }, -{ 0xc, 74, 0, 2025 }, -{ 0xa, 71, 1, 2096 }, -{ 0x5, 75, 0, 2095 }, -{ 0x1a, 71, 1, 2024 }, -{ 0x7, 88, 0, 2023 }, -{ 0x6, 71, 1, 2176 }, -{ 0x3, 75, 0, 2175 }, -{ 0x1, 71, 1, 2184 }, -{ 0x1, 72, 1, 2183 }, -{ 0x1, 73, 1, 2182 }, -{ 0x1, 74, 0, 2181 }, -{ 0x3, 71, 1, 2180 }, -{ 0x3, 72, 1, 2179 }, -{ 0x3, 73, 1, 2178 }, -{ 0x3, 74, 0, 2177 }, -{ 0x8, 52, 1, 2116 }, -{ 0x2, 53, 1, 2115 }, -{ 0x2, 54, 1, 2114 }, -{ 0x2, 55, 0, 2113 }, -{ 0x18, 52, 1, 2112 }, -{ 0x6, 53, 1, 2111 }, -{ 0x6, 54, 1, 2110 }, -{ 0x6, 55, 0, 2109 }, -{ 0x14, 52, 1, 2106 }, -{ 0xa, 56, 0, 2105 }, -{ 0x34, 52, 1, 2030 }, -{ 0xe, 67, 0, 2029 }, -{ 0xc, 52, 1, 2186 }, -{ 0x6, 56, 0, 2185 }, -{ 0x2, 52, 1, 2036 }, -{ 0x4, 55, 0, 2035 }, -{ 0x12, 52, 1, 2034 }, -{ 0xc, 55, 0, 2033 }, -{ 0xa, 52, 1, 2108 }, -{ 0x5, 56, 0, 2107 }, -{ 0x1a, 52, 1, 2032 }, -{ 0x7, 67, 0, 2031 }, -{ 0x6, 52, 1, 2188 }, -{ 0x3, 56, 0, 2187 }, -{ 0x1, 52, 1, 2196 }, -{ 0x1, 53, 1, 2195 }, -{ 0x1, 54, 1, 2194 }, -{ 0x1, 55, 0, 2193 }, -{ 0x3, 52, 1, 2192 }, -{ 0x3, 53, 1, 2191 }, -{ 0x3, 54, 1, 2190 }, -{ 0x3, 55, 0, 2189 }, -{ 0x1, 4, 0, 2197 }, -{ 0x1, 254, 0, 2198 }, -{ 0x1, 336, 0, 2199 }, -{ 0x1, 331, 0, 2200 }, -{ 0x2, 315, 0, 2201 }, -{ 0x1, 315, 0, 2204 }, -{ 0x2, 314, 0, 2202 }, -{ 0x1, 314, 0, 2205 }, -{ 0x2, 313, 0, 2203 }, -{ 0x1, 313, 0, 2206 }, -{ 0x1, 312, 0, 2207 }, -{ 0x1, 311, 0, 2208 }, -{ 0x2, 310, 0, 2209 }, -{ 0x1, 310, 0, 2211 }, -{ 0x2, 309, 0, 2210 }, -{ 0x1, 309, 0, 2212 }, -{ 0x1, 339, 0, 2219 }, -{ 0x8, 338, 0, 2213 }, -{ 0x4, 338, 0, 2215 }, -{ 0x2, 338, 0, 2217 }, -{ 0x1, 338, 0, 2220 }, -{ 0x8, 337, 0, 2214 }, -{ 0x4, 337, 0, 2216 }, -{ 0x2, 337, 0, 2218 }, -{ 0x1, 337, 0, 2221 }, -{ 0x1, 308, 0, 2228 }, -{ 0x8, 307, 0, 2222 }, -{ 0x4, 307, 0, 2224 }, -{ 0x2, 307, 0, 2226 }, -{ 0x1, 307, 0, 2229 }, -{ 0x8, 306, 0, 2223 }, -{ 0x4, 306, 0, 2225 }, -{ 0x2, 306, 1, 2227 }, -{ 0x4, 107, 0, 1271 }, -{ 0x1, 306, 0, 2230 }, -{ 0x1, 6, 0, 2231 }, -{ 0x1, 7, 0, 2232 }, -{ 0x1, 253, 0, 2233 }, -{ 0x1, 252, 0, 2234 }, -{ 0x1, 403, 0, 2235 }, -{ 0x1, 303, 0, 2236 }, -{ 0x1, 12, 0, 2237 }, -{ 0x1, 10, 0, 2238 }, -{ 0x1, 378, 0, 2239 }, -{ 0x1, 351, 0, 2240 }, -{ 0x1, 350, 0, 2241 }, -{ 0x1, 402, 0, 2242 }, -{ 0x1, 302, 0, 2243 }, -{ 0x1, 11, 0, 2244 }, -{ 0x1, 9, 0, 2245 }, -{ 0x1, 5, 0, 2246 }, -{ 0x1, 377, 0, 2247 }, -{ 0x1, 376, 0, 2248 }, -{ 0x1, 1, 0, 2249 }, -{ 0x1, 0, 0, 2250 }, -}; - diff --git a/contrib/binutils/opcodes/ia64-asmtab.h b/contrib/binutils/opcodes/ia64-asmtab.h deleted file mode 100644 index 822007a..0000000 --- a/contrib/binutils/opcodes/ia64-asmtab.h +++ /dev/null @@ -1,148 +0,0 @@ -/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables. - Copyright 1999, 2000 Free Software Foundation, Inc. - Contributed by Bob Manson of Cygnus Support <manson@cygnus.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#ifndef IA64_ASMTAB_H -#define IA64_ASMTAB_H - -#include "opcode/ia64.h" - -/* The primary opcode table is made up of the following: */ -struct ia64_main_table -{ - /* The entry in the string table that corresponds to the name of this - opcode. */ - unsigned short name_index; - - /* The type of opcode; corresponds to the TYPE field in - struct ia64_opcode. */ - unsigned char opcode_type; - - /* The number of outputs for this opcode. */ - unsigned char num_outputs; - - /* The base insn value for this opcode. It may be modified by completers. */ - ia64_insn opcode; - - /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */ - ia64_insn mask; - - /* The operands of this instruction. Corresponds to the OPERANDS field - in struct ia64_opcode. */ - unsigned char operands[5]; - - /* The flags for this instruction. Corresponds to the FLAGS field in - struct ia64_opcode. */ - short flags; - - /* The tree of completers for this instruction; this is an offset into - completer_table. */ - short completers; -}; - -/* Each instruction has a set of possible "completers", or additional - suffixes that can alter the instruction's behavior, and which has - potentially different dependencies. - - The completer entries modify certain bits in the instruction opcode. - Which bits are to be modified are marked by the BITS, MASK and - OFFSET fields. The completer entry may also note dependencies for the - opcode. - - These completers are arranged in a DAG; the pointers are indexes - into the completer_table array. The completer DAG is searched by - find_completer () and ia64_find_matching_opcode (). - - Note that each completer needs to be applied in turn, so that if we - have the instruction - cmp.lt.unc - the completer entries for both "lt" and "unc" would need to be applied - to the opcode's value. - - Some instructions do not require any completers; these contain an - empty completer entry. Instructions that require a completer do - not contain an empty entry. - - Terminal completers (those completers that validly complete an - instruction) are marked by having the TERMINAL_COMPLETER flag set. - - Only dependencies listed in the terminal completer for an opcode are - considered to apply to that opcode instance. */ - -struct ia64_completer_table -{ - /* The bit value that this completer sets. */ - unsigned int bits; - - /* And its mask. 1s are bits that are to be modified in the - instruction. */ - unsigned int mask; - - /* The entry in the string table that corresponds to the name of this - completer. */ - unsigned short name_index; - - /* An alternative completer, or -1 if this is the end of the chain. */ - short alternative; - - /* A pointer to the DAG of completers that can potentially follow - this one, or -1. */ - short subentries; - - /* The bit offset in the instruction where BITS and MASK should be - applied. */ - unsigned char offset : 7; - - unsigned char terminal_completer : 1; - - /* Index into the dependency list table */ - short dependencies; -}; - -/* This contains sufficient information for the disassembler to resolve - the complete name of the original instruction. */ -struct ia64_dis_names -{ - /* COMPLETER_INDEX represents the tree of completers that make up - the instruction. The LSB represents the top of the tree for the - specified instruction. - - A 0 bit indicates to go to the next alternate completer via the - alternative field; a 1 bit indicates that the current completer - is part of the instruction, and to go down the subentries index. - We know we've reached the final completer when we run out of 1 - bits. - - There is always at least one 1 bit. */ - unsigned int completer_index : 20; - - /* The index in the main_table[] array for the instruction. */ - unsigned short insn_index : 11; - - /* If set, the next entry in this table is an alternate possibility - for this instruction encoding. Which one to use is determined by - the instruction type and other factors (see opcode_verify ()). */ - unsigned int next_flag : 1; - - /* The disassembly priority of this entry among instructions. */ - unsigned short priority; -}; - -#endif diff --git a/contrib/binutils/opcodes/ia64-dis.c b/contrib/binutils/opcodes/ia64-dis.c deleted file mode 100644 index 4c63815..0000000 --- a/contrib/binutils/opcodes/ia64-dis.c +++ /dev/null @@ -1,273 +0,0 @@ -/* ia64-dis.c -- Disassemble ia64 instructions - Copyright 1998, 1999, 2000 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <assert.h> -#include <string.h> - -#include "dis-asm.h" -#include "opcode/ia64.h" - -#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0]))) - -/* Disassemble ia64 instruction. */ - -/* Return the instruction type for OPCODE found in unit UNIT. */ - -static enum ia64_insn_type -unit_to_type (ia64_insn opcode, enum ia64_unit unit) -{ - enum ia64_insn_type type; - int op; - - op = IA64_OP (opcode); - - if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M)) - { - type = IA64_TYPE_A; - } - else - { - switch (unit) - { - case IA64_UNIT_I: - type = IA64_TYPE_I; break; - case IA64_UNIT_M: - type = IA64_TYPE_M; break; - case IA64_UNIT_B: - type = IA64_TYPE_B; break; - case IA64_UNIT_F: - type = IA64_TYPE_F; break; - case IA64_UNIT_L: - case IA64_UNIT_X: - type = IA64_TYPE_X; break; - default: - type = -1; - } - } - return type; -} - -int -print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) -{ - ia64_insn t0, t1, slot[3], template, s_bit, insn; - int slotnum, j, status, need_comma, retval, slot_multiplier; - const struct ia64_operand *odesc; - const struct ia64_opcode *idesc; - const char *err, *str, *tname; - BFD_HOST_U_64_BIT value; - bfd_byte bundle[16]; - enum ia64_unit unit; - char regname[16]; - - if (info->bytes_per_line == 0) - info->bytes_per_line = 6; - info->display_endian = info->endian; - - slot_multiplier = info->bytes_per_line; - retval = slot_multiplier; - - slotnum = (((long) memaddr) & 0xf) / slot_multiplier; - if (slotnum > 2) - return -1; - - memaddr -= (memaddr & 0xf); - status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - /* bundles are always in little-endian byte order */ - t0 = bfd_getl64 (bundle); - t1 = bfd_getl64 (bundle + 8); - s_bit = t0 & 1; - template = (t0 >> 1) & 0xf; - slot[0] = (t0 >> 5) & 0x1ffffffffffLL; - slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); - slot[2] = (t1 >> 23) & 0x1ffffffffffLL; - - tname = ia64_templ_desc[template].name; - if (slotnum == 0) - (*info->fprintf_func) (info->stream, "[%s] ", tname); - else - (*info->fprintf_func) (info->stream, " ", tname); - - unit = ia64_templ_desc[template].exec_unit[slotnum]; - - if (template == 2 && slotnum == 1) - { - /* skip L slot in MLI template: */ - slotnum = 2; - retval += slot_multiplier; - } - - insn = slot[slotnum]; - - if (unit == IA64_UNIT_NIL) - goto decoding_failed; - - idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit)); - if (idesc == NULL) - goto decoding_failed; - - /* print predicate, if any: */ - - if ((idesc->flags & IA64_OPCODE_NO_PRED) - || (insn & 0x3f) == 0) - (*info->fprintf_func) (info->stream, " "); - else - (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f)); - - /* now the actual instruction: */ - - (*info->fprintf_func) (info->stream, "%s", idesc->name); - if (idesc->operands[0]) - (*info->fprintf_func) (info->stream, " "); - - need_comma = 0; - for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j) - { - odesc = elf64_ia64_operands + idesc->operands[j]; - - if (need_comma) - (*info->fprintf_func) (info->stream, ","); - - if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) - { - /* special case of 64 bit immediate load: */ - value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7) - | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21) - | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63); - } - else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) - { - /* 62-bit immediate for nop.x/break.x */ - value = ((slot[1] & 0x1ffffffffffLL) << 21) - | (((insn >> 36) & 0x1) << 20) - | ((insn >> 6) & 0xfffff); - } - else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) - { - /* 60-bit immediate for long branches. */ - value = (((insn >> 13) & 0xfffff) - | (((insn >> 36) & 1) << 59) - | (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4; - } - else - { - err = (*odesc->extract) (odesc, insn, &value); - if (err) - { - (*info->fprintf_func) (info->stream, "%s", err); - goto done; - } - } - - switch (odesc->class) - { - case IA64_OPND_CLASS_CST: - (*info->fprintf_func) (info->stream, "%s", odesc->str); - break; - - case IA64_OPND_CLASS_REG: - if (odesc->str[0] == 'a' && odesc->str[1] == 'r') - { - switch (value) - { - case 0: case 1: case 2: case 3: - case 4: case 5: case 6: case 7: - sprintf (regname, "ar.k%u", (unsigned int) value); - break; - case 16: strcpy (regname, "ar.rsc"); break; - case 17: strcpy (regname, "ar.bsp"); break; - case 18: strcpy (regname, "ar.bspstore"); break; - case 19: strcpy (regname, "ar.rnat"); break; - case 32: strcpy (regname, "ar.ccv"); break; - case 36: strcpy (regname, "ar.unat"); break; - case 40: strcpy (regname, "ar.fpsr"); break; - case 44: strcpy (regname, "ar.itc"); break; - case 64: strcpy (regname, "ar.pfs"); break; - case 65: strcpy (regname, "ar.lc"); break; - case 66: strcpy (regname, "ar.ec"); break; - default: - sprintf (regname, "ar%u", (unsigned int) value); - break; - } - (*info->fprintf_func) (info->stream, "%s", regname); - } - else - (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value); - break; - - case IA64_OPND_CLASS_IND: - (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value); - break; - - case IA64_OPND_CLASS_ABS: - str = 0; - if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4) - switch (value) - { - case 0x0: str = "@brcst"; break; - case 0x8: str = "@mix"; break; - case 0x9: str = "@shuf"; break; - case 0xa: str = "@alt"; break; - case 0xb: str = "@rev"; break; - } - - if (str) - (*info->fprintf_func) (info->stream, "%s", str); - else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED) - (*info->fprintf_func) (info->stream, "%lld", value); - else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED) - (*info->fprintf_func) (info->stream, "%llu", value); - else - (*info->fprintf_func) (info->stream, "0x%llx", value); - break; - - case IA64_OPND_CLASS_REL: - (*info->print_address_func) (memaddr + value, info); - break; - } - - need_comma = 1; - if (j + 1 == idesc->num_outputs) - { - (*info->fprintf_func) (info->stream, "="); - need_comma = 0; - } - } - if (slotnum + 1 == ia64_templ_desc[template].group_boundary - || ((slotnum == 2) && s_bit)) - (*info->fprintf_func) (info->stream, ";;"); - - done: - ia64_free_opcode ((struct ia64_opcode *)idesc); - failed: - if (slotnum == 2) - retval += 16 - 3*slot_multiplier; - return retval; - - decoding_failed: - (*info->fprintf_func) (info->stream, " data8 %#011llx", insn); - goto failed; -} diff --git a/contrib/binutils/opcodes/ia64-gen.c b/contrib/binutils/opcodes/ia64-gen.c deleted file mode 100644 index a4e2cec..0000000 --- a/contrib/binutils/opcodes/ia64-gen.c +++ /dev/null @@ -1,2814 +0,0 @@ -/* ia64-gen.c -- Generate a shrunk set of opcode tables - Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. - Written by Bob Manson, Cygnus Solutions, <manson@cygnus.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -/* While the ia64-opc-* set of opcode tables are easy to maintain, - they waste a tremendous amount of space. ia64-gen rearranges the - instructions into a directed acyclic graph (DAG) of instruction opcodes and - their possible completers, as well as compacting the set of strings used. - - The disassembler table consists of a state machine that does - branching based on the bits of the opcode being disassembled. The - state encodings have been chosen to minimize the amount of space - required. - - The resource table is constructed based on some text dependency tables, - which are also easier to maintain than the final representation. */ - -#include <stdio.h> -#include <stdarg.h> -#include <errno.h> - -#include "ansidecl.h" -#include "libiberty.h" -#include "safe-ctype.h" -#include "sysdep.h" -#include "getopt.h" -#include "ia64-opc.h" -#include "ia64-opc-a.c" -#include "ia64-opc-i.c" -#include "ia64-opc-m.c" -#include "ia64-opc-b.c" -#include "ia64-opc-f.c" -#include "ia64-opc-x.c" -#include "ia64-opc-d.c" - -#include <libintl.h> -#define _(String) gettext (String) - -const char * program_name = NULL; -int debug = 0; - -#define tmalloc(X) (X *) xmalloc (sizeof (X)) - -/* The main opcode table entry. Each entry is a unique combination of - name and flags (no two entries in the table compare as being equal - via opcodes_eq). */ -struct main_entry -{ - /* The base name of this opcode. The names of its completers are - appended to it to generate the full instruction name. */ - struct string_entry *name; - /* The base opcode entry. Which one to use is a fairly arbitrary choice; - it uses the first one passed to add_opcode_entry. */ - struct ia64_opcode *opcode; - /* The list of completers that can be applied to this opcode. */ - struct completer_entry *completers; - /* Next entry in the chain. */ - struct main_entry *next; - /* Index in the main table. */ - int main_index; -} *maintable, **ordered_table; - -int otlen = 0; -int ottotlen = 0; -int opcode_count = 0; - -/* The set of possible completers for an opcode. */ -struct completer_entry -{ - /* This entry's index in the ia64_completer_table[] array. */ - int num; - - /* The name of the completer. */ - struct string_entry *name; - - /* This entry's parent. */ - struct completer_entry *parent; - - /* Set if this is a terminal completer (occurs at the end of an - opcode). */ - int is_terminal; - - /* An alternative completer. */ - struct completer_entry *alternative; - - /* Additional completers that can be appended to this one. */ - struct completer_entry *addl_entries; - - /* Before compute_completer_bits () is invoked, this contains the actual - instruction opcode for this combination of opcode and completers. - Afterwards, it contains those bits that are different from its - parent opcode. */ - ia64_insn bits; - - /* Bits set to 1 correspond to those bits in this completer's opcode - that are different from its parent completer's opcode (or from - the base opcode if the entry is the root of the opcode's completer - list). This field is filled in by compute_completer_bits (). */ - ia64_insn mask; - - /* Index into the opcode dependency list, or -1 if none. */ - int dependencies; - - /* Remember the order encountered in the opcode tables. */ - int order; -}; - -/* One entry in the disassembler name table. */ -struct disent -{ - /* The index into the ia64_name_dis array for this entry. */ - int ournum; - - /* The index into the main_table[] array. */ - int insn; - - /* The disassmbly priority of this entry. */ - int priority; - - /* The completer_index value for this entry. */ - int completer_index; - - /* How many other entries share this decode. */ - int nextcnt; - - /* The next entry sharing the same decode. */ - struct disent *nexte; - - /* The next entry in the name list. */ - struct disent *next_ent; -} *disinsntable = NULL; - -/* A state machine that will eventually be used to generate the - disassembler table. */ -struct bittree -{ - struct disent *disent; - struct bittree *bits[3]; /* 0, 1, and X (don't care). */ - int bits_to_skip; - int skip_flag; -} *bittree; - -/* The string table contains all opcodes and completers sorted in - alphabetical order. */ - -/* One entry in the string table. */ -struct string_entry -{ - /* The index in the ia64_strings[] array for this entry. */ - int num; - /* And the string. */ - char *s; -} **string_table = NULL; - -int strtablen = 0; -int strtabtotlen = 0; - - -/* Resource dependency entries. */ -struct rdep -{ - char *name; /* Resource name. */ - unsigned - mode:2, /* RAW, WAW, or WAR. */ - semantics:3; /* Dependency semantics. */ - char *extra; /* Additional semantics info. */ - int nchks; - int total_chks; /* Total #of terminal insns. */ - int *chks; /* Insn classes which read (RAW), write - (WAW), or write (WAR) this rsrc. */ - int *chknotes; /* Dependency notes for each class. */ - int nregs; - int total_regs; /* Total #of terminal insns. */ - int *regs; /* Insn class which write (RAW), write2 - (WAW), or read (WAR) this rsrc. */ - int *regnotes; /* Dependency notes for each class. */ - - int waw_special; /* Special WAW dependency note. */ -} **rdeps = NULL; - -static int rdepslen = 0; -static int rdepstotlen = 0; - -/* Array of all instruction classes. */ -struct iclass -{ - char *name; /* Instruction class name. */ - int is_class; /* Is a class, not a terminal. */ - int nsubs; - int *subs; /* Other classes within this class. */ - int nxsubs; - int xsubs[4]; /* Exclusions. */ - char *comment; /* Optional comment. */ - int note; /* Optional note. */ - int terminal_resolved; /* Did we match this with anything? */ - int orphan; /* Detect class orphans. */ -} **ics = NULL; - -static int iclen = 0; -static int ictotlen = 0; - -/* An opcode dependency (chk/reg pair of dependency lists). */ -struct opdep -{ - int chk; /* index into dlists */ - int reg; /* index into dlists */ -} **opdeps; - -static int opdeplen = 0; -static int opdeptotlen = 0; - -/* A generic list of dependencies w/notes encoded. These may be shared. */ -struct deplist -{ - int len; - unsigned short *deps; -} **dlists; - -static int dlistlen = 0; -static int dlisttotlen = 0; - - -static void fail (const char *, ...); -static void warn (const char *, ...); -static struct rdep * insert_resource (const char *, enum ia64_dependency_mode); -static int deplist_equals (struct deplist *, struct deplist *); -static short insert_deplist (int, unsigned short *); -static short insert_dependencies (int, unsigned short *, int, unsigned short *); -static void mark_used (struct iclass *, int); -static int fetch_insn_class (const char *, int); -static int sub_compare (const void *, const void *); -static void load_insn_classes (void); -static void parse_resource_users (const char *, int **, int *, int **); -static int parse_semantics (char *); -static void add_dep (const char *, const char *, const char *, int, int, char *, int); -static void load_depfile (const char *, enum ia64_dependency_mode); -static void load_dependencies (void); -static int irf_operand (int, const char *); -static int in_iclass_mov_x (struct ia64_opcode *, struct iclass *, const char *, const char *); -static int in_iclass (struct ia64_opcode *, struct iclass *, const char *, const char *, int *); -static int lookup_regindex (const char *, int); -static int lookup_specifier (const char *); -static void print_dependency_table (void); -static struct string_entry * insert_string (char *); -static void gen_dis_table (struct bittree *); -static void print_dis_table (void); -static void generate_disassembler (void); -static void print_string_table (void); -static int completer_entries_eq (struct completer_entry *, struct completer_entry *); -static struct completer_entry * insert_gclist (struct completer_entry *); -static int get_prefix_len (const char *); -static void compute_completer_bits (struct main_entry *, struct completer_entry *); -static void collapse_redundant_completers (void); -static int insert_opcode_dependencies (struct ia64_opcode *, struct completer_entry *); -static void insert_completer_entry (struct ia64_opcode *, struct main_entry *, int); -static void print_completer_entry (struct completer_entry *); -static void print_completer_table (void); -static int opcodes_eq (struct ia64_opcode *, struct ia64_opcode *); -static void add_opcode_entry (struct ia64_opcode *); -static void print_main_table (void); -static void shrink (struct ia64_opcode *); -static void print_version (void); -static void usage (FILE *, int); -static void finish_distable (void); -static void insert_bit_table_ent (struct bittree *, int, ia64_insn, ia64_insn, int, int, int); -static void add_dis_entry (struct bittree *, ia64_insn, ia64_insn, int, struct completer_entry *, int); -static void compact_distree (struct bittree *); -static struct bittree * make_bittree_entry (void); -static struct disent * add_dis_table_ent (struct disent *, int, int, int); - - -static void -fail (const char *message, ...) -{ - va_list args; - - va_start (args, message); - fprintf (stderr, _("%s: Error: "), program_name); - vfprintf (stderr, message, args); - va_end (args); - xexit (1); -} - -static void -warn (const char *message, ...) -{ - va_list args; - - va_start (args, message); - - fprintf (stderr, _("%s: Warning: "), program_name); - vfprintf (stderr, message, args); - va_end (args); -} - -/* Add NAME to the resource table, where TYPE is RAW or WAW. */ -static struct rdep * -insert_resource (const char *name, enum ia64_dependency_mode type) -{ - if (rdepslen == rdepstotlen) - { - rdepstotlen += 20; - rdeps = (struct rdep **) - xrealloc (rdeps, sizeof(struct rdep **) * rdepstotlen); - } - rdeps[rdepslen] = tmalloc(struct rdep); - memset((void *)rdeps[rdepslen], 0, sizeof(struct rdep)); - rdeps[rdepslen]->name = xstrdup (name); - rdeps[rdepslen]->mode = type; - rdeps[rdepslen]->waw_special = 0; - - return rdeps[rdepslen++]; -} - -/* Are the lists of dependency indexes equivalent? */ -static int -deplist_equals (struct deplist *d1, struct deplist *d2) -{ - int i; - - if (d1->len != d2->len) - return 0; - - for (i = 0; i < d1->len; i++) - if (d1->deps[i] != d2->deps[i]) - return 0; - - return 1; -} - -/* Add the list of dependencies to the list of dependency lists. */ -static short -insert_deplist (int count, unsigned short *deps) -{ - /* Sort the list, then see if an equivalent list exists already. - this results in a much smaller set of dependency lists. */ - struct deplist *list; - char set[0x10000]; - int i; - - memset ((void *)set, 0, sizeof (set)); - for (i = 0; i < count; i++) - set[deps[i]] = 1; - - count = 0; - for (i = 0; i < (int) sizeof (set); i++) - if (set[i]) - ++count; - - list = tmalloc (struct deplist); - list->len = count; - list->deps = (unsigned short *) malloc (sizeof (unsigned short) * count); - - for (i = 0, count = 0; i < (int) sizeof (set); i++) - if (set[i]) - list->deps[count++] = i; - - /* Does this list exist already? */ - for (i = 0; i < dlistlen; i++) - if (deplist_equals (list, dlists[i])) - { - free (list->deps); - free (list); - return i; - } - - if (dlistlen == dlisttotlen) - { - dlisttotlen += 20; - dlists = (struct deplist **) - xrealloc (dlists, sizeof(struct deplist **) * dlisttotlen); - } - dlists[dlistlen] = list; - - return dlistlen++; -} - -/* Add the given pair of dependency lists to the opcode dependency list. */ -static short -insert_dependencies (int nchks, unsigned short *chks, - int nregs, unsigned short *regs) -{ - struct opdep *pair; - int i; - int regind = -1; - int chkind = -1; - - if (nregs > 0) - regind = insert_deplist (nregs, regs); - if (nchks > 0) - chkind = insert_deplist (nchks, chks); - - for (i = 0; i < opdeplen; i++) - if (opdeps[i]->chk == chkind - && opdeps[i]->reg == regind) - return i; - - pair = tmalloc (struct opdep); - pair->chk = chkind; - pair->reg = regind; - - if (opdeplen == opdeptotlen) - { - opdeptotlen += 20; - opdeps = (struct opdep **) - xrealloc (opdeps, sizeof(struct opdep **) * opdeptotlen); - } - opdeps[opdeplen] = pair; - - return opdeplen++; -} - -static void -mark_used (struct iclass *ic, int clear_terminals) -{ - int i; - - ic->orphan = 0; - if (clear_terminals) - ic->terminal_resolved = 1; - - for (i = 0; i < ic->nsubs; i++) - mark_used (ics[ic->subs[i]], clear_terminals); - - for (i = 0; i < ic->nxsubs; i++) - mark_used (ics[ic->xsubs[i]], clear_terminals); -} - -/* Look up an instruction class; if CREATE make a new one if none found; - returns the index into the insn class array. */ -static int -fetch_insn_class (const char *full_name, int create) -{ - char *name; - char *notestr; - char *xsect; - char *comment; - int i, note = 0; - int ind; - int is_class = 0; - - if (strncmp (full_name, "IC:", 3) == 0) - { - name = xstrdup (full_name + 3); - is_class = 1; - } - else - name = xstrdup (full_name); - - if ((xsect = strchr(name, '\\')) != NULL) - is_class = 1; - if ((comment = strchr(name, '[')) != NULL) - is_class = 1; - if ((notestr = strchr(name, '+')) != NULL) - is_class = 1; - - /* If it is a composite class, then ignore comments and notes that come after - the '\\', since they don't apply to the part we are decoding now. */ - if (xsect) - { - if (comment > xsect) - comment = 0; - if (notestr > xsect) - notestr = 0; - } - - if (notestr) - { - char *nextnotestr; - - note = atoi (notestr + 1); - if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) - { - if (strcmp (notestr, "+1+13") == 0) - note = 13; - else if (!xsect || nextnotestr < xsect) - warn (_("multiple note %s not handled\n"), notestr); - } - } - - /* If it's a composite class, leave the notes and comments in place so that - we have a unique name for the composite class. Otherwise, we remove - them. */ - if (!xsect) - { - if (notestr) - *notestr = 0; - if (comment) - *comment = 0; - } - - for (i = 0; i < iclen; i++) - if (strcmp (name, ics[i]->name) == 0 - && ((comment == NULL && ics[i]->comment == NULL) - || (comment != NULL && ics[i]->comment != NULL - && strncmp (ics[i]->comment, comment, - strlen (ics[i]->comment)) == 0)) - && note == ics[i]->note) - return i; - - if (!create) - return -1; - - /* Doesn't exist, so make a new one. */ - if (iclen == ictotlen) - { - ictotlen += 20; - ics = (struct iclass **) - xrealloc (ics, (ictotlen) * sizeof (struct iclass *)); - } - - ind = iclen++; - ics[ind] = tmalloc (struct iclass); - memset ((void *)ics[ind], 0, sizeof (struct iclass)); - ics[ind]->name = xstrdup (name); - ics[ind]->is_class = is_class; - ics[ind]->orphan = 1; - - if (comment) - { - ics[ind]->comment = xstrdup (comment + 1); - ics[ind]->comment[strlen (ics[ind]->comment)-1] = 0; - } - - if (notestr) - ics[ind]->note = note; - - /* If it's a composite class, there's a comment or note, look for an - existing class or terminal with the same name. */ - if ((xsect || comment || notestr) && is_class) - { - /* First, populate with the class we're based on. */ - char *subname = name; - - if (xsect) - *xsect = 0; - else if (comment) - *comment = 0; - else if (notestr) - *notestr = 0; - - ics[ind]->nsubs = 1; - ics[ind]->subs = tmalloc(int); - ics[ind]->subs[0] = fetch_insn_class (subname, 1);; - } - - while (xsect) - { - char *subname = xsect + 1; - - xsect = strchr (subname, '\\'); - if (xsect) - *xsect = 0; - ics[ind]->xsubs[ics[ind]->nxsubs] = fetch_insn_class (subname,1); - ics[ind]->nxsubs++; - } - free (name); - - return ind; -} - -/* For sorting a class's sub-class list only; make sure classes appear before - terminals. */ -static int -sub_compare (const void *e1, const void *e2) -{ - struct iclass *ic1 = ics[*(int *)e1]; - struct iclass *ic2 = ics[*(int *)e2]; - - if (ic1->is_class) - { - if (!ic2->is_class) - return -1; - } - else if (ic2->is_class) - return 1; - - return strcmp (ic1->name, ic2->name); -} - -static void -load_insn_classes (void) -{ - FILE *fp = fopen ("ia64-ic.tbl", "r"); - char buf[2048]; - - if (fp == NULL) - fail (_("can't find ia64-ic.tbl for reading\n")); - - /* Discard first line. */ - fgets (buf, sizeof(buf), fp); - - while (!feof (fp)) - { - int iclass; - char *name; - char *tmp; - - if (fgets (buf, sizeof (buf), fp) == NULL) - break; - - while (ISSPACE (buf[strlen (buf) - 1])) - buf[strlen (buf) - 1] = '\0'; - - name = tmp = buf; - while (*tmp != ';') - { - ++tmp; - if (tmp == buf + sizeof (buf)) - abort (); - } - *tmp++ = '\0'; - - iclass = fetch_insn_class (name, 1); - ics[iclass]->is_class = 1; - - if (strcmp (name, "none") == 0) - { - ics[iclass]->is_class = 0; - ics[iclass]->terminal_resolved = 1; - continue; - } - - /* For this class, record all sub-classes. */ - while (*tmp) - { - char *subname; - int sub; - - while (*tmp && ISSPACE (*tmp)) - { - ++tmp; - if (tmp == buf + sizeof (buf)) - abort (); - } - subname = tmp; - while (*tmp && *tmp != ',') - { - ++tmp; - if (tmp == buf + sizeof (buf)) - abort (); - } - if (*tmp == ',') - *tmp++ = '\0'; - - ics[iclass]->subs = (int *) - xrealloc ((void *)ics[iclass]->subs, - (ics[iclass]->nsubs + 1) * sizeof (int)); - - sub = fetch_insn_class (subname, 1); - ics[iclass]->subs = (int *) - xrealloc (ics[iclass]->subs, (ics[iclass]->nsubs + 1) * sizeof (int)); - ics[iclass]->subs[ics[iclass]->nsubs++] = sub; - } - - /* Make sure classes come before terminals. */ - qsort ((void *)ics[iclass]->subs, - ics[iclass]->nsubs, sizeof(int), sub_compare); - } - fclose (fp); - - if (debug) - printf ("%d classes\n", iclen); -} - -/* Extract the insn classes from the given line. */ -static void -parse_resource_users (ref, usersp, nusersp, notesp) - const char *ref; - int **usersp; - int *nusersp; - int **notesp; -{ - int c; - char *line = xstrdup (ref); - char *tmp = line; - int *users = *usersp; - int count = *nusersp; - int *notes = *notesp; - - c = *tmp; - while (c != 0) - { - char *notestr; - int note; - char *xsect; - int iclass; - int create = 0; - char *name; - - while (ISSPACE (*tmp)) - ++tmp; - name = tmp; - while (*tmp && *tmp != ',') - ++tmp; - c = *tmp; - *tmp++ = '\0'; - - xsect = strchr (name, '\\'); - if ((notestr = strstr (name, "+")) != NULL) - { - char *nextnotestr; - - note = atoi (notestr + 1); - if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) - { - /* Note 13 always implies note 1. */ - if (strcmp (notestr, "+1+13") == 0) - note = 13; - else if (!xsect || nextnotestr < xsect) - warn (_("multiple note %s not handled\n"), notestr); - } - if (!xsect) - *notestr = '\0'; - } - else - note = 0; - - /* All classes are created when the insn class table is parsed; - Individual instructions might not appear until the dependency tables - are read. Only create new classes if it's *not* an insn class, - or if it's a composite class (which wouldn't necessarily be in the IC - table). */ - if (strncmp (name, "IC:", 3) != 0 || xsect != NULL) - create = 1; - - iclass = fetch_insn_class (name, create); - if (iclass != -1) - { - users = (int *) - xrealloc ((void *) users,(count + 1) * sizeof (int)); - notes = (int *) - xrealloc ((void *) notes,(count + 1) * sizeof (int)); - notes[count] = note; - users[count++] = iclass; - mark_used (ics[iclass], 0); - } - else if (debug) - printf("Class %s not found\n", name); - } - /* Update the return values. */ - *usersp = users; - *nusersp = count; - *notesp = notes; - - free (line); -} - -static int -parse_semantics (char *sem) -{ - if (strcmp (sem, "none") == 0) - return IA64_DVS_NONE; - else if (strcmp (sem, "implied") == 0) - return IA64_DVS_IMPLIED; - else if (strcmp (sem, "impliedF") == 0) - return IA64_DVS_IMPLIEDF; - else if (strcmp (sem, "data") == 0) - return IA64_DVS_DATA; - else if (strcmp (sem, "instr") == 0) - return IA64_DVS_INSTR; - else if (strcmp (sem, "specific") == 0) - return IA64_DVS_SPECIFIC; - else if (strcmp (sem, "stop") == 0) - return IA64_DVS_STOP; - else - return IA64_DVS_OTHER; -} - -static void -add_dep (const char *name, const char *chk, const char *reg, - int semantics, int mode, char *extra, int flag) -{ - struct rdep *rs; - - rs = insert_resource (name, mode); - - parse_resource_users (chk, &rs->chks, &rs->nchks, &rs->chknotes); - parse_resource_users (reg, &rs->regs, &rs->nregs, &rs->regnotes); - - rs->semantics = semantics; - rs->extra = extra; - rs->waw_special = flag; -} - -static void -load_depfile (const char *filename, enum ia64_dependency_mode mode) -{ - FILE *fp = fopen (filename, "r"); - char buf[1024]; - - if (fp == NULL) - fail (_("can't find %s for reading\n"), filename); - - fgets (buf, sizeof(buf), fp); - while (!feof (fp)) - { - char *name, *tmp; - int semantics; - char *extra; - char *regp, *chkp; - - if (fgets (buf, sizeof(buf), fp) == NULL) - break; - - while (ISSPACE (buf[strlen (buf) - 1])) - buf[strlen (buf) - 1] = '\0'; - - name = tmp = buf; - while (*tmp != ';') - ++tmp; - *tmp++ = '\0'; - - while (ISSPACE (*tmp)) - ++tmp; - regp = tmp; - tmp = strchr (tmp, ';'); - if (!tmp) - abort (); - *tmp++ = 0; - while (ISSPACE (*tmp)) - ++tmp; - chkp = tmp; - tmp = strchr (tmp, ';'); - if (!tmp) - abort (); - *tmp++ = 0; - while (ISSPACE (*tmp)) - ++tmp; - semantics = parse_semantics (tmp); - extra = semantics == IA64_DVS_OTHER ? xstrdup (tmp) : NULL; - - /* For WAW entries, if the chks and regs differ, we need to enter the - entries in both positions so that the tables will be parsed properly, - without a lot of extra work. */ - if (mode == IA64_DV_WAW && strcmp (regp, chkp) != 0) - { - add_dep (name, chkp, regp, semantics, mode, extra, 0); - add_dep (name, regp, chkp, semantics, mode, extra, 1); - } - else - { - add_dep (name, chkp, regp, semantics, mode, extra, 0); - } - } - fclose (fp); -} - -static void -load_dependencies (void) -{ - load_depfile ("ia64-raw.tbl", IA64_DV_RAW); - load_depfile ("ia64-waw.tbl", IA64_DV_WAW); - load_depfile ("ia64-war.tbl", IA64_DV_WAR); - - if (debug) - printf ("%d RAW/WAW/WAR dependencies\n", rdepslen); -} - -/* Is the given operand an indirect register file operand? */ -static int -irf_operand (int op, const char *field) -{ - if (!field) - { - return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3 - || op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3 - || op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3 - || op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3; - } - else - { - return ((op == IA64_OPND_RR_R3 && strstr (field, "rr")) - || (op == IA64_OPND_DBR_R3 && strstr (field, "dbr")) - || (op == IA64_OPND_IBR_R3 && strstr (field, "ibr")) - || (op == IA64_OPND_PKR_R3 && strstr (field, "pkr")) - || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc")) - || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd")) - || (op == IA64_OPND_MSR_R3 && strstr (field, "msr")) - || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid"))); - } -} - -/* Handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and - mov_um insn classes. */ -static int -in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, - const char *format, const char *field) -{ - int plain_mov = strcmp (idesc->name, "mov") == 0; - - if (!format) - return 0; - - switch (ic->name[4]) - { - default: - abort (); - case 'a': - { - int i = strcmp (idesc->name, "mov.i") == 0; - int m = strcmp (idesc->name, "mov.m") == 0; - int i2627 = i && idesc->operands[0] == IA64_OPND_AR3; - int i28 = i && idesc->operands[1] == IA64_OPND_AR3; - int m2930 = m && idesc->operands[0] == IA64_OPND_AR3; - int m31 = m && idesc->operands[1] == IA64_OPND_AR3; - int pseudo0 = plain_mov && idesc->operands[1] == IA64_OPND_AR3; - int pseudo1 = plain_mov && idesc->operands[0] == IA64_OPND_AR3; - - /* IC:mov ar */ - if (i2627) - return strstr (format, "I26") || strstr (format, "I27"); - if (i28) - return strstr (format, "I28") != NULL; - if (m2930) - return strstr (format, "M29") || strstr (format, "M30"); - if (m31) - return strstr (format, "M31") != NULL; - if (pseudo0 || pseudo1) - return 1; - } - break; - case 'b': - { - int i21 = idesc->operands[0] == IA64_OPND_B1; - int i22 = plain_mov && idesc->operands[1] == IA64_OPND_B2; - if (i22) - return strstr (format, "I22") != NULL; - if (i21) - return strstr (format, "I21") != NULL; - } - break; - case 'c': - { - int m32 = plain_mov && idesc->operands[0] == IA64_OPND_CR3; - int m33 = plain_mov && idesc->operands[1] == IA64_OPND_CR3; - if (m32) - return strstr (format, "M32") != NULL; - if (m33) - return strstr (format, "M33") != NULL; - } - break; - case 'i': - if (ic->name[5] == 'n') - { - int m42 = plain_mov && irf_operand (idesc->operands[0], field); - int m43 = plain_mov && irf_operand (idesc->operands[1], field); - if (m42) - return strstr (format, "M42") != NULL; - if (m43) - return strstr (format, "M43") != NULL; - } - else if (ic->name[5] == 'p') - { - return idesc->operands[1] == IA64_OPND_IP; - } - else - abort (); - break; - case 'p': - if (ic->name[5] == 'r') - { - int i25 = plain_mov && idesc->operands[1] == IA64_OPND_PR; - int i23 = plain_mov && idesc->operands[0] == IA64_OPND_PR; - int i24 = plain_mov && idesc->operands[0] == IA64_OPND_PR_ROT; - if (i23) - return strstr (format, "I23") != NULL; - if (i24) - return strstr (format, "I24") != NULL; - if (i25) - return strstr (format, "I25") != NULL; - } - else if (ic->name[5] == 's') - { - int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_L; - int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR; - if (m35) - return strstr (format, "M35") != NULL; - if (m36) - return strstr (format, "M36") != NULL; - } - else - abort (); - break; - case 'u': - { - int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_UM; - int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR_UM; - if (m35) - return strstr (format, "M35") != NULL; - if (m36) - return strstr (format, "M36") != NULL; - } - break; - } - return 0; -} - -/* Is the given opcode in the given insn class? */ -static int -in_iclass (struct ia64_opcode *idesc, struct iclass *ic, - const char *format, const char *field, int *notep) -{ - int i; - int resolved = 0; - - if (ic->comment) - { - if (!strncmp (ic->comment, "Format", 6)) - { - /* Assume that the first format seen is the most restrictive, and - only keep a later one if it looks like it's more restrictive. */ - if (format) - { - if (strlen (ic->comment) < strlen (format)) - { - warn (_("most recent format '%s'\nappears more restrictive than '%s'\n"), - ic->comment, format); - format = ic->comment; - } - } - else - format = ic->comment; - } - else if (!strncmp (ic->comment, "Field", 5)) - { - if (field) - warn (_("overlapping field %s->%s\n"), - ic->comment, field); - field = ic->comment; - } - } - - /* An insn class matches anything that is the same followed by completers, - except when the absence and presence of completers constitutes different - instructions. */ - if (ic->nsubs == 0 && ic->nxsubs == 0) - { - int is_mov = strncmp (idesc->name, "mov", 3) == 0; - int plain_mov = strcmp (idesc->name, "mov") == 0; - int len = strlen(ic->name); - - resolved = ((strncmp (ic->name, idesc->name, len) == 0) - && (idesc->name[len] == '\0' - || idesc->name[len] == '.')); - - /* All break, nop, and hint variations must match exactly. */ - if (resolved && - (strcmp (ic->name, "break") == 0 - || strcmp (ic->name, "nop") == 0 - || strcmp (ic->name, "hint") == 0)) - resolved = strcmp (ic->name, idesc->name) == 0; - - /* Assume restrictions in the FORMAT/FIELD negate resolution, - unless specifically allowed by clauses in this block. */ - if (resolved && field) - { - /* Check Field(sf)==sN against opcode sN. */ - if (strstr(field, "(sf)==") != NULL) - { - char *sf; - - if ((sf = strstr (idesc->name, ".s")) != 0) - resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0; - } - /* Check Field(lftype)==XXX. */ - else if (strstr (field, "(lftype)") != NULL) - { - if (strstr (idesc->name, "fault") != NULL) - resolved = strstr (field, "fault") != NULL; - else - resolved = strstr (field, "fault") == NULL; - } - /* Handle Field(ctype)==XXX. */ - else if (strstr (field, "(ctype)") != NULL) - { - if (strstr (idesc->name, "or.andcm")) - resolved = strstr (field, "or.andcm") != NULL; - else if (strstr (idesc->name, "and.orcm")) - resolved = strstr (field, "and.orcm") != NULL; - else if (strstr (idesc->name, "orcm")) - resolved = strstr (field, "or orcm") != NULL; - else if (strstr (idesc->name, "or")) - resolved = strstr (field, "or orcm") != NULL; - else if (strstr (idesc->name, "andcm")) - resolved = strstr (field, "and andcm") != NULL; - else if (strstr (idesc->name, "and")) - resolved = strstr (field, "and andcm") != NULL; - else if (strstr (idesc->name, "unc")) - resolved = strstr (field, "unc") != NULL; - else - resolved = strcmp (field, "Field(ctype)==") == 0; - } - } - - if (resolved && format) - { - if (strncmp (idesc->name, "dep", 3) == 0 - && strstr (format, "I13") != NULL) - resolved = idesc->operands[1] == IA64_OPND_IMM8; - else if (strncmp (idesc->name, "chk", 3) == 0 - && strstr (format, "M21") != NULL) - resolved = idesc->operands[0] == IA64_OPND_F2; - else if (strncmp (idesc->name, "lfetch", 6) == 0) - resolved = (strstr (format, "M14 M15") != NULL - && (idesc->operands[1] == IA64_OPND_R2 - || idesc->operands[1] == IA64_OPND_IMM9b)); - else if (strncmp (idesc->name, "br.call", 7) == 0 - && strstr (format, "B5") != NULL) - resolved = idesc->operands[1] == IA64_OPND_B2; - else if (strncmp (idesc->name, "br.call", 7) == 0 - && strstr (format, "B3") != NULL) - resolved = idesc->operands[1] == IA64_OPND_TGT25c; - else if (strncmp (idesc->name, "brp", 3) == 0 - && strstr (format, "B7") != NULL) - resolved = idesc->operands[0] == IA64_OPND_B2; - else if (strcmp (ic->name, "invala") == 0) - resolved = strcmp (idesc->name, ic->name) == 0; - else if (strncmp (idesc->name, "st", 2) == 0 - && strstr (format, "M5") != NULL) - resolved = idesc->flags & IA64_OPCODE_POSTINC; - else - resolved = 0; - } - - /* Misc brl variations ('.cond' is optional); - plain brl matches brl.cond. */ - if (!resolved - && (strcmp (idesc->name, "brl") == 0 - || strncmp (idesc->name, "brl.", 4) == 0) - && strcmp (ic->name, "brl.cond") == 0) - { - resolved = 1; - } - - /* Misc br variations ('.cond' is optional). */ - if (!resolved - && (strcmp (idesc->name, "br") == 0 - || strncmp (idesc->name, "br.", 3) == 0) - && strcmp (ic->name, "br.cond") == 0) - { - if (format) - resolved = (strstr (format, "B4") != NULL - && idesc->operands[0] == IA64_OPND_B2) - || (strstr (format, "B1") != NULL - && idesc->operands[0] == IA64_OPND_TGT25c); - else - resolved = 1; - } - - /* probe variations. */ - if (!resolved && strncmp (idesc->name, "probe", 5) == 0) - { - resolved = strcmp (ic->name, "probe") == 0 - && !((strstr (idesc->name, "fault") != NULL) - ^ (format && strstr (format, "M40") != NULL)); - } - - /* mov variations. */ - if (!resolved && is_mov) - { - if (plain_mov) - { - /* mov alias for fmerge. */ - if (strcmp (ic->name, "fmerge") == 0) - { - resolved = idesc->operands[0] == IA64_OPND_F1 - && idesc->operands[1] == IA64_OPND_F3; - } - /* mov alias for adds (r3 or imm14). */ - else if (strcmp (ic->name, "adds") == 0) - { - resolved = (idesc->operands[0] == IA64_OPND_R1 - && (idesc->operands[1] == IA64_OPND_R3 - || (idesc->operands[1] == IA64_OPND_IMM14))); - } - /* mov alias for addl. */ - else if (strcmp (ic->name, "addl") == 0) - { - resolved = idesc->operands[0] == IA64_OPND_R1 - && idesc->operands[1] == IA64_OPND_IMM22; - } - } - - /* Some variants of mov and mov.[im]. */ - if (!resolved && strncmp (ic->name, "mov_", 4) == 0) - resolved = in_iclass_mov_x (idesc, ic, format, field); - } - - /* Keep track of this so we can flag any insn classes which aren't - mapped onto at least one real insn. */ - if (resolved) - ic->terminal_resolved = 1; - } - else for (i = 0; i < ic->nsubs; i++) - { - if (in_iclass (idesc, ics[ic->subs[i]], format, field, notep)) - { - int j; - - for (j = 0; j < ic->nxsubs; j++) - if (in_iclass (idesc, ics[ic->xsubs[j]], NULL, NULL, NULL)) - return 0; - - if (debug > 1) - printf ("%s is in IC %s\n", idesc->name, ic->name); - - resolved = 1; - break; - } - } - - /* If it's in this IC, add the IC note (if any) to the insn. */ - if (resolved) - { - if (ic->note && notep) - { - if (*notep && *notep != ic->note) - warn (_("overwriting note %d with note %d (IC:%s)\n"), - *notep, ic->note, ic->name); - - *notep = ic->note; - } - } - - return resolved; -} - - -static int -lookup_regindex (const char *name, int specifier) -{ - switch (specifier) - { - case IA64_RS_ARX: - if (strstr (name, "[RSC]")) - return 16; - if (strstr (name, "[BSP]")) - return 17; - else if (strstr (name, "[BSPSTORE]")) - return 18; - else if (strstr (name, "[RNAT]")) - return 19; - else if (strstr (name, "[FCR]")) - return 21; - else if (strstr (name, "[EFLAG]")) - return 24; - else if (strstr (name, "[CSD]")) - return 25; - else if (strstr (name, "[SSD]")) - return 26; - else if (strstr (name, "[CFLG]")) - return 27; - else if (strstr (name, "[FSR]")) - return 28; - else if (strstr (name, "[FIR]")) - return 29; - else if (strstr (name, "[FDR]")) - return 30; - else if (strstr (name, "[CCV]")) - return 32; - else if (strstr (name, "[ITC]")) - return 44; - else if (strstr (name, "[PFS]")) - return 64; - else if (strstr (name, "[LC]")) - return 65; - else if (strstr (name, "[EC]")) - return 66; - abort (); - case IA64_RS_CRX: - if (strstr (name, "[DCR]")) - return 0; - else if (strstr (name, "[ITM]")) - return 1; - else if (strstr (name, "[IVA]")) - return 2; - else if (strstr (name, "[PTA]")) - return 8; - else if (strstr (name, "[GPTA]")) - return 9; - else if (strstr (name, "[IPSR]")) - return 16; - else if (strstr (name, "[ISR]")) - return 17; - else if (strstr (name, "[IIP]")) - return 19; - else if (strstr (name, "[IFA]")) - return 20; - else if (strstr (name, "[ITIR]")) - return 21; - else if (strstr (name, "[IIPA]")) - return 22; - else if (strstr (name, "[IFS]")) - return 23; - else if (strstr (name, "[IIM]")) - return 24; - else if (strstr (name, "[IHA]")) - return 25; - else if (strstr (name, "[LID]")) - return 64; - else if (strstr (name, "[IVR]")) - return 65; - else if (strstr (name, "[TPR]")) - return 66; - else if (strstr (name, "[EOI]")) - return 67; - else if (strstr (name, "[ITV]")) - return 72; - else if (strstr (name, "[PMV]")) - return 73; - else if (strstr (name, "[CMCV]")) - return 74; - abort (); - case IA64_RS_PSR: - if (strstr (name, ".be")) - return 1; - else if (strstr (name, ".up")) - return 2; - else if (strstr (name, ".ac")) - return 3; - else if (strstr (name, ".mfl")) - return 4; - else if (strstr (name, ".mfh")) - return 5; - else if (strstr (name, ".ic")) - return 13; - else if (strstr (name, ".i")) - return 14; - else if (strstr (name, ".pk")) - return 15; - else if (strstr (name, ".dt")) - return 17; - else if (strstr (name, ".dfl")) - return 18; - else if (strstr (name, ".dfh")) - return 19; - else if (strstr (name, ".sp")) - return 20; - else if (strstr (name, ".pp")) - return 21; - else if (strstr (name, ".di")) - return 22; - else if (strstr (name, ".si")) - return 23; - else if (strstr (name, ".db")) - return 24; - else if (strstr (name, ".lp")) - return 25; - else if (strstr (name, ".tb")) - return 26; - else if (strstr (name, ".rt")) - return 27; - else if (strstr (name, ".cpl")) - return 32; - else if (strstr (name, ".rs")) - return 34; - else if (strstr (name, ".mc")) - return 35; - else if (strstr (name, ".it")) - return 36; - else if (strstr (name, ".id")) - return 37; - else if (strstr (name, ".da")) - return 38; - else if (strstr (name, ".dd")) - return 39; - else if (strstr (name, ".ss")) - return 40; - else if (strstr (name, ".ri")) - return 41; - else if (strstr (name, ".ed")) - return 43; - else if (strstr (name, ".bn")) - return 44; - else if (strstr (name, ".ia")) - return 45; - else - abort (); - default: - break; - } - return REG_NONE; -} - -static int -lookup_specifier (const char *name) -{ - if (strchr (name, '%')) - { - if (strstr (name, "AR[K%]") != NULL) - return IA64_RS_AR_K; - if (strstr (name, "AR[UNAT]") != NULL) - return IA64_RS_AR_UNAT; - if (strstr (name, "AR%, % in 8") != NULL) - return IA64_RS_AR; - if (strstr (name, "AR%, % in 48") != NULL) - return IA64_RS_ARb; - if (strstr (name, "BR%") != NULL) - return IA64_RS_BR; - if (strstr (name, "CR[IRR%]") != NULL) - return IA64_RS_CR_IRR; - if (strstr (name, "CR[LRR%]") != NULL) - return IA64_RS_CR_LRR; - if (strstr (name, "CR%") != NULL) - return IA64_RS_CR; - if (strstr (name, "FR%, % in 0") != NULL) - return IA64_RS_FR; - if (strstr (name, "FR%, % in 2") != NULL) - return IA64_RS_FRb; - if (strstr (name, "GR%") != NULL) - return IA64_RS_GR; - if (strstr (name, "PR%, % in 1 ") != NULL) - return IA64_RS_PR; - if (strstr (name, "PR%, % in 16 ") != NULL) - return IA64_RS_PRr; - - warn (_("don't know how to specify %% dependency %s\n"), - name); - } - else if (strchr (name, '#')) - { - if (strstr (name, "CPUID#") != NULL) - return IA64_RS_CPUID; - if (strstr (name, "DBR#") != NULL) - return IA64_RS_DBR; - if (strstr (name, "IBR#") != NULL) - return IA64_RS_IBR; - if (strstr (name, "MSR#") != NULL) - return IA64_RS_MSR; - if (strstr (name, "PKR#") != NULL) - return IA64_RS_PKR; - if (strstr (name, "PMC#") != NULL) - return IA64_RS_PMC; - if (strstr (name, "PMD#") != NULL) - return IA64_RS_PMD; - if (strstr (name, "RR#") != NULL) - return IA64_RS_RR; - - warn (_("Don't know how to specify # dependency %s\n"), - name); - } - else if (strncmp (name, "AR[FPSR]", 8) == 0) - return IA64_RS_AR_FPSR; - else if (strncmp (name, "AR[", 3) == 0) - return IA64_RS_ARX; - else if (strncmp (name, "CR[", 3) == 0) - return IA64_RS_CRX; - else if (strncmp (name, "PSR.", 4) == 0) - return IA64_RS_PSR; - else if (strcmp (name, "InService*") == 0) - return IA64_RS_INSERVICE; - else if (strcmp (name, "GR0") == 0) - return IA64_RS_GR0; - else if (strcmp (name, "CFM") == 0) - return IA64_RS_CFM; - else if (strcmp (name, "PR63") == 0) - return IA64_RS_PR63; - else if (strcmp (name, "RSE") == 0) - return IA64_RS_RSE; - - return IA64_RS_ANY; -} - -static void -print_dependency_table () -{ - int i, j; - - if (debug) - { - for (i=0;i < iclen;i++) - { - if (ics[i]->is_class) - { - if (!ics[i]->nsubs) - { - if (ics[i]->comment) - warn (_("IC:%s [%s] has no terminals or sub-classes\n"), - ics[i]->name, ics[i]->comment); - else - warn (_("IC:%s has no terminals or sub-classes\n"), - ics[i]->name); - } - } - else - { - if (!ics[i]->terminal_resolved && !ics[i]->orphan) - { - if (ics[i]->comment) - warn (_("no insns mapped directly to terminal IC %s [%s]"), - ics[i]->name, ics[i]->comment); - else - warn (_("no insns mapped directly to terminal IC %s\n"), - ics[i]->name); - } - } - } - - for (i = 0; i < iclen; i++) - { - if (ics[i]->orphan) - { - mark_used (ics[i], 1); - warn (_("class %s is defined but not used\n"), - ics[i]->name); - } - } - - if (debug > 1) - for (i = 0; i < rdepslen; i++) - { - static const char *mode_str[] = { "RAW", "WAW", "WAR" }; - - if (rdeps[i]->total_chks == 0) - warn (_("Warning: rsrc %s (%s) has no chks%s\n"), - rdeps[i]->name, mode_str[rdeps[i]->mode], - rdeps[i]->total_regs ? "" : " or regs"); - else if (rdeps[i]->total_regs == 0) - warn (_("rsrc %s (%s) has no regs\n"), - rdeps[i]->name, mode_str[rdeps[i]->mode]); - } - } - - /* The dependencies themselves. */ - printf ("static const struct ia64_dependency\ndependencies[] = {\n"); - for (i = 0; i < rdepslen; i++) - { - /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual - resource used. */ - int specifier = lookup_specifier (rdeps[i]->name); - int regindex = lookup_regindex (rdeps[i]->name, specifier); - - printf (" { \"%s\", %d, %d, %d, %d, ", - rdeps[i]->name, specifier, - (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex); - if (rdeps[i]->semantics == IA64_DVS_OTHER) - printf ("\"%s\", ", rdeps[i]->extra); - else - printf ("NULL, "); - printf("},\n"); - } - printf ("};\n\n"); - - /* And dependency lists. */ - for (i=0;i < dlistlen;i++) - { - int len = 2; - printf ("static const short dep%d[] = {\n ", i); - for (j=0;j < dlists[i]->len; j++) - { - len += printf ("%d, ", dlists[i]->deps[j]); - if (len > 75) - { - printf("\n "); - len = 2; - } - } - printf ("\n};\n\n"); - } - - /* And opcode dependency list. */ - printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n"); - printf ("static const struct ia64_opcode_dependency\n"); - printf ("op_dependencies[] = {\n"); - for (i = 0; i < opdeplen; i++) - { - printf (" { "); - if (opdeps[i]->chk == -1) - printf ("0, NULL, "); - else - printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk); - if (opdeps[i]->reg == -1) - printf ("0, NULL, "); - else - printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg); - printf ("},\n"); - } - printf ("};\n\n"); -} - - -/* Add STR to the string table. */ -static struct string_entry * -insert_string (char *str) -{ - int start = 0, end = strtablen; - int i, x; - - if (strtablen == strtabtotlen) - { - strtabtotlen += 20; - string_table = (struct string_entry **) - xrealloc (string_table, - sizeof (struct string_entry **) * strtabtotlen); - } - - if (strtablen == 0) - { - strtablen = 1; - string_table[0] = tmalloc (struct string_entry); - string_table[0]->s = xstrdup (str); - string_table[0]->num = 0; - return string_table[0]; - } - - if (strcmp (str, string_table[strtablen - 1]->s) > 0) - i = end; - else if (strcmp (str, string_table[0]->s) < 0) - i = 0; - else - { - while (1) - { - int c; - - i = (start + end) / 2; - c = strcmp (str, string_table[i]->s); - - if (c < 0) - end = i - 1; - else if (c == 0) - return string_table[i]; - else - start = i + 1; - - if (start > end) - break; - } - } - - for (; i > 0 && i < strtablen; i--) - if (strcmp (str, string_table[i - 1]->s) > 0) - break; - - for (; i < strtablen; i++) - if (strcmp (str, string_table[i]->s) < 0) - break; - - for (x = strtablen - 1; x >= i; x--) - { - string_table[x + 1] = string_table[x]; - string_table[x + 1]->num = x + 1; - } - - string_table[i] = tmalloc (struct string_entry); - string_table[i]->s = xstrdup (str); - string_table[i]->num = i; - strtablen++; - - return string_table[i]; -} - -static struct bittree * -make_bittree_entry (void) -{ - struct bittree *res = tmalloc (struct bittree); - - res->disent = NULL; - res->bits[0] = NULL; - res->bits[1] = NULL; - res->bits[2] = NULL; - res->skip_flag = 0; - res->bits_to_skip = 0; - return res; -} - - -static struct disent * -add_dis_table_ent (which, insn, order, completer_index) - struct disent *which; - int insn; - int order; - int completer_index; -{ - int ci = 0; - struct disent *ent; - - if (which != NULL) - { - ent = which; - - ent->nextcnt++; - while (ent->nexte != NULL) - ent = ent->nexte; - - ent = (ent->nexte = tmalloc (struct disent)); - } - else - { - ent = tmalloc (struct disent); - ent->next_ent = disinsntable; - disinsntable = ent; - which = ent; - } - ent->nextcnt = 0; - ent->nexte = NULL; - ent->insn = insn; - ent->priority = order; - - while (completer_index != 1) - { - ci = (ci << 1) | (completer_index & 1); - completer_index >>= 1; - } - ent->completer_index = ci; - return which; -} - -static void -finish_distable () -{ - struct disent *ent = disinsntable; - struct disent *prev = ent; - - ent->ournum = 32768; - while ((ent = ent->next_ent) != NULL) - { - ent->ournum = prev->ournum + prev->nextcnt + 1; - prev = ent; - } -} - -static void -insert_bit_table_ent (curr_ent, bit, opcode, mask, - opcodenum, order, completer_index) - struct bittree *curr_ent; - int bit; - ia64_insn opcode; - ia64_insn mask; - int opcodenum; - int order; - int completer_index; -{ - ia64_insn m; - int b; - struct bittree *next; - - if (bit == -1) - { - struct disent *nent = add_dis_table_ent (curr_ent->disent, - opcodenum, order, - completer_index); - curr_ent->disent = nent; - return; - } - - m = ((ia64_insn) 1) << bit; - - if (mask & m) - b = (opcode & m) ? 1 : 0; - else - b = 2; - - next = curr_ent->bits[b]; - if (next == NULL) - { - next = make_bittree_entry (); - curr_ent->bits[b] = next; - } - insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum, order, - completer_index); -} - -static void -add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index) - struct bittree *first; - ia64_insn opcode; - ia64_insn mask; - int opcodenum; - struct completer_entry *ent; - int completer_index; -{ - if (completer_index & (1 << 20)) - abort (); - - while (ent != NULL) - { - ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits; - add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries, - (completer_index << 1) | 1); - - if (ent->is_terminal) - { - insert_bit_table_ent (bittree, 40, newopcode, mask, - opcodenum, opcode_count - ent->order - 1, - (completer_index << 1) | 1); - } - completer_index <<= 1; - ent = ent->alternative; - } -} - -/* This optimization pass combines multiple "don't care" nodes. */ -static void -compact_distree (ent) - struct bittree *ent; -{ -#define IS_SKIP(ent) \ - ((ent->bits[2] !=NULL) \ - && (ent->bits[0] == NULL && ent->bits[1] == NULL && ent->skip_flag == 0)) - - int bitcnt = 0; - struct bittree *nent = ent; - int x; - - while (IS_SKIP (nent)) - { - bitcnt++; - nent = nent->bits[2]; - } - - if (bitcnt) - { - struct bittree *next = ent->bits[2]; - - ent->bits[0] = nent->bits[0]; - ent->bits[1] = nent->bits[1]; - ent->bits[2] = nent->bits[2]; - ent->disent = nent->disent; - ent->skip_flag = 1; - ent->bits_to_skip = bitcnt; - while (next != nent) - { - struct bittree *b = next; - next = next->bits[2]; - free (b); - } - free (nent); - } - - for (x = 0; x < 3; x++) - { - struct bittree *i = ent->bits[x]; - - if (i != NULL) - compact_distree (i); - } -} - -static unsigned char *insn_list; -static int insn_list_len = 0; -static int tot_insn_list_len = 0; - -/* Generate the disassembler state machine corresponding to the tree - in ENT. */ -static void -gen_dis_table (ent) - struct bittree *ent; -{ - int x; - int our_offset = insn_list_len; - int bitsused = 5; - int totbits = bitsused; - int needed_bytes; - int zero_count = 0; - int zero_dest = 0; /* Initialize this with 0 to keep gcc quiet... */ - - /* If this is a terminal entry, there's no point in skipping any - bits. */ - if (ent->skip_flag && ent->bits[0] == NULL && ent->bits[1] == NULL && - ent->bits[2] == NULL) - { - if (ent->disent == NULL) - abort (); - else - ent->skip_flag = 0; - } - - /* Calculate the amount of space needed for this entry, or at least - a conservatively large approximation. */ - if (ent->skip_flag) - totbits += 5; - - for (x = 1; x < 3; x++) - if (ent->bits[x] != NULL) - totbits += 16; - - if (ent->disent != NULL) - { - if (ent->bits[2] != NULL) - abort (); - - totbits += 16; - } - - /* Now allocate the space. */ - needed_bytes = (totbits + 7) / 8; - if ((needed_bytes + insn_list_len) > tot_insn_list_len) - { - tot_insn_list_len += 256; - insn_list = (char *) xrealloc (insn_list, tot_insn_list_len); - } - our_offset = insn_list_len; - insn_list_len += needed_bytes; - memset (insn_list + our_offset, 0, needed_bytes); - - /* Encode the skip entry by setting bit 6 set in the state op field, - and store the # of bits to skip immediately after. */ - if (ent->skip_flag) - { - bitsused += 5; - insn_list[our_offset + 0] |= 0x40 | ((ent->bits_to_skip >> 2) & 0xf); - insn_list[our_offset + 1] |= ((ent->bits_to_skip & 3) << 6); - } - -#define IS_ONLY_IFZERO(ENT) \ - ((ENT)->bits[0] != NULL && (ENT)->bits[1] == NULL && (ENT)->bits[2] == NULL \ - && (ENT)->disent == NULL && (ENT)->skip_flag == 0) - - /* Store an "if (bit is zero)" instruction by setting bit 7 in the - state op field. */ - if (ent->bits[0] != NULL) - { - struct bittree *nent = ent->bits[0]; - zero_count = 0; - - insn_list[our_offset] |= 0x80; - - /* We can encode sequences of multiple "if (bit is zero)" tests - by storing the # of zero bits to check in the lower 3 bits of - the instruction. However, this only applies if the state - solely tests for a zero bit. */ - - if (IS_ONLY_IFZERO (ent)) - { - while (IS_ONLY_IFZERO (nent) && zero_count < 7) - { - nent = nent->bits[0]; - zero_count++; - } - - insn_list[our_offset + 0] |= zero_count; - } - zero_dest = insn_list_len; - gen_dis_table (nent); - } - - /* Now store the remaining tests. We also handle a sole "termination - entry" by storing it as an "any bit" test. */ - - for (x = 1; x < 3; x++) - { - if (ent->bits[x] != NULL || (x == 2 && ent->disent != NULL)) - { - struct bittree *i = ent->bits[x]; - int idest; - int currbits = 15; - - if (i != NULL) - { - /* If the instruction being branched to only consists of - a termination entry, use the termination entry as the - place to branch to instead. */ - if (i->bits[0] == NULL && i->bits[1] == NULL - && i->bits[2] == NULL && i->disent != NULL) - { - idest = i->disent->ournum; - i = NULL; - } - else - idest = insn_list_len - our_offset; - } - else - idest = ent->disent->ournum; - - /* If the destination offset for the if (bit is 1) test is less - than 256 bytes away, we can store it as 8-bits instead of 16; - the instruction has bit 5 set for the 16-bit address, and bit - 4 for the 8-bit address. Since we've already allocated 16 - bits for the address we need to deallocate the space. - - Note that branchings within the table are relative, and - there are no branches that branch past our instruction yet - so we do not need to adjust any other offsets. */ - if (x == 1) - { - if (idest <= 256) - { - int start = our_offset + bitsused / 8 + 1; - - memmove (insn_list + start, - insn_list + start + 1, - insn_list_len - (start + 1)); - currbits = 7; - totbits -= 8; - needed_bytes--; - insn_list_len--; - insn_list[our_offset] |= 0x10; - idest--; - } - else - insn_list[our_offset] |= 0x20; - } - else - { - /* An instruction which solely consists of a termination - marker and whose disassembly name index is < 4096 - can be stored in 16 bits. The encoding is slightly - odd; the upper 4 bits of the instruction are 0x3, and - bit 3 loses its normal meaning. */ - - if (ent->bits[0] == NULL && ent->bits[1] == NULL - && ent->bits[2] == NULL && ent->skip_flag == 0 - && ent->disent != NULL - && ent->disent->ournum < (32768 + 4096)) - { - int start = our_offset + bitsused / 8 + 1; - - memmove (insn_list + start, - insn_list + start + 1, - insn_list_len - (start + 1)); - currbits = 11; - totbits -= 5; - bitsused--; - needed_bytes--; - insn_list_len--; - insn_list[our_offset] |= 0x30; - idest &= ~32768; - } - else - insn_list[our_offset] |= 0x08; - } - - if (debug) - { - int id = idest; - - if (i == NULL) - id |= 32768; - else if (! (id & 32768)) - id += our_offset; - - if (x == 1) - printf ("%d: if (1) goto %d\n", our_offset, id); - else - printf ("%d: try %d\n", our_offset, id); - } - - /* Store the address of the entry being branched to. */ - while (currbits >= 0) - { - char *byte = insn_list + our_offset + bitsused / 8; - - if (idest & (1 << currbits)) - *byte |= (1 << (7 - (bitsused % 8))); - - bitsused++; - currbits--; - } - - /* Now generate the states for the entry being branched to. */ - if (i != NULL) - gen_dis_table (i); - } - } - - if (debug) - { - if (ent->skip_flag) - printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip); - - if (ent->bits[0] != NULL) - printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1, - zero_dest); - } - - if (bitsused != totbits) - abort (); -} - -static void -print_dis_table (void) -{ - int x; - struct disent *cent = disinsntable; - - printf ("static const char dis_table[] = {\n"); - for (x = 0; x < insn_list_len; x++) - { - if ((x > 0) && ((x % 12) == 0)) - printf ("\n"); - - printf ("0x%02x, ", insn_list[x]); - } - printf ("\n};\n\n"); - - printf ("static const struct ia64_dis_names ia64_dis_names[] = {\n"); - while (cent != NULL) - { - struct disent *ent = cent; - - while (ent != NULL) - { - printf ("{ 0x%x, %d, %d, %d },\n", ent->completer_index, - ent->insn, (ent->nexte != NULL ? 1 : 0), - ent->priority); - ent = ent->nexte; - } - cent = cent->next_ent; - } - printf ("};\n\n"); -} - -static void -generate_disassembler (void) -{ - int i; - - bittree = make_bittree_entry (); - - for (i = 0; i < otlen; i++) - { - struct main_entry *ptr = ordered_table[i]; - - if (ptr->opcode->type != IA64_TYPE_DYN) - add_dis_entry (bittree, - ptr->opcode->opcode, ptr->opcode->mask, - ptr->main_index, - ptr->completers, 1); - } - - compact_distree (bittree); - finish_distable (); - gen_dis_table (bittree); - - print_dis_table (); -} - -static void -print_string_table (void) -{ - int x; - char lbuf[80], buf[80]; - int blen = 0; - - printf ("static const char * const ia64_strings[] = {\n"); - lbuf[0] = '\0'; - - for (x = 0; x < strtablen; x++) - { - int len; - - if (strlen (string_table[x]->s) > 75) - abort (); - - sprintf (buf, " \"%s\",", string_table[x]->s); - len = strlen (buf); - - if ((blen + len) > 75) - { - printf (" %s\n", lbuf); - lbuf[0] = '\0'; - blen = 0; - } - strcat (lbuf, buf); - blen += len; - } - - if (blen > 0) - printf (" %s\n", lbuf); - - printf ("};\n\n"); -} - -static struct completer_entry **glist; -static int glistlen = 0; -static int glisttotlen = 0; - -/* If the completer trees ENT1 and ENT2 are equal, return 1. */ - -static int -completer_entries_eq (ent1, ent2) - struct completer_entry *ent1, *ent2; -{ - while (ent1 != NULL && ent2 != NULL) - { - if (ent1->name->num != ent2->name->num - || ent1->bits != ent2->bits - || ent1->mask != ent2->mask - || ent1->is_terminal != ent2->is_terminal - || ent1->dependencies != ent2->dependencies - || ent1->order != ent2->order) - return 0; - - if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries)) - return 0; - - ent1 = ent1->alternative; - ent2 = ent2->alternative; - } - - return ent1 == ent2; -} - -/* Insert ENT into the global list of completers and return it. If an - equivalent entry (according to completer_entries_eq) already exists, - it is returned instead. */ -static struct completer_entry * -insert_gclist (struct completer_entry *ent) -{ - if (ent != NULL) - { - int i; - int x; - int start = 0, end; - - ent->addl_entries = insert_gclist (ent->addl_entries); - ent->alternative = insert_gclist (ent->alternative); - - i = glistlen / 2; - end = glistlen; - - if (glisttotlen == glistlen) - { - glisttotlen += 20; - glist = (struct completer_entry **) - xrealloc (glist, sizeof (struct completer_entry *) * glisttotlen); - } - - if (glistlen == 0) - { - glist[0] = ent; - glistlen = 1; - return ent; - } - - if (ent->name->num < glist[0]->name->num) - i = 0; - else if (ent->name->num > glist[end - 1]->name->num) - i = end; - else - { - int c; - - while (1) - { - i = (start + end) / 2; - c = ent->name->num - glist[i]->name->num; - - if (c < 0) - end = i - 1; - else if (c == 0) - { - while (i > 0 - && ent->name->num == glist[i - 1]->name->num) - i--; - - break; - } - else - start = i + 1; - - if (start > end) - break; - } - - if (c == 0) - { - while (i < glistlen) - { - if (ent->name->num != glist[i]->name->num) - break; - - if (completer_entries_eq (ent, glist[i])) - return glist[i]; - - i++; - } - } - } - - for (; i > 0 && i < glistlen; i--) - if (ent->name->num >= glist[i - 1]->name->num) - break; - - for (; i < glistlen; i++) - if (ent->name->num < glist[i]->name->num) - break; - - for (x = glistlen - 1; x >= i; x--) - glist[x + 1] = glist[x]; - - glist[i] = ent; - glistlen++; - } - return ent; -} - -static int -get_prefix_len (name) - const char *name; -{ - char *c; - - if (name[0] == '\0') - return 0; - - c = strchr (name, '.'); - if (c != NULL) - return c - name; - else - return strlen (name); -} - -static void -compute_completer_bits (ment, ent) - struct main_entry *ment; - struct completer_entry *ent; -{ - while (ent != NULL) - { - compute_completer_bits (ment, ent->addl_entries); - - if (ent->is_terminal) - { - ia64_insn mask = 0; - ia64_insn our_bits = ent->bits; - struct completer_entry *p = ent->parent; - ia64_insn p_bits; - int x; - - while (p != NULL && ! p->is_terminal) - p = p->parent; - - if (p != NULL) - p_bits = p->bits; - else - p_bits = ment->opcode->opcode; - - for (x = 0; x < 64; x++) - { - ia64_insn m = ((ia64_insn) 1) << x; - - if ((p_bits & m) != (our_bits & m)) - mask |= m; - else - our_bits &= ~m; - } - ent->bits = our_bits; - ent->mask = mask; - } - else - { - ent->bits = 0; - ent->mask = 0; - } - - ent = ent->alternative; - } -} - -/* Find identical completer trees that are used in different - instructions and collapse their entries. */ -static void -collapse_redundant_completers (void) -{ - struct main_entry *ptr; - int x; - - for (ptr = maintable; ptr != NULL; ptr = ptr->next) - { - if (ptr->completers == NULL) - abort (); - - compute_completer_bits (ptr, ptr->completers); - ptr->completers = insert_gclist (ptr->completers); - } - - /* The table has been finalized, now number the indexes. */ - for (x = 0; x < glistlen; x++) - glist[x]->num = x; -} - - -/* Attach two lists of dependencies to each opcode. - 1) all resources which, when already marked in use, conflict with this - opcode (chks) - 2) all resources which must be marked in use when this opcode is used - (regs). */ -static int -insert_opcode_dependencies (opc, cmp) - struct ia64_opcode *opc; - struct completer_entry *cmp ATTRIBUTE_UNUSED; -{ - /* Note all resources which point to this opcode. rfi has the most chks - (79) and cmpxchng has the most regs (54) so 100 here should be enough. */ - int i; - int nregs = 0; - unsigned short regs[256]; - int nchks = 0; - unsigned short chks[256]; - /* Flag insns for which no class matched; there should be none. */ - int no_class_found = 1; - - for (i = 0; i < rdepslen; i++) - { - struct rdep *rs = rdeps[i]; - int j; - - if (strcmp (opc->name, "cmp.eq.and") == 0 - && strncmp (rs->name, "PR%", 3) == 0 - && rs->mode == 1) - no_class_found = 99; - - for (j=0; j < rs->nregs;j++) - { - int ic_note = 0; - - if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note)) - { - /* We can ignore ic_note 11 for non PR resources. */ - if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) - ic_note = 0; - - if (ic_note != 0 && rs->regnotes[j] != 0 - && ic_note != rs->regnotes[j] - && !(ic_note == 11 && rs->regnotes[j] == 1)) - warn (_("IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"), - ic_note, opc->name, ics[rs->regs[j]]->name, - rs->name, rs->regnotes[j]); - /* Instruction class notes override resource notes. - So far, only note 11 applies to an IC instead of a resource, - and note 11 implies note 1. */ - if (ic_note) - regs[nregs++] = RDEP(ic_note, i); - else - regs[nregs++] = RDEP(rs->regnotes[j], i); - no_class_found = 0; - ++rs->total_regs; - } - } - - for (j = 0; j < rs->nchks; j++) - { - int ic_note = 0; - - if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note)) - { - /* We can ignore ic_note 11 for non PR resources. */ - if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) - ic_note = 0; - - if (ic_note != 0 && rs->chknotes[j] != 0 - && ic_note != rs->chknotes[j] - && !(ic_note == 11 && rs->chknotes[j] == 1)) - warn (_("IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"), - ic_note, opc->name, ics[rs->chks[j]]->name, - rs->name, rs->chknotes[j]); - if (ic_note) - chks[nchks++] = RDEP(ic_note, i); - else - chks[nchks++] = RDEP(rs->chknotes[j], i); - no_class_found = 0; - ++rs->total_chks; - } - } - } - - if (no_class_found) - warn (_("opcode %s has no class (ops %d %d %d)\n"), - opc->name, - opc->operands[0], opc->operands[1], opc->operands[2]); - - return insert_dependencies (nchks, chks, nregs, regs); -} - -static void -insert_completer_entry (opc, tabent, order) - struct ia64_opcode *opc; - struct main_entry *tabent; - int order; -{ - struct completer_entry **ptr = &tabent->completers; - struct completer_entry *parent = NULL; - char pcopy[129], *prefix; - int at_end = 0; - - if (strlen (opc->name) > 128) - abort (); - - strcpy (pcopy, opc->name); - prefix = pcopy + get_prefix_len (pcopy); - - if (prefix[0] != '\0') - prefix++; - - while (! at_end) - { - int need_new_ent = 1; - int plen = get_prefix_len (prefix); - struct string_entry *sent; - - at_end = (prefix[plen] == '\0'); - prefix[plen] = '\0'; - sent = insert_string (prefix); - - while (*ptr != NULL) - { - int cmpres = sent->num - (*ptr)->name->num; - - if (cmpres == 0) - { - need_new_ent = 0; - break; - } - else - ptr = &((*ptr)->alternative); - } - - if (need_new_ent) - { - struct completer_entry *nent = tmalloc (struct completer_entry); - - nent->name = sent; - nent->parent = parent; - nent->addl_entries = NULL; - nent->alternative = *ptr; - *ptr = nent; - nent->is_terminal = 0; - nent->dependencies = -1; - } - - if (! at_end) - { - parent = *ptr; - ptr = &((*ptr)->addl_entries); - prefix += plen + 1; - } - } - - if ((*ptr)->is_terminal) - abort (); - - (*ptr)->is_terminal = 1; - (*ptr)->mask = (ia64_insn)-1; - (*ptr)->bits = opc->opcode; - (*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr); - (*ptr)->order = order; -} - -static void -print_completer_entry (ent) - struct completer_entry *ent; -{ - int moffset = 0; - ia64_insn mask = ent->mask, bits = ent->bits; - - if (mask != 0) - { - while (! (mask & 1)) - { - moffset++; - mask = mask >> 1; - bits = bits >> 1; - } - - if (bits & 0xffffffff00000000LL) - abort (); - } - - printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n", - (int)bits, - (int)mask, - ent->name->num, - ent->alternative != NULL ? ent->alternative->num : -1, - ent->addl_entries != NULL ? ent->addl_entries->num : -1, - moffset, - ent->is_terminal ? 1 : 0, - ent->dependencies); -} - -static void -print_completer_table () -{ - int x; - - printf ("static const struct ia64_completer_table\ncompleter_table[] = {\n"); - for (x = 0; x < glistlen; x++) - print_completer_entry (glist[x]); - printf ("};\n\n"); -} - -static int -opcodes_eq (opc1, opc2) - struct ia64_opcode *opc1; - struct ia64_opcode *opc2; -{ - int x; - int plen1, plen2; - - if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type) - || (opc1->num_outputs != opc2->num_outputs) - || (opc1->flags != opc2->flags)) - return 0; - - for (x = 0; x < 5; x++) - if (opc1->operands[x] != opc2->operands[x]) - return 0; - - plen1 = get_prefix_len (opc1->name); - plen2 = get_prefix_len (opc2->name); - - if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0)) - return 1; - - return 0; -} - -static void -add_opcode_entry (opc) - struct ia64_opcode *opc; -{ - struct main_entry **place; - struct string_entry *name; - char prefix[129]; - int found_it = 0; - - if (strlen (opc->name) > 128) - abort (); - - place = &maintable; - strcpy (prefix, opc->name); - prefix[get_prefix_len (prefix)] = '\0'; - name = insert_string (prefix); - - /* Walk the list of opcode table entries. If it's a new - instruction, allocate and fill in a new entry. Note - the main table is alphabetical by opcode name. */ - - while (*place != NULL) - { - if ((*place)->name->num == name->num - && opcodes_eq ((*place)->opcode, opc)) - { - found_it = 1; - break; - } - if ((*place)->name->num > name->num) - break; - - place = &((*place)->next); - } - if (! found_it) - { - struct main_entry *nent = tmalloc (struct main_entry); - - nent->name = name; - nent->opcode = opc; - nent->next = *place; - nent->completers = 0; - *place = nent; - - if (otlen == ottotlen) - { - ottotlen += 20; - ordered_table = (struct main_entry **) - xrealloc (ordered_table, sizeof (struct main_entry *) * ottotlen); - } - ordered_table[otlen++] = nent; - } - - insert_completer_entry (opc, *place, opcode_count++); -} - -static void -print_main_table (void) -{ - struct main_entry *ptr = maintable; - int index = 0; - - printf ("static const struct ia64_main_table\nmain_table[] = {\n"); - while (ptr != NULL) - { - printf (" { %d, %d, %d, 0x", - ptr->name->num, - ptr->opcode->type, - ptr->opcode->num_outputs); - fprintf_vma (stdout, ptr->opcode->opcode); - printf ("ull, 0x"); - fprintf_vma (stdout, ptr->opcode->mask); - printf ("ull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n", - ptr->opcode->operands[0], - ptr->opcode->operands[1], - ptr->opcode->operands[2], - ptr->opcode->operands[3], - ptr->opcode->operands[4], - ptr->opcode->flags, - ptr->completers->num); - - ptr->main_index = index++; - - ptr = ptr->next; - } - printf ("};\n\n"); -} - -static void -shrink (table) - struct ia64_opcode *table; -{ - int curr_opcode; - - for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++) - add_opcode_entry (table + curr_opcode); -} - - -/* Program options. */ -#define OPTION_SRCDIR 200 - -struct option long_options[] = -{ - {"srcdir", required_argument, NULL, OPTION_SRCDIR}, - {"debug", no_argument, NULL, 'd'}, - {"version", no_argument, NULL, 'V'}, - {"help", no_argument, NULL, 'h'}, - {0, no_argument, NULL, 0} -}; - -static void -print_version (void) -{ - printf ("%s: version 1.0\n", program_name); - xexit (0); -} - -static void -usage (FILE * stream, int status) -{ - fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--srcdir=dirname] [--help]\n", - program_name); - xexit (status); -} - -int -main (int argc, char **argv) -{ - extern int chdir (char *); - char *srcdir = NULL; - int c; - - program_name = *argv; - xmalloc_set_program_name (program_name); - - while ((c = getopt_long (argc, argv, "vVdh", long_options, 0)) != EOF) - switch (c) - { - case OPTION_SRCDIR: - srcdir = optarg; - break; - case 'V': - case 'v': - print_version (); - break; - case 'd': - debug = 1; - break; - case 'h': - case '?': - usage (stderr, 0); - default: - case 0: - break; - } - - if (optind != argc) - usage (stdout, 1); - - if (srcdir != NULL) - if (chdir (srcdir) != 0) - fail (_("unable to change directory to \"%s\", errno = %s\n"), - srcdir, strerror (errno)); - - load_insn_classes (); - load_dependencies (); - - shrink (ia64_opcodes_a); - shrink (ia64_opcodes_b); - shrink (ia64_opcodes_f); - shrink (ia64_opcodes_i); - shrink (ia64_opcodes_m); - shrink (ia64_opcodes_x); - shrink (ia64_opcodes_d); - - collapse_redundant_completers (); - - printf ("/* This file is automatically generated by ia64-gen. Do not edit! */\n"); - print_string_table (); - print_dependency_table (); - print_completer_table (); - print_main_table (); - - generate_disassembler (); - - exit (0); -} diff --git a/contrib/binutils/opcodes/ia64-ic.tbl b/contrib/binutils/opcodes/ia64-ic.tbl deleted file mode 100644 index 45e3bd5..0000000 --- a/contrib/binutils/opcodes/ia64-ic.tbl +++ /dev/null @@ -1,250 +0,0 @@ -Class; Events/Instructions -all; IC:predicatable-instructions, IC:unpredicatable-instructions -branches; IC:indirect-brs, IC:ip-rel-brs -cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e -chk-a; chk.a.clr, chk.a.nc -cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8, cmp8xchg16 -czx; czx1, czx2 -fcmp-s0; fcmp[Field(sf)==s0] -fcmp-s1; fcmp[Field(sf)==s1] -fcmp-s2; fcmp[Field(sf)==s2] -fcmp-s3; fcmp[Field(sf)==s3] -fetchadd; fetchadd4, fetchadd8 -fp-arith; fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin, fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma, fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta, fsub -fp-arith-s0; IC:fp-arith[Field(sf)==s0] -fp-arith-s1; IC:fp-arith[Field(sf)==s1] -fp-arith-s2; IC:fp-arith[Field(sf)==s2] -fp-arith-s3; IC:fp-arith[Field(sf)==s3] -fp-non-arith; fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fnegabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fxor, xma -fpcmp-s0; fpcmp[Field(sf)==s0] -fpcmp-s1; fpcmp[Field(sf)==s1] -fpcmp-s2; fpcmp[Field(sf)==s2] -fpcmp-s3; fpcmp[Field(sf)==s3] -fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf, IC:mem-writers-fp -fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp, setf -gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat -gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt -gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-from-PSR, IC:mov-from-PSR-um, IC:mov-ip, movl -indirect-brp; brp[Format in {B7}] -indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret -invala-all; invala[Format in {M24}], invala.e -ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop -ld; ld1, ld2, ld4, ld8, ld8.fill, ld16 -ld-a; ld1.a, ld2.a, ld4.a, ld8.a -ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}] -ld-c; IC:ld-c-nc, IC:ld-c-clr -ld-c-clr; ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq -ld-c-clr-acq; ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq -ld-c-nc; ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc -ld-s; ld1.s, ld2.s, ld4.s, ld8.s -ld-sa; ld1.sa, ld2.sa, ld4.sa, ld8.sa -ldf; ldfs, ldfd, ldfe, ldf8, ldf.fill -ldf-a; ldfs.a, ldfd.a, ldfe.a, ldf8.a -ldf-c; IC:ldf-c-nc, IC:ldf-c-clr -ldf-c-clr; ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr -ldf-c-nc; ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc -ldf-s; ldfs.s, ldfd.s, ldfe.s, ldf8.s -ldf-sa; ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa -ldfp; ldfps, ldfpd, ldfp8 -ldfp-a; ldfps.a, ldfpd.a, ldfp8.a -ldfp-c; IC:ldfp-c-nc, IC:ldfp-c-clr -ldfp-c-clr; ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr -ldfp-c-nc; ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc -ldfp-s; ldfps.s, ldfpd.s, ldfp8.s -ldfp-sa; ldfps.sa, ldfpd.sa, ldfp8.sa -lfetch-all; lfetch -lfetch-fault; lfetch[Field(lftype)==fault] -lfetch-nofault; lfetch[Field(lftype)==] -lfetch-postinc; lfetch[Format in {M14 M15}] -mem-readers; IC:mem-readers-fp, IC:mem-readers-int -mem-readers-alat; IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ldfp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c -mem-readers-fp; IC:ldf, IC:ldfp -mem-readers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld -mem-readers-spec; IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ldfp-sa -mem-writers; IC:mem-writers-fp, IC:mem-writers-int -mem-writers-fp; IC:stf -mem-writers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st -mix; mix1, mix2, mix4 -mod-sched-brs; br.cexit, br.ctop, br.wexit, br.wtop -mod-sched-brs-counted; br.cexit, br.cloop, br.ctop -mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM -mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP] -mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE] -mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV] -mov-from-AR-CFLG; IC:mov-from-AR-M[Field(ar3) == CFLG] -mov-from-AR-CSD; IC:mov-from-AR-M[Field(ar3) == CSD] -mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC] -mov-from-AR-EFLAG; IC:mov-from-AR-M[Field(ar3) == EFLAG] -mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR] -mov-from-AR-FDR; IC:mov-from-AR-M[Field(ar3) == FDR] -mov-from-AR-FIR; IC:mov-from-AR-M[Field(ar3) == FIR] -mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR] -mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) == FSR] -mov-from-AR-I; mov_ar[Format in {I28}] -mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}] -mov-from-AR-IM; mov_ar[Format in {I28 M31}] -mov-from-AR-ITC; IC:mov-from-AR-M[Field(ar3) == ITC] -mov-from-AR-K; IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] -mov-from-AR-LC; IC:mov-from-AR-I[Field(ar3) == LC] -mov-from-AR-M; mov_ar[Format in {M31}] -mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS] -mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT] -mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC] -mov-from-AR-rv; IC:none -mov-from-AR-SSD; IC:mov-from-AR-M[Field(ar3) == SSD] -mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT] -mov-from-BR; mov_br[Format in {I22}] -mov-from-CR; mov_cr[Format in {M33}] -mov-from-CR-CMCV; IC:mov-from-CR[Field(cr3) == CMCV] -mov-from-CR-DCR; IC:mov-from-CR[Field(cr3) == DCR] -mov-from-CR-EOI; IC:mov-from-CR[Field(cr3) == EOI] -mov-from-CR-GPTA; IC:mov-from-CR[Field(cr3) == GPTA] -mov-from-CR-IFA; IC:mov-from-CR[Field(cr3) == IFA] -mov-from-CR-IFS; IC:mov-from-CR[Field(cr3) == IFS] -mov-from-CR-IHA; IC:mov-from-CR[Field(cr3) == IHA] -mov-from-CR-IIM; IC:mov-from-CR[Field(cr3) == IIM] -mov-from-CR-IIP; IC:mov-from-CR[Field(cr3) == IIP] -mov-from-CR-IIPA; IC:mov-from-CR[Field(cr3) == IIPA] -mov-from-CR-IPSR; IC:mov-from-CR[Field(cr3) == IPSR] -mov-from-CR-IRR; IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] -mov-from-CR-ISR; IC:mov-from-CR[Field(cr3) == ISR] -mov-from-CR-ITIR; IC:mov-from-CR[Field(cr3) == ITIR] -mov-from-CR-ITM; IC:mov-from-CR[Field(cr3) == ITM] -mov-from-CR-ITV; IC:mov-from-CR[Field(cr3) == ITV] -mov-from-CR-IVA; IC:mov-from-CR[Field(cr3) == IVA] -mov-from-CR-IVR; IC:mov-from-CR[Field(cr3) == IVR] -mov-from-CR-LID; IC:mov-from-CR[Field(cr3) == LID] -mov-from-CR-LRR; IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}] -mov-from-CR-PMV; IC:mov-from-CR[Field(cr3) == PMV] -mov-from-CR-PTA; IC:mov-from-CR[Field(cr3) == PTA] -mov-from-CR-rv; IC:none -mov-from-CR-TPR; IC:mov-from-CR[Field(cr3) == TPR] -mov-from-IND; mov_indirect[Format in {M43}] -mov-from-IND-CPUID; IC:mov-from-IND[Field(ireg) == cpuid] -mov-from-IND-DBR; IC:mov-from-IND[Field(ireg) == dbr] -mov-from-IND-IBR; IC:mov-from-IND[Field(ireg) == ibr] -mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr] -mov-from-IND-PKR; IC:mov-from-IND[Field(ireg) == pkr] -mov-from-IND-PMC; IC:mov-from-IND[Field(ireg) == pmc] -mov-from-IND-PMD; IC:mov-from-IND[Field(ireg) == pmd] -mov-from-IND-priv; IC:mov-from-IND[Field(ireg) in {dbr ibr msr pkr pmc rr}] -mov-from-IND-RR; IC:mov-from-IND[Field(ireg) == rr] -mov-from-PR; mov_pr[Format in {I25}] -mov-from-PSR; mov_psr[Format in {M36}] -mov-from-PSR-um; mov_um[Format in {M36}] -mov-ip; mov_ip[Format in {I25}] -mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I -mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP] -mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE] -mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV] -mov-to-AR-CFLG; IC:mov-to-AR-M[Field(ar3) == CFLG] -mov-to-AR-CSD; IC:mov-to-AR-M[Field(ar3) == CSD] -mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC] -mov-to-AR-EFLAG; IC:mov-to-AR-M[Field(ar3) == EFLAG] -mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR] -mov-to-AR-FDR; IC:mov-to-AR-M[Field(ar3) == FDR] -mov-to-AR-FIR; IC:mov-to-AR-M[Field(ar3) == FIR] -mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR] -mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) == FSR] -mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}] -mov-to-AR-I; mov_ar[Format in {I26 I27}] -mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}] -mov-to-AR-IM; mov_ar[Format in {I26 I27 M29 M30}] -mov-to-AR-ITC; IC:mov-to-AR-M[Field(ar3) == ITC] -mov-to-AR-K; IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] -mov-to-AR-LC; IC:mov-to-AR-I[Field(ar3) == LC] -mov-to-AR-M; mov_ar[Format in {M29 M30}] -mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS] -mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT] -mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC] -mov-to-AR-SSD; IC:mov-to-AR-M[Field(ar3) == SSD] -mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT] -mov-to-BR; mov_br[Format in {I21}] -mov-to-CR; mov_cr[Format in {M32}] -mov-to-CR-CMCV; IC:mov-to-CR[Field(cr3) == CMCV] -mov-to-CR-DCR; IC:mov-to-CR[Field(cr3) == DCR] -mov-to-CR-EOI; IC:mov-to-CR[Field(cr3) == EOI] -mov-to-CR-GPTA; IC:mov-to-CR[Field(cr3) == GPTA] -mov-to-CR-IFA; IC:mov-to-CR[Field(cr3) == IFA] -mov-to-CR-IFS; IC:mov-to-CR[Field(cr3) == IFS] -mov-to-CR-IHA; IC:mov-to-CR[Field(cr3) == IHA] -mov-to-CR-IIM; IC:mov-to-CR[Field(cr3) == IIM] -mov-to-CR-IIP; IC:mov-to-CR[Field(cr3) == IIP] -mov-to-CR-IIPA; IC:mov-to-CR[Field(cr3) == IIPA] -mov-to-CR-IPSR; IC:mov-to-CR[Field(cr3) == IPSR] -mov-to-CR-IRR; IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] -mov-to-CR-ISR; IC:mov-to-CR[Field(cr3) == ISR] -mov-to-CR-ITIR; IC:mov-to-CR[Field(cr3) == ITIR] -mov-to-CR-ITM; IC:mov-to-CR[Field(cr3) == ITM] -mov-to-CR-ITV; IC:mov-to-CR[Field(cr3) == ITV] -mov-to-CR-IVA; IC:mov-to-CR[Field(cr3) == IVA] -mov-to-CR-IVR; IC:mov-to-CR[Field(cr3) == IVR] -mov-to-CR-LID; IC:mov-to-CR[Field(cr3) == LID] -mov-to-CR-LRR; IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}] -mov-to-CR-PMV; IC:mov-to-CR[Field(cr3) == PMV] -mov-to-CR-PTA; IC:mov-to-CR[Field(cr3) == PTA] -mov-to-CR-TPR; IC:mov-to-CR[Field(cr3) == TPR] -mov-to-IND; mov_indirect[Format in {M42}] -mov-to-IND-CPUID; IC:mov-to-IND[Field(ireg) == cpuid] -mov-to-IND-DBR; IC:mov-to-IND[Field(ireg) == dbr] -mov-to-IND-IBR; IC:mov-to-IND[Field(ireg) == ibr] -mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr] -mov-to-IND-PKR; IC:mov-to-IND[Field(ireg) == pkr] -mov-to-IND-PMC; IC:mov-to-IND[Field(ireg) == pmc] -mov-to-IND-PMD; IC:mov-to-IND[Field(ireg) == pmd] -mov-to-IND-priv; IC:mov-to-IND -mov-to-IND-RR; IC:mov-to-IND[Field(ireg) == rr] -mov-to-PR; IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg -mov-to-PR-allreg; mov_pr[Format in {I23}] -mov-to-PR-rotreg; mov_pr[Format in {I24}] -mov-to-PSR-l; mov_psr[Format in {M35}] -mov-to-PSR-um; mov_um[Format in {M35}] -mux; mux1, mux2 -none; - -pack; pack2, pack4 -padd; padd1, padd2, padd4 -pavg; pavg1, pavg2 -pavgsub; pavgsub1, pavgsub2 -pcmp; pcmp1, pcmp2, pcmp4 -pmax; pmax1, pmax2 -pmin; pmin1, pmin2 -pmpy; pmpy2 -pmpyshr; pmpyshr2 -pr-and-writers; IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] -pr-gen-writers-fp; fclass, fcmp -pr-gen-writers-int; cmp, cmp4, tbit, tnat -pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==] -pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==] -pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] -pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, hint.b, nop.b, IC:ReservedBQP -pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, hint.f, hint.i, hint.m, hint.x, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt -pr-unc-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==unc]+11, fprcpa+11, fprsqrta+11, frcpa+11, frsqrta+11 -pr-unc-writers-int; IC:pr-gen-writers-int[Field(ctype)==unc]+11 -pr-writers; IC:pr-writers-int, IC:pr-writers-fp -pr-writers-fp; IC:pr-norm-writers-fp, IC:pr-unc-writers-fp -pr-writers-int; IC:pr-norm-writers-int, IC:pr-unc-writers-int, IC:pr-and-writers, IC:pr-or-writers -predicatable-instructions; IC:mov-from-PR, IC:mov-to-PR, IC:pr-readers-br, IC:pr-readers-nobr-nomovpr -priv-ops; IC:mov-to-IND-priv, bsw, itc.i, itc.d, itr.i, itr.d, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-PSR-l, IC:mov-from-PSR, IC:mov-from-IND-priv, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, rfi, rsm, ssm, tak, tpa -probe-all; IC:probe-fault, IC:probe-nofault -probe-fault; probe[Format in {M40}] -probe-nofault; probe[Format in {M38 M39}] -psad; psad1 -pshl; pshl2, pshl4 -pshladd; pshladd2 -pshr; pshr2, pshr4 -pshradd; pshradd2 -psub; psub1, psub2, psub4 -ReservedBQP; -+15 -ReservedQP; -+16 -rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-from-AR-BSP, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-BSPSTORE, IC:mov-from-AR-RNAT, IC:mov-to-AR-RNAT, rfi -rse-writers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-to-AR-BSPSTORE, rfi -st; st1, st2, st4, st8, st8.spill, st16 -st-postinc; IC:stf[Format in {M10}], IC:st[Format in {M5}] -stf; stfs, stfd, stfe, stf8, stf.spill -sxt; sxt1, sxt2, sxt4 -sys-mask-writers-partial; rsm, ssm -unpack; unpack1, unpack2, unpack4 -unpredicatable-instructions; alloc, br.cloop, br.ctop, br.cexit, br.ia, brp, bsw, clrrrb, cover, epc, flushrs, loadrs, rfi -user-mask-writers-partial; rum, sum -xchg; xchg1, xchg2, xchg4, xchg8 -zxt; zxt1, zxt2, zxt4 diff --git a/contrib/binutils/opcodes/ia64-opc-a.c b/contrib/binutils/opcodes/ia64-opc-a.c deleted file mode 100644 index c9e3162..0000000 --- a/contrib/binutils/opcodes/ia64-opc-a.c +++ /dev/null @@ -1,417 +0,0 @@ -/* ia64-opc-a.c -- IA-64 `A' opcode table. - Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include "ia64-opc.h" - -#define A IA64_TYPE_A, 1 -#define A2 IA64_TYPE_A, 2 - -/* instruction bit fields: */ -#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \ - (((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \ - (((ia64_insn) (((x) >> 13) & 0x01)) << 36)) -#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20) -#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20) -#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27) -#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29) -#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) - -/* instruction bit masks: */ -#define mC bC (-1) -#define mImm14 bImm14 (-1) -#define mR3a bR3a (-1) -#define mR3b bR3b (-1) -#define mTa bTa (-1) -#define mTb bTb (-1) -#define mVe bVe (-1) -#define mX bX (-1) -#define mX2 bX2 (-1) -#define mX2a bX2a (-1) -#define mX2b bX2b (-1) -#define mX4 bX4 (-1) -#define mZa bZa (-1) -#define mZb bZb (-1) - -#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b) -#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \ - (mOp | mX2a | mVe) -#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \ - (mOp | mX2a | mVe | mR3a) -#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \ - (mOp | mX2a | mVe | mImm14) -#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \ - (mOp | mX2a | mVe | mX4) -#define OpX2aVeX4X2b(a,b,c,d,e) \ - (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \ - (mOp | mX2a | mVe | mX4 | mX2b) -#define OpX2TbTaC(a,b,c,d,e) \ - (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \ - (mOp | mX2 | mTb | mTa | mC) -#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \ - (mOp | mX2 | mTa | mC) -#define OpX2aZaZbX4(a,b,c,d,e) \ - (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \ - (mOp | mX2a | mZa | mZb | mX4) -#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \ - (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \ - (mOp | mX2a | mZa | mZb | mX4 | mX2b) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_a[] = - { - /* A-type instruction encodings (sorted according to major opcode). */ - - {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, - {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY}, - {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY}, - {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY}, - {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY}, - {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY}, - {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY}, - {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY}, - {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY}, - {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY}, - {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}, EMPTY}, - {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}, EMPTY}, - {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}, EMPTY}, - {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}, EMPTY}, - {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}, EMPTY}, - {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}, EMPTY}, - {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}, EMPTY}, - {"mov", A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO, 0, NULL}, - {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}, EMPTY}, - {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}, EMPTY}, - {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, - {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}, EMPTY}, - {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}, EMPTY}, - {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, - {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}, EMPTY}, - {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}, EMPTY}, - {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}, EMPTY}, - {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}, EMPTY}, - {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}, EMPTY}, - {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}, EMPTY}, - {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}, EMPTY}, - {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}, EMPTY}, - {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}, EMPTY}, - {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}, EMPTY}, - {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}, EMPTY}, - {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}, EMPTY}, - {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}, EMPTY}, - {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}, EMPTY}, - {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}, EMPTY}, - {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}, EMPTY}, - {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}, EMPTY}, - {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}, EMPTY}, - {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}, EMPTY}, - {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}, EMPTY}, - {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}, EMPTY}, - {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}, EMPTY}, - {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}, EMPTY}, - {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}, EMPTY}, - {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}, EMPTY}, - {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}, EMPTY}, - {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}, EMPTY}, - {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}, EMPTY}, - - {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO, 0, NULL}, - {"addl", A, Op (9), {R1, IMM22, R3_2}, EMPTY}, - - {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, - {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, - {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, - {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, - {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, - {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, - {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, - {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, - {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, - {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, - {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, - {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, - {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, - {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, - {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, - {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, - {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY}, - {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY}, - {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY}, - {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY}, - {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY}, - {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY}, - {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY}, - {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY}, - {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, - {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, - {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, - {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, - {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, - {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, - {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, - {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, - {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, - {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, - {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, - {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, - {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, - {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, - {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, - {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, - {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}, EMPTY}, - {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}, EMPTY}, - {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}, EMPTY}, - {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}, EMPTY}, - {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}, EMPTY}, - {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}, EMPTY}, - {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}, EMPTY}, - {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}, EMPTY}, - {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}, EMPTY}, - {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}, EMPTY}, - {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}, EMPTY}, - {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}, EMPTY}, - {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, - {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, - {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, - {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, - {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, - {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, - {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, - {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, - {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, - {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, - {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, - {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, - {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, - {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef A -#undef A2 -#undef bC -#undef bImm14 -#undef bR3a -#undef bR3b -#undef bTa -#undef bTb -#undef bVe -#undef bX -#undef bX2 -#undef bX2a -#undef bX2b -#undef bX4 -#undef bZa -#undef bZb -#undef mC -#undef mImm14 -#undef mR3a -#undef mR3b -#undef mTa -#undef mTb -#undef mVe -#undef mX -#undef mX2 -#undef mX2a -#undef mX2b -#undef mX4 -#undef mZa -#undef mZb -#undef OpR3a -#undef OpR3b -#undef OpX2aVe -#undef OpX2aVeImm14 -#undef OpX2aVeX4 -#undef OpX2aVeX4X2b -#undef OpX2TbTaC -#undef OpX2TaC -#undef OpX2aZaZbX4 -#undef OpX2aZaZbX4X2b -#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-b.c b/contrib/binutils/opcodes/ia64-opc-b.c deleted file mode 100644 index fc57ab6..0000000 --- a/contrib/binutils/opcodes/ia64-opc-b.c +++ /dev/null @@ -1,509 +0,0 @@ -/* ia64-opc-b.c -- IA-64 `B' opcode table. - Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include "ia64-opc.h" - -#define B0 IA64_TYPE_B, 0 -#define B IA64_TYPE_B, 1 - -/* instruction bit fields: */ -#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) -#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) -#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35) -#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) -#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) -#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3) -#define bWhc(x) (((ia64_insn) ((x) & 0x7)) << 32) -#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) - -#define mBtype bBtype (-1) -#define mD bD (-1) -#define mIh bIh (-1) -#define mPa bPa (-1) -#define mPr bPr (-1) -#define mWha bWha (-1) -#define mWhb bWhb (-1) -#define mWhc bWhc (-1) -#define mX6 bX6 (-1) - -#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6) -#define OpPaWhaD(a,b,c,d) \ - (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) -#define OpPaWhcD(a,b,c,d) \ - (bOp (a) | bPa (b) | bWhc (c) | bD (d)), (mOp | mPa | mWhc | mD) -#define OpBtypePaWhaD(a,b,c,d,e) \ - (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ - (mOp | mBtype | mPa | mWha | mD) -#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ - (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ - (mOp | mBtype | mPa | mWha | mD | mPr) -#define OpX6BtypePaWhaD(a,b,c,d,e,f) \ - (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \ - (mOp | mX6 | mBtype | mPa | mWha | mD) -#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \ - (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \ - (mOp | mX6 | mBtype | mPa | mWha | mD | mPr) -#define OpIhWhb(a,b,c) \ - (bOp (a) | bIh (b) | bWhb (c)), \ - (mOp | mIh | mWhb) -#define OpX6IhWhb(a,b,c,d) \ - (bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \ - (mOp | mX6 | mIh | mWhb) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_b[] = - { - /* B-type instruction encodings (sorted according to major opcode) */ - -#define BR(a,b) \ - B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO, 0, NULL - {"br.few", BR (0, 0)}, - {"br", BR (0, 0)}, - {"br.few.clr", BR (0, 1)}, - {"br.clr", BR (0, 1)}, - {"br.many", BR (1, 0)}, - {"br.many.clr", BR (1, 1)}, -#undef BR - -#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, EMPTY -#define BRP(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, PSEUDO, 0, NULL -#define BRT(a,b,c,d,e,f) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, f, 0, NULL - {"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)}, - {"br.cond.sptk", BRP (0x20, 0, 0, 0, 0)}, - {"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, - {"br.cond.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, - {"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)}, - {"br.cond.spnt", BRP (0x20, 0, 0, 1, 0)}, - {"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, - {"br.cond.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, - {"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)}, - {"br.cond.dptk", BRP (0x20, 0, 0, 2, 0)}, - {"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, - {"br.cond.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, - {"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)}, - {"br.cond.dpnt", BRP (0x20, 0, 0, 3, 0)}, - {"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, - {"br.cond.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, - {"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)}, - {"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, - {"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)}, - {"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, - {"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)}, - {"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, - {"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)}, - {"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, - {"br.sptk.few", BR (0x20, 0, 0, 0, 0)}, - {"br.sptk", BRP (0x20, 0, 0, 0, 0)}, - {"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, - {"br.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, - {"br.spnt.few", BR (0x20, 0, 0, 1, 0)}, - {"br.spnt", BRP (0x20, 0, 0, 1, 0)}, - {"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, - {"br.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, - {"br.dptk.few", BR (0x20, 0, 0, 2, 0)}, - {"br.dptk", BRP (0x20, 0, 0, 2, 0)}, - {"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, - {"br.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, - {"br.dpnt.few", BR (0x20, 0, 0, 3, 0)}, - {"br.dpnt", BRP (0x20, 0, 0, 3, 0)}, - {"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, - {"br.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, - {"br.sptk.many", BR (0x20, 0, 1, 0, 0)}, - {"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, - {"br.spnt.many", BR (0x20, 0, 1, 1, 0)}, - {"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, - {"br.dptk.many", BR (0x20, 0, 1, 2, 0)}, - {"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, - {"br.dpnt.many", BR (0x20, 0, 1, 3, 0)}, - {"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, - {"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)}, - {"br.ia.sptk", BRP (0x20, 1, 0, 0, 0)}, - {"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)}, - {"br.ia.sptk.clr", BRP (0x20, 1, 0, 0, 1)}, - {"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)}, - {"br.ia.spnt", BRP (0x20, 1, 0, 1, 0)}, - {"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)}, - {"br.ia.spnt.clr", BRP (0x20, 1, 0, 1, 1)}, - {"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)}, - {"br.ia.dptk", BRP (0x20, 1, 0, 2, 0)}, - {"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)}, - {"br.ia.dptk.clr", BRP (0x20, 1, 0, 2, 1)}, - {"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)}, - {"br.ia.dpnt", BRP (0x20, 1, 0, 3, 0)}, - {"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)}, - {"br.ia.dpnt.clr", BRP (0x20, 1, 0, 3, 1)}, - {"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)}, - {"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)}, - {"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)}, - {"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)}, - {"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)}, - {"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)}, - {"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)}, - {"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)}, - {"br.ret.sptk.few", BRT (0x21, 4, 0, 0, 0, MOD_RRBS)}, - {"br.ret.sptk", BRT (0x21, 4, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.ret.sptk.few.clr", BRT (0x21, 4, 0, 0, 1, MOD_RRBS)}, - {"br.ret.sptk.clr", BRT (0x21, 4, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.ret.spnt.few", BRT (0x21, 4, 0, 1, 0, MOD_RRBS)}, - {"br.ret.spnt", BRT (0x21, 4, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.ret.spnt.few.clr", BRT (0x21, 4, 0, 1, 1, MOD_RRBS)}, - {"br.ret.spnt.clr", BRT (0x21, 4, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.ret.dptk.few", BRT (0x21, 4, 0, 2, 0, MOD_RRBS)}, - {"br.ret.dptk", BRT (0x21, 4, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.ret.dptk.few.clr", BRT (0x21, 4, 0, 2, 1, MOD_RRBS)}, - {"br.ret.dptk.clr", BRT (0x21, 4, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.ret.dpnt.few", BRT (0x21, 4, 0, 3, 0, MOD_RRBS)}, - {"br.ret.dpnt", BRT (0x21, 4, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.ret.dpnt.few.clr", BRT (0x21, 4, 0, 3, 1, MOD_RRBS)}, - {"br.ret.dpnt.clr", BRT (0x21, 4, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.ret.sptk.many", BRT (0x21, 4, 1, 0, 0, MOD_RRBS)}, - {"br.ret.sptk.many.clr", BRT (0x21, 4, 1, 0, 1, MOD_RRBS)}, - {"br.ret.spnt.many", BRT (0x21, 4, 1, 1, 0, MOD_RRBS)}, - {"br.ret.spnt.many.clr", BRT (0x21, 4, 1, 1, 1, MOD_RRBS)}, - {"br.ret.dptk.many", BRT (0x21, 4, 1, 2, 0, MOD_RRBS)}, - {"br.ret.dptk.many.clr", BRT (0x21, 4, 1, 2, 1, MOD_RRBS)}, - {"br.ret.dpnt.many", BRT (0x21, 4, 1, 3, 0, MOD_RRBS)}, - {"br.ret.dpnt.many.clr", BRT (0x21, 4, 1, 3, 1, MOD_RRBS)}, -#undef BR -#undef BRP -#undef BRT - - {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, - {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, - {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, - {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS, 0, NULL}, - {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, - {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, - {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED, 0, NULL}, - - {"break.b", B0, OpX6 (0, 0x00), {IMMU21}, EMPTY}, - - {"br.call.sptk.few", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, EMPTY}, - {"br.call.sptk", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.sptk.few.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, EMPTY}, - {"br.call.sptk.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.spnt.few", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, EMPTY}, - {"br.call.spnt", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.spnt.few.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, EMPTY}, - {"br.call.spnt.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.dptk.few", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, EMPTY}, - {"br.call.dptk", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.dptk.few.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, EMPTY}, - {"br.call.dptk.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.dpnt.few", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, EMPTY}, - {"br.call.dpnt", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.dpnt.few.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, EMPTY}, - {"br.call.dpnt.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.sptk.many", B, OpPaWhcD (1, 1, 1, 0), {B1, B2}, EMPTY}, - {"br.call.sptk.many.clr", B, OpPaWhcD (1, 1, 1, 1), {B1, B2}, EMPTY}, - {"br.call.spnt.many", B, OpPaWhcD (1, 1, 3, 0), {B1, B2}, EMPTY}, - {"br.call.spnt.many.clr", B, OpPaWhcD (1, 1, 3, 1), {B1, B2}, EMPTY}, - {"br.call.dptk.many", B, OpPaWhcD (1, 1, 5, 0), {B1, B2}, EMPTY}, - {"br.call.dptk.many.clr", B, OpPaWhcD (1, 1, 5, 1), {B1, B2}, EMPTY}, - {"br.call.dpnt.many", B, OpPaWhcD (1, 1, 7, 0), {B1, B2}, EMPTY}, - {"br.call.dpnt.many.clr", B, OpPaWhcD (1, 1, 7, 1), {B1, B2}, EMPTY}, - -#define BRP(a,b,c) \ - B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED, 0, NULL - {"brp.sptk", BRP (0x10, 0, 0)}, - {"brp.dptk", BRP (0x10, 0, 2)}, - {"brp.sptk.imp", BRP (0x10, 1, 0)}, - {"brp.dptk.imp", BRP (0x10, 1, 2)}, - {"brp.ret.sptk", BRP (0x11, 0, 0)}, - {"brp.ret.dptk", BRP (0x11, 0, 2)}, - {"brp.ret.sptk.imp", BRP (0x11, 1, 0)}, - {"brp.ret.dptk.imp", BRP (0x11, 1, 2)}, -#undef BRP - - {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}, EMPTY}, - {"hint.b", B0, OpX6 (2, 0x01), {IMMU21}, EMPTY}, - -#define BR(a,b) \ - B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO, 0, NULL - {"br.few", BR (0, 0)}, - {"br", BR (0, 0)}, - {"br.few.clr", BR (0, 1)}, - {"br.clr", BR (0, 1)}, - {"br.many", BR (1, 0)}, - {"br.many.clr", BR (1, 1)}, -#undef BR - -#define BR(a,b,c) \ - B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, EMPTY -#define BRP(a,b,c) \ - B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, PSEUDO, 0, NULL - {"br.cond.sptk.few", BR (0, 0, 0)}, - {"br.cond.sptk", BRP (0, 0, 0)}, - {"br.cond.sptk.few.clr", BR (0, 0, 1)}, - {"br.cond.sptk.clr", BRP (0, 0, 1)}, - {"br.cond.spnt.few", BR (0, 1, 0)}, - {"br.cond.spnt", BRP (0, 1, 0)}, - {"br.cond.spnt.few.clr", BR (0, 1, 1)}, - {"br.cond.spnt.clr", BRP (0, 1, 1)}, - {"br.cond.dptk.few", BR (0, 2, 0)}, - {"br.cond.dptk", BRP (0, 2, 0)}, - {"br.cond.dptk.few.clr", BR (0, 2, 1)}, - {"br.cond.dptk.clr", BRP (0, 2, 1)}, - {"br.cond.dpnt.few", BR (0, 3, 0)}, - {"br.cond.dpnt", BRP (0, 3, 0)}, - {"br.cond.dpnt.few.clr", BR (0, 3, 1)}, - {"br.cond.dpnt.clr", BRP (0, 3, 1)}, - {"br.cond.sptk.many", BR (1, 0, 0)}, - {"br.cond.sptk.many.clr", BR (1, 0, 1)}, - {"br.cond.spnt.many", BR (1, 1, 0)}, - {"br.cond.spnt.many.clr", BR (1, 1, 1)}, - {"br.cond.dptk.many", BR (1, 2, 0)}, - {"br.cond.dptk.many.clr", BR (1, 2, 1)}, - {"br.cond.dpnt.many", BR (1, 3, 0)}, - {"br.cond.dpnt.many.clr", BR (1, 3, 1)}, - {"br.sptk.few", BR (0, 0, 0)}, - {"br.sptk", BRP (0, 0, 0)}, - {"br.sptk.few.clr", BR (0, 0, 1)}, - {"br.sptk.clr", BRP (0, 0, 1)}, - {"br.spnt.few", BR (0, 1, 0)}, - {"br.spnt", BRP (0, 1, 0)}, - {"br.spnt.few.clr", BR (0, 1, 1)}, - {"br.spnt.clr", BRP (0, 1, 1)}, - {"br.dptk.few", BR (0, 2, 0)}, - {"br.dptk", BRP (0, 2, 0)}, - {"br.dptk.few.clr", BR (0, 2, 1)}, - {"br.dptk.clr", BRP (0, 2, 1)}, - {"br.dpnt.few", BR (0, 3, 0)}, - {"br.dpnt", BRP (0, 3, 0)}, - {"br.dpnt.few.clr", BR (0, 3, 1)}, - {"br.dpnt.clr", BRP (0, 3, 1)}, - {"br.sptk.many", BR (1, 0, 0)}, - {"br.sptk.many.clr", BR (1, 0, 1)}, - {"br.spnt.many", BR (1, 1, 0)}, - {"br.spnt.many.clr", BR (1, 1, 1)}, - {"br.dptk.many", BR (1, 2, 0)}, - {"br.dptk.many.clr", BR (1, 2, 1)}, - {"br.dpnt.many", BR (1, 3, 0)}, - {"br.dpnt.many.clr", BR (1, 3, 1)}, -#undef BR -#undef BRP - -#define BR(a,b,c,d, e) \ - B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | e, 0, NULL - {"br.wexit.sptk.few", BR (2, 0, 0, 0, MOD_RRBS)}, - {"br.wexit.sptk", BR (2, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1, MOD_RRBS)}, - {"br.wexit.sptk.clr", BR (2, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.wexit.spnt.few", BR (2, 0, 1, 0, MOD_RRBS)}, - {"br.wexit.spnt", BR (2, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1, MOD_RRBS)}, - {"br.wexit.spnt.clr", BR (2, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.wexit.dptk.few", BR (2, 0, 2, 0, MOD_RRBS)}, - {"br.wexit.dptk", BR (2, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1, MOD_RRBS)}, - {"br.wexit.dptk.clr", BR (2, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.wexit.dpnt.few", BR (2, 0, 3, 0, MOD_RRBS)}, - {"br.wexit.dpnt", BR (2, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1, MOD_RRBS)}, - {"br.wexit.dpnt.clr", BR (2, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.wexit.sptk.many", BR (2, 1, 0, 0, MOD_RRBS)}, - {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1, MOD_RRBS)}, - {"br.wexit.spnt.many", BR (2, 1, 1, 0, MOD_RRBS)}, - {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1, MOD_RRBS)}, - {"br.wexit.dptk.many", BR (2, 1, 2, 0, MOD_RRBS)}, - {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1, MOD_RRBS)}, - {"br.wexit.dpnt.many", BR (2, 1, 3, 0, MOD_RRBS)}, - {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1, MOD_RRBS)}, - {"br.wtop.sptk.few", BR (3, 0, 0, 0, MOD_RRBS)}, - {"br.wtop.sptk", BR (3, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1, MOD_RRBS)}, - {"br.wtop.sptk.clr", BR (3, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.wtop.spnt.few", BR (3, 0, 1, 0, MOD_RRBS)}, - {"br.wtop.spnt", BR (3, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1, MOD_RRBS)}, - {"br.wtop.spnt.clr", BR (3, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.wtop.dptk.few", BR (3, 0, 2, 0, MOD_RRBS)}, - {"br.wtop.dptk", BR (3, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1, MOD_RRBS)}, - {"br.wtop.dptk.clr", BR (3, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.wtop.dpnt.few", BR (3, 0, 3, 0, MOD_RRBS)}, - {"br.wtop.dpnt", BR (3, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1, MOD_RRBS)}, - {"br.wtop.dpnt.clr", BR (3, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.wtop.sptk.many", BR (3, 1, 0, 0, MOD_RRBS)}, - {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1, MOD_RRBS)}, - {"br.wtop.spnt.many", BR (3, 1, 1, 0, MOD_RRBS)}, - {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1, MOD_RRBS)}, - {"br.wtop.dptk.many", BR (3, 1, 2, 0, MOD_RRBS)}, - {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1, MOD_RRBS)}, - {"br.wtop.dpnt.many", BR (3, 1, 3, 0, MOD_RRBS)}, - {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1, MOD_RRBS)}, - -#undef BR -#define BR(a,b,c,d) \ - B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED, 0, NULL -#define BRT(a,b,c,d,e) \ - B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED | e, 0, NULL - {"br.cloop.sptk.few", BR (5, 0, 0, 0)}, - {"br.cloop.sptk", BRT (5, 0, 0, 0, PSEUDO)}, - {"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)}, - {"br.cloop.sptk.clr", BRT (5, 0, 0, 1, PSEUDO)}, - {"br.cloop.spnt.few", BR (5, 0, 1, 0)}, - {"br.cloop.spnt", BRT (5, 0, 1, 0, PSEUDO)}, - {"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)}, - {"br.cloop.spnt.clr", BRT (5, 0, 1, 1, PSEUDO)}, - {"br.cloop.dptk.few", BR (5, 0, 2, 0)}, - {"br.cloop.dptk", BRT (5, 0, 2, 0, PSEUDO)}, - {"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)}, - {"br.cloop.dptk.clr", BRT (5, 0, 2, 1, PSEUDO)}, - {"br.cloop.dpnt.few", BR (5, 0, 3, 0)}, - {"br.cloop.dpnt", BRT (5, 0, 3, 0, PSEUDO)}, - {"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)}, - {"br.cloop.dpnt.clr", BRT (5, 0, 3, 1, PSEUDO)}, - {"br.cloop.sptk.many", BR (5, 1, 0, 0)}, - {"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)}, - {"br.cloop.spnt.many", BR (5, 1, 1, 0)}, - {"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)}, - {"br.cloop.dptk.many", BR (5, 1, 2, 0)}, - {"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)}, - {"br.cloop.dpnt.many", BR (5, 1, 3, 0)}, - {"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)}, - {"br.cexit.sptk.few", BRT (6, 0, 0, 0, MOD_RRBS)}, - {"br.cexit.sptk", BRT (6, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.cexit.sptk.few.clr", BRT (6, 0, 0, 1, MOD_RRBS)}, - {"br.cexit.sptk.clr", BRT (6, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.cexit.spnt.few", BRT (6, 0, 1, 0, MOD_RRBS)}, - {"br.cexit.spnt", BRT (6, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.cexit.spnt.few.clr", BRT (6, 0, 1, 1, MOD_RRBS)}, - {"br.cexit.spnt.clr", BRT (6, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.cexit.dptk.few", BRT (6, 0, 2, 0, MOD_RRBS)}, - {"br.cexit.dptk", BRT (6, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.cexit.dptk.few.clr", BRT (6, 0, 2, 1, MOD_RRBS)}, - {"br.cexit.dptk.clr", BRT (6, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.cexit.dpnt.few", BRT (6, 0, 3, 0, MOD_RRBS)}, - {"br.cexit.dpnt", BRT (6, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.cexit.dpnt.few.clr", BRT (6, 0, 3, 1, MOD_RRBS)}, - {"br.cexit.dpnt.clr", BRT (6, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.cexit.sptk.many", BRT (6, 1, 0, 0, MOD_RRBS)}, - {"br.cexit.sptk.many.clr", BRT (6, 1, 0, 1, MOD_RRBS)}, - {"br.cexit.spnt.many", BRT (6, 1, 1, 0, MOD_RRBS)}, - {"br.cexit.spnt.many.clr", BRT (6, 1, 1, 1, MOD_RRBS)}, - {"br.cexit.dptk.many", BRT (6, 1, 2, 0, MOD_RRBS)}, - {"br.cexit.dptk.many.clr", BRT (6, 1, 2, 1, MOD_RRBS)}, - {"br.cexit.dpnt.many", BRT (6, 1, 3, 0, MOD_RRBS)}, - {"br.cexit.dpnt.many.clr", BRT (6, 1, 3, 1, MOD_RRBS)}, - {"br.ctop.sptk.few", BRT (7, 0, 0, 0, MOD_RRBS)}, - {"br.ctop.sptk", BRT (7, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.ctop.sptk.few.clr", BRT (7, 0, 0, 1, MOD_RRBS)}, - {"br.ctop.sptk.clr", BRT (7, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.ctop.spnt.few", BRT (7, 0, 1, 0, MOD_RRBS)}, - {"br.ctop.spnt", BRT (7, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.ctop.spnt.few.clr", BRT (7, 0, 1, 1, MOD_RRBS)}, - {"br.ctop.spnt.clr", BRT (7, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.ctop.dptk.few", BRT (7, 0, 2, 0, MOD_RRBS)}, - {"br.ctop.dptk", BRT (7, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.ctop.dptk.few.clr", BRT (7, 0, 2, 1, MOD_RRBS)}, - {"br.ctop.dptk.clr", BRT (7, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.ctop.dpnt.few", BRT (7, 0, 3, 0, MOD_RRBS)}, - {"br.ctop.dpnt", BRT (7, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.ctop.dpnt.few.clr", BRT (7, 0, 3, 1, MOD_RRBS)}, - {"br.ctop.dpnt.clr", BRT (7, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.ctop.sptk.many", BRT (7, 1, 0, 0, MOD_RRBS)}, - {"br.ctop.sptk.many.clr", BRT (7, 1, 0, 1, MOD_RRBS)}, - {"br.ctop.spnt.many", BRT (7, 1, 1, 0, MOD_RRBS)}, - {"br.ctop.spnt.many.clr", BRT (7, 1, 1, 1, MOD_RRBS)}, - {"br.ctop.dptk.many", BRT (7, 1, 2, 0, MOD_RRBS)}, - {"br.ctop.dptk.many.clr", BRT (7, 1, 2, 1, MOD_RRBS)}, - {"br.ctop.dpnt.many", BRT (7, 1, 3, 0, MOD_RRBS)}, - {"br.ctop.dpnt.many.clr", BRT (7, 1, 3, 1, MOD_RRBS)}, -#undef BR -#undef BRT - - {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, EMPTY}, - {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, - {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, EMPTY}, - {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, - {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, EMPTY}, - {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, - {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, EMPTY}, - {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, - {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, EMPTY}, - {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, - {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, EMPTY}, - {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, - {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, EMPTY}, - {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, - {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, EMPTY}, - {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, - {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}, EMPTY}, - {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}, EMPTY}, - {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}, EMPTY}, - {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}, EMPTY}, - {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}, EMPTY}, - {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}, EMPTY}, - {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}, EMPTY}, - {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}, EMPTY}, - - /* Branch predict. */ -#define BRP(a,b) \ - B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED, 0, NULL - {"brp.sptk", BRP (0, 0)}, - {"brp.loop", BRP (0, 1)}, - {"brp.dptk", BRP (0, 2)}, - {"brp.exit", BRP (0, 3)}, - {"brp.sptk.imp", BRP (1, 0)}, - {"brp.loop.imp", BRP (1, 1)}, - {"brp.dptk.imp", BRP (1, 2)}, - {"brp.exit.imp", BRP (1, 3)}, -#undef BRP - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef B0 -#undef B -#undef bBtype -#undef bD -#undef bIh -#undef bPa -#undef bPr -#undef bWha -#undef bWhb -#undef bWhc -#undef bX6 -#undef mBtype -#undef mD -#undef mIh -#undef mPa -#undef mPr -#undef mWha -#undef mWhb -#undef mWhc -#undef mX6 -#undef OpX6 -#undef OpPaWhaD -#undef OpPaWhcD -#undef OpBtypePaWhaD -#undef OpBtypePaWhaDPr -#undef OpX6BtypePaWhaD -#undef OpX6BtypePaWhaDPr -#undef OpIhWhb -#undef OpX6IhWhb -#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-d.c b/contrib/binutils/opcodes/ia64-opc-d.c deleted file mode 100644 index d916085..0000000 --- a/contrib/binutils/opcodes/ia64-opc-d.c +++ /dev/null @@ -1,34 +0,0 @@ -/* ia64-opc-d.c -- IA-64 `D' opcode table. - Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -struct ia64_opcode ia64_opcodes_d[] = - { - {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3_2}, 0, 0, NULL}, - {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}, 0, 0, NULL}, - {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, - {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}, 0, 0, NULL}, - {"hint", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, - {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}, 0, 0, NULL}, - {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}, 0, 0, NULL}, - {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}, 0, 0, NULL}, - {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; diff --git a/contrib/binutils/opcodes/ia64-opc-f.c b/contrib/binutils/opcodes/ia64-opc-f.c deleted file mode 100644 index 89dbcde..0000000 --- a/contrib/binutils/opcodes/ia64-opc-f.c +++ /dev/null @@ -1,656 +0,0 @@ -/* ia64-opc-f.c -- IA-64 `F' opcode table. - Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include "ia64-opc.h" - -#define f0 IA64_TYPE_F, 0 -#define f IA64_TYPE_F, 1 -#define f2 IA64_TYPE_F, 2 - -#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13) -#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27) -#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) -#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) - -#define mF2 bF2 (-1) -#define mF4 bF4 (-1) -#define mQ bQ (-1) -#define mRa bRa (-1) -#define mRb bRb (-1) -#define mSf bSf (-1) -#define mTa bTa (-1) -#define mXa bXa (-1) -#define mXb bXb (-1) -#define mX2 bX2 (-1) -#define mX6 bX6 (-1) -#define mY bY (-1) - -#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa) -#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf) -#define OpXaSfF2(a,b,c,d) \ - (bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2) -#define OpXaSfF4(a,b,c,d) \ - (bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4) -#define OpXaSfF2F4(a,b,c,d,e) \ - (bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \ - (mOp | mXa | mSf | mF2 | mF4) -#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2) -#define OpXaX2F2(a,b,c,d) \ - (bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2) -#define OpRaRbTaSf(a,b,c,d,e) \ - (bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \ - (mOp | mRa | mRb | mTa | mSf) -#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa) -#define OpXbQSf(a,b,c,d) \ - (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf) -#define OpXbX6(a,b,c) \ - (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6) -#define OpXbX6Y(a,b,c,d) \ - (bOp (a) | bXb (b) | bX6 (c) | bY (d)), (mOp | mXb | mX6 | mY) -#define OpXbX6F2(a,b,c,d) \ - (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2) -#define OpXbX6Sf(a,b,c,d) \ - (bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_f[] = - { - /* F-type instruction encodings (sorted according to major opcode). */ - - {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, - {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, - {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, - {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, - - {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, EMPTY}, - {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, - {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}, EMPTY}, - {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}, EMPTY}, - {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}, EMPTY}, - - {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, - {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, - {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, - {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, - {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, - {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, - {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, - {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, - {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, - {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, - {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, - {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, - {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, - {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, - {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, - {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, - - {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, - {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, - {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, - {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, - {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}, EMPTY}, - {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}, EMPTY}, - - {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}, EMPTY}, - {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}, EMPTY}, - {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}, EMPTY}, - {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}, EMPTY}, - {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}, EMPTY}, - {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}, EMPTY}, - {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}, EMPTY}, - {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}, EMPTY}, - {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}, EMPTY}, - {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}, EMPTY}, - {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}, EMPTY}, - {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}, EMPTY}, - {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}, EMPTY}, - {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}, EMPTY}, - - {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, EMPTY}, - {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}, EMPTY}, - {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}, EMPTY}, - {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}, EMPTY}, - {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, EMPTY}, - {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}, EMPTY}, - {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}, EMPTY}, - {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}, EMPTY}, - {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, EMPTY}, - {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}, EMPTY}, - {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}, EMPTY}, - {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}, EMPTY}, - {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, EMPTY}, - {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}, EMPTY}, - {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}, EMPTY}, - {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}, EMPTY}, - - {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}, EMPTY}, - - {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, EMPTY}, - {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO, 0, NULL}, - {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}, EMPTY}, - {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}, EMPTY}, - {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}, EMPTY}, - {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0), {}, EMPTY}, - {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO, 0, NULL}, - {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1), {}, EMPTY}, - {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2), {}, EMPTY}, - {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3), {}, EMPTY}, - {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, EMPTY}, - {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO, 0, NULL}, - {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}, EMPTY}, - {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}, EMPTY}, - {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}, EMPTY}, - - {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}, EMPTY}, - {"nop.f", f0, OpXbX6Y (0, 0, 0x01, 0), {IMMU21}, EMPTY}, - {"hint.f", f0, OpXbX6Y (0, 0, 0x01, 1), {IMMU21}, EMPTY}, - - {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, - {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, - {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, - {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, - - {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, EMPTY}, - {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, - {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}, EMPTY}, - {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}, EMPTY}, - {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}, EMPTY}, - - {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, - {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, - {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, - {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, - {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, - {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, - {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, - {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, - {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, - {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, - {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, - {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, - {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, - {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, - {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, - {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, - - {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}, EMPTY}, - - {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, - {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, - {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, - {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}, EMPTY}, - {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}, EMPTY}, - {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}, EMPTY}, - - {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, EMPTY}, - {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}, EMPTY}, - {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}, EMPTY}, - {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}, EMPTY}, - {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, EMPTY}, - {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}, EMPTY}, - {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}, EMPTY}, - {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}, EMPTY}, - {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, EMPTY}, - {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}, EMPTY}, - {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}, EMPTY}, - {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}, EMPTY}, - {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, EMPTY}, - {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}, EMPTY}, - {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}, EMPTY}, - {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}, EMPTY}, - - {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}, EMPTY}, - {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}, EMPTY}, - - /* pseudo-ops of the above */ - {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, - {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, - {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, - {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, - {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, - {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, - {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}, EMPTY}, - {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, - {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, - {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}, EMPTY}, - {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, - {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}, EMPTY}, - {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}, EMPTY}, - - {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}, EMPTY}, - {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL}, - {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}, EMPTY}, - {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL}, - - /* note: fnorm and fcvt.xuf have identical encodings! */ - {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}, EMPTY}, - {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}, EMPTY}, - {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}, EMPTY}, - {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}, EMPTY}, - {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}, EMPTY}, - - {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}, EMPTY}, - {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}, EMPTY}, - - {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}, EMPTY}, - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef f0 -#undef f -#undef f2 -#undef bF2 -#undef bF4 -#undef bQ -#undef bRa -#undef bRb -#undef bSf -#undef bTa -#undef bXa -#undef bXb -#undef bX2 -#undef bX6 -#undef mF2 -#undef mF4 -#undef mQ -#undef mRa -#undef mRb -#undef mSf -#undef mTa -#undef mXa -#undef mXb -#undef mX2 -#undef mX6 -#undef OpXa -#undef OpXaSf -#undef OpXaSfF2 -#undef OpXaSfF4 -#undef OpXaSfF2F4 -#undef OpXaX2 -#undef OpRaRbTaSf -#undef OpTa -#undef OpXbQSf -#undef OpXbX6 -#undef OpXbX6F2 -#undef OpXbX6Sf -#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-i.c b/contrib/binutils/opcodes/ia64-opc-i.c deleted file mode 100644 index 86440f7..0000000 --- a/contrib/binutils/opcodes/ia64-opc-i.c +++ /dev/null @@ -1,304 +0,0 @@ -/* ia64-opc-i.c -- IA-64 `I' opcode table. - Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include "ia64-opc.h" - -#define I0 IA64_TYPE_I, 0 -#define I IA64_TYPE_I, 1 -#define I2 IA64_TYPE_I, 2 - -/* instruction bit fields: */ -#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23) -#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) -#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32) -#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20) -#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22) -#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28) -#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30) -#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) -#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) -#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13) -#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26) -#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) - -/* instruction bit masks: */ -#define mC bC (-1) -#define mIh bIh (-1) -#define mTa bTa (-1) -#define mTag13 bTag13 (-1) -#define mTb bTb (-1) -#define mVc bVc (-1) -#define mVe bVe (-1) -#define mWh bWh (-1) -#define mX bX (-1) -#define mXb bXb (-1) -#define mX2 bX2 (-1) -#define mX2a bX2a (-1) -#define mX2b bX2b (-1) -#define mX2c bX2c (-1) -#define mX3 bX3 (-1) -#define mX6 bX6 (-1) -#define mYa bYa (-1) -#define mYb bYb (-1) -#define mZa bZa (-1) -#define mZb bZb (-1) - -#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \ - (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \ - (mOp | mZa | mZb | mVe | mX2a | mX2b) -#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \ - (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \ - (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c) -#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX) -#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \ - (mOp | mX2 | mX | mYa) -#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \ - (mOp | mX2 | mX | mYb) -#define OpX2TaTbYaC(a,b,c,d,e,f) \ - (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \ - (mOp | mX2 | mTa | mTb | mYa | mC) -#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) -#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ - (mOp | mX3 | mX6) -#define OpX3X6Yb(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \ - (mOp | mX3 | mX6 | mYb) -#define OpX3XbIhWh(a,b,c,d,e) \ - (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \ - (mOp | mX3 | mXb | mIh | mWh) -#define OpX3XbIhWhTag13(a,b,c,d,e,f) \ - (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \ - (mOp | mX3 | mXb | mIh | mWh | mTag13) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_i[] = - { - /* I-type instruction encodings (sorted according to major opcode). */ - - {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL}, - {"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL}, - {"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL}, - {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY}, - - {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL}, -#define MOV(a,b,c,d) \ - I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY - {"mov.sptk", MOV (7, 0, 0, 0)}, - {"mov.sptk.imp", MOV (7, 0, 1, 0)}, - {"mov", MOV (7, 0, 0, 1)}, - {"mov.imp", MOV (7, 0, 1, 1)}, - {"mov.dptk", MOV (7, 0, 0, 2)}, - {"mov.dptk.imp", MOV (7, 0, 1, 2)}, - {"mov.ret.sptk", MOV (7, 1, 0, 0)}, - {"mov.ret.sptk.imp", MOV (7, 1, 1, 0)}, - {"mov.ret", MOV (7, 1, 0, 1)}, - {"mov.ret.imp", MOV (7, 1, 1, 1)}, - {"mov.ret.dptk", MOV (7, 1, 0, 2)}, - {"mov.ret.dptk.imp", MOV (7, 1, 1, 2)}, -#undef MOV - {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY}, - {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY}, - {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY}, - {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY}, - {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY}, - {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY}, - {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY}, - {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY}, - {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY}, - {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY}, - {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY}, - {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY}, - {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY}, - {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY}, - {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY}, - {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY}, - {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY}, - {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY}, - - {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY}, - - {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY}, - - {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6}, - PSEUDO | LEN_EQ_64MCNT, 0, NULL}, - {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY}, - - {"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6}, - PSEUDO | LEN_EQ_64MCNT, 0, NULL}, - {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY}, - - {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a}, - PSEUDO | LEN_EQ_64MCNT, 0, NULL}, - {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY}, - {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY}, - {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY}, -#define TBIT(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY -#define TBITCM(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL - {"tbit.z", TBIT (0, 0, 0, 0)}, - {"tbit.nz", TBITCM (0, 0, 0, 0)}, - {"tbit.z.unc", TBIT (0, 0, 0, 1)}, - {"tbit.nz.unc", TBITCM (0, 0, 0, 1)}, - {"tbit.z.and", TBIT (0, 1, 0, 0)}, - {"tbit.nz.andcm", TBITCM (0, 1, 0, 0)}, - {"tbit.nz.and", TBIT (0, 1, 0, 1)}, - {"tbit.z.andcm", TBITCM (0, 1, 0, 1)}, - {"tbit.z.or", TBIT (1, 0, 0, 0)}, - {"tbit.nz.orcm", TBITCM (1, 0, 0, 0)}, - {"tbit.nz.or", TBIT (1, 0, 0, 1)}, - {"tbit.z.orcm", TBITCM (1, 0, 0, 1)}, - {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)}, - {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)}, - {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)}, - {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)}, -#undef TBIT -#define TNAT(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY -#define TNATCM(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL - {"tnat.z", TNAT (0, 0, 1, 0)}, - {"tnat.nz", TNATCM (0, 0, 1, 0)}, - {"tnat.z.unc", TNAT (0, 0, 1, 1)}, - {"tnat.nz.unc", TNATCM (0, 0, 1, 1)}, - {"tnat.z.and", TNAT (0, 1, 1, 0)}, - {"tnat.nz.andcm", TNATCM (0, 1, 1, 0)}, - {"tnat.nz.and", TNAT (0, 1, 1, 1)}, - {"tnat.z.andcm", TNATCM (0, 1, 1, 1)}, - {"tnat.z.or", TNAT (1, 0, 1, 0)}, - {"tnat.nz.orcm", TNATCM (1, 0, 1, 0)}, - {"tnat.nz.or", TNAT (1, 0, 1, 1)}, - {"tnat.z.orcm", TNATCM (1, 0, 1, 1)}, - {"tnat.z.or.andcm", TNAT (1, 1, 1, 0)}, - {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)}, - {"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)}, - {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)}, -#undef TNAT - - {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY}, - {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY}, - {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY}, - {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY}, - {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, - {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, - {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, - {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, - {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, - {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, - {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY}, - {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY}, - {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY}, - {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, - {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, - {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, - {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, - {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, - {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, - {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY}, - {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY}, - {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY}, - {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY}, - {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY}, - {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY}, - {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY}, - {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, - {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, - {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, - {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, - {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, - {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, - {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY}, - {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY}, - {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY}, - {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY}, - {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, - {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, - {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, - {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY}, - {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY}, - {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY}, - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef I0 -#undef I -#undef I2 -#undef L -#undef bC -#undef bIh -#undef bTa -#undef bTag13 -#undef bTb -#undef bVc -#undef bVe -#undef bWh -#undef bX -#undef bXb -#undef bX2 -#undef bX2a -#undef bX2b -#undef bX2c -#undef bX3 -#undef bX6 -#undef bY -#undef bZa -#undef bZb -#undef mC -#undef mIh -#undef mTa -#undef mTag13 -#undef mTb -#undef mVc -#undef mVe -#undef mWh -#undef mX -#undef mXb -#undef mX2 -#undef mX2a -#undef mX2b -#undef mX2c -#undef mX3 -#undef mX6 -#undef mY -#undef mZa -#undef mZb -#undef OpZaZbVeX2aX2b -#undef OpZaZbVeX2aX2bX2c -#undef OpX2X -#undef OpX2XYa -#undef OpX2XYb -#undef OpX2TaTbYaC -#undef OpX3 -#undef OpX3X6 -#undef OpX3XbIhWh -#undef OpX3XbIhWhTag13 -#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-m.c b/contrib/binutils/opcodes/ia64-opc-m.c deleted file mode 100644 index 8e9454b..0000000 --- a/contrib/binutils/opcodes/ia64-opc-m.c +++ /dev/null @@ -1,1097 +0,0 @@ -/* ia64-opc-m.c -- IA-64 `M' opcode table. - Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include "ia64-opc.h" - -#define M0 IA64_TYPE_M, 0 -#define M IA64_TYPE_M, 1 -#define M2 IA64_TYPE_M, 2 - -/* instruction bit fields: */ -#define bM(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bX(x) (((ia64_insn) ((x) & 0x1)) << 27) -#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 31) -#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) -#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27) -#define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30) -#define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27) -#define bX7(x) (((ia64_insn) ((x) & 0x1)) << 36) /* note: alias for bM() */ -#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) -#define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28) - -#define mM bM (-1) -#define mX bX (-1) -#define mX2 bX2 (-1) -#define mX3 bX3 (-1) -#define mX4 bX4 (-1) -#define mX6a bX6a (-1) -#define mX6b bX6b (-1) -#define mX7 bX7 (-1) -#define mY bY (-1) -#define mHint bHint (-1) - -#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) -#define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \ - (mOp | mX3 | mX6b) -#define OpX3X6bX7(a,b,c,d) (bOp (a) | bX3 (b) | bX6b (c) | bX7 (d)), \ - (mOp | mX3 | mX6b | mX7) -#define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \ - (mOp | mX3 | mX4) -#define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \ - (mOp | mX3 | mX4 | mX2) -#define OpX3X4X2Y(a,b,c,d,e) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d) | bY (e)), \ - (mOp | mX3 | mX4 | mX2 | mY) -#define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \ - (mOp | mX6a | mHint) -#define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \ - (mOp | mX | mX6a | mHint) -#define OpMXX6a(a,b,c,d) \ - (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a) -#define OpMXX6aHint(a,b,c,d,e) \ - (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \ - (mOp | mM | mX | mX6a | mHint) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_m[] = - { - /* M-type instruction encodings (sorted according to major opcode). */ - - {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}, EMPTY}, - {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}, EMPTY}, - {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}, EMPTY}, - {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}, EMPTY}, - - {"invala", M0, OpX3X4X2 (0, 0, 0, 1), {}, EMPTY}, - {"fwb", M0, OpX3X4X2 (0, 0, 0, 2), {}, EMPTY}, - {"mf", M0, OpX3X4X2 (0, 0, 2, 2), {}, EMPTY}, - {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2), {}, EMPTY}, - {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3), {}, EMPTY}, - {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3), {}, EMPTY}, - {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3), {}, EMPTY}, - {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {}, FIRST | NO_PRED, 0, NULL}, - {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {}, FIRST | NO_PRED, 0, NULL}, - {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}, EMPTY}, - {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}, EMPTY}, - {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}, EMPTY}, - - {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}, EMPTY}, - {"nop.m", M0, OpX3X4X2Y (0, 0, 1, 0, 0), {IMMU21}, EMPTY}, - {"hint.m", M0, OpX3X4X2Y (0, 0, 1, 0, 1), {IMMU21}, EMPTY}, - - {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}, EMPTY}, - {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}, EMPTY}, - {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV, 0, NULL}, - {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV, 0, NULL}, - - {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}, EMPTY}, - {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}, EMPTY}, - {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV, 0, NULL}, - - {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS, 0, NULL}, - - {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}, EMPTY}, - {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}, EMPTY}, - {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}, EMPTY}, - {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}, EMPTY}, - {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}, EMPTY}, - {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}, EMPTY}, - {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}, EMPTY}, - {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}, EMPTY}, - {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}, EMPTY}, - {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV, 0, NULL}, - {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV, 0, NULL}, - - {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV, 0, NULL}, - {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV, 0, NULL}, - {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV, 0, NULL}, - - {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}, EMPTY}, - {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}, EMPTY}, - - {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV, 0, NULL}, - {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV, 0, NULL}, - {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV, 0, NULL}, - {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV, 0, NULL}, - {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV, 0, NULL}, - - {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}, EMPTY}, - {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}, EMPTY}, - {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV, 0, NULL}, - {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV, 0, NULL}, - - {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}, EMPTY}, - {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}, EMPTY}, - - {"fc", M0, OpX3X6bX7 (1, 0, 0x30, 0), {R3}, EMPTY}, - {"fc.i", M0, OpX3X6bX7 (1, 0, 0x30, 1), {R3}, EMPTY}, - {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV, 0, NULL}, - - /* integer load */ - {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}, EMPTY}, - {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}, EMPTY}, - {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}, EMPTY}, - {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}, EMPTY}, - {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}, EMPTY}, - {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}, EMPTY}, - {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}, EMPTY}, - {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}, EMPTY}, - {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}, EMPTY}, - {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}, EMPTY}, - {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}, EMPTY}, - {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}, EMPTY}, - {"ld16", M2, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, AR_CSD, MR3}, EMPTY}, - {"ld16.nt1", M2, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, AR_CSD, MR3}, EMPTY}, - {"ld16.nta", M2, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, AR_CSD, MR3}, EMPTY}, - {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}, EMPTY}, - {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}, EMPTY}, - {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}, EMPTY}, - {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}, EMPTY}, - {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}, EMPTY}, - {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}, EMPTY}, - {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}, EMPTY}, - {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}, EMPTY}, - {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}, EMPTY}, - {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}, EMPTY}, - {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}, EMPTY}, - {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}, EMPTY}, - {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}, EMPTY}, - {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}, EMPTY}, - {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}, EMPTY}, - {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}, EMPTY}, - {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}, EMPTY}, - {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}, EMPTY}, - {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}, EMPTY}, - {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}, EMPTY}, - {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}, EMPTY}, - {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}, EMPTY}, - {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}, EMPTY}, - {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}, EMPTY}, - {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}, EMPTY}, - {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}, EMPTY}, - {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}, EMPTY}, - {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}, EMPTY}, - {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}, EMPTY}, - {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}, EMPTY}, - {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}, EMPTY}, - {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}, EMPTY}, - {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}, EMPTY}, - {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}, EMPTY}, - {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}, EMPTY}, - {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}, EMPTY}, - {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}, EMPTY}, - {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}, EMPTY}, - {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}, EMPTY}, - {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}, EMPTY}, - {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}, EMPTY}, - {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}, EMPTY}, - {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}, EMPTY}, - {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}, EMPTY}, - {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}, EMPTY}, - {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}, EMPTY}, - {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}, EMPTY}, - {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}, EMPTY}, - {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}, EMPTY}, - {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}, EMPTY}, - {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}, EMPTY}, - {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}, EMPTY}, - {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}, EMPTY}, - {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}, EMPTY}, - {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}, EMPTY}, - {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}, EMPTY}, - {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}, EMPTY}, - {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}, EMPTY}, - {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}, EMPTY}, - {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}, EMPTY}, - {"ld16.acq", M2, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, AR_CSD, MR3}, EMPTY}, - {"ld16.acq.nt1", M2, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, AR_CSD, MR3}, EMPTY}, - {"ld16.acq.nta", M2, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, AR_CSD, MR3}, EMPTY}, - {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}, EMPTY}, - {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}, EMPTY}, - {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}, EMPTY}, - {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}, EMPTY}, - {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}, EMPTY}, - {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}, EMPTY}, - {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}, EMPTY}, - {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}, EMPTY}, - {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}, EMPTY}, - {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}, EMPTY}, - {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}, EMPTY}, - {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}, EMPTY}, - {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}, EMPTY}, - {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}, EMPTY}, - {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}, EMPTY}, - {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}, EMPTY}, - {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}, EMPTY}, - {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}, EMPTY}, - {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}, EMPTY}, - {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}, EMPTY}, - {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}, EMPTY}, - {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}, EMPTY}, - {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}, EMPTY}, - {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}, EMPTY}, - {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}, EMPTY}, - {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}, EMPTY}, - {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}, EMPTY}, - {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}, EMPTY}, - {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}, EMPTY}, - {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}, EMPTY}, - {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}, EMPTY}, - {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}, EMPTY}, - {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}, EMPTY}, - {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}, EMPTY}, - {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}, EMPTY}, - {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}, EMPTY}, - {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}, EMPTY}, - {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}, EMPTY}, - {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}, EMPTY}, - - /* Pseudo-op that generates ldxmov relocation. */ - {"ld8.mov", M, OpMXX6aHint (4, 0, 0, 0x03, 0), - {R1, MR3, IA64_OPND_LDXMOV}, EMPTY}, - - /* Integer load w/increment by register. */ -#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, 0, NULL - {"ld1", LDINCREG (0x00, 0)}, - {"ld1.nt1", LDINCREG (0x00, 1)}, - {"ld1.nta", LDINCREG (0x00, 3)}, - {"ld2", LDINCREG (0x01, 0)}, - {"ld2.nt1", LDINCREG (0x01, 1)}, - {"ld2.nta", LDINCREG (0x01, 3)}, - {"ld4", LDINCREG (0x02, 0)}, - {"ld4.nt1", LDINCREG (0x02, 1)}, - {"ld4.nta", LDINCREG (0x02, 3)}, - {"ld8", LDINCREG (0x03, 0)}, - {"ld8.nt1", LDINCREG (0x03, 1)}, - {"ld8.nta", LDINCREG (0x03, 3)}, - {"ld1.s", LDINCREG (0x04, 0)}, - {"ld1.s.nt1", LDINCREG (0x04, 1)}, - {"ld1.s.nta", LDINCREG (0x04, 3)}, - {"ld2.s", LDINCREG (0x05, 0)}, - {"ld2.s.nt1", LDINCREG (0x05, 1)}, - {"ld2.s.nta", LDINCREG (0x05, 3)}, - {"ld4.s", LDINCREG (0x06, 0)}, - {"ld4.s.nt1", LDINCREG (0x06, 1)}, - {"ld4.s.nta", LDINCREG (0x06, 3)}, - {"ld8.s", LDINCREG (0x07, 0)}, - {"ld8.s.nt1", LDINCREG (0x07, 1)}, - {"ld8.s.nta", LDINCREG (0x07, 3)}, - {"ld1.a", LDINCREG (0x08, 0)}, - {"ld1.a.nt1", LDINCREG (0x08, 1)}, - {"ld1.a.nta", LDINCREG (0x08, 3)}, - {"ld2.a", LDINCREG (0x09, 0)}, - {"ld2.a.nt1", LDINCREG (0x09, 1)}, - {"ld2.a.nta", LDINCREG (0x09, 3)}, - {"ld4.a", LDINCREG (0x0a, 0)}, - {"ld4.a.nt1", LDINCREG (0x0a, 1)}, - {"ld4.a.nta", LDINCREG (0x0a, 3)}, - {"ld8.a", LDINCREG (0x0b, 0)}, - {"ld8.a.nt1", LDINCREG (0x0b, 1)}, - {"ld8.a.nta", LDINCREG (0x0b, 3)}, - {"ld1.sa", LDINCREG (0x0c, 0)}, - {"ld1.sa.nt1", LDINCREG (0x0c, 1)}, - {"ld1.sa.nta", LDINCREG (0x0c, 3)}, - {"ld2.sa", LDINCREG (0x0d, 0)}, - {"ld2.sa.nt1", LDINCREG (0x0d, 1)}, - {"ld2.sa.nta", LDINCREG (0x0d, 3)}, - {"ld4.sa", LDINCREG (0x0e, 0)}, - {"ld4.sa.nt1", LDINCREG (0x0e, 1)}, - {"ld4.sa.nta", LDINCREG (0x0e, 3)}, - {"ld8.sa", LDINCREG (0x0f, 0)}, - {"ld8.sa.nt1", LDINCREG (0x0f, 1)}, - {"ld8.sa.nta", LDINCREG (0x0f, 3)}, - {"ld1.bias", LDINCREG (0x10, 0)}, - {"ld1.bias.nt1", LDINCREG (0x10, 1)}, - {"ld1.bias.nta", LDINCREG (0x10, 3)}, - {"ld2.bias", LDINCREG (0x11, 0)}, - {"ld2.bias.nt1", LDINCREG (0x11, 1)}, - {"ld2.bias.nta", LDINCREG (0x11, 3)}, - {"ld4.bias", LDINCREG (0x12, 0)}, - {"ld4.bias.nt1", LDINCREG (0x12, 1)}, - {"ld4.bias.nta", LDINCREG (0x12, 3)}, - {"ld8.bias", LDINCREG (0x13, 0)}, - {"ld8.bias.nt1", LDINCREG (0x13, 1)}, - {"ld8.bias.nta", LDINCREG (0x13, 3)}, - {"ld1.acq", LDINCREG (0x14, 0)}, - {"ld1.acq.nt1", LDINCREG (0x14, 1)}, - {"ld1.acq.nta", LDINCREG (0x14, 3)}, - {"ld2.acq", LDINCREG (0x15, 0)}, - {"ld2.acq.nt1", LDINCREG (0x15, 1)}, - {"ld2.acq.nta", LDINCREG (0x15, 3)}, - {"ld4.acq", LDINCREG (0x16, 0)}, - {"ld4.acq.nt1", LDINCREG (0x16, 1)}, - {"ld4.acq.nta", LDINCREG (0x16, 3)}, - {"ld8.acq", LDINCREG (0x17, 0)}, - {"ld8.acq.nt1", LDINCREG (0x17, 1)}, - {"ld8.acq.nta", LDINCREG (0x17, 3)}, - {"ld8.fill", LDINCREG (0x1b, 0)}, - {"ld8.fill.nt1", LDINCREG (0x1b, 1)}, - {"ld8.fill.nta", LDINCREG (0x1b, 3)}, - {"ld1.c.clr", LDINCREG (0x20, 0)}, - {"ld1.c.clr.nt1", LDINCREG (0x20, 1)}, - {"ld1.c.clr.nta", LDINCREG (0x20, 3)}, - {"ld2.c.clr", LDINCREG (0x21, 0)}, - {"ld2.c.clr.nt1", LDINCREG (0x21, 1)}, - {"ld2.c.clr.nta", LDINCREG (0x21, 3)}, - {"ld4.c.clr", LDINCREG (0x22, 0)}, - {"ld4.c.clr.nt1", LDINCREG (0x22, 1)}, - {"ld4.c.clr.nta", LDINCREG (0x22, 3)}, - {"ld8.c.clr", LDINCREG (0x23, 0)}, - {"ld8.c.clr.nt1", LDINCREG (0x23, 1)}, - {"ld8.c.clr.nta", LDINCREG (0x23, 3)}, - {"ld1.c.nc", LDINCREG (0x24, 0)}, - {"ld1.c.nc.nt1", LDINCREG (0x24, 1)}, - {"ld1.c.nc.nta", LDINCREG (0x24, 3)}, - {"ld2.c.nc", LDINCREG (0x25, 0)}, - {"ld2.c.nc.nt1", LDINCREG (0x25, 1)}, - {"ld2.c.nc.nta", LDINCREG (0x25, 3)}, - {"ld4.c.nc", LDINCREG (0x26, 0)}, - {"ld4.c.nc.nt1", LDINCREG (0x26, 1)}, - {"ld4.c.nc.nta", LDINCREG (0x26, 3)}, - {"ld8.c.nc", LDINCREG (0x27, 0)}, - {"ld8.c.nc.nt1", LDINCREG (0x27, 1)}, - {"ld8.c.nc.nta", LDINCREG (0x27, 3)}, - {"ld1.c.clr.acq", LDINCREG (0x28, 0)}, - {"ld1.c.clr.acq.nt1", LDINCREG (0x28, 1)}, - {"ld1.c.clr.acq.nta", LDINCREG (0x28, 3)}, - {"ld2.c.clr.acq", LDINCREG (0x29, 0)}, - {"ld2.c.clr.acq.nt1", LDINCREG (0x29, 1)}, - {"ld2.c.clr.acq.nta", LDINCREG (0x29, 3)}, - {"ld4.c.clr.acq", LDINCREG (0x2a, 0)}, - {"ld4.c.clr.acq.nt1", LDINCREG (0x2a, 1)}, - {"ld4.c.clr.acq.nta", LDINCREG (0x2a, 3)}, - {"ld8.c.clr.acq", LDINCREG (0x2b, 0)}, - {"ld8.c.clr.acq.nt1", LDINCREG (0x2b, 1)}, - {"ld8.c.clr.acq.nta", LDINCREG (0x2b, 3)}, -#undef LDINCREG - - {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}, EMPTY}, - {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}, EMPTY}, - {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}, EMPTY}, - {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}, EMPTY}, - {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}, EMPTY}, - {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}, EMPTY}, - {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}, EMPTY}, - {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}, EMPTY}, - {"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2, AR_CSD}, EMPTY}, - {"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2, AR_CSD}, EMPTY}, - {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}, EMPTY}, - {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}, EMPTY}, - {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}, EMPTY}, - {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}, EMPTY}, - {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}, EMPTY}, - {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}, EMPTY}, - {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}, EMPTY}, - {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}, EMPTY}, - {"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2, AR_CSD}, EMPTY}, - {"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2, AR_CSD}, EMPTY}, - {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}, EMPTY}, - {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}, EMPTY}, - -#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}, EMPTY -#define CMPXCHG16(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CSD, AR_CCV}, EMPTY - {"cmpxchg1.acq", CMPXCHG (0x00, 0)}, - {"cmpxchg1.acq.nt1", CMPXCHG (0x00, 1)}, - {"cmpxchg1.acq.nta", CMPXCHG (0x00, 3)}, - {"cmpxchg2.acq", CMPXCHG (0x01, 0)}, - {"cmpxchg2.acq.nt1", CMPXCHG (0x01, 1)}, - {"cmpxchg2.acq.nta", CMPXCHG (0x01, 3)}, - {"cmpxchg4.acq", CMPXCHG (0x02, 0)}, - {"cmpxchg4.acq.nt1", CMPXCHG (0x02, 1)}, - {"cmpxchg4.acq.nta", CMPXCHG (0x02, 3)}, - {"cmpxchg8.acq", CMPXCHG (0x03, 0)}, - {"cmpxchg8.acq.nt1", CMPXCHG (0x03, 1)}, - {"cmpxchg8.acq.nta", CMPXCHG (0x03, 3)}, - {"cmp8xchg16.acq", CMPXCHG16 (0x20, 0)}, - {"cmp8xchg16.acq.nt1", CMPXCHG16 (0x20, 1)}, - {"cmp8xchg16.acq.nta", CMPXCHG16 (0x20, 3)}, - {"cmpxchg1.rel", CMPXCHG (0x04, 0)}, - {"cmpxchg1.rel.nt1", CMPXCHG (0x04, 1)}, - {"cmpxchg1.rel.nta", CMPXCHG (0x04, 3)}, - {"cmpxchg2.rel", CMPXCHG (0x05, 0)}, - {"cmpxchg2.rel.nt1", CMPXCHG (0x05, 1)}, - {"cmpxchg2.rel.nta", CMPXCHG (0x05, 3)}, - {"cmpxchg4.rel", CMPXCHG (0x06, 0)}, - {"cmpxchg4.rel.nt1", CMPXCHG (0x06, 1)}, - {"cmpxchg4.rel.nta", CMPXCHG (0x06, 3)}, - {"cmpxchg8.rel", CMPXCHG (0x07, 0)}, - {"cmpxchg8.rel.nt1", CMPXCHG (0x07, 1)}, - {"cmpxchg8.rel.nta", CMPXCHG (0x07, 3)}, - {"cmp8xchg16.rel", CMPXCHG16 (0x24, 0)}, - {"cmp8xchg16.rel.nt1", CMPXCHG16 (0x24, 1)}, - {"cmp8xchg16.rel.nta", CMPXCHG16 (0x24, 3)}, -#undef CMPXCHG -#undef CMPXCHG16 - {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}, EMPTY}, - {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}, EMPTY}, - {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}, EMPTY}, - {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}, EMPTY}, - {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}, EMPTY}, - {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}, EMPTY}, - {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}, EMPTY}, - {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}, EMPTY}, - {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}, EMPTY}, - {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}, EMPTY}, - {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}, EMPTY}, - {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}, EMPTY}, - - {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}, EMPTY}, - {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}, EMPTY}, - {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}, EMPTY}, - {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}, EMPTY}, - {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}, EMPTY}, - {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}, EMPTY}, - {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}, EMPTY}, - {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}, EMPTY}, - {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}, EMPTY}, - {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}, EMPTY}, - {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}, EMPTY}, - {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}, EMPTY}, - - {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}, EMPTY}, - {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}, EMPTY}, - {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}, EMPTY}, - {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}, EMPTY}, - - /* Integer load w/increment by immediate. */ -#define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC, 0, NULL - {"ld1", LDINCIMMED (0x00, 0)}, - {"ld1.nt1", LDINCIMMED (0x00, 1)}, - {"ld1.nta", LDINCIMMED (0x00, 3)}, - {"ld2", LDINCIMMED (0x01, 0)}, - {"ld2.nt1", LDINCIMMED (0x01, 1)}, - {"ld2.nta", LDINCIMMED (0x01, 3)}, - {"ld4", LDINCIMMED (0x02, 0)}, - {"ld4.nt1", LDINCIMMED (0x02, 1)}, - {"ld4.nta", LDINCIMMED (0x02, 3)}, - {"ld8", LDINCIMMED (0x03, 0)}, - {"ld8.nt1", LDINCIMMED (0x03, 1)}, - {"ld8.nta", LDINCIMMED (0x03, 3)}, - {"ld1.s", LDINCIMMED (0x04, 0)}, - {"ld1.s.nt1", LDINCIMMED (0x04, 1)}, - {"ld1.s.nta", LDINCIMMED (0x04, 3)}, - {"ld2.s", LDINCIMMED (0x05, 0)}, - {"ld2.s.nt1", LDINCIMMED (0x05, 1)}, - {"ld2.s.nta", LDINCIMMED (0x05, 3)}, - {"ld4.s", LDINCIMMED (0x06, 0)}, - {"ld4.s.nt1", LDINCIMMED (0x06, 1)}, - {"ld4.s.nta", LDINCIMMED (0x06, 3)}, - {"ld8.s", LDINCIMMED (0x07, 0)}, - {"ld8.s.nt1", LDINCIMMED (0x07, 1)}, - {"ld8.s.nta", LDINCIMMED (0x07, 3)}, - {"ld1.a", LDINCIMMED (0x08, 0)}, - {"ld1.a.nt1", LDINCIMMED (0x08, 1)}, - {"ld1.a.nta", LDINCIMMED (0x08, 3)}, - {"ld2.a", LDINCIMMED (0x09, 0)}, - {"ld2.a.nt1", LDINCIMMED (0x09, 1)}, - {"ld2.a.nta", LDINCIMMED (0x09, 3)}, - {"ld4.a", LDINCIMMED (0x0a, 0)}, - {"ld4.a.nt1", LDINCIMMED (0x0a, 1)}, - {"ld4.a.nta", LDINCIMMED (0x0a, 3)}, - {"ld8.a", LDINCIMMED (0x0b, 0)}, - {"ld8.a.nt1", LDINCIMMED (0x0b, 1)}, - {"ld8.a.nta", LDINCIMMED (0x0b, 3)}, - {"ld1.sa", LDINCIMMED (0x0c, 0)}, - {"ld1.sa.nt1", LDINCIMMED (0x0c, 1)}, - {"ld1.sa.nta", LDINCIMMED (0x0c, 3)}, - {"ld2.sa", LDINCIMMED (0x0d, 0)}, - {"ld2.sa.nt1", LDINCIMMED (0x0d, 1)}, - {"ld2.sa.nta", LDINCIMMED (0x0d, 3)}, - {"ld4.sa", LDINCIMMED (0x0e, 0)}, - {"ld4.sa.nt1", LDINCIMMED (0x0e, 1)}, - {"ld4.sa.nta", LDINCIMMED (0x0e, 3)}, - {"ld8.sa", LDINCIMMED (0x0f, 0)}, - {"ld8.sa.nt1", LDINCIMMED (0x0f, 1)}, - {"ld8.sa.nta", LDINCIMMED (0x0f, 3)}, - {"ld1.bias", LDINCIMMED (0x10, 0)}, - {"ld1.bias.nt1", LDINCIMMED (0x10, 1)}, - {"ld1.bias.nta", LDINCIMMED (0x10, 3)}, - {"ld2.bias", LDINCIMMED (0x11, 0)}, - {"ld2.bias.nt1", LDINCIMMED (0x11, 1)}, - {"ld2.bias.nta", LDINCIMMED (0x11, 3)}, - {"ld4.bias", LDINCIMMED (0x12, 0)}, - {"ld4.bias.nt1", LDINCIMMED (0x12, 1)}, - {"ld4.bias.nta", LDINCIMMED (0x12, 3)}, - {"ld8.bias", LDINCIMMED (0x13, 0)}, - {"ld8.bias.nt1", LDINCIMMED (0x13, 1)}, - {"ld8.bias.nta", LDINCIMMED (0x13, 3)}, - {"ld1.acq", LDINCIMMED (0x14, 0)}, - {"ld1.acq.nt1", LDINCIMMED (0x14, 1)}, - {"ld1.acq.nta", LDINCIMMED (0x14, 3)}, - {"ld2.acq", LDINCIMMED (0x15, 0)}, - {"ld2.acq.nt1", LDINCIMMED (0x15, 1)}, - {"ld2.acq.nta", LDINCIMMED (0x15, 3)}, - {"ld4.acq", LDINCIMMED (0x16, 0)}, - {"ld4.acq.nt1", LDINCIMMED (0x16, 1)}, - {"ld4.acq.nta", LDINCIMMED (0x16, 3)}, - {"ld8.acq", LDINCIMMED (0x17, 0)}, - {"ld8.acq.nt1", LDINCIMMED (0x17, 1)}, - {"ld8.acq.nta", LDINCIMMED (0x17, 3)}, - {"ld8.fill", LDINCIMMED (0x1b, 0)}, - {"ld8.fill.nt1", LDINCIMMED (0x1b, 1)}, - {"ld8.fill.nta", LDINCIMMED (0x1b, 3)}, - {"ld1.c.clr", LDINCIMMED (0x20, 0)}, - {"ld1.c.clr.nt1", LDINCIMMED (0x20, 1)}, - {"ld1.c.clr.nta", LDINCIMMED (0x20, 3)}, - {"ld2.c.clr", LDINCIMMED (0x21, 0)}, - {"ld2.c.clr.nt1", LDINCIMMED (0x21, 1)}, - {"ld2.c.clr.nta", LDINCIMMED (0x21, 3)}, - {"ld4.c.clr", LDINCIMMED (0x22, 0)}, - {"ld4.c.clr.nt1", LDINCIMMED (0x22, 1)}, - {"ld4.c.clr.nta", LDINCIMMED (0x22, 3)}, - {"ld8.c.clr", LDINCIMMED (0x23, 0)}, - {"ld8.c.clr.nt1", LDINCIMMED (0x23, 1)}, - {"ld8.c.clr.nta", LDINCIMMED (0x23, 3)}, - {"ld1.c.nc", LDINCIMMED (0x24, 0)}, - {"ld1.c.nc.nt1", LDINCIMMED (0x24, 1)}, - {"ld1.c.nc.nta", LDINCIMMED (0x24, 3)}, - {"ld2.c.nc", LDINCIMMED (0x25, 0)}, - {"ld2.c.nc.nt1", LDINCIMMED (0x25, 1)}, - {"ld2.c.nc.nta", LDINCIMMED (0x25, 3)}, - {"ld4.c.nc", LDINCIMMED (0x26, 0)}, - {"ld4.c.nc.nt1", LDINCIMMED (0x26, 1)}, - {"ld4.c.nc.nta", LDINCIMMED (0x26, 3)}, - {"ld8.c.nc", LDINCIMMED (0x27, 0)}, - {"ld8.c.nc.nt1", LDINCIMMED (0x27, 1)}, - {"ld8.c.nc.nta", LDINCIMMED (0x27, 3)}, - {"ld1.c.clr.acq", LDINCIMMED (0x28, 0)}, - {"ld1.c.clr.acq.nt1", LDINCIMMED (0x28, 1)}, - {"ld1.c.clr.acq.nta", LDINCIMMED (0x28, 3)}, - {"ld2.c.clr.acq", LDINCIMMED (0x29, 0)}, - {"ld2.c.clr.acq.nt1", LDINCIMMED (0x29, 1)}, - {"ld2.c.clr.acq.nta", LDINCIMMED (0x29, 3)}, - {"ld4.c.clr.acq", LDINCIMMED (0x2a, 0)}, - {"ld4.c.clr.acq.nt1", LDINCIMMED (0x2a, 1)}, - {"ld4.c.clr.acq.nta", LDINCIMMED (0x2a, 3)}, - {"ld8.c.clr.acq", LDINCIMMED (0x2b, 0)}, - {"ld8.c.clr.acq.nt1", LDINCIMMED (0x2b, 1)}, - {"ld8.c.clr.acq.nta", LDINCIMMED (0x2b, 3)}, -#undef LDINCIMMED - - /* Store w/increment by immediate. */ -#define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC, 0, NULL - {"st1", STINCIMMED (0x30, 0)}, - {"st1.nta", STINCIMMED (0x30, 3)}, - {"st2", STINCIMMED (0x31, 0)}, - {"st2.nta", STINCIMMED (0x31, 3)}, - {"st4", STINCIMMED (0x32, 0)}, - {"st4.nta", STINCIMMED (0x32, 3)}, - {"st8", STINCIMMED (0x33, 0)}, - {"st8.nta", STINCIMMED (0x33, 3)}, - {"st1.rel", STINCIMMED (0x34, 0)}, - {"st1.rel.nta", STINCIMMED (0x34, 3)}, - {"st2.rel", STINCIMMED (0x35, 0)}, - {"st2.rel.nta", STINCIMMED (0x35, 3)}, - {"st4.rel", STINCIMMED (0x36, 0)}, - {"st4.rel.nta", STINCIMMED (0x36, 3)}, - {"st8.rel", STINCIMMED (0x37, 0)}, - {"st8.rel.nta", STINCIMMED (0x37, 3)}, - {"st8.spill", STINCIMMED (0x3b, 0)}, - {"st8.spill.nta", STINCIMMED (0x3b, 3)}, -#undef STINCIMMED - - /* Floating-point load. */ - {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}, EMPTY}, - {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}, EMPTY}, - {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}, EMPTY}, - {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}, EMPTY}, - {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}, EMPTY}, - {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}, EMPTY}, - {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}, EMPTY}, - {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}, EMPTY}, - {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}, EMPTY}, - {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}, EMPTY}, - {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}, EMPTY}, - {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}, EMPTY}, - {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}, EMPTY}, - {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}, EMPTY}, - {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}, EMPTY}, - {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}, EMPTY}, - {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}, EMPTY}, - {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}, EMPTY}, - {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}, EMPTY}, - {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}, EMPTY}, - {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}, EMPTY}, - {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}, EMPTY}, - {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}, EMPTY}, - {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}, EMPTY}, - {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}, EMPTY}, - {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}, EMPTY}, - {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}, EMPTY}, - {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}, EMPTY}, - {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}, EMPTY}, - {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}, EMPTY}, - {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}, EMPTY}, - {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}, EMPTY}, - {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}, EMPTY}, - {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}, EMPTY}, - {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}, EMPTY}, - {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}, EMPTY}, - {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}, EMPTY}, - {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}, EMPTY}, - {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}, EMPTY}, - {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}, EMPTY}, - {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}, EMPTY}, - {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}, EMPTY}, - {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}, EMPTY}, - {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}, EMPTY}, - {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}, EMPTY}, - {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}, EMPTY}, - {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}, EMPTY}, - {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}, EMPTY}, - {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}, EMPTY}, - {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}, EMPTY}, - {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}, EMPTY}, - {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}, EMPTY}, - {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}, EMPTY}, - {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}, EMPTY}, - {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}, EMPTY}, - {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}, EMPTY}, - {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}, EMPTY}, - {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}, EMPTY}, - {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}, EMPTY}, - {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}, EMPTY}, - {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}, EMPTY}, - {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}, EMPTY}, - {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}, EMPTY}, - {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}, EMPTY}, - {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}, EMPTY}, - {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}, EMPTY}, - {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}, EMPTY}, - {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}, EMPTY}, - {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}, EMPTY}, - {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}, EMPTY}, - {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}, EMPTY}, - {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}, EMPTY}, - {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}, EMPTY}, - {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}, EMPTY}, - {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}, EMPTY}, - - /* Floating-point load w/increment by register. */ -#define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC, 0, NULL - {"ldfs", FLDINCREG (0x02, 0)}, - {"ldfs.nt1", FLDINCREG (0x02, 1)}, - {"ldfs.nta", FLDINCREG (0x02, 3)}, - {"ldfd", FLDINCREG (0x03, 0)}, - {"ldfd.nt1", FLDINCREG (0x03, 1)}, - {"ldfd.nta", FLDINCREG (0x03, 3)}, - {"ldf8", FLDINCREG (0x01, 0)}, - {"ldf8.nt1", FLDINCREG (0x01, 1)}, - {"ldf8.nta", FLDINCREG (0x01, 3)}, - {"ldfe", FLDINCREG (0x00, 0)}, - {"ldfe.nt1", FLDINCREG (0x00, 1)}, - {"ldfe.nta", FLDINCREG (0x00, 3)}, - {"ldfs.s", FLDINCREG (0x06, 0)}, - {"ldfs.s.nt1", FLDINCREG (0x06, 1)}, - {"ldfs.s.nta", FLDINCREG (0x06, 3)}, - {"ldfd.s", FLDINCREG (0x07, 0)}, - {"ldfd.s.nt1", FLDINCREG (0x07, 1)}, - {"ldfd.s.nta", FLDINCREG (0x07, 3)}, - {"ldf8.s", FLDINCREG (0x05, 0)}, - {"ldf8.s.nt1", FLDINCREG (0x05, 1)}, - {"ldf8.s.nta", FLDINCREG (0x05, 3)}, - {"ldfe.s", FLDINCREG (0x04, 0)}, - {"ldfe.s.nt1", FLDINCREG (0x04, 1)}, - {"ldfe.s.nta", FLDINCREG (0x04, 3)}, - {"ldfs.a", FLDINCREG (0x0a, 0)}, - {"ldfs.a.nt1", FLDINCREG (0x0a, 1)}, - {"ldfs.a.nta", FLDINCREG (0x0a, 3)}, - {"ldfd.a", FLDINCREG (0x0b, 0)}, - {"ldfd.a.nt1", FLDINCREG (0x0b, 1)}, - {"ldfd.a.nta", FLDINCREG (0x0b, 3)}, - {"ldf8.a", FLDINCREG (0x09, 0)}, - {"ldf8.a.nt1", FLDINCREG (0x09, 1)}, - {"ldf8.a.nta", FLDINCREG (0x09, 3)}, - {"ldfe.a", FLDINCREG (0x08, 0)}, - {"ldfe.a.nt1", FLDINCREG (0x08, 1)}, - {"ldfe.a.nta", FLDINCREG (0x08, 3)}, - {"ldfs.sa", FLDINCREG (0x0e, 0)}, - {"ldfs.sa.nt1", FLDINCREG (0x0e, 1)}, - {"ldfs.sa.nta", FLDINCREG (0x0e, 3)}, - {"ldfd.sa", FLDINCREG (0x0f, 0)}, - {"ldfd.sa.nt1", FLDINCREG (0x0f, 1)}, - {"ldfd.sa.nta", FLDINCREG (0x0f, 3)}, - {"ldf8.sa", FLDINCREG (0x0d, 0)}, - {"ldf8.sa.nt1", FLDINCREG (0x0d, 1)}, - {"ldf8.sa.nta", FLDINCREG (0x0d, 3)}, - {"ldfe.sa", FLDINCREG (0x0c, 0)}, - {"ldfe.sa.nt1", FLDINCREG (0x0c, 1)}, - {"ldfe.sa.nta", FLDINCREG (0x0c, 3)}, - {"ldf.fill", FLDINCREG (0x1b, 0)}, - {"ldf.fill.nt1", FLDINCREG (0x1b, 1)}, - {"ldf.fill.nta", FLDINCREG (0x1b, 3)}, - {"ldfs.c.clr", FLDINCREG (0x22, 0)}, - {"ldfs.c.clr.nt1", FLDINCREG (0x22, 1)}, - {"ldfs.c.clr.nta", FLDINCREG (0x22, 3)}, - {"ldfd.c.clr", FLDINCREG (0x23, 0)}, - {"ldfd.c.clr.nt1", FLDINCREG (0x23, 1)}, - {"ldfd.c.clr.nta", FLDINCREG (0x23, 3)}, - {"ldf8.c.clr", FLDINCREG (0x21, 0)}, - {"ldf8.c.clr.nt1", FLDINCREG (0x21, 1)}, - {"ldf8.c.clr.nta", FLDINCREG (0x21, 3)}, - {"ldfe.c.clr", FLDINCREG (0x20, 0)}, - {"ldfe.c.clr.nt1", FLDINCREG (0x20, 1)}, - {"ldfe.c.clr.nta", FLDINCREG (0x20, 3)}, - {"ldfs.c.nc", FLDINCREG (0x26, 0)}, - {"ldfs.c.nc.nt1", FLDINCREG (0x26, 1)}, - {"ldfs.c.nc.nta", FLDINCREG (0x26, 3)}, - {"ldfd.c.nc", FLDINCREG (0x27, 0)}, - {"ldfd.c.nc.nt1", FLDINCREG (0x27, 1)}, - {"ldfd.c.nc.nta", FLDINCREG (0x27, 3)}, - {"ldf8.c.nc", FLDINCREG (0x25, 0)}, - {"ldf8.c.nc.nt1", FLDINCREG (0x25, 1)}, - {"ldf8.c.nc.nta", FLDINCREG (0x25, 3)}, - {"ldfe.c.nc", FLDINCREG (0x24, 0)}, - {"ldfe.c.nc.nt1", FLDINCREG (0x24, 1)}, - {"ldfe.c.nc.nta", FLDINCREG (0x24, 3)}, -#undef FLDINCREG - - /* Floating-point store. */ - {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}, EMPTY}, - {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}, EMPTY}, - {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}, EMPTY}, - {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}, EMPTY}, - {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}, EMPTY}, - {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}, EMPTY}, - {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}, EMPTY}, - {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}, EMPTY}, - {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}, EMPTY}, - {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}, EMPTY}, - - /* Floating-point load pair. */ - {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}, EMPTY}, - {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}, EMPTY}, - {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}, EMPTY}, - {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}, EMPTY}, - {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}, EMPTY}, - {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}, EMPTY}, - {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}, EMPTY}, - {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}, EMPTY}, - {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}, EMPTY}, - {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}, EMPTY}, - {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}, EMPTY}, - {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}, EMPTY}, - {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}, EMPTY}, - {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}, EMPTY}, - {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}, EMPTY}, - {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}, EMPTY}, - {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}, EMPTY}, - {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}, EMPTY}, - {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}, EMPTY}, - {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}, EMPTY}, - {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}, EMPTY}, - {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}, EMPTY}, - {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}, EMPTY}, - {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}, EMPTY}, - {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}, EMPTY}, - {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}, EMPTY}, - {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}, EMPTY}, - {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}, EMPTY}, - {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}, EMPTY}, - {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}, EMPTY}, - {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}, EMPTY}, - {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}, EMPTY}, - {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}, EMPTY}, - {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}, EMPTY}, - {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}, EMPTY}, - {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}, EMPTY}, - - /* Floating-point load pair w/increment by immediate. */ -#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC, 0, NULL - {"ldfps", LD (0x02, 0, C8)}, - {"ldfps.nt1", LD (0x02, 1, C8)}, - {"ldfps.nta", LD (0x02, 3, C8)}, - {"ldfpd", LD (0x03, 0, C16)}, - {"ldfpd.nt1", LD (0x03, 1, C16)}, - {"ldfpd.nta", LD (0x03, 3, C16)}, - {"ldfp8", LD (0x01, 0, C16)}, - {"ldfp8.nt1", LD (0x01, 1, C16)}, - {"ldfp8.nta", LD (0x01, 3, C16)}, - {"ldfps.s", LD (0x06, 0, C8)}, - {"ldfps.s.nt1", LD (0x06, 1, C8)}, - {"ldfps.s.nta", LD (0x06, 3, C8)}, - {"ldfpd.s", LD (0x07, 0, C16)}, - {"ldfpd.s.nt1", LD (0x07, 1, C16)}, - {"ldfpd.s.nta", LD (0x07, 3, C16)}, - {"ldfp8.s", LD (0x05, 0, C16)}, - {"ldfp8.s.nt1", LD (0x05, 1, C16)}, - {"ldfp8.s.nta", LD (0x05, 3, C16)}, - {"ldfps.a", LD (0x0a, 0, C8)}, - {"ldfps.a.nt1", LD (0x0a, 1, C8)}, - {"ldfps.a.nta", LD (0x0a, 3, C8)}, - {"ldfpd.a", LD (0x0b, 0, C16)}, - {"ldfpd.a.nt1", LD (0x0b, 1, C16)}, - {"ldfpd.a.nta", LD (0x0b, 3, C16)}, - {"ldfp8.a", LD (0x09, 0, C16)}, - {"ldfp8.a.nt1", LD (0x09, 1, C16)}, - {"ldfp8.a.nta", LD (0x09, 3, C16)}, - {"ldfps.sa", LD (0x0e, 0, C8)}, - {"ldfps.sa.nt1", LD (0x0e, 1, C8)}, - {"ldfps.sa.nta", LD (0x0e, 3, C8)}, - {"ldfpd.sa", LD (0x0f, 0, C16)}, - {"ldfpd.sa.nt1", LD (0x0f, 1, C16)}, - {"ldfpd.sa.nta", LD (0x0f, 3, C16)}, - {"ldfp8.sa", LD (0x0d, 0, C16)}, - {"ldfp8.sa.nt1", LD (0x0d, 1, C16)}, - {"ldfp8.sa.nta", LD (0x0d, 3, C16)}, - {"ldfps.c.clr", LD (0x22, 0, C8)}, - {"ldfps.c.clr.nt1", LD (0x22, 1, C8)}, - {"ldfps.c.clr.nta", LD (0x22, 3, C8)}, - {"ldfpd.c.clr", LD (0x23, 0, C16)}, - {"ldfpd.c.clr.nt1", LD (0x23, 1, C16)}, - {"ldfpd.c.clr.nta", LD (0x23, 3, C16)}, - {"ldfp8.c.clr", LD (0x21, 0, C16)}, - {"ldfp8.c.clr.nt1", LD (0x21, 1, C16)}, - {"ldfp8.c.clr.nta", LD (0x21, 3, C16)}, - {"ldfps.c.nc", LD (0x26, 0, C8)}, - {"ldfps.c.nc.nt1", LD (0x26, 1, C8)}, - {"ldfps.c.nc.nta", LD (0x26, 3, C8)}, - {"ldfpd.c.nc", LD (0x27, 0, C16)}, - {"ldfpd.c.nc.nt1", LD (0x27, 1, C16)}, - {"ldfpd.c.nc.nta", LD (0x27, 3, C16)}, - {"ldfp8.c.nc", LD (0x25, 0, C16)}, - {"ldfp8.c.nc.nt1", LD (0x25, 1, C16)}, - {"ldfp8.c.nc.nta", LD (0x25, 3, C16)}, -#undef LD - - /* Line prefetch. */ - {"lfetch", M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}, EMPTY}, - {"lfetch.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}, EMPTY}, - {"lfetch.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}, EMPTY}, - {"lfetch.nta", M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}, EMPTY}, - {"lfetch.excl", M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}, EMPTY}, - {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}, EMPTY}, - {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}, EMPTY}, - {"lfetch.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}, EMPTY}, - {"lfetch.fault", M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}, EMPTY}, - {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}, EMPTY}, - {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}, EMPTY}, - {"lfetch.fault.nta", M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}, EMPTY}, - {"lfetch.fault.excl", M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}, EMPTY}, - {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}, EMPTY}, - {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}, EMPTY}, - {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}, EMPTY}, - - /* Line prefetch w/increment by register. */ -#define LFETCHINCREG(c,h) M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC, 0, NULL - {"lfetch", LFETCHINCREG (0x2c, 0)}, - {"lfetch.nt1", LFETCHINCREG (0x2c, 1)}, - {"lfetch.nt2", LFETCHINCREG (0x2c, 2)}, - {"lfetch.nta", LFETCHINCREG (0x2c, 3)}, - {"lfetch.excl", LFETCHINCREG (0x2d, 0)}, - {"lfetch.excl.nt1", LFETCHINCREG (0x2d, 1)}, - {"lfetch.excl.nt2", LFETCHINCREG (0x2d, 2)}, - {"lfetch.excl.nta", LFETCHINCREG (0x2d, 3)}, - {"lfetch.fault", LFETCHINCREG (0x2e, 0)}, - {"lfetch.fault.nt1", LFETCHINCREG (0x2e, 1)}, - {"lfetch.fault.nt2", LFETCHINCREG (0x2e, 2)}, - {"lfetch.fault.nta", LFETCHINCREG (0x2e, 3)}, - {"lfetch.fault.excl", LFETCHINCREG (0x2f, 0)}, - {"lfetch.fault.excl.nt1", LFETCHINCREG (0x2f, 1)}, - {"lfetch.fault.excl.nt2", LFETCHINCREG (0x2f, 2)}, - {"lfetch.fault.excl.nta", LFETCHINCREG (0x2f, 3)}, -#undef LFETCHINCREG - - /* Semaphore operations. */ - {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}, EMPTY}, - {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}, EMPTY}, - {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}, EMPTY}, - {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}, EMPTY}, - - /* Floating-point load w/increment by immediate. */ -#define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC, 0, NULL - {"ldfs", FLDINCIMMED (0x02, 0)}, - {"ldfs.nt1", FLDINCIMMED (0x02, 1)}, - {"ldfs.nta", FLDINCIMMED (0x02, 3)}, - {"ldfd", FLDINCIMMED (0x03, 0)}, - {"ldfd.nt1", FLDINCIMMED (0x03, 1)}, - {"ldfd.nta", FLDINCIMMED (0x03, 3)}, - {"ldf8", FLDINCIMMED (0x01, 0)}, - {"ldf8.nt1", FLDINCIMMED (0x01, 1)}, - {"ldf8.nta", FLDINCIMMED (0x01, 3)}, - {"ldfe", FLDINCIMMED (0x00, 0)}, - {"ldfe.nt1", FLDINCIMMED (0x00, 1)}, - {"ldfe.nta", FLDINCIMMED (0x00, 3)}, - {"ldfs.s", FLDINCIMMED (0x06, 0)}, - {"ldfs.s.nt1", FLDINCIMMED (0x06, 1)}, - {"ldfs.s.nta", FLDINCIMMED (0x06, 3)}, - {"ldfd.s", FLDINCIMMED (0x07, 0)}, - {"ldfd.s.nt1", FLDINCIMMED (0x07, 1)}, - {"ldfd.s.nta", FLDINCIMMED (0x07, 3)}, - {"ldf8.s", FLDINCIMMED (0x05, 0)}, - {"ldf8.s.nt1", FLDINCIMMED (0x05, 1)}, - {"ldf8.s.nta", FLDINCIMMED (0x05, 3)}, - {"ldfe.s", FLDINCIMMED (0x04, 0)}, - {"ldfe.s.nt1", FLDINCIMMED (0x04, 1)}, - {"ldfe.s.nta", FLDINCIMMED (0x04, 3)}, - {"ldfs.a", FLDINCIMMED (0x0a, 0)}, - {"ldfs.a.nt1", FLDINCIMMED (0x0a, 1)}, - {"ldfs.a.nta", FLDINCIMMED (0x0a, 3)}, - {"ldfd.a", FLDINCIMMED (0x0b, 0)}, - {"ldfd.a.nt1", FLDINCIMMED (0x0b, 1)}, - {"ldfd.a.nta", FLDINCIMMED (0x0b, 3)}, - {"ldf8.a", FLDINCIMMED (0x09, 0)}, - {"ldf8.a.nt1", FLDINCIMMED (0x09, 1)}, - {"ldf8.a.nta", FLDINCIMMED (0x09, 3)}, - {"ldfe.a", FLDINCIMMED (0x08, 0)}, - {"ldfe.a.nt1", FLDINCIMMED (0x08, 1)}, - {"ldfe.a.nta", FLDINCIMMED (0x08, 3)}, - {"ldfs.sa", FLDINCIMMED (0x0e, 0)}, - {"ldfs.sa.nt1", FLDINCIMMED (0x0e, 1)}, - {"ldfs.sa.nta", FLDINCIMMED (0x0e, 3)}, - {"ldfd.sa", FLDINCIMMED (0x0f, 0)}, - {"ldfd.sa.nt1", FLDINCIMMED (0x0f, 1)}, - {"ldfd.sa.nta", FLDINCIMMED (0x0f, 3)}, - {"ldf8.sa", FLDINCIMMED (0x0d, 0)}, - {"ldf8.sa.nt1", FLDINCIMMED (0x0d, 1)}, - {"ldf8.sa.nta", FLDINCIMMED (0x0d, 3)}, - {"ldfe.sa", FLDINCIMMED (0x0c, 0)}, - {"ldfe.sa.nt1", FLDINCIMMED (0x0c, 1)}, - {"ldfe.sa.nta", FLDINCIMMED (0x0c, 3)}, - {"ldf.fill", FLDINCIMMED (0x1b, 0)}, - {"ldf.fill.nt1", FLDINCIMMED (0x1b, 1)}, - {"ldf.fill.nta", FLDINCIMMED (0x1b, 3)}, - {"ldfs.c.clr", FLDINCIMMED (0x22, 0)}, - {"ldfs.c.clr.nt1", FLDINCIMMED (0x22, 1)}, - {"ldfs.c.clr.nta", FLDINCIMMED (0x22, 3)}, - {"ldfd.c.clr", FLDINCIMMED (0x23, 0)}, - {"ldfd.c.clr.nt1", FLDINCIMMED (0x23, 1)}, - {"ldfd.c.clr.nta", FLDINCIMMED (0x23, 3)}, - {"ldf8.c.clr", FLDINCIMMED (0x21, 0)}, - {"ldf8.c.clr.nt1", FLDINCIMMED (0x21, 1)}, - {"ldf8.c.clr.nta", FLDINCIMMED (0x21, 3)}, - {"ldfe.c.clr", FLDINCIMMED (0x20, 0)}, - {"ldfe.c.clr.nt1", FLDINCIMMED (0x20, 1)}, - {"ldfe.c.clr.nta", FLDINCIMMED (0x20, 3)}, - {"ldfs.c.nc", FLDINCIMMED (0x26, 0)}, - {"ldfs.c.nc.nt1", FLDINCIMMED (0x26, 1)}, - {"ldfs.c.nc.nta", FLDINCIMMED (0x26, 3)}, - {"ldfd.c.nc", FLDINCIMMED (0x27, 0)}, - {"ldfd.c.nc.nt1", FLDINCIMMED (0x27, 1)}, - {"ldfd.c.nc.nta", FLDINCIMMED (0x27, 3)}, - {"ldf8.c.nc", FLDINCIMMED (0x25, 0)}, - {"ldf8.c.nc.nt1", FLDINCIMMED (0x25, 1)}, - {"ldf8.c.nc.nta", FLDINCIMMED (0x25, 3)}, - {"ldfe.c.nc", FLDINCIMMED (0x24, 0)}, - {"ldfe.c.nc.nt1", FLDINCIMMED (0x24, 1)}, - {"ldfe.c.nc.nta", FLDINCIMMED (0x24, 3)}, -#undef FLDINCIMMED - - /* Floating-point store w/increment by immediate. */ -#define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC, 0, NULL - {"stfs", FSTINCIMMED (0x32, 0)}, - {"stfs.nta", FSTINCIMMED (0x32, 3)}, - {"stfd", FSTINCIMMED (0x33, 0)}, - {"stfd.nta", FSTINCIMMED (0x33, 3)}, - {"stf8", FSTINCIMMED (0x31, 0)}, - {"stf8.nta", FSTINCIMMED (0x31, 3)}, - {"stfe", FSTINCIMMED (0x30, 0)}, - {"stfe.nta", FSTINCIMMED (0x30, 3)}, - {"stf.spill", FSTINCIMMED (0x3b, 0)}, - {"stf.spill.nta", FSTINCIMMED (0x3b, 3)}, -#undef FSTINCIMMED - - /* Line prefetch w/increment by immediate. */ -#define LFETCHINCIMMED(c,h) M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC, 0, NULL - {"lfetch", LFETCHINCIMMED (0x2c, 0)}, - {"lfetch.nt1", LFETCHINCIMMED (0x2c, 1)}, - {"lfetch.nt2", LFETCHINCIMMED (0x2c, 2)}, - {"lfetch.nta", LFETCHINCIMMED (0x2c, 3)}, - {"lfetch.excl", LFETCHINCIMMED (0x2d, 0)}, - {"lfetch.excl.nt1", LFETCHINCIMMED (0x2d, 1)}, - {"lfetch.excl.nt2", LFETCHINCIMMED (0x2d, 2)}, - {"lfetch.excl.nta", LFETCHINCIMMED (0x2d, 3)}, - {"lfetch.fault", LFETCHINCIMMED (0x2e, 0)}, - {"lfetch.fault.nt1", LFETCHINCIMMED (0x2e, 1)}, - {"lfetch.fault.nt2", LFETCHINCIMMED (0x2e, 2)}, - {"lfetch.fault.nta", LFETCHINCIMMED (0x2e, 3)}, - {"lfetch.fault.excl", LFETCHINCIMMED (0x2f, 0)}, - {"lfetch.fault.excl.nt1", LFETCHINCIMMED (0x2f, 1)}, - {"lfetch.fault.excl.nt2", LFETCHINCIMMED (0x2f, 2)}, - {"lfetch.fault.excl.nta", LFETCHINCIMMED (0x2f, 3)}, -#undef LFETCHINCIMMED - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef M0 -#undef M -#undef M2 -#undef bM -#undef bX -#undef bX2 -#undef bX3 -#undef bX4 -#undef bX6a -#undef bX6b -#undef bHint -#undef mM -#undef mX -#undef mX2 -#undef mX3 -#undef mX4 -#undef mX6a -#undef mX6b -#undef mHint -#undef OpX3 -#undef OpX3X6b -#undef OpX3X4 -#undef OpX3X4X2 -#undef OpX6aHint -#undef OpXX6aHint -#undef OpMXX6a -#undef OpMXX6aHint -#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-x.c b/contrib/binutils/opcodes/ia64-opc-x.c deleted file mode 100644 index e1d4345..0000000 --- a/contrib/binutils/opcodes/ia64-opc-x.c +++ /dev/null @@ -1,188 +0,0 @@ -/* ia64-opc-x.c -- IA-64 `X' opcode table. - Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. - Contributed by Timothy Wall <twall@cygnus.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include "ia64-opc.h" - -/* Identify the specific X-unit type. */ -#define X0 IA64_TYPE_X, 0 -#define X IA64_TYPE_X, 1 - -/* Instruction bit fields: */ -#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) -#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) -#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) -#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) -#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) -#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) -#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) -#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) - -#define mBtype bBtype (-1) -#define mD bD (-1) -#define mPa bPa (-1) -#define mPr bPr (-1) -#define mVc bVc (-1) -#define mWha bWha (-1) -#define mX3 bX3 (-1) -#define mX6 bX6 (-1) -#define mY bY (-1) - -#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ - (mOp | mX3 | mX6) -#define OpX3X6Y(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bY(d)), \ - (mOp | mX3 | mX6 | mY) -#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc) -#define OpPaWhaD(a,b,c,d) \ - (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) -#define OpBtypePaWhaD(a,b,c,d,e) \ - (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ - (mOp | mBtype | mPa | mWha | mD) -#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ - (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ - (mOp | mBtype | mPa | mWha | mD | mPr) - -struct ia64_opcode ia64_opcodes_x[] = - { - {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL}, - {"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL}, - {"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL}, - {"movl", X, OpVc (6, 0), {R1, IMMU64}, 0, 0, NULL}, -#define BRL(a,b) \ - X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL - {"brl.few", BRL (0, 0)}, - {"brl", BRL (0, 0)}, - {"brl.few.clr", BRL (0, 1)}, - {"brl.clr", BRL (0, 1)}, - {"brl.many", BRL (1, 0)}, - {"brl.many.clr", BRL (1, 1)}, -#undef BRL -#define BRL(a,b,c) \ - X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0, 0, NULL -#define BRLP(a,b,c) \ - X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, PSEUDO, 0, NULL - {"brl.cond.sptk.few", BRL (0, 0, 0)}, - {"brl.cond.sptk", BRLP (0, 0, 0)}, - {"brl.cond.sptk.few.clr", BRL (0, 0, 1)}, - {"brl.cond.sptk.clr", BRLP (0, 0, 1)}, - {"brl.cond.spnt.few", BRL (0, 1, 0)}, - {"brl.cond.spnt", BRLP (0, 1, 0)}, - {"brl.cond.spnt.few.clr", BRL (0, 1, 1)}, - {"brl.cond.spnt.clr", BRLP (0, 1, 1)}, - {"brl.cond.dptk.few", BRL (0, 2, 0)}, - {"brl.cond.dptk", BRLP (0, 2, 0)}, - {"brl.cond.dptk.few.clr", BRL (0, 2, 1)}, - {"brl.cond.dptk.clr", BRLP (0, 2, 1)}, - {"brl.cond.dpnt.few", BRL (0, 3, 0)}, - {"brl.cond.dpnt", BRLP (0, 3, 0)}, - {"brl.cond.dpnt.few.clr", BRL (0, 3, 1)}, - {"brl.cond.dpnt.clr", BRLP (0, 3, 1)}, - {"brl.cond.sptk.many", BRL (1, 0, 0)}, - {"brl.cond.sptk.many.clr", BRL (1, 0, 1)}, - {"brl.cond.spnt.many", BRL (1, 1, 0)}, - {"brl.cond.spnt.many.clr", BRL (1, 1, 1)}, - {"brl.cond.dptk.many", BRL (1, 2, 0)}, - {"brl.cond.dptk.many.clr", BRL (1, 2, 1)}, - {"brl.cond.dpnt.many", BRL (1, 3, 0)}, - {"brl.cond.dpnt.many.clr", BRL (1, 3, 1)}, - {"brl.sptk.few", BRL (0, 0, 0)}, - {"brl.sptk", BRLP (0, 0, 0)}, - {"brl.sptk.few.clr", BRL (0, 0, 1)}, - {"brl.sptk.clr", BRLP (0, 0, 1)}, - {"brl.spnt.few", BRL (0, 1, 0)}, - {"brl.spnt", BRLP (0, 1, 0)}, - {"brl.spnt.few.clr", BRL (0, 1, 1)}, - {"brl.spnt.clr", BRLP (0, 1, 1)}, - {"brl.dptk.few", BRL (0, 2, 0)}, - {"brl.dptk", BRLP (0, 2, 0)}, - {"brl.dptk.few.clr", BRL (0, 2, 1)}, - {"brl.dptk.clr", BRLP (0, 2, 1)}, - {"brl.dpnt.few", BRL (0, 3, 0)}, - {"brl.dpnt", BRLP (0, 3, 0)}, - {"brl.dpnt.few.clr", BRL (0, 3, 1)}, - {"brl.dpnt.clr", BRLP (0, 3, 1)}, - {"brl.sptk.many", BRL (1, 0, 0)}, - {"brl.sptk.many.clr", BRL (1, 0, 1)}, - {"brl.spnt.many", BRL (1, 1, 0)}, - {"brl.spnt.many.clr", BRL (1, 1, 1)}, - {"brl.dptk.many", BRL (1, 2, 0)}, - {"brl.dptk.many.clr", BRL (1, 2, 1)}, - {"brl.dpnt.many", BRL (1, 3, 0)}, - {"brl.dpnt.many.clr", BRL (1, 3, 1)}, -#undef BRL -#undef BRLP -#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0, 0, NULL -#define BRLP(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, PSEUDO, 0, NULL - {"brl.call.sptk.few", BRL (0, 0, 0)}, - {"brl.call.sptk", BRLP (0, 0, 0)}, - {"brl.call.sptk.few.clr", BRL (0, 0, 1)}, - {"brl.call.sptk.clr", BRLP (0, 0, 1)}, - {"brl.call.spnt.few", BRL (0, 1, 0)}, - {"brl.call.spnt", BRLP (0, 1, 0)}, - {"brl.call.spnt.few.clr", BRL (0, 1, 1)}, - {"brl.call.spnt.clr", BRLP (0, 1, 1)}, - {"brl.call.dptk.few", BRL (0, 2, 0)}, - {"brl.call.dptk", BRLP (0, 2, 0)}, - {"brl.call.dptk.few.clr", BRL (0, 2, 1)}, - {"brl.call.dptk.clr", BRLP (0, 2, 1)}, - {"brl.call.dpnt.few", BRL (0, 3, 0)}, - {"brl.call.dpnt", BRLP (0, 3, 0)}, - {"brl.call.dpnt.few.clr", BRL (0, 3, 1)}, - {"brl.call.dpnt.clr", BRLP (0, 3, 1)}, - {"brl.call.sptk.many", BRL (1, 0, 0)}, - {"brl.call.sptk.many.clr", BRL (1, 0, 1)}, - {"brl.call.spnt.many", BRL (1, 1, 0)}, - {"brl.call.spnt.many.clr", BRL (1, 1, 1)}, - {"brl.call.dptk.many", BRL (1, 2, 0)}, - {"brl.call.dptk.many.clr", BRL (1, 2, 1)}, - {"brl.call.dpnt.many", BRL (1, 3, 0)}, - {"brl.call.dpnt.many.clr", BRL (1, 3, 1)}, -#undef BRL -#undef BRLP - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef X0 -#undef X - -#undef bBtype -#undef bD -#undef bPa -#undef bPr -#undef bVc -#undef bWha -#undef bX3 -#undef bX6 - -#undef mBtype -#undef mD -#undef mPa -#undef mPr -#undef mVc -#undef mWha -#undef mX3 -#undef mX6 - -#undef OpX3X6 -#undef OpVc -#undef OpPaWhaD -#undef OpBtypePaWhaD -#undef OpBtypePaWhaDPr diff --git a/contrib/binutils/opcodes/ia64-opc.c b/contrib/binutils/opcodes/ia64-opc.c deleted file mode 100644 index fc90213..0000000 --- a/contrib/binutils/opcodes/ia64-opc.c +++ /dev/null @@ -1,730 +0,0 @@ -/* ia64-opc.c -- Functions to access the compacted opcode table - Copyright 1999, 2000, 2003 Free Software Foundation, Inc. - Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include "ansidecl.h" -#include "libiberty.h" -#include "sysdep.h" -#include "ia64-asmtab.h" -#include "ia64-asmtab.c" - -static void get_opc_prefix (const char **, char *); -static short int find_string_ent (const char *); -static short int find_main_ent (short int); -static short int find_completer (short int, short int, const char *); -static ia64_insn apply_completer (ia64_insn, int); -static int extract_op_bits (int, int, int); -static int extract_op (int, int *, unsigned int *); -static int opcode_verify (ia64_insn, int, enum ia64_insn_type); -static int locate_opcode_ent (ia64_insn, enum ia64_insn_type); -static struct ia64_opcode *make_ia64_opcode - (ia64_insn, const char *, int, int); -static struct ia64_opcode *ia64_find_matching_opcode - (const char *, short int); - -const struct ia64_templ_desc ia64_templ_desc[16] = - { - { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */ - { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, - { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" }, - { 0, { 0, }, "-3-" }, - { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */ - { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, - { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" }, - { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" }, - { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */ - { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" }, - { 0, { 0, }, "-a-" }, - { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" }, - { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */ - { 0, { 0, }, "-d-" }, - { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" }, - { 0, { 0, }, "-f-" }, - }; - - -/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST. - PTR will be adjusted to point to the start of the next portion - of the opcode, or at the NUL character. */ - -static void -get_opc_prefix (const char **ptr, char *dest) -{ - char *c = strchr (*ptr, '.'); - if (c != NULL) - { - memcpy (dest, *ptr, c - *ptr); - dest[c - *ptr] = '\0'; - *ptr = c + 1; - } - else - { - int l = strlen (*ptr); - memcpy (dest, *ptr, l); - dest[l] = '\0'; - *ptr += l; - } -} - -/* Find the index of the entry in the string table corresponding to - STR; return -1 if one does not exist. */ - -static short -find_string_ent (const char *str) -{ - short start = 0; - short end = sizeof (ia64_strings) / sizeof (const char *); - short i = (start + end) / 2; - - if (strcmp (str, ia64_strings[end - 1]) > 0) - { - return -1; - } - while (start <= end) - { - int c = strcmp (str, ia64_strings[i]); - if (c < 0) - { - end = i - 1; - } - else if (c == 0) - { - return i; - } - else - { - start = i + 1; - } - i = (start + end) / 2; - } - return -1; -} - -/* Find the opcode in the main opcode table whose name is STRINGINDEX, or - return -1 if one does not exist. */ - -static short -find_main_ent (short nameindex) -{ - short start = 0; - short end = sizeof (main_table) / sizeof (struct ia64_main_table); - short i = (start + end) / 2; - - if (nameindex < main_table[0].name_index - || nameindex > main_table[end - 1].name_index) - { - return -1; - } - while (start <= end) - { - if (nameindex < main_table[i].name_index) - { - end = i - 1; - } - else if (nameindex == main_table[i].name_index) - { - while (i > 0 && main_table[i - 1].name_index == nameindex) - { - i--; - } - return i; - } - else - { - start = i + 1; - } - i = (start + end) / 2; - } - return -1; -} - -/* Find the index of the entry in the completer table that is part of - MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or - return -1 if one does not exist. */ - -static short -find_completer (short main_ent, short prev_completer, const char *name) -{ - short name_index = find_string_ent (name); - - if (name_index < 0) - { - return -1; - } - - if (prev_completer == -1) - { - prev_completer = main_table[main_ent].completers; - } - else - { - prev_completer = completer_table[prev_completer].subentries; - } - - while (prev_completer != -1) - { - if (completer_table[prev_completer].name_index == name_index) - { - return prev_completer; - } - prev_completer = completer_table[prev_completer].alternative; - } - return -1; -} - -/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and - return the result. */ - -static ia64_insn -apply_completer (ia64_insn opcode, int completer_index) -{ - ia64_insn mask = completer_table[completer_index].mask; - ia64_insn bits = completer_table[completer_index].bits; - int shiftamt = (completer_table[completer_index].offset & 63); - - mask = mask << shiftamt; - bits = bits << shiftamt; - opcode = (opcode & ~mask) | bits; - return opcode; -} - -/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in - the dis_table array, and return its value. (BITOFFSET is numbered - starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the - first byte in OP_POINTER.) */ - -static int -extract_op_bits (int op_pointer, int bitoffset, int bits) -{ - int res = 0; - - op_pointer += (bitoffset / 8); - - if (bitoffset % 8) - { - unsigned int op = dis_table[op_pointer++]; - int numb = 8 - (bitoffset % 8); - int mask = (1 << numb) - 1; - int bata = (bits < numb) ? bits : numb; - int delta = numb - bata; - - res = (res << bata) | ((op & mask) >> delta); - bitoffset += bata; - bits -= bata; - } - while (bits >= 8) - { - res = (res << 8) | (dis_table[op_pointer++] & 255); - bits -= 8; - } - if (bits > 0) - { - unsigned int op = (dis_table[op_pointer++] & 255); - res = (res << bits) | (op >> (8 - bits)); - } - return res; -} - -/* Examine the state machine entry at OP_POINTER in the dis_table - array, and extract its values into OPVAL and OP. The length of the - state entry in bits is returned. */ - -static int -extract_op (int op_pointer, int *opval, unsigned int *op) -{ - int oplen = 5; - - *op = dis_table[op_pointer]; - - if ((*op) & 0x40) - { - opval[0] = extract_op_bits (op_pointer, oplen, 5); - oplen += 5; - } - switch ((*op) & 0x30) - { - case 0x10: - { - opval[1] = extract_op_bits (op_pointer, oplen, 8); - oplen += 8; - opval[1] += op_pointer; - break; - } - case 0x20: - { - opval[1] = extract_op_bits (op_pointer, oplen, 16); - if (! (opval[1] & 32768)) - { - opval[1] += op_pointer; - } - oplen += 16; - break; - } - case 0x30: - { - oplen--; - opval[2] = extract_op_bits (op_pointer, oplen, 12); - oplen += 12; - opval[2] |= 32768; - break; - } - } - if (((*op) & 0x08) && (((*op) & 0x30) != 0x30)) - { - opval[2] = extract_op_bits (op_pointer, oplen, 16); - oplen += 16; - if (! (opval[2] & 32768)) - { - opval[2] += op_pointer; - } - } - return oplen; -} - -/* Returns a non-zero value if the opcode in the main_table list at - PLACE matches OPCODE and is of type TYPE. */ - -static int -opcode_verify (ia64_insn opcode, int place, enum ia64_insn_type type) -{ - if (main_table[place].opcode_type != type) - { - return 0; - } - if (main_table[place].flags - & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT)) - { - const struct ia64_operand *o1, *o2; - ia64_insn f2, f3; - - if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3) - { - o1 = elf64_ia64_operands + IA64_OPND_F2; - o2 = elf64_ia64_operands + IA64_OPND_F3; - (*o1->extract) (o1, opcode, &f2); - (*o2->extract) (o2, opcode, &f3); - if (f2 != f3) - return 0; - } - else - { - ia64_insn len, count; - - /* length must equal 64-count: */ - o1 = elf64_ia64_operands + IA64_OPND_LEN6; - o2 = elf64_ia64_operands + main_table[place].operands[2]; - (*o1->extract) (o1, opcode, &len); - (*o2->extract) (o2, opcode, &count); - if (len != 64 - count) - return 0; - } - } - return 1; -} - -/* Find an instruction entry in the ia64_dis_names array that matches - opcode OPCODE and is of type TYPE. Returns either a positive index - into the array, or a negative value if an entry for OPCODE could - not be found. Checks all matches and returns the one with the highest - priority. */ - -static int -locate_opcode_ent (ia64_insn opcode, enum ia64_insn_type type) -{ - int currtest[41]; - int bitpos[41]; - int op_ptr[41]; - int currstatenum = 0; - short found_disent = -1; - short found_priority = -1; - - currtest[currstatenum] = 0; - op_ptr[currstatenum] = 0; - bitpos[currstatenum] = 40; - - while (1) - { - int op_pointer = op_ptr[currstatenum]; - unsigned int op; - int currbitnum = bitpos[currstatenum]; - int oplen; - int opval[3]; - int next_op; - int currbit; - - oplen = extract_op (op_pointer, opval, &op); - - bitpos[currstatenum] = currbitnum; - - /* Skip opval[0] bits in the instruction. */ - if (op & 0x40) - { - currbitnum -= opval[0]; - } - - /* The value of the current bit being tested. */ - currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0; - next_op = -1; - - /* We always perform the tests specified in the current state in - a particular order, falling through to the next test if the - previous one failed. */ - switch (currtest[currstatenum]) - { - case 0: - currtest[currstatenum]++; - if (currbit == 0 && (op & 0x80)) - { - /* Check for a zero bit. If this test solely checks for - a zero bit, we can check for up to 8 consecutive zero - bits (the number to check is specified by the lower 3 - bits in the state code.) - - If the state instruction matches, we go to the very - next state instruction; otherwise, try the next test. */ - - if ((op & 0xf8) == 0x80) - { - int count = op & 0x7; - int x; - - for (x = 0; x <= count; x++) - { - int i = - opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0; - if (i) - { - break; - } - } - if (x > count) - { - next_op = op_pointer + ((oplen + 7) / 8); - currbitnum -= count; - break; - } - } - else if (! currbit) - { - next_op = op_pointer + ((oplen + 7) / 8); - break; - } - } - /* FALLTHROUGH */ - case 1: - /* If the bit in the instruction is one, go to the state - instruction specified by opval[1]. */ - currtest[currstatenum]++; - if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30)) - { - next_op = opval[1]; - break; - } - /* FALLTHROUGH */ - case 2: - /* Don't care. Skip the current bit and go to the state - instruction specified by opval[2]. - - An encoding of 0x30 is special; this means that a 12-bit - offset into the ia64_dis_names[] array is specified. */ - currtest[currstatenum]++; - if ((op & 0x08) || ((op & 0x30) == 0x30)) - { - next_op = opval[2]; - break; - } - } - - /* If bit 15 is set in the address of the next state, an offset - in the ia64_dis_names array was specified instead. We then - check to see if an entry in the list of opcodes matches the - opcode we were given; if so, we have succeeded. */ - - if ((next_op >= 0) && (next_op & 32768)) - { - short disent = next_op & 32767; - short priority = -1; - - if (next_op > 65535) - { - abort (); - } - - /* Run through the list of opcodes to check, trying to find - one that matches. */ - while (disent >= 0) - { - int place = ia64_dis_names[disent].insn_index; - - priority = ia64_dis_names[disent].priority; - - if (opcode_verify (opcode, place, type) - && priority > found_priority) - { - break; - } - if (ia64_dis_names[disent].next_flag) - { - disent++; - } - else - { - disent = -1; - } - } - - if (disent >= 0) - { - found_disent = disent; - found_priority = priority; - } - /* Try the next test in this state, regardless of whether a match - was found. */ - next_op = -2; - } - - /* next_op == -1 is "back up to the previous state". - next_op == -2 is "stay in this state and try the next test". - Otherwise, transition to the state indicated by next_op. */ - - if (next_op == -1) - { - currstatenum--; - if (currstatenum < 0) - { - return found_disent; - } - } - else if (next_op >= 0) - { - currstatenum++; - bitpos[currstatenum] = currbitnum - 1; - op_ptr[currstatenum] = next_op; - currtest[currstatenum] = 0; - } - } -} - -/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ - -static struct ia64_opcode * -make_ia64_opcode (ia64_insn opcode, const char *name, int place, int depind) -{ - struct ia64_opcode *res = - (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode)); - res->name = xstrdup (name); - res->type = main_table[place].opcode_type; - res->num_outputs = main_table[place].num_outputs; - res->opcode = opcode; - res->mask = main_table[place].mask; - res->operands[0] = main_table[place].operands[0]; - res->operands[1] = main_table[place].operands[1]; - res->operands[2] = main_table[place].operands[2]; - res->operands[3] = main_table[place].operands[3]; - res->operands[4] = main_table[place].operands[4]; - res->flags = main_table[place].flags; - res->ent_index = place; - res->dependencies = &op_dependencies[depind]; - return res; -} - -/* Determine the ia64_opcode entry for the opcode specified by INSN - and TYPE. If a valid entry is not found, return NULL. */ -struct ia64_opcode * -ia64_dis_opcode (ia64_insn insn, enum ia64_insn_type type) -{ - int disent = locate_opcode_ent (insn, type); - - if (disent < 0) - { - return NULL; - } - else - { - unsigned int cb = ia64_dis_names[disent].completer_index; - static char name[128]; - int place = ia64_dis_names[disent].insn_index; - int ci = main_table[place].completers; - ia64_insn tinsn = main_table[place].opcode; - - strcpy (name, ia64_strings [main_table[place].name_index]); - - while (cb) - { - if (cb & 1) - { - int cname = completer_table[ci].name_index; - - tinsn = apply_completer (tinsn, ci); - - if (ia64_strings[cname][0] != '\0') - { - strcat (name, "."); - strcat (name, ia64_strings[cname]); - } - if (cb != 1) - { - ci = completer_table[ci].subentries; - } - } - else - { - ci = completer_table[ci].alternative; - } - if (ci < 0) - { - abort (); - } - cb = cb >> 1; - } - if (tinsn != (insn & main_table[place].mask)) - { - abort (); - } - return make_ia64_opcode (insn, name, place, - completer_table[ci].dependencies); - } -} - -/* Search the main_opcode table starting from PLACE for an opcode that - matches NAME. Return NULL if one is not found. */ - -static struct ia64_opcode * -ia64_find_matching_opcode (const char *name, short place) -{ - char op[129]; - const char *suffix; - short name_index; - - if (strlen (name) > 128) - { - return NULL; - } - suffix = name; - get_opc_prefix (&suffix, op); - name_index = find_string_ent (op); - if (name_index < 0) - { - return NULL; - } - - while (main_table[place].name_index == name_index) - { - const char *curr_suffix = suffix; - ia64_insn curr_insn = main_table[place].opcode; - short completer = -1; - - do { - if (suffix[0] == '\0') - { - completer = find_completer (place, completer, suffix); - } - else - { - get_opc_prefix (&curr_suffix, op); - completer = find_completer (place, completer, op); - } - if (completer != -1) - { - curr_insn = apply_completer (curr_insn, completer); - } - } while (completer != -1 && curr_suffix[0] != '\0'); - - if (completer != -1 && curr_suffix[0] == '\0' - && completer_table[completer].terminal_completer) - { - int depind = completer_table[completer].dependencies; - return make_ia64_opcode (curr_insn, name, place, depind); - } - else - { - place++; - } - } - return NULL; -} - -/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL - if one does not exist. - - It is the caller's responsibility to invoke ia64_free_opcode () to - release any resources used by the returned entry. */ - -struct ia64_opcode * -ia64_find_next_opcode (struct ia64_opcode *prev_ent) -{ - return ia64_find_matching_opcode (prev_ent->name, - prev_ent->ent_index + 1); -} - -/* Find the first opcode that matches NAME, or return NULL if it does - not exist. - - It is the caller's responsibility to invoke ia64_free_opcode () to - release any resources used by the returned entry. */ - -struct ia64_opcode * -ia64_find_opcode (const char *name) -{ - char op[129]; - const char *suffix; - short place; - short name_index; - - if (strlen (name) > 128) - { - return NULL; - } - suffix = name; - get_opc_prefix (&suffix, op); - name_index = find_string_ent (op); - if (name_index < 0) - { - return NULL; - } - - place = find_main_ent (name_index); - - if (place < 0) - { - return NULL; - } - return ia64_find_matching_opcode (name, place); -} - -/* Free any resources used by ENT. */ -void -ia64_free_opcode (struct ia64_opcode *ent) -{ - free ((void *)ent->name); - free (ent); -} - -const struct ia64_dependency * -ia64_find_dependency (int index) -{ - index = DEP(index); - - if (index < 0 - || index >= (int)(sizeof(dependencies) / sizeof(dependencies[0]))) - return NULL; - - return &dependencies[index]; -} diff --git a/contrib/binutils/opcodes/ia64-opc.h b/contrib/binutils/opcodes/ia64-opc.h deleted file mode 100644 index f9476d8..0000000 --- a/contrib/binutils/opcodes/ia64-opc.h +++ /dev/null @@ -1,131 +0,0 @@ -/* ia64-opc.h -- IA-64 opcode table. - Copyright 1998, 1999, 2000 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#ifndef IA64_OPC_H -#define IA64_OPC_H - -#include "opcode/ia64.h" - -/* define a couple of abbreviations: */ - -#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37) -#define mOp bOp (-1) -#define Op(x) bOp (x), mOp - -#define FIRST IA64_OPCODE_FIRST -#define X_IN_MLX IA64_OPCODE_X_IN_MLX -#define LAST IA64_OPCODE_LAST -#define PRIV IA64_OPCODE_PRIV -#define NO_PRED IA64_OPCODE_NO_PRED -#define SLOT2 IA64_OPCODE_SLOT2 -#define PSEUDO IA64_OPCODE_PSEUDO -#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3 -#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT -#define MOD_RRBS IA64_OPCODE_MOD_RRBS -#define POSTINC IA64_OPCODE_POSTINC - -#define AR_CCV IA64_OPND_AR_CCV -#define AR_PFS IA64_OPND_AR_PFS -#define AR_CSD IA64_OPND_AR_CSD -#define C1 IA64_OPND_C1 -#define C8 IA64_OPND_C8 -#define C16 IA64_OPND_C16 -#define GR0 IA64_OPND_GR0 -#define IP IA64_OPND_IP -#define PR IA64_OPND_PR -#define PR_ROT IA64_OPND_PR_ROT -#define PSR IA64_OPND_PSR -#define PSR_L IA64_OPND_PSR_L -#define PSR_UM IA64_OPND_PSR_UM - -#define AR3 IA64_OPND_AR3 -#define B1 IA64_OPND_B1 -#define B2 IA64_OPND_B2 -#define CR3 IA64_OPND_CR3 -#define F1 IA64_OPND_F1 -#define F2 IA64_OPND_F2 -#define F3 IA64_OPND_F3 -#define F4 IA64_OPND_F4 -#define P1 IA64_OPND_P1 -#define P2 IA64_OPND_P2 -#define R1 IA64_OPND_R1 -#define R2 IA64_OPND_R2 -#define R3 IA64_OPND_R3 -#define R3_2 IA64_OPND_R3_2 - -#define CPUID_R3 IA64_OPND_CPUID_R3 -#define DBR_R3 IA64_OPND_DBR_R3 -#define DTR_R3 IA64_OPND_DTR_R3 -#define ITR_R3 IA64_OPND_ITR_R3 -#define IBR_R3 IA64_OPND_IBR_R3 -#define MR3 IA64_OPND_MR3 -#define MSR_R3 IA64_OPND_MSR_R3 -#define PKR_R3 IA64_OPND_PKR_R3 -#define PMC_R3 IA64_OPND_PMC_R3 -#define PMD_R3 IA64_OPND_PMD_R3 -#define RR_R3 IA64_OPND_RR_R3 - -#define CCNT5 IA64_OPND_CCNT5 -#define CNT2a IA64_OPND_CNT2a -#define CNT2b IA64_OPND_CNT2b -#define CNT2c IA64_OPND_CNT2c -#define CNT5 IA64_OPND_CNT5 -#define CNT6 IA64_OPND_CNT6 -#define CPOS6a IA64_OPND_CPOS6a -#define CPOS6b IA64_OPND_CPOS6b -#define CPOS6c IA64_OPND_CPOS6c -#define IMM1 IA64_OPND_IMM1 -#define IMM14 IA64_OPND_IMM14 -#define IMM17 IA64_OPND_IMM17 -#define IMM22 IA64_OPND_IMM22 -#define IMM44 IA64_OPND_IMM44 -#define SOF IA64_OPND_SOF -#define SOL IA64_OPND_SOL -#define SOR IA64_OPND_SOR -#define IMM8 IA64_OPND_IMM8 -#define IMM8U4 IA64_OPND_IMM8U4 -#define IMM8M1 IA64_OPND_IMM8M1 -#define IMM8M1U4 IA64_OPND_IMM8M1U4 -#define IMM8M1U8 IA64_OPND_IMM8M1U8 -#define IMM9a IA64_OPND_IMM9a -#define IMM9b IA64_OPND_IMM9b -#define IMMU2 IA64_OPND_IMMU2 -#define IMMU21 IA64_OPND_IMMU21 -#define IMMU24 IA64_OPND_IMMU24 -#define IMMU62 IA64_OPND_IMMU62 -#define IMMU64 IA64_OPND_IMMU64 -#define IMMU7a IA64_OPND_IMMU7a -#define IMMU7b IA64_OPND_IMMU7b -#define IMMU9 IA64_OPND_IMMU9 -#define INC3 IA64_OPND_INC3 -#define LEN4 IA64_OPND_LEN4 -#define LEN6 IA64_OPND_LEN6 -#define MBTYPE4 IA64_OPND_MBTYPE4 -#define MHTYPE8 IA64_OPND_MHTYPE8 -#define POS6 IA64_OPND_POS6 -#define TAG13 IA64_OPND_TAG13 -#define TAG13b IA64_OPND_TAG13b -#define TGT25 IA64_OPND_TGT25 -#define TGT25b IA64_OPND_TGT25b -#define TGT25c IA64_OPND_TGT25c -#define TGT64 IA64_OPND_TGT64 - -#endif diff --git a/contrib/binutils/opcodes/ia64-raw.tbl b/contrib/binutils/opcodes/ia64-raw.tbl deleted file mode 100644 index 476721c..0000000 --- a/contrib/binutils/opcodes/ia64-raw.tbl +++ /dev/null @@ -1,182 +0,0 @@ -Resource Name; Writers; Readers; Semantics of Dependency -ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none -AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi; impliedF -AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE; impliedF -AR[CFLG]; IC:mov-to-AR-CFLG; br.ia, IC:mov-from-AR-CFLG; impliedF -AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF -AR[CSD]; ld16, IC:mov-to-AR-CSD; br.ia, cmp8xchg16, IC:mov-from-AR-CSD, st16; impliedF -AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF -AR[EFLAG]; IC:mov-to-AR-EFLAG; br.ia, IC:mov-from-AR-EFLAG; impliedF -AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF -AR[FDR]; IC:mov-to-AR-FDR; br.ia, IC:mov-from-AR-FDR; impliedF -AR[FIR]; IC:mov-to-AR-FIR; br.ia, IC:mov-from-AR-FIR; impliedF -AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; br.ia, IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf0.flags; IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; br.ia, fchkf, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf1.flags; IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; br.ia, fchkf.s1, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; br.ia, fchkf.s2, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF -AR[FSR]; IC:mov-to-AR-FSR; br.ia, IC:mov-from-AR-FSR; impliedF -AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF -AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF -AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC; impliedF -AR[PFS]; br.call, brl.call; alloc, br.ia, br.ret, epc, IC:mov-from-AR-PFS; impliedF -AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF -AR[PFS]; IC:mov-to-AR-PFS; br.ret; none -AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF -AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF -AR[SSD]; IC:mov-to-AR-SSD; br.ia, IC:mov-from-AR-SSD; impliedF -AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, IC:mov-from-AR-UNAT; impliedF -AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; br.ia, IC:mov-from-AR-rv+1; none -AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; impliedF -BR%, % in 0 - 7; br.call+1, brl.call+1; IC:indirect-brs+1, IC:indirect-brp+1, IC:mov-from-BR+1; impliedF -BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brs+1; none -BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brp+1, IC:mov-from-BR+1; impliedF -CFM; IC:mod-sched-brs; IC:mod-sched-brs; impliedF -CFM; IC:mod-sched-brs; cover, alloc, rfi, loadrs, br.ret, br.call, brl.call; impliedF -CFM; IC:mod-sched-brs; IC:cfm-readers+2; impliedF -CFM; br.call, brl.call, br.ret, clrrrb, cover, rfi; IC:cfm-readers; impliedF -CFM; alloc; IC:cfm-readers; none -CPUID#; IC:none; IC:mov-from-IND-CPUID+3; specific -CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-from-CR-CMCV; data -CR[DCR]; IC:mov-to-CR-DCR; IC:mov-from-CR-DCR, IC:mem-readers-spec; data -CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 10.8.3.4 -CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-from-CR-GPTA, thash; data -CR[IFA]; IC:mov-to-CR-IFA; itc.i, itc.d, itr.i, itr.d; implied -CR[IFA]; IC:mov-to-CR-IFA; IC:mov-from-CR-IFA; data -CR[IFS]; IC:mov-to-CR-IFS; IC:mov-from-CR-IFS; data -CR[IFS]; IC:mov-to-CR-IFS; rfi; implied -CR[IFS]; cover; rfi, IC:mov-from-CR-IFS; implied -CR[IHA]; IC:mov-to-CR-IHA; IC:mov-from-CR-IHA; data -CR[IIM]; IC:mov-to-CR-IIM; IC:mov-from-CR-IIM; data -CR[IIP]; IC:mov-to-CR-IIP; IC:mov-from-CR-IIP; data -CR[IIP]; IC:mov-to-CR-IIP; rfi; implied -CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-from-CR-IIPA; data -CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-from-CR-IPSR; data -CR[IPSR]; IC:mov-to-CR-IPSR; rfi; implied -CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IRR+1; data -CR[ISR]; IC:mov-to-CR-ISR; IC:mov-from-CR-ISR; data -CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-from-CR-ITIR; data -CR[ITIR]; IC:mov-to-CR-ITIR; itc.i, itc.d, itr.i, itr.d; implied -CR[ITM]; IC:mov-to-CR-ITM; IC:mov-from-CR-ITM; data -CR[ITV]; IC:mov-to-CR-ITV; IC:mov-from-CR-ITV; data -CR[IVA]; IC:mov-to-CR-IVA; IC:mov-from-CR-IVA; instr -CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 10.8.3.2 -CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 10.8.3.1 -CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-from-CR-LRR+1; data -CR[PMV]; IC:mov-to-CR-PMV; IC:mov-from-CR-PMV; data -CR[PTA]; IC:mov-to-CR-PTA; IC:mov-from-CR-PTA, thash; data -CR[TPR]; IC:mov-to-CR-TPR; IC:mov-from-CR-TPR, IC:mov-from-CR-IVR; data -CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l, rfi, rsm, ssm; SC Section 10.8.3.3 -CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:mov-from-CR-rv+1; none -DBR#; IC:mov-to-IND-DBR+3; IC:mov-from-IND-DBR+3; impliedF -DBR#; IC:mov-to-IND-DBR+3; IC:probe-all, IC:lfetch-all, IC:mem-readers, IC:mem-writers; data -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data -DTC; itc.i, itc.d, itr.i, itr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; impliedF -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF -DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF -DTR; itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data -DTR; itr.d; ptc.g, ptc.ga, ptc.l, ptr.d, itr.d; impliedF -DTR; ptr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data -DTR; ptr.d; ptc.g, ptc.ga, ptc.l, ptr.d; none -DTR; ptr.d; itr.d, itc.d; impliedF -FR%, % in 0 - 1; IC:none; IC:fr-readers+1; none -FR%, % in 2 - 127; IC:fr-writers+1\IC:ldf-c+1\IC:ldfp-c+1; IC:fr-readers+1; impliedF -FR%, % in 2 - 127; IC:ldf-c+1, IC:ldfp-c+1; IC:fr-readers+1; none -GR0; IC:none; IC:gr-readers+1; none -GR%, % in 1 - 127; IC:ld-c+1+13; IC:gr-readers+1; none -GR%, % in 1 - 127; IC:gr-writers+1\IC:ld-c+1+13; IC:gr-readers+1; impliedF -IBR#; IC:mov-to-IND-IBR+3; IC:mov-from-IND-IBR+3; impliedF -InService*; IC:mov-to-CR-EOI; IC:mov-from-CR-IVR; data -InService*; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF -InService*; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; impliedF -IP; IC:all; IC:all; none -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; epc; instr -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptr.i, ptr.d, ptc.e, ptc.g, ptc.ga, ptc.l; none -ITC; itc.i, itc.d, itr.i, itr.d; epc; instr -ITC; itc.i, itc.d, itr.i, itr.d; itc.d, itc.i, itr.d, itr.i, ptr.d, ptr.i, ptc.g, ptc.ga, ptc.l; impliedF -ITC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF -ITR; itr.i; itr.i, itc.i, ptc.g, ptc.ga, ptc.l, ptr.i; impliedF -ITR; itr.i; epc; instr -ITR; ptr.i; itc.i, itr.i; impliedF -ITR; ptr.i; ptc.g, ptc.ga, ptc.l, ptr.i; none -ITR; ptr.i; epc; instr -memory; IC:mem-writers; IC:mem-readers; none -MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific -PKR#; IC:mov-to-IND-PKR+3; IC:mem-readers, IC:mem-writers, IC:mov-from-IND-PKR+4, IC:probe-all; data -PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none -PKR#; IC:mov-to-IND-PKR+3; IC:mov-from-IND-PKR+3; impliedF -PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF -PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMC+3; impliedF -PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC+3 Section 12.1.1 -PMD#; IC:mov-to-IND-PMD+3; IC:mov-from-IND-PMD+3; impliedF -PR0; IC:pr-writers+1; IC:pr-readers-br+1, IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR+12, IC:mov-to-PR+12; none -PR%, % in 1 - 15; IC:pr-writers+1, IC:mov-to-PR-allreg+7; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF -PR%, % in 1 - 15; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF -PR%, % in 1 - 15; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7; IC:pr-readers-br+1; none -PR%, % in 16 - 62; IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF -PR%, % in 16 - 62; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF -PR%, % in 16 - 62; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none -PR63; IC:mod-sched-brs, IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF -PR63; IC:pr-writers-fp+1, IC:mod-sched-brs; IC:pr-readers-br+1; impliedF -PR63; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none -PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied -PSR.ac; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data -PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF -PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied -PSR.be; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data -PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF -PSR.bn; bsw, rfi; IC:gr-readers+10, IC:gr-writers+10; impliedF -PSR.cpl; epc, br.ret, rfi; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-writers, IC:lfetch-all; implied -PSR.da; rfi; IC:mem-readers, IC:lfetch-fault, IC:mem-writers, IC:probe-fault; data -PSR.db; IC:mov-to-PSR-l; IC:mem-readers, IC:mem-writers, IC:probe-fault; data -PSR.db; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF -PSR.db; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:probe-fault; data -PSR.dd; rfi; IC:mem-readers, IC:probe-fault, IC:mem-writers, IC:lfetch-fault; data -PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-readers+8, IC:fr-writers+8; data -PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-writers+8, IC:fr-readers+8; data -PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; br.ia; data -PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data -PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.ed; rfi; IC:lfetch-all, IC:mem-readers-spec; data -PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF -PSR.i; rfi; IC:mov-from-PSR; data -PSR.ia; rfi; IC:none; none -PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; cover, itc.i, itc.d, itr.i, itr.d, IC:mov-from-CR-ITIR, IC:mov-from-CR-IFS, IC:mov-from-CR-IIM, IC:mov-from-CR-IIP, IC:mov-from-CR-IPSR, IC:mov-from-CR-ISR, IC:mov-from-CR-IFA, IC:mov-from-CR-IHA, IC:mov-from-CR-IIPA, IC:mov-to-CR-ITIR, IC:mov-to-CR-IFS, IC:mov-to-CR-IIM, IC:mov-to-CR-IIP, IC:mov-to-CR-IPSR, IC:mov-to-CR-ISR, IC:mov-to-CR-IFA, IC:mov-to-CR-IHA, IC:mov-to-CR-IIPA; data -PSR.id; rfi; IC:none; none -PSR.is; br.ia, rfi; IC:none; none -PSR.it; rfi; IC:branches, IC:mov-from-PSR, chk, epc, fchkf; data -PSR.lp; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF -PSR.lp; IC:mov-to-PSR-l; br.ret; data -PSR.lp; rfi; IC:mov-from-PSR, br.ret; data -PSR.mc; rfi; IC:mov-from-PSR; none -PSR.mfh; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF -PSR.mfl; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF -PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers, IC:probe-all; data -PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.ri; rfi; IC:none; none -PSR.rt; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF -PSR.rt; IC:mov-to-PSR-l; alloc, flushrs, loadrs; data -PSR.rt; rfi; IC:mov-from-PSR, alloc, flushrs, loadrs; data -PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-AR-ITC; data -PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-IND-PMD, IC:mov-to-PSR-um, rum, sum; data -PSR.ss; rfi; IC:all; data -PSR.tb; IC:mov-to-PSR-l, rfi; IC:branches, chk, fchkf; data -PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF -PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF -RR#; IC:mov-to-IND-RR+6; IC:mem-readers, IC:mem-writers, itc.i, itc.d, itr.i, itr.d, IC:probe-all, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, tak, thash, tpa, ttag; data -RR#; IC:mov-to-IND-RR+6; IC:mov-from-IND-RR+6; impliedF -RSE; IC:rse-writers+14; IC:rse-readers+14; impliedF diff --git a/contrib/binutils/opcodes/ia64-war.tbl b/contrib/binutils/opcodes/ia64-war.tbl deleted file mode 100644 index 8cdfac5..0000000 --- a/contrib/binutils/opcodes/ia64-war.tbl +++ /dev/null @@ -1,2 +0,0 @@ -Resource Name; Readers; Writers; Semantics of Dependency -PR63; IC:pr-readers-br+1; IC:mod-sched-brs; stop diff --git a/contrib/binutils/opcodes/ia64-waw.tbl b/contrib/binutils/opcodes/ia64-waw.tbl deleted file mode 100644 index 98daebf..0000000 --- a/contrib/binutils/opcodes/ia64-waw.tbl +++ /dev/null @@ -1,135 +0,0 @@ -Resource Name; Writers; Writers; Semantics of Dependency -ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; none -AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF -AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF -AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF -AR[CFLG]; IC:mov-to-AR-CFLG; IC:mov-to-AR-CFLG; impliedF -AR[CSD]; ld16, IC:mov-to-AR-CSD; ld16, IC:mov-to-AR-CSD; impliedF -AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF -AR[EFLAG]; mov-to-AR-EFLAG; mov-to-AR-EFLAG; impliedF -AR[FCR]; mov-to-AR-FCR; mov-to-AR-FCR; impliedF -AR[FDR]; mov-to-AR-FDR; mov-to-AR-FDR; impliedF -AR[FIR]; mov-to-AR-FIR; mov-to-AR-FIR; impliedF -AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF -AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF -AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF -AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; IC:mov-to-AR-FPSR, fsetc.s3; impliedF -AR[FPSR].sf0.flags; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; none -AR[FPSR].sf0.flags; fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; fclrf.s0, IC:mov-to-AR-FPSR; impliedF -AR[FPSR].sf1.flags; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; none -AR[FPSR].sf1.flags; fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; fclrf.s1, IC:mov-to-AR-FPSR; impliedF -AR[FPSR].sf2.flags; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; none -AR[FPSR].sf2.flags; fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; fclrf.s2, IC:mov-to-AR-FPSR; impliedF -AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; none -AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF -AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF -AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF -AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF -AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF -AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF -AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF -AR[PFS]; br.call, brl.call; br.call, brl.call; none -AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF -AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF -AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF -AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT, st8.spill; impliedF -AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; IC:none; none -AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF -BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF -BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF -BR%, % in 0 - 7; br.call+1, brl.call+1; br.call+1, brl.call+1; none -CFM; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; impliedF -CPUID#; IC:none; IC:none; none -CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-to-CR-CMCV; impliedF -CR[DCR]; IC:mov-to-CR-DCR; IC:mov-to-CR-DCR; impliedF -CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 10.8.3.4 -CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-to-CR-GPTA; impliedF -CR[IFA]; IC:mov-to-CR-IFA; IC:mov-to-CR-IFA; impliedF -CR[IFS]; IC:mov-to-CR-IFS, cover; IC:mov-to-CR-IFS, cover; impliedF -CR[IHA]; IC:mov-to-CR-IHA; IC:mov-to-CR-IHA; impliedF -CR[IIM]; IC:mov-to-CR-IIM; IC:mov-to-CR-IIM; impliedF -CR[IIP]; IC:mov-to-CR-IIP; IC:mov-to-CR-IIP; impliedF -CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-to-CR-IIPA; impliedF -CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-to-CR-IPSR; impliedF -CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF -CR[ISR]; IC:mov-to-CR-ISR; IC:mov-to-CR-ISR; impliedF -CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-to-CR-ITIR; impliedF -CR[ITM]; IC:mov-to-CR-ITM; IC:mov-to-CR-ITM; impliedF -CR[ITV]; IC:mov-to-CR-ITV; IC:mov-to-CR-ITV; impliedF -CR[IVA]; IC:mov-to-CR-IVA; IC:mov-to-CR-IVA; impliedF -CR[IVR]; IC:none; IC:none; SC -CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC -CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-to-CR-LRR+1; impliedF -CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF -CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF -CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF -CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:none; none -DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF -DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF -DTR; itr.d; itr.d; impliedF -DTR; itr.d; ptr.d; impliedF -DTR; ptr.d; ptr.d; none -FR%, % in 0 - 1; IC:none; IC:none; none -FR%, % in 2 - 127; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; impliedF -GR0; IC:none; IC:none; none -GR%, % in 1 - 127; IC:ld-c+1, IC:gr-writers+1; IC:ld-c+1, IC:gr-writers+1; impliedF -IBR#; IC:mov-to-IND-IBR+3; IC:mov-to-IND-IBR+3; impliedF -InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC -IP; IC:all; IC:all; none -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF -ITR; itr.i; itr.i, ptr.i; impliedF -ITR; ptr.i; ptr.i; none -memory; IC:mem-writers; IC:mem-writers; none -MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC -PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none -PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF -PMC#; IC:mov-to-IND-PMC+3; IC:mov-to-IND-PMC+3; impliedF -PMD#; IC:mov-to-IND-PMD+3; IC:mov-to-IND-PMD+3; impliedF -PR0; IC:pr-writers+1; IC:pr-writers+1; none -PR%, % in 1 - 15; IC:pr-and-writers+1; IC:pr-and-writers+1; none -PR%, % in 1 - 15; IC:pr-or-writers+1; IC:pr-or-writers+1; none -PR%, % in 1 - 15; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7; impliedF -PR%, % in 16 - 62; IC:pr-and-writers+1; IC:pr-and-writers+1; none -PR%, % in 16 - 62; IC:pr-or-writers+1; IC:pr-or-writers+1; none -PR%, % in 16 - 62; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF -PR63; IC:pr-and-writers+1; IC:pr-and-writers+1; none -PR63; IC:pr-or-writers+1; IC:pr-or-writers+1; none -PR63; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF -PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.bn; bsw, rfi; bsw, rfi; impliedF -PSR.cpl; epc, br.ret, rfi; epc, br.ret, rfi; impliedF -PSR.da; rfi; rfi; impliedF -PSR.db; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF -PSR.dd; rfi; rfi; impliedF -PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.ed; rfi; rfi; impliedF -PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.ia; rfi; rfi; impliedF -PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.id; rfi; rfi; impliedF -PSR.is; br.ia, rfi; br.ia, rfi; impliedF -PSR.it; rfi; rfi; impliedF -PSR.lp; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF -PSR.mc; rfi; rfi; impliedF -PSR.mfh; IC:fr-writers+9; IC:fr-writers+9; none -PSR.mfh; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.mfl; IC:fr-writers+9; IC:fr-writers+9; none -PSR.mfl; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.ri; rfi; rfi; impliedF -PSR.rt; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF -PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.ss; rfi; rfi; impliedF -PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF -PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -RR#; IC:mov-to-IND-RR+6; IC:mov-to-IND-RR+6; impliedF -RSE; IC:rse-writers+14; IC:rse-writers+14; impliedF diff --git a/contrib/binutils/opcodes/mips-dis.c b/contrib/binutils/opcodes/mips-dis.c deleted file mode 100644 index 43fcb3c..0000000 --- a/contrib/binutils/opcodes/mips-dis.c +++ /dev/null @@ -1,1835 +0,0 @@ -/* Print mips instructions for GDB, the GNU debugger, or for objdump. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003 - Free Software Foundation, Inc. - Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). - -This file is part of GDB, GAS, and the GNU binutils. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" -#include "libiberty.h" -#include "opcode/mips.h" -#include "opintl.h" - -/* FIXME: These are needed to figure out if the code is mips16 or - not. The low bit of the address is often a good indicator. No - symbol table is available when this code runs out in an embedded - system as when it is used for disassembler support in a monitor. */ - -#if !defined(EMBEDDED_ENV) -#define SYMTAB_AVAILABLE 1 -#include "elf-bfd.h" -#include "elf/mips.h" -#endif - -/* Mips instructions are at maximum this many bytes long. */ -#define INSNLEN 4 - -static void set_default_mips_dis_options - PARAMS ((struct disassemble_info *)); -static void parse_mips_dis_option - PARAMS ((const char *, unsigned int)); -static void parse_mips_dis_options - PARAMS ((const char *)); -static int _print_insn_mips - PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian)); -static int print_insn_mips - PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *)); -static void print_insn_args - PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *)); -static int print_insn_mips16 - PARAMS ((bfd_vma, struct disassemble_info *)); -static int is_newabi - PARAMS ((Elf_Internal_Ehdr *)); -static void print_mips16_insn_arg - PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma, - struct disassemble_info *)); - -/* FIXME: These should be shared with gdb somehow. */ - -struct mips_cp0sel_name { - unsigned int cp0reg; - unsigned int sel; - const char * const name; -}; - -/* The mips16 register names. */ -static const char * const mips16_reg_names[] = { - "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" -}; - -static const char * const mips_gpr_names_numeric[32] = { - "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", - "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", - "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", - "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" -}; - -static const char * const mips_gpr_names_oldabi[32] = { - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" -}; - -static const char * const mips_gpr_names_newabi[32] = { - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" -}; - -static const char * const mips_fpr_names_numeric[32] = { - "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", - "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", - "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", - "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" -}; - -static const char * const mips_fpr_names_32[32] = { - "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", - "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", - "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", - "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" -}; - -static const char * const mips_fpr_names_n32[32] = { - "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", - "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", - "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", - "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" -}; - -static const char * const mips_fpr_names_64[32] = { - "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", - "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", - "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", - "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" -}; - -static const char * const mips_cp0_names_numeric[32] = { - "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", - "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", - "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", - "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" -}; - -static const char * const mips_cp0_names_mips3264[32] = { - "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", - "c0_context", "c0_pagemask", "c0_wired", "$7", - "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", - "c0_status", "c0_cause", "c0_epc", "c0_prid", - "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", - "c0_xcontext", "$21", "$22", "c0_debug", - "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", - "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", -}; - -static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = { - { 16, 1, "c0_config1" }, - { 16, 2, "c0_config2" }, - { 16, 3, "c0_config3" }, - { 18, 1, "c0_watchlo,1" }, - { 18, 2, "c0_watchlo,2" }, - { 18, 3, "c0_watchlo,3" }, - { 18, 4, "c0_watchlo,4" }, - { 18, 5, "c0_watchlo,5" }, - { 18, 6, "c0_watchlo,6" }, - { 18, 7, "c0_watchlo,7" }, - { 19, 1, "c0_watchhi,1" }, - { 19, 2, "c0_watchhi,2" }, - { 19, 3, "c0_watchhi,3" }, - { 19, 4, "c0_watchhi,4" }, - { 19, 5, "c0_watchhi,5" }, - { 19, 6, "c0_watchhi,6" }, - { 19, 7, "c0_watchhi,7" }, - { 25, 1, "c0_perfcnt,1" }, - { 25, 2, "c0_perfcnt,2" }, - { 25, 3, "c0_perfcnt,3" }, - { 25, 4, "c0_perfcnt,4" }, - { 25, 5, "c0_perfcnt,5" }, - { 25, 6, "c0_perfcnt,6" }, - { 25, 7, "c0_perfcnt,7" }, - { 27, 1, "c0_cacheerr,1" }, - { 27, 2, "c0_cacheerr,2" }, - { 27, 3, "c0_cacheerr,3" }, - { 28, 1, "c0_datalo" }, - { 29, 1, "c0_datahi" } -}; - -static const char * const mips_cp0_names_mips3264r2[32] = { - "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", - "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", - "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", - "c0_status", "c0_cause", "c0_epc", "c0_prid", - "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", - "c0_xcontext", "$21", "$22", "c0_debug", - "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", - "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", -}; - -static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = { - { 4, 1, "c0_contextconfig" }, - { 5, 1, "c0_pagegrain" }, - { 12, 1, "c0_intctl" }, - { 12, 2, "c0_srsctl" }, - { 12, 3, "c0_srsmap" }, - { 15, 1, "c0_ebase" }, - { 16, 1, "c0_config1" }, - { 16, 2, "c0_config2" }, - { 16, 3, "c0_config3" }, - { 18, 1, "c0_watchlo,1" }, - { 18, 2, "c0_watchlo,2" }, - { 18, 3, "c0_watchlo,3" }, - { 18, 4, "c0_watchlo,4" }, - { 18, 5, "c0_watchlo,5" }, - { 18, 6, "c0_watchlo,6" }, - { 18, 7, "c0_watchlo,7" }, - { 19, 1, "c0_watchhi,1" }, - { 19, 2, "c0_watchhi,2" }, - { 19, 3, "c0_watchhi,3" }, - { 19, 4, "c0_watchhi,4" }, - { 19, 5, "c0_watchhi,5" }, - { 19, 6, "c0_watchhi,6" }, - { 19, 7, "c0_watchhi,7" }, - { 23, 1, "c0_tracecontrol" }, - { 23, 2, "c0_tracecontrol2" }, - { 23, 3, "c0_usertracedata" }, - { 23, 4, "c0_tracebpc" }, - { 25, 1, "c0_perfcnt,1" }, - { 25, 2, "c0_perfcnt,2" }, - { 25, 3, "c0_perfcnt,3" }, - { 25, 4, "c0_perfcnt,4" }, - { 25, 5, "c0_perfcnt,5" }, - { 25, 6, "c0_perfcnt,6" }, - { 25, 7, "c0_perfcnt,7" }, - { 27, 1, "c0_cacheerr,1" }, - { 27, 2, "c0_cacheerr,2" }, - { 27, 3, "c0_cacheerr,3" }, - { 28, 1, "c0_datalo" }, - { 28, 2, "c0_taglo1" }, - { 28, 3, "c0_datalo1" }, - { 28, 4, "c0_taglo2" }, - { 28, 5, "c0_datalo2" }, - { 28, 6, "c0_taglo3" }, - { 28, 7, "c0_datalo3" }, - { 29, 1, "c0_datahi" }, - { 29, 2, "c0_taghi1" }, - { 29, 3, "c0_datahi1" }, - { 29, 4, "c0_taghi2" }, - { 29, 5, "c0_datahi2" }, - { 29, 6, "c0_taghi3" }, - { 29, 7, "c0_datahi3" }, -}; - -/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ -static const char * const mips_cp0_names_sb1[32] = { - "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", - "c0_context", "c0_pagemask", "c0_wired", "$7", - "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", - "c0_status", "c0_cause", "c0_epc", "c0_prid", - "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", - "c0_xcontext", "$21", "$22", "c0_debug", - "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", - "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", -}; - -static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = { - { 16, 1, "c0_config1" }, - { 18, 1, "c0_watchlo,1" }, - { 19, 1, "c0_watchhi,1" }, - { 22, 0, "c0_perftrace" }, - { 23, 3, "c0_edebug" }, - { 25, 1, "c0_perfcnt,1" }, - { 25, 2, "c0_perfcnt,2" }, - { 25, 3, "c0_perfcnt,3" }, - { 25, 4, "c0_perfcnt,4" }, - { 25, 5, "c0_perfcnt,5" }, - { 25, 6, "c0_perfcnt,6" }, - { 25, 7, "c0_perfcnt,7" }, - { 26, 1, "c0_buserr_pa" }, - { 27, 1, "c0_cacheerr_d" }, - { 27, 3, "c0_cacheerr_d_pa" }, - { 28, 1, "c0_datalo_i" }, - { 28, 2, "c0_taglo_d" }, - { 28, 3, "c0_datalo_d" }, - { 29, 1, "c0_datahi_i" }, - { 29, 2, "c0_taghi_d" }, - { 29, 3, "c0_datahi_d" }, -}; - -static const char * const mips_hwr_names_numeric[32] = { - "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", - "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", - "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", - "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" -}; - -static const char * const mips_hwr_names_mips3264r2[32] = { - "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", - "$4", "$5", "$6", "$7", - "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", - "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", - "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" -}; - -struct mips_abi_choice { - const char *name; - const char * const *gpr_names; - const char * const *fpr_names; -}; - -struct mips_abi_choice mips_abi_choices[] = { - { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, - { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, - { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, - { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, -}; - -struct mips_arch_choice { - const char *name; - int bfd_mach_valid; - unsigned long bfd_mach; - int processor; - int isa; - const char * const *cp0_names; - const struct mips_cp0sel_name *cp0sel_names; - unsigned int cp0sel_names_len; - const char * const *hwr_names; -}; - -const struct mips_arch_choice mips_arch_choices[] = { - { "numeric", 0, 0, 0, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - - { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, - - /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. - Note that MIPS-3D and MDMX are not applicable to MIPS32. (See - _MIPS32 Architecture For Programmers Volume I: Introduction to the - MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), - page 1. */ - { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, - ISA_MIPS32 | INSN_MIPS16, - mips_cp0_names_mips3264, - mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), - mips_hwr_names_numeric }, - - { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, - ISA_MIPS32R2 | INSN_MIPS16, - mips_cp0_names_mips3264r2, - mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), - mips_hwr_names_mips3264r2 }, - - /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ - { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, - ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, - mips_cp0_names_mips3264, - mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), - mips_hwr_names_numeric }, - - { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, - ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, - mips_cp0_names_mips3264r2, - mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), - mips_hwr_names_mips3264r2 }, - - { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, - ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, - mips_cp0_names_sb1, - mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), - mips_hwr_names_numeric }, - - /* This entry, mips16, is here only for ISA/processor selection; do - not print its name. */ - { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, -}; - -/* ISA and processor type to disassemble for, and register names to use. - set_default_mips_dis_options and parse_mips_dis_options fill in these - values. */ -static int mips_processor; -static int mips_isa; -static const char * const *mips_gpr_names; -static const char * const *mips_fpr_names; -static const char * const *mips_cp0_names; -static const struct mips_cp0sel_name *mips_cp0sel_names; -static int mips_cp0sel_names_len; -static const char * const *mips_hwr_names; - -static const struct mips_abi_choice *choose_abi_by_name - PARAMS ((const char *, unsigned int)); -static const struct mips_arch_choice *choose_arch_by_name - PARAMS ((const char *, unsigned int)); -static const struct mips_arch_choice *choose_arch_by_number - PARAMS ((unsigned long)); -static const struct mips_cp0sel_name *lookup_mips_cp0sel_name - PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int, - unsigned int)); - -static const struct mips_abi_choice * -choose_abi_by_name (name, namelen) - const char *name; - unsigned int namelen; -{ - const struct mips_abi_choice *c; - unsigned int i; - - for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) - { - if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 - && strlen (mips_abi_choices[i].name) == namelen) - c = &mips_abi_choices[i]; - } - return c; -} - -static const struct mips_arch_choice * -choose_arch_by_name (name, namelen) - const char *name; - unsigned int namelen; -{ - const struct mips_arch_choice *c = NULL; - unsigned int i; - - for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) - { - if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 - && strlen (mips_arch_choices[i].name) == namelen) - c = &mips_arch_choices[i]; - } - return c; -} - -static const struct mips_arch_choice * -choose_arch_by_number (mach) - unsigned long mach; -{ - static unsigned long hint_bfd_mach; - static const struct mips_arch_choice *hint_arch_choice; - const struct mips_arch_choice *c; - unsigned int i; - - /* We optimize this because even if the user specifies no - flags, this will be done for every instruction! */ - if (hint_bfd_mach == mach - && hint_arch_choice != NULL - && hint_arch_choice->bfd_mach == hint_bfd_mach) - return hint_arch_choice; - - for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) - { - if (mips_arch_choices[i].bfd_mach_valid - && mips_arch_choices[i].bfd_mach == mach) - { - c = &mips_arch_choices[i]; - hint_bfd_mach = mach; - hint_arch_choice = c; - } - } - return c; -} - -void -set_default_mips_dis_options (info) - struct disassemble_info *info; -{ - const struct mips_arch_choice *chosen_arch; - - /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, - and numeric FPR, CP0 register, and HWR names. */ - mips_isa = ISA_MIPS3; - mips_processor = CPU_R3000; - mips_gpr_names = mips_gpr_names_oldabi; - mips_fpr_names = mips_fpr_names_numeric; - mips_cp0_names = mips_cp0_names_numeric; - mips_cp0sel_names = NULL; - mips_cp0sel_names_len = 0; - mips_hwr_names = mips_hwr_names_numeric; - - /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ - if (info->flavour == bfd_target_elf_flavour && info->section != NULL) - { - Elf_Internal_Ehdr *header; - - header = elf_elfheader (info->section->owner); - if (is_newabi (header)) - mips_gpr_names = mips_gpr_names_newabi; - } - - /* Set ISA, architecture, and cp0 register names as best we can. */ -#if ! SYMTAB_AVAILABLE - /* This is running out on a target machine, not in a host tool. - FIXME: Where does mips_target_info come from? */ - target_processor = mips_target_info.processor; - mips_isa = mips_target_info.isa; -#else - chosen_arch = choose_arch_by_number (info->mach); - if (chosen_arch != NULL) - { - mips_processor = chosen_arch->processor; - mips_isa = chosen_arch->isa; - mips_cp0_names = chosen_arch->cp0_names; - mips_cp0sel_names = chosen_arch->cp0sel_names; - mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; - mips_hwr_names = chosen_arch->hwr_names; - } -#endif -} - -void -parse_mips_dis_option (option, len) - const char *option; - unsigned int len; -{ - unsigned int i, optionlen, vallen; - const char *val; - const struct mips_abi_choice *chosen_abi; - const struct mips_arch_choice *chosen_arch; - - /* Look for the = that delimits the end of the option name. */ - for (i = 0; i < len; i++) - { - if (option[i] == '=') - break; - } - if (i == 0) /* Invalid option: no name before '='. */ - return; - if (i == len) /* Invalid option: no '='. */ - return; - if (i == (len - 1)) /* Invalid option: no value after '='. */ - return; - - optionlen = i; - val = option + (optionlen + 1); - vallen = len - (optionlen + 1); - - if (strncmp("gpr-names", option, optionlen) == 0 - && strlen("gpr-names") == optionlen) - { - chosen_abi = choose_abi_by_name (val, vallen); - if (chosen_abi != NULL) - mips_gpr_names = chosen_abi->gpr_names; - return; - } - - if (strncmp("fpr-names", option, optionlen) == 0 - && strlen("fpr-names") == optionlen) - { - chosen_abi = choose_abi_by_name (val, vallen); - if (chosen_abi != NULL) - mips_fpr_names = chosen_abi->fpr_names; - return; - } - - if (strncmp("cp0-names", option, optionlen) == 0 - && strlen("cp0-names") == optionlen) - { - chosen_arch = choose_arch_by_name (val, vallen); - if (chosen_arch != NULL) - { - mips_cp0_names = chosen_arch->cp0_names; - mips_cp0sel_names = chosen_arch->cp0sel_names; - mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; - } - return; - } - - if (strncmp("hwr-names", option, optionlen) == 0 - && strlen("hwr-names") == optionlen) - { - chosen_arch = choose_arch_by_name (val, vallen); - if (chosen_arch != NULL) - mips_hwr_names = chosen_arch->hwr_names; - return; - } - - if (strncmp("reg-names", option, optionlen) == 0 - && strlen("reg-names") == optionlen) - { - /* We check both ABI and ARCH here unconditionally, so - that "numeric" will do the desirable thing: select - numeric register names for all registers. Other than - that, a given name probably won't match both. */ - chosen_abi = choose_abi_by_name (val, vallen); - if (chosen_abi != NULL) - { - mips_gpr_names = chosen_abi->gpr_names; - mips_fpr_names = chosen_abi->fpr_names; - } - chosen_arch = choose_arch_by_name (val, vallen); - if (chosen_arch != NULL) - { - mips_cp0_names = chosen_arch->cp0_names; - mips_cp0sel_names = chosen_arch->cp0sel_names; - mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; - mips_hwr_names = chosen_arch->hwr_names; - } - return; - } - - /* Invalid option. */ -} - -void -parse_mips_dis_options (options) - const char *options; -{ - const char *option_end; - - if (options == NULL) - return; - - while (*options != '\0') - { - /* Skip empty options. */ - if (*options == ',') - { - options++; - continue; - } - - /* We know that *options is neither NUL or a comma. */ - option_end = options + 1; - while (*option_end != ',' && *option_end != '\0') - option_end++; - - parse_mips_dis_option (options, option_end - options); - - /* Go on to the next one. If option_end points to a comma, it - will be skipped above. */ - options = option_end; - } -} - -static const struct mips_cp0sel_name * -lookup_mips_cp0sel_name(names, len, cp0reg, sel) - const struct mips_cp0sel_name *names; - unsigned int len, cp0reg, sel; -{ - unsigned int i; - - for (i = 0; i < len; i++) - if (names[i].cp0reg == cp0reg && names[i].sel == sel) - return &names[i]; - return NULL; -} - -/* Print insn arguments for 32/64-bit code. */ - -static void -print_insn_args (d, l, pc, info) - const char *d; - register unsigned long int l; - bfd_vma pc; - struct disassemble_info *info; -{ - int op, delta; - unsigned int lsb, msb, msbd; - - lsb = 0; - - for (; *d != '\0'; d++) - { - switch (*d) - { - case ',': - case '(': - case ')': - case '[': - case ']': - (*info->fprintf_func) (info->stream, "%c", *d); - break; - - case '+': - /* Extension character; switch for second char. */ - d++; - switch (*d) - { - case '\0': - /* xgettext:c-format */ - (*info->fprintf_func) (info->stream, - _("# internal error, incomplete extension sequence (+)")); - return; - - case 'A': - lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; - (*info->fprintf_func) (info->stream, "0x%x", lsb); - break; - - case 'B': - msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; - (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); - break; - - case 'C': - case 'H': - msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; - (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); - break; - - case 'D': - { - const struct mips_cp0sel_name *n; - unsigned int cp0reg, sel; - - cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; - sel = (l >> OP_SH_SEL) & OP_MASK_SEL; - - /* CP0 register including 'sel' code for mtcN (et al.), to be - printed textually if known. If not known, print both - CP0 register name and sel numerically since CP0 register - with sel 0 may have a name unrelated to register being - printed. */ - n = lookup_mips_cp0sel_name(mips_cp0sel_names, - mips_cp0sel_names_len, cp0reg, sel); - if (n != NULL) - (*info->fprintf_func) (info->stream, "%s", n->name); - else - (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); - break; - } - - case 'E': - lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; - (*info->fprintf_func) (info->stream, "0x%x", lsb); - break; - - case 'F': - msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; - (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); - break; - - case 'G': - msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; - (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); - break; - - default: - /* xgettext:c-format */ - (*info->fprintf_func) (info->stream, - _("# internal error, undefined extension sequence (+%c)"), - *d); - return; - } - break; - - case 's': - case 'b': - case 'r': - case 'v': - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); - break; - - case 't': - case 'w': - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); - break; - - case 'i': - case 'u': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); - break; - - case 'j': /* Same as i, but sign-extended. */ - case 'o': - delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; - if (delta & 0x8000) - delta |= ~0xffff; - (*info->fprintf_func) (info->stream, "%d", - delta); - break; - - case 'h': - (*info->fprintf_func) (info->stream, "0x%x", - (unsigned int) ((l >> OP_SH_PREFX) - & OP_MASK_PREFX)); - break; - - case 'k': - (*info->fprintf_func) (info->stream, "0x%x", - (unsigned int) ((l >> OP_SH_CACHE) - & OP_MASK_CACHE)); - break; - - case 'a': - info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) - | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); - (*info->print_address_func) (info->target, info); - break; - - case 'p': - /* Sign extend the displacement. */ - delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; - if (delta & 0x8000) - delta |= ~0xffff; - info->target = (delta << 2) + pc + INSNLEN; - (*info->print_address_func) (info->target, info); - break; - - case 'd': - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); - break; - - case 'U': - { - /* First check for both rd and rt being equal. */ - unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; - if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[reg]); - else - { - /* If one is zero use the other. */ - if (reg == 0) - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); - else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[reg]); - else /* Bogus, result depends on processor. */ - (*info->fprintf_func) (info->stream, "%s or %s", - mips_gpr_names[reg], - mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); - } - } - break; - - case 'z': - (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); - break; - - case '<': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); - break; - - case 'c': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_CODE) & OP_MASK_CODE); - break; - - case 'q': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_CODE2) & OP_MASK_CODE2); - break; - - case 'C': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_COPZ) & OP_MASK_COPZ); - break; - - case 'B': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_CODE20) & OP_MASK_CODE20); - break; - - case 'J': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_CODE19) & OP_MASK_CODE19); - break; - - case 'S': - case 'V': - (*info->fprintf_func) (info->stream, "%s", - mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); - break; - - case 'T': - case 'W': - (*info->fprintf_func) (info->stream, "%s", - mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); - break; - - case 'D': - (*info->fprintf_func) (info->stream, "%s", - mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); - break; - - case 'R': - (*info->fprintf_func) (info->stream, "%s", - mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); - break; - - case 'E': - /* Coprocessor register for lwcN instructions, et al. - - Note that there is no load/store cp0 instructions, and - that FPU (cp1) instructions disassemble this field using - 'T' format. Therefore, until we gain understanding of - cp2 register names, we can simply print the register - numbers. */ - (*info->fprintf_func) (info->stream, "$%d", - (l >> OP_SH_RT) & OP_MASK_RT); - break; - - case 'G': - /* Coprocessor register for mtcN instructions, et al. Note - that FPU (cp1) instructions disassemble this field using - 'S' format. Therefore, we only need to worry about cp0, - cp2, and cp3. */ - op = (l >> OP_SH_OP) & OP_MASK_OP; - if (op == OP_OP_COP0) - (*info->fprintf_func) (info->stream, "%s", - mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); - else - (*info->fprintf_func) (info->stream, "$%d", - (l >> OP_SH_RD) & OP_MASK_RD); - break; - - case 'K': - (*info->fprintf_func) (info->stream, "%s", - mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); - break; - - case 'N': - (*info->fprintf_func) (info->stream, "$fcc%d", - (l >> OP_SH_BCC) & OP_MASK_BCC); - break; - - case 'M': - (*info->fprintf_func) (info->stream, "$fcc%d", - (l >> OP_SH_CCC) & OP_MASK_CCC); - break; - - case 'P': - (*info->fprintf_func) (info->stream, "%d", - (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); - break; - - case 'e': - (*info->fprintf_func) (info->stream, "%d", - (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); - break; - - case '%': - (*info->fprintf_func) (info->stream, "%d", - (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); - break; - - case 'H': - (*info->fprintf_func) (info->stream, "%d", - (l >> OP_SH_SEL) & OP_MASK_SEL); - break; - - case 'O': - (*info->fprintf_func) (info->stream, "%d", - (l >> OP_SH_ALN) & OP_MASK_ALN); - break; - - case 'Q': - { - unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; - if ((vsel & 0x10) == 0) - { - int fmt; - vsel &= 0x0f; - for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) - if ((vsel & 1) == 0) - break; - (*info->fprintf_func) (info->stream, "$v%d[%d]", - (l >> OP_SH_FT) & OP_MASK_FT, - vsel >> 1); - } - else if ((vsel & 0x08) == 0) - { - (*info->fprintf_func) (info->stream, "$v%d", - (l >> OP_SH_FT) & OP_MASK_FT); - } - else - { - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_FT) & OP_MASK_FT); - } - } - break; - - case 'X': - (*info->fprintf_func) (info->stream, "$v%d", - (l >> OP_SH_FD) & OP_MASK_FD); - break; - - case 'Y': - (*info->fprintf_func) (info->stream, "$v%d", - (l >> OP_SH_FS) & OP_MASK_FS); - break; - - case 'Z': - (*info->fprintf_func) (info->stream, "$v%d", - (l >> OP_SH_FT) & OP_MASK_FT); - break; - - default: - /* xgettext:c-format */ - (*info->fprintf_func) (info->stream, - _("# internal error, undefined modifier(%c)"), - *d); - return; - } - } -} - -/* Check if the object uses NewABI conventions. */ - -static int -is_newabi (header) - Elf_Internal_Ehdr *header; -{ - /* There are no old-style ABIs which use 64-bit ELF. */ - if (header->e_ident[EI_CLASS] == ELFCLASS64) - return 1; - - /* If a 32-bit ELF file, n32 is a new-style ABI. */ - if ((header->e_flags & EF_MIPS_ABI2) != 0) - return 1; - - return 0; -} - -/* Print the mips instruction at address MEMADDR in debugged memory, - on using INFO. Returns length of the instruction, in bytes, which is - always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if - this is little-endian code. */ - -static int -print_insn_mips (memaddr, word, info) - bfd_vma memaddr; - unsigned long int word; - struct disassemble_info *info; -{ - register const struct mips_opcode *op; - static bfd_boolean init = 0; - static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; - - /* Build a hash table to shorten the search time. */ - if (! init) - { - unsigned int i; - - for (i = 0; i <= OP_MASK_OP; i++) - { - for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) - { - if (op->pinfo == INSN_MACRO) - continue; - if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) - { - mips_hash[i] = op; - break; - } - } - } - - init = 1; - } - - info->bytes_per_chunk = INSNLEN; - info->display_endian = info->endian; - info->insn_info_valid = 1; - info->branch_delay_insns = 0; - info->data_size = 0; - info->insn_type = dis_nonbranch; - info->target = 0; - info->target2 = 0; - - op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; - if (op != NULL) - { - for (; op < &mips_opcodes[NUMOPCODES]; op++) - { - if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match) - { - register const char *d; - - /* We always allow to disassemble the jalx instruction. */ - if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) - && strcmp (op->name, "jalx")) - continue; - - /* Figure out instruction type and branch delay information. */ - if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) - { - if ((info->insn_type & INSN_WRITE_GPR_31) != 0) - info->insn_type = dis_jsr; - else - info->insn_type = dis_branch; - info->branch_delay_insns = 1; - } - else if ((op->pinfo & (INSN_COND_BRANCH_DELAY - | INSN_COND_BRANCH_LIKELY)) != 0) - { - if ((info->insn_type & INSN_WRITE_GPR_31) != 0) - info->insn_type = dis_condjsr; - else - info->insn_type = dis_condbranch; - info->branch_delay_insns = 1; - } - else if ((op->pinfo & (INSN_STORE_MEMORY - | INSN_LOAD_MEMORY_DELAY)) != 0) - info->insn_type = dis_dref; - - (*info->fprintf_func) (info->stream, "%s", op->name); - - d = op->args; - if (d != NULL && *d != '\0') - { - (*info->fprintf_func) (info->stream, "\t"); - print_insn_args (d, word, memaddr, info); - } - - return INSNLEN; - } - } - } - - /* Handle undefined instructions. */ - info->insn_type = dis_noninsn; - (*info->fprintf_func) (info->stream, "0x%x", word); - return INSNLEN; -} - -/* In an environment where we do not know the symbol type of the - instruction we are forced to assume that the low order bit of the - instructions' address may mark it as a mips16 instruction. If we - are single stepping, or the pc is within the disassembled function, - this works. Otherwise, we need a clue. Sometimes. */ - -static int -_print_insn_mips (memaddr, info, endianness) - bfd_vma memaddr; - struct disassemble_info *info; - enum bfd_endian endianness; -{ - bfd_byte buffer[INSNLEN]; - int status; - - set_default_mips_dis_options (info); - parse_mips_dis_options (info->disassembler_options); - -#if 1 - /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ - /* Only a few tools will work this way. */ - if (memaddr & 0x01) - return print_insn_mips16 (memaddr, info); -#endif - -#if SYMTAB_AVAILABLE - if (info->mach == bfd_mach_mips16 - || (info->flavour == bfd_target_elf_flavour - && info->symbols != NULL - && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other - == STO_MIPS16))) - return print_insn_mips16 (memaddr, info); -#endif - - status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); - if (status == 0) - { - unsigned long insn; - - if (endianness == BFD_ENDIAN_BIG) - insn = (unsigned long) bfd_getb32 (buffer); - else - insn = (unsigned long) bfd_getl32 (buffer); - - return print_insn_mips (memaddr, insn, info); - } - else - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } -} - -int -print_insn_big_mips (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); -} - -int -print_insn_little_mips (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); -} - -/* Disassemble mips16 instructions. */ - -static int -print_insn_mips16 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status; - bfd_byte buffer[2]; - int length; - int insn; - bfd_boolean use_extend; - int extend = 0; - const struct mips_opcode *op, *opend; - - info->bytes_per_chunk = 2; - info->display_endian = info->endian; - info->insn_info_valid = 1; - info->branch_delay_insns = 0; - info->data_size = 0; - info->insn_type = dis_nonbranch; - info->target = 0; - info->target2 = 0; - - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - length = 2; - - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - - /* Handle the extend opcode specially. */ - use_extend = FALSE; - if ((insn & 0xf800) == 0xf000) - { - use_extend = TRUE; - extend = insn & 0x7ff; - - memaddr += 2; - - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->fprintf_func) (info->stream, "extend 0x%x", - (unsigned int) extend); - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - - /* Check for an extend opcode followed by an extend opcode. */ - if ((insn & 0xf800) == 0xf000) - { - (*info->fprintf_func) (info->stream, "extend 0x%x", - (unsigned int) extend); - info->insn_type = dis_noninsn; - return length; - } - - length += 2; - } - - /* FIXME: Should probably use a hash table on the major opcode here. */ - - opend = mips16_opcodes + bfd_mips16_num_opcodes; - for (op = mips16_opcodes; op < opend; op++) - { - if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match) - { - const char *s; - - if (strchr (op->args, 'a') != NULL) - { - if (use_extend) - { - (*info->fprintf_func) (info->stream, "extend 0x%x", - (unsigned int) extend); - info->insn_type = dis_noninsn; - return length - 2; - } - - use_extend = FALSE; - - memaddr += 2; - - status = (*info->read_memory_func) (memaddr, buffer, 2, - info); - if (status == 0) - { - use_extend = TRUE; - if (info->endian == BFD_ENDIAN_BIG) - extend = bfd_getb16 (buffer); - else - extend = bfd_getl16 (buffer); - length += 2; - } - } - - (*info->fprintf_func) (info->stream, "%s", op->name); - if (op->args[0] != '\0') - (*info->fprintf_func) (info->stream, "\t"); - - for (s = op->args; *s != '\0'; s++) - { - if (*s == ',' - && s[1] == 'w' - && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) - == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) - { - /* Skip the register and the comma. */ - ++s; - continue; - } - if (*s == ',' - && s[1] == 'v' - && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) - == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) - { - /* Skip the register and the comma. */ - ++s; - continue; - } - print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, - info); - } - - if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) - { - info->branch_delay_insns = 1; - if (info->insn_type != dis_jsr) - info->insn_type = dis_branch; - } - - return length; - } - } - - if (use_extend) - (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); - (*info->fprintf_func) (info->stream, "0x%x", insn); - info->insn_type = dis_noninsn; - - return length; -} - -/* Disassemble an operand for a mips16 instruction. */ - -static void -print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) - char type; - const struct mips_opcode *op; - int l; - bfd_boolean use_extend; - int extend; - bfd_vma memaddr; - struct disassemble_info *info; -{ - switch (type) - { - case ',': - case '(': - case ')': - (*info->fprintf_func) (info->stream, "%c", type); - break; - - case 'y': - case 'w': - (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RY) - & MIPS16OP_MASK_RY)]); - break; - - case 'x': - case 'v': - (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RX) - & MIPS16OP_MASK_RX)]); - break; - - case 'z': - (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RZ) - & MIPS16OP_MASK_RZ)]); - break; - - case 'Z': - (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) - & MIPS16OP_MASK_MOVE32Z)]); - break; - - case '0': - (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); - break; - - case 'S': - (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); - break; - - case 'P': - (*info->fprintf_func) (info->stream, "$pc"); - break; - - case 'R': - (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); - break; - - case 'X': - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[((l >> MIPS16OP_SH_REGR32) - & MIPS16OP_MASK_REGR32)]); - break; - - case 'Y': - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); - break; - - case '<': - case '>': - case '[': - case ']': - case '4': - case '5': - case 'H': - case 'W': - case 'D': - case 'j': - case '6': - case '8': - case 'V': - case 'C': - case 'U': - case 'k': - case 'K': - case 'p': - case 'q': - case 'A': - case 'B': - case 'E': - { - int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; - - shift = 0; - signedp = 0; - extbits = 16; - pcrel = 0; - extu = 0; - branch = 0; - switch (type) - { - case '<': - nbits = 3; - immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; - extbits = 5; - extu = 1; - break; - case '>': - nbits = 3; - immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; - extbits = 5; - extu = 1; - break; - case '[': - nbits = 3; - immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; - extbits = 6; - extu = 1; - break; - case ']': - nbits = 3; - immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; - extbits = 6; - extu = 1; - break; - case '4': - nbits = 4; - immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; - signedp = 1; - extbits = 15; - break; - case '5': - nbits = 5; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - info->insn_type = dis_dref; - info->data_size = 1; - break; - case 'H': - nbits = 5; - shift = 1; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - info->insn_type = dis_dref; - info->data_size = 2; - break; - case 'W': - nbits = 5; - shift = 2; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 - && (op->pinfo & MIPS16_INSN_READ_SP) == 0) - { - info->insn_type = dis_dref; - info->data_size = 4; - } - break; - case 'D': - nbits = 5; - shift = 3; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - info->insn_type = dis_dref; - info->data_size = 8; - break; - case 'j': - nbits = 5; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - signedp = 1; - break; - case '6': - nbits = 6; - immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; - break; - case '8': - nbits = 8; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - break; - case 'V': - nbits = 8; - shift = 2; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - /* FIXME: This might be lw, or it might be addiu to $sp or - $pc. We assume it's load. */ - info->insn_type = dis_dref; - info->data_size = 4; - break; - case 'C': - nbits = 8; - shift = 3; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - info->insn_type = dis_dref; - info->data_size = 8; - break; - case 'U': - nbits = 8; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - extu = 1; - break; - case 'k': - nbits = 8; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - signedp = 1; - break; - case 'K': - nbits = 8; - shift = 3; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - signedp = 1; - break; - case 'p': - nbits = 8; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - signedp = 1; - pcrel = 1; - branch = 1; - info->insn_type = dis_condbranch; - break; - case 'q': - nbits = 11; - immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; - signedp = 1; - pcrel = 1; - branch = 1; - info->insn_type = dis_branch; - break; - case 'A': - nbits = 8; - shift = 2; - immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; - pcrel = 1; - /* FIXME: This can be lw or la. We assume it is lw. */ - info->insn_type = dis_dref; - info->data_size = 4; - break; - case 'B': - nbits = 5; - shift = 3; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - pcrel = 1; - info->insn_type = dis_dref; - info->data_size = 8; - break; - case 'E': - nbits = 5; - shift = 2; - immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; - pcrel = 1; - break; - default: - abort (); - } - - if (! use_extend) - { - if (signedp && immed >= (1 << (nbits - 1))) - immed -= 1 << nbits; - immed <<= shift; - if ((type == '<' || type == '>' || type == '[' || type == ']') - && immed == 0) - immed = 8; - } - else - { - if (extbits == 16) - immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); - else if (extbits == 15) - immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); - else - immed = ((extend >> 6) & 0x1f) | (extend & 0x20); - immed &= (1 << extbits) - 1; - if (! extu && immed >= (1 << (extbits - 1))) - immed -= 1 << extbits; - } - - if (! pcrel) - (*info->fprintf_func) (info->stream, "%d", immed); - else - { - bfd_vma baseaddr; - - if (branch) - { - immed *= 2; - baseaddr = memaddr + 2; - } - else if (use_extend) - baseaddr = memaddr - 2; - else - { - int status; - bfd_byte buffer[2]; - - baseaddr = memaddr; - - /* If this instruction is in the delay slot of a jr - instruction, the base address is the address of the - jr instruction. If it is in the delay slot of jalr - instruction, the base address is the address of the - jalr instruction. This test is unreliable: we have - no way of knowing whether the previous word is - instruction or data. */ - status = (*info->read_memory_func) (memaddr - 4, buffer, 2, - info); - if (status == 0 - && (((info->endian == BFD_ENDIAN_BIG - ? bfd_getb16 (buffer) - : bfd_getl16 (buffer)) - & 0xf800) == 0x1800)) - baseaddr = memaddr - 4; - else - { - status = (*info->read_memory_func) (memaddr - 2, buffer, - 2, info); - if (status == 0 - && (((info->endian == BFD_ENDIAN_BIG - ? bfd_getb16 (buffer) - : bfd_getl16 (buffer)) - & 0xf81f) == 0xe800)) - baseaddr = memaddr - 2; - } - } - info->target = (baseaddr & ~((1 << shift) - 1)) + immed; - (*info->print_address_func) (info->target, info); - } - } - break; - - case 'a': - if (! use_extend) - extend = 0; - l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); - info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; - (*info->print_address_func) (info->target, info); - info->insn_type = dis_jsr; - info->branch_delay_insns = 1; - break; - - case 'l': - case 'L': - { - int need_comma, amask, smask; - - need_comma = 0; - - l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; - - amask = (l >> 3) & 7; - - if (amask > 0 && amask < 5) - { - (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); - if (amask > 1) - (*info->fprintf_func) (info->stream, "-%s", - mips_gpr_names[amask + 3]); - need_comma = 1; - } - - smask = (l >> 1) & 3; - if (smask == 3) - { - (*info->fprintf_func) (info->stream, "%s??", - need_comma ? "," : ""); - need_comma = 1; - } - else if (smask > 0) - { - (*info->fprintf_func) (info->stream, "%s%s", - need_comma ? "," : "", - mips_gpr_names[16]); - if (smask > 1) - (*info->fprintf_func) (info->stream, "-%s", - mips_gpr_names[smask + 15]); - need_comma = 1; - } - - if (l & 1) - { - (*info->fprintf_func) (info->stream, "%s%s", - need_comma ? "," : "", - mips_gpr_names[31]); - need_comma = 1; - } - - if (amask == 5 || amask == 6) - { - (*info->fprintf_func) (info->stream, "%s$f0", - need_comma ? "," : ""); - if (amask == 6) - (*info->fprintf_func) (info->stream, "-$f1"); - } - } - break; - - default: - /* xgettext:c-format */ - (*info->fprintf_func) - (info->stream, - _("# internal disassembler error, unrecognised modifier (%c)"), - type); - abort (); - } -} - -void -print_mips_disassembler_options (stream) - FILE *stream; -{ - unsigned int i; - - fprintf (stream, _("\n\ -The following MIPS specific disassembler options are supported for use\n\ -with the -M switch (multiple options should be separated by commas):\n")); - - fprintf (stream, _("\n\ - gpr-names=ABI Print GPR names according to specified ABI.\n\ - Default: based on binary being disassembled.\n")); - - fprintf (stream, _("\n\ - fpr-names=ABI Print FPR names according to specified ABI.\n\ - Default: numeric.\n")); - - fprintf (stream, _("\n\ - cp0-names=ARCH Print CP0 register names according to\n\ - specified architecture.\n\ - Default: based on binary being disassembled.\n")); - - fprintf (stream, _("\n\ - hwr-names=ARCH Print HWR names according to specified \n\ - architecture.\n\ - Default: based on binary being disassembled.\n")); - - fprintf (stream, _("\n\ - reg-names=ABI Print GPR and FPR names according to\n\ - specified ABI.\n")); - - fprintf (stream, _("\n\ - reg-names=ARCH Print CP0 register and HWR names according to\n\ - specified architecture.\n")); - - fprintf (stream, _("\n\ - For the options above, the following values are supported for \"ABI\":\n\ - ")); - for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) - fprintf (stream, " %s", mips_abi_choices[i].name); - fprintf (stream, _("\n")); - - fprintf (stream, _("\n\ - For the options above, The following values are supported for \"ARCH\":\n\ - ")); - for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) - if (*mips_arch_choices[i].name != '\0') - fprintf (stream, " %s", mips_arch_choices[i].name); - fprintf (stream, _("\n")); - - fprintf (stream, _("\n")); -} diff --git a/contrib/binutils/opcodes/mips-opc.c b/contrib/binutils/opcodes/mips-opc.c deleted file mode 100644 index 9a80e53..0000000 --- a/contrib/binutils/opcodes/mips-opc.c +++ /dev/null @@ -1,1218 +0,0 @@ -/* mips-opc.c -- MIPS opcode list. - Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 - Free Software Foundation, Inc. - Contributed by Ralph Campbell and OSF - Commented and modified by Ian Lance Taylor, Cygnus Support - Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc. - MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom - Corporation (SiByte). - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/mips.h" - -/* Short hand so the lines aren't too long. */ - -#define LDD INSN_LOAD_MEMORY_DELAY -#define LCD INSN_LOAD_COPROC_DELAY -#define UBD INSN_UNCOND_BRANCH_DELAY -#define CBD INSN_COND_BRANCH_DELAY -#define COD INSN_COPROC_MOVE_DELAY -#define CLD INSN_COPROC_MEMORY_DELAY -#define CBL INSN_COND_BRANCH_LIKELY -#define TRAP INSN_TRAP -#define SM INSN_STORE_MEMORY - -#define WR_d INSN_WRITE_GPR_D -#define WR_t INSN_WRITE_GPR_T -#define WR_31 INSN_WRITE_GPR_31 -#define WR_D INSN_WRITE_FPR_D -#define WR_T INSN_WRITE_FPR_T -#define WR_S INSN_WRITE_FPR_S -#define RD_s INSN_READ_GPR_S -#define RD_b INSN_READ_GPR_S -#define RD_t INSN_READ_GPR_T -#define RD_S INSN_READ_FPR_S -#define RD_T INSN_READ_FPR_T -#define RD_R INSN_READ_FPR_R -#define WR_CC INSN_WRITE_COND_CODE -#define RD_CC INSN_READ_COND_CODE -#define RD_C0 INSN_COP -#define RD_C1 INSN_COP -#define RD_C2 INSN_COP -#define RD_C3 INSN_COP -#define WR_C0 INSN_COP -#define WR_C1 INSN_COP -#define WR_C2 INSN_COP -#define WR_C3 INSN_COP - -#define WR_HI INSN_WRITE_HI -#define RD_HI INSN_READ_HI -#define MOD_HI WR_HI|RD_HI - -#define WR_LO INSN_WRITE_LO -#define RD_LO INSN_READ_LO -#define MOD_LO WR_LO|RD_LO - -#define WR_HILO WR_HI|WR_LO -#define RD_HILO RD_HI|RD_LO -#define MOD_HILO WR_HILO|RD_HILO - -#define IS_M INSN_MULT - -#define WR_MACC INSN_WRITE_MDMX_ACC -#define RD_MACC INSN_READ_MDMX_ACC - -#define I1 INSN_ISA1 -#define I2 INSN_ISA2 -#define I3 INSN_ISA3 -#define I4 INSN_ISA4 -#define I5 INSN_ISA5 -#define I32 INSN_ISA32 -#define I64 INSN_ISA64 -#define I33 INSN_ISA32R2 -#define I65 INSN_ISA64R2 - -/* MIPS64 MIPS-3D ASE support. */ -#define I16 INSN_MIPS16 - -/* MIPS64 MIPS-3D ASE support. */ -#define M3D INSN_MIPS3D - -/* MIPS64 MDMX ASE support. */ -#define MX INSN_MDMX - -#define P3 INSN_4650 -#define L1 INSN_4010 -#define V1 (INSN_4100 | INSN_4111 | INSN_4120) -#define T3 INSN_3900 -#define M1 INSN_10000 -#define SB1 INSN_SB1 -#define N411 INSN_4111 -#define N412 INSN_4120 -#define N5 (INSN_5400 | INSN_5500) -#define N54 INSN_5400 -#define N55 INSN_5500 - -#define G1 (T3 \ - ) - -#define G2 (T3 \ - ) - -#define G3 (I4 \ - ) - -/* The order of overloaded instructions matters. Label arguments and - register arguments look the same. Instructions that can have either - for arguments must apear in the correct order in this table for the - assembler to pick the right one. In other words, entries with - immediate operands must apear after the same instruction with - registers. - - Because of the lookup algorithm used, entries with the same opcode - name must be contiguous. - - Many instructions are short hand for other instructions (i.e., The - jal <register> instruction is short for jalr <register>). */ - -const struct mips_opcode mips_builtin_opcodes[] = -{ -/* These instructions appear first so that the disassembler will find - them first. The assemblers uses a hash table based on the - instruction name anyhow. */ -/* name, args, match, mask, pinfo, membership */ -{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3 }, -{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, -{"nop", "", 0x00000000, 0xffffffff, 0, I1 }, /* sll */ -{"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 }, /* sll */ -{"ehb", "", 0x000000c0, 0xffffffff, 0, I33 }, /* sll */ -{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ -{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ -{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, -{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 }, -{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */ -{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */ -{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */ -{"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */ -{"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */ -{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/ - -{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 }, -{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 }, -{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 }, -{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, -{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, -{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, -{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, -{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, -{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, -{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, -{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, -{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, -{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, -{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 }, -{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, N54 }, -{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 }, -{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX|SB1 }, -{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX }, -{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 }, -{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, -/* b is at the top of the table. */ -/* bal is at the top of the table. */ -{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, -{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, -{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, -{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, M3D }, -{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, -{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 }, -{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, -{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 }, -{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, -{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 }, -{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, -{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 }, -{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 }, -{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 }, -{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, -{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 }, -{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, -{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2|T3 }, -{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 }, -{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 }, -{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2|T3 }, -{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2|T3 }, -{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 }, -{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 }, -{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2|T3 }, -{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2|T3 }, -{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 }, -{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, -{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, -{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 }, -{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 }, -{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2|T3 }, -{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2|T3 }, -{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 }, -{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 }, -{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2|T3 }, -{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2|T3 }, -{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 }, -{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 }, -{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2|T3 }, -{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2|T3 }, -{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 }, -{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 }, -{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2|T3 }, -{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2|T3 }, -{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 }, -{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 }, -{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2|T3 }, -{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2|T3 }, -{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 }, -{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 }, -{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2|T3 }, -{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2|T3 }, -{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, -{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, -{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 }, -{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, -{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, -{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 }, -{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, -{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2|T3 }, -{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 }, -{"break", "B", 0x0000000d, 0xfc00003f, TRAP, I32 }, -{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 }, -{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 }, -{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 }, -{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, -{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX }, -{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 }, -{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, -{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX }, -{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 }, -{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, -{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX }, -{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, -{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, -{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, -{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D }, -{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D }, -{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3}, -{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, -{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, -{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, -{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, -{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, -{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 }, -{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 }, -{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, -{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, -{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, -{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, -{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, -{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 }, -{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 }, -{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 }, -{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 }, -{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D }, -{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, -{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D }, -{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 }, -{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, -{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 }, -{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 }, -{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, -{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, -{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 }, -{"dbreak", "", 0x7000003f, 0xffffffff, 0, N5 }, -{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 }, -{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 }, -/* dctr and dctw are used on the r5000. */ -{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, -{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, -{"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2 }, -{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, I65 }, -{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, I65 }, -{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, I65 }, -{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, I65 }, -/* For ddiv, see the comments about div. */ -{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, -{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 }, -{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 }, -/* For ddivu, see the comments about div. */ -{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, -{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 }, -{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 }, -{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, I33 }, -{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, I33 }, -{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, I65 }, -{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, I65 }, -{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, I65 }, -{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, I65 }, -/* The MIPS assembler treats the div opcode with two operands as - though the first operand appeared twice (the first operand is both - a source and a destination). To get the div machine instruction, - you must use an explicit destination of $0. */ -{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, -{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 }, -{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 }, -{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 }, -{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, -{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, -{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, SB1 }, -/* For divu, see the comments about div. */ -{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, -{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 }, -{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 }, -{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 }, -{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 }, -{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, I3 }, -{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */ -{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */ -{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 }, -{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, -{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, -{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, -{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, -{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, -{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, -{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, -{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 }, -{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, N411 }, -{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 }, -{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, -{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 }, -{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 }, -{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, -{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 }, -{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, -{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 }, -{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, -{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 }, -{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 }, -{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 }, -{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 }, -{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 }, -{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, I3 }, -{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, I64 }, -{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I3 }, -{"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I64 }, -{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 }, -{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 }, -{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 }, -{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 }, -{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 }, -{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 }, -{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, -{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, -{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */ -{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/ -{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, -{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 }, -{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 }, -{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, -{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 }, -{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 }, -{"dret", "", 0x7000003e, 0xffffffff, 0, N5 }, -{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 }, -{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 }, -{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 }, -{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 }, -{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, N5|I65 }, -{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5|I65 }, -{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, N5|I65 }, -{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I65 }, -{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I65 }, -{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I65 }, -{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I65 }, -{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, I65 }, -{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, I65 }, -{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, I65 }, -{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, I65 }, -{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, -{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */ -{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */ -{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, -{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */ -{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */ -{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, -{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */ -{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */ -{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 }, -{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, -{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 }, -{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 }, -{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 }, -{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, I33 }, -{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, I33 }, -{"eret", "", 0x42000018, 0xffffffff, 0, I3|I32 }, -{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, I33 }, -{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"flushi", "", 0xbc010000, 0xffffffff, 0, L1 }, -{"flushd", "", 0xbc020000, 0xffffffff, 0, L1 }, -{"flushid", "", 0xbc030000, 0xffffffff, 0, L1 }, -{"hibernate","", 0x42000023, 0xffffffff, 0, V1 }, -{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, I33 }, -{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, -{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, I33 }, -{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */ -/* SVR4 PIC code requires special handling for j, so it must be a - macro. */ -{"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 }, -/* This form of j is used by the disassembler and internally by the - assembler, but will never match user input (because the line above - will match first). */ -{"j", "a", 0x08000000, 0xfc000000, UBD, I1 }, -{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 }, -{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 }, -{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, I33 }, -{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, I33 }, -/* SVR4 PIC code requires special handling for jal, so it must be a - macro. */ -{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 }, -{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 }, -{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 }, -/* This form of jal is used by the disassembler and internally by the - assembler, but will never match user input (because the line above - will match first). */ -{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 }, -{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I16 }, -{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 }, -{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 }, -{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 }, -{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, I1 }, -{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 }, -{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 }, -{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 }, -{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, -{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, -{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, -{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 }, -{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */ -{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 }, -{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 }, -{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, -{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 }, -{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 }, -{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 }, -{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, -{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 }, -{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 }, -{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 }, -{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, -{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 }, -{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 }, -/* li is at the start of the table. */ -{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 }, -{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 }, -{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 }, -{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 }, -{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, -{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 }, -{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, -{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 }, -{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 }, -{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I5|N55 }, -{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 }, -{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, -{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 }, -{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, -{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, -{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, -{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, -{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */ -{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 }, -{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, -{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 }, -{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 }, -{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 }, -{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 }, -{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ -{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */ -{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, -{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 }, -{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */ -{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */ -{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 }, -{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 }, -{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 }, -{"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 }, -{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 }, -{"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 }, -{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 }, -{"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 }, -{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 }, -{"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 }, -{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 }, -{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 }, -{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 }, -{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, -{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, -{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, -{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 }, -{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55}, -{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 }, -{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, -{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 }, -{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55}, -{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 }, -{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, -{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, N411 }, -{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 }, -{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 }, -{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, -{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 }, -{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 }, -{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, -{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, -{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 }, -{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 }, -{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, -{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 }, -{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, I33 }, -{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, -{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 }, -{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, N5 }, -{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 }, -{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 }, -{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 }, -{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32}, -{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 }, -{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 }, -{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 }, -{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 }, -{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 }, -{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 }, -{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 }, -{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 }, -{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 }, -{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 }, -{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 }, -{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 }, -{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32 }, -{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 }, -{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 }, -{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 }, -{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 }, -{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 }, -{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 }, -{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 }, -{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 }, -{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 }, -{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 }, -{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 }, -{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 }, -{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -/* move is at the top of the table. */ -{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, -{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, -{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, -{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 }, -{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55 }, -{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 }, -{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55 }, -{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 }, -{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 }, -{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 }, -{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 }, -{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 }, -{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, -{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, -{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 }, -{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 }, -{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 }, -{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 }, -{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, I33 }, -{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 }, -{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 }, -{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, N5 }, -{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 }, -{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 }, -{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, -{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, -{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, -{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3|N55}, -{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N54 }, -{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 }, -{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 }, -{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, -{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, -{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, -{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, -{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, -{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, -{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 }, -{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 }, -{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 }, -{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 }, -{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, -{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, -{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, -{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, -{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, -{"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 }, -{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N54 }, -{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, -{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 }, -{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, -{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 }, -{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, -{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 }, -{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */ -{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */ -{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 }, -{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 }, -{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, I5 }, -{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, -{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, -{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, -{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, -{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, -{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, -/* nop is at the start of the table. */ -{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 }, -{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/ -{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 }, -{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 }, -{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 }, -{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, SB1 }, -{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 }, -{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, -{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, - /* pref and prefx are at the start of the table. */ -{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, -{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, -{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 }, -{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, N54 }, -{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX }, -{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 }, -{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, N54 }, -{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX }, -{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 }, -{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, N54 }, -{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX }, -{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, -{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, -{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, -{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, M3D }, -{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, M3D }, -{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, M3D }, -{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, -{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, -{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, -{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, -{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 }, -{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 }, -{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, -{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 }, -{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 }, -{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, I33 }, -{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, I33 }, -{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 }, -{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, -{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 }, -{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, -{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, -{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 }, -{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, -{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 }, -{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 }, -{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 }, -{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 }, -{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, N5|I33 }, -{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, N5|I33 }, -{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I33 }, -{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I33 }, -{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I33 }, -{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I33 }, -{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, I33 }, -{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 }, -{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, -{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, -{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, M3D }, -{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, M3D }, -{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, M3D }, -{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, -{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, -{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, -{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, -{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 }, -{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, N54 }, -{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, -{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, -{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, -{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 }, -{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 }, -{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 }, -{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 }, -{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 }, -{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 }, -{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 }, -{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2 }, -{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2 }, -{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, I32 }, -{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 }, -{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, -{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, -{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, -{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, -{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 }, -{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 }, -{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 }, -{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 }, -{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, -{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 }, -{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 }, -{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 }, -{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 }, -{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 }, -{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 }, -{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, -{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, I33 }, -{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, I33 }, -{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, L1 }, -{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, L1 }, -{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 }, -{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 }, -{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 }, -{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 }, -{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 }, -{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 }, -{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 }, -{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 }, -{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 }, -{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 }, -{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 }, -{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 }, -{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 }, -{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 }, -{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 }, -{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, -{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */ -{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 }, -{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 }, -{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 }, -{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 }, -{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 }, -{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 }, -{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 }, -{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, -{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, -{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */ -{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 }, -{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, -{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */ -{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 }, -{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -/* ssnop is at the start of the table. */ -{"standby", "", 0x42000021, 0xffffffff, 0, V1 }, -{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 }, -{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, -{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, -{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, -{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, -{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, -{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, -{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, -{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 }, -{"suspend", "", 0x42000022, 0xffffffff, 0, V1 }, -{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I5|N55 }, -{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 }, -{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 }, -{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 }, -{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, -{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, -{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, -{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, -{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */ -{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 }, -{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 }, -{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 }, -{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 }, -{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 }, -{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 }, -{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ -{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */ -{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 }, -{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 }, -{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */ -{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */ -{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 }, -{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 }, -{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 }, -{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 }, -{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, I33 }, -{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 }, -{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 }, -{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */ -{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 }, -{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */ -{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 }, -{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */ -{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 }, -{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 }, -{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 }, -{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 }, -{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 }, -{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */ -{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 }, -{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */ -{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 }, -{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, -{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 }, -{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 }, -{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */ -{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 }, -{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 }, -{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 }, -{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 }, -{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 }, -{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 }, -{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 }, -{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 }, -{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 }, -{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 }, -{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 }, -{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 }, -{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 }, -{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 }, -{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 }, -{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 }, -{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 }, -{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 }, -{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 }, -{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 }, -{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 }, -{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX|SB1 }, -{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, N54 }, -{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX }, -{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, -{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, N54 }, -{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, -{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32 }, -{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32|N55 }, -{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 }, -{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 }, -{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, I33 }, -{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, I33 }, -{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 }, -{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, -{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, N54 }, -{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, N54 }, -{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, -{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 }, - -/* No hazard protection on coprocessor instructions--they shouldn't - change the state of the processor and if they do it's up to the - user to put in nops as necessary. These are at the end so that the - disassembler recognizes more specific versions first. */ -{"c0", "C", 0x42000000, 0xfe000000, 0, I1 }, -{"c1", "C", 0x46000000, 0xfe000000, 0, I1 }, -{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 }, -{"c3", "C", 0x4e000000, 0xfe000000, 0, I1 }, -{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 }, -{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 }, -{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 }, -{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 }, - - /* Conflicts with the 4650's "mul" instruction. Nobody's using the - 4010 any more, so move this insn out of the way. If the object - format gave us more info, we could do this right. */ -{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, L1 }, -}; - -#define MIPS_NUM_OPCODES \ - ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) -const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; - -/* const removed from the following to allow for dynamic extensions to the - * built-in instruction set. */ -struct mips_opcode *mips_opcodes = - (struct mips_opcode *) mips_builtin_opcodes; -int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; -#undef MIPS_NUM_OPCODES diff --git a/contrib/binutils/opcodes/mips16-opc.c b/contrib/binutils/opcodes/mips16-opc.c deleted file mode 100644 index d7fcfc2..0000000 --- a/contrib/binutils/opcodes/mips16-opc.c +++ /dev/null @@ -1,227 +0,0 @@ -/* mips16-opc.c. Mips16 opcode table. - Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. - Contributed by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/mips.h" - -/* This is the opcodes table for the mips16 processor. The format of - this table is intentionally identical to the one in mips-opc.c. - However, the special letters that appear in the argument string are - different, and the table uses some different flags. */ - -/* Use some short hand macros to keep down the length of the lines in - the opcodes table. */ - -#define UBD INSN_UNCOND_BRANCH_DELAY -#define BR MIPS16_INSN_BRANCH - -#define WR_x MIPS16_INSN_WRITE_X -#define WR_y MIPS16_INSN_WRITE_Y -#define WR_z MIPS16_INSN_WRITE_Z -#define WR_T MIPS16_INSN_WRITE_T -#define WR_SP MIPS16_INSN_WRITE_SP -#define WR_31 MIPS16_INSN_WRITE_31 -#define WR_Y MIPS16_INSN_WRITE_GPR_Y - -#define RD_x MIPS16_INSN_READ_X -#define RD_y MIPS16_INSN_READ_Y -#define RD_Z MIPS16_INSN_READ_Z -#define RD_T MIPS16_INSN_READ_T -#define RD_SP MIPS16_INSN_READ_SP -#define RD_31 MIPS16_INSN_READ_31 -#define RD_PC MIPS16_INSN_READ_PC -#define RD_X MIPS16_INSN_READ_GPR_X - -#define WR_HI INSN_WRITE_HI -#define WR_LO INSN_WRITE_LO -#define RD_HI INSN_READ_HI -#define RD_LO INSN_READ_LO - -#define TRAP INSN_TRAP - -#define I3 INSN_ISA3 - -#define T3 INSN_3900 - -const struct mips_opcode mips16_opcodes[] = -{ -{"nop", "", 0x6500, 0xffff, RD_Z, 0 }, /* move $0,$Z */ -{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0 }, -{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0 }, -{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 }, -{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 }, -{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, -{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, -{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 }, -{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 }, -{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0 }, -{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0 }, -{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0 }, -{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, -{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0 }, -{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0 }, -{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0 }, -{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0 }, -{"b", "q", 0x1000, 0xf800, BR, 0 }, -{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0 }, -{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0 }, -{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0 }, -{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0 }, -{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0 }, -{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0 }, -{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0 }, -{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0 }, -{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0 }, -{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0 }, -{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0 }, -{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0 }, -{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0 }, -{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0 }, -{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0 }, -{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0 }, -{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0 }, -{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0 }, -{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0 }, -{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0 }, -{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0 }, -{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0 }, -{"break", "6", 0xe805, 0xf81f, TRAP, 0 }, -{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0 }, -{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0 }, -{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 }, -{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0 }, -{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0 }, -{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, -{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, -{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, -{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, -{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, -{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, -{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, -{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, I3 }, -{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, I3 }, -{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, I3 }, -{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, -{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, I3 }, -{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, I3 }, -{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, I3 }, -{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0 }, -{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0 }, -{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, -{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0 }, -{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, -{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0 }, -{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, I3 }, -{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0 }, -{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, I3 }, -{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0 }, -{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 }, -{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, I3 }, -{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, I3 }, -{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 }, -{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, I3 }, -{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, I3 }, -{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 }, -{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, I3 }, -{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, I3 }, -{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, I3 }, -{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0 }, -{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0 }, -{"exit", "L", 0xed09, 0xff1f, TRAP, 0 }, -{"exit", "L", 0xee09, 0xff1f, TRAP, 0 }, -{"exit", "L", 0xef09, 0xff1f, TRAP, 0 }, -{"entry", "l", 0xe809, 0xf81f, TRAP, 0 }, -{"extend", "e", 0xf000, 0xf800, 0, 0 }, -{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, -{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, -{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, -{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0 }, -{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0 }, -{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0 }, -{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 }, -{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0 }, -{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0 }, -{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0 }, -{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0 }, -{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0 }, -{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, I3 }, -{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, -{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, I3 }, -{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, I3 }, -{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0 }, -{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0 }, -{"li", "x,U", 0x6800, 0xf800, WR_x, 0 }, -{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0 }, -{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0 }, -{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0 }, -{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0 }, -{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, I3 }, -{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0 }, -{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0 }, -{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0 }, -{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0 }, -{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0 }, -{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, -{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, -{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0 }, -{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0 }, -{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0 }, -{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, -{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0 }, -{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0 }, -{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0 }, -{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0 }, -{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, I3 }, -{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, I3 }, -{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0 }, -{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0 }, -{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 }, -{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0 }, -{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0 }, -{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 }, -{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0 }, -{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0 }, -{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 }, -{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0 }, -{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0 }, -{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 }, -{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0 }, -{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0 }, -{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 }, -{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0 }, -{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0 }, -{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0 }, -{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0 }, -{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0 }, -{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0 }, -{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0 }, -{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0 }, -{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0 }, -}; - -const int bfd_mips16_num_opcodes = - ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0]))); diff --git a/contrib/binutils/opcodes/opintl.h b/contrib/binutils/opcodes/opintl.h deleted file mode 100644 index d19b664..0000000 --- a/contrib/binutils/opcodes/opintl.h +++ /dev/null @@ -1,42 +0,0 @@ -/* opintl.h - opcodes specific header for gettext code. - Copyright 1998, 1999, 2000 Free Software Foundation, Inc. - - Written by Tom Tromey <tromey@cygnus.com> - - This file is part of the opcodes library used by GAS and the GNU binutils. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to the Free - Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#ifdef ENABLE_NLS -# include <libintl.h> -/* Note the use of dgetext() and PACKAGE here, rather than gettext(). - - This is because the code in this directory is used to build a library which - will be linked with code in other directories to form programs. We want to - maintain a seperate translation file for this directory however, rather - than being forced to merge it with that of any program linked to - libopcodes. This is a library, so it cannot depend on the catalog - currently loaded. - - In order to do this, we have to make sure that when we extract messages we - use the OPCODES domain rather than the domain of the program that included - the opcodes library, (eg OBJDUMP). Hence we use dgettext (PACKAGE, String) - and define PACKAGE to be 'opcodes'. (See the code in configure). */ -# define _(String) dgettext (PACKAGE, String) -# ifdef gettext_noop -# define N_(String) gettext_noop (String) -# else -# define N_(String) (String) -# endif -#else -# define gettext(Msgid) (Msgid) -# define dgettext(Domainname, Msgid) (Msgid) -# define dcgettext(Domainname, Msgid, Category) (Msgid) -# define textdomain(Domainname) while (0) /* nothing */ -# define bindtextdomain(Domainname, Dirname) while (0) /* nothing */ -# define _(String) (String) -# define N_(String) (String) -#endif diff --git a/contrib/binutils/opcodes/po/Make-in b/contrib/binutils/opcodes/po/Make-in deleted file mode 100644 index 6176dbf..0000000 --- a/contrib/binutils/opcodes/po/Make-in +++ /dev/null @@ -1,253 +0,0 @@ -# Makefile for program source directory in GNU NLS utilities package. -# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper <drepper@gnu.ai.mit.edu> -# -# This file file be copied and used freely without restrictions. It can -# be used in projects which are not available under the GNU Public License -# but which still want to provide support for the GNU gettext functionality. -# Please note that the actual code is *not* freely available. - -PACKAGE = @PACKAGE@ -VERSION = @VERSION@ - -SHELL = /bin/sh -@SET_MAKE@ - -srcdir = @srcdir@ -top_srcdir = @top_srcdir@ -VPATH = @srcdir@ - -prefix = @prefix@ -exec_prefix = @exec_prefix@ -datadir = $(prefix)/@DATADIRNAME@ -localedir = $(datadir)/locale -gnulocaledir = $(prefix)/share/locale -gettextsrcdir = $(prefix)/share/gettext/po -subdir = po - -DESTDIR = - -INSTALL = @INSTALL@ -INSTALL_DATA = @INSTALL_DATA@ -MKINSTALLDIRS = @MKINSTALLDIRS@ - -CC = @CC@ -GENCAT = @GENCAT@ -GMSGFMT = PATH=../src:$$PATH @GMSGFMT@ -MSGFMT = @MSGFMT@ -XGETTEXT = PATH=../src:$$PATH @XGETTEXT@ -MSGMERGE = PATH=../src:$$PATH msgmerge - -DEFS = @DEFS@ -CFLAGS = @CFLAGS@ -CPPFLAGS = @CPPFLAGS@ - -INCLUDES = -I.. -I$(top_srcdir)/intl - -COMPILE = $(CC) -c $(DEFS) $(INCLUDES) $(CPPFLAGS) $(CFLAGS) $(XCFLAGS) - -SOURCES = cat-id-tbl.c -POFILES = @POFILES@ -GMOFILES = @GMOFILES@ -DISTFILES = ChangeLog Makefile.in.in POTFILES.in $(PACKAGE).pot \ -stamp-cat-id $(POFILES) $(GMOFILES) $(SOURCES) - -POTFILES = \ - -CATALOGS = @CATALOGS@ -CATOBJEXT = @CATOBJEXT@ -INSTOBJEXT = @INSTOBJEXT@ - -.SUFFIXES: -.SUFFIXES: .c .o .po .pox .gmo .mo .msg .cat - -.c.o: - $(COMPILE) $< - -.po.pox: - $(MAKE) $(PACKAGE).pot - $(MSGMERGE) $< $(srcdir)/$(PACKAGE).pot -o $*.pox - -.po.mo: - $(MSGFMT) -o $@ $< - -.po.gmo: - file=$(srcdir)/`echo $* | sed 's,.*/,,'`.gmo \ - && rm -f $$file && $(GMSGFMT) -o $$file $< - -.po.cat: - sed -f ../intl/po2msg.sed < $< > $*.msg \ - && rm -f $@ && $(GENCAT) $@ $*.msg - - -all: all-@USE_NLS@ - -all-yes: $(CATALOGS) @MAINT@ $(PACKAGE).pot -all-no: - -$(srcdir)/$(PACKAGE).pot: $(POTFILES) - $(XGETTEXT) --default-domain=$(PACKAGE) --directory=$(top_srcdir) \ - --add-comments --keyword=_ --keyword=N_ \ - --files-from=$(srcdir)/POTFILES.in - rm -f $(srcdir)/$(PACKAGE).pot - mv $(PACKAGE).po $(srcdir)/$(PACKAGE).pot - -$(srcdir)/cat-id-tbl.c: stamp-cat-id; @: -$(srcdir)/stamp-cat-id: $(PACKAGE).pot - rm -f cat-id-tbl.tmp - sed -f ../intl/po2tbl.sed $(srcdir)/$(PACKAGE).pot \ - | sed -e "s/@PACKAGE NAME@/$(PACKAGE)/" > cat-id-tbl.tmp - if cmp -s cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; then \ - rm cat-id-tbl.tmp; \ - else \ - echo cat-id-tbl.c changed; \ - rm -f $(srcdir)/cat-id-tbl.c; \ - mv cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; \ - fi - cd $(srcdir) && rm -f stamp-cat-id && echo timestamp > stamp-cat-id - - -install: install-exec install-data -install-exec: -install-info: -install-data: install-data-@USE_NLS@ -install-data-no: all -install-data-yes: all - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(DESTDIR)$(datadir); \ - else \ - $(top_srcdir)/mkinstalldirs $(DESTDIR)$(datadir); \ - fi - @catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - case "$$cat" in \ - *.gmo) destdir=$(gnulocaledir);; \ - *) destdir=$(localedir);; \ - esac; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - dir=$(DESTDIR)$$destdir/$$lang/LC_MESSAGES; \ - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $$dir; \ - else \ - $(top_srcdir)/mkinstalldirs $$dir; \ - fi; \ - if test -r $$cat; then \ - $(INSTALL_DATA) $$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ - echo "installing $$cat as $$dir/$(PACKAGE)$(INSTOBJEXT)"; \ - else \ - $(INSTALL_DATA) $(srcdir)/$$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ - echo "installing $(srcdir)/$$cat as" \ - "$$dir/$(PACKAGE)$(INSTOBJEXT)"; \ - fi; \ - if test -r $$cat.m; then \ - $(INSTALL_DATA) $$cat.m $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ - echo "installing $$cat.m as $$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ - else \ - if test -r $(srcdir)/$$cat.m ; then \ - $(INSTALL_DATA) $(srcdir)/$$cat.m \ - $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ - echo "installing $(srcdir)/$$cat as" \ - "$$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ - else \ - true; \ - fi; \ - fi; \ - done - if test "$(PACKAGE)" = "gettext"; then \ - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(DESTDIR)$(gettextsrcdir); \ - else \ - $(top_srcdir)/mkinstalldirs $(DESTDIR)$(gettextsrcdir); \ - fi; \ - $(INSTALL_DATA) $(srcdir)/Makefile.in.in \ - $(DESTDIR)$(gettextsrcdir)/Makefile.in.in; \ - else \ - : ; \ - fi - -# Define this as empty until I found a useful application. -installcheck: - -uninstall: - catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - done - rm -f $(DESTDIR)$(gettextsrcdir)/po-Makefile.in.in - -check: all - -cat-id-tbl.o: ../intl/libgettext.h - -dvi info tags TAGS ID: - -mostlyclean: - rm -f core core.* *.pox $(PACKAGE).po *.old.po cat-id-tbl.tmp - rm -fr *.o - -clean: mostlyclean - -distclean: clean - rm -f Makefile Makefile.in POTFILES *.mo *.msg *.cat *.cat.m - -maintainer-clean: distclean - @echo "This command is intended for maintainers to use;" - @echo "it deletes files that may require special tools to rebuild." - rm -f $(GMOFILES) - -distdir = ../$(PACKAGE)-$(VERSION)/$(subdir) -dist distdir: update-po $(DISTFILES) - dists="$(DISTFILES)"; \ - for file in $$dists; do \ - ln $(srcdir)/$$file $(distdir) 2> /dev/null \ - || cp -p $(srcdir)/$$file $(distdir); \ - done - -update-po: Makefile - $(MAKE) $(PACKAGE).pot - PATH=`pwd`/../src:$$PATH; \ - cd $(srcdir); \ - catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - mv $$lang.po $$lang.old.po; \ - echo "$$lang:"; \ - if $(MSGMERGE) $$lang.old.po $(PACKAGE).pot -o $$lang.po; then \ - rm -f $$lang.old.po; \ - else \ - echo "msgmerge for $$cat failed!"; \ - rm -f $$lang.po; \ - mv $$lang.old.po $$lang.po; \ - fi; \ - done - -POTFILES: POTFILES.in - ( if test 'x$(srcdir)' != 'x.'; then \ - posrcprefix='$(top_srcdir)/'; \ - else \ - posrcprefix="../"; \ - fi; \ - rm -f $@-t $@ \ - && (sed -e '/^#/d' -e '/^[ ]*$$/d' \ - -e "s@.*@ $$posrcprefix& \\\\@" < $(srcdir)/$@.in \ - | sed -e '$$s/\\$$//') > $@-t \ - && chmod a-w $@-t \ - && mv $@-t $@ ) - -POTFILES.in: @MAINT@ ../Makefile - cd .. && $(MAKE) po/POTFILES.in - -Makefile: Make-in ../config.status POTFILES - cd .. \ - && CONFIG_FILES=$(subdir)/Makefile.in:$(subdir)/Make-in \ - CONFIG_HEADERS= $(SHELL) ./config.status - -# Tell versions [3.59,3.63) of GNU make not to export all variables. -# Otherwise a system limit (for SysV at least) may be exceeded. -.NOEXPORT: diff --git a/contrib/binutils/opcodes/po/POTFILES.in b/contrib/binutils/opcodes/po/POTFILES.in deleted file mode 100644 index 333c612..0000000 --- a/contrib/binutils/opcodes/po/POTFILES.in +++ /dev/null @@ -1,144 +0,0 @@ -a29k-dis.c -alpha-dis.c -alpha-opc.c -arc-dis.c -arc-ext.c -arc-opc.c -arm-dis.c -arm-opc.h -avr-dis.c -cgen-asm.c -cgen-dis.c -cgen-opc.c -cris-dis.c -cris-opc.c -d10v-dis.c -d10v-opc.c -d30v-dis.c -d30v-opc.c -disassemble.c -dis-buf.c -dis-init.c -dlx-dis.c -fr30-asm.c -fr30-desc.c -fr30-desc.h -fr30-dis.c -fr30-ibld.c -fr30-opc.c -fr30-opc.h -frv-asm.c -frv-desc.c -frv-desc.h -frv-dis.c -frv-ibld.c -frv-opc.c -frv-opc.h -h8300-dis.c -h8500-dis.c -h8500-opc.h -hppa-dis.c -i370-dis.c -i370-opc.c -i386-dis.c -i860-dis.c -i960-dis.c -ia64-asmtab.c -ia64-asmtab.h -ia64-dis.c -ia64-gen.c -ia64-opc-a.c -ia64-opc-b.c -ia64-opc.c -ia64-opc-d.c -ia64-opc-f.c -ia64-opc.h -ia64-opc-i.c -ia64-opc-m.c -ip2k-asm.c -ip2k-desc.c -ip2k-desc.h -ip2k-dis.c -ip2k-ibld.c -ip2k-opc.c -ip2k-opc.h -iq2000-asm.c -iq2000-desc.c -iq2000-desc.h -iq2000-dis.c -iq2000-ibld.c -iq2000-opc.c -iq2000-opc.h -m10200-dis.c -m10200-opc.c -m10300-dis.c -m10300-opc.c -m32r-asm.c -m32r-desc.c -m32r-desc.h -m32r-dis.c -m32r-ibld.c -m32r-opc.c -m32r-opc.h -m32r-opinst.c -m68hc11-dis.c -m68hc11-opc.c -m68k-dis.c -m68k-opc.c -m88k-dis.c -mcore-dis.c -mcore-opc.h -mips16-opc.c -mips-dis.c -mips-opc.c -mmix-dis.c -mmix-opc.c -ns32k-dis.c -openrisc-asm.c -openrisc-desc.c -openrisc-desc.h -openrisc-dis.c -openrisc-ibld.c -openrisc-opc.c -openrisc-opc.h -or32-dis.c -or32-opc.c -pdp11-dis.c -pdp11-opc.c -pj-dis.c -pj-opc.c -ppc-dis.c -ppc-opc.c -s390-dis.c -s390-mkopc.c -s390-opc.c -sh64-dis.c -sh64-opc.c -sh64-opc.h -sh-dis.c -sh-opc.h -sparc-dis.c -sparc-opc.c -sysdep.h -tic30-dis.c -tic4x-dis.c -tic54x-dis.c -tic54x-opc.c -tic80-dis.c -tic80-opc.c -v850-dis.c -v850-opc.c -vax-dis.c -w65-dis.c -w65-opc.h -xstormy16-asm.c -xstormy16-desc.c -xstormy16-desc.h -xstormy16-dis.c -xstormy16-ibld.c -xstormy16-opc.c -xstormy16-opc.h -xtensa-dis.c -z8k-dis.c -z8kgen.c -z8k-opc.h diff --git a/contrib/binutils/opcodes/po/opcodes.pot b/contrib/binutils/opcodes/po/opcodes.pot deleted file mode 100644 index 15fdff0..0000000 --- a/contrib/binutils/opcodes/po/opcodes.pot +++ /dev/null @@ -1,754 +0,0 @@ -# SOME DESCRIPTIVE TITLE. -# Copyright (C) YEAR Free Software Foundation, Inc. -# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR. -# -#, fuzzy -msgid "" -msgstr "" -"Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2003-07-17 14:54+0100\n" -"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" -"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" -"Language-Team: LANGUAGE <LL@li.org>\n" -"MIME-Version: 1.0\n" -"Content-Type: text/plain; charset=CHARSET\n" -"Content-Transfer-Encoding: 8bit\n" - -#: alpha-opc.c:335 -msgid "branch operand unaligned" -msgstr "" - -#: alpha-opc.c:358 alpha-opc.c:380 -msgid "jump hint unaligned" -msgstr "" - -#: arc-dis.c:52 -msgid "Illegal limm reference in last instruction!\n" -msgstr "" - -#: arm-dis.c:554 -msgid "<illegal precision>" -msgstr "" - -#: arm-dis.c:1162 -#, c-format -msgid "Unrecognised register name set: %s\n" -msgstr "" - -#: arm-dis.c:1169 -#, c-format -msgid "Unrecognised disassembler option: %s\n" -msgstr "" - -#: arm-dis.c:1343 -msgid "" -"\n" -"The following ARM specific disassembler options are supported for use with\n" -"the -M switch:\n" -msgstr "" - -#: avr-dis.c:117 avr-dis.c:127 -msgid "undefined" -msgstr "" - -#: avr-dis.c:179 -msgid "Internal disassembler error" -msgstr "" - -#: avr-dis.c:227 -#, c-format -msgid "unknown constraint `%c'" -msgstr "" - -#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195 -#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 -#, c-format -msgid "operand out of range (%ld not between %ld and %ld)" -msgstr "" - -#: cgen-asm.c:369 -#, c-format -msgid "operand out of range (%lu not between %lu and %lu)" -msgstr "" - -#: d30v-dis.c:312 -#, c-format -msgid "<unknown register %d>" -msgstr "" - -#. Can't happen. -#: dis-buf.c:57 -#, c-format -msgid "Unknown error %d\n" -msgstr "" - -#: dis-buf.c:62 -#, c-format -msgid "Address 0x%x is out of bounds.\n" -msgstr "" - -#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 -#: openrisc-asm.c:244 xstormy16-asm.c:284 -#, c-format -msgid "Unrecognized field %d while parsing.\n" -msgstr "" - -#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 -#: openrisc-asm.c:294 xstormy16-asm.c:334 -msgid "missing mnemonic in syntax string" -msgstr "" - -#. We couldn't parse it. -#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 -#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 -#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 -#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 -#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 -#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:470 -#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 -msgid "unrecognized instruction" -msgstr "" - -#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 -#: openrisc-asm.c:477 xstormy16-asm.c:517 -#, c-format -msgid "syntax error (expected char `%c', found `%c')" -msgstr "" - -#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 -#: openrisc-asm.c:487 xstormy16-asm.c:527 -#, c-format -msgid "syntax error (expected char `%c', found end of instruction)" -msgstr "" - -#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 -#: openrisc-asm.c:515 xstormy16-asm.c:555 -msgid "junk at end of line" -msgstr "" - -#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 -#: m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:662 -msgid "unrecognized form of instruction" -msgstr "" - -#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 -#: m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:674 -#, c-format -msgid "bad instruction `%.50s...'" -msgstr "" - -#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 -#: m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:677 -#, c-format -msgid "bad instruction `%.50s'" -msgstr "" - -#. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 -#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 -msgid "*unknown*" -msgstr "" - -#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 -#: openrisc-dis.c:138 xstormy16-dis.c:171 -#, c-format -msgid "Unrecognized field %d while printing insn.\n" -msgstr "" - -#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166 -#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 -#, c-format -msgid "operand out of range (%ld not between %ld and %lu)" -msgstr "" - -#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 -#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 -#, c-format -msgid "operand out of range (%lu not between 0 and %lu)" -msgstr "" - -#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 -#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 -#, c-format -msgid "Unrecognized field %d while building insn.\n" -msgstr "" - -#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 -#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 -#, c-format -msgid "Unrecognized field %d while decoding insn.\n" -msgstr "" - -#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 -#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 -#, c-format -msgid "Unrecognized field %d while getting int operand.\n" -msgstr "" - -#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 -#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 -#, c-format -msgid "Unrecognized field %d while getting vma operand.\n" -msgstr "" - -#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 -#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 -#, c-format -msgid "Unrecognized field %d while setting int operand.\n" -msgstr "" - -#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 -#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 -#, c-format -msgid "Unrecognized field %d while setting vma operand.\n" -msgstr "" - -#: frv-asm.c:365 -msgid "register number must be even" -msgstr "" - -#: h8300-dis.c:377 -#, c-format -msgid "Hmmmm 0x%x" -msgstr "" - -#: h8300-dis.c:760 -#, c-format -msgid "Don't understand 0x%x \n" -msgstr "" - -#: h8500-dis.c:143 -#, c-format -msgid "can't cope with insert %d\n" -msgstr "" - -#. Couldn't understand anything. -#: h8500-dis.c:350 -#, c-format -msgid "%02x\t\t*unknown*" -msgstr "" - -#: i386-dis.c:1699 -msgid "<internal disassembler error>" -msgstr "" - -#: ia64-gen.c:295 -#, c-format -msgid "%s: Error: " -msgstr "" - -#: ia64-gen.c:308 -#, c-format -msgid "%s: Warning: " -msgstr "" - -#: ia64-gen.c:494 ia64-gen.c:728 -#, c-format -msgid "multiple note %s not handled\n" -msgstr "" - -#: ia64-gen.c:605 -msgid "can't find ia64-ic.tbl for reading\n" -msgstr "" - -#: ia64-gen.c:810 -#, c-format -msgid "can't find %s for reading\n" -msgstr "" - -#: ia64-gen.c:1034 -#, c-format -msgid "" -"most recent format '%s'\n" -"appears more restrictive than '%s'\n" -msgstr "" - -#: ia64-gen.c:1045 -#, c-format -msgid "overlapping field %s->%s\n" -msgstr "" - -#: ia64-gen.c:1236 -#, c-format -msgid "overwriting note %d with note %d (IC:%s)\n" -msgstr "" - -#: ia64-gen.c:1435 -#, c-format -msgid "don't know how to specify %% dependency %s\n" -msgstr "" - -#: ia64-gen.c:1457 -#, c-format -msgid "Don't know how to specify # dependency %s\n" -msgstr "" - -#: ia64-gen.c:1496 -#, c-format -msgid "IC:%s [%s] has no terminals or sub-classes\n" -msgstr "" - -#: ia64-gen.c:1499 -#, c-format -msgid "IC:%s has no terminals or sub-classes\n" -msgstr "" - -#: ia64-gen.c:1508 -#, c-format -msgid "no insns mapped directly to terminal IC %s [%s]" -msgstr "" - -#: ia64-gen.c:1511 -#, c-format -msgid "no insns mapped directly to terminal IC %s\n" -msgstr "" - -#: ia64-gen.c:1522 -#, c-format -msgid "class %s is defined but not used\n" -msgstr "" - -#: ia64-gen.c:1533 -#, c-format -msgid "Warning: rsrc %s (%s) has no chks%s\n" -msgstr "" - -#: ia64-gen.c:1537 -#, c-format -msgid "rsrc %s (%s) has no regs\n" -msgstr "" - -#: ia64-gen.c:2436 -#, c-format -msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" -msgstr "" - -#: ia64-gen.c:2464 -#, c-format -msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" -msgstr "" - -#: ia64-gen.c:2478 -#, c-format -msgid "opcode %s has no class (ops %d %d %d)\n" -msgstr "" - -#: ia64-gen.c:2789 -#, c-format -msgid "unable to change directory to \"%s\", errno = %s\n" -msgstr "" - -#. We've been passed a w. Return with an error message so that -#. cgen will try the next parsing option. -#: ip2k-asm.c:92 -msgid "W keyword invalid in FR operand slot." -msgstr "" - -#. Invalid offset present. -#: ip2k-asm.c:122 -msgid "offset(IP) is not a valid form" -msgstr "" - -#. Found something there in front of (DP) but it's out -#. of range. -#: ip2k-asm.c:175 -msgid "(DP) offset out of range." -msgstr "" - -#. Found something there in front of (SP) but it's out -#. of range. -#: ip2k-asm.c:221 -msgid "(SP) offset out of range." -msgstr "" - -#: ip2k-asm.c:241 -msgid "illegal use of parentheses" -msgstr "" - -#: ip2k-asm.c:248 -msgid "operand out of range (not between 1 and 255)" -msgstr "" - -#. Something is very wrong. opindex has to be one of the above. -#: ip2k-asm.c:273 -msgid "parse_addr16: invalid opindex." -msgstr "" - -#: ip2k-asm.c:353 -msgid "Byte address required. - must be even." -msgstr "" - -#: ip2k-asm.c:362 -msgid "cgen_parse_address returned a symbol. Literal required." -msgstr "" - -#: ip2k-asm.c:420 -#, c-format -msgid "%operator operand is not a symbol" -msgstr "" - -#: ip2k-asm.c:474 -msgid "Attempt to find bit index of 0" -msgstr "" - -#: iq2000-asm.c:110 iq2000-asm.c:141 -msgid "immediate value cannot be register" -msgstr "" - -#: iq2000-asm.c:120 iq2000-asm.c:151 -msgid "immediate value out of range" -msgstr "" - -#: iq2000-asm.c:180 -msgid "21-bit offset out of range" -msgstr "" - -#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 -msgid "missing `)'" -msgstr "" - -#: m10200-dis.c:199 -#, c-format -msgid "unknown\t0x%02x" -msgstr "" - -#: m10200-dis.c:339 -#, c-format -msgid "unknown\t0x%04lx" -msgstr "" - -#: m10300-dis.c:766 -#, c-format -msgid "unknown\t0x%04x" -msgstr "" - -#: m68k-dis.c:429 -#, c-format -msgid "<internal error in opcode table: %s %s>\n" -msgstr "" - -#: m68k-dis.c:1007 -#, c-format -msgid "<function code %d>" -msgstr "" - -#: m88k-dis.c:746 -#, c-format -msgid "# <dis error: %08x>" -msgstr "" - -#: mips-dis.c:703 -msgid "# internal error, incomplete extension sequence (+)" -msgstr "" - -#: mips-dis.c:746 -#, c-format -msgid "# internal error, undefined extension sequence (+%c)" -msgstr "" - -#: mips-dis.c:1004 -#, c-format -msgid "# internal error, undefined modifier(%c)" -msgstr "" - -#: mips-dis.c:1755 -#, c-format -msgid "# internal disassembler error, unrecognised modifier (%c)" -msgstr "" - -#: mips-dis.c:1767 -msgid "" -"\n" -"The following MIPS specific disassembler options are supported for use\n" -"with the -M switch (multiple options should be separated by commas):\n" -msgstr "" - -#: mips-dis.c:1771 -msgid "" -"\n" -" gpr-names=ABI Print GPR names according to specified ABI.\n" -" Default: based on binary being disassembled.\n" -msgstr "" - -#: mips-dis.c:1775 -msgid "" -"\n" -" fpr-names=ABI Print FPR names according to specified ABI.\n" -" Default: numeric.\n" -msgstr "" - -#: mips-dis.c:1779 -msgid "" -"\n" -" cp0-names=ARCH Print CP0 register names according to\n" -" specified architecture.\n" -" Default: based on binary being disassembled.\n" -msgstr "" - -#: mips-dis.c:1784 -msgid "" -"\n" -" hwr-names=ARCH Print HWR names according to specified \n" -"\t\t\t architecture.\n" -" Default: based on binary being disassembled.\n" -msgstr "" - -#: mips-dis.c:1789 -msgid "" -"\n" -" reg-names=ABI Print GPR and FPR names according to\n" -" specified ABI.\n" -msgstr "" - -#: mips-dis.c:1793 -msgid "" -"\n" -" reg-names=ARCH Print CP0 register and HWR names according to\n" -" specified architecture.\n" -msgstr "" - -#: mips-dis.c:1797 -msgid "" -"\n" -" For the options above, the following values are supported for \"ABI\":\n" -" " -msgstr "" - -#: mips-dis.c:1802 mips-dis.c:1810 mips-dis.c:1812 -msgid "\n" -msgstr "" - -#: mips-dis.c:1804 -msgid "" -"\n" -" For the options above, The following values are supported for \"ARCH\":\n" -" " -msgstr "" - -#: mmix-dis.c:34 -#, c-format -msgid "Bad case %d (%s) in %s:%d\n" -msgstr "" - -#: mmix-dis.c:44 -#, c-format -msgid "Internal: Non-debugged code (test-case missing): %s:%d" -msgstr "" - -#: mmix-dis.c:53 -msgid "(unknown)" -msgstr "" - -#: mmix-dis.c:519 -#, c-format -msgid "*unknown operands type: %d*" -msgstr "" - -#. I and Z are output operands and can`t be immediate -#. * A is an address and we can`t have the address of -#. * an immediate either. We don't know how much to increase -#. * aoffsetp by since whatever generated this is broken -#. * anyway! -#. -#: ns32k-dis.c:631 -msgid "$<undefined>" -msgstr "" - -#: ppc-opc.c:781 ppc-opc.c:809 -msgid "invalid conditional option" -msgstr "" - -#: ppc-opc.c:811 -msgid "attempt to set y bit when using + or - modifier" -msgstr "" - -#: ppc-opc.c:840 -msgid "offset not a multiple of 16" -msgstr "" - -#: ppc-opc.c:860 -msgid "offset not a multiple of 2" -msgstr "" - -#: ppc-opc.c:862 -msgid "offset greater than 62" -msgstr "" - -#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975 -msgid "offset not a multiple of 4" -msgstr "" - -#: ppc-opc.c:883 -msgid "offset greater than 124" -msgstr "" - -#: ppc-opc.c:902 -msgid "offset not a multiple of 8" -msgstr "" - -#: ppc-opc.c:904 -msgid "offset greater than 248" -msgstr "" - -#: ppc-opc.c:950 -msgid "offset not between -2048 and 2047" -msgstr "" - -#: ppc-opc.c:973 -msgid "offset not between -8192 and 8191" -msgstr "" - -#: ppc-opc.c:1011 -msgid "ignoring invalid mfcr mask" -msgstr "" - -#: ppc-opc.c:1059 -msgid "ignoring least significant bits in branch offset" -msgstr "" - -#: ppc-opc.c:1090 ppc-opc.c:1125 -msgid "illegal bitmask" -msgstr "" - -#: ppc-opc.c:1192 -msgid "value out of range" -msgstr "" - -#: ppc-opc.c:1262 -msgid "index register in load range" -msgstr "" - -#: ppc-opc.c:1279 -msgid "source and target register operands must be different" -msgstr "" - -#: ppc-opc.c:1294 -msgid "invalid register operand when updating" -msgstr "" - -#: ppc-opc.c:1335 -msgid "target register operand must be even" -msgstr "" - -#: ppc-opc.c:1350 -msgid "source register operand must be even" -msgstr "" - -#. Mark as non-valid instruction. -#: sparc-dis.c:760 -msgid "unknown" -msgstr "" - -#: sparc-dis.c:835 -#, c-format -msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -msgstr "" - -#: sparc-dis.c:846 -#, c-format -msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -msgstr "" - -#: sparc-dis.c:895 -#, c-format -msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" -msgstr "" - -#: v850-dis.c:221 -#, c-format -msgid "unknown operand shift: %x\n" -msgstr "" - -#: v850-dis.c:233 -#, c-format -msgid "unknown pop reg: %d\n" -msgstr "" - -#. The functions used to insert and extract complicated operands. -#. Note: There is a conspiracy between these functions and -#. v850_insert_operand() in gas/config/tc-v850.c. Error messages -#. containing the string 'out of range' will be ignored unless a -#. specific command line option is given to GAS. -#: v850-opc.c:68 -msgid "displacement value is not in range and is not aligned" -msgstr "" - -#: v850-opc.c:69 -msgid "displacement value is out of range" -msgstr "" - -#: v850-opc.c:70 -msgid "displacement value is not aligned" -msgstr "" - -#: v850-opc.c:72 -msgid "immediate value is out of range" -msgstr "" - -#: v850-opc.c:83 -msgid "branch value not in range and to odd offset" -msgstr "" - -#: v850-opc.c:85 v850-opc.c:117 -msgid "branch value out of range" -msgstr "" - -#: v850-opc.c:88 v850-opc.c:120 -msgid "branch to odd offset" -msgstr "" - -#: v850-opc.c:115 -msgid "branch value not in range and to an odd offset" -msgstr "" - -#: v850-opc.c:346 -msgid "invalid register for stack adjustment" -msgstr "" - -#: v850-opc.c:370 -msgid "immediate value not in range and not even" -msgstr "" - -#: v850-opc.c:375 -msgid "immediate value must be even" -msgstr "" - -#: xstormy16-asm.c:76 -msgid "Bad register in preincrement" -msgstr "" - -#: xstormy16-asm.c:81 -msgid "Bad register in postincrement" -msgstr "" - -#: xstormy16-asm.c:83 -msgid "Bad register name" -msgstr "" - -#: xstormy16-asm.c:87 -msgid "Label conflicts with register name" -msgstr "" - -#: xstormy16-asm.c:91 -msgid "Label conflicts with `Rx'" -msgstr "" - -#: xstormy16-asm.c:93 -msgid "Bad immediate expression" -msgstr "" - -#: xstormy16-asm.c:115 -msgid "No relocation for small immediate" -msgstr "" - -#: xstormy16-asm.c:125 -msgid "Small operand was not an immediate number" -msgstr "" - -#: xstormy16-asm.c:164 -msgid "Operand is not a symbol" -msgstr "" - -#: xstormy16-asm.c:172 -msgid "Syntax error: No trailing ')'" -msgstr "" diff --git a/contrib/binutils/opcodes/ppc-dis.c b/contrib/binutils/opcodes/ppc-dis.c deleted file mode 100644 index 4d48b9d..0000000 --- a/contrib/binutils/opcodes/ppc-dis.c +++ /dev/null @@ -1,315 +0,0 @@ -/* ppc-dis.c -- Disassemble PowerPC instructions - Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004 - Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/ppc.h" - -/* This file provides several disassembler functions, all of which use - the disassembler interface defined in dis-asm.h. Several functions - are provided because this file handles disassembly for the PowerPC - in both big and little endian mode and also for the POWER (RS/6000) - chip. */ - -static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int); - -struct dis_private { - /* Stash the result of parsing disassembler_options here. */ - int dialect; -}; - -/* Determine which set of machines to disassemble for. PPC403/601 or - BookE. For convenience, also disassemble instructions supported - by the AltiVec vector unit. */ - -static int -powerpc_dialect (struct disassemble_info *info) -{ - int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC; - - if (BFD_DEFAULT_TARGET_SIZE == 64) - dialect |= PPC_OPCODE_64; - - if (info->disassembler_options - && strstr (info->disassembler_options, "booke") != NULL) - dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; - else if ((info->mach == bfd_mach_ppc_e500) - || (info->disassembler_options - && strstr (info->disassembler_options, "e500") != NULL)) - { - dialect |= PPC_OPCODE_BOOKE - | PPC_OPCODE_SPE | PPC_OPCODE_ISEL - | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK - | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK - | PPC_OPCODE_RFMCI; - /* efs* and AltiVec conflict. */ - dialect &= ~PPC_OPCODE_ALTIVEC; - } - else if (info->disassembler_options - && strstr (info->disassembler_options, "efs") != NULL) - { - dialect |= PPC_OPCODE_EFS; - /* efs* and AltiVec conflict. */ - dialect &= ~PPC_OPCODE_ALTIVEC; - } - else - dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC - | PPC_OPCODE_COMMON); - - if (info->disassembler_options - && strstr (info->disassembler_options, "power4") != NULL) - dialect |= PPC_OPCODE_POWER4; - - if (info->disassembler_options - && strstr (info->disassembler_options, "any") != NULL) - dialect |= PPC_OPCODE_ANY; - - if (info->disassembler_options) - { - if (strstr (info->disassembler_options, "32") != NULL) - dialect &= ~PPC_OPCODE_64; - else if (strstr (info->disassembler_options, "64") != NULL) - dialect |= PPC_OPCODE_64; - } - - ((struct dis_private *) &info->private_data)->dialect = dialect; - return dialect; -} - -/* Print a big endian PowerPC instruction. */ - -int -print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) -{ - int dialect = ((struct dis_private *) &info->private_data)->dialect; - return print_insn_powerpc (memaddr, info, 1, dialect); -} - -/* Print a little endian PowerPC instruction. */ - -int -print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) -{ - int dialect = ((struct dis_private *) &info->private_data)->dialect; - return print_insn_powerpc (memaddr, info, 0, dialect); -} - -/* Print a POWER (RS/6000) instruction. */ - -int -print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) -{ - return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); -} - -/* Print a PowerPC or POWER instruction. */ - -static int -print_insn_powerpc (bfd_vma memaddr, - struct disassemble_info *info, - int bigendian, - int dialect) -{ - bfd_byte buffer[4]; - int status; - unsigned long insn; - const struct powerpc_opcode *opcode; - const struct powerpc_opcode *opcode_end; - unsigned long op; - - if (dialect == 0) - dialect = powerpc_dialect (info); - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - if (bigendian) - insn = bfd_getb32 (buffer); - else - insn = bfd_getl32 (buffer); - - /* Get the major opcode of the instruction. */ - op = PPC_OP (insn); - - /* Find the first match in the opcode table. We could speed this up - a bit by doing a binary search on the major opcode. */ - opcode_end = powerpc_opcodes + powerpc_num_opcodes; - again: - for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) - { - unsigned long table_op; - const unsigned char *opindex; - const struct powerpc_operand *operand; - int invalid; - int need_comma; - int need_paren; - - table_op = PPC_OP (opcode->opcode); - if (op < table_op) - break; - if (op > table_op) - continue; - - if ((insn & opcode->mask) != opcode->opcode - || (opcode->flags & dialect) == 0) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - invalid = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - operand = powerpc_operands + *opindex; - if (operand->extract) - (*operand->extract) (insn, dialect, &invalid); - } - if (invalid) - continue; - - /* The instruction is valid. */ - if (opcode->operands[0] != 0) - (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); - else - (*info->fprintf_func) (info->stream, "%s", opcode->name); - - /* Now extract and print the operands. */ - need_comma = 0; - need_paren = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - long value; - - operand = powerpc_operands + *opindex; - - /* Operands that are marked FAKE are simply ignored. We - already made sure that the extract function considered - the instruction to be valid. */ - if ((operand->flags & PPC_OPERAND_FAKE) != 0) - continue; - - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, dialect, &invalid); - else - { - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & PPC_OPERAND_SIGNED) != 0 - && (value & (1 << (operand->bits - 1))) != 0) - value -= 1 << operand->bits; - } - - /* If the operand is optional, and the value is zero, don't - print anything. */ - if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 - && (operand->flags & PPC_OPERAND_NEXT) == 0 - && value == 0) - continue; - - if (need_comma) - { - (*info->fprintf_func) (info->stream, ","); - need_comma = 0; - } - - /* Print the operand as directed by the flags. */ - if ((operand->flags & PPC_OPERAND_GPR) != 0 - || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) - (*info->fprintf_func) (info->stream, "r%ld", value); - else if ((operand->flags & PPC_OPERAND_FPR) != 0) - (*info->fprintf_func) (info->stream, "f%ld", value); - else if ((operand->flags & PPC_OPERAND_VR) != 0) - (*info->fprintf_func) (info->stream, "v%ld", value); - else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) - (*info->print_address_func) (memaddr + value, info); - else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if ((operand->flags & PPC_OPERAND_CR) == 0 - || (dialect & PPC_OPCODE_PPC) == 0) - (*info->fprintf_func) (info->stream, "%ld", value); - else - { - if (operand->bits == 3) - (*info->fprintf_func) (info->stream, "cr%d", value); - else - { - static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; - int cr; - int cc; - - cr = value >> 2; - if (cr != 0) - (*info->fprintf_func) (info->stream, "4*cr%d+", cr); - cc = value & 3; - (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); - } - } - - if (need_paren) - { - (*info->fprintf_func) (info->stream, ")"); - need_paren = 0; - } - - if ((operand->flags & PPC_OPERAND_PARENS) == 0) - need_comma = 1; - else - { - (*info->fprintf_func) (info->stream, "("); - need_paren = 1; - } - } - - /* We have found and printed an instruction; return. */ - return 4; - } - - if ((dialect & PPC_OPCODE_ANY) != 0) - { - dialect = ~PPC_OPCODE_ANY; - goto again; - } - - /* We could not find a match. */ - (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); - - return 4; -} - -void -print_ppc_disassembler_options (FILE *stream) -{ - fprintf (stream, "\n\ -The following PPC specific disassembler options are supported for use with\n\ -the -M switch:\n"); - - fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n"); - fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n"); - fprintf (stream, " efs Disassemble the EFS instructions\n"); - fprintf (stream, " power4 Disassemble the Power4 instructions\n"); - fprintf (stream, " 32 Do not disassemble 64-bit instructions\n"); - fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n"); -} diff --git a/contrib/binutils/opcodes/ppc-opc.c b/contrib/binutils/opcodes/ppc-opc.c deleted file mode 100644 index 2d0dee5..0000000 --- a/contrib/binutils/opcodes/ppc-opc.c +++ /dev/null @@ -1,4622 +0,0 @@ -/* ppc-opc.c -- PowerPC opcode list - Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004 - Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - - This file is part of GDB, GAS, and the GNU binutils. - - GDB, GAS, and the GNU binutils are free software; you can redistribute - them and/or modify them under the terms of the GNU General Public - License as published by the Free Software Foundation; either version - 2, or (at your option) any later version. - - GDB, GAS, and the GNU binutils are distributed in the hope that they - will be useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the Free - Software Foundation, 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/ppc.h" -#include "opintl.h" - -/* This file holds the PowerPC opcode table. The opcode table - includes almost all of the extended instruction mnemonics. This - permits the disassembler to use them, and simplifies the assembler - logic, at the cost of increasing the table size. The table is - strictly constant data, so the compiler should be able to put it in - the .text section. - - This file also holds the operand table. All knowledge about - inserting operands into instructions and vice-versa is kept in this - file. */ - -/* Local insertion and extraction functions. */ - -static unsigned long insert_bat (unsigned long, long, int, const char **); -static long extract_bat (unsigned long, int, int *); -static unsigned long insert_bba (unsigned long, long, int, const char **); -static long extract_bba (unsigned long, int, int *); -static unsigned long insert_bd (unsigned long, long, int, const char **); -static long extract_bd (unsigned long, int, int *); -static unsigned long insert_bdm (unsigned long, long, int, const char **); -static long extract_bdm (unsigned long, int, int *); -static unsigned long insert_bdp (unsigned long, long, int, const char **); -static long extract_bdp (unsigned long, int, int *); -static unsigned long insert_bo (unsigned long, long, int, const char **); -static long extract_bo (unsigned long, int, int *); -static unsigned long insert_boe (unsigned long, long, int, const char **); -static long extract_boe (unsigned long, int, int *); -static unsigned long insert_dq (unsigned long, long, int, const char **); -static long extract_dq (unsigned long, int, int *); -static unsigned long insert_ds (unsigned long, long, int, const char **); -static long extract_ds (unsigned long, int, int *); -static unsigned long insert_de (unsigned long, long, int, const char **); -static long extract_de (unsigned long, int, int *); -static unsigned long insert_des (unsigned long, long, int, const char **); -static long extract_des (unsigned long, int, int *); -static unsigned long insert_fxm (unsigned long, long, int, const char **); -static long extract_fxm (unsigned long, int, int *); -static unsigned long insert_li (unsigned long, long, int, const char **); -static long extract_li (unsigned long, int, int *); -static unsigned long insert_mbe (unsigned long, long, int, const char **); -static long extract_mbe (unsigned long, int, int *); -static unsigned long insert_mb6 (unsigned long, long, int, const char **); -static long extract_mb6 (unsigned long, int, int *); -static unsigned long insert_nb (unsigned long, long, int, const char **); -static long extract_nb (unsigned long, int, int *); -static unsigned long insert_nsi (unsigned long, long, int, const char **); -static long extract_nsi (unsigned long, int, int *); -static unsigned long insert_ral (unsigned long, long, int, const char **); -static unsigned long insert_ram (unsigned long, long, int, const char **); -static unsigned long insert_raq (unsigned long, long, int, const char **); -static unsigned long insert_ras (unsigned long, long, int, const char **); -static unsigned long insert_rbs (unsigned long, long, int, const char **); -static long extract_rbs (unsigned long, int, int *); -static unsigned long insert_rsq (unsigned long, long, int, const char **); -static unsigned long insert_rtq (unsigned long, long, int, const char **); -static unsigned long insert_sh6 (unsigned long, long, int, const char **); -static long extract_sh6 (unsigned long, int, int *); -static unsigned long insert_spr (unsigned long, long, int, const char **); -static long extract_spr (unsigned long, int, int *); -static unsigned long insert_tbr (unsigned long, long, int, const char **); -static long extract_tbr (unsigned long, int, int *); -static unsigned long insert_ev2 (unsigned long, long, int, const char **); -static long extract_ev2 (unsigned long, int, int *); -static unsigned long insert_ev4 (unsigned long, long, int, const char **); -static long extract_ev4 (unsigned long, int, int *); -static unsigned long insert_ev8 (unsigned long, long, int, const char **); -static long extract_ev8 (unsigned long, int, int *); - -/* The operands table. - - The fields are bits, shift, insert, extract, flags. - - We used to put parens around the various additions, like the one - for BA just below. However, that caused trouble with feeble - compilers with a limit on depth of a parenthesized expression, like - (reportedly) the compiler in Microsoft Developer Studio 5. So we - omit the parens, since the macros are never used in a context where - the addition will be ambiguous. */ - -const struct powerpc_operand powerpc_operands[] = -{ - /* The zero index is used to indicate the end of the list of - operands. */ -#define UNUSED 0 - { 0, 0, 0, 0, 0 }, - - /* The BA field in an XL form instruction. */ -#define BA UNUSED + 1 -#define BA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_CR }, - - /* The BA field in an XL form instruction when it must be the same - as the BT field in the same instruction. */ -#define BAT BA + 1 - { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, - - /* The BB field in an XL form instruction. */ -#define BB BAT + 1 -#define BB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_CR }, - - /* The BB field in an XL form instruction when it must be the same - as the BA field in the same instruction. */ -#define BBA BB + 1 - { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, - - /* The BD field in a B form instruction. The lower two bits are - forced to zero. */ -#define BD BBA + 1 - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when absolute addressing is - used. */ -#define BDA BD + 1 - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDM BDA + 1 - { 16, 0, insert_bdm, extract_bdm, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the - modifier is used - and absolute address is used. */ -#define BDMA BDM + 1 - { 16, 0, insert_bdm, extract_bdm, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used. - This sets the y bit of the BO field appropriately. */ -#define BDP BDMA + 1 - { 16, 0, insert_bdp, extract_bdp, - PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The BD field in a B form instruction when the + modifier is used - and absolute addressing is used. */ -#define BDPA BDP + 1 - { 16, 0, insert_bdp, extract_bdp, - PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The BF field in an X or XL form instruction. */ -#define BF BDPA + 1 - { 3, 23, 0, 0, PPC_OPERAND_CR }, - - /* An optional BF field. This is used for comparison instructions, - in which an omitted BF field is taken as zero. */ -#define OBF BF + 1 - { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The BFA field in an X or XL form instruction. */ -#define BFA OBF + 1 - { 3, 18, 0, 0, PPC_OPERAND_CR }, - - /* The BI field in a B form or XL form instruction. */ -#define BI BFA + 1 -#define BI_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_CR }, - - /* The BO field in a B form instruction. Certain values are - illegal. */ -#define BO BI + 1 -#define BO_MASK (0x1f << 21) - { 5, 21, insert_bo, extract_bo, 0 }, - - /* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. */ -#define BOE BO + 1 - { 5, 21, insert_boe, extract_boe, 0 }, - - /* The BT field in an X or XL form instruction. */ -#define BT BOE + 1 - { 5, 21, 0, 0, PPC_OPERAND_CR }, - - /* The condition register number portion of the BI field in a B form - or XL form instruction. This is used for the extended - conditional branch mnemonics, which set the lower two bits of the - BI field. This field is optional. */ -#define CR BT + 1 - { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, - - /* The CRB field in an X form instruction. */ -#define CRB CR + 1 - { 5, 6, 0, 0, 0 }, - - /* The CRFD field in an X form instruction. */ -#define CRFD CRB + 1 - { 3, 23, 0, 0, PPC_OPERAND_CR }, - - /* The CRFS field in an X form instruction. */ -#define CRFS CRFD + 1 - { 3, 0, 0, 0, PPC_OPERAND_CR }, - - /* The CT field in an X form instruction. */ -#define CT CRFS + 1 - { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, - - /* The D field in a D form instruction. This is a displacement off - a register, and implies that the next operand is a register in - parentheses. */ -#define D CT + 1 - { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The DE field in a DE form instruction. This is like D, but is 12 - bits only. */ -#define DE D + 1 - { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS }, - - /* The DES field in a DES form instruction. This is like DS, but is 14 - bits only (12 stored.) */ -#define DES DE + 1 - { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - - /* The DQ field in a DQ form instruction. This is like D, but the - lower four bits are forced to zero. */ -#define DQ DES + 1 - { 16, 0, insert_dq, extract_dq, - PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, - - /* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ -#define DS DQ + 1 - { 16, 0, insert_ds, extract_ds, - PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, - - /* The E field in a wrteei instruction. */ -#define E DS + 1 - { 1, 15, 0, 0, 0 }, - - /* The FL1 field in a POWER SC form instruction. */ -#define FL1 E + 1 - { 4, 12, 0, 0, 0 }, - - /* The FL2 field in a POWER SC form instruction. */ -#define FL2 FL1 + 1 - { 3, 2, 0, 0, 0 }, - - /* The FLM field in an XFL form instruction. */ -#define FLM FL2 + 1 - { 8, 17, 0, 0, 0 }, - - /* The FRA field in an X or A form instruction. */ -#define FRA FLM + 1 -#define FRA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_FPR }, - - /* The FRB field in an X or A form instruction. */ -#define FRB FRA + 1 -#define FRB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_FPR }, - - /* The FRC field in an A form instruction. */ -#define FRC FRB + 1 -#define FRC_MASK (0x1f << 6) - { 5, 6, 0, 0, PPC_OPERAND_FPR }, - - /* The FRS field in an X form instruction or the FRT field in a D, X - or A form instruction. */ -#define FRS FRC + 1 -#define FRT FRS - { 5, 21, 0, 0, PPC_OPERAND_FPR }, - - /* The FXM field in an XFX instruction. */ -#define FXM FRS + 1 -#define FXM_MASK (0xff << 12) - { 8, 12, insert_fxm, extract_fxm, 0 }, - - /* Power4 version for mfcr. */ -#define FXM4 FXM + 1 - { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, - - /* The L field in a D or X form instruction. */ -#define L FXM4 + 1 - { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL }, - - /* The LEV field in a POWER SC form instruction. */ -#define LEV L + 1 - { 7, 5, 0, 0, 0 }, - - /* The LI field in an I form instruction. The lower two bits are - forced to zero. */ -#define LI LEV + 1 - { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, - - /* The LI field in an I form instruction when used as an absolute - address. */ -#define LIA LI + 1 - { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, - - /* The LS field in an X (sync) form instruction. */ -#define LS LIA + 1 - { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL }, - - /* The MB field in an M form instruction. */ -#define MB LS + 1 -#define MB_MASK (0x1f << 6) - { 5, 6, 0, 0, 0 }, - - /* The ME field in an M form instruction. */ -#define ME MB + 1 -#define ME_MASK (0x1f << 1) - { 5, 1, 0, 0, 0 }, - - /* The MB and ME fields in an M form instruction expressed a single - operand which is a bitmask indicating which bits to select. This - is a two operand form using PPC_OPERAND_NEXT. See the - description in opcode/ppc.h for what this means. */ -#define MBE ME + 1 - { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, - { 32, 0, insert_mbe, extract_mbe, 0 }, - - /* The MB or ME field in an MD or MDS form instruction. The high - bit is wrapped to the low end. */ -#define MB6 MBE + 2 -#define ME6 MB6 -#define MB6_MASK (0x3f << 5) - { 6, 5, insert_mb6, extract_mb6, 0 }, - - /* The MO field in an mbar instruction. */ -#define MO MB6 + 1 - { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, - - /* The NB field in an X form instruction. The value 32 is stored as - 0. */ -#define NB MO + 1 - { 6, 11, insert_nb, extract_nb, 0 }, - - /* The NSI field in a D form instruction. This is the same as the - SI field, only negated. */ -#define NSI NB + 1 - { 16, 0, insert_nsi, extract_nsi, - PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, - - /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ -#define RA NSI + 1 -#define RA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_GPR }, - - /* As above, but 0 in the RA field means zero, not r0. */ -#define RA0 RA + 1 - { 5, 16, 0, 0, PPC_OPERAND_GPR_0 }, - - /* The RA field in the DQ form lq instruction, which has special - value restrictions. */ -#define RAQ RA0 + 1 - { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 }, - - /* The RA field in a D or X form instruction which is an updating - load, which means that the RA field may not be zero and may not - equal the RT field. */ -#define RAL RAQ + 1 - { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 }, - - /* The RA field in an lmw instruction, which has special value - restrictions. */ -#define RAM RAL + 1 - { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 }, - - /* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ -#define RAS RAM + 1 - { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 }, - - /* The RA field of the tlbwe instruction, which is optional. */ -#define RAOPT RAS + 1 - { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, - - /* The RB field in an X, XO, M, or MDS form instruction. */ -#define RB RAOPT + 1 -#define RB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_GPR }, - - /* The RB field in an X form instruction when it must be the same as - the RS field in the instruction. This is used for extended - mnemonics like mr. */ -#define RBS RB + 1 - { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, - - /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form - instruction or the RT field in a D, DS, X, XFX or XO form - instruction. */ -#define RS RBS + 1 -#define RT RS -#define RT_MASK (0x1f << 21) - { 5, 21, 0, 0, PPC_OPERAND_GPR }, - - /* The RS field of the DS form stq instruction, which has special - value restrictions. */ -#define RSQ RS + 1 - { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 }, - - /* The RT field of the DQ form lq instruction, which has special - value restrictions. */ -#define RTQ RSQ + 1 - { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 }, - - /* The RS field of the tlbwe instruction, which is optional. */ -#define RSO RTQ + 1 - { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, - - /* The SH field in an X or M form instruction. */ -#define SH RSO + 1 -#define SH_MASK (0x1f << 11) - { 5, 11, 0, 0, 0 }, - - /* The SH field in an MD form instruction. This is split. */ -#define SH6 SH + 1 -#define SH6_MASK ((0x1f << 11) | (1 << 1)) - { 6, 1, insert_sh6, extract_sh6, 0 }, - - /* The SH field of the tlbwe instruction, which is optional. */ -#define SHO SH6 + 1 - { 5, 11,0, 0, PPC_OPERAND_OPTIONAL }, - - /* The SI field in a D form instruction. */ -#define SI SHO + 1 - { 16, 0, 0, 0, PPC_OPERAND_SIGNED }, - - /* The SI field in a D form instruction when we accept a wide range - of positive values. */ -#define SISIGNOPT SI + 1 - { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, - - /* The SPR field in an XFX form instruction. This is flipped--the - lower 5 bits are stored in the upper 5 and vice- versa. */ -#define SPR SISIGNOPT + 1 -#define PMR SPR -#define SPR_MASK (0x3ff << 11) - { 10, 11, insert_spr, extract_spr, 0 }, - - /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ -#define SPRBAT SPR + 1 -#define SPRBAT_MASK (0x3 << 17) - { 2, 17, 0, 0, 0 }, - - /* The SPRG register number in an XFX form m[ft]sprg instruction. */ -#define SPRG SPRBAT + 1 -#define SPRG_MASK (0x3 << 16) - { 2, 16, 0, 0, 0 }, - - /* The SR field in an X form instruction. */ -#define SR SPRG + 1 - { 4, 16, 0, 0, 0 }, - - /* The STRM field in an X AltiVec form instruction. */ -#define STRM SR + 1 -#define STRM_MASK (0x3 << 21) - { 2, 21, 0, 0, 0 }, - - /* The SV field in a POWER SC form instruction. */ -#define SV STRM + 1 - { 14, 2, 0, 0, 0 }, - - /* The TBR field in an XFX form instruction. This is like the SPR - field, but it is optional. */ -#define TBR SV + 1 - { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, - - /* The TO field in a D or X form instruction. */ -#define TO TBR + 1 -#define TO_MASK (0x1f << 21) - { 5, 21, 0, 0, 0 }, - - /* The U field in an X form instruction. */ -#define U TO + 1 - { 4, 12, 0, 0, 0 }, - - /* The UI field in a D form instruction. */ -#define UI U + 1 - { 16, 0, 0, 0, 0 }, - - /* The VA field in a VA, VX or VXR form instruction. */ -#define VA UI + 1 -#define VA_MASK (0x1f << 16) - { 5, 16, 0, 0, PPC_OPERAND_VR }, - - /* The VB field in a VA, VX or VXR form instruction. */ -#define VB VA + 1 -#define VB_MASK (0x1f << 11) - { 5, 11, 0, 0, PPC_OPERAND_VR }, - - /* The VC field in a VA form instruction. */ -#define VC VB + 1 -#define VC_MASK (0x1f << 6) - { 5, 6, 0, 0, PPC_OPERAND_VR }, - - /* The VD or VS field in a VA, VX, VXR or X form instruction. */ -#define VD VC + 1 -#define VS VD -#define VD_MASK (0x1f << 21) - { 5, 21, 0, 0, PPC_OPERAND_VR }, - - /* The SIMM field in a VX form instruction. */ -#define SIMM VD + 1 - { 5, 16, 0, 0, PPC_OPERAND_SIGNED}, - - /* The UIMM field in a VX form instruction. */ -#define UIMM SIMM + 1 - { 5, 16, 0, 0, 0 }, - - /* The SHB field in a VA form instruction. */ -#define SHB UIMM + 1 - { 4, 6, 0, 0, 0 }, - - /* The other UIMM field in a EVX form instruction. */ -#define EVUIMM SHB + 1 - { 5, 11, 0, 0, 0 }, - - /* The other UIMM field in a half word EVX form instruction. */ -#define EVUIMM_2 EVUIMM + 1 - { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS }, - - /* The other UIMM field in a word EVX form instruction. */ -#define EVUIMM_4 EVUIMM_2 + 1 - { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS }, - - /* The other UIMM field in a double EVX form instruction. */ -#define EVUIMM_8 EVUIMM_4 + 1 - { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS }, - - /* The WS field. */ -#define WS EVUIMM_8 + 1 -#define WS_MASK (0x7 << 11) - { 3, 11, 0, 0, 0 }, - - /* The L field in an mtmsrd instruction */ -#define MTMSRD_L WS + 1 - { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL }, - -}; - -/* The functions used to insert and extract complicated operands. */ - -/* The BA field in an XL form instruction when it must be the same as - the BT field in the same instruction. This operand is marked FAKE. - The insertion function just copies the BT field into the BA field, - and the extraction function just checks that the fields are the - same. */ - -static unsigned long -insert_bat (unsigned long insn, - long value ATTRIBUTE_UNUSED, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn | (((insn >> 21) & 0x1f) << 16); -} - -static long -extract_bat (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) -{ - if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The BB field in an XL form instruction when it must be the same as - the BA field in the same instruction. This operand is marked FAKE. - The insertion function just copies the BA field into the BB field, - and the extraction function just checks that the fields are the - same. */ - -static unsigned long -insert_bba (unsigned long insn, - long value ATTRIBUTE_UNUSED, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn | (((insn >> 16) & 0x1f) << 11); -} - -static long -extract_bba (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) -{ - if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The BD field in a B form instruction. The lower two bits are - forced to zero. */ - -static unsigned long -insert_bd (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn | (value & 0xfffc); -} - -static long -extract_bd (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn & 0xfffc) ^ 0x8000) - 0x8000; -} - -/* The BD field in a B form instruction when the - modifier is used. - This modifier means that the branch is not expected to be taken. - For chips built to versions of the architecture prior to version 2 - (ie. not Power4 compatible), we set the y bit of the BO field to 1 - if the offset is negative. When extracting, we require that the y - bit be 1 and that the offset be positive, since if the y bit is 0 - we just want to print the normal form of the instruction. - Power4 compatible targets use two bits, "a", and "t", instead of - the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, - "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 - in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 - for branch on CTR. We only handle the taken/not-taken hint here. */ - -static unsigned long -insert_bdm (unsigned long insn, - long value, - int dialect, - const char **errmsg ATTRIBUTE_UNUSED) -{ - if ((dialect & PPC_OPCODE_POWER4) == 0) - { - if ((value & 0x8000) != 0) - insn |= 1 << 21; - } - else - { - if ((insn & (0x14 << 21)) == (0x04 << 21)) - insn |= 0x02 << 21; - else if ((insn & (0x14 << 21)) == (0x10 << 21)) - insn |= 0x08 << 21; - } - return insn | (value & 0xfffc); -} - -static long -extract_bdm (unsigned long insn, - int dialect, - int *invalid) -{ - if ((dialect & PPC_OPCODE_POWER4) == 0) - { - if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) - *invalid = 1; - } - else - { - if ((insn & (0x17 << 21)) != (0x06 << 21) - && (insn & (0x1d << 21)) != (0x18 << 21)) - *invalid = 1; - } - - return ((insn & 0xfffc) ^ 0x8000) - 0x8000; -} - -/* The BD field in a B form instruction when the + modifier is used. - This is like BDM, above, except that the branch is expected to be - taken. */ - -static unsigned long -insert_bdp (unsigned long insn, - long value, - int dialect, - const char **errmsg ATTRIBUTE_UNUSED) -{ - if ((dialect & PPC_OPCODE_POWER4) == 0) - { - if ((value & 0x8000) == 0) - insn |= 1 << 21; - } - else - { - if ((insn & (0x14 << 21)) == (0x04 << 21)) - insn |= 0x03 << 21; - else if ((insn & (0x14 << 21)) == (0x10 << 21)) - insn |= 0x09 << 21; - } - return insn | (value & 0xfffc); -} - -static long -extract_bdp (unsigned long insn, - int dialect, - int *invalid) -{ - if ((dialect & PPC_OPCODE_POWER4) == 0) - { - if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) - *invalid = 1; - } - else - { - if ((insn & (0x17 << 21)) != (0x07 << 21) - && (insn & (0x1d << 21)) != (0x19 << 21)) - *invalid = 1; - } - - return ((insn & 0xfffc) ^ 0x8000) - 0x8000; -} - -/* Check for legal values of a BO field. */ - -static int -valid_bo (long value, int dialect) -{ - if ((dialect & PPC_OPCODE_POWER4) == 0) - { - /* Certain encodings have bits that are required to be zero. - These are (z must be zero, y may be anything): - 001zy - 011zy - 1z00y - 1z01y - 1z1zz - */ - switch (value & 0x14) - { - default: - case 0: - return 1; - case 0x4: - return (value & 0x2) == 0; - case 0x10: - return (value & 0x8) == 0; - case 0x14: - return value == 0x14; - } - } - else - { - /* Certain encodings have bits that are required to be zero. - These are (z must be zero, a & t may be anything): - 0000z - 0001z - 0100z - 0101z - 001at - 011at - 1a00t - 1a01t - 1z1zz - */ - if ((value & 0x14) == 0) - return (value & 0x1) == 0; - else if ((value & 0x14) == 0x14) - return value == 0x14; - else - return 1; - } -} - -/* The BO field in a B form instruction. Warn about attempts to set - the field to an illegal value. */ - -static unsigned long -insert_bo (unsigned long insn, - long value, - int dialect, - const char **errmsg) -{ - if (!valid_bo (value, dialect)) - *errmsg = _("invalid conditional option"); - return insn | ((value & 0x1f) << 21); -} - -static long -extract_bo (unsigned long insn, - int dialect, - int *invalid) -{ - long value; - - value = (insn >> 21) & 0x1f; - if (!valid_bo (value, dialect)) - *invalid = 1; - return value; -} - -/* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. When - extracting it, we force it to be even. */ - -static unsigned long -insert_boe (unsigned long insn, - long value, - int dialect, - const char **errmsg) -{ - if (!valid_bo (value, dialect)) - *errmsg = _("invalid conditional option"); - else if ((value & 1) != 0) - *errmsg = _("attempt to set y bit when using + or - modifier"); - - return insn | ((value & 0x1f) << 21); -} - -static long -extract_boe (unsigned long insn, - int dialect, - int *invalid) -{ - long value; - - value = (insn >> 21) & 0x1f; - if (!valid_bo (value, dialect)) - *invalid = 1; - return value & 0x1e; -} - -/* The DQ field in a DQ form instruction. This is like D, but the - lower four bits are forced to zero. */ - -static unsigned long -insert_dq (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 0xf) != 0) - *errmsg = _("offset not a multiple of 16"); - return insn | (value & 0xfff0); -} - -static long -extract_dq (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn & 0xfff0) ^ 0x8000) - 0x8000; -} - -static unsigned long -insert_ev2 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 1) != 0) - *errmsg = _("offset not a multiple of 2"); - if ((value > 62) != 0) - *errmsg = _("offset greater than 62"); - return insn | ((value & 0x3e) << 10); -} - -static long -extract_ev2 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (insn >> 10) & 0x3e; -} - -static unsigned long -insert_ev4 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 3) != 0) - *errmsg = _("offset not a multiple of 4"); - if ((value > 124) != 0) - *errmsg = _("offset greater than 124"); - return insn | ((value & 0x7c) << 9); -} - -static long -extract_ev4 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (insn >> 9) & 0x7c; -} - -static unsigned long -insert_ev8 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 7) != 0) - *errmsg = _("offset not a multiple of 8"); - if ((value > 248) != 0) - *errmsg = _("offset greater than 248"); - return insn | ((value & 0xf8) << 8); -} - -static long -extract_ev8 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (insn >> 8) & 0xf8; -} - -/* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ - -static unsigned long -insert_ds (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 3) != 0) - *errmsg = _("offset not a multiple of 4"); - return insn | (value & 0xfffc); -} - -static long -extract_ds (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn & 0xfffc) ^ 0x8000) - 0x8000; -} - -/* The DE field in a DE form instruction. */ - -static unsigned long -insert_de (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (value > 2047 || value < -2048) - *errmsg = _("offset not between -2048 and 2047"); - return insn | ((value << 4) & 0xfff0); -} - -static long -extract_de (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (insn & 0xfff0) >> 4; -} - -/* The DES field in a DES form instruction. */ - -static unsigned long -insert_des (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (value > 8191 || value < -8192) - *errmsg = _("offset not between -8192 and 8191"); - else if ((value & 3) != 0) - *errmsg = _("offset not a multiple of 4"); - return insn | ((value << 2) & 0xfff0); -} - -static long -extract_des (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000; -} - -/* FXM mask in mfcr and mtcrf instructions. */ - -static unsigned long -insert_fxm (unsigned long insn, - long value, - int dialect, - const char **errmsg) -{ - /* If the optional field on mfcr is missing that means we want to use - the old form of the instruction that moves the whole cr. In that - case we'll have VALUE zero. There doesn't seem to be a way to - distinguish this from the case where someone writes mfcr %r3,0. */ - if (value == 0) - ; - - /* If only one bit of the FXM field is set, we can use the new form - of the instruction, which is faster. Unlike the Power4 branch hint - encoding, this is not backward compatible. */ - else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value) - insn |= 1 << 20; - - /* Any other value on mfcr is an error. */ - else if ((insn & (0x3ff << 1)) == 19 << 1) - { - *errmsg = _("ignoring invalid mfcr mask"); - value = 0; - } - - return insn | ((value & 0xff) << 12); -} - -static long -extract_fxm (unsigned long insn, - int dialect, - int *invalid) -{ - long mask = (insn >> 12) & 0xff; - - /* Is this a Power4 insn? */ - if ((insn & (1 << 20)) != 0) - { - if ((dialect & PPC_OPCODE_POWER4) == 0) - *invalid = 1; - else - { - /* Exactly one bit of MASK should be set. */ - if (mask == 0 || (mask & -mask) != mask) - *invalid = 1; - } - } - - /* Check that non-power4 form of mfcr has a zero MASK. */ - else if ((insn & (0x3ff << 1)) == 19 << 1) - { - if (mask != 0) - *invalid = 1; - } - - return mask; -} - -/* The LI field in an I form instruction. The lower two bits are - forced to zero. */ - -static unsigned long -insert_li (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 3) != 0) - *errmsg = _("ignoring least significant bits in branch offset"); - return insn | (value & 0x3fffffc); -} - -static long -extract_li (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000; -} - -/* The MB and ME fields in an M form instruction expressed as a single - operand which is itself a bitmask. The extraction function always - marks it as invalid, since we never want to recognize an - instruction which uses a field of this type. */ - -static unsigned long -insert_mbe (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - unsigned long uval, mask; - int mb, me, mx, count, last; - - uval = value; - - if (uval == 0) - { - *errmsg = _("illegal bitmask"); - return insn; - } - - mb = 0; - me = 32; - if ((uval & 1) != 0) - last = 1; - else - last = 0; - count = 0; - - /* mb: location of last 0->1 transition */ - /* me: location of last 1->0 transition */ - /* count: # transitions */ - - for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) - { - if ((uval & mask) && !last) - { - ++count; - mb = mx; - last = 1; - } - else if (!(uval & mask) && last) - { - ++count; - me = mx; - last = 0; - } - } - if (me == 0) - me = 32; - - if (count != 2 && (count != 0 || ! last)) - *errmsg = _("illegal bitmask"); - - return insn | (mb << 6) | ((me - 1) << 1); -} - -static long -extract_mbe (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) -{ - long ret; - int mb, me; - int i; - - *invalid = 1; - - mb = (insn >> 6) & 0x1f; - me = (insn >> 1) & 0x1f; - if (mb < me + 1) - { - ret = 0; - for (i = mb; i <= me; i++) - ret |= 1L << (31 - i); - } - else if (mb == me + 1) - ret = ~0; - else /* (mb > me + 1) */ - { - ret = ~0; - for (i = me + 1; i < mb; i++) - ret &= ~(1L << (31 - i)); - } - return ret; -} - -/* The MB or ME field in an MD or MDS form instruction. The high bit - is wrapped to the low end. */ - -static unsigned long -insert_mb6 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn | ((value & 0x1f) << 6) | (value & 0x20); -} - -static long -extract_mb6 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn >> 6) & 0x1f) | (insn & 0x20); -} - -/* The NB field in an X form instruction. The value 32 is stored as - 0. */ - -static unsigned long -insert_nb (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (value < 0 || value > 32) - *errmsg = _("value out of range"); - if (value == 32) - value = 0; - return insn | ((value & 0x1f) << 11); -} - -static long -extract_nb (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - long ret; - - ret = (insn >> 11) & 0x1f; - if (ret == 0) - ret = 32; - return ret; -} - -/* The NSI field in a D form instruction. This is the same as the SI - field, only negated. The extraction function always marks it as - invalid, since we never want to recognize an instruction which uses - a field of this type. */ - -static unsigned long -insert_nsi (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn | (-value & 0xffff); -} - -static long -extract_nsi (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) -{ - *invalid = 1; - return -(((insn & 0xffff) ^ 0x8000) - 0x8000); -} - -/* The RA field in a D or X form instruction which is an updating - load, which means that the RA field may not be zero and may not - equal the RT field. */ - -static unsigned long -insert_ral (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (value == 0 - || (unsigned long) value == ((insn >> 21) & 0x1f)) - *errmsg = "invalid register operand when updating"; - return insn | ((value & 0x1f) << 16); -} - -/* The RA field in an lmw instruction, which has special value - restrictions. */ - -static unsigned long -insert_ram (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((unsigned long) value >= ((insn >> 21) & 0x1f)) - *errmsg = _("index register in load range"); - return insn | ((value & 0x1f) << 16); -} - -/* The RA field in the DQ form lq instruction, which has special - value restrictions. */ - -static unsigned long -insert_raq (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - long rtvalue = (insn & RT_MASK) >> 21; - - if (value == rtvalue) - *errmsg = _("source and target register operands must be different"); - return insn | ((value & 0x1f) << 16); -} - -/* The RA field in a D or X form instruction which is an updating - store or an updating floating point load, which means that the RA - field may not be zero. */ - -static unsigned long -insert_ras (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (value == 0) - *errmsg = _("invalid register operand when updating"); - return insn | ((value & 0x1f) << 16); -} - -/* The RB field in an X form instruction when it must be the same as - the RS field in the instruction. This is used for extended - mnemonics like mr. This operand is marked FAKE. The insertion - function just copies the BT field into the BA field, and the - extraction function just checks that the fields are the same. */ - -static unsigned long -insert_rbs (unsigned long insn, - long value ATTRIBUTE_UNUSED, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn | (((insn >> 21) & 0x1f) << 11); -} - -static long -extract_rbs (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid) -{ - if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) - *invalid = 1; - return 0; -} - -/* The RT field of the DQ form lq instruction, which has special - value restrictions. */ - -static unsigned long -insert_rtq (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 1) != 0) - *errmsg = _("target register operand must be even"); - return insn | ((value & 0x1f) << 21); -} - -/* The RS field of the DS form stq instruction, which has special - value restrictions. */ - -static unsigned long -insert_rsq (unsigned long insn, - long value ATTRIBUTE_UNUSED, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 1) != 0) - *errmsg = _("source register operand must be even"); - return insn | ((value & 0x1f) << 21); -} - -/* The SH field in an MD form instruction. This is split. */ - -static unsigned long -insert_sh6 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); -} - -static long -extract_sh6 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); -} - -/* The SPR field in an XFX form instruction. This is flipped--the - lower 5 bits are stored in the upper 5 and vice- versa. */ - -static unsigned long -insert_spr (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); -} - -static long -extract_spr (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); -} - -/* The TBR field in an XFX instruction. This is just like SPR, but it - is optional. When TBR is omitted, it must be inserted as 268 (the - magic number of the TB register). These functions treat 0 - (indicating an omitted optional operand) as 268. This means that - ``mftb 4,0'' is not handled correctly. This does not matter very - much, since the architecture manual does not define mftb as - accepting any values other than 268 or 269. */ - -#define TB (268) - -static unsigned long -insert_tbr (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - if (value == 0) - value = TB; - return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); -} - -static long -extract_tbr (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - long ret; - - ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); - if (ret == TB) - ret = 0; - return ret; -} - -/* Macros used to form opcodes. */ - -/* The main opcode. */ -#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) -#define OP_MASK OP (0x3f) - -/* The main opcode combined with a trap code in the TO field of a D - form instruction. Used for extended mnemonics for the trap - instructions. */ -#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) -#define OPTO_MASK (OP_MASK | TO_MASK) - -/* The main opcode combined with a comparison size bit in the L field - of a D form or X form instruction. Used for extended mnemonics for - the comparison instructions. */ -#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) -#define OPL_MASK OPL (0x3f,1) - -/* An A form instruction. */ -#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) -#define A_MASK A (0x3f, 0x1f, 1) - -/* An A_MASK with the FRB field fixed. */ -#define AFRB_MASK (A_MASK | FRB_MASK) - -/* An A_MASK with the FRC field fixed. */ -#define AFRC_MASK (A_MASK | FRC_MASK) - -/* An A_MASK with the FRA and FRC fields fixed. */ -#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) - -/* A B form instruction. */ -#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) -#define B_MASK B (0x3f, 1, 1) - -/* A B form instruction setting the BO field. */ -#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) -#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) - -/* A BBO_MASK with the y bit of the BO field removed. This permits - matching a conditional branch regardless of the setting of the y - bit. Similarly for the 'at' bits used for power4 branch hints. */ -#define Y_MASK (((unsigned long) 1) << 21) -#define AT1_MASK (((unsigned long) 3) << 21) -#define AT2_MASK (((unsigned long) 9) << 21) -#define BBOY_MASK (BBO_MASK &~ Y_MASK) -#define BBOAT_MASK (BBO_MASK &~ AT1_MASK) - -/* A B form instruction setting the BO field and the condition bits of - the BI field. */ -#define BBOCB(op, bo, cb, aa, lk) \ - (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) -#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) - -/* A BBOCB_MASK with the y bit of the BO field removed. */ -#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) -#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) -#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) - -/* A BBOYCB_MASK in which the BI field is fixed. */ -#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) -#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) - -/* An Context form instruction. */ -#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) -#define CTX_MASK CTX(0x3f, 0x7) - -/* An User Context form instruction. */ -#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) -#define UCTX_MASK UCTX(0x3f, 0x1f) - -/* The main opcode mask with the RA field clear. */ -#define DRA_MASK (OP_MASK | RA_MASK) - -/* A DS form instruction. */ -#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) -#define DS_MASK DSO (0x3f, 3) - -/* A DE form instruction. */ -#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) -#define DE_MASK DEO (0x3e, 0xf) - -/* An EVSEL form instruction. */ -#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) -#define EVSEL_MASK EVSEL(0x3f, 0xff) - -/* An M form instruction. */ -#define M(op, rc) (OP (op) | ((rc) & 1)) -#define M_MASK M (0x3f, 1) - -/* An M form instruction with the ME field specified. */ -#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) - -/* An M_MASK with the MB and ME fields fixed. */ -#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) - -/* An M_MASK with the SH and ME fields fixed. */ -#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) - -/* An MD form instruction. */ -#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) -#define MD_MASK MD (0x3f, 0x7, 1) - -/* An MD_MASK with the MB field fixed. */ -#define MDMB_MASK (MD_MASK | MB6_MASK) - -/* An MD_MASK with the SH field fixed. */ -#define MDSH_MASK (MD_MASK | SH6_MASK) - -/* An MDS form instruction. */ -#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) -#define MDS_MASK MDS (0x3f, 0xf, 1) - -/* An MDS_MASK with the MB field fixed. */ -#define MDSMB_MASK (MDS_MASK | MB6_MASK) - -/* An SC form instruction. */ -#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) -#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) - -/* An VX form instruction. */ -#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) - -/* The mask for an VX form instruction. */ -#define VX_MASK VX(0x3f, 0x7ff) - -/* An VA form instruction. */ -#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) - -/* The mask for an VA form instruction. */ -#define VXA_MASK VXA(0x3f, 0x3f) - -/* An VXR form instruction. */ -#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) - -/* The mask for a VXR form instruction. */ -#define VXR_MASK VXR(0x3f, 0x3ff, 1) - -/* An X form instruction. */ -#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) - -/* An X form instruction with the RC bit specified. */ -#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) - -/* The mask for an X form instruction. */ -#define X_MASK XRC (0x3f, 0x3ff, 1) - -/* An X_MASK with the RA field fixed. */ -#define XRA_MASK (X_MASK | RA_MASK) - -/* An X_MASK with the RB field fixed. */ -#define XRB_MASK (X_MASK | RB_MASK) - -/* An X_MASK with the RT field fixed. */ -#define XRT_MASK (X_MASK | RT_MASK) - -/* An X_MASK with the RA and RB fields fixed. */ -#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) - -/* An XRARB_MASK, but with the L bit clear. */ -#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) - -/* An X_MASK with the RT and RA fields fixed. */ -#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) - -/* An XRTRA_MASK, but with L bit clear. */ -#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) - -/* An X form comparison instruction. */ -#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) - -/* The mask for an X form comparison instruction. */ -#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) - -/* The mask for an X form comparison instruction with the L field - fixed. */ -#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) - -/* An X form trap instruction with the TO field specified. */ -#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) -#define XTO_MASK (X_MASK | TO_MASK) - -/* An X form tlb instruction with the SH field specified. */ -#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) -#define XTLB_MASK (X_MASK | SH_MASK) - -/* An X form sync instruction. */ -#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) - -/* An X form sync instruction with everything filled in except the LS field. */ -#define XSYNC_MASK (0xff9fffff) - -/* An X form AltiVec dss instruction. */ -#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) -#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) - -/* An XFL form instruction. */ -#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) -#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) - -/* An X form isel instruction. */ -#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) -#define XISEL_MASK XISEL(0x3f, 0x1f) - -/* An XL form instruction with the LK field set to 0. */ -#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) - -/* An XL form instruction which uses the LK field. */ -#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) - -/* The mask for an XL form instruction. */ -#define XL_MASK XLLK (0x3f, 0x3ff, 1) - -/* An XL form instruction which explicitly sets the BO field. */ -#define XLO(op, bo, xop, lk) \ - (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) -#define XLO_MASK (XL_MASK | BO_MASK) - -/* An XL form instruction which explicitly sets the y bit of the BO - field. */ -#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) -#define XLYLK_MASK (XL_MASK | Y_MASK) - -/* An XL form instruction which sets the BO field and the condition - bits of the BI field. */ -#define XLOCB(op, bo, cb, xop, lk) \ - (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) -#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) - -/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ -#define XLBB_MASK (XL_MASK | BB_MASK) -#define XLYBB_MASK (XLYLK_MASK | BB_MASK) -#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) - -/* An XL_MASK with the BO and BB fields fixed. */ -#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) - -/* An XL_MASK with the BO, BI and BB fields fixed. */ -#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) - -/* An XO form instruction. */ -#define XO(op, xop, oe, rc) \ - (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) -#define XO_MASK XO (0x3f, 0x1ff, 1, 1) - -/* An XO_MASK with the RB field fixed. */ -#define XORB_MASK (XO_MASK | RB_MASK) - -/* An XS form instruction. */ -#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) -#define XS_MASK XS (0x3f, 0x1ff, 1) - -/* A mask for the FXM version of an XFX form instruction. */ -#define XFXFXM_MASK (X_MASK | (1 << 11)) - -/* An XFX form instruction with the FXM field filled in. */ -#define XFXM(op, xop, fxm) \ - (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12)) - -/* An XFX form instruction with the SPR field filled in. */ -#define XSPR(op, xop, spr) \ - (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) -#define XSPR_MASK (X_MASK | SPR_MASK) - -/* An XFX form instruction with the SPR field filled in except for the - SPRBAT field. */ -#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) - -/* An XFX form instruction with the SPR field filled in except for the - SPRG field. */ -#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) - -/* An X form instruction with everything filled in except the E field. */ -#define XE_MASK (0xffff7fff) - -/* An X form user context instruction. */ -#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) -#define XUC_MASK XUC(0x3f, 0x1f) - -/* The BO encodings used in extended conditional branch mnemonics. */ -#define BODNZF (0x0) -#define BODNZFP (0x1) -#define BODZF (0x2) -#define BODZFP (0x3) -#define BODNZT (0x8) -#define BODNZTP (0x9) -#define BODZT (0xa) -#define BODZTP (0xb) - -#define BOF (0x4) -#define BOFP (0x5) -#define BOFM4 (0x6) -#define BOFP4 (0x7) -#define BOT (0xc) -#define BOTP (0xd) -#define BOTM4 (0xe) -#define BOTP4 (0xf) - -#define BODNZ (0x10) -#define BODNZP (0x11) -#define BODZ (0x12) -#define BODZP (0x13) -#define BODNZM4 (0x18) -#define BODNZP4 (0x19) -#define BODZM4 (0x1a) -#define BODZP4 (0x1b) - -#define BOU (0x14) - -/* The BI condition bit encodings used in extended conditional branch - mnemonics. */ -#define CBLT (0) -#define CBGT (1) -#define CBEQ (2) -#define CBSO (3) - -/* The TO encodings used in extended trap mnemonics. */ -#define TOLGT (0x1) -#define TOLLT (0x2) -#define TOEQ (0x4) -#define TOLGE (0x5) -#define TOLNL (0x5) -#define TOLLE (0x6) -#define TOLNG (0x6) -#define TOGT (0x8) -#define TOGE (0xc) -#define TONL (0xc) -#define TOLT (0x10) -#define TOLE (0x14) -#define TONG (0x14) -#define TONE (0x18) -#define TOU (0x1f) - -/* Smaller names for the flags so each entry in the opcodes table will - fit on a single line. */ -#undef PPC -#define PPC PPC_OPCODE_PPC -#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON -#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM -#define POWER4 PPC_OPCODE_POWER4 -#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC -#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC -#define PPC403 PPC_OPCODE_403 -#define PPC405 PPC403 -#define PPC440 PPC_OPCODE_440 -#define PPC750 PPC -#define PPC860 PPC -#define PPCVEC PPC_OPCODE_ALTIVEC -#define POWER PPC_OPCODE_POWER -#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 -#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 -#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 -#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON -#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 -#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 -#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON -#define MFDEC1 PPC_OPCODE_POWER -#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE -#define BOOKE PPC_OPCODE_BOOKE -#define BOOKE64 PPC_OPCODE_BOOKE64 -#define CLASSIC PPC_OPCODE_CLASSIC -#define PPCSPE PPC_OPCODE_SPE -#define PPCISEL PPC_OPCODE_ISEL -#define PPCEFS PPC_OPCODE_EFS -#define PPCBRLK PPC_OPCODE_BRLOCK -#define PPCPMR PPC_OPCODE_PMR -#define PPCCHLK PPC_OPCODE_CACHELCK -#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 -#define PPCRFMCI PPC_OPCODE_RFMCI - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK FLAGS { OPERANDS } - - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - FLAGS are flags indicated what processors support the instruction. - OPERANDS is the list of operands. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. */ - -const struct powerpc_opcode powerpc_opcodes[] = { -{ "attn", X(0,256), X_MASK, POWER4, { 0 } }, -{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, -{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, - -{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, -{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, -{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, -{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, - -{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, -{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, -{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, -{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, -{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, -{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, -{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, -{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, -{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, -{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, -{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, -{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, -{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, -{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, -{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, -{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, -{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, -{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, -{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, -{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, - -{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, -{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, -{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, -{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, -{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, -{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, -{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, -{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, -{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, -{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, -{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, - -{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, -{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, -{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, -{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, -{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, -{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, -{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, -{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, -{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, - -{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, -{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, -{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, -{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, -{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, -{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, -{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, -{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, -{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, -{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, -{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, - -{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, -{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, -{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, -{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, -{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, -{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, -{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, -{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, -{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, -{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, - -{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, -{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, -{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, -{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, - -{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, -{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, -{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, -{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, - -{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, - -{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, -{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, - -{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, - -{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, - -{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, - -{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, -{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, -{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, -{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, - -{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, -{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, - -{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, -{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, - -{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, -{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, - -{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, -{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, - -{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, -{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, -{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, -{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, -{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, -{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, - -{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, -{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, -{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, -{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, -{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, - -{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, -{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, -{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, -{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, -{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, -{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, -{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, -{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, -{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, -{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, -{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, -{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, -{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, -{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, -{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, -{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, -{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, -{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, -{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, -{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, -{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, -{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, -{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, -{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, -{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, -{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, -{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, -{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, -{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, -{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, -{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, -{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, -{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, -{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, -{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, -{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, -{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, -{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, -{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, -{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, -{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, -{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, -{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, -{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, -{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, -{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, -{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, -{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, -{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, -{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, -{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, -{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, -{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, -{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, -{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, -{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, -{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, -{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, -{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, -{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, -{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, -{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, -{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, -{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, -{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, -{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, -{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, -{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, -{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, -{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, - -{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, -{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, -{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, -{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, -{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, - -{ "b", B(18,0,0), B_MASK, COM, { LI } }, -{ "bl", B(18,0,1), B_MASK, COM, { LI } }, -{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, -{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, - -{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, - -{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, -{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, -{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, -{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, -{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, -{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, -{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, -{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, -{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, -{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, -{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } }, -{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } }, -{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, -{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, - -{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, - -{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, -{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, -{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, - -{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, -{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, - -{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, - -{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, - -{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, -{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, - -{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, -{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, - -{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, - -{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, - -{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, -{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, - -{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, - -{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, -{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, - -{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, -{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, -{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, -{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, -{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, -{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, -{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, -{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, -{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } }, -{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } }, -{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, -{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } }, -{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } }, - -{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, - -{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, - -{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, -{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, -{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, -{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, -{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, -{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, -{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, - -{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, -{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, - -{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, -{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, -{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, -{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, - -{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, -{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, -{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, -{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, -{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, -{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, - -{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, -{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, -{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, - -{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, -{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, -{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, -{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, -{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, -{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, - -{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, -{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, - -{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, -{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, - -{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, -{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, - -{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, -{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, -{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, -{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, - -{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, -{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, - -{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, -{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, - -{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, -{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, -{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, -{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, -{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, -{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, -{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, - -{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, -{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, - -{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, -{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, -{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, -{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, - -{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } }, -{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, - -{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } }, - -{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, - -{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } }, -{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, - -{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, -{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, -{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, - -{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, -{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, -{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, -{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, - -{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, -{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, - -{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, -{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, - -{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, -{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, - -{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, - -{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, -{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, -{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, - -{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, -{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, - -{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, - -{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, - -{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, -{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, - -{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, - -{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, -{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, - -{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, -{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, - -{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, -{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, -{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, -{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, -{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, -{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, -{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } }, - -{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, -{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, - -{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, - -{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, - -{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } }, - -{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, - -{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, - -{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, - -{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, -{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, -{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, -{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, - -{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, - -{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, - -{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, - -{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, -{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, -{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, -{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, - -{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, - -{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, - -{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, - -{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, - -{ "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }}, -{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, - -{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, - -{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, - -{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, - -{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, -{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, - -{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, - -{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, - -{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, -{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, - -{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, -{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, - -{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, - -{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, -{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, - -{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } }, - -{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, - -{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, -{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } }, - -{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, -{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, - -{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, - -{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, - -{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, - -{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, - -{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, - -{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } }, - -{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, -{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, - -{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, -{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, - -{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, - -{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, - -{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, - -{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, -{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, -{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, - -{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, -{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, -{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, - -{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, - -{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, - -{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, -{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, - -{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } }, - -{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } }, - -{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, - -{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, -{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, - -{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } }, - -{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, - -{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, -{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, - -{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, - -{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, - -{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, -{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, - -{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, - -{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, -{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } }, - -{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, - -{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, - -{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, -{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, - -{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, - -{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, -{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, -{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, -{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, -{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, -{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, -{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, -{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, -{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, -{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, -{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, -{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, -{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, -{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, -{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, -{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, -{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } }, - -{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }}, - -{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, -{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, -{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, -{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, -{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, -{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, -{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, -{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, -{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, -{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, -{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, -{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, -{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, -{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, -{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, -{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, -{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, -{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, -{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } }, -{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } }, -{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, -{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } }, -{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, -{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } }, -{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, -{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, -{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, -{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, -{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, -{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, -{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, -{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, -{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, -{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, -{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, -{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } }, -{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } }, -{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, BOOKE, { RT } }, -{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } }, -{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, BOOKE, { RT } }, -{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } }, -{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, BOOKE, { RT } }, -{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } }, -{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, BOOKE, { RT } }, -{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, -{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, -{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, -{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, -{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, -{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, -{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, -{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, -{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, -{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, -{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, -{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, -{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, -{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, -{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, -{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } }, -{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, -{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } }, -{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, -{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } }, -{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, -{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, -{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, -{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, -{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } }, -{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, -{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } }, -{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, -{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } }, -{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, -{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } }, -{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, -{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } }, -{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, -{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } }, -{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, -{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } }, -{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, -{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } }, -{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } }, -{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, -{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, -{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, -{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } }, -{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } }, -{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } }, -{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } }, -{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, -{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, -{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, -{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, -{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, -{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, -{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, -{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, -{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, -{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, -{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, -{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, -{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, -{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, -{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, -{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, -{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, -{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, -{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, -{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, -{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, -{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, -{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } }, -{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, -{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } }, -{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, -{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, -{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, -{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, -{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, -{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, -{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, -{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, -{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, -{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, -{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, -{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, -{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, -{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, -{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, -{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, -{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, -{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, -{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, -{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, -{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, -{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, -{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, -{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, - -{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } }, - -{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, -{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, - -{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } }, - -{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, -{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, - -{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } }, - -{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, -{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, -{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, -{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, - -{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, -{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, -{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, -{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, - -{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, - -{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, - -{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, - -{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } }, - -{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, - -{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }}, - -{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, -{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, - -{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, -{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, - -{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }}, - -{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, - -{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } }, - -{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, - -{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, - -{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, -{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, - -{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, -{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, - -{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } }, - -{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, - -{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, - -{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, - -{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, - -{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, -{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, -{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, -{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, - -{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } }, -{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } }, -{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } }, -{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } }, -{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } }, -{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } }, -{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } }, -{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } }, -{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } }, -{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } }, -{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } }, -{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } }, -{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } }, -{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } }, -{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } }, -{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } }, -{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } }, -{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } }, -{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } }, -{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } }, -{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } }, -{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } }, -{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } }, -{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } }, - -{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, - -{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } }, - -{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, -{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, -{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, -{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, -{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, -{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, -{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, -{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, -{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, -{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, -{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, -{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, -{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, -{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, -{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, -{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, -{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, -{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } }, -{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } }, -{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } }, -{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } }, -{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } }, -{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } }, -{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } }, -{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } }, -{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } }, -{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } }, -{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } }, -{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } }, -{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } }, -{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } }, -{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } }, -{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } }, -{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } }, -{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, -{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, -{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, -{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } }, -{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, -{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, -{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, -{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } }, -{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } }, -{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } }, -{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } }, -{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } }, -{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, -{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, -{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, -{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, -{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } }, -{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } }, -{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } }, -{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } }, -{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } }, -{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } }, -{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } }, -{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } }, -{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } }, -{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } }, -{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } }, -{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } }, -{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } }, -{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } }, -{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } }, -{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } }, -{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } }, -{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } }, -{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } }, -{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } }, -{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } }, -{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } }, -{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } }, -{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } }, -{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } }, -{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, -{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, -{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, -{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } }, -{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } }, -{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } }, -{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } }, -{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, -{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, -{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } }, -{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } }, -{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } }, -{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } }, -{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } }, -{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } }, -{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } }, -{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } }, -{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } }, -{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } }, -{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } }, -{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } }, -{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } }, -{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } }, -{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } }, -{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } }, -{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } }, -{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } }, -{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } }, -{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } }, -{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } }, -{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } }, -{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } }, -{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } }, -{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } }, -{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } }, -{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } }, -{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } }, -{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } }, -{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } }, -{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } }, -{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } }, -{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } }, -{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } }, -{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } }, -{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } }, -{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } }, -{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } }, -{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } }, -{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } }, -{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, - -{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, - -{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, -{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, - -{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, - -{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }}, - -{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }}, - -{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }}, - -{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, -{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, -{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, -{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, - -{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, -{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, - -{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } }, -{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } }, - -{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, -{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, - -{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, - -{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, - -{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, - -{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, - -{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, - -{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, -{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } }, - -{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, - -{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, -{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, -{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, - -{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, -{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, - -{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, -{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, - -{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, -{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, - -{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, -{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, - -{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, - -{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, - -{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, - -{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, - -{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, - -{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, - -{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, -{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } }, - -{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, -{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, -{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } }, -{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, -{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, - -{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } }, - -{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, - -{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, - -{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, - -{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, - -{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, - -{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, -{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, - -{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, -{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } }, - -{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } }, - -{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, -{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, - -{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, -{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, - -{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, - -{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, - -{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, - -{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, -{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, - -{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, - -{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, -{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } }, - -{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } }, - -{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, -{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, - -{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, -{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, - -{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, - -{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, - -{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, - -{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, -{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, - -{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, - -{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, - -{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, -{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, - -{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, - -{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, -{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, -{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, - -{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, -{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, - -{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, -{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, - -{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, - -{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, -{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, - -{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, -{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, -{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, -{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, - -{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, - -{ "mbar", X(31,854), X_MASK, BOOKE, { MO } }, -{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, - -{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } }, -{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, -{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } }, -{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, -{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } }, -{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } }, - -{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, - -{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, - -{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, -{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, - -{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, -{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, - -{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, -{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, -{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, -{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, - -{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, - -{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, - -{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } }, -{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } }, - -{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, -{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, - -{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, -{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, - -{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, - -{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, - -{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, -{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, - -{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, - -{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, - -{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, -{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, - -{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, - -{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, -{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } }, - -{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, - -{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, -{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, - -{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, - -{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, -{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, -{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, -{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, -{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, -{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, - -{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, -{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, - -{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, -{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } }, - -{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } }, - -{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, - -{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, -{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, - -{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, -{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } }, - -{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } }, - -{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, - -{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } }, - -{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, - -{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } }, - -{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, - -{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } }, - -{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, - -{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, -{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } }, - -{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, -{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } }, - -{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, - -{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, - -{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, - -{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, - -{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } }, - -{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, - -{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } }, - -{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, - -{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, - -{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, - -{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, - -{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, -{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, -{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } }, -{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } }, -{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } }, -{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, -{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } }, -{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, -{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } }, -{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, - -{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, - -{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, - -{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, - -{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, -{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, - -{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, - -{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, - -{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, - -{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, -{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, -{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, -{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, -{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, -{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, -{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } }, -{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, -{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, -{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, -{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, -{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, - -{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, - -{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, - -{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, - -{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, - -{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, -{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, - -{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, -{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, -{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, - -{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, -{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, - -{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, -{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, - -{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, -{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, -{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, - -{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, -{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, - -{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, - -{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, -{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, -{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, -{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, - -{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, - -{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, - -{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, - -{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, - -{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, -{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, -{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, - -{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, - -{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, -{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, - -{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, - -{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, -{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, - -{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, -{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, - -{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, -{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, - -{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, -{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, - -{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, -{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, - -{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, -{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, - -{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, -{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, - -{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, -{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, - -}; - -const int powerpc_num_opcodes = - sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); - -/* The macro table. This is only used by the assembler. */ - -/* The expressions of the form (-x ! 31) & (x | 31) have the value 0 - when x=0; 32-x when x is between 1 and 31; are negative if x is - negative; and are 32 or more otherwise. This is what you want - when, for instance, you are emulating a right shift by a - rotate-left-and-mask, because the underlying instructions support - shifts of size 0 but not shifts of size 32. By comparison, when - extracting x bits from some word you want to use just 32-x, because - the underlying instructions don't support extracting 0 bits but do - support extracting the whole word (32 bits in this case). */ - -const struct powerpc_macro powerpc_macros[] = { -{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, -{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, -{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, -{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, -{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, -{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, -{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, -{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, -{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, -{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, -{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, -{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, -{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, -{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, -{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, -{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, - -{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, -{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, -{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, -{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, -{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, -{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, -{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, -{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, -{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, -{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, -{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, -{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, -{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, -{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, -{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, -{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, -{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, -{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, -{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, -{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, -{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, -{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, -}; - -const int powerpc_num_macros = - sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); diff --git a/contrib/binutils/opcodes/s390-dis.c b/contrib/binutils/opcodes/s390-dis.c deleted file mode 100644 index 42f5151..0000000 --- a/contrib/binutils/opcodes/s390-dis.c +++ /dev/null @@ -1,261 +0,0 @@ -/* s390-dis.c -- Disassemble S390 instructions - Copyright 2000, 2001, 2002 Free Software Foundation, Inc. - Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). - - This file is part of GDB, GAS and the GNU binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/s390.h" - -static int init_flag = 0; -static int opc_index[256]; -static int current_arch_mask = 0; - -static void init_disasm PARAMS ((struct disassemble_info *)); -static unsigned int s390_extract_operand - PARAMS ((unsigned char *, const struct s390_operand *)); - -/* Set up index table for first opcode byte. */ - -static void -init_disasm (info) - struct disassemble_info *info; -{ - const struct s390_opcode *opcode; - const struct s390_opcode *opcode_end; - - memset (opc_index, 0, sizeof (opc_index)); - opcode_end = s390_opcodes + s390_num_opcodes; - for (opcode = s390_opcodes; opcode < opcode_end; opcode++) - { - opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes; - while ((opcode < opcode_end) && - (opcode[1].opcode[0] == opcode->opcode[0])) - opcode++; - } - switch (info->mach) - { - case bfd_mach_s390_31: - current_arch_mask = 1 << S390_OPCODE_ESA; - break; - case bfd_mach_s390_64: - current_arch_mask = 1 << S390_OPCODE_ZARCH; - break; - default: - abort (); - } - init_flag = 1; -} - -/* Extracts an operand value from an instruction. */ - -static inline unsigned int -s390_extract_operand (insn, operand) - unsigned char *insn; - const struct s390_operand *operand; -{ - unsigned int val; - int bits; - - /* Extract fragments of the operand byte for byte. */ - insn += operand->shift / 8; - bits = (operand->shift & 7) + operand->bits; - val = 0; - do - { - val <<= 8; - val |= (unsigned int) *insn++; - bits -= 8; - } - while (bits > 0); - val >>= -bits; - val &= ((1U << (operand->bits - 1)) << 1) - 1; - - /* Check for special long displacement case. */ - if (operand->bits == 20 && operand->shift == 20) - val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; - - /* Sign extend value if the operand is signed or pc relative. */ - if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) - && (val & (1U << (operand->bits - 1)))) - val |= (-1U << (operand->bits - 1)) << 1; - - /* Double value if the operand is pc relative. */ - if (operand->flags & S390_OPERAND_PCREL) - val <<= 1; - - /* Length x in an instructions has real length x+1. */ - if (operand->flags & S390_OPERAND_LENGTH) - val++; - return val; -} - -/* Print a S390 instruction. */ - -int -print_insn_s390 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - bfd_byte buffer[6]; - const struct s390_opcode *opcode; - const struct s390_opcode *opcode_end; - unsigned int value; - int status, opsize, bufsize; - char separator; - - if (init_flag == 0) - init_disasm (info); - - /* The output looks better if we put 6 bytes on a line. */ - info->bytes_per_line = 6; - - /* Every S390 instruction is max 6 bytes long. */ - memset (buffer, 0, 6); - status = (*info->read_memory_func) (memaddr, buffer, 6, info); - if (status != 0) - { - for (bufsize = 0; bufsize < 6; bufsize++) - if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0) - break; - if (bufsize <= 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - /* Opsize calculation looks strange but it works - 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes, - 11xxxxxx -> 6 bytes. */ - opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; - status = opsize > bufsize; - } - else - { - bufsize = 6; - opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; - } - - if (status == 0) - { - /* Find the first match in the opcode table. */ - opcode_end = s390_opcodes + s390_num_opcodes; - for (opcode = s390_opcodes + opc_index[(int) buffer[0]]; - (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]); - opcode++) - { - const struct s390_operand *operand; - const unsigned char *opindex; - - /* Check architecture. */ - if (!(opcode->modes & current_arch_mask)) - continue; - /* Check signature of the opcode. */ - if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1] - || (buffer[2] & opcode->mask[2]) != opcode->opcode[2] - || (buffer[3] & opcode->mask[3]) != opcode->opcode[3] - || (buffer[4] & opcode->mask[4]) != opcode->opcode[4] - || (buffer[5] & opcode->mask[5]) != opcode->opcode[5]) - continue; - - /* The instruction is valid. */ - if (opcode->operands[0] != 0) - (*info->fprintf_func) (info->stream, "%s\t", opcode->name); - else - (*info->fprintf_func) (info->stream, "%s", opcode->name); - - /* Extract the operands. */ - separator = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) - { - unsigned int value; - - operand = s390_operands + *opindex; - value = s390_extract_operand (buffer, operand); - - if ((operand->flags & S390_OPERAND_INDEX) && value == 0) - continue; - if ((operand->flags & S390_OPERAND_BASE) && - value == 0 && separator == '(') - { - separator = ','; - continue; - } - - if (separator) - (*info->fprintf_func) (info->stream, "%c", separator); - - if (operand->flags & S390_OPERAND_GPR) - (*info->fprintf_func) (info->stream, "%%r%i", value); - else if (operand->flags & S390_OPERAND_FPR) - (*info->fprintf_func) (info->stream, "%%f%i", value); - else if (operand->flags & S390_OPERAND_AR) - (*info->fprintf_func) (info->stream, "%%a%i", value); - else if (operand->flags & S390_OPERAND_CR) - (*info->fprintf_func) (info->stream, "%%c%i", value); - else if (operand->flags & S390_OPERAND_PCREL) - (*info->print_address_func) (memaddr + (int) value, info); - else if (operand->flags & S390_OPERAND_SIGNED) - (*info->fprintf_func) (info->stream, "%i", (int) value); - else - (*info->fprintf_func) (info->stream, "%i", value); - - if (operand->flags & S390_OPERAND_DISP) - { - separator = '('; - } - else if (operand->flags & S390_OPERAND_BASE) - { - (*info->fprintf_func) (info->stream, ")"); - separator = ','; - } - else - separator = ','; - } - - /* Found instruction, printed it, return its size. */ - return opsize; - } - /* No matching instruction found, fall through to hex print. */ - } - - if (bufsize >= 4) - { - value = (unsigned int) buffer[0]; - value = (value << 8) + (unsigned int) buffer[1]; - value = (value << 8) + (unsigned int) buffer[2]; - value = (value << 8) + (unsigned int) buffer[3]; - (*info->fprintf_func) (info->stream, ".long\t0x%08x", value); - return 4; - } - else if (bufsize >= 2) - { - value = (unsigned int) buffer[0]; - value = (value << 8) + (unsigned int) buffer[1]; - (*info->fprintf_func) (info->stream, ".short\t0x%04x", value); - return 2; - } - else - { - value = (unsigned int) buffer[0]; - (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value); - return 1; - } -} diff --git a/contrib/binutils/opcodes/s390-mkopc.c b/contrib/binutils/opcodes/s390-mkopc.c deleted file mode 100644 index 34188e62..0000000 --- a/contrib/binutils/opcodes/s390-mkopc.c +++ /dev/null @@ -1,230 +0,0 @@ -/* s390-mkopc.c -- Generates opcode table out of s390-opc.txt - Copyright 2000, 2001 Free Software Foundation, Inc. - Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). - - This file is part of GDB, GAS, and the GNU binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> - -/* Taken from opcodes/s390.h */ -enum s390_opcode_mode_val - { - S390_OPCODE_ESA = 0, - S390_OPCODE_ZARCH - }; - -enum s390_opcode_cpu_val - { - S390_OPCODE_G5 = 0, - S390_OPCODE_G6, - S390_OPCODE_Z900, - S390_OPCODE_Z990 - }; - -struct op_struct - { - char opcode[16]; - char mnemonic[16]; - char format[16]; - int mode_bits; - int min_cpu; - - unsigned long long sort_value; - int no_nibbles; - }; - -struct op_struct *op_array; -int max_ops; -int no_ops; - -static void -createTable (void) -{ - max_ops = 256; - op_array = malloc (max_ops * sizeof (struct op_struct)); - no_ops = 0; -} - -/* `insertOpcode': insert an op_struct into sorted opcode array. */ - -static void -insertOpcode (char *opcode, char *mnemonic, char *format, - int min_cpu, int mode_bits) -{ - char *str; - unsigned long long sort_value; - int no_nibbles; - int ix, k; - - while (no_ops >= max_ops) - { - max_ops = max_ops * 2; - op_array = realloc (op_array, max_ops * sizeof (struct op_struct)); - } - - sort_value = 0; - str = opcode; - for (ix = 0; ix < 16; ix++) - { - if (*str >= '0' && *str <= '9') - sort_value = (sort_value << 4) + (*str - '0'); - else if (*str >= 'a' && *str <= 'f') - sort_value = (sort_value << 4) + (*str - 'a' + 10); - else if (*str >= 'A' && *str <= 'F') - sort_value = (sort_value << 4) + (*str - 'A' + 10); - else if (*str == '?') - sort_value <<= 4; - else - break; - str ++; - } - sort_value <<= 4*(16 - ix); - sort_value += (min_cpu << 8) + mode_bits; - no_nibbles = ix; - for (ix = 0; ix < no_ops; ix++) - if (sort_value > op_array[ix].sort_value) - break; - for (k = no_ops; k > ix; k--) - op_array[k] = op_array[k-1]; - strcpy(op_array[ix].opcode, opcode); - strcpy(op_array[ix].mnemonic, mnemonic); - strcpy(op_array[ix].format, format); - op_array[ix].sort_value = sort_value; - op_array[ix].no_nibbles = no_nibbles; - op_array[ix].min_cpu = min_cpu; - op_array[ix].mode_bits = mode_bits; - no_ops++; -} - -static char file_header[] = - "/* The opcode table. This file was generated by s390-mkopc.\n\n" - " The format of the opcode table is:\n\n" - " NAME OPCODE MASK OPERANDS\n\n" - " Name is the name of the instruction.\n" - " OPCODE is the instruction opcode.\n" - " MASK is the opcode mask; this is used to tell the disassembler\n" - " which bits in the actual opcode must match OPCODE.\n" - " OPERANDS is the list of operands.\n\n" - " The disassembler reads the table in order and prints the first\n" - " instruction which matches. */\n\n" - "const struct s390_opcode s390_opcodes[] =\n {\n"; - -/* `dumpTable': write opcode table. */ - -static void -dumpTable (void) -{ - char *str; - int ix; - - /* Write hash table entries (slots). */ - printf (file_header); - - for (ix = 0; ix < no_ops; ix++) - { - printf (" { \"%s\", ", op_array[ix].mnemonic); - for (str = op_array[ix].opcode; *str != 0; str++) - if (*str == '?') - *str = '0'; - printf ("OP%i(0x%sLL), ", - op_array[ix].no_nibbles*4, op_array[ix].opcode); - printf ("MASK_%s, INSTR_%s, ", - op_array[ix].format, op_array[ix].format); - printf ("%i, ", op_array[ix].mode_bits); - printf ("%i}", op_array[ix].min_cpu); - if (ix < no_ops-1) - printf (",\n"); - else - printf ("\n"); - } - printf ("};\n\n"); - printf ("const int s390_num_opcodes =\n"); - printf (" sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);\n\n"); -} - -int -main (void) -{ - char currentLine[256]; - - createTable (); - - /* Read opcode descriptions from `stdin'. For each mnemonic, - make an entry into the opcode table. */ - while (fgets (currentLine, sizeof (currentLine), stdin) != NULL) - { - char opcode[16]; - char mnemonic[16]; - char format[16]; - char description[64]; - char cpu_string[16]; - char modes_string[16]; - int min_cpu; - int mode_bits; - char *str; - - if (currentLine[0] == '#') - continue; - memset (opcode, 0, 8); - if (sscanf (currentLine, "%15s %15s %15s \"%[^\"]\" %15s %15s", - opcode, mnemonic, format, description, - cpu_string, modes_string) == 6) - { - if (strcmp (cpu_string, "g5") == 0) - min_cpu = S390_OPCODE_G5; - else if (strcmp (cpu_string, "g6") == 0) - min_cpu = S390_OPCODE_G6; - else if (strcmp (cpu_string, "z900") == 0) - min_cpu = S390_OPCODE_Z900; - else if (strcmp (cpu_string, "z990") == 0) - min_cpu = S390_OPCODE_Z990; - else { - fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); - exit (1); - } - - str = modes_string; - mode_bits = 0; - do { - if (strncmp (str, "esa", 3) == 0 - && (str[3] == 0 || str[3] == ',')) { - mode_bits |= 1 << S390_OPCODE_ESA; - str += 3; - } else if (strncmp (str, "zarch", 5) == 0 - && (str[5] == 0 || str[5] == ',')) { - mode_bits |= 1 << S390_OPCODE_ZARCH; - str += 5; - } else { - fprintf (stderr, "Couldn't parse modes string %s\n", - modes_string); - exit (1); - } - if (*str == ',') - str++; - } while (*str != 0); - insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits); - } - else - fprintf (stderr, "Couldn't scan line %s\n", currentLine); - } - - dumpTable (); - return 0; -} diff --git a/contrib/binutils/opcodes/s390-opc.c b/contrib/binutils/opcodes/s390-opc.c deleted file mode 100644 index 1a4b276..0000000 --- a/contrib/binutils/opcodes/s390-opc.c +++ /dev/null @@ -1,339 +0,0 @@ -/* s390-opc.c -- S390 opcode list - Copyright 2000, 2001 Free Software Foundation, Inc. - Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). - - This file is part of GDB, GAS, and the GNU binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <stdio.h> -#include "ansidecl.h" -#include "opcode/s390.h" - -/* This file holds the S390 opcode table. The opcode table - includes almost all of the extended instruction mnemonics. This - permits the disassembler to use them, and simplifies the assembler - logic, at the cost of increasing the table size. The table is - strictly constant data, so the compiler should be able to put it in - the .text section. - - This file also holds the operand table. All knowledge about - inserting operands into instructions and vice-versa is kept in this - file. */ - -/* The operands table. - The fields are bits, shift, insert, extract, flags. */ - -const struct s390_operand s390_operands[] = -{ -#define UNUSED 0 - { 0, 0, 0 }, /* Indicates the end of the operand list */ - -#define R_8 1 /* GPR starting at position 8 */ - { 4, 8, S390_OPERAND_GPR }, -#define R_12 2 /* GPR starting at position 12 */ - { 4, 12, S390_OPERAND_GPR }, -#define R_16 3 /* GPR starting at position 16 */ - { 4, 16, S390_OPERAND_GPR }, -#define R_20 4 /* GPR starting at position 20 */ - { 4, 20, S390_OPERAND_GPR }, -#define R_24 5 /* GPR starting at position 24 */ - { 4, 24, S390_OPERAND_GPR }, -#define R_28 6 /* GPR starting at position 28 */ - { 4, 28, S390_OPERAND_GPR }, -#define R_32 7 /* GPR starting at position 32 */ - { 4, 32, S390_OPERAND_GPR }, - -#define F_8 8 /* FPR starting at position 8 */ - { 4, 8, S390_OPERAND_FPR }, -#define F_12 9 /* FPR starting at position 12 */ - { 4, 12, S390_OPERAND_FPR }, -#define F_16 10 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR }, -#define F_20 11 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR }, -#define F_24 12 /* FPR starting at position 24 */ - { 4, 24, S390_OPERAND_FPR }, -#define F_28 13 /* FPR starting at position 28 */ - { 4, 28, S390_OPERAND_FPR }, -#define F_32 14 /* FPR starting at position 32 */ - { 4, 32, S390_OPERAND_FPR }, - -#define A_8 15 /* Access reg. starting at position 8 */ - { 4, 8, S390_OPERAND_AR }, -#define A_12 16 /* Access reg. starting at position 12 */ - { 4, 12, S390_OPERAND_AR }, -#define A_24 17 /* Access reg. starting at position 24 */ - { 4, 24, S390_OPERAND_AR }, -#define A_28 18 /* Access reg. starting at position 28 */ - { 4, 28, S390_OPERAND_AR }, - -#define C_8 19 /* Control reg. starting at position 8 */ - { 4, 8, S390_OPERAND_CR }, -#define C_12 20 /* Control reg. starting at position 12 */ - { 4, 12, S390_OPERAND_CR }, - -#define B_16 21 /* Base register starting at position 16 */ - { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, -#define B_32 22 /* Base register starting at position 32 */ - { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, - -#define X_12 23 /* Index register starting at position 12 */ - { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, - -#define D_20 24 /* Displacement starting at position 20 */ - { 12, 20, S390_OPERAND_DISP }, -#define D_36 25 /* Displacement starting at position 36 */ - { 12, 36, S390_OPERAND_DISP }, -#define D20_20 26 /* 20 bit displacement starting at 20 */ - { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, - -#define L4_8 27 /* 4 bit length starting at position 8 */ - { 4, 8, S390_OPERAND_LENGTH }, -#define L4_12 28 /* 4 bit length starting at position 12 */ - { 4, 12, S390_OPERAND_LENGTH }, -#define L8_8 29 /* 8 bit length starting at position 8 */ - { 8, 8, S390_OPERAND_LENGTH }, - -#define U4_8 30 /* 4 bit unsigned value starting at 8 */ - { 4, 8, 0 }, -#define U4_12 31 /* 4 bit unsigned value starting at 12 */ - { 4, 12, 0 }, -#define U4_16 32 /* 4 bit unsigned value starting at 16 */ - { 4, 16, 0 }, -#define U4_20 33 /* 4 bit unsigned value starting at 20 */ - { 4, 20, 0 }, -#define U8_8 34 /* 8 bit unsigned value starting at 8 */ - { 8, 8, 0 }, -#define U8_16 35 /* 8 bit unsigned value starting at 16 */ - { 8, 16, 0 }, -#define I16_16 36 /* 16 bit signed value starting at 16 */ - { 16, 16, S390_OPERAND_SIGNED }, -#define U16_16 37 /* 16 bit unsigned value starting at 16 */ - { 16, 16, 0 }, -#define J16_16 38 /* PC relative jump offset at 16 */ - { 16, 16, S390_OPERAND_PCREL }, -#define J32_16 39 /* PC relative long offset at 16 */ - { 32, 16, S390_OPERAND_PCREL } -}; - - -/* Macros used to form opcodes. */ - -/* 8/16/48 bit opcodes. */ -#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } -#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ - (x >> 16) & 255, (x >> 8) & 255, x & 255} - -/* The new format of the INSTR_x_y and MASK_x_y defines is based - on the following rules: - 1) the middle part of the definition (x in INSTR_x_y) is the official - names of the instruction format that you can find in the principals - of operation. - 2) the last part of the definition (y in INSTR_x_y) gives you an idea - which operands the binary represenation of the instruction has. - The meanings of the letters in y are: - a - access register - c - control register - d - displacement, 12 bit - f - floating pointer register - i - signed integer, 4 or 8 bit - l - length, 4 or 8 bit - p - pc relative - r - general purpose register - u - unsigned integer, 4 or 8 bit - 0 - operand skipped. - The order of the letters reflects the layout of the format in - storage and not the order of the paramaters of the instructions. - The use of the letters is not a 100% match with the PoP but it is - quite close. - - For example the instruction "mvo" is defined in the PoP as follows: - - MVO D1(L1,B1),D2(L2,B2) [SS] - - -------------------------------------- - | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | - -------------------------------------- - 0 8 12 16 20 32 36 - - The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ - -#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ -#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ -#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ -#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ -#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ -#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ -#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ -#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ -#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ -#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ -#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ -#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ -#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ -#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ -#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ -#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ -#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ -#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ -#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ -#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ -#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ -#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ -#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ -#define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ -#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */ -#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */ -#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */ -#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ -#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ -#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ -#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ -#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ -#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ -#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ -#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ -#define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ -#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ -#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ -#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ -#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ -#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ -#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ -#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ -#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ -#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ -#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ -#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ -#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ -#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ -#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ -#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ -#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ -#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ -#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ -#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ -#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ -#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ -#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ -#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ -#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ -#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ -#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ -#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ -#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ -#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ -#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ - -#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } -#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } -#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } -#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } -#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } -#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } -#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } - -/* The opcode formats table (blueprints for .insn pseudo mnemonic). */ - -const struct s390_opcode s390_opformats[] = - { - { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, - { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, - { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, - { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, - { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, - { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, - { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, - { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, - { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, - { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, - { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, - { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, - { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, - { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, - { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, - { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, - { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, - { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, - { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, - { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, -}; - -const int s390_num_opformats = - sizeof (s390_opformats) / sizeof (s390_opformats[0]); - -#include "s390-opc.tab" diff --git a/contrib/binutils/opcodes/s390-opc.txt b/contrib/binutils/opcodes/s390-opc.txt deleted file mode 100644 index be08c82..0000000 --- a/contrib/binutils/opcodes/s390-opc.txt +++ /dev/null @@ -1,793 +0,0 @@ -# S/390 opcodes list. Use s390-mkopc to convert it into the opcode table. -# Copyright 2000, 2001 Free Software Foundation, Inc. -# Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). -5a a RX_RRRD "add" g5 esa,zarch -6a ad RX_FRRD "add normalized (long)" g5 esa,zarch -2a adr RR_FF "add normalized (long)" g5 esa,zarch -7a ae RX_FRRD "add normalized (short)" g5 esa,zarch -3a aer RR_FF "add normalized (short)" g5 esa,zarch -4a ah RX_RRRD "add halfword" g5 esa,zarch -5e al RX_RRRD "add logical" g5 esa,zarch -1e alr RR_RR "add logical" g5 esa,zarch -fa ap SS_LLRDRD "add decimal" g5 esa,zarch -1a ar RR_RR "add" g5 esa,zarch -7e au RX_FRRD "add unnormalized (short)" g5 esa,zarch -3e aur RR_FF "add unnormalized (short)" g5 esa,zarch -6e aw RX_FRRD "add unnormalized (long)" g5 esa,zarch -2e awr RR_FF "add unnormalized (long)" g5 esa,zarch -36 axr RR_FF "add normalized" g5 esa,zarch -b240 bakr RRE_RR "branch and stack" g5 esa,zarch -45 bal RX_RRRD "branch and link" g5 esa,zarch -05 balr RR_RR "branch and link" g5 esa,zarch -4d bas RX_RRRD "branch and save" g5 esa,zarch -0d basr RR_RR "branch and save" g5 esa,zarch -0c bassm RR_RR "branch and save and set mode" g5 esa,zarch -47 bc RX_URRD "branch on condition" g5 esa,zarch -07 bcr RR_UR "branch on condition" g5 esa,zarch -46 bct RX_RRRD "branch on count" g5 esa,zarch -06 bctr RR_RR "branch on count" g5 esa,zarch -b258 bsg RRE_RR "branch in subspace group" g5 esa,zarch -0b bsm RR_RR "branch and set mode" g5 esa,zarch -86 bxh RS_RRRD "branch on index high" g5 esa,zarch -87 bxle RS_RRRD "branch on index low or equal" g5 esa,zarch -59 c RX_RRRD "compare" g5 esa,zarch -69 cd RX_FRRD "compare (long)" g5 esa,zarch -29 cdr RR_FF "compare (long)" g5 esa,zarch -bb cds RS_RRRD "compare double and swap" g5 esa,zarch -79 ce RX_FRRD "compare (short)" g5 esa,zarch -39 cer RR_FF "compare (short)" g5 esa,zarch -b21a cfc S_RD "compare and form codeword" g5 esa,zarch -49 ch RX_RRRD "compare halfword" g5 esa,zarch -55 cl RX_RRRD "compare logical" g5 esa,zarch -d5 clc SS_L0RDRD "compare logical" g5 esa,zarch -0f clcl RR_RR "compare logical long" g5 esa,zarch -95 cli SI_URD "compare logical" g5 esa,zarch -bd clm RS_RURD "compare logical characters under mask" g5 esa,zarch -15 clr RR_RR "compare logical" g5 esa,zarch -b25d clst RRE_RR "compare logical string" g5 esa,zarch -b263 cmpsc RRE_RR "compression call" g5 esa,zarch -f9 cp SS_LLRDRD "compare decimal" g5 esa,zarch -b24d cpya RRE_AA "copy access" g5 esa,zarch -19 cr RR_RR "compare" g5 esa,zarch -ba cs RS_RRRD "compare and swap" g5 esa,zarch -b230 csch S_00 "clear subchannel" g5 esa,zarch -b257 cuse RRE_RR "compare until substring equal" g5 esa,zarch -b250 csp RRE_RR "compare and swap and purge" g5 esa,zarch -4f cvb RX_RRRD "convert to binary" g5 esa,zarch -4e cvd RX_RRRD "convert to decimal" g5 esa,zarch -5d d RX_RRRD "divide" g5 esa,zarch -6d dd RX_FRRD "divide (long)" g5 esa,zarch -2d ddr RR_FF "divide (long)" g5 esa,zarch -7d de RX_FRRD "divide (short)" g5 esa,zarch -3d der RR_FF "divide (short)" g5 esa,zarch -83 diag RS_RRRD "diagnose" g5 esa,zarch -fd dp SS_LLRDRD "divide decimal" g5 esa,zarch -1d dr RR_RR "divide" g5 esa,zarch -b22d dxr RRE_F0 "divide (ext.)" g5 esa,zarch -b24f ear RRE_RA "extract access" g5 esa,zarch -de ed SS_L0RDRD "edit" g5 esa,zarch -df edmk SS_L0RDRD "edit and mark" g5 esa,zarch -b226 epar RRE_R0 "extract primary ASN" g5 esa,zarch -b249 ereg RRE_RR "extract stacked registers" g5 esa,zarch -b227 esar RRE_R0 "extract secondary ASN" g5 esa,zarch -b24a esta RRE_RR "extract stacked state" g5 esa,zarch -44 ex RX_RRRD "execute" g5 esa,zarch -24 hdr RR_FF "halve (long)" g5 esa,zarch -34 her RR_FF "halve (short)" g5 esa,zarch -b231 hsch S_00 "halt subchannel" g5 esa,zarch -b224 iac RRE_R0 "insert address space control" g5 esa,zarch -43 ic RX_RRRD "insert character" g5 esa,zarch -bf icm RS_RURD "insert characters under mask" g5 esa,zarch -b20b ipk S_00 "insert PSW key" g5 esa,zarch -b222 ipm RRE_R0 "insert program mask" g5 esa,zarch -b221 ipte RRE_RR "invalidate page table entry" g5 esa,zarch -b229 iske RRE_RR "insert storage key extended" g5 esa,zarch -b223 ivsk RRE_RR "insert virtual storage key" g5 esa,zarch -58 l RX_RRRD "load" g5 esa,zarch -41 la RX_RRRD "load address" g5 esa,zarch -51 lae RX_RRRD "load address extended" g5 esa,zarch -9a lam RS_AARD "load access multiple" g5 esa,zarch -e500 lasp SSE_RDRD "load address space parameters" g5 esa,zarch -23 lcdr RR_FF "load complement (long)" g5 esa,zarch -33 lcer RR_FF "load complement (short)" g5 esa,zarch -13 lcr RR_RR "load complement" g5 esa,zarch -b7 lctl RS_CCRD "load control" g5 esa,zarch -68 ld RX_FRRD "load (long)" g5 esa,zarch -28 ldr RR_FF "load (long)" g5 esa,zarch -78 le RX_FRRD "load (short)" g5 esa,zarch -38 ler RR_FF "load (short)" g5 esa,zarch -48 lh RX_RRRD "load halfword" g5 esa,zarch -98 lm RS_RRRD "load multiple" g5 esa,zarch -21 lndr RR_FF "load negative (long)" g5 esa,zarch -31 lner RR_FF "load negative (short)" g5 esa,zarch -11 lnr RR_RR "load negative" g5 esa,zarch -20 lpdr RR_FF "load positive (long)" g5 esa,zarch -30 lper RR_FF "load positive (short)" g5 esa,zarch -10 lpr RR_RR "load positive" g5 esa,zarch -82 lpsw S_RD "load PSW" g5 esa,zarch -18 lr RR_RR "load" g5 esa,zarch -b1 lra RX_RRRD "load real address" g5 esa,zarch -25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch -35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch -25 ldxr RR_FF "load rounded (ext. to long)" g5 esa,zarch -35 ledr RR_FF "load rounded (long to short)" g5 esa,zarch -22 ltdr RR_FF "load and test (long)" g5 esa,zarch -32 lter RR_FF "load and test (short)" g5 esa,zarch -12 ltr RR_RR "load and test" g5 esa,zarch -b24b lura RRE_RR "load using real address" g5 esa,zarch -5c m RX_RRRD "multiply" g5 esa,zarch -af mc SI_URD "monitor call" g5 esa,zarch -6c md RX_FRRD "multiply (long)" g5 esa,zarch -2c mdr RR_FF "multiply (long)" g5 esa,zarch -7c me RX_FRRD "multiply (short to long)" g5 esa,zarch -7c mde RX_FRRD "multiply (short to long)" g5 esa,zarch -3c mer RR_FF "multiply (short to long)" g5 esa,zarch -3c mder RR_FF "multiply short to long hfp" g5 esa,zarch -4c mh RX_RRRD "multiply halfword" g5 esa,zarch -fc mp SS_LLRDRD "multiply decimal" g5 esa,zarch -1c mr RR_RR "multiply" g5 esa,zarch -b232 msch S_RD "modify subchannel" g5 esa,zarch -b247 msta RRE_R0 "modify stacked state" g5 esa,zarch -d2 mvc SS_L0RDRD "move" g5 esa,zarch -e50f mvcdk SSE_RDRD "move with destination key" g5 esa,zarch -e8 mvcin SS_L0RDRD "move inverse" g5 esa,zarch -d9 mvck SS_RRRDRD "move with key" g5 esa,zarch -0e mvcl RR_RR "move long" g5 esa,zarch -da mvcp SS_RRRDRD "move to primary" g5 esa,zarch -db mvcs SS_RRRDRD "move to secondary" g5 esa,zarch -e50e mvcsk SSE_RDRD "move with source key" g5 esa,zarch -92 mvi SI_URD "move" g5 esa,zarch -d1 mvn SS_L0RDRD "move numerics" g5 esa,zarch -f1 mvo SS_LLRDRD "move with offset" g5 esa,zarch -b254 mvpg RRE_RR "move page" g5 esa,zarch -b255 mvst RRE_RR "move string" g5 esa,zarch -d3 mvz SS_L0RDRD "move zones" g5 esa,zarch -67 mxd RX_FRRD "multiply (long to ext.)" g5 esa,zarch -27 mxdr RR_FF "multiply (long to ext.)" g5 esa,zarch -26 mxr RR_FF "multiply (ext.)" g5 esa,zarch -54 n RX_RRRD "AND" g5 esa,zarch -d4 nc SS_L0RDRD "AND" g5 esa,zarch -94 ni SI_URD "AND" g5 esa,zarch -14 nr RR_RR "AND" g5 esa,zarch -56 o RX_RRRD "OR" g5 esa,zarch -d6 oc SS_L0RDRD "OR" g5 esa,zarch -96 oi SI_URD "OR" g5 esa,zarch -16 or RR_RR "OR" g5 esa,zarch -f2 pack SS_LLRDRD "pack" g5 esa,zarch -b248 palb RRE_00 "purge ALB" g5 esa,zarch -b218 pc S_RD "program call" g5 esa,zarch -0101 pr E "program return" g5 esa,zarch -b228 pt RRE_RR "program transfer" g5 esa,zarch -b20d ptlb S_00 "purge TLB" g5 esa,zarch -b23b rchp S_00 "reset channel path" g5 esa,zarch -b22a rrbe RRE_RR "reset reference bit extended" g5 esa,zarch -b238 rsch S_00 "resume subchannel" g5 esa,zarch -5b s RX_RRRD "subtract" g5 esa,zarch -b219 sac S_RD "set address space control" g5 esa,zarch -b279 sacf S_RD "set address space control fast" g5 esa,zarch -b237 sal S_00 "set address limit" g5 esa,zarch -b24e sar RRE_AR "set access" g5 esa,zarch -b23c schm S_00 "set channel monitor" g5 esa,zarch -b204 sck S_RD "set clock" g5 esa,zarch -b206 sckc S_RD "set clock comparator" g5 esa,zarch -6b sd RX_FRRD "subtract normalized (long)" g5 esa,zarch -2b sdr RR_FF "subtract normalized (long)" g5 esa,zarch -7b se RX_FRRD "subtract normalized (short)" g5 esa,zarch -3b ser RR_FF "subtract normalized (short)" g5 esa,zarch -4b sh RX_RRRD "subtract halfword" g5 esa,zarch -b214 sie S_RD "start interpretive execution" g5 esa,zarch -ae sigp RS_RRRD "signal processor" g5 esa,zarch -5f sl RX_RRRD "subtract logical" g5 esa,zarch -8b sla RS_R0RD "shift left single" g5 esa,zarch -8f slda RS_R0RD "shift left double (long)" g5 esa,zarch -8d sldl RS_R0RD "shift left double logical (long)" g5 esa,zarch -89 sll RS_R0RD "shift left single logical" g5 esa,zarch -1f slr RR_RR "subtract logical" g5 esa,zarch -fb sp SS_LLRDRD "subtract decimal" g5 esa,zarch -b20a spka S_RD "set PSW key from address" g5 esa,zarch -04 spm RR_R0 "set program mask" g5 esa,zarch -b208 spt S_RD "set CPU timer" g5 esa,zarch -b210 spx S_RD "set prefix" g5 esa,zarch -b244 sqdr RRE_F0 "square root (long)" g5 esa,zarch -b245 sqer RRE_F0 "square root (short)" g5 esa,zarch -1b sr RR_RR "subtract" g5 esa,zarch -8a sra RS_R0RD "shift right single" g5 esa,zarch -8e srda RS_R0RD "shift right double (long)" g5 esa,zarch -8c srdl RS_R0RD "shift right double logical (long)" g5 esa,zarch -88 srl RS_R0RD "shift right single logical" g5 esa,zarch -f0 srp SS_LIRDRD "shift and round decimal" g5 esa,zarch -b25e srst RRE_RR "search string" g5 esa,zarch -b225 ssar RRE_R0 "set secondary ASN" g5 esa,zarch -b233 ssch S_RD "start subchannel" g5 esa,zarch -b22b sske RRE_RR "set storage key extended" g5 esa,zarch -80 ssm S_RD "set system mask" g5 esa,zarch -50 st RX_RRRD "store" g5 esa,zarch -9b stam RS_AARD "store access multiple" g5 esa,zarch -b212 stap S_RD "store CPU address" g5 esa,zarch -42 stc RX_RRRD "store character" g5 esa,zarch -b205 stck S_RD "store clock" g5 esa,zarch -b207 stckc S_RD "store clock comparator" g5 esa,zarch -be stcm RS_RURD "store characters under mask" g5 esa,zarch -b23a stcps S_RD "store channel path status" g5 esa,zarch -b239 stcrw S_RD "store channel report word" g5 esa,zarch -b6 stctl RS_CCRD "store control" g5 esa,zarch -60 std RX_FRRD "store (long)" g5 esa,zarch -70 ste RX_FRRD "store (short)" g5 esa,zarch -40 sth RX_RRRD "store halfword" g5 esa,zarch -b202 stidp S_RD "store CPU id" g5 esa,zarch -90 stm RS_RRRD "store multiple" g5 esa,zarch -ac stnsm SI_URD "store then AND system mask" g5 esa,zarch -ad stosm SI_URD "store then OR system mask" g5 esa,zarch -b209 stpt S_RD "store CPU timer" g5 esa,zarch -b211 stpx S_RD "store prefix" g5 esa,zarch -b234 stsch S_RD "store subchannel" g5 esa,zarch -b246 stura RRE_RR "store using real address" g5 esa,zarch -7f su RX_FRRD "subtract unnormalized (short)" g5 esa,zarch -3f sur RR_FF "subtract unnormalized (short)" g5 esa,zarch -0a svc RR_U0 "supervisor call" g5 esa,zarch -6f sw RX_FRRD "subtract unnormalized (long)" g5 esa,zarch -2f swr RR_FF "subtract unnormalized (long)" g5 esa,zarch -37 sxr RR_FF "subtract normalized (ext.)" g5 esa,zarch -b24c tar RRE_AR "test access" g5 esa,zarch -b22c tb RRE_0R "test block" g5 esa,zarch -91 tm SI_URD "test under mask" g5 esa,zarch -b236 tpi S_RD "test pending interruption" g5 esa,zarch -e501 tprot SSE_RDRD "test protection" g5 esa,zarch -dc tr SS_L0RDRD "translate" g5 esa,zarch -99 trace RS_RRRD "trace" g5 esa,zarch -dd trt SS_L0RDRD "translate and test" g5 esa,zarch -93 ts S_RD "test and set" g5 esa,zarch -b235 tsch S_RD "test subchannel" g5 esa,zarch -f3 unpk SS_LLRDRD "unpack" g5 esa,zarch -0102 upt E "update tree" g5 esa,zarch -57 x RX_RRRD "exclusive OR" g5 esa,zarch -d7 xc SS_L0RDRD "exclusive OR" g5 esa,zarch -97 xi SI_URD "exclusive OR" g5 esa,zarch -17 xr RR_RR "exclusive OR" g5 esa,zarch -f8 zap SS_LLRDRD "zero and add" g5 esa,zarch -a70a ahi RI_RI "add halfword immediate" g5 esa,zarch -84 brxh RSI_RRP "branch relative on index high" g5 esa,zarch -85 brxle RSI_RRP "branch relative on index low or equal" g5 esa,zarch -a705 bras RI_RP "branch relative and save" g5 esa,zarch -a704 brc RI_UP "branch relative on condition" g5 esa,zarch -a706 brct RI_RP "branch relative on count" g5 esa,zarch -b241 cksm RRE_RR "checksum" g5 esa,zarch -a70e chi RI_RI "compare halfword immediate" g5 esa,zarch -a9 clcle RS_RRRD "compare logical long extended" g5 esa,zarch -a708 lhi RI_RI "load halfword immediate" g5 esa,zarch -a8 mvcle RS_RRRD "move long extended" g5 esa,zarch -a70c mhi RI_RI "multiply halfword immediate" g5 esa,zarch -b252 msr RRE_RR "multiply single" g5 esa,zarch -71 ms RX_RRRD "multiply single" g5 esa,zarch -a700 tmh RI_RU "test under mask high" g5 esa,zarch -a701 tml RI_RU "test under mask low" g5 esa,zarch -0700 nopr RR_0R "no operation" g5 esa,zarch -0710 bor RR_0R "branch on overflow / if ones" g5 esa,zarch -0720 bhr RR_0R "branch on high" g5 esa,zarch -0720 bpr RR_0R "branch on plus" g5 esa,zarch -0730 bnler RR_0R "branch on not low or equal" g5 esa,zarch -0740 blr RR_0R "branch on low" g5 esa,zarch -0740 bmr RR_0R "branch on minus / if mixed" g5 esa,zarch -0750 bnher RR_0R "branch on not high or equal" g5 esa,zarch -0760 blhr RR_0R "branch on low or high" g5 esa,zarch -0770 bner RR_0R "branch on not equal" g5 esa,zarch -0770 bnzr RR_0R "branch on not zero / if not zeros" g5 esa,zarch -0780 ber RR_0R "branch on equal" g5 esa,zarch -0780 bzr RR_0R "branch on zero / if zeros" g5 esa,zarch -0790 bnlhr RR_0R "branch on not low or high" g5 esa,zarch -07a0 bher RR_0R "branch on high or equal" g5 esa,zarch -07b0 bnlr RR_0R "branch on not low" g5 esa,zarch -07b0 bnmr RR_0R "branch on not minus / if not mixed" g5 esa,zarch -07c0 bler RR_0R "brach on low or equal" g5 esa,zarch -07d0 bnhr RR_0R "branch on not high" g5 esa,zarch -07d0 bnpr RR_0R "branch on not plus" g5 esa,zarch -07e0 bnor RR_0R "branch on not overflow / if not ones" g5 esa,zarch -07f0 br RR_0R "unconditional branch" g5 esa,zarch -4700 nop RX_0RRD "no operation" g5 esa,zarch -4710 bo RX_0RRD "branch on overflow / if ones" g5 esa,zarch -4720 bh RX_0RRD "branch on high" g5 esa,zarch -4720 bp RX_0RRD "branch on plus" g5 esa,zarch -4730 bnle RX_0RRD "branch on not low or equal" g5 esa,zarch -4740 bl RX_0RRD "branch on low" g5 esa,zarch -4740 bm RX_0RRD "branch on minus / if mixed" g5 esa,zarch -4750 bnhe RX_0RRD "branch on not high or equal" g5 esa,zarch -4760 blh RX_0RRD "branch on low or high" g5 esa,zarch -4770 bne RX_0RRD "branch on not equal" g5 esa,zarch -4770 bnz RX_0RRD "branch on not zero / if not zeros" g5 esa,zarch -4780 be RX_0RRD "branch on equal" g5 esa,zarch -4780 bz RX_0RRD "branch on zero / if zeros" g5 esa,zarch -4790 bnlh RX_0RRD "branch on not low or high" g5 esa,zarch -47a0 bhe RX_0RRD "branch on high or equal" g5 esa,zarch -47b0 bnl RX_0RRD "branch on not low" g5 esa,zarch -47b0 bnm RX_0RRD "branch on not minus / if not mixed" g5 esa,zarch -47c0 ble RX_0RRD "branch on low or equal" g5 esa,zarch -47d0 bnh RX_0RRD "branch on not high" g5 esa,zarch -47d0 bnp RX_0RRD "branch on not plus" g5 esa,zarch -47e0 bno RX_0RRD "branch on not overflow / if not ones" g5 esa,zarch -47f0 b RX_0RRD "unconditional branch" g5 esa,zarch -a714 jo RI_0P "jump on overflow / if ones" g5 esa,zarch -a724 jh RI_0P "jump on A high" g5 esa,zarch -a724 jp RI_0P "jump on plus" g5 esa,zarch -a734 jnle RI_0P "jump on not low or equal" g5 esa,zarch -a744 jl RI_0P "jump on A low" g5 esa,zarch -a744 jm RI_0P "jump on minus / if mixed" g5 esa,zarch -a754 jnhe RI_0P "jump on not high or equal" g5 esa,zarch -a764 jlh RI_0P "jump on low or high" g5 esa,zarch -a774 jne RI_0P "jump on A not equal B" g5 esa,zarch -a774 jnz RI_0P "jump on not zero / if not zeros" g5 esa,zarch -a784 je RI_0P "jump on A equal B" g5 esa,zarch -a784 jz RI_0P "jump on zero / if zeros" g5 esa,zarch -a794 jnlh RI_0P "jump on not low or high" g5 esa,zarch -a7a4 jhe RI_0P "jump on high or equal" g5 esa,zarch -a7b4 jnl RI_0P "jump on A not low" g5 esa,zarch -a7b4 jnm RI_0P "jump on not minus / if not mixed" g5 esa,zarch -a7c4 jle RI_0P "jump on low or equal" g5 esa,zarch -a7d4 jnh RI_0P "jump on A not high" g5 esa,zarch -a7d4 jnp RI_0P "jump on not plus" g5 esa,zarch -a7e4 jno RI_0P "jump on not overflow / if not ones" g5 esa,zarch -a7f4 j RI_0P "jump" g5 esa,zarch -b34a axbr RRE_FF "add extended bfp" g5 esa,zarch -b31a adbr RRE_FF "add long bfp" g5 esa,zarch -ed000000001a adb RXE_FRRD "add long bfp" g5 esa,zarch -b30a aebr RRE_FF "add short bfp" g5 esa,zarch -ed000000000a aeb RXE_FRRD "add short bfp" g5 esa,zarch -b349 cxbr RRE_FF "compare extended bfp" g5 esa,zarch -b319 cdbr RRE_FF "compare long bfp" g5 esa,zarch -ed0000000019 cdb RXE_FRRD "compare long bfp" g5 esa,zarch -b309 cebr RRE_FF "compare short bfp" g5 esa,zarch -ed0000000009 ceb RXE_FRRD "compare short bfp" g5 esa,zarch -b348 kxbr RRE_FF "compare and signal extended bfp" g5 esa,zarch -b318 kdbr RRE_FF "compare and signal long bfp" g5 esa,zarch -ed0000000018 kdb RXE_FRRD "compare and signal long bfp" g5 esa,zarch -b308 kebr RRE_FF "compare and signal short bfp" g5 esa,zarch -ed0000000008 keb RXE_FRRD "compare and signal short bfp" g5 esa,zarch -b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" g5 esa,zarch -b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" g5 esa,zarch -b394 cefbr RRE_RF "convert from fixed 32 to short bfp" g5 esa,zarch -b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" g5 esa,zarch -b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" g5 esa,zarch -b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" g5 esa,zarch -b34d dxbr RRE_FF "divide extended bfp" g5 esa,zarch -b31d ddbr RRE_FF "divide long bfp" g5 esa,zarch -ed000000001d ddb RXE_FRRD "divide long bfp" g5 esa,zarch -b30d debr RRE_FF "divide short bfp" g5 esa,zarch -ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch -b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch -b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch -b38c efpc RRE_RR "extract fpc" g5 esa,zarch -b342 ltxbr RRE_FF "load and test extended bfp" g5 esa,zarch -b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch -b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch -b343 lcxbr RRE_FF "load complement extended bfp" g5 esa,zarch -b313 lcdbr RRE_FF "load complement long bfp" g5 esa,zarch -b303 lcebr RRE_FF "load complement short bfp" g5 esa,zarch -b347 fixbr RRF_U0FF "load fp integer extended bfp" g5 esa,zarch -b35f fidbr RRF_U0FF "load fp integer long bfp" g5 esa,zarch -b357 fiebr RRF_U0FF "load fp integer short bfp" g5 esa,zarch -b29d lfpc S_RD "load fpc" g5 esa,zarch -b305 lxdbr RRE_FF "load lengthened long to extended bfp" g5 esa,zarch -ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" g5 esa,zarch -b306 lxebr RRE_FF "load lengthened short to extended bfp" g5 esa,zarch -ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" g5 esa,zarch -b304 ldebr RRE_FF "load lengthened short to long bfp" g5 esa,zarch -ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" g5 esa,zarch -b341 lnxbr RRE_FF "load negative extended bfp" g5 esa,zarch -b311 lndbr RRE_FF "load negative long bfp" g5 esa,zarch -b301 lnebr RRE_FF "load negative short bfp" g5 esa,zarch -b340 lpxbr RRE_FF "load positive extended bfp" g5 esa,zarch -b310 lpdbr RRE_FF "load positive long bfp" g5 esa,zarch -b300 lpebr RRE_FF "load positive short bfp" g5 esa,zarch -b345 ldxbr RRE_FF "load rounded extended to long bfp" g5 esa,zarch -b346 lexbr RRE_FF "load rounded extended to short bfp" g5 esa,zarch -b344 ledbr RRE_FF "load rounded long to short bfp" g5 esa,zarch -b34c mxbr RRE_FF "multiply extended bfp" g5 esa,zarch -b31c mdbr RRE_FF "multiply long bfp" g5 esa,zarch -ed000000001c mdb RXE_FRRD "multiply long bfp" g5 esa,zarch -b307 mxdbr RRE_FF "multiply long to extended bfp" g5 esa,zarch -ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" g5 esa,zarch -b317 meebr RRE_FF "multiply short bfp" g5 esa,zarch -ed0000000017 meeb RXE_FRRD "multiply short bfp" g5 esa,zarch -b30c mdebr RRE_FF "multiply short to long bfp" g5 esa,zarch -ed000000000c mdeb RXE_FRRD "multiply short to long bfp" g5 esa,zarch -b31e madbr RRF_F0FF "multiply and add long bfp" g5 esa,zarch -ed000000001e madb RXF_FRRDF "multiply and add long bfp" g5 esa,zarch -b30e maebr RRF_F0FF "multiply and add short bfp" g5 esa,zarch -ed000000000e maeb RXF_FRRDF "multiply and add short bfp" g5 esa,zarch -b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch -ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch -b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch -ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch -b384 sfpc RRE_RR "set fpc" g5 esa,zarch -b299 srnm S_RD "set rounding mode" g5 esa,zarch -b316 sqxbr RRE_FF "square root extended bfp" g5 esa,zarch -b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch -ed0000000015 sqdb RXE_FRRD "square root long bfp" g5 esa,zarch -b314 sqebr RRE_FF "square root short bfp" g5 esa,zarch -ed0000000014 sqeb RXE_FRRD "square root short bfp" g5 esa,zarch -b29c stfpc S_RD "store fpc" g5 esa,zarch -b34b sxbr RRE_FF "subtract extended bfp" g5 esa,zarch -b31b sdbr RRE_FF "subtract long bfp" g5 esa,zarch -ed000000001b sdb RXE_FRRD "subtract long bfp" g5 esa,zarch -b30b sebr RRE_FF "subtract short bfp" g5 esa,zarch -ed000000000b seb RXE_FRRD "subtract short bfp" g5 esa,zarch -ed0000000012 tcxb RXE_FRRD "test data class extended bfp" g5 esa,zarch -ed0000000011 tcdb RXE_FRRD "test data class long bfp" g5 esa,zarch -ed0000000010 tceb RXE_FRRD "test data class short bfp" g5 esa,zarch -b274 siga S_RD "signal adapter" g5 esa,zarch -b2a6 cuutf RRE_RR "convert unicode to utf-8" g5 esa,zarch -b2a7 cutfu RRE_RR "convert utf-8 to unicode" g5 esa,zarch -ee plo SS_RRRDRD2 "perform locked operation" g5 esa,zarch -b25a bsa RRE_RR "branch and set authority" g5 esa,zarch -b277 rp S_RD "resume program" g5 esa,zarch -0107 sckpf E "set clock programmable field" g5 esa,zarch -b27d stsi S_RD "store system information" g5 esa,zarch -01ff trap2 E "trap" g5 esa,zarch -b2ff trap4 S_RD "trap4" g5 esa,zarch -a700 tmlh RI_RU "test under mask low high" g5 esa,zarch -a701 tmll RI_RU "test under mask low low" g5 esa,zarch -b278 stcke S_RD "store clock extended" g5 esa,zarch -b2a5 tre RRE_RR "translate extended" g5 esa,zarch -eb000000008e mvclu RSE_RRRD "move long unicode" g5 esa,zarch -e9 pka SS_L0RDRD "pack ascii" g5 esa,zarch -e1 pku SS_L0RDRD "pack unicode" g5 esa,zarch -b993 troo RRE_RR "translate one to one" g5 esa,zarch -b992 trot RRE_RR "translate one to two" g5 esa,zarch -b991 trto RRE_RR "translate two to one" g5 esa,zarch -b990 trtt RRE_RR "translate two to two" g5 esa,zarch -ea unpka SS_L0RDRD "unpack ascii" g5 esa,zarch -e2 unpku SS_L0RDRD "unpack unicode" g5 esa,zarch -b358 thder RRE_RR "convert short bfp to long hfp" g5 esa,zarch -b359 thdr RRE_RR "convert long bfp to long hfp" g5 esa,zarch -b350 tbedr RRF_U0FF "convert long hfp to short bfp" g5 esa,zarch -b351 tbdr RRF_U0FF "convert long hfp to long bfp" g5 esa,zarch -b374 lzer RRE_R0 "load short zero" g5 esa,zarch -b375 lzdr RRE_R0 "load long zero" g5 esa,zarch -b376 lzxr RRE_R0 "load extended zero" g5 esa,zarch -# Here are the new esame instructions: -b946 bctgr RRE_RR "branch on count 64" z900 zarch -b900 lpgr RRE_RR "load positive 64" z900 zarch -b910 lpgfr RRE_RR "load positive 64<32" z900 zarch -b901 lngr RRE_RR "load negative 64" z900 zarch -b911 lngfr RRE_RR "load negative 64<32" z900 zarch -b902 ltgr RRE_RR "load and test 64" z900 zarch -b912 ltgfr RRE_RR "load and test 64<32" z900 zarch -b903 lcgr RRE_RR "load complement 64" z900 zarch -b913 lcgfr RRE_RR "load complement 64<32" z900 zarch -b980 ngr RRE_RR "and 64" z900 zarch -b921 clgr RRE_RR "compare logical 64" z900 zarch -b931 clgfr RRE_RR "compare logical 64<32" z900 zarch -b981 ogr RRE_RR "or 64" z900 zarch -b982 xgr RRE_RR "exclusive or 64" z900 zarch -b904 lgr RRE_RR "load 64" z900 zarch -b914 lgfr RRE_RR "load 64<32" z900 zarch -b920 cgr RRE_RR "compare 64" z900 zarch -b930 cgfr RRE_RR "compare 64<32" z900 zarch -b908 agr RRE_RR "add 64" z900 zarch -b918 agfr RRE_RR "add 64<32" z900 zarch -b909 sgr RRE_RR "subtract 64" z900 zarch zarch -b919 sgfr RRE_RR "subtract 64<32" z900 zarch -b90a algr RRE_RR "add logical 64" z900 zarch -b91a algfr RRE_RR "add logical 64<32" z900 zarch -b90b slgr RRE_RR "subtract logical 64" z900 zarch -b91b slgfr RRE_RR "subtract logical 64<32" z900 zarch -e30000000046 bctg RXE_RRRD "branch on count 64" z900 zarch -e3000000002e cvdg RXE_RRRD "convert to decimal 64" z900 zarch -e3000000000e cvbg RXE_RRRD "convert to binary 64" z900 zarch -e30000000024 stg RXE_RRRD "store 64" z900 zarch -e30000000080 ng RXE_RRRD "and 64" z900 zarch -e30000000021 clg RXE_RRRD "compare logical 64" z900 zarch -e30000000031 clgf RXE_RRRD "comparee logical 64<32" z900 zarch -e30000000081 og RXE_RRRD "or 64" z900 zarch -e30000000082 xg RXE_RRRD "exclusive or 64" z900 zarch -e30000000004 lg RXE_RRRD "load 64" z900 zarch -e30000000014 lgf RXE_RRRD "load 64<32" z900 zarch -e30000000015 lgh RXE_RRRD "load halfword 64" z900 zarch -e30000000020 cg RXE_RRRD "compare 64" z900 zarch -e30000000030 cgf RXE_RRRD "compare 64<32" z900 zarch -e30000000008 ag RXE_RRRD "add 64" z900 zarch -e30000000018 agf RXE_RRRD "add 64<32" z900 zarch -e30000000009 sg RXE_RRRD "subtract 64" z900 zarch -e30000000019 sgf RXE_RRRD "subtract 64<32" z900 zarch -e3000000000a alg RXE_RRRD "add logical 64" z900 zarch -e3000000001a algf RXE_RRRD "add logical 64<32" z900 zarch -e3000000000b slg RXE_RRRD "subtract logical 64" z900 zarch -e3000000001b slgf RXE_RRRD "subtract logical 64<32" z900 zarch -e3000000000c msg RXE_RRRD "multiply single 64" z900 zarch -e3000000001c msgf RXE_RRRD "multiply single 64<32" z900 zarch -ec0000000044 brxhg RIE_RRP "branch relative on index high 64" z900 zarch -ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" z900 zarch -eb0000000044 bxhg RSE_RRRD "branch on index high 64" z900 zarch -eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" z900 zarch -eb000000000c srlg RSE_RRRD "shift right single logical 64" z900 zarch -eb000000000d sllg RSE_RRRD "shift left single logical 64" z900 zarch -eb000000000a srag RSE_RRRD "shift right single 64" z900 zarch -eb000000000b slag RSE_RRRD "shift left single 64" z900 zarch -eb0000000024 stmg RSE_RRRD "store multiple 64" z900 zarch -eb0000000026 stmh RSE_RRRD "store multiple high" z900 zarch -eb0000000004 lmg RSE_RRRD "load multiple 64" z900 zarch -eb0000000096 lmh RSE_RRRD "load multiple high" z900 zarch -ef lmd SS_RRRDRD3 "load multiple disjoint" z900 zarch -eb000000000f tracg RSE_RRRD "trace 64" z900 zarch -e30000000003 lrag RXE_RRRD "load real address 64" z900 zarch -e50000000002 strag SSE_RDRD "store read address" z900 zarch -eb0000000025 stctg RSE_RRRD "store control 64" z900 zarch -eb000000002f lctlg RSE_RRRD "load control 64" z900 zarch -eb0000000030 csg RSE_RRRD "compare and swap 64" z900 zarch -eb000000003e cdsg RSE_RRRD "compare double and swap 64" z900 zarch -eb0000000020 clmh RSE_RURD "compare logical characters under mask high" z900 zarch -eb000000002c stcmh RSE_RURD "store characters under mask high" z900 zarch -eb0000000080 icmh RSE_RURD "insert characters under mask high" z900 zarch -a702 tmhh RI_RU "test under mask high high" z900 zarch -a703 tmhl RI_RU "test under mask high low" z900 zarch -c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch -c014 jgo RIL_0P "jump long on overflow / if ones" z900 esa,zarch -c024 jgh RIL_0P "jump long on high" z900 esa,zarch -c024 jgp RIL_0P "jump long on plus" z900 esa,zarch -c034 jgnle RIL_0P "jump long on not low or equal" z900 esa,zarch -c044 jgl RIL_0P "jump long on low" z900 esa,zarch -c044 jgm RIL_0P "jump long on minus / if mixed" z900 esa,zarch -c054 jgnhe RIL_0P "jump long on not high or equal" z900 esa,zarch -c064 jglh RIL_0P "jump long on low or high" z900 esa,zarch -c074 jgne RIL_0P "jump long on not equal" z900 esa,zarch -c074 jgnz RIL_0P "jump long on not zero / if not zeros" z900 esa,zarch -c084 jge RIL_0P "jump long on equal" z900 esa,zarch -c084 jgz RIL_0P "jump long on zero / if zeros" z900 esa,zarch -c094 jgnlh RIL_0P "jump long on not low or high" z900 esa,zarch -c0a4 jghe RIL_0P "jump long on high or equal" z900 esa,zarch -c0b4 jgnl RIL_0P "jump long on not low" z900 esa,zarch -c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" z900 esa,zarch -c0c4 jgle RIL_0P "jump long on low or equal" z900 esa,zarch -c0d4 jgnh RIL_0P "jump long on not high" z900 esa,zarch -c0d4 jgnp RIL_0P "jump long on not plus" z900 esa,zarch -c0e4 jgno RIL_0P "jump long on not overflow / if not ones" z900 esa,zarch -c0f4 jg RIL_0P "jump long" z900 esa,zarch -c005 brasl RIL_RP "branch relative and save long" z900 esa,zarch -a707 brctg RI_RP "branch relative on count 64" z900 zarch -a709 lghi RI_RI "load halfword immediate 64" z900 zarch -a70b aghi RI_RI "add halfword immediate 64" z900 zarch -a70d mghi RI_RI "multiply halfword immediate 64" z900 zarch -a70f cghi RI_RI "compare halfword immediate 64" z900 zarch -b925 sturg RRE_RR "store using real address 64" z900 zarch -b90e eregg RRE_RR "extract stacked registers 64" z900 zarch -b905 lurag RRE_RR "load using real address 64" z900 zarch -b90c msgr RRE_RR "multiply single 64" z900 zarch -b91c msgfr RRE_RR "multiply single 64<32" z900 zarch -b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" z900 zarch -b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" z900 zarch -b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" z900 zarch -b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" z900 zarch -b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" z900 zarch -b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" z900 zarch -b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" z900 zarch -b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" z900 zarch -b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" z900 zarch -b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" z900 zarch -b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" z900 zarch -b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" z900 zarch -010b tam E "test addressing mode" z900 esa,zarch -010c sam24 E "set addressing mode 24" z900 esa,zarch -010d sam31 E "set addressing mode 31" z900 esa,zarch -010e sam64 E "set addressing mode 64" z900 zarch -a500 iihh RI_RU "insert immediate high high" z900 zarch -a501 iihl RI_RU "insert immediate high low" z900 zarch -a502 iilh RI_RU "insert immediate low high" z900 zarch -a503 iill RI_RU "insert immediate low low" z900 zarch -a504 nihh RI_RU "and immediate high high" z900 zarch -a505 nihl RI_RU "and immediate high low" z900 zarch -a506 nilh RI_RU "and immediate low high" z900 zarch -a507 nill RI_RU "and immediate low low" z900 zarch -a508 oihh RI_RU "or immediate high high" z900 zarch -a509 oihl RI_RU "or immediate high low" z900 zarch -a50a oilh RI_RU "or immediate low high" z900 zarch -a50b oill RI_RU "or immediate low low" z900 zarch -a50c llihh RI_RU "load logical immediate high high" z900 zarch -a50d llihl RI_RU "load logical immediate high low" z900 zarch -a50e llilh RI_RU "load logical immediate low high" z900 zarch -a50f llill RI_RU "load logical immediate low low" z900 zarch -b2b1 stfl S_RD "store facility list" z900 esa,zarch -b2b2 lpswe S_RD "load psw extended" z900 zarch -b90d dsgr RRE_RR "divide single 64" z900 zarch -b90f lrvgr RRE_RR "load reversed 64" z900 zarch -b916 llgfr RRE_RR "load logical 64<32" z900 zarch -b917 llgtr RRE_RR "load logical thirty one bits" z900 zarch -b91d dsgfr RRE_RR "divide single 64<32" z900 zarch -b91f lrvr RRE_RR "load reversed 32" z900 esa,zarch -b986 mlgr RRE_RR "multiply logical 64" z900 zarch -b987 dlgr RRE_RR "divide logical 64" z900 zarch -b988 alcgr RRE_RR "add logical with carry 64" z900 zarch -b989 slbgr RRE_RR "subtract logical with borrow 64" z900 zarch -b98d epsw RRE_RR "extract psw" z900 esa,zarch -b996 mlr RRE_RR "multiply logical 32" z900 esa,zarch -b997 dlr RRE_RR "divide logical 32" z900 esa,zarch -b998 alcr RRE_RR "add logical with carry 32" z900 esa,zarch -b999 slbr RRE_RR "subtract logical with borrow 32" z900 esa,zarch -b99d esea RRE_R0 "extract and set extended authority" z900 zarch -c000 larl RIL_RP "load address relative long" z900 esa,zarch -e3000000000d dsg RXE_RRRD "divide single 64" z900 zarch -e3000000000f lrvg RXE_RRRD "load reversed 64" z900 zarch -e30000000016 llgf RXE_RRRD "load logical 64<32" z900 zarch -e30000000017 llgt RXE_RRRD "load logical thirty one bits" z900 zarch -e3000000001d dsgf RXE_RRRD "divide single 64<32" z900 zarch -e3000000001e lrv RXE_RRRD "load reversed 32" z900 esa,zarch -e3000000001f lrvh RXE_RRRD "load reversed 16" z900 esa,zarch -e3000000002f strvg RXE_RRRD "store reversed 64" z900 zarch -e3000000003e strv RXE_RRRD "store reversed 32" z900 esa,zarch -e3000000003f strvh RXE_RRRD "store reversed 64" z900 esa,zarch -e30000000086 mlg RXE_RRRD "multiply logical 64" z900 zarch -e30000000087 dlg RXE_RRRD "divide logical 64" z900 zarch -e30000000088 alcg RXE_RRRD "add logical with carry 64" z900 zarch -e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" z900 zarch -e3000000008e stpq RXE_RRRD "store pair to quadword" z900 zarch -e3000000008f lpq RXE_RRRD "load pair from quadword" z900 zarch -e30000000096 ml RXE_RRRD "multiply logical 32" z900 esa,zarch -e30000000097 dl RXE_RRRD "divide logical 32" z900 esa,zarch -e30000000098 alc RXE_RRRD "add logical with carry 32" z900 esa,zarch -e30000000099 slb RXE_RRRD "subtract logical with borrow 32" z900 esa,zarch -e30000000090 llgc RXE_RRRD "load logical character" z900 zarch -e30000000091 llgh RXE_RRRD "load logical halfword" z900 zarch -eb000000001c rllg RSE_RRRD "rotate left single logical 64" z900 zarch -eb000000001d rll RSE_RRRD "rotate left single logical 32" z900 esa,zarch -b369 cxr RRE_FF "compare extended hfp" g5 esa,zarch -b3b6 cxfr RRE_RF "convert from fixed 32 to extended hfp" g5 esa,zarch -b3b5 cdfr RRE_RF "convert from fixed 32 to long hfp" g5 esa,zarch -b3b4 cefr RRE_RF "convert from fixed 32 to short hfp" g5 esa,zarch -b3ba cfxr RRF_U0FR "convert to fixed extended hfp to 32" z900 zarch -b3b9 cfdr RRF_U0FR "convert to fixed long hfp to 32" z900 zarch -b3b8 cfer RRF_U0FR "convert to fixed short hfp to 32" z900 zarch -b362 ltxr RRE_FF "load and test extended hfp" g5 esa,zarch -b363 lcxr RRE_FF "load complement extended hfp" g5 esa,zarch -b367 fixr RRF_U0FF "load fp integer extended hfp" g5 esa,zarch -b37f fidr RRF_U0FF "load fp integer long hfp" g5 esa,zarch -b377 fier RRF_U0FF "load fp integer short hfp" g5 esa,zarch -b325 lxdr RRE_FF "load lengthened long to extended hfp" g5 esa,zarch -ed0000000025 lxd RXE_FRRD "load lengthened long to extended hfp" g5 esa,zarch -b326 lxer RRE_FF "load lengthened short to extended hfp" g5 esa,zarch -ed0000000026 lxe RXE_FRRD "load lengthened short to extended hfp" g5 esa,zarch -b324 lder RRE_FF "load lengthened short to long hfp" g5 esa,zarch -ed0000000024 lde RXE_FRRD "load lengthened short to long hfp" g5 esa,zarch -b361 lnxr RRE_FF "load negative long hfp" g5 esa,zarch -b360 lpxr RRE_FF "load positive long hfp" g5 esa,zarch -b366 lexr RRE_FF "load rounded extended to short hfp" g5 esa,zarch -35 ledr RR_FF "load rounded long to short hfp" g5 esa,zarch -b337 meer RRE_FF "multiply short hfp" g5 esa,zarch -ed0000000037 mee RXE_FRRD "multiply short hfp" g5 esa,zarch -b336 sqxr RRE_FF "square root extended hfp" g5 esa,zarch -ed0000000034 sqe RXE_FRRD "square root short hfp" g5 esa,zarch -b263 cmpsc RRE_RR "compression call" g5 esa,zarch -eb00000000c0 tp RSL_R0RD "test decimal" g5 esa,zarch -b365 lxr RRE_RR "load extended hfp" g5 esa,zarch -b22e pgin RRE_RR "page in" g5 esa,zarch -b22f pgout RRE_RR "page out" g5 esa,zarch -b276 xsch S_00 "cancel subchannel" g5 esa,zarch -# New long displacement instructions on z990 -e3000000005a ay RXY_RRRD "add with long offset" z990 zarch -e3000000007a ahy RXY_RRRD "add halfword with long offset" z990 zarch -e3000000005e aly RXY_RRRD "add logical with long offset" z990 zarch -eb0000000054 niy SIY_URD "and immediate with long offset" z990 zarch -e30000000054 ny RXY_RRRD "and with long offset" z990 zarch -e30000000059 cy RXY_RRRD "compare with long offset" z990 zarch -eb0000000014 csy RSY_RRRD "compare and swap with long offset" z990 zarch -eb0000000031 cdsy RSY_RRRD "compare double and swap with long offset" z990 zarch -e30000000079 chy RXY_RRRD "compare halfword with long offset" z990 zarch -e30000000055 cly RXY_RRRD "compare logical with long offset" z990 zarch -eb0000000055 cliy SIY_URD "compare logical immediate with long offset" z990 zarch -eb0000000021 clmy RSY_RURD "compare logical characters under mask with long offset" z990 zarch -e30000000006 cvby RXY_RRRD "convert to binary with long offset" z990 zarch -e30000000026 cvdy RXY_RRRD "convert to decimal with long offset" z990 zarch -eb0000000057 xiy SIY_URD "exclusive or immediate with long offset" z990 zarch -e30000000057 xy RXY_RRRD "exclusive or with long offset" z990 zarch -e30000000073 icy RXY_RRRD "insert character with long offset" z990 zarch -eb0000000081 icmy RSY_RURD "insert characters with long offset" z990 zarch -ed0000000065 ldy RXY_FRRD "load (long) with long offset" z990 zarch -ed0000000064 ley RXY_FRRD "load (short) with long offset" z990 zarch -e30000000058 ly RXY_RRRD "load with long offset" z990 zarch -eb000000009a lamy RSY_AARD "load access multiple" z990 zarch -e30000000071 lay RXY_RRRD "load address with long offset" z990 zarch -e30000000076 lb RXY_RRRD "load byte with long offset" z990 zarch -e30000000077 lgb RXY_RRRD "load byte with long offset 64" z990 zarch -e30000000078 lhy RXY_RRRD "load halfword with long offset" z990 zarch -eb0000000098 lmy RSY_RRRD "load multiple with long offset" z990 zarch -e30000000013 lray RXY_RRRD "load real address with long offset" z990 zarch -eb0000000052 mviy SIY_URD "move immediate with long offset" z990 zarch -e30000000051 msy RXY_RRRD "multiply single with long offset" z990 zarch -eb0000000056 oiy SIY_URD "or immediate with long offset" z990 zarch -e30000000056 oy RXY_RRRD "or with long offset" z990 zarch -ed0000000067 stdy RXY_FRRD "load (long) with long offset" z990 zarch -ed0000000066 stey RXY_FRRD "load (short) with long offset" z990 zarch -e30000000050 sty RXY_RRRD "store with long offset" z990 zarch -eb000000009b stamy RSY_AARD "store access multiple with long offset" z990 zarch -e30000000072 stcy RXY_RRRD "store character with long offset" z990 zarch -eb000000002d stcmy RSY_RURD "store characters under mask with long offset" z990 zarch -e30000000070 sthy RXY_RRRD "store halfword with long offset" z990 zarch -eb0000000090 stmy RSY_RRRD "store multiple with long offset" z990 zarch -e3000000005b sy RXY_RRRD "subtract with long offset" z990 zarch -e3000000007b shy RXY_RRRD "subtract halfword with long offset" z990 zarch -e3000000005f sly RXY_RRRD "subtract logical with long offset" z990 zarch -eb0000000051 tmy SIY_URD "test under mask with long offset" z990 zarch -# 'old' instructions extended to long displacement -# these instructions are entered into the opcode table twice. -e30000000003 lrag RXY_RRRD "load real address with long offset 64" z990 zarch -e30000000004 lg RXY_RRRD " load 64" z990 zarch -e30000000008 ag RXY_RRRD "add with long offset 64" z990 zarch -e30000000009 sg RXY_RRRD "subtract with long offset 64" z990 zarch -e3000000000a alg RXY_RRRD "add logical with long offset 64" z990 zarch -e3000000000b slg RXY_RRRD "subtract logical with long offset 64" z990 zarch -e3000000000c msg RXY_RRRD "multiply single with long offset 64" z990 zarch -e3000000000d dsg RXY_RRRD "divide single 64" z990 zarch -e3000000000e cvbg RXY_RRRD "convert to binary with long offset 64" z990 zarch -e3000000000f lrvg RXY_RRRD "load reversed 64" z990 zarch -e30000000014 lgf RXY_RRRD "load 64<32" z990 zarch -e30000000015 lgh RXY_RRRD "load halfword 64" z990 zarch -e30000000016 llgf RXY_RRRD "load logical 64<32" z990 zarch -e30000000017 llgt RXY_RRRD "load logical thirty one bits" z990 zarch -e30000000018 agf RXY_RRRD "add with long offset 64<32" z990 zarch -e30000000019 sgf RXY_RRRD "subtract with long offset 64<32" z990 zarch -e3000000001a algf RXY_RRRD "add logical with long offset 64<32" z990 zarch -e3000000001b slgf RXY_RRRD "subtract logical with long offset 64<32" z990 zarch -e3000000001c msgf RXY_RRRD "multiply single with long offset 64<32" z990 zarch -e3000000001d dsgf RXY_RRRD "divide single 64<32" z990 zarch -e3000000001e lrv RXY_RRRD "load reversed 32" z990 zarch -e3000000001f lrvh RXY_RRRD "load reversed 16" z990 zarch -e30000000020 cg RXY_RRRD "compare with long offset 64" z990 zarch -e30000000021 clg RXY_RRRD "compare logical with long offset 64" z990 zarch -e30000000024 stg RXY_RRRD "store with long offset 64" z990 zarch -e3000000002e cvdg RXY_RRRD "convert to decimal with long offset 64" z990 zarch -e3000000002f strvg RXY_RRRD "store reversed 64" z990 zarch -e30000000030 cgf RXY_RRRD "compare with long offset 64<32" z990 zarch -e30000000031 clgf RXY_RRRD "compare logical with long offset 64<32" z990 zarch -e3000000003e strv RXY_RRRD "store reversed 32" z990 zarch -e3000000003f strvh RXY_RRRD "store reversed 64" z990 zarch -e30000000046 bctg RXY_RRRD "branch on count 64" z990 zarch -e30000000080 ng RXY_RRRD "and with long offset 64" z990 zarch -e30000000081 og RXY_RRRD "or with long offset 64" z990 zarch -e30000000082 xg RXY_RRRD "exclusive or with long offset 64" z990 zarch -e30000000086 mlg RXY_RRRD "multiply logical 64" z990 zarch -e30000000087 dlg RXY_RRRD "divide logical 64" z990 zarch -e30000000088 alcg RXY_RRRD "add logical with carry 64" z990 zarch -e30000000089 slbg RXY_RRRD "subtract logical with borrow 64" z990 zarch -e3000000008e stpq RXY_RRRD "store pair to quadword" z990 zarch -e3000000008f lpq RXY_RRRD "load pair from quadword" z990 zarch -e30000000090 llgc RXY_RRRD "load logical character" z990 zarch -e30000000091 llgh RXY_RRRD "load logical halfword" z990 zarch -e30000000096 ml RXY_RRRD "multiply logical 32" z990 zarch -e30000000097 dl RXY_RRRD "divide logical 32" z990 zarch -e30000000098 alc RXY_RRRD "add logical with carry 32" z990 zarch -e30000000099 slb RXY_RRRD "subtract logical with borrow 32" z990 zarch -eb0000000004 lmg RSY_RRRD "load multiple with long offset 64" z990 zarch -eb000000000a srag RSY_RRRD "shift right single 64" z990 zarch -eb000000000b slag RSY_RRRD "shift left single 64" z990 zarch -eb000000000c srlg RSY_RRRD "shift right single logical 64" z990 zarch -eb000000000d sllg RSY_RRRD "shift left single logical 64" z990 zarch -eb000000000f tracg RSY_RRRD "trace 64" z990 zarch -eb000000001c rllg RSY_RRRD "rotate left single logical 64" z990 zarch -eb000000001d rll RSY_RRRD "rotate left single logical 32" z990 zarch -eb0000000020 clmh RSY_RURD "compare logical characters under mask high with long offset" z990 zarch -eb0000000024 stmg RSY_RRRD "store multiple with long offset 64" z990 zarch -eb0000000025 stctg RSY_RRRD "store control 64" z990 zarch -eb0000000026 stmh RSY_RRRD "store multiple high" z990 zarch -eb000000002c stcmh RSY_RURD "store characters under mask high with long offset" z990 zarch -eb000000002f lctlg RSY_RRRD "load control 64" z990 zarch -eb0000000030 csg RSY_RRRD "compare and swap with long offset 64" z990 zarch -eb000000003e cdsg RSY_RRRD "compare double and swap with long offset 64" z990 zarch -eb0000000044 bxhg RSY_RRRD "branch on index high 64" z990 zarch -eb0000000045 bxleg RSY_RRRD "branch on index low or equal 64" z990 zarch -eb0000000080 icmh RSY_RURD "insert characters under mask high with long offset" z990 zarch -eb000000008e mvclu RSY_RRRD "move long unicode" z990 zarch -eb000000008f clclu RSY_RRRD "compare logical long unicode with long offset" z990 zarch -eb0000000096 lmh RSY_RRRD "load multiple high" z990 zarch -# new z990 instructions -b98a cspg RRE_RR "compare and swap and purge" z990 zarch -b98e idte RRF_R0RR "invalidate dat table entry" z990 zarch -b33e madr RRF_F0FF "multiply and add long hfp" z990 esa,zarch -ed000000003e mad RXF_FRRDF "multiply and add long hfp" z990 esa,zarch -b32e maer RRF_F0FF "multiply and add short hfp" z990 esa,zarch -ed000000002e mae RXF_FRRDF "multiply and add shoft hfp" z990 esa,zarch -b33f msdr RRF_F0FF "multiply and subtract long hfp" z990 esa,zarch -ed000000003f msd RXF_FRRDF "multiply and subtract long hfp" z990 esa,zarch -b32f mser RRF_F0FF "mutliply and subtract short hfp" z990 esa,zarch -ed000000002f mse RXF_FRRDF "multiply and subttract short hfp" z990 esa,zarch -b92e km RRE_RR "cipher message" z990 esa,zarch -b92f kmc RRE_RR "cipher message with chaining" z990 esa,zarch -b93e kimd RRE_RR "compute intermediate message digest" z990 esa,zarch -b93f klmd RRE_RR "compute last message digest" z990 esa,zarch -b91e kmac RRE_RR "compute message authentication code" z990 esa,zarch diff --git a/contrib/binutils/opcodes/sh-dis.c b/contrib/binutils/opcodes/sh-dis.c deleted file mode 100644 index 2512f96..0000000 --- a/contrib/binutils/opcodes/sh-dis.c +++ /dev/null @@ -1,864 +0,0 @@ -/* Disassemble SH instructions. - Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003 - Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#define STATIC_TABLE -#define DEFINE_TABLE - -#include "sh-opc.h" -#include "dis-asm.h" - -#ifdef ARCH_all -#define INCLUDE_SHMEDIA -#endif - -static void print_movxy - PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *)); -static void print_insn_ddt PARAMS ((int, struct disassemble_info *)); -static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *)); -static void print_insn_ppi PARAMS ((int, struct disassemble_info *)); - -static void -print_movxy (op, rn, rm, fprintf_fn, stream) - const sh_opcode_info *op; - int rn, rm; - fprintf_ftype fprintf_fn; - void *stream; -{ - int n; - - fprintf_fn (stream, "%s\t", op->name); - for (n = 0; n < 2; n++) - { - switch (op->arg[n]) - { - case A_IND_N: - case AX_IND_N: - case AXY_IND_N: - case AY_IND_N: - case AYX_IND_N: - fprintf_fn (stream, "@r%d", rn); - break; - case A_INC_N: - case AX_INC_N: - case AXY_INC_N: - case AY_INC_N: - case AYX_INC_N: - fprintf_fn (stream, "@r%d+", rn); - break; - case AX_PMOD_N: - case AXY_PMOD_N: - fprintf_fn (stream, "@r%d+r8", rn); - break; - case AY_PMOD_N: - case AYX_PMOD_N: - fprintf_fn (stream, "@r%d+r9", rn); - break; - case DSP_REG_A_M: - fprintf_fn (stream, "a%c", '0' + rm); - break; - case DSP_REG_X: - fprintf_fn (stream, "x%c", '0' + rm); - break; - case DSP_REG_Y: - fprintf_fn (stream, "y%c", '0' + rm); - break; - case DSP_REG_AX: - fprintf_fn (stream, "%c%c", - (rm & 1) ? 'x' : 'a', - (rm & 2) ? '1' : '0'); - break; - case DSP_REG_XY: - fprintf_fn (stream, "%c%c", - (rm & 1) ? 'y' : 'x', - (rm & 2) ? '1' : '0'); - break; - case DSP_REG_AY: - fprintf_fn (stream, "%c%c", - (rm & 2) ? 'y' : 'a', - (rm & 1) ? '1' : '0'); - break; - case DSP_REG_YX: - fprintf_fn (stream, "%c%c", - (rm & 2) ? 'x' : 'y', - (rm & 1) ? '1' : '0'); - break; - default: - abort (); - } - if (n == 0) - fprintf_fn (stream, ","); - } -} - -/* Print a double data transfer insn. INSN is just the lower three - nibbles of the insn, i.e. field a and the bit that indicates if - a parallel processing insn follows. - Return nonzero if a field b of a parallel processing insns follows. */ - -static void -print_insn_ddt (insn, info) - int insn; - struct disassemble_info *info; -{ - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - - /* If this is just a nop, make sure to emit something. */ - if (insn == 0x000) - fprintf_fn (stream, "nopx\tnopy"); - - /* If a parallel processing insn was printed before, - and we got a non-nop, emit a tab. */ - if ((insn & 0x800) && (insn & 0x3ff)) - fprintf_fn (stream, "\t"); - - /* Check if either the x or y part is invalid. */ - if (((insn & 0xc) == 0 && (insn & 0x2a0)) - || ((insn & 3) == 0 && (insn & 0x150))) - if (info->mach != bfd_mach_sh_dsp - && info->mach != bfd_mach_sh3_dsp) - { - static const sh_opcode_info *first_movx, *first_movy; - const sh_opcode_info *op; - int is_movy; - - if (! first_movx) - { - for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;) - first_movx++; - for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;) - first_movy++; - } - - is_movy = ((insn & 3) != 0); - - if (is_movy) - op = first_movy; - else - op = first_movx; - - while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3) - || op->nibbles[3] != (unsigned) (insn & 0xf)) - op++; - - print_movxy (op, - (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0) - + 2 * is_movy - + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)), - (insn >> 6) & 3, - fprintf_fn, stream); - } - else - fprintf_fn (stream, ".word 0x%x", insn); - else - { - static const sh_opcode_info *first_movx, *first_movy; - const sh_opcode_info *opx, *opy; - unsigned int insn_x, insn_y; - - if (! first_movx) - { - for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;) - first_movx++; - for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;) - first_movy++; - } - insn_x = (insn >> 2) & 0xb; - if (insn_x) - { - for (opx = first_movx; opx->nibbles[2] != insn_x;) - opx++; - print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1, - fprintf_fn, stream); - } - insn_y = (insn & 3) | ((insn >> 1) & 8); - if (insn_y) - { - if (insn_x) - fprintf_fn (stream, "\t"); - for (opy = first_movy; opy->nibbles[2] != insn_y;) - opy++; - print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1, - fprintf_fn, stream); - } - } -} - -static void -print_dsp_reg (rm, fprintf_fn, stream) - int rm; - fprintf_ftype fprintf_fn; - void *stream; -{ - switch (rm) - { - case A_A1_NUM: - fprintf_fn (stream, "a1"); - break; - case A_A0_NUM: - fprintf_fn (stream, "a0"); - break; - case A_X0_NUM: - fprintf_fn (stream, "x0"); - break; - case A_X1_NUM: - fprintf_fn (stream, "x1"); - break; - case A_Y0_NUM: - fprintf_fn (stream, "y0"); - break; - case A_Y1_NUM: - fprintf_fn (stream, "y1"); - break; - case A_M0_NUM: - fprintf_fn (stream, "m0"); - break; - case A_A1G_NUM: - fprintf_fn (stream, "a1g"); - break; - case A_M1_NUM: - fprintf_fn (stream, "m1"); - break; - case A_A0G_NUM: - fprintf_fn (stream, "a0g"); - break; - default: - fprintf_fn (stream, "0x%x", rm); - break; - } -} - -static void -print_insn_ppi (field_b, info) - int field_b; - struct disassemble_info *info; -{ - static char *sx_tab[] = { "x0", "x1", "a0", "a1" }; - static char *sy_tab[] = { "y0", "y1", "m0", "m1" }; - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - unsigned int nib1, nib2, nib3; - unsigned int altnib1, nib4; - char *dc = NULL; - const sh_opcode_info *op; - - if ((field_b & 0xe800) == 0) - { - fprintf_fn (stream, "psh%c\t#%d,", - field_b & 0x1000 ? 'a' : 'l', - (field_b >> 4) & 127); - print_dsp_reg (field_b & 0xf, fprintf_fn, stream); - return; - } - if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000) - { - static char *du_tab[] = { "x0", "y0", "a0", "a1" }; - static char *se_tab[] = { "x0", "x1", "y0", "a1" }; - static char *sf_tab[] = { "y0", "y1", "x0", "a1" }; - static char *sg_tab[] = { "m0", "m1", "a0", "a1" }; - - if (field_b & 0x2000) - { - fprintf_fn (stream, "p%s %s,%s,%s\t", - (field_b & 0x1000) ? "add" : "sub", - sx_tab[(field_b >> 6) & 3], - sy_tab[(field_b >> 4) & 3], - du_tab[(field_b >> 0) & 3]); - } - else if ((field_b & 0xf0) == 0x10 - && info->mach != bfd_mach_sh_dsp - && info->mach != bfd_mach_sh3_dsp) - { - fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]); - } - else if ((field_b & 0xf3) != 0) - { - fprintf_fn (stream, ".word 0x%x\t", field_b); - } - fprintf_fn (stream, "pmuls%c%s,%s,%s", - field_b & 0x2000 ? ' ' : '\t', - se_tab[(field_b >> 10) & 3], - sf_tab[(field_b >> 8) & 3], - sg_tab[(field_b >> 2) & 3]); - return; - } - - nib1 = PPIC; - nib2 = field_b >> 12 & 0xf; - nib3 = field_b >> 8 & 0xf; - nib4 = field_b >> 4 & 0xf; - switch (nib3 & 0x3) - { - case 0: - dc = ""; - nib1 = PPI3; - break; - case 1: - dc = ""; - break; - case 2: - dc = "dct "; - nib3 -= 1; - break; - case 3: - dc = "dcf "; - nib3 -= 2; - break; - } - if (nib1 == PPI3) - altnib1 = PPI3NC; - else - altnib1 = nib1; - for (op = sh_table; op->name; op++) - { - if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1) - && op->nibbles[2] == nib2 - && op->nibbles[3] == nib3) - { - int n; - - switch (op->nibbles[4]) - { - case HEX_0: - break; - case HEX_XX00: - if ((nib4 & 3) != 0) - continue; - break; - case HEX_1: - if ((nib4 & 3) != 1) - continue; - break; - case HEX_00YY: - if ((nib4 & 0xc) != 0) - continue; - break; - case HEX_4: - if ((nib4 & 0xc) != 4) - continue; - break; - default: - abort (); - } - fprintf_fn (stream, "%s%s\t", dc, op->name); - for (n = 0; n < 3 && op->arg[n] != A_END; n++) - { - if (n && op->arg[1] != A_END) - fprintf_fn (stream, ","); - switch (op->arg[n]) - { - case DSP_REG_N: - print_dsp_reg (field_b & 0xf, fprintf_fn, stream); - break; - case DSP_REG_X: - fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]); - break; - case DSP_REG_Y: - fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]); - break; - case A_MACH: - fprintf_fn (stream, "mach"); - break; - case A_MACL: - fprintf_fn (stream, "macl"); - break; - default: - abort (); - } - } - return; - } - } - /* Not found. */ - fprintf_fn (stream, ".word 0x%x", field_b); -} - -int -print_insn_sh (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - unsigned char insn[4]; - unsigned char nibs[4]; - int status; - bfd_vma relmask = ~(bfd_vma) 0; - const sh_opcode_info *op; - int target_arch; - - switch (info->mach) - { - case bfd_mach_sh: - target_arch = arch_sh1; - /* SH coff object files lack information about the machine type, so - we end up with bfd_mach_sh unless it was set explicitly (which - could have happended if this is a call from gdb or the simulator.) */ - if (info->symbols - && bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour) - target_arch = arch_sh4; - break; - case bfd_mach_sh2: - target_arch = arch_sh2; - break; - case bfd_mach_sh2e: - target_arch = arch_sh2e; - break; - case bfd_mach_sh_dsp: - target_arch = arch_sh_dsp; - break; - case bfd_mach_sh3: - target_arch = arch_sh3; - break; - case bfd_mach_sh3_dsp: - target_arch = arch_sh3_dsp; - break; - case bfd_mach_sh3e: - target_arch = arch_sh3e; - break; - case bfd_mach_sh4: - case bfd_mach_sh4_nofpu: - target_arch = arch_sh4; - break; - case bfd_mach_sh4a: - case bfd_mach_sh4a_nofpu: - target_arch = arch_sh4a; - break; - case bfd_mach_sh4al_dsp: - target_arch = arch_sh4al_dsp; - break; - case bfd_mach_sh5: -#ifdef INCLUDE_SHMEDIA - status = print_insn_sh64 (memaddr, info); - if (status != -2) - return status; -#endif - /* When we get here for sh64, it's because we want to disassemble - SHcompact, i.e. arch_sh4. */ - target_arch = arch_sh4; - break; - default: - abort (); - } - - status = info->read_memory_func (memaddr, insn, 2, info); - - if (status != 0) - { - info->memory_error_func (status, memaddr, info); - return -1; - } - - if (info->endian == BFD_ENDIAN_LITTLE) - { - nibs[0] = (insn[1] >> 4) & 0xf; - nibs[1] = insn[1] & 0xf; - - nibs[2] = (insn[0] >> 4) & 0xf; - nibs[3] = insn[0] & 0xf; - } - else - { - nibs[0] = (insn[0] >> 4) & 0xf; - nibs[1] = insn[0] & 0xf; - - nibs[2] = (insn[1] >> 4) & 0xf; - nibs[3] = insn[1] & 0xf; - } - - if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up) - { - if (nibs[1] & 8) - { - int field_b; - - status = info->read_memory_func (memaddr + 2, insn, 2, info); - - if (status != 0) - { - info->memory_error_func (status, memaddr + 2, info); - return -1; - } - - if (info->endian == BFD_ENDIAN_LITTLE) - field_b = insn[1] << 8 | insn[0]; - else - field_b = insn[0] << 8 | insn[1]; - - print_insn_ppi (field_b, info); - print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); - return 4; - } - print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); - return 2; - } - for (op = sh_table; op->name; op++) - { - int n; - int imm = 0; - int rn = 0; - int rm = 0; - int rb = 0; - int disp_pc; - bfd_vma disp_pc_addr = 0; - - if ((op->arch & target_arch) == 0) - goto fail; - for (n = 0; n < 4; n++) - { - int i = op->nibbles[n]; - - if (i < 16) - { - if (nibs[n] == i) - continue; - goto fail; - } - switch (i) - { - case BRANCH_8: - imm = (nibs[2] << 4) | (nibs[3]); - if (imm & 0x80) - imm |= ~0xff; - imm = ((char) imm) * 2 + 4; - goto ok; - case BRANCH_12: - imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); - if (imm & 0x800) - imm |= ~0xfff; - imm = imm * 2 + 4; - goto ok; - case IMM0_4: - case IMM1_4: - imm = nibs[3]; - goto ok; - case IMM0_4BY2: - case IMM1_4BY2: - imm = nibs[3] << 1; - goto ok; - case IMM0_4BY4: - case IMM1_4BY4: - imm = nibs[3] << 2; - goto ok; - case IMM0_8: - case IMM1_8: - imm = (nibs[2] << 4) | nibs[3]; - goto ok; - case PCRELIMM_8BY2: - imm = ((nibs[2] << 4) | nibs[3]) << 1; - relmask = ~(bfd_vma) 1; - goto ok; - case PCRELIMM_8BY4: - imm = ((nibs[2] << 4) | nibs[3]) << 2; - relmask = ~(bfd_vma) 3; - goto ok; - case IMM0_8BY2: - case IMM1_8BY2: - imm = ((nibs[2] << 4) | nibs[3]) << 1; - goto ok; - case IMM0_8BY4: - case IMM1_8BY4: - imm = ((nibs[2] << 4) | nibs[3]) << 2; - goto ok; - case REG_N_D: - if ((nibs[n] & 1) != 0) - goto fail; - /* fall through */ - case REG_N: - rn = nibs[n]; - break; - case REG_M: - rm = nibs[n]; - break; - case REG_N_B01: - if ((nibs[n] & 0x3) != 1 /* binary 01 */) - goto fail; - rn = (nibs[n] & 0xc) >> 2; - break; - case REG_NM: - rn = (nibs[n] & 0xc) >> 2; - rm = (nibs[n] & 0x3); - break; - case REG_B: - rb = nibs[n] & 0x07; - break; - case SDT_REG_N: - /* sh-dsp: single data transfer. */ - rn = nibs[n]; - if ((rn & 0xc) != 4) - goto fail; - rn = rn & 0x3; - rn |= (!(rn & 2)) << 2; - break; - case PPI: - case REPEAT: - goto fail; - default: - abort (); - } - } - - ok: - fprintf_fn (stream, "%s\t", op->name); - disp_pc = 0; - for (n = 0; n < 3 && op->arg[n] != A_END; n++) - { - if (n && op->arg[1] != A_END) - fprintf_fn (stream, ","); - switch (op->arg[n]) - { - case A_IMM: - fprintf_fn (stream, "#%d", (char) (imm)); - break; - case A_R0: - fprintf_fn (stream, "r0"); - break; - case A_REG_N: - fprintf_fn (stream, "r%d", rn); - break; - case A_INC_N: - case AS_INC_N: - fprintf_fn (stream, "@r%d+", rn); - break; - case A_DEC_N: - case AS_DEC_N: - fprintf_fn (stream, "@-r%d", rn); - break; - case A_IND_N: - case AS_IND_N: - fprintf_fn (stream, "@r%d", rn); - break; - case A_DISP_REG_N: - fprintf_fn (stream, "@(%d,r%d)", imm, rn); - break; - case AS_PMOD_N: - fprintf_fn (stream, "@r%d+r8", rn); - break; - case A_REG_M: - fprintf_fn (stream, "r%d", rm); - break; - case A_INC_M: - fprintf_fn (stream, "@r%d+", rm); - break; - case A_DEC_M: - fprintf_fn (stream, "@-r%d", rm); - break; - case A_IND_M: - fprintf_fn (stream, "@r%d", rm); - break; - case A_DISP_REG_M: - fprintf_fn (stream, "@(%d,r%d)", imm, rm); - break; - case A_REG_B: - fprintf_fn (stream, "r%d_bank", rb); - break; - case A_DISP_PC: - disp_pc = 1; - disp_pc_addr = imm + 4 + (memaddr & relmask); - (*info->print_address_func) (disp_pc_addr, info); - break; - case A_IND_R0_REG_N: - fprintf_fn (stream, "@(r0,r%d)", rn); - break; - case A_IND_R0_REG_M: - fprintf_fn (stream, "@(r0,r%d)", rm); - break; - case A_DISP_GBR: - fprintf_fn (stream, "@(%d,gbr)", imm); - break; - case A_R0_GBR: - fprintf_fn (stream, "@(r0,gbr)"); - break; - case A_BDISP12: - case A_BDISP8: - (*info->print_address_func) (imm + memaddr, info); - break; - case A_SR: - fprintf_fn (stream, "sr"); - break; - case A_GBR: - fprintf_fn (stream, "gbr"); - break; - case A_VBR: - fprintf_fn (stream, "vbr"); - break; - case A_DSR: - fprintf_fn (stream, "dsr"); - break; - case A_MOD: - fprintf_fn (stream, "mod"); - break; - case A_RE: - fprintf_fn (stream, "re"); - break; - case A_RS: - fprintf_fn (stream, "rs"); - break; - case A_A0: - fprintf_fn (stream, "a0"); - break; - case A_X0: - fprintf_fn (stream, "x0"); - break; - case A_X1: - fprintf_fn (stream, "x1"); - break; - case A_Y0: - fprintf_fn (stream, "y0"); - break; - case A_Y1: - fprintf_fn (stream, "y1"); - break; - case DSP_REG_M: - print_dsp_reg (rm, fprintf_fn, stream); - break; - case A_SSR: - fprintf_fn (stream, "ssr"); - break; - case A_SPC: - fprintf_fn (stream, "spc"); - break; - case A_MACH: - fprintf_fn (stream, "mach"); - break; - case A_MACL: - fprintf_fn (stream, "macl"); - break; - case A_PR: - fprintf_fn (stream, "pr"); - break; - case A_SGR: - fprintf_fn (stream, "sgr"); - break; - case A_DBR: - fprintf_fn (stream, "dbr"); - break; - case F_REG_N: - fprintf_fn (stream, "fr%d", rn); - break; - case F_REG_M: - fprintf_fn (stream, "fr%d", rm); - break; - case DX_REG_N: - if (rn & 1) - { - fprintf_fn (stream, "xd%d", rn & ~1); - break; - } - case D_REG_N: - fprintf_fn (stream, "dr%d", rn); - break; - case DX_REG_M: - if (rm & 1) - { - fprintf_fn (stream, "xd%d", rm & ~1); - break; - } - case D_REG_M: - fprintf_fn (stream, "dr%d", rm); - break; - case FPSCR_M: - case FPSCR_N: - fprintf_fn (stream, "fpscr"); - break; - case FPUL_M: - case FPUL_N: - fprintf_fn (stream, "fpul"); - break; - case F_FR0: - fprintf_fn (stream, "fr0"); - break; - case V_REG_N: - fprintf_fn (stream, "fv%d", rn * 4); - break; - case V_REG_M: - fprintf_fn (stream, "fv%d", rm * 4); - break; - case XMTRX_M4: - fprintf_fn (stream, "xmtrx"); - break; - default: - abort (); - } - } - -#if 0 - /* This code prints instructions in delay slots on the same line - as the instruction which needs the delay slots. This can be - confusing, since other disassembler don't work this way, and - it means that the instructions are not all in a line. So I - disabled it. Ian. */ - if (!(info->flags & 1) - && (op->name[0] == 'j' - || (op->name[0] == 'b' - && (op->name[1] == 'r' - || op->name[1] == 's')) - || (op->name[0] == 'r' && op->name[1] == 't') - || (op->name[0] == 'b' && op->name[2] == '.'))) - { - info->flags |= 1; - fprintf_fn (stream, "\t(slot "); - print_insn_sh (memaddr + 2, info); - info->flags &= ~1; - fprintf_fn (stream, ")"); - return 4; - } -#endif - - if (disp_pc && strcmp (op->name, "mova") != 0) - { - int size; - bfd_byte bytes[4]; - - if (relmask == ~(bfd_vma) 1) - size = 2; - else - size = 4; - status = info->read_memory_func (disp_pc_addr, bytes, size, info); - if (status == 0) - { - unsigned int val; - - if (size == 2) - { - if (info->endian == BFD_ENDIAN_LITTLE) - val = bfd_getl16 (bytes); - else - val = bfd_getb16 (bytes); - } - else - { - if (info->endian == BFD_ENDIAN_LITTLE) - val = bfd_getl32 (bytes); - else - val = bfd_getb32 (bytes); - } - fprintf_fn (stream, "\t! 0x%x", val); - } - } - - return 2; - fail: - ; - - } - fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); - return 2; -} diff --git a/contrib/binutils/opcodes/sh-opc.h b/contrib/binutils/opcodes/sh-opc.h deleted file mode 100644 index 0ef1fab..0000000 --- a/contrib/binutils/opcodes/sh-opc.h +++ /dev/null @@ -1,955 +0,0 @@ -/* Definitions for SH opcodes. - Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003 - Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -typedef enum - { - HEX_0, - HEX_1, - HEX_2, - HEX_3, - HEX_4, - HEX_5, - HEX_6, - HEX_7, - HEX_8, - HEX_9, - HEX_A, - HEX_B, - HEX_C, - HEX_D, - HEX_E, - HEX_F, - HEX_XX00, - HEX_00YY, - REG_N, - REG_N_D, /* nnn0 */ - REG_N_B01, /* nn01 */ - REG_M, - SDT_REG_N, - REG_NM, - REG_B, - BRANCH_12, - BRANCH_8, - IMM0_4, - IMM0_4BY2, - IMM0_4BY4, - IMM1_4, - IMM1_4BY2, - IMM1_4BY4, - PCRELIMM_8BY2, - PCRELIMM_8BY4, - IMM0_8, - IMM0_8BY2, - IMM0_8BY4, - IMM1_8, - IMM1_8BY2, - IMM1_8BY4, - PPI, - NOPX, - NOPY, - MOVX, - MOVY, - MOVX_NOPY, - MOVY_NOPX, - PSH, - PMUL, - PPI3, - PPI3NC, - PDC, - PPIC, - REPEAT - } -sh_nibble_type; - -typedef enum - { - A_END, - A_BDISP12, - A_BDISP8, - A_DEC_M, - A_DEC_N, - A_DISP_GBR, - A_PC, - A_DISP_PC, - A_DISP_PC_ABS, - A_DISP_REG_M, - A_DISP_REG_N, - A_GBR, - A_IMM, - A_INC_M, - A_INC_N, - A_IND_M, - A_IND_N, - A_IND_R0_REG_M, - A_IND_R0_REG_N, - A_MACH, - A_MACL, - A_PR, - A_R0, - A_R0_GBR, - A_REG_M, - A_REG_N, - A_REG_B, - A_SR, - A_VBR, - A_MOD, - A_RE, - A_RS, - A_DSR, - DSP_REG_M, - DSP_REG_N, - DSP_REG_X, - DSP_REG_Y, - DSP_REG_E, - DSP_REG_F, - DSP_REG_G, - DSP_REG_A_M, - DSP_REG_AX, - DSP_REG_XY, - DSP_REG_AY, - DSP_REG_YX, - AX_INC_N, - AY_INC_N, - AXY_INC_N, - AYX_INC_N, - AX_IND_N, - AY_IND_N, - AXY_IND_N, - AYX_IND_N, - AX_PMOD_N, - AXY_PMOD_N, - AY_PMOD_N, - AYX_PMOD_N, - AS_DEC_N, - AS_INC_N, - AS_IND_N, - AS_PMOD_N, - A_A0, - A_X0, - A_X1, - A_Y0, - A_Y1, - A_SSR, - A_SPC, - A_SGR, - A_DBR, - F_REG_N, - F_REG_M, - D_REG_N, - D_REG_M, - X_REG_N, /* Only used for argument parsing. */ - X_REG_M, /* Only used for argument parsing. */ - DX_REG_N, - DX_REG_M, - V_REG_N, - V_REG_M, - XMTRX_M4, - F_FR0, - FPUL_N, - FPUL_M, - FPSCR_N, - FPSCR_M - } -sh_arg_type; - -typedef enum - { - A_A1_NUM = 5, - A_A0_NUM = 7, - A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM, - A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM - } -sh_dsp_reg_nums; - -#define arch_sh1 0x0001 -#define arch_sh2 0x0002 -#define arch_sh3 0x0004 -#define arch_sh3e 0x0008 -#define arch_sh4 0x0010 -#define arch_sh2e 0x0020 -#define arch_sh4a 0x0040 -#define arch_sh_dsp 0x0100 -#define arch_sh3_dsp 0x0200 -#define arch_sh4al_dsp 0x0400 -#define arch_sh4_nofpu 0x1000 -#define arch_sh4a_nofpu 0x2000 - -#define arch_sh1_up (arch_sh1 | arch_sh2_up) -#define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp) -#define arch_sh2e_up (arch_sh2e | arch_sh3e_up) -#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \ - | arch_sh4_nofp_up) -#define arch_sh3e_up (arch_sh3e | arch_sh4_up) -#define arch_sh4_up (arch_sh4 | arch_sh4a_up) -#define arch_sh4a_up (arch_sh4a) - -#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) -#define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) -#define arch_sh4al_dsp_up (arch_sh4al_dsp) - -#define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) -#define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) - -typedef struct -{ - char *name; - sh_arg_type arg[4]; - sh_nibble_type nibbles[5]; - int arch; -} sh_opcode_info; - -#ifdef DEFINE_TABLE - -const sh_opcode_info sh_table[] = - { -/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up}, - -/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up}, - -/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up}, - -/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up}, - -/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up}, - -/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up}, - -/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up}, - -/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, - -/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, - -/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, - -/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, - -/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up}, - -/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up}, - -/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up}, - -/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up}, - -/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up}, - -/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up}, - -/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up}, - -/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up}, - -/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up}, - -/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up}, - -/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up}, - -/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up}, - -/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up}, - -/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up}, - -/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up}, - -/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up}, - -/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up}, - -/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up}, - -/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up}, - -/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up}, - -/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}, - -/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}, - -/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}, - -/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_up}, - -/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up}, - -/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up}, - -/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up}, - -/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up}, - -/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up}, - -/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up}, - -/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}, - -/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}, - -/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}, - -/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_up}, - -/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up}, - -/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nofp_up}, - -/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up}, - -/* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up}, -/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up}, - -/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}, - -/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}, - -/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up}, - -/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up}, - -/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up}, - -/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}, - -/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}, - -/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up}, - -/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up}, - -/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up}, - -/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}, - -/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}, - -/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, - -/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up}, - -/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up}, - -/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up}, - -/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up}, - -/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up}, - -/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up}, - -/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up}, - -/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up}, - -/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up}, - -/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up}, - -/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up}, - -/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up}, - -/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up}, - -/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up}, - -/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up}, - -/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up}, - -/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up}, - -/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up}, - -/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up}, - -/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up}, - -/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up}, - -/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up}, - -/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up}, - -/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up}, - -/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up}, - -/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up}, - -/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up}, -/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nofp_up}, - -/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up}, -/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up}, - -/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up}, - -/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up}, -/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up}, - -/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, -/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}, - -/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, -/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up}, - -/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up}, - -/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up}, - -/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up}, -/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nofp_up}, - -/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nofp_up}, - -/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nofp_up}, - - -/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up}, - -/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, - -/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nofp_up}, - -/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, - -/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up}, - -/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up}, - -/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up}, - -/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up}, - -/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up}, - -/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up}, - -/* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up}, -/* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up}, - -/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up}, -/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, - -/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}, - -/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, - -/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, - -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_up}, - -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_up}, - -/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, - -/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up}, - -/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up}, - -/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up}, - -/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up}, - -/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up}, - -/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up}, - -/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up}, - -/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up}, - -/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up}, - -/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up}, - -/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}, - -/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, - -/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, - -/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_up}, - -/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up}, - -/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nofp_up}, - -/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up}, - -/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up}, - -/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up}, - -/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up}, - -/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}, - -/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}, - -/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}, - -/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_up}, - -/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_up}, - -/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up}, - -/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nofp_up}, - -/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nofp_up}, - -/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up}, - -/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up}, - -/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up}, - -/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up}, - -/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}, - -/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}, - -/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up}, - -/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up}, - -/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up}, - -/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}, - -/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}, - -/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up}, - -/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up}, - -/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up}, - -/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up}, - -/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up}, - -/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up}, - -/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up}, - -/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up}, - -/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up}, - -/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up}, - -/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up}, - -/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up}, - -/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up}, - -/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}, - -/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}, - -/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}, - -/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}, - -/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}, - -/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}, - -/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}, - -/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}, - -/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}, - -/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}, - -/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}, - -/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}, - -/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}, - -/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}, - -/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}, - -/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}, - -/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}, - -/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}, - -/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}, - -/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}, - -/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}, - -/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}, - -/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}, -/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}, -/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}, -/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}, -/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}, -/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}, -/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}, -/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}, - -/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up}, -/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up}, -/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up}, -/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up}, -/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up}, -/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up}, - -/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up}, -/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up}, -/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up}, -/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up}, -/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up}, -/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up}, - -/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}, -/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}, -/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}, -/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}, -/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}, -/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}, - -/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up}, -/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up}, -/* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up}, -/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up}, -/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up}, -/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up}, - -/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up}, -/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up}, -/* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up}, -/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up}, -/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up}, -/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up}, - -/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}, -/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}, -/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}, -/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ -{"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}, -/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}, -/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}, -/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ -{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}, -/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */ -{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up}, -/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ -{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}, -/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ -{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up}, -/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ -{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}, -/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */ -{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up}, -/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ -{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}, -/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ -{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up}, - -{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up}, -{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up}, - -/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}, -/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}, -/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}, -/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}, -/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}, -/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */ -{"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up}, -/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}, -/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}, -/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}, -/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}, -/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ -{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}, -/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ -{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}, -/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ -{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}, -/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ -{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}, -/* 10001101xxyynnnn pclr <DSP_REG_N> */ -{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}, -/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ -{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}, -/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ -{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}, -/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ -{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}, -/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ -{"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}, -/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ -{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}, -/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ -{"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}, -/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ -{"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}, -/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ -{"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}, -/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ -{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}, -/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ -{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}, -/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ -{"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}, -/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ -{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, - -/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, -/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up}, - -/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, -/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up}, - -/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, -/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up}, - -/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, -/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up}, - -/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up}, - -/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up}, - -/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, -/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up}, - -/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, - -/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}, - -/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}, - -/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, - -/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, -/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up}, - -/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, - -/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, -/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up}, - -/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, -/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, - -/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, -/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, - -/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, -/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, - -/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, -/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, - -/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, -/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, - -/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, -/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, - -/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, - -/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, - -/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, - -/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, - -/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, - -/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, - -/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, - -/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, - -/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, - -/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, - -/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, - -/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, - -/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, -/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up}, - -/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, -/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up}, - -/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, - -/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}, - -/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, - -/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up}, - -/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up}, -/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up}, - -/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, - -/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, - -/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, -/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up}, - -/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, -/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up}, - -/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, - -{ 0, {0}, {0}, 0 } -}; - -#endif diff --git a/contrib/binutils/opcodes/sparc-dis.c b/contrib/binutils/opcodes/sparc-dis.c deleted file mode 100644 index 6f360c6..0000000 --- a/contrib/binutils/opcodes/sparc-dis.c +++ /dev/null @@ -1,993 +0,0 @@ -/* Print SPARC instructions. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2002, 2003, 2004 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> - -#include "sysdep.h" -#include "opcode/sparc.h" -#include "dis-asm.h" -#include "libiberty.h" -#include "opintl.h" - -/* Bitmask of v9 architectures. */ -#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ - | (1 << SPARC_OPCODE_ARCH_V9A) \ - | (1 << SPARC_OPCODE_ARCH_V9B)) -/* 1 if INSN is for v9 only. */ -#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) -/* 1 if INSN is for v9. */ -#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) - -/* The sorted opcode table. */ -static const struct sparc_opcode **sorted_opcodes; - -/* For faster lookup, after insns are sorted they are hashed. */ -/* ??? I think there is room for even more improvement. */ - -#define HASH_SIZE 256 -/* It is important that we only look at insn code bits as that is how the - opcode table is hashed. OPCODE_BITS is a table of valid bits for each - of the main types (0,1,2,3). */ -static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; -#define HASH_INSN(INSN) \ - ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) -struct opcode_hash -{ - struct opcode_hash *next; - const struct sparc_opcode *opcode; -}; -static struct opcode_hash *opcode_hash_table[HASH_SIZE]; - -static void build_hash_table - PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int)); -static int is_delayed_branch PARAMS ((unsigned long)); -static int compare_opcodes PARAMS ((const PTR, const PTR)); -static int compute_arch_mask PARAMS ((unsigned long)); - -/* Sign-extend a value which is N bits long. */ -#define SEX(value, bits) \ - ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ - >> ((8 * sizeof (int)) - bits) ) - -static char *reg_names[] = -{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", - "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", - "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", - "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", - "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", - "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", -/* psr, wim, tbr, fpsr, cpsr are v8 only. */ - "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" -}; - -#define freg_names (®_names[4 * 8]) - -/* These are ordered according to there register number in - rdpr and wrpr insns. */ -static char *v9_priv_reg_names[] = -{ - "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", - "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", - "wstate", "fq" - /* "ver" - special cased */ -}; - -/* These are ordered according to there register number in - rd and wr insns (-16). */ -static char *v9a_asr_reg_names[] = -{ - "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", - "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr" -}; - -/* Macros used to extract instruction fields. Not all fields have - macros defined here, only those which are actually used. */ - -#define X_RD(i) (((i) >> 25) & 0x1f) -#define X_RS1(i) (((i) >> 14) & 0x1f) -#define X_LDST_I(i) (((i) >> 13) & 1) -#define X_ASI(i) (((i) >> 5) & 0xff) -#define X_RS2(i) (((i) >> 0) & 0x1f) -#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) -#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) -#define X_DISP22(i) (((i) >> 0) & 0x3fffff) -#define X_IMM22(i) X_DISP22 (i) -#define X_DISP30(i) (((i) >> 0) & 0x3fffffff) - -/* These are for v9. */ -#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) -#define X_DISP19(i) (((i) >> 0) & 0x7ffff) -#define X_MEMBAR(i) ((i) & 0x7f) - -/* Here is the union which was used to extract instruction fields - before the shift and mask macros were written. - - union sparc_insn - { - unsigned long int code; - struct - { - unsigned int anop:2; - #define op ldst.anop - unsigned int anrd:5; - #define rd ldst.anrd - unsigned int op3:6; - unsigned int anrs1:5; - #define rs1 ldst.anrs1 - unsigned int i:1; - unsigned int anasi:8; - #define asi ldst.anasi - unsigned int anrs2:5; - #define rs2 ldst.anrs2 - #define shcnt rs2 - } ldst; - struct - { - unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; - unsigned int IMM13:13; - #define imm13 IMM13.IMM13 - } IMM13; - struct - { - unsigned int anop:2; - unsigned int a:1; - unsigned int cond:4; - unsigned int op2:3; - unsigned int DISP22:22; - #define disp22 branch.DISP22 - #define imm22 disp22 - } branch; - struct - { - unsigned int anop:2; - unsigned int a:1; - unsigned int z:1; - unsigned int rcond:3; - unsigned int op2:3; - unsigned int DISP16HI:2; - unsigned int p:1; - unsigned int _rs1:5; - unsigned int DISP16LO:14; - } branch16; - struct - { - unsigned int anop:2; - unsigned int adisp30:30; - #define disp30 call.adisp30 - } call; - }; - - */ - -/* Nonzero if INSN is the opcode for a delayed branch. */ -static int -is_delayed_branch (insn) - unsigned long insn; -{ - struct opcode_hash *op; - - for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) - { - const struct sparc_opcode *opcode = op->opcode; - if ((opcode->match & insn) == opcode->match - && (opcode->lose & insn) == 0) - return (opcode->flags & F_DELAYED); - } - return 0; -} - -/* extern void qsort (); */ - -/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value - to compare_opcodes. */ -static unsigned int current_arch_mask; - -/* Print one instruction from MEMADDR on INFO->STREAM. - - We suffix the instruction with a comment that gives the absolute - address involved, as well as its symbolic form, if the instruction - is preceded by a findable `sethi' and it either adds an immediate - displacement to that register, or it is an `add' or `or' instruction - on that register. */ - -int -print_insn_sparc (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; -{ - FILE *stream = info->stream; - bfd_byte buffer[4]; - unsigned long insn; - register struct opcode_hash *op; - /* Nonzero of opcode table has been initialized. */ - static int opcodes_initialized = 0; - /* bfd mach number of last call. */ - static unsigned long current_mach = 0; - bfd_vma (*getword) (const void *); - - if (!opcodes_initialized - || info->mach != current_mach) - { - int i; - - current_arch_mask = compute_arch_mask (info->mach); - - if (!opcodes_initialized) - sorted_opcodes = (const struct sparc_opcode **) - xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *)); - /* Reset the sorted table so we can resort it. */ - for (i = 0; i < sparc_num_opcodes; ++i) - sorted_opcodes[i] = &sparc_opcodes[i]; - qsort ((char *) sorted_opcodes, sparc_num_opcodes, - sizeof (sorted_opcodes[0]), compare_opcodes); - - build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); - current_mach = info->mach; - opcodes_initialized = 1; - } - - { - int status = - (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - } - - /* On SPARClite variants such as DANlite (sparc86x), instructions - are always big-endian even when the machine is in little-endian mode. */ - if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) - getword = bfd_getb32; - else - getword = bfd_getl32; - - insn = getword (buffer); - - info->insn_info_valid = 1; /* We do return this info. */ - info->insn_type = dis_nonbranch; /* Assume non branch insn. */ - info->branch_delay_insns = 0; /* Assume no delay. */ - info->target = 0; /* Assume no target known. */ - - for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) - { - const struct sparc_opcode *opcode = op->opcode; - - /* If the insn isn't supported by the current architecture, skip it. */ - if (! (opcode->architecture & current_arch_mask)) - continue; - - if ((opcode->match & insn) == opcode->match - && (opcode->lose & insn) == 0) - { - /* Nonzero means that we have found an instruction which has - the effect of adding or or'ing the imm13 field to rs1. */ - int imm_added_to_rs1 = 0; - int imm_ored_to_rs1 = 0; - - /* Nonzero means that we have found a plus sign in the args - field of the opcode table. */ - int found_plus = 0; - - /* Nonzero means we have an annulled branch. */ - int is_annulled = 0; - - /* Do we have an `add' or `or' instruction combining an - immediate with rs1? */ - if (opcode->match == 0x80102000) /* or */ - imm_ored_to_rs1 = 1; - if (opcode->match == 0x80002000) /* add */ - imm_added_to_rs1 = 1; - - if (X_RS1 (insn) != X_RD (insn) - && strchr (opcode->args, 'r') != 0) - /* Can't do simple format if source and dest are different. */ - continue; - if (X_RS2 (insn) != X_RD (insn) - && strchr (opcode->args, 'O') != 0) - /* Can't do simple format if source and dest are different. */ - continue; - - (*info->fprintf_func) (stream, opcode->name); - - { - register const char *s; - - if (opcode->args[0] != ',') - (*info->fprintf_func) (stream, " "); - - for (s = opcode->args; *s != '\0'; ++s) - { - while (*s == ',') - { - (*info->fprintf_func) (stream, ","); - ++s; - switch (*s) - { - case 'a': - (*info->fprintf_func) (stream, "a"); - is_annulled = 1; - ++s; - continue; - case 'N': - (*info->fprintf_func) (stream, "pn"); - ++s; - continue; - - case 'T': - (*info->fprintf_func) (stream, "pt"); - ++s; - continue; - - default: - break; - } - } - - (*info->fprintf_func) (stream, " "); - - switch (*s) - { - case '+': - found_plus = 1; - - /* note fall-through */ - default: - (*info->fprintf_func) (stream, "%c", *s); - break; - - case '#': - (*info->fprintf_func) (stream, "0"); - break; - -#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) - case '1': - case 'r': - reg (X_RS1 (insn)); - break; - - case '2': - case 'O': - reg (X_RS2 (insn)); - break; - - case 'd': - reg (X_RD (insn)); - break; -#undef reg - -#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) -#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) - case 'e': - freg (X_RS1 (insn)); - break; - case 'v': /* double/even */ - case 'V': /* quad/multiple of 4 */ - fregx (X_RS1 (insn)); - break; - - case 'f': - freg (X_RS2 (insn)); - break; - case 'B': /* double/even */ - case 'R': /* quad/multiple of 4 */ - fregx (X_RS2 (insn)); - break; - - case 'g': - freg (X_RD (insn)); - break; - case 'H': /* double/even */ - case 'J': /* quad/multiple of 4 */ - fregx (X_RD (insn)); - break; -#undef freg -#undef fregx - -#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) - case 'b': - creg (X_RS1 (insn)); - break; - - case 'c': - creg (X_RS2 (insn)); - break; - - case 'D': - creg (X_RD (insn)); - break; -#undef creg - - case 'h': - (*info->fprintf_func) (stream, "%%hi(%#x)", - ((unsigned) 0xFFFFFFFF - & ((int) X_IMM22 (insn) << 10))); - break; - - case 'i': /* 13 bit immediate */ - case 'I': /* 11 bit immediate */ - case 'j': /* 10 bit immediate */ - { - int imm; - - if (*s == 'i') - imm = X_SIMM (insn, 13); - else if (*s == 'I') - imm = X_SIMM (insn, 11); - else - imm = X_SIMM (insn, 10); - - /* Check to see whether we have a 1+i, and take - note of that fact. - - Note: because of the way we sort the table, - we will be matching 1+i rather than i+1, - so it is OK to assume that i is after +, - not before it. */ - if (found_plus) - imm_added_to_rs1 = 1; - - if (imm <= 9) - (*info->fprintf_func) (stream, "%d", imm); - else - (*info->fprintf_func) (stream, "%#x", imm); - } - break; - - case 'X': /* 5 bit unsigned immediate */ - case 'Y': /* 6 bit unsigned immediate */ - { - int imm = X_IMM (insn, *s == 'X' ? 5 : 6); - - if (imm <= 9) - (info->fprintf_func) (stream, "%d", imm); - else - (info->fprintf_func) (stream, "%#x", (unsigned) imm); - } - break; - - case '3': - (info->fprintf_func) (stream, "%d", X_IMM (insn, 3)); - break; - - case 'K': - { - int mask = X_MEMBAR (insn); - int bit = 0x40, printed_one = 0; - const char *name; - - if (mask == 0) - (info->fprintf_func) (stream, "0"); - else - while (bit) - { - if (mask & bit) - { - if (printed_one) - (info->fprintf_func) (stream, "|"); - name = sparc_decode_membar (bit); - (info->fprintf_func) (stream, "%s", name); - printed_one = 1; - } - bit >>= 1; - } - break; - } - - case 'k': - info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; - (*info->print_address_func) (info->target, info); - break; - - case 'G': - info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; - (*info->print_address_func) (info->target, info); - break; - - case '6': - case '7': - case '8': - case '9': - (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); - break; - - case 'z': - (*info->fprintf_func) (stream, "%%icc"); - break; - - case 'Z': - (*info->fprintf_func) (stream, "%%xcc"); - break; - - case 'E': - (*info->fprintf_func) (stream, "%%ccr"); - break; - - case 's': - (*info->fprintf_func) (stream, "%%fprs"); - break; - - case 'o': - (*info->fprintf_func) (stream, "%%asi"); - break; - - case 'W': - (*info->fprintf_func) (stream, "%%tick"); - break; - - case 'P': - (*info->fprintf_func) (stream, "%%pc"); - break; - - case '?': - if (X_RS1 (insn) == 31) - (*info->fprintf_func) (stream, "%%ver"); - else if ((unsigned) X_RS1 (insn) < 16) - (*info->fprintf_func) (stream, "%%%s", - v9_priv_reg_names[X_RS1 (insn)]); - else - (*info->fprintf_func) (stream, "%%reserved"); - break; - - case '!': - if ((unsigned) X_RD (insn) < 15) - (*info->fprintf_func) (stream, "%%%s", - v9_priv_reg_names[X_RD (insn)]); - else - (*info->fprintf_func) (stream, "%%reserved"); - break; - - case '/': - if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) - (*info->fprintf_func) (stream, "%%reserved"); - else - (*info->fprintf_func) (stream, "%%%s", - v9a_asr_reg_names[X_RS1 (insn)-16]); - break; - - case '_': - if (X_RD (insn) < 16 || X_RD (insn) > 25) - (*info->fprintf_func) (stream, "%%reserved"); - else - (*info->fprintf_func) (stream, "%%%s", - v9a_asr_reg_names[X_RD (insn)-16]); - break; - - case '*': - { - const char *name = sparc_decode_prefetch (X_RD (insn)); - - if (name) - (*info->fprintf_func) (stream, "%s", name); - else - (*info->fprintf_func) (stream, "%d", X_RD (insn)); - break; - } - - case 'M': - (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn)); - break; - - case 'm': - (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn)); - break; - - case 'L': - info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; - (*info->print_address_func) (info->target, info); - break; - - case 'n': - (*info->fprintf_func) - (stream, "%#x", SEX (X_DISP22 (insn), 22)); - break; - - case 'l': - info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; - (*info->print_address_func) (info->target, info); - break; - - case 'A': - { - const char *name = sparc_decode_asi (X_ASI (insn)); - - if (name) - (*info->fprintf_func) (stream, "%s", name); - else - (*info->fprintf_func) (stream, "(%d)", X_ASI (insn)); - break; - } - - case 'C': - (*info->fprintf_func) (stream, "%%csr"); - break; - - case 'F': - (*info->fprintf_func) (stream, "%%fsr"); - break; - - case 'p': - (*info->fprintf_func) (stream, "%%psr"); - break; - - case 'q': - (*info->fprintf_func) (stream, "%%fq"); - break; - - case 'Q': - (*info->fprintf_func) (stream, "%%cq"); - break; - - case 't': - (*info->fprintf_func) (stream, "%%tbr"); - break; - - case 'w': - (*info->fprintf_func) (stream, "%%wim"); - break; - - case 'x': - (*info->fprintf_func) (stream, "%d", - ((X_LDST_I (insn) << 8) - + X_ASI (insn))); - break; - - case 'y': - (*info->fprintf_func) (stream, "%%y"); - break; - - case 'u': - case 'U': - { - int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); - const char *name = sparc_decode_sparclet_cpreg (val); - - if (name) - (*info->fprintf_func) (stream, "%s", name); - else - (*info->fprintf_func) (stream, "%%cpreg(%d)", val); - break; - } - } - } - } - - /* If we are adding or or'ing something to rs1, then - check to see whether the previous instruction was - a sethi to the same register as in the sethi. - If so, attempt to print the result of the add or - or (in this context add and or do the same thing) - and its symbolic value. */ - if (imm_ored_to_rs1 || imm_added_to_rs1) - { - unsigned long prev_insn; - int errcode; - - if (memaddr >= 4) - errcode = - (*info->read_memory_func) - (memaddr - 4, buffer, sizeof (buffer), info); - else - errcode = 1; - - prev_insn = getword (buffer); - - if (errcode == 0) - { - /* If it is a delayed branch, we need to look at the - instruction before the delayed branch. This handles - sequences such as: - - sethi %o1, %hi(_foo), %o1 - call _printf - or %o1, %lo(_foo), %o1 */ - - if (is_delayed_branch (prev_insn)) - { - if (memaddr >= 8) - errcode = (*info->read_memory_func) - (memaddr - 8, buffer, sizeof (buffer), info); - else - errcode = 1; - - prev_insn = getword (buffer); - } - } - - /* If there was a problem reading memory, then assume - the previous instruction was not sethi. */ - if (errcode == 0) - { - /* Is it sethi to the same register? */ - if ((prev_insn & 0xc1c00000) == 0x01000000 - && X_RD (prev_insn) == X_RS1 (insn)) - { - (*info->fprintf_func) (stream, "\t! "); - info->target = - ((unsigned) 0xFFFFFFFF - & ((int) X_IMM22 (prev_insn) << 10)); - if (imm_added_to_rs1) - info->target += X_SIMM (insn, 13); - else - info->target |= X_SIMM (insn, 13); - (*info->print_address_func) (info->target, info); - info->insn_type = dis_dref; - info->data_size = 4; /* FIXME!!! */ - } - } - } - - if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) - { - /* FIXME -- check is_annulled flag */ - if (opcode->flags & F_UNBR) - info->insn_type = dis_branch; - if (opcode->flags & F_CONDBR) - info->insn_type = dis_condbranch; - if (opcode->flags & F_JSR) - info->insn_type = dis_jsr; - if (opcode->flags & F_DELAYED) - info->branch_delay_insns = 1; - } - - return sizeof (buffer); - } - } - - info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ - (*info->fprintf_func) (stream, _("unknown")); - return sizeof (buffer); -} - -/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ - -static int -compute_arch_mask (mach) - unsigned long mach; -{ - switch (mach) - { - case 0 : - case bfd_mach_sparc : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); - case bfd_mach_sparc_sparclet : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); - case bfd_mach_sparc_sparclite : - case bfd_mach_sparc_sparclite_le : - /* sparclites insns are recognized by default (because that's how - they've always been treated, for better or worse). Kludge this by - indicating generic v8 is also selected. */ - return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) - | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); - case bfd_mach_sparc_v8plus : - case bfd_mach_sparc_v9 : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); - case bfd_mach_sparc_v8plusa : - case bfd_mach_sparc_v9a : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); - case bfd_mach_sparc_v8plusb : - case bfd_mach_sparc_v9b : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); - } - abort (); -} - -/* Compare opcodes A and B. */ - -static int -compare_opcodes (a, b) - const PTR a; - const PTR b; -{ - struct sparc_opcode *op0 = * (struct sparc_opcode **) a; - struct sparc_opcode *op1 = * (struct sparc_opcode **) b; - unsigned long int match0 = op0->match, match1 = op1->match; - unsigned long int lose0 = op0->lose, lose1 = op1->lose; - register unsigned int i; - - /* If one (and only one) insn isn't supported by the current architecture, - prefer the one that is. If neither are supported, but they're both for - the same architecture, continue processing. Otherwise (both unsupported - and for different architectures), prefer lower numbered arch's (fudged - by comparing the bitmasks). */ - if (op0->architecture & current_arch_mask) - { - if (! (op1->architecture & current_arch_mask)) - return -1; - } - else - { - if (op1->architecture & current_arch_mask) - return 1; - else if (op0->architecture != op1->architecture) - return op0->architecture - op1->architecture; - } - - /* If a bit is set in both match and lose, there is something - wrong with the opcode table. */ - if (match0 & lose0) - { - fprintf - (stderr, - /* xgettext:c-format */ - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), - op0->name, match0, lose0); - op0->lose &= ~op0->match; - lose0 = op0->lose; - } - - if (match1 & lose1) - { - fprintf - (stderr, - /* xgettext:c-format */ - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), - op1->name, match1, lose1); - op1->lose &= ~op1->match; - lose1 = op1->lose; - } - - /* Because the bits that are variable in one opcode are constant in - another, it is important to order the opcodes in the right order. */ - for (i = 0; i < 32; ++i) - { - unsigned long int x = 1 << i; - int x0 = (match0 & x) != 0; - int x1 = (match1 & x) != 0; - - if (x0 != x1) - return x1 - x0; - } - - for (i = 0; i < 32; ++i) - { - unsigned long int x = 1 << i; - int x0 = (lose0 & x) != 0; - int x1 = (lose1 & x) != 0; - - if (x0 != x1) - return x1 - x0; - } - - /* They are functionally equal. So as long as the opcode table is - valid, we can put whichever one first we want, on aesthetic grounds. */ - - /* Our first aesthetic ground is that aliases defer to real insns. */ - { - int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); - if (alias_diff != 0) - /* Put the one that isn't an alias first. */ - return alias_diff; - } - - /* Except for aliases, two "identical" instructions had - better have the same opcode. This is a sanity check on the table. */ - i = strcmp (op0->name, op1->name); - if (i) - { - if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ - return i; - else - fprintf (stderr, - /* xgettext:c-format */ - _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), - op0->name, op1->name); - } - - /* Fewer arguments are preferred. */ - { - int length_diff = strlen (op0->args) - strlen (op1->args); - if (length_diff != 0) - /* Put the one with fewer arguments first. */ - return length_diff; - } - - /* Put 1+i before i+1. */ - { - char *p0 = (char *) strchr (op0->args, '+'); - char *p1 = (char *) strchr (op1->args, '+'); - - if (p0 && p1) - { - /* There is a plus in both operands. Note that a plus - sign cannot be the first character in args, - so the following [-1]'s are valid. */ - if (p0[-1] == 'i' && p1[1] == 'i') - /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ - return 1; - if (p0[1] == 'i' && p1[-1] == 'i') - /* op0 is 1+i and op1 is i+1, so op0 goes first. */ - return -1; - } - } - - /* Put 1,i before i,1. */ - { - int i0 = strncmp (op0->args, "i,1", 3) == 0; - int i1 = strncmp (op1->args, "i,1", 3) == 0; - - if (i0 ^ i1) - return i0 - i1; - } - - /* They are, as far as we can tell, identical. - Since qsort may have rearranged the table partially, there is - no way to tell which one was first in the opcode table as - written, so just say there are equal. */ - /* ??? This is no longer true now that we sort a vector of pointers, - not the table itself. */ - return 0; -} - -/* Build a hash table from the opcode table. - OPCODE_TABLE is a sorted list of pointers into the opcode table. */ - -static void -build_hash_table (opcode_table, hash_table, num_opcodes) - const struct sparc_opcode **opcode_table; - struct opcode_hash **hash_table; - int num_opcodes; -{ - register int i; - int hash_count[HASH_SIZE]; - static struct opcode_hash *hash_buf = NULL; - - /* Start at the end of the table and work backwards so that each - chain is sorted. */ - - memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); - memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); - if (hash_buf != NULL) - free (hash_buf); - hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes); - for (i = num_opcodes - 1; i >= 0; --i) - { - register int hash = HASH_INSN (opcode_table[i]->match); - register struct opcode_hash *h = &hash_buf[i]; - h->next = hash_table[hash]; - h->opcode = opcode_table[i]; - hash_table[hash] = h; - ++hash_count[hash]; - } - -#if 0 /* for debugging */ - { - int min_count = num_opcodes, max_count = 0; - int total; - - for (i = 0; i < HASH_SIZE; ++i) - { - if (hash_count[i] < min_count) - min_count = hash_count[i]; - if (hash_count[i] > max_count) - max_count = hash_count[i]; - total += hash_count[i]; - } - - printf ("Opcode hash table stats: min %d, max %d, ave %f\n", - min_count, max_count, (double) total / HASH_SIZE); - } -#endif -} diff --git a/contrib/binutils/opcodes/sparc-opc.c b/contrib/binutils/opcodes/sparc-opc.c deleted file mode 100644 index 9470898..0000000 --- a/contrib/binutils/opcodes/sparc-opc.c +++ /dev/null @@ -1,2018 +0,0 @@ -/* Table of opcodes for the sparc. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2002, 2004 - Free Software Foundation, Inc. - -This file is part of the BFD library. - -BFD is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2, or (at your option) any later -version. - -BFD is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with this software; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* FIXME-someday: perhaps the ,a's and such should be embedded in the - instruction's name rather than the args. This would make gas faster, pinsn - slower, but would mess up some macros a bit. xoxorich. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/sparc.h" - -/* Some defines to make life easy. */ -#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) -#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) -#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) -#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) -#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) -#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) -#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) -#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) - -/* Bit masks of architectures supporting the insn. */ - -#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ - | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) -/* v6 insns not supported on the sparclet */ -#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ - | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) -#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ - | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) -/* Although not all insns are implemented in hardware, sparclite is defined - to be a superset of v8. Unimplemented insns trap and are then theoretically - implemented in software. - It's not clear that the same is true for sparclet, although the docs - suggest it is. Rather than complicating things, the sparclet assembler - recognizes all v8 insns. */ -#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \ - | MASK_V9 | MASK_V9A | MASK_V9B) -#define sparclet (MASK_SPARCLET) -#define sparclite (MASK_SPARCLITE) -#define v9 (MASK_V9 | MASK_V9A | MASK_V9B) -#define v9a (MASK_V9A | MASK_V9B) -#define v9b (MASK_V9B) -/* v6 insns not supported by v9 */ -#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ - | MASK_SPARCLET | MASK_SPARCLITE) -/* v9a instructions which would appear to be aliases to v9's impdep's - otherwise */ -#define v9notv9a (MASK_V9) - -/* Table of opcode architectures. - The order is defined in opcode/sparc.h. */ - -const struct sparc_opcode_arch sparc_opcode_archs[] = { - { "v6", MASK_V6 }, - { "v7", MASK_V6 | MASK_V7 }, - { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, - { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET }, - { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE }, - /* ??? Don't some v8 priviledged insns conflict with v9? */ - { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 }, - /* v9 with ultrasparc additions */ - { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A }, - /* v9 with cheetah additions */ - { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B }, - { NULL, 0 } -}; - -/* Given NAME, return it's architecture entry. */ - -enum sparc_opcode_arch_val -sparc_opcode_lookup_arch (name) - const char *name; -{ - const struct sparc_opcode_arch *p; - - for (p = &sparc_opcode_archs[0]; p->name; ++p) - { - if (strcmp (name, p->name) == 0) - return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); - } - - return SPARC_OPCODE_ARCH_BAD; -} - -/* Branch condition field. */ -#define COND(x) (((x)&0xf)<<25) - -/* v9: Move (MOVcc and FMOVcc) condition field. */ -#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */ - -/* v9: Move register (MOVRcc and FMOVRcc) condition field. */ -#define RCOND(x) (((x)&0x7)<<10) /* v9 */ - -#define CONDA (COND(0x8)) -#define CONDCC (COND(0xd)) -#define CONDCS (COND(0x5)) -#define CONDE (COND(0x1)) -#define CONDG (COND(0xa)) -#define CONDGE (COND(0xb)) -#define CONDGU (COND(0xc)) -#define CONDL (COND(0x3)) -#define CONDLE (COND(0x2)) -#define CONDLEU (COND(0x4)) -#define CONDN (COND(0x0)) -#define CONDNE (COND(0x9)) -#define CONDNEG (COND(0x6)) -#define CONDPOS (COND(0xe)) -#define CONDVC (COND(0xf)) -#define CONDVS (COND(0x7)) - -#define CONDNZ CONDNE -#define CONDZ CONDE -#define CONDGEU CONDCC -#define CONDLU CONDCS - -#define FCONDA (COND(0x8)) -#define FCONDE (COND(0x9)) -#define FCONDG (COND(0x6)) -#define FCONDGE (COND(0xb)) -#define FCONDL (COND(0x4)) -#define FCONDLE (COND(0xd)) -#define FCONDLG (COND(0x2)) -#define FCONDN (COND(0x0)) -#define FCONDNE (COND(0x1)) -#define FCONDO (COND(0xf)) -#define FCONDU (COND(0x7)) -#define FCONDUE (COND(0xa)) -#define FCONDUG (COND(0x5)) -#define FCONDUGE (COND(0xc)) -#define FCONDUL (COND(0x3)) -#define FCONDULE (COND(0xe)) - -#define FCONDNZ FCONDNE -#define FCONDZ FCONDE - -#define ICC (0) /* v9 */ -#define XCC (1<<12) /* v9 */ -#define FCC(x) (((x)&0x3)<<11) /* v9 */ -#define FBFCC(x) (((x)&0x3)<<20) /* v9 */ - -/* The order of the opcodes in the table is significant: - - * The assembler requires that all instances of the same mnemonic must - be consecutive. If they aren't, the assembler will bomb at runtime. - - * The disassembler should not care about the order of the opcodes. - -*/ - -/* Entries for commutative arithmetic operations. */ -/* ??? More entries can make use of this. */ -#define COMMUTEOP(opcode, op3, arch_mask) \ -{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ -{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } - -const struct sparc_opcode sparc_opcodes[] = { - -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, -{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, -{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, -{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ - -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, -{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, -{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ - -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, -{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, -{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ - -/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the - 'ld' pseudo-op in v9. */ -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, -{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ - -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, -{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ - -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, -{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ - -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, -{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ - -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ - -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ -{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ - -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ - -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, -{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ - -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ - -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, -{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ - -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, -{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ - -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, -{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ - -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, -{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, -{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, -{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, -{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, -{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, -{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ - -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, -{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, -{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, -{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, -{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, -{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ -{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, -{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ - -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ - -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, -{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, -{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ - -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, -{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, -{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ - -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, -{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, -{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ - -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, -{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ -{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, -{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, -{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ -{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, -{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, -{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ - -{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */ -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */ - -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, -{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ - -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, -{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, -{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ - -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ -{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, -{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ -{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, -{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ - -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ - -{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ -{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ - -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, -{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ - -{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, -{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ -{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, -{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ - -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ - -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, -{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, -{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, -{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ - -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, -{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, -{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ - -{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */ -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */ - -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, -{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, -{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, -{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ - -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, -{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, -{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ - -{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ -{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, -{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, -{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ - -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, -{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ - -{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, -{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ -{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, -{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, -{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ - -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, -{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, -{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ - -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, -{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, -{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ - -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, -{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, -{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ - -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, -{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, -{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ - -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, -{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, -{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ - -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, -{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ - -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, -{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, -{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ - -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, -{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ - -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ - -{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, -{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, - -{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ -{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ - -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, -{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, -{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, - -{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, -{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, - -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, -{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, -{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, - -/* IFLUSH was renamed to FLUSH in v8. */ -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, -{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, -{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, - -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, -{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, -{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, - -{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, - -{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, -{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, - -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, -{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, -{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ - -{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, -{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, -{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, -{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, -{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, -{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, - -{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, -{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, -{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, -{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, -{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, -{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, - -{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, - -{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, -{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, - -{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, -{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, - -{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 }, -{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 }, - -{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ -{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, -{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ - -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, -{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ - -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, -{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ - -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, -{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ - -{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, -{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, - -/* This is not a commutative instruction. */ -{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, - -/* This is not a commutative instruction. */ -{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, - -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ -{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ -{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ - -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ -{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ -{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ -{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ -{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ -{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ -{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ -{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ -{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ -{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ -{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ -{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ - -{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ -{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ -{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ -{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ -{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ -{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ - -{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ -{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ -{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ -{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ -{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ -{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ -{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ -{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ -{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ -{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ -{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ -{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ -{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ -{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ -{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ -{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ -{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */ -{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */ -{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */ -{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */ - -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ -{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ -{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ -{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ -{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ - -{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ -{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ -{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ -{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ - -{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ -{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ -{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ -{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */ -{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */ - -{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ -{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ -{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ - -/* ??? This group seems wrong. A three operand move? */ -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ - -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ -{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ -{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ -{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ -{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ - -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ -{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ -{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ -{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ -{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ -{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ -{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ -{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ -{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ - -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ -{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ -{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ - -{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, -{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, - -{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ -{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ - -/* This is not a commutative instruction. */ -{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, - -/* This is not a commutative instruction. */ -{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, - -{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ -{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ - -{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ -{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ - -{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, - -{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, - -{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, -{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, - -{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, -{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, - -{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, -{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, - -{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, -{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, - -{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ -{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ -{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ -{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ -{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ -{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ -{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ -{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ - -{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ -{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ - -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ -{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ - -{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, -{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, -{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, -{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, - -{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, -{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, -{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, -{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, - -{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, -{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, -{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, -{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, - -{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, -{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, -{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, -{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, -{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, -{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, -{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, -{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, -{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, -{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, -{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, -{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, -{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, -{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, -{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, -{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, - -{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, -{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, -{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, -{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, - -{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, -{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, - -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ -{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ -{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, - - -/* Conditional instructions. - - Because this part of the table was such a mess earlier, I have - macrofied it so that all the branches and traps are generated from - a single-line description of each condition value. John Gilmore. */ - -/* Define branches -- one annulled, one without, etc. */ -#define br(opcode, mask, lose, flags) \ - { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \ - { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 } - -#define brx(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \ - { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \ - { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \ - { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 } - -/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ -#define tr(opcode, mask, lose, flags) \ - { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ - { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ - { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ - { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ - { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ - { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ - { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ - { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ - { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ - { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ - { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ - { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ - -/* v9: We must put `brx' before `br', to ensure that we never match something - v9: against an expression unless it is an expression. Otherwise, we end - v9: up with undefined symbol tables entries, because they get added, but - v9: are not deleted if the pattern fails to match. */ - -/* Define both branches and traps based on condition mask */ -#define cond(bop, top, mask, flags) \ - brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ - br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ - tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) - -/* Define all the conditions, all the branches, all the traps. */ - -/* Standard branch, trap mnemonics */ -cond ("b", "ta", CONDA, F_UNBR), -/* Alternative form (just for assembly, not for disassembly) */ -cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), - -cond ("bcc", "tcc", CONDCC, F_CONDBR), -cond ("bcs", "tcs", CONDCS, F_CONDBR), -cond ("be", "te", CONDE, F_CONDBR), -cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), -cond ("bg", "tg", CONDG, F_CONDBR), -cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), -cond ("bge", "tge", CONDGE, F_CONDBR), -cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ -cond ("bgu", "tgu", CONDGU, F_CONDBR), -cond ("bl", "tl", CONDL, F_CONDBR), -cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), -cond ("ble", "tle", CONDLE, F_CONDBR), -cond ("bleu", "tleu", CONDLEU, F_CONDBR), -cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ -cond ("bn", "tn", CONDN, F_CONDBR), -cond ("bne", "tne", CONDNE, F_CONDBR), -cond ("bneg", "tneg", CONDNEG, F_CONDBR), -cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ -cond ("bpos", "tpos", CONDPOS, F_CONDBR), -cond ("bvc", "tvc", CONDVC, F_CONDBR), -cond ("bvs", "tvs", CONDVS, F_CONDBR), -cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ - -#undef cond -#undef br -#undef brr /* v9 */ -#undef tr - -#define brr(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \ - { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 } - -#define condr(bop, mask, flags) /* v9 */ \ - brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ - -/* v9 */ condr("brnz", 0x5, F_CONDBR), -/* v9 */ condr("brz", 0x1, F_CONDBR), -/* v9 */ condr("brgez", 0x7, F_CONDBR), -/* v9 */ condr("brlz", 0x3, F_CONDBR), -/* v9 */ condr("brlez", 0x2, F_CONDBR), -/* v9 */ condr("brgz", 0x6, F_CONDBR), - -#undef condr /* v9 */ -#undef brr /* v9 */ - -#define movr(opcode, mask, flags) /* v9 */ \ - { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \ - { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 } - -#define fmrrs(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 } -#define fmrrd(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 } -#define fmrrq(opcode, mask, lose, flags) /* v9 */ \ - { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 } - -#define fmovrs(mop, mask, flags) /* v9 */ \ - fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ -#define fmovrd(mop, mask, flags) /* v9 */ \ - fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ -#define fmovrq(mop, mask, flags) /* v9 */ \ - fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ - -/* v9 */ movr("movrne", 0x5, 0), -/* v9 */ movr("movre", 0x1, 0), -/* v9 */ movr("movrgez", 0x7, 0), -/* v9 */ movr("movrlz", 0x3, 0), -/* v9 */ movr("movrlez", 0x2, 0), -/* v9 */ movr("movrgz", 0x6, 0), -/* v9 */ movr("movrnz", 0x5, F_ALIAS), -/* v9 */ movr("movrz", 0x1, F_ALIAS), - -/* v9 */ fmovrs("fmovrsne", 0x5, 0), -/* v9 */ fmovrs("fmovrse", 0x1, 0), -/* v9 */ fmovrs("fmovrsgez", 0x7, 0), -/* v9 */ fmovrs("fmovrslz", 0x3, 0), -/* v9 */ fmovrs("fmovrslez", 0x2, 0), -/* v9 */ fmovrs("fmovrsgz", 0x6, 0), -/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), -/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), - -/* v9 */ fmovrd("fmovrdne", 0x5, 0), -/* v9 */ fmovrd("fmovrde", 0x1, 0), -/* v9 */ fmovrd("fmovrdgez", 0x7, 0), -/* v9 */ fmovrd("fmovrdlz", 0x3, 0), -/* v9 */ fmovrd("fmovrdlez", 0x2, 0), -/* v9 */ fmovrd("fmovrdgz", 0x6, 0), -/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), -/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), - -/* v9 */ fmovrq("fmovrqne", 0x5, 0), -/* v9 */ fmovrq("fmovrqe", 0x1, 0), -/* v9 */ fmovrq("fmovrqgez", 0x7, 0), -/* v9 */ fmovrq("fmovrqlz", 0x3, 0), -/* v9 */ fmovrq("fmovrqlez", 0x2, 0), -/* v9 */ fmovrq("fmovrqgz", 0x6, 0), -/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), -/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), - -#undef movr /* v9 */ -#undef fmovr /* v9 */ -#undef fmrr /* v9 */ - -#define movicc(opcode, cond, flags) /* v9 */ \ - { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 } - -#define movfcc(opcode, fcond, flags) /* v9 */ \ - { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \ - { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 } - -#define movcc(opcode, cond, fcond, flags) /* v9 */ \ - movfcc (opcode, fcond, flags), /* v9 */ \ - movicc (opcode, cond, flags) /* v9 */ - -/* v9 */ movcc ("mova", CONDA, FCONDA, 0), -/* v9 */ movicc ("movcc", CONDCC, 0), -/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), -/* v9 */ movicc ("movcs", CONDCS, 0), -/* v9 */ movicc ("movlu", CONDLU, F_ALIAS), -/* v9 */ movcc ("move", CONDE, FCONDE, 0), -/* v9 */ movcc ("movg", CONDG, FCONDG, 0), -/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), -/* v9 */ movicc ("movgu", CONDGU, 0), -/* v9 */ movcc ("movl", CONDL, FCONDL, 0), -/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), -/* v9 */ movicc ("movleu", CONDLEU, 0), -/* v9 */ movfcc ("movlg", FCONDLG, 0), -/* v9 */ movcc ("movn", CONDN, FCONDN, 0), -/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), -/* v9 */ movicc ("movneg", CONDNEG, 0), -/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ movfcc ("movo", FCONDO, 0), -/* v9 */ movicc ("movpos", CONDPOS, 0), -/* v9 */ movfcc ("movu", FCONDU, 0), -/* v9 */ movfcc ("movue", FCONDUE, 0), -/* v9 */ movfcc ("movug", FCONDUG, 0), -/* v9 */ movfcc ("movuge", FCONDUGE, 0), -/* v9 */ movfcc ("movul", FCONDUL, 0), -/* v9 */ movfcc ("movule", FCONDULE, 0), -/* v9 */ movicc ("movvc", CONDVC, 0), -/* v9 */ movicc ("movvs", CONDVS, 0), -/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), - -#undef movicc /* v9 */ -#undef movfcc /* v9 */ -#undef movcc /* v9 */ - -#define FM_SF 1 /* v9 - values for fpsize */ -#define FM_DF 2 /* v9 */ -#define FM_QF 3 /* v9 */ - -#define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \ -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 } - -#define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \ -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \ -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 } - -/* FIXME: use fmovicc/fmovfcc? */ /* v9 */ -#define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \ -{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \ -{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 } - -#define fmovicc(suffix, cond, flags) /* v9 */ \ -fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \ -fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \ -fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags) - -#define fmovfcc(suffix, fcond, flags) /* v9 */ \ -fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \ -fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \ -fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags) - -#define fmovcc(suffix, cond, fcond, flags) /* v9 */ \ -fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \ -fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \ -fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags) - -/* v9 */ fmovcc ("a", CONDA, FCONDA, 0), -/* v9 */ fmovicc ("cc", CONDCC, 0), -/* v9 */ fmovicc ("cs", CONDCS, 0), -/* v9 */ fmovcc ("e", CONDE, FCONDE, 0), -/* v9 */ fmovcc ("g", CONDG, FCONDG, 0), -/* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0), -/* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS), -/* v9 */ fmovicc ("gu", CONDGU, 0), -/* v9 */ fmovcc ("l", CONDL, FCONDL, 0), -/* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0), -/* v9 */ fmovicc ("leu", CONDLEU, 0), -/* v9 */ fmovfcc ("lg", FCONDLG, 0), -/* v9 */ fmovicc ("lu", CONDLU, F_ALIAS), -/* v9 */ fmovcc ("n", CONDN, FCONDN, 0), -/* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0), -/* v9 */ fmovicc ("neg", CONDNEG, 0), -/* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS), -/* v9 */ fmovfcc ("o", FCONDO, 0), -/* v9 */ fmovicc ("pos", CONDPOS, 0), -/* v9 */ fmovfcc ("u", FCONDU, 0), -/* v9 */ fmovfcc ("ue", FCONDUE, 0), -/* v9 */ fmovfcc ("ug", FCONDUG, 0), -/* v9 */ fmovfcc ("uge", FCONDUGE, 0), -/* v9 */ fmovfcc ("ul", FCONDUL, 0), -/* v9 */ fmovfcc ("ule", FCONDULE, 0), -/* v9 */ fmovicc ("vc", CONDVC, 0), -/* v9 */ fmovicc ("vs", CONDVS, 0), -/* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS), - -#undef fmoviccx /* v9 */ -#undef fmovfccx /* v9 */ -#undef fmovccx /* v9 */ -#undef fmovicc /* v9 */ -#undef fmovfcc /* v9 */ -#undef fmovcc /* v9 */ -#undef FM_DF /* v9 */ -#undef FM_QF /* v9 */ -#undef FM_SF /* v9 */ - -/* Coprocessor branches. */ -#define CBR(opcode, mask, lose, flags, arch) \ - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch } - -/* Floating point branches. */ -#define FBR(opcode, mask, lose, flags) \ - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 } - -/* V9 extended floating point branches. */ -#define FBRX(opcode, mask, lose, flags) /* v9 */ \ - { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \ - { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 } - -/* v9: We must put `FBRX' before `FBR', to ensure that we never match - v9: something against an expression unless it is an expression. Otherwise, - v9: we end up with undefined symbol tables entries, because they get added, - v9: but are not deleted if the pattern fails to match. */ - -#define CONDFC(fop, cop, mask, flags) \ - FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ - FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ - CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) - -#define CONDFCL(fop, cop, mask, flags) \ - FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ - FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ - CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) - -#define CONDF(fop, mask, flags) \ - FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ - FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) - -CONDFC ("fb", "cb", 0x8, F_UNBR), -CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), -CONDFC ("fbe", "cb0", 0x9, F_CONDBR), -CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS), -CONDFC ("fbg", "cb2", 0x6, F_CONDBR), -CONDFC ("fbge", "cb02", 0xb, F_CONDBR), -CONDFC ("fbl", "cb1", 0x4, F_CONDBR), -CONDFC ("fble", "cb01", 0xd, F_CONDBR), -CONDFC ("fblg", "cb12", 0x2, F_CONDBR), -CONDFCL ("fbn", "cbn", 0x0, F_UNBR), -CONDFC ("fbne", "cb123", 0x1, F_CONDBR), -CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS), -CONDFC ("fbo", "cb012", 0xf, F_CONDBR), -CONDFC ("fbu", "cb3", 0x7, F_CONDBR), -CONDFC ("fbue", "cb03", 0xa, F_CONDBR), -CONDFC ("fbug", "cb23", 0x5, F_CONDBR), -CONDFC ("fbuge", "cb023", 0xc, F_CONDBR), -CONDFC ("fbul", "cb13", 0x3, F_CONDBR), -CONDFC ("fbule", "cb013", 0xe, F_CONDBR), - -#undef CONDFC -#undef CONDFCL -#undef CONDF -#undef CBR -#undef FBR -#undef FBRX /* v9 */ - -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ -{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ -{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ - -{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ - -{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, -{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, -{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, -{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, - -{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, - -{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, -{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, -{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, -{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, - -{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, -{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, - -{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, -{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, - -/* This *is* a commutative instruction. */ -{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, -{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, -/* This *is* a commutative instruction. */ -{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, -{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, -{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, -{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, -{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, -{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, - -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ -{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ - -{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ -{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ - -/* FPop1 and FPop2 are not instructions. Don't accept them. */ - -{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, -{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, - -{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 }, -{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 }, - -{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, -{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, - -{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 }, -{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 }, - -{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, -{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, -{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, -{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, -{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, -{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, - -{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, -{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, -{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, -{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, -{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, -{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, - -{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, -{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 }, -{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, - -{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, -{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, -{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, - -{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, -{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, -{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, -{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, -{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, -{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, -{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, -{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, -{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, - -{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, -{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, -{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, -{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, -{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, -{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 }, -{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, - -#define CMPFCC(x) (((x)&0x3)<<25) - -{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, -{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, -{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, -{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, -{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, -{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, -{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, -{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, -{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, -{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, -{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, -{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, -{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, -{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, -{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, -{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, -{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, -{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, -{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, -{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, -{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, -{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, -{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 }, -{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, -{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, -{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, -{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, -{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, -{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, -{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, -{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, -{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, -{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, - -/* These Extended FPop (FIFO) instructions are new in the Fujitsu - MB86934, replacing the CPop instructions from v6 and later - processors. */ - -#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite } -#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } -#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } - -EFPOP1_2 ("efitod", 0x0c8, "f,H"), -EFPOP1_2 ("efitos", 0x0c4, "f,g"), -EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), -EFPOP1_2 ("efstoi", 0x0d1, "f,g"), -EFPOP1_2 ("efstod", 0x0c9, "f,H"), -EFPOP1_2 ("efdtos", 0x0c6, "B,g"), -EFPOP1_2 ("efmovs", 0x001, "f,g"), -EFPOP1_2 ("efnegs", 0x005, "f,g"), -EFPOP1_2 ("efabss", 0x009, "f,g"), -EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), -EFPOP1_2 ("efsqrts", 0x029, "f,g"), -EFPOP1_3 ("efaddd", 0x042, "v,B,H"), -EFPOP1_3 ("efadds", 0x041, "e,f,g"), -EFPOP1_3 ("efsubd", 0x046, "v,B,H"), -EFPOP1_3 ("efsubs", 0x045, "e,f,g"), -EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), -EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), -EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), -EFPOP1_3 ("efmuls", 0x049, "e,f,g"), -EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), -EFPOP2_2 ("efcmpd", 0x052, "v,B"), -EFPOP2_2 ("efcmped", 0x056, "v,B"), -EFPOP2_2 ("efcmps", 0x051, "e,f"), -EFPOP2_2 ("efcmpes", 0x055, "e,f"), - -#undef EFPOP1_2 -#undef EFPOP1_3 -#undef EFPOP2_2 - -/* These are marked F_ALIAS, so that they won't conflict with sparclite insns - present. Otherwise, the F_ALIAS flag is ignored. */ -{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, -{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, - -/* sparclet specific insns */ - -COMMUTEOP ("umac", 0x3e, sparclet), -COMMUTEOP ("smac", 0x3f, sparclet), -COMMUTEOP ("umacd", 0x2e, sparclet), -COMMUTEOP ("smacd", 0x2f, sparclet), -COMMUTEOP ("umuld", 0x09, sparclet), -COMMUTEOP ("smuld", 0x0d, sparclet), - -{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, -{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, - -/* The manual isn't completely accurate on these insns. The `rs2' field is - treated as being 6 bits to account for 6 bit immediates to cpush. It is - assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ -#define BIT5 (1<<5) -{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, -{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, -{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, -{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, -{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, -{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, -{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, -#undef BIT5 - -/* sparclet coprocessor branch insns */ -#define SLCBCC2(opcode, mask, lose) \ - { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet } -#define SLCBCC(opcode, mask) \ - SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) - -/* cbn,cba can't be defined here because they're defined elsewhere and GAS - requires all mnemonics of the same name to be consecutive. */ -/*SLCBCC("cbn", 0), - already defined */ -SLCBCC("cbe", 1), -SLCBCC("cbf", 2), -SLCBCC("cbef", 3), -SLCBCC("cbr", 4), -SLCBCC("cber", 5), -SLCBCC("cbfr", 6), -SLCBCC("cbefr", 7), -/*SLCBCC("cba", 8), - already defined */ -SLCBCC("cbne", 9), -SLCBCC("cbnf", 10), -SLCBCC("cbnef", 11), -SLCBCC("cbnr", 12), -SLCBCC("cbner", 13), -SLCBCC("cbnfr", 14), -SLCBCC("cbnefr", 15), - -#undef SLCBCC2 -#undef SLCBCC - -{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, -{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, -{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, -{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, - -/* v9 synthetic insns */ -{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ -{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ -{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ -{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ -{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ -{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ -{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ -{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ -{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ - -/* Ultrasparc extensions */ -{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, - -/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ -{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, -{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, -{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, -{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, -{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, -{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, -{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, -{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, - -{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, -{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, -{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, -{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, -{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, - -/* Note that the mixing of 32/64 bit regs is intentional. */ -{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, -{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, -{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, -{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, -{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, -{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, -{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, - -{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, -{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, -{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, - -{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, -{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, -{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, -{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, -{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, -{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, -{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, -{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, -{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, -{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, -{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, -{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, -{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, -{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, -{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, -{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, -{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, -{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, -{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, -{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, -{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, -{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, -{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, -{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, -{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, -{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, -{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, -{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, -{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, -{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, -{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, -{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, - -{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, -{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, -{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, -{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, -{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, -{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, -{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, -{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, - -{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, -{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, -{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, -{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, -{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, -{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, - -{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, - -{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, -{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, -{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, - -/* Cheetah instructions */ -{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b }, -{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b }, -{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b }, -{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b }, -{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b }, -{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b }, - -{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b }, -{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b }, - -{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b }, - -/* More v9 specific insns, these need to come last so they do not clash - with v9a instructions such as "edge8" which looks like impdep1. */ - -#define IMPDEP(name, code) \ -{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ -{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ -{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ -{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } - -IMPDEP ("impdep1", 0x36), -IMPDEP ("impdep2", 0x37), - -#undef IMPDEP - -}; - -const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); - -/* Utilities for argument parsing. */ - -typedef struct -{ - int value; - const char *name; -} arg; - -/* Look up NAME in TABLE. */ - -static int lookup_name PARAMS ((const arg *, const char *)); -static const char *lookup_value PARAMS ((const arg *, int)); - -static int -lookup_name (table, name) - const arg *table; - const char *name; -{ - const arg *p; - - for (p = table; p->name; ++p) - if (strcmp (name, p->name) == 0) - return p->value; - - return -1; -} - -/* Look up VALUE in TABLE. */ - -static const char * -lookup_value (table, value) - const arg *table; - int value; -{ - const arg *p; - - for (p = table; p->name; ++p) - if (value == p->value) - return p->name; - - return (char *) 0; -} - -/* Handle ASI's. */ - -static arg asi_table[] = -{ - /* These are in the v9 architecture manual. */ - /* The shorter versions appear first, they're here because Sun's as has them. - Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the - UltraSPARC architecture manual). */ - { 0x04, "#ASI_N" }, - { 0x0c, "#ASI_N_L" }, - { 0x10, "#ASI_AIUP" }, - { 0x11, "#ASI_AIUS" }, - { 0x18, "#ASI_AIUP_L" }, - { 0x19, "#ASI_AIUS_L" }, - { 0x80, "#ASI_P" }, - { 0x81, "#ASI_S" }, - { 0x82, "#ASI_PNF" }, - { 0x83, "#ASI_SNF" }, - { 0x88, "#ASI_P_L" }, - { 0x89, "#ASI_S_L" }, - { 0x8a, "#ASI_PNF_L" }, - { 0x8b, "#ASI_SNF_L" }, - { 0x04, "#ASI_NUCLEUS" }, - { 0x0c, "#ASI_NUCLEUS_LITTLE" }, - { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, - { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, - { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, - { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, - { 0x80, "#ASI_PRIMARY" }, - { 0x81, "#ASI_SECONDARY" }, - { 0x82, "#ASI_PRIMARY_NOFAULT" }, - { 0x83, "#ASI_SECONDARY_NOFAULT" }, - { 0x88, "#ASI_PRIMARY_LITTLE" }, - { 0x89, "#ASI_SECONDARY_LITTLE" }, - { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, - { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, - /* These are UltraSPARC extensions. */ - /* FIXME: There are dozens of them. Not sure we want them all. - Most are for kernel building but some are for vis type stuff. */ - { 0, 0 } -}; - -/* Return the value for ASI NAME, or -1 if not found. */ - -int -sparc_encode_asi (name) - const char *name; -{ - return lookup_name (asi_table, name); -} - -/* Return the name for ASI value VALUE or NULL if not found. */ - -const char * -sparc_decode_asi (value) - int value; -{ - return lookup_value (asi_table, value); -} - -/* Handle membar masks. */ - -static arg membar_table[] = -{ - { 0x40, "#Sync" }, - { 0x20, "#MemIssue" }, - { 0x10, "#Lookaside" }, - { 0x08, "#StoreStore" }, - { 0x04, "#LoadStore" }, - { 0x02, "#StoreLoad" }, - { 0x01, "#LoadLoad" }, - { 0, 0 } -}; - -/* Return the value for membar arg NAME, or -1 if not found. */ - -int -sparc_encode_membar (name) - const char *name; -{ - return lookup_name (membar_table, name); -} - -/* Return the name for membar value VALUE or NULL if not found. */ - -const char * -sparc_decode_membar (value) - int value; -{ - return lookup_value (membar_table, value); -} - -/* Handle prefetch args. */ - -static arg prefetch_table[] = -{ - { 0, "#n_reads" }, - { 1, "#one_read" }, - { 2, "#n_writes" }, - { 3, "#one_write" }, - { 4, "#page" }, - { 16, "#invalidate" }, - { 0, 0 } -}; - -/* Return the value for prefetch arg NAME, or -1 if not found. */ - -int -sparc_encode_prefetch (name) - const char *name; -{ - return lookup_name (prefetch_table, name); -} - -/* Return the name for prefetch value VALUE or NULL if not found. */ - -const char * -sparc_decode_prefetch (value) - int value; -{ - return lookup_value (prefetch_table, value); -} - -/* Handle sparclet coprocessor registers. */ - -static arg sparclet_cpreg_table[] = -{ - { 0, "%ccsr" }, - { 1, "%ccfr" }, - { 2, "%cccrcr" }, - { 3, "%ccpr" }, - { 4, "%ccsr2" }, - { 5, "%cccrr" }, - { 6, "%ccrstr" }, - { 0, 0 } -}; - -/* Return the value for sparclet cpreg arg NAME, or -1 if not found. */ - -int -sparc_encode_sparclet_cpreg (name) - const char *name; -{ - return lookup_name (sparclet_cpreg_table, name); -} - -/* Return the name for sparclet cpreg value VALUE or NULL if not found. */ - -const char * -sparc_decode_sparclet_cpreg (value) - int value; -{ - return lookup_value (sparclet_cpreg_table, value); -} diff --git a/contrib/binutils/opcodes/stamp-h.in b/contrib/binutils/opcodes/stamp-h.in deleted file mode 100644 index 9788f70..0000000 --- a/contrib/binutils/opcodes/stamp-h.in +++ /dev/null @@ -1 +0,0 @@ -timestamp diff --git a/contrib/binutils/opcodes/sysdep.h b/contrib/binutils/opcodes/sysdep.h deleted file mode 100644 index ce9adde..0000000 --- a/contrib/binutils/opcodes/sysdep.h +++ /dev/null @@ -1,42 +0,0 @@ -/* Random host-dependent support code. - Copyright 1995, 1997, 2000 Free Software Foundation, Inc. - Written by Ken Raeburn. - -This file is part of libopcodes, the opcodes library. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* Do system-dependent stuff, mainly driven by autoconf-detected info. - - Well, some generic common stuff is done here too, like including - ansidecl.h. That's because the .h files in bfd/hosts files I'm - trying to replace often did that. If it can be dropped from this - file (check in a non-ANSI environment!), it should be. */ - -#include "config.h" - -#include "ansidecl.h" - -#ifdef HAVE_STDLIB_H -#include <stdlib.h> -#endif - -#ifdef HAVE_STRING_H -#include <string.h> -#else -#ifdef HAVE_STRINGS_H -#include <strings.h> -#endif -#endif |
