diff options
Diffstat (limited to 'contrib/binutils/opcodes')
| -rw-r--r-- | contrib/binutils/opcodes/ChangeLog | 28 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/ppc-opc.c | 6 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/s390-dis.c | 257 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/s390-mkopc.c | 190 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/s390-opc.c | 318 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/s390-opc.txt | 626 |
6 files changed, 1424 insertions, 1 deletions
diff --git a/contrib/binutils/opcodes/ChangeLog b/contrib/binutils/opcodes/ChangeLog index 1a37508..c29dd31 100644 --- a/contrib/binutils/opcodes/ChangeLog +++ b/contrib/binutils/opcodes/ChangeLog @@ -1,3 +1,31 @@ +2002-05-09 Anton Blanchard <anton@samba.org> + + * ppc-opc.c: Add "tlbiel" for POWER4. + +2002-05-09 Alan Modra <amodra@bigpond.net.au> + + Merge from mainline. + 2002-05-01 Alan Modra <amodra@bigpond.net.au> + * ppc-opc.c: Add "tlbsx." and "tlbsxe." for booke. + + 2002-04-17 matthew green <mrg@redhat.com> + * ppc-opc.c (powerpc_opcode): Fix dssall operand list. + +2002-04-29 Chris Demetriou <cgd@broadcom.com> + + Merge from mainline: + 2002-03-06 Chris Demetriou <cgd@broadcom.com> + * mips-opc.c (mips_builtin_opcodes): Mark "pref" as being + present on I4. + + Merge from mainline: + 2002-03-06 Chris Demetriou <cgd@broadcom.com> + * mips-opc.c (mips_builtin_opcodes): Add "movn.ps" and "movz.ps". + + Merge from mainline: + 2002-03-15 Chris Demetriou <cgd@broadcom.com> + * mips-dis.c (is_newabi): Fix ABI decoding. + 2002-04-04 Alan Modra <amodra@bigpond.net.au> * dep-in.sed: Cope with absolute paths. diff --git a/contrib/binutils/opcodes/ppc-opc.c b/contrib/binutils/opcodes/ppc-opc.c index c868ccc..70167f7 100644 --- a/contrib/binutils/opcodes/ppc-opc.c +++ b/contrib/binutils/opcodes/ppc-opc.c @@ -3065,6 +3065,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } }, + { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, @@ -3672,7 +3674,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, -{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { STRM } }, +{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, @@ -3688,7 +3690,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } }, { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE, { RA, RB } }, { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, diff --git a/contrib/binutils/opcodes/s390-dis.c b/contrib/binutils/opcodes/s390-dis.c new file mode 100644 index 0000000..8745a89 --- /dev/null +++ b/contrib/binutils/opcodes/s390-dis.c @@ -0,0 +1,257 @@ +/* s390-dis.c -- Disassemble S390 instructions + Copyright 2000, 2001, 2002 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of GDB, GAS and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include <stdio.h> +#include "ansidecl.h" +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/s390.h" + +static int init_flag = 0; +static int opc_index[256]; +static int current_arch_mask = 0; + +static void init_disasm PARAMS ((struct disassemble_info *)); +static unsigned int s390_extract_operand + PARAMS ((unsigned char *, const struct s390_operand *)); + +/* Set up index table for first opcode byte. */ + +static void +init_disasm (info) + struct disassemble_info *info; +{ + const struct s390_opcode *opcode; + const struct s390_opcode *opcode_end; + + memset (opc_index, 0, sizeof (opc_index)); + opcode_end = s390_opcodes + s390_num_opcodes; + for (opcode = s390_opcodes; opcode < opcode_end; opcode++) + { + opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes; + while ((opcode < opcode_end) && + (opcode[1].opcode[0] == opcode->opcode[0])) + opcode++; + } + switch (info->mach) + { + case bfd_mach_s390_31: + current_arch_mask = 1 << S390_OPCODE_ESA; + break; + case bfd_mach_s390_64: + current_arch_mask = 1 << S390_OPCODE_ESAME; + break; + default: + abort (); + } + init_flag = 1; +} + +/* Extracts an operand value from an instruction. */ + +static inline unsigned int +s390_extract_operand (insn, operand) + unsigned char *insn; + const struct s390_operand *operand; +{ + unsigned int val; + int bits; + + /* Extract fragments of the operand byte for byte. */ + insn += operand->shift / 8; + bits = (operand->shift & 7) + operand->bits; + val = 0; + do + { + val <<= 8; + val |= (unsigned int) *insn++; + bits -= 8; + } + while (bits > 0); + val >>= -bits; + val &= ((1U << (operand->bits - 1)) << 1) - 1; + + /* Sign extend value if the operand is signed or pc relative. */ + if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) + && (val & (1U << (operand->bits - 1)))) + val |= (-1U << (operand->bits - 1)) << 1; + + /* Double value if the operand is pc relative. */ + if (operand->flags & S390_OPERAND_PCREL) + val <<= 1; + + /* Length x in an instructions has real length x+1. */ + if (operand->flags & S390_OPERAND_LENGTH) + val++; + return val; +} + +/* Print a S390 instruction. */ + +int +print_insn_s390 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + bfd_byte buffer[6]; + const struct s390_opcode *opcode; + const struct s390_opcode *opcode_end; + unsigned int value; + int status, opsize, bufsize; + char separator; + + if (init_flag == 0) + init_disasm (info); + + /* The output looks better if we put 6 bytes on a line. */ + info->bytes_per_line = 6; + + /* Every S390 instruction is max 6 bytes long. */ + memset (buffer, 0, 6); + status = (*info->read_memory_func) (memaddr, buffer, 6, info); + if (status != 0) + { + for (bufsize = 0; bufsize < 6; bufsize++) + if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0) + break; + if (bufsize <= 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + /* Opsize calculation looks strange but it works + 00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes, + 11xxxxxx -> 6 bytes. */ + opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; + status = opsize > bufsize; + } + else + { + bufsize = 6; + opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; + } + + if (status == 0) + { + /* Find the first match in the opcode table. */ + opcode_end = s390_opcodes + s390_num_opcodes; + for (opcode = s390_opcodes + opc_index[(int) buffer[0]]; + (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]); + opcode++) + { + const struct s390_operand *operand; + const unsigned char *opindex; + + /* Check architecture. */ + if (!(opcode->architecture & current_arch_mask)) + continue; + /* Check signature of the opcode. */ + if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1] + || (buffer[2] & opcode->mask[2]) != opcode->opcode[2] + || (buffer[3] & opcode->mask[3]) != opcode->opcode[3] + || (buffer[4] & opcode->mask[4]) != opcode->opcode[4] + || (buffer[5] & opcode->mask[5]) != opcode->opcode[5]) + continue; + + /* The instruction is valid. */ + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "%s\t", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + /* Extract the operands. */ + separator = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + unsigned int value; + + operand = s390_operands + *opindex; + value = s390_extract_operand (buffer, operand); + + if ((operand->flags & S390_OPERAND_INDEX) && value == 0) + continue; + if ((operand->flags & S390_OPERAND_BASE) && + value == 0 && separator == '(') + { + separator = ','; + continue; + } + + if (separator) + (*info->fprintf_func) (info->stream, "%c", separator); + + if (operand->flags & S390_OPERAND_GPR) + (*info->fprintf_func) (info->stream, "%%r%i", value); + else if (operand->flags & S390_OPERAND_FPR) + (*info->fprintf_func) (info->stream, "%%f%i", value); + else if (operand->flags & S390_OPERAND_AR) + (*info->fprintf_func) (info->stream, "%%a%i", value); + else if (operand->flags & S390_OPERAND_CR) + (*info->fprintf_func) (info->stream, "%%c%i", value); + else if (operand->flags & S390_OPERAND_PCREL) + (*info->print_address_func) (memaddr + (int) value, info); + else if (operand->flags & S390_OPERAND_SIGNED) + (*info->fprintf_func) (info->stream, "%i", (int) value); + else + (*info->fprintf_func) (info->stream, "%i", value); + + if (operand->flags & S390_OPERAND_DISP) + { + separator = '('; + } + else if (operand->flags & S390_OPERAND_BASE) + { + (*info->fprintf_func) (info->stream, ")"); + separator = ','; + } + else + separator = ','; + } + + /* Found instruction, printed it, return its size. */ + return opsize; + } + /* No matching instruction found, fall through to hex print. */ + } + + if (bufsize >= 4) + { + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + value = (value << 8) + (unsigned int) buffer[2]; + value = (value << 8) + (unsigned int) buffer[3]; + (*info->fprintf_func) (info->stream, ".long\t0x%08x", value); + return 4; + } + else if (bufsize >= 2) + { + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + (*info->fprintf_func) (info->stream, ".short\t0x%04x", value); + return 2; + } + else + { + value = (unsigned int) buffer[0]; + (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value); + return 1; + } +} diff --git a/contrib/binutils/opcodes/s390-mkopc.c b/contrib/binutils/opcodes/s390-mkopc.c new file mode 100644 index 0000000..d79ff81 --- /dev/null +++ b/contrib/binutils/opcodes/s390-mkopc.c @@ -0,0 +1,190 @@ +/* s390-mkopc.c -- Generates opcode table out of s390-opc.txt + Copyright 2000, 2001 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of GDB, GAS, and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +/* ARCHBITS_ESA and ARCH_ESAME correspond to the bit numbers defined + by s390_opcode_arch_val in include/opcode/s390.h: + ARCHBITS_ESAONLY = (1<<S390_OPCODE_ESA) + ARCHBITS_ESA = (1<<S390_OPCODE_ESA) + (1<<S390_OPCODE_ESAME) + ARCHBITS_ESA = (1<<S390_OPCODE_ESAME). */ +#define ARCHBITS_ESAONLY 1 +#define ARCHBITS_ESA 3 +#define ARCHBITS_ESAME 2 + +struct op_struct + { + char opcode[16]; + char mnemonic[16]; + char format[16]; + int archbits; + unsigned long long sort_value; + int no_nibbles; + }; + +struct op_struct *op_array; +int max_ops; +int no_ops; + +static void +createTable (void) +{ + max_ops = 256; + op_array = malloc (max_ops * sizeof (struct op_struct)); + no_ops = 0; +} + +/* `insertOpcode': insert an op_struct into sorted opcode array. */ + +static void +insertOpcode (char *opcode, char *mnemonic, char *format, int archbits) +{ + char *str; + unsigned long long sort_value; + int no_nibbles; + int ix, k; + + while (no_ops >= max_ops) + { + max_ops = max_ops * 2; + op_array = realloc (op_array, max_ops * sizeof (struct op_struct)); + } + + sort_value = 0; + str = opcode; + for (ix = 0; ix < 16; ix++) + { + if (*str >= '0' && *str <= '9') + sort_value = (sort_value << 4) + (*str - '0'); + else if (*str >= 'a' && *str <= 'f') + sort_value = (sort_value << 4) + (*str - 'a' + 10); + else if (*str >= 'A' && *str <= 'F') + sort_value = (sort_value << 4) + (*str - 'A' + 10); + else if (*str == '?') + sort_value <<= 4; + else + break; + str ++; + } + sort_value <<= 4*(16 - ix); + no_nibbles = ix; + for (ix = 0; ix < no_ops; ix++) + if (sort_value > op_array[ix].sort_value) + break; + for (k = no_ops; k > ix; k--) + op_array[k] = op_array[k-1]; + strcpy(op_array[ix].opcode, opcode); + strcpy(op_array[ix].mnemonic, mnemonic); + strcpy(op_array[ix].format, format); + op_array[ix].sort_value = sort_value; + op_array[ix].no_nibbles = no_nibbles; + op_array[ix].archbits = archbits; + no_ops++; +} + +static char file_header[] = + "/* The opcode table. This file was generated by s390-mkopc.\n\n" + " The format of the opcode table is:\n\n" + " NAME OPCODE MASK OPERANDS\n\n" + " Name is the name of the instruction.\n" + " OPCODE is the instruction opcode.\n" + " MASK is the opcode mask; this is used to tell the disassembler\n" + " which bits in the actual opcode must match OPCODE.\n" + " OPERANDS is the list of operands.\n\n" + " The disassembler reads the table in order and prints the first\n" + " instruction which matches. */\n\n" + "const struct s390_opcode s390_opcodes[] =\n {\n"; + +/* `dumpTable': write opcode table. */ + +static void +dumpTable (void) +{ + char *str; + int ix; + + /* Write hash table entries (slots). */ + printf (file_header); + + for (ix = 0; ix < no_ops; ix++) + { + printf (" { \"%s\", ", op_array[ix].mnemonic); + for (str = op_array[ix].opcode; *str != 0; str++) + if (*str == '?') + *str = '0'; + printf ("OP%i(0x%sLL), ", + op_array[ix].no_nibbles*4, op_array[ix].opcode); + printf ("MASK_%s, INSTR_%s, ", + op_array[ix].format, op_array[ix].format); + printf ("%i}", op_array[ix].archbits); + if (ix < no_ops-1) + printf (",\n"); + else + printf ("\n"); + } + printf ("};\n\n"); + printf ("const int s390_num_opcodes =\n"); + printf (" sizeof (s390_opcodes) / sizeof (s390_opcodes[0]);\n\n"); +} + +int +main (void) +{ + char currentLine[256]; + + createTable (); + + /* Read opcode descriptions from `stdin'. For each mnemonic, + make an entry into the opcode table. */ + while (fgets (currentLine, sizeof (currentLine), stdin) != NULL) + { + char opcode[16]; + char mnemonic[16]; + char format[16]; + char description[64]; + char archtag[16]; + int archbits; + + if (currentLine[0] == '#') + continue; + memset (opcode, 0, 8); + if (sscanf (currentLine, "%15s %15s %15s \"%[^\"]\" %15s", + opcode, mnemonic, format, description, archtag) == 5) + { + if (strcmp (archtag, "esaonly") == 0) + archbits = ARCHBITS_ESAONLY; + else if (strcmp (archtag, "esa") == 0) + archbits = ARCHBITS_ESA; + else if (strcmp (archtag, "esame") == 0) + archbits = ARCHBITS_ESAME; + else + archbits = 0; + insertOpcode (opcode, mnemonic, format, archbits); + } + else + fprintf (stderr, "Couldn't scan line %s\n", currentLine); + } + + dumpTable (); + return 0; +} diff --git a/contrib/binutils/opcodes/s390-opc.c b/contrib/binutils/opcodes/s390-opc.c new file mode 100644 index 0000000..7cd8231 --- /dev/null +++ b/contrib/binutils/opcodes/s390-opc.c @@ -0,0 +1,318 @@ +/* s390-opc.c -- S390 opcode list + Copyright 2000, 2001 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of GDB, GAS, and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include <stdio.h> +#include "ansidecl.h" +#include "opcode/s390.h" + +/* This file holds the S390 opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ + +/* The operands table. + The fields are bits, shift, insert, extract, flags. */ + +const struct s390_operand s390_operands[] = +{ +#define UNUSED 0 + { 0, 0, 0 }, /* Indicates the end of the operand list */ + +#define R_8 1 /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR }, +#define R_12 2 /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR }, +#define R_16 3 /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR }, +#define R_20 4 /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR }, +#define R_24 5 /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR }, +#define R_28 6 /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR }, +#define R_32 7 /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR }, + +#define F_8 8 /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR }, +#define F_12 9 /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR }, +#define F_16 10 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +#define F_20 11 /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +#define F_24 12 /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR }, +#define F_28 13 /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR }, +#define F_32 14 /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR }, + +#define A_8 15 /* Access reg. starting at position 8 */ + { 4, 8, S390_OPERAND_AR }, +#define A_12 16 /* Access reg. starting at position 12 */ + { 4, 12, S390_OPERAND_AR }, +#define A_24 17 /* Access reg. starting at position 24 */ + { 4, 24, S390_OPERAND_AR }, +#define A_28 18 /* Access reg. starting at position 28 */ + { 4, 28, S390_OPERAND_AR }, + +#define C_8 19 /* Control reg. starting at position 8 */ + { 4, 8, S390_OPERAND_CR }, +#define C_12 20 /* Control reg. starting at position 12 */ + { 4, 12, S390_OPERAND_CR }, + +#define B_16 21 /* Base register starting at position 16 */ + { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, +#define B_32 22 /* Base register starting at position 32 */ + { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, + +#define X_12 23 /* Index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, + +#define D_20 24 /* Displacement starting at position 20 */ + { 12, 20, S390_OPERAND_DISP }, +#define D_36 25 /* Displacement starting at position 36 */ + { 12, 36, S390_OPERAND_DISP }, + +#define L4_8 26 /* 4 bit length starting at position 8 */ + { 4, 8, S390_OPERAND_LENGTH }, +#define L4_12 27 /* 4 bit length starting at position 12 */ + { 4, 12, S390_OPERAND_LENGTH }, +#define L8_8 28 /* 8 bit length starting at position 8 */ + { 8, 8, S390_OPERAND_LENGTH }, + +#define U4_8 29 /* 4 bit unsigned value starting at 8 */ + { 4, 8, 0 }, +#define U4_12 30 /* 4 bit unsigned value starting at 12 */ + { 4, 12, 0 }, +#define U4_16 31 /* 4 bit unsigned value starting at 16 */ + { 4, 16, 0 }, +#define U4_20 32 /* 4 bit unsigned value starting at 20 */ + { 4, 20, 0 }, +#define U8_8 33 /* 8 bit unsigned value starting at 8 */ + { 8, 8, 0 }, +#define U8_16 34 /* 8 bit unsigned value starting at 16 */ + { 8, 16, 0 }, +#define I16_16 35 /* 16 bit signed value starting at 16 */ + { 16, 16, S390_OPERAND_SIGNED }, +#define U16_16 36 /* 16 bit unsigned value starting at 16 */ + { 16, 16, 0 }, +#define J16_16 37 /* PC relative jump offset at 16 */ + { 16, 16, S390_OPERAND_PCREL }, +#define J32_16 38 /* PC relative long offset at 16 */ + { 32, 16, S390_OPERAND_PCREL } +}; + + +/* Macros used to form opcodes. */ + +/* 8/16/48 bit opcodes. */ +#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } +#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ + (x >> 16) & 255, (x >> 8) & 255, x & 255} + +/* The new format of the INSTR_x_y and MASK_x_y defines is based + on the following rules: + 1) the middle part of the definition (x in INSTR_x_y) is the official + names of the instruction format that you can find in the principals + of operation. + 2) the last part of the definition (y in INSTR_x_y) gives you an idea + which operands the binary represenation of the instruction has. + The meanings of the letters in y are: + a - access register + c - control register + d - displacement, 12 bit + f - floating pointer register + i - signed integer, 4 or 8 bit + l - length, 4 or 8 bit + p - pc relative + r - general purpose register + u - unsigned integer, 4 or 8 bit + 0 - operand skipped. + The order of the letters reflects the layout of the format in + storage and not the order of the paramaters of the instructions. + The use of the letters is not a 100% match with the PoP but it is + quite close. + + For example the instruction "mvo" is defined in the PoP as follows: + + MVO D1(L1,B1),D2(L2,B2) [SS] + + -------------------------------------- + | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | + -------------------------------------- + 0 8 12 16 20 32 36 + + The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ + +#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ +#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ +#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ +#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ +#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ +#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ +#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ +#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ +#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ +#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ +#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ +#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ +#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ +#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ +#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ +#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ +#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ +#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ +#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ +#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ +#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ +#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ +#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ +#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */ +#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */ +#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */ +#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ +#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ +#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ +#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ +#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ +#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ +#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ +#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ +#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ +#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ +#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ +#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ +#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ +#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ +#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ +#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ +#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ +#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ +#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ +#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ +#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ +#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ +#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ +#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ +#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ +#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ +#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ +#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ +#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ +#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ +#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ + +#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } +#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } + +/* The opcode formats table (blueprints for .insn pseudo mnemonic). */ + +const struct s390_opcode s390_opformats[] = + { + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3 }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3 }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3 }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3 }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3 }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3 }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3 }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3 }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3 }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3 }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3 }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3 }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3 }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3 }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3 }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3 }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3 }, +}; + +const int s390_num_opformats = + sizeof (s390_opformats) / sizeof (s390_opformats[0]); + +#include "s390-opc.tab" diff --git a/contrib/binutils/opcodes/s390-opc.txt b/contrib/binutils/opcodes/s390-opc.txt new file mode 100644 index 0000000..ddcf089 --- /dev/null +++ b/contrib/binutils/opcodes/s390-opc.txt @@ -0,0 +1,626 @@ +# S/390 opcodes list. Use s390-mkopc to convert it into the opcode table. +# Copyright 2000, 2001 Free Software Foundation, Inc. +# Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). +5a a RX_RRRD "add" esa +6a ad RX_FRRD "add normalized (long)" esa +2a adr RR_FF "add normalized (long)" esa +7a ae RX_FRRD "add normalized (short)" esa +3a aer RR_FF "add normalized (short)" esa +4a ah RX_RRRD "add halfword" esa +5e al RX_RRRD "add logical" esa +1e alr RR_RR "add logical" esa +fa ap SS_LLRDRD "add decimal" esa +1a ar RR_RR "add" esa +7e au RX_FRRD "add unnormalized (short)" esa +3e aur RR_FF "add unnormalized (short)" esa +6e aw RX_FRRD "add unnormalized (long)" esa +2e awr RR_FF "add unnormalized (long)" esa +36 axr RR_FF "add normalized" esa +b240 bakr RRE_RR "branch and stack" esa +45 bal RX_RRRD "branch and link" esa +05 balr RR_RR "branch and link" esa +4d bas RX_RRRD "branch and save" esa +0d basr RR_RR "branch and save" esa +0c bassm RR_RR "branch and save and set mode" esa +47 bc RX_URRD "branch on condition" esa +07 bcr RR_UR "branch on condition" esa +46 bct RX_RRRD "branch on count" esa +06 bctr RR_RR "branch on count" esa +b258 bsg RRE_RR "branch in subspace group" esa +0b bsm RR_RR "branch and set mode" esa +86 bxh RS_RRRD "branch on index high" esa +87 bxle RS_RRRD "branch on index low or equal" esa +59 c RX_RRRD "compare" esa +69 cd RX_FRRD "compare (long)" esa +29 cdr RR_FF "compare (long)" esa +bb cds RS_RRRD "compare double and swap" esa +79 ce RX_FRRD "compare (short)" esa +39 cer RR_FF "compare (short)" esa +b21a cfc S_RD "compare and form codeword" esa +49 ch RX_RRRD "compare halfword" esa +55 cl RX_RRRD "compare logical" esa +d5 clc SS_L0RDRD "compare logical" esa +0f clcl RR_RR "compare logical long" esa +95 cli SI_URD "compare logical" esa +bd clm RS_RURD "compare logical characters under mask" esa +15 clr RR_RR "compare logical" esa +b25d clst RRE_RR "compare logical string" esa +b263 cmpsc RRE_RR "compression call" esa +f9 cp SS_LLRDRD "compare decimal" esa +b24d cpya RRE_AA "copy access" esa +19 cr RR_RR "compare" esa +ba cs RS_RRRD "compare and swap" esa +b230 csch S_00 "clear subchannel" esa +b257 cuse RRE_RR "compare until substring equal" esa +b250 csp RRE_RR "compare and swap and purge" esa +4f cvb RX_RRRD "convert to binary" esa +4e cvd RX_RRRD "convert to decimal" esa +5d d RX_RRRD "divide" esa +6d dd RX_FRRD "divide (long)" esa +2d ddr RR_FF "divide (long)" esa +7d de RX_FRRD "divide (short)" esa +3d der RR_FF "divide (short)" esa +83 diag RS_RRRD "diagnose" esa +fd dp SS_LLRDRD "divide decimal" esa +1d dr RR_RR "divide" esa +b22d dxr RRE_F0 "divide (ext.)" esa +b24f ear RRE_RA "extract access" esa +de ed SS_L0RDRD "edit" esa +df edmk SS_L0RDRD "edit and mark" esa +b226 epar RRE_R0 "extract primary ASN" esa +b249 ereg RRE_RR "extract stacked registers" esa +b227 esar RRE_R0 "extract secondary ASN" esa +b24a esta RRE_RR "extract stacked state" esa +44 ex RX_RRRD "execute" esa +24 hdr RR_FF "halve (long)" esa +34 her RR_FF "halve (short)" esa +b231 hsch S_00 "halt subchannel" esa +b224 iac RRE_R0 "insert address space control" esa +43 ic RX_RRRD "insert character" esa +bf icm RS_RURD "insert characters under mask" esa +b20b ipk S_00 "insert PSW key" esa +b222 ipm RRE_R0 "insert program mask" esa +b221 ipte RRE_RR "invalidate page table entry" esa +b229 iske RRE_RR "insert storage key extended" esa +b223 ivsk RRE_RR "insert virtual storage key" esa +58 l RX_RRRD "load" esa +41 la RX_RRRD "load address" esa +51 lae RX_RRRD "load address extended" esa +9a lam RS_AARD "load access multiple" esa +e500 lasp SSE_RDRD "load address space parameters" esa +23 lcdr RR_FF "load complement (long)" esa +33 lcer RR_FF "load complement (short)" esa +13 lcr RR_RR "load complement" esa +b7 lctl RS_CCRD "load control" esa +68 ld RX_FRRD "load (long)" esa +28 ldr RR_FF "load (long)" esa +78 le RX_FRRD "load (short)" esa +38 ler RR_FF "load (short)" esa +48 lh RX_RRRD "load halfword" esa +98 lm RS_RRRD "load multiple" esa +21 lndr RR_FF "load negative (long)" esa +31 lner RR_FF "load negative (short)" esa +11 lnr RR_RR "load negative" esa +20 lpdr RR_FF "load positive (long)" esa +30 lper RR_FF "load positive (short)" esa +10 lpr RR_RR "load positive" esa +82 lpsw S_RD "load PSW" esa +18 lr RR_RR "load" esa +b1 lra RX_RRRD "load real address" esa +25 lrdr RR_FF "load rounded (ext. to long)" esa +35 lrer RR_FF "load rounded (long to short)" esa +22 ltdr RR_FF "load and test (long)" esa +32 lter RR_FF "load and test (short)" esa +12 ltr RR_RR "load and test" esa +b24b lura RRE_RR "load using real address" esa +5c m RX_RRRD "multiply" esa +af mc SI_URD "monitor call" esa +6c md RX_FRRD "multiply (long)" esa +2c mdr RR_FF "multiply (long)" esa +7c me RX_FRRD "multiply (short to long)" esa +3c mer RR_FF "multiply (short to long)" esa +4c mh RX_RRRD "multiply halfword" esa +fc mp SS_LLRDRD "multiply decimal" esa +1c mr RR_RR "multiply" esa +b232 msch S_RD "modify subchannel" esa +b247 msta RRE_R0 "modify stacked state" esa +d2 mvc SS_L0RDRD "move" esa +e50f mvcdk SSE_RDRD "move with destination key" esa +e8 mvcin SS_L0RDRD "move inverse" esa +d9 mvck SS_RRRDRD "move with key" esa +0e mvcl RR_RR "move long" esa +da mvcp SS_RRRDRD "move to primary" esa +db mvcs SS_RRRDRD "move to secondary" esa +e50e mvcsk SSE_RDRD "move with source key" esa +92 mvi SI_URD "move" esa +d1 mvn SS_L0RDRD "move numerics" esa +f1 mvo SS_LLRDRD "move with offset" esa +b254 mvpg RRE_RR "move page" esa +b255 mvst RRE_RR "move string" esa +d3 mvz SS_L0RDRD "move zones" esa +67 mxd RX_FRRD "multiply (long to ext.)" esa +27 mxdr RR_FF "multiply (long to ext.)" esa +26 mxr RR_FF "multiply (ext.)" esa +54 n RX_RRRD "AND" esa +d4 nc SS_L0RDRD "AND" esa +94 ni SI_URD "AND" esa +14 nr RR_RR "AND" esa +56 o RX_RRRD "OR" esa +d6 oc SS_L0RDRD "OR" esa +96 oi SI_URD "OR" esa +16 or RR_RR "OR" esa +f2 pack SS_LLRDRD "pack" esa +b248 palb RRE_00 "purge ALB" esa +b218 pc S_RD "program call" esa +0101 pr E "program return" esa +b228 pt RRE_RR "program transfer" esa +b20d ptlb S_00 "purge TLB" esa +b23b rchp S_00 "reset channel path" esa +b22a rrbe RRE_RR "reset reference bit extended" esa +b238 rsch S_00 "resume subchannel" esa +5b s RX_RRRD "subtract" esa +b219 sac S_RD "set address space control" esa +b279 sacf S_RD "set address space control fast" esa +b237 sal S_00 "set address limit" esa +b24e sar RRE_AR "set access" esa +b23c schm S_00 "set channel monitor" esa +b204 sck S_RD "set clock" esa +b206 sckc S_RD "set clock comparator" esa +6b sd RX_FRRD "subtract normalized (long)" esa +2b sdr RR_FF "subtract normalized (long)" esa +7b se RX_FRRD "subtract normalized (short)" esa +3b ser RR_FF "subtract normalized (short)" esa +4b sh RX_RRRD "subtract halfword" esa +b214 sie S_RD "start interpretive execution" esa +ae sigp RS_RRRD "signal processor" esa +5f sl RX_RRRD "subtract logical" esa +8b sla RS_R0RD "shift left single" esa +8f slda RS_R0RD "shift left double (long)" esa +8d sldl RS_R0RD "shift left double logical (long)" esa +89 sll RS_R0RD "shift left single logical" esa +1f slr RR_RR "subtract logical" esa +fb sp SS_LLRDRD "subtract decimal" esa +b20a spka S_RD "set PSW key from address" esa +04 spm RR_R0 "set program mask" esa +b208 spt S_RD "set CPU timer" esa +b210 spx S_RD "set prefix" esa +b244 sqdr RRE_F0 "square root (long)" esa +b245 sqer RRE_F0 "square root (short)" esa +1b sr RR_RR "subtract" esa +8a sra RS_R0RD "shift right single" esa +8e srda RS_R0RD "shift right double (long)" esa +8c srdl RS_R0RD "shift right double logical (long)" esa +88 srl RS_R0RD "shift right single logical" esa +f0 srp SS_LIRDRD "shift and round decimal" esa +b25e srst RRE_RR "search string" esa +b225 ssar RRE_R0 "set secondary ASN" esa +b233 ssch S_RD "start subchannel" esa +b22b sske RRE_RR "set storage key extended" esa +80 ssm S_RD "set system mask" esa +50 st RX_RRRD "store" esa +9b stam RS_AARD "store access multiple" esa +b212 stap S_RD "store CPU address" esa +42 stc RX_RRRD "store character" esa +b205 stck S_RD "store clock" esa +b207 stckc S_RD "store clock comparator" esa +be stcm RS_RURD "store characters under mask" esa +b23a stcps S_RD "store channel path status" esa +b239 stcrw S_RD "store channel report word" esa +b6 stctl RS_CCRD "store control" esa +60 std RX_FRRD "store (long)" esa +70 ste RX_FRRD "store (short)" esa +40 sth RX_RRRD "store halfword" esa +b202 stidp S_RD "store CPU id" esa +90 stm RS_RRRD "store multiple" esa +ac stnsm SI_URD "store then AND system mask" esa +ad stosm SI_URD "store then OR system mask" esa +b209 stpt S_RD "store CPU timer" esa +b211 stpx S_RD "store prefix" esa +b234 stsch S_RD "store subchannel" esa +b246 stura RRE_RR "store using real address" esa +7f su RX_FRRD "subtract unnormalized (short)" esa +3f sur RR_FF "subtract unnormalized (short)" esa +0a svc RR_U0 "supervisor call" esa +6f sw RX_FRRD "subtract unnormalized (long)" esa +2f swr RR_FF "subtract unnormalized (long)" esa +37 sxr RR_FF "subtract normalized (ext.)" esa +b24c tar RRE_AR "test access" esa +b22c tb RRE_0R "test block" esa +91 tm SI_URD "test under mask" esa +b236 tpi S_RD "test pending interruption" esa +e501 tprot SSE_RDRD "test protection" esa +dc tr SS_L0RDRD "translate" esa +99 trace RS_RRRD "trace" esa +dd trt SS_L0RDRD "translate and test" esa +93 ts S_RD "test and set" esa +b235 tsch S_RD "test subchannel" esa +f3 unpk SS_LLRDRD "unpack" esa +0102 upt E "update tree" esa +57 x RX_RRRD "exclusive OR" esa +d7 xc SS_L0RDRD "exclusive OR" esa +97 xi SI_URD "exclusive OR" esa +17 xr RR_RR "exclusive OR" esa +f8 zap SS_LLRDRD "zero and add" esa +a70a ahi RI_RI "add halfword immediate" esa +84 brxh RSI_RRP "branch relative on index high" esa +85 brxle RSI_RRP "branch relative on index low or equal" esa +a705 bras RI_RP "branch relative and save" esa +a704 brc RI_UP "branch relative on condition" esa +a706 brct RI_RP "branch relative on count" esa +b241 cksm RRE_RR "checksum" esa +a70e chi RI_RI "compare halfword immediate" esa +a9 clcle RS_RRRD "compare logical long extended" esa +a708 lhi RI_RI "load halfword immediate" esa +a8 mvcle RS_RRRD "move long extended" esa +a70c mhi RI_RI "multiply halfword immediate" esa +b252 msr RRE_RR "multiply single" esa +71 ms RX_RRRD "multiply single" esa +a700 tmh RI_RU "test under mask high" esa +a701 tml RI_RU "test under mask low" esa +0700 nopr RR_0R "no operation" esa +0710 bor RR_0R "branch on overflow / if ones" esa +0720 bhr RR_0R "branch on high" esa +0720 bpr RR_0R "branch on plus" esa +0730 bnler RR_0R "branch on not low or equal" esa +0740 blr RR_0R "branch on low" esa +0740 bmr RR_0R "branch on minus / if mixed" esa +0750 bnher RR_0R "branch on not high or equal" esa +0760 blhr RR_0R "branch on low or high" esa +0770 bner RR_0R "branch on not equal" esa +0770 bnzr RR_0R "branch on not zero / if not zeros" esa +0780 ber RR_0R "branch on equal" esa +0780 bzr RR_0R "branch on zero / if zeros" esa +0790 bnlhr RR_0R "branch on not low or high" esa +07a0 bher RR_0R "branch on high or equal" esa +07b0 bnlr RR_0R "branch on not low" esa +07b0 bnmr RR_0R "branch on not minus / if not mixed" esa +07c0 bler RR_0R "brach on low or equal" esa +07d0 bnhr RR_0R "branch on not high" esa +07d0 bnpr RR_0R "branch on not plus" esa +07e0 bnor RR_0R "branch on not overflow / if not ones" esa +07f0 br RR_0R "unconditional branch" esa +4700 nop RX_0RRD "no operation" esa +4710 bo RX_0RRD "branch on overflow / if ones" esa +4720 bh RX_0RRD "branch on high" esa +4720 bp RX_0RRD "branch on plus" esa +4730 bnle RX_0RRD "branch on not low or equal" esa +4740 bl RX_0RRD "branch on low" esa +4740 bm RX_0RRD "branch on minus / if mixed" esa +4750 bnhe RX_0RRD "branch on not high or equal" esa +4760 blh RX_0RRD "branch on low or high" esa +4770 bne RX_0RRD "branch on not equal" esa +4770 bnz RX_0RRD "branch on not zero / if not zeros" esa +4780 be RX_0RRD "branch on equal" esa +4780 bz RX_0RRD "branch on zero / if zeros" esa +4790 bnlh RX_0RRD "branch on not low or high" esa +47a0 bhe RX_0RRD "branch on high or equal" esa +47b0 bnl RX_0RRD "branch on not low" esa +47b0 bnm RX_0RRD "branch on not minus / if not mixed" esa +47c0 ble RX_0RRD "branch on low or equal" esa +47d0 bnh RX_0RRD "branch on not high" esa +47d0 bnp RX_0RRD "branch on not plus" esa +47e0 bno RX_0RRD "branch on not overflow / if not ones" esa +47f0 b RX_0RRD "unconditional branch" esa +a714 jo RI_0P "jump on overflow / if ones" esa +a724 jh RI_0P "jump on A high" esa +a724 jp RI_0P "jump on plus" esa +a734 jnle RI_0P "jump on not low or equal" esa +a744 jl RI_0P "jump on A low" esa +a744 jm RI_0P "jump on minus / if mixed" esa +a754 jnhe RI_0P "jump on not high or equal" esa +a764 jlh RI_0P "jump on low or high" esa +a774 jne RI_0P "jump on A not equal B" esa +a774 jnz RI_0P "jump on not zero / if not zeros" esa +a784 je RI_0P "jump on A equal B" esa +a784 jz RI_0P "jump on zero / if zeros" esa +a794 jnlh RI_0P "jump on not low or high" esa +a7a4 jhe RI_0P "jump on high or equal" esa +a7b4 jnl RI_0P "jump on A not low" esa +a7b4 jnm RI_0P "jump on not minus / if not mixed" esa +a7c4 jle RI_0P "jump on low or equal" esa +a7d4 jnh RI_0P "jump on A not high" esa +a7d4 jnp RI_0P "jump on not plus" esa +a7e4 jno RI_0P "jump on not overflow / if not ones" esa +a7f4 j RI_0P "jump" esa +b34a axbr RRE_FF "add extended bfp" esa +b31a adbr RRE_FF "add long bfp" esa +ed000000001a adb RXE_FRRD "add long bfp" esa +b30a aebr RRE_FF "add short bfp" esa +ed000000000a aeb RXE_FRRD "add short bfp" esa +b349 cxbr RRE_FF "compare extended bfp" esa +b319 cdbr RRE_FF "compare long bfp" esa +ed0000000019 cdb RXE_FRRD "compare long bfp" esa +b309 cebr RRE_FF "compare short bfp" esa +ed0000000009 ceb RXE_FRRD "compare short bfp" esa +b348 kxbr RRE_FF "compare and signal extended bfp" esa +b318 kdbr RRE_FF "compare and signal long bfp" esa +ed0000000018 kdb RXE_FRRD "compare and signal long bfp" esa +b308 kebr RRE_FF "compare and signal short bfp" esa +ed0000000008 keb RXE_FRRD "compare and signal short bfp" esa +b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" esa +b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" esa +b394 cefbr RRE_RF "convert from fixed 32 to short bfp" esa +b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" esa +b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" esa +b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" esa +b34d dxbr RRE_FF "divide extended bfp" esa +b31d ddbr RRE_FF "divide long bfp" esa +ed000000001d ddb RXE_FRRD "divide long bfp" esa +b30d debr RRE_FF "divide short bfp" esa +ed000000000d deb RXE_FRRD "divide short bfp" esa +b35b didbr RRF_FUFF "divide to integer long bfp" esa +b353 diebr RRF_FUFF "divide to integer short bfp" esa +b38c efpc RRE_RR "extract fpc" esa +b342 ltxbr RRE_FF "load and test extended bfp" esa +b312 ltdbr RRE_FF "load and test long bfp" esa +b302 ltebr RRE_FF "load and test short bfp" esa +b343 lcxbr RRE_FF "load complement extended bfp" esa +b313 lcdbr RRE_FF "load complement long bfp" esa +b303 lcebr RRE_FF "load complement short bfp" esa +b347 fixbr RRF_U0FF "load fp integer extended bfp" esa +b35f fidbr RRF_U0FF "load fp integer long bfp" esa +b357 fiebr RRF_U0FF "load fp integer short bfp" esa +b29d lfpc S_RD "load fpc" esa +b305 lxdbr RRE_FF "load lengthened long to extended bfp" esa +ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" esa +b306 lxebr RRE_FF "load lengthened short to extended bfp" esa +ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" esa +b304 ldebr RRE_FF "load lengthened short to long bfp" esa +ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" esa +b341 lnxbr RRE_FF "load negative extended bfp" esa +b311 lndbr RRE_FF "load negative long bfp" esa +b301 lnebr RRE_FF "load negative short bfp" esa +b340 lpxbr RRE_FF "load positive extended bfp" esa +b310 lpdbr RRE_FF "load positive long bfp" esa +b300 lpebr RRE_FF "load positive short bfp" esa +b345 ldxbr RRE_FF "load rounded extended to long bfp" esa +b346 lexbr RRE_FF "load rounded extended to short bfp" esa +b344 ledbr RRE_FF "load rounded long to short bfp" esa +b34c mxbr RRE_FF "multiply extended bfp" esa +b31c mdbr RRE_FF "multiply long bfp" esa +ed000000001c mdb RXE_FRRD "multiply long bfp" esa +b307 mxdbr RRE_FF "multiply long to extended bfp" esa +ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" esa +b317 meebr RRE_FF "multiply short bfp" esa +ed0000000017 meeb RXE_FRRD "multiply short bfp" esa +b30c mdebr RRE_FF "multiply short to long bfp" esa +ed000000000c mdeb RXE_FRRD "multiply short to long bfp" esa +b31e madbr RRF_F0FF "multiply and add long bfp" esa +ed000000001e madb RXF_FRRDF "multiply and add long bfp" esa +b30e maebr RRF_F0FF "multiply and add short bfp" esa +ed000000000e maeb RXF_FRRDF "multiply and add short bfp" esa +b31f msdbr RRF_F0FF "multiply and subtract long bfp" esa +ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" esa +b30f msebr RRF_F0FF "multiply and subtract short bfp" esa +ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" esa +b384 sfpc RRE_RR "set fpc" esa +b299 srnm S_RD "set rounding mode" esa +b316 sqxbr RRE_FF "square root extended bfp" esa +b315 sqdbr RRE_FF "square root long bfp" esa +ed0000000015 sqdb RXE_FRRD "square root long bfp" esa +b314 sqebr RRE_FF "square root short bfp" esa +ed0000000014 sqeb RXE_FRRD "square root short bfp" esa +b29c stfpc S_RD "store fpc" esa +b34b sxbr RRE_FF "subtract extended bfp" esa +b31b sdbr RRE_FF "subtract long bfp" esa +ed000000001b sdb RXE_FRRD "subtract long bfp" esa +b30b sebr RRE_FF "subtract short bfp" esa +ed000000000b seb RXE_FRRD "subtract short bfp" esa +ed0000000012 tcxb RXE_FRRD "test data class extended bfp" esa +ed0000000011 tcdb RXE_FRRD "test data class long bfp" esa +ed0000000010 tceb RXE_FRRD "test data class short bfp" esa +b274 siga S_RD "signal adapter" esa +# are the following instructions confidential ?? +b2a6 cuutf RRE_RR "convert unicode to utf-8" esa +b2a7 cutfu RRE_RR "convert utf-8 to unicode" esa +ee plo SS_RRRDRD2 "perform locked operation" esa +b25a bsa RRE_RR "branch and set authority" esa +b277 rp S_RD "resume program" esa +0107 sckpf E "set clock programmable field" esa +b27d stsi S_RD "store system information" esa +01ff trap2 E "trap" esa +b2ff trap4 S_RD "trap4" esa +# Here are the new esame instructions: +b946 bctgr RRE_RR "branch on count 64" esame +b900 lpgr RRE_RR "load positive 64" esame +b910 lpgfr RRE_RR "load positive 64<32" esame +b901 lngr RRE_RR "load negative 64" esame +b911 lngfr RRE_RR "load negative 64<32" esame +b902 ltgr RRE_RR "load and test 64" esame +b912 ltgfr RRE_RR "load and test 64<32" esame +b903 lcgr RRE_RR "load complement 64" esame +b913 lcgfr RRE_RR "load complement 64<32" esame +b980 ngr RRE_RR "and 64" esame +b921 clgr RRE_RR "compare logical 64" esame +b931 clgfr RRE_RR "compare logical 64<32" esame +b981 ogr RRE_RR "or 64" esame +b982 xgr RRE_RR "exclusive or 64" esame +b904 lgr RRE_RR "load 64" esame +b914 lgfr RRE_RR "load 64<32" esame +b920 cgr RRE_RR "compare 64" esame +b930 cgfr RRE_RR "compare 64<32" esame +b908 agr RRE_RR "add 64" esame +b918 agfr RRE_RR "add 64<32" esame +b909 sgr RRE_RR "subtract 64" esame +b919 sgfr RRE_RR "subtract 64<32" esame +b90a algr RRE_RR "add logical 64" esame +b91a algfr RRE_RR "add logical 64<32" esame +b90b slgr RRE_RR "subtract logical 64" esame +b91b slgfr RRE_RR "subtract logical 64<32" esame +e30000000046 bctg RXE_RRRD "branch on count 64" esame +e3000000002e cvdg RXE_RRRD "convert to decimal 64" esame +e3000000000e cvbg RXE_RRRD "convert to binary 64" esame +e30000000024 stg RXE_RRRD "store 64" esame +e30000000080 ng RXE_RRRD "and 64" esame +e30000000021 clg RXE_RRRD "compare logical 64" esame +e30000000031 clgf RXE_RRRD "comparee logical 64<32" esame +e30000000081 og RXE_RRRD "or 64" esame +e30000000082 xg RXE_RRRD "exclusive or 64" esame +e30000000004 lg RXE_RRRD "load 64" esame +e30000000014 lgf RXE_RRRD "load 64<32" esame +e30000000015 lgh RXE_RRRD "load halfword 64" esame +e30000000020 cg RXE_RRRD "compare 64" esame +e30000000030 cgf RXE_RRRD "compare 64<32" esame +e30000000008 ag RXE_RRRD "add 64" esame +e30000000018 agf RXE_RRRD "add 64<32" esame +e30000000009 sg RXE_RRRD "subtract 64" esame +e30000000019 sgf RXE_RRRD "subtract 64<32" esame +e3000000000a alg RXE_RRRD "add logical 64" esame +e3000000001a algf RXE_RRRD "add logical 64<32" esame +e3000000000b slg RXE_RRRD "subtract logical 64" esame +e3000000001b slgf RXE_RRRD "subtract logical 64<32" esame +e3000000000c msg RXE_RRRD "multiply single 64" esame +e3000000001c msgf RXE_RRRD "multiply single 64<32" esame +ec0000000044 brxhg RIE_RRP "branch relative on index high 64" esame +ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" esame +eb0000000044 bxhg RSE_RRRD "branch on index high 64" esame +eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" esame +eb000000000c srlg RSE_RRRD "shift right single logical 64" esame +eb000000000d sllg RSE_RRRD "shift left single logical 64" esame +eb000000000a srag RSE_RRRD "shift right single 64" esame +eb000000000b slag RSE_RRRD "shift left single 64" esame +eb0000000024 stmg RSE_RRRD "store multiple 64" esame +eb0000000026 stmh RSE_RRRD "store multiple high" esame +eb0000000004 lmg RSE_RRRD "load multiple 64" esame +eb0000000096 lmh RSE_RRRD "load multiple high" esame +ef lmd SS_RRRDRD3 "load multiple disjoint" esame +eb000000000f tracg RSE_RRRD "trace 64" esame +e30000000003 lrag RXE_RRRD "load real address 64" esame +e50000000002 strag SSE_RDRD "store read address" esame +eb0000000025 stctg RSE_RRRD "store control 64" esame +eb000000002f lctlg RSE_RRRD "load control 64" esame +eb0000000030 csg RSE_RRRD "compare and swap 64" esame +eb000000003e cdsg RSE_RRRD "compare double and swap 64" esame +eb0000000020 clmh RSE_RURD "compare logical characters under mask high" esame +eb000000002c stcmh RSE_RURD "store characters under mask high" esame +eb0000000080 icmh RSE_RURD "insert characters under mask high" esame +a700 tmlh RI_RU "test under mask low high" esame +a702 tmhh RI_RU "test under mask high high" esame +a701 tmll RI_RU "test under mask low low" esame +a703 tmhl RI_RU "test under mask high low" esame +c004 brcl RIL_UP "branch relative on condition long" esame +c014 jgo RIL_0P "jump long on overflow / if ones" esame +c024 jgh RIL_0P "jump long on high" esame +c024 jgp RIL_0P "jump long on plus" esame +c034 jgnle RIL_0P "jump long on not low or equal" esame +c044 jgl RIL_0P "jump long on low" esame +c044 jgm RIL_0P "jump long on minus / if mixed" esame +c054 jgnhe RIL_0P "jump long on not high or equal" esame +c064 jglh RIL_0P "jump long on low or high" esame +c074 jgne RIL_0P "jump long on not equal" esame +c074 jgnz RIL_0P "jump long on not zero / if not zeros" esame +c084 jge RIL_0P "jump long on equal" esame +c084 jgz RIL_0P "jump long on zero / if zeros" esame +c094 jgnlh RIL_0P "jump long on not low or high" esame +c0a4 jghe RIL_0P "jump long on high or equal" esame +c0b4 jgnl RIL_0P "jump long on not low" esame +c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" esame +c0c4 jgle RIL_0P "jump long on low or equal" esame +c0d4 jgnh RIL_0P "jump long on not high" esame +c0d4 jgnp RIL_0P "jump long on not plus" esame +c0e4 jgno RIL_0P "jump long on not overflow / if not ones" esame +c0f4 jg RIL_0P "jump long" esame +c005 brasl RIL_RP "branch relative and save long" esame +a707 brctg RI_RP "branch relative on count 64" esame +a709 lghi RI_RI "load halfword immediate 64" esame +a70b aghi RI_RI "add halfword immediate 64" esame +a70d mghi RI_RI "multiply halfword immediate 64" esame +a70f cghi RI_RI "compare halfword immediate 64" esame +b925 sturg RRE_RR "store using real address 64" esame +b90e eregg RRE_RR "extract stacked registers 64" esame +b905 lurag RRE_RR "load using real address 64" esame +b90c msgr RRE_RR "multiply single 64" esame +b91c msgfr RRE_RR "multiply single 64<32" esame +b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" esame +b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" esame +b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" esame +b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" esame +b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" esame +b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" esame +b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" esame +b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" esame +b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" esame +b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" esame +b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" esame +b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" esame +010b tam E "test addressing mode" esame +010c sam24 E "set addressing mode 24" esame +010d sam31 E "set addressing mode 31" esame +010e sam64 E "set addressing mode 64" esame +a500 iihh RI_RU "insert immediate high high" esame +a501 iihl RI_RU "insert immediate high low" esame +a502 iilh RI_RU "insert immediate low high" esame +a503 iill RI_RU "insert immediate low low" esame +a504 nihh RI_RU "and immediate high high" esame +a505 nihl RI_RU "and immediate high low" esame +a506 nilh RI_RU "and immediate low high" esame +a507 nill RI_RU "and immediate low low" esame +a508 oihh RI_RU "or immediate high high" esame +a509 oihl RI_RU "or immediate high low" esame +a50a oilh RI_RU "or immediate low high" esame +a50b oill RI_RU "or immediate low low" esame +a50c llihh RI_RU "load logical immediate high high" esame +a50d llihl RI_RU "load logical immediate high low" esame +a50e llilh RI_RU "load logical immediate low high" esame +a50f llill RI_RU "load logical immediate low low" esame +b2b1 stfl S_RD "store facility list" esame +b2b2 lpswe S_RD "load psw extended" esame +b90d dsgr RRE_RR "divide single 64" esame +b90f lrvgr RRE_RR "load reversed 64" esame +b916 llgfr RRE_RR "load logical 64<32" esame +b917 llgtr RRE_RR "load logical thirty one bits" esame +b91d dsgfr RRE_RR "divide single 64<32" esame +b91f lrvr RRE_RR "load reversed 32" esame +b986 mlgr RRE_RR "multiply logical 64" esame +b987 dlgr RRE_RR "divide logical 64" esame +b988 alcgr RRE_RR "add logical with carry 64" esame +b989 slbgr RRE_RR "subtract logical with borrow 64" esame +b98d epsw RRE_RR "extract psw" esame +b996 mlr RRE_RR "multiply logical 32" esame +b997 dlr RRE_RR "divide logical 32" esame +b998 alcr RRE_RR "add logical with carry 32" esame +b999 slbr RRE_RR "subtract logical with borrow 32" esame +b99d esea RRE_R0 "extract and set extended authority" esame +c000 larl RIL_RP "load address relative long" esame +e3000000000d dsg RXE_RRRD "divide single 64" esame +e3000000000f lrvg RXE_RRRD "load reversed 64" esame +e30000000016 llgf RXE_RRRD "load logical 64<32" esame +e30000000017 llgt RXE_RRRD "load logical thirty one bits" esame +e3000000001d dsgf RXE_RRRD "divide single 64<32" esame +e3000000001e lrv RXE_RRRD "load reversed 32" esame +e3000000001f lrvh RXE_RRRD "load reversed 16" esame +e3000000002f strvg RXE_RRRD "store reversed 64" esame +e3000000003e strv RXE_RRRD "store reversed 32" esame +e3000000003f strvh RXE_RRRD "store reversed 64" esame +e30000000086 mlg RXE_RRRD "multiply logical 64" esame +e30000000087 dlg RXE_RRRD "divide logical 64" esame +e30000000088 alcg RXE_RRRD "add logical with carry 64" esame +e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" esame +e3000000008e stpq RXE_RRRD "store pair to quadword" esame +e3000000008f lpq RXE_RRRD "load pair from quadword" esame +e30000000096 ml RXE_RRRD "multiply logical 32" esame +e30000000097 dl RXE_RRRD "divide logical 32" esame +e30000000098 alc RXE_RRRD "add logical with carry 32" esame +e30000000099 slb RXE_RRRD "subtract logical with borrow 32" esame +e30000000090 llgc RXE_RRRD "load logical character" esame +e30000000091 llgh RXE_RRRD "load logical halfword" esame +eb000000001c rllg RSE_RRRD "rotate left single logical 64" esame +eb000000001d rll RSE_RRRD "rotate left single logical 32" esame +b278 stcke S_RD "store clock extended" esame +b2a5 tre RRE_RR "translate extended" esame +eb000000008e mvclu RSE_RRRD "move long unicode" esame +e9 pka SS_L0RDRD "pack ascii" esame +e1 pku SS_L0RDRD "pack unicode" esame +b993 troo RRE_RR "translate one to one" esame +b992 trot RRE_RR "translate one to two" esame +b991 trto RRE_RR "translate two to one" esame +b990 trtt RRE_RR "translate two to two" esame +ea unpka SS_L0RDRD "unpack ascii" esame +e2 unpku SS_L0RDRD "unpack unicode" esame +b358 thder RRE_RR "convert short bfp to long hfp" esame +b359 thdr RRE_RR "convert long bfp to long hfp" esame +b350 tbedr RRF_U0FF "convert long hfp to short bfp" esame +b351 tbdr RRF_U0FF "convert long hfp to long bfp" esame +b374 lzer RRE_R0 "load short zero" esame +b375 lzdr RRE_R0 "load long zero" esame +b376 lzxr RRE_R0 "load extended zero" esame |
