diff options
Diffstat (limited to 'contrib/binutils/opcodes')
44 files changed, 36176 insertions, 7407 deletions
diff --git a/contrib/binutils/opcodes/ChangeLog b/contrib/binutils/opcodes/ChangeLog index aa7e202..f6c6418 100644 --- a/contrib/binutils/opcodes/ChangeLog +++ b/contrib/binutils/opcodes/ChangeLog @@ -1,305 +1,639 @@ -2006-06-09 Nick Clifton <nickc@redhat.com> +2007-07-03 Nathan Sidwell <nathan@codesourcery.com> - * po/fi.po: Updated Finnish translation. + * m68k-dis.c (fetch_arg): Add E. Replace length switch with + direct masking. + (print_ins_arg): Add j & K operand types. + (match_insn_m68k): Check and skip initial '.' arg character. + (m68k_scan_mask): Likewise. + * m68k-opc.c (m68k_opcodes): Add coprocessor instructions. -2006-06-07 Joseph S. Myers <joseph@codesourcery.com> +2007-07-02 Alan Modra <amodra@bigpond.net.au> - * po/Make-in (pdf, ps): New dummy targets. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. -2006-05-30 Nick Clifton <nickc@redhat.com> +2007-06-30 H.J. Lu <hongjiu.lu@intel.com> - * po/es.po: Updated Spanish translation. + * aclocal.m4: Regenerated. + * Makefile.in: Likewise. -2006-05-26 Richard Sandiford <richard@codesourcery.com> +2007-06-29 H.J. Lu <hongjiu.lu@intel.com> - * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd - and fmovem entries. Put register list entries before immediate - mask entries. Use "l" rather than "L" in the fmovem entries. - * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it - out from INFO. - (m68k_scan_mask): New function, split out from... - (print_insn_m68k): ...here. If no architecture has been set, - first try printing an m680x0 instruction, then try a Coldfire one. + * i386-reg.tbl: Remove spaces before comments. -2006-05-24 Nick Clifton <nickc@redhat.com> +2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> - * po/ga.po: Updated Irish translation. + * cr16-opc.c: New file. + * cr16-dis.c: New file. + * Makefile.am: Entries for cr16. + * Makefile.in: Regenerate. + * cofigure.in: Add cr16 target information. + * configure : Regenerate. + * disassemble.c: Add cr16 target information. -2006-05-22 Nick Clifton <nickc@redhat.com> +2007-06-28 H.J. Lu <hongjiu.lu@intel.com> - * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts. + * Makefile.am (HFILES): Add i386-opc.h and i386-tbl.h. + (CFILES): Add i386-gen.c. + (i386-gen): New rule. + (i386-gen.o): Likewise. + (i386-tbl.h): Likewise. + Run "make dep-am". + * Makefile.in: Regenerated. -2006-05-22 Nick Clifton <nickc@redhat.com> + * i386-gen.c: New file. + * i386-opc.tbl: Likewise. + * i386-reg.tbl: Likewise. + * i386-tbl.h: Likewise. - * po/nl.po: Updated translation. + * i386-opc.c: Include "i386-tbl.h". + (i386_optab): Removed. + (i386_regtab): Likewise. + (i386_regtab_size): Likewise. -2006-05-18 Alan Modra <amodra@bigpond.net.au> +2007-06-26 Paul Brook <paul@codesourcery.com> - * avr-dis.c (avr_operand): Warning fix. + * arm-dis.c (coprocessor_opcodes): Add fmxr/fmrx mvfr0/mvfr1. -2006-05-04 Thiemo Seufer <ths@mips.com> +2007-06-25 H.J. Lu <hongjiu.lu@intel.com> - * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order. + * i386-opc.h (regKludge): Renamed to ... + (RegKludge): This. -2006-04-16 Daniel Jacobowitz <dan@codesourcery.com> + * i386-opc.c (i386_optab): Replace regKludge with RegKludge. - * po/POTFILES.in: Regenerated. +2007-06-23 H.J. Lu <hongjiu.lu@intel.com> -2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de> + PR binutils/4667 + * i386-dis.c (EX): Removed. + (EMd): New. + (EMq): Likewise. + (EXd): Likewise. + (EXq): Likewise. + (EXx): Likewise. + (PREGRP93...PREGRP97): Likewise. + (dis386_twobyte): Updated. + (prefix_user_table): Updated. Add PREGRP93...PREGRP97. + (OP_EX): Remove Intel syntax handling. - PR binutils/2454 - * avr-dis.c (avr_operand): Arrange for a comment to appear before - the symolic form of an address, so that the output of objdump -d - can be reassembled. +2007-06-18 Nathan Sidwell <nathan@codesourcery.com> -2006-04-10 DJ Delorie <dj@redhat.com> + * m68k-opc.c (m68k_opcodes): Add wdebugl variants. - * m32c-asm.c: Regenerate. +2007-06-14 H.J. Lu <hongjiu.lu@intel.com> + + * Makefile.am (ACLOCAL_AMFLAGS): Add -I ../config -I ../bfd. + + * acinclude.m4: Removed. + + * Makefile.in: Regenerated. + * doc/Makefile.in: Likewise. + * aclocal.m4: Likewise. + * configure: Likewise. + +2007-06-05 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (thumb32_opcodes): Display writeback ldrd/strd addresses. + +2007-05-24 Steve Ellcey <sje@cup.hp.com> + + * Makefile.in: Regnerate. + * configure: Regenerate. + * aclocal.m4: Regenerate. + +2007-05-18 Alan Modra <amodra@bigpond.net.au> + + * ppc-dis.c (print_insn_powerpc): Don't skip all operands + after setting skip_optional. + +2007-05-16 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-dis.c (operand_value_powerpc, skip_optional_operands): New. + (print_insn_powerpc): Use the new operand_value_powerpc and + skip_optional_operands functions to omit or print all optional + operands as a group. + * ppc-opc.c (BFF, W, XFL_L, XWRA_MASK): New. + (XFL_MASK): Delete L and W bits from the mask. + (mtfsfi, mtfsfi.): Replace use of BF with BFF. Relpace use of XRA_MASK + with XWRA_MASK. Use W. + (mtfsf, mtfsf.): Use XFL_L and W. + +2007-05-14 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/4502 + * i386-dis.c (Suffix3DNow): Replace "pfmulhrw" with "pmulhrw". + +2007-05-10 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.h (ShortForm): Redefined. + (Jump): Likewise. + (JumpDword): Likewise. + (JumpByte): Likewise. + (JumpInterSegment): Likewise. + (FloatMF): Likewise. + (FloatR): Likewise. + (FloatD): Likewise. + (Size16): Likewise. + (Size32): Likewise. + (Size64): Likewise. + (IgnoreSize): Likewise. + (DefaultSize): Likewise. + (No_bSuf): Likewise. + (No_wSuf): Likewise. + (No_lSuf): Likewise. + (No_sSuf): Likewise. + (No_qSuf): Likewise. + (No_xSuf): Likewise. + (FWait): Likewise. + (IsString): Likewise. + (regKludge): Likewise. + (IsPrefix): Likewise. + (ImmExt): Likewise. + (NoRex64): Likewise. + (Rex64): Likewise. + (Ugh): Likewise. + +2007-05-07 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (threebyte_0x38_uses_DATA_prefix): Correct entries + for some SSE4 instructions. + (threebyte_0x3a_uses_DATA_prefix): Likewise. + +2007-05-03 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode. + + * i386-opc.c (i386_optab): Remove IgnoreSize and correct operand + type for crc32. + +2007-05-01 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and + check data size prefix in 16bit mode. + + * i386-opc.c (i386_optab): Default crc32 to non-8bit and + support Intel mode. + +2007-04-30 Mark Salter <msalter@redhat.com> + + * frv-desc.c: Regenerate. + * frv-desc.h: Regenerate. + +2007-04-30 Alan Modra <amodra@bigpond.net.au> + + PR 4436 + * ppc-opc.c (powerpc_operands): Correct bitm for second entry of MBE. + +2007-04-27 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (modrm): Put reg before rm. + +2007-04-26 H.J. Lu <hongjiu.lu@intel.com> -2006-04-06 Carlos O'Donell <carlos@codesourcery.com> + PR binutils/4430 + * i386-dis.c (print_displacement): New. + (OP_E): Call print_displacement instead of print_operand_value + to output displacement when either base or index exist. Print + the explicit zero displacement in 16bit mode. - * Makefile.am: Add install-html target. +2007-04-26 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/4429 + * i386-dis.c (print_insn): Also swap the order of op_riprel + when swapping op_index. Break when the RIP relative address + is printed. + (OP_E): Properly handle RIP relative addressing and print the + explicit zero displacement for Intel mode. + +2007-04-27 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. + * ns32k-dis.c: Include sysdep.h first. -2006-04-06 Nick Clifton <nickc@redhat.com> +2007-04-24 Andreas Krebbel <krebbel1@de.ibm.com> - * po/vi/po: Updated Vietnamese translation. + * opcodes/s390-opc.c (MASK_SSF_RRDRD): Fourth nybble belongs to the + opcode. + * opcodes/s390-opc.txt (pfpo, ectg, csst): Add new z9-ec instructions. -2006-03-31 Paul Koning <ni1d@arrl.net> +2007-04-24 Nick Clifton <nickc@redhat.com> - * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction. + * arm-dis.c (print_insn): Initialise type. -2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com> +2007-04-24 Alan Modra <amodra@bigpond.net.au> - * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the - logic to identify halfword shifts. + * cgen-types.h: Include bfd_stdint.h, not stdint.h. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. -2006-03-16 Paul Brook <paul@codesourcery.com> +2007-04-23 Nathan Sidwell <nathan@codesourcery.com> - * arm-dis.c (arm_opcodes): Rename swi to svc. - (thumb_opcodes): Ditto. + * m68k-opc.c: Mark mcfisa_c instructions. -2006-03-13 DJ Delorie <dj@redhat.com> +2007-04-21 Richard Earnshaw <rearnsha@arm.com> - * m32c-asm.c: Regenerate. - * m32c-desc.c: Likewise. - * m32c-desc.h: Likewise. - * m32c-dis.c: Likewise. - * m32c-ibld.c: Likewise. - * m32c-opc.c: Likewise. - * m32c-opc.h: Likewise. - -2006-03-10 DJ Delorie <dj@redhat.com> - - * m32c-desc.c: Regenerate with mul.l, mulu.l. - * m32c-opc.c: Likewise. - * m32c-opc.h: Likewise. - - -2006-03-09 Nick Clifton <nickc@redhat.com> - - * po/sv.po: Updated Swedish translation. - -2006-03-07 H.J. Lu <hongjiu.lu@intel.com> - - PR binutils/2428 - * i386-dis.c (REP_Fixup): New function. - (AL): Remove duplicate. - (Xbr): New. - (Xvr): Likewise. - (Ybr): Likewise. - (Yvr): Likewise. - (indirDXr): Likewise. - (ALr): Likewise. - (eAXr): Likewise. - (dis386): Updated entries of ins, outs, movs, lods and stos. - -2006-03-05 Nick Clifton <nickc@redhat.com> - - * cgen-ibld.in (insert_normal): Cope with attempts to insert a - signed 32-bit value into an unsigned 32-bit field when the host is - a 64-bit machine. - * fr30-ibld.c: Regenerate. - * frv-ibld.c: Regenerate. - * ip2k-ibld.c: Regenerate. - * iq2000-asm.c: Regenerate. - * iq2000-ibld.c: Regenerate. - * m32c-ibld.c: Regenerate. - * m32r-ibld.c: Regenerate. - * openrisc-ibld.c: Regenerate. - * xc16x-ibld.c: Regenerate. - * xstormy16-ibld.c: Regenerate. + * arm-dis.c (arm_opcodes): Disassemble to unified syntax. + (thumb_opcodes): Add missing white space in adr. + (arm_decode_shift): New parameter, print_shift. Only decode the + shift parameter if set. Adjust callers. + (print_insn_arm): Support for operand type q with no shift decode. -2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com) +2007-04-21 Alan Modra <amodra@bigpond.net.au> - * xc16x-asm.c: Regenerate. - * xc16x-dis.c: Regenerate. + * i386-opc.c (i386_float_regtab, i386_float_regtab_size): Delete. + Move contents to.. + (i386_regtab): ..here. + * i386-opc.h (i386_float_regtab, i386_float_regtab_size): Delete. + + * ppc-opc.c (powerpc_operands): Delete duplicate entries. + (BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete. + (VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete. + (powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L. -2006-02-27 Carlos O'Donell <carlos@codesourcery.com> +2007-04-20 Nathan Sidwell <nathan@codesourcery.com> - * po/Make-in: Add html target. + * m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as + rambar1. -2006-02-27 H.J. Lu <hongjiu.lu@intel.com> +2007-04-20 Alan Modra <amodra@bigpond.net.au> + + * ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand + change. + * ppc-opc.c (powerpc_operands): Replace bit count with bit mask + in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove + references to following deleted functions. + (insert_bd, extract_bd, insert_dq, extract_dq): Delete. + (insert_ds, extract_ds, insert_de, extract_de): Delete. + (insert_des, extract_des, insert_li, extract_li): Delete. + (insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete. + (insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete. + (num_powerpc_operands): New constant. + (XSPRG_MASK): Remove entire SPRG field. + (powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK. + +2007-04-20 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (DCM, DGM, TE, RMC, R, SP, S): Correct shift. + (Z2_MASK): Define. + (powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand. + +2007-04-20 Richard Earnshaw <rearnsha@arm.com> + + * arm-dis.c (print_insn): Only look for a mapping symbol in the section + being disassembled. + +2007-04-19 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. - * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by - Intel Merom New Instructions. - (THREE_BYTE_0): Likewise. - (THREE_BYTE_1): Likewise. +2007-04-19 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (powerpc_opcodes): Add cctpl, cctpm, cctph, db8cyc, + db10cyc, db12cyc, db16cyc. + +2007-04-19 Nathan Froyd <froydnj@codesourcery.com> + + * ppc-opc.c (powerpc_opcodes): Recognize three-operand tlbsxe. + +2007-04-18 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (CRC32_Fixup): New. + (PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90, + PREGRP91): New. + (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2. + (threebyte_0x3a_uses_DATA_prefix): Likewise. + (prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87, + PREGRP88, PREGRP89, PREGRP90 and PREGRP91. (three_byte_table): Likewise. - (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use - THREE_BYTE_1 for entry 0x3a. - (twobyte_has_modrm): Updated. - (twobyte_uses_SSE_prefix): Likewise. - (print_insn): Handle 3-byte opcodes used by Intel Merom New - Instructions. - -2006-02-24 David S. Miller <davem@sunset.davemloft.net> - - * sparc-dis.c (v9_priv_reg_names): Add "gl" entry. - (v9_hpriv_reg_names): New table. - (print_insn_sparc): Allow values up to 16 for '?' and '!'. - New cases '$' and '%' for read/write hyperprivileged register. - * sparc-opc.c (sparc_opcodes): Add new entries for UA2005 - window handling and rdhpr/wrhpr instructions. - -2006-02-24 DJ Delorie <dj@redhat.com> - - * m32c-desc.c: Regenerate with linker relaxation attributes. - * m32c-desc.h: Likewise. - * m32c-dis.c: Likewise. - * m32c-opc.c: Likewise. - -2006-02-24 Paul Brook <paul@codesourcery.com> - - * arm-dis.c (arm_opcodes): Add V7 instructions. - (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. - (print_arm_address): New function. - (print_insn_arm): Use it. Add 'P' and 'U' cases. - (psr_name): New function. - (print_insn_thumb32): Add 'U', 'C' and 'D' cases. - -2006-02-23 H.J. Lu <hongjiu.lu@intel.com> - - * ia64-opc-i.c (bXc): New. - (mXc): Likewise. - (OpX2TaTbYaXcC): Likewise. - (TF). Likewise. - (TFCM). Likewise. - (ia64_opcodes_i): Add instructions for tf. - - * ia64-opc.h (IMMU5b): New. - - * ia64-asmtab.c: Regenerated. - -2006-02-23 H.J. Lu <hongjiu.lu@intel.com> - - * ia64-gen.c: Update copyright years. - * ia64-opc-b.c: Likewise. - -2006-02-22 H.J. Lu <hongjiu.lu@intel.com> - - * ia64-gen.c (lookup_regindex): Handle ".vm". - (print_dependency_table): Handle '\"'. - - * ia64-ic.tbl: Updated from SDM 2.2. - * ia64-raw.tbl: Likewise. - * ia64-waw.tbl: Likewise. - * ia64-asmtab.c: Regenerated. - - * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1. - -2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com> - Anil Paranjape <anilp1@kpitcummins.com> - Shilin Shakti <shilins@kpitcummins.com> - - * xc16x-desc.h: New file - * xc16x-desc.c: New file - * xc16x-opc.h: New file - * xc16x-opc.c: New file - * xc16x-ibld.c: New file - * xc16x-asm.c: New file - * xc16x-dis.c: New file - * Makefile.am: Entries for xc16x - * Makefile.in: Regenerate - * cofigure.in: Add xc16x target information. - * configure: Regenerate. - * disassemble.c: Add xc16x target information. -2006-02-11 H.J. Lu <hongjiu.lu@intel.com> + * i386-opc.c (i386_optab): Add SSE4.2 opcodes. - * i386-dis.c (dis386_twobyte): Use "movZ" for debug register - moves. + * i386-opc.h (CpuSSE4_2): New. + (CpuSSE4): Likewise. + (CpuUnknownFlags): Add CpuSSE4_2. -2006-02-11 H.J. Lu <hongjiu.lu@intel.com> +2007-04-18 H.J. Lu <hongjiu.lu@intel.com> - * i386-dis.c ('Z'): Add a new macro. - (dis386_twobyte): Use "movZ" for control register moves. + * i386-dis.c (XMM_Fixup): New. + (Edqb): New. + (Edqd): New. + (XMM0): New. + (dqb_mode): New. + (dqd_mode): New. + (PREGRP39 ... PREGRP85): New. + (threebyte_0x38_uses_DATA_prefix): Updated for SSE4. + (threebyte_0x3a_uses_DATA_prefix): Likewise. + (prefix_user_table): Add PREGRP39 ... PREGRP85. + (three_byte_table): Likewise. + (putop): Handle 'K'. + (intel_operand_size): Handle dqb_mode, dqd_mode): + (OP_E): Likewise. + (OP_G): Likewise. -2006-02-10 Nick Clifton <nickc@redhat.com> + * i386-opc.c (i386_optab): Add SSE4.1 opcodes. - * iq2000-asm.c: Regenerate. + * i386-opc.h (CpuSSE4_1): New. + (CpuUnknownFlags): Add CpuSSE4_1. + (regKludge): Update comment. -2006-02-07 Nathan Sidwell <nathan@codesourcery.com> +2007-04-18 Matthias Klose <doko@ubuntu.com> - * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features. + * Makefile.am (libopcodes_la_LDFLAGS): Use bfd soversion. + * Makefile.in: Regenerate. + +2007-04-14 Steve Ellcey <sje@cup.hp.com> + + * Makefile.am: Add ACLOCAL_AMFLAGS. + * Makefile.in: Regenerate. -2006-01-26 David Ung <davidu@mips.com> +2007-04-13 H.J. Lu <hongjiu.lu@intel.com> - * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx, - ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d, - floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d, - nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d, - rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s. + * i386-dis.c: Remove trailing white spaces. + * i386-opc.c: Likewise. + * i386-opc.h: Likewise. -2006-01-18 Arnold Metselaar <arnoldm@sourceware.org> +2007-04-11 H.J. Lu <hongjiu.lu@intel.com> - * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d, - ld_d_r, pref_xd_cb): Use signed char to hold data to be - disassembled. - * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes - buffer overflows when disassembling instructions like - ld (ix+123),0x23 - * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed - operand, if the offset is negative. + PR binutils/4333 + * i386-dis.c (GRP1a): New. + (GRP1b ... GRPPADLCK2): Update index. + (dis386): Use GRP1a for entry 0x8f. + (mod, rm, reg): Removed. Replaced by ... + (modrm): This. + (grps): Add GRP1a. -2006-01-17 Arnold Metselaar <arnoldm@sourceware.org> +2007-04-09 Kazu Hirata <kazu@codesourcery.com> - * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use - unsigned char to hold data to be disassembled. + * m68k-dis.c (print_insn_m68k): Restore info->fprintf_func and + info->print_address_func if longjmp is called. -2006-01-17 Andreas Schwab <schwab@suse.de> +2007-03-29 DJ Delorie <dj@redhat.com> - PR binutils/1486 - * disassemble.c (disassemble_init_for_target): Set - disassembler_needs_relocs for bfd_arch_arm. + * m32c-desc.c: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-opc.c: Regenerate. -2006-01-16 Paul Brook <paul@codesourcery.com> +2007-03-28 H.J. Lu <hongjiu.lu@intel.com> - * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss, - f?add?, and f?sub? instructions. + * i386-opc.c (i386_optab): Change InvMem to RegMem for mov and + movq. Remove InvMem from sldt, smsw and str. -2006-01-16 Nick Clifton <nickc@redhat.com> + * i386-opc.h (InvMem): Renamed to ... + (RegMem): Update comments. + (AnyMem): Remove InvMem. - * po/zh_CN.po: New Chinese (simplified) translation. - * configure.in (ALL_LINGUAS): Add "zh_CH". - * configure: Regenerate. +2007-03-27 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (thumb_opcodes): Add entry for undefined insns (0xbe??). -2006-01-05 Paul Brook <paul@codesourcery.com> +2007-03-24 Paul Brook <paul@codesourcery.com> - * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry. + * arm-dis.c (coprocessor_opcodes): Remove superfluous 0x. + (print_insn_coprocessor): Handle %<bitfield>x. -2006-01-06 DJ Delorie <dj@redhat.com> +2007-03-24 Paul Brook <paul@codesourcery.com> + Mark Shinwell <shinwell@codesourcery.com> + * arm-dis.c (arm_opcodes): Print SRS base register. + +2007-03-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (prefix_name): Replace rex64XYZ with rex.WRXB. + + * i386-opc.c (i386_optab): Add rex.wrxb. + +2007-03-21 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (REX_MODE64): Remove definition. + (REX_EXTX): Likewise. + (REX_EXTY): Likewise. + (REX_EXTZ): Likewise. + (USED_REX): Use REX_OPCODE instead of 0x40. + Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W, + REX_R, REX_X and REX_B respectively. + +2007-03-21 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/4218 + * i386-dis.c (PREGRP38): New. + (dis386): Use PREGRP38 for 0x90. + (prefix_user_table): Add PREGRP38. + (print_insn): Set uses_REPZ_prefix to 1 for pause. + (NOP_Fixup1): Properly handle REX bits. + (NOP_Fixup2): Likewise. + + * i386-opc.c (i386_optab): Allow %eax with xchg in 64bit. + Allow register with nop. + +2007-03-20 DJ Delorie <dj@redhat.com> + + * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.h: Regenerate. + * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate. -2006-01-03 DJ Delorie <dj@redhat.com> +2007-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.c: Include "libiberty.h". + (i386_regtab): Remove the last entry. + (i386_regtab_size): New. + (i386_float_regtab_size): Likewise. + + * i386-opc.h (i386_regtab_size): New. + (i386_float_regtab_size): Likewise. + +2007-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * Makefile.am (CFILES): Add i386-opc.c. + (ALL_MACHINES): Add i386-opc.lo. + Run "make dep-am". + * Makefile.in: Regenerated. + + * configure.in: Add i386-opc.lo for bfd_i386_arch. + * configure: Regenerated. + + * i386-dis.c: Include "opcode/i386.h". + (MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition. + (FWAIT_OPCODE): Remove definition. + (UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition. + (MAX_OPERANDS): Remove definition. + + * i386-opc.c: New file. + * i386-opc.h: Likewise. + +2007-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * Makefile.in: Regenerated. + +2007-03-09 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (OP_Rd): Renamed to ... + (OP_R): This. + (Rd): Updated. + (Rm): Likewise. + +2007-03-08 Alan Modra <amodra@bigpond.net.au> + + * fr30-asm.c: Regenerate. + * frv-asm.c: Regenerate. + * ip2k-asm.c: Regenerate. + * iq2000-asm.c: Regenerate. + * m32c-asm.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-dis.c: Regenerate. + * mt-asm.c: Regenerate. + * mt-ibld.c: Regenerate. + * mt-opc.c: Regenerate. + * openrisc-asm.c: Regenerate. + * xc16x-asm.c: Regenerate. + * xstormy16-asm.c: Regenerate. + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com> + + * opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, + INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New + instruction formats added. + (MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF, + MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format + masks added. + * opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point + instructions added. + * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. + (main): z9-ec cpu type option added. + * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. + +2007-02-22 DJ Delorie <dj@redhat.com> + + * s390-opc.c (INSTR_SS_L2RDRD): New. + (MASK_SS_L2RDRD): New. + * s390-opc.txt (pka): Use it. + +2007-02-20 Thiemo Seufer <ths@mips.com> + Chao-Ying Fu <fu@mips.com> + + * mips-dis.c (mips_arch_choices): Add DSP R2 support. + (print_insn_args): Add support for balign instruction. + * mips-opc.c (D33): New shortcut for DSP R2 instructions. + (mips_builtin_opcodes): Add DSP R2 instructions. + +2007-02-19 Andreas Krebbel <krebbel1@de.ibm.com> + + * s390-opc.c (INSTR_RRF_U0FR, MASK_RRF_U0FR): Removed. + (INSTR_RRF_U0RF, MASK_RRF_U0RF): Added. + * s390-opc.txt (cfxbr, cfdbr, cfebr, cgebr, cgdbr, cgxbr, cger, cgdr, + cgxr, cfxr, cfdr, cfer): Instruction type set to INSTR_RRF_U0RF. + +2007-02-19 Andreas Krebbel <krebbel1@de.ibm.com> + + * s390-opc.txt ("efpc", "sfpc"): Set to RRE_RR_OPT instruction type. + * s390-opc.c (s390_operands): Add RO_28 as optional gpr. + (INSTR_RRE_RR_OPT, MASK_RRE_RR_OPT): New instruction type for efpc + and sfpc. + +2007-02-16 Nick Clifton <nickc@redhat.com> + + PR binutils/4045 + * avr-dis.c (comment_start): New variable, contains the prefix to + use when printing addresses in comments. + (print_insn_avr): Set comment_start to an empty space if there is + no symbol table available as the generic address printing code + will prefix the numeric value of the address with 0x. + +2007-02-13 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c: Updated to use an array of MAX_OPERANDS operands + in struct dis386. + +2007-02-05 Dave Brolley <brolley@redhat.com> + Richard Sandiford <rsandifo@redhat.com> + DJ Delorie <dj@redhat.com> + Graydon Hoare <graydon@redhat.com> + Frank Ch. Eigler <fche@redhat.com> + Ben Elliston <bje@redhat.com> + + * Makefile.am (HFILES): Add mep-desc.h mep-opc.h. + (CFILES): Add mep-*.c + (ALL_MACHINES): Add mep-*.lo. + (CLEANFILES): Add stamp-mep. + (CGEN_CPUS): Add mep. + (MEP_DEPS): New variable. + (mep-*): New targets. + * configure.in: Handle bfd_mep_arch. + * disassemble.c (ARCH_mep): New macro. + (disassembler): Handle bfd_arch_mep. + (disassemble_init_for_target): Likewise. + * mep-*: New files for Toshiba Media Processor (MeP). + * Makefile.in: Regenerated. + * configure: Regenerated. + +2007-02-05 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (OP_J): Undo the last change. Properly handle 64K + wrap around within the same segment in 16bit mode. + +2007-02-02 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (OP_J): Mask to 16bit only if there is a data16 + prefix. + +2007-02-02 H.J. Lu <hongjiu.lu@intel.com> + + * avr-dis.c (avr_operand): Correct PR number in comment. + +2007-02-02 H.J. Lu <hongjiu.lu@intel.com> + + * disassemble.c (disassembler_usage): Call + print_i386_disassembler_options for i386 disassembler. + + * i386-dis.c (print_i386_disassembler_options): New. + (print_insn): Support the new addr64 option. + +2007-02-02 Hiroki Kaminaga <kaminaga@sm.sony.co.jp> + + * ppc-dis.c (powerpc_dialect): Handle ppc440. + * ppc-dis.c (print_ppc_disassembler_options): Note the -M440 can + be used. + +2007-02-02 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (insert_bdm): -Many comment. + (valid_bo): Add "extract" param. Accept both powerpc and power4 + BO fields when disassembling with -Many. + (insert_bo, extract_bo, insert_boe, extract_boe): Adjust valid_bo call. + +2007-01-08 Kazu Hirata <kazu@codesourcery.com> + + * m68k-opc.c (m68k_opcodes): Replace cpu32 with + cpu32 | fido_a except on tbl instructions. + +2007-01-04 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (arm_opcodes): Fix cpsie and cpsid entries. + +2007-01-04 Andreas Schwab <schwab@suse.de> + + * m68k-opc.c: Fix encoding of signed bit in the cpu32 tbls insns. + +2007-01-04 Julian Brown <julian@codesourcery.com> - * cgen-ibld.in (extract_normal): Avoid memory range errors. - * m32c-ibld.c: Regenerated. + * arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl, + vqrshl instructions. -For older changes see ChangeLog-2005 +For older changes see ChangeLog-2006 Local Variables: mode: change-log diff --git a/contrib/binutils/opcodes/ChangeLog-2006 b/contrib/binutils/opcodes/ChangeLog-2006 new file mode 100644 index 0000000..cc5ec75d --- /dev/null +++ b/contrib/binutils/opcodes/ChangeLog-2006 @@ -0,0 +1,837 @@ +2006-12-27 Kazu Hirata <kazu@codesourcery.com> + + * m68k-dis.c (print_insn_arg): Add support for cac and mbb. + +2006-12-27 Kazu Hirata <kazu@codesourcery.com> + + * m68k-opc.c (m68k_opcodes): Add sleep and trapx. + +2006-12-15 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (o_mode): New for 16-byte operand. + (intel_operand_size): Generate "OWORD PTR " for o_mode. + (CMPXCHG8B_Fixup): Set bytemode to o_mode instead of x_mode. + +2006-12-14 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (CMPXCHG8B_Fixup): New. + (grps): Use CMPXCHG8B_Fixup for cmpxchg8b. + +2006-12-11 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (Eq): Replaced by ... + (Mq): New. This. + (Ma): Defined with OP_M instead of OP_E. + (grps): Updated cmpxchg8b and vmptrst for Eq -> Mq. + (OP_M): Added bound, cmpxchg8b and vmptrst to bad modrm list. + +2006-12-11 Daniel Jacobowitz <dan@codesourcery.com> + + * po/Make-in (.po.gmo): Put gmo files in objdir. + +2006-12-09 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (X86_64_1): New. + (X86_64_2): Likewise. + (X86_64_3): Likewise. + (dis386): Replace 0x60, 0x61 and 0x62 entries with x86-64 + tables. + (x86_64_table): Add entries for 0x60, 0x61 and 0x62. + +2006-12-09 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c: Adjust white spaces. + +2006-12-04 Jan Beulich <jbeulich@novell.com> + + * i386-dis.c (OP_J): Update used_prefixes in v_mode. + +2006-11-30 Jan Beulich <jbeulich@novell.com> + + * i386-dis.c (SEG_Fixup): Delete. + (Sv): Use OP_SEG. + (putop): New suffix character 'D'. + (dis386): Use it. + (grps): Likewise. + (OP_SEG): Handle bytemode other than w_mode. + +2006-11-30 Jan Beulich <jbeulich@novell.com> + + * i386-dis.c (zAX): New. + (Xz): New. + (Yzr): New. + (z_mode): New. + (z_mode_ax_reg): New. + (putop): New suffix character 'G'. + (dis386): Use it for in, out, ins, and outs. + (intel_operand_size): Handle z_mode. + (OP_REG): Delete unreachable case indir_dx_reg. + (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle + z_mode_ax_reg. + (OP_ESreg): Fix Intel syntax operand size handling. + (OP_DSreg): Likewise. + +2006-11-30 Jan Beulich <jbeulich@novell.com> + + * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally. + (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix + used. For 'R' and 'W' suffix, simplify and fix Intel mode. + +2006-11-29 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd. + +2006-11-22 Daniel Jacobowitz <dan@codesourcery.com> + + * arm-dis.c (last_is_thumb): Delete. + (enum map_type, last_type): New. + (print_insn_data): New. + (get_sym_code_type): Take MAP_TYPE argument. Check the type of + the right symbol. Handle $d. + (print_insn): Check for mapping symbols even without a normal + symbol. Adjust searching. If $d is found see how much data + to print. Handle data. + +2006-11-16 Nathan Sidwell <nathan@codesourcery.com> + + * m68k-opc.c (m68k_opcodes): Place trap instructions before set + conditionals. Add tpf coldfire instruction as alias for trapf. + +2006-11-09 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (print_insn): Check PREFIX_REPNZ before + PREFIX_DATA when prefix user table is used. + +2006-11-09 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ... + (twobyte_uses_DATA_prefix): This. + (twobyte_uses_REPNZ_prefix): New. + (twobyte_uses_REPZ_prefix): Likewise. + (threebyte_0x38_uses_DATA_prefix): Likewise. + (threebyte_0x38_uses_REPNZ_prefix): Likewise. + (threebyte_0x38_uses_REPZ_prefix): Likewise. + (threebyte_0x3a_uses_DATA_prefix): Likewise. + (threebyte_0x3a_uses_REPNZ_prefix): Likewise. + (threebyte_0x3a_uses_REPZ_prefix): Likewise. + (print_insn): Updated checking usages of DATA/REPNZ/REPZ + prefixes. + +2006-11-06 Troy Rollo <troy@corvu.com.au> + + * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04. + +2006-11-01 Mei Ligang <ligang@sunnorth.com.cn> + + * score-opc.h (score_opcodes): Delete modifier '0x'. + +2006-10-30 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New. + (get_sym_code_type): New function. + (print_insn): Search for mapping symbols. + +2006-10-31 Mei Ligang <ligang@sunnorth.com.cn> + + * score-dis.c (print_insn): Correct the error code to print + correct PCE instruction disassembly. + +2006-10-26 Ben Elliston <bje@au.ibm.com> + Anton Blanchard <anton@samba.org> + Peter Bergner <bergner@vnet.ibm.com> + + * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH, + AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define. + (POWER6): Define. + (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.", + "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.". + Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd", + "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr", + "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix", + "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul", + "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.", + "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc", + "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix", + "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.", + "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.", + "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.", + "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.", + "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.", + "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq", + "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.", + "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.", + "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq", + "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.", + "diexq" and "diexq." opcodes. + +2006-10-26 Daniel Jacobowitz <dan@codesourcery.com> + + * h8300-dis.c (bfd_h8_disassemble): Add missing consts. + +2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> + Yukishige Shibata <shibata@rd.scei.sony.co.jp> + Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> + Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> + Alan Modra <amodra@bigpond.net.au> + + * spu-dis.c: New file. + * spu-opc.c: New file. + * configure.in: Add SPU support. + * disassemble.c: Likewise. + * Makefile.am: Likewise. Run "make dep-am". + * Makefile.in: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + +2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> + + * ppc-opc.c (CELL): New define. + (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx, + cell specific instructions. Add {st,l}x{r,l}{,l} cell specific + VMX instructions. + * ppc-dis.c (powerpc_dialect): Handle cell. + +2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + + * i386-dis.c (dis386): Add support for the change in POPCNT opcode in + amdfam10 architecture. + (PREGRP37): NEW. + (print_insn): Disallow REP prefix for POPCNT. + +2006-10-20 Andrew Stubbs <andrew.stubbs@st.com> + + * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB + duplicating it. + +2006-10-18 Dave Brolley <brolley@redhat.com> + + * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch. + * configure: Regenerated. + +2006-09-29 Alan Modra <amodra@bigpond.net.au> + + * po/POTFILES.in: Regenerate. + +2006-09-26 Mark Shinwell <shinwell@codesourcery.com> + Joseph Myers <joseph@codesourcery.com> + Ian Lance Taylor <ian@wasabisystems.com> + Ben Elliston <bje@wasabisystems.com> + + * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may + only be used with the default multiply-add operation, so if N is + set, don't bother printing X. Add new iwmmxt instructions. + (IWMMXT_INSN_COUNT): Update. + (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14 + with a 'c' suffix. + (print_insn_coprocessor): Check for iWMMXt2. Handle format + specifiers 'r', 'i'. + +2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + + PR binutils/3100 + * i386-dis.c (prefix_user_table): Fix the second operand of + maskmovdqu instruction to allow only %xmm register instead of + both %xmm register and memory. + +2006-09-23 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/3235 + * i386-dis.c (OP_OFF64): Get 32bit offset if there is an + address size prefix. + +2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> + + * score-dis.c: New file. + * score-opc.h: New file. + * Makefile.am: Add Score files. + * Makefile.in: Regenerate. + * configure.in: Add support for Score target. + * configure: Regenerate. + * disassemble.c: Add support for Score target. + +2006-09-16 Nick Clifton <nickc@redhat.com> + Pedro Alves <pedro_alves@portugalmail.pt> + + * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ + macros defined in bfd.h. + * cris-dis.c: Likewise. + * h8300-dis.c: Likewise. + * i386-dis.c: Likewise. + * ia64-gen.c: Likewise. + * mips-dis: Likewise. + +2006-09-04 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (neon_opcode): Fix suffix on VMOVN. + +2006-08-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (three_byte_table): Expand to 256 elements. + +2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + + PR binutils/3000 + * i386-dis.c (MXC,EMC): Define. + (OP_MXC): New function to handle cvt* (convert instructions) between + %xmm and %mm register correctly. + (OP_EMC): ditto. + (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi + instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately + with EMC/MXC. + +2006-07-29 Richard Sandiford <richard@codesourcery.com> + + * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire + "fdaddl" entry. + +2006-07-19 Paul Brook <paul@codesourcery.com> + + * armd-dis.c (arm_opcodes): Fix rbit opcode. + +2006-07-18 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to + "sldt", "str" and "smsw". + +2006-07-15 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/2829 + * i386-dis.c (GRP11_C6): NEW. + (GRP11_C7): Likewise. + (GRP12): Updated. + (GRP13): Likewise. + (GRP14): Likewise. + (GRP15): Likewise. + (GRP16): Likewise. + (GRPAMD): Likewise. + (GRPPADLCK1): Likewise. + (GRPPADLCK2): Likewise. + (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7, + respectively. + (grps): Add entries for GRP11_C6 and GRP11_C7. + +2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + Michael Meissner <michael.meissner@amd.com> + + * i386-dis.c (dis386): Add support for 4 operand instructions. Add + support for amdfam10 SSE4a/ABM instructions. Modify all + initializer macros to have additional arguments. Disallow REP + prefix for non-string instructions. + (print_insn): Ditto. + +2006-07-05 Julian Brown <julian@codesourcery.com> + + * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax. + +2006-06-12 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. + (twobyte_has_modrm): Set 1 for 0x1f. + +2006-06-12 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (NOP_Fixup): Removed. + (NOP_Fixup1): New. + (NOP_Fixup2): Likewise. + (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90. + +2006-06-12 Julian Brown <julian@codesourcery.com> + + * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed + on 64-bit hosts. + +2006-06-10 H.J. Lu <hongjiu.lu@intel.com> + + * i386.c (GRP10): Renamed to ... + (GRP12): This. + (GRP11): Renamed to ... + (GRP13): This. + (GRP12): Renamed to ... + (GRP14): This. + (GRP13): Renamed to ... + (GRP15): This. + (GRP14): Renamed to ... + (GRP16): This. + (dis386_twobyte): Updated. + (grps): Likewise. + +2006-06-09 Nick Clifton <nickc@redhat.com> + + * po/fi.po: Updated Finnish translation. + +2006-06-07 Joseph S. Myers <joseph@codesourcery.com> + + * po/Make-in (pdf, ps): New dummy targets. + +2006-06-06 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm + instructions. + (neon_opcodes): Add conditional execution specifiers. + (thumb_opcodes): Ditto. + (thumb32_opcodes): Ditto. + (arm_conditional): Change 0xe to "al" and add "" to end. + (ifthen_state, ifthen_next_state, ifthen_address): New. + (IFTHEN_COND): Define. + (print_insn_coprocessor, print_insn_neon): Print thumb conditions. + (print_insn_arm): Change %c to use new values of arm_conditional. + (print_insn_thumb16): Print thumb conditions. Add %I. + (print_insn_thumb32): Print thumb conditions. + (find_ifthen_state): New function. + (print_insn): Track IT block state. + +2006-06-06 Ben Elliston <bje@au.ibm.com> + Anton Blanchard <anton@samba.org> + Peter Bergner <bergner@vnet.ibm.com> + + * ppc-dis.c (powerpc_dialect): Handle power6 option. + (print_ppc_disassembler_options): Mention power6. + +2006-06-06 Thiemo Seufer <ths@mips.com> + Chao-ying Fu <fu@mips.com> + + * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. + * mips-opc.c: Add DSP64 instructions. + +2006-06-06 Alan Modra <amodra@bigpond.net.au> + + * m68hc11-dis.c (print_insn): Warning fix. + +2006-06-05 Daniel Jacobowitz <dan@codesourcery.com> + + * po/Make-in (top_builddir): Define. + +2006-06-05 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * config.in: Regenerate. + +2006-05-31 Daniel Jacobowitz <dan@codesourcery.com> + + * Makefile.am (INCLUDES): Use @INCINTL@. + * acinclude.m4: Include new gettext macros. + * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS. + Remove local code for po/Makefile. + * Makefile.in, aclocal.m4, configure: Regenerated. + +2006-05-30 Nick Clifton <nickc@redhat.com> + + * po/es.po: Updated Spanish translation. + +2006-05-25 Richard Sandiford <richard@codesourcery.com> + + * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd + and fmovem entries. Put register list entries before immediate + mask entries. Use "l" rather than "L" in the fmovem entries. + * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it + out from INFO. + (m68k_scan_mask): New function, split out from... + (print_insn_m68k): ...here. If no architecture has been set, + first try printing an m680x0 instruction, then try a Coldfire one. + +2006-05-24 Nick Clifton <nickc@redhat.com> + + * po/ga.po: Updated Irish translation. + +2006-05-22 Nick Clifton <nickc@redhat.com> + + * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts. + +2006-05-22 Nick Clifton <nickc@redhat.com> + + * po/nl.po: Updated translation. + +2006-05-18 Alan Modra <amodra@bigpond.net.au> + + * avr-dis.c: Formatting fix. + +2006-05-14 Thiemo Seufer <ths@mips.com> + + * mips16-opc.c (I1, I32, I64): New shortcut defines. + (mips16_opcodes): Change membership of instructions to their + lowest baseline ISA. + +2006-05-09 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (grps): Update sgdt/sidt for 64bit. + +2006-05-05 Julian Brown <julian@codesourcery.com> + + * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as + vldm/vstm. + +2006-05-05 Thiemo Seufer <ths@mips.com> + David Ung <davidu@mips.com> + + * mips-opc.c: Add macro for cache instruction. + +2006-05-04 Thiemo Seufer <ths@mips.com> + Nigel Stephens <nigel@mips.com> + David Ung <davidu@mips.com> + + * mips-dis.c (mips_arch_choices): Add smartmips instruction + decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release + 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to + MIPS64R2. + * mips-opc.c: fix random typos in comments. + (INSN_SMARTMIPS): New defines. + (mips_builtin_opcodes): Add paired single support for MIPS32R2. + Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, + flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the + FP_S and FP_D flags to denote single and double register + accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. + Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 + for MIPS32R2. Add SmartMIPS instructions. Add two-argument + variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to + release 2 ISAs. + * mips16-opc.c (mips16_opcodes): Add sdbbp instruction. + +2006-05-03 Thiemo Seufer <ths@mips.com> + + * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order. + +2006-05-02 Thiemo Seufer <ths@mips.com> + Nigel Stephens <nigel@mips.com> + David Ung <davidu@mips.com> + + * mips-dis.c (print_insn_args): Force mips16 to odd addresses. + (print_mips16_insn_arg): Force mips16 to odd addresses. + +2006-04-30 Thiemo Seufer <ths@mips.com> + David Ung <davidu@mips.com> + + * mips-opc.c (mips_builtin_opcodes): Add udi instructions + "udi0" to "udi15". + * mips-dis.c (print_insn_args): Adds udi argument handling. + +2006-04-28 James E Wilson <wilson@specifix.com> + + * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing + error message. + +2006-04-28 Thiemo Seufer <ths@mips.com> + David Ung <davidu@mips.com> + Nigel Stephens <nigel@mips.com> + + * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register + names. + +2006-04-28 Thiemo Seufer <ths@mips.com> + Nigel Stephens <nigel@mips.com> + David Ung <davidu@mips.com> + + * mips-dis.c (print_insn_args): Add mips_opcode argument. + (print_insn_mips): Adjust print_insn_args call. + +2006-04-28 Thiemo Seufer <ths@mips.com> + Nigel Stephens <nigel@mips.com> + + * mips-dis.c (print_insn_args): Print $fcc only for FP + instructions, use $cc elsewise. + +2006-04-28 Thiemo Seufer <ths@mips.com> + Nigel Stephens <nigel@mips.com> + + * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): + Map MIPS16 registers to O32 names. + (print_mips16_insn_arg): Use mips16_reg_names. + +2006-04-26 Julian Brown <julian@codesourcery.com> + + * arm-dis.c (print_insn_neon): Disassemble floating-point constant + VMOV. + +2006-04-26 Nathan Sidwell <nathan@codesourcery.com> + Julian Brown <julian@codesourcery.com> + + * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert + %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?]. + Add unified load/store instruction names. + (neon_opcode_table): New. + (arm_opcodes): Expand meaning of %<bitfield>['`?]. + (arm_decode_bitfield): New. + (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers. + Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y. + (print_insn_neon): New. + (print_insn_arm): Adjust print_insn_coprocessor call. Call + print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers. + (print_insn_thumb32): Likewise. + +2006-04-19 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2006-04-19 Alan Modra <amodra@bigpond.net.au> + + * avr-dis.c (avr_operand): Warning fix. + + * configure: Regenerate. + +2006-04-16 Daniel Jacobowitz <dan@codesourcery.com> + + * po/POTFILES.in: Regenerated. + +2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de> + + PR binutils/2454 + * avr-dis.c (avr_operand): Arrange for a comment to appear before + the symolic form of an address, so that the output of objdump -d + can be reassembled. + +2006-04-10 DJ Delorie <dj@redhat.com> + + * m32c-asm.c: Regenerate. + +2006-04-06 Carlos O'Donell <carlos@codesourcery.com> + + * Makefile.am: Add install-html target. + * Makefile.in: Regenerate. + +2006-04-06 Nick Clifton <nickc@redhat.com> + + * po/vi/po: Updated Vietnamese translation. + +2006-03-31 Paul Koning <ni1d@arrl.net> + + * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction. + +2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com> + + * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the + logic to identify halfword shifts. + +2006-03-16 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (arm_opcodes): Rename swi to svc. + (thumb_opcodes): Ditto. + +2006-03-13 DJ Delorie <dj@redhat.com> + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Likewise. + * m32c-desc.h: Likewise. + * m32c-dis.c: Likewise. + * m32c-ibld.c: Likewise. + * m32c-opc.c: Likewise. + * m32c-opc.h: Likewise. + +2006-03-10 DJ Delorie <dj@redhat.com> + + * m32c-desc.c: Regenerate with mul.l, mulu.l. + * m32c-opc.c: Likewise. + * m32c-opc.h: Likewise. + + +2006-03-09 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + +2006-03-07 H.J. Lu <hongjiu.lu@intel.com> + + PR binutils/2428 + * i386-dis.c (REP_Fixup): New function. + (AL): Remove duplicate. + (Xbr): New. + (Xvr): Likewise. + (Ybr): Likewise. + (Yvr): Likewise. + (indirDXr): Likewise. + (ALr): Likewise. + (eAXr): Likewise. + (dis386): Updated entries of ins, outs, movs, lods and stos. + +2006-03-05 Nick Clifton <nickc@redhat.com> + + * cgen-ibld.in (insert_normal): Cope with attempts to insert a + signed 32-bit value into an unsigned 32-bit field when the host is + a 64-bit machine. + * fr30-ibld.c: Regenerate. + * frv-ibld.c: Regenerate. + * ip2k-ibld.c: Regenerate. + * iq2000-asm.c: Regenerate. + * iq2000-ibld.c: Regenerate. + * m32c-ibld.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * xc16x-ibld.c: Regenerate. + * xstormy16-ibld.c: Regenerate. + +2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com) + + * xc16x-asm.c: Regenerate. + * xc16x-dis.c: Regenerate. + +2006-02-27 Carlos O'Donell <carlos@codesourcery.com> + + * po/Make-in: Add html target. + +2006-02-27 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by + Intel Merom New Instructions. + (THREE_BYTE_0): Likewise. + (THREE_BYTE_1): Likewise. + (three_byte_table): Likewise. + (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use + THREE_BYTE_1 for entry 0x3a. + (twobyte_has_modrm): Updated. + (twobyte_uses_SSE_prefix): Likewise. + (print_insn): Handle 3-byte opcodes used by Intel Merom New + Instructions. + +2006-02-24 David S. Miller <davem@sunset.davemloft.net> + + * sparc-dis.c (v9_priv_reg_names): Add "gl" entry. + (v9_hpriv_reg_names): New table. + (print_insn_sparc): Allow values up to 16 for '?' and '!'. + New cases '$' and '%' for read/write hyperprivileged register. + * sparc-opc.c (sparc_opcodes): Add new entries for UA2005 + window handling and rdhpr/wrhpr instructions. + +2006-02-24 DJ Delorie <dj@redhat.com> + + * m32c-desc.c: Regenerate with linker relaxation attributes. + * m32c-desc.h: Likewise. + * m32c-dis.c: Likewise. + * m32c-opc.c: Likewise. + +2006-02-24 Paul Brook <paul@codesourcery.com> + + * arm-dis.c (arm_opcodes): Add V7 instructions. + (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. + (print_arm_address): New function. + (print_insn_arm): Use it. Add 'P' and 'U' cases. + (psr_name): New function. + (print_insn_thumb32): Add 'U', 'C' and 'D' cases. + +2006-02-23 H.J. Lu <hongjiu.lu@intel.com> + + * ia64-opc-i.c (bXc): New. + (mXc): Likewise. + (OpX2TaTbYaXcC): Likewise. + (TF). Likewise. + (TFCM). Likewise. + (ia64_opcodes_i): Add instructions for tf. + + * ia64-opc.h (IMMU5b): New. + + * ia64-asmtab.c: Regenerated. + +2006-02-23 H.J. Lu <hongjiu.lu@intel.com> + + * ia64-gen.c: Update copyright years. + * ia64-opc-b.c: Likewise. + +2006-02-22 H.J. Lu <hongjiu.lu@intel.com> + + * ia64-gen.c (lookup_regindex): Handle ".vm". + (print_dependency_table): Handle '\"'. + + * ia64-ic.tbl: Updated from SDM 2.2. + * ia64-raw.tbl: Likewise. + * ia64-waw.tbl: Likewise. + * ia64-asmtab.c: Regenerated. + + * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1. + +2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com> + Anil Paranjape <anilp1@kpitcummins.com> + Shilin Shakti <shilins@kpitcummins.com> + + * xc16x-desc.h: New file + * xc16x-desc.c: New file + * xc16x-opc.h: New file + * xc16x-opc.c: New file + * xc16x-ibld.c: New file + * xc16x-asm.c: New file + * xc16x-dis.c: New file + * Makefile.am: Entries for xc16x + * Makefile.in: Regenerate + * cofigure.in: Add xc16x target information. + * configure: Regenerate. + * disassemble.c: Add xc16x target information. + +2006-02-11 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (dis386_twobyte): Use "movZ" for debug register + moves. + +2006-02-11 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c ('Z'): Add a new macro. + (dis386_twobyte): Use "movZ" for control register moves. + +2006-02-10 Nick Clifton <nickc@redhat.com> + + * iq2000-asm.c: Regenerate. + +2006-02-07 Nathan Sidwell <nathan@codesourcery.com> + + * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features. + +2006-01-26 David Ung <davidu@mips.com> + + * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx, + ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d, + floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d, + nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d, + rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s. + +2006-01-18 Arnold Metselaar <arnoldm@sourceware.org> + + * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d, + ld_d_r, pref_xd_cb): Use signed char to hold data to be + disassembled. + * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes + buffer overflows when disassembling instructions like + ld (ix+123),0x23 + * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed + operand, if the offset is negative. + +2006-01-17 Arnold Metselaar <arnoldm@sourceware.org> + + * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use + unsigned char to hold data to be disassembled. + +2006-01-17 Andreas Schwab <schwab@suse.de> + + PR binutils/1486 + * disassemble.c (disassemble_init_for_target): Set + disassembler_needs_relocs for bfd_arch_arm. + +2006-01-16 Paul Brook <paul@codesourcery.com> + + * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss, + f?add?, and f?sub? instructions. + +2006-01-16 Nick Clifton <nickc@redhat.com> + + * po/zh_CN.po: New Chinese (simplified) translation. + * configure.in (ALL_LINGUAS): Add "zh_CH". + * configure: Regenerate. + +2006-01-05 Paul Brook <paul@codesourcery.com> + + * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry. + +2006-01-06 DJ Delorie <dj@redhat.com> + + * m32c-desc.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2006-01-03 DJ Delorie <dj@redhat.com> + + * cgen-ibld.in (extract_normal): Avoid memory range errors. + * m32c-ibld.c: Regenerated. + +For older changes see ChangeLog-2005 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/contrib/binutils/opcodes/Makefile.am b/contrib/binutils/opcodes/Makefile.am index 57bdb4a..99a2b76 100644 --- a/contrib/binutils/opcodes/Makefile.am +++ b/contrib/binutils/opcodes/Makefile.am @@ -1,6 +1,7 @@ ## Process this file with automake to generate Makefile.in AUTOMAKE_OPTIONS = 1.9 cygnus +ACLOCAL_AMFLAGS = -I .. -I ../config -I ../bfd SUBDIRS = po @@ -32,6 +33,8 @@ HFILES = \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ h8500-opc.h \ + i386-opc.h \ + i386-tbl.h \ ia64-asmtab.h \ ia64-opc.h \ ip2k-desc.h ip2k-opc.h \ @@ -39,8 +42,10 @@ HFILES = \ m32c-desc.h m32c-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ + mep-desc.h mep-opc.h \ mt-desc.h mt-opc.h \ openrisc-desc.h openrisc-opc.h \ + score-opc.h \ sh-opc.h \ sh64-opc.h \ sysdep.h \ @@ -63,6 +68,8 @@ CFILES = \ cgen-bitset.c \ cgen-dis.c \ cgen-opc.c \ + cr16-dis.c \ + cr16-opc.c \ cris-dis.c \ cris-opc.c \ crx-dis.c \ @@ -91,6 +98,8 @@ CFILES = \ i370-dis.c \ i370-opc.c \ i386-dis.c \ + i386-opc.c \ + i386-gen.c \ i860-dis.c \ i960-dis.c \ ia64-dis.c \ @@ -131,6 +140,11 @@ CFILES = \ m88k-dis.c \ maxq-dis.c \ mcore-dis.c \ + mep-asm.c \ + mep-desc.c \ + mep-dis.c \ + mep-ibld.c \ + mep-opc.c \ mips-dis.c \ mips-opc.c \ mips16-opc.c \ @@ -162,11 +176,14 @@ CFILES = \ s390-mkopc.c \ s390-opc.c \ s390-dis.c \ + score-dis.c \ sh-dis.c \ sh64-dis.c \ sh64-opc.c \ sparc-dis.c \ sparc-opc.c \ + spu-dis.c \ + spu-opc.c \ tic30-dis.c \ tic4x-dis.c \ tic54x-dis.c \ @@ -205,6 +222,8 @@ ALL_MACHINES = \ cgen-bitset.lo \ cgen-dis.lo \ cgen-opc.lo \ + cr16-dis.lo \ + cr16-opc.lo \ cris-dis.lo \ cris-opc.lo \ crx-dis.lo \ @@ -228,6 +247,7 @@ ALL_MACHINES = \ h8500-dis.lo \ hppa-dis.lo \ i386-dis.lo \ + i386-opc.lo \ i370-dis.lo \ i370-opc.lo \ i860-dis.lo \ @@ -266,6 +286,11 @@ ALL_MACHINES = \ m10300-opc.lo \ maxq-dis.lo \ mcore-dis.lo \ + mep-asm.lo \ + mep-desc.lo \ + mep-dis.lo \ + mep-ibld.lo \ + mep-opc.lo \ mips-dis.lo \ mips-opc.lo \ mips16-opc.lo \ @@ -293,11 +318,14 @@ ALL_MACHINES = \ ppc-opc.lo \ s390-dis.lo \ s390-opc.lo \ + score-dis.lo \ sh-dis.lo \ sh64-dis.lo \ sh64-opc.lo \ sparc-dis.lo \ sparc-opc.lo \ + spu-dis.lo \ + spu-opc.lo \ tic30-dis.lo \ tic4x-dis.lo \ tic54x-dis.lo \ @@ -328,7 +356,7 @@ OFILES = @BFD_MACHINES@ # that's where the version number in Makefile comes from. CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in -INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ -I$(srcdir)/../intl -I../intl +INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ @INCINTL@ disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c @@ -341,7 +369,7 @@ libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c # if host != build. libopcodes_la_DEPENDENCIES = $(OFILES) libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ -libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ +libopcodes_la_LDFLAGS = -release `cat ../bfd/libtool-soversion` @WIN32LDFLAGS@ # libtool will build .libs/libopcodes.a. We create libopcodes.a in # the build directory so that we don't have to convert all the @@ -392,7 +420,7 @@ uninstall_libopcodes: CLEANFILES = \ stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ - stamp-openrisc stamp-iq2000 stamp-mt stamp-xstormy16 stamp-xc16x\ + stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -408,7 +436,7 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xc16x xstormy16 +CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16 if CGEN_MAINT IP2K_DEPS = stamp-ip2k @@ -416,6 +444,7 @@ M32C_DEPS = stamp-m32c M32R_DEPS = stamp-m32r FR30_DEPS = stamp-fr30 FRV_DEPS = stamp-frv +MEP_DEPS = stamp-mep MT_DEPS = stamp-mt OPENRISC_DEPS = stamp-openrisc IQ2000_DEPS = stamp-iq2000 @@ -427,6 +456,7 @@ M32C_DEPS = M32R_DEPS = FR30_DEPS = FRV_DEPS = +MEP_DEPS = MT_DEPS = OPENRISC_DEPS = IQ2000_DEPS = @@ -500,6 +530,12 @@ stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc $(MAKE) run-cgen arch=frv prefix=frv options= \ archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= +$(srcdir)/mep-desc.h $(srcdir)/mep-desc.c $(srcdir)/mep-opc.h $(srcdir)/mep-opc.c $(srcdir)/mep-ibld.c $(srcdir)/mep-asm.c $(srcdir)/mep-dis.c: $(MEP_DEPS) + @true +stamp-mep: $(CGENDEPS) $(CPUDIR)/mep.cpu $(CPUDIR)/mep-default.cpu $(CPUDIR)/mep-core.cpu $(CPUDIR)/mep-h1.cpu $(CPUDIR)/mep-ext-cop.cpu $(CPUDIR)/mep-sample-ucidsp.cpu $(CPUDIR)/mep-rhcop.cpu $(CPUDIR)/mep-fmax.cpu $(CPUDIR)/mep.opc + $(MAKE) run-cgen arch=mep prefix=mep options= \ + archfile=$(CPUDIR)/mep.cpu opcfile=$(CPUDIR)/mep.opc extrafiles= + $(srcdir)/mt-desc.h $(srcdir)/mt-desc.c $(srcdir)/mt-opc.h $(srcdir)/mt-opc.c $(srcdir)/mt-ibld.c $(srcdir)/mt-asm.c $(srcdir)/mt-dis.c: $(MT_DEPS) @true stamp-mt: $(CGENDEPS) $(srcdir)/../cpu/mt.cpu $(srcdir)/../cpu/mt.opc @@ -534,6 +570,14 @@ stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc $(MAKE) run-cgen arch=xc16x prefix=xc16x options= \ archfile=$(CPUDIR)/xc16x.cpu opcfile=$(CPUDIR)/xc16x.opc extrafiles= +i386-gen: i386-gen.o + $(LINK) i386-gen.o $(LIBIBERTY) + +i386-gen.o: i386-gen.c i386-opc.h + +i386-tbl.h: @MAINT@ i386-gen i386-opc.tbl i386-reg.tbl + ./i386-gen --srcdir $(srcdir) > $(srcdir)/i386-tbl.h + ia64-gen: ia64-gen.o $(LINK) ia64-gen.o $(LIBIBERTY) @@ -601,131 +645,176 @@ dep-am: DEP # DO NOT DELETE THIS LINE -- mkdep uses it. # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/alpha.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/alpha.h alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \ - opintl.h + $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h opintl.h arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ - $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ - $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \ - $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \ + opintl.h arc-dis.h arc-ext.h arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ opintl.h arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \ + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arm.h \ - opintl.h $(INCDIR)/safe-ctype.h $(INCDIR)/coff/internal.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \ + $(INCDIR)/floatformat.h $(INCDIR)/ansidecl.h $(INCDIR)/coff/internal.h \ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(BFDDIR)/elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h + $(INCDIR)/elf/internal.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ - $(INCDIR)/libiberty.h $(INCDIR)/opcode/avr.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/avr.h bfin-dis.lo: bfin-dis.c $(INCDIR)/opcode/bfin.h $(INCDIR)/dis-asm.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \ + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \ opintl.h cgen-bitset.lo: cgen-bitset.c $(INCDIR)/libiberty.h \ $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cgen-bitset.h cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/opcode/cgen-bitset.h + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h +cr16-dis.lo: cr16-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cr16.h $(INCDIR)/libiberty.h \ + $(INCDIR)/ansidecl.h +cr16-opc.lo: cr16-opc.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cr16.h cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ - 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$(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h $(INCDIR)/symcat.h xstormy16-desc.h \ $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ - xstormy16-opc.h $(INCDIR)/libiberty.h -xc16x-asm.lo: xc16x-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen.h \ - xc16x-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ - $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h -xc16x-desc.lo: xc16x-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen.h \ - xc16x-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ - $(INCDIR)/xregex2.h -xc16x-dis.lo: xc16x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ - xc16x-desc.h $(INCDIR)/opcode/cgen.h xc16x-opc.h opintl.h -xc16x-ibld.lo: xc16x-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h \ - $(INCDIR)/opcode/cgen.h xc16x-opc.h opintl.h $(INCDIR)/safe-ctype.h -xc16x-opc.lo: xc16x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen.h \ - xc16x-opc.h $(INCDIR)/libiberty.h + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h xstormy16-opc.h \ + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h xtensa-dis.lo: xtensa-dis.c $(INCDIR)/xtensa-isa.h \ - $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h sysdep.h \ - config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h + $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + sysdep.h config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h z80-dis.lo: z80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h z8k-opc.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + z8k-opc.h z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h # IF YOU PUT ANYTHING HERE IT WILL GO AWAY diff --git a/contrib/binutils/opcodes/Makefile.in b/contrib/binutils/opcodes/Makefile.in index 78faab9..29252e9 100644 --- a/contrib/binutils/opcodes/Makefile.in +++ b/contrib/binutils/opcodes/Makefile.in @@ -1,4 +1,4 @@ -# Makefile.in generated by automake 1.9.5 from Makefile.am. +# Makefile.in generated by automake 1.9.6 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, @@ -15,8 +15,6 @@ @SET_MAKE@ -SOURCES = libopcodes.c $(libopcodes_la_SOURCES) - srcdir = @srcdir@ top_srcdir = @top_srcdir@ VPATH = @srcdir@ @@ -48,11 +46,16 @@ DIST_COMMON = $(srcdir)/../config.guess $(srcdir)/../config.sub \ $(srcdir)/../config.guess $(srcdir)/../config.sub subdir = . ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 -am__aclocal_m4_deps = $(top_srcdir)/acinclude.m4 \ - $(top_srcdir)/../bfd/acinclude.m4 \ - $(top_srcdir)/../config/acx.m4 $(top_srcdir)/../bfd/bfd.m4 \ - $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../libtool.m4 \ - $(top_srcdir)/../gettext.m4 $(top_srcdir)/configure.in +am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \ + $(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../config/acx.m4 \ + $(top_srcdir)/../config/depstand.m4 \ + $(top_srcdir)/../config/gettext-sister.m4 \ + $(top_srcdir)/../config/lead-dot.m4 \ + $(top_srcdir)/../config/nls.m4 $(top_srcdir)/../config/po.m4 \ + $(top_srcdir)/../config/progtest.m4 \ + $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \ + $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \ + $(top_srcdir)/configure.in am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \ @@ -83,11 +86,11 @@ depcomp = am__depfiles_maybe = COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -LTCOMPILE = $(LIBTOOL) --mode=compile $(CC) $(DEFS) \ +LTCOMPILE = $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) \ $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \ $(AM_CFLAGS) $(CFLAGS) CCLD = $(CC) -LINK = $(LIBTOOL) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ +LINK = $(LIBTOOL) --tag=CC --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(AM_LDFLAGS) $(LDFLAGS) -o $@ SOURCES = libopcodes.c $(libopcodes_la_SOURCES) RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \ @@ -100,7 +103,6 @@ ETAGS = etags CTAGS = ctags DIST_SUBDIRS = $(SUBDIRS) ACLOCAL = @ACLOCAL@ -ALLOCA = @ALLOCA@ AMDEP_FALSE = @AMDEP_FALSE@ AMDEP_TRUE = @AMDEP_TRUE@ AMTAR = @AMTAR@ @@ -124,18 +126,19 @@ CYGPATH_W = @CYGPATH_W@ DATADIRNAME = @DATADIRNAME@ DEFS = @DEFS@ DEPDIR = @DEPDIR@ +DUMPBIN = @DUMPBIN@ ECHO_C = @ECHO_C@ ECHO_N = @ECHO_N@ ECHO_T = @ECHO_T@ EGREP = @EGREP@ EXEEXT = @EXEEXT@ EXEEXT_FOR_BUILD = @EXEEXT_FOR_BUILD@ -GMOFILES = @GMOFILES@ +FGREP = @FGREP@ +GENCAT = @GENCAT@ GMSGFMT = @GMSGFMT@ -GT_NO = @GT_NO@ -GT_YES = @GT_YES@ +GREP = @GREP@ HDEFINES = @HDEFINES@ -INCLUDE_LOCALE_H = @INCLUDE_LOCALE_H@ +INCINTL = @INCINTL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_LIBBFD_FALSE = @INSTALL_LIBBFD_FALSE@ INSTALL_LIBBFD_TRUE = @INSTALL_LIBBFD_TRUE@ @@ -143,10 +146,10 @@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_SCRIPT = @INSTALL_SCRIPT@ INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ INSTOBJEXT = @INSTOBJEXT@ -INTLDEPS = @INTLDEPS@ -INTLLIBS = @INTLLIBS@ -INTLOBJS = @INTLOBJS@ +LD = @LD@ LDFLAGS = @LDFLAGS@ +LIBINTL = @LIBINTL@ +LIBINTL_DEP = @LIBINTL_DEP@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ @@ -158,6 +161,8 @@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ MKINSTALLDIRS = @MKINSTALLDIRS@ MSGFMT = @MSGFMT@ +MSGMERGE = @MSGMERGE@ +NM = @NM@ NO_WERROR = @NO_WERROR@ OBJEXT = @OBJEXT@ PACKAGE = @PACKAGE@ @@ -167,13 +172,12 @@ PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ -POFILES = @POFILES@ POSUB = @POSUB@ RANLIB = @RANLIB@ +SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ -USE_INCLUDED_LIBINTL = @USE_INCLUDED_LIBINTL@ USE_NLS = @USE_NLS@ VERSION = @VERSION@ WARN_CFLAGS = @WARN_CFLAGS@ @@ -182,6 +186,7 @@ WIN32LIBADD = @WIN32LIBADD@ XGETTEXT = @XGETTEXT@ ac_ct_AR = @ac_ct_AR@ ac_ct_CC = @ac_ct_CC@ +ac_ct_DUMPBIN = @ac_ct_DUMPBIN@ ac_ct_RANLIB = @ac_ct_RANLIB@ ac_ct_STRIP = @ac_ct_STRIP@ am__fastdepCC_FALSE = @am__fastdepCC_FALSE@ @@ -212,10 +217,10 @@ host_vendor = @host_vendor@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ -l = @l@ libdir = @libdir@ libexecdir = @libexecdir@ localstatedir = @localstatedir@ +lt_ECHO = @lt_ECHO@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ @@ -231,6 +236,7 @@ target_noncanonical = @target_noncanonical@ target_os = @target_os@ target_vendor = @target_vendor@ AUTOMAKE_OPTIONS = 1.9 cygnus +ACLOCAL_AMFLAGS = -I .. -I ../config -I ../bfd SUBDIRS = po INCDIR = $(srcdir)/../include BFDDIR = $(srcdir)/../bfd @@ -250,6 +256,8 @@ HFILES = \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ h8500-opc.h \ + i386-opc.h \ + i386-tbl.h \ ia64-asmtab.h \ ia64-opc.h \ ip2k-desc.h ip2k-opc.h \ @@ -257,8 +265,10 @@ HFILES = \ m32c-desc.h m32c-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ + mep-desc.h mep-opc.h \ mt-desc.h mt-opc.h \ openrisc-desc.h openrisc-opc.h \ + score-opc.h \ sh-opc.h \ sh64-opc.h \ sysdep.h \ @@ -282,6 +292,8 @@ CFILES = \ cgen-bitset.c \ cgen-dis.c \ cgen-opc.c \ + cr16-dis.c \ + cr16-opc.c \ cris-dis.c \ cris-opc.c \ crx-dis.c \ @@ -310,6 +322,8 @@ CFILES = \ i370-dis.c \ i370-opc.c \ i386-dis.c \ + i386-opc.c \ + i386-gen.c \ i860-dis.c \ i960-dis.c \ ia64-dis.c \ @@ -350,6 +364,11 @@ CFILES = \ m88k-dis.c \ maxq-dis.c \ mcore-dis.c \ + mep-asm.c \ + mep-desc.c \ + mep-dis.c \ + mep-ibld.c \ + mep-opc.c \ mips-dis.c \ mips-opc.c \ mips16-opc.c \ @@ -381,11 +400,14 @@ CFILES = \ s390-mkopc.c \ s390-opc.c \ s390-dis.c \ + score-dis.c \ sh-dis.c \ sh64-dis.c \ sh64-opc.c \ sparc-dis.c \ sparc-opc.c \ + spu-dis.c \ + spu-opc.c \ tic30-dis.c \ tic4x-dis.c \ tic54x-dis.c \ @@ -424,6 +446,8 @@ ALL_MACHINES = \ cgen-bitset.lo \ cgen-dis.lo \ cgen-opc.lo \ + cr16-dis.lo \ + cr16-opc.lo \ cris-dis.lo \ cris-opc.lo \ crx-dis.lo \ @@ -447,6 +471,7 @@ ALL_MACHINES = \ h8500-dis.lo \ hppa-dis.lo \ i386-dis.lo \ + i386-opc.lo \ i370-dis.lo \ i370-opc.lo \ i860-dis.lo \ @@ -485,6 +510,11 @@ ALL_MACHINES = \ m10300-opc.lo \ maxq-dis.lo \ mcore-dis.lo \ + mep-asm.lo \ + mep-desc.lo \ + mep-dis.lo \ + mep-ibld.lo \ + mep-opc.lo \ mips-dis.lo \ mips-opc.lo \ mips16-opc.lo \ @@ -512,11 +542,14 @@ ALL_MACHINES = \ ppc-opc.lo \ s390-dis.lo \ s390-opc.lo \ + score-dis.lo \ sh-dis.lo \ sh64-dis.lo \ sh64-opc.lo \ sparc-dis.lo \ sparc-opc.lo \ + spu-dis.lo \ + spu-opc.lo \ tic30-dis.lo \ tic4x-dis.lo \ tic54x-dis.lo \ @@ -546,7 +579,7 @@ OFILES = @BFD_MACHINES@ # We should reconfigure whenever bfd/configure.in changes, because # that's where the version number in Makefile comes from. CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in -INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ -I$(srcdir)/../intl -I../intl +INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ @INCINTL@ libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c # It's desirable to list ../bfd/libbfd.la in DEPENDENCIES and LIBADD. # Unfortunately this causes libtool to add -L$(libdir), referring to the @@ -555,7 +588,7 @@ libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c # if host != build. libopcodes_la_DEPENDENCIES = $(OFILES) libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ -libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ +libopcodes_la_LDFLAGS = -release `cat ../bfd/libtool-soversion` @WIN32LDFLAGS@ # libtool will build .libs/libopcodes.a. We create libopcodes.a in # the build directory so that we don't have to convert all the @@ -565,7 +598,7 @@ noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ - stamp-openrisc stamp-iq2000 stamp-mt stamp-xstormy16 stamp-xc16x\ + stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 CGENDIR = @cgendir@ @@ -579,7 +612,7 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xc16x xstormy16 +CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16 @CGEN_MAINT_FALSE@IP2K_DEPS = @CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k @CGEN_MAINT_FALSE@M32C_DEPS = @@ -590,6 +623,8 @@ CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xc16x xstormy16 @CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30 @CGEN_MAINT_FALSE@FRV_DEPS = @CGEN_MAINT_TRUE@FRV_DEPS = stamp-frv +@CGEN_MAINT_FALSE@MEP_DEPS = +@CGEN_MAINT_TRUE@MEP_DEPS = stamp-mep @CGEN_MAINT_FALSE@MT_DEPS = @CGEN_MAINT_TRUE@MT_DEPS = stamp-mt @CGEN_MAINT_FALSE@OPENRISC_DEPS = @@ -1042,6 +1077,12 @@ stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc $(MAKE) run-cgen arch=frv prefix=frv options= \ archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= +$(srcdir)/mep-desc.h $(srcdir)/mep-desc.c $(srcdir)/mep-opc.h $(srcdir)/mep-opc.c $(srcdir)/mep-ibld.c $(srcdir)/mep-asm.c $(srcdir)/mep-dis.c: $(MEP_DEPS) + @true +stamp-mep: $(CGENDEPS) $(CPUDIR)/mep.cpu $(CPUDIR)/mep-default.cpu $(CPUDIR)/mep-core.cpu $(CPUDIR)/mep-h1.cpu $(CPUDIR)/mep-ext-cop.cpu $(CPUDIR)/mep-sample-ucidsp.cpu $(CPUDIR)/mep-rhcop.cpu $(CPUDIR)/mep-fmax.cpu $(CPUDIR)/mep.opc + $(MAKE) run-cgen arch=mep prefix=mep options= \ + archfile=$(CPUDIR)/mep.cpu opcfile=$(CPUDIR)/mep.opc extrafiles= + $(srcdir)/mt-desc.h $(srcdir)/mt-desc.c $(srcdir)/mt-opc.h $(srcdir)/mt-opc.c $(srcdir)/mt-ibld.c $(srcdir)/mt-asm.c $(srcdir)/mt-dis.c: $(MT_DEPS) @true stamp-mt: $(CGENDEPS) $(srcdir)/../cpu/mt.cpu $(srcdir)/../cpu/mt.opc @@ -1076,6 +1117,14 @@ stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc $(MAKE) run-cgen arch=xc16x prefix=xc16x options= \ archfile=$(CPUDIR)/xc16x.cpu opcfile=$(CPUDIR)/xc16x.opc extrafiles= +i386-gen: i386-gen.o + $(LINK) i386-gen.o $(LIBIBERTY) + +i386-gen.o: i386-gen.c i386-opc.h + +i386-tbl.h: @MAINT@ i386-gen i386-opc.tbl i386-reg.tbl + ./i386-gen --srcdir $(srcdir) > $(srcdir)/i386-tbl.h + ia64-gen: ia64-gen.o $(LINK) ia64-gen.o $(LIBIBERTY) @@ -1143,131 +1192,176 @@ dep-am: DEP # DO NOT DELETE THIS LINE -- mkdep uses it. # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/alpha.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/alpha.h alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \ - opintl.h + $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h opintl.h arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ - $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ - $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \ - $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \ + opintl.h arc-dis.h arc-ext.h arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ opintl.h arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \ + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arm.h \ - opintl.h $(INCDIR)/safe-ctype.h $(INCDIR)/coff/internal.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \ + $(INCDIR)/floatformat.h $(INCDIR)/ansidecl.h $(INCDIR)/coff/internal.h \ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(BFDDIR)/elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h + $(INCDIR)/elf/internal.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ - $(INCDIR)/libiberty.h $(INCDIR)/opcode/avr.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/avr.h bfin-dis.lo: bfin-dis.c $(INCDIR)/opcode/bfin.h $(INCDIR)/dis-asm.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \ + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \ opintl.h cgen-bitset.lo: cgen-bitset.c $(INCDIR)/libiberty.h \ $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cgen-bitset.h cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h \ - $(INCDIR)/opcode/cgen-bitset.h + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h +cr16-dis.lo: cr16-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cr16.h $(INCDIR)/libiberty.h \ + $(INCDIR)/ansidecl.h +cr16-opc.lo: cr16-opc.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cr16.h cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ - $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h + $(INCDIR)/ansidecl.h $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h \ + $(INCDIR)/ansidecl.h cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h crx-dis.lo: crx-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ - $(INCDIR)/opcode/crx.h + $(INCDIR)/ansidecl.h $(INCDIR)/opcode/crx.h crx-opc.lo: crx-opc.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h $(INCDIR)/opcode/crx.h d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/symcat.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d10v.h d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/symcat.h opintl.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h opintl.h d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d30v.h dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/dlx.h dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + opintl.h dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(BFD_H) disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \ - $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/xregex.h \ - $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h fr30-opc.h \ + opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - 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$(INCDIR)/libiberty.h + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h # IF YOU PUT ANYTHING HERE IT WILL GO AWAY # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. diff --git a/contrib/binutils/opcodes/acinclude.m4 b/contrib/binutils/opcodes/acinclude.m4 deleted file mode 100644 index 3a47b1b..0000000 --- a/contrib/binutils/opcodes/acinclude.m4 +++ /dev/null @@ -1,24 +0,0 @@ -sinclude(../bfd/acinclude.m4) - -dnl sinclude(../libtool.m4) already included in bfd/acinclude.m4 -dnl The lines below arrange for aclocal not to bring libtool.m4 -dnl AM_PROG_LIBTOOL into aclocal.m4, while still arranging for automake -dnl to add a definition of LIBTOOL to Makefile.in. -ifelse(yes,no,[ -AC_DEFUN([AM_PROG_LIBTOOL],) -AC_DEFUN([AM_DISABLE_SHARED],) -AC_SUBST(LIBTOOL) -]) - -dnl sinclude(../gettext.m4) already included in bfd/acinclude.m4 -ifelse(yes,no,[ -AC_DEFUN([CY_WITH_NLS],) -AC_SUBST(INTLLIBS) -]) - -dnl AM_INSTALL_LIBBFD already included in bfd/acinclude.m4 -ifelse(yes,no,[ -AC_DEFUN([AM_INSTALL_LIBBFD],) -AC_SUBST(bfdlibdir) -AC_SUBST(bfdincludedir) -]) diff --git a/contrib/binutils/opcodes/aclocal.m4 b/contrib/binutils/opcodes/aclocal.m4 index d5f3158..2785579 100644 --- a/contrib/binutils/opcodes/aclocal.m4 +++ b/contrib/binutils/opcodes/aclocal.m4 @@ -1,4 +1,4 @@ -# generated automatically by aclocal 1.9.5 -*- Autoconf -*- +# generated automatically by aclocal 1.9.6 -*- Autoconf -*- # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, # 2005 Free Software Foundation, Inc. @@ -28,7 +28,7 @@ AC_DEFUN([AM_AUTOMAKE_VERSION], [am__api_version="1.9"]) # Call AM_AUTOMAKE_VERSION so it can be traced. # This function is AC_REQUIREd by AC_INIT_AUTOMAKE. AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION], - [AM_AUTOMAKE_VERSION([1.9.5])]) + [AM_AUTOMAKE_VERSION([1.9.6])]) # AM_AUX_DIR_EXPAND -*- Autoconf -*- @@ -480,27 +480,6 @@ AC_DEFUN([AM_PROG_INSTALL_SH], install_sh=${install_sh-"$am_aux_dir/install-sh"} AC_SUBST(install_sh)]) -# Copyright (C) 2003, 2005 Free Software Foundation, Inc. -# -# This file is free software; the Free Software Foundation -# gives unlimited permission to copy and/or distribute it, -# with or without modifications, as long as this notice is preserved. - -# serial 2 - -# Check whether the underlying file-system supports filenames -# with a leading dot. For instance MS-DOS doesn't. -AC_DEFUN([AM_SET_LEADING_DOT], -[rm -rf .tst 2>/dev/null -mkdir .tst 2>/dev/null -if test -d .tst; then - am__leading_dot=. -else - am__leading_dot=_ -fi -rmdir .tst 2>/dev/null -AC_SUBST([am__leading_dot])]) - # Add --enable-maintainer-mode option to configure. -*- Autoconf -*- # From Jim Meyering @@ -889,4 +868,16 @@ AC_SUBST([am__tar]) AC_SUBST([am__untar]) ]) # _AM_PROG_TAR -m4_include([acinclude.m4]) +m4_include([../bfd/acinclude.m4]) +m4_include([../bfd/warning.m4]) +m4_include([../config/acx.m4]) +m4_include([../config/depstand.m4]) +m4_include([../config/gettext-sister.m4]) +m4_include([../config/lead-dot.m4]) +m4_include([../config/nls.m4]) +m4_include([../config/po.m4]) +m4_include([../config/progtest.m4]) +m4_include([../libtool.m4]) +m4_include([../ltoptions.m4]) +m4_include([../ltsugar.m4]) +m4_include([../ltversion.m4]) diff --git a/contrib/binutils/opcodes/arm-dis.c b/contrib/binutils/opcodes/arm-dis.c index bc5b52c..2af8fda 100644 --- a/contrib/binutils/opcodes/arm-dis.c +++ b/contrib/binutils/opcodes/arm-dis.c @@ -1,6 +1,6 @@ /* Instruction printing code for the ARM Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 - Free Software Foundation, Inc. + 2007, Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) Modification by James G. Smith (jsmith@cygnus.co.uk) @@ -26,6 +26,7 @@ #include "opcode/arm.h" #include "opintl.h" #include "safe-ctype.h" +#include "floatformat.h" /* FIXME: This shouldn't be done here. */ #include "coff/internal.h" @@ -61,8 +62,12 @@ struct opcode16 %% % - %c print condition code (always bits 28-31) + %c print condition code (always bits 28-31 in ARM mode) + %q print shifter argument + %u print condition code (unconditional in ARM mode) %A print address for ldc/stc/ldf/stf instruction + %B print vstm/vldm register list + %C print vstr/vldr address operand %I print cirrus signed shift immediate: bits 0..3|4..6 %F print the COUNT field of a LFM/SFM instruction. %P print floating point precision in arithmetic insn @@ -71,6 +76,7 @@ struct opcode16 %<bitfield>r print as an ARM register %<bitfield>d print the bitfield in decimal + %<bitfield>k print immediate for VFPv3 conversion instruction %<bitfield>x print the bitfield in hex %<bitfield>X print the bitfield as 1 hex digit without leading "0x" %<bitfield>f print a floating point constant if >7 else a @@ -78,19 +84,26 @@ struct opcode16 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us %<bitfield>g print as an iWMMXt 64-bit register %<bitfield>G print as an iWMMXt general purpose or control register + %<bitfield>D print as a NEON D register + %<bitfield>Q print as a NEON Q register - %<code>y print a single precision VFP reg. + %y<code> print a single precision VFP reg. Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair - %<code>z print a double precision VFP reg + %z<code> print a double precision VFP reg Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list - %<bitnum>'c print specified char iff bit is one - %<bitnum>`c print specified char iff bit is zero - %<bitnum>?ab print a if bit is one else print b + %<bitfield>'c print specified char iff bitfield is all ones + %<bitfield>`c print specified char iff bitfield is all zeroes + %<bitfield>?ab... select from array of values in big endian order + %L print as an iWMMXt N/M width field. %Z print the Immediate of a WSHUFH instruction. %l like 'A' except use byte offsets for 'B' & 'H' - versions. */ + versions. + %i print 5-bit immediate in bits 8,3..0 + (print "32" when 0) + %r print register offset address for wldt/wstr instruction +*/ /* Common coprocessor opcodes shared between Arm and Thumb-2. */ @@ -105,7 +118,7 @@ static const struct opcode32 coprocessor_opcodes[] = /* Intel Wireless MMX technology instructions. */ #define FIRST_IWMMXT_INSN 0x0e130130 -#define IWMMXT_INSN_COUNT 47 +#define IWMMXT_INSN_COUNT 73 {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, @@ -120,37 +133,63 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, + {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, + {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, + {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, + {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, + {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, + {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, @@ -201,80 +240,114 @@ static const struct opcode32 coprocessor_opcodes[] = {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, + /* Register load/store */ + {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"}, + {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"}, + {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, + {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, + {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"}, + {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"}, + + /* Data transfer between ARM and NEON registers */ + {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, + {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, + {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, + {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, + {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, + {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, + {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, + {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, + /* Floating point coprocessor (VFP) instructions */ - {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"}, - {FPU_VFP_EXT_V1, 0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %0y"}, - {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"}, - {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"}, - {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%1y"}, - {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fff0ff0, "fcpyd%c\t%1z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%1y, %0y"}, - {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fff0fd0, "fcvtds%c\t%1z, %0y"}, - {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0ff0, "fcvtsd%c\t%1y, %0z"}, - {FPU_VFP_EXT_V1, 0x0e800b00, 0x0ff00ff0, "fdivd%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%1y, %2y, %0y"}, - {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f700f00, "fldd%c\t%1z, %A"}, - {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0fd00f00, "fldmia%0?xd%c\t%16-19r%21'!, %3z"}, - {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0ff00f00, "fldmdb%0?xd%c\t%16-19r!, %3z"}, - {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%1y, %A"}, - {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %3y"}, - {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %3y"}, - {FPU_VFP_EXT_V1, 0x0e000b00, 0x0ff00ff0, "fmacd%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%1y, %2y, %0y"}, - {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%2z, %12-15r"}, - {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%2z, %12-15r"}, - {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00ff0, "fmdrr%c\t%0z, %12-15r, %16-19r"}, - {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %2z"}, - {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %2z"}, - {FPU_VFP_EXT_V1, 0x0c500b10, 0x0ff00ff0, "fmrrd%c\t%12-15r, %16-19r, %0z"}, - {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %4y"}, - {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %2y"}, {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"}, - {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, - {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, - {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, - {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, - {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, - {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"}, - {FPU_VFP_EXT_V1, 0x0e100b00, 0x0ff00ff0, "fmscd%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%1y, %2y, %0y"}, - {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%2y, %12-15r"}, - {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %4y"}, - {FPU_VFP_EXT_V1, 0x0e200b00, 0x0ff00ff0, "fmuld%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%1y, %2y, %0y"}, {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "fmxr%c\tmvfr1, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "fmxr%c\tmvfr0, %12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"}, {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"}, {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"}, - {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"}, - {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fff0ff0, "fnegd%c\t%1z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%1y, %0y"}, - {FPU_VFP_EXT_V1, 0x0e000b40, 0x0ff00ff0, "fnmacd%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%1y, %2y, %0y"}, - {FPU_VFP_EXT_V1, 0x0e100b40, 0x0ff00ff0, "fnmscd%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%1y, %2y, %0y"}, - {FPU_VFP_EXT_V1, 0x0e200b40, 0x0ff00ff0, "fnmuld%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%1y, %2y, %0y"}, - {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fff0fd0, "fsitod%c\t%1z, %0y"}, - {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%1y, %0y"}, - {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fff0ff0, "fsqrtd%c\t%1z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%1y, %0y"}, - {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f700f00, "fstd%c\t%1z, %A"}, - {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0fd00f00, "fstmia%0?xd%c\t%16-19r%21'!, %3z"}, - {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0ff00f00, "fstmdb%0?xd%c\t%16-19r!, %3z"}, - {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%1y, %A"}, - {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %3y"}, - {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %3y"}, - {FPU_VFP_EXT_V1, 0x0e300b40, 0x0ff00ff0, "fsubd%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%1y, %2y, %0y"}, - {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f70, "fto%16?sui%7'zd%c\t%1y, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%1y, %0y"}, - {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fff0fd0, "fuitod%c\t%1z, %0y"}, - {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%1y, %0y"}, + {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, + {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, + {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr1"}, + {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr0"}, + {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, + {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, + {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, + {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"}, + {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"}, + {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"}, + {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"}, + {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"}, + {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"}, + {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"}, + {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"}, + {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"}, + {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"}, + {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"}, + {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"}, + {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"}, + {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"}, + {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"}, + {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"}, + {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"}, + {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"}, + {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"}, + {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"}, + {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"}, + {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"}, + {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"}, + {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"}, + {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"}, + {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"}, + {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"}, + {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"}, + {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"}, + {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"}, + {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"}, + {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"}, + {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"}, + {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"}, + {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"}, + {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"}, + {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"}, + {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"}, + {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"}, /* Cirrus coprocessor instructions. */ {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, @@ -368,22 +441,300 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, /* V6 coprocessor instructions */ - {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, /* V5 coprocessor instructions */ - {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0, 0, 0, 0} }; +/* Neon opcode table: This does not encode the top byte -- that is + checked by the print_insn_neon routine, as it depends on whether we are + doing thumb32 or arm32 disassembly. */ + +/* print_insn_neon recognizes the following format control codes: + + %% % + + %c print condition code + %A print v{st,ld}[1234] operands + %B print v{st,ld}[1234] any one operands + %C print v{st,ld}[1234] single->all operands + %D print scalar + %E print vmov, vmvn, vorr, vbic encoded constant + %F print vtbl,vtbx register list + + %<bitfield>r print as an ARM register + %<bitfield>d print the bitfield in decimal + %<bitfield>e print the 2^N - bitfield in decimal + %<bitfield>D print as a NEON D register + %<bitfield>Q print as a NEON Q register + %<bitfield>R print as a NEON D or Q register + %<bitfield>Sn print byte scaled width limited by n + %<bitfield>Tn print short scaled width limited by n + %<bitfield>Un print long scaled width limited by n + + %<bitfield>'c print specified char iff bitfield is all ones + %<bitfield>`c print specified char iff bitfield is all zeroes + %<bitfield>?ab... select from array of values in big endian order */ + +static const struct opcode32 neon_opcodes[] = +{ + /* Extract */ + {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, + {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, + + /* Move data element to all lanes */ + {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, + {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, + {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, + + /* Table lookup */ + {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, + + /* Two registers, miscellaneous */ + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, + {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, + + /* Three registers of the same length */ + {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + + /* One register and an immediate value */ + {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, + {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, + + /* Two registers and a shift amount */ + {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, + + /* Three registers of different lengths */ + {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + + /* Two registers and a scalar */ + {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + + /* Element and structure load/store */ + {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, + {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, + {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, + {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, + {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, + {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, + {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, + {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, + {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, + {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, + + {0,0 ,0, 0} +}; + /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially ordered: they must be searched linearly from the top to obtain a correct match. */ @@ -410,10 +761,10 @@ static const struct opcode32 coprocessor_opcodes[] = %<bitfield>W print the bitfield plus one in decimal %<bitfield>x print the bitfield in hex %<bitfield>X print the bitfield as 1 hex digit without leading "0x" - - %<bitnum>'c print specified char iff bit is one - %<bitnum>`c print specified char iff bit is zero - %<bitnum>?ab print a if bit is one else print b + + %<bitfield>'c print specified char iff bitfield is all ones + %<bitfield>`c print specified char iff bitfield is all zeroes + %<bitfield>?ab... select from array of values in big endian order %e print arm SMI operand (bits 0..7,8..19). %E print the LSB and WIDTH fields of a BFI or BFC instruction. @@ -424,11 +775,11 @@ static const struct opcode32 arm_opcodes[] = /* ARM instructions. */ {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, - {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"}, + {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, /* V7 instructions. */ {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, @@ -441,11 +792,11 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"}, {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"}, {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"}, - {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"}, + {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %s"}, + {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %s"}, {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"}, {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"}, - {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, /* ARM V6Z instructions. */ @@ -468,15 +819,15 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, /* ARM V6 instructions. */ - {ARM_EXT_V6, 0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"}, - {ARM_EXT_V6, 0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, - {ARM_EXT_V6, 0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"}, - {ARM_EXT_V6, 0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, + {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, + {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"}, + {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, lsl #%7-11d"}, + {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #32"}, + {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #%7-11d"}, {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, @@ -518,54 +869,54 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"}, {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"}, {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"}, - {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"}, - {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"}, - {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #24"}, + {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #24"}, + {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #24"}, + {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #24"}, + {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #24"}, + {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r"}, + {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #24"}, {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #24"}, {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, - {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, - {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, - {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, + {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, + {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, @@ -577,18 +928,18 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"}, + {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, - {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"}, - {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"}, + {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, lsl #%7-11d"}, + {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, asr #%7-11d"}, {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, - {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"}, - {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"}, + {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, lsl #%7-11d"}, + {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, asr #%7-11d"}, {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, /* V5J instruction. */ @@ -601,8 +952,8 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, /* V5E "El Segundo" Instructions. */ - {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"}, - {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"}, + {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, + {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, @@ -631,33 +982,45 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, /* ARM Instructions. */ - {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, - {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, - {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"}, + {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"}, + {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, - {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, - {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, - {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"}, - {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"}, - {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"}, + {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%p%c\t%16-19r, %o"}, + {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, + {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, + {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"}, + {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"}, + {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"}, + {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, + {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"}, + {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"}, + {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, + {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"}, {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"}, - {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, - {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, + {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, + {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, + {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, @@ -677,6 +1040,11 @@ static const struct opcode32 arm_opcodes[] = %M print Thumb register mask %b print CZB's 6-bit unsigned branch destination %s print Thumb right-shift immediate (6..10; 0 == 32). + %c print the condition code + %C print the condition code, or "s" if not conditional + %x print warning if conditional an not at end of IT block" + %X print "\t; unpredictable <IT:code>" if conditional + %I print IT instruction suffix and operands %<bitfield>r print bitfield as an ARM register %<bitfield>d print bitfield as a decimal %<bitfield>H print (bitfield * 2) as a decimal @@ -692,117 +1060,112 @@ static const struct opcode16 thumb_opcodes[] = /* Thumb instructions. */ /* ARM V6K no-argument instructions. */ - {ARM_EXT_V6K, 0xbf00, 0xffff, "nop"}, - {ARM_EXT_V6K, 0xbf10, 0xffff, "yield"}, - {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"}, - {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"}, - {ARM_EXT_V6K, 0xbf40, 0xffff, "sev"}, - {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop\t{%4-7d}"}, + {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, + {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, + {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"}, + {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"}, + {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"}, + {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, /* ARM V6T2 instructions. */ - {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b"}, - {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b"}, - {ARM_EXT_V6T2, 0xbf08, 0xff0f, "it\t%4-7c"}, - {ARM_EXT_V6T2, 0xbf14, 0xff17, "it%3?te\t%4-7c"}, - {ARM_EXT_V6T2, 0xbf04, 0xff17, "it%3?et\t%4-7c"}, - {ARM_EXT_V6T2, 0xbf12, 0xff13, "it%3?te%2?te\t%4-7c"}, - {ARM_EXT_V6T2, 0xbf02, 0xff13, "it%3?et%2?et\t%4-7c"}, - {ARM_EXT_V6T2, 0xbf11, 0xff11, "it%3?te%2?te%1?te\t%4-7c"}, - {ARM_EXT_V6T2, 0xbf01, 0xff11, "it%3?et%2?et%1?et\t%4-7c"}, + {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, + {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, + {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"}, /* ARM V6. */ - {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"}, - {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"}, - {ARM_EXT_V6, 0x4600, 0xffc0, "mov\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xba00, 0xffc0, "rev\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble"}, - {ARM_EXT_V6, 0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, + {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, + {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"}, + {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, + {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, /* ARM V5 ISA extends Thumb. */ - {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, + {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ /* This is BLX(2). BLX(1) is a 32-bit instruction. */ - {ARM_EXT_V5T, 0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */ + {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ /* ARM V4T ISA (Thumb v1). */ - {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"}, + {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"}, /* Format 4. */ - {ARM_EXT_V4T, 0x4000, 0xFFC0, "ands\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4040, 0xFFC0, "eors\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsls\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsrs\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4100, 0xFFC0, "asrs\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4140, 0xFFC0, "adcs\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbcs\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x41C0, 0xFFC0, "rors\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4240, 0xFFC0, "negs\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4300, 0xFFC0, "orrs\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4340, 0xFFC0, "muls\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4380, 0xFFC0, "bics\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvns\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, + {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, /* format 13 */ - {ARM_EXT_V4T, 0xB000, 0xFF80, "add\tsp, #%0-6W"}, - {ARM_EXT_V4T, 0xB080, 0xFF80, "sub\tsp, #%0-6W"}, + {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, + {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, /* format 5 */ - {ARM_EXT_V4T, 0x4700, 0xFF80, "bx\t%S"}, - {ARM_EXT_V4T, 0x4400, 0xFF00, "add\t%D, %S"}, - {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp\t%D, %S"}, - {ARM_EXT_V4T, 0x4600, 0xFF00, "mov\t%D, %S"}, + {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"}, + {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"}, + {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"}, + {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"}, /* format 14 */ - {ARM_EXT_V4T, 0xB400, 0xFE00, "push\t%N"}, - {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop\t%O"}, + {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"}, + {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"}, /* format 2 */ - {ARM_EXT_V4T, 0x1800, 0xFE00, "adds\t%0-2r, %3-5r, %6-8r"}, - {ARM_EXT_V4T, 0x1A00, 0xFE00, "subs\t%0-2r, %3-5r, %6-8r"}, - {ARM_EXT_V4T, 0x1C00, 0xFE00, "adds\t%0-2r, %3-5r, #%6-8d"}, - {ARM_EXT_V4T, 0x1E00, 0xFE00, "subs\t%0-2r, %3-5r, #%6-8d"}, + {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, + {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, + {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, + {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, /* format 8 */ - {ARM_EXT_V4T, 0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"}, - {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"}, - {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, /* format 7 */ - {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"}, - {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, /* format 1 */ - {ARM_EXT_V4T, 0x0000, 0xF800, "lsls\t%0-2r, %3-5r, #%6-10d"}, - {ARM_EXT_V4T, 0x0800, 0xF800, "lsrs\t%0-2r, %3-5r, %s"}, - {ARM_EXT_V4T, 0x1000, 0xF800, "asrs\t%0-2r, %3-5r, %s"}, + {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, + {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, + {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, /* format 3 */ - {ARM_EXT_V4T, 0x2000, 0xF800, "movs\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x3000, 0xF800, "adds\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x3800, 0xF800, "subs\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, + {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, /* format 6 */ - {ARM_EXT_V4T, 0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ + {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ /* format 9 */ - {ARM_EXT_V4T, 0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"}, - {ARM_EXT_V4T, 0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"}, - {ARM_EXT_V4T, 0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"}, - {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"}, + {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, + {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, + {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, + {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, /* format 10 */ - {ARM_EXT_V4T, 0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"}, - {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"}, + {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, + {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, /* format 11 */ - {ARM_EXT_V4T, 0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"}, - {ARM_EXT_V4T, 0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"}, + {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, + {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, /* format 12 */ - {ARM_EXT_V4T, 0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"}, - {ARM_EXT_V4T, 0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"}, + {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"}, + {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, /* format 15 */ - {ARM_EXT_V4T, 0xC000, 0xF800, "stmia\t%8-10r!, %M"}, - {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia\t%8-10r!, %M"}, + {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, + {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"}, /* format 17 */ - {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc\t%0-7d"}, + {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"}, /* format 16 */ - {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B"}, + {ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"}, + {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, /* format 18 */ - {ARM_EXT_V4T, 0xE000, 0xF800, "b.n\t%0-10B"}, + {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, /* The E800 .. FFFF range is unconditionally redirected to the 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs @@ -838,15 +1201,18 @@ static const struct opcode16 thumb_opcodes[] = %R print the rotation field of an SXT instruction %U print barrier type. %P print address for pli instruction. + %c print the condition code + %x print warning if conditional an not at end of IT block" + %X print "\t; unpredictable <IT:code>" if conditional %<bitfield>d print bitfield in decimal %<bitfield>W print bitfield*4 in decimal %<bitfield>r print bitfield as an ARM register %<bitfield>c print bitfield as a condition code - %<bitnum>'c print "c" iff bit is one - %<bitnum>`c print "c" iff bit is zero - %<bitnum>?ab print "a" if bit is one, else "b" + %<bitfield>'c print specified char iff bitfield is all ones + %<bitfield>`c print specified char iff bitfield is all zeroes + %<bitfield>?ab... select from array of values in big endian order With one exception at the bottom (done because BL and BLX(1) need to come dead last), this table was machine-sorted first in @@ -859,202 +1225,204 @@ static const struct opcode16 thumb_opcodes[] = static const struct opcode32 thumb32_opcodes[] = { /* V7 instructions. */ - {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli\t%a"}, - {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg\t#%0-3d"}, - {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb\t%U"}, - {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb\t%U"}, - {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb\t%U"}, - {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, + {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, + {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, + {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, + {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, + {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, /* Instructions defined in the basic V6T2 set. */ - {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop.w"}, - {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield.w"}, - {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe.w"}, - {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi.w"}, - {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev.w"}, - {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop.w\t{%0-7d}"}, - - {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex"}, - {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f"}, - {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f"}, - {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj\t%16-19r"}, - {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb\t%16-19r%21'!"}, - {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia\t%16-19r%21'!"}, - {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs\t%8-11r, %D"}, - {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d"}, - {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb\t[%16-19r, %0-3r]"}, - {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh\t[%16-19r, %0-3r, lsl #1]"}, - {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d"}, - {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d"}, - {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs\tpc, lr, #%0-7d"}, - {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr\t%C, %16-19r"}, - {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb\t#%0-4d%21'!"}, - {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia\t#%0-4d%21'!"}, - {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex\t%8-11r, %12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb\t%0-3r, %12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16\t%8-11r, #%0-4d, %16-19r"}, - {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16\t%8-11r, #%0-4d, %16-19r"}, - {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc\t%8-11r, %E"}, - {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst.w\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn.w\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp.w\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst.w\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn.w\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp.w\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's.w\t%8-11r, %S"}, - {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's.w\t%8-11r, %S"}, - {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex\t%12-15r, [%16-19r, #%0-7W]"}, - {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc\t%K"}, - {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's.w\t%8-11r, %M"}, - {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's.w\t%8-11r, %M"}, - {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld\t%a"}, - {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx\t%8-11r, %16-19r, %F"}, - {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx\t%8-11r, %16-19r, %F"}, - {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi\t%8-11r, %16-19r, %E"}, - {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat\t%8-11r, #%0-4d, %16-19r%s"}, - {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat\t%8-11r, #%0-4d, %16-19r%s"}, - {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw\t%8-11r, %16-19r, %I"}, - {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw\t%8-11r, %J"}, - {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw\t%8-11r, %16-19r, %I"}, - {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt\t%8-11r, %J"}, - {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, - {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia.w\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia.w\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"}, - {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"}, - {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w.w\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w.w\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"}, + {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"}, + {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"}, + {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"}, + {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"}, + {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, + + {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"}, + {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, + {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, + {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, + {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, + {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, + {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"}, + {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, + {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, + {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, + {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, + {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, + {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, + {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, + {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, + {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, + {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, + {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, + {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, + {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, + {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, + {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, + {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, + {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, + {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, + {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, + {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, + {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"}, + {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, + {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, + {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, + {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"}, + {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, + {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, + {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, + {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, + {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, + {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, + {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, + {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, + {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, + {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, + {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, + {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, + {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, + {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, + {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, /* Filter out Bcc with cond=E or F, which are used for other instructions. */ {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, - {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b"}, - {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b.w\t%B"}, + {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, + {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, /* These have been 32-bit since the invention of Thumb. */ - {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx\t%B"}, - {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl\t%B"}, + {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"}, + {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, /* Fallback. */ {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"}, @@ -1063,7 +1431,7 @@ static const struct opcode32 thumb32_opcodes[] = static const char *const arm_conditional[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", "gt", "le", "", "<und>"}; + "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; static const char *const arm_fp_const[] = {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; @@ -1099,10 +1467,10 @@ static const char *const iwmmxt_wwnames[] = {"b", "h", "w", "d"}; static const char *const iwmmxt_wwssnames[] = -{"b", "bus", "b", "bss", - "h", "hus", "h", "hss", - "w", "wus", "w", "wss", - "d", "dus", "d", "dss" +{"b", "bus", "bc", "bss", + "h", "hus", "hc", "hss", + "w", "wus", "wc", "wss", + "d", "dus", "dc", "dss" }; static const char *const iwmmxt_regnames[] = @@ -1123,6 +1491,26 @@ static unsigned int regname_selected = 1; static bfd_boolean force_thumb = FALSE; +/* Current IT instruction state. This contains the same state as the IT + bits in the CPSR. */ +static unsigned int ifthen_state; +/* IT state for the next instruction. */ +static unsigned int ifthen_next_state; +/* The address of the insn for which the IT state is valid. */ +static bfd_vma ifthen_address; +#define IFTHEN_COND ((ifthen_state >> 4) & 0xf) + +/* Cached mapping symbol state. */ +enum map_type { + MAP_ARM, + MAP_THUMB, + MAP_DATA +}; + +enum map_type last_type; +int last_mapping_sym = -1; +bfd_vma last_mapping_addr = 0; + /* Functions. */ int @@ -1149,8 +1537,46 @@ get_arm_regnames (int option, const char **setname, const char **setdescription, return 16; } +/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. + Returns pointer to following character of the format string and + fills in *VALUEP and *WIDTHP with the extracted value and number of + bits extracted. WIDTHP can be NULL. */ + +static const char * +arm_decode_bitfield (const char *ptr, unsigned long insn, + unsigned long *valuep, int *widthp) +{ + unsigned long value = 0; + int width = 0; + + do + { + int start, end; + int bits; + + for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) + start = start * 10 + *ptr - '0'; + if (*ptr == '-') + for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) + end = end * 10 + *ptr - '0'; + else + end = start; + bits = end - start; + if (bits < 0) + abort (); + value |= ((insn >> start) & ((2ul << bits) - 1)) << width; + width += bits + 1; + } + while (*ptr++ == ','); + *valuep = value; + if (widthp) + *widthp = width; + return ptr - 1; +} + static void -arm_decode_shift (long given, fprintf_ftype func, void *stream) +arm_decode_shift (long given, fprintf_ftype func, void *stream, + int print_shift) { func (stream, "%s", arm_regnames[given & 0xf]); @@ -1172,11 +1598,16 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream) amount = 32; } - func (stream, ", %s #%d", arm_shift[shift], amount); + if (print_shift) + func (stream, ", %s #%d", arm_shift[shift], amount); + else + func (stream, ", #%d", amount); } - else + else if (print_shift) func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], arm_regnames[(given & 0xf00) >> 8]); + else + func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); } } @@ -1185,7 +1616,7 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream) recognised coprocessor instruction. */ static bfd_boolean -print_insn_coprocessor (struct disassemble_info *info, long given, +print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, bfd_boolean thumb) { const struct opcode32 *insn; @@ -1193,12 +1624,14 @@ print_insn_coprocessor (struct disassemble_info *info, long given, fprintf_ftype func = info->fprintf_func; unsigned long mask; unsigned long value; + int cond; for (insn = coprocessor_opcodes; insn->assembler; insn++) { if (insn->value == FIRST_IWMMXT_INSN && info->mach != bfd_mach_arm_XScale - && info->mach != bfd_mach_arm_iWMMXt) + && info->mach != bfd_mach_arm_iWMMXt + && info->mach != bfd_mach_arm_iWMMXt2) insn = insn + IWMMXT_INSN_COUNT; mask = insn->mask; @@ -1210,13 +1643,26 @@ print_insn_coprocessor (struct disassemble_info *info, long given, encoding is the same. */ mask |= 0xf0000000; value |= 0xe0000000; + if (ifthen_state) + cond = IFTHEN_COND; + else + cond = 16; } else { /* Only match unconditional instuctions against unconditional patterns. */ if ((given & 0xf0000000) == 0xf0000000) - mask |= 0xf0000000; + { + mask |= 0xf0000000; + cond = 16; + } + else + { + cond = (given >> 28) & 0xf; + if (cond == 0xe) + cond = 16; + } } if ((given & mask) == value) { @@ -1265,9 +1711,48 @@ print_insn_coprocessor (struct disassemble_info *info, long given, } break; + case 'B': + { + int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); + int offset = (given >> 1) & 0x3f; + + if (offset == 1) + func (stream, "{d%d}", regno); + else if (regno + offset > 32) + func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); + else + func (stream, "{d%d-d%d}", regno, regno + offset - 1); + } + break; + + case 'C': + { + int rn = (given >> 16) & 0xf; + int offset = (given & 0xff) * 4; + int add = (given >> 23) & 1; + + func (stream, "[%s", arm_regnames[rn]); + + if (offset) + { + if (!add) + offset = -offset; + func (stream, ", #%d", offset); + } + func (stream, "]"); + if (rn == 15) + { + func (stream, "\t; "); + /* FIXME: Unsure if info->bytes_per_chunk is the + right thing to use here. */ + info->print_address_func (offset + pc + + info->bytes_per_chunk * 2, info); + } + } + break; + case 'c': - func (stream, "%s", - arm_conditional [(given >> 28) & 0xf]); + func (stream, "%s", arm_conditional[cond]); break; case 'I': @@ -1360,206 +1845,163 @@ print_insn_coprocessor (struct disassemble_info *info, long given, case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { - int bitstart = *c++ - '0'; - int bitend = 0; - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; + int width; + unsigned long value; + + c = arm_decode_bitfield (c, given, &value, &width); switch (*c) { - case '-': - c++; - - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - - if (!bitend) - abort (); + case 'r': + func (stream, "%s", arm_regnames[value]); + break; + case 'D': + func (stream, "d%ld", value); + break; + case 'Q': + if (value & 1) + func (stream, "<illegal reg q%ld.5>", value >> 1); + else + func (stream, "q%ld", value >> 1); + break; + case 'd': + func (stream, "%ld", value); + break; + case 'k': + { + int from = (given & (1 << 7)) ? 32 : 16; + func (stream, "%ld", from - value); + } + break; + + case 'f': + if (value > 7) + func (stream, "#%s", arm_fp_const[value & 7]); + else + func (stream, "f%ld", value); + break; - switch (*c) - { - case 'r': - { - long reg; + case 'w': + if (width == 2) + func (stream, "%s", iwmmxt_wwnames[value]); + else + func (stream, "%s", iwmmxt_wwssnames[value]); + break; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; + case 'g': + func (stream, "%s", iwmmxt_regnames[value]); + break; + case 'G': + func (stream, "%s", iwmmxt_cregnames[value]); + break; - func (stream, "%s", arm_regnames[reg]); - } - break; - case 'd': - { - long reg; + case 'x': + func (stream, "0x%lx", value); + break; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; + case '`': + c++; + if (value == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if (value == ((1ul << width) - 1)) + func (stream, "%c", *c); + break; + case '?': + func (stream, "%c", c[(1 << width) - (int)value]); + c += 1 << width; + break; + default: + abort (); + } + break; - func (stream, "%ld", reg); - } - break; - case 'f': + case 'y': + case 'z': + { + int single = *c++ == 'y'; + int regno; + + switch (*c) + { + case '4': /* Sm pair */ + func (stream, "{"); + /* Fall through. */ + case '0': /* Sm, Dm */ + regno = given & 0x0000000f; + if (single) { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - if (reg > 7) - func (stream, "#%s", - arm_fp_const[reg & 7]); - else - func (stream, "f%ld", reg); + regno <<= 1; + regno += (given >> 5) & 1; } - break; + else + regno += ((given >> 5) & 1) << 4; + break; - case 'w': + case '1': /* Sd, Dd */ + regno = (given >> 12) & 0x0000000f; + if (single) { - long reg; - - if (bitstart != bitend) - { - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - if (bitend - bitstart == 1) - func (stream, "%s", iwmmxt_wwnames[reg]); - else - func (stream, "%s", iwmmxt_wwssnames[reg]); - } - else - { - reg = (((given >> 8) & 0x1) | - ((given >> 22) & 0x1)); - func (stream, "%s", iwmmxt_wwnames[reg]); - } + regno <<= 1; + regno += (given >> 22) & 1; } - break; + else + regno += ((given >> 22) & 1) << 4; + break; - case 'g': + case '2': /* Sn, Dn */ + regno = (given >> 16) & 0x0000000f; + if (single) { - long reg; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%s", iwmmxt_regnames[reg]); + regno <<= 1; + regno += (given >> 7) & 1; } - break; - - case 'G': + else + regno += ((given >> 7) & 1) << 4; + break; + + case '3': /* List */ + func (stream, "{"); + regno = (given >> 12) & 0x0000000f; + if (single) { - long reg; - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%s", iwmmxt_cregnames[reg]); + regno <<= 1; + regno += (given >> 22) & 1; } - break; + else + regno += ((given >> 22) & 1) << 4; + break; + + default: + abort (); + } - default: - abort (); - } - break; + func (stream, "%c%d", single ? 's' : 'd', regno); - case 'y': - case 'z': + if (*c == '3') { - int single = *c == 'y'; - int regno; - - switch (bitstart) + int count = given & 0xff; + + if (single == 0) + count >>= 1; + + if (--count) { - case 4: /* Sm pair */ - func (stream, "{"); - /* Fall through. */ - case 0: /* Sm, Dm */ - regno = given & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 5) & 1; - } - break; - - case 1: /* Sd, Dd */ - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - break; - - case 2: /* Sn, Dn */ - regno = (given >> 16) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 7) & 1; - } - break; - - case 3: /* List */ - func (stream, "{"); - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - break; - - - default: - abort (); + func (stream, "-%c%d", + single ? 's' : 'd', + regno + count); } - - func (stream, "%c%d", single ? 's' : 'd', regno); - - if (bitstart == 3) - { - int count = given & 0xff; - - if (single == 0) - count >>= 1; - - if (--count) - { - func (stream, "-%c%d", - single ? 's' : 'd', - regno + count); - } - - func (stream, "}"); - } - else if (bitstart == 4) - func (stream, ", %c%d}", single ? 's' : 'd', - regno + 1); - - break; + + func (stream, "}"); } - - break; - - case '`': - c++; - if ((given & (1 << bitstart)) == 0) - func (stream, "%c", *c); - break; - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - case '?': - ++c; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c++); - else - func (stream, "%c", *++c); - break; - default: - abort (); - } + else if (*c == '4') + func (stream, ", %c%d}", single ? 's' : 'd', + regno + 1); + } break; - + case 'L': switch (given & 0x00400100) { @@ -1608,6 +2050,53 @@ print_insn_coprocessor (struct disassemble_info *info, long given, } break; + case 'r': + { + int imm4 = (given >> 4) & 0xf; + int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1); + int ubit = (given >> 23) & 1; + const char *rm = arm_regnames [given & 0xf]; + const char *rn = arm_regnames [(given >> 16) & 0xf]; + + switch (puw_bits) + { + case 1: + /* fall through */ + case 3: + func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); + if (imm4) + func (stream, ", lsl #%d", imm4); + break; + + case 4: + /* fall through */ + case 5: + /* fall through */ + case 6: + /* fall through */ + case 7: + func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); + if (imm4 > 0) + func (stream, ", lsl #%d", imm4); + func (stream, "]"); + if (puw_bits == 5 || puw_bits == 7) + func (stream, "!"); + break; + + default: + func (stream, "INVALID"); + } + } + break; + + case 'i': + { + long imm5; + imm5 = ((given & 0x100) >> 4) | (given & 0xf); + func (stream, "%ld", (imm5 == 0) ? 32 : imm5); + } + break; + default: abort (); } @@ -1683,7 +2172,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) func (stream, ", %s", (((given & 0x00800000) == 0) ? "-" : "")); - arm_decode_shift (given, func, stream); + arm_decode_shift (given, func, stream, 1); } func (stream, "]%s", @@ -1706,12 +2195,471 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "], %s", (((given & 0x00800000) == 0) ? "-" : "")); - arm_decode_shift (given, func, stream); + arm_decode_shift (given, func, stream, 1); } } } } +/* Print one neon instruction on INFO->STREAM. + Return TRUE if the instuction matched, FALSE if this is not a + recognised neon instruction. */ + +static bfd_boolean +print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) +{ + const struct opcode32 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + if (thumb) + { + if ((given & 0xef000000) == 0xef000000) + { + /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ + unsigned long bit28 = given & (1 << 28); + + given &= 0x00ffffff; + if (bit28) + given |= 0xf3000000; + else + given |= 0xf2000000; + } + else if ((given & 0xff000000) == 0xf9000000) + given ^= 0xf9000000 ^ 0xf4000000; + else + return FALSE; + } + + for (insn = neon_opcodes; insn->assembler; insn++) + { + if ((given & insn->mask) == insn->value) + { + const char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'c': + if (thumb && ifthen_state) + func (stream, "%s", arm_conditional[IFTHEN_COND]); + break; + + case 'A': + { + static const unsigned char enc[16] = + { + 0x4, 0x14, /* st4 0,1 */ + 0x4, /* st1 2 */ + 0x4, /* st2 3 */ + 0x3, /* st3 4 */ + 0x13, /* st3 5 */ + 0x3, /* st1 6 */ + 0x1, /* st1 7 */ + 0x2, /* st2 8 */ + 0x12, /* st2 9 */ + 0x2, /* st1 10 */ + 0, 0, 0, 0, 0 + }; + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); + int rn = ((given >> 16) & 0xf); + int rm = ((given >> 0) & 0xf); + int align = ((given >> 4) & 0x3); + int type = ((given >> 8) & 0xf); + int n = enc[type] & 0xf; + int stride = (enc[type] >> 4) + 1; + int ix; + + func (stream, "{"); + if (stride > 1) + for (ix = 0; ix != n; ix++) + func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); + else if (n == 1) + func (stream, "d%d", rd); + else + func (stream, "d%d-d%d", rd, rd + n - 1); + func (stream, "}, [%s", arm_regnames[rn]); + if (align) + func (stream, ", :%d", 32 << align); + func (stream, "]"); + if (rm == 0xd) + func (stream, "!"); + else if (rm != 0xf) + func (stream, ", %s", arm_regnames[rm]); + } + break; + + case 'B': + { + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); + int rn = ((given >> 16) & 0xf); + int rm = ((given >> 0) & 0xf); + int idx_align = ((given >> 4) & 0xf); + int align = 0; + int size = ((given >> 10) & 0x3); + int idx = idx_align >> (size + 1); + int length = ((given >> 8) & 3) + 1; + int stride = 1; + int i; + + if (length > 1 && size > 0) + stride = (idx_align & (1 << size)) ? 2 : 1; + + switch (length) + { + case 1: + { + int amask = (1 << size) - 1; + if ((idx_align & (1 << size)) != 0) + return FALSE; + if (size > 0) + { + if ((idx_align & amask) == amask) + align = 8 << size; + else if ((idx_align & amask) != 0) + return FALSE; + } + } + break; + + case 2: + if (size == 2 && (idx_align & 2) != 0) + return FALSE; + align = (idx_align & 1) ? 16 << size : 0; + break; + + case 3: + if ((size == 2 && (idx_align & 3) != 0) + || (idx_align & 1) != 0) + return FALSE; + break; + + case 4: + if (size == 2) + { + if ((idx_align & 3) == 3) + return FALSE; + align = (idx_align & 3) * 64; + } + else + align = (idx_align & 1) ? 32 << size : 0; + break; + + default: + abort (); + } + + func (stream, "{"); + for (i = 0; i < length; i++) + func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", + rd + i * stride, idx); + func (stream, "}, [%s", arm_regnames[rn]); + if (align) + func (stream, ", :%d", align); + func (stream, "]"); + if (rm == 0xd) + func (stream, "!"); + else if (rm != 0xf) + func (stream, ", %s", arm_regnames[rm]); + } + break; + + case 'C': + { + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); + int rn = ((given >> 16) & 0xf); + int rm = ((given >> 0) & 0xf); + int align = ((given >> 4) & 0x1); + int size = ((given >> 6) & 0x3); + int type = ((given >> 8) & 0x3); + int n = type + 1; + int stride = ((given >> 5) & 0x1); + int ix; + + if (stride && (n == 1)) + n++; + else + stride++; + + func (stream, "{"); + if (stride > 1) + for (ix = 0; ix != n; ix++) + func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); + else if (n == 1) + func (stream, "d%d[]", rd); + else + func (stream, "d%d[]-d%d[]", rd, rd + n - 1); + func (stream, "}, [%s", arm_regnames[rn]); + if (align) + { + int align = (8 * (type + 1)) << size; + if (type == 3) + align = (size > 1) ? align >> 1 : align; + if (type == 2 || (type == 0 && !size)) + func (stream, ", :<bad align %d>", align); + else + func (stream, ", :%d", align); + } + func (stream, "]"); + if (rm == 0xd) + func (stream, "!"); + else if (rm != 0xf) + func (stream, ", %s", arm_regnames[rm]); + } + break; + + case 'D': + { + int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); + int size = (given >> 20) & 3; + int reg = raw_reg & ((4 << size) - 1); + int ix = raw_reg >> size >> 2; + + func (stream, "d%d[%d]", reg, ix); + } + break; + + case 'E': + /* Neon encoded constant for mov, mvn, vorr, vbic */ + { + int bits = 0; + int cmode = (given >> 8) & 0xf; + int op = (given >> 5) & 0x1; + unsigned long value = 0, hival = 0; + unsigned shift; + int size = 0; + int isfloat = 0; + + bits |= ((given >> 24) & 1) << 7; + bits |= ((given >> 16) & 7) << 4; + bits |= ((given >> 0) & 15) << 0; + + if (cmode < 8) + { + shift = (cmode >> 1) & 3; + value = (unsigned long)bits << (8 * shift); + size = 32; + } + else if (cmode < 12) + { + shift = (cmode >> 1) & 1; + value = (unsigned long)bits << (8 * shift); + size = 16; + } + else if (cmode < 14) + { + shift = (cmode & 1) + 1; + value = (unsigned long)bits << (8 * shift); + value |= (1ul << (8 * shift)) - 1; + size = 32; + } + else if (cmode == 14) + { + if (op) + { + /* bit replication into bytes */ + int ix; + unsigned long mask; + + value = 0; + hival = 0; + for (ix = 7; ix >= 0; ix--) + { + mask = ((bits >> ix) & 1) ? 0xff : 0; + if (ix <= 3) + value = (value << 8) | mask; + else + hival = (hival << 8) | mask; + } + size = 64; + } + else + { + /* byte replication */ + value = (unsigned long)bits; + size = 8; + } + } + else if (!op) + { + /* floating point encoding */ + int tmp; + + value = (unsigned long)(bits & 0x7f) << 19; + value |= (unsigned long)(bits & 0x80) << 24; + tmp = bits & 0x40 ? 0x3c : 0x40; + value |= (unsigned long)tmp << 24; + size = 32; + isfloat = 1; + } + else + { + func (stream, "<illegal constant %.8x:%x:%x>", + bits, cmode, op); + size = 32; + break; + } + switch (size) + { + case 8: + func (stream, "#%ld\t; 0x%.2lx", value, value); + break; + + case 16: + func (stream, "#%ld\t; 0x%.4lx", value, value); + break; + + case 32: + if (isfloat) + { + unsigned char valbytes[4]; + double fvalue; + + /* Do this a byte at a time so we don't have to + worry about the host's endianness. */ + valbytes[0] = value & 0xff; + valbytes[1] = (value >> 8) & 0xff; + valbytes[2] = (value >> 16) & 0xff; + valbytes[3] = (value >> 24) & 0xff; + + floatformat_to_double + (&floatformat_ieee_single_little, valbytes, + &fvalue); + + func (stream, "#%.7g\t; 0x%.8lx", fvalue, + value); + } + else + func (stream, "#%ld\t; 0x%.8lx", + (long) ((value & 0x80000000) + ? value | ~0xffffffffl : value), value); + break; + + case 64: + func (stream, "#0x%.8lx%.8lx", hival, value); + break; + + default: + abort (); + } + } + break; + + case 'F': + { + int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); + int num = (given >> 8) & 0x3; + + if (!num) + func (stream, "{d%d}", regno); + else if (num + regno >= 32) + func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); + else + func (stream, "{d%d-d%d}", regno, regno + num); + } + break; + + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int width; + unsigned long value; + + c = arm_decode_bitfield (c, given, &value, &width); + + switch (*c) + { + case 'r': + func (stream, "%s", arm_regnames[value]); + break; + case 'd': + func (stream, "%ld", value); + break; + case 'e': + func (stream, "%ld", (1ul << width) - value); + break; + + case 'S': + case 'T': + case 'U': + /* various width encodings */ + { + int base = 8 << (*c - 'S'); /* 8,16 or 32 */ + int limit; + unsigned low, high; + + c++; + if (*c >= '0' && *c <= '9') + limit = *c - '0'; + else if (*c >= 'a' && *c <= 'f') + limit = *c - 'a' + 10; + else + abort (); + low = limit >> 2; + high = limit & 3; + + if (value < low || value > high) + func (stream, "<illegal width %d>", base << value); + else + func (stream, "%d", base << value); + } + break; + case 'R': + if (given & (1 << 6)) + goto Q; + /* FALLTHROUGH */ + case 'D': + func (stream, "d%ld", value); + break; + case 'Q': + Q: + if (value & 1) + func (stream, "<illegal reg q%ld.5>", value >> 1); + else + func (stream, "q%ld", value >> 1); + break; + + case '`': + c++; + if (value == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if (value == ((1ul << width) - 1)) + func (stream, "%c", *c); + break; + case '?': + func (stream, "%c", c[(1 << width) - (int)value]); + c += 1 << width; + break; + default: + abort (); + } + break; + + default: + abort (); + } + } + } + else + func (stream, "%c", *c); + } + return TRUE; + } + } + return FALSE; +} + /* Print one ARM instruction from PC on INFO->STREAM. */ static void @@ -1721,7 +2669,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) void *stream = info->stream; fprintf_ftype func = info->fprintf_func; - if (print_insn_coprocessor (info, given, FALSE)) + if (print_insn_coprocessor (pc, info, given, FALSE)) + return; + + if (print_insn_neon (info, given, FALSE)) return; for (insn = arm_opcodes; insn->assembler; insn++) @@ -1835,8 +2786,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) break; case 'c': - func (stream, "%s", - arm_conditional [(given >> 28) & 0xf]); + if (((given >> 28) & 0xf) != 0xe) + func (stream, "%s", + arm_conditional [(given >> 28) & 0xf]); break; case 'm': @@ -1857,6 +2809,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'q': + arm_decode_shift (given, func, stream, 0); + break; + case 'o': if ((given & 0x02000000) != 0) { @@ -1867,7 +2823,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "#%d\t; 0x%x", immed, immed); } else - arm_decode_shift (given, func, stream); + arm_decode_shift (given, func, stream, 1); break; case 'p': @@ -1964,102 +2920,51 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { - int bitstart = *c++ - '0'; - int bitend = 0; - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; + int width; + unsigned long value; + c = arm_decode_bitfield (c, given, &value, &width); + switch (*c) { - case '-': - c++; - - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - - if (!bitend) - abort (); - - switch (*c) - { - case 'r': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%s", arm_regnames[reg]); - } - break; - case 'd': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%ld", reg); - } - break; - case 'W': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%ld", reg + 1); - } - break; - case 'x': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "0x%08lx", reg); - - /* Some SWI instructions have special - meanings. */ - if ((given & 0x0fffffff) == 0x0FF00000) - func (stream, "\t; IMB"); - else if ((given & 0x0fffffff) == 0x0FF00001) - func (stream, "\t; IMBRange"); - } - break; - case 'X': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%01lx", reg & 0xf); - } - break; - default: - abort (); - } + case 'r': + func (stream, "%s", arm_regnames[value]); + break; + case 'd': + func (stream, "%ld", value); + break; + case 'b': + func (stream, "%ld", value * 8); + break; + case 'W': + func (stream, "%ld", value + 1); + break; + case 'x': + func (stream, "0x%08lx", value); + + /* Some SWI instructions have special + meanings. */ + if ((given & 0x0fffffff) == 0x0FF00000) + func (stream, "\t; IMB"); + else if ((given & 0x0fffffff) == 0x0FF00001) + func (stream, "\t; IMBRange"); + break; + case 'X': + func (stream, "%01lx", value & 0xf); break; - case '`': c++; - if ((given & (1 << bitstart)) == 0) + if (value == 0) func (stream, "%c", *c); break; case '\'': c++; - if ((given & (1 << bitstart)) != 0) + if (value == ((1ul << width) - 1)) func (stream, "%c", *c); break; case '?': - ++c; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c++); - else - func (stream, "%c", *++c); + func (stream, "%c", c[(1 << width) - (int)value]); + c += 1 << width; break; default: abort (); @@ -2145,6 +3050,40 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "%%"); break; + case 'c': + if (ifthen_state) + func (stream, "%s", arm_conditional[IFTHEN_COND]); + break; + + case 'C': + if (ifthen_state) + func (stream, "%s", arm_conditional[IFTHEN_COND]); + else + func (stream, "s"); + break; + + case 'I': + { + unsigned int tmp; + + ifthen_next_state = given & 0xff; + for (tmp = given << 1; tmp & 0xf; tmp <<= 1) + func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); + func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); + } + break; + + case 'x': + if (ifthen_next_state) + func (stream, "\t; unpredictable branch in IT block\n"); + break; + + case 'X': + if (ifthen_state) + func (stream, "\t; unpredictable <IT:%s>", + arm_conditional[IFTHEN_COND]); + break; + case 'S': { long reg; @@ -2293,14 +3232,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) break; case 'c': - { - /* Must print 0xE as 'al' to distinguish - unconditional B from conditional BAL. */ - if (reg == 0xE) - func (stream, "al"); - else - func (stream, "%s", arm_conditional [reg]); - } + func (stream, "%s", arm_conditional [reg]); break; default: @@ -2373,7 +3305,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) void *stream = info->stream; fprintf_ftype func = info->fprintf_func; - if (print_insn_coprocessor (info, given, TRUE)) + if (print_insn_coprocessor (pc, info, given, TRUE)) + return; + + if (print_insn_neon (info, given, TRUE)) return; for (insn = thumb32_opcodes; insn->assembler; insn++) @@ -2394,6 +3329,22 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "%%"); break; + case 'c': + if (ifthen_state) + func (stream, "%s", arm_conditional[IFTHEN_COND]); + break; + + case 'x': + if (ifthen_next_state) + func (stream, "\t; unpredictable branch in IT block\n"); + break; + + case 'X': + if (ifthen_state) + func (stream, "\t; unpredictable <IT:%s>", + arm_conditional[IFTHEN_COND]); + break; + case 'I': { unsigned int imm12 = 0; @@ -2752,54 +3703,36 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { - int bitstart = *c++ - '0'; - int bitend = 0; - unsigned int val; - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - if (*c == '-') - { - c++; - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - if (!bitend) - abort (); - - val = given >> bitstart; - val &= (2 << (bitend - bitstart)) - 1; - } - else - val = (given >> bitstart) & 1; + int width; + unsigned long val; + c = arm_decode_bitfield (c, given, &val, &width); + switch (*c) { - case 'd': func (stream, "%u", val); break; - case 'W': func (stream, "%u", val * 4); break; + case 'd': func (stream, "%lu", val); break; + case 'W': func (stream, "%lu", val * 4); break; case 'r': func (stream, "%s", arm_regnames[val]); break; case 'c': - if (val == 0xE) - func (stream, "al"); - else - func (stream, "%s", arm_conditional[val]); + func (stream, "%s", arm_conditional[val]); break; case '\'': - if (val) - func (stream, "%c", c[1]); c++; + if (val == ((1ul << width) - 1)) + func (stream, "%c", *c); break; case '`': - if (!val) - func (stream, "%c", c[1]); c++; + if (val == 0) + func (stream, "%c", *c); break; case '?': - func (stream, "%c", val ? c[1] : c[2]); - c += 2; + func (stream, "%c", c[(1 << width) - (int)val]); + c += 1 << width; break; default: @@ -2819,6 +3752,28 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) abort (); } +/* Print data bytes on INFO->STREAM. */ + +static void +print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info, + long given) +{ + switch (info->bytes_per_chunk) + { + case 1: + info->fprintf_func (info->stream, ".byte\t0x%02lx", given); + break; + case 2: + info->fprintf_func (info->stream, ".short\t0x%04lx", given); + break; + case 4: + info->fprintf_func (info->stream, ".word\t0x%08lx", given); + break; + default: + abort (); + } +} + /* Disallow mapping symbols ($a, $b, $d, $t etc) from being displayed in symbol relative addresses. */ @@ -2844,7 +3799,7 @@ parse_arm_disassembler_option (char *option) if (option == NULL) return; - if (strneq (option, "reg-names-", 10)) + if (CONST_STRNEQ (option, "reg-names-")) { int i; @@ -2861,9 +3816,9 @@ parse_arm_disassembler_option (char *option) /* XXX - should break 'option' at following delimiter. */ fprintf (stderr, _("Unrecognised register name set: %s\n"), option); } - else if (strneq (option, "force-thumb", 11)) + else if (CONST_STRNEQ (option, "force-thumb")) force_thumb = 1; - else if (strneq (option, "no-force-thumb", 14)) + else if (CONST_STRNEQ (option, "no-force-thumb")) force_thumb = 0; else /* XXX - should break 'option' at following delimiter. */ @@ -2894,6 +3849,119 @@ parse_disassembler_options (char *options) } } +/* Search back through the insn stream to determine if this instruction is + conditionally executed. */ +static void +find_ifthen_state (bfd_vma pc, struct disassemble_info *info, + bfd_boolean little) +{ + unsigned char b[2]; + unsigned int insn; + int status; + /* COUNT is twice the number of instructions seen. It will be odd if we + just crossed an instruction boundary. */ + int count; + int it_count; + unsigned int seen_it; + bfd_vma addr; + + ifthen_address = pc; + ifthen_state = 0; + + addr = pc; + count = 1; + it_count = 0; + seen_it = 0; + /* Scan backwards looking for IT instructions, keeping track of where + instruction boundaries are. We don't know if something is actually an + IT instruction until we find a definite instruction boundary. */ + for (;;) + { + if (addr == 0 || info->symbol_at_address_func(addr, info)) + { + /* A symbol must be on an instruction boundary, and will not + be within an IT block. */ + if (seen_it && (count & 1)) + break; + + return; + } + addr -= 2; + status = info->read_memory_func (addr, (bfd_byte *)b, 2, info); + if (status) + return; + + if (little) + insn = (b[0]) | (b[1] << 8); + else + insn = (b[1]) | (b[0] << 8); + if (seen_it) + { + if ((insn & 0xf800) < 0xe800) + { + /* Addr + 2 is an instruction boundary. See if this matches + the expected boundary based on the position of the last + IT candidate. */ + if (count & 1) + break; + seen_it = 0; + } + } + if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) + { + /* This could be an IT instruction. */ + seen_it = insn; + it_count = count >> 1; + } + if ((insn & 0xf800) >= 0xe800) + count++; + else + count = (count + 2) | 1; + /* IT blocks contain at most 4 instructions. */ + if (count >= 8 && !seen_it) + return; + } + /* We found an IT instruction. */ + ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); + if ((ifthen_state & 0xf) == 0) + ifthen_state = 0; +} + +/* Try to infer the code type (Arm or Thumb) from a symbol. + Returns nonzero if *MAP_TYPE was set. */ + +static int +get_sym_code_type (struct disassemble_info *info, int n, + enum map_type *map_type) +{ + elf_symbol_type *es; + unsigned int type; + const char *name; + + es = *(elf_symbol_type **)(info->symtab + n); + type = ELF_ST_TYPE (es->internal_elf_sym.st_info); + + /* If the symbol has function type then use that. */ + if (type == STT_FUNC || type == STT_ARM_TFUNC) + { + *map_type = (type == STT_ARM_TFUNC) ? MAP_THUMB : MAP_ARM; + return TRUE; + } + + /* Check for mapping symbols. */ + name = bfd_asymbol_name(info->symtab[n]); + if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') + && (name[2] == 0 || name[2] == '.')) + { + *map_type = ((name[1] == 'a') ? MAP_ARM + : (name[1] == 't') ? MAP_THUMB + : MAP_DATA); + return TRUE; + } + + return FALSE; +} + /* NOTE: There are no checks in these routines that the relevant number of data bytes exist. */ @@ -2903,9 +3971,11 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) unsigned char b[4]; long given; int status; - int is_thumb; - int size; + int is_thumb = FALSE; + int is_data = FALSE; + unsigned int size = 4; void (*printer) (bfd_vma, struct disassemble_info *, long); + bfd_boolean found = FALSE; if (info->disassembler_options) { @@ -2915,9 +3985,91 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) info->disassembler_options = NULL; } - is_thumb = force_thumb; + /* First check the full symtab for a mapping symbol, even if there + are no usable non-mapping symbols for this address. */ + if (info->symtab != NULL + && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) + { + bfd_vma addr; + int n; + int last_sym = -1; + enum map_type type = MAP_ARM; + + if (pc <= last_mapping_addr) + last_mapping_sym = -1; + is_thumb = (last_type == MAP_THUMB); + found = FALSE; + /* Start scanning at the start of the function, or wherever + we finished last time. */ + n = info->symtab_pos + 1; + if (n < last_mapping_sym) + n = last_mapping_sym; + + /* Scan up to the location being disassembled. */ + for (; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc) + break; + if ((info->section == NULL + || info->section == info->symtab[n]->section) + && get_sym_code_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + } + } + + if (!found) + { + n = info->symtab_pos; + if (n < last_mapping_sym - 1) + n = last_mapping_sym - 1; + + /* No mapping symbol found at this address. Look backwards + for a preceeding one. */ + for (; n >= 0; n--) + { + if (get_sym_code_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + break; + } + } + } + + last_mapping_sym = last_sym; + last_type = type; + is_thumb = (last_type == MAP_THUMB); + is_data = (last_type == MAP_DATA); - if (!is_thumb && info->symbols != NULL) + /* Look a little bit ahead to see if we should print out + two or four bytes of data. If there's a symbol, + mapping or otherwise, after two bytes then don't + print more. */ + if (is_data) + { + size = 4 - (pc & 3); + for (n = last_sym + 1; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc) + { + if (addr - pc < size) + size = addr - pc; + break; + } + } + /* If the next symbol is after three bytes, we need to + print only part of the data, so that we can use either + .byte or .short. */ + if (size == 3) + size = (pc & 1) ? 1 : 2; + } + } + + if (info->symbols != NULL) { if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) { @@ -2930,8 +4082,11 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); } - else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour) + else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour + && !found) { + /* If no mapping symbol has been found then fall back to the type + of the function symbol. */ elf_symbol_type * es; unsigned int type; @@ -2942,10 +4097,30 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) } } - info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + if (force_thumb) + is_thumb = TRUE; + + info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; info->bytes_per_line = 4; - if (!is_thumb) + if (is_data) + { + int i; + + /* size was already set above. */ + info->bytes_per_chunk = size; + printer = print_insn_data; + + status = info->read_memory_func (pc, (bfd_byte *)b, size, info); + given = 0; + if (little) + for (i = size - 1; i >= 0; i--) + given = b[i] | (given << 8); + else + for (i = 0; i < (int) size; i++) + given = b[i] | (given << 8); + } + else if (!is_thumb) { /* In ARM mode endianness is a straightforward issue: the instruction is four bytes long and is either ordered 0123 or 3210. */ @@ -2993,6 +4168,18 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) size = 4; } } + + if (ifthen_address != pc) + find_ifthen_state(pc, info, little); + + if (ifthen_state) + { + if ((ifthen_state & 0xf) == 0x8) + ifthen_next_state = 0; + else + ifthen_next_state = (ifthen_state & 0xe0) + | ((ifthen_state & 0xf) << 1); + } } if (status) @@ -3009,6 +4196,12 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) pc = 0; printer (pc, info, given); + + if (is_thumb) + { + ifthen_state = ifthen_next_state; + ifthen_address += size; + } return size; } diff --git a/contrib/binutils/opcodes/config.in b/contrib/binutils/opcodes/config.in index 9d143c3..6dec095 100644 --- a/contrib/binutils/opcodes/config.in +++ b/contrib/binutils/opcodes/config.in @@ -1,102 +1,34 @@ /* config.in. Generated from configure.in by autoheader. */ -/* Define to one of `_getb67', `GETB67', `getb67' for Cray-2 and Cray-YMP - systems. This function is required for `alloca.c' support on those systems. - */ -#undef CRAY_STACKSEG_END - -/* Define to 1 if using `alloca.c'. */ -#undef C_ALLOCA - -/* Define to 1 if NLS is requested */ +/* Define to 1 if translation of program messages to the user's native + language is requested. */ #undef ENABLE_NLS -/* Define to 1 if you have `alloca', as a function or macro. */ -#undef HAVE_ALLOCA - -/* Define to 1 if you have <alloca.h> and it should be used (not on Ultrix). - */ -#undef HAVE_ALLOCA_H - -/* Define to 1 if you have the <argz.h> header file. */ -#undef HAVE_ARGZ_H - -/* Define to 1 if you have the `dcgettext' function. */ -#undef HAVE_DCGETTEXT - /* Define to 1 if you have the declaration of `basename', and to 0 if you don't. */ #undef HAVE_DECL_BASENAME -/* Define to 1 if you have the `getcwd' function. */ -#undef HAVE_GETCWD - -/* Define to 1 if you have the `getpagesize' function. */ -#undef HAVE_GETPAGESIZE - -/* Define as 1 if you have gettext and don't want to use GNU gettext. */ -#undef HAVE_GETTEXT +/* Define to 1 if you have the <dlfcn.h> header file. */ +#undef HAVE_DLFCN_H /* Define to 1 if you have the <inttypes.h> header file. */ #undef HAVE_INTTYPES_H -/* Define if your locale.h file contains LC_MESSAGES. */ -#undef HAVE_LC_MESSAGES - -/* Define to 1 if you have the <limits.h> header file. */ -#undef HAVE_LIMITS_H - -/* Define to 1 if you have the <locale.h> header file. */ -#undef HAVE_LOCALE_H - -/* Define to 1 if you have the <malloc.h> header file. */ -#undef HAVE_MALLOC_H - /* Define to 1 if you have the <memory.h> header file. */ #undef HAVE_MEMORY_H -/* Define to 1 if you have a working `mmap' system call. */ -#undef HAVE_MMAP - -/* Define to 1 if you have the `munmap' function. */ -#undef HAVE_MUNMAP - -/* Define to 1 if you have the <nl_types.h> header file. */ -#undef HAVE_NL_TYPES_H - -/* Define to 1 if you have the `putenv' function. */ -#undef HAVE_PUTENV - -/* Define to 1 if you have the `setenv' function. */ -#undef HAVE_SETENV - -/* Define to 1 if you have the `setlocale' function. */ -#undef HAVE_SETLOCALE - /* Define to 1 if you have the <stdint.h> header file. */ #undef HAVE_STDINT_H /* Define to 1 if you have the <stdlib.h> header file. */ #undef HAVE_STDLIB_H -/* Define if you have the stpcpy function */ -#undef HAVE_STPCPY - -/* Define to 1 if you have the `strcasecmp' function. */ -#undef HAVE_STRCASECMP - -/* Define to 1 if you have the `strchr' function. */ -#undef HAVE_STRCHR - /* Define to 1 if you have the <strings.h> header file. */ #undef HAVE_STRINGS_H /* Define to 1 if you have the <string.h> header file. */ #undef HAVE_STRING_H -/* Define to 1 if you have the <sys/param.h> header file. */ -#undef HAVE_SYS_PARAM_H - /* Define to 1 if you have the <sys/stat.h> header file. */ #undef HAVE_SYS_STAT_H @@ -106,17 +38,9 @@ /* Define to 1 if you have the <unistd.h> header file. */ #undef HAVE_UNISTD_H -/* Define to 1 if you have the <values.h> header file. */ -#undef HAVE_VALUES_H - -/* Define to 1 if you have the `__argz_count' function. */ -#undef HAVE___ARGZ_COUNT - -/* Define to 1 if you have the `__argz_next' function. */ -#undef HAVE___ARGZ_NEXT - -/* Define to 1 if you have the `__argz_stringify' function. */ -#undef HAVE___ARGZ_STRINGIFY +/* Define to the sub-directory in which libtool stores uninstalled libraries. + */ +#undef LT_OBJDIR /* Name of package */ #undef PACKAGE @@ -136,31 +60,8 @@ /* Define to the version of this package. */ #undef PACKAGE_VERSION -/* If using the C implementation of alloca, define if you know the - direction of stack growth for your system; otherwise it will be - automatically deduced at run-time. - STACK_DIRECTION > 0 => grows toward higher addresses - STACK_DIRECTION < 0 => grows toward lower addresses - STACK_DIRECTION = 0 => direction of growth unknown */ -#undef STACK_DIRECTION - /* Define to 1 if you have the ANSI C header files. */ #undef STDC_HEADERS /* Version number of package */ #undef VERSION - -/* Define to empty if `const' does not conform to ANSI C. */ -#undef const - -/* Define to `__inline__' or `__inline' if that's what the C compiler - calls it, or to nothing if 'inline' is not supported under any name. */ -#ifndef __cplusplus -#undef inline -#endif - -/* Define to `long' if <sys/types.h> does not define. */ -#undef off_t - -/* Define to `unsigned' if <sys/types.h> does not define. */ -#undef size_t diff --git a/contrib/binutils/opcodes/configure b/contrib/binutils/opcodes/configure index b692e83..7b91e40 100755 --- a/contrib/binutils/opcodes/configure +++ b/contrib/binutils/opcodes/configure @@ -241,6 +241,155 @@ IFS=" $as_nl" $as_unset CDPATH + +# Check that we are running under the correct shell. +SHELL=${CONFIG_SHELL-/bin/sh} + +case X$lt_ECHO in +X*--fallback-echo) + # Remove one level of quotation (which was required for Make). + ECHO=`echo "$lt_ECHO" | sed 's,\\\\\$\\$0,'$0','` + ;; +esac + +ECHO=${lt_ECHO-echo} +if test "X$1" = X--no-reexec; then + # Discard the --no-reexec flag, and continue. + shift +elif test "X$1" = X--fallback-echo; then + # Avoid inline document here, it may be left over + : +elif test "X`{ $ECHO '\t'; } 2>/dev/null`" = 'X\t' ; then + # Yippee, $ECHO works! + : +else + # Restart under the correct shell. + exec $SHELL "$0" --no-reexec ${1+"$@"} +fi + +if test "X$1" = X--fallback-echo; then + # used as fallback echo + shift + cat <<_LT_EOF +$* +_LT_EOF + exit 0 +fi + +# The HP-UX ksh and POSIX shell print the target directory to stdout +# if CDPATH is set. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +if test -z "$lt_ECHO"; then + if test "X${echo_test_string+set}" != Xset; then + # find a string as large as possible, as long as the shell can cope with it + for cmd in 'sed 50q "$0"' 'sed 20q "$0"' 'sed 10q "$0"' 'sed 2q "$0"' 'echo test'; do + # expected sizes: less than 2Kb, 1Kb, 512 bytes, 16 bytes, ... + if { echo_test_string=`eval $cmd`; } 2>/dev/null && + { test "X$echo_test_string" = "X$echo_test_string"; } 2>/dev/null + then + break + fi + done + fi + + if test "X`{ $ECHO '\t'; } 2>/dev/null`" = 'X\t' && + echo_testing_string=`{ $ECHO "$echo_test_string"; } 2>/dev/null` && + test "X$echo_testing_string" = "X$echo_test_string"; then + : + else + # The Solaris, AIX, and Digital Unix default echo programs unquote + # backslashes. This makes it impossible to quote backslashes using + # echo "$something" | sed 's/\\/\\\\/g' + # + # So, first we look for a working echo in the user's PATH. + + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + for dir in $PATH /usr/ucb; do + IFS="$lt_save_ifs" + if (test -f $dir/echo || test -f $dir/echo$ac_exeext) && + test "X`($dir/echo '\t') 2>/dev/null`" = 'X\t' && + echo_testing_string=`($dir/echo "$echo_test_string") 2>/dev/null` && + test "X$echo_testing_string" = "X$echo_test_string"; then + ECHO="$dir/echo" + break + fi + done + IFS="$lt_save_ifs" + + if test "X$ECHO" = Xecho; then + # We didn't find a better echo, so look for alternatives. + if test "X`{ print -r '\t'; } 2>/dev/null`" = 'X\t' && + echo_testing_string=`{ print -r "$echo_test_string"; } 2>/dev/null` && + test "X$echo_testing_string" = "X$echo_test_string"; then + # This shell has a builtin print -r that does the trick. + ECHO='print -r' + elif { test -f /bin/ksh || test -f /bin/ksh$ac_exeext; } && + test "X$CONFIG_SHELL" != X/bin/ksh; then + # If we have ksh, try running configure again with it. + ORIGINAL_CONFIG_SHELL=${CONFIG_SHELL-/bin/sh} + export ORIGINAL_CONFIG_SHELL + CONFIG_SHELL=/bin/ksh + export CONFIG_SHELL + exec $CONFIG_SHELL "$0" --no-reexec ${1+"$@"} + else + # Try using printf. + ECHO='printf %s\n' + if test "X`{ $ECHO '\t'; } 2>/dev/null`" = 'X\t' && + echo_testing_string=`{ $ECHO "$echo_test_string"; } 2>/dev/null` && + test "X$echo_testing_string" = "X$echo_test_string"; then + # Cool, printf works + : + elif echo_testing_string=`($ORIGINAL_CONFIG_SHELL "$0" --fallback-echo '\t') 2>/dev/null` && + test "X$echo_testing_string" = 'X\t' && + echo_testing_string=`($ORIGINAL_CONFIG_SHELL "$0" --fallback-echo "$echo_test_string") 2>/dev/null` && + test "X$echo_testing_string" = "X$echo_test_string"; then + CONFIG_SHELL=$ORIGINAL_CONFIG_SHELL + export CONFIG_SHELL + SHELL="$CONFIG_SHELL" + export SHELL + ECHO="$CONFIG_SHELL $0 --fallback-echo" + elif echo_testing_string=`($CONFIG_SHELL "$0" --fallback-echo '\t') 2>/dev/null` && + test "X$echo_testing_string" = 'X\t' && + echo_testing_string=`($CONFIG_SHELL "$0" --fallback-echo "$echo_test_string") 2>/dev/null` && + test "X$echo_testing_string" = "X$echo_test_string"; then + ECHO="$CONFIG_SHELL $0 --fallback-echo" + else + # maybe with a smaller string... + prev=: + + for cmd in 'echo test' 'sed 2q "$0"' 'sed 10q "$0"' 'sed 20q "$0"' 'sed 50q "$0"'; do + if { test "X$echo_test_string" = "X`eval $cmd`"; } 2>/dev/null + then + break + fi + prev="$cmd" + done + + if test "$prev" != 'sed 50q "$0"'; then + echo_test_string=`eval $prev` + export echo_test_string + exec ${ORIGINAL_CONFIG_SHELL-${CONFIG_SHELL-/bin/sh}} "$0" ${1+"$@"} + else + # Oops. We lost completely, so just stick with echo. + ECHO=echo + fi + fi + fi + fi + fi +fi + +# Copy echo and quote the copy suitably for passing to libtool from +# the Makefile, instead of quoting the original, which is used later. +lt_ECHO=$ECHO +if test "X$lt_ECHO" = "X$CONFIG_SHELL $0 --fallback-echo"; then + lt_ECHO="$CONFIG_SHELL \\\$\$0 --fallback-echo" +fi + + + + # Name of the host. # hostname on some systems (SVR3.2, Linux) returns a bogus exit status, # so uname gets run too. @@ -309,7 +458,7 @@ ac_includes_default="\ # include <unistd.h> #endif" -ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE AR ac_ct_AR RANLIB ac_ct_RANLIB LN_S LIBTOOL WARN_CFLAGS NO_WERROR MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT INSTALL_LIBBFD_TRUE INSTALL_LIBBFD_FALSE host_noncanonical target_noncanonical bfdlibdir bfdincludedir CPP EGREP ALLOCA USE_NLS MSGFMT GMSGFMT XGETTEXT USE_INCLUDED_LIBINTL CATALOGS CATOBJEXT DATADIRNAME GMOFILES INSTOBJEXT INTLDEPS INTLLIBS INTLOBJS POFILES POSUB INCLUDE_LOCALE_H GT_NO GT_YES MKINSTALLDIRS l CC_FOR_BUILD EXEEXT_FOR_BUILD HDEFINES CGEN_MAINT_TRUE CGEN_MAINT_FALSE cgendir WIN32LDFLAGS WIN32LIBADD archdefs BFD_MACHINES LIBOBJS LTLIBOBJS' +ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE AR ac_ct_AR RANLIB ac_ct_RANLIB LIBTOOL SED EGREP FGREP GREP LD DUMPBIN ac_ct_DUMPBIN NM LN_S lt_ECHO CPP WARN_CFLAGS NO_WERROR MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT INSTALL_LIBBFD_TRUE INSTALL_LIBBFD_FALSE host_noncanonical target_noncanonical bfdlibdir bfdincludedir USE_NLS LIBINTL LIBINTL_DEP INCINTL XGETTEXT GMSGFMT POSUB CATALOGS DATADIRNAME INSTOBJEXT GENCAT CATOBJEXT MKINSTALLDIRS MSGFMT MSGMERGE CC_FOR_BUILD EXEEXT_FOR_BUILD HDEFINES CGEN_MAINT_TRUE CGEN_MAINT_FALSE cgendir WIN32LDFLAGS WIN32LIBADD archdefs BFD_MACHINES LIBOBJS LTLIBOBJS' ac_subst_files='' # Initialize some variables set by options. @@ -852,14 +1001,17 @@ Optional Features: --enable-FEATURE[=ARG] include FEATURE [ARG=yes] --disable-dependency-tracking speeds up one-time build --enable-dependency-tracking do not reject slow dependency extractors - --enable-shared=PKGS build shared libraries default=no - --enable-static=PKGS build static libraries default=yes - --enable-fast-install=PKGS optimize for fast installation default=yes + --enable-shared[=PKGS] + build shared libraries [default=no] + --enable-static[=PKGS] + build static libraries [default=yes] + --enable-fast-install[=PKGS] + optimize for fast installation [default=yes] --disable-libtool-lock avoid locking (might break parallel builds) --enable-targets alternative target configurations --enable-commonbfdlib build shared BFD/opcodes/libiberty library - --enable-werror treat compile warnings as errors - --enable-build-warnings Enable build-time compiler warnings + --enable-werror treat compile warnings as errors + --enable-build-warnings enable build-time compiler warnings --enable-maintainer-mode enable make rules and dependencies not useful (and sometimes confusing) to the casual installer --enable-install-libbfd controls installation of libbfd and related headers @@ -869,9 +1021,9 @@ Optional Features: Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) - --with-gnu-ld assume the C compiler uses GNU ld default=no - --with-pic try to use only PIC/non-PIC objects default=use both - --with-included-gettext use the GNU gettext library included here + --with-pic try to use only PIC/non-PIC objects [default=use + both] + --with-gnu-ld assume the C compiler uses GNU ld [default=no] Some influential environment variables: CC C compiler command @@ -3243,70 +3395,262 @@ fi if test "${enable_shared+set}" = set; then enableval="$enable_shared" p=${PACKAGE-default} -case $enableval in -yes) enable_shared=yes ;; -no) enable_shared=no ;; -*) - enable_shared=no - # Look at the argument we got. We use all the common list separators. - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:," - for pkg in $enableval; do - if test "X$pkg" = "X$p"; then - enable_shared=yes - fi - done - IFS="$ac_save_ifs" - ;; -esac + case $enableval in + yes) enable_shared=yes ;; + no) enable_shared=no ;; + *) + enable_shared=no + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for pkg in $enableval; do + IFS="$lt_save_ifs" + if test "X$pkg" = "X$p"; then + enable_shared=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac else enable_shared=no fi; + + + + + + + + + + +macro_version='2.1a' +macro_revision='1.2435' + + + + + + + + + + + + +ltmain="$ac_aux_dir/ltmain.sh" + +# Set options + +enable_dlopen=no + + +enable_win32_dll=no + + + # Check whether --enable-static or --disable-static was given. if test "${enable_static+set}" = set; then enableval="$enable_static" p=${PACKAGE-default} -case $enableval in -yes) enable_static=yes ;; -no) enable_static=no ;; -*) - enable_static=no - # Look at the argument we got. We use all the common list separators. - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:," - for pkg in $enableval; do - if test "X$pkg" = "X$p"; then - enable_static=yes - fi - done - IFS="$ac_save_ifs" - ;; -esac + case $enableval in + yes) enable_static=yes ;; + no) enable_static=no ;; + *) + enable_static=no + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for pkg in $enableval; do + IFS="$lt_save_ifs" + if test "X$pkg" = "X$p"; then + enable_static=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac else enable_static=yes fi; + + + + + + + + + +# Check whether --with-pic or --without-pic was given. +if test "${with_pic+set}" = set; then + withval="$with_pic" + pic_mode="$withval" +else + pic_mode=default +fi; + +test -z "$pic_mode" && pic_mode=default + + + + + + + # Check whether --enable-fast-install or --disable-fast-install was given. if test "${enable_fast_install+set}" = set; then enableval="$enable_fast_install" p=${PACKAGE-default} -case $enableval in -yes) enable_fast_install=yes ;; -no) enable_fast_install=no ;; -*) - enable_fast_install=no - # Look at the argument we got. We use all the common list separators. - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:," - for pkg in $enableval; do - if test "X$pkg" = "X$p"; then - enable_fast_install=yes - fi - done - IFS="$ac_save_ifs" - ;; -esac + case $enableval in + yes) enable_fast_install=yes ;; + no) enable_fast_install=no ;; + *) + enable_fast_install=no + # Look at the argument we got. We use all the common list separators. + lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," + for pkg in $enableval; do + IFS="$lt_save_ifs" + if test "X$pkg" = "X$p"; then + enable_fast_install=yes + fi + done + IFS="$lt_save_ifs" + ;; + esac else enable_fast_install=yes fi; + + + + + + + +echo "$as_me:$LINENO: checking for a sed that does not truncate output" >&5 +echo $ECHO_N "checking for a sed that does not truncate output... $ECHO_C" >&6 +if test "${lt_cv_path_SED+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + # Loop through the user's path and test for sed and gsed. +# Then use that list of sed's as ones to test for truncation. +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for lt_ac_prog in sed gsed; do + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$lt_ac_prog$ac_exec_ext"; then + lt_ac_sed_list="$lt_ac_sed_list $as_dir/$lt_ac_prog$ac_exec_ext" + fi + done + done +done +IFS=$as_save_IFS +lt_ac_max=0 +lt_ac_count=0 +# Add /usr/xpg4/bin/sed as it is typically found on Solaris +# along with /bin/sed that truncates output. +for lt_ac_sed in $lt_ac_sed_list /usr/xpg4/bin/sed; do + test ! -f $lt_ac_sed && continue + cat /dev/null > conftest.in + lt_ac_count=0 + echo $ECHO_N "0123456789$ECHO_C" >conftest.in + # Check for GNU sed and select it if it is found. + if "$lt_ac_sed" --version 2>&1 < /dev/null | grep 'GNU' > /dev/null; then + lt_cv_path_SED=$lt_ac_sed + break + fi + while true; do + cat conftest.in conftest.in >conftest.tmp + mv conftest.tmp conftest.in + cp conftest.in conftest.nl + echo >>conftest.nl + $lt_ac_sed -e 's/a$//' < conftest.nl >conftest.out || break + cmp -s conftest.out conftest.nl || break + # 10000 chars as input seems more than enough + test $lt_ac_count -gt 10 && break + lt_ac_count=`expr $lt_ac_count + 1` + if test $lt_ac_count -gt $lt_ac_max; then + lt_ac_max=$lt_ac_count + lt_cv_path_SED=$lt_ac_sed + fi + done +done + +fi + +SED=$lt_cv_path_SED + +echo "$as_me:$LINENO: result: $SED" >&5 +echo "${ECHO_T}$SED" >&6 + +test -z "$SED" && SED=sed +Xsed="$SED -e 1s/^X//" + + + + + + + + + + + +echo "$as_me:$LINENO: checking for egrep" >&5 +echo $ECHO_N "checking for egrep... $ECHO_C" >&6 +if test "${ac_cv_prog_egrep+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if echo a | (grep -E '(a|b)') >/dev/null 2>&1 + then ac_cv_prog_egrep='grep -E' + else ac_cv_prog_egrep='egrep' + fi +fi +echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5 +echo "${ECHO_T}$ac_cv_prog_egrep" >&6 + EGREP=$ac_cv_prog_egrep + + +echo "$as_me:$LINENO: checking for fgrep" >&5 +echo $ECHO_N "checking for fgrep... $ECHO_C" >&6 +if test "${ac_cv_prog_fgrep+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if echo 'ab*c' | (grep -F 'ab*c') >/dev/null 2>&1 + then ac_cv_prog_fgrep='grep -F' + else ac_cv_prog_fgrep='fgrep' + fi +fi +echo "$as_me:$LINENO: result: $ac_cv_prog_fgrep" >&5 +echo "${ECHO_T}$ac_cv_prog_fgrep" >&6 + FGREP=$ac_cv_prog_fgrep + + +test -z "$GREP" && GREP=grep + + + + + + + + + + + + + + + + + + + # Check whether --with-gnu-ld or --without-gnu-ld was given. if test "${with_gnu_ld+set}" = set; then withval="$with_gnu_ld" @@ -3317,8 +3661,8 @@ fi; ac_prog=ld if test "$GCC" = yes; then # Check if gcc -print-prog-name=ld gives a path. - echo "$as_me:$LINENO: checking for ld used by GCC" >&5 -echo $ECHO_N "checking for ld used by GCC... $ECHO_C" >&6 + echo "$as_me:$LINENO: checking for ld used by $CC" >&5 +echo $ECHO_N "checking for ld used by $CC... $ECHO_C" >&6 case $host in *-*-mingw*) # gcc leaves a trailing carriage return which upsets mingw @@ -3328,12 +3672,12 @@ echo $ECHO_N "checking for ld used by GCC... $ECHO_C" >&6 esac case $ac_prog in # Accept absolute paths. - [\\/]* | [A-Za-z]:[\\/]*) + [\\/]* | ?:[\\/]*) re_direlt='/[^/][^/]*/\.\./' - # Canonicalize the path of ld - ac_prog=`echo $ac_prog| sed 's%\\\\%/%g'` - while echo $ac_prog | grep "$re_direlt" > /dev/null 2>&1; do - ac_prog=`echo $ac_prog| sed "s%$re_direlt%/%"` + # Canonicalize the pathname of ld + ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'` + while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do + ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"` done test -z "$LD" && LD="$ac_prog" ;; @@ -3357,22 +3701,26 @@ if test "${lt_cv_path_LD+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -z "$LD"; then - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}" + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR for ac_dir in $PATH; do + IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then lt_cv_path_LD="$ac_dir/$ac_prog" # Check to see if the program is GNU ld. I'd rather use --version, - # but apparently some GNU ld's only accept -v. + # but apparently some variants of GNU ld only accept -v. # Break only if it was the GNU/non-GNU ld that we prefer. - if "$lt_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then + case `"$lt_cv_path_LD" -v 2>&1 </dev/null` in + *GNU* | *'with BFD'*) test "$with_gnu_ld" != no && break - else + ;; + *) test "$with_gnu_ld" != yes && break - fi + ;; + esac fi done - IFS="$ac_save_ifs" + IFS="$lt_save_ifs" else lt_cv_path_LD="$LD" # Let the user override the test with a path. fi @@ -3394,32 +3742,31 @@ echo $ECHO_N "checking if the linker ($LD) is GNU ld... $ECHO_C" >&6 if test "${lt_cv_prog_gnu_ld+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - # I'd rather use --version here, but apparently some GNU ld's only accept -v. -if $LD -v 2>&1 </dev/null | egrep '(GNU|with BFD)' 1>&5; then + # I'd rather use --version here, but apparently some GNU lds only accept -v. +case `$LD -v 2>&1 </dev/null` in +*GNU* | *'with BFD'*) lt_cv_prog_gnu_ld=yes -else + ;; +*) lt_cv_prog_gnu_ld=no -fi + ;; +esac fi echo "$as_me:$LINENO: result: $lt_cv_prog_gnu_ld" >&5 echo "${ECHO_T}$lt_cv_prog_gnu_ld" >&6 with_gnu_ld=$lt_cv_prog_gnu_ld -echo "$as_me:$LINENO: checking for $LD option to reload object files" >&5 -echo $ECHO_N "checking for $LD option to reload object files... $ECHO_C" >&6 -if test "${lt_cv_ld_reload_flag+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - lt_cv_ld_reload_flag='-r' -fi -echo "$as_me:$LINENO: result: $lt_cv_ld_reload_flag" >&5 -echo "${ECHO_T}$lt_cv_ld_reload_flag" >&6 -reload_flag=$lt_cv_ld_reload_flag -test -n "$reload_flag" && reload_flag=" $reload_flag" -echo "$as_me:$LINENO: checking for BSD-compatible nm" >&5 -echo $ECHO_N "checking for BSD-compatible nm... $ECHO_C" >&6 + + + + + + + +echo "$as_me:$LINENO: checking for BSD- or MS-compatible name lister (nm)" >&5 +echo $ECHO_N "checking for BSD- or MS-compatible name lister (nm)... $ECHO_C" >&6 if test "${lt_cv_path_NM+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else @@ -3427,35 +3774,173 @@ else # Let the user override the test. lt_cv_path_NM="$NM" else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}" - for ac_dir in $PATH /usr/ccs/bin /usr/ucb /bin; do - test -z "$ac_dir" && ac_dir=. - tmp_nm=$ac_dir/${ac_tool_prefix}nm - if test -f $tmp_nm || test -f $tmp_nm$ac_exeext ; then - # Check to see if the nm accepts a BSD-compat flag. - # Adding the `sed 1q' prevents false positives on HP-UX, which says: - # nm: unknown option "B" ignored - # Tru64's nm complains that /dev/null is an invalid object file - if ($tmp_nm -B /dev/null 2>&1 | sed '1q'; exit 0) | egrep '(/dev/null|Invalid file or object type)' >/dev/null; then - lt_cv_path_NM="$tmp_nm -B" - break - elif ($tmp_nm -p /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then - lt_cv_path_NM="$tmp_nm -p" - break - else - lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but - continue # so that we can try to find one that supports BSD flags + lt_nm_to_check="${ac_tool_prefix}nm" + if test -n "$ac_tool_prefix" && test "$build" = "$host"; then + lt_nm_to_check="$lt_nm_to_check nm" + fi + for lt_tmp_nm in $lt_nm_to_check; do + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + tmp_nm="$ac_dir/$lt_tmp_nm" + if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then + # Check to see if the nm accepts a BSD-compat flag. + # Adding the `sed 1q' prevents false positives on HP-UX, which says: + # nm: unknown option "B" ignored + # Tru64's nm complains that /dev/null is an invalid object file + case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in + */dev/null* | *'Invalid file or object type'*) + lt_cv_path_NM="$tmp_nm -B" + break + ;; + *) + case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in + */dev/null*) + lt_cv_path_NM="$tmp_nm -p" + break + ;; + *) + lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but + continue # so that we can try to find one that supports BSD flags + ;; + esac + ;; + esac fi - fi + done + IFS="$lt_save_ifs" + done + : ${lt_cv_path_NM=no} +fi +fi +echo "$as_me:$LINENO: result: $lt_cv_path_NM" >&5 +echo "${ECHO_T}$lt_cv_path_NM" >&6 +if test "$lt_cv_path_NM" != "no"; then + NM="$lt_cv_path_NM" +else + # Didn't find any BSD compatible name lister, look for dumpbin. + if test -n "$ac_tool_prefix"; then + for ac_prog in "dumpbin -symbols" "link -dump -symbols" + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_DUMPBIN+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if test -n "$DUMPBIN"; then + ac_cv_prog_DUMPBIN="$DUMPBIN" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_DUMPBIN="$ac_tool_prefix$ac_prog" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done + +fi +fi +DUMPBIN=$ac_cv_prog_DUMPBIN +if test -n "$DUMPBIN"; then + echo "$as_me:$LINENO: result: $DUMPBIN" >&5 +echo "${ECHO_T}$DUMPBIN" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +fi + + test -n "$DUMPBIN" && break done - IFS="$ac_save_ifs" - test -z "$lt_cv_path_NM" && lt_cv_path_NM=nm fi +if test -z "$DUMPBIN"; then + ac_ct_DUMPBIN=$DUMPBIN + for ac_prog in "dumpbin -symbols" "link -dump -symbols" +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_ac_ct_DUMPBIN+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if test -n "$ac_ct_DUMPBIN"; then + ac_cv_prog_ac_ct_DUMPBIN="$ac_ct_DUMPBIN" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_DUMPBIN="$ac_prog" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done + +fi +fi +ac_ct_DUMPBIN=$ac_cv_prog_ac_ct_DUMPBIN +if test -n "$ac_ct_DUMPBIN"; then + echo "$as_me:$LINENO: result: $ac_ct_DUMPBIN" >&5 +echo "${ECHO_T}$ac_ct_DUMPBIN" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 fi -NM="$lt_cv_path_NM" -echo "$as_me:$LINENO: result: $NM" >&5 -echo "${ECHO_T}$NM" >&6 + test -n "$ac_ct_DUMPBIN" && break +done +test -n "$ac_ct_DUMPBIN" || ac_ct_DUMPBIN=":" + + DUMPBIN=$ac_ct_DUMPBIN +fi + + + if test "$DUMPBIN" != ":"; then + NM="$DUMPBIN" + fi +fi +test -z "$NM" && NM=nm + + + + + + +echo "$as_me:$LINENO: checking the name lister ($NM) interface" >&5 +echo $ECHO_N "checking the name lister ($NM) interface... $ECHO_C" >&6 +if test "${lt_cv_nm_interface+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + lt_cv_nm_interface="BSD nm" + echo "int some_variable = 0;" > conftest.$ac_ext + (eval echo "\"\$as_me:3929: $ac_compile\"" >&5) + (eval "$ac_compile" 2>conftest.err) + cat conftest.err >&5 + (eval echo "\"\$as_me:3932: $NM \\\"conftest.$ac_objext\\\"\"" >&5) + (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out) + cat conftest.err >&5 + (eval echo "\"\$as_me:3935: output\"" >&5) + cat conftest.out >&5 + if $GREP 'External.*some_variable' conftest.out > /dev/null; then + lt_cv_nm_interface="MS dumpbin" + fi + rm -f conftest* +fi +echo "$as_me:$LINENO: result: $lt_cv_nm_interface" >&5 +echo "${ECHO_T}$lt_cv_nm_interface" >&6 echo "$as_me:$LINENO: checking whether ln -s works" >&5 echo $ECHO_N "checking whether ln -s works... $ECHO_C" >&6 @@ -3468,8 +3953,234 @@ else echo "${ECHO_T}no, using $LN_S" >&6 fi -echo "$as_me:$LINENO: checking how to recognise dependant libraries" >&5 -echo $ECHO_N "checking how to recognise dependant libraries... $ECHO_C" >&6 +# find the maximum length of command line arguments +echo "$as_me:$LINENO: checking the maximum length of command line arguments" >&5 +echo $ECHO_N "checking the maximum length of command line arguments... $ECHO_C" >&6 +if test "${lt_cv_sys_max_cmd_len+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + i=0 + teststring="ABCD" + + case $build_os in + msdosdjgpp*) + # On DJGPP, this test can blow up pretty badly due to problems in libc + # (any single argument exceeding 2000 bytes causes a buffer overrun + # during glob expansion). Even if it were fixed, the result of this + # check would be larger than it should be. + lt_cv_sys_max_cmd_len=12288; # 12K is about right + ;; + + gnu*) + # Under GNU Hurd, this test is not required because there is + # no limit to the length of command line arguments. + # Libtool will interpret -1 as no limit whatsoever + lt_cv_sys_max_cmd_len=-1; + ;; + + cygwin* | mingw*) + # On Win9x/ME, this test blows up -- it succeeds, but takes + # about 5 minutes as the teststring grows exponentially. + # Worse, since 9x/ME are not pre-emptively multitasking, + # you end up with a "frozen" computer, even though with patience + # the test eventually succeeds (with a max line length of 256k). + # Instead, let's just punt: use the minimum linelength reported by + # all of the supported platforms: 8192 (on NT/2K/XP). + lt_cv_sys_max_cmd_len=8192; + ;; + + amigaos*) + # On AmigaOS with pdksh, this test takes hours, literally. + # So we just punt and use a minimum line length of 8192. + lt_cv_sys_max_cmd_len=8192; + ;; + + netbsd* | freebsd* | openbsd* | darwin* | dragonfly*) + # This has been around since 386BSD, at least. Likely further. + if test -x /sbin/sysctl; then + lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax` + elif test -x /usr/sbin/sysctl; then + lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax` + else + lt_cv_sys_max_cmd_len=65536 # usable default for all BSDs + fi + # And add a safety zone + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` + ;; + + interix*) + # We know the value 262144 and hardcode it with a safety zone (like BSD) + lt_cv_sys_max_cmd_len=196608 + ;; + + osf*) + # Dr. Hans Ekkehard Plesser reports seeing a kernel panic running configure + # due to this test when exec_disable_arg_limit is 1 on Tru64. It is not + # nice to cause kernel panics so lets avoid the loop below. + # First set a reasonable default. + lt_cv_sys_max_cmd_len=16384 + # + if test -x /sbin/sysconfig; then + case `/sbin/sysconfig -q proc exec_disable_arg_limit` in + *1*) lt_cv_sys_max_cmd_len=-1 ;; + esac + fi + ;; + sco3.2v5*) + lt_cv_sys_max_cmd_len=102400 + ;; + sysv5* | sco5v6* | sysv4.2uw2*) + kargmax=`grep ARG_MAX /etc/conf/cf.d/stune 2>/dev/null` + if test -n "$kargmax"; then + lt_cv_sys_max_cmd_len=`echo $kargmax | sed 's/.*[ ]//'` + else + lt_cv_sys_max_cmd_len=32768 + fi + ;; + *) + lt_cv_sys_max_cmd_len=`getconf ARG_MAX 2> /dev/null` + if test -n $lt_cv_sys_max_cmd_len; then + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` + else + # Make teststring a little bigger before we do anything with it. + # a 1K string should be a reasonable start. + for i in 1 2 3 4 5 6 7 8 ; do + teststring=$teststring$teststring + done + SHELL=${SHELL-${CONFIG_SHELL-/bin/sh}} + # If test is not a shell built-in, we'll probably end up computing a + # maximum length that is only half of the actual maximum length, but + # we can't tell. + while { test "X"`$SHELL $0 --fallback-echo "X$teststring$teststring" 2>/dev/null` \ + = "XX$teststring$teststring"; } >/dev/null 2>&1 && + test $i != 17 # 1/2 MB should be enough + do + i=`expr $i + 1` + teststring=$teststring$teststring + done + # Only check the string length outside the loop. + lt_cv_sys_max_cmd_len=`expr "X$teststring" : ".*" 2>&1` + teststring= + # Add a significant safety factor because C++ compilers can tack on + # massive amounts of additional arguments before passing them to the + # linker. It appears as though 1/2 is a usable value. + lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 2` + fi + ;; + esac + +fi + +if test -n $lt_cv_sys_max_cmd_len ; then + echo "$as_me:$LINENO: result: $lt_cv_sys_max_cmd_len" >&5 +echo "${ECHO_T}$lt_cv_sys_max_cmd_len" >&6 +else + echo "$as_me:$LINENO: result: none" >&5 +echo "${ECHO_T}none" >&6 +fi +max_cmd_len=$lt_cv_sys_max_cmd_len + + + + + + + +: ${CP="cp -f"} +: ${MV="mv -f"} +: ${RM="rm -f"} + +echo "$as_me:$LINENO: checking whether the shell understands some XSI constructs" >&5 +echo $ECHO_N "checking whether the shell understands some XSI constructs... $ECHO_C" >&6 +# Try some XSI features +xsi_shell=no +( _lt_dummy="a/b/c" + test "${_lt_dummy##*/},${_lt_dummy%/*},"${_lt_dummy%"$_lt_dummy"}, \ + = c,a/b,, ) >/dev/null 2>&1 \ + && xsi_shell=yes +echo "$as_me:$LINENO: result: $xsi_shell" >&5 +echo "${ECHO_T}$xsi_shell" >&6 + + +echo "$as_me:$LINENO: checking whether the shell understands \"+=\"" >&5 +echo $ECHO_N "checking whether the shell understands \"+=\"... $ECHO_C" >&6 +lt_shell_append=no +( foo=bar; set foo baz; eval "$1+=\$2" && test "$foo" = barbaz ) \ + >/dev/null 2>&1 \ + && lt_shell_append=yes +echo "$as_me:$LINENO: result: $lt_shell_append" >&5 +echo "${ECHO_T}$lt_shell_append" >&6 + + +if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then + lt_unset=unset +else + lt_unset=false +fi + + + + + +# test EBCDIC or ASCII +case `echo X|tr X '\101'` in + A) # ASCII based system + # \n is not interpreted correctly by Solaris 8 /usr/ucb/tr + lt_SP2NL='tr \040 \012' + lt_NL2SP='tr \015\012 \040\040' + ;; + *) # EBCDIC based system + lt_SP2NL='tr \100 \n' + lt_NL2SP='tr \r\n \100\100' + ;; +esac + + + + + + + + + +echo "$as_me:$LINENO: checking for $LD option to reload object files" >&5 +echo $ECHO_N "checking for $LD option to reload object files... $ECHO_C" >&6 +if test "${lt_cv_ld_reload_flag+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + lt_cv_ld_reload_flag='-r' +fi +echo "$as_me:$LINENO: result: $lt_cv_ld_reload_flag" >&5 +echo "${ECHO_T}$lt_cv_ld_reload_flag" >&6 +reload_flag=$lt_cv_ld_reload_flag +case $reload_flag in +"" | " "*) ;; +*) reload_flag=" $reload_flag" ;; +esac +reload_cmds='$LD$reload_flag -o $output$reload_objs' +case $host_os in + darwin*) + if test "$GCC" = yes; then + reload_cmds='$LTCC $LTCFLAGS -nostdlib ${wl}-r -o $output$reload_objs' + else + reload_cmds='$LD$reload_flag -o $output$reload_objs' + fi + ;; +esac + + + + + + + + + + +echo "$as_me:$LINENO: checking how to recognize dependent libraries" >&5 +echo $ECHO_N "checking how to recognize dependent libraries... $ECHO_C" >&6 if test "${lt_cv_deplibs_check_method+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else @@ -3482,13 +4193,13 @@ lt_cv_deplibs_check_method='unknown' # `unknown' -- same as none, but documents that we really don't know. # 'pass_all' -- all dependencies passed with no checks. # 'test_compile' -- check by making test program. -# 'file_magic [regex]' -- check by looking for files in library path -# which responds to the $file_magic_cmd with a given egrep regex. +# 'file_magic [[regex]]' -- check by looking for files in library path +# which responds to the $file_magic_cmd with a given extended regex. # If you have `file' or equivalent on your system and you're not sure # whether `pass_all' will *always* work, you probably want this one. case $host_os in -aix*) +aix4* | aix5*) lt_cv_deplibs_check_method=pass_all ;; @@ -3496,39 +4207,42 @@ beos*) lt_cv_deplibs_check_method=pass_all ;; -bsdi4*) +bsdi[45]*) lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)' lt_cv_file_magic_cmd='/usr/bin/file -L' lt_cv_file_magic_test_file=/shlib/libc.so ;; -cygwin* | mingw* |pw32*) - lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?' - lt_cv_file_magic_cmd='$OBJDUMP -f' +cygwin*) + # func_win32_libid is a shell function defined in ltmain.sh + lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' + lt_cv_file_magic_cmd='func_win32_libid' + ;; + +mingw* | pw32*) + # Base MSYS/MinGW do not provide the 'file' command needed by + # func_win32_libid shell function, so use a weaker test based on 'objdump', + # unless we find 'file', for example because we are cross-compiling. + if ( file / ) >/dev/null 2>&1; then + lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' + lt_cv_file_magic_cmd='func_win32_libid' + else + lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?' + lt_cv_file_magic_cmd='$OBJDUMP -f' + fi ;; darwin* | rhapsody*) - # this will be overwritten by pass_all, but leave it in just in case - lt_cv_deplibs_check_method='file_magic Mach-O dynamically linked shared library' - lt_cv_file_magic_cmd='/usr/bin/file -L' - case "$host_os" in - rhapsody* | darwin1.012) - lt_cv_file_magic_test_file='/System/Library/Frameworks/System.framework/System' - ;; - *) # Darwin 1.3 on - lt_cv_file_magic_test_file='/usr/lib/libSystem.dylib' - ;; - esac lt_cv_deplibs_check_method=pass_all ;; -freebsd* | kfreebsd*-gnu) - if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then +freebsd* | dragonfly*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then case $host_cpu in i*86 ) # Not sure whether the presence of OpenBSD here was a mistake. # Let's accept both of them until this is cleared up. - lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD)/i[3-9]86 (compact )?demand paged shared library' + lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[3-9]86 (compact )?demand paged shared library' lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*` ;; @@ -3542,92 +4256,116 @@ gnu*) lt_cv_deplibs_check_method=pass_all ;; -hpux10.20*|hpux11*) +hpux10.20* | hpux11*) + lt_cv_file_magic_cmd=/usr/bin/file case $host_cpu in - hppa*) - lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9].[0-9]) shared library' - lt_cv_file_magic_cmd=/usr/bin/file - lt_cv_file_magic_test_file=/usr/lib/libc.sl - ;; ia64*) lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - IA64' - lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so ;; - esac - ;; - -irix5* | irix6*) - case $host_os in - irix5*) - # this will be overridden with pass_all, but let us keep it just in case - lt_cv_deplibs_check_method="file_magic ELF 32-bit MSB dynamic lib MIPS - version 1" + hppa*64*) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - PA-RISC [0-9].[0-9]' + lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl ;; *) - case $LD in - *-32|*"-32 ") libmagic=32-bit;; - *-n32|*"-n32 ") libmagic=N32;; - *-64|*"-64 ") libmagic=64-bit;; - *) libmagic=never-match;; - esac - # this will be overridden with pass_all, but let us keep it just in case - lt_cv_deplibs_check_method="file_magic ELF ${libmagic} MSB mips-[1234] dynamic lib MIPS - version 1" + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9].[0-9]) shared library' + lt_cv_file_magic_test_file=/usr/lib/libc.sl ;; esac - lt_cv_file_magic_test_file=`echo /lib${libsuff}/libc.so*` + ;; + +interix[3-9]*) + # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|\.a)$' + ;; + +irix5* | irix6* | nonstopux*) + case $LD in + *-32|*"-32 ") libmagic=32-bit;; + *-n32|*"-n32 ") libmagic=N32;; + *-64|*"-64 ") libmagic=64-bit;; + *) libmagic=never-match;; + esac lt_cv_deplibs_check_method=pass_all ;; # This must be Linux ELF. -linux-gnu*) +linux* | k*bsd*-gnu) lt_cv_deplibs_check_method=pass_all ;; -netbsd* | knetbsd*-gnu) - if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then - lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so\.[0-9]+\.[0-9]+$' +netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' else - lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so$' + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|_pic\.a)$' fi ;; -newsos6) +newos6*) lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)' lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=/usr/lib/libnls.so ;; +*nto* | *qnx*) + lt_cv_deplibs_check_method=pass_all + ;; + +openbsd*) + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|\.so|_pic\.a)$' + else + lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' + fi + ;; + osf3* | osf4* | osf5*) - # this will be overridden with pass_all, but let us keep it just in case - lt_cv_deplibs_check_method='file_magic COFF format alpha shared library' - lt_cv_file_magic_test_file=/shlib/libc.so lt_cv_deplibs_check_method=pass_all ;; -sco3.2v5*) +rdos*) lt_cv_deplibs_check_method=pass_all ;; solaris*) lt_cv_deplibs_check_method=pass_all - lt_cv_file_magic_test_file=/lib/libc.so ;; -sysv5uw[78]* | sysv4*uw2*) +sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) lt_cv_deplibs_check_method=pass_all ;; -sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) +sysv4 | sysv4.3*) case $host_vendor in - ncr) - lt_cv_deplibs_check_method=pass_all - ;; motorola) lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]' lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` ;; + ncr) + lt_cv_deplibs_check_method=pass_all + ;; + sequent) + lt_cv_file_magic_cmd='/bin/file' + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' + ;; + sni) + lt_cv_file_magic_cmd='/bin/file' + lt_cv_deplibs_check_method="file_magic ELF [0-9][0-9]*-bit [LM]SB dynamic lib" + lt_cv_file_magic_test_file=/lib/libc.so + ;; + siemens) + lt_cv_deplibs_check_method=pass_all + ;; + pc) + lt_cv_deplibs_check_method=pass_all + ;; esac ;; + +tpf*) + lt_cv_deplibs_check_method=pass_all + ;; esac fi @@ -3635,222 +4373,29 @@ echo "$as_me:$LINENO: result: $lt_cv_deplibs_check_method" >&5 echo "${ECHO_T}$lt_cv_deplibs_check_method" >&6 file_magic_cmd=$lt_cv_file_magic_cmd deplibs_check_method=$lt_cv_deplibs_check_method +test -z "$deplibs_check_method" && deplibs_check_method=unknown -# Autoconf 2.13's AC_OBJEXT and AC_EXEEXT macros only works for C compilers! -# find the maximum length of command line arguments -echo "$as_me:$LINENO: checking the maximum length of command line arguments" >&5 -echo $ECHO_N "checking the maximum length of command line arguments... $ECHO_C" >&6 -if test "${lt_cv_sys_max_cmd_len+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - i=0 - teststring="ABCD" - - case $build_os in - msdosdjgpp*) - # On DJGPP, this test can blow up pretty badly due to problems in libc - # (any single argument exceeding 2000 bytes causes a buffer overrun - # during glob expansion). Even if it were fixed, the result of this - # check would be larger than it should be. - lt_cv_sys_max_cmd_len=12288; # 12K is about right - ;; - - cygwin* | mingw*) - # On Win9x/ME, this test blows up -- it succeeds, but takes - # about 5 minutes as the teststring grows exponentially. - # Worse, since 9x/ME are not pre-emptively multitasking, - # you end up with a "frozen" computer, even though with patience - # the test eventually succeeds (with a max line length of 256k). - # Instead, let's just punt: use the minimum linelength reported by - # all of the supported platforms: 8192 (on NT/2K/XP). - lt_cv_sys_max_cmd_len=8192; - ;; - - amigaos*) - # On AmigaOS with pdksh, this test takes hours, literally. - # So we just punt and use a minimum line length of 8192. - lt_cv_sys_max_cmd_len=8192; - ;; - - netbsd* | freebsd* | openbsd* | darwin* | dragonfly*) - # This has been around since 386BSD, at least. Likely further. - if test -x /sbin/sysctl; then - lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax` - elif test -x /usr/sbin/sysctl; then - lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax` - else - lt_cv_sys_max_cmd_len=65536 # usable default for *BSD - fi - # And add a safety zone - lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` - lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` - ;; - esac - -fi - -if test -n "$lt_cv_sys_max_cmd_len" ; then - echo "$as_me:$LINENO: result: $lt_cv_sys_max_cmd_len" >&5 -echo "${ECHO_T}$lt_cv_sys_max_cmd_len" >&6 -else - echo "$as_me:$LINENO: result: none" >&5 -echo "${ECHO_T}none" >&6 -fi - - -# Only perform the check for file, if the check method requires it -case $deplibs_check_method in -file_magic*) - if test "$file_magic_cmd" = '$MAGIC_CMD'; then - echo "$as_me:$LINENO: checking for ${ac_tool_prefix}file" >&5 -echo $ECHO_N "checking for ${ac_tool_prefix}file... $ECHO_C" >&6 -if test "${lt_cv_path_MAGIC_CMD+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - case $MAGIC_CMD in - /*) - lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. - ;; - ?:/*) - lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path. - ;; - *) - ac_save_MAGIC_CMD="$MAGIC_CMD" - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_dummy="/usr/bin:$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/${ac_tool_prefix}file; then - lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file" - if test -n "$file_magic_test_file"; then - case $deplibs_check_method in - "file_magic "*) - file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`" - MAGIC_CMD="$lt_cv_path_MAGIC_CMD" - if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | - egrep "$file_magic_regex" > /dev/null; then - : - else - cat <<EOF 1>&2 - -*** Warning: the command libtool uses to detect shared libraries, -*** $file_magic_cmd, produces output that libtool cannot recognize. -*** The result is that libtool may fail to recognize shared libraries -*** as such. This will affect the creation of libtool libraries that -*** depend on shared libraries, but programs linked with such libtool -*** libraries will work regardless of this problem. Nevertheless, you -*** may want to report the problem to your system manager and/or to -*** bug-libtool@gnu.org -EOF - fi ;; - esac - fi - break - fi - done - IFS="$ac_save_ifs" - MAGIC_CMD="$ac_save_MAGIC_CMD" - ;; -esac -fi -MAGIC_CMD="$lt_cv_path_MAGIC_CMD" -if test -n "$MAGIC_CMD"; then - echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5 -echo "${ECHO_T}$MAGIC_CMD" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi -if test -z "$lt_cv_path_MAGIC_CMD"; then - if test -n "$ac_tool_prefix"; then - echo "$as_me:$LINENO: checking for file" >&5 -echo $ECHO_N "checking for file... $ECHO_C" >&6 -if test "${lt_cv_path_MAGIC_CMD+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - case $MAGIC_CMD in - /*) - lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. - ;; - ?:/*) - lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path. - ;; - *) - ac_save_MAGIC_CMD="$MAGIC_CMD" - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_dummy="/usr/bin:$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/file; then - lt_cv_path_MAGIC_CMD="$ac_dir/file" - if test -n "$file_magic_test_file"; then - case $deplibs_check_method in - "file_magic "*) - file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`" - MAGIC_CMD="$lt_cv_path_MAGIC_CMD" - if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | - egrep "$file_magic_regex" > /dev/null; then - : - else - cat <<EOF 1>&2 - -*** Warning: the command libtool uses to detect shared libraries, -*** $file_magic_cmd, produces output that libtool cannot recognize. -*** The result is that libtool may fail to recognize shared libraries -*** as such. This will affect the creation of libtool libraries that -*** depend on shared libraries, but programs linked with such libtool -*** libraries will work regardless of this problem. Nevertheless, you -*** may want to report the problem to your system manager and/or to -*** bug-libtool@gnu.org - -EOF - fi ;; - esac - fi - break - fi - done - IFS="$ac_save_ifs" - MAGIC_CMD="$ac_save_MAGIC_CMD" - ;; -esac -fi -MAGIC_CMD="$lt_cv_path_MAGIC_CMD" -if test -n "$MAGIC_CMD"; then - echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5 -echo "${ECHO_T}$MAGIC_CMD" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi - else - MAGIC_CMD=: - fi -fi - fi - ;; -esac if test -n "$ac_tool_prefix"; then - # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. -set dummy ${ac_tool_prefix}ranlib; ac_word=$2 + # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. +set dummy ${ac_tool_prefix}ar; ac_word=$2 echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_RANLIB+set}" = set; then +if test "${ac_cv_prog_AR+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - if test -n "$RANLIB"; then - ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH @@ -3859,7 +4404,7 @@ do test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + ac_cv_prog_AR="${ac_tool_prefix}ar" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi @@ -3868,27 +4413,27 @@ done fi fi -RANLIB=$ac_cv_prog_RANLIB -if test -n "$RANLIB"; then - echo "$as_me:$LINENO: result: $RANLIB" >&5 -echo "${ECHO_T}$RANLIB" >&6 +AR=$ac_cv_prog_AR +if test -n "$AR"; then + echo "$as_me:$LINENO: result: $AR" >&5 +echo "${ECHO_T}$AR" >&6 else echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6 fi fi -if test -z "$ac_cv_prog_RANLIB"; then - ac_ct_RANLIB=$RANLIB - # Extract the first word of "ranlib", so it can be a program name with args. -set dummy ranlib; ac_word=$2 +if test -z "$ac_cv_prog_AR"; then + ac_ct_AR=$AR + # Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then +if test "${ac_cv_prog_ac_ct_AR+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - if test -n "$ac_ct_RANLIB"; then - ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. + if test -n "$ac_ct_AR"; then + ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH @@ -3897,30 +4442,43 @@ do test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_RANLIB="ranlib" + ac_cv_prog_ac_ct_AR="ar" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done - test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":" + test -z "$ac_cv_prog_ac_ct_AR" && ac_cv_prog_ac_ct_AR="false" fi fi -ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB -if test -n "$ac_ct_RANLIB"; then - echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5 -echo "${ECHO_T}$ac_ct_RANLIB" >&6 +ac_ct_AR=$ac_cv_prog_ac_ct_AR +if test -n "$ac_ct_AR"; then + echo "$as_me:$LINENO: result: $ac_ct_AR" >&5 +echo "${ECHO_T}$ac_ct_AR" >&6 else echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6 fi - RANLIB=$ac_ct_RANLIB + AR=$ac_ct_AR else - RANLIB="$ac_cv_prog_RANLIB" + AR="$ac_cv_prog_AR" fi +test -z "$AR" && AR=ar +test -z "$AR_FLAGS" && AR_FLAGS=cru + + + + + + + + + + + if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. set dummy ${ac_tool_prefix}strip; ac_word=$2 @@ -4001,1179 +4559,555 @@ else STRIP="$ac_cv_prog_STRIP" fi +test -z "$STRIP" && STRIP=: -# Check for any special flags to pass to ltconfig. -libtool_flags="--cache-file=$cache_file" -test "$enable_shared" = no && libtool_flags="$libtool_flags --disable-shared" -test "$enable_static" = no && libtool_flags="$libtool_flags --disable-static" -test "$enable_fast_install" = no && libtool_flags="$libtool_flags --disable-fast-install" -test "$GCC" = yes && libtool_flags="$libtool_flags --with-gcc" -test "$lt_cv_prog_gnu_ld" = yes && libtool_flags="$libtool_flags --with-gnu-ld" -# Check whether --enable-libtool-lock or --disable-libtool-lock was given. -if test "${enable_libtool_lock+set}" = set; then - enableval="$enable_libtool_lock" -fi; -test "x$enable_libtool_lock" = xno && libtool_flags="$libtool_flags --disable-lock" -test x"$silent" = xyes && libtool_flags="$libtool_flags --silent" -# Check whether --with-pic or --without-pic was given. -if test "${with_pic+set}" = set; then - withval="$with_pic" - pic_mode="$withval" +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_RANLIB+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 else - pic_mode=default -fi; -test x"$pic_mode" = xyes && libtool_flags="$libtool_flags --prefer-pic" -test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic" - -# Some flags need to be propagated to the compiler or linker for good -# libtool support. -case $host in -*-*-irix6*) - # Find out which ABI we are using. - echo '#line 4038 "configure"' > conftest.$ac_ext - if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; then - if test "$lt_cv_prog_gnu_ld" = yes; then - case `/usr/bin/file conftest.$ac_objext` in - *32-bit*) - LD="${LD-ld} -melf32bsmip" - ;; - *N32*) - LD="${LD-ld} -melf32bmipn32" - ;; - *64-bit*) - LD="${LD-ld} -melf64bmip" - ;; - esac - else - case `/usr/bin/file conftest.$ac_objext` in - *32-bit*) - LD="${LD-ld} -32" - ;; - *N32*) - LD="${LD-ld} -n32" - ;; - *64-bit*) - LD="${LD-ld} -64" - ;; - esac - fi - fi - rm -rf conftest* - ;; - -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; then - case "`/usr/bin/file conftest.o`" in - *ELF-32*) - HPUX_IA64_MODE="32" - ;; - *ELF-64*) - HPUX_IA64_MODE="64" - ;; - esac + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 fi - rm -rf conftest* - ;; +done +done -x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; then - case "`/usr/bin/file conftest.o`" in - *32-bit*) - case $host in - x86_64-*linux*) - LD="${LD-ld} -m elf_i386" - ;; - ppc64-*linux*|powerpc64-*linux*) - LD="${LD-ld} -m elf32ppclinux" - ;; - s390x-*linux*) - LD="${LD-ld} -m elf_s390" - ;; - sparc64-*linux*) - LD="${LD-ld} -m elf32_sparc" - ;; - esac - ;; - *64-bit*) - case $host in - x86_64-*linux*) - LD="${LD-ld} -m elf_x86_64" - ;; - ppc*-*linux*|powerpc*-*linux*) - LD="${LD-ld} -m elf64ppc" - ;; - s390*-*linux*) - LD="${LD-ld} -m elf64_s390" - ;; - sparc*-*linux*) - LD="${LD-ld} -m elf64_sparc" - ;; - esac - ;; - esac - fi - rm -rf conftest* - ;; +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + echo "$as_me:$LINENO: result: $RANLIB" >&5 +echo "${ECHO_T}$RANLIB" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +fi -*-*-sco3.2v5*) - # On SCO OpenServer 5, we need -belf to get full-featured binaries. - SAVE_CFLAGS="$CFLAGS" - CFLAGS="$CFLAGS -belf" - echo "$as_me:$LINENO: checking whether the C compiler needs -belf" >&5 -echo $ECHO_N "checking whether the C compiler needs -belf... $ECHO_C" >&6 -if test "${lt_cv_cc_needs_belf+set}" = set; then +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - - - ac_ext=c -ac_cpp='$CPP $CPPFLAGS' -ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -ac_compiler_gnu=$ac_cv_c_compiler_gnu - - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ - -int -main () -{ - - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext conftest$ac_exeext -if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest$ac_exeext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - lt_cv_cc_needs_belf=yes + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done -lt_cv_cc_needs_belf=no + test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":" +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5 +echo "${ECHO_T}$ac_ct_RANLIB" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 fi -rm -f conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext - ac_ext=c -ac_cpp='$CPP $CPPFLAGS' -ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -ac_compiler_gnu=$ac_cv_c_compiler_gnu + RANLIB=$ac_ct_RANLIB +else + RANLIB="$ac_cv_prog_RANLIB" fi -echo "$as_me:$LINENO: result: $lt_cv_cc_needs_belf" >&5 -echo "${ECHO_T}$lt_cv_cc_needs_belf" >&6 - if test x"$lt_cv_cc_needs_belf" != x"yes"; then - # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf - CFLAGS="$SAVE_CFLAGS" - fi - ;; +test -z "$RANLIB" && RANLIB=: -esac -# Save cache, so that ltconfig can load it -cat >confcache <<\_ACEOF -# This file is a shell script that caches the results of configure -# tests run on this system so they can be shared between configure -# scripts and configure runs, see configure's option --config-cache. -# It is not useful on other systems. If it contains results you don't -# want to keep, you may remove or edit it. -# -# config.status only pays attention to the cache file if you give it -# the --recheck option to rerun configure. -# -# `ac_cv_env_foo' variables (set or unset) will be overridden when -# loading this file, other *unset* `ac_cv_foo' will be assigned the -# following values. -_ACEOF -# The following way of writing the cache mishandles newlines in values, -# but we know of no workaround that is simple, portable, and efficient. -# So, don't put newlines in cache variables' values. -# Ultrix sh set writes to stderr and can't be redirected directly, -# and sets the high bit in the cache file unless we assign to the vars. -{ - (set) 2>&1 | - case `(ac_space=' '; set | grep ac_space) 2>&1` in - *ac_space=\ *) - # `set' does not quote correctly, so add quotes (double-quote - # substitution turns \\\\ into \\, and sed turns \\ into \). - sed -n \ - "s/'/'\\\\''/g; - s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" - ;; - *) - # `set' quotes correctly as required by POSIX, so do not add quotes. - sed -n \ - "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p" - ;; - esac; -} | - sed ' - t clear - : clear - s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ - t end - /^ac_cv_env/!s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ - : end' >>confcache -if diff $cache_file confcache >/dev/null 2>&1; then :; else - if test -w $cache_file; then - test "x$cache_file" != "x/dev/null" && echo "updating cache $cache_file" - cat confcache >$cache_file - else - echo "not updating unwritable cache $cache_file" - fi -fi -rm -f confcache -# Actually configure libtool. ac_aux_dir is where install-sh is found. -AR="$AR" LTCC="$CC" CC="$CC" CFLAGS="$CFLAGS" CPPFLAGS="$CPPFLAGS" \ -MAGIC_CMD="$MAGIC_CMD" LD="$LD" LDFLAGS="$LDFLAGS" LIBS="$LIBS" \ -LN_S="$LN_S" NM="$NM" RANLIB="$RANLIB" STRIP="$STRIP" \ -AS="$AS" DLLTOOL="$DLLTOOL" OBJDUMP="$OBJDUMP" \ -objext="$OBJEXT" exeext="$EXEEXT" reload_flag="$reload_flag" \ -deplibs_check_method="$deplibs_check_method" file_magic_cmd="$file_magic_cmd" \ -${CONFIG_SHELL-/bin/sh} $ac_aux_dir/ltconfig --no-reexec \ -$libtool_flags --no-verify --build="$build" $ac_aux_dir/ltmain.sh $host \ -|| { { echo "$as_me:$LINENO: error: libtool configure failed" >&5 -echo "$as_me: error: libtool configure failed" >&2;} - { (exit 1); exit 1; }; } +# Determine commands to create old-style static archives. +old_archive_cmds='$AR $AR_FLAGS $oldlib$oldobjs$old_deplibs' +old_postinstall_cmds='chmod 644 $oldlib' +old_postuninstall_cmds= -# Reload cache, that may have been modified by ltconfig -if test -r "$cache_file"; then - # Some versions of bash will fail to source /dev/null (special - # files actually), so we avoid doing that. - if test -f "$cache_file"; then - { echo "$as_me:$LINENO: loading cache $cache_file" >&5 -echo "$as_me: loading cache $cache_file" >&6;} - case $cache_file in - [\\/]* | ?:[\\/]* ) . $cache_file;; - *) . ./$cache_file;; - esac - fi -else - { echo "$as_me:$LINENO: creating cache $cache_file" >&5 -echo "$as_me: creating cache $cache_file" >&6;} - >$cache_file +if test -n "$RANLIB"; then + case $host_os in + openbsd*) + old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB -t \$oldlib" + ;; + *) + old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB \$oldlib" + ;; + esac + old_archive_cmds="$old_archive_cmds~\$RANLIB \$oldlib" fi -# This can be used to rebuild libtool when needed -LIBTOOL_DEPS="$ac_aux_dir/ltconfig $ac_aux_dir/ltmain.sh $ac_aux_dir/ltcf-c.sh" - -# Always use our own libtool. -LIBTOOL='$(SHELL) $(top_builddir)/libtool' - -# Redirect the config.log output again, so that the ltconfig log is not -# clobbered by the next message. -exec 5>>./config.log - -# Check whether --enable-targets or --disable-targets was given. -if test "${enable_targets+set}" = set; then - enableval="$enable_targets" - case "${enableval}" in - yes | "") { { echo "$as_me:$LINENO: error: enable-targets option must specify target names or 'all'" >&5 -echo "$as_me: error: enable-targets option must specify target names or 'all'" >&2;} - { (exit 1); exit 1; }; } - ;; - no) enable_targets= ;; - *) enable_targets=$enableval ;; -esac -fi; # Check whether --enable-commonbfdlib or --disable-commonbfdlib was given. -if test "${enable_commonbfdlib+set}" = set; then - enableval="$enable_commonbfdlib" - case "${enableval}" in - yes) commonbfdlib=true ;; - no) commonbfdlib=false ;; - *) { { echo "$as_me:$LINENO: error: bad value ${enableval} for opcodes commonbfdlib option" >&5 -echo "$as_me: error: bad value ${enableval} for opcodes commonbfdlib option" >&2;} - { (exit 1); exit 1; }; } ;; -esac -fi; -GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" -# Check whether --enable-werror or --disable-werror was given. -if test "${enable_werror+set}" = set; then - enableval="$enable_werror" - case "${enableval}" in - yes | y) ERROR_ON_WARNING="yes" ;; - no | n) ERROR_ON_WARNING="no" ;; - *) { { echo "$as_me:$LINENO: error: bad value ${enableval} for --enable-werror" >&5 -echo "$as_me: error: bad value ${enableval} for --enable-werror" >&2;} - { (exit 1); exit 1; }; } ;; - esac -fi; -# Enable -Werror by default when using gcc -if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then - ERROR_ON_WARNING=yes -fi -NO_WERROR= -if test "${ERROR_ON_WARNING}" = yes ; then - GCC_WARN_CFLAGS="$GCC_WARN_CFLAGS -Werror" - NO_WERROR="-Wno-error" -fi -if test "${GCC}" = yes ; then - WARN_CFLAGS="${GCC_WARN_CFLAGS}" -fi -# Check whether --enable-build-warnings or --disable-build-warnings was given. -if test "${enable_build_warnings+set}" = set; then - enableval="$enable_build_warnings" - case "${enableval}" in - yes) WARN_CFLAGS="${GCC_WARN_CFLAGS}";; - no) if test "${GCC}" = yes ; then - WARN_CFLAGS="-w" - fi;; - ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` - WARN_CFLAGS="${GCC_WARN_CFLAGS} ${t}";; - *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` - WARN_CFLAGS="${t} ${GCC_WARN_CFLAGS}";; - *) WARN_CFLAGS=`echo "${enableval}" | sed -e "s/,/ /g"`;; -esac -fi; -if test x"$silent" != x"yes" && test x"$WARN_CFLAGS" != x""; then - echo "Setting warning flags = $WARN_CFLAGS" 6>&1 -fi - ac_config_headers="$ac_config_headers config.h:config.in" -if test -z "$target" ; then - { { echo "$as_me:$LINENO: error: Unrecognized target system type; please check config.sub." >&5 -echo "$as_me: error: Unrecognized target system type; please check config.sub." >&2;} - { (exit 1); exit 1; }; } -fi -echo "$as_me:$LINENO: checking whether to enable maintainer-specific portions of Makefiles" >&5 -echo $ECHO_N "checking whether to enable maintainer-specific portions of Makefiles... $ECHO_C" >&6 - # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. -if test "${enable_maintainer_mode+set}" = set; then - enableval="$enable_maintainer_mode" - USE_MAINTAINER_MODE=$enableval -else - USE_MAINTAINER_MODE=no -fi; - echo "$as_me:$LINENO: result: $USE_MAINTAINER_MODE" >&5 -echo "${ECHO_T}$USE_MAINTAINER_MODE" >&6 -if test $USE_MAINTAINER_MODE = yes; then - MAINTAINER_MODE_TRUE= - MAINTAINER_MODE_FALSE='#' -else - MAINTAINER_MODE_TRUE='#' - MAINTAINER_MODE_FALSE= -fi - MAINT=$MAINTAINER_MODE_TRUE - case ${build_alias} in - "") build_noncanonical=${build} ;; - *) build_noncanonical=${build_alias} ;; -esac - case ${host_alias} in - "") host_noncanonical=${build_noncanonical} ;; - *) host_noncanonical=${host_alias} ;; -esac - case ${target_alias} in - "") target_noncanonical=${host_noncanonical} ;; - *) target_noncanonical=${target_alias} ;; -esac -echo "$as_me:$LINENO: checking whether to install libbfd" >&5 -echo $ECHO_N "checking whether to install libbfd... $ECHO_C" >&6 - # Check whether --enable-install-libbfd or --disable-install-libbfd was given. -if test "${enable_install_libbfd+set}" = set; then - enableval="$enable_install_libbfd" - install_libbfd_p=$enableval -else - if test "${host}" = "${target}" || test "$enable_shared" = "yes"; then - install_libbfd_p=yes - else - install_libbfd_p=no - fi -fi; - echo "$as_me:$LINENO: result: $install_libbfd_p" >&5 -echo "${ECHO_T}$install_libbfd_p" >&6 -if test $install_libbfd_p = yes; then - INSTALL_LIBBFD_TRUE= - INSTALL_LIBBFD_FALSE='#' -else - INSTALL_LIBBFD_TRUE='#' - INSTALL_LIBBFD_FALSE= -fi - # Need _noncanonical variables for this. +# If no C compiler was specified, use CC. +LTCC=${LTCC-"$CC"} +# If no C compiler flags were specified, use CFLAGS. +LTCFLAGS=${LTCFLAGS-"$CFLAGS"} +# Allow CC to be a program name with arguments. +compiler=$CC - # libbfd.a is a host library containing target dependent code - bfdlibdir='$(libdir)' - bfdincludedir='$(includedir)' - if test "${host}" != "${target}"; then - bfdlibdir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/lib' - bfdincludedir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/include' - fi +# Check for command to grab the raw symbol name followed by C symbol from nm. +echo "$as_me:$LINENO: checking command to parse $NM output from $compiler object" >&5 +echo $ECHO_N "checking command to parse $NM output from $compiler object... $ECHO_C" >&6 +if test "${lt_cv_sys_global_symbol_pipe+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else +# These are sane defaults that work on at least a few old systems. +# [They come from Ultrix. What could be older than Ultrix?!! ;)] +# Character class describing NM global symbol codes. +symcode='[BCDEGRST]' +# Regexp to match symbols that can be accessed directly from C. +sympat='\([_A-Za-z][_A-Za-z0-9]*\)' +# Define system-specific variables. +case $host_os in +aix*) + symcode='[BCDT]' + ;; +cygwin* | mingw* | pw32*) + symcode='[ABCDGISTW]' + ;; +hpux*) + if test "$host_cpu" = ia64; then + symcode='[ABCDEGRST]' + fi + ;; +irix* | nonstopux*) + symcode='[BCDEGRST]' + ;; +osf*) + symcode='[BCDEGQRST]' + ;; +solaris*) + symcode='[BDRT]' + ;; +sco3.2v5*) + symcode='[DT]' + ;; +sysv4.2uw2*) + symcode='[DT]' + ;; +sysv5* | sco5v6* | unixware* | OpenUNIX*) + symcode='[ABDT]' + ;; +sysv4) + symcode='[DFNSTU]' + ;; +esac +# If we're using GNU nm, then use its standard symbol codes. +case `$NM -V 2>&1` in +*GNU* | *'with BFD'*) + symcode='[ABCDGIRSTW]' ;; +esac -# host-specific stuff: +# Transform an extracted symbol line into a proper C declaration. +# Some systems (esp. on ia64) link data and code symbols differently, +# so use this general approach. +lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" -ac_ext=c -ac_cpp='$CPP $CPPFLAGS' -ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -ac_compiler_gnu=$ac_cv_c_compiler_gnu -if test -n "$ac_tool_prefix"; then - # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. -set dummy ${ac_tool_prefix}gcc; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_CC+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CC="${ac_tool_prefix}gcc" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done +# Transform an extracted symbol line into symbol name and symbol address +lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\) $/ {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/ {\"\2\", (void *) \&\2},/p'" -fi -fi -CC=$ac_cv_prog_CC -if test -n "$CC"; then - echo "$as_me:$LINENO: result: $CC" >&5 -echo "${ECHO_T}$CC" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi +# Handle CRLF in mingw tool chain +opt_cr= +case $build_os in +mingw*) + opt_cr=`$ECHO 'x\{0,1\}' | tr x '\015'` # option cr in regexp + ;; +esac -fi -if test -z "$ac_cv_prog_CC"; then - ac_ct_CC=$CC - # Extract the first word of "gcc", so it can be a program name with args. -set dummy gcc; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_ac_ct_CC+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if test -n "$ac_ct_CC"; then - ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_CC="gcc" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 +# Try without a prefix underscore, then with it. +for ac_symprfx in "" "_"; do + + # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol. + symxfrm="\\1 $ac_symprfx\\2 \\2" + + # Write the raw and C identifiers. + if test "$lt_cv_nm_interface" = "MS dumpbin"; then + # Fake it for dumpbin and say T for any non-static function + # and D for any global variable. + # Also find C++ and __fastcall symbols from MSVC++, + # which start with @ or ?. + lt_cv_sys_global_symbol_pipe="$AWK '"\ +" {last_section=section; section=\$ 3};"\ +" /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\ +" \$ 0!~/External *\|/{next};"\ +" / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\ +" {if(hide[section]) next};"\ +" {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\ +" {split(\$ 0, a, /\||\r/); split(a[2], s)};"\ +" s[1]~/^[@?]/{print s[1], s[1]; next};"\ +" s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\ +" ' prfx=^$ac_symprfx" + else + lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[ ]\($symcode$symcode*\)[ ][ ]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'" fi -done -done -fi -fi -ac_ct_CC=$ac_cv_prog_ac_ct_CC -if test -n "$ac_ct_CC"; then - echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 -echo "${ECHO_T}$ac_ct_CC" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi - - CC=$ac_ct_CC -else - CC="$ac_cv_prog_CC" -fi + # Check to see that the pipe works correctly. + pipe_works=no -if test -z "$CC"; then - if test -n "$ac_tool_prefix"; then - # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. -set dummy ${ac_tool_prefix}cc; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_CC+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CC="${ac_tool_prefix}cc" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done + rm -f conftest* + cat > conftest.$ac_ext <<_LT_EOF +#ifdef __cplusplus +extern "C" { +#endif +char nm_test_var; +void nm_test_func(void); +void nm_test_func(void){} +#ifdef __cplusplus +} +#endif +int main(){nm_test_var='a';nm_test_func();return(0);} +_LT_EOF -fi -fi -CC=$ac_cv_prog_CC -if test -n "$CC"; then - echo "$as_me:$LINENO: result: $CC" >&5 -echo "${ECHO_T}$CC" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi + if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; then + # Now try to grab the symbols. + nlist=conftest.nm + if { (eval echo "$as_me:$LINENO: \"$NM conftest.$ac_objext \| $lt_cv_sys_global_symbol_pipe \> $nlist\"") >&5 + (eval $NM conftest.$ac_objext \| $lt_cv_sys_global_symbol_pipe \> $nlist) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && test -s "$nlist"; then + # Try sorting and uniquifying the output. + if sort "$nlist" | uniq > "$nlist"T; then + mv -f "$nlist"T "$nlist" + else + rm -f "$nlist"T + fi -fi -if test -z "$ac_cv_prog_CC"; then - ac_ct_CC=$CC - # Extract the first word of "cc", so it can be a program name with args. -set dummy cc; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_ac_ct_CC+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if test -n "$ac_ct_CC"; then - ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_CC="cc" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done + # Make sure that we snagged all the symbols we need. + if $GREP ' nm_test_var$' "$nlist" >/dev/null; then + if $GREP ' nm_test_func$' "$nlist" >/dev/null; then + cat <<_LT_EOF > conftest.$ac_ext +#ifdef __cplusplus +extern "C" { +#endif -fi -fi -ac_ct_CC=$ac_cv_prog_ac_ct_CC -if test -n "$ac_ct_CC"; then - echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 -echo "${ECHO_T}$ac_ct_CC" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi +_LT_EOF + # Now generate the symbol file. + eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext' - CC=$ac_ct_CC -else - CC="$ac_cv_prog_CC" -fi + cat <<_LT_EOF >> conftest.$ac_ext -fi -if test -z "$CC"; then - # Extract the first word of "cc", so it can be a program name with args. -set dummy cc; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_CC+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - ac_prog_rejected=no -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then - ac_prog_rejected=yes - continue - fi - ac_cv_prog_CC="cc" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done +/* The mapping between symbol names and symbols. */ +const struct { + const char *name; + void *address; +} +lt__PROGRAM__LTX_preloaded_symbols[] = +{ + { "@PROGRAM@", (void *) 0 }, +_LT_EOF + $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/ {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext + cat <<\_LT_EOF >> conftest.$ac_ext + {0, (void *) 0} +}; + +/* This works around a problem in FreeBSD linker */ +#ifdef FREEBSD_WORKAROUND +static const void *lt_preloaded_setup() { + return lt__PROGRAM__LTX_preloaded_symbols; +} +#endif -if test $ac_prog_rejected = yes; then - # We found a bogon in the path, so make sure we never use it. - set dummy $ac_cv_prog_CC - shift - if test $# != 0; then - # We chose a different compiler from the bogus one. - # However, it has the same basename, so the bogon will be chosen - # first if we set CC to just the basename; use the full file name. - shift - ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" +#ifdef __cplusplus +} +#endif +_LT_EOF + # Now try linking the two files. + mv conftest.$ac_objext conftstm.$ac_objext + lt_save_LIBS="$LIBS" + lt_save_CFLAGS="$CFLAGS" + LIBS="conftstm.$ac_objext" + CFLAGS="$CFLAGS$lt_prog_compiler_no_builtin_flag" + if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 + (eval $ac_link) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && test -s conftest${ac_exeext}; then + pipe_works=yes + fi + LIBS="$lt_save_LIBS" + CFLAGS="$lt_save_CFLAGS" + else + echo "cannot find nm_test_func in $nlist" >&5 + fi + else + echo "cannot find nm_test_var in $nlist" >&5 + fi + else + echo "cannot run $lt_cv_sys_global_symbol_pipe" >&5 + fi + else + echo "$progname: failed program was:" >&5 + cat conftest.$ac_ext >&5 fi -fi -fi -fi -CC=$ac_cv_prog_CC -if test -n "$CC"; then - echo "$as_me:$LINENO: result: $CC" >&5 -echo "${ECHO_T}$CC" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi + rm -f conftest* conftst* -fi -if test -z "$CC"; then - if test -n "$ac_tool_prefix"; then - for ac_prog in cl - do - # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. -set dummy $ac_tool_prefix$ac_prog; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_CC+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CC="$ac_tool_prefix$ac_prog" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 + # Do not use the global_symbol_pipe unless it works. + if test "$pipe_works" = yes; then + break + else + lt_cv_sys_global_symbol_pipe= fi done -done fi -fi -CC=$ac_cv_prog_CC -if test -n "$CC"; then - echo "$as_me:$LINENO: result: $CC" >&5 -echo "${ECHO_T}$CC" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi - test -n "$CC" && break - done +if test -z "$lt_cv_sys_global_symbol_pipe"; then + lt_cv_sys_global_symbol_to_cdecl= fi -if test -z "$CC"; then - ac_ct_CC=$CC - for ac_prog in cl -do - # Extract the first word of "$ac_prog", so it can be a program name with args. -set dummy $ac_prog; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_ac_ct_CC+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 +if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then + echo "$as_me:$LINENO: result: failed" >&5 +echo "${ECHO_T}failed" >&6 else - if test -n "$ac_ct_CC"; then - ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_CC="$ac_prog" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done - -fi -fi -ac_ct_CC=$ac_cv_prog_ac_ct_CC -if test -n "$ac_ct_CC"; then - echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 -echo "${ECHO_T}$ac_ct_CC" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 + echo "$as_me:$LINENO: result: ok" >&5 +echo "${ECHO_T}ok" >&6 fi - test -n "$ac_ct_CC" && break -done - CC=$ac_ct_CC -fi -fi -test -z "$CC" && { { echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH -See \`config.log' for more details." >&5 -echo "$as_me: error: no acceptable C compiler found in \$PATH -See \`config.log' for more details." >&2;} - { (exit 1); exit 1; }; } -# Provide some information about the compiler. -echo "$as_me:$LINENO:" \ - "checking for C compiler version" >&5 -ac_compiler=`set X $ac_compile; echo $2` -{ (eval echo "$as_me:$LINENO: \"$ac_compiler --version </dev/null >&5\"") >&5 - (eval $ac_compiler --version </dev/null >&5) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } -{ (eval echo "$as_me:$LINENO: \"$ac_compiler -v </dev/null >&5\"") >&5 - (eval $ac_compiler -v </dev/null >&5) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } -{ (eval echo "$as_me:$LINENO: \"$ac_compiler -V </dev/null >&5\"") >&5 - (eval $ac_compiler -V </dev/null >&5) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } -echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5 -echo $ECHO_N "checking whether we are using the GNU C compiler... $ECHO_C" >&6 -if test "${ac_cv_c_compiler_gnu+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -int -main () -{ -#ifndef __GNUC__ - choke me -#endif - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 - ac_status=$? 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- grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - ac_cv_prog_cc_g=yes -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 -ac_cv_prog_cc_g=no -fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -fi -echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5 -echo "${ECHO_T}$ac_cv_prog_cc_g" >&6 -if test "$ac_test_CFLAGS" = set; then - CFLAGS=$ac_save_CFLAGS -elif test $ac_cv_prog_cc_g = yes; then - if test "$GCC" = yes; then - CFLAGS="-g -O2" - else - CFLAGS="-g" - fi -else - if test "$GCC" = yes; then - CFLAGS="-O2" - else - CFLAGS= - fi -fi -echo "$as_me:$LINENO: checking for $CC option to accept ANSI C" >&5 -echo $ECHO_N "checking for $CC option to accept ANSI C... $ECHO_C" >&6 -if test "${ac_cv_prog_cc_stdc+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - ac_cv_prog_cc_stdc=no -ac_save_CC=$CC -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <stdarg.h> -#include <stdio.h> -#include <sys/types.h> -#include <sys/stat.h> -/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ -struct buf { int x; }; -FILE * (*rcsopen) (struct buf *, struct stat *, int); -static char *e (p, i) - char **p; - int i; -{ - return p[i]; -} -static char *f (char * (*g) (char **, int), char **p, ...) -{ - char *s; - va_list v; - va_start (v,p); - s = g (p, va_arg (v,int)); - va_end (v); - return s; -} -/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has - function prototypes and stuff, but not '\xHH' hex character constants. - These don't provoke an error unfortunately, instead are silently treated - as 'x'. The following induces an error, until -std1 is added to get - proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an - array size at least. It's necessary to write '\x00'==0 to get something - that's true only with -std1. */ -int osf4_cc_array ['\x00' == 0 ? 1 : -1]; -int test (int i, double x); -struct s1 {int (*f) (int a);}; -struct s2 {int (*f) (double a);}; -int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); -int argc; -char **argv; -int -main () -{ -return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; - ; - return 0; -} -_ACEOF -# Don't try gcc -ansi; that turns off useful extensions and -# breaks some systems' header files. -# AIX -qlanglvl=ansi -# Ultrix and OSF/1 -std1 -# HP-UX 10.20 and later -Ae -# HP-UX older versions -Aa -D_HPUX_SOURCE -# SVR4 -Xc -D__EXTENSIONS__ -for ac_arg in "" -qlanglvl=ansi -std1 -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" -do - CC="$ac_save_CC $ac_arg" - rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - ac_cv_prog_cc_stdc=$ac_arg -break -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 -fi -rm -f conftest.err conftest.$ac_objext -done -rm -f conftest.$ac_ext conftest.$ac_objext -CC=$ac_save_CC -fi +# Check whether --enable-libtool-lock or --disable-libtool-lock was given. +if test "${enable_libtool_lock+set}" = set; then + enableval="$enable_libtool_lock" -case "x$ac_cv_prog_cc_stdc" in - x|xno) - echo "$as_me:$LINENO: result: none needed" >&5 -echo "${ECHO_T}none needed" >&6 ;; - *) - echo "$as_me:$LINENO: result: $ac_cv_prog_cc_stdc" >&5 -echo "${ECHO_T}$ac_cv_prog_cc_stdc" >&6 - CC="$CC $ac_cv_prog_cc_stdc" ;; -esac +fi; +test "x$enable_libtool_lock" != xno && enable_libtool_lock=yes -# Some people use a C++ compiler to compile C. Since we use `exit', -# in C++ we need to declare it. In case someone uses the same compiler -# for both compiling C and C++ we need to have the C++ compiler decide -# the declaration of exit, since it's the most demanding environment. -cat >conftest.$ac_ext <<_ACEOF -#ifndef __cplusplus - choke me -#endif -_ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - for ac_declaration in \ - '' \ - 'extern "C" void std::exit (int) throw (); using std::exit;' \ - 'extern "C" void std::exit (int); using std::exit;' \ - 'extern "C" void exit (int) throw ();' \ - 'extern "C" void exit (int);' \ - 'void exit (int);' -do - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -$ac_declaration -#include <stdlib.h> -int -main () -{ -exit (42); - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 +# Some flags need to be propagated to the compiler or linker for good +# libtool support. +case $host in +ia64-*-hpux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>&5 ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 + (exit $ac_status); }; then + case `/usr/bin/file conftest.$ac_objext` in + *ELF-32*) + HPUX_IA64_MODE="32" + ;; + *ELF-64*) + HPUX_IA64_MODE="64" + ;; + esac + fi + rm -rf conftest* + ;; +*-*-irix6*) + # Find out which ABI we are using. + echo '#line 4990 "configure"' > conftest.$ac_ext + if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 + (exit $ac_status); }; then + if test "$lt_cv_prog_gnu_ld" = yes; then + case `/usr/bin/file conftest.$ac_objext` in + *32-bit*) + LD="${LD-ld} -melf32bsmip" + ;; + *N32*) + LD="${LD-ld} -melf32bmipn32" + ;; + *64-bit*) + LD="${LD-ld} -melf64bmip" + ;; + esac + else + case `/usr/bin/file conftest.$ac_objext` in + *32-bit*) + LD="${LD-ld} -32" + ;; + *N32*) + LD="${LD-ld} -n32" + ;; + *64-bit*) + LD="${LD-ld} -64" + ;; + esac + fi + fi + rm -rf conftest* + ;; + +x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ +s390*-*linux*|s390*-*tpf*|sparc*-*linux*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - : + (exit $ac_status); }; then + case `/usr/bin/file conftest.o` in + *32-bit*) + case $host in + x86_64-*kfreebsd*-gnu) + LD="${LD-ld} -m elf_i386_fbsd" + ;; + x86_64-*linux*) + LD="${LD-ld} -m elf_i386" + ;; + ppc64-*linux*|powerpc64-*linux*) + LD="${LD-ld} -m elf32ppclinux" + ;; + s390x-*linux*) + LD="${LD-ld} -m elf_s390" + ;; + sparc64-*linux*) + LD="${LD-ld} -m elf32_sparc" + ;; + esac + ;; + *64-bit*) + case $host in + x86_64-*kfreebsd*-gnu) + LD="${LD-ld} -m elf_x86_64_fbsd" + ;; + x86_64-*linux*) + LD="${LD-ld} -m elf_x86_64" + ;; + ppc*-*linux*|powerpc*-*linux*) + LD="${LD-ld} -m elf64ppc" + ;; + s390*-*linux*|s390*-*tpf*) + LD="${LD-ld} -m elf64_s390" + ;; + sparc*-*linux*) + LD="${LD-ld} -m elf64_sparc" + ;; + esac + ;; + esac + fi + rm -rf conftest* + ;; + +*-*-sco3.2v5*) + # On SCO OpenServer 5, we need -belf to get full-featured binaries. + SAVE_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS -belf" + echo "$as_me:$LINENO: checking whether the C compiler needs -belf" >&5 +echo $ECHO_N "checking whether the C compiler needs -belf... $ECHO_C" >&6 +if test "${lt_cv_cc_needs_belf+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 + ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu -continue -fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext - cat >conftest.$ac_ext <<_ACEOF + cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -$ac_declaration + int main () { -exit (42); + ; return 0; } _ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 +rm -f conftest.$ac_objext conftest$ac_exeext +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -5187,120 +5121,57 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - break -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - -fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -done -rm -f conftest* -if test -n "$ac_declaration"; then - echo '#ifdef __cplusplus' >>confdefs.h - echo $ac_declaration >>confdefs.h - echo '#endif' >>confdefs.h -fi - + lt_cv_cc_needs_belf=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 +lt_cv_cc_needs_belf=no fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -ac_ext=c +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu - -ALL_LINGUAS="fr sv tr es da de id pt_BR ro nl fi vi ga zh_CN" -if test -n "$ac_tool_prefix"; then - # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. -set dummy ${ac_tool_prefix}ranlib; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_RANLIB+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if test -n "$RANLIB"; then - ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done - -fi -fi -RANLIB=$ac_cv_prog_RANLIB -if test -n "$RANLIB"; then - echo "$as_me:$LINENO: result: $RANLIB" >&5 -echo "${ECHO_T}$RANLIB" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi - fi -if test -z "$ac_cv_prog_RANLIB"; then - ac_ct_RANLIB=$RANLIB - # Extract the first word of "ranlib", so it can be a program name with args. -set dummy ranlib; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if test -n "$ac_ct_RANLIB"; then - ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. -else -as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_RANLIB="ranlib" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 +echo "$as_me:$LINENO: result: $lt_cv_cc_needs_belf" >&5 +echo "${ECHO_T}$lt_cv_cc_needs_belf" >&6 + if test x"$lt_cv_cc_needs_belf" != x"yes"; then + # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf + CFLAGS="$SAVE_CFLAGS" fi -done -done - - test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":" -fi -fi -ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB -if test -n "$ac_ct_RANLIB"; then - echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5 -echo "${ECHO_T}$ac_ct_RANLIB" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi + ;; +sparc*-*solaris*) + # Find out which ABI we are using. + echo 'int i;' > conftest.$ac_ext + if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; then + case `/usr/bin/file conftest.o` in + *64-bit*) + case $lt_cv_prog_gnu_ld in + yes*) LD="${LD-ld} -m elf64_sparc" ;; + *) LD="${LD-ld} -64" ;; + esac + ;; + esac + fi + rm -rf conftest* + ;; +esac - RANLIB=$ac_ct_RANLIB -else - RANLIB="$ac_cv_prog_RANLIB" -fi +need_locks="$enable_libtool_lock" ac_ext=c ac_cpp='$CPP $CPPFLAGS' @@ -5537,21 +5408,6 @@ ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $ ac_compiler_gnu=$ac_cv_c_compiler_gnu -echo "$as_me:$LINENO: checking for egrep" >&5 -echo $ECHO_N "checking for egrep... $ECHO_C" >&6 -if test "${ac_cv_prog_egrep+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if echo a | (grep -E '(a|b)') >/dev/null 2>&1 - then ac_cv_prog_egrep='grep -E' - else ac_cv_prog_egrep='egrep' - fi -fi -echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5 -echo "${ECHO_T}$ac_cv_prog_egrep" >&6 - EGREP=$ac_cv_prog_egrep - - echo "$as_me:$LINENO: checking for ANSI C header files" >&5 echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6 if test "${ac_cv_header_stdc+set}" = set; then @@ -5718,132 +5574,34 @@ _ACEOF fi -echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5 -echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6 -if test "${ac_cv_c_const+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ +# On IRIX 5.3, sys/types and inttypes.h are conflicting. + + -int -main () -{ -/* FIXME: Include the comments suggested by Paul. */ -#ifndef __cplusplus - /* Ultrix mips cc rejects this. */ - typedef int charset[2]; - const charset x; - /* SunOS 4.1.1 cc rejects this. */ - char const *const *ccp; - char **p; - /* NEC SVR4.0.2 mips cc rejects this. */ - struct point {int x, y;}; - static struct point const zero = {0,0}; - /* AIX XL C 1.02.0.0 rejects this. - It does not let you subtract one const X* pointer from another in - an arm of an if-expression whose if-part is not a constant - expression */ - const char *g = "string"; - ccp = &g + (g ? g-g : 0); - /* HPUX 7.0 cc rejects these. */ - ++ccp; - p = (char**) ccp; - ccp = (char const *const *) p; - { /* SCO 3.2v4 cc rejects this. */ - char *t; - char const *s = 0 ? (char *) 0 : (char const *) 0; - - *t++ = 0; - } - { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ - int x[] = {25, 17}; - const int *foo = &x[0]; - ++foo; - } - { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ - typedef const int *iptr; - iptr p = 0; - ++p; - } - { /* AIX XL C 1.02.0.0 rejects this saying - "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ - struct s { int j; const int *ap[3]; }; - struct s *b; b->j = 5; - } - { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ - const int foo = 10; - } -#endif - ; - return 0; -} -_ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - ac_cv_c_const=yes -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 -ac_cv_c_const=no -fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -fi -echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5 -echo "${ECHO_T}$ac_cv_c_const" >&6 -if test $ac_cv_c_const = no; then -cat >>confdefs.h <<\_ACEOF -#define const -_ACEOF -fi -echo "$as_me:$LINENO: checking for inline" >&5 -echo $ECHO_N "checking for inline... $ECHO_C" >&6 -if test "${ac_cv_c_inline+set}" = set; then + +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do +as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` +echo "$as_me:$LINENO: checking for $ac_header" >&5 +echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6 +if eval "test \"\${$as_ac_Header+set}\" = set"; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - ac_cv_c_inline=no -for ac_kw in inline __inline__ __inline; do cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -#ifndef __cplusplus -typedef int foo_t; -static $ac_kw foo_t static_foo () {return 0; } -$ac_kw foo_t foo () {return 0; } -#endif +$ac_includes_default +#include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 @@ -5867,47 +5625,29 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - ac_cv_c_inline=$ac_kw; break + eval "$as_ac_Header=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 +eval "$as_ac_Header=no" fi rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -done - fi -echo "$as_me:$LINENO: result: $ac_cv_c_inline" >&5 -echo "${ECHO_T}$ac_cv_c_inline" >&6 - - -case $ac_cv_c_inline in - inline | yes) ;; - *) - case $ac_cv_c_inline in - no) ac_val=;; - *) ac_val=$ac_cv_c_inline;; - esac - cat >>confdefs.h <<_ACEOF -#ifndef __cplusplus -#define inline $ac_val -#endif +echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5 +echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6 +if test `eval echo '${'$as_ac_Header'}'` = yes; then + cat >>confdefs.h <<_ACEOF +#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF - ;; -esac - -# On IRIX 5.3, sys/types and inttypes.h are conflicting. - - - - +fi +done -for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ - inttypes.h stdint.h unistd.h +for ac_header in dlfcn.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` echo "$as_me:$LINENO: checking for $ac_header" >&5 @@ -5968,98 +5708,1364 @@ fi done -echo "$as_me:$LINENO: checking for off_t" >&5 -echo $ECHO_N "checking for off_t... $ECHO_C" >&6 -if test "${ac_cv_type_off_t+set}" = set; then + +# This can be used to rebuild libtool when needed +LIBTOOL_DEPS="$ltmain" + +# Always use our own libtool. +LIBTOOL='$(SHELL) $(top_builddir)/libtool' + + + + + + + + + + + + + + + + + + + + + + + + + +test -z "$LN_S" && LN_S="ln -s" + + + + + + + + + + + + + + +if test -n "${ZSH_VERSION+set}" ; then + setopt NO_GLOB_SUBST +fi + +echo "$as_me:$LINENO: checking for objdir" >&5 +echo $ECHO_N "checking for objdir... $ECHO_C" >&6 +if test "${lt_cv_objdir+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -$ac_includes_default -int -main () -{ -if ((off_t *) 0) - return 0; -if (sizeof (off_t)) - return 0; - ; - return 0; -} + rm -f .libs 2>/dev/null +mkdir .libs 2>/dev/null +if test -d .libs; then + lt_cv_objdir=.libs +else + # MS-DOS does not allow filenames that begin with a dot. + lt_cv_objdir=_libs +fi +rmdir .libs 2>/dev/null +fi +echo "$as_me:$LINENO: result: $lt_cv_objdir" >&5 +echo "${ECHO_T}$lt_cv_objdir" >&6 +objdir=$lt_cv_objdir + + + + + +cat >>confdefs.h <<_ACEOF +#define LT_OBJDIR "$lt_cv_objdir/" _ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - ac_cv_type_off_t=yes + + + + + + + + + + + + + + + + + +case $host_os in +aix3*) + # AIX sometimes has problems with the GCC collect2 program. For some + # reason, if we set the COLLECT_NAMES environment variable, the problems + # vanish in a puff of smoke. + if test "X${COLLECT_NAMES+set}" != Xset; then + COLLECT_NAMES= + export COLLECT_NAMES + fi + ;; +esac + +# Sed substitution that helps us do robust quoting. It backslashifies +# metacharacters that are still active within double-quoted strings. +sed_quote_subst='s/\(["`$\\]\)/\\\1/g' + +# Same as above, but do not quote variable references. +double_quote_subst='s/\(["`\\]\)/\\\1/g' + +# Sed substitution to delay expansion of an escaped shell variable in a +# double_quote_subst'ed string. +delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g' + +# Sed substitution to delay expansion of an escaped single quote. +delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g' + +# Sed substitution to avoid accidental globbing in evaled expressions +no_glob_subst='s/\*/\\\*/g' + +# Global variables: +ofile=libtool +can_build_shared=yes + +# All known linkers require a `.a' archive for static linking (except MSVC, +# which needs '.lib'). +libext=a + +with_gnu_ld="$lt_cv_prog_gnu_ld" + +old_CC="$CC" +old_CFLAGS="$CFLAGS" + +# Set sane defaults for various variables +test -z "$CC" && CC=cc +test -z "$LTCC" && LTCC=$CC +test -z "$LTCFLAGS" && LTCFLAGS=$CFLAGS +test -z "$LD" && LD=ld +test -z "$ac_objext" && ac_objext=o + +for cc_temp in $compiler""; do + case $cc_temp in + compile | *[\\/]compile | ccache | *[\\/]ccache ) ;; + distcc | *[\\/]distcc | purify | *[\\/]purify ) ;; + \-*) ;; + *) break;; + esac +done +cc_basename=`$ECHO "X$cc_temp" | $Xsed -e 's%.*/%%' -e "s%^$host_alias-%%"` + + +# Only perform the check for file, if the check method requires it +test -z "$MAGIC_CMD" && MAGIC_CMD=file +case $deplibs_check_method in +file_magic*) + if test "$file_magic_cmd" = '$MAGIC_CMD'; then + echo "$as_me:$LINENO: checking for ${ac_tool_prefix}file" >&5 +echo $ECHO_N "checking for ${ac_tool_prefix}file... $ECHO_C" >&6 +if test "${lt_cv_path_MAGIC_CMD+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 + case $MAGIC_CMD in +[\\/*] | ?:[\\/]*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. + ;; +*) + lt_save_MAGIC_CMD="$MAGIC_CMD" + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + ac_dummy="/usr/bin$PATH_SEPARATOR$PATH" + for ac_dir in $ac_dummy; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/${ac_tool_prefix}file; then + lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file" + if test -n "$file_magic_test_file"; then + case $deplibs_check_method in + "file_magic "*) + file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"` + MAGIC_CMD="$lt_cv_path_MAGIC_CMD" + if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | + $EGREP "$file_magic_regex" > /dev/null; then + : + else + cat <<_LT_EOF 1>&2 + +*** Warning: the command libtool uses to detect shared libraries, +*** $file_magic_cmd, produces output that libtool cannot recognize. +*** The result is that libtool may fail to recognize shared libraries +*** as such. This will affect the creation of libtool libraries that +*** depend on shared libraries, but programs linked with such libtool +*** libraries will work regardless of this problem. Nevertheless, you +*** may want to report the problem to your system manager and/or to +*** bug-libtool@gnu.org -ac_cv_type_off_t=no +_LT_EOF + fi ;; + esac + fi + break + fi + done + IFS="$lt_save_ifs" + MAGIC_CMD="$lt_save_MAGIC_CMD" + ;; +esac fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext + +MAGIC_CMD="$lt_cv_path_MAGIC_CMD" +if test -n "$MAGIC_CMD"; then + echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5 +echo "${ECHO_T}$MAGIC_CMD" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 fi -echo "$as_me:$LINENO: result: $ac_cv_type_off_t" >&5 -echo "${ECHO_T}$ac_cv_type_off_t" >&6 -if test $ac_cv_type_off_t = yes; then - : + + + + + +if test -z "$lt_cv_path_MAGIC_CMD"; then + if test -n "$ac_tool_prefix"; then + echo "$as_me:$LINENO: checking for file" >&5 +echo $ECHO_N "checking for file... $ECHO_C" >&6 +if test "${lt_cv_path_MAGIC_CMD+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 else + case $MAGIC_CMD in +[\\/*] | ?:[\\/]*) + lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. + ;; +*) + lt_save_MAGIC_CMD="$MAGIC_CMD" + lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR + ac_dummy="/usr/bin$PATH_SEPARATOR$PATH" + for ac_dir in $ac_dummy; do + IFS="$lt_save_ifs" + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/file; then + lt_cv_path_MAGIC_CMD="$ac_dir/file" + if test -n "$file_magic_test_file"; then + case $deplibs_check_method in + "file_magic "*) + file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"` + MAGIC_CMD="$lt_cv_path_MAGIC_CMD" + if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | + $EGREP "$file_magic_regex" > /dev/null; then + : + else + cat <<_LT_EOF 1>&2 -cat >>confdefs.h <<_ACEOF -#define off_t long -_ACEOF +*** Warning: the command libtool uses to detect shared libraries, +*** $file_magic_cmd, produces output that libtool cannot recognize. +*** The result is that libtool may fail to recognize shared libraries +*** as such. This will affect the creation of libtool libraries that +*** depend on shared libraries, but programs linked with such libtool +*** libraries will work regardless of this problem. Nevertheless, you +*** may want to report the problem to your system manager and/or to +*** bug-libtool@gnu.org + +_LT_EOF + fi ;; + esac + fi + break + fi + done + IFS="$lt_save_ifs" + MAGIC_CMD="$lt_save_MAGIC_CMD" + ;; +esac +fi +MAGIC_CMD="$lt_cv_path_MAGIC_CMD" +if test -n "$MAGIC_CMD"; then + echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5 +echo "${ECHO_T}$MAGIC_CMD" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +fi + + + else + MAGIC_CMD=: + fi fi -echo "$as_me:$LINENO: checking for size_t" >&5 -echo $ECHO_N "checking for size_t... $ECHO_C" >&6 -if test "${ac_cv_type_size_t+set}" = set; then + fi + ;; +esac + +# Use C for the default configuration in the libtool script + +lt_save_CC="$CC" +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +# Source file extension for C test sources. +ac_ext=c + +# Object file extension for compiled C test sources. +objext=o +objext=$objext + +# Code to be used in simple compile tests +lt_simple_compile_test_code="int some_variable = 0;" + +# Code to be used in simple link tests +lt_simple_link_test_code='int main(){return(0);}' + + + + + + + +# If no C compiler was specified, use CC. +LTCC=${LTCC-"$CC"} + +# If no C compiler flags were specified, use CFLAGS. +LTCFLAGS=${LTCFLAGS-"$CFLAGS"} + +# Allow CC to be a program name with arguments. +compiler=$CC + +# Save the default compiler, since it gets overwritten when the other +# tags are being tested, and _LT_TAGVAR(compiler, []) is a NOP. +compiler_DEFAULT=$CC + +# save warnings/boilerplate of simple test code +ac_outfile=conftest.$ac_objext +echo "$lt_simple_compile_test_code" >conftest.$ac_ext +eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err +_lt_compiler_boilerplate=`cat conftest.err` +$RM conftest* + +ac_outfile=conftest.$ac_objext +echo "$lt_simple_link_test_code" >conftest.$ac_ext +eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err +_lt_linker_boilerplate=`cat conftest.err` +$RM conftest* + + +## CAVEAT EMPTOR: +## There is no encapsulation within the following macros, do not change +## the running order or otherwise move them around unless you know exactly +## what you are doing... +if test -n "$compiler"; then + +lt_prog_compiler_no_builtin_flag= + +if test "$GCC" = yes; then + lt_prog_compiler_no_builtin_flag=' -fno-builtin' + + echo "$as_me:$LINENO: checking if $compiler supports -fno-rtti -fno-exceptions" >&5 +echo $ECHO_N "checking if $compiler supports -fno-rtti -fno-exceptions... $ECHO_C" >&6 +if test "${lt_cv_prog_compiler_rtti_exceptions+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - cat >conftest.$ac_ext <<_ACEOF + lt_cv_prog_compiler_rtti_exceptions=no + ac_outfile=conftest.$ac_objext + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + lt_compiler_flag="-fno-rtti -fno-exceptions" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + # The option is referenced via a variable to avoid confusing sed. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:6090: $lt_compile\"" >&5) + (eval "$lt_compile" 2>conftest.err) + ac_status=$? + cat conftest.err >&5 + echo "$as_me:6094: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s "$ac_outfile"; then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings other than the usual output. + $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' >conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then + lt_cv_prog_compiler_rtti_exceptions=yes + fi + fi + $RM conftest* + +fi +echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_rtti_exceptions" >&5 +echo "${ECHO_T}$lt_cv_prog_compiler_rtti_exceptions" >&6 + +if test x"$lt_cv_prog_compiler_rtti_exceptions" = xyes; then + lt_prog_compiler_no_builtin_flag="$lt_prog_compiler_no_builtin_flag -fno-rtti -fno-exceptions" +else + : +fi + +fi + + + + + + + lt_prog_compiler_wl= +lt_prog_compiler_pic= +lt_prog_compiler_static= + +echo "$as_me:$LINENO: checking for $compiler option to produce PIC" >&5 +echo $ECHO_N "checking for $compiler option to produce PIC... $ECHO_C" >&6 + + if test "$GCC" = yes; then + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_static='-static' + + case $host_os in + aix*) + # All AIX code is PIC. + if test "$host_cpu" = ia64; then + # AIX 5 now supports IA64 processor + lt_prog_compiler_static='-Bstatic' + fi + ;; + + amigaos*) + if test "$host_cpu" = m68k; then + # FIXME: we need at least 68020 code to build shared libraries, but + # adding the `-m68020' flag to GCC prevents building anything better, + # like `-m68040'. + lt_prog_compiler_pic='-m68020 -resident32 -malways-restore-a4' + fi + ;; + + beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) + # PIC is the default for these OSes. + ;; + + mingw* | cygwin* | pw32* | os2*) + # This hack is so that the source file can tell whether it is being + # built for inclusion in a dll (and should export symbols for example). + # Although the cygwin gcc ignores -fPIC, still need this for old-style + # (--disable-auto-import) libraries + lt_prog_compiler_pic='-DDLL_EXPORT' + ;; + + darwin* | rhapsody*) + # PIC is the default on this platform + # Common symbols not allowed in MH_DYLIB files + lt_prog_compiler_pic='-fno-common' + ;; + + hpux*) + # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but + # not for PA HP-UX. + case $host_cpu in + hppa*64*|ia64*) + # +Z the default + ;; + *) + lt_prog_compiler_pic='-fPIC' + ;; + esac + ;; + + interix[3-9]*) + # Interix 3.x gcc -fpic/-fPIC options generate broken code. + # Instead, we relocate shared libraries at runtime. + ;; + + msdosdjgpp*) + # Just because we use GCC doesn't mean we suddenly get shared libraries + # on systems that don't support them. + lt_prog_compiler_can_build_shared=no + enable_shared=no + ;; + + *nto* | *qnx*) + # QNX uses GNU C++, but need to define -shared option too, otherwise + # it will coredump. + lt_prog_compiler_pic='-fPIC -shared' + ;; + + sysv4*MP*) + if test -d /usr/nec; then + lt_prog_compiler_pic=-Kconform_pic + fi + ;; + + *) + lt_prog_compiler_pic='-fPIC' + ;; + esac + else + # PORTME Check for flag to pass linker flags through the system compiler. + case $host_os in + aix*) + lt_prog_compiler_wl='-Wl,' + if test "$host_cpu" = ia64; then + # AIX 5 now supports IA64 processor + lt_prog_compiler_static='-Bstatic' + else + lt_prog_compiler_static='-bnso -bI:/lib/syscalls.exp' + fi + ;; + darwin*) + # PIC is the default on this platform + # Common symbols not allowed in MH_DYLIB files + case $cc_basename in + xlc*) + lt_prog_compiler_pic='-qnocommon' + lt_prog_compiler_wl='-Wl,' + ;; + esac + ;; + + mingw* | cygwin* | pw32* | os2*) + # This hack is so that the source file can tell whether it is being + # built for inclusion in a dll (and should export symbols for example). + lt_prog_compiler_pic='-DDLL_EXPORT' + ;; + + hpux9* | hpux10* | hpux11*) + lt_prog_compiler_wl='-Wl,' + # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but + # not for PA HP-UX. + case $host_cpu in + hppa*64*|ia64*) + # +Z the default + ;; + *) + lt_prog_compiler_pic='+Z' + ;; + esac + # Is there a better lt_prog_compiler_static that works with the bundled CC? + lt_prog_compiler_static='${wl}-a ${wl}archive' + ;; + + irix5* | irix6* | nonstopux*) + lt_prog_compiler_wl='-Wl,' + # PIC (with -KPIC) is the default. + lt_prog_compiler_static='-non_shared' + ;; + + linux* | k*bsd*-gnu) + case $cc_basename in + icc* | ecc*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-static' + ;; + pgcc* | pgf77* | pgf90* | pgf95*) + # Portland Group compilers (*not* the Pentium gcc compiler, + # which looks to be a dead project) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-fpic' + lt_prog_compiler_static='-Bstatic' + ;; + ccc*) + lt_prog_compiler_wl='-Wl,' + # All Alpha code is PIC. + lt_prog_compiler_static='-non_shared' + ;; + *) + case `$CC -V 2>&1 | sed 5q` in + *Sun\ C*) + # Sun C 5.9 + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + lt_prog_compiler_wl='-Wl,' + ;; + *Sun\ F*) + # Sun Fortran 8.3 passes all unrecognized flags to the linker + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + lt_prog_compiler_wl='' + ;; + esac + ;; + esac + ;; + + newsos6) + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + ;; + + *nto* | *qnx*) + # QNX uses GNU C++, but need to define -shared option too, otherwise + # it will coredump. + lt_prog_compiler_pic='-fPIC -shared' + ;; + + osf3* | osf4* | osf5*) + lt_prog_compiler_wl='-Wl,' + # All OSF/1 code is PIC. + lt_prog_compiler_static='-non_shared' + ;; + + rdos*) + lt_prog_compiler_static='-non_shared' + ;; + + solaris*) + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + case $cc_basename in + f77* | f90* | f95*) + lt_prog_compiler_wl='-Qoption ld ';; + *) + lt_prog_compiler_wl='-Wl,';; + esac + ;; + + sunos4*) + lt_prog_compiler_wl='-Qoption ld ' + lt_prog_compiler_pic='-PIC' + lt_prog_compiler_static='-Bstatic' + ;; + + sysv4 | sysv4.2uw2* | sysv4.3*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + ;; + + sysv4*MP*) + if test -d /usr/nec ;then + lt_prog_compiler_pic='-Kconform_pic' + lt_prog_compiler_static='-Bstatic' + fi + ;; + + sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_pic='-KPIC' + lt_prog_compiler_static='-Bstatic' + ;; + + unicos*) + lt_prog_compiler_wl='-Wl,' + lt_prog_compiler_can_build_shared=no + ;; + + uts4*) + lt_prog_compiler_pic='-pic' + lt_prog_compiler_static='-Bstatic' + ;; + + *) + lt_prog_compiler_can_build_shared=no + ;; + esac + fi + +case $host_os in + # For platforms which do not support PIC, -DPIC is meaningless: + *djgpp*) + lt_prog_compiler_pic= + ;; + *) + lt_prog_compiler_pic="$lt_prog_compiler_pic -DPIC" + ;; +esac +echo "$as_me:$LINENO: result: $lt_prog_compiler_pic" >&5 +echo "${ECHO_T}$lt_prog_compiler_pic" >&6 + + + + + + +# +# Check to make sure the PIC flag actually works. +# +if test -n "$lt_prog_compiler_pic"; then + echo "$as_me:$LINENO: checking if $compiler PIC flag $lt_prog_compiler_pic works" >&5 +echo $ECHO_N "checking if $compiler PIC flag $lt_prog_compiler_pic works... $ECHO_C" >&6 +if test "${lt_prog_compiler_pic_works+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + lt_prog_compiler_pic_works=no + ac_outfile=conftest.$ac_objext + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + lt_compiler_flag="$lt_prog_compiler_pic -DPIC" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + # The option is referenced via a variable to avoid confusing sed. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:6412: $lt_compile\"" >&5) + (eval "$lt_compile" 2>conftest.err) + ac_status=$? + cat conftest.err >&5 + echo "$as_me:6416: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s "$ac_outfile"; then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings other than the usual output. + $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' >conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then + lt_prog_compiler_pic_works=yes + fi + fi + $RM conftest* + +fi +echo "$as_me:$LINENO: result: $lt_prog_compiler_pic_works" >&5 +echo "${ECHO_T}$lt_prog_compiler_pic_works" >&6 + +if test x"$lt_prog_compiler_pic_works" = xyes; then + case $lt_prog_compiler_pic in + "" | " "*) ;; + *) lt_prog_compiler_pic=" $lt_prog_compiler_pic" ;; + esac +else + lt_prog_compiler_pic= + lt_prog_compiler_can_build_shared=no +fi + +fi + + + + + + +# +# Check to make sure the static flag actually works. +# +wl=$lt_prog_compiler_wl eval lt_tmp_static_flag=\"$lt_prog_compiler_static\" +echo "$as_me:$LINENO: checking if $compiler static flag $lt_tmp_static_flag works" >&5 +echo $ECHO_N "checking if $compiler static flag $lt_tmp_static_flag works... $ECHO_C" >&6 +if test "${lt_prog_compiler_static_works+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + lt_prog_compiler_static_works=no + save_LDFLAGS="$LDFLAGS" + LDFLAGS="$LDFLAGS $lt_tmp_static_flag" + echo "$lt_simple_link_test_code" > conftest.$ac_ext + if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then + # The linker can only warn and ignore the option if not recognized + # So say no if there are warnings + if test -s conftest.err; then + # Append any errors to the config.log. + cat conftest.err 1>&5 + $ECHO "X$_lt_linker_boilerplate" | $Xsed -e '/^$/d' > conftest.exp + $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 + if diff conftest.exp conftest.er2 >/dev/null; then + lt_prog_compiler_static_works=yes + fi + else + lt_prog_compiler_static_works=yes + fi + fi + $RM conftest* + LDFLAGS="$save_LDFLAGS" + +fi +echo "$as_me:$LINENO: result: $lt_prog_compiler_static_works" >&5 +echo "${ECHO_T}$lt_prog_compiler_static_works" >&6 + +if test x"$lt_prog_compiler_static_works" = xyes; then + : +else + lt_prog_compiler_static= +fi + + + + + + + + echo "$as_me:$LINENO: checking if $compiler supports -c -o file.$ac_objext" >&5 +echo $ECHO_N "checking if $compiler supports -c -o file.$ac_objext... $ECHO_C" >&6 +if test "${lt_cv_prog_compiler_c_o+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + lt_cv_prog_compiler_c_o=no + $RM -r conftest 2>/dev/null + mkdir conftest + cd conftest + mkdir out + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + lt_compiler_flag="-o out/conftest2.$ac_objext" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:6517: $lt_compile\"" >&5) + (eval "$lt_compile" 2>out/conftest.err) + ac_status=$? + cat out/conftest.err >&5 + echo "$as_me:6521: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s out/conftest2.$ac_objext + then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings + $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' > out/conftest.exp + $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 + if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then + lt_cv_prog_compiler_c_o=yes + fi + fi + chmod u+w . 2>&5 + $RM conftest* + # SGI C++ compiler will create directory out/ii_files/ for + # template instantiation + test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files + $RM out/* && rmdir out + cd .. + $RM -r conftest + $RM conftest* + +fi +echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_c_o" >&5 +echo "${ECHO_T}$lt_cv_prog_compiler_c_o" >&6 + + + + + + + echo "$as_me:$LINENO: checking if $compiler supports -c -o file.$ac_objext" >&5 +echo $ECHO_N "checking if $compiler supports -c -o file.$ac_objext... $ECHO_C" >&6 +if test "${lt_cv_prog_compiler_c_o+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + lt_cv_prog_compiler_c_o=no + $RM -r conftest 2>/dev/null + mkdir conftest + cd conftest + mkdir out + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + lt_compiler_flag="-o out/conftest2.$ac_objext" + # Insert the option either (1) after the last *FLAGS variable, or + # (2) before a word containing "conftest.", or (3) at the end. + # Note that $ac_compile itself does not contain backslashes and begins + # with a dollar sign (not a hyphen), so the echo should work correctly. + lt_compile=`echo "$ac_compile" | $SED \ + -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ + -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ + -e 's:$: $lt_compiler_flag:'` + (eval echo "\"\$as_me:6572: $lt_compile\"" >&5) + (eval "$lt_compile" 2>out/conftest.err) + ac_status=$? + cat out/conftest.err >&5 + echo "$as_me:6576: \$? = $ac_status" >&5 + if (exit $ac_status) && test -s out/conftest2.$ac_objext + then + # The compiler can only warn and ignore the option if not recognized + # So say no if there are warnings + $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' > out/conftest.exp + $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 + if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then + lt_cv_prog_compiler_c_o=yes + fi + fi + chmod u+w . 2>&5 + $RM conftest* + # SGI C++ compiler will create directory out/ii_files/ for + # template instantiation + test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files + $RM out/* && rmdir out + cd .. + $RM -r conftest + $RM conftest* + +fi +echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_c_o" >&5 +echo "${ECHO_T}$lt_cv_prog_compiler_c_o" >&6 + + + + +hard_links="nottested" +if test "$lt_cv_prog_compiler_c_o" = no && test "$need_locks" != no; then + # do not overwrite the value of need_locks provided by the user + echo "$as_me:$LINENO: checking if we can lock with hard links" >&5 +echo $ECHO_N "checking if we can lock with hard links... $ECHO_C" >&6 + hard_links=yes + $RM conftest* + ln conftest.a conftest.b 2>/dev/null && hard_links=no + touch conftest.a + ln conftest.a conftest.b 2>&5 || hard_links=no + ln conftest.a conftest.b 2>/dev/null && hard_links=no + echo "$as_me:$LINENO: result: $hard_links" >&5 +echo "${ECHO_T}$hard_links" >&6 + if test "$hard_links" = no; then + { echo "$as_me:$LINENO: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&5 +echo "$as_me: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&2;} + need_locks=warn + fi +else + need_locks=no +fi + + + + + + + echo "$as_me:$LINENO: checking whether the $compiler linker ($LD) supports shared libraries" >&5 +echo $ECHO_N "checking whether the $compiler linker ($LD) supports shared libraries... $ECHO_C" >&6 + + runpath_var= + allow_undefined_flag= + always_export_symbols=no + archive_cmds= + archive_expsym_cmds= + compiler_needs_object=no + enable_shared_with_static_runtimes=no + export_dynamic_flag_spec= + export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols' + hardcode_automatic=no + hardcode_direct=no + hardcode_direct_absolute=no + hardcode_libdir_flag_spec= + hardcode_libdir_flag_spec_ld= + hardcode_libdir_separator= + hardcode_minus_L=no + hardcode_shlibpath_var=unsupported + inherit_rpath=no + link_all_deplibs=unknown + module_cmds= + module_expsym_cmds= + old_archive_from_new_cmds= + old_archive_from_expsyms_cmds= + thread_safe_flag_spec= + whole_archive_flag_spec= + # include_expsyms should be a list of space-separated symbols to be *always* + # included in the symbol list + include_expsyms= + # exclude_expsyms can be an extended regexp of symbols to exclude + # it will be wrapped by ` (' and `)$', so one must not match beginning or + # end of line. Example: `a|bc|.*d.*' will exclude the symbols `a' and `bc', + # as well as any symbol that contains `d'. + exclude_expsyms="_GLOBAL_OFFSET_TABLE_" + # Although _GLOBAL_OFFSET_TABLE_ is a valid symbol C name, most a.out + # platforms (ab)use it in PIC code, but their linkers get confused if + # the symbol is explicitly referenced. Since portable code cannot + # rely on this symbol name, it's probably fine to never include it in + # preloaded symbol tables. + extract_expsyms_cmds= + + case $host_os in + cygwin* | mingw* | pw32*) + # FIXME: the MSVC++ port hasn't been tested in a loooong time + # When not using gcc, we currently assume that we are using + # Microsoft Visual C++. + if test "$GCC" != yes; then + with_gnu_ld=no + fi + ;; + interix*) + # we just hope/assume this is gcc and not c89 (= MSVC++) + with_gnu_ld=yes + ;; + openbsd*) + with_gnu_ld=no + ;; + esac + + ld_shlibs=yes + if test "$with_gnu_ld" = yes; then + # If archive_cmds runs LD, not CC, wlarc should be empty + wlarc='${wl}' + + # Set some defaults for GNU ld with shared library support. These + # are reset later if shared libraries are not supported. Putting them + # here allows them to be overridden if necessary. + runpath_var=LD_RUN_PATH + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + export_dynamic_flag_spec='${wl}--export-dynamic' + # ancient GNU ld didn't support --whole-archive et. al. + if $LD --help 2>&1 | $GREP 'no-whole-archive' > /dev/null; then + whole_archive_flag_spec="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive' + else + whole_archive_flag_spec= + fi + supports_anon_versioning=no + case `$LD -v 2>&1` in + *\ [01].* | *\ 2.[0-9].* | *\ 2.10.*) ;; # catch versions < 2.11 + *\ 2.11.93.0.2\ *) supports_anon_versioning=yes ;; # RH7.3 ... + *\ 2.11.92.0.12\ *) supports_anon_versioning=yes ;; # Mandrake 8.2 ... + *\ 2.11.*) ;; # other 2.11 versions + *) supports_anon_versioning=yes ;; + esac + + # See if GNU ld supports shared libraries. + case $host_os in + aix3* | aix4* | aix5*) + # On AIX/PPC, the GNU linker is very broken + if test "$host_cpu" != ia64; then + ld_shlibs=no + cat <<_LT_EOF 1>&2 + +*** Warning: the GNU linker, at least up to release 2.9.1, is reported +*** to be unable to reliably create shared libraries on AIX. +*** Therefore, libtool is disabling shared libraries support. If you +*** really care for shared libraries, you may want to modify your PATH +*** so that a non-GNU linker is found, and then restart. + +_LT_EOF + fi + ;; + + amigaos*) + if test "$host_cpu" = m68k; then + archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + fi + + # Samuel A. Falvo II <kc5tja@dolphin.openprojects.net> reports + # that the semantics of dynamic libraries on AmigaOS, at least up + # to version 4, is to share data among multiple programs linked + # with the same dynamic library. Since this doesn't match the + # behavior of shared libraries on other platforms, we can't use + # them. + ld_shlibs=no + ;; + + beos*) + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + allow_undefined_flag=unsupported + # Joseph Beckenbach <jrb3@best.com> says some releases of gcc + # support --undefined. This deserves some investigation. FIXME + archive_cmds='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + else + ld_shlibs=no + fi + ;; + + cygwin* | mingw* | pw32*) + # _LT_TAGVAR(hardcode_libdir_flag_spec, ) is actually meaningless, + # as there is no search path for DLLs. + hardcode_libdir_flag_spec='-L$libdir' + allow_undefined_flag=unsupported + always_export_symbols=no + enable_shared_with_static_runtimes=yes + export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1 DATA/'\'' | $SED -e '\''/^[AITW][ ]/s/.*[ ]//'\'' | sort | uniq > $export_symbols' + + if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' + # If the export-symbols file already is a .def file (1st line + # is EXPORTS), use it as is; otherwise, prepend... + archive_expsym_cmds='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then + cp $export_symbols $output_objdir/$soname.def; + else + echo EXPORTS > $output_objdir/$soname.def; + cat $export_symbols >> $output_objdir/$soname.def; + fi~ + $CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' + else + ld_shlibs=no + fi + ;; + + interix[3-9]*) + hardcode_direct=no + hardcode_shlibpath_var=no + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + export_dynamic_flag_spec='${wl}-E' + # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc. + # Instead, shared libraries are loaded at an image base (0x10000000 by + # default) and relocated if they conflict, which is a slow very memory + # consuming and fragmenting process. To avoid this, we pick a random, + # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link + # time. Moving up from 0x10000000 also allows more sbrk(2) space. + archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' + archive_expsym_cmds='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' + ;; + + gnu* | linux* | tpf* | k*bsd*-gnu) + tmp_diet=no + if test "$host_os" = linux-dietlibc; then + case $cc_basename in + diet\ *) tmp_diet=yes;; # linux-dietlibc with static linking (!diet-dyn) + esac + fi + if $LD --help 2>&1 | $EGREP ': supported targets:.* elf' > /dev/null \ + && test "$tmp_diet" = no + then + tmp_addflag= + case $cc_basename,$host_cpu in + pgcc*) # Portland Group C compiler + whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $ECHO \"$new_convenience\"` ${wl}--no-whole-archive' + tmp_addflag=' $pic_flag' + ;; + pgf77* | pgf90* | pgf95*) # Portland Group f77 and f90 compilers + whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $ECHO \"$new_convenience\"` ${wl}--no-whole-archive' + tmp_addflag=' $pic_flag -Mnomain' ;; + ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 + tmp_addflag=' -i_dynamic' ;; + efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 + tmp_addflag=' -i_dynamic -nofor_main' ;; + ifc* | ifort*) # Intel Fortran compiler + tmp_addflag=' -nofor_main' ;; + esac + case `$CC -V 2>&1 | sed 5q` in + *Sun\ C*) # Sun C 5.9 + whole_archive_flag_spec='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; $ECHO \"$new_convenience\"` ${wl}--no-whole-archive' + compiler_needs_object=yes + tmp_sharedflag='-G' ;; + *Sun\ F*) # Sun Fortran 8.3 + tmp_sharedflag='-G' ;; + *) + tmp_sharedflag='-shared' ;; + esac + archive_cmds='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + + if test "x$supports_anon_versioning" = xyes; then + archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~ + cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ + echo "local: *; };" >> $output_objdir/$libname.ver~ + $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib' + fi + else + ld_shlibs=no + fi + ;; + + netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + archive_cmds='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib' + wlarc= + else + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + fi + ;; + + solaris*) + if $LD -v 2>&1 | $GREP 'BFD 2\.8' > /dev/null; then + ld_shlibs=no + cat <<_LT_EOF 1>&2 + +*** Warning: The releases 2.8.* of the GNU linker cannot reliably +*** create shared libraries on Solaris systems. Therefore, libtool +*** is disabling shared libraries support. We urge you to upgrade GNU +*** binutils to release 2.9.1 or newer. Another option is to modify +*** your PATH or compiler configuration so that the native linker is +*** used, and then restart. + +_LT_EOF + elif $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + else + ld_shlibs=no + fi + ;; + + sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*) + case `$LD -v 2>&1` in + *\ [01].* | *\ 2.[0-9].* | *\ 2.1[0-5].*) + ld_shlibs=no + cat <<_LT_EOF 1>&2 + +*** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not +*** reliably create shared libraries on SCO systems. Therefore, libtool +*** is disabling shared libraries support. We urge you to upgrade GNU +*** binutils to release 2.16.91.0.3 or newer. Another option is to modify +*** your PATH or compiler configuration so that the native linker is +*** used, and then restart. + +_LT_EOF + ;; + *) + # For security reasons, it is highly recommended that you always + # use absolute paths for naming shared libraries, and exclude the + # DT_RUNPATH tag from executables and libraries. But doing so + # requires that you compile everything twice, which is a pain. + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + else + ld_shlibs=no + fi + ;; + esac + ;; + + sunos4*) + archive_cmds='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags' + wlarc= + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + *) + if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' + else + ld_shlibs=no + fi + ;; + esac + + if test "$ld_shlibs" = no; then + runpath_var= + hardcode_libdir_flag_spec= + export_dynamic_flag_spec= + whole_archive_flag_spec= + fi + else + # PORTME fill in a description of your system's linker (not GNU ld) + case $host_os in + aix3*) + allow_undefined_flag=unsupported + always_export_symbols=yes + archive_expsym_cmds='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname' + # Note: this linker hardcodes the directories in LIBPATH if there + # are no directories specified by -L. + hardcode_minus_L=yes + if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then + # Neither direct hardcoding nor static linking is supported with a + # broken collect2. + hardcode_direct=unsupported + fi + ;; + + aix4* | aix5*) + if test "$host_cpu" = ia64; then + # On IA64, the linker does run time linking by default, so we don't + # have to do anything special. + aix_use_runtimelinking=no + exp_sym_flag='-Bexport' + no_entry_flag="" + else + # If we're using GNU nm, then we don't want the "-C" option. + # -C means demangle to AIX nm, but means don't demangle with GNU nm + if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then + export_symbols_cmds='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' + else + export_symbols_cmds='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' + fi + aix_use_runtimelinking=no + + # Test if we are trying to use run time linking or normal + # AIX style linking. If -brtl is somewhere in LDFLAGS, we + # need to do runtime linking. + case $host_os in aix4.[23]|aix4.[23].*|aix5*) + for ld_flag in $LDFLAGS; do + if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then + aix_use_runtimelinking=yes + break + fi + done + ;; + esac + + exp_sym_flag='-bexport' + no_entry_flag='-bnoentry' + fi + + # When large executables or shared objects are built, AIX ld can + # have problems creating the table of contents. If linking a library + # or program results in "error TOC overflow" add -mminimal-toc to + # CXXFLAGS/CFLAGS for g++/gcc. In the cases where that is not + # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS. + + archive_cmds='' + hardcode_direct=yes + hardcode_direct_absolute=yes + hardcode_libdir_separator=':' + link_all_deplibs=yes + file_list_spec='${wl}-f,' + + if test "$GCC" = yes; then + case $host_os in aix4.[012]|aix4.[012].*) + # We only want to do this on AIX 4.2 and lower, the check + # below for broken collect2 doesn't work under 4.3+ + collect2name=`${CC} -print-prog-name=collect2` + if test -f "$collect2name" && + strings "$collect2name" | $GREP resolve_lib_name >/dev/null + then + # We have reworked collect2 + : + else + # We have old collect2 + hardcode_direct=unsupported + # It fails to find uninstalled libraries when the uninstalled + # path is not listed in the libpath. Setting hardcode_minus_L + # to unsupported forces relinking + hardcode_minus_L=yes + hardcode_libdir_flag_spec='-L$libdir' + hardcode_libdir_separator= + fi + ;; + esac + shared_flag='-shared' + if test "$aix_use_runtimelinking" = yes; then + shared_flag="$shared_flag "'${wl}-G' + fi + else + # not using gcc + if test "$host_cpu" = ia64; then + # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release + # chokes on -Wl,-G. The following line is correct: + shared_flag='-G' + else + if test "$aix_use_runtimelinking" = yes; then + shared_flag='${wl}-G' + else + shared_flag='${wl}-bM:SRE' + fi + fi + fi + + # It seems that -bexpall does not export symbols beginning with + # underscore (_), so it is better to generate a list of symbols to export. + always_export_symbols=yes + if test "$aix_use_runtimelinking" = yes; then + # Warning - without using the other runtime loading flags (-brtl), + # -berok will link without error, but may produce a broken library. + allow_undefined_flag='-berok' + # Determine the default libpath from the value encoded in an + # empty executable. + cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -$ac_includes_default + int main () { -if ((size_t *) 0) - return 0; -if (sizeof (size_t)) - return 0; + ; return 0; } _ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 +rm -f conftest.$ac_objext conftest$ac_exeext +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -6073,51 +7079,55 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - ac_cv_type_size_t=yes -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 -ac_cv_type_size_t=no -fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext +lt_aix_libpath_sed=' + /Import File Strings/,/^$/ { + /^0/ { + s/^0 *\(.*\)$/\1/ + p + } + }' +aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` +# Check for a 64-bit object if we didn't find anything. +if test -z "$aix_libpath"; then + aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` fi -echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5 -echo "${ECHO_T}$ac_cv_type_size_t" >&6 -if test $ac_cv_type_size_t = yes; then - : else - -cat >>confdefs.h <<_ACEOF -#define size_t unsigned -_ACEOF + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 fi +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi -# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works -# for constant arguments. Useless! -echo "$as_me:$LINENO: checking for working alloca.h" >&5 -echo $ECHO_N "checking for working alloca.h... $ECHO_C" >&6 -if test "${ac_cv_working_alloca_h+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - cat >conftest.$ac_ext <<_ACEOF + hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" + archive_expsym_cmds='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then $ECHO "X${wl}${allow_undefined_flag}" | $Xsed; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" + else + if test "$host_cpu" = ia64; then + hardcode_libdir_flag_spec='${wl}-R $libdir:/usr/lib:/lib' + allow_undefined_flag="-z nodefs" + archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" + else + # Determine the default libpath from the value encoded in an + # empty executable. + cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -#include <alloca.h> + int main () { -char *p = (char *) alloca (2 * sizeof (int)); + ; return 0; } @@ -6144,65 +7154,277 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - ac_cv_working_alloca_h=yes + +lt_aix_libpath_sed=' + /Import File Strings/,/^$/ { + /^0/ { + s/^0 *\(.*\)$/\1/ + p + } + }' +aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` +# Check for a 64-bit object if we didn't find anything. +if test -z "$aix_libpath"; then + aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` +fi else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -ac_cv_working_alloca_h=no fi rm -f conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext -fi -echo "$as_me:$LINENO: result: $ac_cv_working_alloca_h" >&5 -echo "${ECHO_T}$ac_cv_working_alloca_h" >&6 -if test $ac_cv_working_alloca_h = yes; then +if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi + + hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" + # Warning - without using the other run time loading flags, + # -berok will link without error, but may produce a broken library. + no_undefined_flag=' ${wl}-bernotok' + allow_undefined_flag=' ${wl}-berok' + # Exported symbols can be pulled into shared objects from archives + whole_archive_flag_spec='$convenience' + archive_cmds_need_lc=yes + # This is similar to how AIX traditionally builds its shared libraries. + archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' + fi + fi + ;; -cat >>confdefs.h <<\_ACEOF -#define HAVE_ALLOCA_H 1 -_ACEOF + amigaos*) + if test "$host_cpu" = m68k; then + archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + fi + # see comment about different semantics on the GNU ld section + ld_shlibs=no + ;; -fi + bsdi[45]*) + export_dynamic_flag_spec=-rdynamic + ;; + + cygwin* | mingw* | pw32*) + # When not using gcc, we currently assume that we are using + # Microsoft Visual C++. + # hardcode_libdir_flag_spec is actually meaningless, as there is + # no search path for DLLs. + hardcode_libdir_flag_spec=' ' + allow_undefined_flag=unsupported + # Tell ltmain to make .lib files, not .a files. + libext=lib + # Tell ltmain to make .dll files, not .so files. + shrext_cmds=".dll" + # FIXME: Setting linknames here is a bad hack. + archive_cmds='$CC -o $lib $libobjs $compiler_flags `$ECHO "X$deplibs" | $Xsed -e '\''s/ -lc$//'\''` -link -dll~linknames=' + # The linker will automatically build a .lib file if we build a DLL. + old_archive_from_new_cmds='true' + # FIXME: Should let the user specify the lib program. + old_archive_cmds='lib -OUT:$oldlib$oldobjs$old_deplibs' + fix_srcfile_path='`cygpath -w "$srcfile"`' + enable_shared_with_static_runtimes=yes + ;; -echo "$as_me:$LINENO: checking for alloca" >&5 -echo $ECHO_N "checking for alloca... $ECHO_C" >&6 -if test "${ac_cv_func_alloca_works+set}" = set; then + darwin* | rhapsody*) + case $host_os in + rhapsody* | darwin1.[012]) + allow_undefined_flag='${wl}-undefined ${wl}suppress' + ;; + *) # Darwin 1.3 on + case ${MACOSX_DEPLOYMENT_TARGET-10.0} in + 10.[012]) + allow_undefined_flag='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' + ;; + 10.*) + allow_undefined_flag='${wl}-undefined ${wl}dynamic_lookup' + ;; + esac + ;; + esac + archive_cmds_need_lc=no + hardcode_direct=no + hardcode_automatic=yes + hardcode_shlibpath_var=unsupported + whole_archive_flag_spec='' + link_all_deplibs=yes + if test "$GCC" = yes ; then + if test "${lt_cv_apple_cc_single_mod+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#ifdef __GNUC__ -# define alloca __builtin_alloca -#else -# ifdef _MSC_VER -# include <malloc.h> -# define alloca _alloca -# else -# if HAVE_ALLOCA_H -# include <alloca.h> -# else -# ifdef _AIX - #pragma alloca -# else -# ifndef alloca /* predefined by HP cc +Olibcalls */ -char *alloca (); -# endif -# endif -# endif -# endif -#endif + lt_cv_apple_cc_single_mod=no + if test -z "${LT_MULTI_MODULE}"; then + # By default we will add the -single_module flag. You can override + # by either setting the environment variable LT_MULTI_MODULE + # non-empty at configure time, or by adding -multi-module to the + # link flags. + echo "int foo(void){return 1;}" > conftest.c + $LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \ + -dynamiclib ${wl}-single_module conftest.c + if test -f libconftest.dylib; then + lt_cv_apple_cc_single_mod=yes + rm libconftest.dylib + fi + rm conftest.$ac_ext + fi +fi -int -main () -{ -char *p = (char *) alloca (1); - ; - return 0; -} + output_verbose_link_cmd=echo + if test "X$lt_cv_apple_cc_single_mod" = Xyes ; then + archive_cmds='$CC -dynamiclib $single_module $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring' + archive_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $single_module -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' + else + archive_cmds='$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring' + archive_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' + fi + module_cmds='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' + module_expsym_cmds='sed -e "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' + else + case $cc_basename in + xlc*) + output_verbose_link_cmd=echo + archive_cmds='$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}`$ECHO $rpath/$soname` $verstring' + module_cmds='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags' + # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds + archive_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}$rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' + module_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}' + ;; + *) + ld_shlibs=no + ;; + esac + fi + ;; + + dgux*) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_shlibpath_var=no + ;; + + freebsd1*) + ld_shlibs=no + ;; + + # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor + # support. Future versions do this automatically, but an explicit c++rt0.o + # does not break anything, and helps significantly (at the cost of a little + # extra space). + freebsd2.2*) + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o' + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + # Unfortunately, older versions of FreeBSD 2 do not have this feature. + freebsd2*) + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=yes + hardcode_minus_L=yes + hardcode_shlibpath_var=no + ;; + + # FreeBSD 3 and greater uses gcc -shared to do shared libraries. + freebsd* | dragonfly*) + archive_cmds='$CC -shared -o $lib $libobjs $deplibs $compiler_flags' + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; + + hpux9*) + if test "$GCC" = yes; then + archive_cmds='$RM $output_objdir/$soname~$CC -shared -fPIC ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' + else + archive_cmds='$RM $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' + fi + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_direct=yes + + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + export_dynamic_flag_spec='${wl}-E' + ;; + + hpux10*) + if test "$GCC" = yes -a "$with_gnu_ld" = no; then + archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' + fi + if test "$with_gnu_ld" = no; then + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_flag_spec_ld='+b $libdir' + hardcode_libdir_separator=: + hardcode_direct=yes + hardcode_direct_absolute=yes + export_dynamic_flag_spec='${wl}-E' + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + fi + ;; + + hpux11*) + if test "$GCC" = yes -a "$with_gnu_ld" = no; then + case $host_cpu in + hppa*64*) + archive_cmds='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' + ;; + ia64*) + archive_cmds='$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' + ;; + *) + archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' + ;; + esac + else + case $host_cpu in + hppa*64*) + archive_cmds='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' + ;; + ia64*) + archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' + ;; + *) + archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' + ;; + esac + fi + if test "$with_gnu_ld" = no; then + hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' + hardcode_libdir_separator=: + + case $host_cpu in + hppa*64*|ia64*) + hardcode_direct=no + hardcode_shlibpath_var=no + ;; + *) + hardcode_direct=yes + hardcode_direct_absolute=yes + export_dynamic_flag_spec='${wl}-E' + + # hardcode_minus_L: Not really in the search PATH, + # but as the default location of the library. + hardcode_minus_L=yes + ;; + esac + fi + ;; + + irix5* | irix6* | nonstopux*) + if test "$GCC" = yes; then + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + # Try to use the -exported_symbol ld option, if it does not + # work, assume that -exports_file does not work either and + # implicitly export all symbols. + save_LDFLAGS="$LDFLAGS" + LDFLAGS="$LDFLAGS -shared ${wl}-exported_symbol ${wl}foo ${wl}-update_registry ${wl}/dev/null" + cat >conftest.$ac_ext <<_ACEOF +int foo(void) {} _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 @@ -6226,122 +7448,933 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - ac_cv_func_alloca_works=yes + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations ${wl}-exports_file ${wl}$export_symbols -o $lib' + else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -ac_cv_func_alloca_works=no fi rm -f conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext -fi -echo "$as_me:$LINENO: result: $ac_cv_func_alloca_works" >&5 -echo "${ECHO_T}$ac_cv_func_alloca_works" >&6 + LDFLAGS="$save_LDFLAGS" + else + archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib' + archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -exports_file $export_symbols -o $lib' + fi + archive_cmds_need_lc='no' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + inherit_rpath=yes + link_all_deplibs=yes + ;; -if test $ac_cv_func_alloca_works = yes; then + netbsd*) + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' # a.out + else + archive_cmds='$LD -shared -o $lib $libobjs $deplibs $linker_flags' # ELF + fi + hardcode_libdir_flag_spec='-R$libdir' + hardcode_direct=yes + hardcode_shlibpath_var=no + ;; -cat >>confdefs.h <<\_ACEOF -#define HAVE_ALLOCA 1 -_ACEOF + newsos6) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=yes + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + hardcode_shlibpath_var=no + ;; -else - # The SVR3 libPW and SVR4 libucb both contain incompatible functions -# that cause trouble. Some versions do not even contain alloca or -# contain a buggy version. If you still want to use their alloca, -# use ar to extract alloca.o from them instead of compiling alloca.c. + *nto* | *qnx*) + ;; -ALLOCA=alloca.$ac_objext + openbsd*) + hardcode_direct=yes + hardcode_shlibpath_var=no + hardcode_direct_absolute=yes + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols' + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + export_dynamic_flag_spec='${wl}-E' + else + case $host_os in + openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*) + archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' + hardcode_libdir_flag_spec='-R$libdir' + ;; + *) + archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' + hardcode_libdir_flag_spec='${wl}-rpath,$libdir' + ;; + esac + fi + ;; -cat >>confdefs.h <<\_ACEOF -#define C_ALLOCA 1 -_ACEOF + os2*) + hardcode_libdir_flag_spec='-L$libdir' + hardcode_minus_L=yes + allow_undefined_flag=unsupported + archive_cmds='$ECHO "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$ECHO "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~$ECHO DATA >> $output_objdir/$libname.def~$ECHO " SINGLE NONSHARED" >> $output_objdir/$libname.def~$ECHO EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def' + old_archive_from_new_cmds='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def' + ;; + osf3*) + if test "$GCC" = yes; then + allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + else + allow_undefined_flag=' -expect_unresolved \*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib' + fi + archive_cmds_need_lc='no' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + hardcode_libdir_separator=: + ;; -echo "$as_me:$LINENO: checking whether \`alloca.c' needs Cray hooks" >&5 -echo $ECHO_N "checking whether \`alloca.c' needs Cray hooks... $ECHO_C" >&6 -if test "${ac_cv_os_cray+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#if defined(CRAY) && ! defined(CRAY2) -webecray -#else -wenotbecray -#endif + osf4* | osf5*) # as osf3* with the addition of -msym flag + if test "$GCC" = yes; then + allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' + hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' + else + allow_undefined_flag=' -expect_unresolved \*' + archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -msym -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib' + archive_expsym_cmds='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; printf "%s\\n" "-hidden">> $lib.exp~ + $CC -shared${allow_undefined_flag} ${wl}-input ${wl}$lib.exp $compiler_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib~$RM $lib.exp' -_ACEOF -if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | - $EGREP "webecray" >/dev/null 2>&1; then - ac_cv_os_cray=yes -else - ac_cv_os_cray=no -fi -rm -f conftest* + # Both c and cxx compiler support -rpath directly + hardcode_libdir_flag_spec='-rpath $libdir' + fi + archive_cmds_need_lc='no' + hardcode_libdir_separator=: + ;; -fi -echo "$as_me:$LINENO: result: $ac_cv_os_cray" >&5 -echo "${ECHO_T}$ac_cv_os_cray" >&6 -if test $ac_cv_os_cray = yes; then - for ac_func in _getb67 GETB67 getb67; do - as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` -echo "$as_me:$LINENO: checking for $ac_func" >&5 -echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6 -if eval "test \"\${$as_ac_var+set}\" = set"; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else + solaris*) + no_undefined_flag=' -z defs' + if test "$GCC" = yes; then + wlarc='${wl}' + archive_cmds='$CC -shared ${wl}-z ${wl}text ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $CC -shared ${wl}-z ${wl}text ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' + else + case `$CC -V 2>&1` in + *"Compilers 5.0"*) + wlarc='' + archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags' + archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$RM $lib.exp' + ;; + *) + wlarc='${wl}' + archive_cmds='$CC -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ + $CC -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' + ;; + esac + fi + hardcode_libdir_flag_spec='-R$libdir' + hardcode_shlibpath_var=no + case $host_os in + solaris2.[0-5] | solaris2.[0-5].*) ;; + *) + # The compiler driver will combine and reorder linker options, + # but understands `-z linker_flag'. GCC discards it without `$wl', + # but is careful enough not to reorder. + # Supported since Solaris 2.6 (maybe 2.5.1?) + if test "$GCC" = yes; then + whole_archive_flag_spec='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' + else + whole_archive_flag_spec='-z allextract$convenience -z defaultextract' + fi + ;; + esac + link_all_deplibs=yes + ;; + + sunos4*) + if test "x$host_vendor" = xsequent; then + # Use $CC to link under sequent, because it throws in some extra .o + # files that make .init and .fini sections work. + archive_cmds='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags' + fi + hardcode_libdir_flag_spec='-L$libdir' + hardcode_direct=yes + hardcode_minus_L=yes + hardcode_shlibpath_var=no + ;; + + sysv4) + case $host_vendor in + sni) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=yes # is this really true??? + ;; + siemens) + ## LD is ld it makes a PLAMLIB + ## CC just makes a GrossModule. + archive_cmds='$LD -G -o $lib $libobjs $deplibs $linker_flags' + reload_cmds='$CC -r -o $output$reload_objs' + hardcode_direct=no + ;; + motorola) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_direct=no #Motorola manual says yes, but my tests say they lie + ;; + esac + runpath_var='LD_RUN_PATH' + hardcode_shlibpath_var=no + ;; + + sysv4.3*) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_shlibpath_var=no + export_dynamic_flag_spec='-Bexport' + ;; + + sysv4*MP*) + if test -d /usr/nec; then + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_shlibpath_var=no + runpath_var=LD_RUN_PATH + hardcode_runpath_var=yes + ld_shlibs=yes + fi + ;; + + sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*) + no_undefined_flag='${wl}-z,text' + archive_cmds_need_lc=no + hardcode_shlibpath_var=no + runpath_var='LD_RUN_PATH' + + if test "$GCC" = yes; then + archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + fi + ;; + + sysv5* | sco3.2v5* | sco5v6*) + # Note: We can NOT use -z defs as we might desire, because we do not + # link with -lc, and that would cause any symbols used from libc to + # always be unresolved, which means just about no library would + # ever link correctly. If we're not using GNU ld we use -z text + # though, which does catch some bad symbols but isn't as heavy-handed + # as -z defs. + no_undefined_flag='${wl}-z,text' + allow_undefined_flag='${wl}-z,nodefs' + archive_cmds_need_lc=no + hardcode_shlibpath_var=no + hardcode_libdir_flag_spec='${wl}-R,$libdir' + hardcode_libdir_separator=':' + link_all_deplibs=yes + export_dynamic_flag_spec='${wl}-Bexport' + runpath_var='LD_RUN_PATH' + + if test "$GCC" = yes; then + archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + else + archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' + fi + ;; + + uts4*) + archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' + hardcode_libdir_flag_spec='-L$libdir' + hardcode_shlibpath_var=no + ;; + + *) + ld_shlibs=no + ;; + esac + + if test x$host_vendor = xsni; then + case $host in + sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) + export_dynamic_flag_spec='${wl}-Blargedynsym' + ;; + esac + fi + fi + +echo "$as_me:$LINENO: result: $ld_shlibs" >&5 +echo "${ECHO_T}$ld_shlibs" >&6 +test "$ld_shlibs" = no && can_build_shared=no + +with_gnu_ld=$with_gnu_ld + + + + + + + + + + + + + + + +# +# Do we need to explicitly link libc? +# +case "x$archive_cmds_need_lc" in +x|xyes) + # Assume -lc should be added + archive_cmds_need_lc=yes + + if test "$enable_shared" = yes && test "$GCC" = yes; then + case $archive_cmds in + *'~'*) + # FIXME: we may have to deal with multi-command sequences. + ;; + '$CC '*) + # Test whether the compiler implicitly links with -lc since on some + # systems, -lgcc has to come before -lc. If gcc already passes -lc + # to ld, don't add -lc before -lgcc. + echo "$as_me:$LINENO: checking whether -lc should be explicitly linked in" >&5 +echo $ECHO_N "checking whether -lc should be explicitly linked in... $ECHO_C" >&6 + $RM conftest* + echo "$lt_simple_compile_test_code" > conftest.$ac_ext + + if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } 2>conftest.err; then + soname=conftest + lib=conftest + libobjs=conftest.$ac_objext + deplibs= + wl=$lt_prog_compiler_wl + pic_flag=$lt_prog_compiler_pic + compiler_flags=-v + linker_flags=-v + verstring= + output_objdir=. + libname=conftest + lt_save_allow_undefined_flag=$allow_undefined_flag + allow_undefined_flag= + if { (eval echo "$as_me:$LINENO: \"$archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1\"") >&5 + (eval $archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } + then + archive_cmds_need_lc=no + else + archive_cmds_need_lc=yes + fi + allow_undefined_flag=$lt_save_allow_undefined_flag + else + cat conftest.err 1>&5 + fi + $RM conftest* + echo "$as_me:$LINENO: result: $archive_cmds_need_lc" >&5 +echo "${ECHO_T}$archive_cmds_need_lc" >&6 + ;; + esac + fi + ;; +esac + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + echo "$as_me:$LINENO: checking dynamic linker characteristics" >&5 +echo $ECHO_N "checking dynamic linker characteristics... $ECHO_C" >&6 +withGCC=$GCC +if test "$withGCC" = yes; then + case $host_os in + darwin*) lt_awk_arg="/^libraries:/,/LR/" ;; + *) lt_awk_arg="/^libraries:/" ;; + esac + lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e "s,=/,/,g"` + if $ECHO "$lt_search_path_spec" | $GREP ';' >/dev/null ; then + # if the path contains ";" then we assume it to be the separator + # otherwise default to the standard path separator (i.e. ":") - it is + # assumed that no part of a normal pathname contains ";" but that should + # okay in the real world where ";" in dirpaths is itself problematic. + lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED -e 's/;/ /g'` + else + lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` + fi + # Ok, now we have the path, separated by spaces, we can step through it + # and add multilib dir if necessary. + lt_tmp_lt_search_path_spec= + lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS -print-multi-os-directory 2>/dev/null` + for lt_sys_path in $lt_search_path_spec; do + if test -d "$lt_sys_path/$lt_multi_os_dir"; then + lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path/$lt_multi_os_dir" + else + test -d "$lt_sys_path" && \ + lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path" + fi + done + lt_search_path_spec=`$ECHO $lt_tmp_lt_search_path_spec | awk ' +BEGIN {RS=" "; FS="/|\n";} { + lt_foo=""; + lt_count=0; + for (lt_i = NF; lt_i > 0; lt_i--) { + if ($lt_i != "" && $lt_i != ".") { + if ($lt_i == "..") { + lt_count++; + } else { + if (lt_count == 0) { + lt_foo="/" $lt_i lt_foo; + } else { + lt_count--; + } + } + } + } + if (lt_foo != "") { lt_freq[lt_foo]++; } + if (lt_freq[lt_foo] == 1) { print lt_foo; } +}'` + sys_lib_search_path_spec=`$ECHO $lt_search_path_spec` +else + sys_lib_search_path_spec="/lib /usr/lib /usr/local/lib" +fi +library_names_spec= +libname_spec='lib$name' +soname_spec= +shrext_cmds=".so" +postinstall_cmds= +postuninstall_cmds= +finish_cmds= +finish_eval= +shlibpath_var= +shlibpath_overrides_runpath=unknown +version_type=none +dynamic_linker="$host_os ld.so" +sys_lib_dlsearch_path_spec="/lib /usr/lib" +need_lib_prefix=unknown +hardcode_into_libs=no + +# when you set need_version to no, make sure it does not cause -set_version +# flags to be left without arguments +need_version=unknown + +case $host_os in +aix3*) + version_type=linux + library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a' + shlibpath_var=LIBPATH + + # AIX 3 has no versioning support, so we append a major version to the name. + soname_spec='${libname}${release}${shared_ext}$major' + ;; + +aix4* | aix5*) + version_type=linux + need_lib_prefix=no + need_version=no + hardcode_into_libs=yes + if test "$host_cpu" = ia64; then + # AIX 5 supports IA64 + library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + else + # With GCC up to 2.95.x, collect2 would create an import file + # for dependence libraries. The import file would start with + # the line `#! .'. This would cause the generated library to + # depend on `.', always an invalid library. This was fixed in + # development snapshots of GCC prior to 3.0. + case $host_os in + aix4 | aix4.[01] | aix4.[01].*) + if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)' + echo ' yes ' + echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then + : + else + can_build_shared=no + fi + ;; + esac + # AIX (on Power*) has no versioning support, so currently we can not hardcode correct + # soname into executable. Probably we can add versioning support to + # collect2, so additional links can be useful in future. + if test "$aix_use_runtimelinking" = yes; then + # If using run time linking (on AIX 4.2 or later) use lib<name>.so + # instead of lib<name>.a to let people know that these are not + # typical AIX shared libraries. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + else + # We preserve .a as extension for shared libraries through AIX4.2 + # and later when we are not doing run time linking. + library_names_spec='${libname}${release}.a $libname.a' + soname_spec='${libname}${release}${shared_ext}$major' + fi + shlibpath_var=LIBPATH + fi + ;; + +amigaos*) + if test "$host_cpu" = m68k; then + library_names_spec='$libname.ixlibrary $libname.a' + # Create ${libname}_ixlibrary.a entries in /sys/libs. + finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`$ECHO "X$lib" | $Xsed -e '\''s%^.*/\([^/]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done' + else + dynamic_linker=no + fi + ;; + +beos*) + library_names_spec='${libname}${shared_ext}' + dynamic_linker="$host_os ld.so" + shlibpath_var=LIBRARY_PATH + ;; + +bsdi[45]*) + version_type=linux + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir' + shlibpath_var=LD_LIBRARY_PATH + sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib" + sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib" + # the default ld.so.conf also contains /usr/contrib/lib and + # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow + # libtool to hard-code these into programs + ;; + +cygwin* | mingw* | pw32*) + version_type=windows + shrext_cmds=".dll" + need_version=no + need_lib_prefix=no + + case $withGCC,$host_os in + yes,cygwin* | yes,mingw* | yes,pw32*) + library_names_spec='$libname.dll.a' + # DLL is installed to $(libdir)/../bin by postinstall_cmds + postinstall_cmds='base_file=`basename \${file}`~ + dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ + dldir=$destdir/`dirname \$dlpath`~ + test -d \$dldir || mkdir -p \$dldir~ + $install_prog $dir/$dlname \$dldir/$dlname~ + chmod a+x \$dldir/$dlname~ + if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then + eval '\''$striplib \$dldir/$dlname'\'' || exit \$?; + fi' + postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ + dlpath=$dir/\$dldll~ + $RM \$dlpath' + shlibpath_overrides_runpath=yes + + case $host_os in + cygwin*) + # Cygwin DLLs use 'cyg' prefix rather than 'lib' + soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + sys_lib_search_path_spec="/usr/lib /lib/w32api /lib /usr/local/lib" + ;; + mingw*) + # MinGW DLLs use traditional 'lib' prefix + soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + sys_lib_search_path_spec=`$CC -print-search-dirs | $GREP "^libraries:" | $SED -e "s/^libraries://" -e "s,=/,/,g"` + if $ECHO "$sys_lib_search_path_spec" | $GREP ';[c-zC-Z]:/' >/dev/null; then + # It is most probably a Windows format PATH printed by + # mingw gcc, but we are running on Cygwin. Gcc prints its search + # path with ; separators, and with drive letters. We can handle the + # drive letters (cygwin fileutils understands them), so leave them, + # especially as we might pass files found there to a mingw objdump, + # which wouldn't understand a cygwinified path. Ahh. + sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e 's/;/ /g'` + else + sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` + fi + ;; + pw32*) + # pw32 DLLs use 'pw' prefix rather than 'lib' + library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' + ;; + esac + ;; + + *) + library_names_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext} $libname.lib' + ;; + esac + dynamic_linker='Win32 ld.exe' + # FIXME: first we should search . and the directory the executable is in + shlibpath_var=PATH + ;; + +darwin* | rhapsody*) + dynamic_linker="$host_os dyld" + version_type=darwin + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext' + soname_spec='${libname}${release}${major}$shared_ext' + shlibpath_overrides_runpath=yes + shlibpath_var=DYLD_LIBRARY_PATH + shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`' + + sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/local/lib" + sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib' + ;; + +dgux*) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + ;; + +freebsd1*) + dynamic_linker=no + ;; + +freebsd* | dragonfly*) + # DragonFly does not have aout. When/if they implement a new + # versioning mechanism, adjust this. + if test -x /usr/bin/objformat; then + objformat=`/usr/bin/objformat` + else + case $host_os in + freebsd[123]*) objformat=aout ;; + *) objformat=elf ;; + esac + fi + version_type=freebsd-$objformat + case $version_type in + freebsd-elf*) + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' + need_version=no + need_lib_prefix=no + ;; + freebsd-*) + library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix' + need_version=yes + ;; + esac + shlibpath_var=LD_LIBRARY_PATH + case $host_os in + freebsd2*) + shlibpath_overrides_runpath=yes + ;; + freebsd3.[01]* | freebsdelf3.[01]*) + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + freebsd3.[2-9]* | freebsdelf3.[2-9]* | \ + freebsd4.[0-5] | freebsdelf4.[0-5] | freebsd4.1.1 | freebsdelf4.1.1) + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + *) # from 4.6 on, and DragonFly + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; + esac + ;; + +gnu*) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + hardcode_into_libs=yes + ;; + +hpux9* | hpux10* | hpux11*) + # Give a soname corresponding to the major version so that dld.sl refuses to + # link against other versions. + version_type=sunos + need_lib_prefix=no + need_version=no + case $host_cpu in + ia64*) + shrext_cmds='.so' + hardcode_into_libs=yes + dynamic_linker="$host_os dld.so" + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + if test "X$HPUX_IA64_MODE" = X32; then + sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib" + else + sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64" + fi + sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec + ;; + hppa*64*) + shrext_cmds='.sl' + hardcode_into_libs=yes + dynamic_linker="$host_os dld.sl" + shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH + shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64" + sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec + ;; + *) + shrext_cmds='.sl' + dynamic_linker="$host_os dld.sl" + shlibpath_var=SHLIB_PATH + shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + ;; + esac + # HP-UX runs *really* slowly unless shared libraries are mode 555. + postinstall_cmds='chmod 555 $lib' + ;; + +interix[3-9]*) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +irix5* | irix6* | nonstopux*) + case $host_os in + nonstopux*) version_type=nonstopux ;; + *) + if test "$lt_cv_prog_gnu_ld" = yes; then + version_type=linux + else + version_type=irix + fi ;; + esac + need_lib_prefix=no + need_version=no + soname_spec='${libname}${release}${shared_ext}$major' + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}' + case $host_os in + irix5* | nonstopux*) + libsuff= shlibsuff= + ;; + *) + case $LD in # libtool.m4 will add one of these switches to LD + *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ") + libsuff= shlibsuff= libmagic=32-bit;; + *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ") + libsuff=32 shlibsuff=N32 libmagic=N32;; + *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ") + libsuff=64 shlibsuff=64 libmagic=64-bit;; + *) libsuff= shlibsuff= libmagic=never-match;; + esac + ;; + esac + shlibpath_var=LD_LIBRARY${shlibsuff}_PATH + shlibpath_overrides_runpath=no + sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}" + sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}" + hardcode_into_libs=yes + ;; + +# No shared lib support for Linux oldld, aout, or coff. +linux*oldld* | linux*aout* | linux*coff*) + dynamic_linker=no + ;; + +# This must be Linux ELF. +linux* | k*bsd*-gnu) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + # Some binutils ld are patched to set DT_RUNPATH + save_LDFLAGS=$LDFLAGS + save_libdir=$libdir + eval "libdir=/foo; wl=\"$lt_prog_compiler_wl\"; \ + LDFLAGS=\"\$LDFLAGS $hardcode_libdir_flag_spec\"" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func. - For example, HP-UX 11i <limits.h> declares gettimeofday. */ -#define $ac_func innocuous_$ac_func - -/* System header to define __stub macros and hopefully few prototypes, - which can conflict with char $ac_func (); below. - Prefer <limits.h> to <assert.h> if __STDC__ is defined, since - <limits.h> exists even on freestanding compilers. */ - -#ifdef __STDC__ -# include <limits.h> -#else -# include <assert.h> -#endif - -#undef $ac_func - -/* Override any gcc2 internal prototype to avoid an error. */ -#ifdef __cplusplus -extern "C" -{ -#endif -/* We use char because int might match the return type of a gcc2 - builtin and then its argument prototype would still apply. */ -char $ac_func (); -/* The GNU C library defines this for functions which it implements - to always fail with ENOSYS. Some functions are actually named - something starting with __ and the normal name is an alias. */ -#if defined (__stub_$ac_func) || defined (__stub___$ac_func) -choke me -#else -char (*f) () = $ac_func; -#endif -#ifdef __cplusplus -} -#endif int main () { -return f != $ac_func; + ; return 0; } @@ -6368,126 +8401,425 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - eval "$as_ac_var=yes" + if ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir"; then + shlibpath_overrides_runpath=yes +fi + else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -eval "$as_ac_var=no" fi rm -f conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext -fi -echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 -echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 -if test `eval echo '${'$as_ac_var'}'` = yes; then + LDFLAGS=$save_LDFLAGS + libdir=$save_libdir + + # This implies no fast_install, which is unacceptable. + # Some rework will be needed to allow for fast_install + # before this can be enabled. + hardcode_into_libs=yes + + # Append ld.so.conf contents to the search path + if test -f /etc/ld.so.conf; then + lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;/^$/d' | tr '\n' ' '` + sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra" + fi -cat >>confdefs.h <<_ACEOF -#define CRAY_STACKSEG_END $ac_func -_ACEOF + # We used to test for /lib/ld.so.1 and disable shared libraries on + # powerpc, because MkLinux only supported shared libraries with the + # GNU dynamic linker. Since this was broken with cross compilers, + # most powerpc-linux boxes support dynamic linking these days and + # people can always --disable-shared, the test was removed, and we + # assume the GNU/Linux dynamic linker is in use. + dynamic_linker='GNU/Linux ld.so' + ;; - break -fi +netbsd*) + version_type=sunos + need_lib_prefix=no + need_version=no + if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' + dynamic_linker='NetBSD (a.out) ld.so' + else + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + dynamic_linker='NetBSD ld.elf_so' + fi + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + ;; - done -fi +newsos6) + version_type=linux + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + ;; -echo "$as_me:$LINENO: checking stack direction for C alloca" >&5 -echo $ECHO_N "checking stack direction for C alloca... $ECHO_C" >&6 -if test "${ac_cv_c_stack_direction+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - if test "$cross_compiling" = yes; then - ac_cv_c_stack_direction=0 -else - cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -int -find_stack_direction () -{ - static char *addr = 0; - auto char dummy; - if (addr == 0) - { - addr = &dummy; - return find_stack_direction (); - } +*nto* | *qnx*) + version_type=qnx + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + dynamic_linker='ldqnx.so' + ;; + +openbsd*) + version_type=sunos + sys_lib_dlsearch_path_spec="/usr/lib" + need_lib_prefix=no + # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs. + case $host_os in + openbsd3.3 | openbsd3.3.*) need_version=yes ;; + *) need_version=no ;; + esac + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' + shlibpath_var=LD_LIBRARY_PATH + if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then + case $host_os in + openbsd2.[89] | openbsd2.[89].*) + shlibpath_overrides_runpath=no + ;; + *) + shlibpath_overrides_runpath=yes + ;; + esac else - return (&dummy > addr) ? 1 : -1; -} + shlibpath_overrides_runpath=yes + fi + ;; -int -main () -{ - exit (find_stack_direction () < 0); -} -_ACEOF -rm -f conftest$ac_exeext -if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { ac_try='./conftest$ac_exeext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - ac_cv_c_stack_direction=1 -else - echo "$as_me: program exited with status $ac_status" >&5 -echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 +os2*) + libname_spec='$name' + shrext_cmds=".dll" + need_lib_prefix=no + library_names_spec='$libname${shared_ext} $libname.a' + dynamic_linker='OS/2 ld.exe' + shlibpath_var=LIBPATH + ;; -( exit $ac_status ) -ac_cv_c_stack_direction=-1 +osf3* | osf4* | osf5*) + version_type=osf + need_lib_prefix=no + need_version=no + soname_spec='${libname}${release}${shared_ext}$major' + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib" + sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec" + ;; + +rdos*) + dynamic_linker=no + ;; + +solaris*) + version_type=linux + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + # ldd complains unless libraries are executable + postinstall_cmds='chmod +x $lib' + ;; + +sunos4*) + version_type=sunos + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' + finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + if test "$with_gnu_ld" = yes; then + need_lib_prefix=no + fi + need_version=yes + ;; + +sysv4 | sysv4.3*) + version_type=linux + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + case $host_vendor in + sni) + shlibpath_overrides_runpath=no + need_lib_prefix=no + runpath_var=LD_RUN_PATH + ;; + siemens) + need_lib_prefix=no + ;; + motorola) + need_lib_prefix=no + need_version=no + shlibpath_overrides_runpath=no + sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib' + ;; + esac + ;; + +sysv4*MP*) + if test -d /usr/nec ;then + version_type=linux + library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}' + soname_spec='$libname${shared_ext}.$major' + shlibpath_var=LD_LIBRARY_PATH + fi + ;; + +sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) + version_type=freebsd-elf + need_lib_prefix=no + need_version=no + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=yes + hardcode_into_libs=yes + if test "$with_gnu_ld" = yes; then + sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib' + else + sys_lib_search_path_spec='/usr/ccs/lib /usr/lib' + case $host_os in + sco3.2v5*) + sys_lib_search_path_spec="$sys_lib_search_path_spec /lib" + ;; + esac + fi + sys_lib_dlsearch_path_spec='/usr/lib' + ;; + +tpf*) + # TPF is a cross-target only. Preferred cross-host = GNU/Linux. + version_type=linux + need_lib_prefix=no + need_version=no + library_name_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + shlibpath_var=LD_LIBRARY_PATH + shlibpath_overrides_runpath=no + hardcode_into_libs=yes + ;; + +uts4*) + version_type=linux + library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' + soname_spec='${libname}${release}${shared_ext}$major' + shlibpath_var=LD_LIBRARY_PATH + ;; + +*) + dynamic_linker=no + ;; +esac +echo "$as_me:$LINENO: result: $dynamic_linker" >&5 +echo "${ECHO_T}$dynamic_linker" >&6 +test "$dynamic_linker" = no && can_build_shared=no + +variables_saved_for_relink="PATH $shlibpath_var $runpath_var" +if test "$GCC" = yes; then + variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH" fi -rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + echo "$as_me:$LINENO: checking how to hardcode library paths into programs" >&5 +echo $ECHO_N "checking how to hardcode library paths into programs... $ECHO_C" >&6 +hardcode_action= +if test -n "$hardcode_libdir_flag_spec" || + test -n "$runpath_var" || + test "X$hardcode_automatic" = "Xyes" ; then + + # We can hardcode non-existent directories. + if test "$hardcode_direct" != no && + # If the only mechanism to avoid hardcoding is shlibpath_var, we + # have to relink, otherwise we might link with an installed library + # when we should be linking with a yet-to-be-installed one + ## test "$_LT_TAGVAR(hardcode_shlibpath_var, )" != no && + test "$hardcode_minus_L" != no; then + # Linking always hardcodes the temporary library directory. + hardcode_action=relink + else + # We can link without hardcoding, and we can hardcode nonexisting dirs. + hardcode_action=immediate + fi +else + # We cannot hardcode anything, or else we can only hardcode existing + # directories. + hardcode_action=unsupported fi +echo "$as_me:$LINENO: result: $hardcode_action" >&5 +echo "${ECHO_T}$hardcode_action" >&6 + +if test "$hardcode_action" = relink || + test "$inherit_rpath" = yes; then + # Fast installation is not supported + enable_fast_install=no +elif test "$shlibpath_overrides_runpath" = yes || + test "$enable_shared" = no; then + # Fast installation is not necessary + enable_fast_install=needless fi -echo "$as_me:$LINENO: result: $ac_cv_c_stack_direction" >&5 -echo "${ECHO_T}$ac_cv_c_stack_direction" >&6 -cat >>confdefs.h <<_ACEOF -#define STACK_DIRECTION $ac_cv_c_stack_direction -_ACEOF -fi -for ac_header in stdlib.h unistd.h -do -as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` -if eval "test \"\${$as_ac_Header+set}\" = set"; then - echo "$as_me:$LINENO: checking for $ac_header" >&5 -echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6 -if eval "test \"\${$as_ac_Header+set}\" = set"; then + if test "x$enable_dlopen" != xyes; then + enable_dlopen=unknown + enable_dlopen_self=unknown + enable_dlopen_self_static=unknown +else + lt_cv_dlopen=no + lt_cv_dlopen_libs= + + case $host_os in + beos*) + lt_cv_dlopen="load_add_on" + lt_cv_dlopen_libs= + lt_cv_dlopen_self=yes + ;; + + mingw* | pw32*) + lt_cv_dlopen="LoadLibrary" + lt_cv_dlopen_libs= + ;; + + cygwin*) + lt_cv_dlopen="dlopen" + lt_cv_dlopen_libs= + ;; + + darwin*) + # if libdl is installed we need to link against it + echo "$as_me:$LINENO: checking for dlopen in -ldl" >&5 +echo $ECHO_N "checking for dlopen in -ldl... $ECHO_C" >&6 +if test "${ac_cv_lib_dl_dlopen+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 -fi -echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5 -echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6 else - # Is the header compilable? -echo "$as_me:$LINENO: checking $ac_header usability" >&5 -echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6 + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldl $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -$ac_includes_default -#include <$ac_header> + +/* Override any gcc2 internal prototype to avoid an error. */ +#ifdef __cplusplus +extern "C" +#endif +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char dlopen (); +int +main () +{ +dlopen (); + ; + return 0; +} _ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 +rm -f conftest.$ac_objext conftest$ac_exeext +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -6501,122 +8833,41 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - ac_header_compiler=yes + ac_cv_lib_dl_dlopen=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -ac_header_compiler=no +ac_cv_lib_dl_dlopen=no fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 -echo "${ECHO_T}$ac_header_compiler" >&6 - -# Is the header present? -echo "$as_me:$LINENO: checking $ac_header presence" >&5 -echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6 -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <$ac_header> -_ACEOF -if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 - (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } >/dev/null; then - if test -s conftest.err; then - ac_cpp_err=$ac_c_preproc_warn_flag - ac_cpp_err=$ac_cpp_err$ac_c_werror_flag - else - ac_cpp_err= - fi -else - ac_cpp_err=yes +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS fi -if test -z "$ac_cpp_err"; then - ac_header_preproc=yes +echo "$as_me:$LINENO: result: $ac_cv_lib_dl_dlopen" >&5 +echo "${ECHO_T}$ac_cv_lib_dl_dlopen" >&6 +if test $ac_cv_lib_dl_dlopen = yes; then + lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - ac_header_preproc=no -fi -rm -f conftest.err conftest.$ac_ext -echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 -echo "${ECHO_T}$ac_header_preproc" >&6 + lt_cv_dlopen="dyld" + lt_cv_dlopen_libs= + lt_cv_dlopen_self=yes -# So? What about this header? -case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in - yes:no: ) - { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 -echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 -echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} - ac_header_preproc=yes - ;; - no:yes:* ) - { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 -echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 -echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 -echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 -echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 -echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 -echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} - ( - cat <<\_ASBOX -## ------------------------------------------ ## -## Report this to the AC_PACKAGE_NAME lists. ## -## ------------------------------------------ ## -_ASBOX - ) | - sed "s/^/$as_me: WARNING: /" >&2 - ;; -esac -echo "$as_me:$LINENO: checking for $ac_header" >&5 -echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6 -if eval "test \"\${$as_ac_Header+set}\" = set"; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - eval "$as_ac_Header=\$ac_header_preproc" fi -echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5 -echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6 - -fi -if test `eval echo '${'$as_ac_Header'}'` = yes; then - cat >>confdefs.h <<_ACEOF -#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 -_ACEOF - -fi - -done + ;; -for ac_func in getpagesize -do -as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` -echo "$as_me:$LINENO: checking for $ac_func" >&5 -echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6 -if eval "test \"\${$as_ac_var+set}\" = set"; then + *) + echo "$as_me:$LINENO: checking for shl_load" >&5 +echo $ECHO_N "checking for shl_load... $ECHO_C" >&6 +if test "${ac_cv_func_shl_load+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF @@ -6625,12 +8876,12 @@ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func. +/* Define shl_load to an innocuous variant, in case <limits.h> declares shl_load. For example, HP-UX 11i <limits.h> declares gettimeofday. */ -#define $ac_func innocuous_$ac_func +#define shl_load innocuous_shl_load /* System header to define __stub macros and hopefully few prototypes, - which can conflict with char $ac_func (); below. + which can conflict with char shl_load (); below. Prefer <limits.h> to <assert.h> if __STDC__ is defined, since <limits.h> exists even on freestanding compilers. */ @@ -6640,7 +8891,7 @@ cat >>conftest.$ac_ext <<_ACEOF # include <assert.h> #endif -#undef $ac_func +#undef shl_load /* Override any gcc2 internal prototype to avoid an error. */ #ifdef __cplusplus @@ -6649,14 +8900,14 @@ extern "C" #endif /* We use char because int might match the return type of a gcc2 builtin and then its argument prototype would still apply. */ -char $ac_func (); +char shl_load (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ -#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +#if defined (__stub_shl_load) || defined (__stub___shl_load) choke me #else -char (*f) () = $ac_func; +char (*f) () = shl_load; #endif #ifdef __cplusplus } @@ -6665,7 +8916,7 @@ char (*f) () = $ac_func; int main () { -return f != $ac_func; +return f != shl_load; ; return 0; } @@ -6692,239 +8943,53 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - eval "$as_ac_var=yes" + ac_cv_func_shl_load=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -eval "$as_ac_var=no" +ac_cv_func_shl_load=no fi rm -f conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext fi -echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 -echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 -if test `eval echo '${'$as_ac_var'}'` = yes; then - cat >>confdefs.h <<_ACEOF -#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 -_ACEOF - -fi -done - -echo "$as_me:$LINENO: checking for working mmap" >&5 -echo $ECHO_N "checking for working mmap... $ECHO_C" >&6 -if test "${ac_cv_func_mmap_fixed_mapped+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 +echo "$as_me:$LINENO: result: $ac_cv_func_shl_load" >&5 +echo "${ECHO_T}$ac_cv_func_shl_load" >&6 +if test $ac_cv_func_shl_load = yes; then + lt_cv_dlopen="shl_load" else - if test "$cross_compiling" = yes; then - ac_cv_func_mmap_fixed_mapped=no + echo "$as_me:$LINENO: checking for shl_load in -ldld" >&5 +echo $ECHO_N "checking for shl_load in -ldld... $ECHO_C" >&6 +if test "${ac_cv_lib_dld_shl_load+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 else - cat >conftest.$ac_ext <<_ACEOF + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldld $LIBS" +cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -$ac_includes_default -/* malloc might have been renamed as rpl_malloc. */ -#undef malloc - -/* Thanks to Mike Haertel and Jim Avera for this test. - Here is a matrix of mmap possibilities: - mmap private not fixed - mmap private fixed at somewhere currently unmapped - mmap private fixed at somewhere already mapped - mmap shared not fixed - mmap shared fixed at somewhere currently unmapped - mmap shared fixed at somewhere already mapped - For private mappings, we should verify that changes cannot be read() - back from the file, nor mmap's back from the file at a different - address. (There have been systems where private was not correctly - implemented like the infamous i386 svr4.0, and systems where the - VM page cache was not coherent with the file system buffer cache - like early versions of FreeBSD and possibly contemporary NetBSD.) - For shared mappings, we should conversely verify that changes get - propagated back to all the places they're supposed to be. - - Grep wants private fixed already mapped. - The main things grep needs to know about mmap are: - * does it exist and is it safe to write into the mmap'd area - * how to use it (BSD variants) */ - -#include <fcntl.h> -#include <sys/mman.h> - -#if !STDC_HEADERS && !HAVE_STDLIB_H -char *malloc (); -#endif - -/* This mess was copied from the GNU getpagesize.h. */ -#if !HAVE_GETPAGESIZE -/* Assume that all systems that can run configure have sys/param.h. */ -# if !HAVE_SYS_PARAM_H -# define HAVE_SYS_PARAM_H 1 -# endif - -# ifdef _SC_PAGESIZE -# define getpagesize() sysconf(_SC_PAGESIZE) -# else /* no _SC_PAGESIZE */ -# if HAVE_SYS_PARAM_H -# include <sys/param.h> -# ifdef EXEC_PAGESIZE -# define getpagesize() EXEC_PAGESIZE -# else /* no EXEC_PAGESIZE */ -# ifdef NBPG -# define getpagesize() NBPG * CLSIZE -# ifndef CLSIZE -# define CLSIZE 1 -# endif /* no CLSIZE */ -# else /* no NBPG */ -# ifdef NBPC -# define getpagesize() NBPC -# else /* no NBPC */ -# ifdef PAGESIZE -# define getpagesize() PAGESIZE -# endif /* PAGESIZE */ -# endif /* no NBPC */ -# endif /* no NBPG */ -# endif /* no EXEC_PAGESIZE */ -# else /* no HAVE_SYS_PARAM_H */ -# define getpagesize() 8192 /* punt totally */ -# endif /* no HAVE_SYS_PARAM_H */ -# endif /* no _SC_PAGESIZE */ - -#endif /* no HAVE_GETPAGESIZE */ +/* Override any gcc2 internal prototype to avoid an error. */ +#ifdef __cplusplus +extern "C" +#endif +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char shl_load (); int main () { - char *data, *data2, *data3; - int i, pagesize; - int fd; - - pagesize = getpagesize (); - - /* First, make a file with some known garbage in it. */ - data = (char *) malloc (pagesize); - if (!data) - exit (1); - for (i = 0; i < pagesize; ++i) - *(data + i) = rand (); - umask (0); - fd = creat ("conftest.mmap", 0600); - if (fd < 0) - exit (1); - if (write (fd, data, pagesize) != pagesize) - exit (1); - close (fd); - - /* Next, try to mmap the file at a fixed address which already has - something else allocated at it. If we can, also make sure that - we see the same garbage. */ - fd = open ("conftest.mmap", O_RDWR); - if (fd < 0) - exit (1); - data2 = (char *) malloc (2 * pagesize); - if (!data2) - exit (1); - data2 += (pagesize - ((long) data2 & (pagesize - 1))) & (pagesize - 1); - if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE, - MAP_PRIVATE | MAP_FIXED, fd, 0L)) - exit (1); - for (i = 0; i < pagesize; ++i) - if (*(data + i) != *(data2 + i)) - exit (1); - - /* Finally, make sure that changes to the mapped area do not - percolate back to the file as seen by read(). (This is a bug on - some variants of i386 svr4.0.) */ - for (i = 0; i < pagesize; ++i) - *(data2 + i) = *(data2 + i) + 1; - data3 = (char *) malloc (pagesize); - if (!data3) - exit (1); - if (read (fd, data3, pagesize) != pagesize) - exit (1); - for (i = 0; i < pagesize; ++i) - if (*(data + i) != *(data3 + i)) - exit (1); - close (fd); - exit (0); +shl_load (); + ; + return 0; } _ACEOF -rm -f conftest$ac_exeext +rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && { ac_try='./conftest$ac_exeext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - ac_cv_func_mmap_fixed_mapped=yes -else - echo "$as_me: program exited with status $ac_status" >&5 -echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - -( exit $ac_status ) -ac_cv_func_mmap_fixed_mapped=no -fi -rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext -fi -fi -echo "$as_me:$LINENO: result: $ac_cv_func_mmap_fixed_mapped" >&5 -echo "${ECHO_T}$ac_cv_func_mmap_fixed_mapped" >&6 -if test $ac_cv_func_mmap_fixed_mapped = yes; then - -cat >>confdefs.h <<\_ACEOF -#define HAVE_MMAP 1 -_ACEOF - -fi -rm -f conftest.mmap - - - - - - - - - - - -for ac_header in argz.h limits.h locale.h nl_types.h malloc.h string.h \ -unistd.h values.h sys/param.h -do -as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` -if eval "test \"\${$as_ac_Header+set}\" = set"; then - echo "$as_me:$LINENO: checking for $ac_header" >&5 -echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6 -if eval "test \"\${$as_ac_Header+set}\" = set"; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -fi -echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5 -echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6 -else - # Is the header compilable? -echo "$as_me:$LINENO: checking $ac_header usability" >&5 -echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6 -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -$ac_includes_default -#include <$ac_header> -_ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 + (eval $ac_link) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -6938,132 +9003,31 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - ac_header_compiler=yes + ac_cv_lib_dld_shl_load=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -ac_header_compiler=no +ac_cv_lib_dld_shl_load=no fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 -echo "${ECHO_T}$ac_header_compiler" >&6 - -# Is the header present? -echo "$as_me:$LINENO: checking $ac_header presence" >&5 -echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6 -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <$ac_header> -_ACEOF -if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 - (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } >/dev/null; then - if test -s conftest.err; then - ac_cpp_err=$ac_c_preproc_warn_flag - ac_cpp_err=$ac_cpp_err$ac_c_werror_flag - else - ac_cpp_err= - fi -else - ac_cpp_err=yes -fi -if test -z "$ac_cpp_err"; then - ac_header_preproc=yes -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - - ac_header_preproc=no +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS fi -rm -f conftest.err conftest.$ac_ext -echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 -echo "${ECHO_T}$ac_header_preproc" >&6 - -# So? What about this header? -case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in - yes:no: ) - { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 -echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 -echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} - ac_header_preproc=yes - ;; - no:yes:* ) - { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 -echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 -echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 -echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 -echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 -echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} - { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 -echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} - ( - cat <<\_ASBOX -## ------------------------------------------ ## -## Report this to the AC_PACKAGE_NAME lists. ## -## ------------------------------------------ ## -_ASBOX - ) | - sed "s/^/$as_me: WARNING: /" >&2 - ;; -esac -echo "$as_me:$LINENO: checking for $ac_header" >&5 -echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6 -if eval "test \"\${$as_ac_Header+set}\" = set"; then - echo $ECHO_N "(cached) $ECHO_C" >&6 +echo "$as_me:$LINENO: result: $ac_cv_lib_dld_shl_load" >&5 +echo "${ECHO_T}$ac_cv_lib_dld_shl_load" >&6 +if test $ac_cv_lib_dld_shl_load = yes; then + lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-dld" else - eval "$as_ac_Header=\$ac_header_preproc" -fi -echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5 -echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6 - -fi -if test `eval echo '${'$as_ac_Header'}'` = yes; then - cat >>confdefs.h <<_ACEOF -#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 -_ACEOF - -fi - -done - - - - - - - - - - - -for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \ -__argz_count __argz_stringify __argz_next -do -as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` -echo "$as_me:$LINENO: checking for $ac_func" >&5 -echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6 -if eval "test \"\${$as_ac_var+set}\" = set"; then + echo "$as_me:$LINENO: checking for dlopen" >&5 +echo $ECHO_N "checking for dlopen... $ECHO_C" >&6 +if test "${ac_cv_func_dlopen+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF @@ -7072,12 +9036,12 @@ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func. +/* Define dlopen to an innocuous variant, in case <limits.h> declares dlopen. For example, HP-UX 11i <limits.h> declares gettimeofday. */ -#define $ac_func innocuous_$ac_func +#define dlopen innocuous_dlopen /* System header to define __stub macros and hopefully few prototypes, - which can conflict with char $ac_func (); below. + which can conflict with char dlopen (); below. Prefer <limits.h> to <assert.h> if __STDC__ is defined, since <limits.h> exists even on freestanding compilers. */ @@ -7087,7 +9051,7 @@ cat >>conftest.$ac_ext <<_ACEOF # include <assert.h> #endif -#undef $ac_func +#undef dlopen /* Override any gcc2 internal prototype to avoid an error. */ #ifdef __cplusplus @@ -7096,14 +9060,14 @@ extern "C" #endif /* We use char because int might match the return type of a gcc2 builtin and then its argument prototype would still apply. */ -char $ac_func (); +char dlopen (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ -#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +#if defined (__stub_dlopen) || defined (__stub___dlopen) choke me #else -char (*f) () = $ac_func; +char (*f) () = dlopen; #endif #ifdef __cplusplus } @@ -7112,7 +9076,7 @@ char (*f) () = $ac_func; int main () { -return f != $ac_func; +return f != dlopen; ; return 0; } @@ -7139,84 +9103,46 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - eval "$as_ac_var=yes" + ac_cv_func_dlopen=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -eval "$as_ac_var=no" +ac_cv_func_dlopen=no fi rm -f conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext fi -echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 -echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 -if test `eval echo '${'$as_ac_var'}'` = yes; then - cat >>confdefs.h <<_ACEOF -#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 -_ACEOF - -fi -done - - - if test "${ac_cv_func_stpcpy+set}" != "set"; then - -for ac_func in stpcpy -do -as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` -echo "$as_me:$LINENO: checking for $ac_func" >&5 -echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6 -if eval "test \"\${$as_ac_var+set}\" = set"; then +echo "$as_me:$LINENO: result: $ac_cv_func_dlopen" >&5 +echo "${ECHO_T}$ac_cv_func_dlopen" >&6 +if test $ac_cv_func_dlopen = yes; then + lt_cv_dlopen="dlopen" +else + echo "$as_me:$LINENO: checking for dlopen in -ldl" >&5 +echo $ECHO_N "checking for dlopen in -ldl... $ECHO_C" >&6 +if test "${ac_cv_lib_dl_dlopen+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - cat >conftest.$ac_ext <<_ACEOF + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldl $LIBS" +cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func. - For example, HP-UX 11i <limits.h> declares gettimeofday. */ -#define $ac_func innocuous_$ac_func - -/* System header to define __stub macros and hopefully few prototypes, - which can conflict with char $ac_func (); below. - Prefer <limits.h> to <assert.h> if __STDC__ is defined, since - <limits.h> exists even on freestanding compilers. */ - -#ifdef __STDC__ -# include <limits.h> -#else -# include <assert.h> -#endif - -#undef $ac_func /* Override any gcc2 internal prototype to avoid an error. */ #ifdef __cplusplus extern "C" -{ #endif /* We use char because int might match the return type of a gcc2 builtin and then its argument prototype would still apply. */ -char $ac_func (); -/* The GNU C library defines this for functions which it implements - to always fail with ENOSYS. Some functions are actually named - something starting with __ and the normal name is an alias. */ -#if defined (__stub_$ac_func) || defined (__stub___$ac_func) -choke me -#else -char (*f) () = $ac_func; -#endif -#ifdef __cplusplus -} -#endif - +char dlopen (); int main () { -return f != $ac_func; +dlopen (); ; return 0; } @@ -7243,52 +9169,47 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - eval "$as_ac_var=yes" + ac_cv_lib_dl_dlopen=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -eval "$as_ac_var=no" +ac_cv_lib_dl_dlopen=no fi rm -f conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS fi -echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 -echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 -if test `eval echo '${'$as_ac_var'}'` = yes; then - cat >>confdefs.h <<_ACEOF -#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 -_ACEOF - -fi -done - - fi - if test "${ac_cv_func_stpcpy}" = "yes"; then - -cat >>confdefs.h <<\_ACEOF -#define HAVE_STPCPY 1 -_ACEOF - - fi - - if test $ac_cv_header_locale_h = yes; then - echo "$as_me:$LINENO: checking for LC_MESSAGES" >&5 -echo $ECHO_N "checking for LC_MESSAGES... $ECHO_C" >&6 -if test "${am_cv_val_LC_MESSAGES+set}" = set; then +echo "$as_me:$LINENO: result: $ac_cv_lib_dl_dlopen" >&5 +echo "${ECHO_T}$ac_cv_lib_dl_dlopen" >&6 +if test $ac_cv_lib_dl_dlopen = yes; then + lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" +else + echo "$as_me:$LINENO: checking for dlopen in -lsvld" >&5 +echo $ECHO_N "checking for dlopen in -lsvld... $ECHO_C" >&6 +if test "${ac_cv_lib_svld_dlopen+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - cat >conftest.$ac_ext <<_ACEOF + ac_check_lib_save_LIBS=$LIBS +LIBS="-lsvld $LIBS" +cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -#include <locale.h> + +/* Override any gcc2 internal prototype to avoid an error. */ +#ifdef __cplusplus +extern "C" +#endif +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char dlopen (); int main () { -return LC_MESSAGES +dlopen (); ; return 0; } @@ -7315,85 +9236,54 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - am_cv_val_LC_MESSAGES=yes + ac_cv_lib_svld_dlopen=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -am_cv_val_LC_MESSAGES=no +ac_cv_lib_svld_dlopen=no fi rm -f conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS fi -echo "$as_me:$LINENO: result: $am_cv_val_LC_MESSAGES" >&5 -echo "${ECHO_T}$am_cv_val_LC_MESSAGES" >&6 - if test $am_cv_val_LC_MESSAGES = yes; then - -cat >>confdefs.h <<\_ACEOF -#define HAVE_LC_MESSAGES 1 -_ACEOF - - fi - fi - echo "$as_me:$LINENO: checking whether NLS is requested" >&5 -echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6 - # Check whether --enable-nls or --disable-nls was given. -if test "${enable_nls+set}" = set; then - enableval="$enable_nls" - USE_NLS=$enableval +echo "$as_me:$LINENO: result: $ac_cv_lib_svld_dlopen" >&5 +echo "${ECHO_T}$ac_cv_lib_svld_dlopen" >&6 +if test $ac_cv_lib_svld_dlopen = yes; then + lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld" else - USE_NLS=yes -fi; - echo "$as_me:$LINENO: result: $USE_NLS" >&5 -echo "${ECHO_T}$USE_NLS" >&6 - - - USE_INCLUDED_LIBINTL=no - - if test "$USE_NLS" = "yes"; then - echo "$as_me:$LINENO: checking whether included gettext is requested" >&5 -echo $ECHO_N "checking whether included gettext is requested... $ECHO_C" >&6 - -# Check whether --with-included-gettext or --without-included-gettext was given. -if test "${with_included_gettext+set}" = set; then - withval="$with_included_gettext" - nls_cv_force_use_gnu_gettext=$withval -else - nls_cv_force_use_gnu_gettext=no -fi; - echo "$as_me:$LINENO: result: $nls_cv_force_use_gnu_gettext" >&5 -echo "${ECHO_T}$nls_cv_force_use_gnu_gettext" >&6 - - nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext" - if test "$nls_cv_force_use_gnu_gettext" != "yes"; then - nls_cv_header_intl= - nls_cv_header_libgt= - CATOBJEXT= - - if test "${ac_cv_header_libintl_h+set}" = set; then - echo "$as_me:$LINENO: checking for libintl.h" >&5 -echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6 -if test "${ac_cv_header_libintl_h+set}" = set; then + echo "$as_me:$LINENO: checking for dld_link in -ldld" >&5 +echo $ECHO_N "checking for dld_link in -ldld... $ECHO_C" >&6 +if test "${ac_cv_lib_dld_dld_link+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 -fi -echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5 -echo "${ECHO_T}$ac_cv_header_libintl_h" >&6 else - # Is the header compilable? -echo "$as_me:$LINENO: checking libintl.h usability" >&5 -echo $ECHO_N "checking libintl.h usability... $ECHO_C" >&6 + ac_check_lib_save_LIBS=$LIBS +LIBS="-ldld $LIBS" cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -$ac_includes_default -#include <libintl.h> + +/* Override any gcc2 internal prototype to avoid an error. */ +#ifdef __cplusplus +extern "C" +#endif +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char dld_link (); +int +main () +{ +dld_link (); + ; + return 0; +} _ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 +rm -f conftest.$ac_objext conftest$ac_exeext +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -7407,110 +9297,914 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - ac_header_compiler=yes + ac_cv_lib_dld_dld_link=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -ac_header_compiler=no +ac_cv_lib_dld_dld_link=no +fi +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +echo "$as_me:$LINENO: result: $ac_cv_lib_dld_dld_link" >&5 +echo "${ECHO_T}$ac_cv_lib_dld_dld_link" >&6 +if test $ac_cv_lib_dld_dld_link = yes; then + lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-dld" fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 -echo "${ECHO_T}$ac_header_compiler" >&6 -# Is the header present? -echo "$as_me:$LINENO: checking libintl.h presence" >&5 -echo $ECHO_N "checking libintl.h presence... $ECHO_C" >&6 -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <libintl.h> -_ACEOF -if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 - (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } >/dev/null; then - if test -s conftest.err; then - ac_cpp_err=$ac_c_preproc_warn_flag - ac_cpp_err=$ac_cpp_err$ac_c_werror_flag + +fi + + +fi + + +fi + + +fi + + +fi + + ;; + esac + + if test "x$lt_cv_dlopen" != xno; then + enable_dlopen=yes else - ac_cpp_err= + enable_dlopen=no fi + + case $lt_cv_dlopen in + dlopen) + save_CPPFLAGS="$CPPFLAGS" + test "x$ac_cv_header_dlfcn_h" = xyes && CPPFLAGS="$CPPFLAGS -DHAVE_DLFCN_H" + + save_LDFLAGS="$LDFLAGS" + wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $export_dynamic_flag_spec\" + + save_LIBS="$LIBS" + LIBS="$lt_cv_dlopen_libs $LIBS" + + echo "$as_me:$LINENO: checking whether a program can dlopen itself" >&5 +echo $ECHO_N "checking whether a program can dlopen itself... $ECHO_C" >&6 +if test "${lt_cv_dlopen_self+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 else - ac_cpp_err=yes + if test "$cross_compiling" = yes; then : + lt_cv_dlopen_self=cross +else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +#line 9369 "configure" +#include "confdefs.h" + +#if HAVE_DLFCN_H +#include <dlfcn.h> +#endif + +#include <stdio.h> + +#ifdef RTLD_GLOBAL +# define LT_DLGLOBAL RTLD_GLOBAL +#else +# ifdef DL_GLOBAL +# define LT_DLGLOBAL DL_GLOBAL +# else +# define LT_DLGLOBAL 0 +# endif +#endif + +/* We may have to define LT_DLLAZY_OR_NOW in the command line if we + find out it does not work in some platform. */ +#ifndef LT_DLLAZY_OR_NOW +# ifdef RTLD_LAZY +# define LT_DLLAZY_OR_NOW RTLD_LAZY +# else +# ifdef DL_LAZY +# define LT_DLLAZY_OR_NOW DL_LAZY +# else +# ifdef RTLD_NOW +# define LT_DLLAZY_OR_NOW RTLD_NOW +# else +# ifdef DL_NOW +# define LT_DLLAZY_OR_NOW DL_NOW +# else +# define LT_DLLAZY_OR_NOW 0 +# endif +# endif +# endif +# endif +#endif + +#ifdef __cplusplus +extern "C" void exit (int); +#endif + +void fnord() { int i=42;} +int main () +{ + void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW); + int status = $lt_dlunknown; + + if (self) + { + if (dlsym (self,"fnord")) status = $lt_dlno_uscore; + else if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore; + /* dlclose (self); */ + } + else + puts (dlerror ()); + + exit (status); +} +_LT_EOF + if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 + (eval $ac_link) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && test -s conftest${ac_exeext} 2>/dev/null; then + (./conftest; exit; ) >&5 2>/dev/null + lt_status=$? + case x$lt_status in + x$lt_dlno_uscore) lt_cv_dlopen_self=yes ;; + x$lt_dlneed_uscore) lt_cv_dlopen_self=yes ;; + x$lt_dlunknown|x*) lt_cv_dlopen_self=no ;; + esac + else : + # compilation failed + lt_cv_dlopen_self=no + fi fi -if test -z "$ac_cpp_err"; then - ac_header_preproc=yes +rm -fr conftest* + + +fi +echo "$as_me:$LINENO: result: $lt_cv_dlopen_self" >&5 +echo "${ECHO_T}$lt_cv_dlopen_self" >&6 + + if test "x$lt_cv_dlopen_self" = xyes; then + wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\" + echo "$as_me:$LINENO: checking whether a statically linked program can dlopen itself" >&5 +echo $ECHO_N "checking whether a statically linked program can dlopen itself... $ECHO_C" >&6 +if test "${lt_cv_dlopen_self_static+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 + if test "$cross_compiling" = yes; then : + lt_cv_dlopen_self_static=cross +else + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF +#line 9469 "configure" +#include "confdefs.h" - ac_header_preproc=no +#if HAVE_DLFCN_H +#include <dlfcn.h> +#endif + +#include <stdio.h> + +#ifdef RTLD_GLOBAL +# define LT_DLGLOBAL RTLD_GLOBAL +#else +# ifdef DL_GLOBAL +# define LT_DLGLOBAL DL_GLOBAL +# else +# define LT_DLGLOBAL 0 +# endif +#endif + +/* We may have to define LT_DLLAZY_OR_NOW in the command line if we + find out it does not work in some platform. */ +#ifndef LT_DLLAZY_OR_NOW +# ifdef RTLD_LAZY +# define LT_DLLAZY_OR_NOW RTLD_LAZY +# else +# ifdef DL_LAZY +# define LT_DLLAZY_OR_NOW DL_LAZY +# else +# ifdef RTLD_NOW +# define LT_DLLAZY_OR_NOW RTLD_NOW +# else +# ifdef DL_NOW +# define LT_DLLAZY_OR_NOW DL_NOW +# else +# define LT_DLLAZY_OR_NOW 0 +# endif +# endif +# endif +# endif +#endif + +#ifdef __cplusplus +extern "C" void exit (int); +#endif + +void fnord() { int i=42;} +int main () +{ + void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW); + int status = $lt_dlunknown; + + if (self) + { + if (dlsym (self,"fnord")) status = $lt_dlno_uscore; + else if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore; + /* dlclose (self); */ + } + else + puts (dlerror ()); + + exit (status); +} +_LT_EOF + if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 + (eval $ac_link) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && test -s conftest${ac_exeext} 2>/dev/null; then + (./conftest; exit; ) >&5 2>/dev/null + lt_status=$? + case x$lt_status in + x$lt_dlno_uscore) lt_cv_dlopen_self_static=yes ;; + x$lt_dlneed_uscore) lt_cv_dlopen_self_static=yes ;; + x$lt_dlunknown|x*) lt_cv_dlopen_self_static=no ;; + esac + else : + # compilation failed + lt_cv_dlopen_self_static=no + fi fi -rm -f conftest.err conftest.$ac_ext -echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 -echo "${ECHO_T}$ac_header_preproc" >&6 +rm -fr conftest* -# So? What about this header? -case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in - yes:no: ) - { echo "$as_me:$LINENO: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&5 -echo "$as_me: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&2;} - { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the compiler's result" >&5 -echo "$as_me: WARNING: libintl.h: proceeding with the compiler's result" >&2;} - ac_header_preproc=yes + +fi +echo "$as_me:$LINENO: result: $lt_cv_dlopen_self_static" >&5 +echo "${ECHO_T}$lt_cv_dlopen_self_static" >&6 + fi + + CPPFLAGS="$save_CPPFLAGS" + LDFLAGS="$save_LDFLAGS" + LIBS="$save_LIBS" ;; - no:yes:* ) - { echo "$as_me:$LINENO: WARNING: libintl.h: present but cannot be compiled" >&5 -echo "$as_me: WARNING: libintl.h: present but cannot be compiled" >&2;} - { echo "$as_me:$LINENO: WARNING: libintl.h: check for missing prerequisite headers?" >&5 -echo "$as_me: WARNING: libintl.h: check for missing prerequisite headers?" >&2;} - { echo "$as_me:$LINENO: WARNING: libintl.h: see the Autoconf documentation" >&5 -echo "$as_me: WARNING: libintl.h: see the Autoconf documentation" >&2;} - { echo "$as_me:$LINENO: WARNING: libintl.h: section \"Present But Cannot Be Compiled\"" >&5 -echo "$as_me: WARNING: libintl.h: section \"Present But Cannot Be Compiled\"" >&2;} - { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the preprocessor's result" >&5 -echo "$as_me: WARNING: libintl.h: proceeding with the preprocessor's result" >&2;} - { echo "$as_me:$LINENO: WARNING: libintl.h: in the future, the compiler will take precedence" >&5 -echo "$as_me: WARNING: libintl.h: in the future, the compiler will take precedence" >&2;} - ( - cat <<\_ASBOX -## ------------------------------------------ ## -## Report this to the AC_PACKAGE_NAME lists. ## -## ------------------------------------------ ## -_ASBOX - ) | - sed "s/^/$as_me: WARNING: /" >&2 + esac + + case $lt_cv_dlopen_self in + yes|no) enable_dlopen_self=$lt_cv_dlopen_self ;; + *) enable_dlopen_self=unknown ;; + esac + + case $lt_cv_dlopen_self_static in + yes|no) enable_dlopen_self_static=$lt_cv_dlopen_self_static ;; + *) enable_dlopen_self_static=unknown ;; + esac +fi + + + + + + + + + + + + + + + + + +striplib= +old_striplib= +echo "$as_me:$LINENO: checking whether stripping libraries is possible" >&5 +echo $ECHO_N "checking whether stripping libraries is possible... $ECHO_C" >&6 +if test -n "$STRIP" && $STRIP -V 2>&1 | $GREP "GNU strip" >/dev/null; then + test -z "$old_striplib" && old_striplib="$STRIP --strip-debug" + test -z "$striplib" && striplib="$STRIP --strip-unneeded" + echo "$as_me:$LINENO: result: yes" >&5 +echo "${ECHO_T}yes" >&6 +else +# FIXME - insert some real tests, host_os isn't really good enough + case $host_os in + darwin*) + if test -n "$STRIP" ; then + striplib="$STRIP -x" + old_striplib="$STRIP -S" + echo "$as_me:$LINENO: result: yes" >&5 +echo "${ECHO_T}yes" >&6 + else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 + fi ;; + *) + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 + ;; + esac +fi + + + + + + + + + + + + + # Report which library types will actually be built + echo "$as_me:$LINENO: checking if libtool supports shared libraries" >&5 +echo $ECHO_N "checking if libtool supports shared libraries... $ECHO_C" >&6 + echo "$as_me:$LINENO: result: $can_build_shared" >&5 +echo "${ECHO_T}$can_build_shared" >&6 + + echo "$as_me:$LINENO: checking whether to build shared libraries" >&5 +echo $ECHO_N "checking whether to build shared libraries... $ECHO_C" >&6 + test "$can_build_shared" = "no" && enable_shared=no + + # On AIX, shared libraries and static libraries use the same namespace, and + # are all built from PIC. + case $host_os in + aix3*) + test "$enable_shared" = yes && enable_static=no + if test -n "$RANLIB"; then + archive_cmds="$archive_cmds~\$RANLIB \$lib" + postinstall_cmds='$RANLIB $lib' + fi + ;; + + aix4* | aix5*) + if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then + test "$enable_shared" = yes && enable_static=no + fi + ;; + esac + echo "$as_me:$LINENO: result: $enable_shared" >&5 +echo "${ECHO_T}$enable_shared" >&6 + + echo "$as_me:$LINENO: checking whether to build static libraries" >&5 +echo $ECHO_N "checking whether to build static libraries... $ECHO_C" >&6 + # Make sure either enable_shared or enable_static is yes. + test "$enable_shared" = yes || enable_static=yes + echo "$as_me:$LINENO: result: $enable_static" >&5 +echo "${ECHO_T}$enable_static" >&6 + + + + +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +CC="$lt_save_CC" + + + + + + + + + + + + + + ac_config_commands="$ac_config_commands libtool" + + + + +# Only expand once: + + + +# Check whether --enable-targets or --disable-targets was given. +if test "${enable_targets+set}" = set; then + enableval="$enable_targets" + case "${enableval}" in + yes | "") { { echo "$as_me:$LINENO: error: enable-targets option must specify target names or 'all'" >&5 +echo "$as_me: error: enable-targets option must specify target names or 'all'" >&2;} + { (exit 1); exit 1; }; } + ;; + no) enable_targets= ;; + *) enable_targets=$enableval ;; +esac +fi; # Check whether --enable-commonbfdlib or --disable-commonbfdlib was given. +if test "${enable_commonbfdlib+set}" = set; then + enableval="$enable_commonbfdlib" + case "${enableval}" in + yes) commonbfdlib=true ;; + no) commonbfdlib=false ;; + *) { { echo "$as_me:$LINENO: error: bad value ${enableval} for opcodes commonbfdlib option" >&5 +echo "$as_me: error: bad value ${enableval} for opcodes commonbfdlib option" >&2;} + { (exit 1); exit 1; }; } ;; +esac +fi; + +GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" + +# Check whether --enable-werror or --disable-werror was given. +if test "${enable_werror+set}" = set; then + enableval="$enable_werror" + case "${enableval}" in + yes | y) ERROR_ON_WARNING="yes" ;; + no | n) ERROR_ON_WARNING="no" ;; + *) { { echo "$as_me:$LINENO: error: bad value ${enableval} for --enable-werror" >&5 +echo "$as_me: error: bad value ${enableval} for --enable-werror" >&2;} + { (exit 1); exit 1; }; } ;; + esac +fi; + +# Enable -Werror by default when using gcc +if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then + ERROR_ON_WARNING=yes +fi + +NO_WERROR= +if test "${ERROR_ON_WARNING}" = yes ; then + GCC_WARN_CFLAGS="$GCC_WARN_CFLAGS -Werror" + NO_WERROR="-Wno-error" +fi + +if test "${GCC}" = yes ; then + WARN_CFLAGS="${GCC_WARN_CFLAGS}" +fi + +# Check whether --enable-build-warnings or --disable-build-warnings was given. +if test "${enable_build_warnings+set}" = set; then + enableval="$enable_build_warnings" + case "${enableval}" in + yes) WARN_CFLAGS="${GCC_WARN_CFLAGS}";; + no) if test "${GCC}" = yes ; then + WARN_CFLAGS="-w" + fi;; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + WARN_CFLAGS="${GCC_WARN_CFLAGS} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + WARN_CFLAGS="${t} ${GCC_WARN_CFLAGS}";; + *) WARN_CFLAGS=`echo "${enableval}" | sed -e "s/,/ /g"`;; esac -echo "$as_me:$LINENO: checking for libintl.h" >&5 -echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6 -if test "${ac_cv_header_libintl_h+set}" = set; then +fi; + +if test x"$silent" != x"yes" && test x"$WARN_CFLAGS" != x""; then + echo "Setting warning flags = $WARN_CFLAGS" 6>&1 +fi + + + + + + ac_config_headers="$ac_config_headers config.h:config.in" + + +if test -z "$target" ; then + { { echo "$as_me:$LINENO: error: Unrecognized target system type; please check config.sub." >&5 +echo "$as_me: error: Unrecognized target system type; please check config.sub." >&2;} + { (exit 1); exit 1; }; } +fi + +echo "$as_me:$LINENO: checking whether to enable maintainer-specific portions of Makefiles" >&5 +echo $ECHO_N "checking whether to enable maintainer-specific portions of Makefiles... $ECHO_C" >&6 + # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then + enableval="$enable_maintainer_mode" + USE_MAINTAINER_MODE=$enableval +else + USE_MAINTAINER_MODE=no +fi; + echo "$as_me:$LINENO: result: $USE_MAINTAINER_MODE" >&5 +echo "${ECHO_T}$USE_MAINTAINER_MODE" >&6 + + +if test $USE_MAINTAINER_MODE = yes; then + MAINTAINER_MODE_TRUE= + MAINTAINER_MODE_FALSE='#' +else + MAINTAINER_MODE_TRUE='#' + MAINTAINER_MODE_FALSE= +fi + + MAINT=$MAINTAINER_MODE_TRUE + + + case ${build_alias} in + "") build_noncanonical=${build} ;; + *) build_noncanonical=${build_alias} ;; +esac + + case ${host_alias} in + "") host_noncanonical=${build_noncanonical} ;; + *) host_noncanonical=${host_alias} ;; +esac + + case ${target_alias} in + "") target_noncanonical=${host_noncanonical} ;; + *) target_noncanonical=${target_alias} ;; +esac + +echo "$as_me:$LINENO: checking whether to install libbfd" >&5 +echo $ECHO_N "checking whether to install libbfd... $ECHO_C" >&6 + # Check whether --enable-install-libbfd or --disable-install-libbfd was given. +if test "${enable_install_libbfd+set}" = set; then + enableval="$enable_install_libbfd" + install_libbfd_p=$enableval +else + if test "${host}" = "${target}" || test "$enable_shared" = "yes"; then + install_libbfd_p=yes + else + install_libbfd_p=no + fi +fi; + echo "$as_me:$LINENO: result: $install_libbfd_p" >&5 +echo "${ECHO_T}$install_libbfd_p" >&6 + + +if test $install_libbfd_p = yes; then + INSTALL_LIBBFD_TRUE= + INSTALL_LIBBFD_FALSE='#' +else + INSTALL_LIBBFD_TRUE='#' + INSTALL_LIBBFD_FALSE= +fi + + # Need _noncanonical variables for this. + + + + + # libbfd.a is a host library containing target dependent code + bfdlibdir='$(libdir)' + bfdincludedir='$(includedir)' + if test "${host}" != "${target}"; then + bfdlibdir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/lib' + bfdincludedir='$(exec_prefix)/$(host_noncanonical)/$(target_noncanonical)/include' + fi + + + + + + +# host-specific stuff: + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_CC+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + echo "$as_me:$LINENO: result: $CC" >&5 +echo "${ECHO_T}$CC" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +fi + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="gcc" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 +echo "${ECHO_T}$ac_ct_CC" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +fi + + CC=$ac_ct_CC +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_CC+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + echo "$as_me:$LINENO: result: $CC" >&5 +echo "${ECHO_T}$CC" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +fi + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="cc" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 +echo "${ECHO_T}$ac_ct_CC" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +fi + + CC=$ac_ct_CC +else + CC="$ac_cv_prog_CC" +fi + +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_CC+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + echo "$as_me:$LINENO: result: $CC" >&5 +echo "${ECHO_T}$CC" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +fi + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_CC+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - ac_cv_header_libintl_h=$ac_header_preproc + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + echo "$as_me:$LINENO: result: $CC" >&5 +echo "${ECHO_T}$CC" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 fi -echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5 -echo "${ECHO_T}$ac_cv_header_libintl_h" >&6 + test -n "$CC" && break + done fi -if test $ac_cv_header_libintl_h = yes; then - echo "$as_me:$LINENO: checking for gettext in libc" >&5 -echo $ECHO_N "checking for gettext in libc... $ECHO_C" >&6 -if test "${gt_cv_func_gettext_libc+set}" = set; then +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="$ac_prog" + echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 +echo "${ECHO_T}$ac_ct_CC" >&6 +else + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +fi + + test -n "$ac_ct_CC" && break +done + + CC=$ac_ct_CC +fi + +fi + + +test -z "$CC" && { { echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH +See \`config.log' for more details." >&5 +echo "$as_me: error: no acceptable C compiler found in \$PATH +See \`config.log' for more details." >&2;} + { (exit 1); exit 1; }; } + +# Provide some information about the compiler. +echo "$as_me:$LINENO:" \ + "checking for C compiler version" >&5 +ac_compiler=`set X $ac_compile; echo $2` +{ (eval echo "$as_me:$LINENO: \"$ac_compiler --version </dev/null >&5\"") >&5 + (eval $ac_compiler --version </dev/null >&5) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } +{ (eval echo "$as_me:$LINENO: \"$ac_compiler -v </dev/null >&5\"") >&5 + (eval $ac_compiler -v </dev/null >&5) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } +{ (eval echo "$as_me:$LINENO: \"$ac_compiler -V </dev/null >&5\"") >&5 + (eval $ac_compiler -V </dev/null >&5) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } + +echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5 +echo $ECHO_N "checking whether we are using the GNU C compiler... $ECHO_C" >&6 +if test "${ac_cv_c_compiler_gnu+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF @@ -7519,18 +10213,21 @@ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -#include <libintl.h> + int main () { -return (int) gettext ("") +#ifndef __GNUC__ + choke me +#endif + ; return 0; } _ACEOF -rm -f conftest.$ac_objext conftest$ac_exeext -if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>conftest.er1 +rm -f conftest.$ac_objext +if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -7544,58 +10241,52 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - gt_cv_func_gettext_libc=yes + ac_compiler_gnu=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -gt_cv_func_gettext_libc=no -fi -rm -f conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext +ac_compiler_gnu=no fi -echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libc" >&5 -echo "${ECHO_T}$gt_cv_func_gettext_libc" >&6 +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu - if test "$gt_cv_func_gettext_libc" != "yes"; then - echo "$as_me:$LINENO: checking for bindtextdomain in -lintl" >&5 -echo $ECHO_N "checking for bindtextdomain in -lintl... $ECHO_C" >&6 -if test "${ac_cv_lib_intl_bindtextdomain+set}" = set; then +fi +echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5 +echo "${ECHO_T}$ac_cv_c_compiler_gnu" >&6 +GCC=`test $ac_compiler_gnu = yes && echo yes` +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +CFLAGS="-g" +echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5 +echo $ECHO_N "checking whether $CC accepts -g... $ECHO_C" >&6 +if test "${ac_cv_prog_cc_g+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - ac_check_lib_save_LIBS=$LIBS -LIBS="-lintl $LIBS" -cat >conftest.$ac_ext <<_ACEOF + cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -/* Override any gcc2 internal prototype to avoid an error. */ -#ifdef __cplusplus -extern "C" -#endif -/* We use char because int might match the return type of a gcc2 - builtin and then its argument prototype would still apply. */ -char bindtextdomain (); int main () { -bindtextdomain (); + ; return 0; } _ACEOF -rm -f conftest.$ac_objext conftest$ac_exeext -if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>conftest.er1 +rm -f conftest.$ac_objext +if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -7609,49 +10300,110 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - ac_cv_lib_intl_bindtextdomain=yes + ac_cv_prog_cc_g=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -ac_cv_lib_intl_bindtextdomain=no +ac_cv_prog_cc_g=no fi -rm -f conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext -LIBS=$ac_check_lib_save_LIBS +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi -echo "$as_me:$LINENO: result: $ac_cv_lib_intl_bindtextdomain" >&5 -echo "${ECHO_T}$ac_cv_lib_intl_bindtextdomain" >&6 -if test $ac_cv_lib_intl_bindtextdomain = yes; then - echo "$as_me:$LINENO: checking for gettext in libintl" >&5 -echo $ECHO_N "checking for gettext in libintl... $ECHO_C" >&6 -if test "${gt_cv_func_gettext_libintl+set}" = set; then +echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5 +echo "${ECHO_T}$ac_cv_prog_cc_g" >&6 +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +echo "$as_me:$LINENO: checking for $CC option to accept ANSI C" >&5 +echo $ECHO_N "checking for $CC option to accept ANSI C... $ECHO_C" >&6 +if test "${ac_cv_prog_cc_stdc+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else - cat >conftest.$ac_ext <<_ACEOF + ac_cv_prog_cc_stdc=no +ac_save_CC=$CC +cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ +#include <stdarg.h> +#include <stdio.h> +#include <sys/types.h> +#include <sys/stat.h> +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std1 is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std1. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; int main () { -return (int) gettext ("") +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; ; return 0; } _ACEOF -rm -f conftest.$ac_objext conftest$ac_exeext -if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>conftest.er1 +# Don't try gcc -ansi; that turns off useful extensions and +# breaks some systems' header files. +# AIX -qlanglvl=ansi +# Ultrix and OSF/1 -std1 +# HP-UX 10.20 and later -Ae +# HP-UX older versions -Aa -D_HPUX_SOURCE +# SVR4 -Xc -D__EXTENSIONS__ +for ac_arg in "" -qlanglvl=ansi -std1 -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + rm -f conftest.$ac_objext +if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -7665,134 +10417,94 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - gt_cv_func_gettext_libintl=yes + ac_cv_prog_cc_stdc=$ac_arg +break else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -gt_cv_func_gettext_libintl=no fi -rm -f conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext -fi -echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libintl" >&5 -echo "${ECHO_T}$gt_cv_func_gettext_libintl" >&6 -fi - - fi - - if test "$gt_cv_func_gettext_libc" = "yes" \ - || test "$gt_cv_func_gettext_libintl" = "yes"; then +rm -f conftest.err conftest.$ac_objext +done +rm -f conftest.$ac_ext conftest.$ac_objext +CC=$ac_save_CC -cat >>confdefs.h <<\_ACEOF -#define HAVE_GETTEXT 1 -_ACEOF +fi - # Extract the first word of "msgfmt", so it can be a program name with args. -set dummy msgfmt; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_path_MSGFMT+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - case "$MSGFMT" in - /*) - ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. - ;; +case "x$ac_cv_prog_cc_stdc" in + x|xno) + echo "$as_me:$LINENO: result: none needed" >&5 +echo "${ECHO_T}none needed" >&6 ;; *) - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" - for ac_dir in $PATH; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then - ac_cv_path_MSGFMT="$ac_dir/$ac_word" - break - fi - fi - done - IFS="$ac_save_ifs" - test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no" - ;; + echo "$as_me:$LINENO: result: $ac_cv_prog_cc_stdc" >&5 +echo "${ECHO_T}$ac_cv_prog_cc_stdc" >&6 + CC="$CC $ac_cv_prog_cc_stdc" ;; esac -fi -MSGFMT="$ac_cv_path_MSGFMT" -if test -n "$MSGFMT"; then - echo "$as_me:$LINENO: result: $MSGFMT" >&5 -echo "${ECHO_T}$MSGFMT" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi - if test "$MSGFMT" != "no"; then -for ac_func in dcgettext +# Some people use a C++ compiler to compile C. Since we use `exit', +# in C++ we need to declare it. In case someone uses the same compiler +# for both compiling C and C++ we need to have the C++ compiler decide +# the declaration of exit, since it's the most demanding environment. +cat >conftest.$ac_ext <<_ACEOF +#ifndef __cplusplus + choke me +#endif +_ACEOF +rm -f conftest.$ac_objext +if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + for ac_declaration in \ + '' \ + 'extern "C" void std::exit (int) throw (); using std::exit;' \ + 'extern "C" void std::exit (int); using std::exit;' \ + 'extern "C" void exit (int) throw ();' \ + 'extern "C" void exit (int);' \ + 'void exit (int);' do -as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` -echo "$as_me:$LINENO: checking for $ac_func" >&5 -echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6 -if eval "test \"\${$as_ac_var+set}\" = set"; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func. - For example, HP-UX 11i <limits.h> declares gettimeofday. */ -#define $ac_func innocuous_$ac_func - -/* System header to define __stub macros and hopefully few prototypes, - which can conflict with char $ac_func (); below. - Prefer <limits.h> to <assert.h> if __STDC__ is defined, since - <limits.h> exists even on freestanding compilers. */ - -#ifdef __STDC__ -# include <limits.h> -#else -# include <assert.h> -#endif - -#undef $ac_func - -/* Override any gcc2 internal prototype to avoid an error. */ -#ifdef __cplusplus -extern "C" -{ -#endif -/* We use char because int might match the return type of a gcc2 - builtin and then its argument prototype would still apply. */ -char $ac_func (); -/* The GNU C library defines this for functions which it implements - to always fail with ENOSYS. Some functions are actually named - something starting with __ and the normal name is an alias. */ -#if defined (__stub_$ac_func) || defined (__stub___$ac_func) -choke me -#else -char (*f) () = $ac_func; -#endif -#ifdef __cplusplus -} -#endif - +$ac_declaration +#include <stdlib.h> int main () { -return f != $ac_func; +exit (42); ; return 0; } _ACEOF -rm -f conftest.$ac_objext conftest$ac_exeext -if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>conftest.er1 +rm -f conftest.$ac_objext +if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -7806,127 +10518,38 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - eval "$as_ac_var=yes" + : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -eval "$as_ac_var=no" -fi -rm -f conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext -fi -echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 -echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 -if test `eval echo '${'$as_ac_var'}'` = yes; then - cat >>confdefs.h <<_ACEOF -#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1 -_ACEOF - -fi -done - - # Extract the first word of "gmsgfmt", so it can be a program name with args. -set dummy gmsgfmt; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_path_GMSGFMT+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - case $GMSGFMT in - [\\/]* | ?:[\\/]*) - ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. - ;; - *) - as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_path_GMSGFMT="$as_dir/$ac_word$ac_exec_ext" - echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done -done - - test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" - ;; -esac -fi -GMSGFMT=$ac_cv_path_GMSGFMT - -if test -n "$GMSGFMT"; then - echo "$as_me:$LINENO: result: $GMSGFMT" >&5 -echo "${ECHO_T}$GMSGFMT" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 -fi - - # Extract the first word of "xgettext", so it can be a program name with args. -set dummy xgettext; ac_word=$2 -echo "$as_me:$LINENO: checking for $ac_word" >&5 -echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 -if test "${ac_cv_path_XGETTEXT+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - case "$XGETTEXT" in - /*) - ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. - ;; - *) - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" - for ac_dir in $PATH; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then - ac_cv_path_XGETTEXT="$ac_dir/$ac_word" - break - fi - fi - done - IFS="$ac_save_ifs" - test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" - ;; -esac -fi -XGETTEXT="$ac_cv_path_XGETTEXT" -if test -n "$XGETTEXT"; then - echo "$as_me:$LINENO: result: $XGETTEXT" >&5 -echo "${ECHO_T}$XGETTEXT" >&6 -else - echo "$as_me:$LINENO: result: no" >&5 -echo "${ECHO_T}no" >&6 +continue fi - - cat >conftest.$ac_ext <<_ACEOF +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext + cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ - +$ac_declaration int main () { -extern int _nl_msg_cat_cntr; - return _nl_msg_cat_cntr +exit (42); ; return 0; } _ACEOF -rm -f conftest.$ac_objext conftest$ac_exeext -if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>conftest.er1 +rm -f conftest.$ac_objext +if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 @@ -7940,42 +10563,173 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - CATOBJEXT=.gmo - DATADIRNAME=share + break else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -CATOBJEXT=.mo - DATADIRNAME=lib fi -rm -f conftest.err conftest.$ac_objext \ - conftest$ac_exeext conftest.$ac_ext - INSTOBJEXT=.mo - fi - fi +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext +done +rm -f conftest* +if test -n "$ac_declaration"; then + echo '#ifdef __cplusplus' >>confdefs.h + echo $ac_declaration >>confdefs.h + echo '#endif' >>confdefs.h +fi + +else + echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 fi +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +ALL_LINGUAS="fr sv tr es da de id pt_BR ro nl fi vi ga zh_CN" +# If we haven't got the data from the intl directory, +# assume NLS is disabled. +USE_NLS=no +LIBINTL= +LIBINTL_DEP= +INCINTL= +XGETTEXT= +GMSGFMT= +POSUB= + +if test -f ../intl/config.intl; then + . ../intl/config.intl +fi +echo "$as_me:$LINENO: checking whether NLS is requested" >&5 +echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6 +if test x"$USE_NLS" != xyes; then + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 +else + echo "$as_me:$LINENO: result: yes" >&5 +echo "${ECHO_T}yes" >&6 + +cat >>confdefs.h <<\_ACEOF +#define ENABLE_NLS 1 +_ACEOF + + + echo "$as_me:$LINENO: checking for catalogs to be installed" >&5 +echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6 + # Look for .po and .gmo files in the source directory. + CATALOGS= + XLINGUAS= + for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do + # If there aren't any .gmo files the shell will give us the + # literal string "../path/to/srcdir/po/*.gmo" which has to be + # weeded out. + case "$cat" in *\**) + continue;; + esac + # The quadruple backslash is collapsed to a double backslash + # by the backticks, then collapsed again by the double quotes, + # leaving us with one backslash in the sed expression (right + # before the dot that mustn't act as a wildcard). + cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"` + lang=`echo $cat | sed -e "s!\\\\.gmo!!"` + # The user is allowed to set LINGUAS to a list of languages to + # install catalogs for. If it's empty that means "all of them." + if test "x$LINGUAS" = x; then + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + else + case "$LINGUAS" in *$lang*) + CATALOGS="$CATALOGS $cat" + XLINGUAS="$XLINGUAS $lang" + ;; + esac + fi + done + LINGUAS="$XLINGUAS" + echo "$as_me:$LINENO: result: $LINGUAS" >&5 +echo "${ECHO_T}$LINGUAS" >&6 + + + DATADIRNAME=share + + INSTOBJEXT=.mo + + GENCAT=gencat + + CATOBJEXT=.gmo + +fi + + MKINSTALLDIRS= + if test -n "$ac_aux_dir"; then + case "$ac_aux_dir" in + /*) MKINSTALLDIRS="$ac_aux_dir/mkinstalldirs" ;; + *) MKINSTALLDIRS="\$(top_builddir)/$ac_aux_dir/mkinstalldirs" ;; + esac + fi + if test -z "$MKINSTALLDIRS"; then + MKINSTALLDIRS="\$(top_srcdir)/mkinstalldirs" + fi + + + + echo "$as_me:$LINENO: checking whether NLS is requested" >&5 +echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6 + # Check whether --enable-nls or --disable-nls was given. +if test "${enable_nls+set}" = set; then + enableval="$enable_nls" + USE_NLS=$enableval +else + USE_NLS=yes +fi; + echo "$as_me:$LINENO: result: $USE_NLS" >&5 +echo "${ECHO_T}$USE_NLS" >&6 - if test x"$CATOBJEXT" = x && test -d $srcdir/../intl; then - # Neither gettext nor catgets in included in the C library. - # Fall back on GNU gettext library (assuming it is present). - nls_cv_use_gnu_gettext=yes - fi - fi - if test "$nls_cv_use_gnu_gettext" = "yes"; then - INTLOBJS="\$(GETTOBJS)" - # Extract the first word of "msgfmt", so it can be a program name with args. + + + +# Prepare PATH_SEPARATOR. +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + echo "#! /bin/sh" >conf$$.sh + echo "exit 0" >>conf$$.sh + chmod +x conf$$.sh + if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then + PATH_SEPARATOR=';' + else + PATH_SEPARATOR=: + fi + rm -f conf$$.sh +fi + +# Find out how to test for executable files. Don't use a zero-byte file, +# as systems may use methods other than mode bits to determine executability. +cat >conf$$.file <<_ASEOF +#! /bin/sh +exit 0 +_ASEOF +chmod +x conf$$.file +if test -x conf$$.file >/dev/null 2>&1; then + ac_executable_p="test -x" +else + ac_executable_p="test -f" +fi +rm -f conf$$.file + +# Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 @@ -7983,27 +10737,31 @@ if test "${ac_cv_path_MSGFMT+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else case "$MSGFMT" in - /*) - ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. - ;; + [\\/]* | ?:[\\/]*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; *) - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" - for ac_dir in $PATH; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then - ac_cv_path_MSGFMT="$ac_dir/$ac_word" - break - fi - fi - done - IFS="$ac_save_ifs" - test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt" - ;; + ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH; do + IFS="$ac_save_IFS" + test -z "$ac_dir" && ac_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then + if $ac_dir/$ac_word --statistics /dev/null >/dev/null 2>&1 && + (if $ac_dir/$ac_word --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + ac_cv_path_MSGFMT="$ac_dir/$ac_word$ac_exec_ext" + break 2 + fi + fi + done + done + IFS="$ac_save_IFS" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT=":" + ;; esac fi MSGFMT="$ac_cv_path_MSGFMT" -if test -n "$MSGFMT"; then +if test "$MSGFMT" != ":"; then echo "$as_me:$LINENO: result: $MSGFMT" >&5 echo "${ECHO_T}$MSGFMT" >&6 else @@ -8011,7 +10769,7 @@ else echo "${ECHO_T}no" >&6 fi - # Extract the first word of "gmsgfmt", so it can be a program name with args. + # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 @@ -8051,7 +10809,37 @@ else echo "${ECHO_T}no" >&6 fi - # Extract the first word of "xgettext", so it can be a program name with args. + + +# Prepare PATH_SEPARATOR. +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + echo "#! /bin/sh" >conf$$.sh + echo "exit 0" >>conf$$.sh + chmod +x conf$$.sh + if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then + PATH_SEPARATOR=';' + else + PATH_SEPARATOR=: + fi + rm -f conf$$.sh +fi + +# Find out how to test for executable files. Don't use a zero-byte file, +# as systems may use methods other than mode bits to determine executability. +cat >conf$$.file <<_ASEOF +#! /bin/sh +exit 0 +_ASEOF +chmod +x conf$$.file +if test -x conf$$.file >/dev/null 2>&1; then + ac_executable_p="test -x" +else + ac_executable_p="test -f" +fi +rm -f conf$$.file + +# Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 @@ -8059,27 +10847,31 @@ if test "${ac_cv_path_XGETTEXT+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else case "$XGETTEXT" in - /*) - ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. - ;; + [\\/]* | ?:[\\/]*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; *) - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" - for ac_dir in $PATH; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then - ac_cv_path_XGETTEXT="$ac_dir/$ac_word" - break - fi - fi - done - IFS="$ac_save_ifs" + ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH; do + IFS="$ac_save_IFS" + test -z "$ac_dir" && ac_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then + if $ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 && + (if $ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word$ac_exec_ext" + break 2 + fi + fi + done + done + IFS="$ac_save_IFS" test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" - ;; + ;; esac fi XGETTEXT="$ac_cv_path_XGETTEXT" -if test -n "$XGETTEXT"; then +if test "$XGETTEXT" != ":"; then echo "$as_me:$LINENO: result: $XGETTEXT" >&5 echo "${ECHO_T}$XGETTEXT" >&6 else @@ -8087,282 +10879,103 @@ else echo "${ECHO_T}no" >&6 fi - - USE_INCLUDED_LIBINTL=yes - CATOBJEXT=.gmo - INSTOBJEXT=.mo - DATADIRNAME=share - INTLDEPS='$(top_builddir)/../intl/libintl.a' - INTLLIBS=$INTLDEPS - LIBS=`echo $LIBS | sed -e 's/-lintl//'` - nls_cv_header_intl=libintl.h - nls_cv_header_libgt=libgettext.h - fi - - if test "$XGETTEXT" != ":"; then - if $XGETTEXT --omit-header /dev/null 2> /dev/null; then - : ; - else - echo "$as_me:$LINENO: result: found xgettext programs is not GNU xgettext; ignore it" >&5 -echo "${ECHO_T}found xgettext programs is not GNU xgettext; ignore it" >&6 - XGETTEXT=":" - fi - fi - - # We need to process the po/ directory. - POSUB=po - else - DATADIRNAME=share - nls_cv_header_intl=libintl.h - nls_cv_header_libgt=libgettext.h - fi - - # If this is used in GNU gettext we have to set USE_NLS to `yes' - # because some of the sources are only built for this goal. - if test "$PACKAGE" = gettext; then - USE_NLS=yes - USE_INCLUDED_LIBINTL=yes - fi - - for lang in $ALL_LINGUAS; do - GMOFILES="$GMOFILES $lang.gmo" - POFILES="$POFILES $lang.po" - done - - - + rm -f messages.po - - - - - - - - if test "x$CATOBJEXT" != "x"; then - -cat >>confdefs.h <<\_ACEOF -#define ENABLE_NLS 1 -_ACEOF - - fi - - - if test "x$CATOBJEXT" != "x"; then - if test "x$ALL_LINGUAS" = "x"; then - LINGUAS= - else - echo "$as_me:$LINENO: checking for catalogs to be installed" >&5 -echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6 - NEW_LINGUAS= - for lang in ${LINGUAS=$ALL_LINGUAS}; do - case "$ALL_LINGUAS" in - *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;; - esac - done - LINGUAS=$NEW_LINGUAS - echo "$as_me:$LINENO: result: $LINGUAS" >&5 -echo "${ECHO_T}$LINGUAS" >&6 - fi - - if test -n "$LINGUAS"; then - for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done - fi - fi - - if test $ac_cv_header_locale_h = yes; then - INCLUDE_LOCALE_H="#include <locale.h>" - else - INCLUDE_LOCALE_H="\ -/* The system does not provide the header <locale.h>. Take care yourself. */" - fi - - - if test -f $srcdir/po2tbl.sed.in; then - if test "$CATOBJEXT" = ".cat"; then - if test "${ac_cv_header_linux_version_h+set}" = set; then - echo "$as_me:$LINENO: checking for linux/version.h" >&5 -echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6 -if test "${ac_cv_header_linux_version_h+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -fi -echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5 -echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6 -else - # Is the header compilable? -echo "$as_me:$LINENO: checking linux/version.h usability" >&5 -echo $ECHO_N "checking linux/version.h usability... $ECHO_C" >&6 -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -$ac_includes_default -#include <linux/version.h> -_ACEOF -rm -f conftest.$ac_objext -if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } && - { ac_try='test -z "$ac_c_werror_flag" - || test ! -s conftest.err' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; } && - { ac_try='test -s conftest.$ac_objext' - { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 - (eval $ac_try) 2>&5 - ac_status=$? - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); }; }; then - ac_header_compiler=yes -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - -ac_header_compiler=no -fi -rm -f conftest.err conftest.$ac_objext conftest.$ac_ext -echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 -echo "${ECHO_T}$ac_header_compiler" >&6 - -# Is the header present? -echo "$as_me:$LINENO: checking linux/version.h presence" >&5 -echo $ECHO_N "checking linux/version.h presence... $ECHO_C" >&6 -cat >conftest.$ac_ext <<_ACEOF -/* confdefs.h. */ -_ACEOF -cat confdefs.h >>conftest.$ac_ext -cat >>conftest.$ac_ext <<_ACEOF -/* end confdefs.h. */ -#include <linux/version.h> -_ACEOF -if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 - (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1 - ac_status=$? - grep -v '^ *+' conftest.er1 >conftest.err - rm -f conftest.er1 - cat conftest.err >&5 - echo "$as_me:$LINENO: \$? = $ac_status" >&5 - (exit $ac_status); } >/dev/null; then - if test -s conftest.err; then - ac_cpp_err=$ac_c_preproc_warn_flag - ac_cpp_err=$ac_cpp_err$ac_c_werror_flag +# Prepare PATH_SEPARATOR. +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + echo "#! /bin/sh" >conf$$.sh + echo "exit 0" >>conf$$.sh + chmod +x conf$$.sh + if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then + PATH_SEPARATOR=';' else - ac_cpp_err= + PATH_SEPARATOR=: fi -else - ac_cpp_err=yes + rm -f conf$$.sh fi -if test -z "$ac_cpp_err"; then - ac_header_preproc=yes -else - echo "$as_me: failed program was:" >&5 -sed 's/^/| /' conftest.$ac_ext >&5 - ac_header_preproc=no +# Find out how to test for executable files. Don't use a zero-byte file, +# as systems may use methods other than mode bits to determine executability. +cat >conf$$.file <<_ASEOF +#! /bin/sh +exit 0 +_ASEOF +chmod +x conf$$.file +if test -x conf$$.file >/dev/null 2>&1; then + ac_executable_p="test -x" +else + ac_executable_p="test -f" fi -rm -f conftest.err conftest.$ac_ext -echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 -echo "${ECHO_T}$ac_header_preproc" >&6 +rm -f conf$$.file -# So? What about this header? -case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in - yes:no: ) - { echo "$as_me:$LINENO: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&5 -echo "$as_me: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&2;} - { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the compiler's result" >&5 -echo "$as_me: WARNING: linux/version.h: proceeding with the compiler's result" >&2;} - ac_header_preproc=yes +# Extract the first word of "msgmerge", so it can be a program name with args. +set dummy msgmerge; ac_word=$2 +echo "$as_me:$LINENO: checking for $ac_word" >&5 +echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6 +if test "${ac_cv_path_MSGMERGE+set}" = set; then + echo $ECHO_N "(cached) $ECHO_C" >&6 +else + case "$MSGMERGE" in + [\\/]* | ?:[\\/]*) + ac_cv_path_MSGMERGE="$MSGMERGE" # Let the user override the test with a path. ;; - no:yes:* ) - { echo "$as_me:$LINENO: WARNING: linux/version.h: present but cannot be compiled" >&5 -echo "$as_me: WARNING: linux/version.h: present but cannot be compiled" >&2;} - { echo "$as_me:$LINENO: WARNING: linux/version.h: check for missing prerequisite headers?" >&5 -echo "$as_me: WARNING: linux/version.h: check for missing prerequisite headers?" >&2;} - { echo "$as_me:$LINENO: WARNING: linux/version.h: see the Autoconf documentation" >&5 -echo "$as_me: WARNING: linux/version.h: see the Autoconf documentation" >&2;} - { echo "$as_me:$LINENO: WARNING: linux/version.h: section \"Present But Cannot Be Compiled\"" >&5 -echo "$as_me: WARNING: linux/version.h: section \"Present But Cannot Be Compiled\"" >&2;} - { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the preprocessor's result" >&5 -echo "$as_me: WARNING: linux/version.h: proceeding with the preprocessor's result" >&2;} - { echo "$as_me:$LINENO: WARNING: linux/version.h: in the future, the compiler will take precedence" >&5 -echo "$as_me: WARNING: linux/version.h: in the future, the compiler will take precedence" >&2;} - ( - cat <<\_ASBOX -## ------------------------------------------ ## -## Report this to the AC_PACKAGE_NAME lists. ## -## ------------------------------------------ ## -_ASBOX - ) | - sed "s/^/$as_me: WARNING: /" >&2 + *) + ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR + for ac_dir in $PATH; do + IFS="$ac_save_IFS" + test -z "$ac_dir" && ac_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then + if $ac_dir/$ac_word --update -q /dev/null /dev/null >/dev/null 2>&1; then + ac_cv_path_MSGMERGE="$ac_dir/$ac_word$ac_exec_ext" + break 2 + fi + fi + done + done + IFS="$ac_save_IFS" + test -z "$ac_cv_path_MSGMERGE" && ac_cv_path_MSGMERGE=":" ;; esac -echo "$as_me:$LINENO: checking for linux/version.h" >&5 -echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6 -if test "${ac_cv_header_linux_version_h+set}" = set; then - echo $ECHO_N "(cached) $ECHO_C" >&6 -else - ac_cv_header_linux_version_h=$ac_header_preproc -fi -echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5 -echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6 - fi -if test $ac_cv_header_linux_version_h = yes; then - msgformat=linux +MSGMERGE="$ac_cv_path_MSGMERGE" +if test "$MSGMERGE" != ":"; then + echo "$as_me:$LINENO: result: $MSGMERGE" >&5 +echo "${ECHO_T}$MSGMERGE" >&6 else - msgformat=xopen + echo "$as_me:$LINENO: result: no" >&5 +echo "${ECHO_T}no" >&6 fi + if test "$GMSGFMT" != ":"; then + if $GMSGFMT --statistics /dev/null >/dev/null 2>&1 && + (if $GMSGFMT --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + : ; + else + GMSGFMT=`echo "$GMSGFMT" | sed -e 's,^.*/,,'` + echo "$as_me:$LINENO: result: found $GMSGFMT program is not GNU msgfmt; ignore it" >&5 +echo "${ECHO_T}found $GMSGFMT program is not GNU msgfmt; ignore it" >&6 + GMSGFMT=":" + fi + fi - sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed - fi - sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \ - $srcdir/po2tbl.sed.in > po2tbl.sed - fi - - if test "$PACKAGE" = "gettext"; then - GT_NO="#NO#" - GT_YES= - else - GT_NO= - GT_YES="#YES#" - fi - - - - MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs" + if test "$XGETTEXT" != ":"; then + if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 && + (if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then + : ; + else + echo "$as_me:$LINENO: result: found xgettext program is not GNU xgettext; ignore it" >&5 +echo "${ECHO_T}found xgettext program is not GNU xgettext; ignore it" >&6 + XGETTEXT=":" + fi + rm -f messages.po + fi + ac_config_commands="$ac_config_commands default-1" - l= - - - if test -f $srcdir/po/POTFILES.in; then - test -d po || mkdir po - if test "x$srcdir" != "x."; then - if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then - posrcprefix="$srcdir/" - else - posrcprefix="../$srcdir/" - fi - else - posrcprefix="../" - fi - rm -f po/POTFILES - sed -e "/^#/d" -e "/^\$/d" -e "s,.*, $posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \ - < $srcdir/po/POTFILES.in > po/POTFILES - fi . ${srcdir}/../bfd/configure.host @@ -8806,6 +11419,7 @@ if test x${all_targets} = xfalse ; then bfd_arm_arch) ta="$ta arm-dis.lo" ;; bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; + bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; @@ -8817,7 +11431,7 @@ if test x${all_targets} = xfalse ; then bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;; - bfd_i386_arch) ta="$ta i386-dis.lo" ;; + bfd_i386_arch) ta="$ta i386-dis.lo i386-opc.lo" ;; bfd_i860_arch) ta="$ta i860-dis.lo" ;; bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; @@ -8831,6 +11445,7 @@ if test x${all_targets} = xfalse ; then bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; bfd_maxq_arch) ta="$ta maxq-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; + bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;; bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; @@ -8848,6 +11463,7 @@ if test x${all_targets} = xfalse ; then bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; + bfd_score_arch) ta="$ta score-dis.lo" ;; bfd_sh_arch) # We can't decide what we want just from the CPU family. # We want SH5 support unless a specific version of sh is @@ -8862,8 +11478,9 @@ if test x${all_targets} = xfalse ; then break;; esac; done - ta="$ta sh-dis.lo" ;; + ta="$ta sh-dis.lo cgen-bitset.lo" ;; bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; + bfd_spu_arch) ta="$ta spu-dis.lo spu-opc.lo" ;; bfd_tahoe_arch) ;; bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; @@ -8924,8 +11541,6 @@ fi ac_config_files="$ac_config_files Makefile po/Makefile.in:po/Make-in" - ac_config_commands="$ac_config_commands default" - cat >confcache <<\_ACEOF # This file is a shell script that caches the results of configure # tests run on this system so they can be shared between configure @@ -9488,6 +12103,253 @@ cat >>$CONFIG_STATUS <<_ACEOF AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir" +# The HP-UX ksh and POSIX shell print the target directory to stdout +# if CDPATH is set. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +sed_quote_subst='$sed_quote_subst' +double_quote_subst='$double_quote_subst' +delay_variable_subst='$delay_variable_subst' +enable_shared='`$ECHO "X$enable_shared" | $Xsed -e "$delay_single_quote_subst"`' +macro_version='`$ECHO "X$macro_version" | $Xsed -e "$delay_single_quote_subst"`' +macro_revision='`$ECHO "X$macro_revision" | $Xsed -e "$delay_single_quote_subst"`' +enable_static='`$ECHO "X$enable_static" | $Xsed -e "$delay_single_quote_subst"`' +pic_mode='`$ECHO "X$pic_mode" | $Xsed -e "$delay_single_quote_subst"`' +enable_fast_install='`$ECHO "X$enable_fast_install" | $Xsed -e "$delay_single_quote_subst"`' +host_alias='`$ECHO "X$host_alias" | $Xsed -e "$delay_single_quote_subst"`' +host='`$ECHO "X$host" | $Xsed -e "$delay_single_quote_subst"`' +host_os='`$ECHO "X$host_os" | $Xsed -e "$delay_single_quote_subst"`' +build_alias='`$ECHO "X$build_alias" | $Xsed -e "$delay_single_quote_subst"`' +build='`$ECHO "X$build" | $Xsed -e "$delay_single_quote_subst"`' +build_os='`$ECHO "X$build_os" | $Xsed -e "$delay_single_quote_subst"`' +SED='`$ECHO "X$SED" | $Xsed -e "$delay_single_quote_subst"`' +Xsed='`$ECHO "X$Xsed" | $Xsed -e "$delay_single_quote_subst"`' +GREP='`$ECHO "X$GREP" | $Xsed -e "$delay_single_quote_subst"`' +EGREP='`$ECHO "X$EGREP" | $Xsed -e "$delay_single_quote_subst"`' +FGREP='`$ECHO "X$FGREP" | $Xsed -e "$delay_single_quote_subst"`' +LD='`$ECHO "X$LD" | $Xsed -e "$delay_single_quote_subst"`' +NM='`$ECHO "X$NM" | $Xsed -e "$delay_single_quote_subst"`' +LN_S='`$ECHO "X$LN_S" | $Xsed -e "$delay_single_quote_subst"`' +max_cmd_len='`$ECHO "X$max_cmd_len" | $Xsed -e "$delay_single_quote_subst"`' +ac_objext='`$ECHO "X$ac_objext" | $Xsed -e "$delay_single_quote_subst"`' +exeext='`$ECHO "X$exeext" | $Xsed -e "$delay_single_quote_subst"`' +lt_unset='`$ECHO "X$lt_unset" | $Xsed -e "$delay_single_quote_subst"`' +lt_SP2NL='`$ECHO "X$lt_SP2NL" | $Xsed -e "$delay_single_quote_subst"`' +lt_NL2SP='`$ECHO "X$lt_NL2SP" | $Xsed -e "$delay_single_quote_subst"`' +reload_flag='`$ECHO "X$reload_flag" | $Xsed -e "$delay_single_quote_subst"`' +reload_cmds='`$ECHO "X$reload_cmds" | $Xsed -e "$delay_single_quote_subst"`' +deplibs_check_method='`$ECHO "X$deplibs_check_method" | $Xsed -e "$delay_single_quote_subst"`' +file_magic_cmd='`$ECHO "X$file_magic_cmd" | $Xsed -e "$delay_single_quote_subst"`' +AR='`$ECHO "X$AR" | $Xsed -e "$delay_single_quote_subst"`' +AR_FLAGS='`$ECHO "X$AR_FLAGS" | $Xsed -e "$delay_single_quote_subst"`' +STRIP='`$ECHO "X$STRIP" | $Xsed -e "$delay_single_quote_subst"`' +RANLIB='`$ECHO "X$RANLIB" | $Xsed -e "$delay_single_quote_subst"`' +old_postinstall_cmds='`$ECHO "X$old_postinstall_cmds" | $Xsed -e "$delay_single_quote_subst"`' +old_postuninstall_cmds='`$ECHO "X$old_postuninstall_cmds" | $Xsed -e "$delay_single_quote_subst"`' +old_archive_cmds='`$ECHO "X$old_archive_cmds" | $Xsed -e "$delay_single_quote_subst"`' +CC='`$ECHO "X$CC" | $Xsed -e "$delay_single_quote_subst"`' +CFLAGS='`$ECHO "X$CFLAGS" | $Xsed -e "$delay_single_quote_subst"`' +compiler='`$ECHO "X$compiler" | $Xsed -e "$delay_single_quote_subst"`' +GCC='`$ECHO "X$GCC" | $Xsed -e "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_pipe='`$ECHO "X$lt_cv_sys_global_symbol_pipe" | $Xsed -e "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_to_cdecl='`$ECHO "X$lt_cv_sys_global_symbol_to_cdecl" | $Xsed -e "$delay_single_quote_subst"`' +lt_cv_sys_global_symbol_to_c_name_address='`$ECHO "X$lt_cv_sys_global_symbol_to_c_name_address" | $Xsed -e "$delay_single_quote_subst"`' +objdir='`$ECHO "X$objdir" | $Xsed -e "$delay_single_quote_subst"`' +SHELL='`$ECHO "X$SHELL" | $Xsed -e "$delay_single_quote_subst"`' +ECHO='`$ECHO "X$ECHO" | $Xsed -e "$delay_single_quote_subst"`' +MAGIC_CMD='`$ECHO "X$MAGIC_CMD" | $Xsed -e "$delay_single_quote_subst"`' +lt_prog_compiler_no_builtin_flag='`$ECHO "X$lt_prog_compiler_no_builtin_flag" | $Xsed -e "$delay_single_quote_subst"`' +lt_prog_compiler_wl='`$ECHO "X$lt_prog_compiler_wl" | $Xsed -e "$delay_single_quote_subst"`' +lt_prog_compiler_pic='`$ECHO "X$lt_prog_compiler_pic" | $Xsed -e "$delay_single_quote_subst"`' +lt_prog_compiler_static='`$ECHO "X$lt_prog_compiler_static" | $Xsed -e "$delay_single_quote_subst"`' +lt_cv_prog_compiler_c_o='`$ECHO "X$lt_cv_prog_compiler_c_o" | $Xsed -e "$delay_single_quote_subst"`' +need_locks='`$ECHO "X$need_locks" | $Xsed -e "$delay_single_quote_subst"`' +libext='`$ECHO "X$libext" | $Xsed -e "$delay_single_quote_subst"`' +shrext_cmds='`$ECHO "X$shrext_cmds" | $Xsed -e "$delay_single_quote_subst"`' +extract_expsyms_cmds='`$ECHO "X$extract_expsyms_cmds" | $Xsed -e "$delay_single_quote_subst"`' +archive_cmds_need_lc='`$ECHO "X$archive_cmds_need_lc" | $Xsed -e "$delay_single_quote_subst"`' +enable_shared_with_static_runtimes='`$ECHO "X$enable_shared_with_static_runtimes" | $Xsed -e "$delay_single_quote_subst"`' +export_dynamic_flag_spec='`$ECHO "X$export_dynamic_flag_spec" | $Xsed -e "$delay_single_quote_subst"`' +whole_archive_flag_spec='`$ECHO "X$whole_archive_flag_spec" | $Xsed -e "$delay_single_quote_subst"`' +compiler_needs_object='`$ECHO "X$compiler_needs_object" | $Xsed -e "$delay_single_quote_subst"`' +old_archive_from_new_cmds='`$ECHO "X$old_archive_from_new_cmds" | $Xsed -e "$delay_single_quote_subst"`' +old_archive_from_expsyms_cmds='`$ECHO "X$old_archive_from_expsyms_cmds" | $Xsed -e "$delay_single_quote_subst"`' +archive_cmds='`$ECHO "X$archive_cmds" | $Xsed -e "$delay_single_quote_subst"`' +archive_expsym_cmds='`$ECHO "X$archive_expsym_cmds" | $Xsed -e "$delay_single_quote_subst"`' +module_cmds='`$ECHO "X$module_cmds" | $Xsed -e "$delay_single_quote_subst"`' +module_expsym_cmds='`$ECHO "X$module_expsym_cmds" | $Xsed -e "$delay_single_quote_subst"`' +with_gnu_ld='`$ECHO "X$with_gnu_ld" | $Xsed -e "$delay_single_quote_subst"`' +allow_undefined_flag='`$ECHO "X$allow_undefined_flag" | $Xsed -e "$delay_single_quote_subst"`' +no_undefined_flag='`$ECHO "X$no_undefined_flag" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_libdir_flag_spec='`$ECHO "X$hardcode_libdir_flag_spec" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_libdir_flag_spec_ld='`$ECHO "X$hardcode_libdir_flag_spec_ld" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_libdir_separator='`$ECHO "X$hardcode_libdir_separator" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_direct='`$ECHO "X$hardcode_direct" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_direct_absolute='`$ECHO "X$hardcode_direct_absolute" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_minus_L='`$ECHO "X$hardcode_minus_L" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_shlibpath_var='`$ECHO "X$hardcode_shlibpath_var" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_automatic='`$ECHO "X$hardcode_automatic" | $Xsed -e "$delay_single_quote_subst"`' +inherit_rpath='`$ECHO "X$inherit_rpath" | $Xsed -e "$delay_single_quote_subst"`' +link_all_deplibs='`$ECHO "X$link_all_deplibs" | $Xsed -e "$delay_single_quote_subst"`' +fix_srcfile_path='`$ECHO "X$fix_srcfile_path" | $Xsed -e "$delay_single_quote_subst"`' +always_export_symbols='`$ECHO "X$always_export_symbols" | $Xsed -e "$delay_single_quote_subst"`' +export_symbols_cmds='`$ECHO "X$export_symbols_cmds" | $Xsed -e "$delay_single_quote_subst"`' +exclude_expsyms='`$ECHO "X$exclude_expsyms" | $Xsed -e "$delay_single_quote_subst"`' +include_expsyms='`$ECHO "X$include_expsyms" | $Xsed -e "$delay_single_quote_subst"`' +prelink_cmds='`$ECHO "X$prelink_cmds" | $Xsed -e "$delay_single_quote_subst"`' +file_list_spec='`$ECHO "X$file_list_spec" | $Xsed -e "$delay_single_quote_subst"`' +variables_saved_for_relink='`$ECHO "X$variables_saved_for_relink" | $Xsed -e "$delay_single_quote_subst"`' +need_lib_prefix='`$ECHO "X$need_lib_prefix" | $Xsed -e "$delay_single_quote_subst"`' +need_version='`$ECHO "X$need_version" | $Xsed -e "$delay_single_quote_subst"`' +version_type='`$ECHO "X$version_type" | $Xsed -e "$delay_single_quote_subst"`' +runpath_var='`$ECHO "X$runpath_var" | $Xsed -e "$delay_single_quote_subst"`' +shlibpath_var='`$ECHO "X$shlibpath_var" | $Xsed -e "$delay_single_quote_subst"`' +shlibpath_overrides_runpath='`$ECHO "X$shlibpath_overrides_runpath" | $Xsed -e "$delay_single_quote_subst"`' +libname_spec='`$ECHO "X$libname_spec" | $Xsed -e "$delay_single_quote_subst"`' +library_names_spec='`$ECHO "X$library_names_spec" | $Xsed -e "$delay_single_quote_subst"`' +soname_spec='`$ECHO "X$soname_spec" | $Xsed -e "$delay_single_quote_subst"`' +postinstall_cmds='`$ECHO "X$postinstall_cmds" | $Xsed -e "$delay_single_quote_subst"`' +postuninstall_cmds='`$ECHO "X$postuninstall_cmds" | $Xsed -e "$delay_single_quote_subst"`' +finish_cmds='`$ECHO "X$finish_cmds" | $Xsed -e "$delay_single_quote_subst"`' +finish_eval='`$ECHO "X$finish_eval" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_into_libs='`$ECHO "X$hardcode_into_libs" | $Xsed -e "$delay_single_quote_subst"`' +sys_lib_search_path_spec='`$ECHO "X$sys_lib_search_path_spec" | $Xsed -e "$delay_single_quote_subst"`' +sys_lib_dlsearch_path_spec='`$ECHO "X$sys_lib_dlsearch_path_spec" | $Xsed -e "$delay_single_quote_subst"`' +hardcode_action='`$ECHO "X$hardcode_action" | $Xsed -e "$delay_single_quote_subst"`' +enable_dlopen='`$ECHO "X$enable_dlopen" | $Xsed -e "$delay_single_quote_subst"`' +enable_dlopen_self='`$ECHO "X$enable_dlopen_self" | $Xsed -e "$delay_single_quote_subst"`' +enable_dlopen_self_static='`$ECHO "X$enable_dlopen_self_static" | $Xsed -e "$delay_single_quote_subst"`' +old_striplib='`$ECHO "X$old_striplib" | $Xsed -e "$delay_single_quote_subst"`' +striplib='`$ECHO "X$striplib" | $Xsed -e "$delay_single_quote_subst"`' + +LTCC='$LTCC' +LTCFLAGS='$LTCFLAGS' +compiler='$compiler_DEFAULT' + +# Quote evaled strings. +for var in SED \ +GREP \ +EGREP \ +FGREP \ +LD \ +NM \ +LN_S \ +lt_SP2NL \ +lt_NL2SP \ +reload_flag \ +deplibs_check_method \ +file_magic_cmd \ +AR \ +AR_FLAGS \ +STRIP \ +RANLIB \ +CC \ +CFLAGS \ +compiler \ +lt_cv_sys_global_symbol_pipe \ +lt_cv_sys_global_symbol_to_cdecl \ +lt_cv_sys_global_symbol_to_c_name_address \ +SHELL \ +ECHO \ +lt_prog_compiler_no_builtin_flag \ +lt_prog_compiler_wl \ +lt_prog_compiler_pic \ +lt_prog_compiler_static \ +lt_cv_prog_compiler_c_o \ +need_locks \ +shrext_cmds \ +export_dynamic_flag_spec \ +whole_archive_flag_spec \ +compiler_needs_object \ +with_gnu_ld \ +allow_undefined_flag \ +no_undefined_flag \ +hardcode_libdir_flag_spec \ +hardcode_libdir_flag_spec_ld \ +hardcode_libdir_separator \ +fix_srcfile_path \ +exclude_expsyms \ +include_expsyms \ +file_list_spec \ +variables_saved_for_relink \ +libname_spec \ +library_names_spec \ +soname_spec \ +finish_eval \ +old_striplib \ +striplib; do + case \`eval \\\\\$ECHO "X\\\\\$\$var"\` in + *[\\\\\\\`\\"\\\$]*) + eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"X\\\$\$var\\" | \\\$Xsed -e \\"\\\$sed_quote_subst\\"\\\`\\\\\\"" + ;; + *) + eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" + ;; + esac +done + +# Double-quote double-evaled strings. +for var in reload_cmds \ +old_postinstall_cmds \ +old_postuninstall_cmds \ +old_archive_cmds \ +extract_expsyms_cmds \ +old_archive_from_new_cmds \ +old_archive_from_expsyms_cmds \ +archive_cmds \ +archive_expsym_cmds \ +module_cmds \ +module_expsym_cmds \ +export_symbols_cmds \ +prelink_cmds \ +postinstall_cmds \ +postuninstall_cmds \ +finish_cmds \ +sys_lib_search_path_spec \ +sys_lib_dlsearch_path_spec; do + case \`eval \\\\\$ECHO "X\\\\\$\$var"\` in + *[\\\\\\\`\\"\\\$]*) + eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"X\\\$\$var\\" | \\\$Xsed -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\"" + ;; + *) + eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" + ;; + esac +done + +# Fix-up fallback echo if it was mangled by the above quoting rules. +case \$lt_ECHO in +*'\\\$0 --fallback-echo"') lt_ECHO=\`\$ECHO "X\$lt_ECHO" | \$Xsed -e 's/\\\\\\\\\\\\\\\$0 --fallback-echo"\$/\$0 --fallback-echo"/'\` + ;; +esac + +ac_aux_dir='$ac_aux_dir' +xsi_shell='$xsi_shell' +lt_shell_append='$lt_shell_append' + +# See if we are running on zsh, and set the options which allow our +# commands through without removal of \ escapes INIT. +if test -n "\${ZSH_VERSION+set}" ; then + setopt NO_GLOB_SUBST +fi + + + PACKAGE='$PACKAGE' + VERSION='$VERSION' + TIMESTAMP='$TIMESTAMP' + RM='$RM' + ofile='$ofile' + + + +# Capture the value of obsolete ALL_LINGUAS because we need it to compute + # POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES, CATALOGS. But hide it + # from automake. + eval 'OBSOLETE_ALL_LINGUAS''="$ALL_LINGUAS"' + # Capture the value of LINGUAS because we need it to compute CATALOGS. + LINGUAS="${LINGUAS-%UNSET%}" + + _ACEOF @@ -9500,7 +12362,8 @@ do "Makefile" ) CONFIG_FILES="$CONFIG_FILES Makefile" ;; "po/Makefile.in" ) CONFIG_FILES="$CONFIG_FILES po/Makefile.in:po/Make-in" ;; "depfiles" ) CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;; - "default" ) CONFIG_COMMANDS="$CONFIG_COMMANDS default" ;; + "libtool" ) CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;; + "default-1" ) CONFIG_COMMANDS="$CONFIG_COMMANDS default-1" ;; "config.h" ) CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;; *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5 echo "$as_me: error: invalid argument: $ac_config_target" >&2;} @@ -9641,8 +12504,18 @@ s,@AR@,$AR,;t t s,@ac_ct_AR@,$ac_ct_AR,;t t s,@RANLIB@,$RANLIB,;t t s,@ac_ct_RANLIB@,$ac_ct_RANLIB,;t t -s,@LN_S@,$LN_S,;t t s,@LIBTOOL@,$LIBTOOL,;t t +s,@SED@,$SED,;t t +s,@EGREP@,$EGREP,;t t +s,@FGREP@,$FGREP,;t t +s,@GREP@,$GREP,;t t +s,@LD@,$LD,;t t +s,@DUMPBIN@,$DUMPBIN,;t t +s,@ac_ct_DUMPBIN@,$ac_ct_DUMPBIN,;t t +s,@NM@,$NM,;t t +s,@LN_S@,$LN_S,;t t +s,@lt_ECHO@,$lt_ECHO,;t t +s,@CPP@,$CPP,;t t s,@WARN_CFLAGS@,$WARN_CFLAGS,;t t s,@NO_WERROR@,$NO_WERROR,;t t s,@MAINTAINER_MODE_TRUE@,$MAINTAINER_MODE_TRUE,;t t @@ -9654,29 +12527,21 @@ s,@host_noncanonical@,$host_noncanonical,;t t s,@target_noncanonical@,$target_noncanonical,;t t s,@bfdlibdir@,$bfdlibdir,;t t s,@bfdincludedir@,$bfdincludedir,;t t -s,@CPP@,$CPP,;t t -s,@EGREP@,$EGREP,;t t -s,@ALLOCA@,$ALLOCA,;t t s,@USE_NLS@,$USE_NLS,;t t -s,@MSGFMT@,$MSGFMT,;t t -s,@GMSGFMT@,$GMSGFMT,;t t +s,@LIBINTL@,$LIBINTL,;t t +s,@LIBINTL_DEP@,$LIBINTL_DEP,;t t +s,@INCINTL@,$INCINTL,;t t s,@XGETTEXT@,$XGETTEXT,;t t -s,@USE_INCLUDED_LIBINTL@,$USE_INCLUDED_LIBINTL,;t t +s,@GMSGFMT@,$GMSGFMT,;t t +s,@POSUB@,$POSUB,;t t s,@CATALOGS@,$CATALOGS,;t t -s,@CATOBJEXT@,$CATOBJEXT,;t t s,@DATADIRNAME@,$DATADIRNAME,;t t -s,@GMOFILES@,$GMOFILES,;t t s,@INSTOBJEXT@,$INSTOBJEXT,;t t -s,@INTLDEPS@,$INTLDEPS,;t t -s,@INTLLIBS@,$INTLLIBS,;t t -s,@INTLOBJS@,$INTLOBJS,;t t -s,@POFILES@,$POFILES,;t t -s,@POSUB@,$POSUB,;t t -s,@INCLUDE_LOCALE_H@,$INCLUDE_LOCALE_H,;t t -s,@GT_NO@,$GT_NO,;t t -s,@GT_YES@,$GT_YES,;t t +s,@GENCAT@,$GENCAT,;t t +s,@CATOBJEXT@,$CATOBJEXT,;t t s,@MKINSTALLDIRS@,$MKINSTALLDIRS,;t t -s,@l@,$l,;t t +s,@MSGFMT@,$MSGFMT,;t t +s,@MSGMERGE@,$MSGMERGE,;t t s,@CC_FOR_BUILD@,$CC_FOR_BUILD,;t t s,@EXEEXT_FOR_BUILD@,$EXEEXT_FOR_BUILD,;t t s,@HDEFINES@,$HDEFINES,;t t @@ -10371,7 +13236,656 @@ echo "$as_me: error: cannot create directory $dirpart/$fdir" >&2;} done done ;; - default ) sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile ;; + libtool ) + + # See if we are running on zsh, and set the options which allow our + # commands through without removal of \ escapes. + if test -n "${ZSH_VERSION+set}" ; then + setopt NO_GLOB_SUBST + fi + + cfgfile="${ofile}T" + trap "$RM \"$cfgfile\"; exit 1" 1 2 15 + $RM "$cfgfile" + + cat <<_LT_EOF >> "$cfgfile" +#! $SHELL + +# `$ECHO "$ofile" | sed 's%^.*/%%'` - Provide generalized library-building support services. +# Generated automatically by $as_me (GNU $PACKAGE$TIMESTAMP) $VERSION +# Libtool was configured on host `(hostname || uname -n) 2>/dev/null | sed 1q`: +# NOTE: Changes made to this file will be lost: look at ltmain.sh. +# +# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, +# 2006, 2007 Free Software Foundation, Inc. +# +# This file is part of GNU Libtool: +# Originally by Gordon Matzigkeit <gord@gnu.ai.mit.edu>, 1996 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, a copy can be downloaded from +# http://www.gnu.org/copyleft/gpl.html, or by writing to the Free +# Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301, USA. +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + + +# The names of the tagged configurations supported by this script. +available_tags="" + +# ### BEGIN LIBTOOL CONFIG + +# Whether or not to build shared libraries. +build_libtool_libs=$enable_shared + +# Which release of libtool.m4 was used? +macro_version=$macro_version +macro_revision=$macro_revision + +# Whether or not to build static libraries. +build_old_libs=$enable_static + +# What type of objects to build. +pic_mode=$pic_mode + +# Whether or not to optimize for fast installation. +fast_install=$enable_fast_install + +# The host system. +host_alias=$host_alias +host=$host +host_os=$host_os + +# The build system. +build_alias=$build_alias +build=$build +build_os=$build_os + +# A sed program that does not truncate output. +SED=$lt_SED + +# Sed that helps us avoid accidentally triggering echo(1) options like -n. +Xsed="\$SED -e 1s/^X//" + +# A grep program that handles long lines. +GREP=$lt_GREP + +# An ERE matcher. +EGREP=$lt_EGREP + +# A literal string matcher. +FGREP=$lt_FGREP + +# A BSD- or MS-compatible name lister. +NM=$lt_NM + +# Whether we need soft or hard links. +LN_S=$lt_LN_S + +# What is the maximum length of a command? +max_cmd_len=$max_cmd_len + +# Object file suffix (normally "o"). +objext=$ac_objext + +# Executable file suffix (normally ""). +exeext=$exeext + +# whether the shell understands "unset". +lt_unset=$lt_unset + +# turn spaces into newlines. +SP2NL=$lt_lt_SP2NL + +# turn newlines into spaces. +NL2SP=$lt_lt_NL2SP + +# How to create reloadable object files. +reload_flag=$lt_reload_flag +reload_cmds=$lt_reload_cmds + +# Method to check whether dependent libraries are shared objects. +deplibs_check_method=$lt_deplibs_check_method + +# Command to use when deplibs_check_method == "file_magic". +file_magic_cmd=$lt_file_magic_cmd + +# The archiver. +AR=$lt_AR +AR_FLAGS=$lt_AR_FLAGS + +# A symbol stripping program. +STRIP=$lt_STRIP + +# Commands used to install an old-style archive. +RANLIB=$lt_RANLIB +old_postinstall_cmds=$lt_old_postinstall_cmds +old_postuninstall_cmds=$lt_old_postuninstall_cmds + +# A C compiler. +LTCC=$lt_CC + +# LTCC compiler flags. +LTCFLAGS=$lt_CFLAGS + +# Take the output of nm and produce a listing of raw symbols and C names. +global_symbol_pipe=$lt_lt_cv_sys_global_symbol_pipe + +# Transform the output of nm in a proper C declaration. +global_symbol_to_cdecl=$lt_lt_cv_sys_global_symbol_to_cdecl + +# Transform the output of nm in a C name address pair. +global_symbol_to_c_name_address=$lt_lt_cv_sys_global_symbol_to_c_name_address + +# The name of the directory that contains temporary libtool files. +objdir=$objdir + +# Shell to use when invoking shell scripts. +SHELL=$lt_SHELL + +# An echo program that does not interpret backslashes. +ECHO=$lt_ECHO + +# Used to examine libraries when file_magic_cmd begins with "file". +MAGIC_CMD=$MAGIC_CMD + +# Must we lock files when doing compilation? +need_locks=$lt_need_locks + +# Old archive suffix (normally "a"). +libext=$libext + +# Shared library suffix (normally ".so"). +shrext_cmds=$lt_shrext_cmds + +# The commands to extract the exported symbol list from a shared archive. +extract_expsyms_cmds=$lt_extract_expsyms_cmds + +# Variables whose values should be saved in libtool wrapper scripts and +# restored at link time. +variables_saved_for_relink=$lt_variables_saved_for_relink + +# Do we need the "lib" prefix for modules? +need_lib_prefix=$need_lib_prefix + +# Do we need a version for libraries? +need_version=$need_version + +# Library versioning type. +version_type=$version_type + +# Shared library runtime path variable. +runpath_var=$runpath_var + +# Shared library path variable. +shlibpath_var=$shlibpath_var + +# Is shlibpath searched before the hard-coded library search path? +shlibpath_overrides_runpath=$shlibpath_overrides_runpath + +# Format of library name prefix. +libname_spec=$lt_libname_spec + +# List of archive names. First name is the real one, the rest are links. +# The last name is the one that the linker finds with -lNAME +library_names_spec=$lt_library_names_spec + +# The coded name of the library, if different from the real name. +soname_spec=$lt_soname_spec + +# Command to use after installation of a shared archive. +postinstall_cmds=$lt_postinstall_cmds + +# Command to use after uninstallation of a shared archive. +postuninstall_cmds=$lt_postuninstall_cmds + +# Commands used to finish a libtool library installation in a directory. +finish_cmds=$lt_finish_cmds + +# As "finish_cmds", except a single script fragment to be evaled but +# not shown. +finish_eval=$lt_finish_eval + +# Whether we should hardcode library paths into libraries. +hardcode_into_libs=$hardcode_into_libs + +# Compile-time system search path for libraries. +sys_lib_search_path_spec=$lt_sys_lib_search_path_spec + +# Run-time system search path for libraries. +sys_lib_dlsearch_path_spec=$lt_sys_lib_dlsearch_path_spec + +# Whether dlopen is supported. +dlopen_support=$enable_dlopen + +# Whether dlopen of programs is supported. +dlopen_self=$enable_dlopen_self + +# Whether dlopen of statically linked programs is supported. +dlopen_self_static=$enable_dlopen_self_static + +# Commands to strip libraries. +old_striplib=$lt_old_striplib +striplib=$lt_striplib + + +# The linker used to build libraries. +LD=$lt_LD + +# Commands used to build an old-style archive. +old_archive_cmds=$lt_old_archive_cmds + +# A language specific compiler. +CC=$lt_compiler + +# Is the compiler the GNU compiler? +with_gcc=$GCC + +# Compiler flag to turn off builtin functions. +no_builtin_flag=$lt_lt_prog_compiler_no_builtin_flag + +# How to pass a linker flag through the compiler. +wl=$lt_lt_prog_compiler_wl + +# Additional compiler flags for building library objects. +pic_flag=$lt_lt_prog_compiler_pic + +# Compiler flag to prevent dynamic linking. +link_static_flag=$lt_lt_prog_compiler_static + +# Does compiler simultaneously support -c and -o options? +compiler_c_o=$lt_lt_cv_prog_compiler_c_o + +# Whether or not to add -lc for building shared libraries. +build_libtool_need_lc=$archive_cmds_need_lc + +# Whether or not to disallow shared libs when runtime libs are static. +allow_libtool_libs_with_static_runtimes=$enable_shared_with_static_runtimes + +# Compiler flag to allow reflexive dlopens. +export_dynamic_flag_spec=$lt_export_dynamic_flag_spec + +# Compiler flag to generate shared objects directly from archives. +whole_archive_flag_spec=$lt_whole_archive_flag_spec + +# Whether the compiler copes with passing no objects directly. +compiler_needs_object=$lt_compiler_needs_object + +# Create an old-style archive from a shared archive. +old_archive_from_new_cmds=$lt_old_archive_from_new_cmds + +# Create a temporary old-style archive to link instead of a shared archive. +old_archive_from_expsyms_cmds=$lt_old_archive_from_expsyms_cmds + +# Commands used to build a shared archive. +archive_cmds=$lt_archive_cmds +archive_expsym_cmds=$lt_archive_expsym_cmds + +# Commands used to build a loadable module if different from building +# a shared archive. +module_cmds=$lt_module_cmds +module_expsym_cmds=$lt_module_expsym_cmds + +# Whether we are building with GNU ld or not. +with_gnu_ld=$lt_with_gnu_ld + +# Flag that allows shared libraries with undefined symbols to be built. +allow_undefined_flag=$lt_allow_undefined_flag + +# Flag that enforces no undefined symbols. +no_undefined_flag=$lt_no_undefined_flag + +# Flag to hardcode \$libdir into a binary during linking. +# This must work even if \$libdir does not exist +hardcode_libdir_flag_spec=$lt_hardcode_libdir_flag_spec + +# If ld is used when linking, flag to hardcode \$libdir into a binary +# during linking. This must work even if \$libdir does not exist. +hardcode_libdir_flag_spec_ld=$lt_hardcode_libdir_flag_spec_ld + +# Whether we need a single "-rpath" flag with a separated argument. +hardcode_libdir_separator=$lt_hardcode_libdir_separator + +# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes +# DIR into the resulting binary. +hardcode_direct=$hardcode_direct + +# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes +# DIR into the resulting binary and the resulting library dependency is +# "absolute",i.e impossible to change by setting \${shlibpath_var} if the +# library is relocated. +hardcode_direct_absolute=$hardcode_direct_absolute + +# Set to "yes" if using the -LDIR flag during linking hardcodes DIR +# into the resulting binary. +hardcode_minus_L=$hardcode_minus_L + +# Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR +# into the resulting binary. +hardcode_shlibpath_var=$hardcode_shlibpath_var + +# Set to "yes" if building a shared library automatically hardcodes DIR +# into the library and all subsequent libraries and executables linked +# against it. +hardcode_automatic=$hardcode_automatic + +# Set to yes if linker adds runtime paths of dependent libraries +# to runtime path list. +inherit_rpath=$inherit_rpath + +# Whether libtool must link a program against all its dependency libraries. +link_all_deplibs=$link_all_deplibs + +# Fix the shell variable \$srcfile for the compiler. +fix_srcfile_path=$lt_fix_srcfile_path + +# Set to "yes" if exported symbols are required. +always_export_symbols=$always_export_symbols + +# The commands to list exported symbols. +export_symbols_cmds=$lt_export_symbols_cmds + +# Symbols that should not be listed in the preloaded symbols. +exclude_expsyms=$lt_exclude_expsyms + +# Symbols that must always be exported. +include_expsyms=$lt_include_expsyms + +# Commands necessary for linking programs (against libraries) with templates. +prelink_cmds=$lt_prelink_cmds + +# Specify filename containing input files. +file_list_spec=$lt_file_list_spec + +# How to hardcode a shared library path into an executable. +hardcode_action=$hardcode_action + +# ### END LIBTOOL CONFIG + +_LT_EOF + + case $host_os in + aix3*) + cat <<\_LT_EOF >> "$cfgfile" +# AIX sometimes has problems with the GCC collect2 program. For some +# reason, if we set the COLLECT_NAMES environment variable, the problems +# vanish in a puff of smoke. +if test "X${COLLECT_NAMES+set}" != Xset; then + COLLECT_NAMES= + export COLLECT_NAMES +fi +_LT_EOF + ;; + esac + + +ltmain="$ac_aux_dir/ltmain.sh" + + + # We use sed instead of cat because bash on DJGPP gets confused if + # if finds mixed CR/LF and LF-only lines. Since sed operates in + # text mode, it properly converts lines to CR/LF. This bash problem + # is reportedly fixed, but why not run on old versions too? + sed '/^# Generated shell functions inserted here/q' "$ltmain" >> "$cfgfile" \ + || (rm -f "$cfgfile"; exit 1) + + case $xsi_shell in + yes) + cat << \_LT_EOF >> "$cfgfile" +# func_dirname file append nondir_replacement +# Compute the dirname of FILE. If nonempty, add APPEND to the result, +# otherwise set result to NONDIR_REPLACEMENT. +func_dirname () +{ + case ${1} in + */*) func_dirname_result="${1%/*}${2}" ;; + * ) func_dirname_result="${3}" ;; + esac +} + +# func_basename file +func_basename () +{ + func_basename_result="${1##*/}" +} + +# func_stripname prefix suffix name +# strip PREFIX and SUFFIX off of NAME. +# PREFIX and SUFFIX must not contain globbing or regex special +# characters, hashes, percent signs, but SUFFIX may contain a leading +# dot (in which case that matches only a dot). +func_stripname () +{ + # pdksh 5.2.14 does not do ${X%$Y} correctly if both X and Y are + # positional parameters, so assign one to ordinary parameter first. + func_stripname_result=${3} + func_stripname_result=${func_stripname_result#"${1}"} + func_stripname_result=${func_stripname_result%"${2}"} +} + +# func_opt_split +func_opt_split () +{ + func_opt_split_opt=${1%%=*} + func_opt_split_arg=${1#*=} +} + +# func_lo2o object +func_lo2o () +{ + case ${1} in + *.lo) func_lo2o_result=${1%.lo}.${objext} ;; + *) func_lo2o_result=${1} ;; + esac +} +_LT_EOF + ;; + *) # Bourne compatible functions. + cat << \_LT_EOF >> "$cfgfile" +# func_dirname file append nondir_replacement +# Compute the dirname of FILE. If nonempty, add APPEND to the result, +# otherwise set result to NONDIR_REPLACEMENT. +func_dirname () +{ + # Extract subdirectory from the argument. + func_dirname_result=`$ECHO "X${1}" | $Xsed -e "$dirname"` + if test "X$func_dirname_result" = "X${1}"; then + func_dirname_result="${3}" + else + func_dirname_result="$func_dirname_result${2}" + fi +} + +# func_basename file +func_basename () +{ + func_basename_result=`$ECHO "X${1}" | $Xsed -e "$basename"` +} + +# func_stripname prefix suffix name +# strip PREFIX and SUFFIX off of NAME. +# PREFIX and SUFFIX must not contain globbing or regex special +# characters, hashes, percent signs, but SUFFIX may contain a leading +# dot (in which case that matches only a dot). +# func_strip_suffix prefix name +func_stripname () +{ + case ${2} in + .*) func_stripname_result=`$ECHO "X${3}" \ + | $Xsed -e "s%^${1}%%" -e "s%\\\\${2}\$%%"`;; + *) func_stripname_result=`$ECHO "X${3}" \ + | $Xsed -e "s%^${1}%%" -e "s%${2}\$%%"`;; + esac +} + +# sed scripts: +my_sed_long_opt='1s/^\(-[^=]*\)=.*/\1/;q' +my_sed_long_arg='1s/^-[^=]*=//' + +# func_opt_split +func_opt_split () +{ + func_opt_split_opt=`$ECHO "X${1}" | $Xsed -e "$my_sed_long_opt"` + func_opt_split_arg=`$ECHO "X${1}" | $Xsed -e "$my_sed_long_arg"` +} + +# func_lo2o object +func_lo2o () +{ + func_lo2o_result=`$ECHO "X${1}" | $Xsed -e "$lo2o"` +} +_LT_EOF +esac + +case $lt_shell_append in + yes) + cat << \_LT_EOF >> "$cfgfile" + +# func_append var value +# Append VALUE to the end of shell variable VAR. +func_append () +{ + eval "$1+=\$2" +} +_LT_EOF + ;; + *) + cat << \_LT_EOF >> "$cfgfile" + +# func_append var value +# Append VALUE to the end of shell variable VAR. +func_append () +{ + eval "$1=\$$1\$2" +} +_LT_EOF + ;; + esac + + + sed -n '/^# Generated shell functions inserted here/,$p' "$ltmain" >> "$cfgfile" \ + || (rm -f "$cfgfile"; exit 1) + + mv -f "$cfgfile" "$ofile" || + (rm -f "$ofile" && cp "$cfgfile" "$ofile" && rm -f "$cfgfile") + chmod +x "$ofile" + + ;; + default-1 ) + for ac_file in $CONFIG_FILES; do + # Support "outfile[:infile[:infile...]]" + case "$ac_file" in + *:*) ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + esac + # PO directories have a Makefile.in generated from Makefile.in.in. + case "$ac_file" in */Makefile.in) + # Adjust a relative srcdir. + ac_dir=`echo "$ac_file"|sed 's%/[^/][^/]*$%%'` + ac_dir_suffix="/`echo "$ac_dir"|sed 's%^\./%%'`" + ac_dots=`echo "$ac_dir_suffix"|sed 's%/[^/]*%../%g'` + # In autoconf-2.13 it is called $ac_given_srcdir. + # In autoconf-2.50 it is called $srcdir. + test -n "$ac_given_srcdir" || ac_given_srcdir="$srcdir" + case "$ac_given_srcdir" in + .) top_srcdir=`echo $ac_dots|sed 's%/$%%'` ;; + /*) top_srcdir="$ac_given_srcdir" ;; + *) top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + if test -f "$ac_given_srcdir/$ac_dir/POTFILES.in"; then + rm -f "$ac_dir/POTFILES" + test -n "$as_me" && echo "$as_me: creating $ac_dir/POTFILES" || echo "creating $ac_dir/POTFILES" + cat "$ac_given_srcdir/$ac_dir/POTFILES.in" | sed -e "/^#/d" -e "/^[ ]*\$/d" -e "s,.*, $top_srcdir/& \\\\," | sed -e "\$s/\(.*\) \\\\/\1/" > "$ac_dir/POTFILES" + POMAKEFILEDEPS="POTFILES.in" + # ALL_LINGUAS, POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES depend + # on $ac_dir but don't depend on user-specified configuration + # parameters. + if test -f "$ac_given_srcdir/$ac_dir/LINGUAS"; then + # The LINGUAS file contains the set of available languages. + if test -n "$OBSOLETE_ALL_LINGUAS"; then + test -n "$as_me" && echo "$as_me: setting ALL_LINGUAS in configure.in is obsolete" || echo "setting ALL_LINGUAS in configure.in is obsolete" + fi + ALL_LINGUAS_=`sed -e "/^#/d" "$ac_given_srcdir/$ac_dir/LINGUAS"` + # Hide the ALL_LINGUAS assigment from automake. + eval 'ALL_LINGUAS''=$ALL_LINGUAS_' + POMAKEFILEDEPS="$POMAKEFILEDEPS LINGUAS" + else + # The set of available languages was given in configure.in. + eval 'ALL_LINGUAS''=$OBSOLETE_ALL_LINGUAS' + fi + case "$ac_given_srcdir" in + .) srcdirpre= ;; + *) srcdirpre='$(srcdir)/' ;; + esac + POFILES= + GMOFILES= + UPDATEPOFILES= + DUMMYPOFILES= + for lang in $ALL_LINGUAS; do + POFILES="$POFILES $srcdirpre$lang.po" + GMOFILES="$GMOFILES $srcdirpre$lang.gmo" + UPDATEPOFILES="$UPDATEPOFILES $lang.po-update" + DUMMYPOFILES="$DUMMYPOFILES $lang.nop" + done + # CATALOGS depends on both $ac_dir and the user's LINGUAS + # environment variable. + INST_LINGUAS= + if test -n "$ALL_LINGUAS"; then + for presentlang in $ALL_LINGUAS; do + useit=no + if test "%UNSET%" != "$LINGUAS"; then + desiredlanguages="$LINGUAS" + else + desiredlanguages="$ALL_LINGUAS" + fi + for desiredlang in $desiredlanguages; do + # Use the presentlang catalog if desiredlang is + # a. equal to presentlang, or + # b. a variant of presentlang (because in this case, + # presentlang can be used as a fallback for messages + # which are not translated in the desiredlang catalog). + case "$desiredlang" in + "$presentlang"*) useit=yes;; + esac + done + if test $useit = yes; then + INST_LINGUAS="$INST_LINGUAS $presentlang" + fi + done + fi + CATALOGS= + if test -n "$INST_LINGUAS"; then + for lang in $INST_LINGUAS; do + CATALOGS="$CATALOGS $lang.gmo" + done + fi + test -n "$as_me" && echo "$as_me: creating $ac_dir/Makefile" || echo "creating $ac_dir/Makefile" + sed -e "/^POTFILES =/r $ac_dir/POTFILES" -e "/^# Makevars/r $ac_given_srcdir/$ac_dir/Makevars" -e "s|@POFILES@|$POFILES|g" -e "s|@GMOFILES@|$GMOFILES|g" -e "s|@UPDATEPOFILES@|$UPDATEPOFILES|g" -e "s|@DUMMYPOFILES@|$DUMMYPOFILES|g" -e "s|@CATALOGS@|$CATALOGS|g" -e "s|@POMAKEFILEDEPS@|$POMAKEFILEDEPS|g" "$ac_dir/Makefile.in" > "$ac_dir/Makefile" + for f in "$ac_given_srcdir/$ac_dir"/Rules-*; do + if test -f "$f"; then + case "$f" in + *.orig | *.bak | *~) ;; + *) cat "$f" >> "$ac_dir/Makefile" ;; + esac + fi + done + fi + ;; + esac + done ;; esac done _ACEOF diff --git a/contrib/binutils/opcodes/configure.in b/contrib/binutils/opcodes/configure.in index d19d23c..104653f 100644 --- a/contrib/binutils/opcodes/configure.in +++ b/contrib/binutils/opcodes/configure.in @@ -61,7 +61,8 @@ AC_EXEEXT AC_PROG_CC ALL_LINGUAS="fr sv tr es da de id pt_BR ro nl fi vi ga zh_CN" -CY_GNU_GETTEXT +ZW_GNU_GETTEXT_SISTER_DIR +AM_PO_SUBDIRS . ${srcdir}/../bfd/configure.host @@ -158,6 +159,7 @@ if test x${all_targets} = xfalse ; then bfd_arm_arch) ta="$ta arm-dis.lo" ;; bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; + bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; @@ -169,7 +171,7 @@ if test x${all_targets} = xfalse ; then bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;; - bfd_i386_arch) ta="$ta i386-dis.lo" ;; + bfd_i386_arch) ta="$ta i386-dis.lo i386-opc.lo" ;; bfd_i860_arch) ta="$ta i860-dis.lo" ;; bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; @@ -183,6 +185,7 @@ if test x${all_targets} = xfalse ; then bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; bfd_maxq_arch) ta="$ta maxq-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; + bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;; bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; @@ -200,6 +203,7 @@ if test x${all_targets} = xfalse ; then bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; + bfd_score_arch) ta="$ta score-dis.lo" ;; bfd_sh_arch) # We can't decide what we want just from the CPU family. # We want SH5 support unless a specific version of sh is @@ -214,8 +218,9 @@ if test x${all_targets} = xfalse ; then break;; esac; done - ta="$ta sh-dis.lo" ;; + ta="$ta sh-dis.lo cgen-bitset.lo" ;; bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; + bfd_spu_arch) ta="$ta spu-dis.lo spu-opc.lo" ;; bfd_tahoe_arch) ;; bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; @@ -273,5 +278,4 @@ AC_SUBST(archdefs) AC_SUBST(BFD_MACHINES) AC_CONFIG_FILES([Makefile po/Makefile.in:po/Make-in]) -AC_CONFIG_COMMANDS([default],[[sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile]],[[]]) AC_OUTPUT diff --git a/contrib/binutils/opcodes/cr16-dis.c b/contrib/binutils/opcodes/cr16-dis.c new file mode 100644 index 0000000..724cb9b --- /dev/null +++ b/contrib/binutils/opcodes/cr16-dis.c @@ -0,0 +1,820 @@ +/* Disassembler code for CR16. + Copyright 2007 Free Software Foundation, Inc. + Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com). + + This file is part of GAS, GDB and the GNU binutils. + + This program is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "dis-asm.h" +#include "sysdep.h" +#include "opcode/cr16.h" +#include "libiberty.h" + +/* String to print when opcode was not matched. */ +#define ILLEGAL "illegal" + /* Escape to 16-bit immediate. */ +#define ESCAPE_16_BIT 0xB + +/* Extract 'n_bits' from 'a' starting from offset 'offs'. */ +#define EXTRACT(a, offs, n_bits) \ + (n_bits == 32 ? (((a) >> (offs)) & 0xffffffffL) \ + : (((a) >> (offs)) & ((1 << (n_bits)) -1))) + +/* Set Bit Mask - a mask to set all bits starting from offset 'offs'. */ +#define SBM(offs) ((((1 << (32 - offs)) -1) << (offs))) + +typedef unsigned long dwordU; +typedef unsigned short wordU; + +typedef struct +{ + dwordU val; + int nbits; +} parameter; + +/* Structure to map valid 'cinv' instruction options. */ + +typedef struct + { + /* Cinv printed string. */ + char *istr; + /* Value corresponding to the string. */ + char *ostr; + } +cinv_entry; + +/* CR16 'cinv' options mapping. */ +const cinv_entry cr16_cinvs[] = +{ + {"cinv[i]", "cinv [i]"}, + {"cinv[i,u]", "cinv [i,u]"}, + {"cinv[d]", "cinv [d]"}, + {"cinv[d,u]", "cinv [d,u]"}, + {"cinv[d,i]", "cinv [d,i]"}, + {"cinv[d,i,u]", "cinv [d,i,u]"} +}; + +/* Number of valid 'cinv' instruction options. */ +static int NUMCINVS = ARRAY_SIZE (cr16_cinvs); + +/* Enum to distinguish different registers argument types. */ +typedef enum REG_ARG_TYPE + { + /* General purpose register (r<N>). */ + REG_ARG = 0, + /*Processor register */ + P_ARG, + } +REG_ARG_TYPE; + +/* Current opcode table entry we're disassembling. */ +const inst *instruction; +/* Current instruction we're disassembling. */ +ins currInsn; +/* The current instruction is read into 3 consecutive words. */ +wordU words[3]; +/* Contains all words in appropriate order. */ +ULONGLONG allWords; +/* Holds the current processed argument number. */ +int processing_argument_number; +/* Nonzero means a IMM4 instruction. */ +int imm4flag; +/* Nonzero means the instruction's original size is + incremented (escape sequence is used). */ +int size_changed; + + +/* Print the constant expression length. */ + +static char * +print_exp_len (int size) +{ + switch (size) + { + case 4: + case 5: + case 6: + case 8: + case 14: + case 16: + return ":s"; + case 20: + case 24: + case 32: + return ":m"; + case 48: + return ":l"; + default: + return ""; + } +} + + +/* Retrieve the number of operands for the current assembled instruction. */ + +static int +get_number_of_operands (void) +{ + int i; + + for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++) + ; + + return i; +} + +/* Return the bit size for a given operand. */ + +static int +getbits (operand_type op) +{ + if (op < MAX_OPRD) + return cr16_optab[op].bit_size; + + return 0; +} + +/* Return the argument type of a given operand. */ + +static argtype +getargtype (operand_type op) +{ + if (op < MAX_OPRD) + return cr16_optab[op].arg_type; + + return nullargs; +} + +/* Given a 'CC' instruction constant operand, return its corresponding + string. This routine is used when disassembling the 'CC' instruction. */ + +static char * +getccstring (unsigned cc) +{ + return (char *) cr16_b_cond_tab[cc]; +} + + +/* Given a 'cinv' instruction constant operand, return its corresponding + string. This routine is used when disassembling the 'cinv' instruction. */ + +static char * +getcinvstring (char *str) +{ + const cinv_entry *cinv; + + for (cinv = cr16_cinvs; cinv < (cr16_cinvs + NUMCINVS); cinv++) + if (strcmp (cinv->istr, str) == 0) + return cinv->ostr; + + return ILLEGAL; +} + +/* Given the trap index in dispatch table, return its name. + This routine is used when disassembling the 'excp' instruction. */ + +static char * +gettrapstring (unsigned int index) +{ + const trap_entry *trap; + + for (trap = cr16_traps; trap < cr16_traps + NUMTRAPS; trap++) + if (trap->entry == index) + return trap->name; + + return ILLEGAL; +} + +/* Given a register enum value, retrieve its name. */ + +static char * +getregname (reg r) +{ + const reg_entry *reg = cr16_regtab + r; + + if (reg->type != CR16_R_REGTYPE) + return ILLEGAL; + + return reg->name; +} + +/* Given a register pair enum value, retrieve its name. */ + +static char * +getregpname (reg r) +{ + const reg_entry *reg = cr16_regptab + r; + + if (reg->type != CR16_RP_REGTYPE) + return ILLEGAL; + + return reg->name; +} + +/* Given a index register pair enum value, retrieve its name. */ + +static char * +getidxregpname (reg r) +{ + const reg_entry *reg; + + switch (r) + { + case 0: r = 0; break; + case 1: r = 2; break; + case 2: r = 4; break; + case 3: r = 6; break; + case 4: r = 8; break; + case 5: r = 10; break; + case 6: r = 3; break; + case 7: r = 5; break; + default: + break; + } + + reg = cr16_regptab + r; + + if (reg->type != CR16_RP_REGTYPE) + return ILLEGAL; + + return reg->name; +} + +/* Getting a processor register name. */ + +static char * +getprocregname (int index) +{ + const reg_entry *r; + + for (r = cr16_pregtab; r < cr16_pregtab + NUMPREGS; r++) + if (r->image == index) + return r->name; + + return "ILLEGAL REGISTER"; +} + +/* Getting a processor register name - 32 bit size. */ + +static char * +getprocpregname (int index) +{ + const reg_entry *r; + + for (r = cr16_pregptab; r < cr16_pregptab + NUMPREGPS; r++) + if (r->image == index) + return r->name; + + return "ILLEGAL REGISTER"; +} + +/* START and END are relating 'allWords' struct, which is 48 bits size. + + START|--------|END + +---------+---------+---------+---------+ + | | V | A | L | + +---------+---------+---------+---------+ + 0 16 32 48 + words [0] [1] [2] */ + +static parameter +makelongparameter (ULONGLONG val, int start, int end) +{ + parameter p; + + p.val = (dwordU) EXTRACT (val, 48 - end, end - start); + p.nbits = end - start; + return p; +} + +/* Build a mask of the instruction's 'constant' opcode, + based on the instruction's printing flags. */ + +static unsigned long +build_mask (void) +{ + unsigned long mask = SBM (instruction->match_bits); + return mask; +} + +/* Search for a matching opcode. Return 1 for success, 0 for failure. */ + +static int +match_opcode (void) +{ + unsigned long mask; + /* The instruction 'constant' opcode doewsn't exceed 32 bits. */ + unsigned long doubleWord = words[1] + (words[0] << 16); + + /* Start searching from end of instruction table. */ + instruction = &cr16_instruction[NUMOPCODES - 2]; + + /* Loop over instruction table until a full match is found. */ + while (instruction >= cr16_instruction) + { + mask = build_mask (); + if ((doubleWord & mask) == BIN (instruction->match, + instruction->match_bits)) + return 1; + else + instruction--; + } + return 0; +} + +/* Set the proper parameter value for different type of arguments. */ + +static void +make_argument (argument * a, int start_bits) +{ + int inst_bit_size; + parameter p; + + if ((instruction->size == 3) && a->size >= 16) + inst_bit_size = 48; + else + inst_bit_size = 32; + + switch (a->type) + { + case arg_r: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->r = p.val; + break; + + case arg_rp: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->rp = p.val; + break; + + case arg_pr: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->pr = p.val; + break; + + case arg_prp: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->prp = p.val; + break; + + case arg_ic: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + a->constant = p.val; + break; + + case arg_cc: + p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size), + inst_bit_size - start_bits); + + a->cc = p.val; + break; + + case arg_idxr: + if ((IS_INSN_MNEMONIC ("cbitb")) + || (IS_INSN_MNEMONIC ("sbitb")) + || (IS_INSN_MNEMONIC ("tbitb"))) + p = makelongparameter (allWords, 8, 9); + else + p = makelongparameter (allWords, 9, 10); + a->i_r = p.val; + p = makelongparameter (allWords, inst_bit_size - a->size, inst_bit_size); + a->constant = p.val; + break; + + case arg_idxrp: + p = makelongparameter (allWords, start_bits + 12, start_bits + 13); + a->i_r = p.val; + p = makelongparameter (allWords, start_bits + 13, start_bits + 16); + a->rp = p.val; + if (inst_bit_size > 32) + { + p = makelongparameter (allWords, inst_bit_size - start_bits - 12, + inst_bit_size); + a->constant = ((p.val & 0xffff) | (p.val >> 8 & 0xf0000)); + } + else if (instruction->size == 2) + { + p = makelongparameter (allWords, inst_bit_size - 22, inst_bit_size); + a->constant = (p.val & 0xf) | (((p.val >>20) & 0x3) << 4) + | ((p.val >>14 & 0x3) << 6) | (((p.val >>7) & 0x1f) <<7); + } + else if (instruction->size == 1 && a->size == 0) + a->constant = 0; + + break; + + case arg_rbase: + p = makelongparameter (allWords, inst_bit_size, inst_bit_size); + a->constant = p.val; + p = makelongparameter (allWords, inst_bit_size - (start_bits + 4), + inst_bit_size - start_bits); + a->r = p.val; + break; + + case arg_cr: + p = makelongparameter (allWords, start_bits + 12, start_bits + 16); + a->r = p.val; + p = makelongparameter (allWords, inst_bit_size - 16, inst_bit_size); + a->constant = p.val; + break; + + case arg_crp: + if (instruction->size == 1) + p = makelongparameter (allWords, 12, 16); + else + p = makelongparameter (allWords, start_bits + 12, start_bits + 16); + a->rp = p.val; + + if (inst_bit_size > 32) + { + p = makelongparameter (allWords, inst_bit_size - start_bits - 12, + inst_bit_size); + a->constant = ((p.val & 0xffff) | (p.val >> 8 & 0xf0000)); + } + else if (instruction->size == 2) + { + p = makelongparameter (allWords, inst_bit_size - 16, inst_bit_size); + a->constant = p.val; + } + else if (instruction->size == 1 && a->size != 0) + { + p = makelongparameter (allWords, 4, 8); + if (IS_INSN_MNEMONIC ("loadw") + || IS_INSN_MNEMONIC ("loadd") + || IS_INSN_MNEMONIC ("storw") + || IS_INSN_MNEMONIC ("stord")) + a->constant = (p.val * 2); + else + a->constant = p.val; + } + else /* below case for 0x0(reg pair) */ + a->constant = 0; + + break; + + case arg_c: + + if ((IS_INSN_TYPE (BRANCH_INS)) + || (IS_INSN_MNEMONIC ("bal")) + || (IS_INSN_TYPE (CSTBIT_INS)) + || (IS_INSN_TYPE (LD_STOR_INS))) + { + switch (a->size) + { + case 8 : + p = makelongparameter (allWords, 0, start_bits); + a->constant = ((((p.val&0xf00)>>4)) | (p.val&0xf)); + break; + + case 24: + if (instruction->size == 3) + { + p = makelongparameter (allWords, 16, inst_bit_size); + a->constant = ((((p.val>>16)&0xf) << 20) + | (((p.val>>24)&0xf) << 16) + | (p.val & 0xffff)); + } + else if (instruction->size == 2) + { + p = makelongparameter (allWords, 8, inst_bit_size); + a->constant = p.val; + } + break; + + default: + p = makelongparameter (allWords, inst_bit_size - (start_bits + + a->size), inst_bit_size - start_bits); + a->constant = p.val; + break; + } + } + else + { + p = makelongparameter (allWords, inst_bit_size - + (start_bits + a->size), + inst_bit_size - start_bits); + a->constant = p.val; + } + break; + + default: + break; + } +} + +/* Print a single argument. */ + +static void +print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info) +{ + LONGLONG longdisp, mask; + int sign_flag = 0; + int relative = 0; + bfd_vma number; + PTR stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + switch (a->type) + { + case arg_r: + func (stream, "%s", getregname (a->r)); + break; + + case arg_rp: + func (stream, "%s", getregpname (a->rp)); + break; + + case arg_pr: + func (stream, "%s", getprocregname (a->pr)); + break; + + case arg_prp: + func (stream, "%s", getprocpregname (a->prp)); + break; + + case arg_cc: + func (stream, "%s", getccstring (a->cc)); + func (stream, "%s", "\t"); + break; + + case arg_ic: + if (IS_INSN_MNEMONIC ("excp")) + { + func (stream, "%s", gettrapstring (a->constant)); + break; + } + else if ((IS_INSN_TYPE (ARITH_INS) || IS_INSN_TYPE (ARITH_BYTE_INS)) + && ((instruction->size == 1) && (a->constant == 9))) + func (stream, "$%d", -1); + else if (INST_HAS_REG_LIST) + func (stream, "$0x%lx", a->constant +1); + else if (IS_INSN_TYPE (SHIFT_INS)) + { + longdisp = a->constant; + mask = ((LONGLONG)1 << a->size) - 1; + if (longdisp & ((LONGLONG)1 << (a->size -1))) + { + sign_flag = 1; + longdisp = ~(longdisp) + 1; + } + a->constant = (unsigned long int) (longdisp & mask); + func (stream, "$%d", ((int)(sign_flag ? -a->constant : + a->constant))); + } + else + func (stream, "$0x%lx", a->constant); + switch (a->size) + { + case 4 : case 5 : case 6 : case 8 : + func (stream, "%s", ":s"); break; + case 16 : case 20 : func (stream, "%s", ":m"); break; + case 24 : case 32 : func (stream, "%s", ":l"); break; + default: break; + } + break; + + case arg_idxr: + if (a->i_r == 0) func (stream, "[r12]"); + if (a->i_r == 1) func (stream, "[r13]"); + func (stream, "0x%lx", a->constant); + func (stream, "%s", print_exp_len (instruction->size * 16)); + break; + + case arg_idxrp: + if (a->i_r == 0) func (stream, "[r12]"); + if (a->i_r == 1) func (stream, "[r13]"); + func (stream, "0x%lx", a->constant); + func (stream, "%s", print_exp_len (instruction->size * 16)); + func (stream, "%s", getidxregpname (a->rp)); + break; + + case arg_rbase: + func (stream, "(%s)", getregname (a->r)); + break; + + case arg_cr: + func (stream, "0x%lx", a->constant); + func (stream, "%s", print_exp_len (instruction->size * 16)); + func (stream, "(%s)", getregname (a->r)); + break; + + case arg_crp: + func (stream, "0x%lx", a->constant); + func (stream, "%s", print_exp_len (instruction->size * 16)); + func (stream, "%s", getregpname (a->rp)); + break; + + case arg_c: + /*Removed the *2 part as because implicit zeros are no more required. + Have to fix this as this needs a bit of extension in terms of branch + instructions. */ + if (IS_INSN_TYPE (BRANCH_INS) || IS_INSN_MNEMONIC ("bal")) + { + relative = 1; + longdisp = a->constant; + /* REVISIT: To sync with WinIDEA and CR16 4.1tools, the below + line commented */ + /* longdisp <<= 1; */ + mask = ((LONGLONG)1 << a->size) - 1; + switch (a->size) + { + case 8 : + { + longdisp <<= 1; + if (longdisp & ((LONGLONG)1 << a->size)) + { + sign_flag = 1; + longdisp = ~(longdisp) + 1; + } + break; + } + case 16 : + case 24 : + { + if (longdisp & 1) + { + sign_flag = 1; + longdisp = ~(longdisp) + 1; + } + break; + } + default: + func (stream, "Wrong offset used in branch/bal instruction"); + break; + } + a->constant = (unsigned long int) (longdisp & mask); + } + /* For branch Neq instruction it is 2*offset + 2. */ + else if (IS_INSN_TYPE (BRANCH_NEQ_INS)) + a->constant = 2 * a->constant + 2; + + if ((!IS_INSN_TYPE (CSTBIT_INS)) && (!IS_INSN_TYPE (LD_STOR_INS))) + (sign_flag) ? func (stream, "%s", "*-"): func (stream, "%s","*+"); + + func (stream, "%s", "0x"); + number = ((relative ? memaddr : 0) + + (sign_flag ? ((- a->constant) & 0xffffffe) : a->constant)); + + (*info->print_address_func) ((number & ((1 << 24) - 1)), info); + + func (stream, "%s", print_exp_len (instruction->size * 16)); + break; + + default: + break; + } +} + +/* Print all the arguments of CURRINSN instruction. */ + +static void +print_arguments (ins *currInsn, bfd_vma memaddr, struct disassemble_info *info) +{ + int i; + + /* For "pop/push/popret RA instruction only. */ + if ((IS_INSN_MNEMONIC ("pop") + || (IS_INSN_MNEMONIC ("popret") + || (IS_INSN_MNEMONIC ("push")))) + && currInsn->nargs == 1) + { + info->fprintf_func (info->stream, "RA"); + return; + } + + for (i = 0; i < currInsn->nargs; i++) + { + processing_argument_number = i; + + /* For "bal (ra), disp17" instruction only. */ + if ((IS_INSN_MNEMONIC ("bal")) && (i == 0) && instruction->size == 2) + { + info->fprintf_func (info->stream, "(ra),"); + continue; + } + + if ((INST_HAS_REG_LIST) && (i == 2)) + info->fprintf_func (info->stream, "RA"); + else + print_arg (&currInsn->arg[i], memaddr, info); + + if ((i != currInsn->nargs - 1) && (!IS_INSN_MNEMONIC ("b"))) + info->fprintf_func (info->stream, ","); + } +} + +/* Build the instruction's arguments. */ + +static void +make_instruction (void) +{ + int i; + unsigned int shift; + + for (i = 0; i < currInsn.nargs; i++) + { + argument a; + + memset (&a, 0, sizeof (a)); + a.type = getargtype (instruction->operands[i].op_type); + a.size = getbits (instruction->operands[i].op_type); + shift = instruction->operands[i].shift; + + make_argument (&a, shift); + currInsn.arg[i] = a; + } + + /* Calculate instruction size (in bytes). */ + currInsn.size = instruction->size + (size_changed ? 1 : 0); + /* Now in bits. */ + currInsn.size *= 2; +} + +/* Retrieve a single word from a given memory address. */ + +static wordU +get_word_at_PC (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[4]; + int status; + wordU insn = 0; + + status = info->read_memory_func (memaddr, buffer, 2, info); + + if (status == 0) + insn = (wordU) bfd_getl16 (buffer); + + return insn; +} + +/* Retrieve multiple words (3) from a given memory address. */ + +static void +get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info) +{ + int i; + bfd_vma mem; + + for (i = 0, mem = memaddr; i < 3; i++, mem += 2) + words[i] = get_word_at_PC (mem, info); + + allWords = + ((ULONGLONG) words[0] << 32) + ((unsigned long) words[1] << 16) + words[2]; +} + +/* Prints the instruction by calling print_arguments after proper matching. */ + +int +print_insn_cr16 (bfd_vma memaddr, struct disassemble_info *info) +{ + int is_decoded; /* Nonzero means instruction has a match. */ + + /* Initialize global variables. */ + imm4flag = 0; + size_changed = 0; + + /* Retrieve the encoding from current memory location. */ + get_words_at_PC (memaddr, info); + /* Find a matching opcode in table. */ + is_decoded = match_opcode (); + /* If found, print the instruction's mnemonic and arguments. */ + if (is_decoded > 0 && (words[0] << 16 || words[1]) != 0) + { + if (strneq (instruction->mnemonic, "cinv", 4)) + info->fprintf_func (info->stream,"%s", getcinvstring ((char *)instruction->mnemonic)); + else + info->fprintf_func (info->stream, "%s", instruction->mnemonic); + + if (((currInsn.nargs = get_number_of_operands ()) != 0) + && ! (IS_INSN_MNEMONIC ("b"))) + info->fprintf_func (info->stream, "\t"); + make_instruction (); + /* For push/pop/pushrtn with RA instructions. */ + if ((INST_HAS_REG_LIST) && ((words[0] >> 7) & 0x1)) + currInsn.nargs +=1; + print_arguments (&currInsn, memaddr, info); + return currInsn.size; + } + + /* No match found. */ + info->fprintf_func (info->stream,"%s ",ILLEGAL); + return 2; +} diff --git a/contrib/binutils/opcodes/cr16-opc.c b/contrib/binutils/opcodes/cr16-opc.c new file mode 100644 index 0000000..8b8bf2f --- /dev/null +++ b/contrib/binutils/opcodes/cr16-opc.c @@ -0,0 +1,611 @@ +/* cr16-opc.c -- Table of opcodes for the CR16 processor. + Copyright 2007 Free Software Foundation, Inc. + Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com) + + This file is part of GAS, GDB and the GNU binutils. + + GAS, GDB, and GNU binutils is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2, or (at your + option) any later version. + + GAS, GDB, and GNU binutils are distributed in the hope that they will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include <stdio.h> +#include "libiberty.h" +#include "symcat.h" +#include "opcode/cr16.h" + +const inst cr16_instruction[] = +{ +/* Create an arithmetic instruction - INST[bw]. */ +#define ARITH_BYTE_INST(NAME, OPC, OP1) \ + /* opc8 imm4 r */ \ + {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{uimm4_1,20}, {regr,16}}}, \ + /* opc8 imm16 r */ \ + {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}, \ + /* opc8 r r */ \ + {NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} + +/* for Logincal operations, allow unsinged imm16 also */ +#define ARITH1_BYTE_INST(NAME, OPC, OP1) \ + /* opc8 imm16 r */ \ + {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}} + + + ARITH_BYTE_INST ("andb", 0x20, uimm16), + ARITH1_BYTE_INST ("andb", 0x20, imm16), + ARITH_BYTE_INST ("andw", 0x22, uimm16), + ARITH1_BYTE_INST ("andw", 0x22, imm16), + + ARITH_BYTE_INST ("orb", 0x24, uimm16), + ARITH1_BYTE_INST ("orb", 0x24, imm16), + ARITH_BYTE_INST ("orw", 0x26, uimm16), + ARITH1_BYTE_INST ("orw", 0x26, imm16), + + ARITH_BYTE_INST ("xorb", 0x28, uimm16), + ARITH1_BYTE_INST ("xorb", 0x28, imm16), + ARITH_BYTE_INST ("xorw", 0x2A, uimm16), + ARITH1_BYTE_INST ("xorw", 0x2A, imm16), + + ARITH_BYTE_INST ("addub", 0x2C, imm16), + ARITH_BYTE_INST ("adduw", 0x2E, imm16), + ARITH_BYTE_INST ("addb", 0x30, imm16), + ARITH_BYTE_INST ("addw", 0x32, imm16), + ARITH_BYTE_INST ("addcb", 0x34, imm16), + ARITH_BYTE_INST ("addcw", 0x36, imm16), + + ARITH_BYTE_INST ("subb", 0x38, imm16), + ARITH_BYTE_INST ("subw", 0x3A, imm16), + ARITH_BYTE_INST ("subcb", 0x3C, imm16), + ARITH_BYTE_INST ("subcw", 0x3E, imm16), + + ARITH_BYTE_INST ("cmpb", 0x50, imm16), + ARITH_BYTE_INST ("cmpw", 0x52, imm16), + + ARITH_BYTE_INST ("movb", 0x58, imm16), + ARITH_BYTE_INST ("movw", 0x5A, imm16), + + ARITH_BYTE_INST ("mulb", 0x64, imm16), + ARITH_BYTE_INST ("mulw", 0x66, imm16), + +#define ARITH_BYTE_INST1(NAME, OPC) \ + /* opc8 r r */ \ + {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}} + + ARITH_BYTE_INST1 ("movxb", 0x5C), + ARITH_BYTE_INST1 ("movzb", 0x5D), + ARITH_BYTE_INST1 ("mulsb", 0x0B), + +#define ARITH_BYTE_INST2(NAME, OPC) \ + /* opc8 r rp */ \ + {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regp,16}}} + + ARITH_BYTE_INST2 ("movxw", 0x5E), + ARITH_BYTE_INST2 ("movzw", 0x5F), + ARITH_BYTE_INST2 ("mulsw", 0x62), + ARITH_BYTE_INST2 ("muluw", 0x63), + +/* Create an arithmetic instruction - INST[d]- with 3 types. */ +#define ARITH_INST_D(NAME, OPC) \ + /* opc8 imm4 rp */ \ + {NAME, 1, OPC, 24, ARITH_INS, {{uimm4_1,20}, {regp,16}}}, \ + /* opc8 imm16 rp */ \ + {NAME, 2, (OPC<<4)+0xB, 20, ARITH_INS, {{imm16,0}, {regp,16}}}, \ + /* opc8 rp rp */ \ + {NAME, 1, OPC+1, 24, ARITH_INS, {{regp,20}, {regp,16}}} + +/* Create an arithmetic instruction - INST[d]-20 bit types. */ +#define ARITH_INST20(NAME, OPC) \ + /* opc8 uimm20 rp */ \ + {NAME, 2, OPC, 24, ARITH_INS, {{uimm20,0}, {regp,20}}} + +/* Create an arithmetic instruction - INST[d]-32 bit types. */ +#define ARITH_INST32(NAME, OPC, OP1) \ + /* opc12 imm32 rp */ \ + {NAME, 3, OPC, 20, ARITH_INS, {{OP1,0}, {regp,16}}} + +/* Create an arithmetic instruction - INST[d]-32bit types(reg pairs).*/ +#define ARITH_INST32RP(NAME, OPC) \ + /* opc24 rp rp */ \ + {NAME, 2, OPC, 12, ARITH_INS, {{regp,4}, {regp,0}}} + + ARITH_INST_D ("movd", 0x54), + ARITH_INST20 ("movd", 0x05), + ARITH_INST32 ("movd", 0x007, imm32), + ARITH_INST_D ("addd", 0x60), + ARITH_INST20 ("addd", 0x04), + ARITH_INST32 ("addd", 0x002, imm32), + ARITH_INST32 ("subd", 0x003, imm32), + ARITH_INST32RP ("subd", 0x0014C), + ARITH_INST_D ("cmpd", 0x56), + ARITH_INST32 ("cmpd", 0x009, imm32), + ARITH_INST32 ("andd", 0x004, uimm32), + ARITH_INST32RP ("andd", 0x0014B), + ARITH_INST32 ("ord", 0x005, uimm32), + ARITH_INST32RP ("ord", 0x00149), + ARITH_INST32 ("xord", 0x006, uimm32), + ARITH_INST32RP ("xord", 0x0014A), + +/* Create a shift instruction. */ +#define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ + /* opc imm r */ \ + {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ + /* opc imm r */ \ + {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\ + /* opc r r */ \ + {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} + + SHIFT_INST_A("ashub", 0x80, 0x41, 23, imm4, regr), + SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp), + SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr), + +#define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \ + /* opc imm r */ \ + {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \ + /* opc r r */ \ + {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}} + + SHIFT_INST_L("lshb", 0x13, 0x44, 23, imm4, regr), + SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp), + SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr), + +/* Create a conditional branch instruction. */ +#define BRANCH_INST(NAME, OPC) \ + /* opc4 c4 dispe9 */ \ + {NAME, 1, OPC, 28, BRANCH_INS, {{cc,20}, {dispe9,16}}}, \ + /* opc4 c4 disps17 */ \ + {NAME, 2, ((OPC<<4)+0x8), 24, BRANCH_INS, {{cc,20}, {disps17,0}}}, \ + /* opc4 c4 disps25 */ \ + {NAME, 3, (OPC<<4), 16 , BRANCH_INS, {{cc,4}, {disps25,16}}} + + BRANCH_INST ("b", 0x1), + +/* Create a 'Branch if Equal to 0' instruction. */ +#define BRANCH_NEQ_INST(NAME, OPC) \ + /* opc8 disps5 r */ \ + {NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {disps5,20}}} + + BRANCH_NEQ_INST ("beq0b", 0x0C), + BRANCH_NEQ_INST ("bne0b", 0x0D), + BRANCH_NEQ_INST ("beq0w", 0x0E), + BRANCH_NEQ_INST ("bne0w", 0x0F), + + +/* Create an instruction using a single register operand. */ +#define REG1_INST(NAME, OPC) \ + /* opc8 c4 r */ \ + {NAME, 1, OPC, 20, NO_TYPE_INS, {{regr,16}}} + +#define REGP1_INST(NAME, OPC) \ + /* opc8 c4 r */ \ + {NAME, 1, OPC, 20, NO_TYPE_INS, {{regp,16}}} + +/* Same as REG1_INST, with additional FLAGS. */ +#define REG1_FLAG_INST(NAME, OPC, FLAGS) \ + /* opc8 c4 r */ \ + {NAME, 1, OPC, 20, NO_TYPE_INS | FLAGS, {{regp,16}}} + + /* JCond instructions */ + REGP1_INST ("jeq", 0x0A0), + REGP1_INST ("jne", 0x0A1), + REGP1_INST ("jcs", 0x0A2), + REGP1_INST ("jcc", 0x0A3), + REGP1_INST ("jhi", 0x0A4), + REGP1_INST ("jls", 0x0A5), + REGP1_INST ("jgt", 0x0A6), + REGP1_INST ("jle", 0x0A7), + REGP1_INST ("jfs", 0x0A8), + REGP1_INST ("jfc", 0x0A9), + REGP1_INST ("jlo", 0x0AA), + REGP1_INST ("jhs", 0x0AB), + REGP1_INST ("jlt", 0x0AC), + REGP1_INST ("jge", 0x0AD), + REGP1_INST ("jump", 0x0AE), + REGP1_INST ("jusr", 0x0AF), + + /* SCond instructions */ + REG1_INST ("seq", 0x080), + REG1_INST ("sne", 0x081), + REG1_INST ("scs", 0x082), + REG1_INST ("scc", 0x083), + REG1_INST ("shi", 0x084), + REG1_INST ("sls", 0x085), + REG1_INST ("sgt", 0x086), + REG1_INST ("sle", 0x087), + REG1_INST ("sfs", 0x088), + REG1_INST ("sfc", 0x089), + REG1_INST ("slo", 0x08A), + REG1_INST ("shs", 0x08B), + REG1_INST ("slt", 0x08C), + REG1_INST ("sge", 0x08D), + + +/* Create an instruction using two register operands. */ +#define REG3_INST(NAME, OPC) \ + /* opc24 r r rp */ \ + {NAME, 2, OPC, 12, NO_TYPE_INS, {{regr,4}, {regr,0}, {regp,8}}} + + /* MULTIPLY INSTRUCTIONS */ + REG3_INST ("macqw", 0x0014d), + REG3_INST ("macuw", 0x0014e), + REG3_INST ("macsw", 0x0014f), + +/* Create a branch instruction. */ +#define BR_INST(NAME, OPC) \ + /* opc12 ra disps25 */ \ + {NAME, 2, OPC, 24, NO_TYPE_INS, {{rra,0}, {disps25,0}}} + +#define BR_INST_RP(NAME, OPC) \ + /* opc8 rp disps25 */ \ + {NAME, 3, OPC, 12, NO_TYPE_INS, {{regp,4}, {disps25,16}}} + + BR_INST ("bal", 0xC0), + BR_INST_RP ("bal", 0x00102), + +#define REGPP2_INST(NAME, OPC) \ + /* opc16 rp rp */ \ + {NAME, 2, OPC, 12, NO_TYPE_INS, {{regp,0}, {regp,4}}} + /* Jump and link instructions. */ + REGP1_INST ("jal",0x00D), + REGPP2_INST ("jal",0x00148), + + +/* Instructions including a register list (opcode is represented as a mask). */ +#define REGLIST_INST(NAME, OPC, TYPE) \ + /* opc7 r count3 RA */ \ + {NAME,1, (OPC<<1)+1, 23, TYPE, {{uimm3_1,20},{regr,16},{regr,0}}}, \ + /* opc8 r count3 */ \ + {NAME, 1, OPC, 24, TYPE, {{uimm3_1,20}, {regr,16}}}, \ + /* opc12 RA */ \ + {NAME, 1, (OPC<<8)+0x1E, 16, TYPE, {{regr,0}}} + + REGLIST_INST ("push", 0x01, (NO_TYPE_INS | REG_LIST)), + REGLIST_INST ("pop", 0x02, (NO_TYPE_INS | REG_LIST)), + REGLIST_INST ("popret", 0x03, (NO_TYPE_INS | REG_LIST)), + + {"loadm", 1, 0x14, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, + {"loadmp", 1, 0x15, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, + {"storm", 1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, + {"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}}, + + /* Processor Regsiter Manipulation instructions */ + /* opc16 reg, preg */ + {"lpr", 2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}}, + /* opc16 regp, pregp */ + {"lprd", 2, 0x00141, 12, NO_TYPE_INS, {{regp,0}, {pregrp,4}}}, + /* opc16 preg, reg */ + {"spr", 2, 0x00142, 12, NO_TYPE_INS, {{pregr,4}, {regr,0}}}, + /* opc16 pregp, regp */ + {"sprd", 2, 0x00143, 12, NO_TYPE_INS, {{pregrp,4}, {regp,0}}}, + + /* Miscellaneous. */ + /* opc12 ui4 */ + {"excp", 1, 0x00C, 20, NO_TYPE_INS, {{uimm4,16}}}, + +/* Create a bit-b instruction. */ +#define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \ + /* opcNN iN abs20 */ \ + {NAME, 2, (OPC3+1), 23, CSTBIT_INS, {{OP,20},{abs20,0}}}, \ + /* opcNN iN abs24 */ \ + {NAME, 3, (OPC2+3), 12, CSTBIT_INS, {{OP,4},{abs24,16}}}, \ + /* opcNN iN (Rindex)abs20 */ \ + {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}}, \ + /* opcNN iN (prp) disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \ + /* opcNN iN disps20(Rbase) */ \ + {NAME, 3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}}, \ + /* opcNN iN (rp) disps0(RPbase) */ \ + {NAME, 1, OPC3-2, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \ + /* opcNN iN (rp) disps16(RPBase) */ \ + {NAME, 2, OPC3, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}}, \ + /* opcNN iN (rp) disps20(RPBase) */ \ + {NAME, 3, (OPC2+1), 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \ + /* opcNN iN rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, (OPC2+2), 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}} + + CSTBIT_INST_B ("cbitb", uimm3, 0x68, 0x00104, 0xD6, 0x1AA), + CSTBIT_INST_B ("sbitb", uimm3, 0x70, 0x00108, 0xE6, 0x1CA), + CSTBIT_INST_B ("tbitb", uimm3, 0x78, 0x0010C, 0xF6, 0x1EA), + +/* Create a bit-w instruction. */ +#define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \ + /* opcNN iN abs20 */ \ + {NAME, 2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}}, \ + /* opcNN iN abs24 */ \ + {NAME, 3, OPC2+3, 12, CSTBIT_INS, {{OP,4},{abs24,16}}}, \ + /* opcNN iN (Rindex)abs20 */ \ + {NAME, 2, OPC3, 25, CSTBIT_INS, {{OP,20}, {rindex8_abs20,0}}}, \ + /* opcNN iN (prp) disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \ + /* opcNN iN disps20(Rbase) */ \ + {NAME, 3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}}, \ + /* opcNN iN (rp) disps0(RPbase) */ \ + {NAME, 1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \ + /* opcNN iN (rp) disps16(RPBase) */ \ + {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}}, \ + /* opcNN iN (rp) disps20(RPBase) */ \ + {NAME, 3, OPC2+1, 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \ + /* opcNN iN rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, OPC2+2, 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}} + + CSTBIT_INST_W ("cbitw", uimm4, 0x69, 0x00114, 0x36, 0x1AB), + CSTBIT_INST_W ("sbitw", uimm4, 0x71, 0x00118, 0x3A, 0x1CB), + CSTBIT_INST_W ("tbitw", uimm4, 0x79, 0x0011C, 0x3E, 0x1EB), + + /* tbit cnt */ + {"tbit", 1, 0x06, 24, CSTBIT_INS, {{uimm4,20}, {regr,16}}}, + /* tbit reg reg */ + {"tbit", 1, 0x07, 24, CSTBIT_INS, {{regr,20}, {regr,16}}}, + + +/* Load instructions (from memory to register). */ +#define LD_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_S, OP_D) \ + /* opc8 reg abs20 */ \ + {NAME, 2, OPC3, 24, LD_STOR_INS, {{abs20,0}, {OP_D,20}}}, \ + /* opc20 reg abs24 */ \ + {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{abs24,16}, {OP_D,4}}}, \ + /* opc7 reg rindex8_abs20 */ \ + {NAME, 2, OPC5, 25, LD_STOR_INS, {{rindex8_abs20,0}, {OP_D,20}}}, \ + /* opc4 reg disps4(RPbase) */ \ + {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,24}, {OP_D,20}}}, \ + /* opcNN reg disps0(RPbase) */ \ + {NAME, 1, OPC2, 24, LD_STOR_INS, {{rpindex_disps0,0}, {OP_D,20}}}, \ + /* opc reg disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, LD_STOR_INS, {{rpindex_disps14,0}, {OP_D,20}}}, \ + /* opc reg -disps20(Rbase) */ \ + {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{rbase_dispe20,16}, {OP_D,4}}}, \ + /* opc reg disps20(Rbase) */ \ + {NAME, 3, OPC1, 12, LD_STOR_INS, {{rbase_disps20,16}, {OP_D,4}}}, \ + /* opc reg (rp) disps16(RPbase) */ \ + {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{rpbase_disps16,0}, {OP_D,20}}}, \ + /* opc16 reg (rp) disps20(RPbase) */ \ + {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{rpbase_disps20,16}, {OP_D,4}}}, \ + /* op reg (rp) -disps20(RPbase) */ \ + {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{rpbase_dispe20,16}, {OP_D,4}}}, \ + /* opc reg rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, (OPC1+2), 12, LD_STOR_INS, {{rpindex_disps20,16}, {OP_D,4}}} + + LD_REG_INST ("loadb", 0x00124, 0xBE, 0x88, 0x219, 0x45, rpbase_disps4, regr), + LD_REG_INST ("loadd", 0x00128, 0xAE, 0x87, 0x21A, 0x46, rpbase_dispe4, regp), + LD_REG_INST ("loadw", 0x0012C, 0x9E, 0x89, 0x21B, 0x47, rpbase_dispe4, regr), + +/* Store instructions (from reg to memory). */ +#define ST_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_D, OP_S) \ + /* opc8 reg abs20 */ \ + {NAME, 2, OPC3, 24, LD_STOR_INS, {{OP_S,20}, {abs20,0}}}, \ + /* opc20 reg abs24 */ \ + {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{OP_S,4}, {abs24,16}}}, \ + /* opc7 reg rindex8_abs20 */ \ + {NAME, 2, OPC5, 25, LD_STOR_INS, {{OP_S,20}, {rindex8_abs20,0}}}, \ + /* opc4 reg disps4(RPbase) */ \ + {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,20}, {OP_D,24}}}, \ + /* opcNN reg disps0(RPbase) */ \ + {NAME, 1, OPC2, 24, LD_STOR_INS, {{OP_S,20}, {rpindex_disps0,0}}}, \ + /* opc reg disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, LD_STOR_INS, {{OP_S,20}, {rpindex_disps14,0}}}, \ + /* opc reg -disps20(Rbase) */ \ + {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{OP_S,4}, {rbase_dispe20,16}}}, \ + /* opc reg disps20(Rbase) */ \ + {NAME, 3, OPC1, 12, LD_STOR_INS, {{OP_S,4}, {rbase_disps20,16}}}, \ + /* opc reg disps16(RPbase) */ \ + {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{OP_S,20}, {rpbase_disps16,0}}}, \ + /* opc16 reg disps20(RPbase) */ \ + {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_disps20,16}}}, \ + /* op reg (rp) -disps20(RPbase) */ \ + {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_dispe20,16}}}, \ + /* opc reg rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, OPC1+2, 12, LD_STOR_INS, {{OP_S,4}, {rpindex_disps20,16}}} + + +/* Store instructions (from imm to memory). */ +#define ST_IMM_INST(NAME, OPC1, OPC2, OPC3, OPC4) \ + /* opcNN iN abs20 */ \ + {NAME, 2, OPC1, 24, LD_STOR_INS, {{uimm4,20},{abs20,0}}}, \ + /* opcNN iN abs24 */ \ + {NAME, 3, OPC2+3, 12, LD_STOR_INS, {{uimm4,4},{abs24,16}}}, \ + /* opcNN iN (Rindex)abs20 */ \ + {NAME, 2, OPC3, 25, LD_STOR_INS, {{uimm4,20}, {rindex8_abs20,0}}}, \ + /* opcNN iN (prp) disps14(RPbase) */ \ + {NAME, 2, OPC4, 22, LD_STOR_INS, {{uimm4,4},{rpindex_disps14,0}}}, \ + /* opcNN iN (rp) disps0(RPbase) */ \ + {NAME, 1, OPC1+1, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps0,16}}}, \ + /* opcNN iN disps20(Rbase) */ \ + {NAME, 3, OPC2, 12, LD_STOR_INS, {{uimm4,4}, {rbase_disps20,16}}}, \ + /* opcNN iN (rp) disps16(RPBase) */ \ + {NAME, 2, OPC1+2, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps16,0}}}, \ + /* opcNN iN (rp) disps20(RPBase) */ \ + {NAME, 3, OPC2+1, 12, LD_STOR_INS, {{uimm4,4}, {rpbase_disps20,16}}}, \ + /* opcNN iN rrp (Rindex)disps20(RPbase) */ \ + {NAME, 3, OPC2+2, 12, LD_STOR_INS, {{uimm4,4}, {rpindex_disps20,16}}} + + ST_REG_INST ("storb", 0x00134, 0xFE, 0xC8, 0x319, 0x65, rpbase_disps4, regr), + ST_IMM_INST ("storb", 0x81, 0x00120, 0x42, 0x218), + ST_REG_INST ("stord", 0x00138, 0xEE, 0xC7, 0x31A, 0x66, rpbase_dispe4, regp), + ST_REG_INST ("storw", 0x0013C, 0xDE, 0xC9, 0x31B, 0x67, rpbase_dispe4, regr), + ST_IMM_INST ("storw", 0xC1, 0x00130, 0x62, 0x318), + +/* Create instruction with no operands. */ +#define NO_OP_INST(NAME, OPC) \ + /* opc16 */ \ + {NAME, 1, OPC, 16, 0, {{0, 0}}} + + NO_OP_INST ("cinv[i]", 0x000A), + NO_OP_INST ("cinv[i,u]", 0x000B), + NO_OP_INST ("cinv[d]", 0x000C), + NO_OP_INST ("cinv[d,u]", 0x000D), + NO_OP_INST ("cinv[d,i]", 0x000E), + NO_OP_INST ("cinv[d,i,u]", 0x000F), + NO_OP_INST ("nop", 0x2C00), + NO_OP_INST ("retx", 0x0003), + NO_OP_INST ("di", 0x0004), + NO_OP_INST ("ei", 0x0005), + NO_OP_INST ("wait", 0x0006), + NO_OP_INST ("eiwait", 0x0007), + + {NULL, 0, 0, 0, 0, {{0, 0}}} +}; + +const unsigned int cr16_num_opcodes = ARRAY_SIZE (cr16_instruction); + +/* Macro to build a reg_entry, which have an opcode image : + For example : + REG(u4, 0x84, CR16_U_REGTYPE) + is interpreted as : + {"u4", u4, 0x84, CR16_U_REGTYPE} */ +#define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE} + +#define REGP(NAME, BNAME, N, TYPE) {STRINGX(NAME), {BNAME}, N, TYPE} + +const reg_entry cr16_regtab[] = +{ /* Build a general purpose register r<N>. */ +#define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE) + + REG_R(0), REG_R(1), REG_R(2), REG_R(3), + REG_R(4), REG_R(5), REG_R(6), REG_R(7), + REG_R(8), REG_R(9), REG_R(10), REG_R(11), + REG_R(12), REG_R(13), REG_R(14), REG_R(15), + REG(r12_L, 12, CR16_R_REGTYPE), + REG(r13_L, 13, CR16_R_REGTYPE), + REG(ra, 0xe, CR16_R_REGTYPE), + REG(sp, 0xf, CR16_R_REGTYPE), + REG(sp_L, 0xf, CR16_R_REGTYPE), + REG(RA, 0xe, CR16_R_REGTYPE), +}; + +const reg_entry cr16_regptab[] = +{ /* Build a general purpose register r<N>. */ + +#define REG_RP(M,N) REGP((CONCAT2(r,M),CONCAT2(r,N)), CONCAT2(r,N), N, CR16_RP_REGTYPE) + + REG_RP(1,0), REG_RP(2,1), REG_RP(3,2), REG_RP(4,3), + REG_RP(5,4), REG_RP(6,5), REG_RP(7,6), REG_RP(8,7), + REG_RP(9,8), REG_RP(10,9), REG_RP(11,10), REG_RP(12,11), + REG((r12), 0xc, CR16_RP_REGTYPE), + REG((r13), 0xd, CR16_RP_REGTYPE), + //REG((r14), 0xe, CR16_RP_REGTYPE), + REG((ra), 0xe, CR16_RP_REGTYPE), + REG((sp), 0xf, CR16_RP_REGTYPE), +}; + + +const unsigned int cr16_num_regs = ARRAY_SIZE (cr16_regtab) ; +const unsigned int cr16_num_regps = ARRAY_SIZE (cr16_regptab) ; + +const reg_entry cr16_pregtab[] = +{ +/* Build a processor register. */ + REG(dbs, 0x0, CR16_P_REGTYPE), + REG(dsr, 0x1, CR16_P_REGTYPE), + REG(dcrl, 0x2, CR16_P_REGTYPE), + REG(dcrh, 0x3, CR16_P_REGTYPE), + REG(car0l, 0x4, CR16_P_REGTYPE), + REG(car0h, 0x5, CR16_P_REGTYPE), + REG(car1l, 0x6, CR16_P_REGTYPE), + REG(car1h, 0x7, CR16_P_REGTYPE), + REG(cfg, 0x8, CR16_P_REGTYPE), + REG(psr, 0x9, CR16_P_REGTYPE), + REG(intbasel, 0xa, CR16_P_REGTYPE), + REG(intbaseh, 0xb, CR16_P_REGTYPE), + REG(ispl, 0xc, CR16_P_REGTYPE), + REG(isph, 0xd, CR16_P_REGTYPE), + REG(uspl, 0xe, CR16_P_REGTYPE), + REG(usph, 0xf, CR16_P_REGTYPE), +}; + +const reg_entry cr16_pregptab[] = +{ + REG(dbs, 0, CR16_P_REGTYPE), + REG(dsr, 1, CR16_P_REGTYPE), + REG(dcr, 2, CR16_P_REGTYPE), + REG(car0, 4, CR16_P_REGTYPE), + REG(car1, 6, CR16_P_REGTYPE), + REG(cfg, 8, CR16_P_REGTYPE), + REG(psr, 9, CR16_P_REGTYPE), + REG(intbase, 10, CR16_P_REGTYPE), + REG(isp, 12, CR16_P_REGTYPE), + REG(usp, 14, CR16_P_REGTYPE), +}; + +const unsigned int cr16_num_pregs = ARRAY_SIZE (cr16_pregtab); +const unsigned int cr16_num_pregps = ARRAY_SIZE (cr16_pregptab); + +const char *cr16_b_cond_tab[]= +{ + "eq","ne","cs","cc","hi","ls","gt","le","fs","fc", + "lo","hs","lt","ge","r", "???" +}; + +const unsigned int cr16_num_cc = ARRAY_SIZE (cr16_b_cond_tab); + +/* CR16 operands table. */ +const operand_entry cr16_optab[] = +{ + /* Index 0 is dummy, so we can count the instruction's operands. */ + {0, nullargs, 0}, /* dummy */ + {3, arg_ic, OP_SIGNED}, /* imm3 */ + {4, arg_ic, OP_SIGNED}, /* imm4 */ + {5, arg_ic, OP_SIGNED}, /* imm5 */ + {6, arg_ic, OP_SIGNED}, /* imm6 */ + {16, arg_ic, OP_SIGNED}, /* imm16 */ + {20, arg_ic, OP_SIGNED}, /* imm20 */ + {32, arg_ic, OP_SIGNED}, /* imm32 */ + {3, arg_ic, OP_UNSIGNED}, /* uimm3 */ + {3, arg_ic, OP_UNSIGNED|OP_DEC}, /* uimm3_1 */ + {4, arg_ic, OP_UNSIGNED}, /* uimm4 */ + {4, arg_ic, OP_UNSIGNED|OP_ESC}, /* uimm4_1 */ + {5, arg_ic, OP_UNSIGNED}, /* uimm5 */ + {16, arg_ic, OP_UNSIGNED}, /* uimm16 */ + {20, arg_ic, OP_UNSIGNED}, /* uimm20 */ + {32, arg_ic, OP_UNSIGNED}, /* uimm32 */ + {5, arg_c, OP_EVEN|OP_SHIFT_DEC|OP_SIGNED}, /* disps5 */ + {16, arg_c, OP_EVEN|OP_UNSIGNED}, /* disps17 */ + {24, arg_c, OP_EVEN|OP_UNSIGNED}, /* disps25 */ + {8, arg_c, OP_EVEN|OP_UNSIGNED}, /* dispe9 */ + {20, arg_c, OP_UNSIGNED|OP_ABS20}, /* abs20 */ + {24, arg_c, OP_UNSIGNED|OP_ABS24}, /* abs24 */ + {4, arg_rp, 0}, /* rra */ + {4, arg_rbase, 0}, /* rbase */ + {20, arg_cr, OP_UNSIGNED}, /* rbase_disps20 */ + {21, arg_cr, OP_NEG}, /* rbase_dispe20 */ + {0, arg_crp, 0}, /* rpbase_disps0 */ + {4, arg_crp, OP_EVEN|OP_SHIFT|OP_UNSIGNED|OP_ESC1},/* rpbase_dispe4 */ + {4, arg_crp, OP_UNSIGNED|OP_ESC1}, /* rpbase_disps4 */ + {16, arg_crp, OP_UNSIGNED}, /* rpbase_disps16 */ + {20, arg_crp, OP_UNSIGNED}, /* rpbase_disps20 */ + {21, arg_crp, OP_NEG}, /* rpbase_dispe20 */ + {20, arg_idxr, OP_UNSIGNED}, /* rindex7_abs20 */ + {20, arg_idxr, OP_UNSIGNED}, /* rindex8_abs20 */ + {0, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps0 */ + {14, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps14 */ + {20, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps20 */ + {4, arg_r, 0}, /* regr */ + {4, arg_rp, 0}, /* reg pair */ + {4, arg_pr, 0}, /* proc reg */ + {4, arg_prp, 0}, /* 32 bit proc reg */ + {4, arg_cc, OP_UNSIGNED} /* cc - code */ +}; + + +/* CR16 traps/interrupts. */ +const trap_entry cr16_traps[] = +{ + {"svc", 5}, {"dvz", 6}, {"flg", 7}, {"bpt", 8}, {"trc", 9}, + {"und", 10}, {"iad", 12}, {"dbg",14}, {"ise",15} +}; + +const unsigned int cr16_num_traps = ARRAY_SIZE (cr16_traps); + +/* CR16 instructions that don't have arguments. */ +const char * cr16_no_op_insn[] = +{ + "cinv[i]", "cinv[i,u]", "cinv[d]", "cinv[d,u]", "cinv[d,i]", "cinv[d,i,u]", + "di", "ei", "eiwait", "nop", "retx", "wait", NULL +}; diff --git a/contrib/binutils/opcodes/disassemble.c b/contrib/binutils/opcodes/disassemble.c index 3ea4583..df98dc2 100644 --- a/contrib/binutils/opcodes/disassemble.c +++ b/contrib/binutils/opcodes/disassemble.c @@ -1,6 +1,6 @@ /* Select disassembly routine for specified architecture. Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, - 2004, 2005 Free Software Foundation, Inc. + 2004, 2005, 2006 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -25,6 +25,7 @@ #define ARCH_arm #define ARCH_avr #define ARCH_bfin +#define ARCH_cr16 #define ARCH_cris #define ARCH_crx #define ARCH_d10v @@ -50,6 +51,7 @@ #define ARCH_m88k #define ARCH_maxq #define ARCH_mcore +#define ARCH_mep #define ARCH_mips #define ARCH_mmix #define ARCH_mn10200 @@ -64,8 +66,10 @@ #define ARCH_powerpc #define ARCH_rs6000 #define ARCH_s390 +#define ARCH_score #define ARCH_sh #define ARCH_sparc +#define ARCH_spu #define ARCH_tic30 #define ARCH_tic4x #define ARCH_tic54x @@ -126,6 +130,11 @@ disassembler (abfd) disassemble = print_insn_bfin; break; #endif +#ifdef ARCH_cr16 + case bfd_arch_cr16: + disassemble = print_insn_cr16; + break; +#endif #ifdef ARCH_cris case bfd_arch_cris: disassemble = cris_get_disassembler (abfd); @@ -259,6 +268,11 @@ disassembler (abfd) disassemble = print_insn_mcore; break; #endif +#ifdef ARCH_mep + case bfd_arch_mep: + disassemble = print_insn_mep; + break; +#endif #ifdef ARCH_mips case bfd_arch_mips: if (bfd_big_endian (abfd)) @@ -326,6 +340,14 @@ disassembler (abfd) disassemble = print_insn_s390; break; #endif +#ifdef ARCH_score + case bfd_arch_score: + if (bfd_big_endian (abfd)) + disassemble = print_insn_big_score; + else + disassemble = print_insn_little_score; + break; +#endif #ifdef ARCH_sh case bfd_arch_sh: disassemble = print_insn_sh; @@ -336,6 +358,11 @@ disassembler (abfd) disassemble = print_insn_sparc; break; #endif +#ifdef ARCH_spu + case bfd_arch_spu: + disassemble = print_insn_spu; + break; +#endif #ifdef ARCH_tic30 case bfd_arch_tic30: disassemble = print_insn_tic30; @@ -433,6 +460,9 @@ disassembler_usage (stream) #ifdef ARCH_powerpc print_ppc_disassembler_options (stream); #endif +#ifdef ARCH_i386 + print_i386_disassembler_options (stream); +#endif return; } @@ -461,6 +491,12 @@ disassemble_init_for_target (struct disassemble_info * info) info->skip_zeroes = 32; break; #endif +#ifdef ARCH_mep + case bfd_arch_mep: + info->skip_zeroes = 256; + info->skip_zeroes_at_end = 0; + break; +#endif #ifdef ARCH_m32c case bfd_arch_m32c: info->endian = BFD_ENDIAN_BIG; diff --git a/contrib/binutils/opcodes/i386-dis.c b/contrib/binutils/opcodes/i386-dis.c index f73e883..e84d314 100644 --- a/contrib/binutils/opcodes/i386-dis.c +++ b/contrib/binutils/opcodes/i386-dis.c @@ -1,6 +1,6 @@ /* Print i386 instructions for GDB, the GNU debugger. Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. + 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. This file is part of GDB. @@ -34,17 +34,10 @@ #include "dis-asm.h" #include "sysdep.h" #include "opintl.h" - -#define MAXLEN 15 +#include "opcode/i386.h" #include <setjmp.h> -#ifndef UNIXWARE_COMPAT -/* Set non-zero for broken, compatible instructions. Set to zero for - non-broken opcodes. */ -#define UNIXWARE_COMPAT 1 -#endif - static int fetch_data (struct disassemble_info *, bfd_byte *); static void ckprefix (void); static const char *prefix_name (int, int); @@ -57,6 +50,7 @@ static void oappend (const char *); static void append_seg (void); static void OP_indirE (int, int); static void print_operand_value (char *, int, bfd_vma); +static void print_displacement (char *, bfd_vma); static void OP_E (int, int); static void OP_G (int, int); static bfd_vma get64 (void); @@ -80,18 +74,21 @@ static void OP_DSreg (int, int); static void OP_C (int, int); static void OP_D (int, int); static void OP_T (int, int); -static void OP_Rd (int, int); +static void OP_R (int, int); static void OP_MMX (int, int); static void OP_XMM (int, int); static void OP_EM (int, int); static void OP_EX (int, int); +static void OP_EMC (int,int); +static void OP_MXC (int,int); static void OP_MS (int, int); static void OP_XS (int, int); static void OP_M (int, int); static void OP_VMX (int, int); static void OP_0fae (int, int); static void OP_0f07 (int, int); -static void NOP_Fixup (int, int); +static void NOP_Fixup1 (int, int); +static void NOP_Fixup2 (int, int); static void OP_3DNowSuffix (int, int); static void OP_SIMD_Suffix (int, int); static void SIMD_Fixup (int, int); @@ -99,23 +96,21 @@ static void PNI_Fixup (int, int); static void SVME_Fixup (int, int); static void INVLPG_Fixup (int, int); static void BadOp (void); -static void SEG_Fixup (int, int); static void VMX_Fixup (int, int); static void REP_Fixup (int, int); +static void CMPXCHG8B_Fixup (int, int); +static void XMM_Fixup (int, int); +static void CRC32_Fixup (int, int); struct dis_private { /* Points to first byte not fetched. */ bfd_byte *max_fetched; - bfd_byte the_buffer[MAXLEN]; + bfd_byte the_buffer[MAX_MNEM_SIZE]; bfd_vma insn_start; int orig_sizeflag; jmp_buf bailout; }; -/* The opcode for the fwait instruction, which we treat as a prefix - when we can. */ -#define FWAIT_OPCODE (0x9b) - enum address_mode { mode_16bit, @@ -132,10 +127,6 @@ static int prefixes; static int rex; /* Bits of REX we've already used. */ static int rex_used; -#define REX_MODE64 8 -#define REX_EXTX 4 -#define REX_EXTY 2 -#define REX_EXTZ 1 /* Mark parts used in the REX prefix. When we are testing for empty prefix (for 8bit register REX extension), just mask it out. Otherwise test for REX bit is excuse for existence of REX @@ -143,9 +134,12 @@ static int rex_used; #define USED_REX(value) \ { \ if (value) \ - rex_used |= (rex & value) ? (value) | 0x40 : 0; \ + { \ + if ((rex & value)) \ + rex_used |= (value) | REX_OPCODE; \ + } \ else \ - rex_used |= 0x40; \ + rex_used |= REX_OPCODE; \ } /* Flags for prefixes which we somehow handled when printing the @@ -180,7 +174,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) struct dis_private *priv = (struct dis_private *) info->private_data; bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); - if (addr <= priv->the_buffer + MAXLEN) + if (addr <= priv->the_buffer + MAX_MNEM_SIZE) status = (*info->read_memory_func) (start, priv->max_fetched, addr - priv->max_fetched, @@ -202,130 +196,142 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) return 1; } -#define XX NULL, 0 - -#define Eb OP_E, b_mode -#define Ev OP_E, v_mode -#define Ed OP_E, d_mode -#define Eq OP_E, q_mode -#define Edq OP_E, dq_mode -#define Edqw OP_E, dqw_mode -#define indirEv OP_indirE, stack_v_mode -#define indirEp OP_indirE, f_mode -#define stackEv OP_E, stack_v_mode -#define Em OP_E, m_mode -#define Ew OP_E, w_mode -#define Ma OP_E, v_mode -#define M OP_M, 0 /* lea, lgdt, etc. */ -#define Mp OP_M, f_mode /* 32 or 48 bit memory operand for LDS, LES etc */ -#define Gb OP_G, b_mode -#define Gv OP_G, v_mode -#define Gd OP_G, d_mode -#define Gdq OP_G, dq_mode -#define Gm OP_G, m_mode -#define Gw OP_G, w_mode -#define Rd OP_Rd, d_mode -#define Rm OP_Rd, m_mode -#define Ib OP_I, b_mode -#define sIb OP_sI, b_mode /* sign extened byte */ -#define Iv OP_I, v_mode -#define Iq OP_I, q_mode -#define Iv64 OP_I64, v_mode -#define Iw OP_I, w_mode -#define I1 OP_I, const_1_mode -#define Jb OP_J, b_mode -#define Jv OP_J, v_mode -#define Cm OP_C, m_mode -#define Dm OP_D, m_mode -#define Td OP_T, d_mode -#define Sv SEG_Fixup, v_mode - -#define RMeAX OP_REG, eAX_reg -#define RMeBX OP_REG, eBX_reg -#define RMeCX OP_REG, eCX_reg -#define RMeDX OP_REG, eDX_reg -#define RMeSP OP_REG, eSP_reg -#define RMeBP OP_REG, eBP_reg -#define RMeSI OP_REG, eSI_reg -#define RMeDI OP_REG, eDI_reg -#define RMrAX OP_REG, rAX_reg -#define RMrBX OP_REG, rBX_reg -#define RMrCX OP_REG, rCX_reg -#define RMrDX OP_REG, rDX_reg -#define RMrSP OP_REG, rSP_reg -#define RMrBP OP_REG, rBP_reg -#define RMrSI OP_REG, rSI_reg -#define RMrDI OP_REG, rDI_reg -#define RMAL OP_REG, al_reg -#define RMAL OP_REG, al_reg -#define RMCL OP_REG, cl_reg -#define RMDL OP_REG, dl_reg -#define RMBL OP_REG, bl_reg -#define RMAH OP_REG, ah_reg -#define RMCH OP_REG, ch_reg -#define RMDH OP_REG, dh_reg -#define RMBH OP_REG, bh_reg -#define RMAX OP_REG, ax_reg -#define RMDX OP_REG, dx_reg - -#define eAX OP_IMREG, eAX_reg -#define eBX OP_IMREG, eBX_reg -#define eCX OP_IMREG, eCX_reg -#define eDX OP_IMREG, eDX_reg -#define eSP OP_IMREG, eSP_reg -#define eBP OP_IMREG, eBP_reg -#define eSI OP_IMREG, eSI_reg -#define eDI OP_IMREG, eDI_reg -#define AL OP_IMREG, al_reg -#define CL OP_IMREG, cl_reg -#define DL OP_IMREG, dl_reg -#define BL OP_IMREG, bl_reg -#define AH OP_IMREG, ah_reg -#define CH OP_IMREG, ch_reg -#define DH OP_IMREG, dh_reg -#define BH OP_IMREG, bh_reg -#define AX OP_IMREG, ax_reg -#define DX OP_IMREG, dx_reg -#define indirDX OP_IMREG, indir_dx_reg - -#define Sw OP_SEG, w_mode -#define Ap OP_DIR, 0 -#define Ob OP_OFF64, b_mode -#define Ov OP_OFF64, v_mode -#define Xb OP_DSreg, eSI_reg -#define Xv OP_DSreg, eSI_reg -#define Yb OP_ESreg, eDI_reg -#define Yv OP_ESreg, eDI_reg -#define DSBX OP_DSreg, eBX_reg - -#define es OP_REG, es_reg -#define ss OP_REG, ss_reg -#define cs OP_REG, cs_reg -#define ds OP_REG, ds_reg -#define fs OP_REG, fs_reg -#define gs OP_REG, gs_reg - -#define MX OP_MMX, 0 -#define XM OP_XMM, 0 -#define EM OP_EM, v_mode -#define EX OP_EX, v_mode -#define MS OP_MS, v_mode -#define XS OP_XS, v_mode -#define VM OP_VMX, q_mode -#define OPSUF OP_3DNowSuffix, 0 -#define OPSIMD OP_SIMD_Suffix, 0 +#define XX { NULL, 0 } + +#define Eb { OP_E, b_mode } +#define Ev { OP_E, v_mode } +#define Ed { OP_E, d_mode } +#define Edq { OP_E, dq_mode } +#define Edqw { OP_E, dqw_mode } +#define Edqb { OP_E, dqb_mode } +#define Edqd { OP_E, dqd_mode } +#define indirEv { OP_indirE, stack_v_mode } +#define indirEp { OP_indirE, f_mode } +#define stackEv { OP_E, stack_v_mode } +#define Em { OP_E, m_mode } +#define Ew { OP_E, w_mode } +#define M { OP_M, 0 } /* lea, lgdt, etc. */ +#define Ma { OP_M, v_mode } +#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ +#define Mq { OP_M, q_mode } +#define Gb { OP_G, b_mode } +#define Gv { OP_G, v_mode } +#define Gd { OP_G, d_mode } +#define Gdq { OP_G, dq_mode } +#define Gm { OP_G, m_mode } +#define Gw { OP_G, w_mode } +#define Rd { OP_R, d_mode } +#define Rm { OP_R, m_mode } +#define Ib { OP_I, b_mode } +#define sIb { OP_sI, b_mode } /* sign extened byte */ +#define Iv { OP_I, v_mode } +#define Iq { OP_I, q_mode } +#define Iv64 { OP_I64, v_mode } +#define Iw { OP_I, w_mode } +#define I1 { OP_I, const_1_mode } +#define Jb { OP_J, b_mode } +#define Jv { OP_J, v_mode } +#define Cm { OP_C, m_mode } +#define Dm { OP_D, m_mode } +#define Td { OP_T, d_mode } + +#define RMeAX { OP_REG, eAX_reg } +#define RMeBX { OP_REG, eBX_reg } +#define RMeCX { OP_REG, eCX_reg } +#define RMeDX { OP_REG, eDX_reg } +#define RMeSP { OP_REG, eSP_reg } +#define RMeBP { OP_REG, eBP_reg } +#define RMeSI { OP_REG, eSI_reg } +#define RMeDI { OP_REG, eDI_reg } +#define RMrAX { OP_REG, rAX_reg } +#define RMrBX { OP_REG, rBX_reg } +#define RMrCX { OP_REG, rCX_reg } +#define RMrDX { OP_REG, rDX_reg } +#define RMrSP { OP_REG, rSP_reg } +#define RMrBP { OP_REG, rBP_reg } +#define RMrSI { OP_REG, rSI_reg } +#define RMrDI { OP_REG, rDI_reg } +#define RMAL { OP_REG, al_reg } +#define RMAL { OP_REG, al_reg } +#define RMCL { OP_REG, cl_reg } +#define RMDL { OP_REG, dl_reg } +#define RMBL { OP_REG, bl_reg } +#define RMAH { OP_REG, ah_reg } +#define RMCH { OP_REG, ch_reg } +#define RMDH { OP_REG, dh_reg } +#define RMBH { OP_REG, bh_reg } +#define RMAX { OP_REG, ax_reg } +#define RMDX { OP_REG, dx_reg } + +#define eAX { OP_IMREG, eAX_reg } +#define eBX { OP_IMREG, eBX_reg } +#define eCX { OP_IMREG, eCX_reg } +#define eDX { OP_IMREG, eDX_reg } +#define eSP { OP_IMREG, eSP_reg } +#define eBP { OP_IMREG, eBP_reg } +#define eSI { OP_IMREG, eSI_reg } +#define eDI { OP_IMREG, eDI_reg } +#define AL { OP_IMREG, al_reg } +#define CL { OP_IMREG, cl_reg } +#define DL { OP_IMREG, dl_reg } +#define BL { OP_IMREG, bl_reg } +#define AH { OP_IMREG, ah_reg } +#define CH { OP_IMREG, ch_reg } +#define DH { OP_IMREG, dh_reg } +#define BH { OP_IMREG, bh_reg } +#define AX { OP_IMREG, ax_reg } +#define DX { OP_IMREG, dx_reg } +#define zAX { OP_IMREG, z_mode_ax_reg } +#define indirDX { OP_IMREG, indir_dx_reg } + +#define Sw { OP_SEG, w_mode } +#define Sv { OP_SEG, v_mode } +#define Ap { OP_DIR, 0 } +#define Ob { OP_OFF64, b_mode } +#define Ov { OP_OFF64, v_mode } +#define Xb { OP_DSreg, eSI_reg } +#define Xv { OP_DSreg, eSI_reg } +#define Xz { OP_DSreg, eSI_reg } +#define Yb { OP_ESreg, eDI_reg } +#define Yv { OP_ESreg, eDI_reg } +#define DSBX { OP_DSreg, eBX_reg } + +#define es { OP_REG, es_reg } +#define ss { OP_REG, ss_reg } +#define cs { OP_REG, cs_reg } +#define ds { OP_REG, ds_reg } +#define fs { OP_REG, fs_reg } +#define gs { OP_REG, gs_reg } + +#define MX { OP_MMX, 0 } +#define XM { OP_XMM, 0 } +#define EM { OP_EM, v_mode } +#define EMd { OP_EM, d_mode } +#define EMq { OP_EM, q_mode } +#define EXd { OP_EX, d_mode } +#define EXq { OP_EX, q_mode } +#define EXx { OP_EX, x_mode } +#define MS { OP_MS, v_mode } +#define XS { OP_XS, v_mode } +#define EMC { OP_EMC, v_mode } +#define MXC { OP_MXC, 0 } +#define VM { OP_VMX, q_mode } +#define OPSUF { OP_3DNowSuffix, 0 } +#define OPSIMD { OP_SIMD_Suffix, 0 } +#define XMM0 { XMM_Fixup, 0 } /* Used handle "rep" prefix for string instructions. */ -#define Xbr REP_Fixup, eSI_reg -#define Xvr REP_Fixup, eSI_reg -#define Ybr REP_Fixup, eDI_reg -#define Yvr REP_Fixup, eDI_reg -#define indirDXr REP_Fixup, indir_dx_reg -#define ALr REP_Fixup, al_reg -#define eAXr REP_Fixup, eAX_reg - -#define cond_jump_flag NULL, cond_jump_mode -#define loop_jcxz_flag NULL, loop_jcxz_mode +#define Xbr { REP_Fixup, eSI_reg } +#define Xvr { REP_Fixup, eSI_reg } +#define Ybr { REP_Fixup, eDI_reg } +#define Yvr { REP_Fixup, eDI_reg } +#define Yzr { REP_Fixup, eDI_reg } +#define indirDXr { REP_Fixup, indir_dx_reg } +#define ALr { REP_Fixup, al_reg } +#define eAXr { REP_Fixup, eAX_reg } + +#define cond_jump_flag { NULL, cond_jump_mode } +#define loop_jcxz_flag { NULL, loop_jcxz_mode } /* bits in sizeflag */ #define SUFFIX_ALWAYS 4 @@ -347,6 +353,10 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define f_mode 13 /* 4- or 6-byte pointer operand */ #define const_1_mode 14 #define stack_v_mode 15 /* v_mode for stack-related opcodes. */ +#define z_mode 16 /* non-quad operand size depends on prefixes */ +#define o_mode 17 /* 16-byte operand */ +#define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */ +#define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */ #define es_reg 100 #define cs_reg 101 @@ -391,6 +401,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define rSI_reg 138 #define rDI_reg 139 +#define z_mode_ax_reg 149 #define indir_dx_reg 150 #define FLOATCODE 1 @@ -399,83 +410,154 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define X86_64_SPECIAL 4 #define IS_3BYTE_OPCODE 5 -#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0 - -#define GRP1b NULL, NULL, USE_GROUPS, NULL, 0, NULL, 0 -#define GRP1S NULL, NULL, USE_GROUPS, NULL, 1, NULL, 0 -#define GRP1Ss NULL, NULL, USE_GROUPS, NULL, 2, NULL, 0 -#define GRP2b NULL, NULL, USE_GROUPS, NULL, 3, NULL, 0 -#define GRP2S NULL, NULL, USE_GROUPS, NULL, 4, NULL, 0 -#define GRP2b_one NULL, NULL, USE_GROUPS, NULL, 5, NULL, 0 -#define GRP2S_one NULL, NULL, USE_GROUPS, NULL, 6, NULL, 0 -#define GRP2b_cl NULL, NULL, USE_GROUPS, NULL, 7, NULL, 0 -#define GRP2S_cl NULL, NULL, USE_GROUPS, NULL, 8, NULL, 0 -#define GRP3b NULL, NULL, USE_GROUPS, NULL, 9, NULL, 0 -#define GRP3S NULL, NULL, USE_GROUPS, NULL, 10, NULL, 0 -#define GRP4 NULL, NULL, USE_GROUPS, NULL, 11, NULL, 0 -#define GRP5 NULL, NULL, USE_GROUPS, NULL, 12, NULL, 0 -#define GRP6 NULL, NULL, USE_GROUPS, NULL, 13, NULL, 0 -#define GRP7 NULL, NULL, USE_GROUPS, NULL, 14, NULL, 0 -#define GRP8 NULL, NULL, USE_GROUPS, NULL, 15, NULL, 0 -#define GRP9 NULL, NULL, USE_GROUPS, NULL, 16, NULL, 0 -#define GRP10 NULL, NULL, USE_GROUPS, NULL, 17, NULL, 0 -#define GRP11 NULL, NULL, USE_GROUPS, NULL, 18, NULL, 0 -#define GRP12 NULL, NULL, USE_GROUPS, NULL, 19, NULL, 0 -#define GRP13 NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0 -#define GRP14 NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0 -#define GRPAMD NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0 -#define GRPPADLCK1 NULL, NULL, USE_GROUPS, NULL, 23, NULL, 0 -#define GRPPADLCK2 NULL, NULL, USE_GROUPS, NULL, 24, NULL, 0 - -#define PREGRP0 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 0, NULL, 0 -#define PREGRP1 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 1, NULL, 0 -#define PREGRP2 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 2, NULL, 0 -#define PREGRP3 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 3, NULL, 0 -#define PREGRP4 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 4, NULL, 0 -#define PREGRP5 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 5, NULL, 0 -#define PREGRP6 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 6, NULL, 0 -#define PREGRP7 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 7, NULL, 0 -#define PREGRP8 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 8, NULL, 0 -#define PREGRP9 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 9, NULL, 0 -#define PREGRP10 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 10, NULL, 0 -#define PREGRP11 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 11, NULL, 0 -#define PREGRP12 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 12, NULL, 0 -#define PREGRP13 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 13, NULL, 0 -#define PREGRP14 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 14, NULL, 0 -#define PREGRP15 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 15, NULL, 0 -#define PREGRP16 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 16, NULL, 0 -#define PREGRP17 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 17, NULL, 0 -#define PREGRP18 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 18, NULL, 0 -#define PREGRP19 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 19, NULL, 0 -#define PREGRP20 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 20, NULL, 0 -#define PREGRP21 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 21, NULL, 0 -#define PREGRP22 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 22, NULL, 0 -#define PREGRP23 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 23, NULL, 0 -#define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0 -#define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0 -#define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0 -#define PREGRP27 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 27, NULL, 0 -#define PREGRP28 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 28, NULL, 0 -#define PREGRP29 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 29, NULL, 0 -#define PREGRP30 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 30, NULL, 0 -#define PREGRP31 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 31, NULL, 0 -#define PREGRP32 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 32, NULL, 0 - -#define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0 - -#define THREE_BYTE_0 NULL, NULL, IS_3BYTE_OPCODE, NULL, 0, NULL, 0 -#define THREE_BYTE_1 NULL, NULL, IS_3BYTE_OPCODE, NULL, 1, NULL, 0 +#define FLOAT NULL, { { NULL, FLOATCODE } } + +#define GRP1a NULL, { { NULL, USE_GROUPS }, { NULL, 0 } } +#define GRP1b NULL, { { NULL, USE_GROUPS }, { NULL, 1 } } +#define GRP1S NULL, { { NULL, USE_GROUPS }, { NULL, 2 } } +#define GRP1Ss NULL, { { NULL, USE_GROUPS }, { NULL, 3 } } +#define GRP2b NULL, { { NULL, USE_GROUPS }, { NULL, 4 } } +#define GRP2S NULL, { { NULL, USE_GROUPS }, { NULL, 5 } } +#define GRP2b_one NULL, { { NULL, USE_GROUPS }, { NULL, 6 } } +#define GRP2S_one NULL, { { NULL, USE_GROUPS }, { NULL, 7 } } +#define GRP2b_cl NULL, { { NULL, USE_GROUPS }, { NULL, 8 } } +#define GRP2S_cl NULL, { { NULL, USE_GROUPS }, { NULL, 9 } } +#define GRP3b NULL, { { NULL, USE_GROUPS }, { NULL, 10 } } +#define GRP3S NULL, { { NULL, USE_GROUPS }, { NULL, 11 } } +#define GRP4 NULL, { { NULL, USE_GROUPS }, { NULL, 12 } } +#define GRP5 NULL, { { NULL, USE_GROUPS }, { NULL, 13 } } +#define GRP6 NULL, { { NULL, USE_GROUPS }, { NULL, 14 } } +#define GRP7 NULL, { { NULL, USE_GROUPS }, { NULL, 15 } } +#define GRP8 NULL, { { NULL, USE_GROUPS }, { NULL, 16 } } +#define GRP9 NULL, { { NULL, USE_GROUPS }, { NULL, 17 } } +#define GRP11_C6 NULL, { { NULL, USE_GROUPS }, { NULL, 18 } } +#define GRP11_C7 NULL, { { NULL, USE_GROUPS }, { NULL, 19 } } +#define GRP12 NULL, { { NULL, USE_GROUPS }, { NULL, 20 } } +#define GRP13 NULL, { { NULL, USE_GROUPS }, { NULL, 21 } } +#define GRP14 NULL, { { NULL, USE_GROUPS }, { NULL, 22 } } +#define GRP15 NULL, { { NULL, USE_GROUPS }, { NULL, 23 } } +#define GRP16 NULL, { { NULL, USE_GROUPS }, { NULL, 24 } } +#define GRPAMD NULL, { { NULL, USE_GROUPS }, { NULL, 25 } } +#define GRPPADLCK1 NULL, { { NULL, USE_GROUPS }, { NULL, 26 } } +#define GRPPADLCK2 NULL, { { NULL, USE_GROUPS }, { NULL, 27 } } + +#define PREGRP0 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 0 } } +#define PREGRP1 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 1 } } +#define PREGRP2 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 2 } } +#define PREGRP3 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 3 } } +#define PREGRP4 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 4 } } +#define PREGRP5 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 5 } } +#define PREGRP6 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 6 } } +#define PREGRP7 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 7 } } +#define PREGRP8 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 8 } } +#define PREGRP9 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 9 } } +#define PREGRP10 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 10 } } +#define PREGRP11 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 11 } } +#define PREGRP12 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 12 } } +#define PREGRP13 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 13 } } +#define PREGRP14 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 14 } } +#define PREGRP15 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 15 } } +#define PREGRP16 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 16 } } +#define PREGRP17 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 17 } } +#define PREGRP18 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 18 } } +#define PREGRP19 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 19 } } +#define PREGRP20 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 20 } } +#define PREGRP21 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 21 } } +#define PREGRP22 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 22 } } +#define PREGRP23 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 23 } } +#define PREGRP24 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 24 } } +#define PREGRP25 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 25 } } +#define PREGRP26 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 26 } } +#define PREGRP27 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 27 } } +#define PREGRP28 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 28 } } +#define PREGRP29 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 29 } } +#define PREGRP30 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 30 } } +#define PREGRP31 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 31 } } +#define PREGRP32 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 32 } } +#define PREGRP33 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 33 } } +#define PREGRP34 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 34 } } +#define PREGRP35 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 35 } } +#define PREGRP36 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 36 } } +#define PREGRP37 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 37 } } +#define PREGRP38 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 38 } } +#define PREGRP39 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 39 } } +#define PREGRP40 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 40 } } +#define PREGRP41 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 41 } } +#define PREGRP42 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 42 } } +#define PREGRP43 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 43 } } +#define PREGRP44 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 44 } } +#define PREGRP45 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 45 } } +#define PREGRP46 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 46 } } +#define PREGRP47 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 47 } } +#define PREGRP48 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 48 } } +#define PREGRP49 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 49 } } +#define PREGRP50 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 50 } } +#define PREGRP51 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 51 } } +#define PREGRP52 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 52 } } +#define PREGRP53 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 53 } } +#define PREGRP54 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 54 } } +#define PREGRP55 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 55 } } +#define PREGRP56 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 56 } } +#define PREGRP57 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 57 } } +#define PREGRP58 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 58 } } +#define PREGRP59 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 59 } } +#define PREGRP60 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 60 } } +#define PREGRP61 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 61 } } +#define PREGRP62 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 62 } } +#define PREGRP63 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 63 } } +#define PREGRP64 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 64 } } +#define PREGRP65 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 65 } } +#define PREGRP66 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 66 } } +#define PREGRP67 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 67 } } +#define PREGRP68 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 68 } } +#define PREGRP69 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 69 } } +#define PREGRP70 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 70 } } +#define PREGRP71 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 71 } } +#define PREGRP72 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 72 } } +#define PREGRP73 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 73 } } +#define PREGRP74 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 74 } } +#define PREGRP75 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 75 } } +#define PREGRP76 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 76 } } +#define PREGRP77 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 77 } } +#define PREGRP78 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 78 } } +#define PREGRP79 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 79 } } +#define PREGRP80 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 80 } } +#define PREGRP81 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 81 } } +#define PREGRP82 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 82 } } +#define PREGRP83 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 83 } } +#define PREGRP84 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 84 } } +#define PREGRP85 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 85 } } +#define PREGRP86 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 86 } } +#define PREGRP87 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 87 } } +#define PREGRP88 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 88 } } +#define PREGRP89 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 89 } } +#define PREGRP90 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 90 } } +#define PREGRP91 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 91 } } +#define PREGRP92 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 92 } } +#define PREGRP93 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 93 } } +#define PREGRP94 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 94 } } +#define PREGRP95 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 95 } } +#define PREGRP96 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 96 } } +#define PREGRP97 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 97 } } + + +#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } } +#define X86_64_1 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 1 } } +#define X86_64_2 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 2 } } +#define X86_64_3 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 3 } } + +#define THREE_BYTE_0 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 0 } } +#define THREE_BYTE_1 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 1 } } typedef void (*op_rtn) (int bytemode, int sizeflag); struct dis386 { const char *name; - op_rtn op1; - int bytemode1; - op_rtn op2; - int bytemode2; - op_rtn op3; - int bytemode3; + struct + { + op_rtn rtn; + int bytemode; + } op[MAX_OPERANDS]; }; /* Upper case letters in the instruction names here are macros. @@ -483,25 +565,29 @@ struct dis386 { 'B' => print 'b' if suffix_always is true 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand . size prefix + 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if + . suffix_always is true 'E' => print 'e' if 32-bit form of jcxz 'F' => print 'w' or 'l' depending on address size prefix (loop insns) + 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) 'H' => print ",pt" or ",pn" branch hint 'I' => honor following macro letter even in Intel mode (implemented only . for some of the macro letters) 'J' => print 'l' + 'K' => print 'd' or 'q' if rex prefix is present. 'L' => print 'l' if suffix_always is true 'N' => print 'n' if instruction has no wait "prefix" - 'O' => print 'd', or 'o' + 'O' => print 'd' or 'o' (or 'q' in Intel mode) 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, . or suffix_always is true. print 'q' if rex prefix is present. 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always . is true - 'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode) + 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) 'S' => print 'w', 'l' or 'q' if suffix_always is true 'T' => print 'q' in 64bit mode and behave as 'P' otherwise 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise 'V' => print 'q' in 64bit mode and behave as 'S' otherwise - 'W' => print 'b' or 'w' ("w" or "de" in intel mode) + 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 'X' => print 's', 'd' depending on data16 prefix (for XMM) 'Y' => 'q' if instruction has an REX 64bit overwrite prefix 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise @@ -517,248 +603,248 @@ struct dis386 { static const struct dis386 dis386[] = { /* 00 */ - { "addB", Eb, Gb, XX }, - { "addS", Ev, Gv, XX }, - { "addB", Gb, Eb, XX }, - { "addS", Gv, Ev, XX }, - { "addB", AL, Ib, XX }, - { "addS", eAX, Iv, XX }, - { "push{T|}", es, XX, XX }, - { "pop{T|}", es, XX, XX }, + { "addB", { Eb, Gb } }, + { "addS", { Ev, Gv } }, + { "addB", { Gb, Eb } }, + { "addS", { Gv, Ev } }, + { "addB", { AL, Ib } }, + { "addS", { eAX, Iv } }, + { "push{T|}", { es } }, + { "pop{T|}", { es } }, /* 08 */ - { "orB", Eb, Gb, XX }, - { "orS", Ev, Gv, XX }, - { "orB", Gb, Eb, XX }, - { "orS", Gv, Ev, XX }, - { "orB", AL, Ib, XX }, - { "orS", eAX, Iv, XX }, - { "push{T|}", cs, XX, XX }, - { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */ + { "orB", { Eb, Gb } }, + { "orS", { Ev, Gv } }, + { "orB", { Gb, Eb } }, + { "orS", { Gv, Ev } }, + { "orB", { AL, Ib } }, + { "orS", { eAX, Iv } }, + { "push{T|}", { cs } }, + { "(bad)", { XX } }, /* 0x0f extended opcode escape */ /* 10 */ - { "adcB", Eb, Gb, XX }, - { "adcS", Ev, Gv, XX }, - { "adcB", Gb, Eb, XX }, - { "adcS", Gv, Ev, XX }, - { "adcB", AL, Ib, XX }, - { "adcS", eAX, Iv, XX }, - { "push{T|}", ss, XX, XX }, - { "pop{T|}", ss, XX, XX }, + { "adcB", { Eb, Gb } }, + { "adcS", { Ev, Gv } }, + { "adcB", { Gb, Eb } }, + { "adcS", { Gv, Ev } }, + { "adcB", { AL, Ib } }, + { "adcS", { eAX, Iv } }, + { "push{T|}", { ss } }, + { "pop{T|}", { ss } }, /* 18 */ - { "sbbB", Eb, Gb, XX }, - { "sbbS", Ev, Gv, XX }, - { "sbbB", Gb, Eb, XX }, - { "sbbS", Gv, Ev, XX }, - { "sbbB", AL, Ib, XX }, - { "sbbS", eAX, Iv, XX }, - { "push{T|}", ds, XX, XX }, - { "pop{T|}", ds, XX, XX }, + { "sbbB", { Eb, Gb } }, + { "sbbS", { Ev, Gv } }, + { "sbbB", { Gb, Eb } }, + { "sbbS", { Gv, Ev } }, + { "sbbB", { AL, Ib } }, + { "sbbS", { eAX, Iv } }, + { "push{T|}", { ds } }, + { "pop{T|}", { ds } }, /* 20 */ - { "andB", Eb, Gb, XX }, - { "andS", Ev, Gv, XX }, - { "andB", Gb, Eb, XX }, - { "andS", Gv, Ev, XX }, - { "andB", AL, Ib, XX }, - { "andS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG ES prefix */ - { "daa{|}", XX, XX, XX }, + { "andB", { Eb, Gb } }, + { "andS", { Ev, Gv } }, + { "andB", { Gb, Eb } }, + { "andS", { Gv, Ev } }, + { "andB", { AL, Ib } }, + { "andS", { eAX, Iv } }, + { "(bad)", { XX } }, /* SEG ES prefix */ + { "daa{|}", { XX } }, /* 28 */ - { "subB", Eb, Gb, XX }, - { "subS", Ev, Gv, XX }, - { "subB", Gb, Eb, XX }, - { "subS", Gv, Ev, XX }, - { "subB", AL, Ib, XX }, - { "subS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG CS prefix */ - { "das{|}", XX, XX, XX }, + { "subB", { Eb, Gb } }, + { "subS", { Ev, Gv } }, + { "subB", { Gb, Eb } }, + { "subS", { Gv, Ev } }, + { "subB", { AL, Ib } }, + { "subS", { eAX, Iv } }, + { "(bad)", { XX } }, /* SEG CS prefix */ + { "das{|}", { XX } }, /* 30 */ - { "xorB", Eb, Gb, XX }, - { "xorS", Ev, Gv, XX }, - { "xorB", Gb, Eb, XX }, - { "xorS", Gv, Ev, XX }, - { "xorB", AL, Ib, XX }, - { "xorS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG SS prefix */ - { "aaa{|}", XX, XX, XX }, + { "xorB", { Eb, Gb } }, + { "xorS", { Ev, Gv } }, + { "xorB", { Gb, Eb } }, + { "xorS", { Gv, Ev } }, + { "xorB", { AL, Ib } }, + { "xorS", { eAX, Iv } }, + { "(bad)", { XX } }, /* SEG SS prefix */ + { "aaa{|}", { XX } }, /* 38 */ - { "cmpB", Eb, Gb, XX }, - { "cmpS", Ev, Gv, XX }, - { "cmpB", Gb, Eb, XX }, - { "cmpS", Gv, Ev, XX }, - { "cmpB", AL, Ib, XX }, - { "cmpS", eAX, Iv, XX }, - { "(bad)", XX, XX, XX }, /* SEG DS prefix */ - { "aas{|}", XX, XX, XX }, + { "cmpB", { Eb, Gb } }, + { "cmpS", { Ev, Gv } }, + { "cmpB", { Gb, Eb } }, + { "cmpS", { Gv, Ev } }, + { "cmpB", { AL, Ib } }, + { "cmpS", { eAX, Iv } }, + { "(bad)", { XX } }, /* SEG DS prefix */ + { "aas{|}", { XX } }, /* 40 */ - { "inc{S|}", RMeAX, XX, XX }, - { "inc{S|}", RMeCX, XX, XX }, - { "inc{S|}", RMeDX, XX, XX }, - { "inc{S|}", RMeBX, XX, XX }, - { "inc{S|}", RMeSP, XX, XX }, - { "inc{S|}", RMeBP, XX, XX }, - { "inc{S|}", RMeSI, XX, XX }, - { "inc{S|}", RMeDI, XX, XX }, + { "inc{S|}", { RMeAX } }, + { "inc{S|}", { RMeCX } }, + { "inc{S|}", { RMeDX } }, + { "inc{S|}", { RMeBX } }, + { "inc{S|}", { RMeSP } }, + { "inc{S|}", { RMeBP } }, + { "inc{S|}", { RMeSI } }, + { "inc{S|}", { RMeDI } }, /* 48 */ - { "dec{S|}", RMeAX, XX, XX }, - { "dec{S|}", RMeCX, XX, XX }, - { "dec{S|}", RMeDX, XX, XX }, - { "dec{S|}", RMeBX, XX, XX }, - { "dec{S|}", RMeSP, XX, XX }, - { "dec{S|}", RMeBP, XX, XX }, - { "dec{S|}", RMeSI, XX, XX }, - { "dec{S|}", RMeDI, XX, XX }, + { "dec{S|}", { RMeAX } }, + { "dec{S|}", { RMeCX } }, + { "dec{S|}", { RMeDX } }, + { "dec{S|}", { RMeBX } }, + { "dec{S|}", { RMeSP } }, + { "dec{S|}", { RMeBP } }, + { "dec{S|}", { RMeSI } }, + { "dec{S|}", { RMeDI } }, /* 50 */ - { "pushV", RMrAX, XX, XX }, - { "pushV", RMrCX, XX, XX }, - { "pushV", RMrDX, XX, XX }, - { "pushV", RMrBX, XX, XX }, - { "pushV", RMrSP, XX, XX }, - { "pushV", RMrBP, XX, XX }, - { "pushV", RMrSI, XX, XX }, - { "pushV", RMrDI, XX, XX }, + { "pushV", { RMrAX } }, + { "pushV", { RMrCX } }, + { "pushV", { RMrDX } }, + { "pushV", { RMrBX } }, + { "pushV", { RMrSP } }, + { "pushV", { RMrBP } }, + { "pushV", { RMrSI } }, + { "pushV", { RMrDI } }, /* 58 */ - { "popV", RMrAX, XX, XX }, - { "popV", RMrCX, XX, XX }, - { "popV", RMrDX, XX, XX }, - { "popV", RMrBX, XX, XX }, - { "popV", RMrSP, XX, XX }, - { "popV", RMrBP, XX, XX }, - { "popV", RMrSI, XX, XX }, - { "popV", RMrDI, XX, XX }, + { "popV", { RMrAX } }, + { "popV", { RMrCX } }, + { "popV", { RMrDX } }, + { "popV", { RMrBX } }, + { "popV", { RMrSP } }, + { "popV", { RMrBP } }, + { "popV", { RMrSI } }, + { "popV", { RMrDI } }, /* 60 */ - { "pusha{P|}", XX, XX, XX }, - { "popa{P|}", XX, XX, XX }, - { "bound{S|}", Gv, Ma, XX }, { X86_64_0 }, - { "(bad)", XX, XX, XX }, /* seg fs */ - { "(bad)", XX, XX, XX }, /* seg gs */ - { "(bad)", XX, XX, XX }, /* op size prefix */ - { "(bad)", XX, XX, XX }, /* adr size prefix */ + { X86_64_1 }, + { X86_64_2 }, + { X86_64_3 }, + { "(bad)", { XX } }, /* seg fs */ + { "(bad)", { XX } }, /* seg gs */ + { "(bad)", { XX } }, /* op size prefix */ + { "(bad)", { XX } }, /* adr size prefix */ /* 68 */ - { "pushT", Iq, XX, XX }, - { "imulS", Gv, Ev, Iv }, - { "pushT", sIb, XX, XX }, - { "imulS", Gv, Ev, sIb }, - { "ins{b||b|}", Ybr, indirDX, XX }, - { "ins{R||R|}", Yvr, indirDX, XX }, - { "outs{b||b|}", indirDXr, Xb, XX }, - { "outs{R||R|}", indirDXr, Xv, XX }, + { "pushT", { Iq } }, + { "imulS", { Gv, Ev, Iv } }, + { "pushT", { sIb } }, + { "imulS", { Gv, Ev, sIb } }, + { "ins{b||b|}", { Ybr, indirDX } }, + { "ins{R||G|}", { Yzr, indirDX } }, + { "outs{b||b|}", { indirDXr, Xb } }, + { "outs{R||G|}", { indirDXr, Xz } }, /* 70 */ - { "joH", Jb, XX, cond_jump_flag }, - { "jnoH", Jb, XX, cond_jump_flag }, - { "jbH", Jb, XX, cond_jump_flag }, - { "jaeH", Jb, XX, cond_jump_flag }, - { "jeH", Jb, XX, cond_jump_flag }, - { "jneH", Jb, XX, cond_jump_flag }, - { "jbeH", Jb, XX, cond_jump_flag }, - { "jaH", Jb, XX, cond_jump_flag }, + { "joH", { Jb, XX, cond_jump_flag } }, + { "jnoH", { Jb, XX, cond_jump_flag } }, + { "jbH", { Jb, XX, cond_jump_flag } }, + { "jaeH", { Jb, XX, cond_jump_flag } }, + { "jeH", { Jb, XX, cond_jump_flag } }, + { "jneH", { Jb, XX, cond_jump_flag } }, + { "jbeH", { Jb, XX, cond_jump_flag } }, + { "jaH", { Jb, XX, cond_jump_flag } }, /* 78 */ - { "jsH", Jb, XX, cond_jump_flag }, - { "jnsH", Jb, XX, cond_jump_flag }, - { "jpH", Jb, XX, cond_jump_flag }, - { "jnpH", Jb, XX, cond_jump_flag }, - { "jlH", Jb, XX, cond_jump_flag }, - { "jgeH", Jb, XX, cond_jump_flag }, - { "jleH", Jb, XX, cond_jump_flag }, - { "jgH", Jb, XX, cond_jump_flag }, + { "jsH", { Jb, XX, cond_jump_flag } }, + { "jnsH", { Jb, XX, cond_jump_flag } }, + { "jpH", { Jb, XX, cond_jump_flag } }, + { "jnpH", { Jb, XX, cond_jump_flag } }, + { "jlH", { Jb, XX, cond_jump_flag } }, + { "jgeH", { Jb, XX, cond_jump_flag } }, + { "jleH", { Jb, XX, cond_jump_flag } }, + { "jgH", { Jb, XX, cond_jump_flag } }, /* 80 */ { GRP1b }, { GRP1S }, - { "(bad)", XX, XX, XX }, + { "(bad)", { XX } }, { GRP1Ss }, - { "testB", Eb, Gb, XX }, - { "testS", Ev, Gv, XX }, - { "xchgB", Eb, Gb, XX }, - { "xchgS", Ev, Gv, XX }, + { "testB", { Eb, Gb } }, + { "testS", { Ev, Gv } }, + { "xchgB", { Eb, Gb } }, + { "xchgS", { Ev, Gv } }, /* 88 */ - { "movB", Eb, Gb, XX }, - { "movS", Ev, Gv, XX }, - { "movB", Gb, Eb, XX }, - { "movS", Gv, Ev, XX }, - { "movQ", Sv, Sw, XX }, - { "leaS", Gv, M, XX }, - { "movQ", Sw, Sv, XX }, - { "popU", stackEv, XX, XX }, + { "movB", { Eb, Gb } }, + { "movS", { Ev, Gv } }, + { "movB", { Gb, Eb } }, + { "movS", { Gv, Ev } }, + { "movD", { Sv, Sw } }, + { "leaS", { Gv, M } }, + { "movD", { Sw, Sv } }, + { GRP1a }, /* 90 */ - { "nop", NOP_Fixup, 0, XX, XX }, - { "xchgS", RMeCX, eAX, XX }, - { "xchgS", RMeDX, eAX, XX }, - { "xchgS", RMeBX, eAX, XX }, - { "xchgS", RMeSP, eAX, XX }, - { "xchgS", RMeBP, eAX, XX }, - { "xchgS", RMeSI, eAX, XX }, - { "xchgS", RMeDI, eAX, XX }, + { PREGRP38 }, + { "xchgS", { RMeCX, eAX } }, + { "xchgS", { RMeDX, eAX } }, + { "xchgS", { RMeBX, eAX } }, + { "xchgS", { RMeSP, eAX } }, + { "xchgS", { RMeBP, eAX } }, + { "xchgS", { RMeSI, eAX } }, + { "xchgS", { RMeDI, eAX } }, /* 98 */ - { "cW{tR||tR|}", XX, XX, XX }, - { "cR{tO||tO|}", XX, XX, XX }, - { "Jcall{T|}", Ap, XX, XX }, - { "(bad)", XX, XX, XX }, /* fwait */ - { "pushfT", XX, XX, XX }, - { "popfT", XX, XX, XX }, - { "sahf{|}", XX, XX, XX }, - { "lahf{|}", XX, XX, XX }, + { "cW{t||t|}R", { XX } }, + { "cR{t||t|}O", { XX } }, + { "Jcall{T|}", { Ap } }, + { "(bad)", { XX } }, /* fwait */ + { "pushfT", { XX } }, + { "popfT", { XX } }, + { "sahf{|}", { XX } }, + { "lahf{|}", { XX } }, /* a0 */ - { "movB", AL, Ob, XX }, - { "movS", eAX, Ov, XX }, - { "movB", Ob, AL, XX }, - { "movS", Ov, eAX, XX }, - { "movs{b||b|}", Ybr, Xb, XX }, - { "movs{R||R|}", Yvr, Xv, XX }, - { "cmps{b||b|}", Xb, Yb, XX }, - { "cmps{R||R|}", Xv, Yv, XX }, + { "movB", { AL, Ob } }, + { "movS", { eAX, Ov } }, + { "movB", { Ob, AL } }, + { "movS", { Ov, eAX } }, + { "movs{b||b|}", { Ybr, Xb } }, + { "movs{R||R|}", { Yvr, Xv } }, + { "cmps{b||b|}", { Xb, Yb } }, + { "cmps{R||R|}", { Xv, Yv } }, /* a8 */ - { "testB", AL, Ib, XX }, - { "testS", eAX, Iv, XX }, - { "stosB", Ybr, AL, XX }, - { "stosS", Yvr, eAX, XX }, - { "lodsB", ALr, Xb, XX }, - { "lodsS", eAXr, Xv, XX }, - { "scasB", AL, Yb, XX }, - { "scasS", eAX, Yv, XX }, + { "testB", { AL, Ib } }, + { "testS", { eAX, Iv } }, + { "stosB", { Ybr, AL } }, + { "stosS", { Yvr, eAX } }, + { "lodsB", { ALr, Xb } }, + { "lodsS", { eAXr, Xv } }, + { "scasB", { AL, Yb } }, + { "scasS", { eAX, Yv } }, /* b0 */ - { "movB", RMAL, Ib, XX }, - { "movB", RMCL, Ib, XX }, - { "movB", RMDL, Ib, XX }, - { "movB", RMBL, Ib, XX }, - { "movB", RMAH, Ib, XX }, - { "movB", RMCH, Ib, XX }, - { "movB", RMDH, Ib, XX }, - { "movB", RMBH, Ib, XX }, + { "movB", { RMAL, Ib } }, + { "movB", { RMCL, Ib } }, + { "movB", { RMDL, Ib } }, + { "movB", { RMBL, Ib } }, + { "movB", { RMAH, Ib } }, + { "movB", { RMCH, Ib } }, + { "movB", { RMDH, Ib } }, + { "movB", { RMBH, Ib } }, /* b8 */ - { "movS", RMeAX, Iv64, XX }, - { "movS", RMeCX, Iv64, XX }, - { "movS", RMeDX, Iv64, XX }, - { "movS", RMeBX, Iv64, XX }, - { "movS", RMeSP, Iv64, XX }, - { "movS", RMeBP, Iv64, XX }, - { "movS", RMeSI, Iv64, XX }, - { "movS", RMeDI, Iv64, XX }, + { "movS", { RMeAX, Iv64 } }, + { "movS", { RMeCX, Iv64 } }, + { "movS", { RMeDX, Iv64 } }, + { "movS", { RMeBX, Iv64 } }, + { "movS", { RMeSP, Iv64 } }, + { "movS", { RMeBP, Iv64 } }, + { "movS", { RMeSI, Iv64 } }, + { "movS", { RMeDI, Iv64 } }, /* c0 */ { GRP2b }, { GRP2S }, - { "retT", Iw, XX, XX }, - { "retT", XX, XX, XX }, - { "les{S|}", Gv, Mp, XX }, - { "ldsS", Gv, Mp, XX }, - { "movA", Eb, Ib, XX }, - { "movQ", Ev, Iv, XX }, + { "retT", { Iw } }, + { "retT", { XX } }, + { "les{S|}", { Gv, Mp } }, + { "ldsS", { Gv, Mp } }, + { GRP11_C6 }, + { GRP11_C7 }, /* c8 */ - { "enterT", Iw, Ib, XX }, - { "leaveT", XX, XX, XX }, - { "lretP", Iw, XX, XX }, - { "lretP", XX, XX, XX }, - { "int3", XX, XX, XX }, - { "int", Ib, XX, XX }, - { "into{|}", XX, XX, XX }, - { "iretP", XX, XX, XX }, + { "enterT", { Iw, Ib } }, + { "leaveT", { XX } }, + { "lretP", { Iw } }, + { "lretP", { XX } }, + { "int3", { XX } }, + { "int", { Ib } }, + { "into{|}", { XX } }, + { "iretP", { XX } }, /* d0 */ { GRP2b_one }, { GRP2S_one }, { GRP2b_cl }, { GRP2S_cl }, - { "aam{|}", sIb, XX, XX }, - { "aad{|}", sIb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "xlat", DSBX, XX, XX }, + { "aam{|}", { sIb } }, + { "aad{|}", { sIb } }, + { "(bad)", { XX } }, + { "xlat", { DSBX } }, /* d8 */ { FLOAT }, { FLOAT }, @@ -769,39 +855,39 @@ static const struct dis386 dis386[] = { { FLOAT }, { FLOAT }, /* e0 */ - { "loopneFH", Jb, XX, loop_jcxz_flag }, - { "loopeFH", Jb, XX, loop_jcxz_flag }, - { "loopFH", Jb, XX, loop_jcxz_flag }, - { "jEcxzH", Jb, XX, loop_jcxz_flag }, - { "inB", AL, Ib, XX }, - { "inS", eAX, Ib, XX }, - { "outB", Ib, AL, XX }, - { "outS", Ib, eAX, XX }, + { "loopneFH", { Jb, XX, loop_jcxz_flag } }, + { "loopeFH", { Jb, XX, loop_jcxz_flag } }, + { "loopFH", { Jb, XX, loop_jcxz_flag } }, + { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, + { "inB", { AL, Ib } }, + { "inG", { zAX, Ib } }, + { "outB", { Ib, AL } }, + { "outG", { Ib, zAX } }, /* e8 */ - { "callT", Jv, XX, XX }, - { "jmpT", Jv, XX, XX }, - { "Jjmp{T|}", Ap, XX, XX }, - { "jmp", Jb, XX, XX }, - { "inB", AL, indirDX, XX }, - { "inS", eAX, indirDX, XX }, - { "outB", indirDX, AL, XX }, - { "outS", indirDX, eAX, XX }, + { "callT", { Jv } }, + { "jmpT", { Jv } }, + { "Jjmp{T|}", { Ap } }, + { "jmp", { Jb } }, + { "inB", { AL, indirDX } }, + { "inG", { zAX, indirDX } }, + { "outB", { indirDX, AL } }, + { "outG", { indirDX, zAX } }, /* f0 */ - { "(bad)", XX, XX, XX }, /* lock prefix */ - { "icebp", XX, XX, XX }, - { "(bad)", XX, XX, XX }, /* repne */ - { "(bad)", XX, XX, XX }, /* repz */ - { "hlt", XX, XX, XX }, - { "cmc", XX, XX, XX }, + { "(bad)", { XX } }, /* lock prefix */ + { "icebp", { XX } }, + { "(bad)", { XX } }, /* repne */ + { "(bad)", { XX } }, /* repz */ + { "hlt", { XX } }, + { "cmc", { XX } }, { GRP3b }, { GRP3S }, /* f8 */ - { "clc", XX, XX, XX }, - { "stc", XX, XX, XX }, - { "cli", XX, XX, XX }, - { "sti", XX, XX, XX }, - { "cld", XX, XX, XX }, - { "std", XX, XX, XX }, + { "clc", { XX } }, + { "stc", { XX } }, + { "cli", { XX } }, + { "sti", { XX } }, + { "cld", { XX } }, + { "std", { XX } }, { GRP4 }, { GRP5 }, }; @@ -810,102 +896,102 @@ static const struct dis386 dis386_twobyte[] = { /* 00 */ { GRP6 }, { GRP7 }, - { "larS", Gv, Ew, XX }, - { "lslS", Gv, Ew, XX }, - { "(bad)", XX, XX, XX }, - { "syscall", XX, XX, XX }, - { "clts", XX, XX, XX }, - { "sysretP", XX, XX, XX }, + { "larS", { Gv, Ew } }, + { "lslS", { Gv, Ew } }, + { "(bad)", { XX } }, + { "syscall", { XX } }, + { "clts", { XX } }, + { "sysretP", { XX } }, /* 08 */ - { "invd", XX, XX, XX }, - { "wbinvd", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "ud2a", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "invd", { XX } }, + { "wbinvd", { XX } }, + { "(bad)", { XX } }, + { "ud2a", { XX } }, + { "(bad)", { XX } }, { GRPAMD }, - { "femms", XX, XX, XX }, - { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix. */ + { "femms", { XX } }, + { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ /* 10 */ { PREGRP8 }, { PREGRP9 }, { PREGRP30 }, - { "movlpX", EX, XM, SIMD_Fixup, 'h' }, - { "unpcklpX", XM, EX, XX }, - { "unpckhpX", XM, EX, XX }, + { "movlpX", { EXq, XM, { SIMD_Fixup, 'h' } } }, + { "unpcklpX", { XM, EXq } }, + { "unpckhpX", { XM, EXq } }, { PREGRP31 }, - { "movhpX", EX, XM, SIMD_Fixup, 'l' }, + { "movhpX", { EXq, XM, { SIMD_Fixup, 'l' } } }, /* 18 */ - { GRP14 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { GRP16 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "nopQ", { Ev } }, /* 20 */ - { "movZ", Rm, Cm, XX }, - { "movZ", Rm, Dm, XX }, - { "movZ", Cm, Rm, XX }, - { "movZ", Dm, Rm, XX }, - { "movL", Rd, Td, XX }, - { "(bad)", XX, XX, XX }, - { "movL", Td, Rd, XX }, - { "(bad)", XX, XX, XX }, + { "movZ", { Rm, Cm } }, + { "movZ", { Rm, Dm } }, + { "movZ", { Cm, Rm } }, + { "movZ", { Dm, Rm } }, + { "movL", { Rd, Td } }, + { "(bad)", { XX } }, + { "movL", { Td, Rd } }, + { "(bad)", { XX } }, /* 28 */ - { "movapX", XM, EX, XX }, - { "movapX", EX, XM, XX }, + { "movapX", { XM, EXx } }, + { "movapX", { EXx, XM } }, { PREGRP2 }, - { "movntpX", Ev, XM, XX }, + { PREGRP33 }, { PREGRP4 }, { PREGRP3 }, - { "ucomisX", XM,EX, XX }, - { "comisX", XM,EX, XX }, + { PREGRP93 }, + { PREGRP94 }, /* 30 */ - { "wrmsr", XX, XX, XX }, - { "rdtsc", XX, XX, XX }, - { "rdmsr", XX, XX, XX }, - { "rdpmc", XX, XX, XX }, - { "sysenter", XX, XX, XX }, - { "sysexit", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "wrmsr", { XX } }, + { "rdtsc", { XX } }, + { "rdmsr", { XX } }, + { "rdpmc", { XX } }, + { "sysenter", { XX } }, + { "sysexit", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, /* 38 */ { THREE_BYTE_0 }, - { "(bad)", XX, XX, XX }, + { "(bad)", { XX } }, { THREE_BYTE_1 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, /* 40 */ - { "cmovo", Gv, Ev, XX }, - { "cmovno", Gv, Ev, XX }, - { "cmovb", Gv, Ev, XX }, - { "cmovae", Gv, Ev, XX }, - { "cmove", Gv, Ev, XX }, - { "cmovne", Gv, Ev, XX }, - { "cmovbe", Gv, Ev, XX }, - { "cmova", Gv, Ev, XX }, + { "cmovo", { Gv, Ev } }, + { "cmovno", { Gv, Ev } }, + { "cmovb", { Gv, Ev } }, + { "cmovae", { Gv, Ev } }, + { "cmove", { Gv, Ev } }, + { "cmovne", { Gv, Ev } }, + { "cmovbe", { Gv, Ev } }, + { "cmova", { Gv, Ev } }, /* 48 */ - { "cmovs", Gv, Ev, XX }, - { "cmovns", Gv, Ev, XX }, - { "cmovp", Gv, Ev, XX }, - { "cmovnp", Gv, Ev, XX }, - { "cmovl", Gv, Ev, XX }, - { "cmovge", Gv, Ev, XX }, - { "cmovle", Gv, Ev, XX }, - { "cmovg", Gv, Ev, XX }, + { "cmovs", { Gv, Ev } }, + { "cmovns", { Gv, Ev } }, + { "cmovp", { Gv, Ev } }, + { "cmovnp", { Gv, Ev } }, + { "cmovl", { Gv, Ev } }, + { "cmovge", { Gv, Ev } }, + { "cmovle", { Gv, Ev } }, + { "cmovg", { Gv, Ev } }, /* 50 */ - { "movmskpX", Gdq, XS, XX }, + { "movmskpX", { Gdq, XS } }, { PREGRP13 }, { PREGRP12 }, { PREGRP11 }, - { "andpX", XM, EX, XX }, - { "andnpX", XM, EX, XX }, - { "orpX", XM, EX, XX }, - { "xorpX", XM, EX, XX }, + { "andpX", { XM, EXx } }, + { "andnpX", { XM, EXx } }, + { "orpX", { XM, EXx } }, + { "xorpX", { XM, EXx } }, /* 58 */ { PREGRP0 }, { PREGRP10 }, @@ -916,185 +1002,185 @@ static const struct dis386 dis386_twobyte[] = { { PREGRP5 }, { PREGRP6 }, /* 60 */ - { "punpcklbw", MX, EM, XX }, - { "punpcklwd", MX, EM, XX }, - { "punpckldq", MX, EM, XX }, - { "packsswb", MX, EM, XX }, - { "pcmpgtb", MX, EM, XX }, - { "pcmpgtw", MX, EM, XX }, - { "pcmpgtd", MX, EM, XX }, - { "packuswb", MX, EM, XX }, + { PREGRP95 }, + { PREGRP96 }, + { PREGRP97 }, + { "packsswb", { MX, EM } }, + { "pcmpgtb", { MX, EM } }, + { "pcmpgtw", { MX, EM } }, + { "pcmpgtd", { MX, EM } }, + { "packuswb", { MX, EM } }, /* 68 */ - { "punpckhbw", MX, EM, XX }, - { "punpckhwd", MX, EM, XX }, - { "punpckhdq", MX, EM, XX }, - { "packssdw", MX, EM, XX }, + { "punpckhbw", { MX, EM } }, + { "punpckhwd", { MX, EM } }, + { "punpckhdq", { MX, EM } }, + { "packssdw", { MX, EM } }, { PREGRP26 }, { PREGRP24 }, - { "movd", MX, Edq, XX }, + { "movd", { MX, Edq } }, { PREGRP19 }, /* 70 */ { PREGRP22 }, - { GRP10 }, - { GRP11 }, { GRP12 }, - { "pcmpeqb", MX, EM, XX }, - { "pcmpeqw", MX, EM, XX }, - { "pcmpeqd", MX, EM, XX }, - { "emms", XX, XX, XX }, + { GRP13 }, + { GRP14 }, + { "pcmpeqb", { MX, EM } }, + { "pcmpeqw", { MX, EM } }, + { "pcmpeqd", { MX, EM } }, + { "emms", { XX } }, /* 78 */ - { "vmread", Em, Gm, XX }, - { "vmwrite", Gm, Em, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { PREGRP34 }, + { PREGRP35 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, { PREGRP28 }, { PREGRP29 }, { PREGRP23 }, { PREGRP20 }, /* 80 */ - { "joH", Jv, XX, cond_jump_flag }, - { "jnoH", Jv, XX, cond_jump_flag }, - { "jbH", Jv, XX, cond_jump_flag }, - { "jaeH", Jv, XX, cond_jump_flag }, - { "jeH", Jv, XX, cond_jump_flag }, - { "jneH", Jv, XX, cond_jump_flag }, - { "jbeH", Jv, XX, cond_jump_flag }, - { "jaH", Jv, XX, cond_jump_flag }, + { "joH", { Jv, XX, cond_jump_flag } }, + { "jnoH", { Jv, XX, cond_jump_flag } }, + { "jbH", { Jv, XX, cond_jump_flag } }, + { "jaeH", { Jv, XX, cond_jump_flag } }, + { "jeH", { Jv, XX, cond_jump_flag } }, + { "jneH", { Jv, XX, cond_jump_flag } }, + { "jbeH", { Jv, XX, cond_jump_flag } }, + { "jaH", { Jv, XX, cond_jump_flag } }, /* 88 */ - { "jsH", Jv, XX, cond_jump_flag }, - { "jnsH", Jv, XX, cond_jump_flag }, - { "jpH", Jv, XX, cond_jump_flag }, - { "jnpH", Jv, XX, cond_jump_flag }, - { "jlH", Jv, XX, cond_jump_flag }, - { "jgeH", Jv, XX, cond_jump_flag }, - { "jleH", Jv, XX, cond_jump_flag }, - { "jgH", Jv, XX, cond_jump_flag }, + { "jsH", { Jv, XX, cond_jump_flag } }, + { "jnsH", { Jv, XX, cond_jump_flag } }, + { "jpH", { Jv, XX, cond_jump_flag } }, + { "jnpH", { Jv, XX, cond_jump_flag } }, + { "jlH", { Jv, XX, cond_jump_flag } }, + { "jgeH", { Jv, XX, cond_jump_flag } }, + { "jleH", { Jv, XX, cond_jump_flag } }, + { "jgH", { Jv, XX, cond_jump_flag } }, /* 90 */ - { "seto", Eb, XX, XX }, - { "setno", Eb, XX, XX }, - { "setb", Eb, XX, XX }, - { "setae", Eb, XX, XX }, - { "sete", Eb, XX, XX }, - { "setne", Eb, XX, XX }, - { "setbe", Eb, XX, XX }, - { "seta", Eb, XX, XX }, + { "seto", { Eb } }, + { "setno", { Eb } }, + { "setb", { Eb } }, + { "setae", { Eb } }, + { "sete", { Eb } }, + { "setne", { Eb } }, + { "setbe", { Eb } }, + { "seta", { Eb } }, /* 98 */ - { "sets", Eb, XX, XX }, - { "setns", Eb, XX, XX }, - { "setp", Eb, XX, XX }, - { "setnp", Eb, XX, XX }, - { "setl", Eb, XX, XX }, - { "setge", Eb, XX, XX }, - { "setle", Eb, XX, XX }, - { "setg", Eb, XX, XX }, + { "sets", { Eb } }, + { "setns", { Eb } }, + { "setp", { Eb } }, + { "setnp", { Eb } }, + { "setl", { Eb } }, + { "setge", { Eb } }, + { "setle", { Eb } }, + { "setg", { Eb } }, /* a0 */ - { "pushT", fs, XX, XX }, - { "popT", fs, XX, XX }, - { "cpuid", XX, XX, XX }, - { "btS", Ev, Gv, XX }, - { "shldS", Ev, Gv, Ib }, - { "shldS", Ev, Gv, CL }, + { "pushT", { fs } }, + { "popT", { fs } }, + { "cpuid", { XX } }, + { "btS", { Ev, Gv } }, + { "shldS", { Ev, Gv, Ib } }, + { "shldS", { Ev, Gv, CL } }, { GRPPADLCK2 }, { GRPPADLCK1 }, /* a8 */ - { "pushT", gs, XX, XX }, - { "popT", gs, XX, XX }, - { "rsm", XX, XX, XX }, - { "btsS", Ev, Gv, XX }, - { "shrdS", Ev, Gv, Ib }, - { "shrdS", Ev, Gv, CL }, - { GRP13 }, - { "imulS", Gv, Ev, XX }, + { "pushT", { gs } }, + { "popT", { gs } }, + { "rsm", { XX } }, + { "btsS", { Ev, Gv } }, + { "shrdS", { Ev, Gv, Ib } }, + { "shrdS", { Ev, Gv, CL } }, + { GRP15 }, + { "imulS", { Gv, Ev } }, /* b0 */ - { "cmpxchgB", Eb, Gb, XX }, - { "cmpxchgS", Ev, Gv, XX }, - { "lssS", Gv, Mp, XX }, - { "btrS", Ev, Gv, XX }, - { "lfsS", Gv, Mp, XX }, - { "lgsS", Gv, Mp, XX }, - { "movz{bR|x|bR|x}", Gv, Eb, XX }, - { "movz{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movzww ! */ + { "cmpxchgB", { Eb, Gb } }, + { "cmpxchgS", { Ev, Gv } }, + { "lssS", { Gv, Mp } }, + { "btrS", { Ev, Gv } }, + { "lfsS", { Gv, Mp } }, + { "lgsS", { Gv, Mp } }, + { "movz{bR|x|bR|x}", { Gv, Eb } }, + { "movz{wR|x|wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ /* b8 */ - { "(bad)", XX, XX, XX }, - { "ud2b", XX, XX, XX }, + { PREGRP37 }, + { "ud2b", { XX } }, { GRP8 }, - { "btcS", Ev, Gv, XX }, - { "bsfS", Gv, Ev, XX }, - { "bsrS", Gv, Ev, XX }, - { "movs{bR|x|bR|x}", Gv, Eb, XX }, - { "movs{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movsww ! */ + { "btcS", { Ev, Gv } }, + { "bsfS", { Gv, Ev } }, + { PREGRP36 }, + { "movs{bR|x|bR|x}", { Gv, Eb } }, + { "movs{wR|x|wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ /* c0 */ - { "xaddB", Eb, Gb, XX }, - { "xaddS", Ev, Gv, XX }, + { "xaddB", { Eb, Gb } }, + { "xaddS", { Ev, Gv } }, { PREGRP1 }, - { "movntiS", Ev, Gv, XX }, - { "pinsrw", MX, Edqw, Ib }, - { "pextrw", Gdq, MS, Ib }, - { "shufpX", XM, EX, Ib }, + { "movntiS", { Ev, Gv } }, + { "pinsrw", { MX, Edqw, Ib } }, + { "pextrw", { Gdq, MS, Ib } }, + { "shufpX", { XM, EXx, Ib } }, { GRP9 }, /* c8 */ - { "bswap", RMeAX, XX, XX }, - { "bswap", RMeCX, XX, XX }, - { "bswap", RMeDX, XX, XX }, - { "bswap", RMeBX, XX, XX }, - { "bswap", RMeSP, XX, XX }, - { "bswap", RMeBP, XX, XX }, - { "bswap", RMeSI, XX, XX }, - { "bswap", RMeDI, XX, XX }, + { "bswap", { RMeAX } }, + { "bswap", { RMeCX } }, + { "bswap", { RMeDX } }, + { "bswap", { RMeBX } }, + { "bswap", { RMeSP } }, + { "bswap", { RMeBP } }, + { "bswap", { RMeSI } }, + { "bswap", { RMeDI } }, /* d0 */ { PREGRP27 }, - { "psrlw", MX, EM, XX }, - { "psrld", MX, EM, XX }, - { "psrlq", MX, EM, XX }, - { "paddq", MX, EM, XX }, - { "pmullw", MX, EM, XX }, + { "psrlw", { MX, EM } }, + { "psrld", { MX, EM } }, + { "psrlq", { MX, EM } }, + { "paddq", { MX, EM } }, + { "pmullw", { MX, EM } }, { PREGRP21 }, - { "pmovmskb", Gdq, MS, XX }, + { "pmovmskb", { Gdq, MS } }, /* d8 */ - { "psubusb", MX, EM, XX }, - { "psubusw", MX, EM, XX }, - { "pminub", MX, EM, XX }, - { "pand", MX, EM, XX }, - { "paddusb", MX, EM, XX }, - { "paddusw", MX, EM, XX }, - { "pmaxub", MX, EM, XX }, - { "pandn", MX, EM, XX }, + { "psubusb", { MX, EM } }, + { "psubusw", { MX, EM } }, + { "pminub", { MX, EM } }, + { "pand", { MX, EM } }, + { "paddusb", { MX, EM } }, + { "paddusw", { MX, EM } }, + { "pmaxub", { MX, EM } }, + { "pandn", { MX, EM } }, /* e0 */ - { "pavgb", MX, EM, XX }, - { "psraw", MX, EM, XX }, - { "psrad", MX, EM, XX }, - { "pavgw", MX, EM, XX }, - { "pmulhuw", MX, EM, XX }, - { "pmulhw", MX, EM, XX }, + { "pavgb", { MX, EM } }, + { "psraw", { MX, EM } }, + { "psrad", { MX, EM } }, + { "pavgw", { MX, EM } }, + { "pmulhuw", { MX, EM } }, + { "pmulhw", { MX, EM } }, { PREGRP15 }, { PREGRP25 }, /* e8 */ - { "psubsb", MX, EM, XX }, - { "psubsw", MX, EM, XX }, - { "pminsw", MX, EM, XX }, - { "por", MX, EM, XX }, - { "paddsb", MX, EM, XX }, - { "paddsw", MX, EM, XX }, - { "pmaxsw", MX, EM, XX }, - { "pxor", MX, EM, XX }, + { "psubsb", { MX, EM } }, + { "psubsw", { MX, EM } }, + { "pminsw", { MX, EM } }, + { "por", { MX, EM } }, + { "paddsb", { MX, EM } }, + { "paddsw", { MX, EM } }, + { "pmaxsw", { MX, EM } }, + { "pxor", { MX, EM } }, /* f0 */ { PREGRP32 }, - { "psllw", MX, EM, XX }, - { "pslld", MX, EM, XX }, - { "psllq", MX, EM, XX }, - { "pmuludq", MX, EM, XX }, - { "pmaddwd", MX, EM, XX }, - { "psadbw", MX, EM, XX }, + { "psllw", { MX, EM } }, + { "pslld", { MX, EM } }, + { "psllq", { MX, EM } }, + { "pmuludq", { MX, EM } }, + { "pmaddwd", { MX, EM } }, + { "psadbw", { MX, EM } }, { PREGRP18 }, /* f8 */ - { "psubb", MX, EM, XX }, - { "psubw", MX, EM, XX }, - { "psubd", MX, EM, XX }, - { "psubq", MX, EM, XX }, - { "paddb", MX, EM, XX }, - { "paddw", MX, EM, XX }, - { "paddd", MX, EM, XX }, - { "(bad)", XX, XX, XX } + { "psubb", { MX, EM } }, + { "psubw", { MX, EM } }, + { "psubd", { MX, EM } }, + { "psubq", { MX, EM } }, + { "paddb", { MX, EM } }, + { "paddw", { MX, EM } }, + { "paddd", { MX, EM } }, + { "(bad)", { XX } }, }; static const unsigned char onebyte_has_modrm[256] = { @@ -1124,7 +1210,7 @@ static const unsigned char twobyte_has_modrm[256] = { /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ /* ------------------------------- */ /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ - /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 1f */ + /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */ /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */ /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ @@ -1134,7 +1220,7 @@ static const unsigned char twobyte_has_modrm[256] = { /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ - /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */ + /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ @@ -1143,17 +1229,17 @@ static const unsigned char twobyte_has_modrm[256] = { /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; -static const unsigned char twobyte_uses_SSE_prefix[256] = { +static const unsigned char twobyte_uses_DATA_prefix[256] = { /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ /* ------------------------------- */ /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */ - /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */ + /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0, /* 2f */ /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */ /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */ - /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1, /* 7f */ + /* 70 */ 1,0,0,0,0,0,0,0,1,1,0,0,1,1,1,1, /* 7f */ /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ @@ -1166,6 +1252,196 @@ static const unsigned char twobyte_uses_SSE_prefix[256] = { /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; +static const unsigned char twobyte_uses_REPNZ_prefix[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ + /* 10 */ 1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ + /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ + /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ + /* 50 */ 0,1,0,0,0,0,0,0,1,1,1,0,1,1,1,1, /* 5f */ + /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */ + /* 70 */ 1,0,0,0,0,0,0,0,1,1,0,0,1,1,0,0, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ + /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */ + /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */ + /* f0 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +static const unsigned char twobyte_uses_REPZ_prefix[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ + /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */ + /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ + /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ + /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */ + /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1, /* 6f */ + /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ + /* b0 */ 0,0,0,0,0,0,0,0,1,0,0,0,0,1,0,0, /* bf */ + /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */ + /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */ + /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +/* This is used to determine if opcode 0f 38 XX uses DATA prefix. */ +static const unsigned char threebyte_0x38_uses_DATA_prefix[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0, /* 0f */ + /* 10 */ 1,0,0,0,1,1,0,1,0,0,0,0,1,1,1,0, /* 1f */ + /* 20 */ 1,1,1,1,1,1,0,0,1,1,1,1,0,0,0,0, /* 2f */ + /* 30 */ 1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1, /* 3f */ + /* 40 */ 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ + /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */ + /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */ + /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ + /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ + /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ + /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +/* This is used to determine if opcode 0f 38 XX uses REPNZ prefix. */ +static const unsigned char threebyte_0x38_uses_REPNZ_prefix[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ + /* 10 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ + /* 20 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ + /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ + /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */ + /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */ + /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ + /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ + /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ + /* f0 */ 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +/* This is used to determine if opcode 0f 38 XX uses REPZ prefix. */ +static const unsigned char threebyte_0x38_uses_REPZ_prefix[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ + /* 10 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ + /* 20 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ + /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ + /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */ + /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */ + /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ + /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ + /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ + /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +/* This is used to determine if opcode 0f 3a XX uses DATA prefix. */ +static const unsigned char threebyte_0x3a_uses_DATA_prefix[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1, /* 0f */ + /* 10 */ 0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */ + /* 20 */ 1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ + /* 40 */ 1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ + /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */ + /* 60 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */ + /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ + /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ + /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ + /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +/* This is used to determine if opcode 0f 3a XX uses REPNZ prefix. */ +static const unsigned char threebyte_0x3a_uses_REPNZ_prefix[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ + /* 10 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ + /* 20 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ + /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ + /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */ + /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */ + /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ + /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ + /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ + /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + +/* This is used to determine if opcode 0f 3a XX uses REPZ prefix. */ +static const unsigned char threebyte_0x3a_uses_REPZ_prefix[256] = { + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ + /* ------------------------------- */ + /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ + /* 10 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ + /* 20 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */ + /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ + /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ + /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */ + /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */ + /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */ + /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ + /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ + /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ + /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ + /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ + /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ + /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ + /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* ------------------------------- */ + /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ +}; + static char obuf[100]; static char *obufp; static char scratchbuf[100]; @@ -1173,9 +1449,13 @@ static unsigned char *start_codep; static unsigned char *insn_codep; static unsigned char *codep; static disassemble_info *the_info; -static int mod; -static int rm; -static int reg; +static struct + { + int mod; + int reg; + int rm; + } +modrm; static unsigned char need_modrm; /* If we are accessing mod/rm/reg without need_modrm set, then the @@ -1244,595 +1524,1671 @@ static const char *att_index16[] = { }; static const struct dis386 grps[][8] = { + /* GRP1a */ + { + { "popU", { stackEv } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + }, /* GRP1b */ { - { "addA", Eb, Ib, XX }, - { "orA", Eb, Ib, XX }, - { "adcA", Eb, Ib, XX }, - { "sbbA", Eb, Ib, XX }, - { "andA", Eb, Ib, XX }, - { "subA", Eb, Ib, XX }, - { "xorA", Eb, Ib, XX }, - { "cmpA", Eb, Ib, XX } + { "addA", { Eb, Ib } }, + { "orA", { Eb, Ib } }, + { "adcA", { Eb, Ib } }, + { "sbbA", { Eb, Ib } }, + { "andA", { Eb, Ib } }, + { "subA", { Eb, Ib } }, + { "xorA", { Eb, Ib } }, + { "cmpA", { Eb, Ib } }, }, /* GRP1S */ { - { "addQ", Ev, Iv, XX }, - { "orQ", Ev, Iv, XX }, - { "adcQ", Ev, Iv, XX }, - { "sbbQ", Ev, Iv, XX }, - { "andQ", Ev, Iv, XX }, - { "subQ", Ev, Iv, XX }, - { "xorQ", Ev, Iv, XX }, - { "cmpQ", Ev, Iv, XX } + { "addQ", { Ev, Iv } }, + { "orQ", { Ev, Iv } }, + { "adcQ", { Ev, Iv } }, + { "sbbQ", { Ev, Iv } }, + { "andQ", { Ev, Iv } }, + { "subQ", { Ev, Iv } }, + { "xorQ", { Ev, Iv } }, + { "cmpQ", { Ev, Iv } }, }, /* GRP1Ss */ { - { "addQ", Ev, sIb, XX }, - { "orQ", Ev, sIb, XX }, - { "adcQ", Ev, sIb, XX }, - { "sbbQ", Ev, sIb, XX }, - { "andQ", Ev, sIb, XX }, - { "subQ", Ev, sIb, XX }, - { "xorQ", Ev, sIb, XX }, - { "cmpQ", Ev, sIb, XX } + { "addQ", { Ev, sIb } }, + { "orQ", { Ev, sIb } }, + { "adcQ", { Ev, sIb } }, + { "sbbQ", { Ev, sIb } }, + { "andQ", { Ev, sIb } }, + { "subQ", { Ev, sIb } }, + { "xorQ", { Ev, sIb } }, + { "cmpQ", { Ev, sIb } }, }, /* GRP2b */ { - { "rolA", Eb, Ib, XX }, - { "rorA", Eb, Ib, XX }, - { "rclA", Eb, Ib, XX }, - { "rcrA", Eb, Ib, XX }, - { "shlA", Eb, Ib, XX }, - { "shrA", Eb, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "sarA", Eb, Ib, XX }, + { "rolA", { Eb, Ib } }, + { "rorA", { Eb, Ib } }, + { "rclA", { Eb, Ib } }, + { "rcrA", { Eb, Ib } }, + { "shlA", { Eb, Ib } }, + { "shrA", { Eb, Ib } }, + { "(bad)", { XX } }, + { "sarA", { Eb, Ib } }, }, /* GRP2S */ { - { "rolQ", Ev, Ib, XX }, - { "rorQ", Ev, Ib, XX }, - { "rclQ", Ev, Ib, XX }, - { "rcrQ", Ev, Ib, XX }, - { "shlQ", Ev, Ib, XX }, - { "shrQ", Ev, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "sarQ", Ev, Ib, XX }, + { "rolQ", { Ev, Ib } }, + { "rorQ", { Ev, Ib } }, + { "rclQ", { Ev, Ib } }, + { "rcrQ", { Ev, Ib } }, + { "shlQ", { Ev, Ib } }, + { "shrQ", { Ev, Ib } }, + { "(bad)", { XX } }, + { "sarQ", { Ev, Ib } }, }, /* GRP2b_one */ { - { "rolA", Eb, I1, XX }, - { "rorA", Eb, I1, XX }, - { "rclA", Eb, I1, XX }, - { "rcrA", Eb, I1, XX }, - { "shlA", Eb, I1, XX }, - { "shrA", Eb, I1, XX }, - { "(bad)", XX, XX, XX }, - { "sarA", Eb, I1, XX }, + { "rolA", { Eb, I1 } }, + { "rorA", { Eb, I1 } }, + { "rclA", { Eb, I1 } }, + { "rcrA", { Eb, I1 } }, + { "shlA", { Eb, I1 } }, + { "shrA", { Eb, I1 } }, + { "(bad)", { XX } }, + { "sarA", { Eb, I1 } }, }, /* GRP2S_one */ { - { "rolQ", Ev, I1, XX }, - { "rorQ", Ev, I1, XX }, - { "rclQ", Ev, I1, XX }, - { "rcrQ", Ev, I1, XX }, - { "shlQ", Ev, I1, XX }, - { "shrQ", Ev, I1, XX }, - { "(bad)", XX, XX, XX}, - { "sarQ", Ev, I1, XX }, + { "rolQ", { Ev, I1 } }, + { "rorQ", { Ev, I1 } }, + { "rclQ", { Ev, I1 } }, + { "rcrQ", { Ev, I1 } }, + { "shlQ", { Ev, I1 } }, + { "shrQ", { Ev, I1 } }, + { "(bad)", { XX } }, + { "sarQ", { Ev, I1 } }, }, /* GRP2b_cl */ { - { "rolA", Eb, CL, XX }, - { "rorA", Eb, CL, XX }, - { "rclA", Eb, CL, XX }, - { "rcrA", Eb, CL, XX }, - { "shlA", Eb, CL, XX }, - { "shrA", Eb, CL, XX }, - { "(bad)", XX, XX, XX }, - { "sarA", Eb, CL, XX }, + { "rolA", { Eb, CL } }, + { "rorA", { Eb, CL } }, + { "rclA", { Eb, CL } }, + { "rcrA", { Eb, CL } }, + { "shlA", { Eb, CL } }, + { "shrA", { Eb, CL } }, + { "(bad)", { XX } }, + { "sarA", { Eb, CL } }, }, /* GRP2S_cl */ { - { "rolQ", Ev, CL, XX }, - { "rorQ", Ev, CL, XX }, - { "rclQ", Ev, CL, XX }, - { "rcrQ", Ev, CL, XX }, - { "shlQ", Ev, CL, XX }, - { "shrQ", Ev, CL, XX }, - { "(bad)", XX, XX, XX }, - { "sarQ", Ev, CL, XX } + { "rolQ", { Ev, CL } }, + { "rorQ", { Ev, CL } }, + { "rclQ", { Ev, CL } }, + { "rcrQ", { Ev, CL } }, + { "shlQ", { Ev, CL } }, + { "shrQ", { Ev, CL } }, + { "(bad)", { XX } }, + { "sarQ", { Ev, CL } }, }, /* GRP3b */ { - { "testA", Eb, Ib, XX }, - { "(bad)", Eb, XX, XX }, - { "notA", Eb, XX, XX }, - { "negA", Eb, XX, XX }, - { "mulA", Eb, XX, XX }, /* Don't print the implicit %al register, */ - { "imulA", Eb, XX, XX }, /* to distinguish these opcodes from other */ - { "divA", Eb, XX, XX }, /* mul/imul opcodes. Do the same for div */ - { "idivA", Eb, XX, XX } /* and idiv for consistency. */ + { "testA", { Eb, Ib } }, + { "(bad)", { Eb } }, + { "notA", { Eb } }, + { "negA", { Eb } }, + { "mulA", { Eb } }, /* Don't print the implicit %al register, */ + { "imulA", { Eb } }, /* to distinguish these opcodes from other */ + { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ + { "idivA", { Eb } }, /* and idiv for consistency. */ }, /* GRP3S */ { - { "testQ", Ev, Iv, XX }, - { "(bad)", XX, XX, XX }, - { "notQ", Ev, XX, XX }, - { "negQ", Ev, XX, XX }, - { "mulQ", Ev, XX, XX }, /* Don't print the implicit register. */ - { "imulQ", Ev, XX, XX }, - { "divQ", Ev, XX, XX }, - { "idivQ", Ev, XX, XX }, + { "testQ", { Ev, Iv } }, + { "(bad)", { XX } }, + { "notQ", { Ev } }, + { "negQ", { Ev } }, + { "mulQ", { Ev } }, /* Don't print the implicit register. */ + { "imulQ", { Ev } }, + { "divQ", { Ev } }, + { "idivQ", { Ev } }, }, /* GRP4 */ { - { "incA", Eb, XX, XX }, - { "decA", Eb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "incA", { Eb } }, + { "decA", { Eb } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, }, /* GRP5 */ { - { "incQ", Ev, XX, XX }, - { "decQ", Ev, XX, XX }, - { "callT", indirEv, XX, XX }, - { "JcallT", indirEp, XX, XX }, - { "jmpT", indirEv, XX, XX }, - { "JjmpT", indirEp, XX, XX }, - { "pushU", stackEv, XX, XX }, - { "(bad)", XX, XX, XX }, + { "incQ", { Ev } }, + { "decQ", { Ev } }, + { "callT", { indirEv } }, + { "JcallT", { indirEp } }, + { "jmpT", { indirEv } }, + { "JjmpT", { indirEp } }, + { "pushU", { stackEv } }, + { "(bad)", { XX } }, }, /* GRP6 */ { - { "sldtQ", Ev, XX, XX }, - { "strQ", Ev, XX, XX }, - { "lldt", Ew, XX, XX }, - { "ltr", Ew, XX, XX }, - { "verr", Ew, XX, XX }, - { "verw", Ew, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX } + { "sldtD", { Sv } }, + { "strD", { Sv } }, + { "lldt", { Ew } }, + { "ltr", { Ew } }, + { "verr", { Ew } }, + { "verw", { Ew } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, }, /* GRP7 */ { - { "sgdtIQ", VMX_Fixup, 0, XX, XX }, - { "sidtIQ", PNI_Fixup, 0, XX, XX }, - { "lgdt{Q|Q||}", M, XX, XX }, - { "lidt{Q|Q||}", SVME_Fixup, 0, XX, XX }, - { "smswQ", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "lmsw", Ew, XX, XX }, - { "invlpg", INVLPG_Fixup, w_mode, XX, XX }, + { "sgdt{Q|IQ||}", { { VMX_Fixup, 0 } } }, + { "sidt{Q|IQ||}", { { PNI_Fixup, 0 } } }, + { "lgdt{Q|Q||}", { M } }, + { "lidt{Q|Q||}", { { SVME_Fixup, 0 } } }, + { "smswD", { Sv } }, + { "(bad)", { XX } }, + { "lmsw", { Ew } }, + { "invlpg", { { INVLPG_Fixup, w_mode } } }, }, /* GRP8 */ { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "btQ", Ev, Ib, XX }, - { "btsQ", Ev, Ib, XX }, - { "btrQ", Ev, Ib, XX }, - { "btcQ", Ev, Ib, XX }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "btQ", { Ev, Ib } }, + { "btsQ", { Ev, Ib } }, + { "btrQ", { Ev, Ib } }, + { "btcQ", { Ev, Ib } }, }, /* GRP9 */ { - { "(bad)", XX, XX, XX }, - { "cmpxchg8b", Eq, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "", VM, XX, XX }, /* See OP_VMX. */ - { "vmptrst", Eq, XX, XX }, - }, - /* GRP10 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psrlw", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "psraw", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "psllw", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - }, - /* GRP11 */ - { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psrld", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "psrad", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "pslld", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, + { "(bad)", { XX } }, + { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "", { VM } }, /* See OP_VMX. */ + { "vmptrst", { Mq } }, + }, + /* GRP11_C6 */ + { + { "movA", { Eb, Ib } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + }, + /* GRP11_C7 */ + { + { "movQ", { Ev, Iv } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, }, /* GRP12 */ { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psrlq", MS, Ib, XX }, - { "psrldq", MS, Ib, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "psllq", MS, Ib, XX }, - { "pslldq", MS, Ib, XX }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "psrlw", { MS, Ib } }, + { "(bad)", { XX } }, + { "psraw", { MS, Ib } }, + { "(bad)", { XX } }, + { "psllw", { MS, Ib } }, + { "(bad)", { XX } }, }, /* GRP13 */ { - { "fxsave", Ev, XX, XX }, - { "fxrstor", Ev, XX, XX }, - { "ldmxcsr", Ev, XX, XX }, - { "stmxcsr", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "lfence", OP_0fae, 0, XX, XX }, - { "mfence", OP_0fae, 0, XX, XX }, - { "clflush", OP_0fae, 0, XX, XX }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "psrld", { MS, Ib } }, + { "(bad)", { XX } }, + { "psrad", { MS, Ib } }, + { "(bad)", { XX } }, + { "pslld", { MS, Ib } }, + { "(bad)", { XX } }, }, /* GRP14 */ { - { "prefetchnta", Ev, XX, XX }, - { "prefetcht0", Ev, XX, XX }, - { "prefetcht1", Ev, XX, XX }, - { "prefetcht2", Ev, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "psrlq", { MS, Ib } }, + { "psrldq", { MS, Ib } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "psllq", { MS, Ib } }, + { "pslldq", { MS, Ib } }, + }, + /* GRP15 */ + { + { "fxsave", { Ev } }, + { "fxrstor", { Ev } }, + { "ldmxcsr", { Ev } }, + { "stmxcsr", { Ev } }, + { "(bad)", { XX } }, + { "lfence", { { OP_0fae, 0 } } }, + { "mfence", { { OP_0fae, 0 } } }, + { "clflush", { { OP_0fae, 0 } } }, + }, + /* GRP16 */ + { + { "prefetchnta", { Ev } }, + { "prefetcht0", { Ev } }, + { "prefetcht1", { Ev } }, + { "prefetcht2", { Ev } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, }, /* GRPAMD */ { - { "prefetch", Eb, XX, XX }, - { "prefetchw", Eb, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "prefetch", { Eb } }, + { "prefetchw", { Eb } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, }, /* GRPPADLCK1 */ { - { "xstore-rng", OP_0f07, 0, XX, XX }, - { "xcrypt-ecb", OP_0f07, 0, XX, XX }, - { "xcrypt-cbc", OP_0f07, 0, XX, XX }, - { "xcrypt-ctr", OP_0f07, 0, XX, XX }, - { "xcrypt-cfb", OP_0f07, 0, XX, XX }, - { "xcrypt-ofb", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, + { "xstore-rng", { { OP_0f07, 0 } } }, + { "xcrypt-ecb", { { OP_0f07, 0 } } }, + { "xcrypt-cbc", { { OP_0f07, 0 } } }, + { "xcrypt-ctr", { { OP_0f07, 0 } } }, + { "xcrypt-cfb", { { OP_0f07, 0 } } }, + { "xcrypt-ofb", { { OP_0f07, 0 } } }, + { "(bad)", { { OP_0f07, 0 } } }, + { "(bad)", { { OP_0f07, 0 } } }, }, /* GRPPADLCK2 */ { - { "montmul", OP_0f07, 0, XX, XX }, - { "xsha1", OP_0f07, 0, XX, XX }, - { "xsha256", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, - { "(bad)", OP_0f07, 0, XX, XX }, + { "montmul", { { OP_0f07, 0 } } }, + { "xsha1", { { OP_0f07, 0 } } }, + { "xsha256", { { OP_0f07, 0 } } }, + { "(bad)", { { OP_0f07, 0 } } }, + { "(bad)", { { OP_0f07, 0 } } }, + { "(bad)", { { OP_0f07, 0 } } }, + { "(bad)", { { OP_0f07, 0 } } }, + { "(bad)", { { OP_0f07, 0 } } }, } }; static const struct dis386 prefix_user_table[][4] = { /* PREGRP0 */ { - { "addps", XM, EX, XX }, - { "addss", XM, EX, XX }, - { "addpd", XM, EX, XX }, - { "addsd", XM, EX, XX }, + { "addps", { XM, EXx } }, + { "addss", { XM, EXd } }, + { "addpd", { XM, EXx } }, + { "addsd", { XM, EXq } }, }, /* PREGRP1 */ { - { "", XM, EX, OPSIMD }, /* See OP_SIMD_SUFFIX. */ - { "", XM, EX, OPSIMD }, - { "", XM, EX, OPSIMD }, - { "", XM, EX, OPSIMD }, + { "", { XM, EXx, OPSIMD } }, /* See OP_SIMD_SUFFIX. */ + { "", { XM, EXx, OPSIMD } }, + { "", { XM, EXx, OPSIMD } }, + { "", { XM, EXx, OPSIMD } }, }, /* PREGRP2 */ { - { "cvtpi2ps", XM, EM, XX }, - { "cvtsi2ssY", XM, Ev, XX }, - { "cvtpi2pd", XM, EM, XX }, - { "cvtsi2sdY", XM, Ev, XX }, + { "cvtpi2ps", { XM, EMC } }, + { "cvtsi2ssY", { XM, Ev } }, + { "cvtpi2pd", { XM, EMC } }, + { "cvtsi2sdY", { XM, Ev } }, }, /* PREGRP3 */ { - { "cvtps2pi", MX, EX, XX }, - { "cvtss2siY", Gv, EX, XX }, - { "cvtpd2pi", MX, EX, XX }, - { "cvtsd2siY", Gv, EX, XX }, + { "cvtps2pi", { MXC, EXx } }, + { "cvtss2siY", { Gv, EXx } }, + { "cvtpd2pi", { MXC, EXx } }, + { "cvtsd2siY", { Gv, EXx } }, }, /* PREGRP4 */ { - { "cvttps2pi", MX, EX, XX }, - { "cvttss2siY", Gv, EX, XX }, - { "cvttpd2pi", MX, EX, XX }, - { "cvttsd2siY", Gv, EX, XX }, + { "cvttps2pi", { MXC, EXx } }, + { "cvttss2siY", { Gv, EXx } }, + { "cvttpd2pi", { MXC, EXx } }, + { "cvttsd2siY", { Gv, EXx } }, }, /* PREGRP5 */ { - { "divps", XM, EX, XX }, - { "divss", XM, EX, XX }, - { "divpd", XM, EX, XX }, - { "divsd", XM, EX, XX }, + { "divps", { XM, EXx } }, + { "divss", { XM, EXx } }, + { "divpd", { XM, EXx } }, + { "divsd", { XM, EXx } }, }, /* PREGRP6 */ { - { "maxps", XM, EX, XX }, - { "maxss", XM, EX, XX }, - { "maxpd", XM, EX, XX }, - { "maxsd", XM, EX, XX }, + { "maxps", { XM, EXx } }, + { "maxss", { XM, EXx } }, + { "maxpd", { XM, EXx } }, + { "maxsd", { XM, EXx } }, }, /* PREGRP7 */ { - { "minps", XM, EX, XX }, - { "minss", XM, EX, XX }, - { "minpd", XM, EX, XX }, - { "minsd", XM, EX, XX }, + { "minps", { XM, EXx } }, + { "minss", { XM, EXx } }, + { "minpd", { XM, EXx } }, + { "minsd", { XM, EXx } }, }, /* PREGRP8 */ { - { "movups", XM, EX, XX }, - { "movss", XM, EX, XX }, - { "movupd", XM, EX, XX }, - { "movsd", XM, EX, XX }, + { "movups", { XM, EXx } }, + { "movss", { XM, EXx } }, + { "movupd", { XM, EXx } }, + { "movsd", { XM, EXx } }, }, /* PREGRP9 */ { - { "movups", EX, XM, XX }, - { "movss", EX, XM, XX }, - { "movupd", EX, XM, XX }, - { "movsd", EX, XM, XX }, + { "movups", { EXx, XM } }, + { "movss", { EXx, XM } }, + { "movupd", { EXx, XM } }, + { "movsd", { EXx, XM } }, }, /* PREGRP10 */ { - { "mulps", XM, EX, XX }, - { "mulss", XM, EX, XX }, - { "mulpd", XM, EX, XX }, - { "mulsd", XM, EX, XX }, + { "mulps", { XM, EXx } }, + { "mulss", { XM, EXx } }, + { "mulpd", { XM, EXx } }, + { "mulsd", { XM, EXx } }, }, /* PREGRP11 */ { - { "rcpps", XM, EX, XX }, - { "rcpss", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - { "(bad)", XM, EX, XX }, + { "rcpps", { XM, EXx } }, + { "rcpss", { XM, EXx } }, + { "(bad)", { XM, EXx } }, + { "(bad)", { XM, EXx } }, }, /* PREGRP12 */ { - { "rsqrtps", XM, EX, XX }, - { "rsqrtss", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - { "(bad)", XM, EX, XX }, + { "rsqrtps",{ XM, EXx } }, + { "rsqrtss",{ XM, EXx } }, + { "(bad)", { XM, EXx } }, + { "(bad)", { XM, EXx } }, }, /* PREGRP13 */ { - { "sqrtps", XM, EX, XX }, - { "sqrtss", XM, EX, XX }, - { "sqrtpd", XM, EX, XX }, - { "sqrtsd", XM, EX, XX }, + { "sqrtps", { XM, EXx } }, + { "sqrtss", { XM, EXx } }, + { "sqrtpd", { XM, EXx } }, + { "sqrtsd", { XM, EXx } }, }, /* PREGRP14 */ { - { "subps", XM, EX, XX }, - { "subss", XM, EX, XX }, - { "subpd", XM, EX, XX }, - { "subsd", XM, EX, XX }, + { "subps", { XM, EXx } }, + { "subss", { XM, EXx } }, + { "subpd", { XM, EXx } }, + { "subsd", { XM, EXx } }, }, /* PREGRP15 */ { - { "(bad)", XM, EX, XX }, - { "cvtdq2pd", XM, EX, XX }, - { "cvttpd2dq", XM, EX, XX }, - { "cvtpd2dq", XM, EX, XX }, + { "(bad)", { XM, EXx } }, + { "cvtdq2pd", { XM, EXq } }, + { "cvttpd2dq", { XM, EXx } }, + { "cvtpd2dq", { XM, EXx } }, }, /* PREGRP16 */ { - { "cvtdq2ps", XM, EX, XX }, - { "cvttps2dq",XM, EX, XX }, - { "cvtps2dq",XM, EX, XX }, - { "(bad)", XM, EX, XX }, + { "cvtdq2ps", { XM, EXx } }, + { "cvttps2dq", { XM, EXx } }, + { "cvtps2dq", { XM, EXx } }, + { "(bad)", { XM, EXx } }, }, /* PREGRP17 */ { - { "cvtps2pd", XM, EX, XX }, - { "cvtss2sd", XM, EX, XX }, - { "cvtpd2ps", XM, EX, XX }, - { "cvtsd2ss", XM, EX, XX }, + { "cvtps2pd", { XM, EXq } }, + { "cvtss2sd", { XM, EXx } }, + { "cvtpd2ps", { XM, EXx } }, + { "cvtsd2ss", { XM, EXx } }, }, /* PREGRP18 */ { - { "maskmovq", MX, MS, XX }, - { "(bad)", XM, EX, XX }, - { "maskmovdqu", XM, EX, XX }, - { "(bad)", XM, EX, XX }, + { "maskmovq", { MX, MS } }, + { "(bad)", { XM, EXx } }, + { "maskmovdqu", { XM, XS } }, + { "(bad)", { XM, EXx } }, }, /* PREGRP19 */ { - { "movq", MX, EM, XX }, - { "movdqu", XM, EX, XX }, - { "movdqa", XM, EX, XX }, - { "(bad)", XM, EX, XX }, + { "movq", { MX, EM } }, + { "movdqu", { XM, EXx } }, + { "movdqa", { XM, EXx } }, + { "(bad)", { XM, EXx } }, }, /* PREGRP20 */ { - { "movq", EM, MX, XX }, - { "movdqu", EX, XM, XX }, - { "movdqa", EX, XM, XX }, - { "(bad)", EX, XM, XX }, + { "movq", { EM, MX } }, + { "movdqu", { EXx, XM } }, + { "movdqa", { EXx, XM } }, + { "(bad)", { EXx, XM } }, }, /* PREGRP21 */ { - { "(bad)", EX, XM, XX }, - { "movq2dq", XM, MS, XX }, - { "movq", EX, XM, XX }, - { "movdq2q", MX, XS, XX }, + { "(bad)", { EXx, XM } }, + { "movq2dq",{ XM, MS } }, + { "movq", { EXx, XM } }, + { "movdq2q",{ MX, XS } }, }, /* PREGRP22 */ { - { "pshufw", MX, EM, Ib }, - { "pshufhw", XM, EX, Ib }, - { "pshufd", XM, EX, Ib }, - { "pshuflw", XM, EX, Ib }, + { "pshufw", { MX, EM, Ib } }, + { "pshufhw",{ XM, EXx, Ib } }, + { "pshufd", { XM, EXx, Ib } }, + { "pshuflw",{ XM, EXx, Ib } }, }, /* PREGRP23 */ { - { "movd", Edq, MX, XX }, - { "movq", XM, EX, XX }, - { "movd", Edq, XM, XX }, - { "(bad)", Ed, XM, XX }, + { "movd", { Edq, MX } }, + { "movq", { XM, EXx } }, + { "movd", { Edq, XM } }, + { "(bad)", { Ed, XM } }, }, /* PREGRP24 */ { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "punpckhqdq", XM, EX, XX }, - { "(bad)", XM, EX, XX }, + { "(bad)", { MX, EXx } }, + { "(bad)", { XM, EXx } }, + { "punpckhqdq", { XM, EXx } }, + { "(bad)", { XM, EXx } }, }, /* PREGRP25 */ { - { "movntq", EM, MX, XX }, - { "(bad)", EM, XM, XX }, - { "movntdq", EM, XM, XX }, - { "(bad)", EM, XM, XX }, + { "movntq", { EM, MX } }, + { "(bad)", { EM, XM } }, + { "movntdq",{ EM, XM } }, + { "(bad)", { EM, XM } }, }, /* PREGRP26 */ { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "punpcklqdq", XM, EX, XX }, - { "(bad)", XM, EX, XX }, + { "(bad)", { MX, EXx } }, + { "(bad)", { XM, EXx } }, + { "punpcklqdq", { XM, EXx } }, + { "(bad)", { XM, EXx } }, }, /* PREGRP27 */ { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "addsubpd", XM, EX, XX }, - { "addsubps", XM, EX, XX }, + { "(bad)", { MX, EXx } }, + { "(bad)", { XM, EXx } }, + { "addsubpd", { XM, EXx } }, + { "addsubps", { XM, EXx } }, }, /* PREGRP28 */ { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "haddpd", XM, EX, XX }, - { "haddps", XM, EX, XX }, + { "(bad)", { MX, EXx } }, + { "(bad)", { XM, EXx } }, + { "haddpd", { XM, EXx } }, + { "haddps", { XM, EXx } }, }, /* PREGRP29 */ { - { "(bad)", MX, EX, XX }, - { "(bad)", XM, EX, XX }, - { "hsubpd", XM, EX, XX }, - { "hsubps", XM, EX, XX }, + { "(bad)", { MX, EXx } }, + { "(bad)", { XM, EXx } }, + { "hsubpd", { XM, EXx } }, + { "hsubps", { XM, EXx } }, }, /* PREGRP30 */ { - { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */ - { "movsldup", XM, EX, XX }, - { "movlpd", XM, EX, XX }, - { "movddup", XM, EX, XX }, + { "movlpX", { XM, EXq, { SIMD_Fixup, 'h' } } }, /* really only 2 operands */ + { "movsldup", { XM, EXx } }, + { "movlpd", { XM, EXq } }, + { "movddup", { XM, EXq } }, }, /* PREGRP31 */ { - { "movhpX", XM, EX, SIMD_Fixup, 'l' }, - { "movshdup", XM, EX, XX }, - { "movhpd", XM, EX, XX }, - { "(bad)", XM, EX, XX }, + { "movhpX", { XM, EXq, { SIMD_Fixup, 'l' } } }, + { "movshdup", { XM, EXx } }, + { "movhpd", { XM, EXq } }, + { "(bad)", { XM, EXq } }, }, /* PREGRP32 */ { - { "(bad)", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - { "(bad)", XM, EX, XX }, - { "lddqu", XM, M, XX }, + { "(bad)", { XM, EXx } }, + { "(bad)", { XM, EXx } }, + { "(bad)", { XM, EXx } }, + { "lddqu", { XM, M } }, + }, + /* PREGRP33 */ + { + {"movntps", { Ev, XM } }, + {"movntss", { Ev, XM } }, + {"movntpd", { Ev, XM } }, + {"movntsd", { Ev, XM } }, + }, + + /* PREGRP34 */ + { + {"vmread", { Em, Gm } }, + {"(bad)", { XX } }, + {"extrq", { XS, Ib, Ib } }, + {"insertq", { XM, XS, Ib, Ib } }, + }, + + /* PREGRP35 */ + { + {"vmwrite", { Gm, Em } }, + {"(bad)", { XX } }, + {"extrq", { XM, XS } }, + {"insertq", { XM, XS } }, + }, + + /* PREGRP36 */ + { + { "bsrS", { Gv, Ev } }, + { "lzcntS", { Gv, Ev } }, + { "bsrS", { Gv, Ev } }, + { "(bad)", { XX } }, + }, + + /* PREGRP37 */ + { + { "(bad)", { XX } }, + { "popcntS", { Gv, Ev } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + }, + + /* PREGRP38 */ + { + { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, + { "pause", { XX } }, + { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, + { "(bad)", { XX } }, + }, + + /* PREGRP39 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pblendvb", {XM, EXx, XMM0 } }, + { "(bad)", { XX } }, + }, + + /* PREGRP40 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "blendvps", {XM, EXx, XMM0 } }, + { "(bad)", { XX } }, + }, + + /* PREGRP41 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "blendvpd", { XM, EXx, XMM0 } }, + { "(bad)", { XX } }, + }, + + /* PREGRP42 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "ptest", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP43 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovsxbw", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP44 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovsxbd", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP45 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovsxbq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP46 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovsxwd", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP47 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovsxwq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP48 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovsxdq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP49 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmuldq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP50 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pcmpeqq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP51 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "movntdqa", { XM, EM } }, + { "(bad)", { XX } }, + }, + + /* PREGRP52 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "packusdw", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP53 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovzxbw", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP54 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovzxbd", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP55 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovzxbq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP56 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovzxwd", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP57 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovzxwq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP58 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmovzxdq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP59 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pminsb", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP60 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pminsd", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP61 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pminuw", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP62 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pminud", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP63 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmaxsb", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP64 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmaxsd", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP65 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmaxuw", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP66 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmaxud", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP67 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pmulld", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP68 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "phminposuw", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP69 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "roundps", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP70 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "roundpd", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP71 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "roundss", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP72 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "roundsd", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP73 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "blendps", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP74 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "blendpd", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP75 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pblendw", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP76 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pextrb", { Edqb, XM, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP77 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pextrw", { Edqw, XM, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP78 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pextrK", { Edq, XM, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP79 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "extractps", { Edqd, XM, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP80 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pinsrb", { XM, Edqb, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP81 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "insertps", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP82 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pinsrK", { XM, Edq, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP83 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "dpps", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP84 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "dppd", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP85 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "mpsadbw", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP86 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pcmpgtq", { XM, EXx } }, + { "(bad)", { XX } }, + }, + + /* PREGRP87 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, + }, + + /* PREGRP88 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, + }, + + /* PREGRP89 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pcmpestrm", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP90 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pcmpestri", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP91 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pcmpistrm", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP92 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pcmpistri", { XM, EXx, Ib } }, + { "(bad)", { XX } }, + }, + + /* PREGRP93 */ + { + { "ucomiss",{ XM, EXd } }, + { "(bad)", { XX } }, + { "ucomisd",{ XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* PREGRP94 */ + { + { "comiss", { XM, EXd } }, + { "(bad)", { XX } }, + { "comisd", { XM, EXq } }, + { "(bad)", { XX } }, + }, + + /* PREGRP95 */ + { + { "punpcklbw",{ MX, EMd } }, + { "(bad)", { XX } }, + { "punpcklbw",{ MX, EMq } }, + { "(bad)", { XX } }, + }, + + /* PREGRP96 */ + { + { "punpcklwd",{ MX, EMd } }, + { "(bad)", { XX } }, + { "punpcklwd",{ MX, EMq } }, + { "(bad)", { XX } }, + }, + + /* PREGRP97 */ + { + { "punpckldq",{ MX, EMd } }, + { "(bad)", { XX } }, + { "punpckldq",{ MX, EMq } }, + { "(bad)", { XX } }, }, }; static const struct dis386 x86_64_table[][2] = { { - { "arpl", Ew, Gw, XX }, - { "movs{||lq|xd}", Gv, Ed, XX }, + { "pusha{P|}", { XX } }, + { "(bad)", { XX } }, + }, + { + { "popa{P|}", { XX } }, + { "(bad)", { XX } }, + }, + { + { "bound{S|}", { Gv, Ma } }, + { "(bad)", { XX } }, + }, + { + { "arpl", { Ew, Gw } }, + { "movs{||lq|xd}", { Gv, Ed } }, }, }; -static const struct dis386 three_byte_table[][32] = { +static const struct dis386 three_byte_table[][256] = { /* THREE_BYTE_0 */ { - { "pshufb", MX, EM, XX }, - { "phaddw", MX, EM, XX }, - { "phaddd", MX, EM, XX }, - { "phaddsw", MX, EM, XX }, - { "pmaddubsw", MX, EM, XX }, - { "phsubw", MX, EM, XX }, - { "phsubd", MX, EM, XX }, - { "phsubsw", MX, EM, XX }, - { "psignb", MX, EM, XX }, - { "psignw", MX, EM, XX }, - { "psignd", MX, EM, XX }, - { "pmulhrsw", MX, EM, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "pabsb", MX, EM, XX }, - { "pabsw", MX, EM, XX }, - { "pabsd", MX, EM, XX }, - { "(bad)", XX, XX, XX } + /* 00 */ + { "pshufb", { MX, EM } }, + { "phaddw", { MX, EM } }, + { "phaddd", { MX, EM } }, + { "phaddsw", { MX, EM } }, + { "pmaddubsw", { MX, EM } }, + { "phsubw", { MX, EM } }, + { "phsubd", { MX, EM } }, + { "phsubsw", { MX, EM } }, + /* 08 */ + { "psignb", { MX, EM } }, + { "psignw", { MX, EM } }, + { "psignd", { MX, EM } }, + { "pmulhrsw", { MX, EM } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 10 */ + { PREGRP39 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { PREGRP40 }, + { PREGRP41 }, + { "(bad)", { XX } }, + { PREGRP42 }, + /* 18 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "pabsb", { MX, EM } }, + { "pabsw", { MX, EM } }, + { "pabsd", { MX, EM } }, + { "(bad)", { XX } }, + /* 20 */ + { PREGRP43 }, + { PREGRP44 }, + { PREGRP45 }, + { PREGRP46 }, + { PREGRP47 }, + { PREGRP48 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 28 */ + { PREGRP49 }, + { PREGRP50 }, + { PREGRP51 }, + { PREGRP52 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 30 */ + { PREGRP53 }, + { PREGRP54 }, + { PREGRP55 }, + { PREGRP56 }, + { PREGRP57 }, + { PREGRP58 }, + { "(bad)", { XX } }, + { PREGRP86 }, + /* 38 */ + { PREGRP59 }, + { PREGRP60 }, + { PREGRP61 }, + { PREGRP62 }, + { PREGRP63 }, + { PREGRP64 }, + { PREGRP65 }, + { PREGRP66 }, + /* 40 */ + { PREGRP67 }, + { PREGRP68 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 48 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 50 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 58 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 60 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 68 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 70 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 78 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 80 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 88 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 90 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 98 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* e0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* e8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* f0 */ + { PREGRP87 }, + { PREGRP88 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* f8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, }, /* THREE_BYTE_1 */ { - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "palignr", MX, EM, Ib }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX } - }, + /* 00 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 08 */ + { PREGRP69 }, + { PREGRP70 }, + { PREGRP71 }, + { PREGRP72 }, + { PREGRP73 }, + { PREGRP74 }, + { PREGRP75 }, + { "palignr", { MX, EM, Ib } }, + /* 10 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { PREGRP76 }, + { PREGRP77 }, + { PREGRP78 }, + { PREGRP79 }, + /* 18 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 20 */ + { PREGRP80 }, + { PREGRP81 }, + { PREGRP82 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 28 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 30 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 38 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 40 */ + { PREGRP83 }, + { PREGRP84 }, + { PREGRP85 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 48 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 50 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 58 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 60 */ + { PREGRP89 }, + { PREGRP90 }, + { PREGRP91 }, + { PREGRP92 }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 68 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 70 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 78 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 80 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 88 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 90 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 98 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* e0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* e8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* f0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* f8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + } }; #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") @@ -1938,41 +3294,46 @@ ckprefix (void) static const char * prefix_name (int pref, int sizeflag) { + static const char *rexes [16] = + { + "rex", /* 0x40 */ + "rex.B", /* 0x41 */ + "rex.X", /* 0x42 */ + "rex.XB", /* 0x43 */ + "rex.R", /* 0x44 */ + "rex.RB", /* 0x45 */ + "rex.RX", /* 0x46 */ + "rex.RXB", /* 0x47 */ + "rex.W", /* 0x48 */ + "rex.WB", /* 0x49 */ + "rex.WX", /* 0x4a */ + "rex.WXB", /* 0x4b */ + "rex.WR", /* 0x4c */ + "rex.WRB", /* 0x4d */ + "rex.WRX", /* 0x4e */ + "rex.WRXB", /* 0x4f */ + }; + switch (pref) { /* REX prefixes family. */ case 0x40: - return "rex"; case 0x41: - return "rexZ"; case 0x42: - return "rexY"; case 0x43: - return "rexYZ"; case 0x44: - return "rexX"; case 0x45: - return "rexXZ"; case 0x46: - return "rexXY"; case 0x47: - return "rexXYZ"; case 0x48: - return "rex64"; case 0x49: - return "rex64Z"; case 0x4a: - return "rex64Y"; case 0x4b: - return "rex64YZ"; case 0x4c: - return "rex64X"; case 0x4d: - return "rex64XZ"; case 0x4e: - return "rex64XY"; case 0x4f: - return "rex64XYZ"; + return rexes [pref - 0x40]; case 0xf3: return "repz"; case 0xf2: @@ -2005,13 +3366,13 @@ prefix_name (int pref, int sizeflag) } } -static char op1out[100], op2out[100], op3out[100]; -static int op_ad, op_index[3]; +static char op_out[MAX_OPERANDS][100]; +static int op_ad, op_index[MAX_OPERANDS]; static int two_source_ops; -static bfd_vma op_address[3]; -static bfd_vma op_riprel[3]; +static bfd_vma op_address[MAX_OPERANDS]; +static bfd_vma op_riprel[MAX_OPERANDS]; static bfd_vma start_pc; - + /* * On the 386's of 1988, the maximum length of an instruction is 15 bytes. * (see topic "Redundant prefixes" in the "Differences from 8086" @@ -2054,17 +3415,39 @@ print_insn_i386 (bfd_vma pc, disassemble_info *info) return print_insn (pc, info); } +void +print_i386_disassembler_options (FILE *stream) +{ + fprintf (stream, _("\n\ +The following i386/x86-64 specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); + fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); + fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); + fprintf (stream, _(" att Display instruction in AT&T syntax\n")); + fprintf (stream, _(" intel Display instruction in Intel syntax\n")); + fprintf (stream, _(" addr64 Assume 64bit address size\n")); + fprintf (stream, _(" addr32 Assume 32bit address size\n")); + fprintf (stream, _(" addr16 Assume 16bit address size\n")); + fprintf (stream, _(" data32 Assume 32bit data size\n")); + fprintf (stream, _(" data16 Assume 16bit data size\n")); + fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); +} + static int print_insn (bfd_vma pc, disassemble_info *info) { const struct dis386 *dp; int i; - char *first, *second, *third; + char *op_txt[MAX_OPERANDS]; int needcomma; - unsigned char uses_SSE_prefix, uses_LOCK_prefix; + unsigned char uses_DATA_prefix, uses_LOCK_prefix; + unsigned char uses_REPNZ_prefix, uses_REPZ_prefix; int sizeflag; const char *p; struct dis_private priv; + unsigned char op; if (info->mach == bfd_mach_x86_64_intel_syntax || info->mach == bfd_mach_x86_64) @@ -2088,44 +3471,54 @@ print_insn (bfd_vma pc, disassemble_info *info) for (p = info->disassembler_options; p != NULL; ) { - if (strncmp (p, "x86-64", 6) == 0) + if (CONST_STRNEQ (p, "x86-64")) { address_mode = mode_64bit; priv.orig_sizeflag = AFLAG | DFLAG; } - else if (strncmp (p, "i386", 4) == 0) + else if (CONST_STRNEQ (p, "i386")) { address_mode = mode_32bit; priv.orig_sizeflag = AFLAG | DFLAG; } - else if (strncmp (p, "i8086", 5) == 0) + else if (CONST_STRNEQ (p, "i8086")) { address_mode = mode_16bit; priv.orig_sizeflag = 0; } - else if (strncmp (p, "intel", 5) == 0) + else if (CONST_STRNEQ (p, "intel")) { intel_syntax = 1; } - else if (strncmp (p, "att", 3) == 0) + else if (CONST_STRNEQ (p, "att")) { intel_syntax = 0; } - else if (strncmp (p, "addr", 4) == 0) + else if (CONST_STRNEQ (p, "addr")) { - if (p[4] == '1' && p[5] == '6') - priv.orig_sizeflag &= ~AFLAG; - else if (p[4] == '3' && p[5] == '2') - priv.orig_sizeflag |= AFLAG; + if (address_mode == mode_64bit) + { + if (p[4] == '3' && p[5] == '2') + priv.orig_sizeflag &= ~AFLAG; + else if (p[4] == '6' && p[5] == '4') + priv.orig_sizeflag |= AFLAG; + } + else + { + if (p[4] == '1' && p[5] == '6') + priv.orig_sizeflag &= ~AFLAG; + else if (p[4] == '3' && p[5] == '2') + priv.orig_sizeflag |= AFLAG; + } } - else if (strncmp (p, "data", 4) == 0) + else if (CONST_STRNEQ (p, "data")) { if (p[4] == '1' && p[5] == '6') priv.orig_sizeflag &= ~DFLAG; else if (p[4] == '3' && p[5] == '2') priv.orig_sizeflag |= DFLAG; } - else if (strncmp (p, "suffix", 6) == 0) + else if (CONST_STRNEQ (p, "suffix")) priv.orig_sizeflag |= SUFFIX_ALWAYS; p = strchr (p, ','); @@ -2171,11 +3564,11 @@ print_insn (bfd_vma pc, disassemble_info *info) priv.insn_start = pc; obuf[0] = 0; - op1out[0] = 0; - op2out[0] = 0; - op3out[0] = 0; - - op_index[0] = op_index[1] = op_index[2] = -1; + for (i = 0; i < MAX_OPERANDS; ++i) + { + op_out[i][0] = 0; + op_index[i] = -1; + } the_info = info; start_pc = pc; @@ -2231,33 +3624,63 @@ print_insn (bfd_vma pc, disassemble_info *info) return 1; } + op = 0; if (*codep == 0x0f) { + unsigned char threebyte; FETCH_DATA (info, codep + 2); - dp = &dis386_twobyte[*++codep]; + threebyte = *++codep; + dp = &dis386_twobyte[threebyte]; need_modrm = twobyte_has_modrm[*codep]; - uses_SSE_prefix = twobyte_uses_SSE_prefix[*codep]; + uses_DATA_prefix = twobyte_uses_DATA_prefix[*codep]; + uses_REPNZ_prefix = twobyte_uses_REPNZ_prefix[*codep]; + uses_REPZ_prefix = twobyte_uses_REPZ_prefix[*codep]; uses_LOCK_prefix = (*codep & ~0x02) == 0x20; + codep++; + if (dp->name == NULL && dp->op[0].bytemode == IS_3BYTE_OPCODE) + { + FETCH_DATA (info, codep + 2); + op = *codep++; + switch (threebyte) + { + case 0x38: + uses_DATA_prefix = threebyte_0x38_uses_DATA_prefix[op]; + uses_REPNZ_prefix = threebyte_0x38_uses_REPNZ_prefix[op]; + uses_REPZ_prefix = threebyte_0x38_uses_REPZ_prefix[op]; + break; + case 0x3a: + uses_DATA_prefix = threebyte_0x3a_uses_DATA_prefix[op]; + uses_REPNZ_prefix = threebyte_0x3a_uses_REPNZ_prefix[op]; + uses_REPZ_prefix = threebyte_0x3a_uses_REPZ_prefix[op]; + break; + default: + break; + } + } } else { dp = &dis386[*codep]; need_modrm = onebyte_has_modrm[*codep]; - uses_SSE_prefix = 0; + uses_DATA_prefix = 0; + uses_REPNZ_prefix = 0; + /* pause is 0xf3 0x90. */ + uses_REPZ_prefix = *codep == 0x90; uses_LOCK_prefix = 0; + codep++; } - codep++; - if (!uses_SSE_prefix && (prefixes & PREFIX_REPZ)) + if (!uses_REPZ_prefix && (prefixes & PREFIX_REPZ)) { oappend ("repz "); used_prefixes |= PREFIX_REPZ; } - if (!uses_SSE_prefix && (prefixes & PREFIX_REPNZ)) + if (!uses_REPNZ_prefix && (prefixes & PREFIX_REPNZ)) { oappend ("repnz "); used_prefixes |= PREFIX_REPNZ; } + if (!uses_LOCK_prefix && (prefixes & PREFIX_LOCK)) { oappend ("lock "); @@ -2267,7 +3690,7 @@ print_insn (bfd_vma pc, disassemble_info *info) if (prefixes & PREFIX_ADDR) { sizeflag ^= AFLAG; - if (dp->bytemode3 != loop_jcxz_mode || intel_syntax) + if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) { if ((sizeflag & AFLAG) || address_mode == mode_64bit) oappend ("addr32 "); @@ -2277,11 +3700,11 @@ print_insn (bfd_vma pc, disassemble_info *info) } } - if (!uses_SSE_prefix && (prefixes & PREFIX_DATA)) + if (!uses_DATA_prefix && (prefixes & PREFIX_DATA)) { sizeflag ^= DFLAG; - if (dp->bytemode3 == cond_jump_mode - && dp->bytemode1 == v_mode + if (dp->op[2].bytemode == cond_jump_mode + && dp->op[0].bytemode == v_mode && !intel_syntax) { if (sizeflag & DFLAG) @@ -2292,23 +3715,22 @@ print_insn (bfd_vma pc, disassemble_info *info) } } - if (dp->name == NULL && dp->bytemode1 == IS_3BYTE_OPCODE) + if (dp->name == NULL && dp->op[0].bytemode == IS_3BYTE_OPCODE) { - FETCH_DATA (info, codep + 2); - dp = &three_byte_table[dp->bytemode2][*codep++]; - mod = (*codep >> 6) & 3; - reg = (*codep >> 3) & 7; - rm = *codep & 7; + dp = &three_byte_table[dp->op[1].bytemode][op]; + modrm.mod = (*codep >> 6) & 3; + modrm.reg = (*codep >> 3) & 7; + modrm.rm = *codep & 7; } else if (need_modrm) { FETCH_DATA (info, codep + 1); - mod = (*codep >> 6) & 3; - reg = (*codep >> 3) & 7; - rm = *codep & 7; + modrm.mod = (*codep >> 6) & 3; + modrm.reg = (*codep >> 3) & 7; + modrm.rm = *codep & 7; } - if (dp->name == NULL && dp->bytemode1 == FLOATCODE) + if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) { dofloat (sizeflag); } @@ -2317,10 +3739,10 @@ print_insn (bfd_vma pc, disassemble_info *info) int index; if (dp->name == NULL) { - switch (dp->bytemode1) + switch (dp->op[0].bytemode) { case USE_GROUPS: - dp = &grps[dp->bytemode2][reg]; + dp = &grps[dp->op[1].bytemode][modrm.reg]; break; case USE_PREFIX_USER_TABLE: @@ -2330,22 +3752,24 @@ print_insn (bfd_vma pc, disassemble_info *info) index = 1; else { - used_prefixes |= (prefixes & PREFIX_DATA); - if (prefixes & PREFIX_DATA) - index = 2; + /* We should check PREFIX_REPNZ and PREFIX_REPZ + before PREFIX_DATA. */ + used_prefixes |= (prefixes & PREFIX_REPNZ); + if (prefixes & PREFIX_REPNZ) + index = 3; else { - used_prefixes |= (prefixes & PREFIX_REPNZ); - if (prefixes & PREFIX_REPNZ) - index = 3; + used_prefixes |= (prefixes & PREFIX_DATA); + if (prefixes & PREFIX_DATA) + index = 2; } } - dp = &prefix_user_table[dp->bytemode2][index]; + dp = &prefix_user_table[dp->op[1].bytemode][index]; break; case X86_64_SPECIAL: index = address_mode == mode_64bit ? 1 : 0; - dp = &x86_64_table[dp->bytemode2][index]; + dp = &x86_64_table[dp->op[1].bytemode][index]; break; default: @@ -2355,21 +3779,14 @@ print_insn (bfd_vma pc, disassemble_info *info) } if (putop (dp->name, sizeflag) == 0) - { - obufp = op1out; - op_ad = 2; - if (dp->op1) - (*dp->op1) (dp->bytemode1, sizeflag); - - obufp = op2out; - op_ad = 1; - if (dp->op2) - (*dp->op2) (dp->bytemode2, sizeflag); - - obufp = op3out; - op_ad = 0; - if (dp->op3) - (*dp->op3) (dp->bytemode3, sizeflag); + { + for (i = 0; i < MAX_OPERANDS; ++i) + { + obufp = op_out[i]; + op_ad = MAX_OPERANDS - 1 - i; + if (dp->op[i].rtn) + (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); + } } } @@ -2406,53 +3823,47 @@ print_insn (bfd_vma pc, disassemble_info *info) order as the intel book; everything else is printed in reverse order. */ if (intel_syntax || two_source_ops) { - first = op1out; - second = op2out; - third = op3out; - op_ad = op_index[0]; - op_index[0] = op_index[2]; - op_index[2] = op_ad; + bfd_vma riprel; + + for (i = 0; i < MAX_OPERANDS; ++i) + op_txt[i] = op_out[i]; + + for (i = 0; i < (MAX_OPERANDS >> 1); ++i) + { + op_ad = op_index[i]; + op_index[i] = op_index[MAX_OPERANDS - 1 - i]; + op_index[MAX_OPERANDS - 1 - i] = op_ad; + riprel = op_riprel[i]; + op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; + op_riprel[MAX_OPERANDS - 1 - i] = riprel; + } } else { - first = op3out; - second = op2out; - third = op1out; + for (i = 0; i < MAX_OPERANDS; ++i) + op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; } + needcomma = 0; - if (*first) - { - if (op_index[0] != -1 && !op_riprel[0]) - (*info->print_address_func) ((bfd_vma) op_address[op_index[0]], info); - else - (*info->fprintf_func) (info->stream, "%s", first); - needcomma = 1; - } - if (*second) - { - if (needcomma) - (*info->fprintf_func) (info->stream, ","); - if (op_index[1] != -1 && !op_riprel[1]) - (*info->print_address_func) ((bfd_vma) op_address[op_index[1]], info); - else - (*info->fprintf_func) (info->stream, "%s", second); - needcomma = 1; - } - if (*third) - { - if (needcomma) - (*info->fprintf_func) (info->stream, ","); - if (op_index[2] != -1 && !op_riprel[2]) - (*info->print_address_func) ((bfd_vma) op_address[op_index[2]], info); - else - (*info->fprintf_func) (info->stream, "%s", third); - } - for (i = 0; i < 3; i++) + for (i = 0; i < MAX_OPERANDS; ++i) + if (*op_txt[i]) + { + if (needcomma) + (*info->fprintf_func) (info->stream, ","); + if (op_index[i] != -1 && !op_riprel[i]) + (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); + else + (*info->fprintf_func) (info->stream, "%s", op_txt[i]); + needcomma = 1; + } + + for (i = 0; i < MAX_OPERANDS; i++) if (op_index[i] != -1 && op_riprel[i]) { (*info->fprintf_func) (info->stream, " # "); (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep + op_address[op_index[i]]), info); + break; } return codep - priv.the_buffer; } @@ -2607,37 +4018,37 @@ static const unsigned char float_mem_mode[] = { q_mode }; -#define ST OP_ST, 0 -#define STi OP_STi, 0 +#define ST { OP_ST, 0 } +#define STi { OP_STi, 0 } -#define FGRPd9_2 NULL, NULL, 0, NULL, 0, NULL, 0 -#define FGRPd9_4 NULL, NULL, 1, NULL, 0, NULL, 0 -#define FGRPd9_5 NULL, NULL, 2, NULL, 0, NULL, 0 -#define FGRPd9_6 NULL, NULL, 3, NULL, 0, NULL, 0 -#define FGRPd9_7 NULL, NULL, 4, NULL, 0, NULL, 0 -#define FGRPda_5 NULL, NULL, 5, NULL, 0, NULL, 0 -#define FGRPdb_4 NULL, NULL, 6, NULL, 0, NULL, 0 -#define FGRPde_3 NULL, NULL, 7, NULL, 0, NULL, 0 -#define FGRPdf_4 NULL, NULL, 8, NULL, 0, NULL, 0 +#define FGRPd9_2 NULL, { { NULL, 0 } } +#define FGRPd9_4 NULL, { { NULL, 1 } } +#define FGRPd9_5 NULL, { { NULL, 2 } } +#define FGRPd9_6 NULL, { { NULL, 3 } } +#define FGRPd9_7 NULL, { { NULL, 4 } } +#define FGRPda_5 NULL, { { NULL, 5 } } +#define FGRPdb_4 NULL, { { NULL, 6 } } +#define FGRPde_3 NULL, { { NULL, 7 } } +#define FGRPdf_4 NULL, { { NULL, 8 } } static const struct dis386 float_reg[][8] = { /* d8 */ { - { "fadd", ST, STi, XX }, - { "fmul", ST, STi, XX }, - { "fcom", STi, XX, XX }, - { "fcomp", STi, XX, XX }, - { "fsub", ST, STi, XX }, - { "fsubr", ST, STi, XX }, - { "fdiv", ST, STi, XX }, - { "fdivr", ST, STi, XX }, + { "fadd", { ST, STi } }, + { "fmul", { ST, STi } }, + { "fcom", { STi } }, + { "fcomp", { STi } }, + { "fsub", { ST, STi } }, + { "fsubr", { ST, STi } }, + { "fdiv", { ST, STi } }, + { "fdivr", { ST, STi } }, }, /* d9 */ { - { "fld", STi, XX, XX }, - { "fxch", STi, XX, XX }, + { "fld", { STi } }, + { "fxch", { STi } }, { FGRPd9_2 }, - { "(bad)", XX, XX, XX }, + { "(bad)", { XX } }, { FGRPd9_4 }, { FGRPd9_5 }, { FGRPd9_6 }, @@ -2645,83 +4056,83 @@ static const struct dis386 float_reg[][8] = { }, /* da */ { - { "fcmovb", ST, STi, XX }, - { "fcmove", ST, STi, XX }, - { "fcmovbe",ST, STi, XX }, - { "fcmovu", ST, STi, XX }, - { "(bad)", XX, XX, XX }, + { "fcmovb", { ST, STi } }, + { "fcmove", { ST, STi } }, + { "fcmovbe",{ ST, STi } }, + { "fcmovu", { ST, STi } }, + { "(bad)", { XX } }, { FGRPda_5 }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, }, /* db */ { - { "fcmovnb",ST, STi, XX }, - { "fcmovne",ST, STi, XX }, - { "fcmovnbe",ST, STi, XX }, - { "fcmovnu",ST, STi, XX }, + { "fcmovnb",{ ST, STi } }, + { "fcmovne",{ ST, STi } }, + { "fcmovnbe",{ ST, STi } }, + { "fcmovnu",{ ST, STi } }, { FGRPdb_4 }, - { "fucomi", ST, STi, XX }, - { "fcomi", ST, STi, XX }, - { "(bad)", XX, XX, XX }, + { "fucomi", { ST, STi } }, + { "fcomi", { ST, STi } }, + { "(bad)", { XX } }, }, /* dc */ { - { "fadd", STi, ST, XX }, - { "fmul", STi, ST, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, -#if UNIXWARE_COMPAT - { "fsub", STi, ST, XX }, - { "fsubr", STi, ST, XX }, - { "fdiv", STi, ST, XX }, - { "fdivr", STi, ST, XX }, + { "fadd", { STi, ST } }, + { "fmul", { STi, ST } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, +#if SYSV386_COMPAT + { "fsub", { STi, ST } }, + { "fsubr", { STi, ST } }, + { "fdiv", { STi, ST } }, + { "fdivr", { STi, ST } }, #else - { "fsubr", STi, ST, XX }, - { "fsub", STi, ST, XX }, - { "fdivr", STi, ST, XX }, - { "fdiv", STi, ST, XX }, + { "fsubr", { STi, ST } }, + { "fsub", { STi, ST } }, + { "fdivr", { STi, ST } }, + { "fdiv", { STi, ST } }, #endif }, /* dd */ { - { "ffree", STi, XX, XX }, - { "(bad)", XX, XX, XX }, - { "fst", STi, XX, XX }, - { "fstp", STi, XX, XX }, - { "fucom", STi, XX, XX }, - { "fucomp", STi, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "ffree", { STi } }, + { "(bad)", { XX } }, + { "fst", { STi } }, + { "fstp", { STi } }, + { "fucom", { STi } }, + { "fucomp", { STi } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, }, /* de */ { - { "faddp", STi, ST, XX }, - { "fmulp", STi, ST, XX }, - { "(bad)", XX, XX, XX }, + { "faddp", { STi, ST } }, + { "fmulp", { STi, ST } }, + { "(bad)", { XX } }, { FGRPde_3 }, -#if UNIXWARE_COMPAT - { "fsubp", STi, ST, XX }, - { "fsubrp", STi, ST, XX }, - { "fdivp", STi, ST, XX }, - { "fdivrp", STi, ST, XX }, +#if SYSV386_COMPAT + { "fsubp", { STi, ST } }, + { "fsubrp", { STi, ST } }, + { "fdivp", { STi, ST } }, + { "fdivrp", { STi, ST } }, #else - { "fsubrp", STi, ST, XX }, - { "fsubp", STi, ST, XX }, - { "fdivrp", STi, ST, XX }, - { "fdivp", STi, ST, XX }, + { "fsubrp", { STi, ST } }, + { "fsubp", { STi, ST } }, + { "fdivrp", { STi, ST } }, + { "fdivp", { STi, ST } }, #endif }, /* df */ { - { "ffreep", STi, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "ffreep", { STi } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, { FGRPdf_4 }, - { "fucomip",ST, STi, XX }, - { "fcomip", ST, STi, XX }, - { "(bad)", XX, XX, XX }, + { "fucomip", { ST, STi } }, + { "fcomip", { ST, STi } }, + { "(bad)", { XX } }, }, }; @@ -2781,12 +4192,12 @@ dofloat (int sizeflag) floatop = codep[-1]; - if (mod != 3) + if (modrm.mod != 3) { - int fp_indx = (floatop - 0xd8) * 8 + reg; + int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; putop (float_mem[fp_indx], sizeflag); - obufp = op1out; + obufp = op_out[0]; op_ad = 2; OP_E (float_mem_mode[fp_indx], sizeflag); return; @@ -2795,28 +4206,28 @@ dofloat (int sizeflag) MODRM_CHECK; codep++; - dp = &float_reg[floatop - 0xd8][reg]; + dp = &float_reg[floatop - 0xd8][modrm.reg]; if (dp->name == NULL) { - putop (fgrps[dp->bytemode1][rm], sizeflag); + putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); /* Instruction fnstsw is only one with strange arg. */ if (floatop == 0xdf && codep[-1] == 0xe0) - strcpy (op1out, names16[0]); + strcpy (op_out[0], names16[0]); } else { putop (dp->name, sizeflag); - obufp = op1out; + obufp = op_out[0]; op_ad = 2; - if (dp->op1) - (*dp->op1) (dp->bytemode1, sizeflag); + if (dp->op[0].rtn) + (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); - obufp = op2out; + obufp = op_out[1]; op_ad = 1; - if (dp->op2) - (*dp->op2) (dp->bytemode2, sizeflag); + if (dp->op[1].rtn) + (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); } } @@ -2829,7 +4240,7 @@ OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) static void OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { - sprintf (scratchbuf, "%%st(%d)", rm); + sprintf (scratchbuf, "%%st(%d)", modrm.rm); oappend (scratchbuf + intel_syntax); } @@ -2885,7 +4296,7 @@ putop (const char *template, int sizeflag) case 'A': if (intel_syntax) break; - if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) + if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) *obufp++ = 'b'; break; case 'B': @@ -2906,6 +4317,23 @@ putop (const char *template, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case 'D': + if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) + break; + USED_REX (REX_W); + if (modrm.mod == 3) + { + if (rex & REX_W) + *obufp++ = 'q'; + else if (sizeflag & DFLAG) + *obufp++ = intel_syntax ? 'd' : 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + else + *obufp++ = 'w'; + break; case 'E': /* For jcxz/jecxz */ if (address_mode == mode_64bit) { @@ -2931,6 +4359,16 @@ putop (const char *template, int sizeflag) used_prefixes |= (prefixes & PREFIX_ADDR); } break; + case 'G': + if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) + break; + if ((rex & REX_W) || (sizeflag & DFLAG)) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; case 'H': if (intel_syntax) break; @@ -2951,6 +4389,13 @@ putop (const char *template, int sizeflag) break; *obufp++ = 'l'; break; + case 'K': + USED_REX (REX_W); + if (rex & REX_W) + *obufp++ = 'q'; + else + *obufp++ = 'd'; + break; case 'Z': if (intel_syntax) break; @@ -2973,11 +4418,15 @@ putop (const char *template, int sizeflag) used_prefixes |= PREFIX_FWAIT; break; case 'O': - USED_REX (REX_MODE64); - if (rex & REX_MODE64) + USED_REX (REX_W); + if (rex & REX_W) *obufp++ = 'o'; + else if (intel_syntax && (sizeflag & DFLAG)) + *obufp++ = 'q'; else *obufp++ = 'd'; + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); break; case 'T': if (intel_syntax) @@ -2992,11 +4441,11 @@ putop (const char *template, int sizeflag) if (intel_syntax) break; if ((prefixes & PREFIX_DATA) - || (rex & REX_MODE64) + || (rex & REX_W) || (sizeflag & SUFFIX_ALWAYS)) { - USED_REX (REX_MODE64); - if (rex & REX_MODE64) + USED_REX (REX_W); + if (rex & REX_W) *obufp++ = 'q'; else { @@ -3013,7 +4462,7 @@ putop (const char *template, int sizeflag) break; if (address_mode == mode_64bit && (sizeflag & DFLAG)) { - if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) + if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) *obufp++ = 'q'; break; } @@ -3021,10 +4470,10 @@ putop (const char *template, int sizeflag) case 'Q': if (intel_syntax && !alt) break; - USED_REX (REX_MODE64); - if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) + USED_REX (REX_W); + if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) { - if (rex & REX_MODE64) + if (rex & REX_W) *obufp++ = 'q'; else { @@ -3037,35 +4486,22 @@ putop (const char *template, int sizeflag) } break; case 'R': - USED_REX (REX_MODE64); - if (intel_syntax) + USED_REX (REX_W); + if (rex & REX_W) + *obufp++ = 'q'; + else if (sizeflag & DFLAG) { - if (rex & REX_MODE64) - { - *obufp++ = 'q'; - *obufp++ = 't'; - } - else if (sizeflag & DFLAG) - { + if (intel_syntax) *obufp++ = 'd'; - *obufp++ = 'q'; - } else - { - *obufp++ = 'w'; - *obufp++ = 'd'; - } + *obufp++ = 'l'; } else - { - if (rex & REX_MODE64) - *obufp++ = 'q'; - else if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - } - if (!(rex & REX_MODE64)) + *obufp++ = 'w'; + if (intel_syntax && !p[1] + && ((rex & REX_W) || (sizeflag & DFLAG))) + *obufp++ = 'e'; + if (!(rex & REX_W)) used_prefixes |= (prefixes & PREFIX_DATA); break; case 'V': @@ -3083,7 +4519,7 @@ putop (const char *template, int sizeflag) break; if (sizeflag & SUFFIX_ALWAYS) { - if (rex & REX_MODE64) + if (rex & REX_W) *obufp++ = 'q'; else { @@ -3105,40 +4541,28 @@ putop (const char *template, int sizeflag) case 'Y': if (intel_syntax) break; - if (rex & REX_MODE64) + if (rex & REX_W) { - USED_REX (REX_MODE64); + USED_REX (REX_W); *obufp++ = 'q'; } break; /* implicit operand size 'l' for i386 or 'q' for x86-64 */ case 'W': /* operand size flag for cwtl, cbtw */ - USED_REX (0); - if (rex) - *obufp++ = 'l'; + USED_REX (REX_W); + if (rex & REX_W) + { + if (intel_syntax) + *obufp++ = 'd'; + else + *obufp++ = 'l'; + } else if (sizeflag & DFLAG) *obufp++ = 'w'; else *obufp++ = 'b'; - if (intel_syntax) - { - if (rex) - { - *obufp++ = 'q'; - *obufp++ = 'e'; - } - if (sizeflag & DFLAG) - { - *obufp++ = 'd'; - *obufp++ = 'e'; - } - else - { - *obufp++ = 'w'; - } - } - if (!rex) + if (!(rex & REX_W)) used_prefixes |= (prefixes & PREFIX_DATA); break; } @@ -3255,12 +4679,57 @@ print_operand_value (char *buf, int hex, bfd_vma disp) } } +/* Put DISP in BUF as signed hex number. */ + +static void +print_displacement (char *buf, bfd_vma disp) +{ + bfd_signed_vma val = disp; + char tmp[30]; + int i, j = 0; + + if (val < 0) + { + buf[j++] = '-'; + val = -disp; + + /* Check for possible overflow. */ + if (val < 0) + { + switch (address_mode) + { + case mode_64bit: + strcpy (buf + j, "0x8000000000000000"); + break; + case mode_32bit: + strcpy (buf + j, "0x80000000"); + break; + case mode_16bit: + strcpy (buf + j, "0x8000"); + break; + } + return; + } + } + + buf[j++] = '0'; + buf[j++] = 'x'; + + sprintf_vma (tmp, val); + for (i = 0; tmp[i] == '0'; i++) + continue; + if (tmp[i] == '\0') + i--; + strcpy (buf + j, tmp + i); +} + static void intel_operand_size (int bytemode, int sizeflag) { switch (bytemode) { case b_mode: + case dqb_mode: oappend ("BYTE PTR "); break; case w_mode: @@ -3277,8 +4746,8 @@ intel_operand_size (int bytemode, int sizeflag) /* FALLTHRU */ case v_mode: case dq_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) + USED_REX (REX_W); + if (rex & REX_W) oappend ("QWORD PTR "); else if ((sizeflag & DFLAG) || bytemode == dq_mode) oappend ("DWORD PTR "); @@ -3286,7 +4755,15 @@ intel_operand_size (int bytemode, int sizeflag) oappend ("WORD PTR "); used_prefixes |= (prefixes & PREFIX_DATA); break; + case z_mode: + if ((rex & REX_W) || (sizeflag & DFLAG)) + *obufp++ = 'D'; + oappend ("WORD PTR "); + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; case d_mode: + case dqd_mode: oappend ("DWORD PTR "); break; case q_mode: @@ -3311,6 +4788,9 @@ intel_operand_size (int bytemode, int sizeflag) case x_mode: oappend ("XMMWORD PTR "); break; + case o_mode: + oappend ("OWORD PTR "); + break; default: break; } @@ -3322,44 +4802,44 @@ OP_E (int bytemode, int sizeflag) bfd_vma disp; int add = 0; int riprel = 0; - USED_REX (REX_EXTZ); - if (rex & REX_EXTZ) + USED_REX (REX_B); + if (rex & REX_B) add += 8; /* Skip mod/rm byte. */ MODRM_CHECK; codep++; - if (mod == 3) + if (modrm.mod == 3) { switch (bytemode) { case b_mode: USED_REX (0); if (rex) - oappend (names8rex[rm + add]); + oappend (names8rex[modrm.rm + add]); else - oappend (names8[rm + add]); + oappend (names8[modrm.rm + add]); break; case w_mode: - oappend (names16[rm + add]); + oappend (names16[modrm.rm + add]); break; case d_mode: - oappend (names32[rm + add]); + oappend (names32[modrm.rm + add]); break; case q_mode: - oappend (names64[rm + add]); + oappend (names64[modrm.rm + add]); break; case m_mode: if (address_mode == mode_64bit) - oappend (names64[rm + add]); + oappend (names64[modrm.rm + add]); else - oappend (names32[rm + add]); + oappend (names32[modrm.rm + add]); break; case stack_v_mode: if (address_mode == mode_64bit && (sizeflag & DFLAG)) { - oappend (names64[rm + add]); + oappend (names64[modrm.rm + add]); used_prefixes |= (prefixes & PREFIX_DATA); break; } @@ -3367,14 +4847,16 @@ OP_E (int bytemode, int sizeflag) /* FALLTHRU */ case v_mode: case dq_mode: + case dqb_mode: + case dqd_mode: case dqw_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - oappend (names64[rm + add]); + USED_REX (REX_W); + if (rex & REX_W) + oappend (names64[modrm.rm + add]); else if ((sizeflag & DFLAG) || bytemode != v_mode) - oappend (names32[rm + add]); + oappend (names32[modrm.rm + add]); else - oappend (names16[rm + add]); + oappend (names16[modrm.rm + add]); used_prefixes |= (prefixes & PREFIX_DATA); break; case 0: @@ -3391,8 +4873,10 @@ OP_E (int bytemode, int sizeflag) intel_operand_size (bytemode, sizeflag); append_seg (); - if ((sizeflag & AFLAG) || address_mode == mode_64bit) /* 32 bit address mode */ + if ((sizeflag & AFLAG) || address_mode == mode_64bit) { + /* 32/64 bit address mode */ + int havedisp; int havesib; int havebase; int base; @@ -3401,7 +4885,7 @@ OP_E (int bytemode, int sizeflag) havesib = 0; havebase = 1; - base = rm; + base = modrm.rm; if (base == 4) { @@ -3412,14 +4896,14 @@ OP_E (int bytemode, int sizeflag) /* When INDEX == 0x4 in 32 bit mode, SCALE is ignored. */ scale = (*codep >> 6) & 3; base = *codep & 7; - USED_REX (REX_EXTY); - if (rex & REX_EXTY) + USED_REX (REX_X); + if (rex & REX_X) index += 8; codep++; } base += add; - switch (mod) + switch (modrm.mod) { case 0: if ((base & 7) == 5) @@ -3441,10 +4925,15 @@ OP_E (int bytemode, int sizeflag) break; } + havedisp = havebase || (havesib && (index != 4 || scale != 0)); + if (!intel_syntax) - if (mod != 0 || (base & 7) == 5) + if (modrm.mod != 0 || (base & 7) == 5) { - print_operand_value (scratchbuf, !riprel, disp); + if (havedisp || riprel) + print_displacement (scratchbuf, disp); + else + print_operand_value (scratchbuf, 1, disp); oappend (scratchbuf); if (riprel) { @@ -3453,11 +4942,14 @@ OP_E (int bytemode, int sizeflag) } } - if (havebase || (havesib && (index != 4 || scale != 0))) + if (havedisp || (intel_syntax && riprel)) { *obufp++ = open_char; if (intel_syntax && riprel) - oappend ("rip + "); + { + set_op (disp, 1); + oappend ("rip"); + } *obufp = '\0'; if (havebase) oappend (address_mode == mode_64bit && (sizeflag & AFLAG) @@ -3482,21 +4974,22 @@ OP_E (int bytemode, int sizeflag) oappend (scratchbuf); } } - if (intel_syntax && disp) + if (intel_syntax + && (disp || modrm.mod != 0 || (base & 7) == 5)) { - if ((bfd_signed_vma) disp > 0) + if ((bfd_signed_vma) disp >= 0) { *obufp++ = '+'; *obufp = '\0'; } - else if (mod != 1) + else if (modrm.mod != 1) { *obufp++ = '-'; *obufp = '\0'; disp = - (bfd_signed_vma) disp; } - print_operand_value (scratchbuf, mod != 1, disp); + print_displacement (scratchbuf, disp); oappend (scratchbuf); } @@ -3505,7 +4998,7 @@ OP_E (int bytemode, int sizeflag) } else if (intel_syntax) { - if (mod != 0 || (base & 7) == 5) + if (modrm.mod != 0 || (base & 7) == 5) { if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES | PREFIX_FS | PREFIX_GS)) @@ -3522,10 +5015,10 @@ OP_E (int bytemode, int sizeflag) } else { /* 16 bit address mode */ - switch (mod) + switch (modrm.mod) { case 0: - if (rm == 6) + if (modrm.rm == 6) { disp = get16 (); if ((disp & 0x8000) != 0) @@ -3546,32 +5039,33 @@ OP_E (int bytemode, int sizeflag) } if (!intel_syntax) - if (mod != 0 || rm == 6) + if (modrm.mod != 0 || modrm.rm == 6) { - print_operand_value (scratchbuf, 0, disp); + print_displacement (scratchbuf, disp); oappend (scratchbuf); } - if (mod != 0 || rm != 6) + if (modrm.mod != 0 || modrm.rm != 6) { *obufp++ = open_char; *obufp = '\0'; - oappend (index16[rm]); - if (intel_syntax && disp) + oappend (index16[modrm.rm]); + if (intel_syntax + && (disp || modrm.mod != 0 || modrm.rm == 6)) { - if ((bfd_signed_vma) disp > 0) + if ((bfd_signed_vma) disp >= 0) { *obufp++ = '+'; *obufp = '\0'; } - else if (mod != 1) + else if (modrm.mod != 1) { *obufp++ = '-'; *obufp = '\0'; disp = - (bfd_signed_vma) disp; } - print_operand_value (scratchbuf, mod != 1, disp); + print_displacement (scratchbuf, disp); oappend (scratchbuf); } @@ -3598,44 +5092,46 @@ static void OP_G (int bytemode, int sizeflag) { int add = 0; - USED_REX (REX_EXTX); - if (rex & REX_EXTX) + USED_REX (REX_R); + if (rex & REX_R) add += 8; switch (bytemode) { case b_mode: USED_REX (0); if (rex) - oappend (names8rex[reg + add]); + oappend (names8rex[modrm.reg + add]); else - oappend (names8[reg + add]); + oappend (names8[modrm.reg + add]); break; case w_mode: - oappend (names16[reg + add]); + oappend (names16[modrm.reg + add]); break; case d_mode: - oappend (names32[reg + add]); + oappend (names32[modrm.reg + add]); break; case q_mode: - oappend (names64[reg + add]); + oappend (names64[modrm.reg + add]); break; case v_mode: case dq_mode: + case dqb_mode: + case dqd_mode: case dqw_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - oappend (names64[reg + add]); + USED_REX (REX_W); + if (rex & REX_W) + oappend (names64[modrm.reg + add]); else if ((sizeflag & DFLAG) || bytemode != v_mode) - oappend (names32[reg + add]); + oappend (names32[modrm.reg + add]); else - oappend (names16[reg + add]); + oappend (names16[modrm.reg + add]); used_prefixes |= (prefixes & PREFIX_DATA); break; case m_mode: if (address_mode == mode_64bit) - oappend (names64[reg + add]); + oappend (names64[modrm.reg + add]); else - oappend (names32[reg + add]); + oappend (names32[modrm.reg + add]); break; default: oappend (INTERNAL_DISASSEMBLER_ERROR); @@ -3730,18 +5226,12 @@ OP_REG (int code, int sizeflag) { const char *s; int add = 0; - USED_REX (REX_EXTZ); - if (rex & REX_EXTZ) + USED_REX (REX_B); + if (rex & REX_B) add = 8; switch (code) { - case indir_dx_reg: - if (intel_syntax) - s = "[dx]"; - else - s = "(%dx)"; - break; case ax_reg: case cx_reg: case dx_reg: case bx_reg: case sp_reg: case bp_reg: case si_reg: case di_reg: s = names16[code - ax_reg + add]; @@ -3769,8 +5259,8 @@ OP_REG (int code, int sizeflag) /* Fall through. */ case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) + USED_REX (REX_W); + if (rex & REX_W) s = names64[code - eAX_reg + add]; else if (sizeflag & DFLAG) s = names32[code - eAX_reg + add]; @@ -3794,7 +5284,7 @@ OP_IMREG (int code, int sizeflag) { case indir_dx_reg: if (intel_syntax) - s = "[dx]"; + s = "dx"; else s = "(%dx)"; break; @@ -3816,8 +5306,8 @@ OP_IMREG (int code, int sizeflag) break; case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) + USED_REX (REX_W); + if (rex & REX_W) s = names64[code - eAX_reg]; else if (sizeflag & DFLAG) s = names32[code - eAX_reg]; @@ -3825,6 +5315,14 @@ OP_IMREG (int code, int sizeflag) s = names16[code - eAX_reg]; used_prefixes |= (prefixes & PREFIX_DATA); break; + case z_mode_ax_reg: + if ((rex & REX_W) || (sizeflag & DFLAG)) + s = *names32; + else + s = *names16; + if (!(rex & REX_W)) + used_prefixes |= (prefixes & PREFIX_DATA); + break; default: s = INTERNAL_DISASSEMBLER_ERROR; break; @@ -3853,8 +5351,8 @@ OP_I (int bytemode, int sizeflag) } /* Fall through. */ case v_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) + USED_REX (REX_W); + if (rex & REX_W) op = get32s (); else if (sizeflag & DFLAG) { @@ -3908,8 +5406,8 @@ OP_I64 (int bytemode, int sizeflag) mask = 0xff; break; case v_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) + USED_REX (REX_W); + if (rex & REX_W) op = get64 (); else if (sizeflag & DFLAG) { @@ -3955,8 +5453,8 @@ OP_sI (int bytemode, int sizeflag) mask = 0xffffffff; break; case v_mode: - USED_REX (REX_MODE64); - if (rex & REX_MODE64) + USED_REX (REX_W); + if (rex & REX_W) op = get32s (); else if (sizeflag & DFLAG) { @@ -3993,6 +5491,7 @@ OP_J (int bytemode, int sizeflag) { bfd_vma disp; bfd_vma mask = -1; + bfd_vma segment = 0; switch (bytemode) { @@ -4003,31 +5502,41 @@ OP_J (int bytemode, int sizeflag) disp -= 0x100; break; case v_mode: - if ((sizeflag & DFLAG) || (rex & REX_MODE64)) + if ((sizeflag & DFLAG) || (rex & REX_W)) disp = get32s (); else { disp = get16 (); - /* For some reason, a data16 prefix on a jump instruction - means that the pc is masked to 16 bits after the - displacement is added! */ + if ((disp & 0x8000) != 0) + disp -= 0x10000; + /* In 16bit mode, address is wrapped around at 64k within + the same segment. Otherwise, a data16 prefix on a jump + instruction means that the pc is masked to 16 bits after + the displacement is added! */ mask = 0xffff; + if ((prefixes & PREFIX_DATA) == 0) + segment = ((start_pc + codep - start_codep) + & ~((bfd_vma) 0xffff)); } + used_prefixes |= (prefixes & PREFIX_DATA); break; default: oappend (INTERNAL_DISASSEMBLER_ERROR); return; } - disp = (start_pc + codep - start_codep + disp) & mask; + disp = ((start_pc + codep - start_codep + disp) & mask) | segment; set_op (disp, 0); print_operand_value (scratchbuf, 1, disp); oappend (scratchbuf); } static void -OP_SEG (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +OP_SEG (int bytemode, int sizeflag) { - oappend (names_seg[reg]); + if (bytemode == w_mode) + oappend (names_seg[modrm.reg]); + else + OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); } static void @@ -4085,7 +5594,8 @@ OP_OFF64 (int bytemode, int sizeflag) { bfd_vma off; - if (address_mode != mode_64bit) + if (address_mode != mode_64bit + || (prefixes & PREFIX_ADDR)) { OP_OFF (bytemode, sizeflag); return; @@ -4137,7 +5647,22 @@ static void OP_ESreg (int code, int sizeflag) { if (intel_syntax) - intel_operand_size (codep[-1] & 1 ? v_mode : b_mode, sizeflag); + { + switch (codep[-1]) + { + case 0x6d: /* insw/insl */ + intel_operand_size (z_mode, sizeflag); + break; + case 0xa5: /* movsw/movsl/movsq */ + case 0xa7: /* cmpsw/cmpsl/cmpsq */ + case 0xab: /* stosw/stosl */ + case 0xaf: /* scasw/scasl */ + intel_operand_size (v_mode, sizeflag); + break; + default: + intel_operand_size (b_mode, sizeflag); + } + } oappend ("%es:" + intel_syntax); ptr_reg (code, sizeflag); } @@ -4146,10 +5671,21 @@ static void OP_DSreg (int code, int sizeflag) { if (intel_syntax) - intel_operand_size (codep[-1] != 0xd7 && (codep[-1] & 1) - ? v_mode - : b_mode, - sizeflag); + { + switch (codep[-1]) + { + case 0x6f: /* outsw/outsl */ + intel_operand_size (z_mode, sizeflag); + break; + case 0xa5: /* movsw/movsl/movsq */ + case 0xa7: /* cmpsw/cmpsl/cmpsq */ + case 0xad: /* lodsw/lodsl/lodsq */ + intel_operand_size (v_mode, sizeflag); + break; + default: + intel_operand_size (b_mode, sizeflag); + } + } if ((prefixes & (PREFIX_CS | PREFIX_DS @@ -4166,9 +5702,9 @@ static void OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; - if (rex & REX_EXTX) + if (rex & REX_R) { - USED_REX (REX_EXTX); + USED_REX (REX_R); add = 8; } else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) @@ -4176,7 +5712,7 @@ OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) used_prefixes |= PREFIX_LOCK; add = 8; } - sprintf (scratchbuf, "%%cr%d", reg + add); + sprintf (scratchbuf, "%%cr%d", modrm.reg + add); oappend (scratchbuf + intel_syntax); } @@ -4184,27 +5720,27 @@ static void OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; - USED_REX (REX_EXTX); - if (rex & REX_EXTX) + USED_REX (REX_R); + if (rex & REX_R) add = 8; if (intel_syntax) - sprintf (scratchbuf, "db%d", reg + add); + sprintf (scratchbuf, "db%d", modrm.reg + add); else - sprintf (scratchbuf, "%%db%d", reg + add); + sprintf (scratchbuf, "%%db%d", modrm.reg + add); oappend (scratchbuf); } static void OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { - sprintf (scratchbuf, "%%tr%d", reg); + sprintf (scratchbuf, "%%tr%d", modrm.reg); oappend (scratchbuf + intel_syntax); } static void -OP_Rd (int bytemode, int sizeflag) +OP_R (int bytemode, int sizeflag) { - if (mod == 3) + if (modrm.mod == 3) OP_E (bytemode, sizeflag); else BadOp (); @@ -4217,13 +5753,13 @@ OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) if (prefixes & PREFIX_DATA) { int add = 0; - USED_REX (REX_EXTX); - if (rex & REX_EXTX) + USED_REX (REX_R); + if (rex & REX_R) add = 8; - sprintf (scratchbuf, "%%xmm%d", reg + add); + sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); } else - sprintf (scratchbuf, "%%mm%d", reg); + sprintf (scratchbuf, "%%mm%d", modrm.reg); oappend (scratchbuf + intel_syntax); } @@ -4231,17 +5767,17 @@ static void OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; - USED_REX (REX_EXTX); - if (rex & REX_EXTX) + USED_REX (REX_R); + if (rex & REX_R) add = 8; - sprintf (scratchbuf, "%%xmm%d", reg + add); + sprintf (scratchbuf, "%%xmm%d", modrm.reg + add); oappend (scratchbuf + intel_syntax); } static void OP_EM (int bytemode, int sizeflag) { - if (mod != 3) + if (modrm.mod != 3) { if (intel_syntax && bytemode == v_mode) { @@ -4260,51 +5796,75 @@ OP_EM (int bytemode, int sizeflag) { int add = 0; - USED_REX (REX_EXTZ); - if (rex & REX_EXTZ) + USED_REX (REX_B); + if (rex & REX_B) add = 8; - sprintf (scratchbuf, "%%xmm%d", rm + add); + sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); } else - sprintf (scratchbuf, "%%mm%d", rm); + sprintf (scratchbuf, "%%mm%d", modrm.rm); oappend (scratchbuf + intel_syntax); } +/* cvt* are the only instructions in sse2 which have + both SSE and MMX operands and also have 0x66 prefix + in their opcode. 0x66 was originally used to differentiate + between SSE and MMX instruction(operands). So we have to handle the + cvt* separately using OP_EMC and OP_MXC */ static void -OP_EX (int bytemode, int sizeflag) +OP_EMC (int bytemode, int sizeflag) { - int add = 0; - if (mod != 3) + if (modrm.mod != 3) { if (intel_syntax && bytemode == v_mode) { - switch (prefixes & (PREFIX_DATA|PREFIX_REPZ|PREFIX_REPNZ)) - { - case 0: bytemode = x_mode; break; - case PREFIX_REPZ: bytemode = d_mode; used_prefixes |= PREFIX_REPZ; break; - case PREFIX_DATA: bytemode = x_mode; used_prefixes |= PREFIX_DATA; break; - case PREFIX_REPNZ: bytemode = q_mode; used_prefixes |= PREFIX_REPNZ; break; - default: bytemode = 0; break; - } - } + bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; + used_prefixes |= (prefixes & PREFIX_DATA); + } OP_E (bytemode, sizeflag); return; } - USED_REX (REX_EXTZ); - if (rex & REX_EXTZ) + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + used_prefixes |= (prefixes & PREFIX_DATA); + sprintf (scratchbuf, "%%mm%d", modrm.rm); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + used_prefixes |= (prefixes & PREFIX_DATA); + sprintf (scratchbuf, "%%mm%d", modrm.reg); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_EX (int bytemode, int sizeflag) +{ + int add = 0; + if (modrm.mod != 3) + { + OP_E (bytemode, sizeflag); + return; + } + USED_REX (REX_B); + if (rex & REX_B) add = 8; /* Skip mod/rm byte. */ MODRM_CHECK; codep++; - sprintf (scratchbuf, "%%xmm%d", rm + add); + sprintf (scratchbuf, "%%xmm%d", modrm.rm + add); oappend (scratchbuf + intel_syntax); } static void OP_MS (int bytemode, int sizeflag) { - if (mod == 3) + if (modrm.mod == 3) OP_EM (bytemode, sizeflag); else BadOp (); @@ -4313,7 +5873,7 @@ OP_MS (int bytemode, int sizeflag) static void OP_XS (int bytemode, int sizeflag) { - if (mod == 3) + if (modrm.mod == 3) OP_EX (bytemode, sizeflag); else BadOp (); @@ -4322,8 +5882,9 @@ OP_XS (int bytemode, int sizeflag) static void OP_M (int bytemode, int sizeflag) { - if (mod == 3) - BadOp (); /* bad lea,lds,les,lfs,lgs,lss modrm */ + if (modrm.mod == 3) + /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ + BadOp (); else OP_E (bytemode, sizeflag); } @@ -4331,7 +5892,7 @@ OP_M (int bytemode, int sizeflag) static void OP_0f07 (int bytemode, int sizeflag) { - if (mod != 3 || rm != 0) + if (modrm.mod != 3 || modrm.rm != 0) BadOp (); else OP_E (bytemode, sizeflag); @@ -4340,18 +5901,18 @@ OP_0f07 (int bytemode, int sizeflag) static void OP_0fae (int bytemode, int sizeflag) { - if (mod == 3) + if (modrm.mod == 3) { - if (reg == 7) + if (modrm.reg == 7) strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence"); - if (reg < 5 || rm != 0) + if (modrm.reg < 5 || modrm.rm != 0) { BadOp (); /* bad sfence, mfence, or lfence */ return; } } - else if (reg != 7) + else if (modrm.reg != 7) { BadOp (); /* bad clflush */ return; @@ -4360,12 +5921,29 @@ OP_0fae (int bytemode, int sizeflag) OP_E (bytemode, sizeflag); } +/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in + 32bit mode and "xchg %rax,%rax" in 64bit mode. */ + +static void +NOP_Fixup1 (int bytemode, int sizeflag) +{ + if ((prefixes & PREFIX_DATA) != 0 + || (rex != 0 + && rex != 0x48 + && address_mode == mode_64bit)) + OP_REG (bytemode, sizeflag); + else + strcpy (obuf, "nop"); +} + static void -NOP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +NOP_Fixup2 (int bytemode, int sizeflag) { - /* NOP with REPZ prefix is called PAUSE. */ - if (prefixes == PREFIX_REPZ) - strcpy (obuf, "pause"); + if ((prefixes & PREFIX_DATA) != 0 + || (rex != 0 + && rex != 0x48 + && address_mode == mode_64bit)) + OP_IMREG (bytemode, sizeflag); } static const char *const Suffix3DNow[] = { @@ -4414,7 +5992,7 @@ static const char *const Suffix3DNow[] = { /* A8 */ NULL, NULL, "pfsubr", NULL, /* AC */ NULL, NULL, "pfacc", NULL, /* B0 */ "pfcmpeq", NULL, NULL, NULL, -/* B4 */ "pfmul", NULL, "pfrcpit2", "pfmulhrw", +/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", /* B8 */ NULL, NULL, NULL, "pswapd", /* BC */ NULL, NULL, NULL, "pavgusb", /* C0 */ NULL, NULL, NULL, NULL, @@ -4454,8 +6032,8 @@ OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) of the opcode (0x0f0f) and the opcode suffix, we need to do all the modrm processing first, and don't know until now that we have a bad opcode. This necessitates some cleaning up. */ - op1out[0] = '\0'; - op2out[0] = '\0'; + op_out[0][0] = '\0'; + op_out[1][0] = '\0'; BadOp (); } } @@ -4505,8 +6083,8 @@ OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) else { /* We have a bad extension byte. Clean up. */ - op1out[0] = '\0'; - op2out[0] = '\0'; + op_out[0][0] = '\0'; + op_out[1][0] = '\0'; BadOp (); } } @@ -4516,7 +6094,7 @@ SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED) { /* Change movlps/movhps to movhlps/movlhps for 2 register operand forms of these instructions. */ - if (mod == 3) + if (modrm.mod == 3) { char *p = obuf + strlen (obuf); *(p + 1) = '\0'; @@ -4530,7 +6108,7 @@ SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED) static void PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag) { - if (mod == 3 && reg == 1 && rm <= 1) + if (modrm.mod == 3 && modrm.reg == 1 && modrm.rm <= 1) { /* Override "sidt". */ size_t olen = strlen (obuf); @@ -4547,17 +6125,17 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag) && (prefixes & PREFIX_ADDR) && olen >= (4 + 7) && *(p - 1) == ' ' - && strncmp (p - 7, "addr", 4) == 0 - && (strncmp (p - 3, "16", 2) == 0 - || strncmp (p - 3, "32", 2) == 0)) + && CONST_STRNEQ (p - 7, "addr") + && (CONST_STRNEQ (p - 3, "16") + || CONST_STRNEQ (p - 3, "32"))) p -= 7; - if (rm) + if (modrm.rm) { /* mwait %eax,%ecx */ strcpy (p, "mwait"); if (!intel_syntax) - strcpy (op1out, names[0]); + strcpy (op_out[0], names[0]); } else { @@ -4575,13 +6153,13 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag) ? names32 : names16); used_prefixes |= PREFIX_ADDR; } - strcpy (op1out, op1_names[0]); - strcpy (op3out, names[2]); + strcpy (op_out[0], op1_names[0]); + strcpy (op_out[2], names[2]); } } if (!intel_syntax) { - strcpy (op2out, names[1]); + strcpy (op_out[1], names[1]); two_source_ops = 1; } @@ -4642,7 +6220,7 @@ SVME_Fixup (int bytemode, int sizeflag) switch (*codep++) { case 0xdf: - strcpy (op2out, names32[1]); + strcpy (op_out[1], names32[1]); two_source_ops = 1; /* Fall through. */ case 0xd8: @@ -4692,58 +6270,12 @@ BadOp (void) } static void -SEG_Fixup (int extrachar, int sizeflag) -{ - if (mod == 3) - { - /* We need to add a proper suffix with - - movw %ds,%ax - movl %ds,%eax - movq %ds,%rax - movw %ax,%ds - movl %eax,%ds - movq %rax,%ds - */ - const char *suffix; - - if (prefixes & PREFIX_DATA) - suffix = "w"; - else - { - USED_REX (REX_MODE64); - if (rex & REX_MODE64) - suffix = "q"; - else - suffix = "l"; - } - strcat (obuf, suffix); - } - else - { - /* We need to fix the suffix for - - movw %ds,(%eax) - movw %ds,(%rax) - movw (%eax),%ds - movw (%rax),%ds - - Override "mov[l|q]". */ - char *p = obuf + strlen (obuf) - 1; - - /* We might not have a suffix. */ - if (*p == 'v') - ++p; - *p = 'w'; - } - - OP_E (extrachar, sizeflag); -} - -static void VMX_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag) { - if (mod == 3 && reg == 0 && rm >=1 && rm <= 4) + if (modrm.mod == 3 + && modrm.reg == 0 + && modrm.rm >=1 + && modrm.rm <= 4) { /* Override "sgdt". */ char *p = obuf + strlen (obuf) - 4; @@ -4752,7 +6284,7 @@ VMX_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag) if (*p == 'g') --p; - switch (rm) + switch (modrm.rm) { case 1: strcpy (p, "vmcall"); @@ -4795,7 +6327,7 @@ REP_Fixup (int bytemode, int sizeflag) size_t ilen = 0; if (prefixes & PREFIX_REPZ) - switch (*insn_codep) + switch (*insn_codep) { case 0x6e: /* outsb */ case 0x6f: /* outsw/outsl */ @@ -4859,3 +6391,90 @@ REP_Fixup (int bytemode, int sizeflag) break; } } + +static void +CMPXCHG8B_Fixup (int bytemode, int sizeflag) +{ + USED_REX (REX_W); + if (rex & REX_W) + { + /* Change cmpxchg8b to cmpxchg16b. */ + char *p = obuf + strlen (obuf) - 2; + strcpy (p, "16b"); + bytemode = o_mode; + } + OP_M (bytemode, sizeflag); +} + +static void +XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) +{ + sprintf (scratchbuf, "%%xmm%d", reg); + oappend (scratchbuf + intel_syntax); +} + +static void +CRC32_Fixup (int bytemode, int sizeflag) +{ + /* Add proper suffix to "crc32". */ + char *p = obuf + strlen (obuf); + + switch (bytemode) + { + case b_mode: + if (intel_syntax) + break; + + *p++ = 'b'; + break; + case v_mode: + if (intel_syntax) + break; + + USED_REX (REX_W); + if (rex & REX_W) + *p++ = 'q'; + else if (sizeflag & DFLAG) + *p++ = 'l'; + else + *p++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + break; + } + *p = '\0'; + + if (modrm.mod == 3) + { + int add; + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + + USED_REX (REX_B); + add = (rex & REX_B) ? 8 : 0; + if (bytemode == b_mode) + { + USED_REX (0); + if (rex) + oappend (names8rex[modrm.rm + add]); + else + oappend (names8[modrm.rm + add]); + } + else + { + USED_REX (REX_W); + if (rex & REX_W) + oappend (names64[modrm.rm + add]); + else if ((prefixes & PREFIX_DATA)) + oappend (names16[modrm.rm + add]); + else + oappend (names32[modrm.rm + add]); + } + } + else + OP_E (bytemode, sizeflag); +} diff --git a/contrib/binutils/opcodes/i386-gen.c b/contrib/binutils/opcodes/i386-gen.c new file mode 100644 index 0000000..80d414f --- /dev/null +++ b/contrib/binutils/opcodes/i386-gen.c @@ -0,0 +1,394 @@ +/* Copyright 2007 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include "getopt.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#include "i386-opc.h" + +#include <libintl.h> +#define _(String) gettext (String) + +static const char *program_name = NULL; +static int debug = 0; + +static void +fail (const char *message, ...) +{ + va_list args; + + va_start (args, message); + fprintf (stderr, _("%s: Error: "), program_name); + vfprintf (stderr, message, args); + va_end (args); + xexit (1); +} + +/* Remove leading white spaces. */ + +static char * +remove_leading_whitespaces (char *str) +{ + while (ISSPACE (*str)) + str++; + return str; +} + +/* Remove trailing white spaces. */ + +static void +remove_trailing_whitespaces (char *str) +{ + size_t last = strlen (str); + + if (last == 0) + return; + + do + { + last--; + if (ISSPACE (str [last])) + str[last] = '\0'; + else + break; + } + while (last != 0); +} + +/* Find next field separated by '.' and terminate it. Return a + pointer to the one after it. */ + +static char * +next_field (char *str, char **next) +{ + char *p; + + p = remove_leading_whitespaces (str); + for (str = p; *str != ',' && *str != '\0'; str++); + + *str = '\0'; + remove_trailing_whitespaces (p); + + *next = str + 1; + + return p; +} + +static void +process_i386_opcodes (void) +{ + FILE *fp = fopen ("i386-opc.tbl", "r"); + char buf[2048]; + unsigned int i; + char *str, *p, *last; + char *name, *operands, *base_opcode, *extension_opcode; + char *cpu_flags, *opcode_modifier, *operand_types [MAX_OPERANDS]; + + if (fp == NULL) + fail (_("can't find i386-opc.tbl for reading\n")); + + printf ("\n/* i386 opcode table. */\n\n"); + printf ("const template i386_optab[] =\n{\n"); + + while (!feof (fp)) + { + if (fgets (buf, sizeof (buf), fp) == NULL) + break; + + p = remove_leading_whitespaces (buf); + + /* Skip comments. */ + str = strstr (p, "//"); + if (str != NULL) + str[0] = '\0'; + + /* Remove trailing white spaces. */ + remove_trailing_whitespaces (p); + + switch (p[0]) + { + case '#': + printf ("%s\n", p); + case '\0': + continue; + break; + default: + break; + } + + last = p + strlen (p); + + /* Find name. */ + name = next_field (p, &str); + + if (str >= last) + abort (); + + /* Find number of operands. */ + operands = next_field (str, &str); + + if (str >= last) + abort (); + + /* Find base_opcode. */ + base_opcode = next_field (str, &str); + + if (str >= last) + abort (); + + /* Find extension_opcode. */ + extension_opcode = next_field (str, &str); + + if (str >= last) + abort (); + + /* Find cpu_flags. */ + cpu_flags = next_field (str, &str); + + if (str >= last) + abort (); + + /* Find opcode_modifier. */ + opcode_modifier = next_field (str, &str); + + if (str >= last) + abort (); + + /* Remove the first {. */ + str = remove_leading_whitespaces (str); + if (*str != '{') + abort (); + str = remove_leading_whitespaces (str + 1); + + i = strlen (str); + + /* There are at least "X}". */ + if (i < 2) + abort (); + + /* Remove trailing white spaces and }. */ + do + { + i--; + if (ISSPACE (str[i]) || str[i] == '}') + str[i] = '\0'; + else + break; + } + while (i != 0); + + last = str + i; + + /* Find operand_types. */ + for (i = 0; i < ARRAY_SIZE (operand_types); i++) + { + if (str >= last) + { + operand_types [i] = NULL; + break; + } + + operand_types [i] = next_field (str, &str); + if (*operand_types[i] == '0') + { + if (i != 0) + operand_types[i] = NULL; + break; + } + } + + printf (" { \"%s\", %s, %s, %s, %s,\n", + name, operands, base_opcode, extension_opcode, + cpu_flags); + + printf (" %s,\n", opcode_modifier); + + printf (" { "); + + for (i = 0; i < ARRAY_SIZE (operand_types); i++) + { + if (operand_types[i] == NULL + || *operand_types[i] == '0') + { + if (i == 0) + printf ("0"); + break; + } + + if (i != 0) + printf (",\n "); + + printf ("%s", operand_types[i]); + } + printf (" } },\n"); + } + + printf (" { NULL, 0, 0, 0, 0, 0, { 0 } }\n"); + printf ("};\n"); +} + +static void +process_i386_registers (void) +{ + FILE *fp = fopen ("i386-reg.tbl", "r"); + char buf[2048]; + char *str, *p, *last; + char *reg_name, *reg_type, *reg_flags, *reg_num; + + if (fp == NULL) + fail (_("can't find i386-reg.tbl for reading\n")); + + printf ("\n/* i386 register table. */\n\n"); + printf ("const reg_entry i386_regtab[] =\n{\n"); + + while (!feof (fp)) + { + if (fgets (buf, sizeof (buf), fp) == NULL) + break; + + p = remove_leading_whitespaces (buf); + + /* Skip comments. */ + str = strstr (p, "//"); + if (str != NULL) + str[0] = '\0'; + + /* Remove trailing white spaces. */ + remove_trailing_whitespaces (p); + + switch (p[0]) + { + case '#': + printf ("%s\n", p); + case '\0': + continue; + break; + default: + break; + } + + last = p + strlen (p); + + /* Find reg_name. */ + reg_name = next_field (p, &str); + + if (str >= last) + abort (); + + /* Find reg_type. */ + reg_type = next_field (str, &str); + + if (str >= last) + abort (); + + /* Find reg_flags. */ + reg_flags = next_field (str, &str); + + if (str >= last) + abort (); + + /* Find reg_num. */ + reg_num = next_field (str, &str); + + printf (" { \"%s\", %s, %s, %s },\n", + reg_name, reg_type, reg_flags, reg_num); + } + + printf ("};\n"); + + printf ("\nconst unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);\n"); +} + +/* Program options. */ +#define OPTION_SRCDIR 200 + +struct option long_options[] = +{ + {"srcdir", required_argument, NULL, OPTION_SRCDIR}, + {"debug", no_argument, NULL, 'd'}, + {"version", no_argument, NULL, 'V'}, + {"help", no_argument, NULL, 'h'}, + {0, no_argument, NULL, 0} +}; + +static void +print_version (void) +{ + printf ("%s: version 1.0\n", program_name); + xexit (0); +} + +static void +usage (FILE * stream, int status) +{ + fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--srcdir=dirname] [--help]\n", + program_name); + xexit (status); +} + +int +main (int argc, char **argv) +{ + extern int chdir (char *); + char *srcdir = NULL; + int c; + + program_name = *argv; + xmalloc_set_program_name (program_name); + + while ((c = getopt_long (argc, argv, "vVdh", long_options, 0)) != EOF) + switch (c) + { + case OPTION_SRCDIR: + srcdir = optarg; + break; + case 'V': + case 'v': + print_version (); + break; + case 'd': + debug = 1; + break; + case 'h': + case '?': + usage (stderr, 0); + default: + case 0: + break; + } + + if (optind != argc) + usage (stdout, 1); + + if (srcdir != NULL) + if (chdir (srcdir) != 0) + fail (_("unable to change directory to \"%s\", errno = %s\n"), + srcdir, strerror (errno)); + + printf ("/* This file is automatically generated by i386-gen. Do not edit! */\n"); + + process_i386_opcodes (); + process_i386_registers (); + + exit (0); +} diff --git a/contrib/binutils/opcodes/i386-opc.c b/contrib/binutils/opcodes/i386-opc.c new file mode 100644 index 0000000..2018488 --- /dev/null +++ b/contrib/binutils/opcodes/i386-opc.c @@ -0,0 +1,32 @@ +/* Intel 80386 opcode table + Copyright 2007 + Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "libiberty.h" +#include "i386-opc.h" +#include "i386-tbl.h" + +/* Segment stuff. */ +const seg_entry cs = { "cs", 0x2e }; +const seg_entry ds = { "ds", 0x3e }; +const seg_entry ss = { "ss", 0x36 }; +const seg_entry es = { "es", 0x26 }; +const seg_entry fs = { "fs", 0x64 }; +const seg_entry gs = { "gs", 0x65 }; diff --git a/contrib/binutils/opcodes/i386-opc.h b/contrib/binutils/opcodes/i386-opc.h new file mode 100644 index 0000000..5372d4a --- /dev/null +++ b/contrib/binutils/opcodes/i386-opc.h @@ -0,0 +1,239 @@ +/* Declarations for Intel 80386 opcode table + Copyright 2007 + Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "opcode/i386.h" + +typedef struct template +{ + /* instruction name sans width suffix ("mov" for movl insns) */ + char *name; + + /* how many operands */ + unsigned int operands; + + /* base_opcode is the fundamental opcode byte without optional + prefix(es). */ + unsigned int base_opcode; +#define Opcode_D 0x2 /* Direction bit: + set if Reg --> Regmem; + unset if Regmem --> Reg. */ +#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ +#define Opcode_FloatD 0x400 /* Direction bit for float insns. */ + + /* extension_opcode is the 3 bit extension for group <n> insns. + This field is also used to store the 8-bit opcode suffix for the + AMD 3DNow! instructions. + If this template has no extension opcode (the usual case) use None */ + unsigned int extension_opcode; +#define None 0xffff /* If no extension_opcode is possible. */ + + /* cpu feature flags */ + unsigned int cpu_flags; +#define Cpu186 0x1 /* i186 or better required */ +#define Cpu286 0x2 /* i286 or better required */ +#define Cpu386 0x4 /* i386 or better required */ +#define Cpu486 0x8 /* i486 or better required */ +#define Cpu586 0x10 /* i585 or better required */ +#define Cpu686 0x20 /* i686 or better required */ +#define CpuP4 0x40 /* Pentium4 or better required */ +#define CpuK6 0x80 /* AMD K6 or better required*/ +#define CpuSledgehammer 0x100 /* Sledgehammer or better required */ +#define CpuMMX 0x200 /* MMX support required */ +#define CpuMMX2 0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */ +#define CpuSSE 0x800 /* Streaming SIMD extensions required */ +#define CpuSSE2 0x1000 /* Streaming SIMD extensions 2 required */ +#define Cpu3dnow 0x2000 /* 3dnow! support required */ +#define Cpu3dnowA 0x4000 /* 3dnow!Extensions support required */ +#define CpuSSE3 0x8000 /* Streaming SIMD extensions 3 required */ +#define CpuPadLock 0x10000 /* VIA PadLock required */ +#define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */ +#define CpuVMX 0x40000 /* VMX Instructions required */ +#define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */ +#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */ +#define CpuABM 0x200000 /* ABM New Instructions required */ +#define CpuSSE4_1 0x400000 /* SSE4.1 Instructions required */ +#define CpuSSE4_2 0x800000 /* SSE4.2 Instructions required */ + +/* SSE4.1/4.2 Instructions required */ +#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2) + + /* These flags are set by gas depending on the flag_code. */ +#define Cpu64 0x4000000 /* 64bit support required */ +#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ + + /* The default value for unknown CPUs - enable all features to avoid problems. */ +#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ + |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \ + |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \ + |CpuSSE4_2|CpuABM|CpuSSE4a) + + /* the bits in opcode_modifier are used to generate the final opcode from + the base_opcode. These bits also are used to detect alternate forms of + the same instruction */ + unsigned int opcode_modifier; + + /* opcode_modifier bits: */ +#define D 0x1 /* has direction bit. */ +#define W 0x2 /* set if operands can be words or dwords + encoded the canonical way */ +#define Modrm 0x4 /* insn has a modrm byte. */ +#define ShortForm 0x8 /* register is in low 3 bits of opcode */ +#define Jump 0x10 /* special case for jump insns. */ +#define JumpDword 0x20 /* call and jump */ +#define JumpByte 0x40 /* loop and jecxz */ +#define JumpInterSegment 0x80 /* special case for intersegment leaps/calls */ +#define FloatMF 0x100 /* FP insn memory format bit, sized by 0x4 */ +#define FloatR 0x200 /* src/dest swap for floats. */ +#define FloatD 0x400 /* has float insn direction bit. */ +#define Size16 0x800 /* needs size prefix if in 32-bit mode */ +#define Size32 0x1000 /* needs size prefix if in 16-bit mode */ +#define Size64 0x2000 /* needs size prefix if in 64-bit mode */ +#define IgnoreSize 0x4000 /* instruction ignores operand size prefix */ +#define DefaultSize 0x8000 /* default insn size depends on mode */ +#define No_bSuf 0x10000 /* b suffix on instruction illegal */ +#define No_wSuf 0x20000 /* w suffix on instruction illegal */ +#define No_lSuf 0x40000 /* l suffix on instruction illegal */ +#define No_sSuf 0x80000 /* s suffix on instruction illegal */ +#define No_qSuf 0x100000 /* q suffix on instruction illegal */ +#define No_xSuf 0x200000 /* x suffix on instruction illegal */ +#define FWait 0x400000 /* instruction needs FWAIT */ +#define IsString 0x800000 /* quick test for string instructions */ +#define RegKludge 0x1000000 /* fake an extra reg operand for clr, imul + and special register processing for + some instructions. */ +#define IsPrefix 0x2000000 /* opcode is a prefix */ +#define ImmExt 0x4000000 /* instruction has extension in 8 bit imm */ +#define NoRex64 0x8000000 /* instruction don't need Rex64 prefix. */ +#define Rex64 0x10000000 /* instruction require Rex64 prefix. */ +#define Ugh 0x20000000 /* deprecated fp insn, gets a warning */ + + /* operand_types[i] describes the type of operand i. This is made + by OR'ing together all of the possible type masks. (e.g. + 'operand_types[i] = Reg|Imm' specifies that operand i can be + either a register or an immediate operand. */ + unsigned int operand_types[MAX_OPERANDS]; + + /* operand_types[i] bits */ + /* register */ +#define Reg8 0x1 /* 8 bit reg */ +#define Reg16 0x2 /* 16 bit reg */ +#define Reg32 0x4 /* 32 bit reg */ +#define Reg64 0x8 /* 64 bit reg */ + /* immediate */ +#define Imm8 0x10 /* 8 bit immediate */ +#define Imm8S 0x20 /* 8 bit immediate sign extended */ +#define Imm16 0x40 /* 16 bit immediate */ +#define Imm32 0x80 /* 32 bit immediate */ +#define Imm32S 0x100 /* 32 bit immediate sign extended */ +#define Imm64 0x200 /* 64 bit immediate */ +#define Imm1 0x400 /* 1 bit immediate */ + /* memory */ +#define BaseIndex 0x800 + /* Disp8,16,32 are used in different ways, depending on the + instruction. For jumps, they specify the size of the PC relative + displacement, for baseindex type instructions, they specify the + size of the offset relative to the base register, and for memory + offset instructions such as `mov 1234,%al' they specify the size of + the offset relative to the segment base. */ +#define Disp8 0x1000 /* 8 bit displacement */ +#define Disp16 0x2000 /* 16 bit displacement */ +#define Disp32 0x4000 /* 32 bit displacement */ +#define Disp32S 0x8000 /* 32 bit signed displacement */ +#define Disp64 0x10000 /* 64 bit displacement */ + /* specials */ +#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ +#define ShiftCount 0x40000 /* register to hold shift count = cl */ +#define Control 0x80000 /* Control register */ +#define Debug 0x100000 /* Debug register */ +#define Test 0x200000 /* Test register */ +#define FloatReg 0x400000 /* Float register */ +#define FloatAcc 0x800000 /* Float stack top %st(0) */ +#define SReg2 0x1000000 /* 2 bit segment register */ +#define SReg3 0x2000000 /* 3 bit segment register */ +#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ +#define JumpAbsolute 0x8000000 +#define RegMMX 0x10000000 /* MMX register */ +#define RegXMM 0x20000000 /* XMM registers in PIII */ +#define EsSeg 0x40000000 /* String insn operand with fixed es segment */ + + /* RegMem is for instructions with a modrm byte where the register + destination operand should be encoded in the mod and regmem fields. + Normally, it will be encoded in the reg field. We add a RegMem + flag to the destination register operand to indicate that it should + be encoded in the regmem field. */ +#define RegMem 0x80000000 + +#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ +#define WordReg (Reg16|Reg32|Reg64) +#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) +#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ +#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ +#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ +#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */ + /* The following aliases are defined because the opcode table + carefully specifies the allowed memory types for each instruction. + At the moment we can only tell a memory reference size by the + instruction suffix, so there's not much point in defining Mem8, + Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use + the suffix directly to check memory operands. */ +#define LLongMem AnyMem /* 64 bits (or more) */ +#define LongMem AnyMem /* 32 bit memory ref */ +#define ShortMem AnyMem /* 16 bit memory ref */ +#define WordMem AnyMem /* 16, 32 or 64 bit memory ref */ +#define ByteMem AnyMem /* 8 bit memory ref */ +} +template; + +extern const template i386_optab[]; + +/* these are for register name --> number & type hash lookup */ +typedef struct +{ + char *reg_name; + unsigned int reg_type; + unsigned int reg_flags; +#define RegRex 0x1 /* Extended register. */ +#define RegRex64 0x2 /* Extended 8 bit register. */ + unsigned int reg_num; +} +reg_entry; + +/* Entries in i386_regtab. */ +#define REGNAM_AL 1 +#define REGNAM_AX 25 +#define REGNAM_EAX 41 + +extern const reg_entry i386_regtab[]; +extern const unsigned int i386_regtab_size; + +typedef struct +{ + char *seg_name; + unsigned int seg_prefix; +} +seg_entry; + +extern const seg_entry cs; +extern const seg_entry ds; +extern const seg_entry ss; +extern const seg_entry es; +extern const seg_entry fs; +extern const seg_entry gs; diff --git a/contrib/binutils/opcodes/i386-opc.tbl b/contrib/binutils/opcodes/i386-opc.tbl new file mode 100644 index 0000000..5465608 --- /dev/null +++ b/contrib/binutils/opcodes/i386-opc.tbl @@ -0,0 +1,1489 @@ +// i386 opcode table. + +// Move instructions. +// We put the 64bit displacement first and we only mark constants +// larger than 32bit as Disp64. +mov, 2, 0xa0, None, Cpu64, D|W|No_sSuf|No_xSuf, { Disp64, Acc } +mov, 2, 0xa0, None, CpuNo64, D|W|No_sSuf|No_qSuf|No_xSuf, { Disp16|Disp32, Acc } +mov, 2, 0x88, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +// In the 64bit mode the short form mov immediate is redefined to have +// 64bit value. +mov, 2, 0xb0, None, 0, W|ShortForm|No_sSuf|No_qSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } +mov, 2, 0xc6, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +mov, 2, 0xb0, None, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { Imm64, Reg64 } +// The segment register moves accept WordReg so that a segment register +// can be copied to a 32 bit register, and vice versa, without using a +// size prefix. When moving to a 32 bit register, the upper 16 bits +// are set to an implementation defined value (on the Pentium Pro, the +// implementation defined value is zero). +mov, 2, 0x8c, None, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2, Reg16|Reg32|Reg64|RegMem } +mov, 2, 0x8c, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +mov, 2, 0x8c, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3, Reg16|Reg32|Reg64|RegMem } +mov, 2, 0x8c, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +mov, 2, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64, SReg2 } +mov, 2, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg2 } +mov, 2, 0x8e, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64, SReg3 } +mov, 2, 0x8e, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg3 } +// Move to/from control debug registers. In the 16 or 32bit modes +// they are 32bit. In the 64bit mode they are 64bit. +mov, 2, 0xf20, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Control, Reg32|RegMem } +mov, 2, 0xf20, None, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Control, Reg64|RegMem } +mov, 2, 0xf21, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Debug, Reg32|RegMem } +mov, 2, 0xf21, None, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Debug, Reg64|RegMem } +mov, 2, 0xf24, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Test, Reg32|RegMem } +movabs, 2, 0xa0, None, Cpu64, D|W|No_sSuf|No_xSuf, { Disp64, Acc } +movabs, 2, 0xb0, None, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { Imm64, Reg64 } + +// Move with sign extend. +// "movsbl" & "movsbw" must not be unified into "movsb" to avoid +// conflict with the "movs" string move instruction. +movsbl, 2, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +movsbw, 2, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } +movswl, 2, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +movsbq, 2, 0xfbe, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } +movswq, 2, 0xfbf, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } +movslq, 2, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } +// Intel Syntax next 3 insns +movsx, 2, 0xfbe, None, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +movsx, 2, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } +movsx, 2, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } + +// Move with zero extend. We can't remove "movzb" since existing +// assembly codes may use it. +movzb, 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +// "movzbl" & "movzbw" should not be unified into "movzb" for +// consistency with the sign extending moves above. +movzbl, 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +movzbw, 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } +movzwl, 2, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +// These instructions are not particulary useful, since the zero extend +// 32->64 is implicit, but we can encode them. +movzbq, 2, 0xfb6, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } +movzwq, 2, 0xfb7, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } +// Intel Syntax next 2 insns (the 64-bit variants are not particulary +// useful since the zero extend 32->64 is implicit, but we can encode them). +movzx, 2, 0xfb6, None, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +movzx, 2, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } + +// Push instructions. +push, 1, 0x50, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } +push, 1, 0xff, 0x6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +push, 1, 0x6a, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8S } +push, 1, 0x68, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16|Imm32 } +push, 1, 0x6, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2 } +push, 1, 0xfa0, None, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3 } +// In 64bit mode, the operand size is implicitly 64bit. +push, 1, 0x50, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64 } +push, 1, 0xff, 0x6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +push, 1, 0x6a, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm8S } +push, 1, 0x68, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm16|Imm32S } +push, 1, 0xfa0, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { SReg3 } + +pusha, 0, 0x60, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// Pop instructions. +pop, 1, 0x58, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } +pop, 1, 0x8f, 0x0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pop, 1, 0x7, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2 } +pop, 1, 0xfa1, None, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3 } +// In 64bit mode, the operand size is implicitly 64bit. +pop, 1, 0x58, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64 } +pop, 1, 0x8f, 0x0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pop, 1, 0xfa1, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { SReg3 } + +popa, 0, 0x61, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// Exchange instructions. +// xchg commutes: we allow both operand orders. + +// In the 64bit code, xchg rax, rax is reused for new nop instruction. +xchg, 2, 0x90, None, 0, ShortForm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Acc } +xchg, 2, 0x90, None, 0, ShortForm|No_bSuf|No_sSuf|No_xSuf, { Acc, Reg16|Reg32|Reg64 } +xchg, 2, 0x86, None, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xchg, 2, 0x86, None, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } + +// In/out from ports. +// XXX should reject %rax +in, 2, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Imm8, Acc } +in, 2, 0xec, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { InOutPortReg, Acc } +in, 1, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Imm8 } +in, 1, 0xec, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { InOutPortReg } +out, 2, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Acc, Imm8 } +out, 2, 0xee, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Acc, InOutPortReg } +out, 1, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Imm8 } +out, 1, 0xee, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { InOutPortReg } + +// Load effective address. +lea, 2, 0x8d, None, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + +// Load segment registers from memory. +lds, 2, 0xc5, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +les, 2, 0xc4, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +lfs, 2, 0xfb4, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +lgs, 2, 0xfb5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +lss, 2, 0xfb2, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + +// Flags register instructions. +clc, 0, 0xf8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cld, 0, 0xfc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cli, 0, 0xfa, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +clts, 0, 0xf06, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cmc, 0, 0xf5, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +lahf, 0, 0x9f, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +sahf, 0, 0x9e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +pushf, 0, 0x9c, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +pushf, 0, 0x9c, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } +popf, 0, 0x9d, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +popf, 0, 0x9d, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } +stc, 0, 0xf9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +std, 0, 0xfd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +sti, 0, 0xfb, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// Arithmetic. +add, 2, 0x0, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +add, 2, 0x83, 0x0, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +add, 2, 0x4, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } +add, 2, 0x80, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +inc, 1, 0x40, None, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } +inc, 1, 0xfe, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sub, 2, 0x28, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sub, 2, 0x83, 0x5, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sub, 2, 0x2c, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } +sub, 2, 0x80, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +dec, 1, 0x48, None, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } +dec, 1, 0xfe, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sbb, 2, 0x18, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sbb, 2, 0x83, 0x3, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sbb, 2, 0x1c, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } +sbb, 2, 0x80, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +cmp, 2, 0x38, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +cmp, 2, 0x83, 0x7, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +cmp, 2, 0x3c, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } +cmp, 2, 0x80, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +test, 2, 0x84, None, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +test, 2, 0x84, None, 0, W|Modrm|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } +test, 2, 0xa8, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } +test, 2, 0xf6, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +and, 2, 0x20, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +and, 2, 0x83, 0x4, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +and, 2, 0x24, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } +and, 2, 0x80, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +or, 2, 0x8, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +or, 2, 0x83, 0x1, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +or, 2, 0xc, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } +or, 2, 0x80, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +xor, 2, 0x30, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xor, 2, 0x83, 0x6, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xor, 2, 0x34, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } +xor, 2, 0x80, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// clr with 1 operand is really xor with 2 operands. +clr, 1, 0x30, None, 0, W|Modrm|No_sSuf|No_xSuf|RegKludge, { Reg8|Reg16|Reg32|Reg64 } + +adc, 2, 0x10, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +adc, 2, 0x83, 0x2, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +adc, 2, 0x14, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } +adc, 2, 0x80, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +neg, 1, 0xf6, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +not, 1, 0xf6, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +aaa, 0, 0x37, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +aas, 0, 0x3f, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +daa, 0, 0x27, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +das, 0, 0x2f, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +aad, 0, 0xd50a, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +aad, 1, 0xd5, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8 } +aam, 0, 0xd40a, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +aam, 1, 0xd4, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8 } + +// Conversion insns. +// Intel naming +cbw, 0, 0x98, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cdqe, 0, 0x98, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cwde, 0, 0x98, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cwd, 0, 0x99, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cdq, 0, 0x99, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cqo, 0, 0x99, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +// AT&T naming +cbtw, 0, 0x98, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cltq, 0, 0x98, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cwtl, 0, 0x98, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cwtd, 0, 0x99, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cltd, 0, 0x99, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cqto, 0, 0x99, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are +// expanding 64-bit multiplies, and *cannot* be selected to accomplish +// 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) +// These multiplies can only be selected with single operand forms. +mul, 1, 0xf6, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +imul, 1, 0xf6, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +imul, 2, 0xfaf, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +imul, 3, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +imul, 3, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +// imul with 2 operands mimics imul with 3 by putting the register in +// both i.rm.reg & i.rm.regmem fields. RegKludge enables this +// transformation. +imul, 2, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } +imul, 2, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } + +div, 1, 0xf6, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +div, 2, 0xf6, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } +idiv, 1, 0xf6, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +idiv, 2, 0xf6, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } + +rol, 2, 0xd0, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rol, 2, 0xc0, 0x0, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rol, 2, 0xd2, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rol, 1, 0xd0, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +ror, 2, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +ror, 2, 0xc0, 0x1, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +ror, 2, 0xd2, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +ror, 1, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +rcl, 2, 0xd0, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcl, 2, 0xc0, 0x2, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcl, 2, 0xd2, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcl, 1, 0xd0, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +rcr, 2, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcr, 2, 0xc0, 0x3, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcr, 2, 0xd2, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rcr, 1, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sal, 2, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sal, 2, 0xc0, 0x4, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sal, 2, 0xd2, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sal, 1, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +shl, 2, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shl, 2, 0xc0, 0x4, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shl, 2, 0xd2, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shl, 1, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +shr, 2, 0xd0, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shr, 2, 0xc0, 0x5, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shr, 2, 0xd2, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shr, 1, 0xd0, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sar, 2, 0xd0, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sar, 2, 0xc0, 0x7, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sar, 2, 0xd2, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sar, 1, 0xd0, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +shld, 3, 0xfa4, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shld, 3, 0xfa5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shld, 2, 0xfa5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +shrd, 3, 0xfac, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shrd, 3, 0xfad, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +shrd, 2, 0xfad, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Control transfer instructions. +call, 1, 0xe8, None, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp16|Disp32 } +call, 1, 0xe8, None, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Disp16|Disp32 } +call, 1, 0xff, 0x2, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } +call, 1, 0xff, 0x2, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } +// Intel Syntax +call, 2, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } +// Intel Syntax +call, 1, 0xff, 0x3, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } +lcall, 2, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } +lcall, 1, 0xff, 0x3, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } + +jmp, 1, 0xeb, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jmp, 1, 0xff, 0x4, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } +jmp, 1, 0xff, 0x4, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } +// Intel Syntax. +jmp, 2, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } +// Intel Syntax. +jmp, 1, 0xff, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } +ljmp, 2, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } +ljmp, 1, 0xff, 0x5, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } + +ret, 0, 0xc3, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +ret, 1, 0xc2, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16 } +ret, 0, 0xc3, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } +ret, 1, 0xc2, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm16 } +lret, 0, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, { 0 } +lret, 1, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, { Imm16 } +enter, 2, 0xc8, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm8 } +enter, 2, 0xc8, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm16, Imm8 } +leave, 0, 0xc9, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +leave, 0, 0xc9, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } + +// Conditional jumps. +jo, 1, 0x70, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jno, 1, 0x71, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jb, 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jc, 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jnae, 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jnb, 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jnc, 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jae, 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +je, 1, 0x74, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jz, 1, 0x74, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jne, 1, 0x75, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jnz, 1, 0x75, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jbe, 1, 0x76, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jna, 1, 0x76, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jnbe, 1, 0x77, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +ja, 1, 0x77, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +js, 1, 0x78, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jns, 1, 0x79, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jp, 1, 0x7a, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jpe, 1, 0x7a, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jnp, 1, 0x7b, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jpo, 1, 0x7b, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jl, 1, 0x7c, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jnge, 1, 0x7c, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jnl, 1, 0x7d, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jge, 1, 0x7d, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jle, 1, 0x7e, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jng, 1, 0x7e, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jnle, 1, 0x7f, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jg, 1, 0x7f, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } + +// jcxz vs. jecxz is chosen on the basis of the address size prefix. +jcxz, 1, 0xe3, None, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jecxz, 1, 0xe3, None, CpuNo64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jecxz, 1, 0x67e3, None, Cpu64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +jrcxz, 1, 0xe3, None, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } + +// The loop instructions also use the address size prefix to select +// %cx rather than %ecx for the loop count, so the `w' form of these +// instructions emit an address size prefix rather than a data size +// prefix. +loop, 1, 0xe2, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +loop, 1, 0xe2, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +loopz, 1, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +loopz, 1, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +loope, 1, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +loope, 1, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +loopnz, 1, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +loopnz, 1, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +loopne, 1, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } +loopne, 1, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } + +// Set byte on flag instructions. +seto, 1, 0xf90, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setno, 1, 0xf91, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setb, 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setc, 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnae, 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnb, 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnc, 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setae, 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sete, 1, 0xf94, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setz, 1, 0xf94, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setne, 1, 0xf95, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnz, 1, 0xf95, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setbe, 1, 0xf96, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setna, 1, 0xf96, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnbe, 1, 0xf97, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +seta, 1, 0xf97, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sets, 1, 0xf98, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setns, 1, 0xf99, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setp, 1, 0xf9a, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setpe, 1, 0xf9a, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnp, 1, 0xf9b, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setpo, 1, 0xf9b, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setl, 1, 0xf9c, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnge, 1, 0xf9c, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnl, 1, 0xf9d, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setge, 1, 0xf9d, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setle, 1, 0xf9e, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setng, 1, 0xf9e, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setnle, 1, 0xf9f, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +setg, 1, 0xf9f, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// String manipulation. +cmps, 0, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +cmps, 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +scmp, 0, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +scmp, 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +ins, 0, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } +ins, 2, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { InOutPortReg, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +outs, 0, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } +outs, 2, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, InOutPortReg } +lods, 0, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +lods, 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lods, 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } +slod, 0, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +slod, 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +slod, 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } +movs, 0, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +movs, 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +smov, 0, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +smov, 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +scas, 0, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +scas, 1, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +scas, 2, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc } +ssca, 0, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +ssca, 1, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +ssca, 2, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc } +stos, 0, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +stos, 1, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +stos, 2, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { Acc, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +ssto, 0, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } +ssto, 1, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +ssto, 2, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { Acc, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +xlat, 0, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } +xlat, 1, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Bit manipulation. +bsf, 2, 0xfbc, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +bsr, 2, 0xfbd, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +bt, 2, 0xfa3, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +bt, 2, 0xfba, 0x4, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +btc, 2, 0xfbb, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +btc, 2, 0xfba, 0x7, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +btr, 2, 0xfb3, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +btr, 2, 0xfba, 0x6, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +bts, 2, 0xfab, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +bts, 2, 0xfba, 0x5, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Interrupts & op. sys insns. +// See gas/config/tc-i386.c for conversion of 'int $3' into the special +// int 3 insn. +int, 1, 0xcd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8 } +int3, 0, 0xcc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +into, 0, 0xce, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +iret, 0, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, { 0 } +// i386sl, i486sl, later 486, and Pentium. +rsm, 0, 0xfaa, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +bound, 2, 0x62, None, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64, BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +hlt, 0, 0xf4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +nop, 1, 0xf1f, 0x0, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in +// 32bit mode and "xchg %rax,%rax" in 64bit mode. +nop, 0, 0x90, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// Protection control. +arpl, 2, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16, Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lar, 2, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +lgdt, 1, 0xf01, 0x2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lgdt, 1, 0xf01, 0x2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lidt, 1, 0xf01, 0x3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lidt, 1, 0xf01, 0x3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lldt, 1, 0xf00, 0x2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lmsw, 1, 0xf01, 0x6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lsl, 2, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +ltr, 1, 0xf00, 0x3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +sgdt, 1, 0xf01, 0x0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sgdt, 1, 0xf01, 0x0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sidt, 1, 0xf01, 0x1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sidt, 1, 0xf01, 0x1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +sldt, 1, 0xf00, 0x0, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64 } +sldt, 1, 0xf00, 0x0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +smsw, 1, 0xf01, 0x4, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64 } +smsw, 1, 0xf01, 0x4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +str, 1, 0xf00, 0x1, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64 } +str, 1, 0xf00, 0x1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +verr, 1, 0xf00, 0x4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +verw, 1, 0xf00, 0x5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Floating point instructions. + +// load +fld, 1, 0xd9c0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fld, 1, 0xd9, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fld, 1, 0xd9c0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } +// Intel Syntax +fld, 1, 0xdb, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fild, 1, 0xdf, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fild, 1, 0xdf, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fildll, 1, 0xdf, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fldt, 1, 0xdb, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fbld, 1, 0xdf, 0x4, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// store (no pop) +fst, 1, 0xddd0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fst, 1, 0xd9, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fst, 1, 0xddd0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } +fist, 1, 0xdf, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// store (with pop) +fstp, 1, 0xddd8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fstp, 1, 0xd9, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstp, 1, 0xddd8, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } +// Intel Syntax +fstp, 1, 0xdb, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fistp, 1, 0xdf, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fistp, 1, 0xdf, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fistpll, 1, 0xdf, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstpt, 1, 0xdb, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fbstp, 1, 0xdf, 0x6, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// exchange %st<n> with %st0 +fxch, 1, 0xd9c8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +// alias for fxch %st(1) +fxch, 0, 0xd9c9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// comparison (without pop) +fcom, 1, 0xd8d0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +// alias for fcom %st(1) +fcom, 0, 0xd8d1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fcom, 1, 0xd8, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fcom, 1, 0xd8d0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } +ficom, 1, 0xde, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// comparison (with pop) +fcomp, 1, 0xd8d8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +// alias for fcomp %st(1) +fcomp, 0, 0xd8d9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fcomp, 1, 0xd8, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fcomp, 1, 0xd8d8, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } +ficomp, 1, 0xde, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fcompp, 0, 0xded9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// unordered comparison (with pop) +fucom, 1, 0xdde0, None, Cpu286, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +// alias for fucom %st(1) +fucom, 0, 0xdde1, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fucomp, 1, 0xdde8, None, Cpu286, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +// alias for fucomp %st(1) +fucomp, 0, 0xdde9, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fucompp, 0, 0xdae9, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +ftst, 0, 0xd9e4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fxam, 0, 0xd9e5, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// load constants into %st0 +fld1, 0, 0xd9e8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fldl2t, 0, 0xd9e9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fldl2e, 0, 0xd9ea, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fldpi, 0, 0xd9eb, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fldlg2, 0, 0xd9ec, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fldln2, 0, 0xd9ed, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fldz, 0, 0xd9ee, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// Arithmetic. + +// add +fadd, 2, 0xd8c0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +// alias for fadd %st(i), %st +fadd, 1, 0xd8c0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +#if SYSV386_COMPAT +// alias for faddp +fadd, 0, 0xdec1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } +#endif +fadd, 1, 0xd8, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fiadd, 1, 0xde, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +faddp, 2, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } +faddp, 1, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +// alias for faddp %st, %st(1) +faddp, 0, 0xdec1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +faddp, 2, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } + +// subtract +fsub, 1, 0xd8e0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +#if SYSV386_COMPAT +fsub, 2, 0xd8e0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +// alias for fsubp +fsub, 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } +#else +fsub, 2, 0xd8e0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } +#endif +fsub, 1, 0xd8, 0x4, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fisub, 1, 0xde, 0x4, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +#if SYSV386_COMPAT +fsubp, 2, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } +fsubp, 1, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fsubp, 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +#if OLDGCC_COMPAT +fsubp, 2, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } +#endif +#else +fsubp, 2, 0xdee8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } +fsubp, 1, 0xdee8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } +fsubp, 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } +#endif + +// subtract reverse +fsubr, 1, 0xd8e8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +#if SYSV386_COMPAT +fsubr, 2, 0xd8e8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +// alias for fsubrp +fsubr, 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } +#else +fsubr, 2, 0xd8e8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } +#endif +fsubr, 1, 0xd8, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fisubr, 1, 0xde, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +#if SYSV386_COMPAT +fsubrp, 2, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } +fsubrp, 1, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fsubrp, 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +#if OLDGCC_COMPAT +fsubrp, 2, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } +#endif +#else +fsubrp, 2, 0xdee0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } +fsubrp, 1, 0xdee0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } +fsubrp, 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } +#endif + +// multiply +fmul, 2, 0xd8c8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fmul, 1, 0xd8c8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +#if SYSV386_COMPAT +// alias for fmulp +fmul, 0, 0xdec9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } +#endif +fmul, 1, 0xd8, 0x1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fimul, 1, 0xde, 0x1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +fmulp, 2, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } +fmulp, 1, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fmulp, 0, 0xdec9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fmulp, 2, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } + +// divide +fdiv, 1, 0xd8f0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +#if SYSV386_COMPAT +fdiv, 2, 0xd8f0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +// alias for fdivp +fdiv, 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } +#else +fdiv, 2, 0xd8f0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } +#endif +fdiv, 1, 0xd8, 0x6, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fidiv, 1, 0xde, 0x6, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +#if SYSV386_COMPAT +fdivp, 2, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } +fdivp, 1, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fdivp, 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +#if OLDGCC_COMPAT +fdivp, 2, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } +#endif +#else +fdivp, 2, 0xdef8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } +fdivp, 1, 0xdef8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } +fdivp, 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } +#endif + +// divide reverse +fdivr, 1, 0xd8f8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +#if SYSV386_COMPAT +fdivr, 2, 0xd8f8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +// alias for fdivrp +fdivr, 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } +#else +fdivr, 2, 0xd8f8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } +#endif +fdivr, 1, 0xd8, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fidivr, 1, 0xde, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +#if SYSV386_COMPAT +fdivrp, 2, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } +fdivrp, 1, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fdivrp, 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +#if OLDGCC_COMPAT +fdivrp, 2, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } +#endif +#else +fdivrp, 2, 0xdef0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } +fdivrp, 1, 0xdef0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } +fdivrp, 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } +#endif + +f2xm1, 0, 0xd9f0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fyl2x, 0, 0xd9f1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fptan, 0, 0xd9f2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fpatan, 0, 0xd9f3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fxtract, 0, 0xd9f4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fprem1, 0, 0xd9f5, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fdecstp, 0, 0xd9f6, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fincstp, 0, 0xd9f7, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fprem, 0, 0xd9f8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fyl2xp1, 0, 0xd9f9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fsqrt, 0, 0xd9fa, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fsincos, 0, 0xd9fb, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +frndint, 0, 0xd9fc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fscale, 0, 0xd9fd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fsin, 0, 0xd9fe, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fcos, 0, 0xd9ff, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fchs, 0, 0xd9e0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fabs, 0, 0xd9e1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// processor control +fninit, 0, 0xdbe3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +finit, 0, 0xdbe3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { 0 } +fldcw, 1, 0xd9, 0x5, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fnstcw, 1, 0xd9, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstcw, 1, 0xd9, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +// XXX should reject %al, %eax, and %rax +fnstsw, 1, 0xdfe0, None, 0, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Acc } +fnstsw, 1, 0xdd, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fnstsw, 0, 0xdfe0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +// XXX should reject %al, %eax, and %rax +fstsw, 1, 0xdfe0, None, 0, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { Acc } +fstsw, 1, 0xdd, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstsw, 0, 0xdfe0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { 0 } +fnclex, 0, 0xdbe2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fclex, 0, 0xdbe2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { 0 } +// Short forms of fldenv, fstenv use data size prefix. +fnstenv, 1, 0xd9, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fstenv, 1, 0xd9, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fldenv, 1, 0xd9, 0x4, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fnsave, 1, 0xdd, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fsave, 1, 0xdd, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +frstor, 1, 0xdd, 0x4, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +ffree, 1, 0xddc0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +// P6:free st(i), pop st +ffreep, 1, 0xdfc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fnop, 0, 0xd9d0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fwait, 0, 0x9b, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// Opcode prefixes; we allow them as separate insns too. + +addr16, 0, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +addr32, 0, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +aword, 0, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +adword, 0, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +data16, 0, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +data32, 0, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +word, 0, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +dword, 0, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +lock, 0, 0xf0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +wait, 0, 0x9b, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +cs, 0, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +ds, 0, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +es, 0, 0x26, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +fs, 0, 0x64, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +gs, 0, 0x65, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +ss, 0, 0x36, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rep, 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +repe, 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +repz, 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +repne, 0, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +repnz, 0, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +ht, 0, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +hnt, 0, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex, 0, 0x40, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rexz, 0, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rexy, 0, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rexyz, 0, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rexx, 0, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rexxz, 0, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rexxy, 0, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rexxyz, 0, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex64, 0, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex64z, 0, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex64y, 0, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex64yz, 0, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex64x, 0, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex64xz, 0, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex64xy, 0, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex64xyz, 0, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.b, 0, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.x, 0, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.xb, 0, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.r, 0, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.rb, 0, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.rx, 0, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.rxb, 0, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.w, 0, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.wb, 0, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.wx, 0, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.wxb, 0, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.wr, 0, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.wrb, 0, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.wrx, 0, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } +rex.wrxb, 0, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } + +// 486 extensions. + +bswap, 1, 0xfc8, None, Cpu486, ShortForm|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64 } +xadd, 2, 0xfc0, None, Cpu486, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +cmpxchg, 2, 0xfb0, None, Cpu486, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +invd, 0, 0xf08, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +wbinvd, 0, 0xf09, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +invlpg, 1, 0xf01, 0x7, Cpu486, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// 586 and late 486 extensions. +cpuid, 0, 0xfa2, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// Pentium extensions. +wrmsr, 0, 0xf30, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +rdtsc, 0, 0xf31, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +rdmsr, 0, 0xf32, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +cmpxchg8b, 1, 0xfc7, 0x1, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Pentium II/Pentium Pro extensions. +sysenter, 0, 0xf34, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +sysexit, 0, 0xf35, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fxsave, 1, 0xfae, 0x0, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fxrstor, 1, 0xfae, 0x1, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +rdpmc, 0, 0xf33, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +// official undefined instr. +ud2, 0, 0xf0b, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +// alias for ud2 +ud2a, 0, 0xf0b, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +// 2nd. official undefined instr. +ud2b, 0, 0xfb9, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +cmovo, 2, 0xf40, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovno, 2, 0xf41, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovb, 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovc, 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnae, 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovae, 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnc, 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnb, 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmove, 2, 0xf44, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovz, 2, 0xf44, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovne, 2, 0xf45, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnz, 2, 0xf45, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovbe, 2, 0xf46, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovna, 2, 0xf46, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmova, 2, 0xf47, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnbe, 2, 0xf47, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovs, 2, 0xf48, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovns, 2, 0xf49, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovp, 2, 0xf4a, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnp, 2, 0xf4b, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovl, 2, 0xf4c, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnge, 2, 0xf4c, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovge, 2, 0xf4d, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnl, 2, 0xf4d, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovle, 2, 0xf4e, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovng, 2, 0xf4e, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovg, 2, 0xf4f, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +cmovnle, 2, 0xf4f, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + +fcmovb, 2, 0xdac0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmovnae, 2, 0xdac0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmove, 2, 0xdac8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmovbe, 2, 0xdad0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmovna, 2, 0xdad0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmovu, 2, 0xdad8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmovae, 2, 0xdbc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmovnb, 2, 0xdbc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmovne, 2, 0xdbc8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmova, 2, 0xdbd0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmovnbe, 2, 0xdbd0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcmovnu, 2, 0xdbd8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } + +fcomi, 2, 0xdbf0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcomi, 0, 0xdbf1, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fcomi, 1, 0xdbf0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fucomi, 2, 0xdbe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fucomi, 0, 0xdbe9, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fucomi, 1, 0xdbe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fcomip, 2, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcompi, 2, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fcompi, 0, 0xdff1, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fcompi, 1, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } +fucomip, 2, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fucompi, 2, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } +fucompi, 0, 0xdfe9, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +fucompi, 1, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } + +// Pentium4 extensions. + +movnti, 2, 0xfc3, None, CpuP4, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +clflush, 1, 0xfae, 0x7, CpuP4, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +lfence, 0, 0xfae, 0xe8, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +mfence, 0, 0xfae, 0xf0, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +pause, 0, 0xf390, None, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } + +// MMX/SSE2 instructions. + +emms, 0, 0xf77, None, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +// These really shouldn't allow for Reg64 (movq is the right mnemonic for +// copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's +// spec). AMD's spec, having been in existence for much longer, failed to +// recognize that and specified movd for 32- and 64-bit operations. +movd, 2, 0xf6e, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } +movd, 2, 0xf7e, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movd, 2, 0x660f6e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movd, 2, 0x660f7e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +// In the 64bit mode the short form mov immediate is redefined to have +// 64bit displacement value. +movq, 2, 0xf6f, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +movq, 2, 0xf7f, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } +movq, 2, 0xf30f7e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movq, 2, 0x660fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movq, 2, 0xf6e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } +movq, 2, 0xf7e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movq, 2, 0x660f6e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movq, 2, 0x660f7e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +// We put the 64bit displacement first and we only mark constants +// larger than 32bit as Disp64. +movq, 2, 0xa0, None, Cpu64, D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp64, Acc } +movq, 2, 0x88, None, Cpu64, D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movq, 2, 0xc6, 0x0, Cpu64, W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm32S, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movq, 2, 0xb0, None, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm64, Reg64 } +// The segment register moves accept Reg64 so that a segment register +// can be copied to a 64 bit register, and vice versa. +movq, 2, 0x8c, None, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2|SReg3, Reg64|RegMem } +movq, 2, 0x8e, None, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64, SReg2|SReg3 } +// Move to/from control debug registers. In the 16 or 32bit modes they +// are 32bit. In the 64bit mode they are 64bit. +movq, 2, 0xf20, None, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Control, Reg64|RegMem } +movq, 2, 0xf21, None, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Debug, Reg64|RegMem } +// Real MMX instructions. +packssdw, 2, 0xf6b, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packssdw, 2, 0x660f6b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packsswb, 2, 0xf63, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packsswb, 2, 0x660f63, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packuswb, 2, 0xf67, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +packuswb, 2, 0x660f67, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddb, 2, 0xffc, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddb, 2, 0x660ffc, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddw, 2, 0xffd, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddw, 2, 0x660ffd, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddd, 2, 0xffe, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddd, 2, 0x660ffe, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddq, 2, 0xfd4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddq, 2, 0x660fd4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddsb, 2, 0xfec, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddsb, 2, 0x660fec, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddsw, 2, 0xfed, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddsw, 2, 0x660fed, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddusb, 2, 0xfdc, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddusb, 2, 0x660fdc, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +paddusw, 2, 0xfdd, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +paddusw, 2, 0x660fdd, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pand, 2, 0xfdb, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pand, 2, 0x660fdb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pandn, 2, 0xfdf, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pandn, 2, 0x660fdf, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqb, 2, 0xf74, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqb, 2, 0x660f74, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqw, 2, 0xf75, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqw, 2, 0x660f75, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqd, 2, 0xf76, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpeqd, 2, 0x660f76, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtb, 2, 0xf64, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtb, 2, 0x660f64, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtw, 2, 0xf65, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtw, 2, 0x660f65, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpgtd, 2, 0xf66, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pcmpgtd, 2, 0x660f66, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaddwd, 2, 0xff5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaddwd, 2, 0x660ff5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulhw, 2, 0xfe5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhw, 2, 0x660fe5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmullw, 2, 0xfd5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmullw, 2, 0x660fd5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +por, 2, 0xfeb, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +por, 2, 0x660feb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psllw, 2, 0xff1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psllw, 2, 0x660ff1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psllw, 2, 0xf71, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } +psllw, 2, 0x660f71, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +pslld, 2, 0xff2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pslld, 2, 0x660ff2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pslld, 2, 0xf72, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } +pslld, 2, 0x660f72, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +psllq, 2, 0xff3, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psllq, 2, 0x660ff3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psllq, 2, 0xf73, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } +psllq, 2, 0x660f73, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +psraw, 2, 0xfe1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psraw, 2, 0x660fe1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psraw, 2, 0xf71, 0x4, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } +psraw, 2, 0x660f71, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +psrad, 2, 0xfe2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrad, 2, 0x660fe2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrad, 2, 0xf72, 0x4, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } +psrad, 2, 0x660f72, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +psrlw, 2, 0xfd1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrlw, 2, 0x660fd1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrlw, 2, 0xf71, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } +psrlw, 2, 0x660f71, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +psrld, 2, 0xfd2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrld, 2, 0x660fd2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrld, 2, 0xf72, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } +psrld, 2, 0x660f72, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +psrlq, 2, 0xfd3, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psrlq, 2, 0x660fd3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psrlq, 2, 0xf73, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } +psrlq, 2, 0x660f73, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +psubb, 2, 0xff8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubb, 2, 0x660ff8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubw, 2, 0xff9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubw, 2, 0x660ff9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubd, 2, 0xffa, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubd, 2, 0x660ffa, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubq, 2, 0xffb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubq, 2, 0x660ffb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubsb, 2, 0xfe8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubsb, 2, 0x660fe8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubsw, 2, 0xfe9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubsw, 2, 0x660fe9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubusb, 2, 0xfd8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubusb, 2, 0x660fd8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psubusw, 2, 0xfd9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psubusw, 2, 0x660fd9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhbw, 2, 0xf68, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhbw, 2, 0x660f68, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhwd, 2, 0xf69, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhwd, 2, 0x660f69, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckhdq, 2, 0xf6a, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckhdq, 2, 0x660f6a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklbw, 2, 0xf60, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpcklbw, 2, 0x660f60, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklwd, 2, 0xf61, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpcklwd, 2, 0x660f61, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpckldq, 2, 0xf62, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +punpckldq, 2, 0x660f62, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pxor, 2, 0xfef, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pxor, 2, 0x660fef, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// PIII Katmai New Instructions / SIMD instructions. + +addps, 2, 0xf58, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addss, 2, 0xf30f58, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andnps, 2, 0xf55, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andps, 2, 0xf54, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqps, 2, 0xfc2, 0x0, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqss, 2, 0xf30fc2, 0x0, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpleps, 2, 0xfc2, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpless, 2, 0xf30fc2, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltps, 2, 0xfc2, 0x1, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltss, 2, 0xf30fc2, 0x1, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqps, 2, 0xfc2, 0x4, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqss, 2, 0xf30fc2, 0x4, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnleps, 2, 0xfc2, 0x6, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnless, 2, 0xf30fc2, 0x6, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltps, 2, 0xfc2, 0x5, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltss, 2, 0xf30fc2, 0x5, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordps, 2, 0xfc2, 0x7, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordss, 2, 0xf30fc2, 0x7, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordps, 2, 0xfc2, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordss, 2, 0xf30fc2, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpps, 3, 0xfc2, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpss, 3, 0xf30fc2, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +comiss, 2, 0xf2f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpi2ps, 2, 0xf2a, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } +cvtps2pi, 2, 0xf2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvtsi2ss, 2, 0xf30f2a, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +cvtss2si, 2, 0xf30f2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvttps2pi, 2, 0xf2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvttss2si, 2, 0xf30f2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +divps, 2, 0xf5e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divss, 2, 0xf30f5e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ldmxcsr, 1, 0xfae, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +maskmovq, 2, 0xff7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, RegMMX } +maxps, 2, 0xf5f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxss, 2, 0xf30f5f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minps, 2, 0xf5d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minss, 2, 0xf30f5d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movaps, 2, 0xf28, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movaps, 2, 0xf29, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movhlps, 2, 0xf12, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } +movhps, 2, 0xf16, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movhps, 2, 0xf17, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movlhps, 2, 0xf16, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } +movlps, 2, 0xf12, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movlps, 2, 0xf13, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movmskps, 2, 0xf50, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegXMM, Reg32|Reg64 } +movntps, 2, 0xf2b, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntq, 2, 0xfe7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntdq, 2, 0x660fe7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movss, 2, 0xf30f10, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movss, 2, 0xf30f11, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movups, 2, 0xf10, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movups, 2, 0xf11, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +mulps, 2, 0xf59, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulss, 2, 0xf30f59, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +orps, 2, 0xf56, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pavgb, 2, 0xfe0, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pavgb, 2, 0x660fe0, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pavgw, 2, 0xfe3, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pavgw, 2, 0x660fe3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pextrw, 3, 0xfc5, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, RegMMX, Reg32|Reg64 } +pextrw, 3, 0x660fc5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64 } + +// Streaming SIMD extensions 4.1 Instructions. +pextrw, 3, 0x660f3a15, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +pinsrw, 3, 0xfc4, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } +pinsrw, 3, 0x660fc4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pmaxsw, 2, 0xfee, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaxsw, 2, 0x660fee, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxub, 2, 0xfde, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaxub, 2, 0x660fde, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsw, 2, 0xfea, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pminsw, 2, 0x660fea, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminub, 2, 0xfda, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pminub, 2, 0x660fda, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovmskb, 2, 0xfd7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegMMX, Reg32|Reg64 } +pmovmskb, 2, 0x660fd7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegXMM, Reg32|Reg64 } +pmulhuw, 2, 0xfe4, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhuw, 2, 0x660fe4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +prefetchnta, 1, 0xf18, 0x0, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +prefetcht0, 1, 0xf18, 0x1, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +prefetcht1, 1, 0xf18, 0x2, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +prefetcht2, 1, 0xf18, 0x3, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +psadbw, 2, 0xff6, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psadbw, 2, 0x660ff6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufw, 3, 0xf70, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +rcpps, 2, 0xf53, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rcpss, 2, 0xf30f53, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rsqrtps, 2, 0xf52, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +rsqrtss, 2, 0xf30f52, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sfence, 0, 0xfae, 0xf8, CpuMMX2, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +shufps, 3, 0xfc6, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtps, 2, 0xf51, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtss, 2, 0xf30f51, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +stmxcsr, 1, 0xfae, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +subps, 2, 0xf5c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subss, 2, 0xf30f5c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ucomiss, 2, 0xf2e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpckhps, 2, 0xf15, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpcklps, 2, 0xf14, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +xorps, 2, 0xf57, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// SSE-2 instructions. + +addpd, 2, 0x660f58, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addsd, 2, 0xf20f58, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andnpd, 2, 0x660f55, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +andpd, 2, 0x660f54, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqpd, 2, 0x660fc2, 0x0, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpeqsd, 2, 0xf20fc2, 0x0, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmplepd, 2, 0x660fc2, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmplesd, 2, 0xf20fc2, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltpd, 2, 0x660fc2, 0x1, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpltsd, 2, 0xf20fc2, 0x1, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqpd, 2, 0x660fc2, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpneqsd, 2, 0xf20fc2, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnlepd, 2, 0x660fc2, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnlesd, 2, 0xf20fc2, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltpd, 2, 0x660fc2, 0x5, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpnltsd, 2, 0xf20fc2, 0x5, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordpd, 2, 0x660fc2, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpordsd, 2, 0xf20fc2, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordpd, 2, 0x660fc2, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpunordsd, 2, 0xf20fc2, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmppd, 3, 0x660fc2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +// Intel mode string compare. +cmpsd, 0, 0xa7, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } +cmpsd, 2, 0xa7, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +cmpsd, 3, 0xf20fc2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +comisd, 2, 0x660f2f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpi2pd, 2, 0x660f2a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } +cvtsi2sd, 2, 0xf20f2a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +divpd, 2, 0x660f5e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +divsd, 2, 0xf20f5e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxpd, 2, 0x660f5f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maxsd, 2, 0xf20f5f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minpd, 2, 0x660f5d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +minsd, 2, 0xf20f5d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movapd, 2, 0x660f28, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movapd, 2, 0x660f29, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movhpd, 2, 0x660f16, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movhpd, 2, 0x660f17, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movlpd, 2, 0x660f12, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movlpd, 2, 0x660f13, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movmskpd, 2, 0x660f50, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegXMM, Reg32|Reg64 } +movntpd, 2, 0x660f2b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +// Intel mode string move. +movsd, 0, 0xa5, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } +movsd, 2, 0xa5, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } +movsd, 2, 0xf20f10, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movsd, 2, 0xf20f11, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movupd, 2, 0x660f10, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movupd, 2, 0x660f11, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +mulpd, 2, 0x660f59, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mulsd, 2, 0xf20f59, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +orpd, 2, 0x660f56, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +shufpd, 3, 0x660fc6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtpd, 2, 0x660f51, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +sqrtsd, 2, 0xf20f51, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subpd, 2, 0x660f5c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +subsd, 2, 0xf20f5c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ucomisd, 2, 0x660f2e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpckhpd, 2, 0x660f15, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +unpcklpd, 2, 0x660f14, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +xorpd, 2, 0x660f57, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtdq2pd, 2, 0xf30fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpd2dq, 2, 0xf20fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtdq2ps, 2, 0xf5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtpd2pi, 2, 0x660f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvtpd2ps, 2, 0x660f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtps2pd, 2, 0xf5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtps2dq, 2, 0x660f5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtsd2si, 2, 0xf20f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvtsd2ss, 2, 0xf20f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvtss2sd, 2, 0xf30f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvttpd2pi, 2, 0x660f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } +cvttsd2si, 2, 0xf20f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } +cvttpd2dq, 2, 0x660fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cvttps2dq, 2, 0xf30f5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +maskmovdqu, 2, 0x660ff7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } +movdqa, 2, 0x660f6f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqa, 2, 0x660f7f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movdqu, 2, 0xf30f6f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqu, 2, 0xf30f7f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movdq2q, 2, 0xf20fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegMMX } +movq2dq, 2, 0xf30fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, RegXMM } +pmuludq, 2, 0xff4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmuludq, 2, 0x660ff4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufd, 3, 0x660f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufhw, 3, 0xf30f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshuflw, 3, 0xf20f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pslldq, 2, 0x660f73, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +psrldq, 2, 0x660f73, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } +punpckhqdq, 2, 0x660f6d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +punpcklqdq, 2, 0x660f6c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// SSE-3 instructions. + +addsubpd, 2, 0x660fd0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +addsubps, 2, 0xf20fd0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +cmpxchg16b, 1, 0xfc7, 0x1, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fisttp, 1, 0xdf, 0x1, CpuSSE3, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fisttp, 1, 0xdd, 0x1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fisttpll, 1, 0xdd, 0x1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +haddpd, 2, 0x660f7c, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +haddps, 2, 0xf20f7c, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +hsubpd, 2, 0x660f7d, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +hsubps, 2, 0xf20f7d, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +lddqu, 2, 0xf20ff0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +monitor, 0, 0xf01, 0xc8, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +// monitor is very special. CX and DX are always 64bits with zero upper +// 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The +// address size override prefix can be used to overrride the AX size in +// all modes. +// Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. +monitor, 3, 0xf01, 0xc8, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg16|Reg32, Reg32, Reg32 } +// Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. +monitor, 3, 0xf01, 0xc8, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64, Reg64, Reg64 } +movddup, 2, 0xf20f12, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movshdup, 2, 0xf30f16, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movsldup, 2, 0xf30f12, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +mwait, 0, 0xf01, 0xc9, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +// mwait is very special. AX and CX are always 64bits with zero upper +// 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. +// Need to ensure only "mwait %eax,%ecx" is accepted. +mwait, 2, 0xf01, 0xc9, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg32, Reg32 } +// Need to ensure only "mwait %rax,%rcx" is accepted. +mwait, 2, 0xf01, 0xc9, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64, Reg64 } + +// VMX instructions. +vmcall, 0, 0xf01, 0xc1, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +vmclear, 1, 0x660fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmlaunch, 0, 0xf01, 0xc2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +vmresume, 0, 0xf01, 0xc3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +vmptrld, 1, 0xfc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmptrst, 1, 0xfc7, 0x7, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmread, 2, 0xf78, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmread, 2, 0xf78, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg64, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmwrite, 2, 0xf79, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +vmwrite, 2, 0xf79, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } +vmxoff, 0, 0xf01, 0xc4, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +vmxon, 1, 0xf30fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + +// Supplemental Streaming SIMD extensions 3 Instructions. + +phaddw, 2, 0xf3801, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddw, 2, 0x660f3801, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phaddd, 2, 0xf3802, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddd, 2, 0x660f3802, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phaddsw, 2, 0xf3803, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phaddsw, 2, 0x660f3803, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phsubw, 2, 0xf3805, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubw, 2, 0x660f3805, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phsubd, 2, 0xf3806, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubd, 2, 0x660f3806, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +phsubsw, 2, 0xf3807, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +phsubsw, 2, 0x660f3807, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaddubsw, 2, 0xf3804, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmaddubsw, 2, 0x660f3804, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulhrsw, 2, 0xf380b, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhrsw, 2, 0x660f380b, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pshufb, 2, 0xf3800, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pshufb, 2, 0x660f3800, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psignb, 2, 0xf3808, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignb, 2, 0x660f3808, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psignw, 2, 0xf3809, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignw, 2, 0x660f3809, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +psignd, 2, 0xf380a, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +psignd, 2, 0x660f380a, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +palignr, 3, 0xf3a0f, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +palignr, 3, 0x660f3a0f, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsb, 2, 0xf381c, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsb, 2, 0x660f381c, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsw, 2, 0xf381d, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsw, 2, 0x660f381d, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pabsd, 2, 0xf381e, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pabsd, 2, 0x660f381e, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// Streaming SIMD extensions 4.1 Instructions. + +blendpd, 3, 0x660f3a0d, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendps, 3, 0x660f3a0c, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvpd, 3, 0x660f3815, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +blendvps, 3, 0x660f3814, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +dppd, 3, 0x660f3a41, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +dpps, 3, 0x660f3a40, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +extractps, 3, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +insertps, 3, 0x660f3a21, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movntdqa, 2, 0x660f382a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +mpsadbw, 3, 0x660f3a42, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +packusdw, 2, 0x660f382b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendvb, 3, 0x660f3810, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pblendw, 3, 0x660f3a0e, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpeqq, 2, 0x660f3829, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pextrb, 3, 0x660f3a14, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrd, 3, 0x660f3a16, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +pextrq, 3, 0x660f3a16, None, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +phminposuw, 2, 0x660f3841, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pinsrb, 3, 0x660f3a20, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrd, 3, 0x660f3a22, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pinsrq, 3, 0x660f3a22, None, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +pmaxsb, 2, 0x660f383c, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxsd, 2, 0x660f383d, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxud, 2, 0x660f383f, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmaxuw, 2, 0x660f383e, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsb, 2, 0x660f3838, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminsd, 2, 0x660f3839, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminud, 2, 0x660f383b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pminuw, 2, 0x660f383a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbw, 2, 0x660f3820, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbd, 2, 0x660f3821, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxbq, 2, 0x660f3822, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxwd, 2, 0x660f3823, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxwq, 2, 0x660f3824, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovsxdq, 2, 0x660f3825, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbw, 2, 0x660f3830, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbd, 2, 0x660f3831, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxbq, 2, 0x660f3832, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxwd, 2, 0x660f3833, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxwq, 2, 0x660f3834, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmovzxdq, 2, 0x660f3835, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmuldq, 2, 0x660f3828, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pmulld, 2, 0x660f3840, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +ptest, 2, 0x660f3817, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundpd, 3, 0x660f3a09, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundps, 3, 0x660f3a08, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundsd, 3, 0x660f3a0b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +roundss, 3, 0x660f3a0a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } + +// Streaming SIMD extensions 4.2 Instructions. + +pcmpgtq, 2, 0x660f3837, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpestri, 3, 0x660f3a61, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpestrm, 3, 0x660f3a60, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpistri, 3, 0x660f3a63, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pcmpistrm, 3, 0x660f3a62, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +// We put non-8bit version before 8bit so that crc32 with memory operand +// defaults to non-8bit. +crc32, 2, 0xf20f38f1, None, CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +crc32, 2, 0xf20f38f1, None, CpuSSE4_2|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|Rex64, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } +crc32, 2, 0xf20f38f0, None, CpuSSE4_2, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +crc32, 2, 0xf20f38f0, None, CpuSSE4_2|Cpu64, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } + +// AMD 3DNow! instructions. + +prefetch, 1, 0xf0d, 0x0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +prefetchw, 1, 0xf0d, 0x1, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +femms, 0, 0xf0e, None, Cpu3dnow, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +pavgusb, 2, 0xf0f, 0xbf, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pf2id, 2, 0xf0f, 0x1d, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pf2iw, 2, 0xf0f, 0x1c, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfacc, 2, 0xf0f, 0xae, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfadd, 2, 0xf0f, 0x9e, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfcmpeq, 2, 0xf0f, 0xb0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfcmpge, 2, 0xf0f, 0x90, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfcmpgt, 2, 0xf0f, 0xa0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfmax, 2, 0xf0f, 0xa4, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfmin, 2, 0xf0f, 0x94, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfmul, 2, 0xf0f, 0xb4, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfnacc, 2, 0xf0f, 0x8a, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfpnacc, 2, 0xf0f, 0x8e, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrcp, 2, 0xf0f, 0x96, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrcpit1, 2, 0xf0f, 0xa6, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrcpit2, 2, 0xf0f, 0xb6, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrsqit1, 2, 0xf0f, 0xa7, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfrsqrt, 2, 0xf0f, 0x97, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfsub, 2, 0xf0f, 0x9a, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pfsubr, 2, 0xf0f, 0xaa, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pi2fd, 2, 0xf0f, 0xd, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pi2fw, 2, 0xf0f, 0xc, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pmulhrw, 2, 0xf0f, 0xb7, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +pswapd, 2, 0xf0f, 0xbb, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } + +// AMD extensions. +syscall, 0, 0xf05, None, CpuK6, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } +sysret, 0, 0xf07, None, CpuK6, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { 0 } +swapgs, 0, 0xf01, 0xf8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +rdtscp, 0, 0xf01, 0xf9, CpuSledgehammer, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } + +// AMD Pacifica additions. +clgi, 0, 0xf01, 0xdd, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +invlpga, 0, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +// Need to ensure only "invlpga ...,%ecx" is accepted. +invlpga, 2, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } +skinit, 0, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +skinit, 1, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +stgi, 0, 0xf01, 0xdc, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +vmload, 0, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +vmload, 1, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmmcall, 0, 0xf01, 0xd9, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +vmrun, 0, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +vmrun, 1, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +vmsave, 0, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +vmsave, 1, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } + + +// SSE4a instructions +movntsd, 2, 0xf20f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movntss, 2, 0xf30f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } +extrq, 3, 0x660f78, 0x0, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Imm8, RegXMM } +extrq, 2, 0x660f79, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } +insertq, 2, 0xf20f79, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } +insertq, 4, 0xf20f78, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Imm8, RegXMM, RegXMM } + +// ABM instructions +popcnt, 2, 0xf30fb8, None, CpuABM|CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } +lzcnt, 2, 0xf30fbd, None, CpuABM, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + + +// VIA PadLock extensions. +xstore-rng, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcrypt-ecb, 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcrypt-cbc, 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcrypt-ctr, 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcrypt-cfb, 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcrypt-ofb, 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +montmul, 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xsha1, 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xsha256, 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +// Aliases without hyphens. +xstorerng, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcryptecb, 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcryptcbc, 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcryptctr, 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcryptcfb, 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +xcryptofb, 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } +// Alias for xstore-rng. +xstore, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } diff --git a/contrib/binutils/opcodes/i386-reg.tbl b/contrib/binutils/opcodes/i386-reg.tbl new file mode 100644 index 0000000..7240a10 --- /dev/null +++ b/contrib/binutils/opcodes/i386-reg.tbl @@ -0,0 +1,182 @@ +// i386 register table. + +// Make %st first as we test for it. +st, FloatReg|FloatAcc, 0, 0 +// 8 bit regs +al, Reg8|Acc, 0, 0 +cl, Reg8|ShiftCount, 0, 1 +dl, Reg8, 0, 2 +bl, Reg8, 0, 3 +ah, Reg8, 0, 4 +ch, Reg8, 0, 5 +dh, Reg8, 0, 6 +bh, Reg8, 0, 7 +axl, Reg8|Acc, RegRex64, 0 +cxl, Reg8, RegRex64, 1 +dxl, Reg8, RegRex64, 2 +bxl, Reg8, RegRex64, 3 +spl, Reg8, RegRex64, 4 +bpl, Reg8, RegRex64, 5 +sil, Reg8, RegRex64, 6 +dil, Reg8, RegRex64, 7 +r8b, Reg8, RegRex|RegRex64, 0 +r9b, Reg8, RegRex|RegRex64, 1 +r10b, Reg8, RegRex|RegRex64, 2 +r11b, Reg8, RegRex|RegRex64, 3 +r12b, Reg8, RegRex|RegRex64, 4 +r13b, Reg8, RegRex|RegRex64, 5 +r14b, Reg8, RegRex|RegRex64, 6 +r15b, Reg8, RegRex|RegRex64, 7 +// 16 bit regs +ax, Reg16|Acc, 0, 0 +cx, Reg16, 0, 1 +dx, Reg16|InOutPortReg, 0, 2 +bx, Reg16|BaseIndex, 0, 3 +sp, Reg16, 0, 4 +bp, Reg16|BaseIndex, 0, 5 +si, Reg16|BaseIndex, 0, 6 +di, Reg16|BaseIndex, 0, 7 +r8w, Reg16, RegRex, 0 +r9w, Reg16, RegRex, 1 +r10w, Reg16, RegRex, 2 +r11w, Reg16, RegRex, 3 +r12w, Reg16, RegRex, 4 +r13w, Reg16, RegRex, 5 +r14w, Reg16, RegRex, 6 +r15w, Reg16, RegRex, 7 +// 32 bit regs +eax, Reg32|BaseIndex|Acc, 0, 0 +ecx, Reg32|BaseIndex, 0, 1 +edx, Reg32|BaseIndex, 0, 2 +ebx, Reg32|BaseIndex, 0, 3 +esp, Reg32, 0, 4 +ebp, Reg32|BaseIndex, 0, 5 +esi, Reg32|BaseIndex, 0, 6 +edi, Reg32|BaseIndex, 0, 7 +r8d, Reg32|BaseIndex, RegRex, 0 +r9d, Reg32|BaseIndex, RegRex, 1 +r10d, Reg32|BaseIndex, RegRex, 2 +r11d, Reg32|BaseIndex, RegRex, 3 +r12d, Reg32|BaseIndex, RegRex, 4 +r13d, Reg32|BaseIndex, RegRex, 5 +r14d, Reg32|BaseIndex, RegRex, 6 +r15d, Reg32|BaseIndex, RegRex, 7 +rax, Reg64|BaseIndex|Acc, 0, 0 +rcx, Reg64|BaseIndex, 0, 1 +rdx, Reg64|BaseIndex, 0, 2 +rbx, Reg64|BaseIndex, 0, 3 +rsp, Reg64, 0, 4 +rbp, Reg64|BaseIndex, 0, 5 +rsi, Reg64|BaseIndex, 0, 6 +rdi, Reg64|BaseIndex, 0, 7 +r8, Reg64|BaseIndex, RegRex, 0 +r9, Reg64|BaseIndex, RegRex, 1 +r10, Reg64|BaseIndex, RegRex, 2 +r11, Reg64|BaseIndex, RegRex, 3 +r12, Reg64|BaseIndex, RegRex, 4 +r13, Reg64|BaseIndex, RegRex, 5 +r14, Reg64|BaseIndex, RegRex, 6 +r15, Reg64|BaseIndex, RegRex, 7 +// Segment registers. +es, SReg2, 0, 0 +cs, SReg2, 0, 1 +ss, SReg2, 0, 2 +ds, SReg2, 0, 3 +fs, SReg3, 0, 4 +gs, SReg3, 0, 5 +// Control registers. +cr0, Control, 0, 0 +cr1, Control, 0, 1 +cr2, Control, 0, 2 +cr3, Control, 0, 3 +cr4, Control, 0, 4 +cr5, Control, 0, 5 +cr6, Control, 0, 6 +cr7, Control, 0, 7 +cr8, Control, RegRex, 0 +cr9, Control, RegRex, 1 +cr10, Control, RegRex, 2 +cr11, Control, RegRex, 3 +cr12, Control, RegRex, 4 +cr13, Control, RegRex, 5 +cr14, Control, RegRex, 6 +cr15, Control, RegRex, 7 +// Debug registers. +db0, Debug, 0, 0 +db1, Debug, 0, 1 +db2, Debug, 0, 2 +db3, Debug, 0, 3 +db4, Debug, 0, 4 +db5, Debug, 0, 5 +db6, Debug, 0, 6 +db7, Debug, 0, 7 +db8, Debug, RegRex, 0 +db9, Debug, RegRex, 1 +db10, Debug, RegRex, 2 +db11, Debug, RegRex, 3 +db12, Debug, RegRex, 4 +db13, Debug, RegRex, 5 +db14, Debug, RegRex, 6 +db15, Debug, RegRex, 7 +dr0, Debug, 0, 0 +dr1, Debug, 0, 1 +dr2, Debug, 0, 2 +dr3, Debug, 0, 3 +dr4, Debug, 0, 4 +dr5, Debug, 0, 5 +dr6, Debug, 0, 6 +dr7, Debug, 0, 7 +dr8, Debug, RegRex, 0 +dr9, Debug, RegRex, 1 +dr10, Debug, RegRex, 2 +dr11, Debug, RegRex, 3 +dr12, Debug, RegRex, 4 +dr13, Debug, RegRex, 5 +dr14, Debug, RegRex, 6 +dr15, Debug, RegRex, 7 +// Test registers. +tr0, Test, 0, 0 +tr1, Test, 0, 1 +tr2, Test, 0, 2 +tr3, Test, 0, 3 +tr4, Test, 0, 4 +tr5, Test, 0, 5 +tr6, Test, 0, 6 +tr7, Test, 0, 7 +// MMX and simd registers. +mm0, RegMMX, 0, 0 +mm1, RegMMX, 0, 1 +mm2, RegMMX, 0, 2 +mm3, RegMMX, 0, 3 +mm4, RegMMX, 0, 4 +mm5, RegMMX, 0, 5 +mm6, RegMMX, 0, 6 +mm7, RegMMX, 0, 7 +xmm0, RegXMM, 0, 0 +xmm1, RegXMM, 0, 1 +xmm2, RegXMM, 0, 2 +xmm3, RegXMM, 0, 3 +xmm4, RegXMM, 0, 4 +xmm5, RegXMM, 0, 5 +xmm6, RegXMM, 0, 6 +xmm7, RegXMM, 0, 7 +xmm8, RegXMM, RegRex, 0 +xmm9, RegXMM, RegRex, 1 +xmm10, RegXMM, RegRex, 2 +xmm11, RegXMM, RegRex, 3 +xmm12, RegXMM, RegRex, 4 +xmm13, RegXMM, RegRex, 5 +xmm14, RegXMM, RegRex, 6 +xmm15, RegXMM, RegRex, 7 +// No type will make this register rejected for all purposes except +// for addressing. This saves creating one extra type for RIP. +rip, BaseIndex, 0, 0 +// fp regs. +st(0), FloatReg|FloatAcc, 0, 0 +st(1), FloatReg, 0, 1 +st(2), FloatReg, 0, 2 +st(3), FloatReg, 0, 3 +st(4), FloatReg, 0, 4 +st(5), FloatReg, 0, 5 +st(6), FloatReg, 0, 6 +st(7), FloatReg, 0, 7 diff --git a/contrib/binutils/opcodes/i386-tbl.h b/contrib/binutils/opcodes/i386-tbl.h new file mode 100644 index 0000000..fa843b3 --- /dev/null +++ b/contrib/binutils/opcodes/i386-tbl.h @@ -0,0 +1,4468 @@ +/* This file is automatically generated by i386-gen. Do not edit! */ + +/* i386 opcode table. */ + +const template i386_optab[] = +{ + { "mov", 2, 0xa0, None, Cpu64, + D|W|No_sSuf|No_xSuf, + { Disp64, + Acc } }, + { "mov", 2, 0xa0, None, CpuNo64, + D|W|No_sSuf|No_qSuf|No_xSuf, + { Disp16|Disp32, + Acc } }, + { "mov", 2, 0x88, None, 0, + D|W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "mov", 2, 0xb0, None, 0, + W|ShortForm|No_sSuf|No_qSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32 } }, + { "mov", 2, 0xc6, 0x0, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "mov", 2, 0xb0, None, Cpu64, + W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + { Imm64, + Reg64 } }, + { "mov", 2, 0x8c, None, 0, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { SReg2, + Reg16|Reg32|Reg64|RegMem } }, + { "mov", 2, 0x8c, None, 0, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { SReg2, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "mov", 2, 0x8c, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { SReg3, + Reg16|Reg32|Reg64|RegMem } }, + { "mov", 2, 0x8c, None, Cpu386, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { SReg3, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "mov", 2, 0x8e, None, 0, + Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64, + SReg2 } }, + { "mov", 2, 0x8e, None, 0, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + SReg2 } }, + { "mov", 2, 0x8e, None, Cpu386, + Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64, + SReg3 } }, + { "mov", 2, 0x8e, None, Cpu386, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + SReg3 } }, + { "mov", 2, 0xf20, None, Cpu386|CpuNo64, + D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + { Control, + Reg32|RegMem } }, + { "mov", 2, 0xf20, None, Cpu64, + D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Control, + Reg64|RegMem } }, + { "mov", 2, 0xf21, None, Cpu386|CpuNo64, + D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + { Debug, + Reg32|RegMem } }, + { "mov", 2, 0xf21, None, Cpu64, + D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Debug, + Reg64|RegMem } }, + { "mov", 2, 0xf24, None, Cpu386|CpuNo64, + D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + { Test, + Reg32|RegMem } }, + { "movabs", 2, 0xa0, None, Cpu64, + D|W|No_sSuf|No_xSuf, + { Disp64, + Acc } }, + { "movabs", 2, 0xb0, None, Cpu64, + W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + { Imm64, + Reg64 } }, + { "movsbl", 2, 0xfbe, None, Cpu386, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32 } }, + { "movsbw", 2, 0xfbe, None, Cpu386, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16 } }, + { "movswl", 2, 0xfbf, None, Cpu386, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32 } }, + { "movsbq", 2, 0xfbe, None, Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg64 } }, + { "movswq", 2, 0xfbf, None, Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg64 } }, + { "movslq", 2, 0x63, None, Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg64 } }, + { "movsx", 2, 0xfbe, None, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "movsx", 2, 0xfbf, None, Cpu386, + Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32|Reg64 } }, + { "movsx", 2, 0x63, None, Cpu64, + Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg64 } }, + { "movzb", 2, 0xfb6, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "movzbl", 2, 0xfb6, None, Cpu386, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32 } }, + { "movzbw", 2, 0xfb6, None, Cpu386, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16 } }, + { "movzwl", 2, 0xfb7, None, Cpu386, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32 } }, + { "movzbq", 2, 0xfb6, None, Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg64 } }, + { "movzwq", 2, 0xfb7, None, Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg64 } }, + { "movzx", 2, 0xfb6, None, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "movzx", 2, 0xfb7, None, Cpu386, + Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32|Reg64 } }, + { "push", 1, 0x50, None, CpuNo64, + ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64 } }, + { "push", 1, 0xff, 0x6, CpuNo64, + Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "push", 1, 0x6a, None, Cpu186|CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8S } }, + { "push", 1, 0x68, None, Cpu186|CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm16|Imm32 } }, + { "push", 1, 0x6, None, CpuNo64, + ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { SReg2 } }, + { "push", 1, 0xfa0, None, Cpu386|CpuNo64, + ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { SReg3 } }, + { "push", 1, 0x50, None, Cpu64, + ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Reg16|Reg64 } }, + { "push", 1, 0xff, 0x6, Cpu64, + Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "push", 1, 0x6a, None, Cpu64, + DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Imm8S } }, + { "push", 1, 0x68, None, Cpu64, + DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Imm16|Imm32S } }, + { "push", 1, 0xfa0, None, Cpu64, + ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { SReg3 } }, + { "pusha", 0, 0x60, None, Cpu186|CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "pop", 1, 0x58, None, CpuNo64, + ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64 } }, + { "pop", 1, 0x8f, 0x0, CpuNo64, + Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "pop", 1, 0x7, None, CpuNo64, + ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { SReg2 } }, + { "pop", 1, 0xfa1, None, Cpu386|CpuNo64, + ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { SReg3 } }, + { "pop", 1, 0x58, None, Cpu64, + ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Reg16|Reg64 } }, + { "pop", 1, 0x8f, 0x0, Cpu64, + Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "pop", 1, 0xfa1, None, Cpu64, + ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { SReg3 } }, + { "popa", 0, 0x61, None, Cpu186|CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "xchg", 2, 0x90, None, 0, + ShortForm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64, + Acc } }, + { "xchg", 2, 0x90, None, 0, + ShortForm|No_bSuf|No_sSuf|No_xSuf, + { Acc, + Reg16|Reg32|Reg64 } }, + { "xchg", 2, 0x86, None, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "xchg", 2, 0x86, None, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg8|Reg16|Reg32|Reg64 } }, + { "in", 2, 0xe4, None, 0, + W|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + Acc } }, + { "in", 2, 0xec, None, 0, + W|No_sSuf|No_qSuf|No_xSuf, + { InOutPortReg, + Acc } }, + { "in", 1, 0xe4, None, 0, + W|No_sSuf|No_qSuf|No_xSuf, + { Imm8 } }, + { "in", 1, 0xec, None, 0, + W|No_sSuf|No_qSuf|No_xSuf, + { InOutPortReg } }, + { "out", 2, 0xe6, None, 0, + W|No_sSuf|No_qSuf|No_xSuf, + { Acc, + Imm8 } }, + { "out", 2, 0xee, None, 0, + W|No_sSuf|No_qSuf|No_xSuf, + { Acc, + InOutPortReg } }, + { "out", 1, 0xe6, None, 0, + W|No_sSuf|No_qSuf|No_xSuf, + { Imm8 } }, + { "out", 1, 0xee, None, 0, + W|No_sSuf|No_qSuf|No_xSuf, + { InOutPortReg } }, + { "lea", 2, 0x8d, None, 0, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "lds", 2, 0xc5, None, CpuNo64, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "les", 2, 0xc4, None, CpuNo64, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "lfs", 2, 0xfb4, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "lgs", 2, 0xfb5, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "lss", 2, 0xfb2, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "clc", 0, 0xf8, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cld", 0, 0xfc, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cli", 0, 0xfa, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "clts", 0, 0xf06, None, Cpu286, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cmc", 0, 0xf5, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "lahf", 0, 0x9f, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "sahf", 0, 0x9e, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "pushf", 0, 0x9c, None, CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "pushf", 0, 0x9c, None, Cpu64, + DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { 0 } }, + { "popf", 0, 0x9d, None, CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "popf", 0, 0x9d, None, Cpu64, + DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { 0 } }, + { "stc", 0, 0xf9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "std", 0, 0xfd, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "sti", 0, 0xfb, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "add", 2, 0x0, None, 0, + D|W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "add", 2, 0x83, 0x0, 0, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "add", 2, 0x4, None, 0, + W|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Acc } }, + { "add", 2, 0x80, 0x0, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "inc", 1, 0x40, None, CpuNo64, + ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64 } }, + { "inc", 1, 0xfe, 0x0, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sub", 2, 0x28, None, 0, + D|W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sub", 2, 0x83, 0x5, 0, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sub", 2, 0x2c, None, 0, + W|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Acc } }, + { "sub", 2, 0x80, 0x5, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "dec", 1, 0x48, None, CpuNo64, + ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64 } }, + { "dec", 1, 0xfe, 0x1, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sbb", 2, 0x18, None, 0, + D|W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sbb", 2, 0x83, 0x3, 0, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sbb", 2, 0x1c, None, 0, + W|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Acc } }, + { "sbb", 2, 0x80, 0x3, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "cmp", 2, 0x38, None, 0, + D|W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "cmp", 2, 0x83, 0x7, 0, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "cmp", 2, 0x3c, None, 0, + W|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Acc } }, + { "cmp", 2, 0x80, 0x7, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "test", 2, 0x84, None, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "test", 2, 0x84, None, 0, + W|Modrm|No_sSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg8|Reg16|Reg32|Reg64 } }, + { "test", 2, 0xa8, None, 0, + W|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Acc } }, + { "test", 2, 0xf6, 0x0, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "and", 2, 0x20, None, 0, + D|W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "and", 2, 0x83, 0x4, 0, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "and", 2, 0x24, None, 0, + W|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Acc } }, + { "and", 2, 0x80, 0x4, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "or", 2, 0x8, None, 0, + D|W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "or", 2, 0x83, 0x1, 0, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "or", 2, 0xc, None, 0, + W|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Acc } }, + { "or", 2, 0x80, 0x1, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "xor", 2, 0x30, None, 0, + D|W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "xor", 2, 0x83, 0x6, 0, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "xor", 2, 0x34, None, 0, + W|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Acc } }, + { "xor", 2, 0x80, 0x6, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "clr", 1, 0x30, None, 0, + W|Modrm|No_sSuf|No_xSuf|RegKludge, + { Reg8|Reg16|Reg32|Reg64 } }, + { "adc", 2, 0x10, None, 0, + D|W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "adc", 2, 0x83, 0x2, 0, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "adc", 2, 0x14, None, 0, + W|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Acc } }, + { "adc", 2, 0x80, 0x2, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm8|Imm16|Imm32|Imm32S, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "neg", 1, 0xf6, 0x3, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "not", 1, 0xf6, 0x2, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "aaa", 0, 0x37, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "aas", 0, 0x3f, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "daa", 0, 0x27, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "das", 0, 0x2f, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "aad", 0, 0xd50a, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "aad", 1, 0xd5, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8 } }, + { "aam", 0, 0xd40a, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "aam", 1, 0xd4, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8 } }, + { "cbw", 0, 0x98, None, 0, + Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cdqe", 0, 0x98, None, Cpu64, + Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cwde", 0, 0x98, None, 0, + Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cwd", 0, 0x99, None, 0, + Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cdq", 0, 0x99, None, 0, + Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cqo", 0, 0x99, None, Cpu64, + Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cbtw", 0, 0x98, None, 0, + Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cltq", 0, 0x98, None, Cpu64, + Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cwtl", 0, 0x98, None, 0, + Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cwtd", 0, 0x99, None, 0, + Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cltd", 0, 0x99, None, 0, + Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cqto", 0, 0x99, None, Cpu64, + Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "mul", 1, 0xf6, 0x4, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "imul", 1, 0xf6, 0x5, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "imul", 2, 0xfaf, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "imul", 3, 0x6b, None, Cpu186, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "imul", 3, 0x69, None, Cpu186, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm16|Imm32|Imm32S, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "imul", 2, 0x6b, None, Cpu186, + Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, + { Imm8S, + Reg16|Reg32|Reg64 } }, + { "imul", 2, 0x69, None, Cpu186, + Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, + { Imm16|Imm32|Imm32S, + Reg16|Reg32|Reg64 } }, + { "div", 1, 0xf6, 0x6, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "div", 2, 0xf6, 0x6, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Acc } }, + { "idiv", 1, 0xf6, 0x7, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "idiv", 2, 0xf6, 0x7, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Acc } }, + { "rol", 2, 0xd0, 0x0, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm1, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rol", 2, 0xc0, 0x0, Cpu186, + W|Modrm|No_sSuf|No_xSuf, + { Imm8, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rol", 2, 0xd2, 0x0, 0, + W|Modrm|No_sSuf|No_xSuf, + { ShiftCount, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rol", 1, 0xd0, 0x0, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "ror", 2, 0xd0, 0x1, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm1, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "ror", 2, 0xc0, 0x1, Cpu186, + W|Modrm|No_sSuf|No_xSuf, + { Imm8, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "ror", 2, 0xd2, 0x1, 0, + W|Modrm|No_sSuf|No_xSuf, + { ShiftCount, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "ror", 1, 0xd0, 0x1, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rcl", 2, 0xd0, 0x2, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm1, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rcl", 2, 0xc0, 0x2, Cpu186, + W|Modrm|No_sSuf|No_xSuf, + { Imm8, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rcl", 2, 0xd2, 0x2, 0, + W|Modrm|No_sSuf|No_xSuf, + { ShiftCount, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rcl", 1, 0xd0, 0x2, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rcr", 2, 0xd0, 0x3, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm1, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rcr", 2, 0xc0, 0x3, Cpu186, + W|Modrm|No_sSuf|No_xSuf, + { Imm8, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rcr", 2, 0xd2, 0x3, 0, + W|Modrm|No_sSuf|No_xSuf, + { ShiftCount, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rcr", 1, 0xd0, 0x3, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sal", 2, 0xd0, 0x4, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm1, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sal", 2, 0xc0, 0x4, Cpu186, + W|Modrm|No_sSuf|No_xSuf, + { Imm8, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sal", 2, 0xd2, 0x4, 0, + W|Modrm|No_sSuf|No_xSuf, + { ShiftCount, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sal", 1, 0xd0, 0x4, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shl", 2, 0xd0, 0x4, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm1, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shl", 2, 0xc0, 0x4, Cpu186, + W|Modrm|No_sSuf|No_xSuf, + { Imm8, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shl", 2, 0xd2, 0x4, 0, + W|Modrm|No_sSuf|No_xSuf, + { ShiftCount, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shl", 1, 0xd0, 0x4, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shr", 2, 0xd0, 0x5, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm1, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shr", 2, 0xc0, 0x5, Cpu186, + W|Modrm|No_sSuf|No_xSuf, + { Imm8, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shr", 2, 0xd2, 0x5, 0, + W|Modrm|No_sSuf|No_xSuf, + { ShiftCount, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shr", 1, 0xd0, 0x5, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sar", 2, 0xd0, 0x7, 0, + W|Modrm|No_sSuf|No_xSuf, + { Imm1, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sar", 2, 0xc0, 0x7, Cpu186, + W|Modrm|No_sSuf|No_xSuf, + { Imm8, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sar", 2, 0xd2, 0x7, 0, + W|Modrm|No_sSuf|No_xSuf, + { ShiftCount, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sar", 1, 0xd0, 0x7, 0, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shld", 3, 0xfa4, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8, + Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shld", 3, 0xfa5, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { ShiftCount, + Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shld", 2, 0xfa5, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shrd", 3, 0xfac, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8, + Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shrd", 3, 0xfad, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { ShiftCount, + Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "shrd", 2, 0xfad, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "call", 1, 0xe8, None, CpuNo64, + JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp16|Disp32 } }, + { "call", 1, 0xe8, None, Cpu64, + JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Disp16|Disp32 } }, + { "call", 1, 0xff, 0x2, CpuNo64, + Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, + { "call", 1, 0xff, 0x2, Cpu64, + Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, + { "call", 2, 0x9a, None, CpuNo64, + JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm16, + Imm16|Imm32 } }, + { "call", 1, 0xff, 0x3, 0, + Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, + { "lcall", 2, 0x9a, None, CpuNo64, + JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm16, + Imm16|Imm32 } }, + { "lcall", 1, 0xff, 0x3, 0, + Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, + { "jmp", 1, 0xeb, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jmp", 1, 0xff, 0x4, CpuNo64, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, + { "jmp", 1, 0xff, 0x4, Cpu64, + Modrm|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, + { "jmp", 2, 0xea, None, CpuNo64, + JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm16, + Imm16|Imm32 } }, + { "jmp", 1, 0xff, 0x5, 0, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, + { "ljmp", 2, 0xea, None, CpuNo64, + JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm16, + Imm16|Imm32 } }, + { "ljmp", 1, 0xff, 0x5, 0, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, + { "ret", 0, 0xc3, None, CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "ret", 1, 0xc2, None, CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm16 } }, + { "ret", 0, 0xc3, None, Cpu64, + DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { 0 } }, + { "ret", 1, 0xc2, None, Cpu64, + DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Imm16 } }, + { "lret", 0, 0xcb, None, 0, + DefaultSize|No_bSuf|No_sSuf|No_xSuf, + { 0 } }, + { "lret", 1, 0xca, None, 0, + DefaultSize|No_bSuf|No_sSuf|No_xSuf, + { Imm16 } }, + { "enter", 2, 0xc8, None, Cpu186|CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm16, + Imm8 } }, + { "enter", 2, 0xc8, None, Cpu64, + DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Imm16, + Imm8 } }, + { "leave", 0, 0xc9, None, Cpu186|CpuNo64, + DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "leave", 0, 0xc9, None, Cpu64, + DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { 0 } }, + { "jo", 1, 0x70, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jno", 1, 0x71, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jb", 1, 0x72, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jc", 1, 0x72, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jnae", 1, 0x72, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jnb", 1, 0x73, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jnc", 1, 0x73, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jae", 1, 0x73, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "je", 1, 0x74, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jz", 1, 0x74, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jne", 1, 0x75, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jnz", 1, 0x75, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jbe", 1, 0x76, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jna", 1, 0x76, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jnbe", 1, 0x77, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "ja", 1, 0x77, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "js", 1, 0x78, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jns", 1, 0x79, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jp", 1, 0x7a, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jpe", 1, 0x7a, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jnp", 1, 0x7b, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jpo", 1, 0x7b, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jl", 1, 0x7c, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jnge", 1, 0x7c, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jnl", 1, 0x7d, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jge", 1, 0x7d, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jle", 1, 0x7e, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jng", 1, 0x7e, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jnle", 1, 0x7f, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jg", 1, 0x7f, None, 0, + Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jcxz", 1, 0xe3, None, CpuNo64, + JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jecxz", 1, 0xe3, None, CpuNo64, + JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jecxz", 1, 0x67e3, None, Cpu64, + JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "jrcxz", 1, 0xe3, None, Cpu64, + JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loop", 1, 0xe2, None, CpuNo64, + JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loop", 1, 0xe2, None, Cpu64, + JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loopz", 1, 0xe1, None, CpuNo64, + JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loopz", 1, 0xe1, None, Cpu64, + JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loope", 1, 0xe1, None, CpuNo64, + JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loope", 1, 0xe1, None, Cpu64, + JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loopnz", 1, 0xe0, None, CpuNo64, + JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loopnz", 1, 0xe0, None, Cpu64, + JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loopne", 1, 0xe0, None, CpuNo64, + JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "loopne", 1, 0xe0, None, Cpu64, + JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, + { "seto", 1, 0xf90, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setno", 1, 0xf91, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setb", 1, 0xf92, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setc", 1, 0xf92, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setnae", 1, 0xf92, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setnb", 1, 0xf93, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setnc", 1, 0xf93, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setae", 1, 0xf93, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sete", 1, 0xf94, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setz", 1, 0xf94, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setne", 1, 0xf95, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setnz", 1, 0xf95, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setbe", 1, 0xf96, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setna", 1, 0xf96, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setnbe", 1, 0xf97, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "seta", 1, 0xf97, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sets", 1, 0xf98, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setns", 1, 0xf99, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setp", 1, 0xf9a, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setpe", 1, 0xf9a, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setnp", 1, 0xf9b, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setpo", 1, 0xf9b, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setl", 1, 0xf9c, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setnge", 1, 0xf9c, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setnl", 1, 0xf9d, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setge", 1, 0xf9d, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setle", 1, 0xf9e, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setng", 1, 0xf9e, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setnle", 1, 0xf9f, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "setg", 1, 0xf9f, 0x0, Cpu386, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "cmps", 0, 0xa6, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "cmps", 2, 0xa6, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "scmp", 0, 0xa6, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "scmp", 2, 0xa6, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "ins", 0, 0x6c, None, Cpu186, + W|No_sSuf|No_qSuf|No_xSuf|IsString, + { 0 } }, + { "ins", 2, 0x6c, None, Cpu186, + W|No_sSuf|No_qSuf|No_xSuf|IsString, + { InOutPortReg, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "outs", 0, 0x6e, None, Cpu186, + W|No_sSuf|No_qSuf|No_xSuf|IsString, + { 0 } }, + { "outs", 2, 0x6e, None, Cpu186, + W|No_sSuf|No_qSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + InOutPortReg } }, + { "lods", 0, 0xac, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "lods", 1, 0xac, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "lods", 2, 0xac, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Acc } }, + { "slod", 0, 0xac, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "slod", 1, 0xac, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "slod", 2, 0xac, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Acc } }, + { "movs", 0, 0xa4, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "movs", 2, 0xa4, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "smov", 0, 0xa4, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "smov", 2, 0xa4, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "scas", 0, 0xae, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "scas", 1, 0xae, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "scas", 2, 0xae, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, + Acc } }, + { "ssca", 0, 0xae, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "ssca", 1, 0xae, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "ssca", 2, 0xae, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, + Acc } }, + { "stos", 0, 0xaa, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "stos", 1, 0xaa, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "stos", 2, 0xaa, None, 0, + W|No_sSuf|No_xSuf|IsString, + { Acc, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "ssto", 0, 0xaa, None, 0, + W|No_sSuf|No_xSuf|IsString, + { 0 } }, + { "ssto", 1, 0xaa, None, 0, + W|No_sSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "ssto", 2, 0xaa, None, 0, + W|No_sSuf|No_xSuf|IsString, + { Acc, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "xlat", 0, 0xd7, None, 0, + No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + { 0 } }, + { "xlat", 1, 0xd7, None, 0, + No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "bsf", 2, 0xfbc, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "bsr", 2, 0xfbd, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "bt", 2, 0xfa3, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "bt", 2, 0xfba, 0x4, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "btc", 2, 0xfbb, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "btc", 2, 0xfba, 0x7, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "btr", 2, 0xfb3, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "btr", 2, 0xfba, 0x6, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "bts", 2, 0xfab, None, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "bts", 2, 0xfba, 0x5, Cpu386, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Imm8, + Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "int", 1, 0xcd, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8 } }, + { "int3", 0, 0xcc, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "into", 0, 0xce, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "iret", 0, 0xcf, None, 0, + DefaultSize|No_bSuf|No_sSuf|No_xSuf, + { 0 } }, + { "rsm", 0, 0xfaa, None, Cpu386, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "bound", 2, 0x62, None, Cpu186|CpuNo64, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|Reg64, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "hlt", 0, 0xf4, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "nop", 1, 0xf1f, 0x0, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "nop", 0, 0x90, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "arpl", 2, 0x63, None, Cpu286|CpuNo64, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16, + Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "lar", 2, 0xf02, None, Cpu286, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "lgdt", 1, 0xf01, 0x2, Cpu286|CpuNo64, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "lgdt", 1, 0xf01, 0x2, Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "lidt", 1, 0xf01, 0x3, Cpu286|CpuNo64, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "lidt", 1, 0xf01, 0x3, Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "lldt", 1, 0xf00, 0x2, Cpu286, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "lmsw", 1, 0xf01, 0x6, Cpu286, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "lsl", 2, 0xf03, None, Cpu286, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "ltr", 1, 0xf00, 0x3, Cpu286, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sgdt", 1, 0xf01, 0x0, Cpu286|CpuNo64, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sgdt", 1, 0xf01, 0x0, Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sidt", 1, 0xf01, 0x1, Cpu286|CpuNo64, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sidt", 1, 0xf01, 0x1, Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sldt", 1, 0xf00, 0x0, Cpu286, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64 } }, + { "sldt", 1, 0xf00, 0x0, Cpu286, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "smsw", 1, 0xf01, 0x4, Cpu286, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64 } }, + { "smsw", 1, 0xf01, 0x4, Cpu286, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "str", 1, 0xf00, 0x1, Cpu286, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64 } }, + { "str", 1, 0xf00, 0x1, Cpu286, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "verr", 1, 0xf00, 0x4, Cpu286, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "verw", 1, 0xf00, 0x5, Cpu286, + Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fld", 1, 0xd9c0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fld", 1, 0xd9, 0x0, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fld", 1, 0xd9c0, None, 0, + ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg } }, + { "fld", 1, 0xdb, 0x5, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fild", 1, 0xdf, 0x0, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fild", 1, 0xdf, 0x5, 0, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fildll", 1, 0xdf, 0x5, 0, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fldt", 1, 0xdb, 0x5, 0, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fbld", 1, 0xdf, 0x4, 0, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fst", 1, 0xddd0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fst", 1, 0xd9, 0x2, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fst", 1, 0xddd0, None, 0, + ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg } }, + { "fist", 1, 0xdf, 0x2, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fstp", 1, 0xddd8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fstp", 1, 0xd9, 0x3, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fstp", 1, 0xddd8, None, 0, + ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg } }, + { "fstp", 1, 0xdb, 0x7, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fistp", 1, 0xdf, 0x3, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fistp", 1, 0xdf, 0x7, 0, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fistpll", 1, 0xdf, 0x7, 0, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fstpt", 1, 0xdb, 0x7, 0, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fbstp", 1, 0xdf, 0x6, 0, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fxch", 1, 0xd9c8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fxch", 0, 0xd9c9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fcom", 1, 0xd8d0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fcom", 0, 0xd8d1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fcom", 1, 0xd8, 0x2, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fcom", 1, 0xd8d0, None, 0, + ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg } }, + { "ficom", 1, 0xde, 0x2, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fcomp", 1, 0xd8d8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fcomp", 0, 0xd8d9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fcomp", 1, 0xd8, 0x3, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fcomp", 1, 0xd8d8, None, 0, + ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg } }, + { "ficomp", 1, 0xde, 0x3, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fcompp", 0, 0xded9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fucom", 1, 0xdde0, None, Cpu286, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fucom", 0, 0xdde1, None, Cpu286, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fucomp", 1, 0xdde8, None, Cpu286, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fucomp", 0, 0xdde9, None, Cpu286, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fucompp", 0, 0xdae9, None, Cpu286, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "ftst", 0, 0xd9e4, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fxam", 0, 0xd9e5, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fld1", 0, 0xd9e8, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fldl2t", 0, 0xd9e9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fldl2e", 0, 0xd9ea, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fldpi", 0, 0xd9eb, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fldlg2", 0, 0xd9ec, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fldln2", 0, 0xd9ed, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fldz", 0, 0xd9ee, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fadd", 2, 0xd8c0, None, 0, + ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fadd", 1, 0xd8c0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, +#if SYSV386_COMPAT + { "fadd", 0, 0xdec1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { 0 } }, +#endif + { "fadd", 1, 0xd8, 0x0, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fiadd", 1, 0xde, 0x0, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "faddp", 2, 0xdec0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatAcc, + FloatReg } }, + { "faddp", 1, 0xdec0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "faddp", 0, 0xdec1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "faddp", 2, 0xdec0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg, + FloatAcc } }, + { "fsub", 1, 0xd8e0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, +#if SYSV386_COMPAT + { "fsub", 2, 0xd8e0, None, 0, + ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fsub", 0, 0xdee1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { 0 } }, +#else + { "fsub", 2, 0xd8e0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, + { FloatReg, + FloatAcc } }, +#endif + { "fsub", 1, 0xd8, 0x4, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fisub", 1, 0xde, 0x4, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, +#if SYSV386_COMPAT + { "fsubp", 2, 0xdee0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatAcc, + FloatReg } }, + { "fsubp", 1, 0xdee0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fsubp", 0, 0xdee1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, +#if OLDGCC_COMPAT + { "fsubp", 2, 0xdee0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg, + FloatAcc } }, +#endif +#else + { "fsubp", 2, 0xdee8, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + { FloatAcc, + FloatReg } }, + { "fsubp", 1, 0xdee8, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + { FloatReg } }, + { "fsubp", 0, 0xdee9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, + { 0 } }, +#endif + { "fsubr", 1, 0xd8e8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, +#if SYSV386_COMPAT + { "fsubr", 2, 0xd8e8, None, 0, + ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fsubr", 0, 0xdee9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { 0 } }, +#else + { "fsubr", 2, 0xd8e8, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, + { FloatReg, + FloatAcc } }, +#endif + { "fsubr", 1, 0xd8, 0x5, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fisubr", 1, 0xde, 0x5, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, +#if SYSV386_COMPAT + { "fsubrp", 2, 0xdee8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatAcc, + FloatReg } }, + { "fsubrp", 1, 0xdee8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fsubrp", 0, 0xdee9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, +#if OLDGCC_COMPAT + { "fsubrp", 2, 0xdee8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg, + FloatAcc } }, +#endif +#else + { "fsubrp", 2, 0xdee0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + { FloatAcc, + FloatReg } }, + { "fsubrp", 1, 0xdee0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + { FloatReg } }, + { "fsubrp", 0, 0xdee1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, + { 0 } }, +#endif + { "fmul", 2, 0xd8c8, None, 0, + ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fmul", 1, 0xd8c8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, +#if SYSV386_COMPAT + { "fmul", 0, 0xdec9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { 0 } }, +#endif + { "fmul", 1, 0xd8, 0x1, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fimul", 1, 0xde, 0x1, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fmulp", 2, 0xdec8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatAcc, + FloatReg } }, + { "fmulp", 1, 0xdec8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fmulp", 0, 0xdec9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fmulp", 2, 0xdec8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg, + FloatAcc } }, + { "fdiv", 1, 0xd8f0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, +#if SYSV386_COMPAT + { "fdiv", 2, 0xd8f0, None, 0, + ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fdiv", 0, 0xdef1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { 0 } }, +#else + { "fdiv", 2, 0xd8f0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, + { FloatReg, + FloatAcc } }, +#endif + { "fdiv", 1, 0xd8, 0x6, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fidiv", 1, 0xde, 0x6, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, +#if SYSV386_COMPAT + { "fdivp", 2, 0xdef0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatAcc, + FloatReg } }, + { "fdivp", 1, 0xdef0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fdivp", 0, 0xdef1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, +#if OLDGCC_COMPAT + { "fdivp", 2, 0xdef0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg, + FloatAcc } }, +#endif +#else + { "fdivp", 2, 0xdef8, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + { FloatAcc, + FloatReg } }, + { "fdivp", 1, 0xdef8, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + { FloatReg } }, + { "fdivp", 0, 0xdef9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, + { 0 } }, +#endif + { "fdivr", 1, 0xd8f8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, +#if SYSV386_COMPAT + { "fdivr", 2, 0xd8f8, None, 0, + ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fdivr", 0, 0xdef9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { 0 } }, +#else + { "fdivr", 2, 0xd8f8, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, + { FloatReg, + FloatAcc } }, +#endif + { "fdivr", 1, 0xd8, 0x7, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fidivr", 1, 0xde, 0x7, 0, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, +#if SYSV386_COMPAT + { "fdivrp", 2, 0xdef8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatAcc, + FloatReg } }, + { "fdivrp", 1, 0xdef8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fdivrp", 0, 0xdef9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, +#if OLDGCC_COMPAT + { "fdivrp", 2, 0xdef8, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + { FloatReg, + FloatAcc } }, +#endif +#else + { "fdivrp", 2, 0xdef0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + { FloatAcc, + FloatReg } }, + { "fdivrp", 1, 0xdef0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + { FloatReg } }, + { "fdivrp", 0, 0xdef1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, + { 0 } }, +#endif + { "f2xm1", 0, 0xd9f0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fyl2x", 0, 0xd9f1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fptan", 0, 0xd9f2, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fpatan", 0, 0xd9f3, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fxtract", 0, 0xd9f4, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fprem1", 0, 0xd9f5, None, Cpu286, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fdecstp", 0, 0xd9f6, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fincstp", 0, 0xd9f7, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fprem", 0, 0xd9f8, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fyl2xp1", 0, 0xd9f9, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fsqrt", 0, 0xd9fa, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fsincos", 0, 0xd9fb, None, Cpu286, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "frndint", 0, 0xd9fc, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fscale", 0, 0xd9fd, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fsin", 0, 0xd9fe, None, Cpu286, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fcos", 0, 0xd9ff, None, Cpu286, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fchs", 0, 0xd9e0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fabs", 0, 0xd9e1, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fninit", 0, 0xdbe3, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "finit", 0, 0xdbe3, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + { 0 } }, + { "fldcw", 1, 0xd9, 0x5, 0, + Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fnstcw", 1, 0xd9, 0x7, 0, + Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fstcw", 1, 0xd9, 0x7, 0, + Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fnstsw", 1, 0xdfe0, None, 0, + IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Acc } }, + { "fnstsw", 1, 0xdd, 0x7, 0, + Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fnstsw", 0, 0xdfe0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fstsw", 1, 0xdfe0, None, 0, + IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + { Acc } }, + { "fstsw", 1, 0xdd, 0x7, 0, + Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fstsw", 0, 0xdfe0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + { 0 } }, + { "fnclex", 0, 0xdbe2, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fclex", 0, 0xdbe2, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + { 0 } }, + { "fnstenv", 1, 0xd9, 0x6, 0, + Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fstenv", 1, 0xd9, 0x6, 0, + Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fldenv", 1, 0xd9, 0x4, 0, + Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fnsave", 1, 0xdd, 0x6, 0, + Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fsave", 1, 0xdd, 0x6, 0, + Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "frstor", 1, 0xdd, 0x4, 0, + Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "ffree", 1, 0xddc0, None, 0, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "ffreep", 1, 0xdfc0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fnop", 0, 0xd9d0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fwait", 0, 0x9b, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "addr16", 0, 0x67, None, Cpu386|CpuNo64, + Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "addr32", 0, 0x67, None, Cpu386, + Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "aword", 0, 0x67, None, Cpu386|CpuNo64, + Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "adword", 0, 0x67, None, Cpu386, + Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "data16", 0, 0x66, None, Cpu386, + Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "data32", 0, 0x66, None, Cpu386|CpuNo64, + Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "word", 0, 0x66, None, Cpu386, + Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "dword", 0, 0x66, None, Cpu386|CpuNo64, + Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "lock", 0, 0xf0, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "wait", 0, 0x9b, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "cs", 0, 0x2e, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "ds", 0, 0x3e, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "es", 0, 0x26, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "fs", 0, 0x64, None, Cpu386, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "gs", 0, 0x65, None, Cpu386, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "ss", 0, 0x36, None, CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rep", 0, 0xf3, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "repe", 0, 0xf3, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "repz", 0, 0xf3, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "repne", 0, 0xf2, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "repnz", 0, 0xf2, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "ht", 0, 0x3e, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "hnt", 0, 0x2e, None, 0, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex", 0, 0x40, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rexz", 0, 0x41, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rexy", 0, 0x42, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rexyz", 0, 0x43, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rexx", 0, 0x44, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rexxz", 0, 0x45, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rexxy", 0, 0x46, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rexxyz", 0, 0x47, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex64", 0, 0x48, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex64z", 0, 0x49, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex64y", 0, 0x4a, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex64yz", 0, 0x4b, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex64x", 0, 0x4c, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex64xz", 0, 0x4d, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex64xy", 0, 0x4e, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex64xyz", 0, 0x4f, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.b", 0, 0x41, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.x", 0, 0x42, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.xb", 0, 0x43, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.r", 0, 0x44, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.rb", 0, 0x45, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.rx", 0, 0x46, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.rxb", 0, 0x47, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.w", 0, 0x48, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.wb", 0, 0x49, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.wx", 0, 0x4a, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.wxb", 0, 0x4b, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.wr", 0, 0x4c, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.wrb", 0, 0x4d, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.wrx", 0, 0x4e, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "rex.wrxb", 0, 0x4f, None, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + { 0 } }, + { "bswap", 1, 0xfc8, None, Cpu486, + ShortForm|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { Reg32|Reg64 } }, + { "xadd", 2, 0xfc0, None, Cpu486, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "cmpxchg", 2, 0xfb0, None, Cpu486, + W|Modrm|No_sSuf|No_xSuf, + { Reg8|Reg16|Reg32|Reg64, + Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "invd", 0, 0xf08, None, Cpu486, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "wbinvd", 0, 0xf09, None, Cpu486, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "invlpg", 1, 0xf01, 0x7, Cpu486, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "cpuid", 0, 0xfa2, None, Cpu486, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "wrmsr", 0, 0xf30, None, Cpu586, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "rdtsc", 0, 0xf31, None, Cpu586, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "rdmsr", 0, 0xf32, None, Cpu586, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cmpxchg8b", 1, 0xfc7, 0x1, Cpu586, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "sysenter", 0, 0xf34, None, Cpu686, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "sysexit", 0, 0xf35, None, Cpu686, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fxsave", 1, 0xfae, 0x0, Cpu686, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fxrstor", 1, 0xfae, 0x1, Cpu686, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "rdpmc", 0, 0xf33, None, Cpu686, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "ud2", 0, 0xf0b, None, Cpu686, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "ud2a", 0, 0xf0b, None, Cpu686, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "ud2b", 0, 0xfb9, None, Cpu686, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "cmovo", 2, 0xf40, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovno", 2, 0xf41, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovb", 2, 0xf42, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovc", 2, 0xf42, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovnae", 2, 0xf42, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovae", 2, 0xf43, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovnc", 2, 0xf43, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovnb", 2, 0xf43, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmove", 2, 0xf44, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovz", 2, 0xf44, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovne", 2, 0xf45, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovnz", 2, 0xf45, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovbe", 2, 0xf46, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovna", 2, 0xf46, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmova", 2, 0xf47, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovnbe", 2, 0xf47, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovs", 2, 0xf48, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovns", 2, 0xf49, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovp", 2, 0xf4a, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovnp", 2, 0xf4b, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovl", 2, 0xf4c, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovnge", 2, 0xf4c, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovge", 2, 0xf4d, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovnl", 2, 0xf4d, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovle", 2, 0xf4e, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovng", 2, 0xf4e, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovg", 2, 0xf4f, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "cmovnle", 2, 0xf4f, None, Cpu686, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "fcmovb", 2, 0xdac0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmovnae", 2, 0xdac0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmove", 2, 0xdac8, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmovbe", 2, 0xdad0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmovna", 2, 0xdad0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmovu", 2, 0xdad8, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmovae", 2, 0xdbc0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmovnb", 2, 0xdbc0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmovne", 2, 0xdbc8, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmova", 2, 0xdbd0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmovnbe", 2, 0xdbd0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcmovnu", 2, 0xdbd8, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcomi", 2, 0xdbf0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcomi", 0, 0xdbf1, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fcomi", 1, 0xdbf0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fucomi", 2, 0xdbe8, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fucomi", 0, 0xdbe9, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fucomi", 1, 0xdbe8, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fcomip", 2, 0xdff0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcompi", 2, 0xdff0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fcompi", 0, 0xdff1, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fcompi", 1, 0xdff0, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "fucomip", 2, 0xdfe8, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fucompi", 2, 0xdfe8, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg, + FloatAcc } }, + { "fucompi", 0, 0xdfe9, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "fucompi", 1, 0xdfe8, None, Cpu686, + ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { FloatReg } }, + { "movnti", 2, 0xfc3, None, CpuP4, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "clflush", 1, 0xfae, 0x7, CpuP4, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "lfence", 0, 0xfae, 0xe8, CpuP4, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "mfence", 0, 0xfae, 0xf0, CpuP4, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "pause", 0, 0xf390, None, CpuP4, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "emms", 0, 0xf77, None, CpuMMX, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "movd", 2, 0xf6e, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegMMX } }, + { "movd", 2, 0xf7e, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegMMX, + Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movd", 2, 0x660f6e, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "movd", 2, 0x660f7e, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movq", 2, 0xf6f, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "movq", 2, 0xf7f, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { RegMMX, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } }, + { "movq", 2, 0xf30f7e, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movq", 2, 0x660fd6, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, + { "movq", 2, 0xf6e, None, Cpu64, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegMMX } }, + { "movq", 2, 0xf7e, None, Cpu64, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegMMX, + Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movq", 2, 0x660f6e, None, Cpu64, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "movq", 2, 0x660f7e, None, Cpu64, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movq", 2, 0xa0, None, Cpu64, + D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Disp64, + Acc } }, + { "movq", 2, 0x88, None, Cpu64, + D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg64, + Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movq", 2, 0xc6, 0x0, Cpu64, + W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm32S, + Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movq", 2, 0xb0, None, Cpu64, + W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm64, + Reg64 } }, + { "movq", 2, 0x8c, None, Cpu64, + Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { SReg2|SReg3, + Reg64|RegMem } }, + { "movq", 2, 0x8e, None, Cpu64, + Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg64, + SReg2|SReg3 } }, + { "movq", 2, 0xf20, None, Cpu64, + D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { Control, + Reg64|RegMem } }, + { "movq", 2, 0xf21, None, Cpu64, + D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { Debug, + Reg64|RegMem } }, + { "packssdw", 2, 0xf6b, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "packssdw", 2, 0x660f6b, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "packsswb", 2, 0xf63, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "packsswb", 2, 0x660f63, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "packuswb", 2, 0xf67, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "packuswb", 2, 0x660f67, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "paddb", 2, 0xffc, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "paddb", 2, 0x660ffc, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "paddw", 2, 0xffd, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "paddw", 2, 0x660ffd, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "paddd", 2, 0xffe, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "paddd", 2, 0x660ffe, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "paddq", 2, 0xfd4, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "paddq", 2, 0x660fd4, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "paddsb", 2, 0xfec, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "paddsb", 2, 0x660fec, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "paddsw", 2, 0xfed, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "paddsw", 2, 0x660fed, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "paddusb", 2, 0xfdc, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "paddusb", 2, 0x660fdc, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "paddusw", 2, 0xfdd, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "paddusw", 2, 0x660fdd, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pand", 2, 0xfdb, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pand", 2, 0x660fdb, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pandn", 2, 0xfdf, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pandn", 2, 0x660fdf, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpeqb", 2, 0xf74, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pcmpeqb", 2, 0x660f74, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpeqw", 2, 0xf75, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pcmpeqw", 2, 0x660f75, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpeqd", 2, 0xf76, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pcmpeqd", 2, 0x660f76, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpgtb", 2, 0xf64, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pcmpgtb", 2, 0x660f64, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpgtw", 2, 0xf65, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pcmpgtw", 2, 0x660f65, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpgtd", 2, 0xf66, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pcmpgtd", 2, 0x660f66, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmaddwd", 2, 0xff5, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmaddwd", 2, 0x660ff5, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmulhw", 2, 0xfe5, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmulhw", 2, 0x660fe5, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmullw", 2, 0xfd5, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmullw", 2, 0x660fd5, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "por", 2, 0xfeb, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "por", 2, 0x660feb, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psllw", 2, 0xff1, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psllw", 2, 0x660ff1, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psllw", 2, 0xf71, 0x6, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegMMX } }, + { "psllw", 2, 0x660f71, 0x6, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "pslld", 2, 0xff2, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pslld", 2, 0x660ff2, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pslld", 2, 0xf72, 0x6, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegMMX } }, + { "pslld", 2, 0x660f72, 0x6, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "psllq", 2, 0xff3, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psllq", 2, 0x660ff3, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psllq", 2, 0xf73, 0x6, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegMMX } }, + { "psllq", 2, 0x660f73, 0x6, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "psraw", 2, 0xfe1, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psraw", 2, 0x660fe1, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psraw", 2, 0xf71, 0x4, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegMMX } }, + { "psraw", 2, 0x660f71, 0x4, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "psrad", 2, 0xfe2, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psrad", 2, 0x660fe2, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psrad", 2, 0xf72, 0x4, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegMMX } }, + { "psrad", 2, 0x660f72, 0x4, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "psrlw", 2, 0xfd1, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psrlw", 2, 0x660fd1, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psrlw", 2, 0xf71, 0x2, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegMMX } }, + { "psrlw", 2, 0x660f71, 0x2, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "psrld", 2, 0xfd2, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psrld", 2, 0x660fd2, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psrld", 2, 0xf72, 0x2, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegMMX } }, + { "psrld", 2, 0x660f72, 0x2, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "psrlq", 2, 0xfd3, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psrlq", 2, 0x660fd3, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psrlq", 2, 0xf73, 0x2, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegMMX } }, + { "psrlq", 2, 0x660f73, 0x2, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "psubb", 2, 0xff8, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psubb", 2, 0x660ff8, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psubw", 2, 0xff9, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psubw", 2, 0x660ff9, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psubd", 2, 0xffa, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psubd", 2, 0x660ffa, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psubq", 2, 0xffb, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psubq", 2, 0x660ffb, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psubsb", 2, 0xfe8, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psubsb", 2, 0x660fe8, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psubsw", 2, 0xfe9, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psubsw", 2, 0x660fe9, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psubusb", 2, 0xfd8, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psubusb", 2, 0x660fd8, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psubusw", 2, 0xfd9, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psubusw", 2, 0x660fd9, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "punpckhbw", 2, 0xf68, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "punpckhbw", 2, 0x660f68, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "punpckhwd", 2, 0xf69, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "punpckhwd", 2, 0x660f69, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "punpckhdq", 2, 0xf6a, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "punpckhdq", 2, 0x660f6a, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "punpcklbw", 2, 0xf60, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "punpcklbw", 2, 0x660f60, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "punpcklwd", 2, 0xf61, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "punpcklwd", 2, 0x660f61, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "punpckldq", 2, 0xf62, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "punpckldq", 2, 0x660f62, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pxor", 2, 0xfef, None, CpuMMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pxor", 2, 0x660fef, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "addps", 2, 0xf58, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "addss", 2, 0xf30f58, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "andnps", 2, 0xf55, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "andps", 2, 0xf54, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpeqps", 2, 0xfc2, 0x0, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpeqss", 2, 0xf30fc2, 0x0, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpleps", 2, 0xfc2, 0x2, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpless", 2, 0xf30fc2, 0x2, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpltps", 2, 0xfc2, 0x1, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpltss", 2, 0xf30fc2, 0x1, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpneqps", 2, 0xfc2, 0x4, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpneqss", 2, 0xf30fc2, 0x4, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpnleps", 2, 0xfc2, 0x6, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpnless", 2, 0xf30fc2, 0x6, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpnltps", 2, 0xfc2, 0x5, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpnltss", 2, 0xf30fc2, 0x5, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpordps", 2, 0xfc2, 0x7, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpordss", 2, 0xf30fc2, 0x7, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpunordps", 2, 0xfc2, 0x3, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpunordss", 2, 0xf30fc2, 0x3, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpps", 3, 0xfc2, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpss", 3, 0xf30fc2, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "comiss", 2, 0xf2f, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtpi2ps", 2, 0xf2a, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegXMM } }, + { "cvtps2pi", 2, 0xf2d, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegMMX } }, + { "cvtsi2ss", 2, 0xf30f2a, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "cvtss2si", 2, 0xf30f2d, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + Reg32|Reg64 } }, + { "cvttps2pi", 2, 0xf2c, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegMMX } }, + { "cvttss2si", 2, 0xf30f2c, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + Reg32|Reg64 } }, + { "divps", 2, 0xf5e, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "divss", 2, 0xf30f5e, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "ldmxcsr", 1, 0xfae, 0x2, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "maskmovq", 2, 0xff7, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegMMX, + RegMMX } }, + { "maxps", 2, 0xf5f, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "maxss", 2, 0xf30f5f, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "minps", 2, 0xf5d, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "minss", 2, 0xf30f5d, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movaps", 2, 0xf28, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movaps", 2, 0xf29, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, + { "movhlps", 2, 0xf12, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + RegXMM } }, + { "movhps", 2, 0xf16, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "movhps", 2, 0xf17, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movlhps", 2, 0xf16, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + RegXMM } }, + { "movlps", 2, 0xf12, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "movlps", 2, 0xf13, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movmskps", 2, 0xf50, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { RegXMM, + Reg32|Reg64 } }, + { "movntps", 2, 0xf2b, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movntq", 2, 0xfe7, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegMMX, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movntdq", 2, 0x660fe7, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movss", 2, 0xf30f10, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movss", 2, 0xf30f11, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, + { "movups", 2, 0xf10, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movups", 2, 0xf11, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, + { "mulps", 2, 0xf59, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "mulss", 2, 0xf30f59, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "orps", 2, 0xf56, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pavgb", 2, 0xfe0, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pavgb", 2, 0x660fe0, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pavgw", 2, 0xfe3, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pavgw", 2, 0x660fe3, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pextrw", 3, 0xfc5, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { Imm8, + RegMMX, + Reg32|Reg64 } }, + { "pextrw", 3, 0x660fc5, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { Imm8, + RegXMM, + Reg32|Reg64 } }, + { "pextrw", 3, 0x660f3a15, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM, + Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "pinsrw", 3, 0xfc4, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { Imm8, + Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegMMX } }, + { "pinsrw", 3, 0x660fc4, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { Imm8, + Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "pmaxsw", 2, 0xfee, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmaxsw", 2, 0x660fee, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmaxub", 2, 0xfde, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmaxub", 2, 0x660fde, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pminsw", 2, 0xfea, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pminsw", 2, 0x660fea, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pminub", 2, 0xfda, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pminub", 2, 0x660fda, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovmskb", 2, 0xfd7, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { RegMMX, + Reg32|Reg64 } }, + { "pmovmskb", 2, 0x660fd7, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { RegXMM, + Reg32|Reg64 } }, + { "pmulhuw", 2, 0xfe4, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmulhuw", 2, 0x660fe4, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "prefetchnta", 1, 0xf18, 0x0, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "prefetcht0", 1, 0xf18, 0x1, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "prefetcht1", 1, 0xf18, 0x2, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "prefetcht2", 1, 0xf18, 0x3, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "psadbw", 2, 0xff6, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psadbw", 2, 0x660ff6, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pshufw", 3, 0xf70, None, CpuMMX2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "rcpps", 2, 0xf53, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "rcpss", 2, 0xf30f53, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "rsqrtps", 2, 0xf52, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "rsqrtss", 2, 0xf30f52, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "sfence", 0, 0xfae, 0xf8, CpuMMX2, + IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "shufps", 3, 0xfc6, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "sqrtps", 2, 0xf51, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "sqrtss", 2, 0xf30f51, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "stmxcsr", 1, 0xfae, 0x3, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "subps", 2, 0xf5c, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "subss", 2, 0xf30f5c, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "ucomiss", 2, 0xf2e, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "unpckhps", 2, 0xf15, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "unpcklps", 2, 0xf14, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "xorps", 2, 0xf57, None, CpuSSE, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "addpd", 2, 0x660f58, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "addsd", 2, 0xf20f58, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "andnpd", 2, 0x660f55, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "andpd", 2, 0x660f54, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpeqpd", 2, 0x660fc2, 0x0, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpeqsd", 2, 0xf20fc2, 0x0, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmplepd", 2, 0x660fc2, 0x2, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmplesd", 2, 0xf20fc2, 0x2, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpltpd", 2, 0x660fc2, 0x1, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpltsd", 2, 0xf20fc2, 0x1, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpneqpd", 2, 0x660fc2, 0x4, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpneqsd", 2, 0xf20fc2, 0x4, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpnlepd", 2, 0x660fc2, 0x6, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpnlesd", 2, 0xf20fc2, 0x6, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpnltpd", 2, 0x660fc2, 0x5, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpnltsd", 2, 0xf20fc2, 0x5, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpordpd", 2, 0x660fc2, 0x7, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpordsd", 2, 0xf20fc2, 0x7, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpunordpd", 2, 0x660fc2, 0x3, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpunordsd", 2, 0xf20fc2, 0x3, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmppd", 3, 0x660fc2, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpsd", 0, 0xa7, None, 0, + Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + { 0 } }, + { "cmpsd", 2, 0xa7, None, 0, + Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "cmpsd", 3, 0xf20fc2, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "comisd", 2, 0x660f2f, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtpi2pd", 2, 0x660f2a, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegXMM } }, + { "cvtsi2sd", 2, 0xf20f2a, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "divpd", 2, 0x660f5e, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "divsd", 2, 0xf20f5e, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "maxpd", 2, 0x660f5f, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "maxsd", 2, 0xf20f5f, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "minpd", 2, 0x660f5d, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "minsd", 2, 0xf20f5d, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movapd", 2, 0x660f28, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movapd", 2, 0x660f29, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, + { "movhpd", 2, 0x660f16, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "movhpd", 2, 0x660f17, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movlpd", 2, 0x660f12, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "movlpd", 2, 0x660f13, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movmskpd", 2, 0x660f50, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { RegXMM, + Reg32|Reg64 } }, + { "movntpd", 2, 0x660f2b, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movsd", 0, 0xa5, None, 0, + Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + { 0 } }, + { "movsd", 2, 0xa5, None, 0, + Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, + { "movsd", 2, 0xf20f10, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movsd", 2, 0xf20f11, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, + { "movupd", 2, 0x660f10, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movupd", 2, 0x660f11, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, + { "mulpd", 2, 0x660f59, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "mulsd", 2, 0xf20f59, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "orpd", 2, 0x660f56, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "shufpd", 3, 0x660fc6, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "sqrtpd", 2, 0x660f51, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "sqrtsd", 2, 0xf20f51, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "subpd", 2, 0x660f5c, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "subsd", 2, 0xf20f5c, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "ucomisd", 2, 0x660f2e, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "unpckhpd", 2, 0x660f15, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "unpcklpd", 2, 0x660f14, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "xorpd", 2, 0x660f57, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtdq2pd", 2, 0xf30fe6, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtpd2dq", 2, 0xf20fe6, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtdq2ps", 2, 0xf5b, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtpd2pi", 2, 0x660f2d, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegMMX } }, + { "cvtpd2ps", 2, 0x660f5a, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtps2pd", 2, 0xf5a, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtps2dq", 2, 0x660f5b, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtsd2si", 2, 0xf20f2d, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + Reg32|Reg64 } }, + { "cvtsd2ss", 2, 0xf20f5a, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvtss2sd", 2, 0xf30f5a, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvttpd2pi", 2, 0x660f2c, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegMMX } }, + { "cvttsd2si", 2, 0xf20f2c, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + Reg32|Reg64 } }, + { "cvttpd2dq", 2, 0x660fe6, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cvttps2dq", 2, 0xf30f5b, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "maskmovdqu", 2, 0x660ff7, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + RegXMM } }, + { "movdqa", 2, 0x660f6f, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movdqa", 2, 0x660f7f, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, + { "movdqu", 2, 0xf30f6f, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movdqu", 2, 0xf30f7f, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, + { "movdq2q", 2, 0xf20fd6, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + RegMMX } }, + { "movq2dq", 2, 0xf30fd6, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegMMX, + RegXMM } }, + { "pmuludq", 2, 0xff4, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmuludq", 2, 0x660ff4, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pshufd", 3, 0x660f70, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pshufhw", 3, 0xf30f70, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pshuflw", 3, 0xf20f70, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pslldq", 2, 0x660f73, 0x7, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "psrldq", 2, 0x660f73, 0x3, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM } }, + { "punpckhqdq", 2, 0x660f6d, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "punpcklqdq", 2, 0x660f6c, None, CpuSSE2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "addsubpd", 2, 0x660fd0, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "addsubps", 2, 0xf20fd0, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "cmpxchg16b", 1, 0xfc7, 0x1, CpuSSE3|Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fisttp", 1, 0xdf, 0x1, CpuSSE3, + Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fisttp", 1, 0xdd, 0x1, CpuSSE3, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "fisttpll", 1, 0xdd, 0x1, CpuSSE3, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "haddpd", 2, 0x660f7c, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "haddps", 2, 0xf20f7c, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "hsubpd", 2, 0x660f7d, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "hsubps", 2, 0xf20f7d, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "lddqu", 2, 0xf20ff0, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "monitor", 0, 0xf01, 0xc8, CpuSSE3, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "monitor", 3, 0xf01, 0xc8, CpuSSE3|CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { Reg16|Reg32, + Reg32, + Reg32 } }, + { "monitor", 3, 0xf01, 0xc8, CpuSSE3|Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, + { Reg32|Reg64, + Reg64, + Reg64 } }, + { "movddup", 2, 0xf20f12, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movshdup", 2, 0xf30f16, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movsldup", 2, 0xf30f12, None, CpuSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "mwait", 0, 0xf01, 0xc9, CpuSSE3, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "mwait", 2, 0xf01, 0xc9, CpuSSE3|CpuNo64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { Reg32, + Reg32 } }, + { "mwait", 2, 0xf01, 0xc9, CpuSSE3|Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, + { Reg64, + Reg64 } }, + { "vmcall", 0, 0xf01, 0xc1, CpuVMX, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "vmclear", 1, 0x660fc7, 0x6, CpuVMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "vmlaunch", 0, 0xf01, 0xc2, CpuVMX, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "vmresume", 0, 0xf01, 0xc3, CpuVMX, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "vmptrld", 1, 0xfc7, 0x6, CpuVMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "vmptrst", 1, 0xfc7, 0x7, CpuVMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "vmread", 2, 0xf78, None, CpuVMX|CpuNo64, + Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg32, + Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "vmread", 2, 0xf78, None, CpuVMX|Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Reg64, + Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "vmwrite", 2, 0xf79, None, CpuVMX|CpuNo64, + Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32 } }, + { "vmwrite", 2, 0xf79, None, CpuVMX|Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg64 } }, + { "vmxoff", 0, 0xf01, 0xc4, CpuVMX, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "vmxon", 1, 0xf30fc7, 0x6, CpuVMX, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "phaddw", 2, 0xf3801, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "phaddw", 2, 0x660f3801, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "phaddd", 2, 0xf3802, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "phaddd", 2, 0x660f3802, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "phaddsw", 2, 0xf3803, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "phaddsw", 2, 0x660f3803, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "phsubw", 2, 0xf3805, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "phsubw", 2, 0x660f3805, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "phsubd", 2, 0xf3806, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "phsubd", 2, 0x660f3806, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "phsubsw", 2, 0xf3807, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "phsubsw", 2, 0x660f3807, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmaddubsw", 2, 0xf3804, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmaddubsw", 2, 0x660f3804, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmulhrsw", 2, 0xf380b, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmulhrsw", 2, 0x660f380b, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pshufb", 2, 0xf3800, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pshufb", 2, 0x660f3800, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psignb", 2, 0xf3808, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psignb", 2, 0x660f3808, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psignw", 2, 0xf3809, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psignw", 2, 0x660f3809, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "psignd", 2, 0xf380a, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "psignd", 2, 0x660f380a, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "palignr", 3, 0xf3a0f, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "palignr", 3, 0x660f3a0f, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pabsb", 2, 0xf381c, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pabsb", 2, 0x660f381c, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pabsw", 2, 0xf381d, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pabsw", 2, 0x660f381d, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pabsd", 2, 0xf381e, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pabsd", 2, 0x660f381e, None, CpuSSSE3, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "blendpd", 3, 0x660f3a0d, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "blendps", 3, 0x660f3a0c, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "blendvpd", 3, 0x660f3815, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "blendvps", 3, 0x660f3814, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "dppd", 3, 0x660f3a41, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "dpps", 3, 0x660f3a40, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "extractps", 3, 0x660f3a17, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM, + Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "insertps", 3, 0x660f3a21, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "movntdqa", 2, 0x660f382a, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "mpsadbw", 3, 0x660f3a42, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "packusdw", 2, 0x660f382b, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pblendvb", 3, 0x660f3810, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pblendw", 3, 0x660f3a0e, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpeqq", 2, 0x660f3829, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pextrb", 3, 0x660f3a14, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM, + Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "pextrd", 3, 0x660f3a16, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM, + Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "pextrq", 3, 0x660f3a16, None, CpuSSE4_1|Cpu64, + Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + RegXMM, + Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "phminposuw", 2, 0x660f3841, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pinsrb", 3, 0x660f3a20, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "pinsrd", 3, 0x660f3a22, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "pinsrq", 3, 0x660f3a22, None, CpuSSE4_1|Cpu64, + Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + RegXMM } }, + { "pmaxsb", 2, 0x660f383c, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmaxsd", 2, 0x660f383d, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmaxud", 2, 0x660f383f, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmaxuw", 2, 0x660f383e, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pminsb", 2, 0x660f3838, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pminsd", 2, 0x660f3839, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pminud", 2, 0x660f383b, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pminuw", 2, 0x660f383a, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovsxbw", 2, 0x660f3820, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovsxbd", 2, 0x660f3821, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovsxbq", 2, 0x660f3822, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovsxwd", 2, 0x660f3823, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovsxwq", 2, 0x660f3824, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovsxdq", 2, 0x660f3825, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovzxbw", 2, 0x660f3830, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovzxbd", 2, 0x660f3831, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovzxbq", 2, 0x660f3832, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovzxwd", 2, 0x660f3833, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovzxwq", 2, 0x660f3834, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmovzxdq", 2, 0x660f3835, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmuldq", 2, 0x660f3828, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pmulld", 2, 0x660f3840, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "ptest", 2, 0x660f3817, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "roundpd", 3, 0x660f3a09, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "roundps", 3, 0x660f3a08, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "roundsd", 3, 0x660f3a0b, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "roundss", 3, 0x660f3a0a, None, CpuSSE4_1, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpgtq", 2, 0x660f3837, None, CpuSSE4_2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpestri", 3, 0x660f3a61, None, CpuSSE4_2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpestrm", 3, 0x660f3a60, None, CpuSSE4_2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpistri", 3, 0x660f3a63, None, CpuSSE4_2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "pcmpistrm", 3, 0x660f3a62, None, CpuSSE4_2, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, + RegXMM } }, + { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2, + Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg16|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32 } }, + { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2|Cpu64, + Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|Rex64, + { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg64 } }, + { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32 } }, + { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2|Cpu64, + Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg64 } }, + { "prefetch", 1, 0xf0d, 0x0, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "prefetchw", 1, 0xf0d, 0x1, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "femms", 0, 0xf0e, None, Cpu3dnow, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "pavgusb", 2, 0xf0f, 0xbf, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pf2id", 2, 0xf0f, 0x1d, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pf2iw", 2, 0xf0f, 0x1c, Cpu3dnowA, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfacc", 2, 0xf0f, 0xae, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfadd", 2, 0xf0f, 0x9e, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfcmpeq", 2, 0xf0f, 0xb0, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfcmpge", 2, 0xf0f, 0x90, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfcmpgt", 2, 0xf0f, 0xa0, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfmax", 2, 0xf0f, 0xa4, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfmin", 2, 0xf0f, 0x94, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfmul", 2, 0xf0f, 0xb4, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfnacc", 2, 0xf0f, 0x8a, Cpu3dnowA, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfpnacc", 2, 0xf0f, 0x8e, Cpu3dnowA, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfrcp", 2, 0xf0f, 0x96, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfrcpit1", 2, 0xf0f, 0xa6, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfrcpit2", 2, 0xf0f, 0xb6, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfrsqit1", 2, 0xf0f, 0xa7, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfrsqrt", 2, 0xf0f, 0x97, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfsub", 2, 0xf0f, 0x9a, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pfsubr", 2, 0xf0f, 0xaa, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pi2fd", 2, 0xf0f, 0xd, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pi2fw", 2, 0xf0f, 0xc, Cpu3dnowA, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pmulhrw", 2, 0xf0f, 0xb7, Cpu3dnow, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "pswapd", 2, 0xf0f, 0xbb, Cpu3dnowA, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, + RegMMX } }, + { "syscall", 0, 0xf05, None, CpuK6, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { 0 } }, + { "sysret", 0, 0xf07, None, CpuK6, + DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + { 0 } }, + { "swapgs", 0, 0xf01, 0xf8, Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "rdtscp", 0, 0xf01, 0xf9, CpuSledgehammer, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "clgi", 0, 0xf01, 0xdd, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "invlpga", 0, 0xf01, 0xdf, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "invlpga", 2, 0xf01, 0xdf, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg32 } }, + { "skinit", 0, 0xf01, 0xde, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "skinit", 1, 0xf01, 0xde, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "stgi", 0, 0xf01, 0xdc, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "vmload", 0, 0xf01, 0xda, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "vmload", 1, 0xf01, 0xda, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "vmmcall", 0, 0xf01, 0xd9, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "vmrun", 0, 0xf01, 0xd8, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "vmrun", 1, 0xf01, 0xd8, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "vmsave", 0, 0xf01, 0xdb, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { 0 } }, + { "vmsave", 1, 0xf01, 0xdb, CpuSVME, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movntsd", 2, 0xf20f2b, None, CpuSSE4a, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "movntss", 2, 0xf30f2b, None, CpuSSE4a, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { "extrq", 3, 0x660f78, 0x0, CpuSSE4a, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + Imm8, + RegXMM } }, + { "extrq", 2, 0x660f79, None, CpuSSE4a, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + RegXMM } }, + { "insertq", 2, 0xf20f79, None, CpuSSE4a, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { RegXMM, + RegXMM } }, + { "insertq", 4, 0xf20f78, None, CpuSSE4a, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + { Imm8, + Imm8, + RegXMM, + RegXMM } }, + { "popcnt", 2, 0xf30fb8, None, CpuABM|CpuSSE4_2, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "lzcnt", 2, 0xf30fbd, None, CpuABM, + Modrm|No_bSuf|No_sSuf|No_xSuf, + { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, + Reg16|Reg32|Reg64 } }, + { "xstore-rng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcrypt-ecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcrypt-cbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcrypt-ctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcrypt-cfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcrypt-ofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xstorerng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { "xstore", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + { 0 } }, + { NULL, 0, 0, 0, 0, 0, { 0 } } +}; + +/* i386 register table. */ + +const reg_entry i386_regtab[] = +{ + { "st", FloatReg|FloatAcc, 0, 0 }, + { "al", Reg8|Acc, 0, 0 }, + { "cl", Reg8|ShiftCount, 0, 1 }, + { "dl", Reg8, 0, 2 }, + { "bl", Reg8, 0, 3 }, + { "ah", Reg8, 0, 4 }, + { "ch", Reg8, 0, 5 }, + { "dh", Reg8, 0, 6 }, + { "bh", Reg8, 0, 7 }, + { "axl", Reg8|Acc, RegRex64, 0 }, + { "cxl", Reg8, RegRex64, 1 }, + { "dxl", Reg8, RegRex64, 2 }, + { "bxl", Reg8, RegRex64, 3 }, + { "spl", Reg8, RegRex64, 4 }, + { "bpl", Reg8, RegRex64, 5 }, + { "sil", Reg8, RegRex64, 6 }, + { "dil", Reg8, RegRex64, 7 }, + { "r8b", Reg8, RegRex|RegRex64, 0 }, + { "r9b", Reg8, RegRex|RegRex64, 1 }, + { "r10b", Reg8, RegRex|RegRex64, 2 }, + { "r11b", Reg8, RegRex|RegRex64, 3 }, + { "r12b", Reg8, RegRex|RegRex64, 4 }, + { "r13b", Reg8, RegRex|RegRex64, 5 }, + { "r14b", Reg8, RegRex|RegRex64, 6 }, + { "r15b", Reg8, RegRex|RegRex64, 7 }, + { "ax", Reg16|Acc, 0, 0 }, + { "cx", Reg16, 0, 1 }, + { "dx", Reg16|InOutPortReg, 0, 2 }, + { "bx", Reg16|BaseIndex, 0, 3 }, + { "sp", Reg16, 0, 4 }, + { "bp", Reg16|BaseIndex, 0, 5 }, + { "si", Reg16|BaseIndex, 0, 6 }, + { "di", Reg16|BaseIndex, 0, 7 }, + { "r8w", Reg16, RegRex, 0 }, + { "r9w", Reg16, RegRex, 1 }, + { "r10w", Reg16, RegRex, 2 }, + { "r11w", Reg16, RegRex, 3 }, + { "r12w", Reg16, RegRex, 4 }, + { "r13w", Reg16, RegRex, 5 }, + { "r14w", Reg16, RegRex, 6 }, + { "r15w", Reg16, RegRex, 7 }, + { "eax", Reg32|BaseIndex|Acc, 0, 0 }, + { "ecx", Reg32|BaseIndex, 0, 1 }, + { "edx", Reg32|BaseIndex, 0, 2 }, + { "ebx", Reg32|BaseIndex, 0, 3 }, + { "esp", Reg32, 0, 4 }, + { "ebp", Reg32|BaseIndex, 0, 5 }, + { "esi", Reg32|BaseIndex, 0, 6 }, + { "edi", Reg32|BaseIndex, 0, 7 }, + { "r8d", Reg32|BaseIndex, RegRex, 0 }, + { "r9d", Reg32|BaseIndex, RegRex, 1 }, + { "r10d", Reg32|BaseIndex, RegRex, 2 }, + { "r11d", Reg32|BaseIndex, RegRex, 3 }, + { "r12d", Reg32|BaseIndex, RegRex, 4 }, + { "r13d", Reg32|BaseIndex, RegRex, 5 }, + { "r14d", Reg32|BaseIndex, RegRex, 6 }, + { "r15d", Reg32|BaseIndex, RegRex, 7 }, + { "rax", Reg64|BaseIndex|Acc, 0, 0 }, + { "rcx", Reg64|BaseIndex, 0, 1 }, + { "rdx", Reg64|BaseIndex, 0, 2 }, + { "rbx", Reg64|BaseIndex, 0, 3 }, + { "rsp", Reg64, 0, 4 }, + { "rbp", Reg64|BaseIndex, 0, 5 }, + { "rsi", Reg64|BaseIndex, 0, 6 }, + { "rdi", Reg64|BaseIndex, 0, 7 }, + { "r8", Reg64|BaseIndex, RegRex, 0 }, + { "r9", Reg64|BaseIndex, RegRex, 1 }, + { "r10", Reg64|BaseIndex, RegRex, 2 }, + { "r11", Reg64|BaseIndex, RegRex, 3 }, + { "r12", Reg64|BaseIndex, RegRex, 4 }, + { "r13", Reg64|BaseIndex, RegRex, 5 }, + { "r14", Reg64|BaseIndex, RegRex, 6 }, + { "r15", Reg64|BaseIndex, RegRex, 7 }, + { "es", SReg2, 0, 0 }, + { "cs", SReg2, 0, 1 }, + { "ss", SReg2, 0, 2 }, + { "ds", SReg2, 0, 3 }, + { "fs", SReg3, 0, 4 }, + { "gs", SReg3, 0, 5 }, + { "cr0", Control, 0, 0 }, + { "cr1", Control, 0, 1 }, + { "cr2", Control, 0, 2 }, + { "cr3", Control, 0, 3 }, + { "cr4", Control, 0, 4 }, + { "cr5", Control, 0, 5 }, + { "cr6", Control, 0, 6 }, + { "cr7", Control, 0, 7 }, + { "cr8", Control, RegRex, 0 }, + { "cr9", Control, RegRex, 1 }, + { "cr10", Control, RegRex, 2 }, + { "cr11", Control, RegRex, 3 }, + { "cr12", Control, RegRex, 4 }, + { "cr13", Control, RegRex, 5 }, + { "cr14", Control, RegRex, 6 }, + { "cr15", Control, RegRex, 7 }, + { "db0", Debug, 0, 0 }, + { "db1", Debug, 0, 1 }, + { "db2", Debug, 0, 2 }, + { "db3", Debug, 0, 3 }, + { "db4", Debug, 0, 4 }, + { "db5", Debug, 0, 5 }, + { "db6", Debug, 0, 6 }, + { "db7", Debug, 0, 7 }, + { "db8", Debug, RegRex, 0 }, + { "db9", Debug, RegRex, 1 }, + { "db10", Debug, RegRex, 2 }, + { "db11", Debug, RegRex, 3 }, + { "db12", Debug, RegRex, 4 }, + { "db13", Debug, RegRex, 5 }, + { "db14", Debug, RegRex, 6 }, + { "db15", Debug, RegRex, 7 }, + { "dr0", Debug, 0, 0 }, + { "dr1", Debug, 0, 1 }, + { "dr2", Debug, 0, 2 }, + { "dr3", Debug, 0, 3 }, + { "dr4", Debug, 0, 4 }, + { "dr5", Debug, 0, 5 }, + { "dr6", Debug, 0, 6 }, + { "dr7", Debug, 0, 7 }, + { "dr8", Debug, RegRex, 0 }, + { "dr9", Debug, RegRex, 1 }, + { "dr10", Debug, RegRex, 2 }, + { "dr11", Debug, RegRex, 3 }, + { "dr12", Debug, RegRex, 4 }, + { "dr13", Debug, RegRex, 5 }, + { "dr14", Debug, RegRex, 6 }, + { "dr15", Debug, RegRex, 7 }, + { "tr0", Test, 0, 0 }, + { "tr1", Test, 0, 1 }, + { "tr2", Test, 0, 2 }, + { "tr3", Test, 0, 3 }, + { "tr4", Test, 0, 4 }, + { "tr5", Test, 0, 5 }, + { "tr6", Test, 0, 6 }, + { "tr7", Test, 0, 7 }, + { "mm0", RegMMX, 0, 0 }, + { "mm1", RegMMX, 0, 1 }, + { "mm2", RegMMX, 0, 2 }, + { "mm3", RegMMX, 0, 3 }, + { "mm4", RegMMX, 0, 4 }, + { "mm5", RegMMX, 0, 5 }, + { "mm6", RegMMX, 0, 6 }, + { "mm7", RegMMX, 0, 7 }, + { "xmm0", RegXMM, 0, 0 }, + { "xmm1", RegXMM, 0, 1 }, + { "xmm2", RegXMM, 0, 2 }, + { "xmm3", RegXMM, 0, 3 }, + { "xmm4", RegXMM, 0, 4 }, + { "xmm5", RegXMM, 0, 5 }, + { "xmm6", RegXMM, 0, 6 }, + { "xmm7", RegXMM, 0, 7 }, + { "xmm8", RegXMM, RegRex, 0 }, + { "xmm9", RegXMM, RegRex, 1 }, + { "xmm10", RegXMM, RegRex, 2 }, + { "xmm11", RegXMM, RegRex, 3 }, + { "xmm12", RegXMM, RegRex, 4 }, + { "xmm13", RegXMM, RegRex, 5 }, + { "xmm14", RegXMM, RegRex, 6 }, + { "xmm15", RegXMM, RegRex, 7 }, + { "rip", BaseIndex, 0, 0 }, + { "st(0)", FloatReg|FloatAcc, 0, 0 }, + { "st(1)", FloatReg, 0, 1 }, + { "st(2)", FloatReg, 0, 2 }, + { "st(3)", FloatReg, 0, 3 }, + { "st(4)", FloatReg, 0, 4 }, + { "st(5)", FloatReg, 0, 5 }, + { "st(6)", FloatReg, 0, 6 }, + { "st(7)", FloatReg, 0, 7 }, +}; + +const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab); diff --git a/contrib/binutils/opcodes/ia64-gen.c b/contrib/binutils/opcodes/ia64-gen.c index 5562283..b1d0225 100644 --- a/contrib/binutils/opcodes/ia64-gen.c +++ b/contrib/binutils/opcodes/ia64-gen.c @@ -467,7 +467,7 @@ fetch_insn_class (const char *full_name, int create) int ind; int is_class = 0; - if (strncmp (full_name, "IC:", 3) == 0) + if (CONST_STRNEQ (full_name, "IC:")) { name = xstrdup (full_name + 3); is_class = 1; @@ -749,7 +749,7 @@ parse_resource_users (ref, usersp, nusersp, notesp) are read. Only create new classes if it's *not* an insn class, or if it's a composite class (which wouldn't necessarily be in the IC table). */ - if (strncmp (name, "IC:", 3) != 0 || xsect != NULL) + if (! CONST_STRNEQ (name, "IC:") || xsect != NULL) create = 1; iclass = fetch_insn_class (name, create); @@ -1034,7 +1034,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic, if (ic->comment) { - if (!strncmp (ic->comment, "Format", 6)) + if (CONST_STRNEQ (ic->comment, "Format")) { /* Assume that the first format seen is the most restrictive, and only keep a later one if it looks like it's more restrictive. */ @@ -1050,7 +1050,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic, else format = ic->comment; } - else if (!strncmp (ic->comment, "Field", 5)) + else if (CONST_STRNEQ (ic->comment, "Field")) { if (field) warn (_("overlapping field %s->%s\n"), @@ -1064,7 +1064,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic, instructions. */ if (ic->nsubs == 0 && ic->nxsubs == 0) { - int is_mov = strncmp (idesc->name, "mov", 3) == 0; + int is_mov = CONST_STRNEQ (idesc->name, "mov"); int plain_mov = strcmp (idesc->name, "mov") == 0; int len = strlen(ic->name); @@ -1123,32 +1123,32 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic, if (resolved && format) { - if (strncmp (idesc->name, "dep", 3) == 0 + if (CONST_STRNEQ (idesc->name, "dep") && strstr (format, "I13") != NULL) resolved = idesc->operands[1] == IA64_OPND_IMM8; - else if (strncmp (idesc->name, "chk", 3) == 0 + else if (CONST_STRNEQ (idesc->name, "chk") && strstr (format, "M21") != NULL) resolved = idesc->operands[0] == IA64_OPND_F2; - else if (strncmp (idesc->name, "lfetch", 6) == 0) + else if (CONST_STRNEQ (idesc->name, "lfetch")) resolved = (strstr (format, "M14 M15") != NULL && (idesc->operands[1] == IA64_OPND_R2 || idesc->operands[1] == IA64_OPND_IMM9b)); - else if (strncmp (idesc->name, "br.call", 7) == 0 + else if (CONST_STRNEQ (idesc->name, "br.call") && strstr (format, "B5") != NULL) resolved = idesc->operands[1] == IA64_OPND_B2; - else if (strncmp (idesc->name, "br.call", 7) == 0 + else if (CONST_STRNEQ (idesc->name, "br.call") && strstr (format, "B3") != NULL) resolved = idesc->operands[1] == IA64_OPND_TGT25c; - else if (strncmp (idesc->name, "brp", 3) == 0 + else if (CONST_STRNEQ (idesc->name, "brp") && strstr (format, "B7") != NULL) resolved = idesc->operands[0] == IA64_OPND_B2; else if (strcmp (ic->name, "invala") == 0) resolved = strcmp (idesc->name, ic->name) == 0; - else if (strncmp (idesc->name, "st", 2) == 0 + else if (CONST_STRNEQ (idesc->name, "st") && (strstr (format, "M5") != NULL || strstr (format, "M10") != NULL)) resolved = idesc->flags & IA64_OPCODE_POSTINC; - else if (strncmp (idesc->name, "ld", 2) == 0 + else if (CONST_STRNEQ (idesc->name, "ld") && (strstr (format, "M2 M3") != NULL || strstr (format, "M12") != NULL || strstr (format, "M7 M8") != NULL)) @@ -1161,7 +1161,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic, plain brl matches brl.cond. */ if (!resolved && (strcmp (idesc->name, "brl") == 0 - || strncmp (idesc->name, "brl.", 4) == 0) + || CONST_STRNEQ (idesc->name, "brl.")) && strcmp (ic->name, "brl.cond") == 0) { resolved = 1; @@ -1170,7 +1170,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic, /* Misc br variations ('.cond' is optional). */ if (!resolved && (strcmp (idesc->name, "br") == 0 - || strncmp (idesc->name, "br.", 3) == 0) + || CONST_STRNEQ (idesc->name, "br.")) && strcmp (ic->name, "br.cond") == 0) { if (format) @@ -1183,7 +1183,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic, } /* probe variations. */ - if (!resolved && strncmp (idesc->name, "probe", 5) == 0) + if (!resolved && CONST_STRNEQ (idesc->name, "probe")) { resolved = strcmp (ic->name, "probe") == 0 && !((strstr (idesc->name, "fault") != NULL) @@ -1217,7 +1217,7 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic, } /* Some variants of mov and mov.[im]. */ - if (!resolved && strncmp (ic->name, "mov_", 4) == 0) + if (!resolved && CONST_STRNEQ (ic->name, "mov_")) resolved = in_iclass_mov_x (idesc, ic, format, field); } @@ -1476,13 +1476,13 @@ lookup_specifier (const char *name) warn (_("Don't know how to specify # dependency %s\n"), name); } - else if (strncmp (name, "AR[FPSR]", 8) == 0) + else if (CONST_STRNEQ (name, "AR[FPSR]")) return IA64_RS_AR_FPSR; - else if (strncmp (name, "AR[", 3) == 0) + else if (CONST_STRNEQ (name, "AR[")) return IA64_RS_ARX; - else if (strncmp (name, "CR[", 3) == 0) + else if (CONST_STRNEQ (name, "CR[")) return IA64_RS_CRX; - else if (strncmp (name, "PSR.", 4) == 0) + else if (CONST_STRNEQ (name, "PSR.")) return IA64_RS_PSR; else if (strcmp (name, "InService*") == 0) return IA64_RS_INSERVICE; @@ -2448,7 +2448,7 @@ insert_opcode_dependencies (opc, cmp) int j; if (strcmp (opc->name, "cmp.eq.and") == 0 - && strncmp (rs->name, "PR%", 3) == 0 + && CONST_STRNEQ (rs->name, "PR%") && rs->mode == 1) no_class_found = 99; @@ -2459,7 +2459,7 @@ insert_opcode_dependencies (opc, cmp) if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note)) { /* We can ignore ic_note 11 for non PR resources. */ - if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + if (ic_note == 11 && ! CONST_STRNEQ (rs->name, "PR")) ic_note = 0; if (ic_note != 0 && rs->regnotes[j] != 0 @@ -2487,7 +2487,7 @@ insert_opcode_dependencies (opc, cmp) if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note)) { /* We can ignore ic_note 11 for non PR resources. */ - if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + if (ic_note == 11 && ! CONST_STRNEQ (rs->name, "PR")) ic_note = 0; if (ic_note != 0 && rs->chknotes[j] != 0 diff --git a/contrib/binutils/opcodes/mep-asm.c b/contrib/binutils/opcodes/mep-asm.c new file mode 100644 index 0000000..66f20a7 --- /dev/null +++ b/contrib/binutils/opcodes/mep-asm.c @@ -0,0 +1,1398 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. + + This file is part of the GNU Binutils and GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ + +#define CGEN_VALIDATE_INSN_SUPPORTED + + const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); + const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); + const char * parse_spreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); + const char * parse_mep_align (CGEN_CPU_DESC, const char **, enum cgen_operand_type, long *); + const char * parse_mep_alignu (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); +static const char * parse_signed16 (CGEN_CPU_DESC, const char **, int, long *); +static const char * parse_unsigned16 (CGEN_CPU_DESC, const char **, int, unsigned long *); +static const char * parse_lo16 (CGEN_CPU_DESC, const char **, int, long *, long); +static const char * parse_unsigned7 (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); +static const char * parse_zero (CGEN_CPU_DESC, const char **, int, long *); + +const char * +parse_csrn (CGEN_CPU_DESC cd, const char **strp, + CGEN_KEYWORD *keyword_table, long *field) +{ + const char *err; + unsigned long value; + + err = cgen_parse_keyword (cd, strp, keyword_table, field); + if (!err) + return NULL; + + err = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, & value); + if (err) + return err; + *field = value; + return NULL; +} + +/* begin-cop-ip-parse-handlers */ +static const char * +parse_fmax_cr (CGEN_CPU_DESC cd, + const char **strp, + CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, + long *field) +{ + return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_fmax, field); +} +static const char * +parse_fmax_ccr (CGEN_CPU_DESC cd, + const char **strp, + CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, + long *field) +{ + return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_fmax, field); +} +/* end-cop-ip-parse-handlers */ + +const char * +parse_tpreg (CGEN_CPU_DESC cd, const char ** strp, + CGEN_KEYWORD *keyword_table, long *field) +{ + const char *err; + + err = cgen_parse_keyword (cd, strp, keyword_table, field); + if (err) + return err; + if (*field != 13) + return _("Only $tp or $13 allowed for this opcode"); + return NULL; +} + +const char * +parse_spreg (CGEN_CPU_DESC cd, const char ** strp, + CGEN_KEYWORD *keyword_table, long *field) +{ + const char *err; + + err = cgen_parse_keyword (cd, strp, keyword_table, field); + if (err) + return err; + if (*field != 15) + return _("Only $sp or $15 allowed for this opcode"); + return NULL; +} + +const char * +parse_mep_align (CGEN_CPU_DESC cd, const char ** strp, + enum cgen_operand_type type, long *field) +{ + long lsbs = 0; + const char *err; + + switch (type) + { + case MEP_OPERAND_PCREL8A2: + case MEP_OPERAND_PCREL12A2: + case MEP_OPERAND_PCREL17A2: + case MEP_OPERAND_PCREL24A2: + case MEP_OPERAND_CDISP8A2: + case MEP_OPERAND_CDISP8A4: + case MEP_OPERAND_CDISP8A8: + err = cgen_parse_signed_integer (cd, strp, type, field); + break; + case MEP_OPERAND_PCABS24A2: + case MEP_OPERAND_UDISP7: + case MEP_OPERAND_UDISP7A2: + case MEP_OPERAND_UDISP7A4: + case MEP_OPERAND_UIMM7A4: + case MEP_OPERAND_ADDR24A4: + err = cgen_parse_unsigned_integer (cd, strp, type, (unsigned long *) field); + break; + default: + abort(); + } + if (err) + return err; + switch (type) + { + case MEP_OPERAND_UDISP7: + lsbs = 0; + break; + case MEP_OPERAND_PCREL8A2: + case MEP_OPERAND_PCREL12A2: + case MEP_OPERAND_PCREL17A2: + case MEP_OPERAND_PCREL24A2: + case MEP_OPERAND_PCABS24A2: + case MEP_OPERAND_UDISP7A2: + case MEP_OPERAND_CDISP8A2: + lsbs = *field & 1; + break; + case MEP_OPERAND_UDISP7A4: + case MEP_OPERAND_UIMM7A4: + case MEP_OPERAND_ADDR24A4: + case MEP_OPERAND_CDISP8A4: + lsbs = *field & 3; + break; + case MEP_OPERAND_CDISP8A8: + lsbs = *field & 7; + break; + default: + /* Safe assumption? */ + abort (); + } + if (lsbs) + return "Value is not aligned enough"; + return NULL; +} + +const char * +parse_mep_alignu (CGEN_CPU_DESC cd, const char ** strp, + enum cgen_operand_type type, unsigned long *field) +{ + return parse_mep_align (cd, strp, type, (long *) field); +} + + +/* Handle %lo(), %tpoff(), %sdaoff(), %hi(), and other signed + constants in a signed context. */ + +static const char * +parse_signed16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) +{ + return parse_lo16 (cd, strp, opindex, valuep, 1); +} + +static const char * +parse_lo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep, + long signedp) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, + & result_type, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + if (signedp) + *valuep = (long)(short) value; + else + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%hi(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, + & result_type, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = (value + 0x8000) >> 16; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%uhi(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, + & result_type, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = value >> 16; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%sdaoff(", 8) == 0) + { + *strp += 8; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, + NULL, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%tpoff(", 7) == 0) + { + *strp += 7; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, + NULL, & value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + *valuep = value; + return errmsg; + } + + if (**strp == '%') + return _("invalid %function() here"); + + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +static const char * +parse_unsigned16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + return parse_lo16 (cd, strp, opindex, (long *) valuep, 0); +} + +/* A special case of parse_signed16 which accepts only the value zero. */ + +static const char * +parse_zero (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + /*fprintf(stderr, "dj: signed parse opindex `%s'\n", *strp);*/ + + /* Prevent ($ry) from being attempted as an expression on 'sw $rx,($ry)'. + It will fail and cause ry to be listed as an undefined symbol in the + listing. */ + if (strncmp (*strp, "($", 2) == 0) + return "not zero"; /* any string will do -- will never be seen. */ + + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%hi(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%uhi(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%sdaoff(", 8) == 0) + { + *strp += 8; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "%tpoff(", 7) == 0) + { + *strp += 7; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, + &result_type, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + *valuep = value; + return errmsg; + } + + if (**strp == '%') + return "invalid %function() here"; + + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_NONE, + &result_type, &value); + if (errmsg == NULL + && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) + return "not zero"; /* any string will do -- will never be seen. */ + + return errmsg; +} + +static const char * +parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp, + enum cgen_operand_type opindex, unsigned long *valuep) +{ + const char *errmsg; + bfd_vma value; + + /* fprintf(stderr, "dj: unsigned7 parse `%s'\n", *strp); */ + + if (strncasecmp (*strp, "%tpoff(", 7) == 0) + { + int reloc; + *strp += 7; + switch (opindex) + { + case MEP_OPERAND_UDISP7: + reloc = BFD_RELOC_MEP_TPREL7; + break; + case MEP_OPERAND_UDISP7A2: + reloc = BFD_RELOC_MEP_TPREL7A2; + break; + case MEP_OPERAND_UDISP7A4: + reloc = BFD_RELOC_MEP_TPREL7A4; + break; + default: + /* Safe assumption? */ + abort (); + } + errmsg = cgen_parse_address (cd, strp, opindex, reloc, + NULL, &value); + if (**strp != ')') + return "missing `)'"; + ++*strp; + *valuep = value; + return errmsg; + } + + if (**strp == '%') + return _("invalid %function() here"); + + return parse_mep_alignu (cd, strp, opindex, valuep); +} + +/* BEGIN LIGHTWEIGHT MACRO PROCESSOR. */ + +#define MAXARGS 9 + +typedef struct +{ + char *name; + char *expansion; +} macro; + +typedef struct +{ + const char *start; + int len; +} arg; + +macro macros[] = +{ + { "sizeof", "(`1.end + (- `1))"}, + { "startof", "(`1 | 0)" }, + { "align4", "(`1&(~3))"}, +/*{ "hi", "(((`1+0x8000)>>16) & 0xffff)" }, */ +/*{ "lo", "(`1 & 0xffff)" }, */ +/*{ "sdaoff", "((`1-__sdabase) & 0x7f)"}, */ +/*{ "tpoff", "((`1-__tpbase) & 0x7f)"}, */ + { 0,0 } +}; + +static char * expand_string (const char *, int); + +static const char * +mep_cgen_expand_macros_and_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +static char * +str_append (char *dest, const char *input, int len) +{ + char *new_dest; + int oldlen; + + if (len == 0) + return dest; + /* printf("str_append: <<%s>>, <<%s>>, %d\n", dest, input, len); */ + oldlen = (dest ? strlen(dest) : 0); + new_dest = realloc (dest, oldlen + len + 1); + memset (new_dest + oldlen, 0, len + 1); + return strncat (new_dest, input, len); +} + +static macro * +lookup_macro (const char *name) +{ + macro *m; + + for (m = macros; m->name; ++m) + if (strncmp (m->name, name, strlen(m->name)) == 0) + return m; + + return 0; +} + +static char * +expand_macro (arg *args, int narg, macro *mac) +{ + char *result = 0, *rescanned_result = 0; + char *e = mac->expansion; + char *mark = e; + int arg = 0; + + /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ + while (*e) + { + if (*e == '`' && + (*e+1) && + ((*(e + 1) - '1') <= MAXARGS) && + ((*(e + 1) - '1') <= narg)) + { + result = str_append (result, mark, e - mark); + arg = (*(e + 1) - '1'); + /* printf("replacing `%d with %s\n", arg+1, args[arg].start); */ + result = str_append (result, args[arg].start, args[arg].len); + ++e; + mark = e+1; + } + ++e; + } + + if (mark != e) + result = str_append (result, mark, e - mark); + + if (result) + { + rescanned_result = expand_string (result, 0); + free (result); + return rescanned_result; + } + else + return result; +} + +#define IN_TEXT 0 +#define IN_ARGS 1 + +static char * +expand_string (const char *in, int first_only) +{ + int num_expansions = 0; + int depth = 0; + int narg = -1; + arg args[MAXARGS]; + int state = IN_TEXT; + const char *mark = in; + macro *macro = 0; + + char *expansion = 0; + char *result = 0; + + while (*in) + { + switch (state) + { + case IN_TEXT: + if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) + { + macro = lookup_macro (in + 1); + if (macro) + { + /* printf("entering state %d at '%s'...\n", state, in); */ + result = str_append (result, mark, in - mark); + mark = in; + in += 1 + strlen (macro->name); + while (*in == ' ') ++in; + if (*in != '(') + { + state = IN_TEXT; + macro = 0; + } + else + { + state = IN_ARGS; + narg = 0; + args[narg].start = in + 1; + args[narg].len = 0; + mark = in + 1; + } + } + } + break; + case IN_ARGS: + if (depth == 0) + { + switch (*in) + { + case ',': + narg++; + args[narg].start = (in + 1); + args[narg].len = 0; + break; + case ')': + state = IN_TEXT; + /* printf("entering state %d at '%s'...\n", state, in); */ + if (macro) + { + expansion = 0; + expansion = expand_macro (args, narg, macro); + num_expansions++; + if (expansion) + { + result = str_append (result, expansion, strlen (expansion)); + free (expansion); + } + } + else + { + result = str_append (result, mark, in - mark); + } + macro = 0; + mark = in + 1; + break; + case '(': + depth++; + default: + args[narg].len++; + break; + } + } + else + { + if (*in == ')') + depth--; + if (narg > -1) + args[narg].len++; + } + + } + ++in; + } + + if (mark != in) + result = str_append (result, mark, in - mark); + + return result; +} + +#undef IN_ARGS +#undef IN_TEXT +#undef MAXARGS + + +/* END LIGHTWEIGHT MACRO PROCESSOR. */ + +const char * mep_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +const char * +mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex, + const char ** strp_in, CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + char *str = 0, *hold = 0; + const char **strp = 0; + + /* Set up a new pointer to macro-expanded string. */ + str = expand_string (*strp_in, 1); + /* fprintf (stderr, " expanded <<%s>> to <<%s>>\n", *strp_in, str); */ + + hold = str; + strp = (const char **)(&str); + + errmsg = mep_cgen_parse_operand (cd, opindex, strp, fields); + + /* Now work out the advance. */ + if (strlen (str) == 0) + *strp_in += strlen (*strp_in); + + else + { + if (strstr (*strp_in, str)) + /* A macro-expansion was pulled off the front. */ + *strp_in = strstr (*strp_in, str); + else + /* A non-macro-expansion was pulled off the front. */ + *strp_in += (str - hold); + } + + if (hold) + free (hold); + + return errmsg; +} + +#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); + +/* -- dis.c */ + +const char * mep_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +mep_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + errmsg = parse_mep_alignu (cd, strp, MEP_OPERAND_ADDR24A4, (unsigned long *) (& fields->f_24u8a4n)); + break; + case MEP_OPERAND_CALLNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CALLNUM, (unsigned long *) (& fields->f_callnum)); + break; + case MEP_OPERAND_CCCC : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CCCC, (unsigned long *) (& fields->f_rm)); + break; + case MEP_OPERAND_CCRN : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr, & fields->f_ccrn); + break; + case MEP_OPERAND_CDISP8 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_CDISP8, (long *) (& fields->f_8s24)); + break; + case MEP_OPERAND_CDISP8A2 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_CDISP8A2, (long *) (& fields->f_8s24a2)); + break; + case MEP_OPERAND_CDISP8A4 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_CDISP8A4, (long *) (& fields->f_8s24a4)); + break; + case MEP_OPERAND_CDISP8A8 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_CDISP8A8, (long *) (& fields->f_8s24a8)); + break; + case MEP_OPERAND_CIMM4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CIMM4, (unsigned long *) (& fields->f_rn)); + break; + case MEP_OPERAND_CIMM5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CIMM5, (unsigned long *) (& fields->f_5u24)); + break; + case MEP_OPERAND_CODE16 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CODE16, (unsigned long *) (& fields->f_16u16)); + break; + case MEP_OPERAND_CODE24 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CODE24, (unsigned long *) (& fields->f_24u4n)); + break; + case MEP_OPERAND_CP_FLAG : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr, & junk); + break; + case MEP_OPERAND_CRN : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr, & fields->f_crn); + break; + case MEP_OPERAND_CRN64 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_crn); + break; + case MEP_OPERAND_CRNX : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr, & fields->f_crnx); + break; + case MEP_OPERAND_CRNX64 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_crnx); + break; + case MEP_OPERAND_CSRN : + errmsg = parse_csrn (cd, strp, & mep_cgen_opval_h_csr, & fields->f_csrn); + break; + case MEP_OPERAND_CSRN_IDX : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, (unsigned long *) (& fields->f_csrn)); + break; + case MEP_OPERAND_DBG : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_DEPC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_EPC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_EXC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_FMAX_CCRN : + errmsg = parse_fmax_ccr (cd, strp, & mep_cgen_opval_h_ccr, & fields->f_fmax_4_4); + break; + case MEP_OPERAND_FMAX_FRD : + errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frd); + break; + case MEP_OPERAND_FMAX_FRD_INT : + errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frd); + break; + case MEP_OPERAND_FMAX_FRM : + errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frm); + break; + case MEP_OPERAND_FMAX_FRN : + errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frn); + break; + case MEP_OPERAND_FMAX_FRN_INT : + errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frn); + break; + case MEP_OPERAND_FMAX_RM : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_fmax_rm); + break; + case MEP_OPERAND_HI : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_LO : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_LP : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_MB0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_MB1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_ME0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_ME1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_NPC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_OPT : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_PCABS24A2 : + errmsg = parse_mep_alignu (cd, strp, MEP_OPERAND_PCABS24A2, (unsigned long *) (& fields->f_24u5a2n)); + break; + case MEP_OPERAND_PCREL12A2 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_PCREL12A2, (long *) (& fields->f_12s4a2)); + break; + case MEP_OPERAND_PCREL17A2 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_PCREL17A2, (long *) (& fields->f_17s16a2)); + break; + case MEP_OPERAND_PCREL24A2 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_PCREL24A2, (long *) (& fields->f_24s5a2n)); + break; + case MEP_OPERAND_PCREL8A2 : + errmsg = parse_mep_align (cd, strp, MEP_OPERAND_PCREL8A2, (long *) (& fields->f_8s8a2)); + break; + case MEP_OPERAND_PSW : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_R0 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_R1 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_RL : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rl); + break; + case MEP_OPERAND_RM : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rm); + break; + case MEP_OPERAND_RMA : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rm); + break; + case MEP_OPERAND_RN : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RN3 : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3C : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3L : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3S : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3UC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3UL : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RN3US : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn3); + break; + case MEP_OPERAND_RNC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNL : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNS : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNUC : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNUL : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_RNUS : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_rn); + break; + case MEP_OPERAND_SAR : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk); + break; + case MEP_OPERAND_SDISP16 : + errmsg = parse_signed16 (cd, strp, MEP_OPERAND_SDISP16, (long *) (& fields->f_16s16)); + break; + case MEP_OPERAND_SIMM16 : + errmsg = parse_signed16 (cd, strp, MEP_OPERAND_SIMM16, (long *) (& fields->f_16s16)); + break; + case MEP_OPERAND_SIMM6 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM6, (long *) (& fields->f_6s8)); + break; + case MEP_OPERAND_SIMM8 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8, (long *) (& fields->f_8s8)); + break; + case MEP_OPERAND_SP : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_SPR : + errmsg = parse_spreg (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_TP : + errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_TPR : + errmsg = parse_tpreg (cd, strp, & mep_cgen_opval_h_gpr, & junk); + break; + case MEP_OPERAND_UDISP2 : + errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_UDISP2, (long *) (& fields->f_2u6)); + break; + case MEP_OPERAND_UDISP7 : + errmsg = parse_unsigned7 (cd, strp, MEP_OPERAND_UDISP7, (unsigned long *) (& fields->f_7u9)); + break; + case MEP_OPERAND_UDISP7A2 : + errmsg = parse_unsigned7 (cd, strp, MEP_OPERAND_UDISP7A2, (unsigned long *) (& fields->f_7u9a2)); + break; + case MEP_OPERAND_UDISP7A4 : + errmsg = parse_unsigned7 (cd, strp, MEP_OPERAND_UDISP7A4, (unsigned long *) (& fields->f_7u9a4)); + break; + case MEP_OPERAND_UIMM16 : + errmsg = parse_unsigned16 (cd, strp, MEP_OPERAND_UIMM16, (unsigned long *) (& fields->f_16u16)); + break; + case MEP_OPERAND_UIMM2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM2, (unsigned long *) (& fields->f_2u10)); + break; + case MEP_OPERAND_UIMM24 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM24, (unsigned long *) (& fields->f_24u8n)); + break; + case MEP_OPERAND_UIMM3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM3, (unsigned long *) (& fields->f_3u5)); + break; + case MEP_OPERAND_UIMM4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM4, (unsigned long *) (& fields->f_4u8)); + break; + case MEP_OPERAND_UIMM5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_UIMM5, (unsigned long *) (& fields->f_5u8)); + break; + case MEP_OPERAND_UIMM7A4 : + errmsg = parse_mep_alignu (cd, strp, MEP_OPERAND_UIMM7A4, (unsigned long *) (& fields->f_7u9a4)); + break; + case MEP_OPERAND_ZERO : + errmsg = parse_zero (cd, strp, MEP_OPERAND_ZERO, (long *) (& junk)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const mep_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +mep_cgen_init_asm (CGEN_CPU_DESC cd) +{ + mep_cgen_init_opcode_table (cd); + mep_cgen_init_ibld_table (cd); + cd->parse_handlers = & mep_cgen_parse_handlers[0]; + cd->parse_operand = mep_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by mep_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +mep_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +mep_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! mep_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} diff --git a/contrib/binutils/opcodes/mep-desc.c b/contrib/binutils/opcodes/mep-desc.c new file mode 100644 index 0000000..ab0f9bd --- /dev/null +++ b/contrib/binutils/opcodes/mep-desc.c @@ -0,0 +1,2729 @@ +/* CPU data for mep. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include <stdio.h> +#include <stdarg.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "mep", MACH_MEP }, + { "h1", MACH_H1 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "mep", ISA_MEP }, + { "ext_core1", ISA_EXT_CORE1 }, + { "ext_core2", ISA_EXT_CORE2 }, + { "ext_cop2_16", ISA_EXT_COP2_16 }, + { "ext_cop2_32", ISA_EXT_COP2_32 }, + { "ext_cop2_48", ISA_EXT_COP2_48 }, + { "ext_cop2_64", ISA_EXT_COP2_64 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED = +{ + { "LABEL", CDATA_LABEL }, + { "REGNUM", CDATA_REGNUM }, + { "FMAX_FLOAT", CDATA_FMAX_FLOAT }, + { "FMAX_INT", CDATA_FMAX_INT }, + { "POINTER", CDATA_POINTER }, + { "LONG", CDATA_LONG }, + { "ULONG", CDATA_ULONG }, + { "SHORT", CDATA_SHORT }, + { "USHORT", CDATA_USHORT }, + { "CHAR", CDATA_CHAR }, + { "UCHAR", CDATA_UCHAR }, + { "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED = +{ + {"integer", 1}, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED = +{ + {"integer", 0}, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED = +{ + { "NONE", CONFIG_NONE }, + { "simple", CONFIG_SIMPLE }, + { "fmax", CONFIG_FMAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { "IS_FLOAT", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "CDATA", & CDATA_attr[0], & CDATA_attr[0] }, + { "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] }, + { "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] }, + { "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] }, + { "MAY_TRAP", &bool_attr[0], &bool_attr[0] }, + { "VLIW_ALONE", &bool_attr[0], &bool_attr[0] }, + { "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] }, + { "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] }, + { "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] }, + { "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] }, + { "VOLATILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA mep_cgen_isa_table[] = { + { "mep", 32, 32, 16, 32 }, + { "ext_core1", 32, 32, 16, 32 }, + { "ext_core2", 32, 32, 16, 32 }, + { "ext_cop2_16", 32, 32, 65535, 0 }, + { "ext_cop2_32", 32, 32, 65535, 0 }, + { "ext_cop2_48", 32, 32, 65535, 0 }, + { "ext_cop2_64", 32, 32, 65535, 0 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH mep_cgen_mach_table[] = { + { "mep", "mep", MACH_MEP, 16 }, + { "h1", "h1", MACH_H1, 16 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] = +{ + { "$0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$fp", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$tp", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$gp", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$sp", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_gpr = +{ + & mep_cgen_opval_h_gpr_entries[0], + 20, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] = +{ + { "$pc", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$lp", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$sar", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$hi", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$lo", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$me0", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$me1", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$psw", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$id", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$epc", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$exc", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$npc", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$depc", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$opt", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_csr = +{ + & mep_cgen_opval_h_csr_entries[0], + 24, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] = +{ + { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_cr64 = +{ + & mep_cgen_opval_h_cr64_entries[0], + 32, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] = +{ + { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_cr = +{ + & mep_cgen_opval_h_cr_entries[0], + 32, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] = +{ + { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_ccr = +{ + & mep_cgen_opval_h_ccr_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_fmax_entries[] = +{ + { "$fr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$fr31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "$c0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$c1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$c2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "$c3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "$c4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "$c5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "$c6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "$c7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "$c8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "$c9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "$c10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "$c11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "$c12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "$c13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "$c14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "$c15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$c16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "$c17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "$c18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "$c19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "$c20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "$c21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "$c22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "$c23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "$c24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "$c25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "$c26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "$c27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "$c28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "$c29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "$c30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "$c31", 31, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_cr_fmax = +{ + & mep_cgen_opval_h_cr_fmax_entries[0], + 64, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_fmax_entries[] = +{ + { "$cirr", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$fcr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "$cbcr", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$fcr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "$cerr", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$fcr15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax = +{ + & mep_cgen_opval_h_ccr_fmax_entries[0], + 9, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY mep_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { "h-cr-fmax", HW_H_CR_FMAX, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_fmax, { 0|A(IS_FLOAT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { "h-ccr-fmax", HW_H_CCR_FMAX, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_fmax, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { "h-fmax-compare-i-p", HW_H_FMAX_COMPARE_I_P, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } +}; + +#undef A + + +/* The instruction field table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_IFLD_##a) +#else +#define A(a) (1 << CGEN_IFLD_/**/a) +#endif + +const CGEN_IFLD mep_cgen_ifld_table[] = +{ + { MEP_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { MEP_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, + { MEP_F_MAJOR, "f-major", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_RN3, "f-rn3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_RL, "f-rl", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_SUB2, "f-sub2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CRNX, "f-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_0, "f-0", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_1, "f-1", 0, 32, 1, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_2, "f-2", 0, 32, 2, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_3, "f-3", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_4, "f-4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_6, "f-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_7, "f-7", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_8, "f-8", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_9, "f-9", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_11, "f-11", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_12, "f-12", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_13, "f-13", 0, 32, 13, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_14, "f-14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_15, "f-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_16, "f-16", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_17, "f-17", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_18, "f-18", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_19, "f-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_20, "f-20", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_21, "f-21", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_22, "f-22", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_23, "f-23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_24, "f-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_26, "f-26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_27, "f-27", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_28, "f-28", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_29, "f-29", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_30, "f-30", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_31, "f-31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } } } } }, + { MEP_F_8S8A2, "f-8s8a2", 0, 32, 8, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_12S4A2, "f-12s4a2", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_17S16A2, "f-17s16a2", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24S5A2N_HI, "f-24s5a2n-hi", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24S5A2N_LO, "f-24s5a2n-lo", 0, 32, 5, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24S5A2N, "f-24s5a2n", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U5A2N_HI, "f-24u5a2n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U5A2N_LO, "f-24u5a2n-lo", 0, 32, 5, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U5A2N, "f-24u5a2n", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_2U6, "f-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_7U9, "f-7u9", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_7U9A2, "f-7u9a2", 0, 32, 9, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_7U9A4, "f-7u9a4", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_16S16, "f-16s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_2U10, "f-2u10", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_3U5, "f-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_4U8, "f-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_5U8, "f-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_5U24, "f-5u24", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_6S8, "f-6s8", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_8S8, "f-8s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_8S24, "f-8s24", 0, 32, 24, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_8S24A2, "f-8s24a2", 0, 32, 24, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_8S24A4, "f-8s24a4", 0, 32, 24, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_8S24A8, "f-8s24a8", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U8N_HI, "f-24u8n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U8N_LO, "f-24u8n-lo", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U8N, "f-24u8n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U4N_HI, "f-24u4n-hi", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U4N_LO, "f-24u4n-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_24U4N, "f-24u4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CALLNUM, "f-callnum", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } } } } }, + { MEP_F_FMAX_0_4, "f-fmax-0-4", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_4_4, "f-fmax-4-4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_8_4, "f-fmax-8-4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_12_4, "f-fmax-12-4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_16_4, "f-fmax-16-4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_20_4, "f-fmax-20-4", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_24_4, "f-fmax-24-4", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_28_1, "f-fmax-28-1", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_29_1, "f-fmax-29-1", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_30_1, "f-fmax-30-1", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_31_1, "f-fmax-31-1", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_FRD, "f-fmax-frd", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_FRN, "f-fmax-frn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_FRM, "f-fmax-frm", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { MEP_F_FMAX_RM, "f-fmax-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } +}; + +#undef A + + + +/* multi ifield declarations */ + +const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRD_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRN_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRM_MULTI_IFIELD []; + + +/* multi ifield definitions */ + +const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRD_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_28_1] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_4_4] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRN_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_29_1] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_20_4] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD MEP_F_FMAX_FRM_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_30_1] } }, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_24_4] } }, + { 0, { (const PTR) 0 } } +}; + +/* The operand table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_OPERAND_##a) +#else +#define A(a) (1 << CGEN_OPERAND_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) MEP_OPERAND_##op +#else +#define OPERAND(op) MEP_OPERAND_/**/op +#endif + +const CGEN_OPERAND mep_cgen_operand_table[] = +{ +/* pc: program counter */ + { "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* r0: register 0 */ + { "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* rn: register Rn */ + { "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* rm: register Rm */ + { "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* rl: register Rl */ + { "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* rn3: register 0-7 */ + { "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* rma: register Rm holding pointer */ + { "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } } }, +/* rnc: register Rn holding char */ + { "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CHAR, 0 } }, { { 1, 0 } } } } }, +/* rnuc: register Rn holding unsigned char */ + { "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_UCHAR, 0 } }, { { 1, 0 } } } } }, +/* rns: register Rn holding short */ + { "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_SHORT, 0 } }, { { 1, 0 } } } } }, +/* rnus: register Rn holding unsigned short */ + { "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_USHORT, 0 } }, { { 1, 0 } } } } }, +/* rnl: register Rn holding long */ + { "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* rnul: register Rn holding unsigned long */ + { "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } }, +/* rn3c: register 0-7 holding unsigned char */ + { "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CHAR, 0 } }, { { 1, 0 } } } } }, +/* rn3uc: register 0-7 holding byte */ + { "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_UCHAR, 0 } }, { { 1, 0 } } } } }, +/* rn3s: register 0-7 holding unsigned short */ + { "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_SHORT, 0 } }, { { 1, 0 } } } } }, +/* rn3us: register 0-7 holding short */ + { "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_USHORT, 0 } }, { { 1, 0 } } } } }, +/* rn3l: register 0-7 holding unsigned long */ + { "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* rn3ul: register 0-7 holding long */ + { "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } }, +/* lp: link pointer */ + { "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* sar: shift amount register */ + { "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* hi: high result */ + { "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* lo: low result */ + { "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* mb0: modulo begin register 0 */ + { "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* me0: modulo end register 0 */ + { "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* mb1: modulo begin register 1 */ + { "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* me1: modulo end register 1 */ + { "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* psw: program status word */ + { "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* epc: exception prog counter */ + { "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* exc: exception cause */ + { "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* npc: nmi program counter */ + { "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* dbg: debug register */ + { "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* depc: debug exception pc */ + { "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* opt: option register */ + { "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* r1: register 1 */ + { "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* tp: tiny data area pointer */ + { "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* sp: stack pointer */ + { "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* tpr: comment */ + { "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* spr: comment */ + { "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* csrn: control/special register */ + { "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5, + { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } }, +/* csrn-idx: control/special reg idx */ + { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5, + { 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* crn64: copro Rn (64-bit) */ + { "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } }, +/* crn: copro Rn (32-bit) */ + { "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } }, +/* crnx64: copro Rn (0-31, 64-bit) */ + { "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5, + { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } }, +/* crnx: copro Rn (0-31, 32-bit) */ + { "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5, + { 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } }, +/* ccrn: copro control reg CCRn */ + { "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6, + { 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } }, +/* cccc: copro flags */ + { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* pcrel8a2: comment */ + { "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } }, + { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } }, +/* pcrel12a2: comment */ + { "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } }, + { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } }, +/* pcrel17a2: comment */ + { "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } }, + { 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } }, +/* pcrel24a2: comment */ + { "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23, + { 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } }, + { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } }, +/* pcabs24a2: comment */ + { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23, + { 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } }, + { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } }, +/* sdisp16: comment */ + { "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* simm16: comment */ + { "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* uimm16: comment */ + { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* code16: uci/dsp code (16 bits) */ + { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* udisp2: SSARB addend (2 bits) */ + { "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* uimm2: interrupt (2 bits) */ + { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* simm6: add const (6 bits) */ + { "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* simm8: mov const (8 bits) */ + { "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } }, + { 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* addr24a4: comment */ + { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22, + { 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } }, +/* code24: coprocessor code */ + { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24, + { 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* callnum: system call number */ + { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4, + { 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* uimm3: bit immediate (3 bits) */ + { "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* uimm4: bCC const (4 bits) */ + { "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* uimm5: bit/shift val (5 bits) */ + { "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* udisp7: comment */ + { "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* udisp7a2: comment */ + { "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } } }, +/* udisp7a4: comment */ + { "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } }, +/* uimm7a4: comment */ + { "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } }, +/* uimm24: immediate (24 bits) */ + { "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24, + { 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* cimm4: cache immed'te (4 bits) */ + { "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* cimm5: clip immediate (5 bits) */ + { "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* cdisp8: copro addend (8 bits) */ + { "cdisp8", MEP_OPERAND_CDISP8, HW_H_SINT, 24, 8, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* cdisp8a2: comment */ + { "cdisp8a2", MEP_OPERAND_CDISP8A2, HW_H_SINT, 24, 7, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A2] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } } }, +/* cdisp8a4: comment */ + { "cdisp8a4", MEP_OPERAND_CDISP8A4, HW_H_SINT, 24, 6, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A4] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } }, +/* cdisp8a8: comment */ + { "cdisp8a8", MEP_OPERAND_CDISP8A8, HW_H_SINT, 24, 5, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S24A8] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 8, 0 } } } } }, +/* zero: Zero operand */ + { "zero", MEP_OPERAND_ZERO, HW_H_SINT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* cp_flag: branch condition register */ + { "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfe" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* fmax-FRd: FRd */ + { "fmax-FRd", MEP_OPERAND_FMAX_FRD, HW_H_CR, 4, 5, + { 2, { (const PTR) &MEP_F_FMAX_FRD_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_FLOAT, 0 } }, { { 1, 0 } } } } }, +/* fmax-FRn: FRn */ + { "fmax-FRn", MEP_OPERAND_FMAX_FRN, HW_H_CR, 20, 5, + { 2, { (const PTR) &MEP_F_FMAX_FRN_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_FLOAT, 0 } }, { { 1, 0 } } } } }, +/* fmax-FRm: FRm */ + { "fmax-FRm", MEP_OPERAND_FMAX_FRM, HW_H_CR, 24, 5, + { 2, { (const PTR) &MEP_F_FMAX_FRM_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_FLOAT, 0 } }, { { 1, 0 } } } } }, +/* fmax-FRd-int: FRd as an integer */ + { "fmax-FRd-int", MEP_OPERAND_FMAX_FRD_INT, HW_H_CR, 4, 5, + { 2, { (const PTR) &MEP_F_FMAX_FRD_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_INT, 0 } }, { { 1, 0 } } } } }, +/* fmax-FRn-int: FRn as an integer */ + { "fmax-FRn-int", MEP_OPERAND_FMAX_FRN_INT, HW_H_CR, 20, 5, + { 2, { (const PTR) &MEP_F_FMAX_FRN_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_FMAX_INT, 0 } }, { { 1, 0 } } } } }, +/* fmax-CCRn: CCRn */ + { "fmax-CCRn", MEP_OPERAND_FMAX_CCRN, HW_H_CCR, 4, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_4_4] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } }, +/* fmax-CIRR: CIRR */ + { "fmax-CIRR", MEP_OPERAND_FMAX_CIRR, HW_H_CCR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* fmax-CBCR: CBCR */ + { "fmax-CBCR", MEP_OPERAND_FMAX_CBCR, HW_H_CCR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* fmax-CERR: CERR */ + { "fmax-CERR", MEP_OPERAND_FMAX_CERR, HW_H_CCR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* fmax-Rm: Rm */ + { "fmax-Rm", MEP_OPERAND_FMAX_RM, HW_H_GPR, 8, 4, + { 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_FMAX_RM] } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* fmax-Compare-i-p: flag */ + { "fmax-Compare-i-p", MEP_OPERAND_FMAX_COMPARE_I_P, HW_H_FMAX_COMPARE_I_P, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } }, +/* sentinel */ + { 0, 0, 0, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } } +}; + +#undef A + + +/* The instruction table. */ + +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif + +static const CGEN_IBASE mep_cgen_insn_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } }, +/* sb $rnc,($rma) */ + { + MEP_INSN_SB, "sb", "sb", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sh $rns,($rma) */ + { + MEP_INSN_SH, "sh", "sh", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sw $rnl,($rma) */ + { + MEP_INSN_SW, "sw", "sw", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lb $rnc,($rma) */ + { + MEP_INSN_LB, "lb", "lb", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lh $rns,($rma) */ + { + MEP_INSN_LH, "lh", "lh", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lw $rnl,($rma) */ + { + MEP_INSN_LW, "lw", "lw", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lbu $rnuc,($rma) */ + { + MEP_INSN_LBU, "lbu", "lbu", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lhu $rnus,($rma) */ + { + MEP_INSN_LHU, "lhu", "lhu", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sw $rnl,$udisp7a4($spr) */ + { + MEP_INSN_SW_SP, "sw-sp", "sw", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lw $rnl,$udisp7a4($spr) */ + { + MEP_INSN_LW_SP, "lw-sp", "lw", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sb $rn3c,$udisp7($tpr) */ + { + MEP_INSN_SB_TP, "sb-tp", "sb", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sh $rn3s,$udisp7a2($tpr) */ + { + MEP_INSN_SH_TP, "sh-tp", "sh", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sw $rn3l,$udisp7a4($tpr) */ + { + MEP_INSN_SW_TP, "sw-tp", "sw", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lb $rn3c,$udisp7($tpr) */ + { + MEP_INSN_LB_TP, "lb-tp", "lb", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lh $rn3s,$udisp7a2($tpr) */ + { + MEP_INSN_LH_TP, "lh-tp", "lh", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lw $rn3l,$udisp7a4($tpr) */ + { + MEP_INSN_LW_TP, "lw-tp", "lw", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lbu $rn3uc,$udisp7($tpr) */ + { + MEP_INSN_LBU_TP, "lbu-tp", "lbu", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lhu $rn3us,$udisp7a2($tpr) */ + { + MEP_INSN_LHU_TP, "lhu-tp", "lhu", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sb $rnc,$sdisp16($rma) */ + { + MEP_INSN_SB16, "sb16", "sb", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sh $rns,$sdisp16($rma) */ + { + MEP_INSN_SH16, "sh16", "sh", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sw $rnl,$sdisp16($rma) */ + { + MEP_INSN_SW16, "sw16", "sw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lb $rnc,$sdisp16($rma) */ + { + MEP_INSN_LB16, "lb16", "lb", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lh $rns,$sdisp16($rma) */ + { + MEP_INSN_LH16, "lh16", "lh", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lw $rnl,$sdisp16($rma) */ + { + MEP_INSN_LW16, "lw16", "lw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lbu $rnuc,$sdisp16($rma) */ + { + MEP_INSN_LBU16, "lbu16", "lbu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lhu $rnus,$sdisp16($rma) */ + { + MEP_INSN_LHU16, "lhu16", "lhu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sw $rnl,($addr24a4) */ + { + MEP_INSN_SW24, "sw24", "sw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lw $rnl,($addr24a4) */ + { + MEP_INSN_LW24, "lw24", "lw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* extb $rn */ + { + MEP_INSN_EXTB, "extb", "extb", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* exth $rn */ + { + MEP_INSN_EXTH, "exth", "exth", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* extub $rn */ + { + MEP_INSN_EXTUB, "extub", "extub", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* extuh $rn */ + { + MEP_INSN_EXTUH, "extuh", "extuh", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ssarb $udisp2($rm) */ + { + MEP_INSN_SSARB, "ssarb", "ssarb", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* mov $rn,$rm */ + { + MEP_INSN_MOV, "mov", "mov", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* mov $rn,$simm8 */ + { + MEP_INSN_MOVI8, "movi8", "mov", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* mov $rn,$simm16 */ + { + MEP_INSN_MOVI16, "movi16", "mov", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* movu $rn3,$uimm24 */ + { + MEP_INSN_MOVU24, "movu24", "movu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* movu $rn,$uimm16 */ + { + MEP_INSN_MOVU16, "movu16", "movu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* movh $rn,$uimm16 */ + { + MEP_INSN_MOVH, "movh", "movh", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* add3 $rl,$rn,$rm */ + { + MEP_INSN_ADD3, "add3", "add3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* add $rn,$simm6 */ + { + MEP_INSN_ADD, "add", "add", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* add3 $rn,$spr,$uimm7a4 */ + { + MEP_INSN_ADD3I, "add3i", "add3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* advck3 \$0,$rn,$rm */ + { + MEP_INSN_ADVCK3, "advck3", "advck3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sub $rn,$rm */ + { + MEP_INSN_SUB, "sub", "sub", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sbvck3 \$0,$rn,$rm */ + { + MEP_INSN_SBVCK3, "sbvck3", "sbvck3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* neg $rn,$rm */ + { + MEP_INSN_NEG, "neg", "neg", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* slt3 \$0,$rn,$rm */ + { + MEP_INSN_SLT3, "slt3", "slt3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sltu3 \$0,$rn,$rm */ + { + MEP_INSN_SLTU3, "sltu3", "sltu3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* slt3 \$0,$rn,$uimm5 */ + { + MEP_INSN_SLT3I, "slt3i", "slt3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sltu3 \$0,$rn,$uimm5 */ + { + MEP_INSN_SLTU3I, "sltu3i", "sltu3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sl1ad3 \$0,$rn,$rm */ + { + MEP_INSN_SL1AD3, "sl1ad3", "sl1ad3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sl2ad3 \$0,$rn,$rm */ + { + MEP_INSN_SL2AD3, "sl2ad3", "sl2ad3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* add3 $rn,$rm,$simm16 */ + { + MEP_INSN_ADD3X, "add3x", "add3", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* slt3 $rn,$rm,$simm16 */ + { + MEP_INSN_SLT3X, "slt3x", "slt3", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sltu3 $rn,$rm,$uimm16 */ + { + MEP_INSN_SLTU3X, "sltu3x", "sltu3", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* or $rn,$rm */ + { + MEP_INSN_OR, "or", "or", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* and $rn,$rm */ + { + MEP_INSN_AND, "and", "and", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* xor $rn,$rm */ + { + MEP_INSN_XOR, "xor", "xor", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* nor $rn,$rm */ + { + MEP_INSN_NOR, "nor", "nor", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* or3 $rn,$rm,$uimm16 */ + { + MEP_INSN_OR3, "or3", "or3", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* and3 $rn,$rm,$uimm16 */ + { + MEP_INSN_AND3, "and3", "and3", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* xor3 $rn,$rm,$uimm16 */ + { + MEP_INSN_XOR3, "xor3", "xor3", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sra $rn,$rm */ + { + MEP_INSN_SRA, "sra", "sra", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* srl $rn,$rm */ + { + MEP_INSN_SRL, "srl", "srl", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sll $rn,$rm */ + { + MEP_INSN_SLL, "sll", "sll", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sra $rn,$uimm5 */ + { + MEP_INSN_SRAI, "srai", "sra", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* srl $rn,$uimm5 */ + { + MEP_INSN_SRLI, "srli", "srl", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sll $rn,$uimm5 */ + { + MEP_INSN_SLLI, "slli", "sll", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sll3 \$0,$rn,$uimm5 */ + { + MEP_INSN_SLL3, "sll3", "sll3", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fsft $rn,$rm */ + { + MEP_INSN_FSFT, "fsft", "fsft", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bra $pcrel12a2 */ + { + MEP_INSN_BRA, "bra", "bra", 16, + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* beqz $rn,$pcrel8a2 */ + { + MEP_INSN_BEQZ, "beqz", "beqz", 16, + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bnez $rn,$pcrel8a2 */ + { + MEP_INSN_BNEZ, "bnez", "bnez", 16, + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* beqi $rn,$uimm4,$pcrel17a2 */ + { + MEP_INSN_BEQI, "beqi", "beqi", 32, + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bnei $rn,$uimm4,$pcrel17a2 */ + { + MEP_INSN_BNEI, "bnei", "bnei", 32, + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* blti $rn,$uimm4,$pcrel17a2 */ + { + MEP_INSN_BLTI, "blti", "blti", 32, + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bgei $rn,$uimm4,$pcrel17a2 */ + { + MEP_INSN_BGEI, "bgei", "bgei", 32, + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* beq $rn,$rm,$pcrel17a2 */ + { + MEP_INSN_BEQ, "beq", "beq", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bne $rn,$rm,$pcrel17a2 */ + { + MEP_INSN_BNE, "bne", "bne", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bsr $pcrel12a2 */ + { + MEP_INSN_BSR12, "bsr12", "bsr", 16, + { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bsr $pcrel24a2 */ + { + MEP_INSN_BSR24, "bsr24", "bsr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* jmp $rm */ + { + MEP_INSN_JMP, "jmp", "jmp", 16, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* jmp $pcabs24a2 */ + { + MEP_INSN_JMP24, "jmp24", "jmp", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* jsr $rm */ + { + MEP_INSN_JSR, "jsr", "jsr", 16, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ret */ + { + MEP_INSN_RET, "ret", "ret", 16, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* repeat $rn,$pcrel17a2 */ + { + MEP_INSN_REPEAT, "repeat", "repeat", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* erepeat $pcrel17a2 */ + { + MEP_INSN_EREPEAT, "erepeat", "erepeat", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* stc $rn,\$lp */ + { + MEP_INSN_STC_LP, "stc_lp", "stc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* stc $rn,\$hi */ + { + MEP_INSN_STC_HI, "stc_hi", "stc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* stc $rn,\$lo */ + { + MEP_INSN_STC_LO, "stc_lo", "stc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* stc $rn,$csrn */ + { + MEP_INSN_STC, "stc", "stc", 16, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ldc $rn,\$lp */ + { + MEP_INSN_LDC_LP, "ldc_lp", "ldc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ldc $rn,\$hi */ + { + MEP_INSN_LDC_HI, "ldc_hi", "ldc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ldc $rn,\$lo */ + { + MEP_INSN_LDC_LO, "ldc_lo", "ldc", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ldc $rn,$csrn */ + { + MEP_INSN_LDC, "ldc", "ldc", 16, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* di */ + { + MEP_INSN_DI, "di", "di", 16, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ei */ + { + MEP_INSN_EI, "ei", "ei", 16, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* reti */ + { + MEP_INSN_RETI, "reti", "reti", 16, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* halt */ + { + MEP_INSN_HALT, "halt", "halt", 16, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sleep */ + { + MEP_INSN_SLEEP, "sleep", "sleep", 16, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* swi $uimm2 */ + { + MEP_INSN_SWI, "swi", "swi", 16, + { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* break */ + { + MEP_INSN_BREAK, "break", "break", 16, + { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* syncm */ + { + MEP_INSN_SYNCM, "syncm", "syncm", 16, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* stcb $rn,$uimm16 */ + { + MEP_INSN_STCB, "stcb", "stcb", 32, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ldcb $rn,$uimm16 */ + { + MEP_INSN_LDCB, "ldcb", "ldcb", 32, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bsetm ($rma),$uimm3 */ + { + MEP_INSN_BSETM, "bsetm", "bsetm", 16, + { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bclrm ($rma),$uimm3 */ + { + MEP_INSN_BCLRM, "bclrm", "bclrm", 16, + { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bnotm ($rma),$uimm3 */ + { + MEP_INSN_BNOTM, "bnotm", "bnotm", 16, + { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* btstm \$0,($rma),$uimm3 */ + { + MEP_INSN_BTSTM, "btstm", "btstm", 16, + { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* tas $rn,($rma) */ + { + MEP_INSN_TAS, "tas", "tas", 16, + { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* cache $cimm4,($rma) */ + { + MEP_INSN_CACHE, "cache", "cache", 16, + { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* mul $rn,$rm */ + { + MEP_INSN_MUL, "mul", "mul", 16, + { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* mulu $rn,$rm */ + { + MEP_INSN_MULU, "mulu", "mulu", 16, + { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* mulr $rn,$rm */ + { + MEP_INSN_MULR, "mulr", "mulr", 16, + { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* mulru $rn,$rm */ + { + MEP_INSN_MULRU, "mulru", "mulru", 16, + { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* madd $rn,$rm */ + { + MEP_INSN_MADD, "madd", "madd", 32, + { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* maddu $rn,$rm */ + { + MEP_INSN_MADDU, "maddu", "maddu", 32, + { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* maddr $rn,$rm */ + { + MEP_INSN_MADDR, "maddr", "maddr", 32, + { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* maddru $rn,$rm */ + { + MEP_INSN_MADDRU, "maddru", "maddru", 32, + { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* div $rn,$rm */ + { + MEP_INSN_DIV, "div", "div", 16, + { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* divu $rn,$rm */ + { + MEP_INSN_DIVU, "divu", "divu", 16, + { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* dret */ + { + MEP_INSN_DRET, "dret", "dret", 16, + { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* dbreak */ + { + MEP_INSN_DBREAK, "dbreak", "dbreak", 16, + { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ldz $rn,$rm */ + { + MEP_INSN_LDZ, "ldz", "ldz", 32, + { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* abs $rn,$rm */ + { + MEP_INSN_ABS, "abs", "abs", 32, + { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ave $rn,$rm */ + { + MEP_INSN_AVE, "ave", "ave", 32, + { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* min $rn,$rm */ + { + MEP_INSN_MIN, "min", "min", 32, + { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* max $rn,$rm */ + { + MEP_INSN_MAX, "max", "max", 32, + { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* minu $rn,$rm */ + { + MEP_INSN_MINU, "minu", "minu", 32, + { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* maxu $rn,$rm */ + { + MEP_INSN_MAXU, "maxu", "maxu", 32, + { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* clip $rn,$cimm5 */ + { + MEP_INSN_CLIP, "clip", "clip", 32, + { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* clipu $rn,$cimm5 */ + { + MEP_INSN_CLIPU, "clipu", "clipu", 32, + { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sadd $rn,$rm */ + { + MEP_INSN_SADD, "sadd", "sadd", 32, + { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ssub $rn,$rm */ + { + MEP_INSN_SSUB, "ssub", "ssub", 32, + { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* saddu $rn,$rm */ + { + MEP_INSN_SADDU, "saddu", "saddu", 32, + { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ssubu $rn,$rm */ + { + MEP_INSN_SSUBU, "ssubu", "ssubu", 32, + { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* swcp $crn,($rma) */ + { + MEP_INSN_SWCP, "swcp", "swcp", 16, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lwcp $crn,($rma) */ + { + MEP_INSN_LWCP, "lwcp", "lwcp", 16, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* smcp $crn64,($rma) */ + { + MEP_INSN_SMCP, "smcp", "smcp", 16, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lmcp $crn64,($rma) */ + { + MEP_INSN_LMCP, "lmcp", "lmcp", 16, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* swcpi $crn,($rma+) */ + { + MEP_INSN_SWCPI, "swcpi", "swcpi", 16, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lwcpi $crn,($rma+) */ + { + MEP_INSN_LWCPI, "lwcpi", "lwcpi", 16, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* smcpi $crn64,($rma+) */ + { + MEP_INSN_SMCPI, "smcpi", "smcpi", 16, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lmcpi $crn64,($rma+) */ + { + MEP_INSN_LMCPI, "lmcpi", "lmcpi", 16, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* swcp $crn,$sdisp16($rma) */ + { + MEP_INSN_SWCP16, "swcp16", "swcp", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lwcp $crn,$sdisp16($rma) */ + { + MEP_INSN_LWCP16, "lwcp16", "lwcp", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* smcp $crn64,$sdisp16($rma) */ + { + MEP_INSN_SMCP16, "smcp16", "smcp", 32, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lmcp $crn64,$sdisp16($rma) */ + { + MEP_INSN_LMCP16, "lmcp16", "lmcp", 32, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sbcpa $crn,($rma+),$cdisp8 */ + { + MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lbcpa $crn,($rma+),$cdisp8 */ + { + MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* shcpa $crn,($rma+),$cdisp8a2 */ + { + MEP_INSN_SHCPA, "shcpa", "shcpa", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lhcpa $crn,($rma+),$cdisp8a2 */ + { + MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* swcpa $crn,($rma+),$cdisp8a4 */ + { + MEP_INSN_SWCPA, "swcpa", "swcpa", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lwcpa $crn,($rma+),$cdisp8a4 */ + { + MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* smcpa $crn64,($rma+),$cdisp8a8 */ + { + MEP_INSN_SMCPA, "smcpa", "smcpa", 32, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lmcpa $crn64,($rma+),$cdisp8a8 */ + { + MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sbcpm0 $crn,($rma+),$cdisp8 */ + { + MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lbcpm0 $crn,($rma+),$cdisp8 */ + { + MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* shcpm0 $crn,($rma+),$cdisp8a2 */ + { + MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lhcpm0 $crn,($rma+),$cdisp8a2 */ + { + MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* swcpm0 $crn,($rma+),$cdisp8a4 */ + { + MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lwcpm0 $crn,($rma+),$cdisp8a4 */ + { + MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* smcpm0 $crn64,($rma+),$cdisp8a8 */ + { + MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lmcpm0 $crn64,($rma+),$cdisp8a8 */ + { + MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sbcpm1 $crn,($rma+),$cdisp8 */ + { + MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lbcpm1 $crn,($rma+),$cdisp8 */ + { + MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* shcpm1 $crn,($rma+),$cdisp8a2 */ + { + MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lhcpm1 $crn,($rma+),$cdisp8a2 */ + { + MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* swcpm1 $crn,($rma+),$cdisp8a4 */ + { + MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lwcpm1 $crn,($rma+),$cdisp8a4 */ + { + MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* smcpm1 $crn64,($rma+),$cdisp8a8 */ + { + MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lmcpm1 $crn64,($rma+),$cdisp8a8 */ + { + MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32, + { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bcpeq $cccc,$pcrel17a2 */ + { + MEP_INSN_BCPEQ, "bcpeq", "bcpeq", 32, + { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bcpne $cccc,$pcrel17a2 */ + { + MEP_INSN_BCPNE, "bcpne", "bcpne", 32, + { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bcpat $cccc,$pcrel17a2 */ + { + MEP_INSN_BCPAT, "bcpat", "bcpat", 32, + { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bcpaf $cccc,$pcrel17a2 */ + { + MEP_INSN_BCPAF, "bcpaf", "bcpaf", 32, + { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* synccp */ + { + MEP_INSN_SYNCCP, "synccp", "synccp", 16, + { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* jsrv $rm */ + { + MEP_INSN_JSRV, "jsrv", "jsrv", 16, + { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* bsrv $pcrel24a2 */ + { + MEP_INSN_BSRV, "bsrv", "bsrv", 32, + { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --unused-- */ + { + MEP_INSN_SIM_SYSCALL, "sim-syscall", "--unused--", 16, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_0, "ri-0", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_1, "ri-1", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_2, "ri-2", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_3, "ri-3", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_4, "ri-4", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_5, "ri-5", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_6, "ri-6", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_7, "ri-7", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_8, "ri-8", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_9, "ri-9", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_10, "ri-10", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_11, "ri-11", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_12, "ri-12", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_13, "ri-13", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_14, "ri-14", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_15, "ri-15", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_17, "ri-17", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_20, "ri-20", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_21, "ri-21", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_22, "ri-22", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_23, "ri-23", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_24, "ri-24", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_25, "ri-25", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_26, "ri-26", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_16, "ri-16", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_18, "ri-18", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* --reserved-- */ + { + MEP_INSN_RI_19, "ri-19", "--reserved--", 16, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fadds ${fmax-FRd},${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FADDS, "fadds", "fadds", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fsubs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FSUBS, "fsubs", "fsubs", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fmuls ${fmax-FRd},${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FMULS, "fmuls", "fmuls", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fdivs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FDIVS, "fdivs", "fdivs", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fsqrts ${fmax-FRd},${fmax-FRn} */ + { + MEP_INSN_FSQRTS, "fsqrts", "fsqrts", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fabss ${fmax-FRd},${fmax-FRn} */ + { + MEP_INSN_FABSS, "fabss", "fabss", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fnegs ${fmax-FRd},${fmax-FRn} */ + { + MEP_INSN_FNEGS, "fnegs", "fnegs", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fmovs ${fmax-FRd},${fmax-FRn} */ + { + MEP_INSN_FMOVS, "fmovs", "fmovs", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* froundws ${fmax-FRd-int},${fmax-FRn} */ + { + MEP_INSN_FROUNDWS, "froundws", "froundws", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ftruncws ${fmax-FRd-int},${fmax-FRn} */ + { + MEP_INSN_FTRUNCWS, "ftruncws", "ftruncws", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fceilws ${fmax-FRd-int},${fmax-FRn} */ + { + MEP_INSN_FCEILWS, "fceilws", "fceilws", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* ffloorws ${fmax-FRd-int},${fmax-FRn} */ + { + MEP_INSN_FFLOORWS, "ffloorws", "ffloorws", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcvtws ${fmax-FRd-int},${fmax-FRn} */ + { + MEP_INSN_FCVTWS, "fcvtws", "fcvtws", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcvtsw ${fmax-FRd},${fmax-FRn-int} */ + { + MEP_INSN_FCVTSW, "fcvtsw", "fcvtsw", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpfs ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPFS, "fcmpfs", "fcmpfs", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpus ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPUS, "fcmpus", "fcmpus", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpes ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPES, "fcmpes", "fcmpes", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpues ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPUES, "fcmpues", "fcmpues", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpls ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPLS, "fcmpls", "fcmpls", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpuls ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPULS, "fcmpuls", "fcmpuls", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmples ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPLES, "fcmples", "fcmples", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpules ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPULES, "fcmpules", "fcmpules", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpfis ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPFIS, "fcmpfis", "fcmpfis", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpuis ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPUIS, "fcmpuis", "fcmpuis", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpeis ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPEIS, "fcmpeis", "fcmpeis", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpueis ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPUEIS, "fcmpueis", "fcmpueis", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmplis ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPLIS, "fcmplis", "fcmplis", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpulis ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPULIS, "fcmpulis", "fcmpulis", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpleis ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPLEIS, "fcmpleis", "fcmpleis", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* fcmpuleis ${fmax-FRn},${fmax-FRm} */ + { + MEP_INSN_FCMPULEIS, "fcmpuleis", "fcmpuleis", 32, + { 0|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* cmov ${fmax-FRd-int},${fmax-Rm} */ + { + MEP_INSN_CMOV_FRN_RM, "cmov-frn-rm", "cmov", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* cmov ${fmax-Rm},${fmax-FRd-int} */ + { + MEP_INSN_CMOV_RM_FRN, "cmov-rm-frn", "cmov", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* cmovc ${fmax-CCRn},${fmax-Rm} */ + { + MEP_INSN_CMOVC_CCRN_RM, "cmovc-ccrn-rm", "cmovc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* cmovc ${fmax-Rm},${fmax-CCRn} */ + { + MEP_INSN_CMOVC_RM_CCRN, "cmovc-rm-ccrn", "cmovc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +}; + +#undef OP +#undef A + +/* Initialize anything needed to be done once, before any cpu_open call. */ + +static void +init_tables (void) +{ +} + +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void mep_cgen_rebuild_tables (CGEN_CPU_TABLE *); + +/* Subroutine of mep_cgen_cpu_open to look up a mach via its bfd name. */ + +static const CGEN_MACH * +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) +{ + while (table->name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of mep_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & mep_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of mep_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & mep_cgen_ifld_table[0]; +} + +/* Subroutine of mep_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & mep_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of mep_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & mep_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of mep_cgen_cpu_open to rebuild the tables. */ + +static void +mep_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & mep_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & mep_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "mep_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +mep_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (mep_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "mep_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "mep_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = mep_cgen_rebuild_tables; + mep_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to mep_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +mep_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +mep_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/contrib/binutils/opcodes/mep-desc.h b/contrib/binutils/opcodes/mep-desc.h new file mode 100644 index 0000000..606d347 --- /dev/null +++ b/contrib/binutils/opcodes/mep-desc.h @@ -0,0 +1,342 @@ +/* CPU data header for mep. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef MEP_CPU_H +#define MEP_CPU_H + +#include "opcode/cgen-bitset.h" + +#define CGEN_ARCH mep + +/* Given symbol S, return mep_cgen_<S>. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) mep##_cgen_##s +#else +#define CGEN_SYM(s) mep/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_MEPF + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 11 + +/* Enums. */ + +/* Enum declaration for major opcodes. */ +typedef enum major { + MAJ_0, MAJ_1, MAJ_2, MAJ_3 + , MAJ_4, MAJ_5, MAJ_6, MAJ_7 + , MAJ_8, MAJ_9, MAJ_10, MAJ_11 + , MAJ_12, MAJ_13, MAJ_14, MAJ_15 +} MAJOR; + +/* Enum declaration for condition opcode enum. */ +typedef enum fmax_cond { + FMAX_F, FMAX_U, FMAX_E, FMAX_UE + , FMAX_L, FMAX_UL, FMAX_LE, FMAX_ULE + , FMAX_FI, FMAX_UI, FMAX_EI, FMAX_UEI + , FMAX_LI, FMAX_ULI, FMAX_LEI, FMAX_ULEI +} FMAX_COND; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2, ISA_EXT_COP2_16 + , ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for datatype to use for C intrinsics mapping. */ +typedef enum cdata_attr { + CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT + , CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT + , CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT +} CDATA_ATTR; + +/* Enum declaration for . */ +typedef enum config_attr { + CONFIG_NONE, CONFIG_SIMPLE, CONFIG_FMAX +} CONFIG_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS ((int) ISA_MAX) +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for mep ifield types. */ +typedef enum ifield_type { + MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN + , MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2 + , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN + , MEP_F_CSRN_HI, MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI + , MEP_F_CRNX_LO, MEP_F_CRNX, MEP_F_0, MEP_F_1 + , MEP_F_2, MEP_F_3, MEP_F_4, MEP_F_5 + , MEP_F_6, MEP_F_7, MEP_F_8, MEP_F_9 + , MEP_F_10, MEP_F_11, MEP_F_12, MEP_F_13 + , MEP_F_14, MEP_F_15, MEP_F_16, MEP_F_17 + , MEP_F_18, MEP_F_19, MEP_F_20, MEP_F_21 + , MEP_F_22, MEP_F_23, MEP_F_24, MEP_F_25 + , MEP_F_26, MEP_F_27, MEP_F_28, MEP_F_29 + , MEP_F_30, MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2 + , MEP_F_17S16A2, MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N + , MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6 + , MEP_F_7U9, MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16 + , MEP_F_2U10, MEP_F_3U5, MEP_F_4U8, MEP_F_5U8 + , MEP_F_5U24, MEP_F_6S8, MEP_F_8S8, MEP_F_16U16 + , MEP_F_12U16, MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2 + , MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO + , MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N + , MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM + , MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_FMAX_0_4 + , MEP_F_FMAX_4_4, MEP_F_FMAX_8_4, MEP_F_FMAX_12_4, MEP_F_FMAX_16_4 + , MEP_F_FMAX_20_4, MEP_F_FMAX_24_4, MEP_F_FMAX_28_1, MEP_F_FMAX_29_1 + , MEP_F_FMAX_30_1, MEP_F_FMAX_31_1, MEP_F_FMAX_FRD, MEP_F_FMAX_FRN + , MEP_F_FMAX_FRM, MEP_F_FMAX_RM, MEP_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) MEP_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH + , CGEN_HW_ISA, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) +#define CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_IS_FLOAT)) != 0) + +/* Enum declaration for mep hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR + , HW_H_CR64, HW_H_CR, HW_H_CCR, HW_H_CR_FMAX + , HW_H_CCR_FMAX, HW_H_FMAX_COMPARE_I_P, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH + , CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA, CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_OPERAND_CDATA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_CDATA-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_ALIGN_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ALIGN-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW)) != 0) + +/* Enum declaration for mep operand types. */ +typedef enum cgen_operand_type { + MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM + , MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC + , MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL + , MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S + , MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP + , MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0 + , MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW + , MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG + , MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP + , MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN + , MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64 + , MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2 + , MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2 + , MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16 + , MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8 + , MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3 + , MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2 + , MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4 + , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4 + , MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD + , MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT + , MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR + , MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 90 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN + , CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN, CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN + , CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN + , CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN + , CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP + , CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE + , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA + , CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) +#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_BIT_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MUL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MUL_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DIV_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DEBUG_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_LDZ_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_ABS_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_ABS_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_AVE_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_AVE_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MINMAX_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CLIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_SAT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_SAT_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_UCI_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_UCI_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DSP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DSP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP64_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_OPTIONAL_VLIW64_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_VLIW64)) != 0) +#define CGEN_ATTR_CGEN_INSN_MAY_TRAP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MAY_TRAP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW_ALONE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_ALONE)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW_NO_CORE_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_CORE_NOP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW_NO_COP_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_COP_NOP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW64_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW64_NO_MATCHING_NOP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VLIW32_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW32_NO_MATCHING_NOP)) != 0) +#define CGEN_ATTR_CGEN_INSN_VOLATILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VOLATILE)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld mep_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD mep_cgen_opval_h_gpr; +extern CGEN_KEYWORD mep_cgen_opval_h_csr; +extern CGEN_KEYWORD mep_cgen_opval_h_cr64; +extern CGEN_KEYWORD mep_cgen_opval_h_cr; +extern CGEN_KEYWORD mep_cgen_opval_h_ccr; +extern CGEN_KEYWORD mep_cgen_opval_h_cr_fmax; +extern CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax; + +extern const CGEN_HW_ENTRY mep_cgen_hw_table[]; + + + +#endif /* MEP_CPU_H */ diff --git a/contrib/binutils/opcodes/mep-dis.c b/contrib/binutils/opcodes/mep-dis.c new file mode 100644 index 0000000..769a80a --- /dev/null +++ b/contrib/binutils/opcodes/mep-dis.c @@ -0,0 +1,1205 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 + Free Software Foundation, Inc. + + This file is part of the GNU Binutils and GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ + +#include "elf/mep.h" +#include "elf-bfd.h" + +#define CGEN_VALIDATE_INSN_SUPPORTED + +static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); +static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); + +static void +print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, + CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, + unsigned int flags ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$tp"); +} + +static void +print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, + CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, + unsigned int flags ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$sp"); +} + +/* begin-cop-ip-print-handlers */ +static void +print_fmax_cr (CGEN_CPU_DESC cd, + void *dis_info, + CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, + long value, + unsigned int attrs) +{ + print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_fmax, value, attrs); +} +static void +print_fmax_ccr (CGEN_CPU_DESC cd, + void *dis_info, + CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, + long value, + unsigned int attrs) +{ + print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_fmax, value, attrs); +} +/* end-cop-ip-print-handlers */ + +/************************************************************\ +*********************** Experimental ************************* +\************************************************************/ + +#undef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN mep_print_insn + +static int +mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, + bfd_byte *buf, int corelength, int copro1length, + int copro2length ATTRIBUTE_UNUSED) +{ + int i; + int status = 0; + /* char insnbuf[CGEN_MAX_INSN_SIZE]; */ + bfd_byte insnbuf[64]; + + /* If corelength > 0 then there is a core insn present. It + will be at the beginning of the buffer. After printing + the core insn, we need to print the + on the next line. */ + if (corelength > 0) + { + int my_status = 0; + + for (i = 0; i < corelength; i++ ) + insnbuf[i] = buf[i]; + cd->isas = & MEP_CORE_ISA; + + my_status = print_insn (cd, pc, info, insnbuf, corelength); + if (my_status != corelength) + { + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + my_status = corelength; + } + status += my_status; + + /* Print the + to indicate that the following copro insn is */ + /* part of a vliw group. */ + if (copro1length > 0) + (*info->fprintf_func) (info->stream, " + "); + } + + /* Now all that is left to be processed is the coprocessor insns + In vliw mode, there will always be one. Its positioning will + be from byte corelength to byte corelength+copro1length -1. + No need to check for existence. Also, the first vliw insn, + will, as spec'd, always be at least as long as the core insn + so we don't need to flush the buffer. */ + if (copro1length > 0) + { + int my_status = 0; + + for (i = corelength; i < corelength + copro1length; i++ ) + insnbuf[i - corelength] = buf[i]; + + switch (copro1length) + { + case 0: + break; + case 2: + cd->isas = & MEP_COP16_ISA; + break; + case 4: + cd->isas = & MEP_COP32_ISA; + break; + case 6: + cd->isas = & MEP_COP48_ISA; + break; + case 8: + cd->isas = & MEP_COP64_ISA; + break; + default: + /* Shouldn't be anything but 16,32,48,64. */ + break; + } + + my_status = print_insn (cd, pc, info, insnbuf, copro1length); + + if (my_status != copro1length) + { + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + my_status = copro1length; + } + status += my_status; + } + +#if 0 + /* Now we need to process the second copro insn if it exists. We + have no guarantee that the second copro insn will be longer + than the first, so we have to flush the buffer if we are have + a second copro insn to process. If present, this insn will + be in the position from byte corelength+copro1length to byte + corelength+copro1length+copro2length-1 (which better equal 8 + or else we're in big trouble. */ + if (copro2length > 0) + { + int my_status = 0; + + for (i = 0; i < 64 ; i++) + insnbuf[i] = 0; + + for (i = corelength + copro1length; i < 64; i++) + insnbuf[i - (corelength + copro1length)] = buf[i]; + + switch (copro2length) + { + case 2: + cd->isas = 1 << ISA_EXT_COP1_16; + break; + case 4: + cd->isas = 1 << ISA_EXT_COP1_32; + break; + case 6: + cd->isas = 1 << ISA_EXT_COP1_48; + break; + case 8: + cd->isas = 1 << ISA_EXT_COP1_64; + break; + default: + /* Shouldn't be anything but 16,32,48,64. */ + break; + } + + my_status = print_insn (cd, pc, info, insnbuf, copro2length); + + if (my_status != copro2length) + { + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + my_status = copro2length; + } + + status += my_status; + } +#endif + + /* Status should now be the number of bytes that were printed + which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */ + + if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8))) + return -1; + else + return status; +} + +/* The two functions mep_examine_vliw[32,64]_insns are used find out + which vliw combinaion (16 bit core with 48 bit copro, 32 bit core + with 32 bit copro, etc.) is present. Later on, when internally + parallel coprocessors are handled, only these functions should + need to be changed. + + At this time only the following combinations are supported: + + VLIW32 Mode: + 16 bit core insn (core) and 16 bit coprocessor insn (cop1) + 32 bit core insn (core) + 32 bit coprocessor insn (cop1) + Note: As of this time, I do not believe we have enough information + to distinguish a 32 bit core insn from a 32 bit cop insn. Also, + no 16 bit coprocessor insns have been specified. + + VLIW64 Mode: + 16 bit core insn (core) and 48 bit coprocessor insn (cop1) + 32 bit core insn (core) and 32 bit coprocessor insn (cop1) + 64 bit coprocessor insn (cop1) + + The framework for an internally parallel coprocessor is also + present (2nd coprocessor insn is cop2), but at this time it + is not used. This only appears to be valid in VLIW64 mode. */ + +static int +mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + int status; + int buflength; + int corebuflength; + int cop1buflength; + int cop2buflength; + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + char indicator16[1]; + char indicatorcop32[2]; + + /* At this time we're not supporting internally parallel coprocessors, + so cop2buflength will always be 0. */ + cop2buflength = 0; + + /* Read in 32 bits. */ + buflength = 4; /* VLIW insn spans 4 bytes. */ + status = (*info->read_memory_func) (pc, buf, buflength, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + /* Put the big endian representation of the bytes to be examined + in the temporary buffers for examination. */ + + if (info->endian == BFD_ENDIAN_BIG) + { + indicator16[0] = buf[0]; + indicatorcop32[0] = buf[0]; + indicatorcop32[1] = buf[1]; + } + else + { + indicator16[0] = buf[1]; + indicatorcop32[0] = buf[1]; + indicatorcop32[1] = buf[0]; + } + + /* If the two high order bits are 00, 01 or 10, we have a 16 bit + core insn and a 48 bit copro insn. */ + + if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) + { + if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) + { + /* We have a 32 bit copro insn. */ + corebuflength = 0; + /* All 4 4ytes are one copro insn. */ + cop1buflength = 4; + } + else + { + /* We have a 32 bit core. */ + corebuflength = 4; + cop1buflength = 0; + } + } + else + { + /* We have a 16 bit core insn and a 16 bit copro insn. */ + corebuflength = 2; + cop1buflength = 2; + } + + /* Now we have the distrubution set. Print them out. */ + status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, + cop1buflength, cop2buflength); + + return status; +} + +static int +mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + int status; + int buflength; + int corebuflength; + int cop1buflength; + int cop2buflength; + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + char indicator16[1]; + char indicator64[4]; + + /* At this time we're not supporting internally parallel + coprocessors, so cop2buflength will always be 0. */ + cop2buflength = 0; + + /* Read in 64 bits. */ + buflength = 8; /* VLIW insn spans 8 bytes. */ + status = (*info->read_memory_func) (pc, buf, buflength, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + /* We have all 64 bits in the buffer now. We have to figure out + what combination of instruction sizes are present. The two + high order bits will indicate whether or not we have a 16 bit + core insn or not. If not, then we have to look at the 7,8th + bytes to tell whether we have 64 bit copro insn or a 32 bit + core insn with a 32 bit copro insn. Endianness will make a + difference here. */ + + /* Put the big endian representation of the bytes to be examined + in the temporary buffers for examination. */ + + /* indicator16[0] = buf[0]; */ + if (info->endian == BFD_ENDIAN_BIG) + { + indicator16[0] = buf[0]; + indicator64[0] = buf[0]; + indicator64[1] = buf[1]; + indicator64[2] = buf[2]; + indicator64[3] = buf[3]; + } + else + { + indicator16[0] = buf[1]; + indicator64[0] = buf[1]; + indicator64[1] = buf[0]; + indicator64[2] = buf[3]; + indicator64[3] = buf[2]; + } + + /* If the two high order bits are 00, 01 or 10, we have a 16 bit + core insn and a 48 bit copro insn. */ + + if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) + { + if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 + && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) + { + /* We have a 64 bit copro insn. */ + corebuflength = 0; + /* All 8 bytes are one copro insn. */ + cop1buflength = 8; + } + else + { + /* We have a 32 bit core insn and a 32 bit copro insn. */ + corebuflength = 4; + cop1buflength = 4; + } + } + else + { + /* We have a 16 bit core insn and a 48 bit copro insn. */ + corebuflength = 2; + cop1buflength = 6; + } + + /* Now we have the distrubution set. Print them out. */ + status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, + cop1buflength, cop2buflength); + + return status; +} + +static int +mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + int status; + + /* Extract and adapt to configuration number, if available. */ + if (info->section && info->section->owner) + { + bfd *abfd = info->section->owner; + mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK; + /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */ + } + + /* Picking the right ISA bitmask for the current context is tricky. */ + if (info->section) + { + if (info->section->flags & SEC_MEP_VLIW) + { + /* Are we in 32 or 64 bit vliw mode? */ + if (MEP_VLIW64) + status = mep_examine_vliw64_insns (cd, pc, info); + else + status = mep_examine_vliw32_insns (cd, pc, info); + /* Both the above branches set their own isa bitmasks. */ + } + else + { + cd->isas = & MEP_CORE_ISA; + status = default_print_insn (cd, pc, info); + } + } + else /* sid or gdb */ + { + status = default_print_insn (cd, pc, info); + } + + return status; +} + + +/* -- opc.c */ + +void mep_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +mep_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + print_normal (cd, info, fields->f_24u8a4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case MEP_OPERAND_CALLNUM : + print_normal (cd, info, fields->f_callnum, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case MEP_OPERAND_CCCC : + print_normal (cd, info, fields->f_rm, 0, pc, length); + break; + case MEP_OPERAND_CCRN : + print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case MEP_OPERAND_CDISP8 : + print_normal (cd, info, fields->f_8s24, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case MEP_OPERAND_CDISP8A2 : + print_normal (cd, info, fields->f_8s24a2, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case MEP_OPERAND_CDISP8A4 : + print_normal (cd, info, fields->f_8s24a4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case MEP_OPERAND_CDISP8A8 : + print_normal (cd, info, fields->f_8s24a8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case MEP_OPERAND_CIMM4 : + print_normal (cd, info, fields->f_rn, 0, pc, length); + break; + case MEP_OPERAND_CIMM5 : + print_normal (cd, info, fields->f_5u24, 0, pc, length); + break; + case MEP_OPERAND_CODE16 : + print_normal (cd, info, fields->f_16u16, 0, pc, length); + break; + case MEP_OPERAND_CODE24 : + print_normal (cd, info, fields->f_24u4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case MEP_OPERAND_CP_FLAG : + print_keyword (cd, info, & mep_cgen_opval_h_ccr, 0, 0); + break; + case MEP_OPERAND_CRN : + print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crn, 0); + break; + case MEP_OPERAND_CRN64 : + print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crn, 0); + break; + case MEP_OPERAND_CRNX : + print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case MEP_OPERAND_CRNX64 : + print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case MEP_OPERAND_CSRN : + print_keyword (cd, info, & mep_cgen_opval_h_csr, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case MEP_OPERAND_CSRN_IDX : + print_normal (cd, info, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case MEP_OPERAND_DBG : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_DEPC : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_EPC : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_EXC : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_FMAX_CCRN : + print_fmax_ccr (cd, info, & mep_cgen_opval_h_ccr, fields->f_fmax_4_4, 0); + break; + case MEP_OPERAND_FMAX_FRD : + print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frd, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case MEP_OPERAND_FMAX_FRD_INT : + print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frd, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case MEP_OPERAND_FMAX_FRM : + print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frm, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case MEP_OPERAND_FMAX_FRN : + print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frn, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case MEP_OPERAND_FMAX_FRN_INT : + print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frn, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case MEP_OPERAND_FMAX_RM : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_fmax_rm, 0); + break; + case MEP_OPERAND_HI : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_LO : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_LP : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_MB0 : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_MB1 : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_ME0 : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_ME1 : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_NPC : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_OPT : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_PCABS24A2 : + print_address (cd, info, fields->f_24u5a2n, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case MEP_OPERAND_PCREL12A2 : + print_address (cd, info, fields->f_12s4a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case MEP_OPERAND_PCREL17A2 : + print_address (cd, info, fields->f_17s16a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case MEP_OPERAND_PCREL24A2 : + print_address (cd, info, fields->f_24s5a2n, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case MEP_OPERAND_PCREL8A2 : + print_address (cd, info, fields->f_8s8a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case MEP_OPERAND_PSW : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_R0 : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0); + break; + case MEP_OPERAND_R1 : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0); + break; + case MEP_OPERAND_RL : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl, 0); + break; + case MEP_OPERAND_RM : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0); + break; + case MEP_OPERAND_RMA : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0); + break; + case MEP_OPERAND_RN : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RN3 : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3C : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3L : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3S : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3UC : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3UL : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RN3US : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); + break; + case MEP_OPERAND_RNC : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNL : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNS : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNUC : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNUL : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_RNUS : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); + break; + case MEP_OPERAND_SAR : + print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); + break; + case MEP_OPERAND_SDISP16 : + print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case MEP_OPERAND_SIMM16 : + print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case MEP_OPERAND_SIMM6 : + print_normal (cd, info, fields->f_6s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case MEP_OPERAND_SIMM8 : + print_normal (cd, info, fields->f_8s8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW), pc, length); + break; + case MEP_OPERAND_SP : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0); + break; + case MEP_OPERAND_SPR : + print_spreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0); + break; + case MEP_OPERAND_TP : + print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0); + break; + case MEP_OPERAND_TPR : + print_tpreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0); + break; + case MEP_OPERAND_UDISP2 : + print_normal (cd, info, fields->f_2u6, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case MEP_OPERAND_UDISP7 : + print_normal (cd, info, fields->f_7u9, 0, pc, length); + break; + case MEP_OPERAND_UDISP7A2 : + print_normal (cd, info, fields->f_7u9a2, 0, pc, length); + break; + case MEP_OPERAND_UDISP7A4 : + print_normal (cd, info, fields->f_7u9a4, 0, pc, length); + break; + case MEP_OPERAND_UIMM16 : + print_normal (cd, info, fields->f_16u16, 0, pc, length); + break; + case MEP_OPERAND_UIMM2 : + print_normal (cd, info, fields->f_2u10, 0, pc, length); + break; + case MEP_OPERAND_UIMM24 : + print_normal (cd, info, fields->f_24u8n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case MEP_OPERAND_UIMM3 : + print_normal (cd, info, fields->f_3u5, 0, pc, length); + break; + case MEP_OPERAND_UIMM4 : + print_normal (cd, info, fields->f_4u8, 0, pc, length); + break; + case MEP_OPERAND_UIMM5 : + print_normal (cd, info, fields->f_5u8, 0, pc, length); + break; + case MEP_OPERAND_UIMM7A4 : + print_normal (cd, info, fields->f_7u9a4, 0, pc, length); + break; + case MEP_OPERAND_ZERO : + print_normal (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const mep_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +mep_cgen_init_dis (CGEN_CPU_DESC cd) +{ + mep_cgen_init_opcode_table (cd); + mep_cgen_init_ibld_table (cd); + cd->print_handlers = & mep_cgen_print_handlers[0]; + cd->print_operand = mep_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + mep_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! mep_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_mep (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_mep +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = mep_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + mep_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/contrib/binutils/opcodes/mep-ibld.c b/contrib/binutils/opcodes/mep-ibld.c new file mode 100644 index 0000000..7dd6496 --- /dev/null +++ b/contrib/binutils/opcodes/mep-ibld.c @@ -0,0 +1,2541 @@ +/* Instruction building/extraction support for mep. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006 + Free Software Foundation, Inc. + + This file is part of the GNU Binutils and GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * mep_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +mep_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + { +{ + FLD (f_24u8a4n_hi) = ((unsigned int) (FLD (f_24u8a4n)) >> (8)); + FLD (f_24u8a4n_lo) = ((unsigned int) (((FLD (f_24u8a4n)) & (252))) >> (2)); +} + errmsg = insert_normal (cd, fields->f_24u8a4n_hi, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_24u8a4n_lo, 0, 0, 8, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CALLNUM : + { +{ + FLD (f_5) = ((((unsigned int) (FLD (f_callnum)) >> (3))) & (1)); + FLD (f_6) = ((((unsigned int) (FLD (f_callnum)) >> (2))) & (1)); + FLD (f_7) = ((((unsigned int) (FLD (f_callnum)) >> (1))) & (1)); + FLD (f_11) = ((FLD (f_callnum)) & (1)); +} + errmsg = insert_normal (cd, fields->f_5, 0, 0, 5, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_6, 0, 0, 6, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_11, 0, 0, 11, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CCCC : + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_CCRN : + { +{ + FLD (f_ccrn_hi) = ((((unsigned int) (FLD (f_ccrn)) >> (4))) & (3)); + FLD (f_ccrn_lo) = ((FLD (f_ccrn)) & (15)); +} + errmsg = insert_normal (cd, fields->f_ccrn_hi, 0, 0, 28, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_ccrn_lo, 0, 0, 4, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CDISP8 : + errmsg = insert_normal (cd, fields->f_8s24, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 8, 32, total_length, buffer); + break; + case MEP_OPERAND_CDISP8A2 : + { + long value = fields->f_8s24a2; + value = ((int) (value) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 7, 32, total_length, buffer); + } + break; + case MEP_OPERAND_CDISP8A4 : + { + long value = fields->f_8s24a4; + value = ((int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 6, 32, total_length, buffer); + } + break; + case MEP_OPERAND_CDISP8A8 : + { + long value = fields->f_8s24a8; + value = ((int) (value) >> (3)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 5, 32, total_length, buffer); + } + break; + case MEP_OPERAND_CIMM4 : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_CIMM5 : + errmsg = insert_normal (cd, fields->f_5u24, 0, 0, 24, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_CODE16 : + errmsg = insert_normal (cd, fields->f_16u16, 0, 0, 16, 16, 32, total_length, buffer); + break; + case MEP_OPERAND_CODE24 : + { +{ + FLD (f_24u4n_hi) = ((unsigned int) (FLD (f_24u4n)) >> (16)); + FLD (f_24u4n_lo) = ((FLD (f_24u4n)) & (65535)); +} + errmsg = insert_normal (cd, fields->f_24u4n_hi, 0, 0, 4, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_24u4n_lo, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CP_FLAG : + break; + case MEP_OPERAND_CRN : + errmsg = insert_normal (cd, fields->f_crn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_CRN64 : + errmsg = insert_normal (cd, fields->f_crn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_CRNX : + { +{ + FLD (f_crnx_lo) = ((FLD (f_crnx)) & (15)); + FLD (f_crnx_hi) = ((unsigned int) (FLD (f_crnx)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_crnx_hi, 0, 0, 28, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_crnx_lo, 0, 0, 4, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CRNX64 : + { +{ + FLD (f_crnx_lo) = ((FLD (f_crnx)) & (15)); + FLD (f_crnx_hi) = ((unsigned int) (FLD (f_crnx)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_crnx_hi, 0, 0, 28, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_crnx_lo, 0, 0, 4, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CSRN : + { +{ + FLD (f_csrn_lo) = ((FLD (f_csrn)) & (15)); + FLD (f_csrn_hi) = ((unsigned int) (FLD (f_csrn)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_csrn_hi, 0, 0, 15, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_csrn_lo, 0, 0, 8, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_CSRN_IDX : + { +{ + FLD (f_csrn_lo) = ((FLD (f_csrn)) & (15)); + FLD (f_csrn_hi) = ((unsigned int) (FLD (f_csrn)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_csrn_hi, 0, 0, 15, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_csrn_lo, 0, 0, 8, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_DBG : + break; + case MEP_OPERAND_DEPC : + break; + case MEP_OPERAND_EPC : + break; + case MEP_OPERAND_EXC : + break; + case MEP_OPERAND_FMAX_CCRN : + errmsg = insert_normal (cd, fields->f_fmax_4_4, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_FMAX_FRD : + { +{ + FLD (f_fmax_4_4) = ((FLD (f_fmax_frd)) & (15)); + FLD (f_fmax_28_1) = ((unsigned int) (FLD (f_fmax_frd)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_fmax_28_1, 0, 0, 28, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_fmax_4_4, 0, 0, 4, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_FMAX_FRD_INT : + { +{ + FLD (f_fmax_4_4) = ((FLD (f_fmax_frd)) & (15)); + FLD (f_fmax_28_1) = ((unsigned int) (FLD (f_fmax_frd)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_fmax_28_1, 0, 0, 28, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_fmax_4_4, 0, 0, 4, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_FMAX_FRM : + { +{ + FLD (f_fmax_24_4) = ((FLD (f_fmax_frm)) & (15)); + FLD (f_fmax_30_1) = ((unsigned int) (FLD (f_fmax_frm)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_fmax_30_1, 0, 0, 30, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_fmax_24_4, 0, 0, 24, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_FMAX_FRN : + { +{ + FLD (f_fmax_20_4) = ((FLD (f_fmax_frn)) & (15)); + FLD (f_fmax_29_1) = ((unsigned int) (FLD (f_fmax_frn)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_fmax_29_1, 0, 0, 29, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_fmax_20_4, 0, 0, 20, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_FMAX_FRN_INT : + { +{ + FLD (f_fmax_20_4) = ((FLD (f_fmax_frn)) & (15)); + FLD (f_fmax_29_1) = ((unsigned int) (FLD (f_fmax_frn)) >> (4)); +} + errmsg = insert_normal (cd, fields->f_fmax_29_1, 0, 0, 29, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_fmax_20_4, 0, 0, 20, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_FMAX_RM : + errmsg = insert_normal (cd, fields->f_fmax_rm, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_HI : + break; + case MEP_OPERAND_LO : + break; + case MEP_OPERAND_LP : + break; + case MEP_OPERAND_MB0 : + break; + case MEP_OPERAND_MB1 : + break; + case MEP_OPERAND_ME0 : + break; + case MEP_OPERAND_ME1 : + break; + case MEP_OPERAND_NPC : + break; + case MEP_OPERAND_OPT : + break; + case MEP_OPERAND_PCABS24A2 : + { +{ + FLD (f_24u5a2n_lo) = ((unsigned int) (((FLD (f_24u5a2n)) & (255))) >> (1)); + FLD (f_24u5a2n_hi) = ((unsigned int) (FLD (f_24u5a2n)) >> (8)); +} + errmsg = insert_normal (cd, fields->f_24u5a2n_hi, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_24u5a2n_lo, 0, 0, 5, 7, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_PCREL12A2 : + { + long value = fields->f_12s4a2; + value = ((int) (((value) - (pc))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 4, 11, 32, total_length, buffer); + } + break; + case MEP_OPERAND_PCREL17A2 : + { + long value = fields->f_17s16a2; + value = ((int) (((value) - (pc))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer); + } + break; + case MEP_OPERAND_PCREL24A2 : + { +{ + FLD (f_24s5a2n) = ((FLD (f_24s5a2n)) - (pc)); + FLD (f_24s5a2n_lo) = ((unsigned int) (((FLD (f_24s5a2n)) & (254))) >> (1)); + FLD (f_24s5a2n_hi) = ((int) (FLD (f_24s5a2n)) >> (8)); +} + errmsg = insert_normal (cd, fields->f_24s5a2n_hi, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_24s5a2n_lo, 0|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 7, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_PCREL8A2 : + { + long value = fields->f_8s8a2; + value = ((int) (((value) - (pc))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 7, 32, total_length, buffer); + } + break; + case MEP_OPERAND_PSW : + break; + case MEP_OPERAND_R0 : + break; + case MEP_OPERAND_R1 : + break; + case MEP_OPERAND_RL : + errmsg = insert_normal (cd, fields->f_rl, 0, 0, 12, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RM : + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RMA : + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RN : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3 : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3C : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3L : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3S : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3UC : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3UL : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RN3US : + errmsg = insert_normal (cd, fields->f_rn3, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_RNC : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNL : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNS : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNUC : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNUL : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_RNUS : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 4, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_SAR : + break; + case MEP_OPERAND_SDISP16 : + errmsg = insert_normal (cd, fields->f_16s16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer); + break; + case MEP_OPERAND_SIMM16 : + errmsg = insert_normal (cd, fields->f_16s16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer); + break; + case MEP_OPERAND_SIMM6 : + errmsg = insert_normal (cd, fields->f_6s8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 6, 32, total_length, buffer); + break; + case MEP_OPERAND_SIMM8 : + errmsg = insert_normal (cd, fields->f_8s8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer); + break; + case MEP_OPERAND_SP : + break; + case MEP_OPERAND_SPR : + break; + case MEP_OPERAND_TP : + break; + case MEP_OPERAND_TPR : + break; + case MEP_OPERAND_UDISP2 : + errmsg = insert_normal (cd, fields->f_2u6, 0, 0, 6, 2, 32, total_length, buffer); + break; + case MEP_OPERAND_UDISP7 : + errmsg = insert_normal (cd, fields->f_7u9, 0, 0, 9, 7, 32, total_length, buffer); + break; + case MEP_OPERAND_UDISP7A2 : + { + long value = fields->f_7u9a2; + value = ((unsigned int) (value) >> (1)); + errmsg = insert_normal (cd, value, 0, 0, 9, 6, 32, total_length, buffer); + } + break; + case MEP_OPERAND_UDISP7A4 : + { + long value = fields->f_7u9a4; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 9, 5, 32, total_length, buffer); + } + break; + case MEP_OPERAND_UIMM16 : + errmsg = insert_normal (cd, fields->f_16u16, 0, 0, 16, 16, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM2 : + errmsg = insert_normal (cd, fields->f_2u10, 0, 0, 10, 2, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM24 : + { +{ + FLD (f_24u8n_hi) = ((unsigned int) (FLD (f_24u8n)) >> (8)); + FLD (f_24u8n_lo) = ((FLD (f_24u8n)) & (255)); +} + errmsg = insert_normal (cd, fields->f_24u8n_hi, 0, 0, 16, 16, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_24u8n_lo, 0, 0, 8, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case MEP_OPERAND_UIMM3 : + errmsg = insert_normal (cd, fields->f_3u5, 0, 0, 5, 3, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM4 : + errmsg = insert_normal (cd, fields->f_4u8, 0, 0, 8, 4, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM5 : + errmsg = insert_normal (cd, fields->f_5u8, 0, 0, 8, 5, 32, total_length, buffer); + break; + case MEP_OPERAND_UIMM7A4 : + { + long value = fields->f_7u9a4; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 9, 5, 32, total_length, buffer); + } + break; + case MEP_OPERAND_ZERO : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int mep_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +mep_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_24u8a4n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 6, 32, total_length, pc, & fields->f_24u8a4n_lo); + if (length <= 0) break; + FLD (f_24u8a4n) = ((((FLD (f_24u8a4n_hi)) << (8))) | (((FLD (f_24u8a4n_lo)) << (2)))); + } + break; + case MEP_OPERAND_CALLNUM : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_5); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_6); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_11); + if (length <= 0) break; + FLD (f_callnum) = ((((FLD (f_5)) << (3))) | (((((FLD (f_6)) << (2))) | (((((FLD (f_7)) << (1))) | (FLD (f_11))))))); + } + break; + case MEP_OPERAND_CCCC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_rm); + break; + case MEP_OPERAND_CCRN : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ccrn_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ccrn_lo); + if (length <= 0) break; + FLD (f_ccrn) = ((((FLD (f_ccrn_hi)) << (4))) | (FLD (f_ccrn_lo))); + } + break; + case MEP_OPERAND_CDISP8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 8, 32, total_length, pc, & fields->f_8s24); + break; + case MEP_OPERAND_CDISP8A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 7, 32, total_length, pc, & value); + value = ((value) << (1)); + fields->f_8s24a2 = value; + } + break; + case MEP_OPERAND_CDISP8A4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 6, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_8s24a4 = value; + } + break; + case MEP_OPERAND_CDISP8A8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 24, 5, 32, total_length, pc, & value); + value = ((value) << (3)); + fields->f_8s24a8 = value; + } + break; + case MEP_OPERAND_CIMM4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_CIMM5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 5, 32, total_length, pc, & fields->f_5u24); + break; + case MEP_OPERAND_CODE16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_16u16); + break; + case MEP_OPERAND_CODE24 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 32, total_length, pc, & fields->f_24u4n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_24u4n_lo); + if (length <= 0) break; + FLD (f_24u4n) = ((((FLD (f_24u4n_hi)) << (16))) | (FLD (f_24u4n_lo))); + } + break; + case MEP_OPERAND_CP_FLAG : + break; + case MEP_OPERAND_CRN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_crn); + break; + case MEP_OPERAND_CRN64 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_crn); + break; + case MEP_OPERAND_CRNX : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 1, 32, total_length, pc, & fields->f_crnx_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_crnx_lo); + if (length <= 0) break; + FLD (f_crnx) = ((((FLD (f_crnx_hi)) << (4))) | (FLD (f_crnx_lo))); + } + break; + case MEP_OPERAND_CRNX64 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 1, 32, total_length, pc, & fields->f_crnx_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_crnx_lo); + if (length <= 0) break; + FLD (f_crnx) = ((((FLD (f_crnx_hi)) << (4))) | (FLD (f_crnx_lo))); + } + break; + case MEP_OPERAND_CSRN : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_csrn_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_csrn_lo); + if (length <= 0) break; + FLD (f_csrn) = ((((FLD (f_csrn_hi)) << (4))) | (FLD (f_csrn_lo))); + } + break; + case MEP_OPERAND_CSRN_IDX : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_csrn_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_csrn_lo); + if (length <= 0) break; + FLD (f_csrn) = ((((FLD (f_csrn_hi)) << (4))) | (FLD (f_csrn_lo))); + } + break; + case MEP_OPERAND_DBG : + break; + case MEP_OPERAND_DEPC : + break; + case MEP_OPERAND_EPC : + break; + case MEP_OPERAND_EXC : + break; + case MEP_OPERAND_FMAX_CCRN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_fmax_4_4); + break; + case MEP_OPERAND_FMAX_FRD : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 1, 32, total_length, pc, & fields->f_fmax_28_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_fmax_4_4); + if (length <= 0) break; + FLD (f_fmax_frd) = ((((FLD (f_fmax_28_1)) << (4))) | (FLD (f_fmax_4_4))); + } + break; + case MEP_OPERAND_FMAX_FRD_INT : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 1, 32, total_length, pc, & fields->f_fmax_28_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_fmax_4_4); + if (length <= 0) break; + FLD (f_fmax_frd) = ((((FLD (f_fmax_28_1)) << (4))) | (FLD (f_fmax_4_4))); + } + break; + case MEP_OPERAND_FMAX_FRM : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 1, 32, total_length, pc, & fields->f_fmax_30_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 4, 32, total_length, pc, & fields->f_fmax_24_4); + if (length <= 0) break; + FLD (f_fmax_frm) = ((((FLD (f_fmax_30_1)) << (4))) | (FLD (f_fmax_24_4))); + } + break; + case MEP_OPERAND_FMAX_FRN : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 29, 1, 32, total_length, pc, & fields->f_fmax_29_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 4, 32, total_length, pc, & fields->f_fmax_20_4); + if (length <= 0) break; + FLD (f_fmax_frn) = ((((FLD (f_fmax_29_1)) << (4))) | (FLD (f_fmax_20_4))); + } + break; + case MEP_OPERAND_FMAX_FRN_INT : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 29, 1, 32, total_length, pc, & fields->f_fmax_29_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 4, 32, total_length, pc, & fields->f_fmax_20_4); + if (length <= 0) break; + FLD (f_fmax_frn) = ((((FLD (f_fmax_29_1)) << (4))) | (FLD (f_fmax_20_4))); + } + break; + case MEP_OPERAND_FMAX_RM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_fmax_rm); + break; + case MEP_OPERAND_HI : + break; + case MEP_OPERAND_LO : + break; + case MEP_OPERAND_LP : + break; + case MEP_OPERAND_MB0 : + break; + case MEP_OPERAND_MB1 : + break; + case MEP_OPERAND_ME0 : + break; + case MEP_OPERAND_ME1 : + break; + case MEP_OPERAND_NPC : + break; + case MEP_OPERAND_OPT : + break; + case MEP_OPERAND_PCABS24A2 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_24u5a2n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 7, 32, total_length, pc, & fields->f_24u5a2n_lo); + if (length <= 0) break; + FLD (f_24u5a2n) = ((((FLD (f_24u5a2n_hi)) << (8))) | (((FLD (f_24u5a2n_lo)) << (1)))); + } + break; + case MEP_OPERAND_PCREL12A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 4, 11, 32, total_length, pc, & value); + value = ((((value) << (1))) + (pc)); + fields->f_12s4a2 = value; + } + break; + case MEP_OPERAND_PCREL17A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value); + value = ((((value) << (1))) + (pc)); + fields->f_17s16a2 = value; + } + break; + case MEP_OPERAND_PCREL24A2 : + { + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & fields->f_24s5a2n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 7, 32, total_length, pc, & fields->f_24s5a2n_lo); + if (length <= 0) break; + FLD (f_24s5a2n) = ((((((FLD (f_24s5a2n_hi)) << (8))) | (((FLD (f_24s5a2n_lo)) << (1))))) + (pc)); + } + break; + case MEP_OPERAND_PCREL8A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 7, 32, total_length, pc, & value); + value = ((((value) << (1))) + (pc)); + fields->f_8s8a2 = value; + } + break; + case MEP_OPERAND_PSW : + break; + case MEP_OPERAND_R0 : + break; + case MEP_OPERAND_R1 : + break; + case MEP_OPERAND_RL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_rl); + break; + case MEP_OPERAND_RM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_rm); + break; + case MEP_OPERAND_RMA : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_rm); + break; + case MEP_OPERAND_RN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RN3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3C : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3L : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3UC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3UL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RN3US : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_rn3); + break; + case MEP_OPERAND_RNC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNUC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNUL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_RNUS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_rn); + break; + case MEP_OPERAND_SAR : + break; + case MEP_OPERAND_SDISP16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_16s16); + break; + case MEP_OPERAND_SIMM16 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_16s16); + break; + case MEP_OPERAND_SIMM6 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 6, 32, total_length, pc, & fields->f_6s8); + break; + case MEP_OPERAND_SIMM8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_8s8); + break; + case MEP_OPERAND_SP : + break; + case MEP_OPERAND_SPR : + break; + case MEP_OPERAND_TP : + break; + case MEP_OPERAND_TPR : + break; + case MEP_OPERAND_UDISP2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 2, 32, total_length, pc, & fields->f_2u6); + break; + case MEP_OPERAND_UDISP7 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 7, 32, total_length, pc, & fields->f_7u9); + break; + case MEP_OPERAND_UDISP7A2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 6, 32, total_length, pc, & value); + value = ((value) << (1)); + fields->f_7u9a2 = value; + } + break; + case MEP_OPERAND_UDISP7A4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_7u9a4 = value; + } + break; + case MEP_OPERAND_UIMM16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_16u16); + break; + case MEP_OPERAND_UIMM2 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & fields->f_2u10); + break; + case MEP_OPERAND_UIMM24 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_24u8n_hi); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_24u8n_lo); + if (length <= 0) break; + FLD (f_24u8n) = ((((FLD (f_24u8n_hi)) << (8))) | (FLD (f_24u8n_lo))); + } + break; + case MEP_OPERAND_UIMM3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_3u5); + break; + case MEP_OPERAND_UIMM4 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_4u8); + break; + case MEP_OPERAND_UIMM5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 5, 32, total_length, pc, & fields->f_5u8); + break; + case MEP_OPERAND_UIMM7A4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_7u9a4 = value; + } + break; + case MEP_OPERAND_ZERO : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const mep_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const mep_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int mep_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma mep_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + value = fields->f_24u8a4n; + break; + case MEP_OPERAND_CALLNUM : + value = fields->f_callnum; + break; + case MEP_OPERAND_CCCC : + value = fields->f_rm; + break; + case MEP_OPERAND_CCRN : + value = fields->f_ccrn; + break; + case MEP_OPERAND_CDISP8 : + value = fields->f_8s24; + break; + case MEP_OPERAND_CDISP8A2 : + value = fields->f_8s24a2; + break; + case MEP_OPERAND_CDISP8A4 : + value = fields->f_8s24a4; + break; + case MEP_OPERAND_CDISP8A8 : + value = fields->f_8s24a8; + break; + case MEP_OPERAND_CIMM4 : + value = fields->f_rn; + break; + case MEP_OPERAND_CIMM5 : + value = fields->f_5u24; + break; + case MEP_OPERAND_CODE16 : + value = fields->f_16u16; + break; + case MEP_OPERAND_CODE24 : + value = fields->f_24u4n; + break; + case MEP_OPERAND_CP_FLAG : + value = 0; + break; + case MEP_OPERAND_CRN : + value = fields->f_crn; + break; + case MEP_OPERAND_CRN64 : + value = fields->f_crn; + break; + case MEP_OPERAND_CRNX : + value = fields->f_crnx; + break; + case MEP_OPERAND_CRNX64 : + value = fields->f_crnx; + break; + case MEP_OPERAND_CSRN : + value = fields->f_csrn; + break; + case MEP_OPERAND_CSRN_IDX : + value = fields->f_csrn; + break; + case MEP_OPERAND_DBG : + value = 0; + break; + case MEP_OPERAND_DEPC : + value = 0; + break; + case MEP_OPERAND_EPC : + value = 0; + break; + case MEP_OPERAND_EXC : + value = 0; + break; + case MEP_OPERAND_FMAX_CCRN : + value = fields->f_fmax_4_4; + break; + case MEP_OPERAND_FMAX_FRD : + value = fields->f_fmax_frd; + break; + case MEP_OPERAND_FMAX_FRD_INT : + value = fields->f_fmax_frd; + break; + case MEP_OPERAND_FMAX_FRM : + value = fields->f_fmax_frm; + break; + case MEP_OPERAND_FMAX_FRN : + value = fields->f_fmax_frn; + break; + case MEP_OPERAND_FMAX_FRN_INT : + value = fields->f_fmax_frn; + break; + case MEP_OPERAND_FMAX_RM : + value = fields->f_fmax_rm; + break; + case MEP_OPERAND_HI : + value = 0; + break; + case MEP_OPERAND_LO : + value = 0; + break; + case MEP_OPERAND_LP : + value = 0; + break; + case MEP_OPERAND_MB0 : + value = 0; + break; + case MEP_OPERAND_MB1 : + value = 0; + break; + case MEP_OPERAND_ME0 : + value = 0; + break; + case MEP_OPERAND_ME1 : + value = 0; + break; + case MEP_OPERAND_NPC : + value = 0; + break; + case MEP_OPERAND_OPT : + value = 0; + break; + case MEP_OPERAND_PCABS24A2 : + value = fields->f_24u5a2n; + break; + case MEP_OPERAND_PCREL12A2 : + value = fields->f_12s4a2; + break; + case MEP_OPERAND_PCREL17A2 : + value = fields->f_17s16a2; + break; + case MEP_OPERAND_PCREL24A2 : + value = fields->f_24s5a2n; + break; + case MEP_OPERAND_PCREL8A2 : + value = fields->f_8s8a2; + break; + case MEP_OPERAND_PSW : + value = 0; + break; + case MEP_OPERAND_R0 : + value = 0; + break; + case MEP_OPERAND_R1 : + value = 0; + break; + case MEP_OPERAND_RL : + value = fields->f_rl; + break; + case MEP_OPERAND_RM : + value = fields->f_rm; + break; + case MEP_OPERAND_RMA : + value = fields->f_rm; + break; + case MEP_OPERAND_RN : + value = fields->f_rn; + break; + case MEP_OPERAND_RN3 : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3C : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3L : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3S : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3UC : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3UL : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3US : + value = fields->f_rn3; + break; + case MEP_OPERAND_RNC : + value = fields->f_rn; + break; + case MEP_OPERAND_RNL : + value = fields->f_rn; + break; + case MEP_OPERAND_RNS : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUC : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUL : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUS : + value = fields->f_rn; + break; + case MEP_OPERAND_SAR : + value = 0; + break; + case MEP_OPERAND_SDISP16 : + value = fields->f_16s16; + break; + case MEP_OPERAND_SIMM16 : + value = fields->f_16s16; + break; + case MEP_OPERAND_SIMM6 : + value = fields->f_6s8; + break; + case MEP_OPERAND_SIMM8 : + value = fields->f_8s8; + break; + case MEP_OPERAND_SP : + value = 0; + break; + case MEP_OPERAND_SPR : + value = 0; + break; + case MEP_OPERAND_TP : + value = 0; + break; + case MEP_OPERAND_TPR : + value = 0; + break; + case MEP_OPERAND_UDISP2 : + value = fields->f_2u6; + break; + case MEP_OPERAND_UDISP7 : + value = fields->f_7u9; + break; + case MEP_OPERAND_UDISP7A2 : + value = fields->f_7u9a2; + break; + case MEP_OPERAND_UDISP7A4 : + value = fields->f_7u9a4; + break; + case MEP_OPERAND_UIMM16 : + value = fields->f_16u16; + break; + case MEP_OPERAND_UIMM2 : + value = fields->f_2u10; + break; + case MEP_OPERAND_UIMM24 : + value = fields->f_24u8n; + break; + case MEP_OPERAND_UIMM3 : + value = fields->f_3u5; + break; + case MEP_OPERAND_UIMM4 : + value = fields->f_4u8; + break; + case MEP_OPERAND_UIMM5 : + value = fields->f_5u8; + break; + case MEP_OPERAND_UIMM7A4 : + value = fields->f_7u9a4; + break; + case MEP_OPERAND_ZERO : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + value = fields->f_24u8a4n; + break; + case MEP_OPERAND_CALLNUM : + value = fields->f_callnum; + break; + case MEP_OPERAND_CCCC : + value = fields->f_rm; + break; + case MEP_OPERAND_CCRN : + value = fields->f_ccrn; + break; + case MEP_OPERAND_CDISP8 : + value = fields->f_8s24; + break; + case MEP_OPERAND_CDISP8A2 : + value = fields->f_8s24a2; + break; + case MEP_OPERAND_CDISP8A4 : + value = fields->f_8s24a4; + break; + case MEP_OPERAND_CDISP8A8 : + value = fields->f_8s24a8; + break; + case MEP_OPERAND_CIMM4 : + value = fields->f_rn; + break; + case MEP_OPERAND_CIMM5 : + value = fields->f_5u24; + break; + case MEP_OPERAND_CODE16 : + value = fields->f_16u16; + break; + case MEP_OPERAND_CODE24 : + value = fields->f_24u4n; + break; + case MEP_OPERAND_CP_FLAG : + value = 0; + break; + case MEP_OPERAND_CRN : + value = fields->f_crn; + break; + case MEP_OPERAND_CRN64 : + value = fields->f_crn; + break; + case MEP_OPERAND_CRNX : + value = fields->f_crnx; + break; + case MEP_OPERAND_CRNX64 : + value = fields->f_crnx; + break; + case MEP_OPERAND_CSRN : + value = fields->f_csrn; + break; + case MEP_OPERAND_CSRN_IDX : + value = fields->f_csrn; + break; + case MEP_OPERAND_DBG : + value = 0; + break; + case MEP_OPERAND_DEPC : + value = 0; + break; + case MEP_OPERAND_EPC : + value = 0; + break; + case MEP_OPERAND_EXC : + value = 0; + break; + case MEP_OPERAND_FMAX_CCRN : + value = fields->f_fmax_4_4; + break; + case MEP_OPERAND_FMAX_FRD : + value = fields->f_fmax_frd; + break; + case MEP_OPERAND_FMAX_FRD_INT : + value = fields->f_fmax_frd; + break; + case MEP_OPERAND_FMAX_FRM : + value = fields->f_fmax_frm; + break; + case MEP_OPERAND_FMAX_FRN : + value = fields->f_fmax_frn; + break; + case MEP_OPERAND_FMAX_FRN_INT : + value = fields->f_fmax_frn; + break; + case MEP_OPERAND_FMAX_RM : + value = fields->f_fmax_rm; + break; + case MEP_OPERAND_HI : + value = 0; + break; + case MEP_OPERAND_LO : + value = 0; + break; + case MEP_OPERAND_LP : + value = 0; + break; + case MEP_OPERAND_MB0 : + value = 0; + break; + case MEP_OPERAND_MB1 : + value = 0; + break; + case MEP_OPERAND_ME0 : + value = 0; + break; + case MEP_OPERAND_ME1 : + value = 0; + break; + case MEP_OPERAND_NPC : + value = 0; + break; + case MEP_OPERAND_OPT : + value = 0; + break; + case MEP_OPERAND_PCABS24A2 : + value = fields->f_24u5a2n; + break; + case MEP_OPERAND_PCREL12A2 : + value = fields->f_12s4a2; + break; + case MEP_OPERAND_PCREL17A2 : + value = fields->f_17s16a2; + break; + case MEP_OPERAND_PCREL24A2 : + value = fields->f_24s5a2n; + break; + case MEP_OPERAND_PCREL8A2 : + value = fields->f_8s8a2; + break; + case MEP_OPERAND_PSW : + value = 0; + break; + case MEP_OPERAND_R0 : + value = 0; + break; + case MEP_OPERAND_R1 : + value = 0; + break; + case MEP_OPERAND_RL : + value = fields->f_rl; + break; + case MEP_OPERAND_RM : + value = fields->f_rm; + break; + case MEP_OPERAND_RMA : + value = fields->f_rm; + break; + case MEP_OPERAND_RN : + value = fields->f_rn; + break; + case MEP_OPERAND_RN3 : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3C : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3L : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3S : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3UC : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3UL : + value = fields->f_rn3; + break; + case MEP_OPERAND_RN3US : + value = fields->f_rn3; + break; + case MEP_OPERAND_RNC : + value = fields->f_rn; + break; + case MEP_OPERAND_RNL : + value = fields->f_rn; + break; + case MEP_OPERAND_RNS : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUC : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUL : + value = fields->f_rn; + break; + case MEP_OPERAND_RNUS : + value = fields->f_rn; + break; + case MEP_OPERAND_SAR : + value = 0; + break; + case MEP_OPERAND_SDISP16 : + value = fields->f_16s16; + break; + case MEP_OPERAND_SIMM16 : + value = fields->f_16s16; + break; + case MEP_OPERAND_SIMM6 : + value = fields->f_6s8; + break; + case MEP_OPERAND_SIMM8 : + value = fields->f_8s8; + break; + case MEP_OPERAND_SP : + value = 0; + break; + case MEP_OPERAND_SPR : + value = 0; + break; + case MEP_OPERAND_TP : + value = 0; + break; + case MEP_OPERAND_TPR : + value = 0; + break; + case MEP_OPERAND_UDISP2 : + value = fields->f_2u6; + break; + case MEP_OPERAND_UDISP7 : + value = fields->f_7u9; + break; + case MEP_OPERAND_UDISP7A2 : + value = fields->f_7u9a2; + break; + case MEP_OPERAND_UDISP7A4 : + value = fields->f_7u9a4; + break; + case MEP_OPERAND_UIMM16 : + value = fields->f_16u16; + break; + case MEP_OPERAND_UIMM2 : + value = fields->f_2u10; + break; + case MEP_OPERAND_UIMM24 : + value = fields->f_24u8n; + break; + case MEP_OPERAND_UIMM3 : + value = fields->f_3u5; + break; + case MEP_OPERAND_UIMM4 : + value = fields->f_4u8; + break; + case MEP_OPERAND_UIMM5 : + value = fields->f_5u8; + break; + case MEP_OPERAND_UIMM7A4 : + value = fields->f_7u9a4; + break; + case MEP_OPERAND_ZERO : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void mep_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void mep_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + fields->f_24u8a4n = value; + break; + case MEP_OPERAND_CALLNUM : + fields->f_callnum = value; + break; + case MEP_OPERAND_CCCC : + fields->f_rm = value; + break; + case MEP_OPERAND_CCRN : + fields->f_ccrn = value; + break; + case MEP_OPERAND_CDISP8 : + fields->f_8s24 = value; + break; + case MEP_OPERAND_CDISP8A2 : + fields->f_8s24a2 = value; + break; + case MEP_OPERAND_CDISP8A4 : + fields->f_8s24a4 = value; + break; + case MEP_OPERAND_CDISP8A8 : + fields->f_8s24a8 = value; + break; + case MEP_OPERAND_CIMM4 : + fields->f_rn = value; + break; + case MEP_OPERAND_CIMM5 : + fields->f_5u24 = value; + break; + case MEP_OPERAND_CODE16 : + fields->f_16u16 = value; + break; + case MEP_OPERAND_CODE24 : + fields->f_24u4n = value; + break; + case MEP_OPERAND_CP_FLAG : + break; + case MEP_OPERAND_CRN : + fields->f_crn = value; + break; + case MEP_OPERAND_CRN64 : + fields->f_crn = value; + break; + case MEP_OPERAND_CRNX : + fields->f_crnx = value; + break; + case MEP_OPERAND_CRNX64 : + fields->f_crnx = value; + break; + case MEP_OPERAND_CSRN : + fields->f_csrn = value; + break; + case MEP_OPERAND_CSRN_IDX : + fields->f_csrn = value; + break; + case MEP_OPERAND_DBG : + break; + case MEP_OPERAND_DEPC : + break; + case MEP_OPERAND_EPC : + break; + case MEP_OPERAND_EXC : + break; + case MEP_OPERAND_FMAX_CCRN : + fields->f_fmax_4_4 = value; + break; + case MEP_OPERAND_FMAX_FRD : + fields->f_fmax_frd = value; + break; + case MEP_OPERAND_FMAX_FRD_INT : + fields->f_fmax_frd = value; + break; + case MEP_OPERAND_FMAX_FRM : + fields->f_fmax_frm = value; + break; + case MEP_OPERAND_FMAX_FRN : + fields->f_fmax_frn = value; + break; + case MEP_OPERAND_FMAX_FRN_INT : + fields->f_fmax_frn = value; + break; + case MEP_OPERAND_FMAX_RM : + fields->f_fmax_rm = value; + break; + case MEP_OPERAND_HI : + break; + case MEP_OPERAND_LO : + break; + case MEP_OPERAND_LP : + break; + case MEP_OPERAND_MB0 : + break; + case MEP_OPERAND_MB1 : + break; + case MEP_OPERAND_ME0 : + break; + case MEP_OPERAND_ME1 : + break; + case MEP_OPERAND_NPC : + break; + case MEP_OPERAND_OPT : + break; + case MEP_OPERAND_PCABS24A2 : + fields->f_24u5a2n = value; + break; + case MEP_OPERAND_PCREL12A2 : + fields->f_12s4a2 = value; + break; + case MEP_OPERAND_PCREL17A2 : + fields->f_17s16a2 = value; + break; + case MEP_OPERAND_PCREL24A2 : + fields->f_24s5a2n = value; + break; + case MEP_OPERAND_PCREL8A2 : + fields->f_8s8a2 = value; + break; + case MEP_OPERAND_PSW : + break; + case MEP_OPERAND_R0 : + break; + case MEP_OPERAND_R1 : + break; + case MEP_OPERAND_RL : + fields->f_rl = value; + break; + case MEP_OPERAND_RM : + fields->f_rm = value; + break; + case MEP_OPERAND_RMA : + fields->f_rm = value; + break; + case MEP_OPERAND_RN : + fields->f_rn = value; + break; + case MEP_OPERAND_RN3 : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3C : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3L : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3S : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3UC : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3UL : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3US : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RNC : + fields->f_rn = value; + break; + case MEP_OPERAND_RNL : + fields->f_rn = value; + break; + case MEP_OPERAND_RNS : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUC : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUL : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUS : + fields->f_rn = value; + break; + case MEP_OPERAND_SAR : + break; + case MEP_OPERAND_SDISP16 : + fields->f_16s16 = value; + break; + case MEP_OPERAND_SIMM16 : + fields->f_16s16 = value; + break; + case MEP_OPERAND_SIMM6 : + fields->f_6s8 = value; + break; + case MEP_OPERAND_SIMM8 : + fields->f_8s8 = value; + break; + case MEP_OPERAND_SP : + break; + case MEP_OPERAND_SPR : + break; + case MEP_OPERAND_TP : + break; + case MEP_OPERAND_TPR : + break; + case MEP_OPERAND_UDISP2 : + fields->f_2u6 = value; + break; + case MEP_OPERAND_UDISP7 : + fields->f_7u9 = value; + break; + case MEP_OPERAND_UDISP7A2 : + fields->f_7u9a2 = value; + break; + case MEP_OPERAND_UDISP7A4 : + fields->f_7u9a4 = value; + break; + case MEP_OPERAND_UIMM16 : + fields->f_16u16 = value; + break; + case MEP_OPERAND_UIMM2 : + fields->f_2u10 = value; + break; + case MEP_OPERAND_UIMM24 : + fields->f_24u8n = value; + break; + case MEP_OPERAND_UIMM3 : + fields->f_3u5 = value; + break; + case MEP_OPERAND_UIMM4 : + fields->f_4u8 = value; + break; + case MEP_OPERAND_UIMM5 : + fields->f_5u8 = value; + break; + case MEP_OPERAND_UIMM7A4 : + fields->f_7u9a4 = value; + break; + case MEP_OPERAND_ZERO : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case MEP_OPERAND_ADDR24A4 : + fields->f_24u8a4n = value; + break; + case MEP_OPERAND_CALLNUM : + fields->f_callnum = value; + break; + case MEP_OPERAND_CCCC : + fields->f_rm = value; + break; + case MEP_OPERAND_CCRN : + fields->f_ccrn = value; + break; + case MEP_OPERAND_CDISP8 : + fields->f_8s24 = value; + break; + case MEP_OPERAND_CDISP8A2 : + fields->f_8s24a2 = value; + break; + case MEP_OPERAND_CDISP8A4 : + fields->f_8s24a4 = value; + break; + case MEP_OPERAND_CDISP8A8 : + fields->f_8s24a8 = value; + break; + case MEP_OPERAND_CIMM4 : + fields->f_rn = value; + break; + case MEP_OPERAND_CIMM5 : + fields->f_5u24 = value; + break; + case MEP_OPERAND_CODE16 : + fields->f_16u16 = value; + break; + case MEP_OPERAND_CODE24 : + fields->f_24u4n = value; + break; + case MEP_OPERAND_CP_FLAG : + break; + case MEP_OPERAND_CRN : + fields->f_crn = value; + break; + case MEP_OPERAND_CRN64 : + fields->f_crn = value; + break; + case MEP_OPERAND_CRNX : + fields->f_crnx = value; + break; + case MEP_OPERAND_CRNX64 : + fields->f_crnx = value; + break; + case MEP_OPERAND_CSRN : + fields->f_csrn = value; + break; + case MEP_OPERAND_CSRN_IDX : + fields->f_csrn = value; + break; + case MEP_OPERAND_DBG : + break; + case MEP_OPERAND_DEPC : + break; + case MEP_OPERAND_EPC : + break; + case MEP_OPERAND_EXC : + break; + case MEP_OPERAND_FMAX_CCRN : + fields->f_fmax_4_4 = value; + break; + case MEP_OPERAND_FMAX_FRD : + fields->f_fmax_frd = value; + break; + case MEP_OPERAND_FMAX_FRD_INT : + fields->f_fmax_frd = value; + break; + case MEP_OPERAND_FMAX_FRM : + fields->f_fmax_frm = value; + break; + case MEP_OPERAND_FMAX_FRN : + fields->f_fmax_frn = value; + break; + case MEP_OPERAND_FMAX_FRN_INT : + fields->f_fmax_frn = value; + break; + case MEP_OPERAND_FMAX_RM : + fields->f_fmax_rm = value; + break; + case MEP_OPERAND_HI : + break; + case MEP_OPERAND_LO : + break; + case MEP_OPERAND_LP : + break; + case MEP_OPERAND_MB0 : + break; + case MEP_OPERAND_MB1 : + break; + case MEP_OPERAND_ME0 : + break; + case MEP_OPERAND_ME1 : + break; + case MEP_OPERAND_NPC : + break; + case MEP_OPERAND_OPT : + break; + case MEP_OPERAND_PCABS24A2 : + fields->f_24u5a2n = value; + break; + case MEP_OPERAND_PCREL12A2 : + fields->f_12s4a2 = value; + break; + case MEP_OPERAND_PCREL17A2 : + fields->f_17s16a2 = value; + break; + case MEP_OPERAND_PCREL24A2 : + fields->f_24s5a2n = value; + break; + case MEP_OPERAND_PCREL8A2 : + fields->f_8s8a2 = value; + break; + case MEP_OPERAND_PSW : + break; + case MEP_OPERAND_R0 : + break; + case MEP_OPERAND_R1 : + break; + case MEP_OPERAND_RL : + fields->f_rl = value; + break; + case MEP_OPERAND_RM : + fields->f_rm = value; + break; + case MEP_OPERAND_RMA : + fields->f_rm = value; + break; + case MEP_OPERAND_RN : + fields->f_rn = value; + break; + case MEP_OPERAND_RN3 : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3C : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3L : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3S : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3UC : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3UL : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RN3US : + fields->f_rn3 = value; + break; + case MEP_OPERAND_RNC : + fields->f_rn = value; + break; + case MEP_OPERAND_RNL : + fields->f_rn = value; + break; + case MEP_OPERAND_RNS : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUC : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUL : + fields->f_rn = value; + break; + case MEP_OPERAND_RNUS : + fields->f_rn = value; + break; + case MEP_OPERAND_SAR : + break; + case MEP_OPERAND_SDISP16 : + fields->f_16s16 = value; + break; + case MEP_OPERAND_SIMM16 : + fields->f_16s16 = value; + break; + case MEP_OPERAND_SIMM6 : + fields->f_6s8 = value; + break; + case MEP_OPERAND_SIMM8 : + fields->f_8s8 = value; + break; + case MEP_OPERAND_SP : + break; + case MEP_OPERAND_SPR : + break; + case MEP_OPERAND_TP : + break; + case MEP_OPERAND_TPR : + break; + case MEP_OPERAND_UDISP2 : + fields->f_2u6 = value; + break; + case MEP_OPERAND_UDISP7 : + fields->f_7u9 = value; + break; + case MEP_OPERAND_UDISP7A2 : + fields->f_7u9a2 = value; + break; + case MEP_OPERAND_UDISP7A4 : + fields->f_7u9a4 = value; + break; + case MEP_OPERAND_UIMM16 : + fields->f_16u16 = value; + break; + case MEP_OPERAND_UIMM2 : + fields->f_2u10 = value; + break; + case MEP_OPERAND_UIMM24 : + fields->f_24u8n = value; + break; + case MEP_OPERAND_UIMM3 : + fields->f_3u5 = value; + break; + case MEP_OPERAND_UIMM4 : + fields->f_4u8 = value; + break; + case MEP_OPERAND_UIMM5 : + fields->f_5u8 = value; + break; + case MEP_OPERAND_UIMM7A4 : + fields->f_7u9a4 = value; + break; + case MEP_OPERAND_ZERO : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +mep_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & mep_cgen_insert_handlers[0]; + cd->extract_handlers = & mep_cgen_extract_handlers[0]; + + cd->insert_operand = mep_cgen_insert_operand; + cd->extract_operand = mep_cgen_extract_operand; + + cd->get_int_operand = mep_cgen_get_int_operand; + cd->set_int_operand = mep_cgen_set_int_operand; + cd->get_vma_operand = mep_cgen_get_vma_operand; + cd->set_vma_operand = mep_cgen_set_vma_operand; +} diff --git a/contrib/binutils/opcodes/mep-opc.c b/contrib/binutils/opcodes/mep-opc.c new file mode 100644 index 0000000..ab5cf4a --- /dev/null +++ b/contrib/binutils/opcodes/mep-opc.c @@ -0,0 +1,2274 @@ +/* Instruction opcode table for mep. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "mep-desc.h" +#include "mep-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +#include "elf/mep.h" + +/* A mask for all ISAs executed by the core. */ +CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask = {0, 0}; + +void +init_mep_all_core_isas_mask (void) +{ + if (mep_all_core_isas_mask.length != 0) + return; + cgen_bitset_init (& mep_all_core_isas_mask, ISA_MAX); + cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP); + /* begin-all-core-isas */ + cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1); + cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE2); + /* end-all-core-isas */ +} + +CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask = {0, 0}; + +void +init_mep_all_cop_isas_mask (void) +{ + if (mep_all_cop_isas_mask.length != 0) + return; + cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX); + /* begin-all-cop-isas */ + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_16); + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_32); + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_48); + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_64); + /* end-all-cop-isas */ +} + +int +mep_insn_supported_by_isa (const CGEN_INSN *insn, CGEN_ATTR_VALUE_BITSET_TYPE *isa_mask) +{ + CGEN_BITSET insn_isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); + return cgen_bitset_intersect_p (& insn_isas, isa_mask); +} + +#define OPTION_MASK \ + ( (1 << CGEN_INSN_OPTIONAL_BIT_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_CP_INSN) \ + | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) ) + + +mep_config_map_struct mep_config_map[] = +{ + /* config-map-start */ + /* Default entry: mep core only, all options enabled. */ + { "", 0, EF_MEP_CPU_C2, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK }, + { "simple", CONFIG_SIMPLE, EF_MEP_CPU_C2, 1, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" }, + 0 }, + { "fmax", CONFIG_FMAX, EF_MEP_CPU_C2, 1, 0, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x2" }, { 1, "\x1e" }, { 1, "\xa0" }, + 0 + | (1 << CGEN_INSN_OPTIONAL_CP_INSN) + | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) + | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) + | (1 << CGEN_INSN_OPTIONAL_BIT_INSN) + | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) + | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) + | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) + | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) + | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) + | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) }, + /* config-map-end */ + { 0, 0, 0, 0, 0, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, 0 } +}; + +int mep_config_index = 0; + +static int +check_configured_mach (int machs) +{ + /* All base insns are supported. */ + int mach = 1 << MACH_BASE; + switch (MEP_CPU) + { + case EF_MEP_CPU_C2: + case EF_MEP_CPU_C3: + mach |= (1 << MACH_MEP); + break; + case EF_MEP_CPU_H1: + mach |= (1 << MACH_H1); + break; + default: + break; + } + return machs & mach; +} + +int +mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) +{ + int iconfig = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG); + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); + int ok1; + int ok2; + int ok3; + + /* If the insn has an option bit set that we don't want, + reject it. */ + if (CGEN_INSN_ATTRS (insn)->bool & OPTION_MASK & ~MEP_OMASK) + return 0; + + /* If attributes are absent, assume no restriction. */ + if (machs == 0) + machs = ~0; + + ok1 = ((machs & cd->machs) && cgen_bitset_intersect_p (& isas, cd->isas)); + /* If the insn is config-specific, make sure it matches. */ + ok2 = (iconfig == 0 || iconfig == MEP_CONFIG); + /* Make sure the insn is supported by the configured mach */ + ok3 = check_configured_mach (machs); + + return (ok1 && ok2 && ok3); +} +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & mep_cgen_ifld_table[MEP_##f] +#else +#define F(f) & mep_cgen_ifld_table[MEP_/**/f] +#endif +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_sb ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lhu ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw_sp ATTRIBUTE_UNUSED = { + 16, 16, 0xf083, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8) }, { F (F_7U9A4) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf880, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf881, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9A2) }, { F (F_15) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf883, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9A4) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf880, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lhu_tp ATTRIBUTE_UNUSED = { + 16, 16, 0xf881, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_8) }, { F (F_7U9A2) }, { F (F_15) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lhu16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw24 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0030000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_24U8A4N) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extb ATTRIBUTE_UNUSED = { + 16, 16, 0xf0ff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ssarb ATTRIBUTE_UNUSED = { + 16, 16, 0xfc0f, { { F (F_MAJOR) }, { F (F_4) }, { F (F_5) }, { F (F_2U6) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movi8 ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movi16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movu24 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_MAJOR) }, { F (F_4) }, { F (F_RN3) }, { F (F_24U8N) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movu16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add3 ATTRIBUTE_UNUSED = { + 16, 16, 0xf000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_RL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 16, 16, 0xf003, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_6S8) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add3i ATTRIBUTE_UNUSED = { + 16, 16, 0xf083, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8) }, { F (F_7U9A4) }, { F (F_SUB2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slt3i ATTRIBUTE_UNUSED = { + 16, 16, 0xf007, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_5U8) }, { F (F_SUB3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add3x ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sltu3x ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bra ATTRIBUTE_UNUSED = { + 16, 16, 0xf001, { { F (F_MAJOR) }, { F (F_12S4A2) }, { F (F_15) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beqz ATTRIBUTE_UNUSED = { + 16, 16, 0xf001, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8S8A2) }, { F (F_15) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beqi ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_4U8) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bsr24 ATTRIBUTE_UNUSED = { + 32, 32, 0xf80f0000, { { F (F_MAJOR) }, { F (F_4) }, { F (F_24S5A2N) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp24 ATTRIBUTE_UNUSED = { + 32, 32, 0xf80f0000, { { F (F_MAJOR) }, { F (F_4) }, { F (F_24U5A2N) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ret ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_repeat ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ff0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_erepeat ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc_lp ATTRIBUTE_UNUSED = { + 16, 16, 0xf0ff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_CSRN_LO) }, { F (F_12) }, { F (F_13) }, { F (F_14) }, { F (F_CSRN_HI) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc ATTRIBUTE_UNUSED = { + 16, 16, 0xf00e, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_CSRN) }, { F (F_12) }, { F (F_13) }, { F (F_14) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swi ATTRIBUTE_UNUSED = { + 16, 16, 0xffcf, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_8) }, { F (F_9) }, { F (F_2U10) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bsetm ATTRIBUTE_UNUSED = { + 16, 16, 0xf80f, { { F (F_MAJOR) }, { F (F_4) }, { F (F_3U5) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tas ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cache ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_madd ATTRIBUTE_UNUSED = { + 32, 32, 0xf00fffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip ATTRIBUTE_UNUSED = { + 32, 32, 0xf0ffff07, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_5U24) }, { F (F_29) }, { F (F_30) }, { F (F_31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swcp ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smcp ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swcp16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smcp16 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbcpa ATTRIBUTE_UNUSED = { + 32, 32, 0xf00fff00, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shcpa ATTRIBUTE_UNUSED = { + 32, 32, 0xf00fff01, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24A2) }, { F (F_31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swcpa ATTRIBUTE_UNUSED = { + 32, 32, 0xf00fff03, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24A4) }, { F (F_30) }, { F (F_31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smcpa ATTRIBUTE_UNUSED = { + 32, 32, 0xf00fff07, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_EXT) }, { F (F_8S24A8) }, { F (F_29) }, { F (F_30) }, { F (F_31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bcpeq ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_17S16A2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sim_syscall ATTRIBUTE_UNUSED = { + 16, 16, 0xf8ef, { { F (F_MAJOR) }, { F (F_4) }, { F (F_CALLNUM) }, { F (F_8) }, { F (F_9) }, { F (F_10) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fadds ATTRIBUTE_UNUSED = { + 32, 32, 0xf0fff001, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_FRM) }, { F (F_FMAX_31_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fsqrts ATTRIBUTE_UNUSED = { + 32, 32, 0xf0fff0f3, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_24_4) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_froundws ATTRIBUTE_UNUSED = { + 32, 32, 0xf0fff0f3, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_24_4) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcvtsw ATTRIBUTE_UNUSED = { + 32, 32, 0xf0fff0f3, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_24_4) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fcmpfs ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff009, { { F (F_FMAX_0_4) }, { F (F_FMAX_4_4) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_FRM) }, { F (F_FMAX_28_1) }, { F (F_FMAX_31_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_frn_rm ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ffff7, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_RM) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_20_4) }, { F (F_FMAX_24_4) }, { F (F_FMAX_29_1) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmovc_ccrn_rm ATTRIBUTE_UNUSED = { + 32, 32, 0xf00fffff, { { F (F_FMAX_0_4) }, { F (F_FMAX_4_4) }, { F (F_FMAX_RM) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_20_4) }, { F (F_FMAX_24_4) }, { F (F_FMAX_28_1) }, { F (F_FMAX_29_1) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) MEP_OPERAND_##op +#else +#define OPERAND(op) MEP_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* sb $rnc,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sb, { 0x8 } + }, +/* sh $rns,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sh, { 0x9 } + }, +/* sw $rnl,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sw, { 0xa } + }, +/* lb $rnc,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sb, { 0xc } + }, +/* lh $rns,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sh, { 0xd } + }, +/* lw $rnl,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_sw, { 0xe } + }, +/* lbu $rnuc,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUC), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_lbu, { 0xb } + }, +/* lhu $rnus,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUS), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_lhu, { 0xf } + }, +/* sw $rnl,$udisp7a4($spr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } }, + & ifmt_sw_sp, { 0x4002 } + }, +/* lw $rnl,$udisp7a4($spr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } }, + & ifmt_sw_sp, { 0x4003 } + }, +/* sb $rn3c,$udisp7($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3C), ',', OP (UDISP7), '(', OP (TPR), ')', 0 } }, + & ifmt_sb_tp, { 0x8000 } + }, +/* sh $rn3s,$udisp7a2($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3S), ',', OP (UDISP7A2), '(', OP (TPR), ')', 0 } }, + & ifmt_sh_tp, { 0x8080 } + }, +/* sw $rn3l,$udisp7a4($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3L), ',', OP (UDISP7A4), '(', OP (TPR), ')', 0 } }, + & ifmt_sw_tp, { 0x4082 } + }, +/* lb $rn3c,$udisp7($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3C), ',', OP (UDISP7), '(', OP (TPR), ')', 0 } }, + & ifmt_sb_tp, { 0x8800 } + }, +/* lh $rn3s,$udisp7a2($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3S), ',', OP (UDISP7A2), '(', OP (TPR), ')', 0 } }, + & ifmt_sh_tp, { 0x8880 } + }, +/* lw $rn3l,$udisp7a4($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3L), ',', OP (UDISP7A4), '(', OP (TPR), ')', 0 } }, + & ifmt_sw_tp, { 0x4083 } + }, +/* lbu $rn3uc,$udisp7($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3UC), ',', OP (UDISP7), '(', OP (TPR), ')', 0 } }, + & ifmt_lbu_tp, { 0x4880 } + }, +/* lhu $rn3us,$udisp7a2($tpr) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3US), ',', OP (UDISP7A2), '(', OP (TPR), ')', 0 } }, + & ifmt_lhu_tp, { 0x8881 } + }, +/* sb $rnc,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sb16, { 0xc0080000 } + }, +/* sh $rns,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sh16, { 0xc0090000 } + }, +/* sw $rnl,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sw16, { 0xc00a0000 } + }, +/* lb $rnc,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sb16, { 0xc00c0000 } + }, +/* lh $rns,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sh16, { 0xc00d0000 } + }, +/* lw $rnl,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_sw16, { 0xc00e0000 } + }, +/* lbu $rnuc,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUC), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_lbu16, { 0xc00b0000 } + }, +/* lhu $rnus,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUS), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_lhu16, { 0xc00f0000 } + }, +/* sw $rnl,($addr24a4) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', '(', OP (ADDR24A4), ')', 0 } }, + & ifmt_sw24, { 0xe0020000 } + }, +/* lw $rnl,($addr24a4) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', '(', OP (ADDR24A4), ')', 0 } }, + & ifmt_sw24, { 0xe0030000 } + }, +/* extb $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_extb, { 0x100d } + }, +/* exth $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_extb, { 0x102d } + }, +/* extub $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_extb, { 0x108d } + }, +/* extuh $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_extb, { 0x10ad } + }, +/* ssarb $udisp2($rm) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UDISP2), '(', OP (RM), ')', 0 } }, + & ifmt_ssarb, { 0x100c } + }, +/* mov $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x0 } + }, +/* mov $rn,$simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (SIMM8), 0 } }, + & ifmt_movi8, { 0x5000 } + }, +/* mov $rn,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (SIMM16), 0 } }, + & ifmt_movi16, { 0xc0010000 } + }, +/* movu $rn3,$uimm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN3), ',', OP (UIMM24), 0 } }, + & ifmt_movu24, { 0xd0000000 } + }, +/* movu $rn,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM16), 0 } }, + & ifmt_movu16, { 0xc0110000 } + }, +/* movh $rn,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM16), 0 } }, + & ifmt_movu16, { 0xc0210000 } + }, +/* add3 $rl,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RL), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add3, { 0x9000 } + }, +/* add $rn,$simm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (SIMM6), 0 } }, + & ifmt_add, { 0x6000 } + }, +/* add3 $rn,$spr,$uimm7a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (SPR), ',', OP (UIMM7A4), 0 } }, + & ifmt_add3i, { 0x4000 } + }, +/* advck3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x7 } + }, +/* sub $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x4 } + }, +/* sbvck3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x5 } + }, +/* neg $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1 } + }, +/* slt3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x2 } + }, +/* sltu3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x3 } + }, +/* slt3 \$0,$rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6001 } + }, +/* sltu3 \$0,$rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6005 } + }, +/* sl1ad3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x2006 } + }, +/* sl2ad3 \$0,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x2007 } + }, +/* add3 $rn,$rm,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (SIMM16), 0 } }, + & ifmt_add3x, { 0xc0000000 } + }, +/* slt3 $rn,$rm,$simm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (SIMM16), 0 } }, + & ifmt_add3x, { 0xc0020000 } + }, +/* sltu3 $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_sltu3x, { 0xc0030000 } + }, +/* or $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1000 } + }, +/* and $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1001 } + }, +/* xor $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1002 } + }, +/* nor $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1003 } + }, +/* or3 $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_sltu3x, { 0xc0040000 } + }, +/* and3 $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_sltu3x, { 0xc0050000 } + }, +/* xor3 $rn,$rm,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, + & ifmt_sltu3x, { 0xc0060000 } + }, +/* sra $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x200d } + }, +/* srl $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x200c } + }, +/* sll $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x200e } + }, +/* sra $rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6003 } + }, +/* srl $rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6002 } + }, +/* sll $rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6006 } + }, +/* sll3 \$0,$rn,$uimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', OP (RN), ',', OP (UIMM5), 0 } }, + & ifmt_slt3i, { 0x6007 } + }, +/* fsft $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x200f } + }, +/* bra $pcrel12a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL12A2), 0 } }, + & ifmt_bra, { 0xb000 } + }, +/* beqz $rn,$pcrel8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (PCREL8A2), 0 } }, + & ifmt_beqz, { 0xa000 } + }, +/* bnez $rn,$pcrel8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (PCREL8A2), 0 } }, + & ifmt_beqz, { 0xa001 } + }, +/* beqi $rn,$uimm4,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM4), ',', OP (PCREL17A2), 0 } }, + & ifmt_beqi, { 0xe0000000 } + }, +/* bnei $rn,$uimm4,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM4), ',', OP (PCREL17A2), 0 } }, + & ifmt_beqi, { 0xe0040000 } + }, +/* blti $rn,$uimm4,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM4), ',', OP (PCREL17A2), 0 } }, + & ifmt_beqi, { 0xe00c0000 } + }, +/* bgei $rn,$uimm4,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM4), ',', OP (PCREL17A2), 0 } }, + & ifmt_beqi, { 0xe0080000 } + }, +/* beq $rn,$rm,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (PCREL17A2), 0 } }, + & ifmt_beq, { 0xe0010000 } + }, +/* bne $rn,$rm,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (PCREL17A2), 0 } }, + & ifmt_beq, { 0xe0050000 } + }, +/* bsr $pcrel12a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL12A2), 0 } }, + & ifmt_bra, { 0xb001 } + }, +/* bsr $pcrel24a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL24A2), 0 } }, + & ifmt_bsr24, { 0xd8090000 } + }, +/* jmp $rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), 0 } }, + & ifmt_jmp, { 0x100e } + }, +/* jmp $pcabs24a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCABS24A2), 0 } }, + & ifmt_jmp24, { 0xd8080000 } + }, +/* jsr $rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), 0 } }, + & ifmt_jmp, { 0x100f } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7002 } + }, +/* repeat $rn,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (PCREL17A2), 0 } }, + & ifmt_repeat, { 0xe0090000 } + }, +/* erepeat $pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL17A2), 0 } }, + & ifmt_erepeat, { 0xe0190000 } + }, +/* stc $rn,\$lp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'l', 'p', 0 } }, + & ifmt_stc_lp, { 0x7018 } + }, +/* stc $rn,\$hi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'h', 'i', 0 } }, + & ifmt_stc_lp, { 0x7078 } + }, +/* stc $rn,\$lo */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'l', 'o', 0 } }, + & ifmt_stc_lp, { 0x7088 } + }, +/* stc $rn,$csrn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (CSRN), 0 } }, + & ifmt_stc, { 0x7008 } + }, +/* ldc $rn,\$lp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'l', 'p', 0 } }, + & ifmt_stc_lp, { 0x701a } + }, +/* ldc $rn,\$hi */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'h', 'i', 0 } }, + & ifmt_stc_lp, { 0x707a } + }, +/* ldc $rn,\$lo */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '$', 'l', 'o', 0 } }, + & ifmt_stc_lp, { 0x708a } + }, +/* ldc $rn,$csrn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (CSRN), 0 } }, + & ifmt_stc, { 0x700a } + }, +/* di */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7000 } + }, +/* ei */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7010 } + }, +/* reti */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7012 } + }, +/* halt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7022 } + }, +/* sleep */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7062 } + }, +/* swi $uimm2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (UIMM2), 0 } }, + & ifmt_swi, { 0x7006 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7032 } + }, +/* syncm */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7011 } + }, +/* stcb $rn,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM16), 0 } }, + & ifmt_movu16, { 0xf0040000 } + }, +/* ldcb $rn,$uimm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (UIMM16), 0 } }, + & ifmt_movu16, { 0xf0140000 } + }, +/* bsetm ($rma),$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (RMA), ')', ',', OP (UIMM3), 0 } }, + & ifmt_bsetm, { 0x2000 } + }, +/* bclrm ($rma),$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (RMA), ')', ',', OP (UIMM3), 0 } }, + & ifmt_bsetm, { 0x2001 } + }, +/* bnotm ($rma),$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '(', OP (RMA), ')', ',', OP (UIMM3), 0 } }, + & ifmt_bsetm, { 0x2002 } + }, +/* btstm \$0,($rma),$uimm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '$', '0', ',', '(', OP (RMA), ')', ',', OP (UIMM3), 0 } }, + & ifmt_bsetm, { 0x2003 } + }, +/* tas $rn,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_tas, { 0x2004 } + }, +/* cache $cimm4,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CIMM4), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_cache, { 0x7004 } + }, +/* mul $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1004 } + }, +/* mulu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1005 } + }, +/* mulr $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1006 } + }, +/* mulru $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1007 } + }, +/* madd $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0013004 } + }, +/* maddu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0013005 } + }, +/* maddr $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0013006 } + }, +/* maddru $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0013007 } + }, +/* div $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1008 } + }, +/* divu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_mov, { 0x1009 } + }, +/* dret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7013 } + }, +/* dbreak */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7033 } + }, +/* ldz $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010000 } + }, +/* abs $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010003 } + }, +/* ave $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010002 } + }, +/* min $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010004 } + }, +/* max $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010005 } + }, +/* minu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010006 } + }, +/* maxu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010007 } + }, +/* clip $rn,$cimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (CIMM5), 0 } }, + & ifmt_clip, { 0xf0011000 } + }, +/* clipu $rn,$cimm5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (CIMM5), 0 } }, + & ifmt_clip, { 0xf0011001 } + }, +/* sadd $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010008 } + }, +/* ssub $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf001000a } + }, +/* saddu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf0010009 } + }, +/* ssubu $rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (RM), 0 } }, + & ifmt_madd, { 0xf001000b } + }, +/* swcp $crn,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_swcp, { 0x3008 } + }, +/* lwcp $crn,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_swcp, { 0x3009 } + }, +/* smcp $crn64,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_smcp, { 0x300a } + }, +/* lmcp $crn64,($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), ')', 0 } }, + & ifmt_smcp, { 0x300b } + }, +/* swcpi $crn,($rma+) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', 0 } }, + & ifmt_swcp, { 0x3000 } + }, +/* lwcpi $crn,($rma+) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', 0 } }, + & ifmt_swcp, { 0x3001 } + }, +/* smcpi $crn64,($rma+) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', 0 } }, + & ifmt_smcp, { 0x3002 } + }, +/* lmcpi $crn64,($rma+) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', 0 } }, + & ifmt_smcp, { 0x3003 } + }, +/* swcp $crn,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_swcp16, { 0xf00c0000 } + }, +/* lwcp $crn,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_swcp16, { 0xf00d0000 } + }, +/* smcp $crn64,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_smcp16, { 0xf00e0000 } + }, +/* lmcp $crn64,$sdisp16($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', OP (SDISP16), '(', OP (RMA), ')', 0 } }, + & ifmt_smcp16, { 0xf00f0000 } + }, +/* sbcpa $crn,($rma+),$cdisp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } }, + & ifmt_sbcpa, { 0xf0050000 } + }, +/* lbcpa $crn,($rma+),$cdisp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } }, + & ifmt_sbcpa, { 0xf0054000 } + }, +/* shcpa $crn,($rma+),$cdisp8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } }, + & ifmt_shcpa, { 0xf0051000 } + }, +/* lhcpa $crn,($rma+),$cdisp8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } }, + & ifmt_shcpa, { 0xf0055000 } + }, +/* swcpa $crn,($rma+),$cdisp8a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } }, + & ifmt_swcpa, { 0xf0052000 } + }, +/* lwcpa $crn,($rma+),$cdisp8a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } }, + & ifmt_swcpa, { 0xf0056000 } + }, +/* smcpa $crn64,($rma+),$cdisp8a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } }, + & ifmt_smcpa, { 0xf0053000 } + }, +/* lmcpa $crn64,($rma+),$cdisp8a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } }, + & ifmt_smcpa, { 0xf0057000 } + }, +/* sbcpm0 $crn,($rma+),$cdisp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } }, + & ifmt_sbcpa, { 0xf0050800 } + }, +/* lbcpm0 $crn,($rma+),$cdisp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } }, + & ifmt_sbcpa, { 0xf0054800 } + }, +/* shcpm0 $crn,($rma+),$cdisp8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } }, + & ifmt_shcpa, { 0xf0051800 } + }, +/* lhcpm0 $crn,($rma+),$cdisp8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } }, + & ifmt_shcpa, { 0xf0055800 } + }, +/* swcpm0 $crn,($rma+),$cdisp8a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } }, + & ifmt_swcpa, { 0xf0052800 } + }, +/* lwcpm0 $crn,($rma+),$cdisp8a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } }, + & ifmt_swcpa, { 0xf0056800 } + }, +/* smcpm0 $crn64,($rma+),$cdisp8a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } }, + & ifmt_smcpa, { 0xf0053800 } + }, +/* lmcpm0 $crn64,($rma+),$cdisp8a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } }, + & ifmt_smcpa, { 0xf0057800 } + }, +/* sbcpm1 $crn,($rma+),$cdisp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } }, + & ifmt_sbcpa, { 0xf0050c00 } + }, +/* lbcpm1 $crn,($rma+),$cdisp8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8), 0 } }, + & ifmt_sbcpa, { 0xf0054c00 } + }, +/* shcpm1 $crn,($rma+),$cdisp8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } }, + & ifmt_shcpa, { 0xf0051c00 } + }, +/* lhcpm1 $crn,($rma+),$cdisp8a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A2), 0 } }, + & ifmt_shcpa, { 0xf0055c00 } + }, +/* swcpm1 $crn,($rma+),$cdisp8a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } }, + & ifmt_swcpa, { 0xf0052c00 } + }, +/* lwcpm1 $crn,($rma+),$cdisp8a4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A4), 0 } }, + & ifmt_swcpa, { 0xf0056c00 } + }, +/* smcpm1 $crn64,($rma+),$cdisp8a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } }, + & ifmt_smcpa, { 0xf0053c00 } + }, +/* lmcpm1 $crn64,($rma+),$cdisp8a8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', '(', OP (RMA), '+', ')', ',', OP (CDISP8A8), 0 } }, + & ifmt_smcpa, { 0xf0057c00 } + }, +/* bcpeq $cccc,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CCCC), ',', OP (PCREL17A2), 0 } }, + & ifmt_bcpeq, { 0xd8040000 } + }, +/* bcpne $cccc,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CCCC), ',', OP (PCREL17A2), 0 } }, + & ifmt_bcpeq, { 0xd8050000 } + }, +/* bcpat $cccc,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CCCC), ',', OP (PCREL17A2), 0 } }, + & ifmt_bcpeq, { 0xd8060000 } + }, +/* bcpaf $cccc,$pcrel17a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CCCC), ',', OP (PCREL17A2), 0 } }, + & ifmt_bcpeq, { 0xd8070000 } + }, +/* synccp */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ret, { 0x7021 } + }, +/* jsrv $rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RM), 0 } }, + & ifmt_jmp, { 0x180f } + }, +/* bsrv $pcrel24a2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (PCREL24A2), 0 } }, + & ifmt_bsr24, { 0xd80b0000 } + }, +/* --unused-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_sim_syscall, { 0x7800 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x6 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x100a } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x100b } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x2005 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x2008 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x2009 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x200a } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x200b } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x3004 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x3005 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x3006 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x3007 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x300c } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x300d } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x300e } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x300f } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x7007 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x700e } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x700f } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0xc007 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0xe00d } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0xf003 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0xf006 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0xf008 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x7005 } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x700c } + }, +/* --reserved-- */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_mov, { 0x700d } + }, +/* fadds ${fmax-FRd},${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fadds, { 0xf0070000 } + }, +/* fsubs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fadds, { 0xf0170000 } + }, +/* fmuls ${fmax-FRd},${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fadds, { 0xf0270000 } + }, +/* fdivs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fadds, { 0xf0370000 } + }, +/* fsqrts ${fmax-FRd},${fmax-FRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), 0 } }, + & ifmt_fsqrts, { 0xf0470000 } + }, +/* fabss ${fmax-FRd},${fmax-FRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), 0 } }, + & ifmt_fsqrts, { 0xf0570000 } + }, +/* fnegs ${fmax-FRd},${fmax-FRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), 0 } }, + & ifmt_fsqrts, { 0xf0770000 } + }, +/* fmovs ${fmax-FRd},${fmax-FRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), 0 } }, + & ifmt_fsqrts, { 0xf0670000 } + }, +/* froundws ${fmax-FRd-int},${fmax-FRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } }, + & ifmt_froundws, { 0xf0c70000 } + }, +/* ftruncws ${fmax-FRd-int},${fmax-FRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } }, + & ifmt_froundws, { 0xf0d70000 } + }, +/* fceilws ${fmax-FRd-int},${fmax-FRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } }, + & ifmt_froundws, { 0xf0e70000 } + }, +/* ffloorws ${fmax-FRd-int},${fmax-FRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } }, + & ifmt_froundws, { 0xf0f70000 } + }, +/* fcvtws ${fmax-FRd-int},${fmax-FRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } }, + & ifmt_froundws, { 0xf0471000 } + }, +/* fcvtsw ${fmax-FRd},${fmax-FRn-int} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN_INT), 0 } }, + & ifmt_fcvtsw, { 0xf0079000 } + }, +/* fcmpfs ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0072000 } + }, +/* fcmpus ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0172000 } + }, +/* fcmpes ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0272000 } + }, +/* fcmpues ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0372000 } + }, +/* fcmpls ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0472000 } + }, +/* fcmpuls ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0572000 } + }, +/* fcmples ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0672000 } + }, +/* fcmpules ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0772000 } + }, +/* fcmpfis ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0872000 } + }, +/* fcmpuis ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0972000 } + }, +/* fcmpeis ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0a72000 } + }, +/* fcmpueis ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0b72000 } + }, +/* fcmplis ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0c72000 } + }, +/* fcmpulis ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0d72000 } + }, +/* fcmpleis ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0e72000 } + }, +/* fcmpuleis ${fmax-FRn},${fmax-FRm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } }, + & ifmt_fcmpfs, { 0xf0f72000 } + }, +/* cmov ${fmax-FRd-int},${fmax-Rm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_RM), 0 } }, + & ifmt_cmov_frn_rm, { 0xf007f000 } + }, +/* cmov ${fmax-Rm},${fmax-FRd-int} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_RM), ',', OP (FMAX_FRD_INT), 0 } }, + & ifmt_cmov_frn_rm, { 0xf007f001 } + }, +/* cmovc ${fmax-CCRn},${fmax-Rm} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_CCRN), ',', OP (FMAX_RM), 0 } }, + & ifmt_cmovc_ccrn_rm, { 0xf007f002 } + }, +/* cmovc ${fmax-Rm},${fmax-CCRn} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FMAX_RM), ',', OP (FMAX_CCRN), 0 } }, + & ifmt_cmovc_ccrn_rm, { 0xf007f003 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & mep_cgen_ifld_table[MEP_##f] +#else +#define F(f) & mep_cgen_ifld_table[MEP_/**/f] +#endif +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lb16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lh16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lw16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lhu16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swcp16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lwcp16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_smcp16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lmcp16_0 ATTRIBUTE_UNUSED = { + 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) MEP_OPERAND_##op +#else +#define OPERAND(op) MEP_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE mep_cgen_macro_insn_table[] = +{ +/* nop */ + { + -1, "nop", "nop", 16, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sb $rnc,$zero($rma) */ + { + -1, "sb16-0", "sb", 16, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sh $rns,$zero($rma) */ + { + -1, "sh16-0", "sh", 16, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* sw $rnl,$zero($rma) */ + { + -1, "sw16-0", "sw", 16, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lb $rnc,$zero($rma) */ + { + -1, "lb16-0", "lb", 16, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lh $rns,$zero($rma) */ + { + -1, "lh16-0", "lh", 16, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lw $rnl,$zero($rma) */ + { + -1, "lw16-0", "lw", 16, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lbu $rnuc,$zero($rma) */ + { + -1, "lbu16-0", "lbu", 16, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lhu $rnus,$zero($rma) */ + { + -1, "lhu16-0", "lhu", 16, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* swcp $crn,$zero($rma) */ + { + -1, "swcp16-0", "swcp", 16, + { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lwcp $crn,$zero($rma) */ + { + -1, "lwcp16-0", "lwcp", 16, + { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* smcp $crn64,$zero($rma) */ + { + -1, "smcp16-0", "smcp", 16, + { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +/* lmcp $crn64,$zero($rma) */ + { + -1, "lmcp16-0", "lmcp", 16, + { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } } + }, +}; + +/* The macro instruction opcode table. */ + +static const CGEN_OPCODE mep_cgen_macro_insn_opcode_table[] = +{ +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x0 } + }, +/* sb $rnc,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_sb16_0, { 0x8 } + }, +/* sh $rns,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_sh16_0, { 0x9 } + }, +/* sw $rnl,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_sw16_0, { 0xa } + }, +/* lb $rnc,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNC), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_lb16_0, { 0xc } + }, +/* lh $rns,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNS), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_lh16_0, { 0xd } + }, +/* lw $rnl,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNL), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_lw16_0, { 0xe } + }, +/* lbu $rnuc,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUC), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_lbu16_0, { 0xb } + }, +/* lhu $rnus,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RNUS), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_lhu16_0, { 0xf } + }, +/* swcp $crn,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_swcp16_0, { 0x3008 } + }, +/* lwcp $crn,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_lwcp16_0, { 0x3009 } + }, +/* smcp $crn64,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_smcp16_0, { 0x300a } + }, +/* lmcp $crn64,$zero($rma) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CRN64), ',', OP (ZERO), '(', OP (RMA), ')', 0 } }, + & ifmt_lmcp16_0, { 0x300b } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif + +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif + +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ + +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; +{ + return CGEN_ASM_HASH_P (insn); +} + +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; +{ + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); +} + +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; +{ + return CGEN_ASM_HASH (mnem); +} + +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +static unsigned int +dis_hash_insn (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; +{ + return CGEN_DIS_HASH (buf, value); +} + +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ + +static void +set_fields_bitsize (CGEN_FIELDS *fields, int size) +{ + CGEN_FIELDS_BITSIZE (fields) = size; +} + +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ + +void +mep_cgen_init_opcode_table (CGEN_CPU_DESC cd) +{ + int i; + int num_macros = (sizeof (mep_cgen_macro_insn_table) / + sizeof (mep_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & mep_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & mep_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + mep_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & mep_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + mep_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/contrib/binutils/opcodes/mep-opc.h b/contrib/binutils/opcodes/mep-opc.h new file mode 100644 index 0000000..d9dbd4b --- /dev/null +++ b/contrib/binutils/opcodes/mep-opc.h @@ -0,0 +1,294 @@ +/* Instruction opcode header for mep. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef MEP_OPC_H +#define MEP_OPC_H + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 1 + +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, insn) 0 + +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +typedef struct +{ + char * name; + int config_enum; + unsigned cpu_flag; + int big_endian; + int vliw_bits; + CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa; + CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa; + CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa; + CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa; + CGEN_ATTR_VALUE_BITSET_TYPE cop_isa; + CGEN_ATTR_VALUE_BITSET_TYPE core_isa; + unsigned int option_mask; +} mep_config_map_struct; + +extern mep_config_map_struct mep_config_map[]; +extern int mep_config_index; + +extern void init_mep_all_core_isas_mask (void); +extern void init_mep_all_cop_isas_mask (void); +extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void); + +#define MEP_CONFIG (mep_config_map[mep_config_index].config_enum) +#define MEP_CPU (mep_config_map[mep_config_index].cpu_flag) +#define MEP_OMASK (mep_config_map[mep_config_index].option_mask) +#define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0) +#define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32) +#define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64) +#define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa) +#define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa) +#define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa) +#define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa) +#define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa) +#define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa) + +extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *); + +/* A mask for all ISAs executed by the core. */ +#define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask +extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask; + +#define MEP_INSN_CORE_P(insn) ( \ + init_mep_all_core_isas_mask (), \ + mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \ +) + +/* A mask for all ISAs executed by a VLIW coprocessor. */ +#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask +extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask; + +#define MEP_INSN_COP_P(insn) ( \ + init_mep_all_cop_isas_mask (), \ + mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \ +) + +extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); + +/* -- asm.c */ +/* Enum declaration for mep instruction types. */ +typedef enum cgen_insn_type { + MEP_INSN_INVALID, MEP_INSN_SB, MEP_INSN_SH, MEP_INSN_SW + , MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW, MEP_INSN_LBU + , MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP, MEP_INSN_SB_TP + , MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP, MEP_INSN_LH_TP + , MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP, MEP_INSN_SB16 + , MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16, MEP_INSN_LH16 + , MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16, MEP_INSN_SW24 + , MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH, MEP_INSN_EXTUB + , MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV, MEP_INSN_MOVI8 + , MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16, MEP_INSN_MOVH + , MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I, MEP_INSN_ADVCK3 + , MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG, MEP_INSN_SLT3 + , MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I, MEP_INSN_SL1AD3 + , MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X, MEP_INSN_SLTU3X + , MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR, MEP_INSN_NOR + , MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3, MEP_INSN_SRA + , MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI, MEP_INSN_SRLI + , MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT, MEP_INSN_BRA + , MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI, MEP_INSN_BNEI + , MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ, MEP_INSN_BNE + , MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP, MEP_INSN_JMP24 + , MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT, MEP_INSN_EREPEAT + , MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO, MEP_INSN_STC + , MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO, MEP_INSN_LDC + , MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI, MEP_INSN_HALT + , MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK, MEP_INSN_SYNCM + , MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM, MEP_INSN_BCLRM + , MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS, MEP_INSN_CACHE + , MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR, MEP_INSN_MULRU + , MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR, MEP_INSN_MADDRU + , MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET, MEP_INSN_DBREAK + , MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE, MEP_INSN_MIN + , MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU, MEP_INSN_CLIP + , MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB, MEP_INSN_SADDU + , MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP, MEP_INSN_SMCP + , MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI, MEP_INSN_SMCPI + , MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16, MEP_INSN_SMCP16 + , MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA, MEP_INSN_SHCPA + , MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA, MEP_INSN_SMCPA + , MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0, MEP_INSN_SHCPM0 + , MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0, MEP_INSN_SMCPM0 + , MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1, MEP_INSN_SHCPM1 + , MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1, MEP_INSN_SMCPM1 + , MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE, MEP_INSN_BCPAT + , MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV, MEP_INSN_BSRV + , MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1, MEP_INSN_RI_2 + , MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5, MEP_INSN_RI_6 + , MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9, MEP_INSN_RI_10 + , MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13, MEP_INSN_RI_14 + , MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21 + , MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_24, MEP_INSN_RI_25 + , MEP_INSN_RI_26, MEP_INSN_RI_16, MEP_INSN_RI_18, MEP_INSN_RI_19 + , MEP_INSN_FADDS, MEP_INSN_FSUBS, MEP_INSN_FMULS, MEP_INSN_FDIVS + , MEP_INSN_FSQRTS, MEP_INSN_FABSS, MEP_INSN_FNEGS, MEP_INSN_FMOVS + , MEP_INSN_FROUNDWS, MEP_INSN_FTRUNCWS, MEP_INSN_FCEILWS, MEP_INSN_FFLOORWS + , MEP_INSN_FCVTWS, MEP_INSN_FCVTSW, MEP_INSN_FCMPFS, MEP_INSN_FCMPUS + , MEP_INSN_FCMPES, MEP_INSN_FCMPUES, MEP_INSN_FCMPLS, MEP_INSN_FCMPULS + , MEP_INSN_FCMPLES, MEP_INSN_FCMPULES, MEP_INSN_FCMPFIS, MEP_INSN_FCMPUIS + , MEP_INSN_FCMPEIS, MEP_INSN_FCMPUEIS, MEP_INSN_FCMPLIS, MEP_INSN_FCMPULIS + , MEP_INSN_FCMPLEIS, MEP_INSN_FCMPULEIS, MEP_INSN_CMOV_FRN_RM, MEP_INSN_CMOV_RM_FRN + , MEP_INSN_CMOVC_CCRN_RM, MEP_INSN_CMOVC_RM_CCRN +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID MEP_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) MEP_INSN_CMOVC_RM_CCRN + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_major; + long f_rn; + long f_rn3; + long f_rm; + long f_rl; + long f_sub2; + long f_sub3; + long f_sub4; + long f_ext; + long f_crn; + long f_csrn_hi; + long f_csrn_lo; + long f_csrn; + long f_crnx_hi; + long f_crnx_lo; + long f_crnx; + long f_0; + long f_1; + long f_2; + long f_3; + long f_4; + long f_5; + long f_6; + long f_7; + long f_8; + long f_9; + long f_10; + long f_11; + long f_12; + long f_13; + long f_14; + long f_15; + long f_16; + long f_17; + long f_18; + long f_19; + long f_20; + long f_21; + long f_22; + long f_23; + long f_24; + long f_25; + long f_26; + long f_27; + long f_28; + long f_29; + long f_30; + long f_31; + long f_8s8a2; + long f_12s4a2; + long f_17s16a2; + long f_24s5a2n_hi; + long f_24s5a2n_lo; + long f_24s5a2n; + long f_24u5a2n_hi; + long f_24u5a2n_lo; + long f_24u5a2n; + long f_2u6; + long f_7u9; + long f_7u9a2; + long f_7u9a4; + long f_16s16; + long f_2u10; + long f_3u5; + long f_4u8; + long f_5u8; + long f_5u24; + long f_6s8; + long f_8s8; + long f_16u16; + long f_12u16; + long f_3u29; + long f_8s24; + long f_8s24a2; + long f_8s24a4; + long f_8s24a8; + long f_24u8a4n_hi; + long f_24u8a4n_lo; + long f_24u8a4n; + long f_24u8n_hi; + long f_24u8n_lo; + long f_24u8n; + long f_24u4n_hi; + long f_24u4n_lo; + long f_24u4n; + long f_callnum; + long f_ccrn_hi; + long f_ccrn_lo; + long f_ccrn; + long f_fmax_0_4; + long f_fmax_4_4; + long f_fmax_8_4; + long f_fmax_12_4; + long f_fmax_16_4; + long f_fmax_20_4; + long f_fmax_24_4; + long f_fmax_28_1; + long f_fmax_29_1; + long f_fmax_30_1; + long f_fmax_31_1; + long f_fmax_frd; + long f_fmax_frn; + long f_fmax_frm; + long f_fmax_rm; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* MEP_OPC_H */ diff --git a/contrib/binutils/opcodes/mips-dis.c b/contrib/binutils/opcodes/mips-dis.c index 2329a9f..b8e2257 100644 --- a/contrib/binutils/opcodes/mips-dis.c +++ b/contrib/binutils/opcodes/mips-dis.c @@ -58,12 +58,15 @@ struct mips_cp0sel_name const char * const name; }; -/* The mips16 register names. */ -static const char * const mips16_reg_names[] = +/* The mips16 registers. */ +static const unsigned int mips16_to_32_reg_map[] = { - "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" + 16, 17, 2, 3, 4, 5, 6, 7 }; +#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] + + static const char * const mips_gpr_names_numeric[32] = { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", @@ -188,7 +191,28 @@ static const char * const mips_cp0_names_mips3264r2[32] = static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = { { 4, 1, "c0_contextconfig" }, + { 0, 1, "c0_mvpcontrol" }, + { 0, 2, "c0_mvpconf0" }, + { 0, 3, "c0_mvpconf1" }, + { 1, 1, "c0_vpecontrol" }, + { 1, 2, "c0_vpeconf0" }, + { 1, 3, "c0_vpeconf1" }, + { 1, 4, "c0_yqmask" }, + { 1, 5, "c0_vpeschedule" }, + { 1, 6, "c0_vpeschefback" }, + { 2, 1, "c0_tcstatus" }, + { 2, 2, "c0_tcbind" }, + { 2, 3, "c0_tcrestart" }, + { 2, 4, "c0_tchalt" }, + { 2, 5, "c0_tccontext" }, + { 2, 6, "c0_tcschedule" }, + { 2, 7, "c0_tcschefback" }, { 5, 1, "c0_pagegrain" }, + { 6, 1, "c0_srsconf0" }, + { 6, 2, "c0_srsconf1" }, + { 6, 3, "c0_srsconf2" }, + { 6, 4, "c0_srsconf3" }, + { 6, 5, "c0_srsconf4" }, { 12, 1, "c0_intctl" }, { 12, 2, "c0_srsctl" }, { 12, 3, "c0_srsmap" }, @@ -407,26 +431,28 @@ const struct mips_arch_choice mips_arch_choices[] = MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), page 1. */ { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, - ISA_MIPS32 | INSN_MIPS16 | INSN_DSP, + ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), mips_hwr_names_numeric }, { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, - ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT, + (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 + | INSN_MIPS3D | INSN_MT), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_hwr_names_mips3264r2 }, /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, - ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP, + ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), mips_hwr_names_numeric }, { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, - ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP, + (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 + | INSN_DSP64 | INSN_MT | INSN_MDMX), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_hwr_names_mips3264r2 }, @@ -602,7 +628,7 @@ parse_mips_dis_option (const char *option, unsigned int len) } /* Try to match options that are simple flags */ - if (strncmp (option, "no-aliases", 10) == 0) + if (CONST_STRNEQ (option, "no-aliases")) { no_aliases = 1; return; @@ -741,7 +767,8 @@ static void print_insn_args (const char *d, register unsigned long int l, bfd_vma pc, - struct disassemble_info *info) + struct disassemble_info *info, + const struct mips_opcode *opp) { int op, delta; unsigned int lsb, msb, msbd; @@ -781,6 +808,26 @@ print_insn_args (const char *d, (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); break; + case '1': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI1) & OP_MASK_UDI1); + break; + + case '2': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI2) & OP_MASK_UDI2); + break; + + case '3': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI3) & OP_MASK_UDI3); + break; + + case '4': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI4) & OP_MASK_UDI4); + break; + case 'C': case 'H': msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; @@ -861,6 +908,11 @@ print_insn_args (const char *d, } break; + case '2': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_BP) & OP_MASK_BP); + break; + case '3': (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_SA3) & OP_MASK_SA3); @@ -992,6 +1044,10 @@ print_insn_args (const char *d, case 'a': info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); + /* For gdb disassembler, force odd address on jalx. */ + if (info->flavour == bfd_target_unknown_flavour + && strcmp (opp->name, "jalx") == 0) + info->target |= 1; (*info->print_address_func) (info->target, info); break; @@ -1138,7 +1194,9 @@ print_insn_args (const char *d, break; case 'N': - (*info->fprintf_func) (info->stream, "$fcc%ld", + (*info->fprintf_func) (info->stream, + ((opp->pinfo & (FP_D | FP_S)) != 0 + ? "$fcc%ld" : "$cc%ld"), (l >> OP_SH_BCC) & OP_MASK_BCC); break; @@ -1337,7 +1395,7 @@ print_insn_mips (bfd_vma memaddr, if (d != NULL && *d != '\0') { (*info->fprintf_func) (info->stream, "\t"); - print_insn_args (d, word, memaddr, info); + print_insn_args (d, word, memaddr, info, op); } return INSNLEN; @@ -1373,27 +1431,27 @@ print_mips16_insn_arg (char type, case 'y': case 'w': (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RY) - & MIPS16OP_MASK_RY)]); + mips16_reg_names(((l >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY))); break; case 'x': case 'v': (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RX) - & MIPS16OP_MASK_RX)]); + mips16_reg_names(((l >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX))); break; case 'z': (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RZ) - & MIPS16OP_MASK_RZ)]); + mips16_reg_names(((l >> MIPS16OP_SH_RZ) + & MIPS16OP_MASK_RZ))); break; case 'Z': (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) - & MIPS16OP_MASK_MOVE32Z)]); + mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) + & MIPS16OP_MASK_MOVE32Z))); break; case '0': @@ -1675,15 +1733,26 @@ print_mips16_insn_arg (char type, } } info->target = (baseaddr & ~((1 << shift) - 1)) + immed; + if (pcrel && branch + && info->flavour == bfd_target_unknown_flavour) + /* For gdb disassembler, maintain odd address. */ + info->target |= 1; (*info->print_address_func) (info->target, info); } } break; case 'a': - if (! use_extend) - extend = 0; - l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); + { + int jalx = l & 0x400; + + if (! use_extend) + extend = 0; + l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); + if (!jalx && info->flavour == bfd_target_unknown_flavour) + /* For gdb disassembler, maintain odd address. */ + l |= 1; + } info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; (*info->print_address_func) (info->target, info); info->insn_type = dis_jsr; diff --git a/contrib/binutils/opcodes/mips-opc.c b/contrib/binutils/opcodes/mips-opc.c index 145b254..69a6b75 100644 --- a/contrib/binutils/opcodes/mips-opc.c +++ b/contrib/binutils/opcodes/mips-opc.c @@ -92,12 +92,15 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US /* Octeon specific instructions. */ #define IOCTEON INSN_OCTEON -/* MIPS64 MIPS-3D ASE support. */ +/* MIPS16 ASE support. */ #define I16 INSN_MIPS16 /* MIPS64 MIPS-3D ASE support. */ #define M3D INSN_MIPS3D +/* MIPS32 SmartMIPS ASE support. */ +#define SMT INSN_SMARTMIPS + /* MIPS64 MDMX ASE support. */ #define MX INSN_MDMX @@ -128,29 +131,31 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have the same structure as $ac0 (HI + LO). For DSP instructions that write or read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a - (RD_HILO) attritubes, such that HILO dependences are maintained + (RD_HILO) attributes, such that HILO dependencies are maintained conservatively. 2. For some mul. instructions that use integer registers as destinations - but destroy HI+LO as side-effect, we add WR_HILO to their attritubes. + but destroy HI+LO as side-effect, we add WR_HILO to their attributes. 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write certain fields of the DSP control register. For simplicity, we decide not - to track dependences of these fields. + to track dependencies of these fields. However, "bposge32" is a branch instruction that depends on the "pos" field. In order to make sure that GAS does not reorder DSP instructions that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP) - attritube to those instructions that write the "pos" field. */ + attribute to those instructions that write the "pos" field. */ #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */ #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */ #define MOD_a WR_a|RD_a #define DSP_VOLA INSN_TRAP -#define D32 (INSN_DSP) +#define D32 INSN_DSP +#define D33 INSN_DSPR2 +#define D64 INSN_DSP64 /* MIPS MT ASE support. */ -#define MT32 (INSN_MT) +#define MT32 INSN_MT /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either @@ -190,7 +195,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, -{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 }, +{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 }, @@ -199,7 +204,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, -{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, +{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, @@ -213,7 +218,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 }, {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, -{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, +{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 }, {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX }, {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, @@ -247,10 +252,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 }, /* bc2* are at the bottom of the table. */ -{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, -{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, -{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, -{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +/* bc3* are at the bottom of the table. */ {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 }, {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 }, @@ -314,14 +316,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, @@ -330,63 +332,63 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, -{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, @@ -395,15 +397,15 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, -{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, @@ -412,15 +414,15 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 }, {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, -{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX }, {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 }, {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 }, {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 }, {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 }, -{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, -{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5 }, +{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, +{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 }, {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, @@ -469,7 +471,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D }, {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D }, +/* CW4010 instructions which are aliases for the cache instruction. */ +{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, +{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, +{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, +{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3}, +{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3}, {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, @@ -478,7 +486,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 }, /* cfc2 is at the bottom of the table. */ -{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, +/* cfc3 is at the bottom of the table. */ {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 }, {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 }, @@ -491,7 +499,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 }, /* ctc2 is at the bottom of the table. */ -{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +/* ctc3 is at the bottom of the table. */ {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 }, {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 }, @@ -499,16 +507,16 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, -{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_S, 0, I3|I33 }, -{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_S, 0, I3|I33 }, +{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, +{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, -{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5 }, -{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5 }, +{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, +{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 }, {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 }, {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, -{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5 }, +{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 }, {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D }, {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 }, {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 }, @@ -586,10 +594,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 }, /* dmfc2 is at the bottom of the table. */ /* dmtc2 is at the bottom of the table. */ -{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, -{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I64 }, -{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, -{"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I64 }, +/* dmfc3 is at the bottom of the table. */ +/* dmtc3 is at the bottom of the table. */ {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, IOCTEON }, {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 }, @@ -657,16 +663,15 @@ const struct mips_opcode mips_builtin_opcodes[] = {"exts", "t,r,>,h", 0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCTEON }, /* exts32 */ {"exts", "t,r,<,h", 0x7000003a, 0xfc00003f, WR_t|RD_s, 0, IOCTEON }, {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, -{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_S, 0, I3|I33 }, +{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, -{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 }, -{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 }, -{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 }, {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 }, {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 }, {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, -{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I33 }, +/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with + the same hazard barrier effect. */ +{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 }, {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */ /* SVR4 PIC code requires special handling for j, so it must be a macro. */ @@ -677,8 +682,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 }, {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 }, {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 }, -{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I33 }, -{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I33 }, +/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr + with the same hazard barrier effect. */ +{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 }, +{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 }, /* SVR4 PIC code requires special handling for jal, so it must be a macro. */ {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 }, @@ -728,7 +735,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 }, {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 }, -{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I5|N55 }, +{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55}, {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 }, {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 }, @@ -755,6 +762,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 }, {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 }, {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 }, +{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT }, {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 }, @@ -771,14 +779,17 @@ const struct mips_opcode mips_builtin_opcodes[] = {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 }, {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, -{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, -{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, -{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55}, -{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, -{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, -{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, -{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55}, +{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, +{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, +{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, +{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, +{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 }, +{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 }, {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, @@ -815,13 +826,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 }, /* mfc2 is at the bottom of the table. */ /* mfhc2 is at the bottom of the table. */ -{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, -{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, +/* mfc3 is at the bottom of the table. */ {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 }, {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 }, {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 }, {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 }, {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 }, +{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT }, {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 }, {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, @@ -829,33 +840,33 @@ const struct mips_opcode mips_builtin_opcodes[] = {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, -{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 }, +{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, -{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 }, +{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, -{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5 }, +{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 }, {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 }, {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 }, {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 }, -{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5 }, +{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 }, {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 }, {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 }, {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 }, {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 }, {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 }, -{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5 }, +{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 }, {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, @@ -864,11 +875,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, -{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, +{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 }, {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 }, +{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 }, {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 }, @@ -880,13 +893,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 }, /* mtc2 is at the bottom of the table. */ /* mthc2 is at the bottom of the table. */ -{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, -{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, +/* mtc3 is at the bottom of the table. */ {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 }, {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 }, {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 }, {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 }, {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 }, +{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT }, {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_s, 0, IOCTEON }, {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_s, 0, IOCTEON }, {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_s, 0, IOCTEON }, @@ -917,7 +930,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, -{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, +{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55}, {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 }, @@ -955,21 +968,24 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 }, {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, +{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, +{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT }, {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 }, +{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 }, {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 }, {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 }, {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */ {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */ {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 }, {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 }, -{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 }, +{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 }, {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, -{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, +{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 }, {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 }, -{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 }, +{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 }, /* nop is at the start of the table. */ {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 }, @@ -1000,12 +1016,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, -{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, -{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, +{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, {"pop", "d,s", 0x7000002c, 0xfc1f07ff, WR_d|RD_s, 0, IOCTEON }, /* pref and prefx are at the start of the table. */ -{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, -{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, +{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, +{"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT }, {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 }, {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX }, @@ -1043,15 +1060,15 @@ const struct mips_opcode mips_builtin_opcodes[] = {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 }, {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 }, {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 }, -{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33 }, -{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33 }, -{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33 }, -{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33 }, -{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33 }, -{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33 }, -{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33 }, +{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT }, +{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT }, +{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT }, +{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT }, +{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT }, +{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT }, +{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT }, {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 }, -{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3 }, +{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 }, {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 }, {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 }, {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 }, @@ -1179,7 +1196,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 }, {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 }, -{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5 }, +{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 }, {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX }, {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 }, {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX }, @@ -1188,7 +1205,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 }, -{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|N55 }, +{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55}, {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 }, {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 }, @@ -1296,7 +1313,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 }, {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 }, {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 }, -{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 }, {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 }, {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 }, {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, @@ -1310,12 +1326,82 @@ const struct mips_opcode mips_builtin_opcodes[] = {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 }, {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 }, +/* User Defined Instruction. */ +{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, +{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 }, + /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format instructions so they are here for the latters to take precedence. */ {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 }, {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 }, {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 }, {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 }, {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, {"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCTEON }, @@ -1326,11 +1412,30 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 }, {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 }, {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 }, +{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 }, +{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 }, {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 }, {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 }, {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 }, +{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 }, {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 }, +/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X + instructions, so they are here for the latters to take precedence. */ +{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 }, +{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, +{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, +{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 }, +{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 }, +{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 }, +{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 }, +{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 }, +{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 }, +{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 }, + /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the user to put in nops as necessary. These are at the end so that the @@ -1343,40 +1448,94 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 }, {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 }, {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }, - /* Conflicts with the 4650's "mul" instruction. Nobody's using the 4010 any more, so move this insn out of the way. If the object format gave us more info, we could do this right. */ {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 }, /* MIPS DSP ASE */ {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 }, {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 }, +{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 }, {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 }, {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 }, +{"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 }, {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 }, {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 }, {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 }, +{"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 }, +{"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 }, +{"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 }, +{"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 }, +{"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 }, +{"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 }, +{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 }, +{"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 }, {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 }, {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 }, {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, @@ -1391,69 +1550,191 @@ const struct mips_opcode mips_builtin_opcodes[] = {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 }, {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 }, {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, +{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 }, {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 }, {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, +{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 }, +{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 }, +{"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 }, +{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 }, +{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 }, {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 }, {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 }, {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 }, +{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 }, {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 }, {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 }, {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 }, +{"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 }, {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 }, +{"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 }, {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 }, +{"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 }, +{"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 }, +{"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 }, {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 }, {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 }, +{"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 }, {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 }, {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 }, +{"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 }, {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 }, {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 }, +{"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 }, {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 }, +{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 }, +{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 }, {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 }, {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 }, {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 }, +{"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, +{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, +{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 }, {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 }, {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 }, {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 }, +/* MIPS DSP ASE Rev2 */ +{"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 }, +{"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 }, +{"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 }, +{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 }, +{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 }, +{"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 }, +{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 }, +{"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 }, +{"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 }, +{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, +{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 }, /* Move bc0* after mftr and mttr to avoid opcode collision. */ {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 }, {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 }, diff --git a/contrib/binutils/opcodes/mips16-opc.c b/contrib/binutils/opcodes/mips16-opc.c index 4e5ae44..8144986 100644 --- a/contrib/binutils/opcodes/mips16-opc.c +++ b/contrib/binutils/opcodes/mips16-opc.c @@ -58,58 +58,61 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA #define TRAP INSN_TRAP +#define I1 INSN_ISA1 #define I3 INSN_ISA3 - -#define T3 INSN_3900 +#define I32 INSN_ISA32 +#define I64 INSN_ISA64 +#define T3 INSN_3900 const struct mips_opcode mips16_opcodes[] = { -{"nop", "", 0x6500, 0xffff, RD_Z, 0, 0 }, /* move $0,$Z */ -{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, 0 }, -{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, 0 }, -{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, 0 }, -{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, 0 }, -{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 }, -{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 }, -{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, 0 }, -{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, 0 }, -{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, 0 }, -{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, 0 }, -{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, 0 }, -{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 }, -{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, 0 }, -{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, 0 }, -{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, 0 }, -{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, 0 }, -{"b", "q", 0x1000, 0xf800, BR, 0, 0 }, -{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, 0 }, -{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, 0 }, -{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0, 0 }, -{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, 0 }, -{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0, 0 }, -{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, 0 }, -{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, 0 }, -{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, 0 }, -{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0, 0 }, -{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, 0 }, -{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, 0 }, -{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, 0 }, -{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0, 0 }, -{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, 0 }, -{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, 0 }, -{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, 0 }, -{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0, 0 }, -{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, 0 }, -{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, 0 }, -{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, 0 }, -{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0, 0 }, -{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0, 0 }, -{"break", "6", 0xe805, 0xf81f, TRAP, 0, 0 }, -{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0, 0 }, -{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0, 0 }, -{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, 0 }, -{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, 0 }, -{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, 0 }, +/* name, args, match, mask, pinfo, pinfo2, membership */ +{"nop", "", 0x6500, 0xffff, RD_Z, 0, I1 }, /* move $0,$Z */ +{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 }, +{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1 }, +{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1 }, +{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1 }, +{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 }, +{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 }, +{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 }, +{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 }, +{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, I1 }, +{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1 }, +{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1 }, +{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 }, +{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 }, +{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 }, +{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 }, +{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, +{"b", "q", 0x1000, 0xf800, BR, 0, I1 }, +{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1 }, +{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, +{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0, I1 }, +{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, +{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, +{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, +{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 }, +{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 }, +{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 }, +{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 }, +{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 }, +{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 }, +{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 }, +{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 }, +{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 }, +{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 }, +{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 }, +{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 }, +{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, +{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1 }, +{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, +{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0, I1 }, +{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1 }, +{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0, I1 }, +{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0, I1 }, +{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 }, +{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1 }, +{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 }, {"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 }, {"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 }, {"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 }, @@ -125,20 +128,20 @@ const struct mips_opcode mips16_opcodes[] = {"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 }, {"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 }, {"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, -{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, 0 }, +{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1 }, {"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, -{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, 0 }, -{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 }, -{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, 0 }, -{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 }, -{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, 0 }, +{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1 }, +{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 }, +{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 }, {"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3 }, {"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, {"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, {"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, -{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, 0 }, +{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1 }, {"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 }, -{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, 0 }, +{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1 }, {"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, {"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, 0, I3 }, {"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, @@ -149,91 +152,92 @@ const struct mips_opcode mips16_opcodes[] = {"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3 }, {"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 }, {"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3 }, -{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0, 0 }, -{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, 0 }, -{"exit", "L", 0xed09, 0xff1f, TRAP, 0, 0 }, -{"exit", "L", 0xee09, 0xff1f, TRAP, 0, 0 }, -{"exit", "L", 0xef09, 0xff1f, TRAP, 0, 0 }, -{"entry", "l", 0xe809, 0xf81f, TRAP, 0, 0 }, -{"extend", "e", 0xf000, 0xf800, 0, 0, 0 }, -{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 }, -{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 }, -{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 }, -{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, 0 }, -{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, 0 }, -{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0, 0 }, -{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, 0 }, -{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, 0 }, -{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, 0 }, -{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, 0 }, -{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, 0 }, -{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, 0 }, +{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1 }, +{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1 }, +{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1 }, +{"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1 }, +{"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1 }, +{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1 }, +{"extend", "e", 0xf000, 0xf800, 0, 0, I1 }, +{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 }, +{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 }, +{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 }, +{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 }, +{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, I1 }, +{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0, I1 }, +{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 }, +{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 }, +{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 }, +{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 }, +{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1 }, +{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1 }, {"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 }, {"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 }, {"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 }, {"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3 }, -{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, 0 }, -{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, 0 }, -{"li", "x,U", 0x6800, 0xf800, WR_x, 0, 0 }, -{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, 0 }, -{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, 0 }, -{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, 0 }, -{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, 0 }, +{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, I1 }, +{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, I1 }, +{"li", "x,U", 0x6800, 0xf800, WR_x, 0, I1 }, +{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, I1 }, +{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, I1 }, +{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, I1 }, +{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, I1 }, {"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3 }, -{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, 0 }, -{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, 0 }, -{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, 0 }, -{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, 0 }, -{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, 0 }, -{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 }, -{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 }, -{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, 0 }, -{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, 0 }, -{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, 0 }, -{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 }, -{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, 0 }, -{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, 0 }, -{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, 0 }, -{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, 0 }, +{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, I1 }, +{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, I1 }, +{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, I1 }, +{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, I1 }, +{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1 }, +{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, I1 }, +{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, I1 }, +{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, +{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1 }, +{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 }, +{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 }, +{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, I1 }, {"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3 }, {"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, 0, I3 }, -{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, 0 }, -{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, 0 }, -{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, 0 }, -{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, 0 }, -{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, 0 }, -{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, 0 }, -{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, 0 }, -{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, 0 }, -{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, 0 }, -{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, 0 }, -{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, 0 }, -{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, 0 }, -{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, 0 }, -{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, 0 }, -{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, 0 }, -{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, 0 }, -{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, 0 }, -{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, 0 }, -{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0, 0 }, -{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0, 0 }, -{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, 0 }, -{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, 0 }, -{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, 0 }, -{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, 0 }, +{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, I1 }, +{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, I1 }, +{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, I1 }, +{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1 }, +{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, I1 }, +{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1 }, +{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1 }, +{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, I1 }, +{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1 }, +{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, I1 }, +{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, I1 }, +{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1 }, +{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, I1 }, +{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 }, +{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0, I1 }, +{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1 }, +{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1 }, +{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 }, +{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, /* MIPS16e additions */ -{"jalrc", "x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, 0 }, -{"jalrc", "R,x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, 0 }, -{"jrc", "x", 0xe880, 0xf8ff, RD_x|TRAP, 0, 0 }, -{"jrc", "R", 0xe8a0, 0xffff, RD_31|TRAP, 0, 0 }, -{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, 0 }, -{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, 0 }, -{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, 0 }, -{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, 0 }, -{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I3 }, -{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, 0 }, -{"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, 0 }, -{"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I3 }, +{"jalrc", "x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, I32 }, +{"jalrc", "R,x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, I32 }, +{"jrc", "x", 0xe880, 0xf8ff, RD_x|TRAP, 0, I32 }, +{"jrc", "R", 0xe8a0, 0xffff, RD_31|TRAP, 0, I32 }, +{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, I32 }, +{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, I32 }, +{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 }, +{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32 }, +{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32 }, +{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64 }, +{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, I32 }, +{"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, I32 }, +{"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I64 }, }; const int bfd_mips16_num_opcodes = diff --git a/contrib/binutils/opcodes/po/Make-in b/contrib/binutils/opcodes/po/Make-in index 199100d..9bc5bb1 100644 --- a/contrib/binutils/opcodes/po/Make-in +++ b/contrib/binutils/opcodes/po/Make-in @@ -16,6 +16,7 @@ SHELL = /bin/sh srcdir = @srcdir@ top_srcdir = @top_srcdir@ VPATH = @srcdir@ +top_builddir = @top_builddir@ prefix = @prefix@ exec_prefix = @exec_prefix@ @@ -72,7 +73,7 @@ INSTOBJEXT = @INSTOBJEXT@ $(MSGFMT) -o $@ $< .po.gmo: - file=$(srcdir)/`echo $* | sed 's,.*/,,'`.gmo \ + file=`echo $* | sed 's,.*/,,'`.gmo \ && rm -f $$file && $(GMSGFMT) -o $$file $< .po.cat: diff --git a/contrib/binutils/opcodes/po/POTFILES.in b/contrib/binutils/opcodes/po/POTFILES.in index 67e98c4..c8837a0 100644 --- a/contrib/binutils/opcodes/po/POTFILES.in +++ b/contrib/binutils/opcodes/po/POTFILES.in @@ -12,6 +12,8 @@ cgen-dis.c cgen-opc.c cgen-ops.h cgen-types.h +cr16-dis.c +cr16-opc.c cris-dis.c cris-opc.c crx-dis.c @@ -45,6 +47,10 @@ hppa-dis.c i370-dis.c i370-opc.c i386-dis.c +i386-gen.c +i386-opc.c +i386-opc.h +i386-tbl.h i860-dis.c i960-dis.c ia64-asmtab.c @@ -100,6 +106,13 @@ m88k-dis.c maxq-dis.c mcore-dis.c mcore-opc.h +mep-asm.c +mep-desc.c +mep-desc.h +mep-dis.c +mep-ibld.c +mep-opc.c +mep-opc.h mips16-opc.c mips-dis.c mips-opc.c @@ -131,6 +144,8 @@ ppc-opc.c s390-dis.c s390-mkopc.c s390-opc.c +score-dis.c +score-opc.h sh64-dis.c sh64-opc.c sh64-opc.h @@ -138,6 +153,8 @@ sh-dis.c sh-opc.h sparc-dis.c sparc-opc.c +spu-dis.c +spu-opc.c sysdep.h tic30-dis.c tic4x-dis.c diff --git a/contrib/binutils/opcodes/po/opcodes.pot b/contrib/binutils/opcodes/po/opcodes.pot index e387290..a988933 100644 --- a/contrib/binutils/opcodes/po/opcodes.pot +++ b/contrib/binutils/opcodes/po/opcodes.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2005-10-25 10:50+0930\n" +"POT-Creation-Date: 2007-07-01 13:40+0930\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -110,23 +110,23 @@ msgstr "" msgid "must specify .jd or no nullify suffix" msgstr "" -#: arm-dis.c:1302 +#: arm-dis.c:1807 msgid "<illegal precision>" msgstr "" #. XXX - should break 'option' at following delimiter. -#: arm-dis.c:2746 +#: arm-dis.c:3817 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "" #. XXX - should break 'option' at following delimiter. -#: arm-dis.c:2754 +#: arm-dis.c:3825 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "" -#: arm-dis.c:2916 +#: arm-dis.c:4225 #, c-format msgid "" "\n" @@ -134,24 +134,24 @@ msgid "" "the -M switch:\n" msgstr "" -#: avr-dis.c:109 avr-dis.c:119 +#: avr-dis.c:112 avr-dis.c:122 #, c-format msgid "undefined" msgstr "" -#: avr-dis.c:176 +#: avr-dis.c:184 #, c-format msgid "Internal disassembler error" msgstr "" -#: avr-dis.c:225 +#: avr-dis.c:233 #, c-format msgid "unknown constraint `%c'" msgstr "" -#: cgen-asm.c:336 fr30-ibld.c:192 frv-ibld.c:192 ip2k-ibld.c:192 -#: iq2000-ibld.c:192 m32c-ibld.c:192 m32r-ibld.c:192 ms1-ibld.c:192 -#: openrisc-ibld.c:192 xstormy16-ibld.c:192 +#: cgen-asm.c:336 fr30-ibld.c:200 frv-ibld.c:200 ip2k-ibld.c:200 +#: iq2000-ibld.c:200 m32c-ibld.c:200 m32r-ibld.c:200 mep-ibld.c:200 +#: mt-ibld.c:200 openrisc-ibld.c:200 xc16x-ibld.c:200 xstormy16-ibld.c:200 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "" @@ -177,7 +177,7 @@ msgstr "" msgid "Address 0x%s is out of bounds.\n" msgstr "" -#: fr30-asm.c:92 m32c-asm.c:782 m32c-asm.c:789 +#: fr30-asm.c:92 m32c-asm.c:876 m32c-asm.c:883 msgid "Register number is not valid" msgstr "" @@ -189,141 +189,144 @@ msgstr "" msgid "Register must be between r8 and r15" msgstr "" -#: fr30-asm.c:115 m32c-asm.c:820 +#: fr30-asm.c:115 m32c-asm.c:914 msgid "Register list is not valid" msgstr "" -#: fr30-asm.c:309 frv-asm.c:1262 ip2k-asm.c:510 iq2000-asm.c:456 -#: m32c-asm.c:1476 m32r-asm.c:323 ms1-asm.c:546 openrisc-asm.c:240 -#: xstormy16-asm.c:275 +#: fr30-asm.c:309 frv-asm.c:1262 ip2k-asm.c:510 iq2000-asm.c:458 +#: m32c-asm.c:1588 m32r-asm.c:327 mep-asm.c:1000 mt-asm.c:594 +#: openrisc-asm.c:240 xc16x-asm.c:375 xstormy16-asm.c:275 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "" -#: fr30-asm.c:357 frv-asm.c:1310 ip2k-asm.c:558 iq2000-asm.c:504 -#: m32c-asm.c:1524 m32r-asm.c:371 ms1-asm.c:594 openrisc-asm.c:288 -#: xstormy16-asm.c:323 +#: fr30-asm.c:360 frv-asm.c:1313 ip2k-asm.c:561 iq2000-asm.c:509 +#: m32c-asm.c:1639 m32r-asm.c:378 mep-asm.c:1051 mt-asm.c:645 +#: openrisc-asm.c:291 xc16x-asm.c:426 xstormy16-asm.c:326 msgid "missing mnemonic in syntax string" msgstr "" #. We couldn't parse it. -#: fr30-asm.c:492 fr30-asm.c:496 fr30-asm.c:583 fr30-asm.c:684 frv-asm.c:1445 -#: frv-asm.c:1449 frv-asm.c:1536 frv-asm.c:1637 ip2k-asm.c:693 ip2k-asm.c:697 -#: ip2k-asm.c:784 ip2k-asm.c:885 iq2000-asm.c:639 iq2000-asm.c:643 -#: iq2000-asm.c:730 iq2000-asm.c:831 m32c-asm.c:1659 m32c-asm.c:1663 -#: m32c-asm.c:1750 m32c-asm.c:1851 m32r-asm.c:506 m32r-asm.c:510 -#: m32r-asm.c:597 m32r-asm.c:698 ms1-asm.c:729 ms1-asm.c:733 ms1-asm.c:820 -#: ms1-asm.c:921 openrisc-asm.c:423 openrisc-asm.c:427 openrisc-asm.c:514 -#: openrisc-asm.c:615 xstormy16-asm.c:458 xstormy16-asm.c:462 -#: xstormy16-asm.c:549 xstormy16-asm.c:650 +#: fr30-asm.c:495 fr30-asm.c:499 fr30-asm.c:586 fr30-asm.c:687 frv-asm.c:1448 +#: frv-asm.c:1452 frv-asm.c:1539 frv-asm.c:1640 ip2k-asm.c:696 ip2k-asm.c:700 +#: ip2k-asm.c:787 ip2k-asm.c:888 iq2000-asm.c:644 iq2000-asm.c:648 +#: iq2000-asm.c:735 iq2000-asm.c:836 m32c-asm.c:1774 m32c-asm.c:1778 +#: m32c-asm.c:1865 m32c-asm.c:1966 m32r-asm.c:513 m32r-asm.c:517 +#: m32r-asm.c:604 m32r-asm.c:705 mep-asm.c:1186 mep-asm.c:1190 mep-asm.c:1277 +#: mep-asm.c:1378 mt-asm.c:780 mt-asm.c:784 mt-asm.c:871 mt-asm.c:972 +#: openrisc-asm.c:426 openrisc-asm.c:430 openrisc-asm.c:517 openrisc-asm.c:618 +#: xc16x-asm.c:561 xc16x-asm.c:565 xc16x-asm.c:652 xc16x-asm.c:753 +#: xstormy16-asm.c:461 xstormy16-asm.c:465 xstormy16-asm.c:552 +#: xstormy16-asm.c:653 msgid "unrecognized instruction" msgstr "" -#: fr30-asm.c:539 frv-asm.c:1492 ip2k-asm.c:740 iq2000-asm.c:686 -#: m32c-asm.c:1706 m32r-asm.c:553 ms1-asm.c:776 openrisc-asm.c:470 -#: xstormy16-asm.c:505 +#: fr30-asm.c:542 frv-asm.c:1495 ip2k-asm.c:743 iq2000-asm.c:691 +#: m32c-asm.c:1821 m32r-asm.c:560 mep-asm.c:1233 mt-asm.c:827 +#: openrisc-asm.c:473 xc16x-asm.c:608 xstormy16-asm.c:508 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "" -#: fr30-asm.c:549 frv-asm.c:1502 ip2k-asm.c:750 iq2000-asm.c:696 -#: m32c-asm.c:1716 m32r-asm.c:563 ms1-asm.c:786 openrisc-asm.c:480 -#: xstormy16-asm.c:515 +#: fr30-asm.c:552 frv-asm.c:1505 ip2k-asm.c:753 iq2000-asm.c:701 +#: m32c-asm.c:1831 m32r-asm.c:570 mep-asm.c:1243 mt-asm.c:837 +#: openrisc-asm.c:483 xc16x-asm.c:618 xstormy16-asm.c:518 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "" -#: fr30-asm.c:577 frv-asm.c:1530 ip2k-asm.c:778 iq2000-asm.c:724 -#: m32c-asm.c:1744 m32r-asm.c:591 ms1-asm.c:814 openrisc-asm.c:508 -#: xstormy16-asm.c:543 +#: fr30-asm.c:580 frv-asm.c:1533 ip2k-asm.c:781 iq2000-asm.c:729 +#: m32c-asm.c:1859 m32r-asm.c:598 mep-asm.c:1271 mt-asm.c:865 +#: openrisc-asm.c:511 xc16x-asm.c:646 xstormy16-asm.c:546 msgid "junk at end of line" msgstr "" -#: fr30-asm.c:683 frv-asm.c:1636 ip2k-asm.c:884 iq2000-asm.c:830 -#: m32c-asm.c:1850 m32r-asm.c:697 ms1-asm.c:920 openrisc-asm.c:614 -#: xstormy16-asm.c:649 +#: fr30-asm.c:686 frv-asm.c:1639 ip2k-asm.c:887 iq2000-asm.c:835 +#: m32c-asm.c:1965 m32r-asm.c:704 mep-asm.c:1377 mt-asm.c:971 +#: openrisc-asm.c:617 xc16x-asm.c:752 xstormy16-asm.c:652 msgid "unrecognized form of instruction" msgstr "" -#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:842 -#: m32c-asm.c:1862 m32r-asm.c:709 ms1-asm.c:932 openrisc-asm.c:626 -#: xstormy16-asm.c:661 +#: fr30-asm.c:698 frv-asm.c:1651 ip2k-asm.c:899 iq2000-asm.c:847 +#: m32c-asm.c:1977 m32r-asm.c:716 mep-asm.c:1389 mt-asm.c:983 +#: openrisc-asm.c:629 xc16x-asm.c:764 xstormy16-asm.c:664 #, c-format msgid "bad instruction `%.50s...'" msgstr "" -#: fr30-asm.c:698 frv-asm.c:1651 ip2k-asm.c:899 iq2000-asm.c:845 -#: m32c-asm.c:1865 m32r-asm.c:712 ms1-asm.c:935 openrisc-asm.c:629 -#: xstormy16-asm.c:664 +#: fr30-asm.c:701 frv-asm.c:1654 ip2k-asm.c:902 iq2000-asm.c:850 +#: m32c-asm.c:1980 m32r-asm.c:719 mep-asm.c:1392 mt-asm.c:986 +#: openrisc-asm.c:632 xc16x-asm.c:767 xstormy16-asm.c:667 #, c-format msgid "bad instruction `%.50s'" msgstr "" #. Default text to print if an instruction isn't recognized. #: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32c-dis.c:41 -#: m32r-dis.c:41 mmix-dis.c:278 ms1-dis.c:41 openrisc-dis.c:41 -#: xstormy16-dis.c:41 +#: m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:278 mt-dis.c:41 openrisc-dis.c:41 +#: xc16x-dis.c:41 xstormy16-dis.c:41 msgid "*unknown*" msgstr "" -#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 m32c-dis.c:860 -#: m32r-dis.c:256 ms1-dis.c:258 openrisc-dis.c:135 xstormy16-dis.c:168 +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 m32c-dis.c:891 +#: m32r-dis.c:256 mep-dis.c:776 mt-dis.c:290 openrisc-dis.c:135 +#: xc16x-dis.c:375 xstormy16-dis.c:168 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "" #: fr30-ibld.c:163 frv-ibld.c:163 ip2k-ibld.c:163 iq2000-ibld.c:163 -#: m32c-ibld.c:163 m32r-ibld.c:163 ms1-ibld.c:163 openrisc-ibld.c:163 -#: xstormy16-ibld.c:163 +#: m32c-ibld.c:163 m32r-ibld.c:163 mep-ibld.c:163 mt-ibld.c:163 +#: openrisc-ibld.c:163 xc16x-ibld.c:163 xstormy16-ibld.c:163 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" msgstr "" -#: fr30-ibld.c:176 frv-ibld.c:176 ip2k-ibld.c:176 iq2000-ibld.c:176 -#: m32c-ibld.c:176 m32r-ibld.c:176 ms1-ibld.c:176 openrisc-ibld.c:176 -#: xstormy16-ibld.c:176 +#: fr30-ibld.c:184 frv-ibld.c:184 ip2k-ibld.c:184 iq2000-ibld.c:184 +#: m32c-ibld.c:184 m32r-ibld.c:184 mep-ibld.c:184 mt-ibld.c:184 +#: openrisc-ibld.c:184 xc16x-ibld.c:184 xstormy16-ibld.c:184 #, c-format -msgid "operand out of range (%lu not between 0 and %lu)" +msgid "operand out of range (0x%lx not between 0 and 0x%lx)" msgstr "" -#: fr30-ibld.c:719 frv-ibld.c:845 ip2k-ibld.c:596 iq2000-ibld.c:702 -#: m32c-ibld.c:1668 m32r-ibld.c:654 ms1-ibld.c:713 openrisc-ibld.c:622 -#: xstormy16-ibld.c:667 +#: fr30-ibld.c:726 frv-ibld.c:852 ip2k-ibld.c:603 iq2000-ibld.c:709 +#: m32c-ibld.c:1727 m32r-ibld.c:661 mep-ibld.c:1024 mt-ibld.c:745 +#: openrisc-ibld.c:629 xc16x-ibld.c:748 xstormy16-ibld.c:674 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "" -#: fr30-ibld.c:924 frv-ibld.c:1162 ip2k-ibld.c:671 iq2000-ibld.c:877 -#: m32c-ibld.c:2780 m32r-ibld.c:791 ms1-ibld.c:907 openrisc-ibld.c:722 -#: xstormy16-ibld.c:813 +#: fr30-ibld.c:931 frv-ibld.c:1169 ip2k-ibld.c:678 iq2000-ibld.c:884 +#: m32c-ibld.c:2888 m32r-ibld.c:798 mep-ibld.c:1444 mt-ibld.c:965 +#: openrisc-ibld.c:729 xc16x-ibld.c:968 xstormy16-ibld.c:820 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "" -#: fr30-ibld.c:1070 frv-ibld.c:1440 ip2k-ibld.c:745 iq2000-ibld.c:1008 -#: m32c-ibld.c:3379 m32r-ibld.c:904 ms1-ibld.c:1086 openrisc-ibld.c:799 -#: xstormy16-ibld.c:923 +#: fr30-ibld.c:1077 frv-ibld.c:1447 ip2k-ibld.c:752 iq2000-ibld.c:1015 +#: m32c-ibld.c:3505 m32r-ibld.c:911 mep-ibld.c:1737 mt-ibld.c:1165 +#: openrisc-ibld.c:806 xc16x-ibld.c:1189 xstormy16-ibld.c:930 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "" -#: fr30-ibld.c:1198 frv-ibld.c:1700 ip2k-ibld.c:801 iq2000-ibld.c:1121 -#: m32c-ibld.c:3960 m32r-ibld.c:999 ms1-ibld.c:1247 openrisc-ibld.c:858 -#: xstormy16-ibld.c:1015 +#: fr30-ibld.c:1205 frv-ibld.c:1707 ip2k-ibld.c:808 iq2000-ibld.c:1128 +#: m32c-ibld.c:4104 m32r-ibld.c:1006 mep-ibld.c:2012 mt-ibld.c:1347 +#: openrisc-ibld.c:865 xc16x-ibld.c:1392 xstormy16-ibld.c:1022 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "" -#: fr30-ibld.c:1329 frv-ibld.c:1967 ip2k-ibld.c:860 iq2000-ibld.c:1241 -#: m32c-ibld.c:4529 m32r-ibld.c:1100 ms1-ibld.c:1415 openrisc-ibld.c:924 -#: xstormy16-ibld.c:1114 +#: fr30-ibld.c:1336 frv-ibld.c:1974 ip2k-ibld.c:867 iq2000-ibld.c:1248 +#: m32c-ibld.c:4691 m32r-ibld.c:1107 mep-ibld.c:2271 mt-ibld.c:1536 +#: openrisc-ibld.c:931 xc16x-ibld.c:1596 xstormy16-ibld.c:1121 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "" -#: fr30-ibld.c:1450 frv-ibld.c:2224 ip2k-ibld.c:909 iq2000-ibld.c:1351 -#: m32c-ibld.c:5088 m32r-ibld.c:1191 ms1-ibld.c:1573 openrisc-ibld.c:980 -#: xstormy16-ibld.c:1203 +#: fr30-ibld.c:1457 frv-ibld.c:2231 ip2k-ibld.c:916 iq2000-ibld.c:1358 +#: m32c-ibld.c:5268 m32r-ibld.c:1198 mep-ibld.c:2520 mt-ibld.c:1715 +#: openrisc-ibld.c:987 xc16x-ibld.c:1790 xstormy16-ibld.c:1210 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" @@ -346,8 +349,9 @@ msgstr "" #. -- assembler routines inserted here. #. -- asm.c -#: frv-asm.c:971 iq2000-asm.c:55 m32c-asm.c:140 m32c-asm.c:211 m32c-asm.c:253 -#: m32c-asm.c:312 m32c-asm.c:334 m32r-asm.c:52 openrisc-asm.c:53 +#: frv-asm.c:971 iq2000-asm.c:55 m32c-asm.c:140 m32c-asm.c:236 m32c-asm.c:278 +#: m32c-asm.c:337 m32c-asm.c:359 m32r-asm.c:52 mep-asm.c:231 mep-asm.c:249 +#: mep-asm.c:264 mep-asm.c:279 mep-asm.c:291 openrisc-asm.c:53 msgid "missing `)'" msgstr "" @@ -372,116 +376,188 @@ msgstr "" msgid "%02x\t\t*unknown*" msgstr "" -#: i386-dis.c:1742 +#: i386-dis.c:3194 msgid "<internal disassembler error>" msgstr "" -#: ia64-gen.c:297 +#: i386-dis.c:3421 +#, c-format +msgid "" +"\n" +"The following i386/x86-64 specific disassembler options are supported for " +"use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" + +#: i386-dis.c:3425 +#, c-format +msgid " x86-64 Disassemble in 64bit mode\n" +msgstr "" + +#: i386-dis.c:3426 +#, c-format +msgid " i386 Disassemble in 32bit mode\n" +msgstr "" + +#: i386-dis.c:3427 +#, c-format +msgid " i8086 Disassemble in 16bit mode\n" +msgstr "" + +#: i386-dis.c:3428 +#, c-format +msgid " att Display instruction in AT&T syntax\n" +msgstr "" + +#: i386-dis.c:3429 +#, c-format +msgid " intel Display instruction in Intel syntax\n" +msgstr "" + +#: i386-dis.c:3430 +#, c-format +msgid " addr64 Assume 64bit address size\n" +msgstr "" + +#: i386-dis.c:3431 +#, c-format +msgid " addr32 Assume 32bit address size\n" +msgstr "" + +#: i386-dis.c:3432 +#, c-format +msgid " addr16 Assume 16bit address size\n" +msgstr "" + +#: i386-dis.c:3433 +#, c-format +msgid " data32 Assume 32bit data size\n" +msgstr "" + +#: i386-dis.c:3434 +#, c-format +msgid " data16 Assume 16bit data size\n" +msgstr "" + +#: i386-dis.c:3435 +#, c-format +msgid " suffix Always display instruction suffix in AT&T syntax\n" +msgstr "" + +#: i386-gen.c:41 ia64-gen.c:306 #, c-format msgid "%s: Error: " msgstr "" -#: ia64-gen.c:310 +#: i386-gen.c:108 +msgid "can't find i386-opc.tbl for reading\n" +msgstr "" + +#: i386-gen.c:259 +msgid "can't find i386-reg.tbl for reading\n" +msgstr "" + +#: i386-gen.c:385 ia64-gen.c:2840 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "" + +#: ia64-gen.c:319 #, c-format msgid "%s: Warning: " msgstr "" -#: ia64-gen.c:496 ia64-gen.c:730 +#: ia64-gen.c:505 ia64-gen.c:739 #, c-format msgid "multiple note %s not handled\n" msgstr "" -#: ia64-gen.c:607 +#: ia64-gen.c:616 msgid "can't find ia64-ic.tbl for reading\n" msgstr "" -#: ia64-gen.c:812 +#: ia64-gen.c:821 #, c-format msgid "can't find %s for reading\n" msgstr "" -#: ia64-gen.c:1036 +#: ia64-gen.c:1045 #, c-format msgid "" "most recent format '%s'\n" "appears more restrictive than '%s'\n" msgstr "" -#: ia64-gen.c:1047 +#: ia64-gen.c:1056 #, c-format msgid "overlapping field %s->%s\n" msgstr "" -#: ia64-gen.c:1244 +#: ia64-gen.c:1253 #, c-format msgid "overwriting note %d with note %d (IC:%s)\n" msgstr "" -#: ia64-gen.c:1443 +#: ia64-gen.c:1454 #, c-format msgid "don't know how to specify %% dependency %s\n" msgstr "" -#: ia64-gen.c:1465 +#: ia64-gen.c:1476 #, c-format msgid "Don't know how to specify # dependency %s\n" msgstr "" -#: ia64-gen.c:1504 +#: ia64-gen.c:1515 #, c-format msgid "IC:%s [%s] has no terminals or sub-classes\n" msgstr "" -#: ia64-gen.c:1507 +#: ia64-gen.c:1518 #, c-format msgid "IC:%s has no terminals or sub-classes\n" msgstr "" -#: ia64-gen.c:1516 +#: ia64-gen.c:1527 #, c-format msgid "no insns mapped directly to terminal IC %s [%s]" msgstr "" -#: ia64-gen.c:1519 +#: ia64-gen.c:1530 #, c-format msgid "no insns mapped directly to terminal IC %s\n" msgstr "" -#: ia64-gen.c:1530 +#: ia64-gen.c:1541 #, c-format msgid "class %s is defined but not used\n" msgstr "" -#: ia64-gen.c:1541 +#: ia64-gen.c:1552 #, c-format msgid "Warning: rsrc %s (%s) has no chks%s\n" msgstr "" -#: ia64-gen.c:1545 +#: ia64-gen.c:1556 #, c-format msgid "rsrc %s (%s) has no regs\n" msgstr "" -#: ia64-gen.c:2444 +#: ia64-gen.c:2468 #, c-format msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" msgstr "" -#: ia64-gen.c:2472 +#: ia64-gen.c:2496 #, c-format msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" msgstr "" -#: ia64-gen.c:2486 +#: ia64-gen.c:2510 #, c-format msgid "opcode %s has no class (ops %d %d %d)\n" msgstr "" -#: ia64-gen.c:2816 -#, c-format -msgid "unable to change directory to \"%s\", errno = %s\n" -msgstr "" - #. We've been passed a w. Return with an error message so that #. cgen will try the next parsing option. #: ip2k-asm.c:80 @@ -565,7 +641,7 @@ msgstr "" msgid "%dsp8() takes a symbolic address, not a number" msgstr "" -#: m32c-asm.c:159 m32c-asm.c:163 m32c-asm.c:229 +#: m32c-asm.c:159 m32c-asm.c:163 m32c-asm.c:254 msgid "dsp:8 immediate is out of range" msgstr "" @@ -573,57 +649,69 @@ msgstr "" msgid "Immediate is out of range -8 to 7" msgstr "" -#: m32c-asm.c:259 +#: m32c-asm.c:209 m32c-asm.c:213 +msgid "Immediate is out of range -7 to 8" +msgstr "" + +#: m32c-asm.c:284 #, c-format msgid "%dsp16() takes a symbolic address, not a number" msgstr "" -#: m32c-asm.c:282 m32c-asm.c:289 m32c-asm.c:352 +#: m32c-asm.c:307 m32c-asm.c:314 m32c-asm.c:377 msgid "dsp:16 immediate is out of range" msgstr "" -#: m32c-asm.c:378 +#: m32c-asm.c:403 msgid "dsp:20 immediate is out of range" msgstr "" -#: m32c-asm.c:404 +#: m32c-asm.c:429 m32c-asm.c:449 msgid "dsp:24 immediate is out of range" msgstr "" -#: m32c-asm.c:437 +#: m32c-asm.c:482 msgid "immediate is out of range 1-2" msgstr "" -#: m32c-asm.c:455 +#: m32c-asm.c:500 msgid "immediate is out of range 1-8" msgstr "" -#: m32c-asm.c:491 +#: m32c-asm.c:518 +msgid "immediate is out of range 0-7" +msgstr "" + +#: m32c-asm.c:554 msgid "immediate is out of range 2-9" msgstr "" -#: m32c-asm.c:509 +#: m32c-asm.c:572 msgid "Bit number for indexing general register is out of range 0-15" msgstr "" -#: m32c-asm.c:541 m32c-asm.c:576 +#: m32c-asm.c:610 m32c-asm.c:666 msgid "bit,base is out of range" msgstr "" -#: m32c-asm.c:712 +#: m32c-asm.c:617 m32c-asm.c:622 m32c-asm.c:670 +msgid "bit,base out of range for symbol" +msgstr "" + +#: m32c-asm.c:806 msgid "not a valid r0l/r0h pair" msgstr "" -#: m32c-asm.c:742 +#: m32c-asm.c:836 msgid "Invalid size specifier" msgstr "" -#: m68k-dis.c:1162 +#: m68k-dis.c:1167 #, c-format msgid "<function code %d>" msgstr "" -#: m68k-dis.c:1313 +#: m68k-dis.c:1322 #, c-format msgid "<internal error in opcode table: %s %s>\n" msgstr "" @@ -633,26 +721,39 @@ msgstr "" msgid "# <dis error: %08lx>" msgstr "" -#: mips-dis.c:718 +#: mep-asm.c:113 +msgid "Only $tp or $13 allowed for this opcode" +msgstr "" + +#: mep-asm.c:127 +msgid "Only $sp or $15 allowed for this opcode" +msgstr "" + +#: mep-asm.c:298 mep-asm.c:454 +#, c-format +msgid "invalid %function() here" +msgstr "" + +#: mips-dis.c:745 msgid "# internal error, incomplete extension sequence (+)" msgstr "" -#: mips-dis.c:805 +#: mips-dis.c:852 #, c-format msgid "# internal error, undefined extension sequence (+%c)" msgstr "" -#: mips-dis.c:1153 +#: mips-dis.c:1211 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "" -#: mips-dis.c:1663 +#: mips-dis.c:1818 #, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" msgstr "" -#: mips-dis.c:1894 +#: mips-dis.c:2049 #, c-format msgid "" "\n" @@ -660,7 +761,7 @@ msgid "" "with the -M switch (multiple options should be separated by commas):\n" msgstr "" -#: mips-dis.c:1898 +#: mips-dis.c:2053 #, c-format msgid "" "\n" @@ -668,7 +769,7 @@ msgid "" " Default: based on binary being disassembled.\n" msgstr "" -#: mips-dis.c:1902 +#: mips-dis.c:2057 #, c-format msgid "" "\n" @@ -676,7 +777,7 @@ msgid "" " Default: numeric.\n" msgstr "" -#: mips-dis.c:1906 +#: mips-dis.c:2061 #, c-format msgid "" "\n" @@ -685,7 +786,7 @@ msgid "" " Default: based on binary being disassembled.\n" msgstr "" -#: mips-dis.c:1911 +#: mips-dis.c:2066 #, c-format msgid "" "\n" @@ -694,7 +795,7 @@ msgid "" " Default: based on binary being disassembled.\n" msgstr "" -#: mips-dis.c:1916 +#: mips-dis.c:2071 #, c-format msgid "" "\n" @@ -702,7 +803,7 @@ msgid "" " specified ABI.\n" msgstr "" -#: mips-dis.c:1920 +#: mips-dis.c:2075 #, c-format msgid "" "\n" @@ -710,7 +811,7 @@ msgid "" " specified architecture.\n" msgstr "" -#: mips-dis.c:1924 +#: mips-dis.c:2079 #, c-format msgid "" "\n" @@ -718,12 +819,12 @@ msgid "" " " msgstr "" -#: mips-dis.c:1929 mips-dis.c:1937 mips-dis.c:1939 +#: mips-dis.c:2084 mips-dis.c:2092 mips-dis.c:2094 #, c-format msgid "\n" msgstr "" -#: mips-dis.c:1931 +#: mips-dis.c:2086 #, c-format msgid "" "\n" @@ -750,20 +851,20 @@ msgstr "" msgid "*unknown operands type: %d*" msgstr "" -#: ms1-asm.c:84 ms1-asm.c:162 +#: mt-asm.c:109 mt-asm.c:189 msgid "Operand out of range. Must be between -32768 and 32767." msgstr "" -#: ms1-asm.c:121 +#: mt-asm.c:148 msgid "Biiiig Trouble in parse_imm16!" msgstr "" -#: ms1-asm.c:129 +#: mt-asm.c:156 #, c-format msgid "%operator operand is not a symbol" msgstr "" -#: ms1-asm.c:367 +#: mt-asm.c:394 msgid "invalid operand. type may have values 0,1,2 only." msgstr "" @@ -777,111 +878,63 @@ msgstr "" msgid "$<undefined>" msgstr "" -#: ppc-opc.c:800 ppc-opc.c:828 +#: ppc-opc.c:782 ppc-opc.c:810 msgid "invalid conditional option" msgstr "" -#: ppc-opc.c:830 +#: ppc-opc.c:812 msgid "attempt to set y bit when using + or - modifier" msgstr "" -#: ppc-opc.c:858 -msgid "offset not a multiple of 16" -msgstr "" - -#: ppc-opc.c:877 -msgid "offset not a multiple of 2" -msgstr "" - -#: ppc-opc.c:879 -msgid "offset greater than 62" -msgstr "" - -#: ppc-opc.c:898 ppc-opc.c:943 ppc-opc.c:987 -msgid "offset not a multiple of 4" -msgstr "" - -#: ppc-opc.c:900 -msgid "offset greater than 124" -msgstr "" - -#: ppc-opc.c:919 -msgid "offset not a multiple of 8" -msgstr "" - -#: ppc-opc.c:921 -msgid "offset greater than 248" -msgstr "" - -#: ppc-opc.c:964 -msgid "offset not between -2048 and 2047" -msgstr "" - -#: ppc-opc.c:985 -msgid "offset not between -8192 and 8191" -msgstr "" - -#: ppc-opc.c:1013 +#: ppc-opc.c:844 msgid "invalid mask field" msgstr "" -#: ppc-opc.c:1039 +#: ppc-opc.c:870 msgid "ignoring invalid mfcr mask" msgstr "" -#: ppc-opc.c:1081 -msgid "ignoring least significant bits in branch offset" -msgstr "" - -#: ppc-opc.c:1111 ppc-opc.c:1146 +#: ppc-opc.c:920 ppc-opc.c:955 msgid "illegal bitmask" msgstr "" -#: ppc-opc.c:1211 -msgid "value out of range" -msgstr "" - -#: ppc-opc.c:1279 +#: ppc-opc.c:1075 msgid "index register in load range" msgstr "" -#: ppc-opc.c:1295 +#: ppc-opc.c:1091 msgid "source and target register operands must be different" msgstr "" -#: ppc-opc.c:1310 +#: ppc-opc.c:1106 msgid "invalid register operand when updating" msgstr "" -#: ppc-opc.c:1349 -msgid "target register operand must be even" -msgstr "" - -#: ppc-opc.c:1363 -msgid "source register operand must be even" +#: ppc-opc.c:1188 +msgid "invalid sprg number" msgstr "" -#: ppc-opc.c:1420 -msgid "invalid sprg number" +#: score-dis.c:220 score-dis.c:383 +msgid "<illegal instruction>" msgstr "" -#: sparc-dis.c:269 +#: sparc-dis.c:280 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:280 +#: sparc-dis.c:291 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:330 +#: sparc-dis.c:341 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "" #. Mark as non-valid instruction. -#: sparc-dis.c:984 +#: sparc-dis.c:1011 msgid "unknown" msgstr "" @@ -944,6 +997,30 @@ msgstr "" msgid "immediate value must be even" msgstr "" +#: xc16x-asm.c:65 +msgid "Missing '#' prefix" +msgstr "" + +#: xc16x-asm.c:81 +msgid "Missing '.' prefix" +msgstr "" + +#: xc16x-asm.c:97 +msgid "Missing 'pof:' prefix" +msgstr "" + +#: xc16x-asm.c:113 +msgid "Missing 'pag:' prefix" +msgstr "" + +#: xc16x-asm.c:129 +msgid "Missing 'sof:' prefix" +msgstr "" + +#: xc16x-asm.c:145 +msgid "Missing 'seg:' prefix" +msgstr "" + #: xstormy16-asm.c:70 msgid "Bad register in preincrement" msgstr "" diff --git a/contrib/binutils/opcodes/ppc-dis.c b/contrib/binutils/opcodes/ppc-dis.c index 35875d1..2545a36 100644 --- a/contrib/binutils/opcodes/ppc-dis.c +++ b/contrib/binutils/opcodes/ppc-dis.c @@ -1,5 +1,5 @@ /* ppc-dis.c -- Disassemble PowerPC instructions - Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005 + Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support @@ -61,6 +61,10 @@ powerpc_dialect (struct disassemble_info *info) else if (info->disassembler_options && strstr (info->disassembler_options, "e300") != NULL) dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON; + else if (info->disassembler_options + && strstr (info->disassembler_options, "440") != NULL) + dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32 + | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI; else dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC); @@ -74,6 +78,14 @@ powerpc_dialect (struct disassemble_info *info) dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5; if (info->disassembler_options + && strstr (info->disassembler_options, "cell") != NULL) + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; + + if (info->disassembler_options + && strstr (info->disassembler_options, "power6") != NULL) + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; + + if (info->disassembler_options && strstr (info->disassembler_options, "any") != NULL) dialect |= PPC_OPCODE_ANY; @@ -115,6 +127,56 @@ print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); } +/* Extract the operand value from the PowerPC or POWER instruction. */ + +static long +operand_value_powerpc (const struct powerpc_operand *operand, + unsigned long insn, int dialect) +{ + long value; + int invalid; + /* Extract the value from the instruction. */ + if (operand->extract) + value = (*operand->extract) (insn, dialect, &invalid); + else + { + value = (insn >> operand->shift) & operand->bitm; + if ((operand->flags & PPC_OPERAND_SIGNED) != 0) + { + /* BITM is always some number of zeros followed by some + number of ones, followed by some numer of zeros. */ + unsigned long top = operand->bitm; + /* top & -top gives the rightmost 1 bit, so this + fills in any trailing zeros. */ + top |= (top & -top) - 1; + top &= ~(top >> 1); + value = (value ^ top) - top; + } + } + + return value; +} + +/* Determine whether the optional operand(s) should be printed. */ + +static int +skip_optional_operands (const unsigned char *opindex, + unsigned long insn, int dialect) +{ + const struct powerpc_operand *operand; + + for (; *opindex != 0; opindex++) + { + operand = &powerpc_operands[*opindex]; + if ((operand->flags & PPC_OPERAND_NEXT) != 0 + || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 + && operand_value_powerpc (operand, insn, dialect) != 0)) + return 0; + } + + return 1; +} + /* Print a PowerPC or POWER instruction. */ static int @@ -160,6 +222,7 @@ print_insn_powerpc (bfd_vma memaddr, int invalid; int need_comma; int need_paren; + int skip_optional; table_op = PPC_OP (opcode->opcode); if (op < table_op) @@ -193,6 +256,7 @@ print_insn_powerpc (bfd_vma memaddr, /* Now extract and print the operands. */ need_comma = 0; need_paren = 0; + skip_optional = -1; for (opindex = opcode->operands; *opindex != 0; opindex++) { long value; @@ -205,23 +269,18 @@ print_insn_powerpc (bfd_vma memaddr, if ((operand->flags & PPC_OPERAND_FAKE) != 0) continue; - /* Extract the value from the instruction. */ - if (operand->extract) - value = (*operand->extract) (insn, dialect, &invalid); - else + /* If all of the optional operands have the value zero, + then don't print any of them. */ + if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) { - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & PPC_OPERAND_SIGNED) != 0 - && (value & (1 << (operand->bits - 1))) != 0) - value -= 1 << operand->bits; + if (skip_optional < 0) + skip_optional = skip_optional_operands (opindex, insn, + dialect); + if (skip_optional) + continue; } - /* If the operand is optional, and the value is zero, don't - print anything. */ - if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 - && (operand->flags & PPC_OPERAND_NEXT) == 0 - && value == 0) - continue; + value = operand_value_powerpc (operand, insn, dialect); if (need_comma) { @@ -246,7 +305,7 @@ print_insn_powerpc (bfd_vma memaddr, (*info->fprintf_func) (info->stream, "%ld", value); else { - if (operand->bits == 3) + if (operand->bitm == 7) (*info->fprintf_func) (info->stream, "cr%ld", value); else { @@ -303,9 +362,11 @@ the -M switch:\n"); fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n"); fprintf (stream, " e300 Disassemble the e300 instructions\n"); fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n"); + fprintf (stream, " 440 Disassemble the 440 instructions\n"); fprintf (stream, " efs Disassemble the EFS instructions\n"); fprintf (stream, " power4 Disassemble the Power4 instructions\n"); fprintf (stream, " power5 Disassemble the Power5 instructions\n"); + fprintf (stream, " power6 Disassemble the Power6 instructions\n"); fprintf (stream, " 32 Do not disassemble 64-bit instructions\n"); fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n"); } diff --git a/contrib/binutils/opcodes/ppc-opc.c b/contrib/binutils/opcodes/ppc-opc.c index 84e6d6a..5995f81 100644 --- a/contrib/binutils/opcodes/ppc-opc.c +++ b/contrib/binutils/opcodes/ppc-opc.c @@ -1,6 +1,6 @@ /* ppc-opc.c -- PowerPC opcode list Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, - 2005 Free Software Foundation, Inc. + 2005, 2006, 2007 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -42,8 +42,6 @@ static unsigned long insert_bat (unsigned long, long, int, const char **); static long extract_bat (unsigned long, int, int *); static unsigned long insert_bba (unsigned long, long, int, const char **); static long extract_bba (unsigned long, int, int *); -static unsigned long insert_bd (unsigned long, long, int, const char **); -static long extract_bd (unsigned long, int, int *); static unsigned long insert_bdm (unsigned long, long, int, const char **); static long extract_bdm (unsigned long, int, int *); static unsigned long insert_bdp (unsigned long, long, int, const char **); @@ -52,23 +50,12 @@ static unsigned long insert_bo (unsigned long, long, int, const char **); static long extract_bo (unsigned long, int, int *); static unsigned long insert_boe (unsigned long, long, int, const char **); static long extract_boe (unsigned long, int, int *); -static unsigned long insert_dq (unsigned long, long, int, const char **); -static long extract_dq (unsigned long, int, int *); -static unsigned long insert_ds (unsigned long, long, int, const char **); -static long extract_ds (unsigned long, int, int *); -static unsigned long insert_de (unsigned long, long, int, const char **); -static long extract_de (unsigned long, int, int *); -static unsigned long insert_des (unsigned long, long, int, const char **); -static long extract_des (unsigned long, int, int *); static unsigned long insert_fxm (unsigned long, long, int, const char **); static long extract_fxm (unsigned long, int, int *); -static unsigned long insert_li (unsigned long, long, int, const char **); -static long extract_li (unsigned long, int, int *); static unsigned long insert_mbe (unsigned long, long, int, const char **); static long extract_mbe (unsigned long, int, int *); static unsigned long insert_mb6 (unsigned long, long, int, const char **); static long extract_mb6 (unsigned long, int, int *); -static unsigned long insert_nb (unsigned long, long, int, const char **); static long extract_nb (unsigned long, int, int *); static unsigned long insert_nsi (unsigned long, long, int, const char **); static long extract_nsi (unsigned long, int, int *); @@ -78,8 +65,6 @@ static unsigned long insert_raq (unsigned long, long, int, const char **); static unsigned long insert_ras (unsigned long, long, int, const char **); static unsigned long insert_rbs (unsigned long, long, int, const char **); static long extract_rbs (unsigned long, int, int *); -static unsigned long insert_rsq (unsigned long, long, int, const char **); -static unsigned long insert_rtq (unsigned long, long, int, const char **); static unsigned long insert_sh6 (unsigned long, long, int, const char **); static long extract_sh6 (unsigned long, int, int *); static unsigned long insert_spr (unsigned long, long, int, const char **); @@ -88,16 +73,10 @@ static unsigned long insert_sprg (unsigned long, long, int, const char **); static long extract_sprg (unsigned long, int, int *); static unsigned long insert_tbr (unsigned long, long, int, const char **); static long extract_tbr (unsigned long, int, int *); -static unsigned long insert_ev2 (unsigned long, long, int, const char **); -static long extract_ev2 (unsigned long, int, int *); -static unsigned long insert_ev4 (unsigned long, long, int, const char **); -static long extract_ev4 (unsigned long, int, int *); -static unsigned long insert_ev8 (unsigned long, long, int, const char **); -static long extract_ev8 (unsigned long, int, int *); /* The operands table. - The fields are bits, shift, insert, extract, flags. + The fields are bitm, shift, insert, extract, flags. We used to put parens around the various additions, like the one for BA just below. However, that caused trouble with feeble @@ -115,302 +94,298 @@ const struct powerpc_operand powerpc_operands[] = /* The BA field in an XL form instruction. */ #define BA UNUSED + 1 -#define BA_MASK (0x1f << 16) - { 5, 16, NULL, NULL, PPC_OPERAND_CR }, + /* The BI field in a B form or XL form instruction. */ +#define BI BA +#define BI_MASK (0x1f << 16) + { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, /* The BA field in an XL form instruction when it must be the same as the BT field in the same instruction. */ #define BAT BA + 1 - { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, + { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, /* The BB field in an XL form instruction. */ #define BB BAT + 1 #define BB_MASK (0x1f << 11) - { 5, 11, NULL, NULL, PPC_OPERAND_CR }, + { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, /* The BB field in an XL form instruction when it must be the same as the BA field in the same instruction. */ #define BBA BB + 1 - { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, + { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, /* The BD field in a B form instruction. The lower two bits are forced to zero. */ #define BD BBA + 1 - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, /* The BD field in a B form instruction when absolute addressing is used. */ #define BDA BD + 1 - { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, /* The BD field in a B form instruction when the - modifier is used. This sets the y bit of the BO field appropriately. */ #define BDM BDA + 1 - { 16, 0, insert_bdm, extract_bdm, + { 0xfffc, 0, insert_bdm, extract_bdm, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, /* The BD field in a B form instruction when the - modifier is used and absolute address is used. */ #define BDMA BDM + 1 - { 16, 0, insert_bdm, extract_bdm, + { 0xfffc, 0, insert_bdm, extract_bdm, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, /* The BD field in a B form instruction when the + modifier is used. This sets the y bit of the BO field appropriately. */ #define BDP BDMA + 1 - { 16, 0, insert_bdp, extract_bdp, + { 0xfffc, 0, insert_bdp, extract_bdp, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, /* The BD field in a B form instruction when the + modifier is used and absolute addressing is used. */ #define BDPA BDP + 1 - { 16, 0, insert_bdp, extract_bdp, + { 0xfffc, 0, insert_bdp, extract_bdp, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, /* The BF field in an X or XL form instruction. */ #define BF BDPA + 1 - { 3, 23, NULL, NULL, PPC_OPERAND_CR }, + /* The CRFD field in an X form instruction. */ +#define CRFD BF + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, + + /* The BF field in an X or XL form instruction. */ +#define BFF BF + 1 + { 0x7, 23, NULL, NULL, 0 }, /* An optional BF field. This is used for comparison instructions, in which an omitted BF field is taken as zero. */ -#define OBF BF + 1 - { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, +#define OBF BFF + 1 + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, /* The BFA field in an X or XL form instruction. */ #define BFA OBF + 1 - { 3, 18, NULL, NULL, PPC_OPERAND_CR }, - - /* The BI field in a B form or XL form instruction. */ -#define BI BFA + 1 -#define BI_MASK (0x1f << 16) - { 5, 16, NULL, NULL, PPC_OPERAND_CR }, + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, /* The BO field in a B form instruction. Certain values are illegal. */ -#define BO BI + 1 +#define BO BFA + 1 #define BO_MASK (0x1f << 21) - { 5, 21, insert_bo, extract_bo, 0 }, + { 0x1f, 21, insert_bo, extract_bo, 0 }, /* The BO field in a B form instruction when the + or - modifier is used. This is like the BO field, but it must be even. */ #define BOE BO + 1 - { 5, 21, insert_boe, extract_boe, 0 }, + { 0x1e, 21, insert_boe, extract_boe, 0 }, #define BH BOE + 1 - { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, + { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, /* The BT field in an X or XL form instruction. */ #define BT BH + 1 - { 5, 21, NULL, NULL, PPC_OPERAND_CR }, + { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, /* The condition register number portion of the BI field in a B form or XL form instruction. This is used for the extended conditional branch mnemonics, which set the lower two bits of the BI field. This field is optional. */ #define CR BT + 1 - { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, /* The CRB field in an X form instruction. */ #define CRB CR + 1 - { 5, 6, NULL, NULL, 0 }, - - /* The CRFD field in an X form instruction. */ -#define CRFD CRB + 1 - { 3, 23, NULL, NULL, PPC_OPERAND_CR }, + /* The MB field in an M form instruction. */ +#define MB CRB +#define MB_MASK (0x1f << 6) + { 0x1f, 6, NULL, NULL, 0 }, /* The CRFS field in an X form instruction. */ -#define CRFS CRFD + 1 - { 3, 0, NULL, NULL, PPC_OPERAND_CR }, +#define CRFS CRB + 1 + { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, /* The CT field in an X form instruction. */ #define CT CRFS + 1 - { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + /* The MO field in an mbar instruction. */ +#define MO CT + { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, /* The D field in a D form instruction. This is a displacement off a register, and implies that the next operand is a register in parentheses. */ #define D CT + 1 - { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, /* The DE field in a DE form instruction. This is like D, but is 12 bits only. */ #define DE D + 1 - { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS }, + { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, /* The DES field in a DES form instruction. This is like DS, but is 14 bits only (12 stored.) */ #define DES DE + 1 - { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, /* The DQ field in a DQ form instruction. This is like D, but the lower four bits are forced to zero. */ #define DQ DES + 1 - { 16, 0, insert_dq, extract_dq, - PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, + { 0xfff0, 0, NULL, NULL, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, /* The DS field in a DS form instruction. This is like D, but the lower two bits are forced to zero. */ #define DS DQ + 1 - { 16, 0, insert_ds, extract_ds, - PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, + { 0xfffc, 0, NULL, NULL, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, /* The E field in a wrteei instruction. */ #define E DS + 1 - { 1, 15, NULL, NULL, 0 }, + { 0x1, 15, NULL, NULL, 0 }, /* The FL1 field in a POWER SC form instruction. */ #define FL1 E + 1 - { 4, 12, NULL, NULL, 0 }, + /* The U field in an X form instruction. */ +#define U FL1 + { 0xf, 12, NULL, NULL, 0 }, /* The FL2 field in a POWER SC form instruction. */ #define FL2 FL1 + 1 - { 3, 2, NULL, NULL, 0 }, + { 0x7, 2, NULL, NULL, 0 }, /* The FLM field in an XFL form instruction. */ #define FLM FL2 + 1 - { 8, 17, NULL, NULL, 0 }, + { 0xff, 17, NULL, NULL, 0 }, /* The FRA field in an X or A form instruction. */ #define FRA FLM + 1 #define FRA_MASK (0x1f << 16) - { 5, 16, NULL, NULL, PPC_OPERAND_FPR }, + { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, /* The FRB field in an X or A form instruction. */ #define FRB FRA + 1 #define FRB_MASK (0x1f << 11) - { 5, 11, NULL, NULL, PPC_OPERAND_FPR }, + { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, /* The FRC field in an A form instruction. */ #define FRC FRB + 1 #define FRC_MASK (0x1f << 6) - { 5, 6, NULL, NULL, PPC_OPERAND_FPR }, + { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, /* The FRS field in an X form instruction or the FRT field in a D, X or A form instruction. */ #define FRS FRC + 1 #define FRT FRS - { 5, 21, NULL, NULL, PPC_OPERAND_FPR }, + { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, /* The FXM field in an XFX instruction. */ #define FXM FRS + 1 -#define FXM_MASK (0xff << 12) - { 8, 12, insert_fxm, extract_fxm, 0 }, + { 0xff, 12, insert_fxm, extract_fxm, 0 }, /* Power4 version for mfcr. */ #define FXM4 FXM + 1 - { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, + { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, /* The L field in a D or X form instruction. */ #define L FXM4 + 1 - { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, /* The LEV field in a POWER SVC form instruction. */ #define SVC_LEV L + 1 - { 7, 5, NULL, NULL, 0 }, + { 0x7f, 5, NULL, NULL, 0 }, /* The LEV field in an SC form instruction. */ #define LEV SVC_LEV + 1 - { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, + { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, /* The LI field in an I form instruction. The lower two bits are forced to zero. */ #define LI LEV + 1 - { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, /* The LI field in an I form instruction when used as an absolute address. */ #define LIA LI + 1 - { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, /* The LS field in an X (sync) form instruction. */ #define LS LIA + 1 - { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, - - /* The MB field in an M form instruction. */ -#define MB LS + 1 -#define MB_MASK (0x1f << 6) - { 5, 6, NULL, NULL, 0 }, + { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, /* The ME field in an M form instruction. */ -#define ME MB + 1 +#define ME LS + 1 #define ME_MASK (0x1f << 1) - { 5, 1, NULL, NULL, 0 }, + { 0x1f, 1, NULL, NULL, 0 }, /* The MB and ME fields in an M form instruction expressed a single operand which is a bitmask indicating which bits to select. This is a two operand form using PPC_OPERAND_NEXT. See the description in opcode/ppc.h for what this means. */ #define MBE ME + 1 - { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, - { 32, 0, insert_mbe, extract_mbe, 0 }, + { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, + { -1, 0, insert_mbe, extract_mbe, 0 }, /* The MB or ME field in an MD or MDS form instruction. The high bit is wrapped to the low end. */ #define MB6 MBE + 2 #define ME6 MB6 #define MB6_MASK (0x3f << 5) - { 6, 5, insert_mb6, extract_mb6, 0 }, - - /* The MO field in an mbar instruction. */ -#define MO MB6 + 1 - { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + { 0x3f, 5, insert_mb6, extract_mb6, 0 }, /* The NB field in an X form instruction. The value 32 is stored as 0. */ -#define NB MO + 1 - { 6, 11, insert_nb, extract_nb, 0 }, +#define NB MB6 + 1 + { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, /* The NSI field in a D form instruction. This is the same as the SI field, only negated. */ #define NSI NB + 1 - { 16, 0, insert_nsi, extract_nsi, + { 0xffff, 0, insert_nsi, extract_nsi, PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ #define RA NSI + 1 #define RA_MASK (0x1f << 16) - { 5, 16, NULL, NULL, PPC_OPERAND_GPR }, + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, /* As above, but 0 in the RA field means zero, not r0. */ #define RA0 RA + 1 - { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, /* The RA field in the DQ form lq instruction, which has special value restrictions. */ #define RAQ RA0 + 1 - { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, + { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, /* The RA field in a D or X form instruction which is an updating load, which means that the RA field may not be zero and may not equal the RT field. */ #define RAL RAQ + 1 - { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, + { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, /* The RA field in an lmw instruction, which has special value restrictions. */ #define RAM RAL + 1 - { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, + { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, /* The RA field in a D or X form instruction which is an updating store or an updating floating point load, which means that the RA field may not be zero. */ #define RAS RAM + 1 - { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, + { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, /* The RA field of the tlbwe instruction, which is optional. */ #define RAOPT RAS + 1 - { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, /* The RB field in an X, XO, M, or MDS form instruction. */ #define RB RAOPT + 1 #define RB_MASK (0x1f << 11) - { 5, 11, NULL, NULL, PPC_OPERAND_GPR }, + { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, /* The RB field in an X form instruction when it must be the same as the RS field in the instruction. This is used for extended mnemonics like mr. */ #define RBS RB + 1 - { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, + { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form instruction or the RT field in a D, DS, X, XFX or XO form @@ -418,153 +393,168 @@ const struct powerpc_operand powerpc_operands[] = #define RS RBS + 1 #define RT RS #define RT_MASK (0x1f << 21) - { 5, 21, NULL, NULL, PPC_OPERAND_GPR }, + { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, - /* The RS field of the DS form stq instruction, which has special - value restrictions. */ + /* The RS and RT fields of the DS form stq instruction, which have + special value restrictions. */ #define RSQ RS + 1 - { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 }, - - /* The RT field of the DQ form lq instruction, which has special - value restrictions. */ -#define RTQ RSQ + 1 - { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 }, +#define RTQ RSQ + { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 }, /* The RS field of the tlbwe instruction, which is optional. */ -#define RSO RTQ + 1 +#define RSO RSQ + 1 #define RTO RSO - { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, /* The SH field in an X or M form instruction. */ #define SH RSO + 1 #define SH_MASK (0x1f << 11) - { 5, 11, NULL, NULL, 0 }, + /* The other UIMM field in a EVX form instruction. */ +#define EVUIMM SH + { 0x1f, 11, NULL, NULL, 0 }, /* The SH field in an MD form instruction. This is split. */ #define SH6 SH + 1 #define SH6_MASK ((0x1f << 11) | (1 << 1)) - { 6, 1, insert_sh6, extract_sh6, 0 }, + { 0x3f, -1, insert_sh6, extract_sh6, 0 }, /* The SH field of the tlbwe instruction, which is optional. */ #define SHO SH6 + 1 - { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL }, + { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, /* The SI field in a D form instruction. */ #define SI SHO + 1 - { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED }, + { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, /* The SI field in a D form instruction when we accept a wide range of positive values. */ #define SISIGNOPT SI + 1 - { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, + { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, /* The SPR field in an XFX form instruction. This is flipped--the lower 5 bits are stored in the upper 5 and vice- versa. */ #define SPR SISIGNOPT + 1 #define PMR SPR #define SPR_MASK (0x3ff << 11) - { 10, 11, insert_spr, extract_spr, 0 }, + { 0x3ff, 11, insert_spr, extract_spr, 0 }, /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ #define SPRBAT SPR + 1 #define SPRBAT_MASK (0x3 << 17) - { 2, 17, NULL, NULL, 0 }, + { 0x3, 17, NULL, NULL, 0 }, /* The SPRG register number in an XFX form m[ft]sprg instruction. */ #define SPRG SPRBAT + 1 - { 5, 16, insert_sprg, extract_sprg, 0 }, + { 0x1f, 16, insert_sprg, extract_sprg, 0 }, /* The SR field in an X form instruction. */ #define SR SPRG + 1 - { 4, 16, NULL, NULL, 0 }, + { 0xf, 16, NULL, NULL, 0 }, /* The STRM field in an X AltiVec form instruction. */ #define STRM SR + 1 -#define STRM_MASK (0x3 << 21) - { 2, 21, NULL, NULL, 0 }, + { 0x3, 21, NULL, NULL, 0 }, /* The SV field in a POWER SC form instruction. */ #define SV STRM + 1 - { 14, 2, NULL, NULL, 0 }, + { 0x3fff, 2, NULL, NULL, 0 }, /* The TBR field in an XFX form instruction. This is like the SPR field, but it is optional. */ #define TBR SV + 1 - { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, + { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, /* The TO field in a D or X form instruction. */ #define TO TBR + 1 #define TO_MASK (0x1f << 21) - { 5, 21, NULL, NULL, 0 }, - - /* The U field in an X form instruction. */ -#define U TO + 1 - { 4, 12, NULL, NULL, 0 }, + { 0x1f, 21, NULL, NULL, 0 }, /* The UI field in a D form instruction. */ -#define UI U + 1 - { 16, 0, NULL, NULL, 0 }, +#define UI TO + 1 + { 0xffff, 0, NULL, NULL, 0 }, /* The VA field in a VA, VX or VXR form instruction. */ #define VA UI + 1 -#define VA_MASK (0x1f << 16) - { 5, 16, NULL, NULL, PPC_OPERAND_VR }, + { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, /* The VB field in a VA, VX or VXR form instruction. */ #define VB VA + 1 -#define VB_MASK (0x1f << 11) - { 5, 11, NULL, NULL, PPC_OPERAND_VR }, + { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, /* The VC field in a VA form instruction. */ #define VC VB + 1 -#define VC_MASK (0x1f << 6) - { 5, 6, NULL, NULL, PPC_OPERAND_VR }, + { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, /* The VD or VS field in a VA, VX, VXR or X form instruction. */ #define VD VC + 1 #define VS VD -#define VD_MASK (0x1f << 21) - { 5, 21, NULL, NULL, PPC_OPERAND_VR }, + { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, /* The SIMM field in a VX form instruction. */ #define SIMM VD + 1 - { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED}, + { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, - /* The UIMM field in a VX form instruction. */ + /* The UIMM field in a VX form instruction, and TE in Z form. */ #define UIMM SIMM + 1 - { 5, 16, NULL, NULL, 0 }, +#define TE UIMM + { 0x1f, 16, NULL, NULL, 0 }, /* The SHB field in a VA form instruction. */ #define SHB UIMM + 1 - { 4, 6, NULL, NULL, 0 }, - - /* The other UIMM field in a EVX form instruction. */ -#define EVUIMM SHB + 1 - { 5, 11, NULL, NULL, 0 }, + { 0xf, 6, NULL, NULL, 0 }, /* The other UIMM field in a half word EVX form instruction. */ -#define EVUIMM_2 EVUIMM + 1 - { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS }, +#define EVUIMM_2 SHB + 1 + { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, /* The other UIMM field in a word EVX form instruction. */ #define EVUIMM_4 EVUIMM_2 + 1 - { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS }, + { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, /* The other UIMM field in a double EVX form instruction. */ #define EVUIMM_8 EVUIMM_4 + 1 - { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS }, + { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, /* The WS field. */ #define WS EVUIMM_8 + 1 -#define WS_MASK (0x7 << 11) - { 3, 11, NULL, NULL, 0 }, + { 0x7, 11, NULL, NULL, 0 }, + + /* The L field in an mtmsrd or A form instruction or W in an X form. */ +#define A_L WS + 1 +#define W A_L + { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, + +#define RMC A_L + 1 + { 0x3, 9, NULL, NULL, 0 }, + +#define R RMC + 1 + { 0x1, 16, NULL, NULL, 0 }, - /* The L field in an mtmsrd instruction */ -#define MTMSRD_L WS + 1 - { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, +#define SP R + 1 + { 0x3, 19, NULL, NULL, 0 }, +#define S SP + 1 + { 0x1, 20, NULL, NULL, 0 }, + + /* SH field starting at bit position 16. */ +#define SH16 S + 1 + /* The DCM and DGM fields in a Z form instruction. */ +#define DCM SH16 +#define DGM DCM + { 0x3f, 10, NULL, NULL, 0 }, + + /* The EH field in larx instruction. */ +#define EH SH16 + 1 + { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The L field in an mtfsf or XFL form instruction. */ +#define XFL_L EH + 1 + { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, }; +const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) + / sizeof (powerpc_operands[0])); + /* The functions used to insert and extract complicated operands. */ /* The BA field in an XL form instruction when it must be the same as @@ -617,26 +607,6 @@ extract_bba (unsigned long insn, return 0; } -/* The BD field in a B form instruction. The lower two bits are - forced to zero. */ - -static unsigned long -insert_bd (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn | (value & 0xfffc); -} - -static long -extract_bd (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn & 0xfffc) ^ 0x8000) - 0x8000; -} - /* The BD field in a B form instruction when the - modifier is used. This modifier means that the branch is not expected to be taken. For chips built to versions of the architecture prior to version 2 @@ -648,7 +618,11 @@ extract_bd (unsigned long insn, the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 - for branch on CTR. We only handle the taken/not-taken hint here. */ + for branch on CTR. We only handle the taken/not-taken hint here. + Note that we don't relax the conditions tested here when + disassembling with -Many because insns using extract_bdm and + extract_bdp always occur in pairs. One or the other will always + be valid. */ static unsigned long insert_bdm (unsigned long insn, @@ -739,10 +713,11 @@ extract_bdp (unsigned long insn, /* Check for legal values of a BO field. */ static int -valid_bo (long value, int dialect) +valid_bo (long value, int dialect, int extract) { if ((dialect & PPC_OPCODE_POWER4) == 0) { + int valid; /* Certain encodings have bits that are required to be zero. These are (z must be zero, y may be anything): 001zy @@ -755,36 +730,43 @@ valid_bo (long value, int dialect) { default: case 0: - return 1; + valid = 1; + break; case 0x4: - return (value & 0x2) == 0; + valid = (value & 0x2) == 0; + break; case 0x10: - return (value & 0x8) == 0; + valid = (value & 0x8) == 0; + break; case 0x14: - return value == 0x14; + valid = value == 0x14; + break; } + /* When disassembling with -Many, accept power4 encodings too. */ + if (valid + || (dialect & PPC_OPCODE_ANY) == 0 + || !extract) + return valid; } + + /* Certain encodings have bits that are required to be zero. + These are (z must be zero, a & t may be anything): + 0000z + 0001z + 0100z + 0101z + 001at + 011at + 1a00t + 1a01t + 1z1zz + */ + if ((value & 0x14) == 0) + return (value & 0x1) == 0; + else if ((value & 0x14) == 0x14) + return value == 0x14; else - { - /* Certain encodings have bits that are required to be zero. - These are (z must be zero, a & t may be anything): - 0000z - 0001z - 0100z - 0101z - 001at - 011at - 1a00t - 1a01t - 1z1zz - */ - if ((value & 0x14) == 0) - return (value & 0x1) == 0; - else if ((value & 0x14) == 0x14) - return value == 0x14; - else - return 1; - } + return 1; } /* The BO field in a B form instruction. Warn about attempts to set @@ -796,7 +778,7 @@ insert_bo (unsigned long insn, int dialect, const char **errmsg) { - if (!valid_bo (value, dialect)) + if (!valid_bo (value, dialect, 0)) *errmsg = _("invalid conditional option"); return insn | ((value & 0x1f) << 21); } @@ -809,7 +791,7 @@ extract_bo (unsigned long insn, long value; value = (insn >> 21) & 0x1f; - if (!valid_bo (value, dialect)) + if (!valid_bo (value, dialect, 1)) *invalid = 1; return value; } @@ -824,7 +806,7 @@ insert_boe (unsigned long insn, int dialect, const char **errmsg) { - if (!valid_bo (value, dialect)) + if (!valid_bo (value, dialect, 0)) *errmsg = _("invalid conditional option"); else if ((value & 1) != 0) *errmsg = _("attempt to set y bit when using + or - modifier"); @@ -840,162 +822,11 @@ extract_boe (unsigned long insn, long value; value = (insn >> 21) & 0x1f; - if (!valid_bo (value, dialect)) + if (!valid_bo (value, dialect, 1)) *invalid = 1; return value & 0x1e; } -/* The DQ field in a DQ form instruction. This is like D, but the - lower four bits are forced to zero. */ - -static unsigned long -insert_dq (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 0xf) != 0) - *errmsg = _("offset not a multiple of 16"); - return insn | (value & 0xfff0); -} - -static long -extract_dq (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn & 0xfff0) ^ 0x8000) - 0x8000; -} - -static unsigned long -insert_ev2 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 1) != 0) - *errmsg = _("offset not a multiple of 2"); - if ((value > 62) != 0) - *errmsg = _("offset greater than 62"); - return insn | ((value & 0x3e) << 10); -} - -static long -extract_ev2 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (insn >> 10) & 0x3e; -} - -static unsigned long -insert_ev4 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 3) != 0) - *errmsg = _("offset not a multiple of 4"); - if ((value > 124) != 0) - *errmsg = _("offset greater than 124"); - return insn | ((value & 0x7c) << 9); -} - -static long -extract_ev4 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (insn >> 9) & 0x7c; -} - -static unsigned long -insert_ev8 (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 7) != 0) - *errmsg = _("offset not a multiple of 8"); - if ((value > 248) != 0) - *errmsg = _("offset greater than 248"); - return insn | ((value & 0xf8) << 8); -} - -static long -extract_ev8 (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (insn >> 8) & 0xf8; -} - -/* The DS field in a DS form instruction. This is like D, but the - lower two bits are forced to zero. */ - -static unsigned long -insert_ds (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 3) != 0) - *errmsg = _("offset not a multiple of 4"); - return insn | (value & 0xfffc); -} - -static long -extract_ds (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn & 0xfffc) ^ 0x8000) - 0x8000; -} - -/* The DE field in a DE form instruction. */ - -static unsigned long -insert_de (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (value > 2047 || value < -2048) - *errmsg = _("offset not between -2048 and 2047"); - return insn | ((value << 4) & 0xfff0); -} - -static long -extract_de (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (insn & 0xfff0) >> 4; -} - -/* The DES field in a DES form instruction. */ - -static unsigned long -insert_des (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (value > 8191 || value < -8192) - *errmsg = _("offset not between -8192 and 8191"); - else if ((value & 3) != 0) - *errmsg = _("offset not a multiple of 4"); - return insn | ((value << 2) & 0xfff0); -} - -static long -extract_des (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000; -} - /* FXM mask in mfcr and mtcrf instructions. */ static unsigned long @@ -1068,28 +899,6 @@ extract_fxm (unsigned long insn, return mask; } -/* The LI field in an I form instruction. The lower two bits are - forced to zero. */ - -static unsigned long -insert_li (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 3) != 0) - *errmsg = _("ignoring least significant bits in branch offset"); - return insn | (value & 0x3fffffc); -} - -static long -extract_li (unsigned long insn, - int dialect ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000; -} - /* The MB and ME fields in an M form instruction expressed as a single operand which is itself a bitmask. The extraction function always marks it as invalid, since we never want to recognize an @@ -1201,19 +1010,6 @@ extract_mb6 (unsigned long insn, /* The NB field in an X form instruction. The value 32 is stored as 0. */ -static unsigned long -insert_nb (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (value < 0 || value > 32) - *errmsg = _("value out of range"); - if (value == 32) - value = 0; - return insn | ((value & 0x1f) << 11); -} - static long extract_nb (unsigned long insn, int dialect ATTRIBUTE_UNUSED, @@ -1336,34 +1132,6 @@ extract_rbs (unsigned long insn, return 0; } -/* The RT field of the DQ form lq instruction, which has special - value restrictions. */ - -static unsigned long -insert_rtq (unsigned long insn, - long value, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 1) != 0) - *errmsg = _("target register operand must be even"); - return insn | ((value & 0x1f) << 21); -} - -/* The RS field of the DS form stq instruction, which has special - value restrictions. */ - -static unsigned long -insert_rsq (unsigned long insn, - long value ATTRIBUTE_UNUSED, - int dialect ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if ((value & 1) != 0) - *errmsg = _("source register operand must be even"); - return insn | ((value & 0x1f) << 21); -} - /* The SH field in an MD form instruction. This is split. */ static unsigned long @@ -1509,6 +1277,9 @@ extract_tbr (unsigned long insn, /* An A_MASK with the FRA and FRC fields fixed. */ #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) +/* An AFRAFRC_MASK, but with L bit clear. */ +#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) + /* A B form instruction. */ #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) #define B_MASK B (0x3f, 1, 1) @@ -1619,21 +1390,37 @@ extract_tbr (unsigned long insn, /* An X form instruction. */ #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) +/* A Z form instruction. */ +#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) + /* An X form instruction with the RC bit specified. */ #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) +/* A Z form instruction with the RC bit specified. */ +#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) + /* The mask for an X form instruction. */ #define X_MASK XRC (0x3f, 0x3ff, 1) +/* The mask for a Z form instruction. */ +#define Z_MASK ZRC (0x3f, 0x1ff, 1) +#define Z2_MASK ZRC (0x3f, 0xff, 1) + /* An X_MASK with the RA field fixed. */ #define XRA_MASK (X_MASK | RA_MASK) +/* An XRA_MASK with the W field clear. */ +#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) + /* An X_MASK with the RB field fixed. */ #define XRB_MASK (X_MASK | RB_MASK) /* An X_MASK with the RT field fixed. */ #define XRT_MASK (X_MASK | RT_MASK) +/* An XRT_MASK mask with the L bits clear. */ +#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) + /* An X_MASK with the RA and RB fields fixed. */ #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) @@ -1670,13 +1457,16 @@ extract_tbr (unsigned long insn, /* An X form sync instruction with everything filled in except the LS field. */ #define XSYNC_MASK (0xff9fffff) +/* An X_MASK, but with the EH bit clear. */ +#define XEH_MASK (X_MASK & ~((unsigned long )1)) + /* An X form AltiVec dss instruction. */ #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) /* An XFL form instruction. */ #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) -#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) +#define XFL_MASK XFL (0x3f, 0x3ff, 1) /* An X form isel instruction. */ #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) @@ -1752,7 +1542,7 @@ extract_tbr (unsigned long insn, /* An XFX form instruction with the SPR field filled in except for the SPRG field. */ -#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16)) +#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) /* An X form instruction with everything filled in except the E field. */ #define XE_MASK (0xffff7fff) @@ -1823,6 +1613,8 @@ extract_tbr (unsigned long insn, #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM #define POWER4 PPC_OPCODE_POWER4 #define POWER5 PPC_OPCODE_POWER5 +#define POWER6 PPC_OPCODE_POWER6 +#define CELL PPC_OPCODE_CELL #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC #define PPC403 PPC_OPCODE_403 @@ -3014,16 +2806,23 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, -{ "hrfid", XL(19,274), 0xffffffff, POWER5, { 0 } }, +{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, +{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } }, + { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, +{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } }, + { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, +{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } }, +{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } }, + { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, @@ -3174,8 +2973,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, -{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } }, -{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } }, +{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } }, +{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } }, { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, @@ -3321,10 +3120,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } }, -{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } }, +{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } }, { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, -{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } }, +{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } }, { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, @@ -3417,9 +3216,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, -{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } }, +{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } }, -{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, +{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } }, +{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } }, { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, @@ -3501,12 +3301,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, +{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } }, + { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, -{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } }, +{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } }, { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, @@ -3516,6 +3318,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, +{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } }, + { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, @@ -3622,7 +3426,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, -{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, +{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, @@ -3703,6 +3507,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, +{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } }, { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, @@ -3924,12 +3729,18 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } }, +{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } }, + { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, +{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } }, + { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, +{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } }, + { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, @@ -3948,6 +3759,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, +{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }}, +{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }}, +{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }}, +{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }}, +{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }}, +{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }}, +{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }}, { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, @@ -4019,6 +3837,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, +{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } }, { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, @@ -4206,6 +4025,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, +{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } }, + { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, @@ -4255,6 +4076,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, +{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } }, + { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, @@ -4265,6 +4088,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, +{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } }, + { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, @@ -4303,6 +4128,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, +{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } }, + { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, @@ -4317,6 +4144,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, +{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } }, + { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, @@ -4334,6 +4163,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, +{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } }, + { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, @@ -4344,16 +4175,24 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, +{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } }, + { "mbar", X(31,854), X_MASK, BOOKE, { MO } }, { "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, +{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } }, + +{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } }, + { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, -{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } }, -{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } }, +{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } }, +{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } }, { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, +{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } }, + { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, @@ -4375,6 +4214,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, +{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } }, + { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, @@ -4390,6 +4231,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, +{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } }, + { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, @@ -4404,6 +4247,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, +{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } }, + { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, @@ -4423,6 +4268,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, +/* New load/store left/right index vector instructions that are in the Cell only. */ +{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } }, +{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } }, +{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } }, +{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } }, +{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } }, +{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } }, +{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } }, +{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } }, + { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, @@ -4483,6 +4338,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, +{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } }, + { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, @@ -4504,6 +4361,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, +{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + +{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, +{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, + { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, @@ -4516,14 +4379,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, +{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, +{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, -{ "frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER5, { FRT, FRB } }, -{ "frsqrtes.",A(59,26,1), AFRAFRC_MASK, POWER5, { FRT, FRB } }, +{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, +{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, @@ -4537,10 +4400,73 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, +{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + +{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, +{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, + +{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, +{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, + +{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, +{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, + +{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, +{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, + +{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, +{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, + +{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } }, + +{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } }, +{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } }, +{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } }, + +{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, +{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, + +{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } }, +{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } }, + +{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } }, +{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } }, + +{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, +{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, + +{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } }, +{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } }, + +{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + +{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + +{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } }, + +{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } }, + +{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } }, +{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } }, + +{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } }, +{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } }, + +{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } }, +{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } }, + +{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, +{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } }, + { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, @@ -4562,6 +4488,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, +{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + +{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, +{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, + +{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, @@ -4596,16 +4531,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, -{ "fre", A(63,24,0), AFRAFRC_MASK, POWER5, { FRT, FRB } }, -{ "fre.", A(63,24,1), AFRAFRC_MASK, POWER5, { FRT, FRB } }, +{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, +{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, -{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, -{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, +{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, +{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, @@ -4629,6 +4564,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, +{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + +{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, +{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, + { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, @@ -4637,21 +4578,54 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, +{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, +{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, + +{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } }, +{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } }, + { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, -{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, -{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, +{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, +{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, + +{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, +{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, + +{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } }, + +{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, +{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } }, { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, +{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } }, +{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } }, +{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } }, + +{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, +{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } }, + +{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } }, +{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } }, + { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, +{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } }, +{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } }, + +{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, +{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, + +{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } }, +{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } }, + { "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } }, { "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } }, { "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } }, @@ -4661,11 +4635,27 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } }, { "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } }, +{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + +{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, -{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, -{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, +{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } }, + +{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } }, + +{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, +{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } }, + +{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } }, +{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } }, + +{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } }, +{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } }, { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, @@ -4673,9 +4663,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, +{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } }, +{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } }, + { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, +{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, +{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, + }; const int powerpc_num_opcodes = diff --git a/contrib/binutils/opcodes/s390-mkopc.c b/contrib/binutils/opcodes/s390-mkopc.c index 5a794fd..9e94f24 100644 --- a/contrib/binutils/opcodes/s390-mkopc.c +++ b/contrib/binutils/opcodes/s390-mkopc.c @@ -36,7 +36,8 @@ enum s390_opcode_cpu_val S390_OPCODE_G6, S390_OPCODE_Z900, S390_OPCODE_Z990, - S390_OPCODE_Z9_109 + S390_OPCODE_Z9_109, + S390_OPCODE_Z9_EC }; struct op_struct @@ -198,6 +199,8 @@ main (void) min_cpu = S390_OPCODE_Z990; else if (strcmp (cpu_string, "z9-109") == 0) min_cpu = S390_OPCODE_Z9_109; + else if (strcmp (cpu_string, "z9-ec") == 0) + min_cpu = S390_OPCODE_Z9_EC; else { fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); exit (1); diff --git a/contrib/binutils/opcodes/s390-opc.c b/contrib/binutils/opcodes/s390-opc.c index aa2e5a3..a443fcf 100644 --- a/contrib/binutils/opcodes/s390-opc.c +++ b/contrib/binutils/opcodes/s390-opc.c @@ -133,7 +133,10 @@ const struct s390_operand s390_operands[] = #define U32_16 41 /* 32 bit unsigned value starting at 16 */ { 32, 16, 0 }, #define M_16 42 /* 4 bit optional mask starting at 16 */ - { 4, 16, S390_OPERAND_OPTIONAL } + { 4, 16, S390_OPERAND_OPTIONAL }, +#define RO_28 43 /* optional GPR starting at position 28 */ + { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) } + }; @@ -202,13 +205,21 @@ const struct s390_operand s390_operands[] = #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ +#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ +/* Actually efpc and sfpc do not take an optional operand. + This is just a workaround for existing code e.g. glibc. */ +#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ +#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ +#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ -#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */ -#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */ -#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */ +#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ +#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ +#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ +#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ +#define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ @@ -216,6 +227,7 @@ const struct s390_operand s390_operands[] = #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ +#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ @@ -244,6 +256,7 @@ const struct s390_operand s390_operands[] = #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ +#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ @@ -275,13 +288,19 @@ const struct s390_operand s390_operands[] = #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } -#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } @@ -289,6 +308,7 @@ const struct s390_operand s390_operands[] = #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } @@ -317,6 +337,7 @@ const struct s390_operand s390_operands[] = #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } @@ -324,7 +345,7 @@ const struct s390_operand s390_operands[] = #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } -#define MASK_SSF_RRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ diff --git a/contrib/binutils/opcodes/s390-opc.txt b/contrib/binutils/opcodes/s390-opc.txt index bbe1588..865e264 100644 --- a/contrib/binutils/opcodes/s390-opc.txt +++ b/contrib/binutils/opcodes/s390-opc.txt @@ -344,9 +344,9 @@ ed0000000008 keb RXE_FRRD "compare and signal short bfp" g5 esa,zarch b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" g5 esa,zarch b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" g5 esa,zarch b394 cefbr RRE_RF "convert from fixed 32 to short bfp" g5 esa,zarch -b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" g5 esa,zarch -b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" g5 esa,zarch -b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" g5 esa,zarch +b39a cfxbr RRF_U0RF "convert to fixed extended bfp to 32" g5 esa,zarch +b399 cfdbr RRF_U0RF "convert to fixed long bfp to 32" g5 esa,zarch +b398 cfebr RRF_U0RF "convert to fixed short bfp to 32" g5 esa,zarch b34d dxbr RRE_FF "divide extended bfp" g5 esa,zarch b31d ddbr RRE_FF "divide long bfp" g5 esa,zarch ed000000001d ddb RXE_FRRD "divide long bfp" g5 esa,zarch @@ -354,7 +354,7 @@ b30d debr RRE_FF "divide short bfp" g5 esa,zarch ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch -b38c efpc RRE_RR "extract fpc" g5 esa,zarch +b38c efpc RRE_RR_OPT "extract fpc" g5 esa,zarch b342 ltxbr RRE_FF "load and test extended bfp" g5 esa,zarch b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch @@ -397,7 +397,7 @@ b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch -b384 sfpc RRE_RR "set fpc" g5 esa,zarch +b384 sfpc RRE_RR_OPT "set fpc" g5 esa,zarch b299 srnm S_RD "set rounding mode" g5 esa,zarch b316 sqxbr RRE_FF "square root extended bfp" g5 esa,zarch b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch @@ -428,7 +428,7 @@ a701 tmll RI_RU "test under mask low low" g5 esa,zarch b278 stcke S_RD "store clock extended" g5 esa,zarch b2a5 tre RRE_RR "translate extended" g5 esa,zarch eb000000008e mvclu RSE_RRRD "move long unicode" g5 esa,zarch -e9 pka SS_L0RDRD "pack ascii" g5 esa,zarch +e9 pka SS_L2RDRD "pack ascii" g5 esa,zarch e1 pku SS_L0RDRD "pack unicode" g5 esa,zarch b993 troo RRE_RR "translate one to one" g5 esa,zarch b992 trot RRE_RR "translate one to two" g5 esa,zarch @@ -555,15 +555,15 @@ b91c msgfr RRE_RR "multiply single 64<32" z900 zarch b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" z900 zarch b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" z900 zarch b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" z900 zarch -b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" z900 zarch -b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" z900 zarch -b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" z900 zarch +b3a8 cgebr RRF_U0RF "convert to fixed short bfd to 64" z900 zarch +b3a9 cgdbr RRF_U0RF "convert to fixed long bfp to 64" z900 zarch +b3aa cgxbr RRF_U0RF "convert to fixed extended bfp to 64" z900 zarch b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" z900 zarch b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" z900 zarch b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" z900 zarch -b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" z900 zarch -b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" z900 zarch -b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" z900 zarch +b3c8 cger RRF_U0RF "convert to fixed short hfp to 64" z900 zarch +b3c9 cgdr RRF_U0RF "convert to fixed long hfp to 64" z900 zarch +b3ca cgxr RRF_U0RF "convert to fixed extended hfp to 64" z900 zarch 010b tam E "test addressing mode" z900 esa,zarch 010c sam24 E "set addressing mode 24" z900 esa,zarch 010d sam31 E "set addressing mode 31" z900 esa,zarch @@ -631,9 +631,9 @@ b369 cxr RRE_FF "compare extended hfp" g5 esa,zarch b3b6 cxfr RRE_RF "convert from fixed 32 to extended hfp" g5 esa,zarch b3b5 cdfr RRE_RF "convert from fixed 32 to long hfp" g5 esa,zarch b3b4 cefr RRE_RF "convert from fixed 32 to short hfp" g5 esa,zarch -b3ba cfxr RRF_U0FR "convert to fixed extended hfp to 32" z900 zarch -b3b9 cfdr RRF_U0FR "convert to fixed long hfp to 32" z900 zarch -b3b8 cfer RRF_U0FR "convert to fixed short hfp to 32" z900 zarch +b3ba cfxr RRF_U0RF "convert to fixed extended hfp to 32" z900 zarch +b3b9 cfdr RRF_U0RF "convert to fixed long hfp to 32" z900 zarch +b3b8 cfer RRF_U0RF "convert to fixed short hfp to 32" z900 zarch b362 ltxr RRE_FF "load and test extended hfp" g5 esa,zarch b363 lcxr RRE_FF "load complement extended hfp" g5 esa,zarch b367 fixr RRF_U0FF "load fp integer extended hfp" g5 esa,zarch @@ -863,3 +863,69 @@ b338 maylr RRF_F0FF "multiply and add unnormalized long hfp low" z9-109 zarch ed000000003a may RXF_FRRDF "multiply and add unnormalized long hfp" z9-109 zarch ed000000003c mayh RXF_FRRDF "multiply and add unnormalized long hfp high" z9-109 zarch ed0000000038 mayl RXF_FRRDF "multiply and add unnormalized long hfp low" z9-109 zarch +b370 lpdfr RRE_FF "load positive no cc" z9-ec zarch +b371 lndfr RRE_FF "load negative no cc" z9-ec zarch +b372 cpsdr RRF_F0FF2 "copy sign" z9-ec zarch +b373 lcdfr RRE_FF "load complement no cc" z9-ec zarch +b3c1 ldgr RRE_FR "load fpr from gr" z9-ec zarch +b3cd lgdr RRE_RF "load gr from fpr" z9-ec zarch +b3d2 adtr RRR_F0FF "add long dfp" z9-ec zarch +b3da axtr RRR_F0FF "add extended dfp" z9-ec zarch +b3e4 cdtr RRE_FF "compare long dfp" z9-ec zarch +b3ec cxtr RRE_FF "compare extended dfp" z9-ec zarch +b3e0 kdtr RRE_FF "compare and signal long dfp" z9-ec zarch +b3e8 kxtr RRE_FF "compare and signal extended dfp" z9-ec zarch +b3f4 cedtr RRE_FF "compare exponent long dfp" z9-ec zarch +b3fc cextr RRE_FF "compare exponent extended dfp" z9-ec zarch +b3f1 cdgtr RRE_FR "convert from fixed long dfp" z9-ec zarch +b3f9 cxgtr RRE_FR "convert from fixed extended dfp" z9-ec zarch +b3f3 cdstr RRE_FR "convert from signed bcd long dfp" z9-ec zarch +b3fb cxstr RRE_FR "convert from signed bcd extended dfp" z9-ec zarch +b3f2 cdutr RRE_FR "convert from unsigned bcd to long dfp" z9-ec zarch +b3fa cxutr RRE_FR "convert from unsigned bcd to extended dfp" z9-ec zarch +b3e1 cgdtr RRF_U0RF "convert from long dfp to fixed" z9-ec zarch +b3e9 cgxtr RRF_U0RF "convert from extended dfp to fixed" z9-ec zarch +b3e3 csdtr RRE_RF "convert from long dfp to signed bcd" z9-ec zarch +b3eb csxtr RRE_RF "convert from extended dfp to signed bcd" z9-ec zarch +b3e2 cudtr RRE_RF "convert from long dfp to unsigned bcd" z9-ec zarch +b3ea cuxtr RRE_RF "convert from extended dfp to unsigned bcd" z9-ec zarch +b3d1 ddtr RRR_F0FF "divide long dfp" z9-ec zarch +b3d9 dxtr RRR_F0FF "divide extended dfp" z9-ec zarch +b3e5 eedtr RRE_RF "extract biased exponent from long dfp" z9-ec zarch +b3ed eextr RRE_RF "extract biased exponent from extended dfp" z9-ec zarch +b3e7 esdtr RRE_RF "extract significance from long dfp" z9-ec zarch +b3ef esxtr RRE_RF "extract significance from extended dfp" z9-ec zarch +b3f6 iedtr RRF_F0FR "insert biased exponent long dfp" z9-ec zarch +b3fe iextr RRF_F0FR "insert biased exponent extended dfp" z9-ec zarch +b3d6 ltdtr RRE_FF "load and test long dfp" z9-ec zarch +b3de ltxtr RRE_FF "load and test extended dfp" z9-ec zarch +b3d7 fidtr RRF_UUFF "load fp integer long dfp" z9-ec zarch +b3df fixtr RRF_UUFF "load fp integer extended dfp" z9-ec zarch +b2bd lfas S_RD "load fpd and signal" z9-ec zarch +b3d4 ldetr RRF_0UFF "load lengthened long dfp" z9-ec zarch +b3dc lxdtr RRF_0UFF "load lengthened extended dfp" z9-ec zarch +b3d5 ledtr RRF_UUFF "load rounded long dfp" z9-ec zarch +b3dd ldxtr RRF_UUFF "load rounded extended dfp" z9-ec zarch +b3d0 mdtr RRR_F0FF "multiply long dfp" z9-ec zarch +b3d8 mxtr RRR_F0FF "multiply extended dfp" z9-ec zarch +b3f5 qadtr RRF_FFFU "Quantize long dfp" z9-ec zarch +b3fd qaxtr RRF_FFFU "Quantize extended dfp" z9-ec zarch +b3f7 rrdtr RRF_FFFU "Reround long dfp" z9-ec zarch +b3ff rrxtr RRF_FFFU "Reround extended dfp" z9-ec zarch +b2b9 srnmt S_RD "set rounding mode dfp" z9-ec zarch +b385 sfasr RRE_R0 "set fpc and signal" z9-ec zarch +ed0000000040 sldt RXF_FRRDF "shift coefficient left long dfp" z9-ec zarch +ed0000000048 slxt RXF_FRRDF "shift coefficient left extended dfp" z9-ec zarch +ed0000000041 srdt RXF_FRRDF "shift coefficient right long dfp" z9-ec zarch +ed0000000049 srxt RXF_FRRDF "shift coefficient right extended dfp" z9-ec zarch +b3d3 sdtr RRR_F0FF "subtract long dfp" z9-ec zarch +b3db sxtr RRR_F0FF "subtract extended dfp" z9-ec zarch +ed0000000050 tcet RXE_FRRD "test data class short dfp" z9-ec zarch +ed0000000054 tcdt RXE_FRRD "test data class long dfp" z9-ec zarch +ed0000000058 tcxt RXE_FRRD "test data class extended dfp" z9-ec zarch +ed0000000051 tget RXE_FRRD "test data group short dfp" z9-ec zarch +ed0000000055 tgdt RXE_FRRD "test data group long dfp" z9-ec zarch +ed0000000059 tgxt RXE_FRRD "test data group extended dfp" z9-ec zarch +010a pfpo E "perform floating point operation" z9-ec zarch +c801 ectg SSF_RRDRD "extract cpu time" z9-ec zarch +c802 csst SSF_RRDRD "compare and swap and store" z9-ec zarch diff --git a/contrib/binutils/opcodes/score-dis.c b/contrib/binutils/opcodes/score-dis.c new file mode 100644 index 0000000..96d1ec4 --- /dev/null +++ b/contrib/binutils/opcodes/score-dis.c @@ -0,0 +1,504 @@ +/* Instruction printing code for Score + Copyright 2006 Free Software Foundation, Inc. + Contributed by: + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of libopcodes. + + This program is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#define DEFINE_TABLE +#include "score-opc.h" +#include "opintl.h" +#include "bfd.h" + +/* FIXME: This shouldn't be done here. */ +#include "elf-bfd.h" +#include "elf/internal.h" +#include "elf/score.h" + +#ifndef streq +#define streq(a,b) (strcmp ((a), (b)) == 0) +#endif + +#ifndef strneq +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) +#endif + +#ifndef NUM_ELEM +#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) +#endif + +typedef struct +{ + const char *name; + const char *description; + const char *reg_names[32]; +} score_regname; + +static score_regname regnames[] = +{ + {"gcc", "Select register names used by GCC", + {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", + "r21", "r22", "r23", "r24", "r25", "r26", "r27", "gp", "r29", "r30", "r31"}}, +}; + +static unsigned int regname_selected = 0; + +#define NUM_SCORE_REGNAMES NUM_ELEM (regnames) +#define score_regnames regnames[regname_selected].reg_names + +/* Print one instruction from PC on INFO->STREAM. + Return the size of the instruction. */ +static int +print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given) +{ + struct score_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + for (insn = score_opcodes; insn->assembler; insn++) + { + if ((insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) + { + char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case 'j': + { + int target; + + if (info->flags & INSN_HAS_RELOC) + pc = 0; + target = (pc & 0xfe000000) | (given & 0x01fffffe); + (*info->print_address_func) (target, info); + } + break; + case 'b': + { + /* Sign-extend a 20-bit number. */ +#define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000) + int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe); + int target = (pc + SEXT20 (disp)); + + (*info->print_address_func) (target, info); + } + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + + if (!bitend) + abort (); + + switch (*c) + { + case 'r': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%s", score_regnames[reg]); + } + break; + case 'd': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%ld", reg); + } + break; + case 'i': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + reg = ((reg ^ (1 << (bitend - bitstart))) - + (1 << (bitend - bitstart))); + + if (((given & insn->mask) == 0x0c00000a) /* ldc1 */ + || ((given & insn->mask) == 0x0c000012) /* ldc2 */ + || ((given & insn->mask) == 0x0c00001c) /* ldc3 */ + || ((given & insn->mask) == 0x0c00000b) /* stc1 */ + || ((given & insn->mask) == 0x0c000013) /* stc2 */ + || ((given & insn->mask) == 0x0c00001b)) /* stc3 */ + reg <<= 2; + + func (stream, "%ld", reg); + } + break; + case 'x': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + + func (stream, "%lx", reg); + } + break; + default: + abort (); + } + break; + case '`': + c++; + if ((given & (1 << bitstart)) == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + default: + abort (); + } + break; + + default: + abort (); + } + } + } + else + func (stream, "%c", *c); + } + return 4; + } + } + +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("<illegal instruction>")); + return 4; +#endif + + abort (); +} + +static void +print_insn_parallel_sym (struct disassemble_info *info) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + /* 10: 0000 nop! + 4 space + 1 colon + 1 space + 1 tab + 8 opcode + 2 space + 1 tab. + FIXME: the space number is not accurate. */ + func (stream, "%s", " ||\n \t \t"); +} + +/* Print one instruction from PC on INFO->STREAM. + Return the size of the instruction. */ +static int +print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given) +{ + struct score_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + given &= 0xffff; + for (insn = score_opcodes; insn->assembler; insn++) + { + if (!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) + { + char *c = insn->assembler; + + info->bytes_per_chunk = 2; + info->bytes_per_line = 4; + given &= 0xffff; + + for (; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + + case 'j': + { + int target; + + if (info->flags & INSN_HAS_RELOC) + pc = 0; + + target = (pc & 0xfffff000) | (given & 0x00000ffe); + (*info->print_address_func) (target, info); + } + break; + case 'b': + { + /* Sign-extend a 9-bit number. */ +#define SEXT9(x) ((((x) & 0x1ff) ^ (~ 0xff)) + 0x100) + int disp = (given & 0xff) << 1; + int target = (pc + SEXT9 (disp)); + + (*info->print_address_func) (target, info); + } + break; + + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + { + long reg; + + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + if (!bitend) + abort (); + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + switch (*c) + { + case 'R': + func (stream, "%s", score_regnames[reg + 16]); + break; + case 'r': + func (stream, "%s", score_regnames[reg]); + break; + case 'd': + if (*(c + 1) == '\0') + func (stream, "%ld", reg); + else + { + c++; + if (*c == '1') + func (stream, "%ld", reg << 1); + else if (*c == '2') + func (stream, "%ld", reg << 2); + } + break; + + case 'x': + if (*(c + 1) == '\0') + func (stream, "%lx", reg); + else + { + c++; + if (*c == '1') + func (stream, "%lx", reg << 1); + else if (*c == '2') + func (stream, "%lx", reg << 2); + } + break; + case 'i': + reg = ((reg ^ (1 << bitend)) - (1 << bitend)); + func (stream, "%ld", reg); + break; + default: + abort (); + } + } + break; + + case '\'': + c++; + if ((given & (1 << bitstart)) != 0) + func (stream, "%c", *c); + break; + default: + abort (); + } + } + break; + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + + return 2; + } + } +#if (SCORE_SIMULATOR_ACTIVE) + func (stream, _("<illegal instruction>")); + return 2; +#endif + /* No match. */ + abort (); +} + +/* NOTE: There are no checks in these routines that + the relevant number of data bytes exist. */ +static int +print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) +{ + unsigned char b[4]; + long given; + long ridparity; + int status; + bfd_boolean insn_pce_p = FALSE; + bfd_boolean insn_16_p = FALSE; + + info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; + + if (pc & 0x2) + { + info->bytes_per_chunk = 2; + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); + b[3] = b[2] = 0; + insn_16_p = TRUE; + } + else + { + info->bytes_per_chunk = 4; + status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info); + if (status != 0) + { + info->bytes_per_chunk = 2; + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); + b[3] = b[2] = 0; + insn_16_p = TRUE; + } + } + + if (status != 0) + { + info->memory_error_func (status, pc, info); + return -1; + } + + if (little) + { + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); + } + else + { + given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); + } + + if ((given & 0x80008000) == 0x80008000) + { + insn_pce_p = FALSE; + insn_16_p = FALSE; + } + else if ((given & 0x8000) == 0x8000) + { + insn_pce_p = TRUE; + } + else + { + insn_16_p = TRUE; + } + + /* 16 bit instruction. */ + if (insn_16_p) + { + if (little) + { + given = b[0] | (b[1] << 8); + } + else + { + given = (b[0] << 8) | b[1]; + } + + status = print_insn_score16 (pc, info, given); + } + /* pce instruction. */ + else if (insn_pce_p) + { + long other; + + other = given & 0xFFFF; + given = (given & 0xFFFF0000) >> 16; + + status = print_insn_score16 (pc, info, given); + print_insn_parallel_sym (info); + status += print_insn_score16 (pc, info, other); + /* disassemble_bytes() will output 4 byte per chunk for pce instructio. */ + info->bytes_per_chunk = 4; + } + /* 32 bit instruction. */ + else + { + /* Get rid of parity. */ + ridparity = (given & 0x7FFF); + ridparity |= (given & 0x7FFF0000) >> 1; + given = ridparity; + status = print_insn_score32 (pc, info, given); + } + + return status; +} + +int +print_insn_big_score (bfd_vma pc, struct disassemble_info *info) +{ + return print_insn (pc, info, FALSE); +} + +int +print_insn_little_score (bfd_vma pc, struct disassemble_info *info) +{ + return print_insn (pc, info, TRUE); +} diff --git a/contrib/binutils/opcodes/score-opc.h b/contrib/binutils/opcodes/score-opc.h new file mode 100644 index 0000000..20437d7 --- /dev/null +++ b/contrib/binutils/opcodes/score-opc.h @@ -0,0 +1,487 @@ +/* Copyright 2006 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +struct score_opcode +{ + unsigned long value; + unsigned long mask; /* Recognise instruction if (op & mask) == value. */ + char *assembler; /* Disassembly string. */ +}; + +/* Note: There is a partial ordering in this table - it must be searched from + the top to obtain a correct match. */ + +static struct score_opcode score_opcodes[] = +{ + /* Score Instructions. */ + {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"}, + {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"}, + {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000012, 0x3e0003ff, "addc\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000013, 0x3e0003ff, "addc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x02000000, 0x3e0e0001, "addi\t\t%20-24r, %1-16i"}, + {0x02000001, 0x3e0e0001, "addi.c\t\t%20-24r, %1-16i"}, + {0x0a000000, 0x3e0e0001, "addis\t\t%20-24r, %1-16d(0x%1-16x)"}, + {0x0a000001, 0x3e0e0001, "addis.c\t\t%20-24r, %1-16d(0x%1-16x)"}, + {0x10000000, 0x3e000001, "addri\t\t%20-24r, %15-19r, %1-14i"}, + {0x10000001, 0x3e000001, "addri.c\t\t%20-24r, %15-19r, %1-14i"}, + {0x00000009, 0x0000700f, "addc!\t\t%8-11r, %4-7r"}, + {0x00002000, 0x0000700f, "add!\t\t%8-11r, %4-7r"}, + {0x00006000, 0x00007087, "addei!\t\t%8-11r, %3-6d"}, + {0x00000020, 0x3e0003ff, "and\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000021, 0x3e0003ff, "and.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x02080000, 0x3e0e0001, "andi\t\t%20-24r, 0x%1-16x"}, + {0x02080001, 0x3e0e0001, "andi.c\t\t%20-24r, 0x%1-16x"}, + {0x0a080000, 0x3e0e0001, "andis\t\t%20-24r, 0x%1-16x"}, + {0x0a080001, 0x3e0e0001, "andis.c\t\t%20-24r, 0x%1-16x"}, + {0x18000000, 0x3e000001, "andri\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x18000001, 0x3e000001, "andri.c\t\t%20-24r, %15-19r,0x%1-14x"}, + {0x00002004, 0x0000700f, "and!\t\t%8-11r, %4-7r"}, + {0x08000000, 0x3e007c01, "bcs\t\t%b" }, + {0x08000400, 0x3e007c01, "bcc\t\t%b" }, + {0x08003800, 0x3e007c01, "bcnz\t\t%b" }, + {0x08000001, 0x3e007c01, "bcsl\t\t%b" }, + {0x08000401, 0x3e007c01, "bccl\t\t%b" }, + {0x08003801, 0x3e007c01, "bcnzl\t\t%b" }, + {0x00004000, 0x00007f00, "bcs!\t\t%b" }, + {0x00004100, 0x00007f00, "bcc!\t\t%b" }, + {0x00004e00, 0x00007f00, "bcnz!\t\t%b" }, + {0x08001000, 0x3e007c01, "beq\t\t%b" }, + {0x08001001, 0x3e007c01, "beql\t\t%b" }, + {0x00004400, 0x00007f00, "beq!\t\t%b" }, + {0x08000800, 0x3e007c01, "bgtu\t\t%b" }, + {0x08001800, 0x3e007c01, "bgt\t\t%b" }, + {0x08002000, 0x3e007c01, "bge\t\t%b" }, + {0x08000801, 0x3e007c01, "bgtul\t\t%b" }, + {0x08001801, 0x3e007c01, "bgtl\t\t%b" }, + {0x08002001, 0x3e007c01, "bgel\t\t%b" }, + {0x00004200, 0x00007f00, "bgtu!\t\t%b" }, + {0x00004600, 0x00007f00, "bgt!\t\t%b" }, + {0x00004800, 0x00007f00, "bge!\t\t%b" }, + {0x00000029, 0x3e0003ff, "bitclr.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002b, 0x3e0003ff, "bitset.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x0000002d, 0x3e0003ff, "bittst.c\t%15-19r, 0x%10-14x"}, + {0x0000002f, 0x3e0003ff, "bittgl.c\t%20-24r, %15-19r, 0x%10-14x"}, + {0x00006004, 0x00007007, "bitclr!\t\t%8-11r, 0x%3-7x"}, + {0x3800000c, 0x3e0003ff, "bitrev\t\t%20-24r, %15-19r,%10-14r"}, + {0x00006005, 0x00007007, "bitset!\t\t%8-11r, 0x%3-7x"}, + {0x00006006, 0x00007007, "bittst!\t\t%8-11r, 0x%3-7x"}, + {0x00006007, 0x00007007, "bittgl!\t\t%8-11r, 0x%3-7x"}, + {0x08000c00, 0x3e007c01, "bleu\t\t%b" }, + {0x08001c00, 0x3e007c01, "ble\t\t%b" }, + {0x08002400, 0x3e007c01, "blt\t\t%b" }, + {0x08000c01, 0x3e007c01, "bleul\t\t%b" }, + {0x08001c01, 0x3e007c01, "blel\t\t%b" }, + {0x08002401, 0x3e007c01, "bltl\t\t%b" }, + {0x08003c01, 0x3e007c01, "bl\t\t%b" }, + {0x00004300, 0x00007f00, "bleu!\t\t%b" }, + {0x00004700, 0x00007f00, "ble!\t\t%b" }, + {0x00004900, 0x00007f00, "blt!\t\t%b" }, + {0x08002800, 0x3e007c01, "bmi\t\t%b" }, + {0x08002801, 0x3e007c01, "bmil\t\t%b" }, + {0x00004a00, 0x00007f00, "bmi!\t\t%b" }, + {0x08001400, 0x3e007c01, "bne\t\t%b" }, + {0x08001401, 0x3e007c01, "bnel\t\t%b" }, + {0x00004500, 0x00007f00, "bne!\t\t%b" }, + {0x08002c00, 0x3e007c01, "bpl\t\t%b" }, + {0x08002c01, 0x3e007c01, "bpll\t\t%b" }, + {0x00004b00, 0x00007f00, "bpl!\t\t%b" }, + {0x00000008, 0x3e007fff, "brcs\t\t%15-19r" }, + {0x00000408, 0x3e007fff, "brcc\t\t%15-19r" }, + {0x00000808, 0x3e007fff, "brgtu\t\t%15-19r" }, + {0x00000c08, 0x3e007fff, "brleu\t\t%15-19r" }, + {0x00001008, 0x3e007fff, "breq\t\t%15-19r" }, + {0x00001408, 0x3e007fff, "brne\t\t%15-19r" }, + {0x00001808, 0x3e007fff, "brgt\t\t%15-19r" }, + {0x00001c08, 0x3e007fff, "brle\t\t%15-19r" }, + {0x00002008, 0x3e007fff, "brge\t\t%15-19r" }, + {0x00002408, 0x3e007fff, "brlt\t\t%15-19r" }, + {0x00002808, 0x3e007fff, "brmi\t\t%15-19r" }, + {0x00002c08, 0x3e007fff, "brpl\t\t%15-19r" }, + {0x00003008, 0x3e007fff, "brvs\t\t%15-19r" }, + {0x00003408, 0x3e007fff, "brvc\t\t%15-19r" }, + {0x00003808, 0x3e007fff, "brcnz\t\t%15-19r" }, + {0x00003c08, 0x3e007fff, "br\t\t%15-19r" }, + {0x00000009, 0x3e007fff, "brcsl\t\t%15-19r" }, + {0x00000409, 0x3e007fff, "brccl\t\t%15-19r" }, + {0x00000809, 0x3e007fff, "brgtul\t\t%15-19r" }, + {0x00000c09, 0x3e007fff, "brleul\t\t%15-19r" }, + {0x00001009, 0x3e007fff, "breql\t\t%15-19r" }, + {0x00001409, 0x3e007fff, "brnel\t\t%15-19r" }, + {0x00001809, 0x3e007fff, "brgtl\t\t%15-19r" }, + {0x00001c09, 0x3e007fff, "brlel\t\t%15-19r" }, + {0x00002009, 0x3e007fff, "brgel\t\t%15-19r" }, + {0x00002409, 0x3e007fff, "brltl\t\t%15-19r" }, + {0x00002809, 0x3e007fff, "brmil\t\t%15-19r" }, + {0x00002c09, 0x3e007fff, "brpll\t\t%15-19r" }, + {0x00003009, 0x3e007fff, "brvsl\t\t%15-19r" }, + {0x00003409, 0x3e007fff, "brvcl\t\t%15-19r" }, + {0x00003809, 0x3e007fff, "brcnzl\t\t%15-19r" }, + {0x00003c09, 0x3e007fff, "brl\t\t%15-19r" }, + {0x00000004, 0x00007f0f, "brcs!\t\t%4-7r" }, + {0x00000104, 0x00007f0f, "brcc!\t\t%4-7r" }, + {0x00000204, 0x00007f0f, "brgtu!\t\t%4-7r" }, + {0x00000304, 0x00007f0f, "brleu!\t\t%4-7r" }, + {0x00000404, 0x00007f0f, "breq!\t\t%4-7r" }, + {0x00000504, 0x00007f0f, "brne!\t\t%4-7r" }, + {0x00000604, 0x00007f0f, "brgt!\t\t%4-7r" }, + {0x00000704, 0x00007f0f, "brle!\t\t%4-7r" }, + {0x00000804, 0x00007f0f, "brge!\t\t%4-7r" }, + {0x00000904, 0x00007f0f, "brlt!\t\t%4-7r" }, + {0x00000a04, 0x00007f0f, "brmi!\t\t%4-7r" }, + {0x00000b04, 0x00007f0f, "brpl!\t\t%4-7r" }, + {0x00000c04, 0x00007f0f, "brvs!\t\t%4-7r" }, + {0x00000d04, 0x00007f0f, "brvc!\t\t%4-7r" }, + {0x00000e04, 0x00007f0f, "brcnz!\t\t%4-7r" }, + {0x00000f04, 0x00007f0f, "br!\t\t%4-7r" }, + {0x0000000c, 0x00007f0f, "brcsl!\t\t%4-7r" }, + {0x0000010c, 0x00007f0f, "brccl!\t\t%4-7r" }, + {0x0000020c, 0x00007f0f, "brgtul!\t\t%4-7r" }, + {0x0000030c, 0x00007f0f, "brleul!\t\t%4-7r" }, + {0x0000040c, 0x00007f0f, "breql!\t\t%4-7r" }, + {0x0000050c, 0x00007f0f, "brnel!\t\t%4-7r" }, + {0x0000060c, 0x00007f0f, "brgtl!\t\t%4-7r" }, + {0x0000070c, 0x00007f0f, "brlel!\t\t%4-7r" }, + {0x0000080c, 0x00007f0f, "brgel!\t\t%4-7r" }, + {0x0000090c, 0x00007f0f, "brltl!\t\t%4-7r" }, + {0x00000a0c, 0x00007f0f, "brmil!\t\t%4-7r" }, + {0x00000b0c, 0x00007f0f, "brpll!\t\t%4-7r" }, + {0x00000c0c, 0x00007f0f, "brvsl!\t\t%4-7r" }, + {0x00000d0c, 0x00007f0f, "brvcl!\t\t%4-7r" }, + {0x00000e0c, 0x00007f0f, "brcnzl!\t\t%4-7r" }, + {0x00000f0c, 0x00007f0f, "brl!\t\t%4-7r" }, + {0x08003000, 0x3e007c01, "bvs\t\t%b" }, + {0x08003400, 0x3e007c01, "bvc\t\t%b" }, + {0x08003001, 0x3e007c01, "bvsl\t\t%b" }, + {0x08003401, 0x3e007c01, "bvcl\t\t%b" }, + {0x00004c00, 0x00007f00, "bvs!\t\t%b" }, + {0x00004d00, 0x00007f00, "bvc!\t\t%b" }, + {0x00004f00, 0x00007f00, "b!\t\t%b" }, + {0x08003c00, 0x3e007c01, "b\t\t%b" }, + {0x30000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30200000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30300000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30400000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30900000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x30e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31000000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31100000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31800000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31a00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31b00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31c00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31d00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, + {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"}, + {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"}, + {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"}, + {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"}, + {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"}, + {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"}, + {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"}, + {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"}, + {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"}, + {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"}, + {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"}, + {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"}, + {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"}, + {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"}, + {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"}, + {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"}, + {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"}, + {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"}, + {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"}, + {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"}, + {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"}, + {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"}, + {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"}, + {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"}, + {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"}, + {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"}, + {0x00300019, 0x3ff003ff, "cmp.c\t\t%15-19r, %10-14r"}, + {0x0000001b, 0x3ff07fff, "cmpzteq.c\t%15-19r"}, + {0x0010001b, 0x3ff07fff, "cmpztmi.c\t%15-19r"}, + {0x0030001b, 0x3ff07fff, "cmpz.c\t\t%15-19r"}, + {0x02040001, 0x3e0e0001, "cmpi.c\t\t%20-24r, %1-16i"}, + {0x00002003, 0x0000700f, "cmp!\t\t%8-11r, %4-7r"}, + {0x0c00000c, 0x3e00001f, "cop1\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x0c000014, 0x3e00001f, "cop2\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x0c00001c, 0x3e00001f, "cop3\t\tc%20-24r, c%15-19r, c%10-14r, %5-9d"}, + {0x00000044, 0x3e0003ff, "div\t\t%15-19r, %10-14r"}, + {0x00000046, 0x3e0003ff, "divu\t\t%15-19r, %10-14r"}, + {0x0c0000a4, 0x3e0003ff, "drte" }, + {0x00000058, 0x3e0003ff, "extsb\t\t%20-24r, %15-19r"}, + {0x00000059, 0x3e0003ff, "extsb.c\t\t%20-24r, %15-19r"}, + {0x0000005a, 0x3e0003ff, "extsh\t\t%20-24r, %15-19r"}, + {0x0000005b, 0x3e0003ff, "extsh.c\t\t%20-24r, %15-19r"}, + {0x0000005c, 0x3e0003ff, "extzb\t\t%20-24r, %15-19r"}, + {0x0000005d, 0x3e0003ff, "extzb.c\t\t%20-24r, %15-19r"}, + {0x0000005e, 0x3e0003ff, "extzh\t\t%20-24r, %15-19r"}, + {0x0000005f, 0x3e0003ff, "extzh.c\t\t%20-24r, %15-19r"}, + {0x04000001, 0x3e000001, "jl\t\t%j"}, + {0x00003001, 0x00007001, "jl!\t\t%j" }, + {0x00003000, 0x00007001, "j!\t\t%j" }, + {0x04000000, 0x3e000001, "j\t\t%j"}, + {0x26000000, 0x3e000000, "lb\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x2c000000, 0x3e000000, "lbu\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x06000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000003, 0x3e000007, "lb\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0e000006, 0x3e000007, "lbu\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000200b, 0x0000700f, "lbu!\t\t%8-11r, [%4-7r]"}, + {0x00007003, 0x00007007, "lbup!\t\t%8-11r, %3-7d"}, + {0x00000060, 0x3e0003ff, "lcb\t\t[%15-19r]+"}, + {0x00000062, 0x3e0003ff, "lcw\t\t%20-24r, [%15-19r]+"}, + {0x00000066, 0x3e0003ff, "lce\t\t%20-24r, [%15-19r]+"}, + {0x0c00000a, 0x3e00001f, "ldc1\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c000012, 0x3e00001f, "ldc2\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c00001a, 0x3e00001f, "ldc3\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x22000000, 0x3e000000, "lh\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x24000000, 0x3e000000, "lhu\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x06000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000001, 0x3e000007, "lh\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0e000002, 0x3e000007, "lhu\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00002009, 0x0000700f, "lh!\t\t%8-11r, [%4-7r]"}, + {0x00007001, 0x00007007, "lhp!\t\t%8-11r, %3-7d1"}, + {0x020c0000, 0x3e0e0000, "ldi\t\t%20-24r, 0x%1-16x(%1-16i)"}, + {0x0a0c0000, 0x3e0e0000, "ldis\t\t%20-24r, 0x%1-16x(%1-16i)"}, + {0x00005000, 0x00007000, "ldiu!\t\t%8-11r, %0-7d"}, + {0x0000000c, 0x3e0003ff, "alw\t\t%20-24r, [%15-19r]"}, + {0x20000000, 0x3e000000, "lw\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x00002008, 0x0000700f, "lw!\t\t%8-11r, [%4-7r]"}, + {0x00007000, 0x00007007, "lwp!\t\t%8-11r, %3-7d2"}, + {0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"}, + {0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"}, + {0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"}, + {0x00001004, 0x0000700f, "mad.f!\t\t%8-11r, %4-7r"}, + {0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"}, + {0x00001008, 0x0000700f, "mazl.f!\t\t%8-11r, %4-7r"}, + {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"}, + {0x00001001, 0x00007f0f, "mfcel!\t\t%4-7r"}, + {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"}, + {0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"}, + {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"}, + {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"}, + {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"}, + {0x0c000001, 0x3e00001f, "mfcr\t\t%20-24r, c%15-19r"}, + {0x0c000009, 0x3e00001f, "mfc1\t\t%20-24r, c%15-19r"}, + {0x0c000011, 0x3e00001f, "mfc2\t\t%20-24r, c%15-19r"}, + {0x0c000019, 0x3e00001f, "mfc3\t\t%20-24r, c%15-19r"}, + {0x0c00000f, 0x3e00001f, "mfcc1\t\t%20-24r, c%15-19r"}, + {0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"}, + {0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"}, + {0x00000002, 0x0000700f, "mhfl!\t\t%8-11R, %4-7r"}, + {0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"}, + {0x00001006, 0x0000700f, "msb.f!\t\t%8-11r, %4-7r"}, + {0x0000100f, 0x0000700f, "msbh.fs!\t\t%8-11r, %4-7r"}, + {0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"}, + {0x00001007, 0x0000700f, "msbu!\t\t%8-11r, %4-7r"}, + {0x0000100d, 0x0000700f, "mszh.f!\t\t%8-11r, %4-7r"}, + {0x0000100c, 0x0000700f, "mszl.f!\t\t%8-11r, %4-7r"}, + {0x0000044a, 0x3e007fff, "mtcel\t\t%20-24r"}, + {0x00001000, 0x00007f0f, "mtcel!\t\t%4-7r"}, + {0x0000084a, 0x3e007fff, "mtceh\t\t%20-24r"}, + {0x00001100, 0x00007f0f, "mtceh!\t\t%4-7r"}, + {0x00000c4a, 0x3e007fff, "mtcehl\t\t%20-24r, %15-19r"}, + {0x0000004a, 0x3e0003ff, "mtce\t\t%20-24r, er%10-14d"}, + {0x00000052, 0x3e0003ff, "mtsr\t\t%15-19r, sr%10-14d"}, + {0x0c000000, 0x3e00001f, "mtcr\t\t%20-24r, c%15-19r"}, + {0x0c000008, 0x3e00001f, "mtc1\t\t%20-24r, c%15-19r"}, + {0x0c000010, 0x3e00001f, "mtc2\t\t%20-24r, c%15-19r"}, + {0x0c000018, 0x3e00001f, "mtc3\t\t%20-24r, c%15-19r"}, + {0x0c00000e, 0x3e00001f, "mtcc1\t\t%20-24r, c%15-19r"}, + {0x0c000016, 0x3e00001f, "mtcc2\t\t%20-24r, c%15-19r"}, + {0x0c00001e, 0x3e00001f, "mtcc3\t\t%20-24r, c%15-19r"}, + {0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"}, + {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"}, + {0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"}, + {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"}, + {0x00001002, 0x0000700f, "mul.f!\t\t%8-11r, %4-7r"}, + {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"}, + {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"}, + {0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"}, + {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"}, + {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"}, + {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"}, + {0x00000c56, 0x3e007fff, "mvleu\t\t%20-24r, %15-19r"}, + {0x00001056, 0x3e007fff, "mveq\t\t%20-24r, %15-19r"}, + {0x00001456, 0x3e007fff, "mvne\t\t%20-24r, %15-19r"}, + {0x00001856, 0x3e007fff, "mvgt\t\t%20-24r, %15-19r"}, + {0x00001c56, 0x3e007fff, "mvle\t\t%20-24r, %15-19r"}, + {0x00002056, 0x3e007fff, "mvge\t\t%20-24r, %15-19r"}, + {0x00002456, 0x3e007fff, "mvlt\t\t%20-24r, %15-19r"}, + {0x00002856, 0x3e007fff, "mvmi\t\t%20-24r, %15-19r"}, + {0x00002c56, 0x3e007fff, "mvpl\t\t%20-24r, %15-19r"}, + {0x00003056, 0x3e007fff, "mvvs\t\t%20-24r, %15-19r"}, + {0x00003456, 0x3e007fff, "mvvc\t\t%20-24r, %15-19r"}, + {0x00003c56, 0x3e007fff, "mv\t\t%20-24r, %15-19r"}, + {0x00000003, 0x0000700f, "mv!\t\t%8-11r, %4-7r"}, + {0x0000001e, 0x3e0003ff, "neg\t\t%20-24r, %10-14r" }, + {0x0000001f, 0x3e0003ff, "neg.c\t\t%20-24r, %10-14r" }, + {0x00002002, 0x0000700f, "neg!\t\t%8-11r, %4-7r"}, + {0x00000000, 0x3e0003ff, "nop" }, + {0x00000024, 0x3e0003ff, "not\t\t%20-24r, %15-19r" }, + {0x00000025, 0x3e0003ff, "not.c\t\t%20-24r, %15-19r" }, + {0x00000000, 0x0000700f, "nop!" }, + {0x00002006, 0x0000700f, "not!\t\t%8-11r, %4-7r"}, + {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"}, + {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"}, + {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"}, + {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"}, + {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x1a000001, 0x3e000001, "orri.c\t\t%20-24r, %15-19r, 0x%1-14x"}, + {0x00002005, 0x0000700f, "or!\t\t%8-11r, %4-7r"}, + {0x0000000a, 0x3e0003ff, "pflush"}, + {0x0000208a, 0x0000708f, "pop!\t\t%8-11R, [%4-6r]"}, + {0x0000200a, 0x0000700f, "pop!\t\t%8-11r, [%4-7r]"}, + {0x0000208e, 0x0000708f, "push!\t\t%8-11R, [%4-6r]"}, + {0x0000200e, 0x0000700f, "push!\t\t%8-11r, [%4-7r]"}, + {0x00000038, 0x3e0003ff, "ror\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000039, 0x3e0003ff, "ror.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003b, 0x3e0003ff, "rorc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003c, 0x3e0003ff, "rol\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003d, 0x3e0003ff, "rol.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x0000003f, 0x3e0003ff, "rolc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000078, 0x3e0003ff, "rori\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000079, 0x3e0003ff, "rori.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007b, 0x3e0003ff, "roric.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007c, 0x3e0003ff, "roli\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007d, 0x3e0003ff, "roli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000007f, 0x3e0003ff, "rolic.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0c000084, 0x3e0003ff, "rte" }, + {0x2e000000, 0x3e000000, "sb\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000007, 0x3e000007, "sb\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000200f, 0x0000700f, "sb!\t\t%8-11r, [%4-7r]"}, + {0x00007007, 0x00007007, "sbp!\t\t%8-11r, %3-7d"}, + {0x0000000e, 0x3e0003ff, "asw\t\t%20-24r, [%15-19r]"}, + {0x00000068, 0x3e0003ff, "scb\t\t%20-24r, [%15-19r]+"}, + {0x0000006a, 0x3e0003ff, "scw\t\t%20-24r, [%15-19r]+"}, + {0x0000006e, 0x3e0003ff, "sce\t\t[%15-19r]+"}, + {0x00000006, 0x3e0003ff, "sdbbp\t\t%15-19d"}, + {0x00006002, 0x00007007, "sdbbp!\t\t%3-7d"}, + {0x2a000000, 0x3e000000, "sh\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000005, 0x3e000007, "sh\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000200d, 0x0000700f, "sh!\t\t%8-11r, [%4-7r]"}, + {0x00007005, 0x00007007, "shp!\t\t%8-11r, %3-7d1"}, + {0x0c0000c4, 0x3e0003ff, "sleep" }, + {0x00000030, 0x3e0003ff, "sll\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000031, 0x3e0003ff, "sll.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000070, 0x3e0003ff, "slli\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000071, 0x3e0003ff, "slli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000008, 0x0000700f, "sll!\t\t%8-11r, %4-7r"}, + {0x00006001, 0x00007007, "slli!\t\t%8-11r, %3-7d"}, + {0x00000034, 0x3e0003ff, "srl\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000035, 0x3e0003ff, "srl.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000036, 0x3e0003ff, "sra\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000037, 0x3e0003ff, "sra.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000074, 0x3e0003ff, "srli\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000075, 0x3e0003ff, "srli.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000076, 0x3e0003ff, "srai\t\t%20-24r, %15-19r, %10-14d"}, + {0x00000077, 0x3e0003ff, "srai.c\t\t%20-24r, %15-19r, %10-14d"}, + {0x0000000a, 0x0000700f, "srl!\t\t%8-11r, %4-7r"}, + {0x00006003, 0x00007007, "srli!\t\t%8-11r, %3-7d"}, + {0x0000000b, 0x0000700f, "sra!\t\t%8-11r, %4-7r"}, + {0x0c00000b, 0x3e00001f, "stc1\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c000013, 0x3e00001f, "stc2\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x0c00001b, 0x3e00001f, "stc3\t\tc%15-19r, [%20-24r, %5-14i]"}, + {0x00000014, 0x3e0003ff, "sub\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000015, 0x3e0003ff, "sub.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000016, 0x3e0003ff, "subc\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000017, 0x3e0003ff, "subc.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00002001, 0x0000700f, "sub!\t\t%8-11r, %4-7r"}, + {0x00006080, 0x00007087, "subei!\t\t%8-11r, %3-6d"}, + {0x28000000, 0x3e000000, "sw\t\t%20-24r, [%15-19r, %0-14i]"}, + {0x06000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r, %3-14i]+"}, + {0x0e000004, 0x3e000007, "sw\t\t%20-24r, [%15-19r]+, %3-14i"}, + {0x0000200c, 0x0000700f, "sw!\t\t%8-11r, [%4-7r]"}, + {0x00007004, 0x00007007, "swp!\t\t%8-11r, %3-7d2"}, + {0x00000002, 0x3e0003ff, "syscall\t\t%10-24d"}, + {0x00000054, 0x3e007fff, "tcs" }, + {0x00000454, 0x3e007fff, "tcc" }, + {0x00003854, 0x3e007fff, "tcnz" }, + {0x00000005, 0x00007f0f, "tcs!" }, + {0x00000105, 0x00007f0f, "tcc!" }, + {0x00000e05, 0x00007f0f, "tcnz!" }, + {0x00001054, 0x3e007fff, "teq" }, + {0x00000405, 0x00007f0f, "teq!" }, + {0x00000854, 0x3e007fff, "tgtu" }, + {0x00001854, 0x3e007fff, "tgt" }, + {0x00002054, 0x3e007fff, "tge" }, + {0x00000205, 0x00007f0f, "tgtu!" }, + {0x00000605, 0x00007f0f, "tgt!" }, + {0x00000805, 0x00007f0f, "tge!" }, + {0x00000c54, 0x3e007fff, "tleu" }, + {0x00001c54, 0x3e007fff, "tle" }, + {0x00002454, 0x3e007fff, "tlt" }, + {0x0c000004, 0x3e0003ff, "stlb" }, + {0x0c000024, 0x3e0003ff, "mftlb" }, + {0x0c000044, 0x3e0003ff, "mtptlb" }, + {0x0c000064, 0x3e0003ff, "mtrtlb" }, + {0x00000305, 0x00007f0f, "tleu!" }, + {0x00000705, 0x00007f0f, "tle!" }, + {0x00000905, 0x00007f0f, "tlt!" }, + {0x00002854, 0x3e007fff, "tmi" }, + {0x00000a05, 0x00007f0f, "tmi!" }, + {0x00001454, 0x3e007fff, "tne" }, + {0x00000505, 0x00007f0f, "tne!" }, + {0x00002c54, 0x3e007fff, "tpl" }, + {0x00000b05, 0x00007f0f, "tpl!" }, + {0x00000004, 0x3e007fff, "trapcs\t\t%15-19d"}, + {0x00000404, 0x3e007fff, "trapcc\t\t%15-19d"}, + {0x00000804, 0x3e007fff, "trapgtu\t\t%15-19d"}, + {0x00000c04, 0x3e007fff, "trapleu\t\t%15-19d"}, + {0x00001004, 0x3e007fff, "trapeq\t\t%15-19d"}, + {0x00001404, 0x3e007fff, "trapne\t\t%15-19d"}, + {0x00001804, 0x3e007fff, "trapgt\t\t%15-19d"}, + {0x00001c04, 0x3e007fff, "traple\t\t%15-19d"}, + {0x00002004, 0x3e007fff, "trapge\t\t%15-19d"}, + {0x00002404, 0x3e007fff, "traplt\t\t%15-19d"}, + {0x00002804, 0x3e007fff, "trapmi\t\t%15-19d"}, + {0x00002c04, 0x3e007fff, "trappl\t\t%15-19d"}, + {0x00003004, 0x3e007fff, "trapvs\t\t%15-19d"}, + {0x00003404, 0x3e007fff, "trapvc\t\t%15-19d"}, + {0x00003c04, 0x3e007fff, "trap\t\t%15-19d"}, + {0x00003c54, 0x3e007fff, "tset" }, + {0x00000f05, 0x00007f0f, "tset!" }, + {0x00003054, 0x3e007fff, "tvs" }, + {0x00003454, 0x3e007fff, "tvc" }, + {0x00000c05, 0x00007f0f, "tvs!" }, + {0x00000d05, 0x00007f0f, "tvc!" }, + {0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"}, + {0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"}, + {0x00002007, 0x0000700f, "xor!\t\t%8-11r, %4-7r"} +}; diff --git a/contrib/binutils/opcodes/sh-dis.c b/contrib/binutils/opcodes/sh-dis.c index 381fa4d..0dee910 100644 --- a/contrib/binutils/opcodes/sh-dis.c +++ b/contrib/binutils/opcodes/sh-dis.c @@ -924,11 +924,11 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info) } if ((*info->symbol_at_address_func) (val, info)) { - fprintf_fn (stream, "\t! 0x"); + fprintf_fn (stream, "\t! "); (*info->print_address_func) (val, info); } else - fprintf_fn (stream, "\t! 0x%x", val); + fprintf_fn (stream, "\t! %x", val); } } diff --git a/contrib/binutils/opcodes/spu-dis.c b/contrib/binutils/opcodes/spu-dis.c new file mode 100644 index 0000000..a0dd1a0 --- /dev/null +++ b/contrib/binutils/opcodes/spu-dis.c @@ -0,0 +1,260 @@ +/* Disassemble SPU instructions + + Copyright 2006 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include <stdio.h> +#include "sysdep.h" +#include "dis-asm.h" +#include "opcode/spu.h" + +/* This file provides a disassembler function which uses + the disassembler interface defined in dis-asm.h. */ + +extern const struct spu_opcode spu_opcodes[]; +extern const int spu_num_opcodes; + +static const struct spu_opcode *spu_disassemble_table[(1<<11)]; + +static void +init_spu_disassemble (void) +{ + int i; + + /* If two instructions have the same opcode then we prefer the first + * one. In most cases it is just an alternate mnemonic. */ + for (i = 0; i < spu_num_opcodes; i++) + { + int o = spu_opcodes[i].opcode; + if (o >= (1 << 11)) + abort (); + if (spu_disassemble_table[o] == 0) + spu_disassemble_table[o] = &spu_opcodes[i]; + } +} + +/* Determine the instruction from the 10 least significant bits. */ +static const struct spu_opcode * +get_index_for_opcode (unsigned int insn) +{ + const struct spu_opcode *index; + unsigned int opcode = insn >> (32-11); + + /* Init the table. This assumes that element 0/opcode 0 (currently + * NOP) is always used */ + if (spu_disassemble_table[0] == 0) + init_spu_disassemble (); + + if ((index = spu_disassemble_table[opcode & 0x780]) != 0 + && index->insn_type == RRR) + return index; + + if ((index = spu_disassemble_table[opcode & 0x7f0]) != 0 + && (index->insn_type == RI18 || index->insn_type == LBT)) + return index; + + if ((index = spu_disassemble_table[opcode & 0x7f8]) != 0 + && index->insn_type == RI10) + return index; + + if ((index = spu_disassemble_table[opcode & 0x7fc]) != 0 + && (index->insn_type == RI16)) + return index; + + if ((index = spu_disassemble_table[opcode & 0x7fe]) != 0 + && (index->insn_type == RI8)) + return index; + + if ((index = spu_disassemble_table[opcode & 0x7ff]) != 0) + return index; + + return 0; +} + +/* Print a Spu instruction. */ + +int +print_insn_spu (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[4]; + int value; + int hex_value; + int status; + unsigned int insn; + const struct spu_opcode *index; + enum spu_insns tag; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = bfd_getb32 (buffer); + + index = get_index_for_opcode (insn); + + if (index == 0) + { + (*info->fprintf_func) (info->stream, ".long 0x%x", insn); + } + else + { + int i; + int paren = 0; + tag = (enum spu_insns)(index - spu_opcodes); + (*info->fprintf_func) (info->stream, "%s", index->mnemonic); + if (tag == M_BI || tag == M_BISL || tag == M_IRET || tag == M_BISLED + || tag == M_BIHNZ || tag == M_BIHZ || tag == M_BINZ || tag == M_BIZ + || tag == M_SYNC || tag == M_HBR) + { + int fb = (insn >> (32-18)) & 0x7f; + if (fb & 0x40) + (*info->fprintf_func) (info->stream, tag == M_SYNC ? "c" : "p"); + if (fb & 0x20) + (*info->fprintf_func) (info->stream, "d"); + if (fb & 0x10) + (*info->fprintf_func) (info->stream, "e"); + } + if (index->arg[0] != 0) + (*info->fprintf_func) (info->stream, "\t"); + hex_value = 0; + for (i = 1; i <= index->arg[0]; i++) + { + int arg = index->arg[i]; + if (arg != A_P && !paren && i > 1) + (*info->fprintf_func) (info->stream, ","); + + switch (arg) + { + case A_T: + (*info->fprintf_func) (info->stream, "$%d", + DECODE_INSN_RT (insn)); + break; + case A_A: + (*info->fprintf_func) (info->stream, "$%d", + DECODE_INSN_RA (insn)); + break; + case A_B: + (*info->fprintf_func) (info->stream, "$%d", + DECODE_INSN_RB (insn)); + break; + case A_C: + (*info->fprintf_func) (info->stream, "$%d", + DECODE_INSN_RC (insn)); + break; + case A_S: + (*info->fprintf_func) (info->stream, "$sp%d", + DECODE_INSN_RA (insn)); + break; + case A_H: + (*info->fprintf_func) (info->stream, "$ch%d", + DECODE_INSN_RA (insn)); + break; + case A_P: + paren++; + (*info->fprintf_func) (info->stream, "("); + break; + case A_U7A: + (*info->fprintf_func) (info->stream, "%d", + 173 - DECODE_INSN_U8 (insn)); + break; + case A_U7B: + (*info->fprintf_func) (info->stream, "%d", + 155 - DECODE_INSN_U8 (insn)); + break; + case A_S3: + case A_S6: + case A_S7: + case A_S7N: + case A_U3: + case A_U5: + case A_U6: + case A_U7: + hex_value = DECODE_INSN_I7 (insn); + (*info->fprintf_func) (info->stream, "%d", hex_value); + break; + case A_S11: + (*info->print_address_func) (memaddr + DECODE_INSN_I9a (insn) * 4, + info); + break; + case A_S11I: + (*info->print_address_func) (memaddr + DECODE_INSN_I9b (insn) * 4, + info); + break; + case A_S10: + case A_S10B: + hex_value = DECODE_INSN_I10 (insn); + (*info->fprintf_func) (info->stream, "%d", hex_value); + break; + case A_S14: + hex_value = DECODE_INSN_I10 (insn) * 16; + (*info->fprintf_func) (info->stream, "%d", hex_value); + break; + case A_S16: + hex_value = DECODE_INSN_I16 (insn); + (*info->fprintf_func) (info->stream, "%d", hex_value); + break; + case A_X16: + hex_value = DECODE_INSN_U16 (insn); + (*info->fprintf_func) (info->stream, "%u", hex_value); + break; + case A_R18: + value = DECODE_INSN_I16 (insn) * 4; + if (value == 0) + (*info->fprintf_func) (info->stream, "%d", value); + else + { + hex_value = memaddr + value; + (*info->print_address_func) (hex_value & 0x3ffff, info); + } + break; + case A_S18: + value = DECODE_INSN_U16 (insn) * 4; + if (value == 0) + (*info->fprintf_func) (info->stream, "%d", value); + else + (*info->print_address_func) (value, info); + break; + case A_U18: + value = DECODE_INSN_U18 (insn); + if (value == 0 || !(*info->symbol_at_address_func)(0, info)) + { + hex_value = value; + (*info->fprintf_func) (info->stream, "%u", value); + } + else + (*info->print_address_func) (value, info); + break; + case A_U14: + hex_value = DECODE_INSN_U14 (insn); + (*info->fprintf_func) (info->stream, "%u", hex_value); + break; + } + if (arg != A_P && paren) + { + (*info->fprintf_func) (info->stream, ")"); + paren--; + } + } + if (hex_value > 16) + (*info->fprintf_func) (info->stream, "\t# %x", hex_value); + } + return 4; +} diff --git a/contrib/binutils/opcodes/spu-opc.c b/contrib/binutils/opcodes/spu-opc.c new file mode 100644 index 0000000..683f96f --- /dev/null +++ b/contrib/binutils/opcodes/spu-opc.c @@ -0,0 +1,44 @@ +/* SPU opcode list + + Copyright 2006 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "opcode/spu.h" + +/* This file holds the Spu opcode table */ + + +/* + Example contents of spu-insn.h + id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction + QUAD WORD (0,RC,RB,RA,RT) latency + APUOP(M_LQD, 1, 0, RI9, 0x1f8, "lqd", ASM_RI9IDX, 00012, FXU, 1, 0) Load Quadword d-form + */ + +const struct spu_opcode spu_opcodes[] = { +#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT }, +#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT }, +#include "opcode/spu-insns.h" +#undef APUOP +#undef APUOPFB +}; + +const int spu_num_opcodes = + sizeof (spu_opcodes) / sizeof (spu_opcodes[0]); |
