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-rw-r--r--contrib/binutils/opcodes/ChangeLog75
-rw-r--r--contrib/binutils/opcodes/arc-dis.c1365
-rw-r--r--contrib/binutils/opcodes/arc-dis.h81
-rw-r--r--contrib/binutils/opcodes/arc-ext.c259
-rw-r--r--contrib/binutils/opcodes/arc-ext.h62
-rw-r--r--contrib/binutils/opcodes/arc-opc.c1378
-rw-r--r--contrib/binutils/opcodes/cgen-asm.c6
-rw-r--r--contrib/binutils/opcodes/cgen-asm.in321
-rw-r--r--contrib/binutils/opcodes/cgen-dis.c55
-rw-r--r--contrib/binutils/opcodes/cgen-dis.in417
-rw-r--r--contrib/binutils/opcodes/cgen-ibld.in514
-rw-r--r--contrib/binutils/opcodes/cgen-opc.c62
-rw-r--r--contrib/binutils/opcodes/cgen.sh154
-rw-r--r--contrib/binutils/opcodes/i386-dis.c3102
-rw-r--r--contrib/binutils/opcodes/ia64-asmtab.c794
-rw-r--r--contrib/binutils/opcodes/sh-dis.c170
-rw-r--r--contrib/binutils/opcodes/sh-opc.h127
17 files changed, 5643 insertions, 3299 deletions
diff --git a/contrib/binutils/opcodes/ChangeLog b/contrib/binutils/opcodes/ChangeLog
index a3bacf9..ad0dc07 100644
--- a/contrib/binutils/opcodes/ChangeLog
+++ b/contrib/binutils/opcodes/ChangeLog
@@ -1,3 +1,78 @@
+2001-10-24 Richard Henderson <rth@redhat.com>
+
+ * ia64-asmtab.c: Regenerate.
+
+2001-10-09 Nick Clifton <nickc@cambridge.redhat.com>
+
+ * sh-opc.h: Fix encoding of least significant nibble of the
+ DSP single data transfer instructions.
+
+ * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP
+ instructions.
+
+2001-09-04 Alan Modra <amodra@bigpond.net.au>
+
+ * i386-dis.c (grps): Don't print the implicit al/ax/eax register
+ for opcode 0xf6 or 0xf7 forms of mul, imul, div, idiv insns.
+
+ Merge from mainline.
+ 2001-07-28 Kazu Hirata <kazu@hxi.com>
+ * i386-dis.c: Fix formatting.
+
+ 2001-07-28 Matthias Kramm <kramm@quiss.org>
+ * i386-dis.c: Change formatting conventions for architecture
+ i386:intel to better match the format of various intel i386
+ assemblers, like nasm, tasm or masm.
+
+ 2001-07-18 Alan Modra <amodra@bigpond.net.au>
+ * i386-dis.c (grps): Print l or w suffix, and require mem modrm
+ for lgdt, lidt, sgdt, sidt.
+
+ 2001-07-09 Andreas Jaeger <aj@suse.de>, Karsten Keil <kkeil@suse.de>
+ * i386-dis.c (set_op): Handle 64 bit and 32 bit mode.
+ (OP_J): Use bfd_vma for mask to work properly with 64 bits.
+ (op_address,op_riprel): Use bfd_vma to handle 64 bits.
+
+ 2001-06-11 Alan Modra <amodra@bigpond.net.au>
+ * i386-dis.c: Group function prototypes in one place.
+ (FLOATCODE): Redefine as 1.
+ (USE_GROUPS): Redefine as 2.
+ (USE_PREFIX_USER_TABLE): Redefine as 3.
+ (X86_64_SPECIAL): Define as 4.
+ (GRP1b..GRPAMD): Move USE_GROUPS to bytecode1, index to bytecode2.
+ (PREGRP0..PREGRP26): Similarly with USE_PREFIX_USER_TABLE.
+ (dis386_att, dis386_intel, disx86_64_att, disx86_64_intel): Delete.
+ (dis386): New table combining above four tables.
+ (dis386_twobyte_att, dis386_twobyte_intel): Delete.
+ (dis386_twobyte): New table combining above two tables.
+ (x86_64_table): New table to handle x86_64.
+ (X86_64_0): Define.
+ (float_mem_att, float_mem_intel): Delet.
+ (float_mem): New table combining above two tables.
+ (print_insn_i386): Modify for above.
+ (dofloat): Likewise.
+ (putop): Handle '{', '|' and '}' to select alternative mnemonics.
+ Return 0 on success, 1 if no valid alternative.
+ (putop <case 'F'>, <case 'H'>): Print nothing for intel_syntax.
+ (putop <case 'T'>): Move to case 'U', and share case 'Q' code.
+ (putop <case 'I'>): Move to case 'T', and share case 'P' code.
+ (OP_REG <case rAX_reg .. rDI_reg>): Handle as for eAX_reg .. eDI_reg
+ if not 64-bit mode.
+ (OP_I <case q_mode>): Handle as for v_mode if not 64-bit mode.
+ (OP_I64): If not 64-bit mode, call OP_I.
+ OP_OFF64): If not 64-bit mode, call OP_OFF.
+ (OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename
+ 'ignore'/'ignored' to 'bytemode'.
+
+ 2001-06-10 Alan Modra <amodra@bigpond.net.au>
+ * i386-dis.c (dis386_att): Add 'H' to conditional branch and
+ loop,jcxz insns.
+ (disx86_64_att): Likewise.
+ (dis386_twobyte_att): Likewise.
+ (print_insn_i386): Don't print branch hints as a prefix.
+ (putop): 'H' macro prints branch hints.
+ (get64): Kill compile warnings.
+
2001-07-16 Philip Blundell <philb@gnu.org>
* arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR.
diff --git a/contrib/binutils/opcodes/arc-dis.c b/contrib/binutils/opcodes/arc-dis.c
index 03f1379..18325a9 100644
--- a/contrib/binutils/opcodes/arc-dis.c
+++ b/contrib/binutils/opcodes/arc-dis.c
@@ -1,268 +1,1221 @@
/* Instruction printing code for the ARC.
- Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 1997, 1998, 2000, 2001
+ Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-#include "sysdep.h"
+#include <ansidecl.h>
+#include <libiberty.h>
#include "dis-asm.h"
#include "opcode/arc.h"
#include "elf-bfd.h"
#include "elf/arc.h"
+#include <string.h>
#include "opintl.h"
-static int print_insn_arc_base_little PARAMS ((bfd_vma, disassemble_info *));
-static int print_insn_arc_base_big PARAMS ((bfd_vma, disassemble_info *));
+#include <ctype.h>
+#include <stdarg.h>
+#include "arc-dis.h"
+#include "arc-ext.h"
-static int print_insn PARAMS ((bfd_vma, disassemble_info *, int, int));
+#ifndef dbg
+#define dbg (0)
+#endif
-/* Print one instruction from PC on INFO->STREAM.
- Return the size of the instruction (4 or 8 for the ARC). */
+#define BIT(word,n) ((word) & (1 << n))
+#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
+#define OPCODE(word) (BITS ((word), 27, 31))
+#define FIELDA(word) (BITS ((word), 21, 26))
+#define FIELDB(word) (BITS ((word), 15, 20))
+#define FIELDC(word) (BITS ((word), 9, 14))
-static int
-print_insn (pc, info, mach, big_p)
- bfd_vma pc;
- disassemble_info *info;
- int mach;
- int big_p;
+/* FIELD D is signed in all of its uses, so we make sure argument is
+ treated as signed for bit shifting purposes: */
+#define FIELDD(word) (BITS (((signed int)word), 0, 8))
+
+#define PUT_NEXT_WORD_IN(a) \
+ do \
+ { \
+ if (is_limm == 1 && !NEXT_WORD (1)) \
+ mwerror (state, _("Illegal limm reference in last instruction!\n")); \
+ a = state->words[1]; \
+ } \
+ while (0)
+
+#define CHECK_FLAG_COND_NULLIFY() \
+ do \
+ { \
+ if (is_shimm == 0) \
+ { \
+ flag = BIT (state->words[0], 8); \
+ state->nullifyMode = BITS (state->words[0], 5, 6); \
+ cond = BITS (state->words[0], 0, 4); \
+ } \
+ } \
+ while (0)
+
+#define CHECK_COND() \
+ do \
+ { \
+ if (is_shimm == 0) \
+ cond = BITS (state->words[0], 0, 4); \
+ } \
+ while (0)
+
+#define CHECK_FIELD(field) \
+ do \
+ { \
+ if (field == 62) \
+ { \
+ is_limm++; \
+ field##isReg = 0; \
+ PUT_NEXT_WORD_IN (field); \
+ limm_value = field; \
+ } \
+ else if (field > 60) \
+ { \
+ field##isReg = 0; \
+ is_shimm++; \
+ flag = (field == 61); \
+ field = FIELDD (state->words[0]); \
+ } \
+ } \
+ while (0)
+
+#define CHECK_FIELD_A() \
+ do \
+ { \
+ fieldA = FIELDA(state->words[0]); \
+ if (fieldA > 60) \
+ { \
+ fieldAisReg = 0; \
+ fieldA = 0; \
+ } \
+ } \
+ while (0)
+
+#define CHECK_FIELD_B() \
+ do \
+ { \
+ fieldB = FIELDB (state->words[0]); \
+ CHECK_FIELD (fieldB); \
+ } \
+ while (0)
+
+#define CHECK_FIELD_C() \
+ do \
+ { \
+ fieldC = FIELDC (state->words[0]); \
+ CHECK_FIELD (fieldC); \
+ } \
+ while (0)
+
+#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
+#define IS_REG(x) (field##x##isReg)
+#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","")
+#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[")
+#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]")
+#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]")
+#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","")
+#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",")
+#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","")
+#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
+ (IS_REG (x) ? cb1"%r"ca1 : \
+ usesAuxReg ? cb"%a"ca : \
+ IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
+#define WRITE_FORMAT_RB() strcat (formatString, "]")
+#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
+#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
+
+#define NEXT_WORD(x) (offset += 4, state->words[x])
+
+#define add_target(x) (state->targets[state->tcnt++] = (x))
+
+static char comment_prefix[] = "\t; ";
+
+static const char *
+core_reg_name (state, val)
+ struct arcDisState * state;
+ int val;
{
- const struct arc_opcode *opcode;
- bfd_byte buffer[4];
- void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
- int status;
- /* First element is insn, second element is limm (if present). */
- arc_insn insn[2];
- int got_limm_p = 0;
- static int initialized = 0;
- static int current_mach = 0;
+ if (state->coreRegName)
+ return (*state->coreRegName)(state->_this, val);
+ return 0;
+}
- if (!initialized || mach != current_mach)
- {
- initialized = 1;
- current_mach = arc_get_opcode_mach (mach, big_p);
- arc_opcode_init_tables (current_mach);
- }
+static const char *
+aux_reg_name (state, val)
+ struct arcDisState * state;
+ int val;
+{
+ if (state->auxRegName)
+ return (*state->auxRegName)(state->_this, val);
+ return 0;
+}
- status = (*info->read_memory_func) (pc, buffer, 4, info);
- if (status != 0)
+static const char *
+cond_code_name (state, val)
+ struct arcDisState * state;
+ int val;
+{
+ if (state->condCodeName)
+ return (*state->condCodeName)(state->_this, val);
+ return 0;
+}
+
+static const char *
+instruction_name (state, op1, op2, flags)
+ struct arcDisState * state;
+ int op1;
+ int op2;
+ int * flags;
+{
+ if (state->instName)
+ return (*state->instName)(state->_this, op1, op2, flags);
+ return 0;
+}
+
+static void
+mwerror (state, msg)
+ struct arcDisState * state;
+ const char * msg;
+{
+ if (state->err != 0)
+ (*state->err)(state->_this, (msg));
+}
+
+static const char *
+post_address (state, addr)
+ struct arcDisState * state;
+ int addr;
+{
+ static char id[3 * ARRAY_SIZE (state->addresses)];
+ int j, i = state->acnt;
+
+ if (i < ((int) ARRAY_SIZE (state->addresses)))
{
- (*info->memory_error_func) (status, pc, info);
- return -1;
+ state->addresses[i] = addr;
+ ++state->acnt;
+ j = i*3;
+ id[j+0] = '@';
+ id[j+1] = '0'+i;
+ id[j+2] = 0;
+
+ return id + j;
}
- if (big_p)
- insn[0] = bfd_getb32 (buffer);
- else
- insn[0] = bfd_getl32 (buffer);
+ return "";
+}
- (*func) (stream, "%08lx\t", insn[0]);
+static void
+my_sprintf (
+ struct arcDisState * state,
+ char * buf,
+ const char * format,
+ ...)
+{
+ char *bp;
+ const char *p;
+ int size, leading_zero, regMap[2];
+ long auxNum;
+ va_list ap;
+
+ va_start (ap, format);
+
+ bp = buf;
+ *bp = 0;
+ p = format;
+ auxNum = -1;
+ regMap[0] = 0;
+ regMap[1] = 0;
+
+ while (1)
+ switch (*p++)
+ {
+ case 0:
+ goto DOCOMM; /* (return) */
+ default:
+ *bp++ = p[-1];
+ break;
+ case '%':
+ size = 0;
+ leading_zero = 0;
+ RETRY: ;
+ switch (*p++)
+ {
+ case '0':
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ {
+ /* size. */
+ size = p[-1] - '0';
+ if (size == 0)
+ leading_zero = 1; /* e.g. %08x */
+ while (*p >= '0' && *p <= '9')
+ {
+ size = size * 10 + *p - '0';
+ p++;
+ }
+ goto RETRY;
+ }
+#define inc_bp() bp = bp + strlen (bp)
- /* The instructions are stored in lists hashed by the insn code
- (though we needn't care how they're hashed). */
+ case 'h':
+ {
+ unsigned u = va_arg (ap, int);
- opcode = arc_opcode_lookup_dis (insn[0]);
- for ( ; opcode != NULL; opcode = ARC_OPCODE_NEXT_DIS (opcode))
- {
- char *syn;
- int mods,invalid;
- long value;
- const struct arc_operand *operand;
- const struct arc_operand_value *opval;
-
- /* Basic bit mask must be correct. */
- if ((insn[0] & opcode->mask) != opcode->value)
- continue;
-
- /* Supported by this cpu? */
- if (! arc_opcode_supported (opcode))
- continue;
-
- /* Make two passes over the operands. First see if any of them
- have extraction functions, and, if they do, make sure the
- instruction is valid. */
-
- arc_opcode_init_extract ();
- invalid = 0;
-
- /* ??? Granted, this is slower than the `ppc' way. Maybe when this is
- done it'll be clear what the right way to do this is. */
- /* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets
- printed first, but we don't know how to print it until we've processed
- the regs. Since we're scanning all the args before printing the insn
- anyways, it's actually quite easy. */
-
- for (syn = opcode->syntax; *syn; ++syn)
- {
- int c;
+ /* Hex. We can change the format to 0x%08x in
+ one place, here, if we wish.
+ We add underscores for easy reading. */
+ if (u > 65536)
+ sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
+ else
+ sprintf (bp, "0x%x", u);
+ inc_bp ();
+ }
+ break;
+ case 'X': case 'x':
+ {
+ int val = va_arg (ap, int);
- if (*syn != '%' || *++syn == '%')
- continue;
- mods = 0;
- c = *syn;
- while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags))
+ if (size != 0)
+ if (leading_zero)
+ sprintf (bp, "%0*x", size, val);
+ else
+ sprintf (bp, "%*x", size, val);
+ else
+ sprintf (bp, "%x", val);
+ inc_bp ();
+ }
+ break;
+ case 'd':
{
- mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS;
- ++syn;
- c = *syn;
+ int val = va_arg (ap, int);
+
+ if (size != 0)
+ sprintf (bp, "%*d", size, val);
+ else
+ sprintf (bp, "%d", val);
+ inc_bp ();
}
- operand = arc_operands + arc_operand_map[c];
- if (operand->extract)
- (*operand->extract) (insn, operand, mods,
- (const struct arc_operand_value **) NULL,
- &invalid);
- }
- if (invalid)
- continue;
+ break;
+ case 'r':
+ {
+ /* Register. */
+ int val = va_arg (ap, int);
+
+#define REG2NAME(num, name) case num: sprintf (bp, ""name); \
+ regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
+
+ switch (val)
+ {
+ REG2NAME (26, "gp");
+ REG2NAME (27, "fp");
+ REG2NAME (28, "sp");
+ REG2NAME (29, "ilink1");
+ REG2NAME (30, "ilink2");
+ REG2NAME (31, "blink");
+ REG2NAME (60, "lp_count");
+ default:
+ {
+ const char * ext;
+
+ ext = core_reg_name (state, val);
+ if (ext)
+ sprintf (bp, "%s", ext);
+ else
+ sprintf (bp,"r%d",val);
+ }
+ break;
+ }
+ inc_bp ();
+ } break;
+
+ case 'a':
+ {
+ /* Aux Register. */
+ int val = va_arg (ap, int);
- /* The instruction is valid. */
+#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
- /* If we have an insn with a limm, fetch it now. Scanning the insns
- twice lets us do this. */
- if (arc_opcode_limm_p (NULL))
- {
- status = (*info->read_memory_func) (pc + 4, buffer, 4, info);
- if (status != 0)
+ switch (val)
+ {
+ AUXREG2NAME (0x0, "status");
+ AUXREG2NAME (0x1, "semaphore");
+ AUXREG2NAME (0x2, "lp_start");
+ AUXREG2NAME (0x3, "lp_end");
+ AUXREG2NAME (0x4, "identity");
+ AUXREG2NAME (0x5, "debug");
+ default:
+ {
+ const char *ext;
+
+ ext = aux_reg_name (state, val);
+ if (ext)
+ sprintf (bp, "%s", ext);
+ else
+ my_sprintf (state, bp, "%h", val);
+ }
+ break;
+ }
+ inc_bp ();
+ }
+ break;
+
+ case 's':
{
- (*info->memory_error_func) (status, pc, info);
- return -1;
+ sprintf (bp, "%s", va_arg (ap, char *));
+ inc_bp ();
}
- if (big_p)
- insn[1] = bfd_getb32 (buffer);
+ break;
+
+ default:
+ fprintf (stderr, "?? format %c\n", p[-1]);
+ break;
+ }
+ }
+
+ DOCOMM: *bp = 0;
+}
+
+static void
+write_comments_(state, shimm, is_limm, limm_value)
+ struct arcDisState * state;
+ int shimm;
+ int is_limm;
+ long limm_value;
+{
+ if (state->commentBuffer != 0)
+ {
+ int i;
+
+ if (is_limm)
+ {
+ const char *name = post_address (state, limm_value + shimm);
+
+ if (*name != 0)
+ WRITE_COMMENT (name);
+ }
+ for (i = 0; i < state->commNum; i++)
+ {
+ if (i == 0)
+ strcpy (state->commentBuffer, comment_prefix);
else
- insn[1] = bfd_getl32 (buffer);
- got_limm_p = 1;
+ strcat (state->commentBuffer, ", ");
+ strncat (state->commentBuffer, state->comm[i], sizeof (state->commentBuffer));
}
+ }
+}
- for (syn = opcode->syntax; *syn; ++syn)
- {
- int c;
+#define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
+#define write_comments() write_comments2(0)
+
+static const char *condName[] = {
+ /* 0..15. */
+ "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
+ "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
+};
+
+static void
+write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
+ struct arcDisState * state;
+ const char * instrName;
+ int cond;
+ int condCodeIsPartOfName;
+ int flag;
+ int signExtend;
+ int addrWriteBack;
+ int directMem;
+{
+ strcpy (state->instrBuffer, instrName);
+
+ if (cond > 0)
+ {
+ const char *cc = 0;
+
+ if (!condCodeIsPartOfName)
+ strcat (state->instrBuffer, ".");
+
+ if (cond < 16)
+ cc = condName[cond];
+ else
+ cc = cond_code_name (state, cond);
+
+ if (!cc)
+ cc = "???";
+
+ strcat (state->instrBuffer, cc);
+ }
+
+ if (flag)
+ strcat (state->instrBuffer, ".f");
+
+ switch (state->nullifyMode)
+ {
+ case BR_exec_always:
+ strcat (state->instrBuffer, ".d");
+ break;
+ case BR_exec_when_jump:
+ strcat (state->instrBuffer, ".jd");
+ break;
+ }
+
+ if (signExtend)
+ strcat (state->instrBuffer, ".x");
+
+ if (addrWriteBack)
+ strcat (state->instrBuffer, ".a");
+
+ if (directMem)
+ strcat (state->instrBuffer, ".di");
+}
+
+#define write_instr_name() \
+ do \
+ { \
+ write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
+ flag, signExtend, addrWriteBack, directMem); \
+ formatString[0] = '\0'; \
+ } \
+ while (0)
+
+enum {
+ op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
+ op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
+ op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
+ op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15
+};
+
+extern disassemble_info tm_print_insn_info;
- if (*syn != '%' || *++syn == '%')
+static int
+dsmOneArcInst (addr, state)
+ bfd_vma addr;
+ struct arcDisState * state;
+{
+ int condCodeIsPartOfName = 0;
+ int decodingClass;
+ const char * instrName;
+ int repeatsOp = 0;
+ int fieldAisReg = 1;
+ int fieldBisReg = 1;
+ int fieldCisReg = 1;
+ int fieldA;
+ int fieldB;
+ int fieldC = 0;
+ int flag = 0;
+ int cond = 0;
+ int is_shimm = 0;
+ int is_limm = 0;
+ long limm_value = 0;
+ int signExtend = 0;
+ int addrWriteBack = 0;
+ int directMem = 0;
+ int is_linked = 0;
+ int offset = 0;
+ int usesAuxReg = 0;
+ int flags;
+ int ignoreFirstOpd;
+ char formatString[60];
+
+ state->instructionLen = 4;
+ state->nullifyMode = BR_exec_when_no_jump;
+ state->opWidth = 12;
+ state->isBranch = 0;
+
+ state->_mem_load = 0;
+ state->_ea_present = 0;
+ state->_load_len = 0;
+ state->ea_reg1 = no_reg;
+ state->ea_reg2 = no_reg;
+ state->_offset = 0;
+
+ if (! NEXT_WORD (0))
+ return 0;
+
+ state->_opcode = OPCODE (state->words[0]);
+ instrName = 0;
+ decodingClass = 0; /* default! */
+ repeatsOp = 0;
+ condCodeIsPartOfName=0;
+ state->commNum = 0;
+ state->tcnt = 0;
+ state->acnt = 0;
+ state->flow = noflow;
+ ignoreFirstOpd = 0;
+
+ if (state->commentBuffer)
+ state->commentBuffer[0] = '\0';
+
+ switch (state->_opcode)
+ {
+ case op_LD0:
+ switch (BITS (state->words[0],1,2))
+ {
+ case 0:
+ instrName = "ld";
+ state->_load_len = 4;
+ break;
+ case 1:
+ instrName = "ldb";
+ state->_load_len = 1;
+ break;
+ case 2:
+ instrName = "ldw";
+ state->_load_len = 2;
+ break;
+ default:
+ instrName = "??? (0[3])";
+ state->flow = invalid_instr;
+ break;
+ }
+ decodingClass = 5;
+ break;
+
+ case op_LD1:
+ if (BIT (state->words[0],13))
+ {
+ instrName = "lr";
+ decodingClass = 10;
+ }
+ else
+ {
+ switch (BITS (state->words[0],10,11))
{
- (*func) (stream, "%c", *syn);
- continue;
+ case 0:
+ instrName = "ld";
+ state->_load_len = 4;
+ break;
+ case 1:
+ instrName = "ldb";
+ state->_load_len = 1;
+ break;
+ case 2:
+ instrName = "ldw";
+ state->_load_len = 2;
+ break;
+ default:
+ instrName = "??? (1[3])";
+ state->flow = invalid_instr;
+ break;
}
-
- /* We have an operand. Fetch any special modifiers. */
- mods = 0;
- c = *syn;
- while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags))
+ decodingClass = 6;
+ }
+ break;
+
+ case op_ST:
+ if (BIT (state->words[0],25))
+ {
+ instrName = "sr";
+ decodingClass = 8;
+ }
+ else
+ {
+ switch (BITS (state->words[0],22,23))
+ {
+ case 0:
+ instrName = "st";
+ break;
+ case 1:
+ instrName = "stb";
+ break;
+ case 2:
+ instrName = "stw";
+ break;
+ default:
+ instrName = "??? (2[3])";
+ state->flow = invalid_instr;
+ break;
+ }
+ decodingClass = 7;
+ }
+ break;
+
+ case op_3:
+ decodingClass = 1; /* default for opcode 3... */
+ switch (FIELDC (state->words[0]))
+ {
+ case 0:
+ instrName = "flag";
+ decodingClass = 2;
+ break;
+ case 1:
+ instrName = "asr";
+ break;
+ case 2:
+ instrName = "lsr";
+ break;
+ case 3:
+ instrName = "ror";
+ break;
+ case 4:
+ instrName = "rrc";
+ break;
+ case 5:
+ instrName = "sexb";
+ break;
+ case 6:
+ instrName = "sexw";
+ break;
+ case 7:
+ instrName = "extb";
+ break;
+ case 8:
+ instrName = "extw";
+ break;
+ case 0x3f:
+ {
+ decodingClass = 9;
+ switch( FIELDD (state->words[0]) )
+ {
+ case 0:
+ instrName = "brk";
+ break;
+ case 1:
+ instrName = "sleep";
+ break;
+ case 2:
+ instrName = "swi";
+ break;
+ default:
+ instrName = "???";
+ state->flow=invalid_instr;
+ break;
+ }
+ }
+ break;
+
+ /* ARC Extension Library Instructions
+ NOTE: We assume that extension codes are these instrs. */
+ default:
+ instrName = instruction_name (state,
+ state->_opcode,
+ FIELDC (state->words[0]),
+ & flags);
+ if (!instrName)
{
- mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS;
- ++syn;
- c = *syn;
+ instrName = "???";
+ state->flow = invalid_instr;
}
- operand = arc_operands + arc_operand_map[c];
+ if (flags & IGNORE_FIRST_OPD)
+ ignoreFirstOpd = 1;
+ break;
+ }
+ break;
- /* Extract the value from the instruction. */
- opval = NULL;
- if (operand->extract)
+ case op_BC:
+ instrName = "b";
+ case op_BLC:
+ if (!instrName)
+ instrName = "bl";
+ case op_LPC:
+ if (!instrName)
+ instrName = "lp";
+ case op_JC:
+ if (!instrName)
+ {
+ if (BITS (state->words[0],9,9))
{
- value = (*operand->extract) (insn, operand, mods,
- &opval, (int *) NULL);
+ instrName = "jl";
+ is_linked = 1;
}
- else
+ else
{
- value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (value & (1 << (operand->bits - 1))))
- value -= 1 << operand->bits;
-
- /* If this is a suffix operand, set `opval'. */
- if (operand->flags & ARC_OPERAND_SUFFIX)
- opval = arc_opcode_lookup_suffix (operand, value);
+ instrName = "j";
+ is_linked = 0;
}
+ }
+ condCodeIsPartOfName = 1;
+ decodingClass = ((state->_opcode == op_JC) ? 4 : 3);
+ state->isBranch = 1;
+ break;
+
+ case op_ADD:
+ case op_ADC:
+ case op_AND:
+ repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
+ decodingClass = 0;
- /* Print the operand as directed by the flags. */
- if (operand->flags & ARC_OPERAND_FAKE)
- ; /* nothing to do (??? at least not yet) */
- else if (operand->flags & ARC_OPERAND_SUFFIX)
- {
- /* Default suffixes aren't printed. Fortunately, they all have
- zero values. Also, zero values for boolean suffixes are
- represented by the absence of text. */
+ switch (state->_opcode)
+ {
+ case op_ADD:
+ instrName = (repeatsOp ? "asl" : "add");
+ break;
+ case op_ADC:
+ instrName = (repeatsOp ? "rlc" : "adc");
+ break;
+ case op_AND:
+ instrName = (repeatsOp ? "mov" : "and");
+ break;
+ }
+ break;
+
+ case op_SUB: instrName = "sub";
+ break;
+ case op_SBC: instrName = "sbc";
+ break;
+ case op_OR: instrName = "or";
+ break;
+ case op_BIC: instrName = "bic";
+ break;
- if (value != 0)
- {
- /* ??? OPVAL should have a value. If it doesn't just cope
- as we want disassembly to be reasonably robust.
- Also remember that several condition code values (16-31)
- aren't defined yet. For these cases just print the
- number suitably decorated. */
- if (opval)
- (*func) (stream, "%s%s",
- mods & ARC_MOD_DOT ? "." : "",
- opval->name);
- else
- (*func) (stream, "%s%c%d",
- mods & ARC_MOD_DOT ? "." : "",
- operand->fmt, value);
- }
+ case op_XOR:
+ if (state->words[0] == 0x7fffffff)
+ {
+ /* nop encoded as xor -1, -1, -1 */
+ instrName = "nop";
+ decodingClass = 9;
+ }
+ else
+ instrName = "xor";
+ break;
+
+ default:
+ instrName = instruction_name (state,state->_opcode,0,&flags);
+ /* if (instrName) printf("FLAGS=0x%x\n", flags); */
+ if (!instrName)
+ {
+ instrName = "???";
+ state->flow=invalid_instr;
+ }
+ if (flags & IGNORE_FIRST_OPD)
+ ignoreFirstOpd = 1;
+ break;
+ }
+
+ fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
+ flag = cond = is_shimm = is_limm = 0;
+ state->nullifyMode = BR_exec_when_no_jump; /* 0 */
+ signExtend = addrWriteBack = directMem = 0;
+ usesAuxReg = 0;
+
+ switch (decodingClass)
+ {
+ case 0:
+ CHECK_FIELD_A ();
+ CHECK_FIELD_B ();
+ if (!repeatsOp)
+ CHECK_FIELD_C ();
+ CHECK_FLAG_COND_NULLIFY ();
+
+ write_instr_name ();
+ if (!ignoreFirstOpd)
+ {
+ WRITE_FORMAT_x (A);
+ WRITE_FORMAT_COMMA_x (B);
+ if (!repeatsOp)
+ WRITE_FORMAT_COMMA_x (C);
+ WRITE_NOP_COMMENT ();
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+ }
+ else
+ {
+ WRITE_FORMAT_x (B);
+ if (!repeatsOp)
+ WRITE_FORMAT_COMMA_x (C);
+ my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC);
+ }
+ write_comments ();
+ break;
+
+ case 1:
+ CHECK_FIELD_A ();
+ CHECK_FIELD_B ();
+ CHECK_FLAG_COND_NULLIFY ();
+
+ write_instr_name ();
+ if (!ignoreFirstOpd)
+ {
+ WRITE_FORMAT_x (A);
+ WRITE_FORMAT_COMMA_x (B);
+ WRITE_NOP_COMMENT ();
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
+ }
+ else
+ {
+ WRITE_FORMAT_x (B);
+ my_sprintf (state, state->operandBuffer, formatString, fieldB);
+ }
+ write_comments ();
+ break;
+
+ case 2:
+ CHECK_FIELD_B ();
+ CHECK_FLAG_COND_NULLIFY ();
+ flag = 0; /* this is the FLAG instruction -- it's redundant */
+
+ write_instr_name ();
+ WRITE_FORMAT_x (B);
+ my_sprintf (state, state->operandBuffer, formatString, fieldB);
+ write_comments ();
+ break;
+
+ case 3:
+ fieldA = BITS (state->words[0],7,26) << 2;
+ fieldA = (fieldA << 10) >> 10; /* make it signed */
+ fieldA += addr + 4;
+ CHECK_FLAG_COND_NULLIFY ();
+ flag = 0;
+
+ write_instr_name ();
+ /* This address could be a label we know. Convert it. */
+ if (state->_opcode != op_LPC /* LP */)
+ {
+ add_target (fieldA); /* For debugger. */
+ state->flow = state->_opcode == op_BLC /* BL */
+ ? direct_call
+ : direct_jump;
+ /* indirect calls are achieved by "lr blink,[status];
+ lr dest<- func addr; j [dest]" */
+ }
+
+ strcat (formatString, "%s"); /* address/label name */
+ my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA));
+ write_comments ();
+ break;
+
+ case 4:
+ /* For op_JC -- jump to address specified.
+ Also covers jump and link--bit 9 of the instr. word
+ selects whether linked, thus "is_linked" is set above. */
+ fieldA = 0;
+ CHECK_FIELD_B ();
+ CHECK_FLAG_COND_NULLIFY ();
+
+ if (!fieldBisReg)
+ {
+ fieldAisReg = 0;
+ fieldA = (fieldB >> 25) & 0x7F; /* flags */
+ fieldB = (fieldB & 0xFFFFFF) << 2;
+ state->flow = is_linked ? direct_call : direct_jump;
+ add_target (fieldB);
+ /* screwy JLcc requires .jd mode to execute correctly
+ * but we pretend it is .nd (no delay slot). */
+ if (is_linked && state->nullifyMode == BR_exec_when_jump)
+ state->nullifyMode = BR_exec_when_no_jump;
+ }
+ else
+ {
+ state->flow = is_linked ? indirect_call : indirect_jump;
+ /* We should also treat this as indirect call if NOT linked
+ * but the preceding instruction was a "lr blink,[status]"
+ * and we have a delay slot with "add blink,blink,2".
+ * For now we can't detect such. */
+ state->register_for_indirect_jump = fieldB;
+ }
+
+ write_instr_name ();
+ strcat (formatString,
+ IS_REG (B) ? "[%r]" : "%s"); /* address/label name */
+ if (fieldA != 0)
+ {
+ fieldAisReg = 0;
+ WRITE_FORMAT_COMMA_x (A);
+ }
+ if (IS_REG (B))
+ my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
+ else
+ my_sprintf (state, state->operandBuffer, formatString,
+ post_address (state, fieldB), fieldA);
+ write_comments ();
+ break;
+
+ case 5:
+ /* LD instruction.
+ B and C can be regs, or one (both?) can be limm. */
+ CHECK_FIELD_A ();
+ CHECK_FIELD_B ();
+ CHECK_FIELD_C ();
+ if (dbg)
+ printf ("5:b reg %d %d c reg %d %d \n",
+ fieldBisReg,fieldB,fieldCisReg,fieldC);
+ state->_offset = 0;
+ state->_ea_present = 1;
+ if (fieldBisReg)
+ state->ea_reg1 = fieldB;
+ else
+ state->_offset += fieldB;
+ if (fieldCisReg)
+ state->ea_reg2 = fieldC;
+ else
+ state->_offset += fieldC;
+ state->_mem_load = 1;
+
+ directMem = BIT (state->words[0],5);
+ addrWriteBack = BIT (state->words[0],3);
+ signExtend = BIT (state->words[0],0);
+
+ write_instr_name ();
+ WRITE_FORMAT_x_COMMA_LB(A);
+ if (fieldBisReg || fieldB != 0)
+ WRITE_FORMAT_x_COMMA (B);
+ else
+ fieldB = fieldC;
+
+ WRITE_FORMAT_x_RB (C);
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+ write_comments ();
+ break;
+
+ case 6:
+ /* LD instruction. */
+ CHECK_FIELD_B ();
+ CHECK_FIELD_A ();
+ fieldC = FIELDD (state->words[0]);
+
+ if (dbg)
+ printf ("6:b reg %d %d c 0x%x \n",
+ fieldBisReg, fieldB, fieldC);
+ state->_ea_present = 1;
+ state->_offset = fieldC;
+ state->_mem_load = 1;
+ if (fieldBisReg)
+ state->ea_reg1 = fieldB;
+ /* field B is either a shimm (same as fieldC) or limm (different!)
+ Say ea is not present, so only one of us will do the name lookup. */
+ else
+ state->_offset += fieldB, state->_ea_present = 0;
+
+ directMem = BIT (state->words[0],14);
+ addrWriteBack = BIT (state->words[0],12);
+ signExtend = BIT (state->words[0],9);
+
+ write_instr_name ();
+ WRITE_FORMAT_x_COMMA_LB (A);
+ if (!fieldBisReg)
+ {
+ fieldB = state->_offset;
+ WRITE_FORMAT_x_RB (B);
+ }
+ else
+ {
+ WRITE_FORMAT_x (B);
+ if (fieldC != 0 && !BIT (state->words[0],13))
+ {
+ fieldCisReg = 0;
+ WRITE_FORMAT_COMMA_x_RB (C);
}
- else if (operand->flags & ARC_OPERAND_RELATIVE_BRANCH)
- (*info->print_address_func) (pc + 4 + value, info);
- /* ??? Not all cases of this are currently caught. */
- else if (operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH)
- (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
- else if (operand->flags & ARC_OPERAND_ADDRESS)
- (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
- else if (opval)
- /* Note that this case catches both normal and auxiliary regs. */
- (*func) (stream, "%s", opval->name);
else
- (*func) (stream, "%ld", value);
+ WRITE_FORMAT_RB ();
}
-
- /* We have found and printed an instruction; return. */
- return got_limm_p ? 8 : 4;
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+ write_comments ();
+ break;
+
+ case 7:
+ /* ST instruction. */
+ CHECK_FIELD_B();
+ CHECK_FIELD_C();
+ fieldA = FIELDD(state->words[0]); /* shimm */
+
+ /* [B,A offset] */
+ if (dbg) printf("7:b reg %d %x off %x\n",
+ fieldBisReg,fieldB,fieldA);
+ state->_ea_present = 1;
+ state->_offset = fieldA;
+ if (fieldBisReg)
+ state->ea_reg1 = fieldB;
+ /* field B is either a shimm (same as fieldA) or limm (different!)
+ Say ea is not present, so only one of us will do the name lookup.
+ (for is_limm we do the name translation here). */
+ else
+ state->_offset += fieldB, state->_ea_present = 0;
+
+ directMem = BIT(state->words[0],26);
+ addrWriteBack = BIT(state->words[0],24);
+
+ write_instr_name();
+ WRITE_FORMAT_x_COMMA_LB(C);
+
+ if (!fieldBisReg)
+ {
+ fieldB = state->_offset;
+ WRITE_FORMAT_x_RB(B);
+ }
+ else
+ {
+ WRITE_FORMAT_x(B);
+ if (fieldBisReg && fieldA != 0)
+ {
+ fieldAisReg = 0;
+ WRITE_FORMAT_COMMA_x_RB(A);
+ }
+ else
+ WRITE_FORMAT_RB();
+ }
+ my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
+ write_comments2(fieldA);
+ break;
+ case 8:
+ /* SR instruction */
+ CHECK_FIELD_B();
+ CHECK_FIELD_C();
+
+ write_instr_name();
+ WRITE_FORMAT_x_COMMA_LB(C);
+ /* Try to print B as an aux reg if it is not a core reg. */
+ usesAuxReg = 1;
+ WRITE_FORMAT_x(B);
+ WRITE_FORMAT_RB();
+ my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
+ write_comments();
+ break;
+
+ case 9:
+ write_instr_name();
+ state->operandBuffer[0] = '\0';
+ break;
+
+ case 10:
+ /* LR instruction */
+ CHECK_FIELD_A();
+ CHECK_FIELD_B();
+
+ write_instr_name();
+ WRITE_FORMAT_x_COMMA_LB(A);
+ /* Try to print B as an aux reg if it is not a core reg. */
+ usesAuxReg = 1;
+ WRITE_FORMAT_x(B);
+ WRITE_FORMAT_RB();
+ my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
+ write_comments();
+ break;
+
+ case 11:
+ CHECK_COND();
+ write_instr_name();
+ state->operandBuffer[0] = '\0';
+ break;
+
+ default:
+ mwerror (state, "Bad decoding class in ARC disassembler");
+ break;
}
+
+ state->_cond = cond;
+ return state->instructionLen = offset;
+}
+
- (*func) (stream, _("*unknown*"));
- return 4;
+/* Returns the name the user specified core extension register. */
+static const char *
+_coreRegName(arg, regval)
+ void * arg ATTRIBUTE_UNUSED;
+ int regval;
+{
+ return arcExtMap_coreRegName (regval);
}
-/* Given MACH, one of bfd_mach_arc_xxx, return the print_insn function to use.
- This does things a non-standard way (the "standard" way would be to copy
- this code into disassemble.c). Since there are more than a couple of
- variants, hiding all this crud here seems cleaner. */
+/* Returns the name the user specified AUX extension register. */
+static const char *
+_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
+{
+ return arcExtMap_auxRegName(regval);
+}
-disassembler_ftype
-arc_get_disassembler (mach, big_p)
- int mach;
- int big_p;
+
+/* Returns the name the user specified condition code name. */
+static const char *
+_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
{
- switch (mach)
- {
- case bfd_mach_arc_base:
- return big_p ? print_insn_arc_base_big : print_insn_arc_base_little;
- }
- return print_insn_arc_base_little;
+ return arcExtMap_condCodeName(regval);
}
-static int
-print_insn_arc_base_little (pc, info)
- bfd_vma pc;
- disassemble_info *info;
+/* Returns the name the user specified extension instruction. */
+static const char *
+_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
{
- return print_insn (pc, info, bfd_mach_arc_base, 0);
+ return arcExtMap_instName(majop, minop, flags);
}
+/* Decode an instruction returning the size of the instruction
+ in bytes or zero if unrecognized. */
static int
-print_insn_arc_base_big (pc, info)
- bfd_vma pc;
- disassemble_info *info;
+decodeInstr (address, info)
+ bfd_vma address; /* Address of this instruction. */
+ disassemble_info * info;
+{
+ int status;
+ bfd_byte buffer[4];
+ struct arcDisState s; /* ARC Disassembler state */
+ void *stream = info->stream; /* output stream */
+ fprintf_ftype func = info->fprintf_func;
+ int bytes;
+
+ memset (&s, 0, sizeof(struct arcDisState));
+
+ /* read first instruction */
+ status = (*info->read_memory_func) (address, buffer, 4, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, address, info);
+ return 0;
+ }
+ if (info->endian == BFD_ENDIAN_LITTLE)
+ s.words[0] = bfd_getl32(buffer);
+ else
+ s.words[0] = bfd_getb32(buffer);
+ /* always read second word in case of limm */
+
+ /* we ignore the result since last insn may not have a limm */
+ status = (*info->read_memory_func) (address + 4, buffer, 4, info);
+ if (info->endian == BFD_ENDIAN_LITTLE)
+ s.words[1] = bfd_getl32(buffer);
+ else
+ s.words[1] = bfd_getb32(buffer);
+
+ s._this = &s;
+ s.coreRegName = _coreRegName;
+ s.auxRegName = _auxRegName;
+ s.condCodeName = _condCodeName;
+ s.instName = _instName;
+
+ /* disassemble */
+ bytes = dsmOneArcInst(address, (void *)&s);
+
+ /* display the disassembly instruction */
+ (*func) (stream, "%08x ", s.words[0]);
+ (*func) (stream, " ");
+
+ (*func) (stream, "%-10s ", s.instrBuffer);
+
+ if (__TRANSLATION_REQUIRED(s))
+ {
+ bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
+ (*info->print_address_func) ((bfd_vma) addr, info);
+ (*func) (stream, "\n");
+ }
+ else
+ (*func) (stream, "%s",s.operandBuffer);
+ return s.instructionLen;
+}
+
+/* Return the print_insn function to use.
+ Side effect: load (possibly empty) extension section */
+
+disassembler_ftype
+arc_get_disassembler (void *ptr)
{
- return print_insn (pc, info, bfd_mach_arc_base, 1);
+ if (ptr)
+ build_ARC_extmap (ptr);
+ return decodeInstr;
}
diff --git a/contrib/binutils/opcodes/arc-dis.h b/contrib/binutils/opcodes/arc-dis.h
new file mode 100644
index 0000000..04bfbbb
--- /dev/null
+++ b/contrib/binutils/opcodes/arc-dis.h
@@ -0,0 +1,81 @@
+/* Disassembler structures definitions for the ARC.
+ Copyright 1994, 1995, 1997, 1998, 2000, 2001
+ Free Software Foundation, Inc.
+ Contributed by Doug Evans (dje@cygnus.com).
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef ARCDIS_H
+#define ARCDIS_H
+
+enum
+{
+ BR_exec_when_no_jump,
+ BR_exec_always,
+ BR_exec_when_jump
+};
+
+enum Flow
+{
+ noflow,
+ direct_jump,
+ direct_call,
+ indirect_jump,
+ indirect_call,
+ invalid_instr
+};
+
+enum { no_reg = 99 };
+enum { allOperandsSize = 256 };
+
+struct arcDisState
+{
+ void *_this;
+ int instructionLen;
+ void (*err)(void*, const char*);
+ const char *(*coreRegName)(void*, int);
+ const char *(*auxRegName)(void*, int);
+ const char *(*condCodeName)(void*, int);
+ const char *(*instName)(void*, int, int, int*);
+
+ unsigned char* instruction;
+ unsigned index;
+ const char *comm[6]; /* instr name, cond, NOP, 3 operands */
+ int opWidth;
+ int targets[4];
+ int addresses[4];
+ /* Set as a side-effect of calling the disassembler.
+ Used only by the debugger. */
+ enum Flow flow;
+ int register_for_indirect_jump;
+ int ea_reg1, ea_reg2, _offset;
+ int _cond, _opcode;
+ unsigned long words[2];
+ char *commentBuffer;
+ char instrBuffer[40];
+ char operandBuffer[allOperandsSize];
+ char _ea_present;
+ char _mem_load;
+ char _load_len;
+ char nullifyMode;
+ unsigned char commNum;
+ unsigned char isBranch;
+ unsigned char tcnt;
+ unsigned char acnt;
+};
+
+#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0)
+
+#endif
diff --git a/contrib/binutils/opcodes/arc-ext.c b/contrib/binutils/opcodes/arc-ext.c
new file mode 100644
index 0000000..1a53da9
--- /dev/null
+++ b/contrib/binutils/opcodes/arc-ext.c
@@ -0,0 +1,259 @@
+/* ARC target-dependent stuff. Extension structure access functions
+ Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc.
+
+ This file is part of GDB.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "bfd.h"
+#include "arc-ext.h"
+#include "libiberty.h"
+
+/* Extension structure */
+static struct arcExtMap arc_extension_map;
+
+/* Get the name of an extension instruction. */
+
+const char *
+arcExtMap_instName(int opcode, int minor, int *flags)
+{
+ if (opcode == 3)
+ {
+ /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */
+ if (minor < 0x09 || minor == 0x3f)
+ return 0;
+ else
+ opcode = 0x1f - 0x10 + minor - 0x09 + 1;
+ }
+ else
+ if (opcode < 0x10)
+ return 0;
+ else
+ opcode -= 0x10;
+ if (!arc_extension_map.instructions[opcode])
+ return 0;
+ *flags = arc_extension_map.instructions[opcode]->flags;
+ return arc_extension_map.instructions[opcode]->name;
+}
+
+/* Get the name of an extension core register. */
+
+const char *
+arcExtMap_coreRegName(int value)
+{
+ if (value < 32)
+ return 0;
+ return (const char *) arc_extension_map.coreRegisters[value-32];
+}
+
+/* Get the name of an extension condition code. */
+
+const char *
+arcExtMap_condCodeName(int value)
+{
+ if (value < 16)
+ return 0;
+ return (const char *) arc_extension_map.condCodes[value-16];
+}
+
+/* Get the name of an extension aux register. */
+
+const char *
+arcExtMap_auxRegName(long address)
+{
+ /* walk the list of aux reg names and find the name */
+ struct ExtAuxRegister *r;
+
+ for (r = arc_extension_map.auxRegisters; r; r = r->next) {
+ if (r->address == address)
+ return (const char *) r->name;
+ }
+ return 0;
+}
+
+/* Recursively free auxilliary register strcture pointers until
+ the list is empty. */
+
+static void
+clean_aux_registers(struct ExtAuxRegister *r)
+{
+ if (r -> next)
+ {
+ clean_aux_registers( r->next);
+ free(r -> name);
+ free(r -> next);
+ r ->next = NULL;
+ }
+ else
+ free(r -> name);
+}
+
+/* Free memory that has been allocated for the extensions. */
+
+static void
+cleanup_ext_map(void)
+{
+ struct ExtAuxRegister *r;
+ struct ExtInstruction *insn;
+ int i;
+
+ /* clean aux reg structure */
+ r = arc_extension_map.auxRegisters;
+ if (r)
+ {
+ (clean_aux_registers(r));
+ free(r);
+ }
+
+ /* clean instructions */
+ for (i = 0; i < NUM_EXT_INST; i++)
+ {
+ insn = arc_extension_map.instructions[i];
+ if (insn)
+ free(insn->name);
+ }
+
+ /* clean core reg struct */
+ for (i = 0; i < NUM_EXT_CORE; i++)
+ {
+ if (arc_extension_map.coreRegisters[i])
+ free(arc_extension_map.coreRegisters[i]);
+ }
+
+ for (i = 0; i < NUM_EXT_COND; i++) {
+ if (arc_extension_map.condCodes[i])
+ free(arc_extension_map.condCodes[i]);
+ }
+
+ memset(&arc_extension_map, 0, sizeof(struct arcExtMap));
+}
+
+int
+arcExtMap_add(void *base, unsigned long length)
+{
+ unsigned char *block = base;
+ unsigned char *p = block;
+
+ /* Clean up and reset everything if needed. */
+ cleanup_ext_map();
+
+ while (p && p < (block + length))
+ {
+ /* p[0] == length of record
+ p[1] == type of record
+ For instructions:
+ p[2] = opcode
+ p[3] = minor opcode (if opcode == 3)
+ p[4] = flags
+ p[5]+ = name
+ For core regs and condition codes:
+ p[2] = value
+ p[3]+ = name
+ For aux regs:
+ p[2..5] = value
+ p[6]+ = name
+ (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */
+
+ if (p[0] == 0)
+ return -1;
+
+ switch (p[1])
+ {
+ case EXT_INSTRUCTION:
+ {
+ char opcode = p[2];
+ char minor = p[3];
+ char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char));
+ struct ExtInstruction * insn =
+ (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction));
+
+ if (opcode==3)
+ opcode = 0x1f - 0x10 + minor - 0x09 + 1;
+ else
+ opcode -= 0x10;
+ insn -> flags = (char) *(p+4);
+ strcpy(insn_name, (p+5));
+ insn -> name = insn_name;
+ arc_extension_map.instructions[(int) opcode] = insn;
+ }
+ break;
+
+ case EXT_CORE_REGISTER:
+ {
+ char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char));
+
+ strcpy(core_name, (p+3));
+ arc_extension_map.coreRegisters[p[2]-32] = core_name;
+ }
+ break;
+
+ case EXT_COND_CODE:
+ {
+ char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char));
+ strcpy(cc_name, (p+3));
+ arc_extension_map.condCodes[p[2]-16] = cc_name;
+ }
+ break;
+
+ case EXT_AUX_REGISTER:
+ {
+ /* trickier -- need to store linked list to these */
+ struct ExtAuxRegister *newAuxRegister =
+ (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister));
+ char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char));
+
+ strcpy (aux_name, (p+6));
+ newAuxRegister->name = aux_name;
+ newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5];
+ newAuxRegister->next = arc_extension_map.auxRegisters;
+ arc_extension_map.auxRegisters = newAuxRegister;
+ }
+ break;
+
+ default:
+ return -1;
+
+ }
+ p += p[0]; /* move to next record */
+ }
+
+ return 0;
+}
+
+/* Load hw extension descibed in .extArcMap ELF section. */
+
+void
+build_ARC_extmap (text_bfd)
+ bfd *text_bfd;
+{
+ char *arcExtMap;
+ bfd_size_type count;
+ asection *p;
+
+ for (p = text_bfd->sections; p != NULL; p = p->next)
+ if (!strcmp (p->name, ".arcextmap"))
+ {
+ count = p->_raw_size;
+ arcExtMap = (char *) xmalloc (count);
+ if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count))
+ {
+ arcExtMap_add ((PTR) arcExtMap, count);
+ break;
+ }
+ free ((PTR) arcExtMap);
+ }
+}
diff --git a/contrib/binutils/opcodes/arc-ext.h b/contrib/binutils/opcodes/arc-ext.h
new file mode 100644
index 0000000..bfe9750b
--- /dev/null
+++ b/contrib/binutils/opcodes/arc-ext.h
@@ -0,0 +1,62 @@
+/* ARC target-dependent stuff. Extension data structures.
+ Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef ARCEXT_H
+#define ARCEXT_H
+
+enum {EXT_INSTRUCTION = 0};
+enum {EXT_CORE_REGISTER = 1};
+enum {EXT_AUX_REGISTER = 2};
+enum {EXT_COND_CODE = 3};
+
+enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)};
+enum {NUM_EXT_CORE = 59-32+1};
+enum {NUM_EXT_COND = 0x1f-0x10+1};
+
+struct ExtInstruction
+{
+ char flags;
+ char *name;
+};
+
+struct ExtAuxRegister
+{
+ long address;
+ char *name;
+ struct ExtAuxRegister *next;
+};
+
+struct arcExtMap
+{
+ struct ExtAuxRegister *auxRegisters;
+ struct ExtInstruction *instructions[NUM_EXT_INST];
+ unsigned char *coreRegisters[NUM_EXT_CORE];
+ unsigned char *condCodes[NUM_EXT_COND];
+};
+
+extern int arcExtMap_add(void*, unsigned long);
+extern const char *arcExtMap_coreRegName(int);
+extern const char *arcExtMap_auxRegName(long);
+extern const char *arcExtMap_condCodeName(int);
+extern const char *arcExtMap_instName(int, int, int*);
+extern void build_ARC_extmap(bfd *);
+
+#define IGNORE_FIRST_OPD 1
+
+#endif
diff --git a/contrib/binutils/opcodes/arc-opc.c b/contrib/binutils/opcodes/arc-opc.c
index f17ffc0..c67cd88 100644
--- a/contrib/binutils/opcodes/arc-opc.c
+++ b/contrib/binutils/opcodes/arc-opc.c
@@ -1,7 +1,8 @@
/* Opcode table for the ARC.
- Copyright (c) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
+ Copyright 1994, 1995, 1997, 1998, 2000, 2001
+ Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
-
+
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
@@ -13,17 +14,12 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
-#include "sysdep.h"
+#include "ansidecl.h"
#include "opcode/arc.h"
-#include "opintl.h"
-
-#ifndef NULL
-#define NULL 0
-#endif
#define INSERT_FN(fn) \
static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
@@ -36,22 +32,43 @@ static long fn PARAMS ((arc_insn *, const struct arc_operand *, \
INSERT_FN (insert_reg);
INSERT_FN (insert_shimmfinish);
INSERT_FN (insert_limmfinish);
-INSERT_FN (insert_shimmoffset);
-INSERT_FN (insert_shimmzero);
+INSERT_FN (insert_offset);
+INSERT_FN (insert_base);
+INSERT_FN (insert_st_syntax);
+INSERT_FN (insert_ld_syntax);
+INSERT_FN (insert_addr_wb);
INSERT_FN (insert_flag);
+INSERT_FN (insert_nullify);
INSERT_FN (insert_flagfinish);
INSERT_FN (insert_cond);
INSERT_FN (insert_forcelimm);
INSERT_FN (insert_reladdr);
INSERT_FN (insert_absaddr);
+INSERT_FN (insert_jumpflags);
INSERT_FN (insert_unopmacro);
EXTRACT_FN (extract_reg);
+EXTRACT_FN (extract_ld_offset);
+EXTRACT_FN (extract_ld_syntax);
+EXTRACT_FN (extract_st_offset);
+EXTRACT_FN (extract_st_syntax);
EXTRACT_FN (extract_flag);
EXTRACT_FN (extract_cond);
EXTRACT_FN (extract_reladdr);
+EXTRACT_FN (extract_jumpflags);
EXTRACT_FN (extract_unopmacro);
+enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM};
+
+#define OPERANDS 3
+
+enum operand ls_operand[OPERANDS];
+
+#define LS_VALUE 0
+#define LS_DEST 0
+#define LS_BASE 1
+#define LS_OFFSET 2
+
/* Various types of ARC operands, including insn suffixes. */
/* Insn format values:
@@ -61,8 +78,13 @@ EXTRACT_FN (extract_unopmacro);
'c' REGC register C field
'S' SHIMMFINISH finish inserting a shimm value
'L' LIMMFINISH finish inserting a limm value
- 'd' SHIMMOFFSET shimm offset in ld,st insns
- '0' SHIMMZERO 0 shimm value in ld,st insns
+ 'o' OFFSET offset in st insns
+ 'O' OFFSET offset in ld insns
+ '0' SYNTAX_ST_NE enforce store insn syntax, no errors
+ '1' SYNTAX_LD_NE enforce load insn syntax, no errors
+ '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only
+ '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only
+ 's' BASE base in st insn
'f' FLAG F flag
'F' FLAGFINISH finish inserting the F flag
'G' FLAGINSN insert F flag in "flag" insn
@@ -71,6 +93,7 @@ EXTRACT_FN (extract_unopmacro);
'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm
'B' BRANCH branch address (22 bit pc relative)
'J' JUMP jump address (26 bit absolute)
+ 'j' JUMPFLAGS optional high order bits of 'J'
'z' SIZE1 size field in ld a,[b,c]
'Z' SIZE10 size field in ld a,[b,shimm]
'y' SIZE22 size field in st c,[b,shimm]
@@ -92,28 +115,27 @@ EXTRACT_FN (extract_unopmacro);
Fields are:
- CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN
-*/
+ CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */
const struct arc_operand arc_operands[] =
{
-/* place holder (??? not sure if needed) */
+/* place holder (??? not sure if needed). */
#define UNUSED 0
- { 0 },
+ { 0, 0, 0, 0, 0, 0 },
-/* register A or shimm/limm indicator */
+/* register A or shimm/limm indicator. */
#define REGA (UNUSED + 1)
- { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
+ { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-/* register B or shimm/limm indicator */
+/* register B or shimm/limm indicator. */
#define REGB (REGA + 1)
- { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
+ { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-/* register C or shimm/limm indicator */
+/* register C or shimm/limm indicator. */
#define REGC (REGB + 1)
- { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
+ { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
-/* fake operand used to insert shimm value into most instructions */
+/* fake operand used to insert shimm value into most instructions. */
#define SHIMMFINISH (REGC + 1)
{ 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
@@ -121,123 +143,141 @@ const struct arc_operand arc_operands[] =
#define LIMMFINISH (SHIMMFINISH + 1)
{ 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
-/* shimm operand when there is no reg indicator (ld,st) */
-#define SHIMMOFFSET (LIMMFINISH + 1)
- { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 },
+/* shimm operand when there is no reg indicator (st). */
+#define ST_OFFSET (LIMMFINISH + 1)
+ { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset },
+
+/* shimm operand when there is no reg indicator (ld). */
+#define LD_OFFSET (ST_OFFSET + 1)
+ { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset },
+
+/* operand for base. */
+#define BASE (LD_OFFSET + 1)
+ { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg},
+
+/* 0 enforce syntax for st insns. */
+#define SYNTAX_ST_NE (BASE + 1)
+ { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax },
+
+/* 1 enforce syntax for ld insns. */
+#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1)
+ { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax },
-/* 0 shimm operand for ld,st insns */
-#define SHIMMZERO (SHIMMOFFSET + 1)
- { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 },
+/* 0 enforce syntax for st insns. */
+#define SYNTAX_ST (SYNTAX_LD_NE + 1)
+ { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax },
-/* flag update bit (insertion is defered until we know how) */
-#define FLAG (SHIMMZERO + 1)
+/* 0 enforce syntax for ld insns. */
+#define SYNTAX_LD (SYNTAX_ST + 1)
+ { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax },
+
+/* flag update bit (insertion is defered until we know how). */
+#define FLAG (SYNTAX_LD + 1)
{ 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
-/* fake utility operand to finish 'f' suffix handling */
+/* fake utility operand to finish 'f' suffix handling. */
#define FLAGFINISH (FLAG + 1)
{ 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
-/* fake utility operand to set the 'f' flag for the "flag" insn */
+/* fake utility operand to set the 'f' flag for the "flag" insn. */
#define FLAGINSN (FLAGFINISH + 1)
{ 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
-/* branch delay types */
+/* branch delay types. */
#define DELAY (FLAGINSN + 1)
- { 'n', 2, 5, ARC_OPERAND_SUFFIX },
+ { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 },
-/* conditions */
+/* conditions. */
#define COND (DELAY + 1)
{ 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
-/* set `cond_p' to 1 to ensure a constant is treated as a limm */
+/* set `cond_p' to 1 to ensure a constant is treated as a limm. */
#define FORCELIMM (COND + 1)
- { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm },
+ { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 },
-/* branch address; b, bl, and lp insns */
+/* branch address; b, bl, and lp insns. */
#define BRANCH (FORCELIMM + 1)
- { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr },
+ { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr },
/* jump address; j insn (this is basically the same as 'L' except that the
- value is right shifted by 2) */
+ value is right shifted by 2). */
#define JUMP (BRANCH + 1)
- { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr },
+ { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 },
+
+/* jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */
+#define JUMPFLAGS (JUMP + 1)
+ { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags },
-/* size field, stored in bit 1,2 */
-#define SIZE1 (JUMP + 1)
- { 'z', 2, 1, ARC_OPERAND_SUFFIX },
+/* size field, stored in bit 1,2. */
+#define SIZE1 (JUMPFLAGS + 1)
+ { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 },
-/* size field, stored in bit 10,11 */
+/* size field, stored in bit 10,11. */
#define SIZE10 (SIZE1 + 1)
- { 'Z', 2, 10, ARC_OPERAND_SUFFIX, },
+ { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 },
-/* size field, stored in bit 22,23 */
+/* size field, stored in bit 22,23. */
#define SIZE22 (SIZE10 + 1)
- { 'y', 2, 22, ARC_OPERAND_SUFFIX, },
+ { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 },
-/* sign extend field, stored in bit 0 */
+/* sign extend field, stored in bit 0. */
#define SIGN0 (SIZE22 + 1)
- { 'x', 1, 0, ARC_OPERAND_SUFFIX },
+ { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 },
-/* sign extend field, stored in bit 9 */
+/* sign extend field, stored in bit 9. */
#define SIGN9 (SIGN0 + 1)
- { 'X', 1, 9, ARC_OPERAND_SUFFIX },
+ { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 },
-/* address write back, stored in bit 3 */
+/* address write back, stored in bit 3. */
#define ADDRESS3 (SIGN9 + 1)
- { 'w', 1, 3, ARC_OPERAND_SUFFIX },
+ { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-/* address write back, stored in bit 12 */
+/* address write back, stored in bit 12. */
#define ADDRESS12 (ADDRESS3 + 1)
- { 'W', 1, 12, ARC_OPERAND_SUFFIX },
+ { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-/* address write back, stored in bit 24 */
+/* address write back, stored in bit 24. */
#define ADDRESS24 (ADDRESS12 + 1)
- { 'v', 1, 24, ARC_OPERAND_SUFFIX },
+ { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
-/* cache bypass, stored in bit 5 */
+/* cache bypass, stored in bit 5. */
#define CACHEBYPASS5 (ADDRESS24 + 1)
- { 'e', 1, 5, ARC_OPERAND_SUFFIX },
+ { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 },
-/* cache bypass, stored in bit 14 */
+/* cache bypass, stored in bit 14. */
#define CACHEBYPASS14 (CACHEBYPASS5 + 1)
- { 'E', 1, 14, ARC_OPERAND_SUFFIX },
+ { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 },
-/* cache bypass, stored in bit 26 */
+/* cache bypass, stored in bit 26. */
#define CACHEBYPASS26 (CACHEBYPASS14 + 1)
- { 'D', 1, 26, ARC_OPERAND_SUFFIX },
+ { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 },
-/* unop macro, used to copy REGB to REGC */
+/* unop macro, used to copy REGB to REGC. */
#define UNOPMACRO (CACHEBYPASS26 + 1)
{ 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
/* '.' modifier ('.' required). */
#define MODDOT (UNOPMACRO + 1)
- { '.', 1, 0, ARC_MOD_DOT },
+ { '.', 1, 0, ARC_MOD_DOT, 0, 0 },
/* Dummy 'r' modifier for the register table.
It's called a "dummy" because there's no point in inserting an 'r' into all
the %a/%b/%c occurrences in the insn table. */
#define REG (MODDOT + 1)
- { 'r', 6, 0, ARC_MOD_REG },
+ { 'r', 6, 0, ARC_MOD_REG, 0, 0 },
/* Known auxiliary register modifier (stored in shimm field). */
#define AUXREG (REG + 1)
- { 'A', 9, 0, ARC_MOD_AUXREG },
+ { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 },
-/* end of list place holder */
- { 0 }
+/* end of list place holder. */
+ { 0, 0, 0, 0, 0, 0 }
};
/* Given a format letter, yields the index into `arc_operands'.
eg: arc_operand_map['a'] = REGA. */
unsigned char arc_operand_map[256];
-#define I(x) (((x) & 31) << 27)
-#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
-#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
-#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
-#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
-
/* ARC instructions.
Longer versions of insns must appear before shorter ones (if gas sees
@@ -246,110 +286,141 @@ unsigned char arc_operand_map[256];
Instructions that are really macros based on other insns must appear
before the real insn so they're chosen when disassembling. Eg: The `mov'
- insn is really the `and' insn.
-
- This table is best viewed on a wide screen (161 columns). I'd prefer to
- keep it this way. The rest of the file, however, should be viewable on an
- 80 column terminal. */
-
-/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has
- a more general facility for dealing with macros which could be used if
- we need to. */
-
-/* This table can't be `const' because members `next_asm' and `next_dis' are
- computed at run-time. We could split this into two, but that doesn't seem
- worth it. */
+ insn is really the `and' insn. */
-struct arc_opcode arc_opcodes[] = {
+struct arc_opcode arc_opcodes[] =
+{
+ /* Base case instruction set (core versions 5-8) */
- /* Macros appear first. */
/* "mov" is really an "and". */
- { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) },
+ { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 },
/* "asl" is really an "add". */
- { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
+ { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
/* "lsl" is really an "add". */
- { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
+ { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
/* "nop" is really an "xor". */
- { "nop", 0xffffffff, 0x7fffffff },
+ { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 },
/* "rlc" is really an "adc". */
- { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
-
- /* The rest of these needn't be sorted, but it helps to find them if they are. */
- { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) },
- { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) },
- { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) },
- { "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) },
- { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) },
- { "b%q%.n %B", I(-1), I(4), ARC_OPCODE_COND_BRANCH },
- { "bl%q%.n %B", I(-1), I(5), ARC_OPCODE_COND_BRANCH },
- { "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) },
- { "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) },
- { "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) },
- /* %Q: force cond_p=1 --> no shimm values */
- /* ??? This insn allows an optional flags spec. */
- { "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) },
- /* Put opcode 1 ld insns first so shimm gets prefered over limm. */
- /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
- { "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) },
- { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) },
- { "ld%z%.x%.w%.e%Q %a,[%b,%c]%L", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) },
- { "lp%q%.n %B", I(-1), I(6), },
- { "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) },
- { "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) },
- { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) },
- { "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) },
- { "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) },
- { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) },
- { "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) },
- { "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) },
- { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) },
- /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
- { "st%y%.v%.D%Q %0%c,[%b]%L", I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) },
- { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,1)+R(-1,21,1), I(2)+R(0,25,1)+R(0,21,1) },
- { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) },
- { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) }
+ { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 },
+ { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 },
+ { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 },
+ { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 },
+ { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 },
+ { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 },
+ { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 },
+ { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 },
+ { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 },
+ { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 },
+ { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 },
+ { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 },
+ /* %Q: force cond_p=1 -> no shimm values. This insn allows an
+ optional flags spec. */
+ { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ /* This insn allows an optional flags spec. */
+ { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
+ /* Put opcode 1 ld insns first so shimm gets prefered over limm.
+ "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
+ { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 },
+ { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
+ { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
+ { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 },
+ { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 },
+ { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 },
+ { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 },
+ { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 },
+ { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 },
+ { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 },
+ { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 },
+ { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 },
+ { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 },
+ { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 },
+ /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
+ { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
+ { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
+ { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 },
+ { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 }
};
+
const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
const struct arc_operand_value arc_reg_names[] =
{
- /* Sort this so that the first 61 entries are sequential.
- IE: For each i (i<61), arc_reg_names[i].value == i. */
-
- { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG },
- { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG },
- { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG },
- { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG },
- { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG },
- { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG },
- { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG },
- { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG },
- { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG },
- { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG },
- { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG },
- { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG },
- { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG },
- { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG },
- { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG },
- { "lp_count", 60, REG },
-
- /* I'd prefer to output these as "fp" and "sp" by default, but we still need
- to recognize the canonical values. */
- { "r27", 27, REG }, { "r28", 28, REG },
-
- /* Someone may wish to refer to these in this way, and it's probably a
- good idea to reserve them as such anyway. */
- { "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG },
-
- /* Standard auxiliary registers. */
- { "status", 0, AUXREG },
- { "semaphore", 1, AUXREG },
- { "lp_start", 2, AUXREG },
- { "lp_end", 3, AUXREG },
- { "identity", 4, AUXREG },
- { "debug", 5, AUXREG },
+ /* Core register set r0-r63. */
+
+ /* r0-r28 - general purpose registers. */
+ { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
+ { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
+ { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
+ { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
+ { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
+ { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
+ { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
+ { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
+ { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 },
+ { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 },
+ /* Maskable interrupt link register. */
+ { "ilink1", 29, REG, 0 },
+ /* Maskable interrupt link register. */
+ { "ilink2", 30, REG, 0 },
+ /* Branch-link register. */
+ { "blink", 31, REG, 0 },
+
+ /* r32-r59 reserved for extensions. */
+ { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 },
+ { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 },
+ { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 },
+ { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 },
+ { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 },
+ { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 },
+ { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 },
+ { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 },
+ { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 },
+ { "r59", 59, REG, 0 },
+
+ /* Loop count register (24 bits). */
+ { "lp_count", 60, REG, 0 },
+ /* Short immediate data indicator setting flags. */
+ { "r61", 61, REG, ARC_REGISTER_READONLY },
+ /* Long immediate data indicator setting flags. */
+ { "r62", 62, REG, ARC_REGISTER_READONLY },
+ /* Short immediate data indicator not setting flags. */
+ { "r63", 63, REG, ARC_REGISTER_READONLY },
+
+ /* Small-data base register. */
+ { "gp", 26, REG, 0 },
+ /* Frame pointer. */
+ { "fp", 27, REG, 0 },
+ /* Stack pointer. */
+ { "sp", 28, REG, 0 },
+
+ { "r29", 29, REG, 0 },
+ { "r30", 30, REG, 0 },
+ { "r31", 31, REG, 0 },
+ { "r60", 60, REG, 0 },
+
+ /* Auxiliary register set. */
+
+ /* Auxiliary register address map:
+ 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
+ 0xfffffeff-0x80000000 - customer limm allocation
+ 0x7fffffff-0x00000100 - ARC limm allocation
+ 0x000000ff-0x00000000 - ARC shimm allocation */
+
+ /* Base case auxiliary registers (shimm address). */
+ { "status", 0x00, AUXREG, 0 },
+ { "semaphore", 0x01, AUXREG, 0 },
+ { "lp_start", 0x02, AUXREG, 0 },
+ { "lp_end", 0x03, AUXREG, 0 },
+ { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY },
+ { "debug", 0x05, AUXREG, 0 },
};
-const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
+
+const int arc_reg_names_count =
+ sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
/* The suffix table.
Operands with the same name must be stored together. */
@@ -357,58 +428,64 @@ const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0
const struct arc_operand_value arc_suffixes[] =
{
/* Entry 0 is special, default values aren't printed by the disassembler. */
- { "", 0, -1 },
- { "al", 0, COND },
- { "ra", 0, COND },
- { "eq", 1, COND },
- { "z", 1, COND },
- { "ne", 2, COND },
- { "nz", 2, COND },
- { "p", 3, COND },
- { "pl", 3, COND },
- { "n", 4, COND },
- { "mi", 4, COND },
- { "c", 5, COND },
- { "cs", 5, COND },
- { "lo", 5, COND },
- { "nc", 6, COND },
- { "cc", 6, COND },
- { "hs", 6, COND },
- { "v", 7, COND },
- { "vs", 7, COND },
- { "nv", 8, COND },
- { "vc", 8, COND },
- { "gt", 9, COND },
- { "ge", 10, COND },
- { "lt", 11, COND },
- { "le", 12, COND },
- { "hi", 13, COND },
- { "ls", 14, COND },
- { "pnz", 15, COND },
- { "f", 1, FLAG },
- { "nd", ARC_DELAY_NONE, DELAY },
- { "d", ARC_DELAY_NORMAL, DELAY },
- { "jd", ARC_DELAY_JUMP, DELAY },
-/*{ "b", 7, SIZEEXT },*/
-/*{ "b", 5, SIZESEX },*/
- { "b", 1, SIZE1 },
- { "b", 1, SIZE10 },
- { "b", 1, SIZE22 },
-/*{ "w", 8, SIZEEXT },*/
-/*{ "w", 6, SIZESEX },*/
- { "w", 2, SIZE1 },
- { "w", 2, SIZE10 },
- { "w", 2, SIZE22 },
- { "x", 1, SIGN0 },
- { "x", 1, SIGN9 },
- { "a", 1, ADDRESS3 },
- { "a", 1, ADDRESS12 },
- { "a", 1, ADDRESS24 },
- { "di", 1, CACHEBYPASS5 },
- { "di", 1, CACHEBYPASS14 },
- { "di", 1, CACHEBYPASS26 },
+ { "", 0, -1, 0 },
+
+ /* Base case condition codes. */
+ { "al", 0, COND, 0 },
+ { "ra", 0, COND, 0 },
+ { "eq", 1, COND, 0 },
+ { "z", 1, COND, 0 },
+ { "ne", 2, COND, 0 },
+ { "nz", 2, COND, 0 },
+ { "pl", 3, COND, 0 },
+ { "p", 3, COND, 0 },
+ { "mi", 4, COND, 0 },
+ { "n", 4, COND, 0 },
+ { "cs", 5, COND, 0 },
+ { "c", 5, COND, 0 },
+ { "lo", 5, COND, 0 },
+ { "cc", 6, COND, 0 },
+ { "nc", 6, COND, 0 },
+ { "hs", 6, COND, 0 },
+ { "vs", 7, COND, 0 },
+ { "v", 7, COND, 0 },
+ { "vc", 8, COND, 0 },
+ { "nv", 8, COND, 0 },
+ { "gt", 9, COND, 0 },
+ { "ge", 10, COND, 0 },
+ { "lt", 11, COND, 0 },
+ { "le", 12, COND, 0 },
+ { "hi", 13, COND, 0 },
+ { "ls", 14, COND, 0 },
+ { "pnz", 15, COND, 0 },
+
+ /* Condition codes 16-31 reserved for extensions. */
+
+ { "f", 1, FLAG, 0 },
+
+ { "nd", ARC_DELAY_NONE, DELAY, 0 },
+ { "d", ARC_DELAY_NORMAL, DELAY, 0 },
+ { "jd", ARC_DELAY_JUMP, DELAY, 0 },
+
+ { "b", 1, SIZE1, 0 },
+ { "b", 1, SIZE10, 0 },
+ { "b", 1, SIZE22, 0 },
+ { "w", 2, SIZE1, 0 },
+ { "w", 2, SIZE10, 0 },
+ { "w", 2, SIZE22, 0 },
+ { "x", 1, SIGN0, 0 },
+ { "x", 1, SIGN9, 0 },
+ { "a", 1, ADDRESS3, 0 },
+ { "a", 1, ADDRESS12, 0 },
+ { "a", 1, ADDRESS24, 0 },
+
+ { "di", 1, CACHEBYPASS5, 0 },
+ { "di", 1, CACHEBYPASS14, 0 },
+ { "di", 1, CACHEBYPASS26, 0 },
};
-const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
+
+const int arc_suffixes_count =
+ sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
/* Indexed by first letter of opcode. Points to chain of opcodes with same
first letter. */
@@ -429,10 +506,12 @@ arc_get_opcode_mach (bfd_mach, big_p)
int bfd_mach, big_p;
{
static int mach_type_map[] =
- {
- ARC_MACH_BASE
- };
-
+ {
+ ARC_MACH_5,
+ ARC_MACH_6,
+ ARC_MACH_7,
+ ARC_MACH_8
+ };
return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0);
}
@@ -453,8 +532,6 @@ arc_opcode_init_tables (flags)
/* We may be intentionally called more than once (for example gdb will call
us each time the user switches cpu). These tables only need to be init'd
once though. */
- /* ??? We can remove the need for arc_opcode_supported by taking it into
- account here, but I'm not sure I want to do that yet (if ever). */
if (!init_p)
{
register int i,n;
@@ -490,23 +567,7 @@ int
arc_opcode_supported (opcode)
const struct arc_opcode *opcode;
{
- if (ARC_OPCODE_CPU (opcode->flags) == 0)
- return 1;
- if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type))
- return 1;
- return 0;
-}
-
-/* Return non-zero if OPVAL is supported on the specified cpu.
- Cpu selection is made when calling `arc_opcode_init_tables'. */
-
-int
-arc_opval_supported (opval)
- const struct arc_operand_value *opval;
-{
- if (ARC_OPVAL_CPU (opval->flags) == 0)
- return 1;
- if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type))
+ if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type)
return 1;
return 0;
}
@@ -535,14 +596,26 @@ static int flag_p;
/* Nonzero if we've finished processing the 'f' suffix. */
static int flagshimm_handled_p;
+/* Nonzero if we've seen a 'a' suffix (address writeback). */
+static int addrwb_p;
+
/* Nonzero if we've seen a 'q' suffix (condition code). */
static int cond_p;
+/* Nonzero if we've inserted a nullify condition. */
+static int nullify_p;
+
+/* The value of the a nullify condition we inserted. */
+static int nullify;
+
+/* Nonzero if we've inserted jumpflags. */
+static int jumpflags_p;
+
/* Nonzero if we've inserted a shimm. */
static int shimm_p;
/* The value of the shimm we inserted (each insn only gets one but it can
- appear multiple times. */
+ appear multiple times). */
static int shimm;
/* Nonzero if we've inserted a limm (during assembly) or seen a limm
@@ -560,11 +633,20 @@ static long limm;
void
arc_opcode_init_insert ()
{
+ int i;
+
+ for(i = 0; i < OPERANDS; i++)
+ ls_operand[i] = OP_NONE;
+
flag_p = 0;
flagshimm_handled_p = 0;
cond_p = 0;
+ addrwb_p = 0;
shimm_p = 0;
limm_p = 0;
+ jumpflags_p = 0;
+ nullify_p = 0;
+ nullify = 0; /* the default is important. */
}
/* Called by the assembler to see if the insn has a limm operand.
@@ -594,6 +676,7 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
const char **errmsg;
{
static char buf[100];
+ enum operand op_type = OP_NONE;
if (reg == NULL)
{
@@ -609,16 +692,30 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
we have to use a limm. */
&& (!shimm_p || shimm == value))
{
- int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
- flagshimm_handled_p = 1;
- shimm_p = 1;
- shimm = value;
+ int marker;
+
+ op_type = OP_SHIMM;
+ /* forget about shimm as dest mlm. */
+
+ if ('a' != operand->fmt)
+ {
+ shimm_p = 1;
+ shimm = value;
+ flagshimm_handled_p = 1;
+ marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
+ }
+ else
+ {
+ /* don't request flag setting on shimm as dest. */
+ marker = ARC_REG_SHIMM;
+ }
insn |= marker << operand->shift;
- /* insn |= value & 511; - done later */
+ /* insn |= value & 511; - done later. */
}
/* We have to use a limm. If we've already seen one they must match. */
else if (!limm_p || limm == value)
{
+ op_type = OP_LIMM;
limm_p = 1;
limm = value;
insn |= ARC_REG_LIMM << operand->shift;
@@ -626,7 +723,7 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
}
else
{
- *errmsg = _("unable to fit different valued constants into instruction");
+ *errmsg = "unable to fit different valued constants into instruction";
}
}
else
@@ -636,27 +733,66 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
if (reg->type == AUXREG)
{
if (!(mods & ARC_MOD_AUXREG))
- *errmsg = _("auxiliary register not allowed here");
+ *errmsg = "auxiliary register not allowed here";
else
{
+ if ((insn & I(-1)) == I(2)) /* check for use validity. */
+ {
+ if (reg->flags & ARC_REGISTER_READONLY)
+ *errmsg = "attempt to set readonly register";
+ }
+ else
+ {
+ if (reg->flags & ARC_REGISTER_WRITEONLY)
+ *errmsg = "attempt to read writeonly register";
+ }
insn |= ARC_REG_SHIMM << operand->shift;
insn |= reg->value << arc_operands[reg->type].shift;
}
}
else
{
+ /* check for use validity. */
+ if ('a' == operand->fmt || ((insn & I(-1)) < I(2)))
+ {
+ if (reg->flags & ARC_REGISTER_READONLY)
+ *errmsg = "attempt to set readonly register";
+ }
+ if ('a' != operand->fmt)
+ {
+ if (reg->flags & ARC_REGISTER_WRITEONLY)
+ *errmsg = "attempt to read writeonly register";
+ }
/* We should never get an invalid register number here. */
if ((unsigned int) reg->value > 60)
{
- /* xgettext:c-format */
- sprintf (buf, _("invalid register number `%d'"), reg->value);
+ sprintf (buf, "invalid register number `%d'", reg->value);
*errmsg = buf;
}
- else
- insn |= reg->value << operand->shift;
+ insn |= reg->value << operand->shift;
+ op_type = OP_REG;
}
}
+ switch (operand->fmt)
+ {
+ case 'a':
+ ls_operand[LS_DEST] = op_type;
+ break;
+ case 's':
+ ls_operand[LS_BASE] = op_type;
+ break;
+ case 'c':
+ if ((insn & I(-1)) == I(2))
+ ls_operand[LS_VALUE] = op_type;
+ else
+ ls_operand[LS_OFFSET] = op_type;
+ break;
+ case 'o': case 'O':
+ ls_operand[LS_OFFSET] = op_type;
+ break;
+ }
+
return insn;
}
@@ -665,17 +801,33 @@ insert_reg (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_flag (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
/* We can't store anything in the insn until we've parsed the registers.
Just record the fact that we've got this flag. `insert_reg' will use it
to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */
flag_p = 1;
+ return insn;
+}
+/* Called when we see an nullify condition. */
+
+static arc_insn
+insert_nullify (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value;
+ const char **errmsg ATTRIBUTE_UNUSED;
+{
+ nullify_p = 1;
+ insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ nullify = value;
return insn;
}
@@ -687,10 +839,10 @@ static arc_insn
insert_flagfinish (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
if (flag_p && !flagshimm_handled_p)
{
@@ -708,10 +860,10 @@ static arc_insn
insert_cond (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
long value;
- const char **errmsg;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
cond_p = 1;
insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
@@ -727,20 +879,82 @@ insert_cond (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_forcelimm (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
+{
+ cond_p = 1;
+ return insn;
+}
+
+static arc_insn
+insert_addr_wb (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
+{
+ addrwb_p = 1 << operand->shift;
+ return insn;
+}
+
+static arc_insn
+insert_base (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
- cond_p = 1;
+ if (reg != NULL)
+ {
+ arc_insn myinsn;
+ myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift;
+ insn |= B(myinsn);
+ ls_operand[LS_BASE] = OP_REG;
+ }
+ else if (ARC_SHIMM_CONST_P (value) && !cond_p)
+ {
+ if (shimm_p && value != shimm)
+ {
+ /* convert the previous shimm operand to a limm. */
+ limm_p = 1;
+ limm = shimm;
+ insn &= ~C(-1); /* we know where the value is in insn. */
+ insn |= C(ARC_REG_LIMM);
+ ls_operand[LS_VALUE] = OP_LIMM;
+ }
+ insn |= ARC_REG_SHIMM << operand->shift;
+ shimm_p = 1;
+ shimm = value;
+ ls_operand[LS_BASE] = OP_SHIMM;
+ }
+ else
+ {
+ if (limm_p && value != limm)
+ {
+ *errmsg = "too many long constants";
+ return insn;
+ }
+ limm_p = 1;
+ limm = value;
+ insn |= B(ARC_REG_LIMM);
+ ls_operand[LS_BASE] = OP_LIMM;
+ }
+
return insn;
}
-/* Used in ld/st insns to handle the shimm offset field. */
+/* Used in ld/st insns to handle the offset field. We don't try to
+ match operand syntax here. we catch bad combinations later. */
static arc_insn
-insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
+insert_offset (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
@@ -749,11 +963,15 @@ insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
const char **errmsg;
{
long minval, maxval;
- static char buf[100];
if (reg != NULL)
{
- *errmsg = "register appears where shimm value expected";
+ arc_insn myinsn;
+ myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift;
+ ls_operand[LS_OFFSET] = OP_REG;
+ if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later. */
+ if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later. */
+ insn |= C(myinsn);
}
else
{
@@ -769,35 +987,271 @@ insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
minval = 0;
maxval = (1 << operand->bits) - 1;
}
- if (value < minval || value > maxval)
+ if ((cond_p && !limm_p) || (value < minval || value > maxval))
{
- /* xgettext:c-format */
- sprintf (buf, _("value won't fit in range %ld - %ld"),
- minval, maxval);
- *errmsg = buf;
+ if (limm_p && value != limm)
+ {
+ *errmsg = "too many long constants";
+ }
+ else
+ {
+ limm_p = 1;
+ limm = value;
+ if (operand->flags & ARC_OPERAND_STORE)
+ insn |= B(ARC_REG_LIMM);
+ if (operand->flags & ARC_OPERAND_LOAD)
+ insn |= C(ARC_REG_LIMM);
+ ls_operand[LS_OFFSET] = OP_LIMM;
+ }
}
else
- insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ {
+ if ((value < minval || value > maxval))
+ *errmsg = "need too many limms";
+ else if (shimm_p && value != shimm)
+ {
+ /* check for bad operand combinations before we lose info about them. */
+ if ((insn & I(-1)) == I(1))
+ {
+ *errmsg = "to many shimms in load";
+ goto out;
+ }
+ if (limm_p && operand->flags & ARC_OPERAND_LOAD)
+ {
+ *errmsg = "too many long constants";
+ goto out;
+ }
+ /* convert what we thought was a shimm to a limm. */
+ limm_p = 1;
+ limm = shimm;
+ if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
+ {
+ insn &= ~C(-1);
+ insn |= C(ARC_REG_LIMM);
+ ls_operand[LS_VALUE] = OP_LIMM;
+ }
+ if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
+ {
+ insn &= ~B(-1);
+ insn |= B(ARC_REG_LIMM);
+ ls_operand[LS_BASE] = OP_LIMM;
+ }
+ }
+ shimm = value;
+ shimm_p = 1;
+ ls_operand[LS_OFFSET] = OP_SHIMM;
+ }
}
+ out:
return insn;
}
-/* Used in ld/st insns when the shimm offset is 0. */
+/* Used in st insns to do final disasemble syntax check. */
+
+static long
+extract_st_syntax (insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid;
+{
+#define ST_SYNTAX(V,B,O) \
+((ls_operand[LS_VALUE] == (V) && \
+ ls_operand[LS_BASE] == (B) && \
+ ls_operand[LS_OFFSET] == (O)))
+
+ if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
+ || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
+ || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
+ || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0)
+ || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
+ || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
+ || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
+ || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+ || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
+ || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)
+ || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
+ *invalid = 1;
+ return 0;
+}
+
+int
+arc_limm_fixup_adjust(insn)
+ arc_insn insn;
+{
+ int retval = 0;
+
+ /* check for st shimm,[limm]. */
+ if ((insn & (I(-1) | C(-1) | B(-1))) ==
+ (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
+ {
+ retval = insn & 0x1ff;
+ if (retval & 0x100) /* sign extend 9 bit offset. */
+ retval |= ~0x1ff;
+ }
+ return -retval; /* negate offset for return. */
+}
+
+/* Used in st insns to do final syntax check. */
static arc_insn
-insert_shimmzero (insn, operand, mods, reg, value, errmsg)
+insert_st_syntax (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
const char **errmsg;
{
- shimm_p = 1;
- shimm = 0;
+ if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0)
+ {
+ /* change an illegal insn into a legal one, it's easier to
+ do it here than to try to handle it during operand scan. */
+ limm_p = 1;
+ limm = shimm;
+ shimm_p = 0;
+ shimm = 0;
+ insn = insn & ~(C(-1) | 511);
+ insn |= ARC_REG_LIMM << ARC_SHIFT_REGC;
+ ls_operand[LS_VALUE] = OP_LIMM;
+ }
+
+ if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE))
+ {
+ /* try to salvage this syntax. */
+ if (shimm & 0x1) /* odd shimms won't work. */
+ {
+ if (limm_p) /* do we have a limm already? */
+ {
+ *errmsg = "impossible store";
+ }
+ limm_p = 1;
+ limm = shimm;
+ shimm = 0;
+ shimm_p = 0;
+ insn = insn & ~(B(-1) | 511);
+ insn |= B(ARC_REG_LIMM);
+ ls_operand[LS_BASE] = OP_LIMM;
+ }
+ else
+ {
+ shimm >>= 1;
+ insn = insn & ~511;
+ insn |= shimm;
+ ls_operand[LS_OFFSET] = OP_SHIMM;
+ }
+ }
+ if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE))
+ {
+ limm += arc_limm_fixup_adjust(insn);
+ }
+ if (ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) && (shimm * 2 == limm))
+ {
+ insn &= ~C(-1);
+ limm_p = 0;
+ limm = 0;
+ insn |= C(ARC_REG_SHIMM);
+ ls_operand[LS_VALUE] = OP_SHIMM;
+ }
+ if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE)
+ || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
+ || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+ || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+ || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0))
+ || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
+ || ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE)
+ || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
+ || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
+ || ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE)
+ || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
+ *errmsg = "st operand error";
+ if (addrwb_p)
+ {
+ if (ls_operand[LS_BASE] != OP_REG)
+ *errmsg = "address writeback not allowed";
+ insn |= addrwb_p;
+ }
+ if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm)
+ *errmsg = "store value must be zero";
+ return insn;
+}
+
+/* Used in ld insns to do final syntax check. */
+
+static arc_insn
+insert_ld_syntax (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg;
+{
+#define LD_SYNTAX(D,B,O) \
+((ls_operand[LS_DEST] == (D) && \
+ ls_operand[LS_BASE] == (B) && \
+ ls_operand[LS_OFFSET] == (O)))
+
+ int test = insn & I(-1);
+
+ if (!(test == I(1)))
+ {
+ if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
+ || ls_operand[LS_OFFSET] == OP_SHIMM))
+ *errmsg = "invalid load/shimm insn";
+ }
+ if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE)
+ || LD_SYNTAX(OP_REG,OP_REG,OP_REG)
+ || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+ || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
+ || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
+ || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+ || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
+ *errmsg = "ld operand error";
+ if (addrwb_p)
+ {
+ if (ls_operand[LS_BASE] != OP_REG)
+ *errmsg = "address writeback not allowed";
+ insn |= addrwb_p;
+ }
return insn;
}
+/* Used in ld insns to do final syntax check. */
+
+static long
+extract_ld_syntax (insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid;
+{
+ int test = insn[0] & I(-1);
+
+ if (!(test == I(1)))
+ {
+ if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
+ || ls_operand[LS_OFFSET] == OP_SHIMM))
+ *invalid = 1;
+ }
+ if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1)))
+ || LD_SYNTAX(OP_REG,OP_REG,OP_REG)
+ || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
+ || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
+ || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
+ || (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0))
+ || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
+ || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
+ *invalid = 1;
+ return 0;
+}
+
/* Called at the end of processing normal insns (eg: add) to insert a shimm
value (if present) into the insn. */
@@ -805,10 +1259,10 @@ static arc_insn
insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
if (shimm_p)
insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
@@ -830,14 +1284,51 @@ insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
static arc_insn
insert_limmfinish (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
+{
+#if 0
+ if (limm_p)
+ ; /* nothing to do, gas does it. */
+#endif
+ return insn;
+}
+
+static arc_insn
+insert_jumpflags (insn, operand, mods, reg, value, errmsg)
+ arc_insn insn;
const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
long value;
const char **errmsg;
{
- if (limm_p)
- ; /* nothing to do, gas does it */
+ if (!flag_p)
+ {
+ *errmsg = "jump flags, but no .f seen";
+ }
+ if (!limm_p)
+ {
+ *errmsg = "jump flags, but no limm addr";
+ }
+ if (limm & 0xfc000000)
+ {
+ *errmsg = "flag bits of jump address limm lost";
+ }
+ if (limm & 0x03000000)
+ {
+ *errmsg = "attempt to set HR bits";
+ }
+ if ((value & ((1 << operand->bits) - 1)) != value)
+ {
+ *errmsg = "bad jump flags value";
+ }
+ jumpflags_p = 1;
+ limm = ((limm & ((1 << operand->shift) - 1))
+ | ((value & ((1 << operand->bits) - 1)) << operand->shift));
return insn;
}
@@ -847,10 +1338,10 @@ static arc_insn
insert_unopmacro (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
{
insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
return insn;
@@ -862,13 +1353,13 @@ static arc_insn
insert_reladdr (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
long value;
const char **errmsg;
{
if (value & 3)
- *errmsg = _("branch address not on 4 byte boundary");
+ *errmsg = "branch address not on 4 byte boundary";
insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
return insn;
}
@@ -878,23 +1369,42 @@ insert_reladdr (insn, operand, mods, reg, value, errmsg)
Note that this function is only intended to handle instructions (with 4 byte
immediate operands). It is not intended to handle data. */
-/* ??? Actually, there's nothing for us to do as we can't call frag_more, the
+/* ??? Actually, there's little for us to do as we can't call frag_more, the
caller must do that. The extract fns take a pointer to two words. The
insert fns could be converted and then we could do something useful, but
then the reloc handlers would have to know to work on the second word of
- a 2 word quantity. That's too much so we don't handle them. */
+ a 2 word quantity. That's too much so we don't handle them.
+
+ We do check for correct usage of the nullify suffix, or we
+ set the default correctly, though. */
static arc_insn
insert_absaddr (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
+ long value ATTRIBUTE_UNUSED;
const char **errmsg;
{
if (limm_p)
- ; /* nothing to do */
+ {
+ /* if it is a jump and link, .jd must be specified. */
+ if (insn & R(-1,9,1))
+ {
+ if (!nullify_p)
+ {
+ insn |= 0x02 << 5; /* default nullify to .jd. */
+ }
+ else
+ {
+ if (nullify != 0x02)
+ {
+ *errmsg = "must specify .jd or no nullify suffix";
+ }
+ }
+ }
+ }
return insn;
}
@@ -912,10 +1422,7 @@ static const struct arc_operand_value *lookup_register (int type, long regno);
void
arc_opcode_init_extract ()
{
- flag_p = 0;
- flagshimm_handled_p = 0;
- shimm_p = 0;
- limm_p = 0;
+ arc_opcode_init_insert();
}
/* As we're extracting registers, keep an eye out for the 'f' indicator
@@ -931,42 +1438,72 @@ extract_reg (insn, operand, mods, opval, invalid)
const struct arc_operand *operand;
int mods;
const struct arc_operand_value **opval;
- int *invalid;
+ int *invalid ATTRIBUTE_UNUSED;
{
int regno;
long value;
+ enum operand op_type;
/* Get the register number. */
- regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
/* Is it a constant marker? */
if (regno == ARC_REG_SHIMM)
{
- value = insn[0] & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (value & 256))
- value -= 512;
- flagshimm_handled_p = 1;
+ op_type = OP_SHIMM;
+ /* always return zero if dest is a shimm mlm. */
+
+ if ('a' != operand->fmt)
+ {
+ value = *insn & 511;
+ if ((operand->flags & ARC_OPERAND_SIGNED)
+ && (value & 256))
+ value -= 512;
+ if (!flagshimm_handled_p)
+ flag_p = 0;
+ flagshimm_handled_p = 1;
+ }
+ else
+ {
+ value = 0;
+ }
}
else if (regno == ARC_REG_SHIMM_UPDATE)
{
- value = insn[0] & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (value & 256))
- value -= 512;
+ op_type = OP_SHIMM;
+
+ /* always return zero if dest is a shimm mlm. */
+
+ if ('a' != operand->fmt)
+ {
+ value = *insn & 511;
+ if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
+ value -= 512;
+ }
+ else
+ {
+ value = 0;
+ }
flag_p = 1;
flagshimm_handled_p = 1;
}
else if (regno == ARC_REG_LIMM)
{
+ op_type = OP_LIMM;
value = insn[1];
limm_p = 1;
+ /* if this is a jump instruction (j,jl), show new pc correctly. */
+ if (0x07 == ((*insn & I(-1)) >> 27))
+ {
+ value = (value & 0xffffff);
+ }
}
/* It's a register, set OPVAL (that's the only way we distinguish registers
from constants here). */
else
{
const struct arc_operand_value *reg = lookup_register (REG, regno);
+ op_type = OP_REG;
if (reg == NULL)
abort ();
@@ -986,6 +1523,24 @@ extract_reg (insn, operand, mods, opval, invalid)
if (reg != NULL && opval != NULL)
*opval = reg;
}
+ switch(operand->fmt)
+ {
+ case 'a':
+ ls_operand[LS_DEST] = op_type;
+ break;
+ case 's':
+ ls_operand[LS_BASE] = op_type;
+ break;
+ case 'c':
+ if ((insn[0]& I(-1)) == I(2))
+ ls_operand[LS_VALUE] = op_type;
+ else
+ ls_operand[LS_OFFSET] = op_type;
+ break;
+ case 'o': case 'O':
+ ls_operand[LS_OFFSET] = op_type;
+ break;
+ }
return value;
}
@@ -997,9 +1552,9 @@ static long
extract_flag (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
- int mods;
+ int mods ATTRIBUTE_UNUSED;
const struct arc_operand_value **opval;
- int *invalid;
+ int *invalid ATTRIBUTE_UNUSED;
{
int f;
const struct arc_operand_value *val;
@@ -1007,12 +1562,12 @@ extract_flag (insn, operand, mods, opval, invalid)
if (flagshimm_handled_p)
f = flag_p != 0;
else
- f = (insn[0] & (1 << operand->shift)) != 0;
+ f = (*insn & (1 << operand->shift)) != 0;
/* There is no text for zero values. */
if (f == 0)
return 0;
-
+ flag_p = 1;
val = arc_opcode_lookup_suffix (operand, 1);
if (opval != NULL && val != NULL)
*opval = val;
@@ -1028,9 +1583,9 @@ static long
extract_cond (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
- int mods;
+ int mods ATTRIBUTE_UNUSED;
const struct arc_operand_value **opval;
- int *invalid;
+ int *invalid ATTRIBUTE_UNUSED;
{
long cond;
const struct arc_operand_value *val;
@@ -1038,7 +1593,7 @@ extract_cond (insn, operand, mods, opval, invalid)
if (flagshimm_handled_p)
return 0;
- cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
val = arc_opcode_lookup_suffix (operand, cond);
/* Ignore NULL values of `val'. Several condition code values are
@@ -1055,20 +1610,88 @@ static long
extract_reladdr (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid ATTRIBUTE_UNUSED;
{
long addr;
- addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
if ((operand->flags & ARC_OPERAND_SIGNED)
&& (addr & (1 << (operand->bits - 1))))
addr -= 1 << operand->bits;
-
return addr << 2;
}
+/* extract the flags bits from a j or jl long immediate. */
+static long
+extract_jumpflags(insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid;
+{
+ if (!flag_p || !limm_p)
+ *invalid = 1;
+ return ((flag_p && limm_p)
+ ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
+}
+
+/* extract st insn's offset. */
+
+static long
+extract_st_offset (insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
+ int *invalid;
+{
+ int value = 0;
+
+ if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM)
+ {
+ value = insn[0] & 511;
+ if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
+ value -= 512;
+ if (value)
+ ls_operand[LS_OFFSET] = OP_SHIMM;
+ }
+ else
+ {
+ *invalid = 1;
+ }
+ return(value);
+}
+
+/* extract ld insn's offset. */
+
+static long
+extract_ld_offset (insn, operand, mods, opval, invalid)
+ arc_insn *insn;
+ const struct arc_operand *operand;
+ int mods;
+ const struct arc_operand_value **opval;
+ int *invalid;
+{
+ int test = insn[0] & I(-1);
+ int value;
+
+ if (test)
+ {
+ value = insn[0] & 511;
+ if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
+ value -= 512;
+ if (value)
+ ls_operand[LS_OFFSET] = OP_SHIMM;
+ return(value);
+ }
+ /* if it isn't in the insn, it's concealed behind reg 'c'. */
+ return extract_reg (insn, &arc_operands[arc_operand_map['c']],
+ mods, opval, invalid);
+}
+
/* The only thing this does is set the `invalid' flag if B != C.
This is needed because the "mov" macro appears before it's real insn "and"
and we don't want the disassembler to confuse them. */
@@ -1076,19 +1699,18 @@ extract_reladdr (insn, operand, mods, opval, invalid)
static long
extract_unopmacro (insn, operand, mods, opval, invalid)
arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
+ const struct arc_operand *operand ATTRIBUTE_UNUSED;
+ int mods ATTRIBUTE_UNUSED;
+ const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
int *invalid;
{
/* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
printed as "and"s. */
- if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG)
- != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG))
+ if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG)
+ != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG))
if (invalid != NULL)
*invalid = 1;
-
return 0;
}
@@ -1101,6 +1723,15 @@ arc_opcode_lookup_suffix (type, value)
int value;
{
register const struct arc_operand_value *v,*end;
+ struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+
+ while (ext_oper)
+ {
+ if (type == &arc_operands[ext_oper->operand.type]
+ && value == ext_oper->operand.value)
+ return (&ext_oper->operand);
+ ext_oper = ext_oper->next;
+ }
/* ??? This is a little slow and can be speeded up. */
@@ -1117,6 +1748,14 @@ lookup_register (type, regno)
long regno;
{
register const struct arc_operand_value *r,*end;
+ struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+
+ while (ext_oper)
+ {
+ if (ext_oper->operand.type == type && ext_oper->operand.value == regno)
+ return (&ext_oper->operand);
+ ext_oper = ext_oper->next;
+ }
if (type == REG)
return &arc_reg_names[regno];
@@ -1129,3 +1768,58 @@ lookup_register (type, regno)
return r;
return 0;
}
+
+int
+arc_insn_is_j(insn)
+ arc_insn insn;
+{
+ return (insn & (I(-1))) == I(0x7);
+}
+
+int
+arc_insn_not_jl(insn)
+ arc_insn insn;
+{
+ return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1)))
+ != (I(0x7) | R(-1,9,1)));
+}
+
+int
+arc_operand_type(int opertype)
+{
+ switch (opertype)
+ {
+ case 0:
+ return(COND);
+ break;
+ case 1:
+ return(REG);
+ break;
+ case 2:
+ return(AUXREG);
+ break;
+ }
+ return -1;
+}
+
+struct arc_operand_value *
+get_ext_suffix(s)
+ char *s;
+{
+ struct arc_ext_operand_value *suffix = arc_ext_operands;
+
+ while (suffix)
+ {
+ if ((COND == suffix->operand.type)
+ && !strcmp(s,suffix->operand.name))
+ return(&suffix->operand);
+ suffix = suffix->next;
+ }
+ return NULL;
+}
+
+int
+arc_get_noshortcut_flag()
+{
+ return ARC_REGISTER_NOSHORT_CUT;
+}
diff --git a/contrib/binutils/opcodes/cgen-asm.c b/contrib/binutils/opcodes/cgen-asm.c
index 4ed6936..a8d6ff8 100644
--- a/contrib/binutils/opcodes/cgen-asm.c
+++ b/contrib/binutils/opcodes/cgen-asm.c
@@ -1,6 +1,6 @@
/* CGEN generic assembler support code.
- Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -66,7 +66,7 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf)
CGEN_CPU_DESC cd;
const CGEN_INSN *insns;
int count;
- int entsize;
+ int entsize ATTRIBUTE_UNUSED;
CGEN_INSN_LIST **htable;
CGEN_INSN_LIST *hentbuf;
{
@@ -198,7 +198,7 @@ cgen_asm_lookup_insn (cd, insn)
const char *
cgen_parse_keyword (cd, strp, keyword_table, valuep)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
const char **strp;
CGEN_KEYWORD *keyword_table;
long *valuep;
diff --git a/contrib/binutils/opcodes/cgen-asm.in b/contrib/binutils/opcodes/cgen-asm.in
new file mode 100644
index 0000000..7249708
--- /dev/null
+++ b/contrib/binutils/opcodes/cgen-asm.in
@@ -0,0 +1,321 @@
+/* Assembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+- the resultant file is machine generated, cgen-asm.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <ctype.h>
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "@prefix@-desc.h"
+#include "@prefix@-opc.h"
+#include "opintl.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *));
+
+/* -- assembler routines inserted here */
+
+/* Default insn parser.
+
+ The syntax string is scanned and operands are parsed and stored in FIELDS.
+ Relocs are queued as we go via other callbacks.
+
+ ??? Note that this is currently an all-or-nothing parser. If we fail to
+ parse the instruction, we return 0 and the caller will start over from
+ the beginning. Backtracking will be necessary in parsing subexpressions,
+ but that can be handled there. Not handling backtracking here may get
+ expensive in the case of the m68k. Deal with later.
+
+ Returns NULL for success, an error message for failure.
+*/
+
+static const char *
+parse_insn_normal (cd, insn, strp, fields)
+ CGEN_CPU_DESC cd;
+ const CGEN_INSN *insn;
+ const char **strp;
+ CGEN_FIELDS *fields;
+{
+ /* ??? Runtime added insns not handled yet. */
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const char *str = *strp;
+ const char *errmsg;
+ const char *p;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+ /* FIXME: wip */
+ int past_opcode_p;
+#endif
+
+ /* For now we assume the mnemonic is first (there are no leading operands).
+ We can parse it without needing to set up operand parsing.
+ GAS's input scrubber will ensure mnemonics are lowercase, but we may
+ not be called from GAS. */
+ p = CGEN_INSN_MNEMONIC (insn);
+ while (*p && tolower (*p) == tolower (*str))
+ ++p, ++str;
+
+ if (* p)
+ return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+ if (* str && !isspace (* str))
+ return _("unrecognized instruction");
+#endif
+
+ CGEN_INIT_PARSE (cd);
+ cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+ past_opcode_p = 0;
+#endif
+
+ /* We don't check for (*str != '\0') here because we want to parse
+ any trailing fake arguments in the syntax string. */
+ syn = CGEN_SYNTAX_STRING (syntax);
+
+ /* Mnemonics come first for now, ensure valid string. */
+ if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+ abort ();
+
+ ++syn;
+
+ while (* syn != 0)
+ {
+ /* Non operand chars must match exactly. */
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ {
+ /* FIXME: While we allow for non-GAS callers above, we assume the
+ first char after the mnemonic part is a space. */
+ /* FIXME: We also take inappropriate advantage of the fact that
+ GAS's input scrubber will remove extraneous blanks. */
+ if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn)))
+ {
+#ifdef CGEN_MNEMONIC_OPERANDS
+ if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+ past_opcode_p = 1;
+#endif
+ ++ syn;
+ ++ str;
+ }
+ else if (*str)
+ {
+ /* Syntax char didn't match. Can't be this insn. */
+ static char msg [80];
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+ CGEN_SYNTAX_CHAR(*syn), *str);
+ return msg;
+ }
+ else
+ {
+ /* Ran out of input. */
+ static char msg [80];
+ /* xgettext:c-format */
+ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+ CGEN_SYNTAX_CHAR(*syn));
+ return msg;
+ }
+ continue;
+ }
+
+ /* We have an operand of some sort. */
+ errmsg = @arch@_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+ &str, fields);
+ if (errmsg)
+ return errmsg;
+
+ /* Done with this operand, continue with next one. */
+ ++ syn;
+ }
+
+ /* If we're at the end of the syntax string, we're done. */
+ if (* syn == 0)
+ {
+ /* FIXME: For the moment we assume a valid `str' can only contain
+ blanks now. IE: We needn't try again with a longer version of
+ the insn and it is assumed that longer versions of insns appear
+ before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
+ while (isspace (* str))
+ ++ str;
+
+ if (* str != '\0')
+ return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+ return NULL;
+ }
+
+ /* We couldn't parse it. */
+ return _("unrecognized instruction");
+}
+
+/* Main entry point.
+ This routine is called for each instruction to be assembled.
+ STR points to the insn to be assembled.
+ We assume all necessary tables have been initialized.
+ The assembled instruction, less any fixups, is stored in BUF.
+ Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+ still needs to be converted to target byte order, otherwise BUF is an array
+ of bytes in target byte order.
+ The result is a pointer to the insn's entry in the opcode table,
+ or NULL if an error occured (an error message will have already been
+ printed).
+
+ Note that when processing (non-alias) macro-insns,
+ this function recurses.
+
+ ??? It's possible to make this cpu-independent.
+ One would have to deal with a few minor things.
+ At this point in time doing so would be more of a curiosity than useful
+ [for example this file isn't _that_ big], but keeping the possibility in
+ mind helps keep the design clean. */
+
+const CGEN_INSN *
+@arch@_cgen_assemble_insn (cd, str, fields, buf, errmsg)
+ CGEN_CPU_DESC cd;
+ const char *str;
+ CGEN_FIELDS *fields;
+ CGEN_INSN_BYTES_PTR buf;
+ char **errmsg;
+{
+ const char *start;
+ CGEN_INSN_LIST *ilist;
+ const char *parse_errmsg = NULL;
+ const char *insert_errmsg = NULL;
+
+ /* Skip leading white space. */
+ while (isspace (* str))
+ ++ str;
+
+ /* The instructions are stored in hashed lists.
+ Get the first in the list. */
+ ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+ /* Keep looking until we find a match. */
+
+ start = str;
+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+ {
+ const CGEN_INSN *insn = ilist->insn;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* not usually needed as unsupported opcodes shouldn't be in the hash lists */
+ /* Is this insn supported by the selected cpu? */
+ if (! @arch@_cgen_insn_supported (cd, insn))
+ continue;
+#endif
+
+ /* If the RELAX attribute is set, this is an insn that shouldn't be
+ chosen immediately. Instead, it is used during assembler/linker
+ relaxation if possible. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0)
+ continue;
+
+ str = start;
+
+ /* Allow parse/insert handlers to obtain length of insn. */
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+ if (parse_errmsg != NULL)
+ continue;
+
+ /* ??? 0 is passed for `pc' */
+ insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+ (bfd_vma) 0);
+ if (insert_errmsg != NULL)
+ continue;
+
+ /* It is up to the caller to actually output the insn and any
+ queued relocs. */
+ return insn;
+ }
+
+ {
+ static char errbuf[150];
+ const char *tmp_errmsg;
+
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+ /* If requesting verbose error messages, use insert_errmsg.
+ Failing that, use parse_errmsg */
+ tmp_errmsg = (insert_errmsg ? insert_errmsg :
+ parse_errmsg ? parse_errmsg :
+ _("unrecognized instruction"));
+
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+#else
+ if (strlen (start) > 50)
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+ else
+ /* xgettext:c-format */
+ sprintf (errbuf, _("bad instruction `%.50s'"), start);
+#endif
+
+ *errmsg = errbuf;
+ return NULL;
+ }
+}
+
+#if 0 /* This calls back to GAS which we can't do without care. */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+ This lets GAS parse registers for us.
+ ??? Interesting idea but not currently used. */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+ FIXME: Not currently used. */
+
+void
+@arch@_cgen_asm_hash_keywords (cd, opvals)
+ CGEN_CPU_DESC cd;
+ CGEN_KEYWORD *opvals;
+{
+ CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
+ const CGEN_KEYWORD_ENTRY * ke;
+
+ while ((ke = cgen_keyword_search_next (& search)) != NULL)
+ {
+#if 0 /* Unnecessary, should be done in the search routine. */
+ if (! @arch@_cgen_opval_supported (ke))
+ continue;
+#endif
+ cgen_asm_record_register (cd, ke->name, ke->value);
+ }
+}
+
+#endif /* 0 */
diff --git a/contrib/binutils/opcodes/cgen-dis.c b/contrib/binutils/opcodes/cgen-dis.c
index 78b1cd9..b4297bb 100644
--- a/contrib/binutils/opcodes/cgen-dis.c
+++ b/contrib/binutils/opcodes/cgen-dis.c
@@ -1,6 +1,7 @@
/* CGEN generic disassembler support code.
- Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001
+ Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -43,7 +44,7 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf)
CGEN_CPU_DESC cd;
const CGEN_INSN * insns;
int count;
- int entsize;
+ int entsize ATTRIBUTE_UNUSED;
CGEN_INSN_LIST ** htable;
CGEN_INSN_LIST * hentbuf;
{
@@ -64,27 +65,10 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf)
to hash on, so set both up. */
value = CGEN_INSN_BASE_VALUE (insn);
- switch (CGEN_INSN_MASK_BITSIZE (insn))
- {
- case 8:
- buf[0] = value;
- break;
- case 16:
- if (big_p)
- bfd_putb16 ((bfd_vma) value, buf);
- else
- bfd_putl16 ((bfd_vma) value, buf);
- break;
- case 32:
- if (big_p)
- bfd_putb32 ((bfd_vma) value, buf);
- else
- bfd_putl32 ((bfd_vma) value, buf);
- break;
- default:
- abort ();
- }
-
+ bfd_put_bits ((bfd_vma) value,
+ buf,
+ CGEN_INSN_MASK_BITSIZE (insn),
+ big_p);
hash = (* cd->dis_hash) (buf, value);
hentbuf->next = htable[hash];
hentbuf->insn = insn;
@@ -121,27 +105,10 @@ hash_insn_list (cd, insns, htable, hentbuf)
to hash on, so set both up. */
value = CGEN_INSN_BASE_VALUE (ilist->insn);
- switch (CGEN_INSN_MASK_BITSIZE (ilist->insn))
- {
- case 8:
- buf[0] = value;
- break;
- case 16:
- if (big_p)
- bfd_putb16 ((bfd_vma) value, buf);
- else
- bfd_putl16 ((bfd_vma) value, buf);
- break;
- case 32:
- if (big_p)
- bfd_putb32 ((bfd_vma) value, buf);
- else
- bfd_putl32 ((bfd_vma) value, buf);
- break;
- default:
- abort ();
- }
-
+ bfd_put_bits((bfd_vma) value,
+ buf,
+ CGEN_INSN_MASK_BITSIZE (ilist->insn),
+ big_p);
hash = (* cd->dis_hash) (buf, value);
hentbuf->next = htable [hash];
hentbuf->insn = ilist->insn;
diff --git a/contrib/binutils/opcodes/cgen-dis.in b/contrib/binutils/opcodes/cgen-dis.in
new file mode 100644
index 0000000..0e7c35a
--- /dev/null
+++ b/contrib/binutils/opcodes/cgen-dis.in
@@ -0,0 +1,417 @@
+/* Disassembler interface for targets using CGEN. -*- C -*-
+ CGEN: Cpu tools GENerator
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+- the resultant file is machine generated, cgen-dis.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "@prefix@-desc.h"
+#include "@prefix@-opc.h"
+#include "opintl.h"
+
+/* Default text to print if an instruction isn't recognized. */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static void print_normal
+ PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
+static void print_address
+ PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+static void print_keyword
+ PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+static void print_insn_normal
+ PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
+ bfd_vma, int));
+static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
+ disassemble_info *, char *, int));
+static int default_print_insn
+ PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
+
+/* -- disassembler routines inserted here */
+
+/* Default print handler. */
+
+static void
+print_normal (cd, dis_info, value, attrs, pc, length)
+#ifdef CGEN_PRINT_NORMAL
+ CGEN_CPU_DESC cd;
+#else
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+#endif
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+#ifdef CGEN_PRINT_NORMAL
+ bfd_vma pc;
+ int length;
+#else
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
+#endif
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_NORMAL
+ CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
+#endif
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", value);
+}
+
+/* Default address handler. */
+
+static void
+print_address (cd, dis_info, value, attrs, pc, length)
+#ifdef CGEN_PRINT_NORMAL
+ CGEN_CPU_DESC cd;
+#else
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+#endif
+ PTR dis_info;
+ bfd_vma value;
+ unsigned int attrs;
+#ifdef CGEN_PRINT_NORMAL
+ bfd_vma pc;
+ int length;
+#else
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
+#endif
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_ADDRESS
+ CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
+#endif
+
+ /* Print the operand as directed by the attributes. */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+ ; /* nothing to do */
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+ (*info->print_address_func) (value, info);
+ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+ (*info->fprintf_func) (info->stream, "%ld", (long) value);
+ else
+ (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+}
+
+/* Keyword print handler. */
+
+static void
+print_keyword (cd, dis_info, keyword_table, value, attrs)
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+ PTR dis_info;
+ CGEN_KEYWORD *keyword_table;
+ long value;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_KEYWORD_ENTRY *ke;
+
+ ke = cgen_keyword_lookup_value (keyword_table, value);
+ if (ke != NULL)
+ (*info->fprintf_func) (info->stream, "%s", ke->name);
+ else
+ (*info->fprintf_func) (info->stream, "???");
+}
+
+/* Default insn printer.
+
+ DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+ about disassemble_info. */
+
+static void
+print_insn_normal (cd, dis_info, insn, fields, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ const CGEN_INSN *insn;
+ CGEN_FIELDS *fields;
+ bfd_vma pc;
+ int length;
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ disassemble_info *info = (disassemble_info *) dis_info;
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_INIT_PRINT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+ continue;
+ }
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ {
+ (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+ continue;
+ }
+
+ /* We have an operand. */
+ @arch@_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+ fields, CGEN_INSN_ATTRS (insn), pc, length);
+ }
+}
+
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+ the extract info.
+ Returns 0 if all is well, non-zero otherwise. */
+static int
+read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
+ CGEN_CPU_DESC cd;
+ bfd_vma pc;
+ disassemble_info *info;
+ char *buf;
+ int buflen;
+ CGEN_EXTRACT_INFO *ex_info;
+ unsigned long *insn_value;
+{
+ int status = (*info->read_memory_func) (pc, buf, buflen, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ ex_info->dis_info = info;
+ ex_info->valid = (1 << buflen) - 1;
+ ex_info->insn_bytes = buf;
+
+ *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+ return 0;
+}
+
+/* Utility to print an insn.
+ BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+print_insn (cd, pc, info, buf, buflen)
+ CGEN_CPU_DESC cd;
+ bfd_vma pc;
+ disassemble_info *info;
+ char *buf;
+ int buflen;
+{
+ unsigned long insn_value;
+ const CGEN_INSN_LIST *insn_list;
+ CGEN_EXTRACT_INFO ex_info;
+
+ int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value);
+ if (rc != 0)
+ return rc;
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
+ while (insn_list != NULL)
+ {
+ const CGEN_INSN *insn = insn_list->insn;
+ CGEN_FIELDS fields;
+ int length;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+ /* not needed as insn shouldn't be in hash lists if not supported */
+ /* Supported by this cpu? */
+ if (! @arch@_cgen_insn_supported (cd, insn))
+ {
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ continue;
+ }
+#endif
+
+ /* Basic bit mask must be correct. */
+ /* ??? May wish to allow target to defer this check until the extract
+ handler. */
+ if ((insn_value & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
+ {
+ /* Printing is handled in two passes. The first pass parses the
+ machine insn and extracts the fields. The second pass prints
+ them. */
+
+ /* Make sure the entire insn is loaded into insn_value, if it
+ can fit. */
+ if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
+ (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+ {
+ unsigned long full_insn_value;
+ int rc = read_insn (cd, pc, info, buf,
+ CGEN_INSN_BITSIZE (insn) / 8,
+ & ex_info, & full_insn_value);
+ if (rc != 0)
+ return rc;
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, full_insn_value, &fields, pc);
+ }
+ else
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, insn_value, &fields, pc);
+
+ /* length < 0 -> error */
+ if (length < 0)
+ return length;
+ if (length > 0)
+ {
+ CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+ /* length is in bits, result is in bytes */
+ return length / 8;
+ }
+ }
+
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ }
+
+ return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+ The result is the size of the insn in bytes or zero for an unknown insn
+ or -1 if an error occured fetching bytes. */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (cd, pc, info)
+ CGEN_CPU_DESC cd;
+ bfd_vma pc;
+ disassemble_info *info;
+{
+ char buf[CGEN_MAX_INSN_SIZE];
+ int status;
+
+ /* Read the base part of the insn. */
+
+ status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8);
+}
+
+/* Main entry point.
+ Print one instruction from PC on INFO->STREAM.
+ Return the size of the instruction (in bytes). */
+
+int
+print_insn_@arch@ (pc, info)
+ bfd_vma pc;
+ disassemble_info *info;
+{
+ static CGEN_CPU_DESC cd = 0;
+ static int prev_isa;
+ static int prev_mach;
+ static int prev_endian;
+ int length;
+ int isa,mach;
+ int endian = (info->endian == BFD_ENDIAN_BIG
+ ? CGEN_ENDIAN_BIG
+ : CGEN_ENDIAN_LITTLE);
+ enum bfd_architecture arch;
+
+ /* ??? gdb will set mach but leave the architecture as "unknown" */
+#ifndef CGEN_BFD_ARCH
+#define CGEN_BFD_ARCH bfd_arch_@arch@
+#endif
+ arch = info->arch;
+ if (arch == bfd_arch_unknown)
+ arch = CGEN_BFD_ARCH;
+
+ /* There's no standard way to compute the isa number (e.g. for arm thumb)
+ so we leave it to the target. */
+#ifdef CGEN_COMPUTE_ISA
+ isa = CGEN_COMPUTE_ISA (info);
+#else
+ isa = 0;
+#endif
+
+ mach = info->mach;
+
+ /* If we've switched cpu's, close the current table and open a new one. */
+ if (cd
+ && (isa != prev_isa
+ || mach != prev_mach
+ || endian != prev_endian))
+ {
+ @arch@_cgen_cpu_close (cd);
+ cd = 0;
+ }
+
+ /* If we haven't initialized yet, initialize the opcode table. */
+ if (! cd)
+ {
+ const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
+ const char *mach_name;
+
+ if (!arch_type)
+ abort ();
+ mach_name = arch_type->printable_name;
+
+ prev_isa = isa;
+ prev_mach = mach;
+ prev_endian = endian;
+ cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+ CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, prev_endian,
+ CGEN_CPU_OPEN_END);
+ if (!cd)
+ abort ();
+ @arch@_cgen_init_dis (cd);
+ }
+
+ /* We try to have as much common code as possible.
+ But at this point some targets need to take over. */
+ /* ??? Some targets may need a hook elsewhere. Try to avoid this,
+ but if not possible try to move this hook elsewhere rather than
+ have two hooks. */
+ length = CGEN_PRINT_INSN (cd, pc, info);
+ if (length > 0)
+ return length;
+ if (length < 0)
+ return -1;
+
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+ return cd->default_insn_bitsize / 8;
+}
diff --git a/contrib/binutils/opcodes/cgen-ibld.in b/contrib/binutils/opcodes/cgen-ibld.in
new file mode 100644
index 0000000..6921a53
--- /dev/null
+++ b/contrib/binutils/opcodes/cgen-ibld.in
@@ -0,0 +1,514 @@
+/* Instruction building/extraction support for @arch@. -*- C -*-
+
+THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+- the resultant file is machine generated, cgen-ibld.in isn't
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+ Keep that in mind. */
+
+#include "sysdep.h"
+#include <ctype.h>
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "@prefix@-desc.h"
+#include "@prefix@-opc.h"
+#include "opintl.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+ PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+static const char * insert_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *,
+ CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+
+static int extract_normal
+ PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ unsigned int, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, bfd_vma, long *));
+static int extract_insn_normal
+ PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+static void put_insn_int_value
+ PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
+
+
+/* Operand insertion. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal. */
+
+static CGEN_INLINE void
+insert_1 (cd, value, start, length, word_length, bufp)
+ CGEN_CPU_DESC cd;
+ unsigned long value;
+ int start,length,word_length;
+ unsigned char *bufp;
+{
+ unsigned long x,mask;
+ int shift;
+ int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+
+ x = bfd_get_bits (bufp, word_length, big_p);
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+ bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p);
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+ ATTRS is a mask of the boolean attributes.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ The result is an error message or NULL if success. */
+
+/* ??? This duplicates functionality with bfd's howto table and
+ bfd_install_relocation. */
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static const char *
+insert_normal (cd, value, attrs, word_offset, start, length, word_length,
+ total_length, buffer)
+ CGEN_CPU_DESC cd;
+ long value;
+ unsigned int attrs;
+ unsigned int word_offset, start, length, word_length, total_length;
+ CGEN_INSN_BYTES_PTR buffer;
+{
+ static char errbuf[100];
+ /* Written this way to avoid undefined behaviour. */
+ unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value. */
+ if (length == 0)
+ return NULL;
+
+#if 0
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
+#endif
+
+ if (word_length > 32)
+ abort ();
+
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+ }
+
+ /* Ensure VALUE will fit. */
+ if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
+ {
+ unsigned long maxval = mask;
+
+ if ((unsigned long) value > maxval)
+ {
+ /* xgettext:c-format */
+ sprintf (errbuf,
+ _("operand out of range (%lu not between 0 and %lu)"),
+ value, maxval);
+ return errbuf;
+ }
+ }
+ else
+ {
+ if (! cgen_signed_overflow_ok_p (cd))
+ {
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+
+ if (value < minval || value > maxval)
+ {
+ sprintf
+ /* xgettext:c-format */
+ (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+ value, minval, maxval);
+ return errbuf;
+ }
+ }
+ }
+
+#if CGEN_INT_INSN_P
+
+ {
+ int shift;
+
+ if (CGEN_INSN_LSB0_P)
+ shift = (word_offset + start + 1) - length;
+ else
+ shift = total_length - (word_offset + start + length);
+ *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+ }
+
+#else /* ! CGEN_INT_INSN_P */
+
+ {
+ unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+ insert_1 (cd, value, start, length, word_length, bufp);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ return NULL;
+}
+
+/* Default insn builder (insert handler).
+ The instruction is recorded in CGEN_INT_INSN_P byte order
+ (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is
+ recorded in host byte order, otherwise BUFFER is an array of bytes and the
+ value is recorded in target byte order).
+ The result is an error message or NULL if success. */
+
+static const char *
+insert_insn_normal (cd, insn, fields, buffer, pc)
+ CGEN_CPU_DESC cd;
+ const CGEN_INSN * insn;
+ CGEN_FIELDS * fields;
+ CGEN_INSN_BYTES_PTR buffer;
+ bfd_vma pc;
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ unsigned long value;
+ const CGEN_SYNTAX_CHAR_TYPE * syn;
+
+ CGEN_INIT_INSERT (cd);
+ value = CGEN_INSN_BASE_VALUE (insn);
+
+ /* If we're recording insns as numbers (rather than a string of bytes),
+ target byte order handling is deferred until later. */
+
+#if CGEN_INT_INSN_P
+
+ put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
+ CGEN_FIELDS_BITSIZE (fields), value);
+
+#else
+
+ cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize,
+ CGEN_FIELDS_BITSIZE (fields)),
+ value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* ??? It would be better to scan the format's fields.
+ Still need to be able to insert a value based on the operand though;
+ e.g. storing a branch displacement that got resolved later.
+ Needs more thought first. */
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+ {
+ const char *errmsg;
+
+ if (CGEN_SYNTAX_CHAR_P (* syn))
+ continue;
+
+ errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ fields, buffer, pc);
+ if (errmsg)
+ return errmsg;
+ }
+
+ return NULL;
+}
+
+/* Cover function to store an insn value into an integral insn. Must go here
+ because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
+
+static void
+put_insn_int_value (cd, buf, length, insn_length, value)
+ CGEN_CPU_DESC cd;
+ CGEN_INSN_BYTES_PTR buf;
+ int length;
+ int insn_length;
+ CGEN_INSN_INT value;
+{
+ /* For architectures with insns smaller than the base-insn-bitsize,
+ length may be too big. */
+ if (length > insn_length)
+ *buf = value;
+ else
+ {
+ int shift = insn_length - length;
+ /* Written this way to avoid undefined behaviour. */
+ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
+ }
+}
+
+/* Operand extraction. */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+ Ensure sufficient bytes are cached in EX_INFO.
+ OFFSET is the offset in bytes from the start of the insn of the value.
+ BYTES is the length of the needed value.
+ Returns 1 for success, 0 for failure. */
+
+static CGEN_INLINE int
+fill_cache (cd, ex_info, offset, bytes, pc)
+ CGEN_CPU_DESC cd;
+ CGEN_EXTRACT_INFO *ex_info;
+ int offset, bytes;
+ bfd_vma pc;
+{
+ /* It's doubtful that the middle part has already been fetched so
+ we don't optimize that case. kiss. */
+ int mask;
+ disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+ /* First do a quick check. */
+ mask = (1 << bytes) - 1;
+ if (((ex_info->valid >> offset) & mask) == mask)
+ return 1;
+
+ /* Search for the first byte we need to read. */
+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+ if (! (mask & ex_info->valid))
+ break;
+
+ if (bytes)
+ {
+ int status;
+
+ pc += offset;
+ status = (*info->read_memory_func)
+ (pc, ex_info->insn_bytes + offset, bytes, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return 0;
+ }
+
+ ex_info->valid |= ((1 << bytes) - 1) << offset;
+ }
+
+ return 1;
+}
+
+/* Subroutine of extract_normal. */
+
+static CGEN_INLINE long
+extract_1 (cd, ex_info, start, length, word_length, bufp, pc)
+ CGEN_CPU_DESC cd;
+ CGEN_EXTRACT_INFO *ex_info;
+ int start,length,word_length;
+ unsigned char *bufp;
+ bfd_vma pc;
+{
+ unsigned long x;
+ int shift;
+ int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+
+ x = bfd_get_bits (bufp, word_length, big_p);
+
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ return x >> shift;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+ INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
+ or sometimes less for cases like the m32r where the base insn size is 32
+ but some insns are 16 bits.
+ ATTRS is a mask of the boolean attributes. We only need `SIGNED',
+ but for generality we take a bitmask of all of them.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ Returns 1 for success, 0 for failure. */
+
+/* ??? The return code isn't properly used. wip. */
+
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
+
+static int
+extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
+ word_length, total_length, pc, valuep)
+ CGEN_CPU_DESC cd;
+#if ! CGEN_INT_INSN_P
+ CGEN_EXTRACT_INFO *ex_info;
+#else
+ CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
+#endif
+ CGEN_INSN_INT insn_value;
+ unsigned int attrs;
+ unsigned int word_offset, start, length, word_length, total_length;
+#if ! CGEN_INT_INSN_P
+ bfd_vma pc;
+#else
+ bfd_vma pc ATTRIBUTE_UNUSED;
+#endif
+ long *valuep;
+{
+ CGEN_INSN_INT value, mask;
+
+ /* If LENGTH is zero, this operand doesn't contribute to the value
+ so give it a standard value of zero. */
+ if (length == 0)
+ {
+ *valuep = 0;
+ return 1;
+ }
+
+#if 0
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
+#endif
+
+ if (word_length > 32)
+ abort ();
+
+ /* For architectures with insns smaller than the insn-base-bitsize,
+ word_length may be too big. */
+ if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+ {
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+ }
+
+ /* Does the value reside in INSN_VALUE? */
+
+ if (CGEN_INT_INSN_P || word_offset == 0)
+ {
+ if (CGEN_INSN_LSB0_P)
+ value = insn_value >> ((word_offset + start + 1) - length);
+ else
+ value = insn_value >> (total_length - ( word_offset + start + length));
+ }
+
+#if ! CGEN_INT_INSN_P
+
+ else
+ {
+ unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+ if (word_length > 32)
+ abort ();
+
+ if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+ return 0;
+
+ value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ value &= mask;
+ /* sign extend? */
+ if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
+ && (value & (1L << (length - 1))))
+ value |= ~mask;
+
+ *valuep = value;
+
+ return 1;
+}
+
+/* Default insn extractor.
+
+ INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
+ The extracted fields are stored in FIELDS.
+ EX_INFO is used to handle reading variable length insns.
+ Return the length of the insn in bits, or 0 if no match,
+ or -1 if an error occurs fetching data (memory_error_func will have
+ been called). */
+
+static int
+extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc)
+ CGEN_CPU_DESC cd;
+ const CGEN_INSN *insn;
+ CGEN_EXTRACT_INFO *ex_info;
+ CGEN_INSN_INT insn_value;
+ CGEN_FIELDS *fields;
+ bfd_vma pc;
+{
+ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+ const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ CGEN_INIT_EXTRACT (cd);
+
+ for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+ {
+ int length;
+
+ if (CGEN_SYNTAX_CHAR_P (*syn))
+ continue;
+
+ length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+ ex_info, insn_value, fields, pc);
+ if (length <= 0)
+ return length;
+ }
+
+ /* We recognized and successfully extracted this insn. */
+ return CGEN_INSN_BITSIZE (insn);
+}
+
+/* machine generated code added here */
diff --git a/contrib/binutils/opcodes/cgen-opc.c b/contrib/binutils/opcodes/cgen-opc.c
index ede3add..e55482c 100644
--- a/contrib/binutils/opcodes/cgen-opc.c
+++ b/contrib/binutils/opcodes/cgen-opc.c
@@ -1,6 +1,7 @@
/* CGEN generic opcode support.
- Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 1999, 2000, 2001
+ Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -27,6 +28,10 @@
#include "symcat.h"
#include "opcode/cgen.h"
+#ifdef HAVE_ALLOCA_H
+#include <alloca.h>
+#endif
+
static unsigned int hash_keyword_name
PARAMS ((const CGEN_KEYWORD *, const char *, int));
static unsigned int hash_keyword_value
@@ -263,7 +268,7 @@ cgen_hw_lookup_by_name (cd, name)
CGEN_CPU_DESC cd;
const char *name;
{
- int i;
+ unsigned int i;
const CGEN_HW_ENTRY **hw = cd->hw_table.entries;
for (i = 0; i < cd->hw_table.num_entries; ++i)
@@ -281,9 +286,9 @@ cgen_hw_lookup_by_name (cd, name)
const CGEN_HW_ENTRY *
cgen_hw_lookup_by_num (cd, hwnum)
CGEN_CPU_DESC cd;
- int hwnum;
+ unsigned int hwnum;
{
- int i;
+ unsigned int i;
const CGEN_HW_ENTRY **hw = cd->hw_table.entries;
/* ??? This can be speeded up. */
@@ -305,7 +310,7 @@ cgen_operand_lookup_by_name (cd, name)
CGEN_CPU_DESC cd;
const char *name;
{
- int i;
+ unsigned int i;
const CGEN_OPERAND **op = cd->operand_table.entries;
for (i = 0; i < cd->operand_table.num_entries; ++i)
@@ -370,30 +375,7 @@ cgen_get_insn_value (cd, buf, length)
unsigned char *buf;
int length;
{
- CGEN_INSN_INT value;
-
- switch (length)
- {
- case 8:
- value = *buf;
- break;
- case 16:
- if (cd->insn_endian == CGEN_ENDIAN_BIG)
- value = bfd_getb16 (buf);
- else
- value = bfd_getl16 (buf);
- break;
- case 32:
- if (cd->insn_endian == CGEN_ENDIAN_BIG)
- value = bfd_getb32 (buf);
- else
- value = bfd_getl32 (buf);
- break;
- default:
- abort ();
- }
-
- return value;
+ bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG);
}
/* Cover function to store an insn value properly byteswapped. */
@@ -405,26 +387,8 @@ cgen_put_insn_value (cd, buf, length, value)
int length;
CGEN_INSN_INT value;
{
- switch (length)
- {
- case 8:
- buf[0] = value;
- break;
- case 16:
- if (cd->insn_endian == CGEN_ENDIAN_BIG)
- bfd_putb16 (value, buf);
- else
- bfd_putl16 (value, buf);
- break;
- case 32:
- if (cd->insn_endian == CGEN_ENDIAN_BIG)
- bfd_putb32 (value, buf);
- else
- bfd_putl32 (value, buf);
- break;
- default:
- abort ();
- }
+ bfd_put_bits ((bfd_vma) value, buf, length,
+ cd->insn_endian == CGEN_ENDIAN_BIG);
}
/* Look up instruction INSN_*_VALUE and extract its fields.
diff --git a/contrib/binutils/opcodes/cgen.sh b/contrib/binutils/opcodes/cgen.sh
new file mode 100644
index 0000000..a9483bd
--- /dev/null
+++ b/contrib/binutils/opcodes/cgen.sh
@@ -0,0 +1,154 @@
+#! /bin/sh
+# CGEN generic assembler support code.
+#
+# Copyright 2001 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils and GDB, the GNU debugger.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+#
+# Generate CGEN opcode files: arch-desc.[ch], arch-opc.[ch],
+# arch-asm.c, arch-dis.c, arch-opinst.c, arch-ibld.[ch].
+#
+# Usage:
+# cgen.sh action srcdir cgen cgendir cgenflags arch prefix options
+#
+# ACTION is currently always "opcodes". It exists to be consistent with the
+# simulator.
+# OPTIONS is comma separated list of options:
+# - opinst - arch-opinst.c is being made, causes semantic analysis
+#
+# We store the generated files in the source directory until we decide to
+# ship a Scheme interpreter (or other implementation) with gdb/binutils.
+# Maybe we never will.
+
+# We want to behave like make, any error forces us to stop.
+set -e
+
+action=$1
+srcdir=$2
+cgen=$3
+cgendir=$4
+cgenflags=$5
+arch=$6
+prefix=$7
+options=$8
+
+# List of extra files to build.
+# Values: opinst (only 1 extra file at present)
+extrafiles=$9
+
+rootdir=${srcdir}/..
+
+# $arch is $6, as passed on the command line.
+# $ARCH is the same argument but in all uppercase.
+# Both forms are used in this script.
+
+lowercase='abcdefghijklmnopqrstuvwxyz'
+uppercase='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+ARCH=`echo ${arch} | tr "${lowercase}" "${uppercase}"`
+
+extrafile_args=""
+for ef in .. $extrafiles
+do
+ case $ef in
+ ..) ;;
+ opinst) extrafile_args="-Q tmp-opinst.c1 $extrafile_args" ;;
+ esac
+done
+
+case $action in
+opcodes)
+ # Remove residual working files.
+ rm -f tmp-desc.h tmp-desc.h1
+ rm -f tmp-desc.c tmp-desc.c1
+ rm -f tmp-opc.h tmp-opc.h1
+ rm -f tmp-opc.c tmp-opc.c1
+ rm -f tmp-opinst.c tmp-opinst.c1
+ rm -f tmp-ibld.h tmp-ibld.h1
+ rm -f tmp-ibld.c tmp-ibld.in1
+ rm -f tmp-asm.c tmp-asm.in1
+ rm -f tmp-dis.c tmp-dis.in1
+
+ # Run CGEN.
+ ${cgen} -s ${cgendir}/cgen-opc.scm \
+ -s ${cgendir} \
+ ${cgenflags} \
+ -f "${options}" \
+ -m all \
+ -a ${arch} \
+ -H tmp-desc.h1 \
+ -C tmp-desc.c1 \
+ -O tmp-opc.h1 \
+ -P tmp-opc.c1 \
+ -L tmp-ibld.in1 \
+ -A tmp-asm.in1 \
+ -D tmp-dis.in1 \
+ ${extrafile_args}
+
+ # Customise generated files for the particular architecture.
+ sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-desc.h1 > tmp-desc.h
+ ${rootdir}/move-if-change tmp-desc.h ${srcdir}/${prefix}-desc.h
+
+ sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \
+ -e "s/@prefix@/${prefix}/" < tmp-desc.c1 > tmp-desc.c
+ ${rootdir}/move-if-change tmp-desc.c ${srcdir}/${prefix}-desc.c
+
+ sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" < tmp-opc.h1 > tmp-opc.h
+ ${rootdir}/move-if-change tmp-opc.h ${srcdir}/${prefix}-opc.h
+
+ sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \
+ -e "s/@prefix@/${prefix}/" < tmp-opc.c1 > tmp-opc.c
+ ${rootdir}/move-if-change tmp-opc.c ${srcdir}/${prefix}-opc.c
+
+ case $extrafiles in
+ *opinst*)
+ sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \
+ -e "s/@prefix@/${prefix}/" < tmp-opinst.c1 >tmp-opinst.c
+ ${rootdir}/move-if-change tmp-opinst.c ${srcdir}/${prefix}-opinst.c
+ ;;
+ esac
+
+ cat ${srcdir}/cgen-ibld.in tmp-ibld.in1 | \
+ sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \
+ -e "s/@prefix@/${prefix}/" > tmp-ibld.c
+ ${rootdir}/move-if-change tmp-ibld.c ${srcdir}/${prefix}-ibld.c
+
+ sed -e "/ -- assembler routines/ r tmp-asm.in1" ${srcdir}/cgen-asm.in \
+ | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \
+ -e "s/@prefix@/${prefix}/" > tmp-asm.c
+ ${rootdir}/move-if-change tmp-asm.c ${srcdir}/${prefix}-asm.c
+
+ sed -e "/ -- disassembler routines/ r tmp-dis.in1" ${srcdir}/cgen-dis.in \
+ | sed -e "s/@ARCH@/${ARCH}/g" -e "s/@arch@/${arch}/g" \
+ -e "s/@prefix@/${prefix}/" > tmp-dis.c
+ ${rootdir}/move-if-change tmp-dis.c ${srcdir}/${prefix}-dis.c
+
+ # Remove temporary files.
+ rm -f tmp-desc.h1 tmp-desc.c1
+ rm -f tmp-opc.h1 tmp-opc.c1
+ rm -f tmp-opinst.c1
+ rm -f tmp-ibld.h1 tmp-ibld.in1
+ rm -f tmp-asm.in1 tmp-dis.in1
+ ;;
+
+*)
+ echo "$0: bad action: ${action}" >&2
+ exit 1
+ ;;
+
+esac
+
+exit 0
diff --git a/contrib/binutils/opcodes/i386-dis.c b/contrib/binutils/opcodes/i386-dis.c
index 5621d8a..3eb40c6 100644
--- a/contrib/binutils/opcodes/i386-dis.c
+++ b/contrib/binutils/opcodes/i386-dis.c
@@ -50,9 +50,53 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#endif
static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));
+static void ckprefix PARAMS ((void));
+static const char *prefix_name PARAMS ((int, int));
+static int print_insn_i386 PARAMS ((bfd_vma, disassemble_info *));
+static void dofloat PARAMS ((int));
+static void OP_ST PARAMS ((int, int));
+static void OP_STi PARAMS ((int, int));
+static int putop PARAMS ((const char *, int));
+static void oappend PARAMS ((const char *));
+static void append_seg PARAMS ((void));
+static void OP_indirE PARAMS ((int, int));
+static void print_operand_value PARAMS ((char *, int, bfd_vma));
+static void OP_E PARAMS ((int, int));
+static void OP_G PARAMS ((int, int));
+static bfd_vma get64 PARAMS ((void));
+static bfd_signed_vma get32 PARAMS ((void));
+static bfd_signed_vma get32s PARAMS ((void));
+static int get16 PARAMS ((void));
+static void set_op PARAMS ((bfd_vma, int));
+static void OP_REG PARAMS ((int, int));
+static void OP_IMREG PARAMS ((int, int));
+static void OP_I PARAMS ((int, int));
+static void OP_I64 PARAMS ((int, int));
+static void OP_sI PARAMS ((int, int));
+static void OP_J PARAMS ((int, int));
+static void OP_SEG PARAMS ((int, int));
+static void OP_DIR PARAMS ((int, int));
+static void OP_OFF PARAMS ((int, int));
+static void OP_OFF64 PARAMS ((int, int));
+static void ptr_reg PARAMS ((int, int));
+static void OP_ESreg PARAMS ((int, int));
+static void OP_DSreg PARAMS ((int, int));
+static void OP_C PARAMS ((int, int));
+static void OP_D PARAMS ((int, int));
+static void OP_T PARAMS ((int, int));
+static void OP_Rd PARAMS ((int, int));
+static void OP_MMX PARAMS ((int, int));
+static void OP_XMM PARAMS ((int, int));
+static void OP_EM PARAMS ((int, int));
+static void OP_EX PARAMS ((int, int));
+static void OP_MS PARAMS ((int, int));
+static void OP_XS PARAMS ((int, int));
+static void OP_3DNowSuffix PARAMS ((int, int));
+static void OP_SIMD_Suffix PARAMS ((int, int));
+static void SIMD_Fixup PARAMS ((int, int));
+static void BadOp PARAMS ((void));
-struct dis_private
-{
+struct dis_private {
/* Points to first byte not fetched. */
bfd_byte *max_fetched;
bfd_byte the_buffer[MAXLEN];
@@ -112,7 +156,7 @@ static int used_prefixes;
to ADDR (exclusive) are valid. Returns 1 for success, longjmps
on error. */
#define FETCH_DATA(info, addr) \
- ((addr) <= ((struct dis_private *)(info->private_data))->max_fetched \
+ ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
? 1 : fetch_data ((info), (addr)))
static int
@@ -121,7 +165,7 @@ fetch_data (info, addr)
bfd_byte *addr;
{
int status;
- struct dis_private *priv = (struct dis_private *)info->private_data;
+ struct dis_private *priv = (struct dis_private *) info->private_data;
bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
status = (*info->read_memory_func) (start,
@@ -152,7 +196,7 @@ fetch_data (info, addr)
#define indirEv OP_indirE, v_mode
#define Ew OP_E, w_mode
#define Ma OP_E, v_mode
-#define M OP_E, 0 /* lea */
+#define M OP_E, 0 /* lea, lgdt, etc. */
#define Mp OP_E, 0 /* 32 or 48 bit memory operand for LDS, LES etc */
#define Gb OP_G, b_mode
#define Gv OP_G, v_mode
@@ -254,60 +298,12 @@ fetch_data (info, addr)
#define loop_jcxz_flag NULL, loop_jcxz_mode
/* bits in sizeflag */
-#if 0 /* leave undefined until someone adds the extra flag to objdump */
+#if 0 /* Leave undefined until someone adds the extra flag to objdump. */
#define SUFFIX_ALWAYS 4
#endif
#define AFLAG 2
#define DFLAG 1
-typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag));
-
-static void OP_E PARAMS ((int, int));
-static void OP_G PARAMS ((int, int));
-static void OP_I PARAMS ((int, int));
-static void OP_I64 PARAMS ((int, int));
-static void OP_OFF PARAMS ((int, int));
-static void OP_REG PARAMS ((int, int));
-static void OP_IMREG PARAMS ((int, int));
-static void OP_OFF64 PARAMS ((int, int));
-static void OP_indirE PARAMS ((int, int));
-static void OP_sI PARAMS ((int, int));
-static void OP_REG PARAMS ((int, int));
-static void OP_J PARAMS ((int, int));
-static void OP_DIR PARAMS ((int, int));
-static void OP_OFF PARAMS ((int, int));
-static void OP_ESreg PARAMS ((int, int));
-static void OP_DSreg PARAMS ((int, int));
-static void OP_SEG PARAMS ((int, int));
-static void OP_C PARAMS ((int, int));
-static void OP_D PARAMS ((int, int));
-static void OP_T PARAMS ((int, int));
-static void OP_Rd PARAMS ((int, int));
-static void OP_ST PARAMS ((int, int));
-static void OP_STi PARAMS ((int, int));
-static void OP_MMX PARAMS ((int, int));
-static void OP_XMM PARAMS ((int, int));
-static void OP_EM PARAMS ((int, int));
-static void OP_EX PARAMS ((int, int));
-static void OP_MS PARAMS ((int, int));
-static void OP_XS PARAMS ((int, int));
-static void OP_3DNowSuffix PARAMS ((int, int));
-static void OP_SIMD_Suffix PARAMS ((int, int));
-static void SIMD_Fixup PARAMS ((int, int));
-
-static void append_seg PARAMS ((void));
-static void set_op PARAMS ((unsigned int op, int));
-static void putop PARAMS ((const char *template, int sizeflag));
-static void dofloat PARAMS ((int sizeflag));
-static int get16 PARAMS ((void));
-static bfd_vma get64 PARAMS ((void));
-static bfd_signed_vma get32 PARAMS ((void));
-static bfd_signed_vma get32s PARAMS ((void));
-static void ckprefix PARAMS ((void));
-static const char *prefix_name PARAMS ((int, int));
-static void ptr_reg PARAMS ((int, int));
-static void BadOp PARAMS ((void));
-
#define b_mode 1 /* byte operand */
#define v_mode 2 /* operand size depends on prefixes */
#define w_mode 3 /* word operand */
@@ -363,63 +359,68 @@ static void BadOp PARAMS ((void));
#define indir_dx_reg 150
-#define USE_GROUPS 1
-#define USE_PREFIX_USER_TABLE 2
-
-#define GRP1b NULL, NULL, 0, NULL, USE_GROUPS, NULL, 0
-#define GRP1S NULL, NULL, 1, NULL, USE_GROUPS, NULL, 0
-#define GRP1Ss NULL, NULL, 2, NULL, USE_GROUPS, NULL, 0
-#define GRP2b NULL, NULL, 3, NULL, USE_GROUPS, NULL, 0
-#define GRP2S NULL, NULL, 4, NULL, USE_GROUPS, NULL, 0
-#define GRP2b_one NULL, NULL, 5, NULL, USE_GROUPS, NULL, 0
-#define GRP2S_one NULL, NULL, 6, NULL, USE_GROUPS, NULL, 0
-#define GRP2b_cl NULL, NULL, 7, NULL, USE_GROUPS, NULL, 0
-#define GRP2S_cl NULL, NULL, 8, NULL, USE_GROUPS, NULL, 0
-#define GRP3b NULL, NULL, 9, NULL, USE_GROUPS, NULL, 0
-#define GRP3S NULL, NULL, 10, NULL, USE_GROUPS, NULL, 0
-#define GRP4 NULL, NULL, 11, NULL, USE_GROUPS, NULL, 0
-#define GRP5 NULL, NULL, 12, NULL, USE_GROUPS, NULL, 0
-#define GRP6 NULL, NULL, 13, NULL, USE_GROUPS, NULL, 0
-#define GRP7 NULL, NULL, 14, NULL, USE_GROUPS, NULL, 0
-#define GRP8 NULL, NULL, 15, NULL, USE_GROUPS, NULL, 0
-#define GRP9 NULL, NULL, 16, NULL, USE_GROUPS, NULL, 0
-#define GRP10 NULL, NULL, 17, NULL, USE_GROUPS, NULL, 0
-#define GRP11 NULL, NULL, 18, NULL, USE_GROUPS, NULL, 0
-#define GRP12 NULL, NULL, 19, NULL, USE_GROUPS, NULL, 0
-#define GRP13 NULL, NULL, 20, NULL, USE_GROUPS, NULL, 0
-#define GRP14 NULL, NULL, 21, NULL, USE_GROUPS, NULL, 0
-#define GRPAMD NULL, NULL, 22, NULL, USE_GROUPS, NULL, 0
-
-#define PREGRP0 NULL, NULL, 0, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP1 NULL, NULL, 1, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP2 NULL, NULL, 2, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP3 NULL, NULL, 3, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP4 NULL, NULL, 4, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP5 NULL, NULL, 5, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP6 NULL, NULL, 6, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP7 NULL, NULL, 7, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP8 NULL, NULL, 8, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP9 NULL, NULL, 9, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP10 NULL, NULL, 10, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP11 NULL, NULL, 11, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP12 NULL, NULL, 12, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP13 NULL, NULL, 13, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP14 NULL, NULL, 14, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP15 NULL, NULL, 15, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP16 NULL, NULL, 16, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP17 NULL, NULL, 17, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP18 NULL, NULL, 18, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP19 NULL, NULL, 19, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP20 NULL, NULL, 20, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP21 NULL, NULL, 21, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP22 NULL, NULL, 22, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP23 NULL, NULL, 23, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP24 NULL, NULL, 24, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP25 NULL, NULL, 25, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-#define PREGRP26 NULL, NULL, 26, NULL, USE_PREFIX_USER_TABLE, NULL, 0
-
-#define FLOATCODE 50
-#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0
+#define FLOATCODE 1
+#define USE_GROUPS 2
+#define USE_PREFIX_USER_TABLE 3
+#define X86_64_SPECIAL 4
+
+#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0
+
+#define GRP1b NULL, NULL, USE_GROUPS, NULL, 0, NULL, 0
+#define GRP1S NULL, NULL, USE_GROUPS, NULL, 1, NULL, 0
+#define GRP1Ss NULL, NULL, USE_GROUPS, NULL, 2, NULL, 0
+#define GRP2b NULL, NULL, USE_GROUPS, NULL, 3, NULL, 0
+#define GRP2S NULL, NULL, USE_GROUPS, NULL, 4, NULL, 0
+#define GRP2b_one NULL, NULL, USE_GROUPS, NULL, 5, NULL, 0
+#define GRP2S_one NULL, NULL, USE_GROUPS, NULL, 6, NULL, 0
+#define GRP2b_cl NULL, NULL, USE_GROUPS, NULL, 7, NULL, 0
+#define GRP2S_cl NULL, NULL, USE_GROUPS, NULL, 8, NULL, 0
+#define GRP3b NULL, NULL, USE_GROUPS, NULL, 9, NULL, 0
+#define GRP3S NULL, NULL, USE_GROUPS, NULL, 10, NULL, 0
+#define GRP4 NULL, NULL, USE_GROUPS, NULL, 11, NULL, 0
+#define GRP5 NULL, NULL, USE_GROUPS, NULL, 12, NULL, 0
+#define GRP6 NULL, NULL, USE_GROUPS, NULL, 13, NULL, 0
+#define GRP7 NULL, NULL, USE_GROUPS, NULL, 14, NULL, 0
+#define GRP8 NULL, NULL, USE_GROUPS, NULL, 15, NULL, 0
+#define GRP9 NULL, NULL, USE_GROUPS, NULL, 16, NULL, 0
+#define GRP10 NULL, NULL, USE_GROUPS, NULL, 17, NULL, 0
+#define GRP11 NULL, NULL, USE_GROUPS, NULL, 18, NULL, 0
+#define GRP12 NULL, NULL, USE_GROUPS, NULL, 19, NULL, 0
+#define GRP13 NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0
+#define GRP14 NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0
+#define GRPAMD NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0
+
+#define PREGRP0 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 0, NULL, 0
+#define PREGRP1 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 1, NULL, 0
+#define PREGRP2 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 2, NULL, 0
+#define PREGRP3 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 3, NULL, 0
+#define PREGRP4 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 4, NULL, 0
+#define PREGRP5 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 5, NULL, 0
+#define PREGRP6 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 6, NULL, 0
+#define PREGRP7 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 7, NULL, 0
+#define PREGRP8 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 8, NULL, 0
+#define PREGRP9 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 9, NULL, 0
+#define PREGRP10 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 10, NULL, 0
+#define PREGRP11 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 11, NULL, 0
+#define PREGRP12 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 12, NULL, 0
+#define PREGRP13 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 13, NULL, 0
+#define PREGRP14 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 14, NULL, 0
+#define PREGRP15 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 15, NULL, 0
+#define PREGRP16 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 16, NULL, 0
+#define PREGRP17 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 17, NULL, 0
+#define PREGRP18 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 18, NULL, 0
+#define PREGRP19 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 19, NULL, 0
+#define PREGRP20 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 20, NULL, 0
+#define PREGRP21 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 21, NULL, 0
+#define PREGRP22 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 22, NULL, 0
+#define PREGRP23 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 23, NULL, 0
+#define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0
+#define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0
+#define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0
+
+#define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0
+
+typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag));
struct dis386 {
const char *name;
@@ -436,1145 +437,276 @@ struct dis386 {
'B' => print 'b' if suffix_always is true
'E' => print 'e' if 32-bit form of jcxz
'F' => print 'w' or 'l' depending on address size prefix (loop insns)
+ 'H' => print ",pt" or ",pn" branch hint
'L' => print 'l' if suffix_always is true
'N' => print 'n' if instruction has no wait "prefix"
'O' => print 'd', or 'o'
'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
or suffix_always is true
print 'q' if rex prefix is present.
- 'I' => print 'q' in 64bit mode and behave as 'P' otherwise
'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always is true
'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode)
'S' => print 'w', 'l' or 'q' if suffix_always is true
- 'T' => print 'q' in 64bit mode and behave as 'I' otherwise
+ 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
+ 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
'X' => print 's', 'd' depending on data16 prefix (for XMM)
'W' => print 'b' or 'w' ("w" or "de" in intel mode)
'Y' => 'q' if instruction has an REX 64bit overwrite prefix
-*/
-
-static const struct dis386 dis386_att[] = {
- /* 00 */
- { "addB", Eb, Gb, XX },
- { "addS", Ev, Gv, XX },
- { "addB", Gb, Eb, XX },
- { "addS", Gv, Ev, XX },
- { "addB", AL, Ib, XX },
- { "addS", eAX, Iv, XX },
- { "pushI", es, XX, XX },
- { "popI", es, XX, XX },
- /* 08 */
- { "orB", Eb, Gb, XX },
- { "orS", Ev, Gv, XX },
- { "orB", Gb, Eb, XX },
- { "orS", Gv, Ev, XX },
- { "orB", AL, Ib, XX },
- { "orS", eAX, Iv, XX },
- { "pushI", cs, XX, XX },
- { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
- /* 10 */
- { "adcB", Eb, Gb, XX },
- { "adcS", Ev, Gv, XX },
- { "adcB", Gb, Eb, XX },
- { "adcS", Gv, Ev, XX },
- { "adcB", AL, Ib, XX },
- { "adcS", eAX, Iv, XX },
- { "pushI", ss, XX, XX },
- { "popI", ss, XX, XX },
- /* 18 */
- { "sbbB", Eb, Gb, XX },
- { "sbbS", Ev, Gv, XX },
- { "sbbB", Gb, Eb, XX },
- { "sbbS", Gv, Ev, XX },
- { "sbbB", AL, Ib, XX },
- { "sbbS", eAX, Iv, XX },
- { "pushI", ds, XX, XX },
- { "popI", ds, XX, XX },
- /* 20 */
- { "andB", Eb, Gb, XX },
- { "andS", Ev, Gv, XX },
- { "andB", Gb, Eb, XX },
- { "andS", Gv, Ev, XX },
- { "andB", AL, Ib, XX },
- { "andS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG ES prefix */
- { "daa", XX, XX, XX },
- /* 28 */
- { "subB", Eb, Gb, XX },
- { "subS", Ev, Gv, XX },
- { "subB", Gb, Eb, XX },
- { "subS", Gv, Ev, XX },
- { "subB", AL, Ib, XX },
- { "subS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG CS prefix */
- { "das", XX, XX, XX },
- /* 30 */
- { "xorB", Eb, Gb, XX },
- { "xorS", Ev, Gv, XX },
- { "xorB", Gb, Eb, XX },
- { "xorS", Gv, Ev, XX },
- { "xorB", AL, Ib, XX },
- { "xorS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG SS prefix */
- { "aaa", XX, XX, XX },
- /* 38 */
- { "cmpB", Eb, Gb, XX },
- { "cmpS", Ev, Gv, XX },
- { "cmpB", Gb, Eb, XX },
- { "cmpS", Gv, Ev, XX },
- { "cmpB", AL, Ib, XX },
- { "cmpS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG DS prefix */
- { "aas", XX, XX, XX },
- /* 40 */
- { "incS", RMeAX, XX, XX },
- { "incS", RMeCX, XX, XX },
- { "incS", RMeDX, XX, XX },
- { "incS", RMeBX, XX, XX },
- { "incS", RMeSP, XX, XX },
- { "incS", RMeBP, XX, XX },
- { "incS", RMeSI, XX, XX },
- { "incS", RMeDI, XX, XX },
- /* 48 */
- { "decS", RMeAX, XX, XX },
- { "decS", RMeCX, XX, XX },
- { "decS", RMeDX, XX, XX },
- { "decS", RMeBX, XX, XX },
- { "decS", RMeSP, XX, XX },
- { "decS", RMeBP, XX, XX },
- { "decS", RMeSI, XX, XX },
- { "decS", RMeDI, XX, XX },
- /* 50 */
- { "pushS", RMeAX, XX, XX },
- { "pushS", RMeCX, XX, XX },
- { "pushS", RMeDX, XX, XX },
- { "pushS", RMeBX, XX, XX },
- { "pushS", RMeSP, XX, XX },
- { "pushS", RMeBP, XX, XX },
- { "pushS", RMeSI, XX, XX },
- { "pushS", RMeDI, XX, XX },
- /* 58 */
- { "popS", RMeAX, XX, XX },
- { "popS", RMeCX, XX, XX },
- { "popS", RMeDX, XX, XX },
- { "popS", RMeBX, XX, XX },
- { "popS", RMeSP, XX, XX },
- { "popS", RMeBP, XX, XX },
- { "popS", RMeSI, XX, XX },
- { "popS", RMeDI, XX, XX },
- /* 60 */
- { "pushaP", XX, XX, XX },
- { "popaP", XX, XX, XX },
- { "boundS", Gv, Ma, XX },
- { "arpl", Ew, Gw, XX },
- { "(bad)", XX, XX, XX }, /* seg fs */
- { "(bad)", XX, XX, XX }, /* seg gs */
- { "(bad)", XX, XX, XX }, /* op size prefix */
- { "(bad)", XX, XX, XX }, /* adr size prefix */
- /* 68 */
- { "pushI", Iv, XX, XX }, /* 386 book wrong */
- { "imulS", Gv, Ev, Iv },
- { "pushI", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */
- { "imulS", Gv, Ev, sIb },
- { "insb", Yb, indirDX, XX },
- { "insR", Yv, indirDX, XX },
- { "outsb", indirDX, Xb, XX },
- { "outsR", indirDX, Xv, XX },
- /* 70 */
- { "jo", Jb, cond_jump_flag, XX },
- { "jno", Jb, cond_jump_flag, XX },
- { "jb", Jb, cond_jump_flag, XX },
- { "jae", Jb, cond_jump_flag, XX },
- { "je", Jb, cond_jump_flag, XX },
- { "jne", Jb, cond_jump_flag, XX },
- { "jbe", Jb, cond_jump_flag, XX },
- { "ja", Jb, cond_jump_flag, XX },
- /* 78 */
- { "js", Jb, cond_jump_flag, XX },
- { "jns", Jb, cond_jump_flag, XX },
- { "jp", Jb, cond_jump_flag, XX },
- { "jnp", Jb, cond_jump_flag, XX },
- { "jl", Jb, cond_jump_flag, XX },
- { "jge", Jb, cond_jump_flag, XX },
- { "jle", Jb, cond_jump_flag, XX },
- { "jg", Jb, cond_jump_flag, XX },
- /* 80 */
- { GRP1b },
- { GRP1S },
- { "(bad)", XX, XX, XX },
- { GRP1Ss },
- { "testB", Eb, Gb, XX },
- { "testS", Ev, Gv, XX },
- { "xchgB", Eb, Gb, XX },
- { "xchgS", Ev, Gv, XX },
- /* 88 */
- { "movB", Eb, Gb, XX },
- { "movS", Ev, Gv, XX },
- { "movB", Gb, Eb, XX },
- { "movS", Gv, Ev, XX },
- { "movQ", Ev, Sw, XX },
- { "leaS", Gv, M, XX },
- { "movQ", Sw, Ev, XX },
- { "popT", Ev, XX, XX },
- /* 90 */
- { "nop", XX, XX, XX },
- /* FIXME: NOP with REPz prefix is called PAUSE. */
- { "xchgS", RMeCX, eAX, XX },
- { "xchgS", RMeDX, eAX, XX },
- { "xchgS", RMeBX, eAX, XX },
- { "xchgS", RMeSP, eAX, XX },
- { "xchgS", RMeBP, eAX, XX },
- { "xchgS", RMeSI, eAX, XX },
- { "xchgS", RMeDI, eAX, XX },
- /* 98 */
- { "cWtR", XX, XX, XX },
- { "cRtO", XX, XX, XX },
- { "lcallI", Ap, XX, XX },
- { "(bad)", XX, XX, XX }, /* fwait */
- { "pushfI", XX, XX, XX },
- { "popfI", XX, XX, XX },
- { "sahf", XX, XX, XX },
- { "lahf", XX, XX, XX },
- /* a0 */
- { "movB", AL, Ob, XX },
- { "movS", eAX, Ov, XX },
- { "movB", Ob, AL, XX },
- { "movS", Ov, eAX, XX },
- { "movsb", Yb, Xb, XX },
- { "movsR", Yv, Xv, XX },
- { "cmpsb", Xb, Yb, XX },
- { "cmpsR", Xv, Yv, XX },
- /* a8 */
- { "testB", AL, Ib, XX },
- { "testS", eAX, Iv, XX },
- { "stosB", Yb, AL, XX },
- { "stosS", Yv, eAX, XX },
- { "lodsB", AL, Xb, XX },
- { "lodsS", eAX, Xv, XX },
- { "scasB", AL, Yb, XX },
- { "scasS", eAX, Yv, XX },
- /* b0 */
- { "movB", RMAL, Ib, XX },
- { "movB", RMCL, Ib, XX },
- { "movB", RMDL, Ib, XX },
- { "movB", RMBL, Ib, XX },
- { "movB", RMAH, Ib, XX },
- { "movB", RMCH, Ib, XX },
- { "movB", RMDH, Ib, XX },
- { "movB", RMBH, Ib, XX },
- /* b8 */
- { "movS", RMeAX, Iv, XX },
- { "movS", RMeCX, Iv, XX },
- { "movS", RMeDX, Iv, XX },
- { "movS", RMeBX, Iv, XX },
- { "movS", RMeSP, Iv, XX },
- { "movS", RMeBP, Iv, XX },
- { "movS", RMeSI, Iv, XX },
- { "movS", RMeDI, Iv, XX },
- /* c0 */
- { GRP2b },
- { GRP2S },
- { "retI", Iw, XX, XX },
- { "retI", XX, XX, XX },
- { "lesS", Gv, Mp, XX },
- { "ldsS", Gv, Mp, XX },
- { "movA", Eb, Ib, XX },
- { "movQ", Ev, Iv, XX },
- /* c8 */
- { "enterI", Iw, Ib, XX },
- { "leaveI", XX, XX, XX },
- { "lretP", Iw, XX, XX },
- { "lretP", XX, XX, XX },
- { "int3", XX, XX, XX },
- { "int", Ib, XX, XX },
- { "into", XX, XX, XX},
- { "iretP", XX, XX, XX },
- /* d0 */
- { GRP2b_one },
- { GRP2S_one },
- { GRP2b_cl },
- { GRP2S_cl },
- { "aam", sIb, XX, XX },
- { "aad", sIb, XX, XX },
- { "(bad)", XX, XX, XX },
- { "xlat", DSBX, XX, XX },
- /* d8 */
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- /* e0 */
- { "loopneF", Jb, loop_jcxz_flag, XX },
- { "loopeF", Jb, loop_jcxz_flag, XX },
- { "loopF", Jb, loop_jcxz_flag, XX },
- { "jEcxz", Jb, loop_jcxz_flag, XX },
- { "inB", AL, Ib, XX },
- { "inS", eAX, Ib, XX },
- { "outB", Ib, AL, XX },
- { "outS", Ib, eAX, XX },
- /* e8 */
- { "callI", Jv, XX, XX },
- { "jmpI", Jv, XX, XX },
- { "ljmpI", Ap, XX, XX },
- { "jmp", Jb, XX, XX },
- { "inB", AL, indirDX, XX },
- { "inS", eAX, indirDX, XX },
- { "outB", indirDX, AL, XX },
- { "outS", indirDX, eAX, XX },
- /* f0 */
- { "(bad)", XX, XX, XX }, /* lock prefix */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX }, /* repne */
- { "(bad)", XX, XX, XX }, /* repz */
- { "hlt", XX, XX, XX },
- { "cmc", XX, XX, XX },
- { GRP3b },
- { GRP3S },
- /* f8 */
- { "clc", XX, XX, XX },
- { "stc", XX, XX, XX },
- { "cli", XX, XX, XX },
- { "sti", XX, XX, XX },
- { "cld", XX, XX, XX },
- { "std", XX, XX, XX },
- { GRP4 },
- { GRP5 },
-};
-static const struct dis386 dis386_intel[] = {
- /* 00 */
- { "add", Eb, Gb, XX },
- { "add", Ev, Gv, XX },
- { "add", Gb, Eb, XX },
- { "add", Gv, Ev, XX },
- { "add", AL, Ib, XX },
- { "add", eAX, Iv, XX },
- { "push", es, XX, XX },
- { "pop", es, XX, XX },
- /* 08 */
- { "or", Eb, Gb, XX },
- { "or", Ev, Gv, XX },
- { "or", Gb, Eb, XX },
- { "or", Gv, Ev, XX },
- { "or", AL, Ib, XX },
- { "or", eAX, Iv, XX },
- { "push", cs, XX, XX },
- { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
- /* 10 */
- { "adc", Eb, Gb, XX },
- { "adc", Ev, Gv, XX },
- { "adc", Gb, Eb, XX },
- { "adc", Gv, Ev, XX },
- { "adc", AL, Ib, XX },
- { "adc", eAX, Iv, XX },
- { "push", ss, XX, XX },
- { "pop", ss, XX, XX },
- /* 18 */
- { "sbb", Eb, Gb, XX },
- { "sbb", Ev, Gv, XX },
- { "sbb", Gb, Eb, XX },
- { "sbb", Gv, Ev, XX },
- { "sbb", AL, Ib, XX },
- { "sbb", eAX, Iv, XX },
- { "push", ds, XX, XX },
- { "pop", ds, XX, XX },
- /* 20 */
- { "and", Eb, Gb, XX },
- { "and", Ev, Gv, XX },
- { "and", Gb, Eb, XX },
- { "and", Gv, Ev, XX },
- { "and", AL, Ib, XX },
- { "and", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG ES prefix */
- { "daa", XX, XX, XX },
- /* 28 */
- { "sub", Eb, Gb, XX },
- { "sub", Ev, Gv, XX },
- { "sub", Gb, Eb, XX },
- { "sub", Gv, Ev, XX },
- { "sub", AL, Ib, XX },
- { "sub", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG CS prefix */
- { "das", XX, XX, XX },
- /* 30 */
- { "xor", Eb, Gb, XX },
- { "xor", Ev, Gv, XX },
- { "xor", Gb, Eb, XX },
- { "xor", Gv, Ev, XX },
- { "xor", AL, Ib, XX },
- { "xor", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG SS prefix */
- { "aaa", XX, XX, XX },
- /* 38 */
- { "cmp", Eb, Gb, XX },
- { "cmp", Ev, Gv, XX },
- { "cmp", Gb, Eb, XX },
- { "cmp", Gv, Ev, XX },
- { "cmp", AL, Ib, XX },
- { "cmp", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG DS prefix */
- { "aas", XX, XX, XX },
- /* 40 */
- { "inc", RMeAX, XX, XX },
- { "inc", RMeCX, XX, XX },
- { "inc", RMeDX, XX, XX },
- { "inc", RMeBX, XX, XX },
- { "inc", RMeSP, XX, XX },
- { "inc", RMeBP, XX, XX },
- { "inc", RMeSI, XX, XX },
- { "inc", RMeDI, XX, XX },
- /* 48 */
- { "dec", RMeAX, XX, XX },
- { "dec", RMeCX, XX, XX },
- { "dec", RMeDX, XX, XX },
- { "dec", RMeBX, XX, XX },
- { "dec", RMeSP, XX, XX },
- { "dec", RMeBP, XX, XX },
- { "dec", RMeSI, XX, XX },
- { "dec", RMeDI, XX, XX },
- /* 50 */
- { "push", RMeAX, XX, XX },
- { "push", RMeCX, XX, XX },
- { "push", RMeDX, XX, XX },
- { "push", RMeBX, XX, XX },
- { "push", RMeSP, XX, XX },
- { "push", RMeBP, XX, XX },
- { "push", RMeSI, XX, XX },
- { "push", RMeDI, XX, XX },
- /* 58 */
- { "pop", RMeAX, XX, XX },
- { "pop", RMeCX, XX, XX },
- { "pop", RMeDX, XX, XX },
- { "pop", RMeBX, XX, XX },
- { "pop", RMeSP, XX, XX },
- { "pop", RMeBP, XX, XX },
- { "pop", RMeSI, XX, XX },
- { "pop", RMeDI, XX, XX },
- /* 60 */
- { "pusha", XX, XX, XX },
- { "popa", XX, XX, XX },
- { "bound", Gv, Ma, XX },
- { "arpl", Ew, Gw, XX },
- { "(bad)", XX, XX, XX }, /* seg fs */
- { "(bad)", XX, XX, XX }, /* seg gs */
- { "(bad)", XX, XX, XX }, /* op size prefix */
- { "(bad)", XX, XX, XX }, /* adr size prefix */
- /* 68 */
- { "push", Iv, XX, XX }, /* 386 book wrong */
- { "imul", Gv, Ev, Iv },
- { "push", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */
- { "imul", Gv, Ev, sIb },
- { "ins", Yb, indirDX, XX },
- { "ins", Yv, indirDX, XX },
- { "outs", indirDX, Xb, XX },
- { "outs", indirDX, Xv, XX },
- /* 70 */
- { "jo", Jb, XX, XX },
- { "jno", Jb, XX, XX },
- { "jb", Jb, XX, XX },
- { "jae", Jb, XX, XX },
- { "je", Jb, XX, XX },
- { "jne", Jb, XX, XX },
- { "jbe", Jb, XX, XX },
- { "ja", Jb, XX, XX },
- /* 78 */
- { "js", Jb, XX, XX },
- { "jns", Jb, XX, XX },
- { "jp", Jb, XX, XX },
- { "jnp", Jb, XX, XX },
- { "jl", Jb, XX, XX },
- { "jge", Jb, XX, XX },
- { "jle", Jb, XX, XX },
- { "jg", Jb, XX, XX },
- /* 80 */
- { GRP1b },
- { GRP1S },
- { "(bad)", XX, XX, XX },
- { GRP1Ss },
- { "test", Eb, Gb, XX },
- { "test", Ev, Gv, XX },
- { "xchg", Eb, Gb, XX },
- { "xchg", Ev, Gv, XX },
- /* 88 */
- { "mov", Eb, Gb, XX },
- { "mov", Ev, Gv, XX },
- { "mov", Gb, Eb, XX },
- { "mov", Gv, Ev, XX },
- { "mov", Ev, Sw, XX },
- { "lea", Gv, M, XX },
- { "mov", Sw, Ev, XX },
- { "pop", Ev, XX, XX },
- /* 90 */
- { "nop", XX, XX, XX },
- /* FIXME: NOP with REPz prefix is called PAUSE. */
- { "xchg", RMeCX, eAX, XX },
- { "xchg", RMeDX, eAX, XX },
- { "xchg", RMeBX, eAX, XX },
- { "xchg", RMeSP, eAX, XX },
- { "xchg", RMeBP, eAX, XX },
- { "xchg", RMeSI, eAX, XX },
- { "xchg", RMeDI, eAX, XX },
- /* 98 */
- { "cW", XX, XX, XX }, /* cwde and cbw */
- { "cR", XX, XX, XX }, /* cdq and cwd */
- { "lcall", Ap, XX, XX },
- { "(bad)", XX, XX, XX }, /* fwait */
- { "pushf", XX, XX, XX },
- { "popf", XX, XX, XX },
- { "sahf", XX, XX, XX },
- { "lahf", XX, XX, XX },
- /* a0 */
- { "mov", AL, Ob, XX },
- { "mov", eAX, Ov, XX },
- { "mov", Ob, AL, XX },
- { "mov", Ov, eAX, XX },
- { "movs", Yb, Xb, XX },
- { "movs", Yv, Xv, XX },
- { "cmps", Xb, Yb, XX },
- { "cmps", Xv, Yv, XX },
- /* a8 */
- { "test", AL, Ib, XX },
- { "test", eAX, Iv, XX },
- { "stos", Yb, AL, XX },
- { "stos", Yv, eAX, XX },
- { "lods", AL, Xb, XX },
- { "lods", eAX, Xv, XX },
- { "scas", AL, Yb, XX },
- { "scas", eAX, Yv, XX },
- /* b0 */
- { "mov", RMAL, Ib, XX },
- { "mov", RMCL, Ib, XX },
- { "mov", RMDL, Ib, XX },
- { "mov", RMBL, Ib, XX },
- { "mov", RMAH, Ib, XX },
- { "mov", RMCH, Ib, XX },
- { "mov", RMDH, Ib, XX },
- { "mov", RMBH, Ib, XX },
- /* b8 */
- { "mov", RMeAX, Iv, XX },
- { "mov", RMeCX, Iv, XX },
- { "mov", RMeDX, Iv, XX },
- { "mov", RMeBX, Iv, XX },
- { "mov", RMeSP, Iv, XX },
- { "mov", RMeBP, Iv, XX },
- { "mov", RMeSI, Iv, XX },
- { "mov", RMeDI, Iv, XX },
- /* c0 */
- { GRP2b },
- { GRP2S },
- { "ret", Iw, XX, XX },
- { "ret", XX, XX, XX },
- { "les", Gv, Mp, XX },
- { "lds", Gv, Mp, XX },
- { "mov", Eb, Ib, XX },
- { "mov", Ev, Iv, XX },
- /* c8 */
- { "enter", Iw, Ib, XX },
- { "leave", XX, XX, XX },
- { "lret", Iw, XX, XX },
- { "lret", XX, XX, XX },
- { "int3", XX, XX, XX },
- { "int", Ib, XX, XX },
- { "into", XX, XX, XX },
- { "iret", XX, XX, XX },
- /* d0 */
- { GRP2b_one },
- { GRP2S_one },
- { GRP2b_cl },
- { GRP2S_cl },
- { "aam", sIb, XX, XX },
- { "aad", sIb, XX, XX },
- { "(bad)", XX, XX, XX },
- { "xlat", DSBX, XX, XX },
- /* d8 */
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- /* e0 */
- { "loopne", Jb, XX, XX },
- { "loope", Jb, XX, XX },
- { "loop", Jb, XX, XX },
- { "jEcxz", Jb, XX, XX },
- { "in", AL, Ib, XX },
- { "in", eAX, Ib, XX },
- { "out", Ib, AL, XX },
- { "out", Ib, eAX, XX },
- /* e8 */
- { "call", Jv, XX, XX },
- { "jmp", Jv, XX, XX },
- { "ljmp", Ap, XX, XX },
- { "jmp", Jb, XX, XX },
- { "in", AL, indirDX, XX },
- { "in", eAX, indirDX, XX },
- { "out", indirDX, AL, XX },
- { "out", indirDX, eAX, XX },
- /* f0 */
- { "(bad)", XX, XX, XX }, /* lock prefix */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX }, /* repne */
- { "(bad)", XX, XX, XX }, /* repz */
- { "hlt", XX, XX, XX },
- { "cmc", XX, XX, XX },
- { GRP3b },
- { GRP3S },
- /* f8 */
- { "clc", XX, XX, XX },
- { "stc", XX, XX, XX },
- { "cli", XX, XX, XX },
- { "sti", XX, XX, XX },
- { "cld", XX, XX, XX },
- { "std", XX, XX, XX },
- { GRP4 },
- { GRP5 },
-};
+ Many of the above letters print nothing in Intel mode. See "putop"
+ for the details.
-/* 64bit mode is having some instruction set differences, so separate table is
- needed. */
-static const struct dis386 disx86_64_att[] = {
- /* 00 */
- { "addB", Eb, Gb, XX },
- { "addS", Ev, Gv, XX },
- { "addB", Gb, Eb, XX },
- { "addS", Gv, Ev, XX },
- { "addB", AL, Ib, XX },
- { "addS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- /* 08 */
- { "orB", Eb, Gb, XX },
- { "orS", Ev, Gv, XX },
- { "orB", Gb, Eb, XX },
- { "orS", Gv, Ev, XX },
- { "orB", AL, Ib, XX },
- { "orS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
- /* 10 */
- { "adcB", Eb, Gb, XX },
- { "adcS", Ev, Gv, XX },
- { "adcB", Gb, Eb, XX },
- { "adcS", Gv, Ev, XX },
- { "adcB", AL, Ib, XX },
- { "adcS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- /* 18 */
- { "sbbB", Eb, Gb, XX },
- { "sbbS", Ev, Gv, XX },
- { "sbbB", Gb, Eb, XX },
- { "sbbS", Gv, Ev, XX },
- { "sbbB", AL, Ib, XX },
- { "sbbS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- /* 20 */
- { "andB", Eb, Gb, XX },
- { "andS", Ev, Gv, XX },
- { "andB", Gb, Eb, XX },
- { "andS", Gv, Ev, XX },
- { "andB", AL, Ib, XX },
- { "andS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG ES prefix */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- /* 28 */
- { "subB", Eb, Gb, XX },
- { "subS", Ev, Gv, XX },
- { "subB", Gb, Eb, XX },
- { "subS", Gv, Ev, XX },
- { "subB", AL, Ib, XX },
- { "subS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG CS prefix */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- /* 30 */
- { "xorB", Eb, Gb, XX },
- { "xorS", Ev, Gv, XX },
- { "xorB", Gb, Eb, XX },
- { "xorS", Gv, Ev, XX },
- { "xorB", AL, Ib, XX },
- { "xorS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG SS prefix */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- /* 38 */
- { "cmpB", Eb, Gb, XX },
- { "cmpS", Ev, Gv, XX },
- { "cmpB", Gb, Eb, XX },
- { "cmpS", Gv, Ev, XX },
- { "cmpB", AL, Ib, XX },
- { "cmpS", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG DS prefix */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- /* 40 */
- { "(bad)", XX, XX, XX }, /* REX prefix area. */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- /* 48 */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- /* 50 */
- { "pushI", RMrAX, XX, XX },
- { "pushI", RMrCX, XX, XX },
- { "pushI", RMrDX, XX, XX },
- { "pushI", RMrBX, XX, XX },
- { "pushI", RMrSP, XX, XX },
- { "pushI", RMrBP, XX, XX },
- { "pushI", RMrSI, XX, XX },
- { "pushI", RMrDI, XX, XX },
- /* 58 */
- { "popI", RMrAX, XX, XX },
- { "popI", RMrCX, XX, XX },
- { "popI", RMrDX, XX, XX },
- { "popI", RMrBX, XX, XX },
- { "popI", RMrSP, XX, XX },
- { "popI", RMrBP, XX, XX },
- { "popI", RMrSI, XX, XX },
- { "popI", RMrDI, XX, XX },
- /* 60 */
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "movslR", Gv, Ed, XX },
- { "(bad)", XX, XX, XX }, /* seg fs */
- { "(bad)", XX, XX, XX }, /* seg gs */
- { "(bad)", XX, XX, XX }, /* op size prefix */
- { "(bad)", XX, XX, XX }, /* adr size prefix */
- /* 68 */
- { "pushI", Iq, XX, XX }, /* 386 book wrong */
- { "imulS", Gv, Ev, Iv },
- { "pushI", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */
- { "imulS", Gv, Ev, sIb },
- { "insb", Yb, indirDX, XX },
- { "insR", Yv, indirDX, XX },
- { "outsb", indirDX, Xb, XX },
- { "outsR", indirDX, Xv, XX },
- /* 70 */
- { "jo", Jb, cond_jump_flag, XX },
- { "jno", Jb, cond_jump_flag, XX },
- { "jb", Jb, cond_jump_flag, XX },
- { "jae", Jb, cond_jump_flag, XX },
- { "je", Jb, cond_jump_flag, XX },
- { "jne", Jb, cond_jump_flag, XX },
- { "jbe", Jb, cond_jump_flag, XX },
- { "ja", Jb, cond_jump_flag, XX },
- /* 78 */
- { "js", Jb, cond_jump_flag, XX },
- { "jns", Jb, cond_jump_flag, XX },
- { "jp", Jb, cond_jump_flag, XX },
- { "jnp", Jb, cond_jump_flag, XX },
- { "jl", Jb, cond_jump_flag, XX },
- { "jge", Jb, cond_jump_flag, XX },
- { "jle", Jb, cond_jump_flag, XX },
- { "jg", Jb, cond_jump_flag, XX },
- /* 80 */
- { GRP1b },
- { GRP1S },
- { "(bad)", XX, XX, XX },
- { GRP1Ss },
- { "testB", Eb, Gb, XX },
- { "testS", Ev, Gv, XX },
- { "xchgB", Eb, Gb, XX },
- { "xchgS", Ev, Gv, XX },
- /* 88 */
- { "movB", Eb, Gb, XX },
- { "movS", Ev, Gv, XX },
- { "movB", Gb, Eb, XX },
- { "movS", Gv, Ev, XX },
- { "movQ", Ev, Sw, XX },
- { "leaS", Gv, M, XX },
- { "movQ", Sw, Ev, XX },
- { "popI", Ev, XX, XX },
- /* 90 */
- { "nop", XX, XX, XX },
- /* FIXME: NOP with REPz prefix is called PAUSE. */
- { "xchgS", RMeCX, eAX, XX },
- { "xchgS", RMeDX, eAX, XX },
- { "xchgS", RMeBX, eAX, XX },
- { "xchgS", RMeSP, eAX, XX },
- { "xchgS", RMeBP, eAX, XX },
- { "xchgS", RMeSI, eAX, XX },
- { "xchgS", RMeDI, eAX, XX },
- /* 98 */
- { "cWtR", XX, XX, XX },
- { "cRtO", XX, XX, XX },
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "(bad)", XX, XX, XX }, /* fwait */
- { "pushfI", XX, XX, XX },
- { "popfI", XX, XX, XX },
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "(bad)", XX, XX, XX }, /* reserved. */
- /* a0 */
- { "movB", AL, Ob64, XX },
- { "movS", eAX, Ov64, XX },
- { "movB", Ob64, AL, XX },
- { "movS", Ov64, eAX, XX },
- { "movsb", Yb, Xb, XX },
- { "movsR", Yv, Xv, XX },
- { "cmpsb", Xb, Yb, XX },
- { "cmpsR", Xv, Yv, XX },
- /* a8 */
- { "testB", AL, Ib, XX },
- { "testS", eAX, Iv, XX },
- { "stosB", Yb, AL, XX },
- { "stosS", Yv, eAX, XX },
- { "lodsB", AL, Xb, XX },
- { "lodsS", eAX, Xv, XX },
- { "scasB", AL, Yb, XX },
- { "scasS", eAX, Yv, XX },
- /* b0 */
- { "movB", RMAL, Ib, XX },
- { "movB", RMCL, Ib, XX },
- { "movB", RMDL, Ib, XX },
- { "movB", RMBL, Ib, XX },
- { "movB", RMAH, Ib, XX },
- { "movB", RMCH, Ib, XX },
- { "movB", RMDH, Ib, XX },
- { "movB", RMBH, Ib, XX },
- /* b8 */
- { "movS", RMeAX, Iv64, XX },
- { "movS", RMeCX, Iv64, XX },
- { "movS", RMeDX, Iv64, XX },
- { "movS", RMeBX, Iv64, XX },
- { "movS", RMeSP, Iv64, XX },
- { "movS", RMeBP, Iv64, XX },
- { "movS", RMeSI, Iv64, XX },
- { "movS", RMeDI, Iv64, XX },
- /* c0 */
- { GRP2b },
- { GRP2S },
- { "retI", Iw, XX, XX },
- { "retI", XX, XX, XX },
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "ldsS", Gv, Mp, XX },
- { "movA", Eb, Ib, XX },
- { "movQ", Ev, Iv, XX },
- /* c8 */
- { "enterI", Iw, Ib, XX },
- { "leaveI", XX, XX, XX },
- { "lretP", Iw, XX, XX },
- { "lretP", XX, XX, XX },
- { "int3", XX, XX, XX },
- { "int", Ib, XX, XX },
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "iretP", XX, XX, XX },
- /* d0 */
- { GRP2b_one },
- { GRP2S_one },
- { GRP2b_cl },
- { GRP2S_cl },
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "xlat", DSBX, XX, XX },
- /* d8 */
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- /* e0 */
- { "loopneF", Jb, loop_jcxz_flag, XX },
- { "loopeF", Jb, loop_jcxz_flag, XX },
- { "loopF", Jb, loop_jcxz_flag, XX },
- { "jEcxz", Jb, loop_jcxz_flag, XX },
- { "inB", AL, Ib, XX },
- { "inS", eAX, Ib, XX },
- { "outB", Ib, AL, XX },
- { "outS", Ib, eAX, XX },
- /* e8 */
- { "callI", Jv, XX, XX },
- { "jmpI", Jv, XX, XX },
- { "(bad)", XX, XX, XX }, /* reserved. */
- { "jmp", Jb, XX, XX },
- { "inB", AL, indirDX, XX },
- { "inS", eAX, indirDX, XX },
- { "outB", indirDX, AL, XX },
- { "outS", indirDX, eAX, XX },
- /* f0 */
- { "(bad)", XX, XX, XX }, /* lock prefix */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX }, /* repne */
- { "(bad)", XX, XX, XX }, /* repz */
- { "hlt", XX, XX, XX },
- { "cmc", XX, XX, XX },
- { GRP3b },
- { GRP3S },
- /* f8 */
- { "clc", XX, XX, XX },
- { "stc", XX, XX, XX },
- { "cli", XX, XX, XX },
- { "sti", XX, XX, XX },
- { "cld", XX, XX, XX },
- { "std", XX, XX, XX },
- { GRP4 },
- { GRP5 },
-};
+ Braces '{' and '}', and vertical bars '|', indicate alternative
+ mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel
+ modes. In cases where there are only two alternatives, the X86_64
+ instruction is reserved, and "(bad)" is printed.
+*/
-static const struct dis386 dis386_64_intel[] = {
+static const struct dis386 dis386[] = {
/* 00 */
- { "add", Eb, Gb, XX },
- { "add", Ev, Gv, XX },
- { "add", Gb, Eb, XX },
- { "add", Gv, Ev, XX },
- { "add", AL, Ib, XX },
- { "add", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
+ { "addB", Eb, Gb, XX },
+ { "addS", Ev, Gv, XX },
+ { "addB", Gb, Eb, XX },
+ { "addS", Gv, Ev, XX },
+ { "addB", AL, Ib, XX },
+ { "addS", eAX, Iv, XX },
+ { "push{T|}", es, XX, XX },
+ { "pop{T|}", es, XX, XX },
/* 08 */
- { "or", Eb, Gb, XX },
- { "or", Ev, Gv, XX },
- { "or", Gb, Eb, XX },
- { "or", Gv, Ev, XX },
- { "or", AL, Ib, XX },
- { "or", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
+ { "orB", Eb, Gb, XX },
+ { "orS", Ev, Gv, XX },
+ { "orB", Gb, Eb, XX },
+ { "orS", Gv, Ev, XX },
+ { "orB", AL, Ib, XX },
+ { "orS", eAX, Iv, XX },
+ { "push{T|}", cs, XX, XX },
+ { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
/* 10 */
- { "adc", Eb, Gb, XX },
- { "adc", Ev, Gv, XX },
- { "adc", Gb, Eb, XX },
- { "adc", Gv, Ev, XX },
- { "adc", AL, Ib, XX },
- { "adc", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
+ { "adcB", Eb, Gb, XX },
+ { "adcS", Ev, Gv, XX },
+ { "adcB", Gb, Eb, XX },
+ { "adcS", Gv, Ev, XX },
+ { "adcB", AL, Ib, XX },
+ { "adcS", eAX, Iv, XX },
+ { "push{T|}", ss, XX, XX },
+ { "popT|}", ss, XX, XX },
/* 18 */
- { "sbb", Eb, Gb, XX },
- { "sbb", Ev, Gv, XX },
- { "sbb", Gb, Eb, XX },
- { "sbb", Gv, Ev, XX },
- { "sbb", AL, Ib, XX },
- { "sbb", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
+ { "sbbB", Eb, Gb, XX },
+ { "sbbS", Ev, Gv, XX },
+ { "sbbB", Gb, Eb, XX },
+ { "sbbS", Gv, Ev, XX },
+ { "sbbB", AL, Ib, XX },
+ { "sbbS", eAX, Iv, XX },
+ { "push{T|}", ds, XX, XX },
+ { "pop{T|}", ds, XX, XX },
/* 20 */
- { "and", Eb, Gb, XX },
- { "and", Ev, Gv, XX },
- { "and", Gb, Eb, XX },
- { "and", Gv, Ev, XX },
- { "and", AL, Ib, XX },
- { "and", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG ES prefix */
- { "(bad)", XX, XX, XX }, /* Reserved. */
+ { "andB", Eb, Gb, XX },
+ { "andS", Ev, Gv, XX },
+ { "andB", Gb, Eb, XX },
+ { "andS", Gv, Ev, XX },
+ { "andB", AL, Ib, XX },
+ { "andS", eAX, Iv, XX },
+ { "(bad)", XX, XX, XX }, /* SEG ES prefix */
+ { "daa{|}", XX, XX, XX },
/* 28 */
- { "sub", Eb, Gb, XX },
- { "sub", Ev, Gv, XX },
- { "sub", Gb, Eb, XX },
- { "sub", Gv, Ev, XX },
- { "sub", AL, Ib, XX },
- { "sub", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG CS prefix */
- { "(bad)", XX, XX, XX }, /* Reserved. */
+ { "subB", Eb, Gb, XX },
+ { "subS", Ev, Gv, XX },
+ { "subB", Gb, Eb, XX },
+ { "subS", Gv, Ev, XX },
+ { "subB", AL, Ib, XX },
+ { "subS", eAX, Iv, XX },
+ { "(bad)", XX, XX, XX }, /* SEG CS prefix */
+ { "das{|}", XX, XX, XX },
/* 30 */
- { "xor", Eb, Gb, XX },
- { "xor", Ev, Gv, XX },
- { "xor", Gb, Eb, XX },
- { "xor", Gv, Ev, XX },
- { "xor", AL, Ib, XX },
- { "xor", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG SS prefix */
- { "(bad)", XX, XX, XX }, /* Reserved. */
+ { "xorB", Eb, Gb, XX },
+ { "xorS", Ev, Gv, XX },
+ { "xorB", Gb, Eb, XX },
+ { "xorS", Gv, Ev, XX },
+ { "xorB", AL, Ib, XX },
+ { "xorS", eAX, Iv, XX },
+ { "(bad)", XX, XX, XX }, /* SEG SS prefix */
+ { "aaa{|}", XX, XX, XX },
/* 38 */
- { "cmp", Eb, Gb, XX },
- { "cmp", Ev, Gv, XX },
- { "cmp", Gb, Eb, XX },
- { "cmp", Gv, Ev, XX },
- { "cmp", AL, Ib, XX },
- { "cmp", eAX, Iv, XX },
- { "(bad)", XX, XX, XX }, /* SEG DS prefix */
- { "(bad)", XX, XX, XX }, /* Reserved. */
+ { "cmpB", Eb, Gb, XX },
+ { "cmpS", Ev, Gv, XX },
+ { "cmpB", Gb, Eb, XX },
+ { "cmpS", Gv, Ev, XX },
+ { "cmpB", AL, Ib, XX },
+ { "cmpS", eAX, Iv, XX },
+ { "(bad)", XX, XX, XX }, /* SEG DS prefix */
+ { "aas{|}", XX, XX, XX },
/* 40 */
- { "(bad)", XX, XX, XX }, /* REX prefix area. */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
+ { "inc{S|}", RMeAX, XX, XX },
+ { "inc{S|}", RMeCX, XX, XX },
+ { "inc{S|}", RMeDX, XX, XX },
+ { "inc{S|}", RMeBX, XX, XX },
+ { "inc{S|}", RMeSP, XX, XX },
+ { "inc{S|}", RMeBP, XX, XX },
+ { "inc{S|}", RMeSI, XX, XX },
+ { "inc{S|}", RMeDI, XX, XX },
/* 48 */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
+ { "dec{S|}", RMeAX, XX, XX },
+ { "dec{S|}", RMeCX, XX, XX },
+ { "dec{S|}", RMeDX, XX, XX },
+ { "dec{S|}", RMeBX, XX, XX },
+ { "dec{S|}", RMeSP, XX, XX },
+ { "dec{S|}", RMeBP, XX, XX },
+ { "dec{S|}", RMeSI, XX, XX },
+ { "dec{S|}", RMeDI, XX, XX },
/* 50 */
- { "push", RMrAX, XX, XX },
- { "push", RMrCX, XX, XX },
- { "push", RMrDX, XX, XX },
- { "push", RMrBX, XX, XX },
- { "push", RMrSP, XX, XX },
- { "push", RMrBP, XX, XX },
- { "push", RMrSI, XX, XX },
- { "push", RMrDI, XX, XX },
+ { "pushS", RMrAX, XX, XX },
+ { "pushS", RMrCX, XX, XX },
+ { "pushS", RMrDX, XX, XX },
+ { "pushS", RMrBX, XX, XX },
+ { "pushS", RMrSP, XX, XX },
+ { "pushS", RMrBP, XX, XX },
+ { "pushS", RMrSI, XX, XX },
+ { "pushS", RMrDI, XX, XX },
/* 58 */
- { "pop", RMrAX, XX, XX },
- { "pop", RMrCX, XX, XX },
- { "pop", RMrDX, XX, XX },
- { "pop", RMrBX, XX, XX },
- { "pop", RMrSP, XX, XX },
- { "pop", RMrBP, XX, XX },
- { "pop", RMrSI, XX, XX },
- { "pop", RMrDI, XX, XX },
+ { "popS", RMrAX, XX, XX },
+ { "popS", RMrCX, XX, XX },
+ { "popS", RMrDX, XX, XX },
+ { "popS", RMrBX, XX, XX },
+ { "popS", RMrSP, XX, XX },
+ { "popS", RMrBP, XX, XX },
+ { "popS", RMrSI, XX, XX },
+ { "popS", RMrDI, XX, XX },
/* 60 */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "movsx", Gv, Ed, XX },
- { "(bad)", XX, XX, XX }, /* seg fs */
- { "(bad)", XX, XX, XX }, /* seg gs */
- { "(bad)", XX, XX, XX }, /* op size prefix */
- { "(bad)", XX, XX, XX }, /* adr size prefix */
+ { "pusha{P|}", XX, XX, XX },
+ { "popa{P|}", XX, XX, XX },
+ { "bound{S|}", Gv, Ma, XX },
+ { X86_64_0 },
+ { "(bad)", XX, XX, XX }, /* seg fs */
+ { "(bad)", XX, XX, XX }, /* seg gs */
+ { "(bad)", XX, XX, XX }, /* op size prefix */
+ { "(bad)", XX, XX, XX }, /* adr size prefix */
/* 68 */
- { "push", Iq, XX, XX }, /* 386 book wrong */
- { "imul", Gv, Ev, Iv },
- { "push", sIb, XX, XX }, /* push of byte really pushes 2 or 4 bytes */
- { "imul", Gv, Ev, sIb },
- { "ins", Yb, indirDX, XX },
- { "ins", Yv, indirDX, XX },
- { "outs", indirDX, Xb, XX },
- { "outs", indirDX, Xv, XX },
+ { "pushT", Iq, XX, XX },
+ { "imulS", Gv, Ev, Iv },
+ { "pushT", sIb, XX, XX },
+ { "imulS", Gv, Ev, sIb },
+ { "ins{b||b|}", Yb, indirDX, XX },
+ { "ins{R||R|}", Yv, indirDX, XX },
+ { "outs{b||b|}", indirDX, Xb, XX },
+ { "outs{R||R|}", indirDX, Xv, XX },
/* 70 */
- { "jo", Jb, XX, XX },
- { "jno", Jb, XX, XX },
- { "jb", Jb, XX, XX },
- { "jae", Jb, XX, XX },
- { "je", Jb, XX, XX },
- { "jne", Jb, XX, XX },
- { "jbe", Jb, XX, XX },
- { "ja", Jb, XX, XX },
+ { "joH", Jb, XX, cond_jump_flag },
+ { "jnoH", Jb, XX, cond_jump_flag },
+ { "jbH", Jb, XX, cond_jump_flag },
+ { "jaeH", Jb, XX, cond_jump_flag },
+ { "jeH", Jb, XX, cond_jump_flag },
+ { "jneH", Jb, XX, cond_jump_flag },
+ { "jbeH", Jb, XX, cond_jump_flag },
+ { "jaH", Jb, XX, cond_jump_flag },
/* 78 */
- { "js", Jb, XX, XX },
- { "jns", Jb, XX, XX },
- { "jp", Jb, XX, XX },
- { "jnp", Jb, XX, XX },
- { "jl", Jb, XX, XX },
- { "jge", Jb, XX, XX },
- { "jle", Jb, XX, XX },
- { "jg", Jb, XX, XX },
+ { "jsH", Jb, XX, cond_jump_flag },
+ { "jnsH", Jb, XX, cond_jump_flag },
+ { "jpH", Jb, XX, cond_jump_flag },
+ { "jnpH", Jb, XX, cond_jump_flag },
+ { "jlH", Jb, XX, cond_jump_flag },
+ { "jgeH", Jb, XX, cond_jump_flag },
+ { "jleH", Jb, XX, cond_jump_flag },
+ { "jgH", Jb, XX, cond_jump_flag },
/* 80 */
{ GRP1b },
{ GRP1S },
- { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
{ GRP1Ss },
- { "test", Eb, Gb, XX },
- { "test", Ev, Gv, XX },
- { "xchg", Eb, Gb, XX },
- { "xchg", Ev, Gv, XX },
+ { "testB", Eb, Gb, XX },
+ { "testS", Ev, Gv, XX },
+ { "xchgB", Eb, Gb, XX },
+ { "xchgS", Ev, Gv, XX },
/* 88 */
- { "mov", Eb, Gb, XX },
- { "mov", Ev, Gv, XX },
- { "mov", Gb, Eb, XX },
- { "mov", Gv, Ev, XX },
- { "mov", Ev, Sw, XX },
- { "lea", Gv, M, XX },
- { "mov", Sw, Ev, XX },
- { "pop", Ev, XX, XX },
+ { "movB", Eb, Gb, XX },
+ { "movS", Ev, Gv, XX },
+ { "movB", Gb, Eb, XX },
+ { "movS", Gv, Ev, XX },
+ { "movQ", Ev, Sw, XX },
+ { "leaS", Gv, M, XX },
+ { "movQ", Sw, Ev, XX },
+ { "popU", Ev, XX, XX },
/* 90 */
- { "nop", XX, XX, XX },
+ { "nop", XX, XX, XX },
/* FIXME: NOP with REPz prefix is called PAUSE. */
- { "xchg", RMeCX, eAX, XX },
- { "xchg", RMeDX, eAX, XX },
- { "xchg", RMeBX, eAX, XX },
- { "xchg", RMeSP, eAX, XX },
- { "xchg", RMeBP, eAX, XX },
- { "xchg", RMeSI, eAX, XX },
- { "xchg", RMeDI, eAX, XX },
+ { "xchgS", RMeCX, eAX, XX },
+ { "xchgS", RMeDX, eAX, XX },
+ { "xchgS", RMeBX, eAX, XX },
+ { "xchgS", RMeSP, eAX, XX },
+ { "xchgS", RMeBP, eAX, XX },
+ { "xchgS", RMeSI, eAX, XX },
+ { "xchgS", RMeDI, eAX, XX },
/* 98 */
- { "cW", XX, XX, XX }, /* cwde and cbw */
- { "cR", XX, XX, XX }, /* cdq and cwd */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* fwait */
- { "pushf", XX, XX, XX },
- { "popf", XX, XX, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
+ { "cW{tR||tR|}", XX, XX, XX },
+ { "cR{tO||tO|}", XX, XX, XX },
+ { "lcall{T|}", Ap, XX, XX },
+ { "(bad)", XX, XX, XX }, /* fwait */
+ { "pushfT", XX, XX, XX },
+ { "popfT", XX, XX, XX },
+ { "sahf{|}", XX, XX, XX },
+ { "lahf{|}", XX, XX, XX },
/* a0 */
- { "mov", AL, Ob, XX },
- { "mov", eAX, Ov, XX },
- { "mov", Ob, AL, XX },
- { "mov", Ov, eAX, XX },
- { "movs", Yb, Xb, XX },
- { "movs", Yv, Xv, XX },
- { "cmps", Xb, Yb, XX },
- { "cmps", Xv, Yv, XX },
+ { "movB", AL, Ob64, XX },
+ { "movS", eAX, Ov64, XX },
+ { "movB", Ob64, AL, XX },
+ { "movS", Ov64, eAX, XX },
+ { "movs{b||b|}", Yb, Xb, XX },
+ { "movs{R||R|}", Yv, Xv, XX },
+ { "cmps{b||b|}", Xb, Yb, XX },
+ { "cmps{R||R|}", Xv, Yv, XX },
/* a8 */
- { "test", AL, Ib, XX },
- { "test", eAX, Iv, XX },
- { "stos", Yb, AL, XX },
- { "stos", Yv, eAX, XX },
- { "lods", AL, Xb, XX },
- { "lods", eAX, Xv, XX },
- { "scas", AL, Yb, XX },
- { "scas", eAX, Yv, XX },
+ { "testB", AL, Ib, XX },
+ { "testS", eAX, Iv, XX },
+ { "stosB", Yb, AL, XX },
+ { "stosS", Yv, eAX, XX },
+ { "lodsB", AL, Xb, XX },
+ { "lodsS", eAX, Xv, XX },
+ { "scasB", AL, Yb, XX },
+ { "scasS", eAX, Yv, XX },
/* b0 */
- { "mov", RMAL, Ib, XX },
- { "mov", RMCL, Ib, XX },
- { "mov", RMDL, Ib, XX },
- { "mov", RMBL, Ib, XX },
- { "mov", RMAH, Ib, XX },
- { "mov", RMCH, Ib, XX },
- { "mov", RMDH, Ib, XX },
- { "mov", RMBH, Ib, XX },
+ { "movB", RMAL, Ib, XX },
+ { "movB", RMCL, Ib, XX },
+ { "movB", RMDL, Ib, XX },
+ { "movB", RMBL, Ib, XX },
+ { "movB", RMAH, Ib, XX },
+ { "movB", RMCH, Ib, XX },
+ { "movB", RMDH, Ib, XX },
+ { "movB", RMBH, Ib, XX },
/* b8 */
- { "mov", RMeAX, Iv, XX },
- { "mov", RMeCX, Iv, XX },
- { "mov", RMeDX, Iv, XX },
- { "mov", RMeBX, Iv, XX },
- { "mov", RMeSP, Iv, XX },
- { "mov", RMeBP, Iv, XX },
- { "mov", RMeSI, Iv, XX },
- { "mov", RMeDI, Iv, XX },
+ { "movS", RMeAX, Iv64, XX },
+ { "movS", RMeCX, Iv64, XX },
+ { "movS", RMeDX, Iv64, XX },
+ { "movS", RMeBX, Iv64, XX },
+ { "movS", RMeSP, Iv64, XX },
+ { "movS", RMeBP, Iv64, XX },
+ { "movS", RMeSI, Iv64, XX },
+ { "movS", RMeDI, Iv64, XX },
/* c0 */
{ GRP2b },
{ GRP2S },
- { "ret", Iw, XX, XX },
- { "ret", XX, XX, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "lds", Gv, Mp, XX },
- { "mov", Eb, Ib, XX },
- { "mov", Ev, Iv, XX },
+ { "retT", Iw, XX, XX },
+ { "retT", XX, XX, XX },
+ { "les{S|}", Gv, Mp, XX },
+ { "ldsS", Gv, Mp, XX },
+ { "movA", Eb, Ib, XX },
+ { "movQ", Ev, Iv, XX },
/* c8 */
- { "enter", Iw, Ib, XX },
- { "leave", XX, XX, XX },
- { "lret", Iw, XX, XX },
- { "lret", XX, XX, XX },
- { "int3", XX, XX, XX },
- { "int", Ib, XX, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "iret", XX, XX, XX },
+ { "enterT", Iw, Ib, XX },
+ { "leaveT", XX, XX, XX },
+ { "lretP", Iw, XX, XX },
+ { "lretP", XX, XX, XX },
+ { "int3", XX, XX, XX },
+ { "int", Ib, XX, XX },
+ { "into{|}", XX, XX, XX },
+ { "iretP", XX, XX, XX },
/* d0 */
{ GRP2b_one },
{ GRP2S_one },
{ GRP2b_cl },
{ GRP2S_cl },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "xlat", DSBX, XX, XX },
+ { "aam{|}", sIb, XX, XX },
+ { "aad{|}", sIb, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "xlat", DSBX, XX, XX },
/* d8 */
{ FLOAT },
{ FLOAT },
@@ -1585,436 +717,143 @@ static const struct dis386 dis386_64_intel[] = {
{ FLOAT },
{ FLOAT },
/* e0 */
- { "loopne", Jb, XX, XX },
- { "loope", Jb, XX, XX },
- { "loop", Jb, XX, XX },
- { "jEcxz", Jb, XX, XX },
- { "in", AL, Ib, XX },
- { "in", eAX, Ib, XX },
- { "out", Ib, AL, XX },
- { "out", Ib, eAX, XX },
+ { "loopneFH", Jb, XX, loop_jcxz_flag },
+ { "loopeFH", Jb, XX, loop_jcxz_flag },
+ { "loopFH", Jb, XX, loop_jcxz_flag },
+ { "jEcxzH", Jb, XX, loop_jcxz_flag },
+ { "inB", AL, Ib, XX },
+ { "inS", eAX, Ib, XX },
+ { "outB", Ib, AL, XX },
+ { "outS", Ib, eAX, XX },
/* e8 */
- { "call", Jv, XX, XX },
- { "jmp", Jv, XX, XX },
- { "(bad)", XX, XX, XX }, /* Reserved. */
- { "jmp", Jb, XX, XX },
- { "in", AL, indirDX, XX },
- { "in", eAX, indirDX, XX },
- { "out", indirDX, AL, XX },
- { "out", indirDX, eAX, XX },
+ { "callT", Jv, XX, XX },
+ { "jmpT", Jv, XX, XX },
+ { "ljmp{T|}", Ap, XX, XX },
+ { "jmp", Jb, XX, XX },
+ { "inB", AL, indirDX, XX },
+ { "inS", eAX, indirDX, XX },
+ { "outB", indirDX, AL, XX },
+ { "outS", indirDX, eAX, XX },
/* f0 */
- { "(bad)", XX, XX, XX }, /* lock prefix */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX }, /* repne */
- { "(bad)", XX, XX, XX }, /* repz */
- { "hlt", XX, XX, XX },
- { "cmc", XX, XX, XX },
+ { "(bad)", XX, XX, XX }, /* lock prefix */
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX }, /* repne */
+ { "(bad)", XX, XX, XX }, /* repz */
+ { "hlt", XX, XX, XX },
+ { "cmc", XX, XX, XX },
{ GRP3b },
{ GRP3S },
/* f8 */
- { "clc", XX, XX, XX },
- { "stc", XX, XX, XX },
- { "cli", XX, XX, XX },
- { "sti", XX, XX, XX },
- { "cld", XX, XX, XX },
- { "std", XX, XX, XX },
+ { "clc", XX, XX, XX },
+ { "stc", XX, XX, XX },
+ { "cli", XX, XX, XX },
+ { "sti", XX, XX, XX },
+ { "cld", XX, XX, XX },
+ { "std", XX, XX, XX },
{ GRP4 },
{ GRP5 },
};
-static const struct dis386 dis386_twobyte_att[] = {
- /* 00 */
- { GRP6 },
- { GRP7 },
- { "larS", Gv, Ew, XX },
- { "lslS", Gv, Ew, XX },
- { "(bad)", XX, XX, XX },
- { "syscall", XX, XX, XX },
- { "clts", XX, XX, XX },
- { "sysretP", XX, XX, XX },
- /* 08 */
- { "invd", XX, XX, XX },
- { "wbinvd", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "ud2a", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { GRPAMD },
- { "femms", XX, XX, XX },
- { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix */
- /* 10 */
- { PREGRP8 },
- { PREGRP9 },
- { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */
- { "movlpX", EX, XM, SIMD_Fixup, 'h' },
- { "unpcklpX", XM, EX, XX },
- { "unpckhpX", XM, EX, XX },
- { "movhpX", XM, EX, SIMD_Fixup, 'l' },
- { "movhpX", EX, XM, SIMD_Fixup, 'l' },
- /* 18 */
- { GRP14 },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- /* 20 */
- /* these are all backward in appendix A of the intel book */
- { "movL", Rm, Cm, XX },
- { "movL", Rm, Dm, XX },
- { "movL", Cm, Rm, XX },
- { "movL", Dm, Rm, XX },
- { "movL", Rd, Td, XX },
- { "(bad)", XX, XX, XX },
- { "movL", Td, Rd, XX },
- { "(bad)", XX, XX, XX },
- /* 28 */
- { "movapX", XM, EX, XX },
- { "movapX", EX, XM, XX },
- { PREGRP2 },
- { "movntpX", Ev, XM, XX },
- { PREGRP4 },
- { PREGRP3 },
- { "ucomisX", XM,EX, XX },
- { "comisX", XM,EX, XX },
- /* 30 */
- { "wrmsr", XX, XX, XX },
- { "rdtsc", XX, XX, XX },
- { "rdmsr", XX, XX, XX },
- { "rdpmc", XX, XX, XX },
- { "sysenter", XX, XX, XX },
- { "sysexit", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- /* 38 */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- /* 40 */
- { "cmovo", Gv, Ev, XX },
- { "cmovno", Gv, Ev, XX },
- { "cmovb", Gv, Ev, XX },
- { "cmovae", Gv, Ev, XX },
- { "cmove", Gv, Ev, XX },
- { "cmovne", Gv, Ev, XX },
- { "cmovbe", Gv, Ev, XX },
- { "cmova", Gv, Ev, XX },
- /* 48 */
- { "cmovs", Gv, Ev, XX },
- { "cmovns", Gv, Ev, XX },
- { "cmovp", Gv, Ev, XX },
- { "cmovnp", Gv, Ev, XX },
- { "cmovl", Gv, Ev, XX },
- { "cmovge", Gv, Ev, XX },
- { "cmovle", Gv, Ev, XX },
- { "cmovg", Gv, Ev, XX },
- /* 50 */
- { "movmskpX", Gd, XS, XX },
- { PREGRP13 },
- { PREGRP12 },
- { PREGRP11 },
- { "andpX", XM, EX, XX },
- { "andnpX", XM, EX, XX },
- { "orpX", XM, EX, XX },
- { "xorpX", XM, EX, XX },
- /* 58 */
- { PREGRP0 },
- { PREGRP10 },
- { PREGRP17 },
- { PREGRP16 },
- { PREGRP14 },
- { PREGRP7 },
- { PREGRP5 },
- { PREGRP6 },
- /* 60 */
- { "punpcklbw", MX, EM, XX },
- { "punpcklwd", MX, EM, XX },
- { "punpckldq", MX, EM, XX },
- { "packsswb", MX, EM, XX },
- { "pcmpgtb", MX, EM, XX },
- { "pcmpgtw", MX, EM, XX },
- { "pcmpgtd", MX, EM, XX },
- { "packuswb", MX, EM, XX },
- /* 68 */
- { "punpckhbw", MX, EM, XX },
- { "punpckhwd", MX, EM, XX },
- { "punpckhdq", MX, EM, XX },
- { "packssdw", MX, EM, XX },
- { PREGRP26 },
- { PREGRP24 },
- { "movd", MX, Ed, XX },
- { PREGRP19 },
- /* 70 */
- { PREGRP22 },
- { GRP10 },
- { GRP11 },
- { GRP12 },
- { "pcmpeqb", MX, EM, XX },
- { "pcmpeqw", MX, EM, XX },
- { "pcmpeqd", MX, EM, XX },
- { "emms", XX, XX, XX },
- /* 78 */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { PREGRP23 },
- { PREGRP20 },
- /* 80 */
- { "jo", Jv, cond_jump_flag, XX },
- { "jno", Jv, cond_jump_flag, XX },
- { "jb", Jv, cond_jump_flag, XX },
- { "jae", Jv, cond_jump_flag, XX },
- { "je", Jv, cond_jump_flag, XX },
- { "jne", Jv, cond_jump_flag, XX },
- { "jbe", Jv, cond_jump_flag, XX },
- { "ja", Jv, cond_jump_flag, XX },
- /* 88 */
- { "js", Jv, cond_jump_flag, XX },
- { "jns", Jv, cond_jump_flag, XX },
- { "jp", Jv, cond_jump_flag, XX },
- { "jnp", Jv, cond_jump_flag, XX },
- { "jl", Jv, cond_jump_flag, XX },
- { "jge", Jv, cond_jump_flag, XX },
- { "jle", Jv, cond_jump_flag, XX },
- { "jg", Jv, cond_jump_flag, XX },
- /* 90 */
- { "seto", Eb, XX, XX },
- { "setno", Eb, XX, XX },
- { "setb", Eb, XX, XX },
- { "setae", Eb, XX, XX },
- { "sete", Eb, XX, XX },
- { "setne", Eb, XX, XX },
- { "setbe", Eb, XX, XX },
- { "seta", Eb, XX, XX },
- /* 98 */
- { "sets", Eb, XX, XX },
- { "setns", Eb, XX, XX },
- { "setp", Eb, XX, XX },
- { "setnp", Eb, XX, XX },
- { "setl", Eb, XX, XX },
- { "setge", Eb, XX, XX },
- { "setle", Eb, XX, XX },
- { "setg", Eb, XX, XX },
- /* a0 */
- { "pushI", fs, XX, XX },
- { "popI", fs, XX, XX },
- { "cpuid", XX, XX, XX },
- { "btS", Ev, Gv, XX },
- { "shldS", Ev, Gv, Ib },
- { "shldS", Ev, Gv, CL },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- /* a8 */
- { "pushI", gs, XX, XX },
- { "popI", gs, XX, XX },
- { "rsm", XX, XX, XX },
- { "btsS", Ev, Gv, XX },
- { "shrdS", Ev, Gv, Ib },
- { "shrdS", Ev, Gv, CL },
- { GRP13 },
- { "imulS", Gv, Ev, XX },
- /* b0 */
- { "cmpxchgB", Eb, Gb, XX },
- { "cmpxchgS", Ev, Gv, XX },
- { "lssS", Gv, Mp, XX },
- { "btrS", Ev, Gv, XX },
- { "lfsS", Gv, Mp, XX },
- { "lgsS", Gv, Mp, XX },
- { "movzbR", Gv, Eb, XX },
- { "movzwR", Gv, Ew, XX }, /* yes, there really is movzww ! */
- /* b8 */
- { "(bad)", XX, XX, XX },
- { "ud2b", XX, XX, XX },
- { GRP8 },
- { "btcS", Ev, Gv, XX },
- { "bsfS", Gv, Ev, XX },
- { "bsrS", Gv, Ev, XX },
- { "movsbR", Gv, Eb, XX },
- { "movswR", Gv, Ew, XX }, /* yes, there really is movsww ! */
- /* c0 */
- { "xaddB", Eb, Gb, XX },
- { "xaddS", Ev, Gv, XX },
- { PREGRP1 },
- { "movntiS", Ev, Gv, XX },
- { "pinsrw", MX, Ed, Ib },
- { "pextrw", Gd, MS, Ib },
- { "shufpX", XM, EX, Ib },
- { GRP9 },
- /* c8 */
- { "bswap", RMeAX, XX, XX }, /* bswap doesn't support 16 bit regs */
- { "bswap", RMeCX, XX, XX },
- { "bswap", RMeDX, XX, XX },
- { "bswap", RMeBX, XX, XX },
- { "bswap", RMeSP, XX, XX },
- { "bswap", RMeBP, XX, XX },
- { "bswap", RMeSI, XX, XX },
- { "bswap", RMeDI, XX, XX },
- /* d0 */
- { "(bad)", XX, XX, XX },
- { "psrlw", MX, EM, XX },
- { "psrld", MX, EM, XX },
- { "psrlq", MX, EM, XX },
- { "paddq", MX, EM, XX },
- { "pmullw", MX, EM, XX },
- { PREGRP21 },
- { "pmovmskb", Gd, MS, XX },
- /* d8 */
- { "psubusb", MX, EM, XX },
- { "psubusw", MX, EM, XX },
- { "pminub", MX, EM, XX },
- { "pand", MX, EM, XX },
- { "paddusb", MX, EM, XX },
- { "paddusw", MX, EM, XX },
- { "pmaxub", MX, EM, XX },
- { "pandn", MX, EM, XX },
- /* e0 */
- { "pavgb", MX, EM, XX },
- { "psraw", MX, EM, XX },
- { "psrad", MX, EM, XX },
- { "pavgw", MX, EM, XX },
- { "pmulhuw", MX, EM, XX },
- { "pmulhw", MX, EM, XX },
- { PREGRP15 },
- { PREGRP25 },
- /* e8 */
- { "psubsb", MX, EM, XX },
- { "psubsw", MX, EM, XX },
- { "pminsw", MX, EM, XX },
- { "por", MX, EM, XX },
- { "paddsb", MX, EM, XX },
- { "paddsw", MX, EM, XX },
- { "pmaxsw", MX, EM, XX },
- { "pxor", MX, EM, XX },
- /* f0 */
- { "(bad)", XX, XX, XX },
- { "psllw", MX, EM, XX },
- { "pslld", MX, EM, XX },
- { "psllq", MX, EM, XX },
- { "pmuludq", MX, EM, XX },
- { "pmaddwd", MX, EM, XX },
- { "psadbw", MX, EM, XX },
- { PREGRP18 },
- /* f8 */
- { "psubb", MX, EM, XX },
- { "psubw", MX, EM, XX },
- { "psubd", MX, EM, XX },
- { "psubq", MX, EM, XX },
- { "paddb", MX, EM, XX },
- { "paddw", MX, EM, XX },
- { "paddd", MX, EM, XX },
- { "(bad)", XX, XX, XX }
-};
-
-static const struct dis386 dis386_twobyte_intel[] = {
+static const struct dis386 dis386_twobyte[] = {
/* 00 */
{ GRP6 },
{ GRP7 },
- { "lar", Gv, Ew, XX },
- { "lsl", Gv, Ew, XX },
- { "(bad)", XX, XX, XX },
- { "syscall", XX, XX, XX },
- { "clts", XX, XX, XX },
- { "sysretP", XX, XX, XX },
+ { "larS", Gv, Ew, XX },
+ { "lslS", Gv, Ew, XX },
+ { "(bad)", XX, XX, XX },
+ { "syscall", XX, XX, XX },
+ { "clts", XX, XX, XX },
+ { "sysretP", XX, XX, XX },
/* 08 */
- { "invd", XX, XX, XX },
- { "wbinvd", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "ud2a", XX, XX, XX },
- { "(bad)", XX, XX, XX },
+ { "invd", XX, XX, XX },
+ { "wbinvd", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "ud2a", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
{ GRPAMD },
- { "femms" , XX, XX, XX},
- { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix */
+ { "femms", XX, XX, XX },
+ { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix. */
/* 10 */
{ PREGRP8 },
{ PREGRP9 },
- { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */
- { "movlpX", EX, XM, SIMD_Fixup, 'h' },
- { "unpcklpX", XM, EX, XX },
- { "unpckhpX", XM, EX, XX },
- { "movhpX", XM, EX, SIMD_Fixup, 'l' },
- { "movhpX", EX, XM, SIMD_Fixup, 'l' },
+ { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */
+ { "movlpX", EX, XM, SIMD_Fixup, 'h' },
+ { "unpcklpX", XM, EX, XX },
+ { "unpckhpX", XM, EX, XX },
+ { "movhpX", XM, EX, SIMD_Fixup, 'l' },
+ { "movhpX", EX, XM, SIMD_Fixup, 'l' },
/* 18 */
{ GRP14 },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
/* 20 */
- /* these are all backward in appendix A of the intel book */
- { "mov", Rm, Cm, XX },
- { "mov", Rm, Dm, XX },
- { "mov", Cm, Rm, XX },
- { "mov", Dm, Rm, XX },
- { "mov", Rd, Td, XX },
- { "(bad)", XX, XX, XX },
- { "mov", Td, Rd, XX },
- { "(bad)", XX, XX, XX },
+ { "movL", Rm, Cm, XX },
+ { "movL", Rm, Dm, XX },
+ { "movL", Cm, Rm, XX },
+ { "movL", Dm, Rm, XX },
+ { "movL", Rd, Td, XX },
+ { "(bad)", XX, XX, XX },
+ { "movL", Td, Rd, XX },
+ { "(bad)", XX, XX, XX },
/* 28 */
- { "movapX", XM, EX, XX },
- { "movapX", EX, XM, XX },
+ { "movapX", XM, EX, XX },
+ { "movapX", EX, XM, XX },
{ PREGRP2 },
- { "movntpX", Ev, XM, XX },
+ { "movntpX", Ev, XM, XX },
{ PREGRP4 },
{ PREGRP3 },
- { "ucomisX", XM,EX, XX },
- { "comisX", XM,EX, XX },
+ { "ucomisX", XM,EX, XX },
+ { "comisX", XM,EX, XX },
/* 30 */
- { "wrmsr", XX, XX, XX },
- { "rdtsc", XX, XX, XX },
- { "rdmsr", XX, XX, XX },
- { "rdpmc", XX, XX, XX },
- { "sysenter", XX, XX, XX },
- { "sysexit", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
+ { "wrmsr", XX, XX, XX },
+ { "rdtsc", XX, XX, XX },
+ { "rdmsr", XX, XX, XX },
+ { "rdpmc", XX, XX, XX },
+ { "sysenter", XX, XX, XX },
+ { "sysexit", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
/* 38 */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
/* 40 */
- { "cmovo", Gv, Ev, XX },
- { "cmovno", Gv, Ev, XX },
- { "cmovb", Gv, Ev, XX },
- { "cmovae", Gv, Ev, XX },
- { "cmove", Gv, Ev, XX },
- { "cmovne", Gv, Ev, XX },
- { "cmovbe", Gv, Ev, XX },
- { "cmova", Gv, Ev, XX },
+ { "cmovo", Gv, Ev, XX },
+ { "cmovno", Gv, Ev, XX },
+ { "cmovb", Gv, Ev, XX },
+ { "cmovae", Gv, Ev, XX },
+ { "cmove", Gv, Ev, XX },
+ { "cmovne", Gv, Ev, XX },
+ { "cmovbe", Gv, Ev, XX },
+ { "cmova", Gv, Ev, XX },
/* 48 */
- { "cmovs", Gv, Ev, XX },
- { "cmovns", Gv, Ev, XX },
- { "cmovp", Gv, Ev, XX },
- { "cmovnp", Gv, Ev, XX },
- { "cmovl", Gv, Ev, XX },
- { "cmovge", Gv, Ev, XX },
- { "cmovle", Gv, Ev, XX },
- { "cmovg", Gv, Ev, XX },
+ { "cmovs", Gv, Ev, XX },
+ { "cmovns", Gv, Ev, XX },
+ { "cmovp", Gv, Ev, XX },
+ { "cmovnp", Gv, Ev, XX },
+ { "cmovl", Gv, Ev, XX },
+ { "cmovge", Gv, Ev, XX },
+ { "cmovle", Gv, Ev, XX },
+ { "cmovg", Gv, Ev, XX },
/* 50 */
- { "movmskpX", Gd, XS, XX },
+ { "movmskpX", Gd, XS, XX },
{ PREGRP13 },
{ PREGRP12 },
{ PREGRP11 },
- { "andpX", XM, EX, XX },
- { "andnpX", XM, EX, XX },
- { "orpX", XM, EX, XX },
- { "xorpX", XM, EX, XX },
+ { "andpX", XM, EX, XX },
+ { "andnpX", XM, EX, XX },
+ { "orpX", XM, EX, XX },
+ { "xorpX", XM, EX, XX },
/* 58 */
{ PREGRP0 },
{ PREGRP10 },
@@ -2025,185 +864,185 @@ static const struct dis386 dis386_twobyte_intel[] = {
{ PREGRP5 },
{ PREGRP6 },
/* 60 */
- { "punpcklbw", MX, EM, XX },
- { "punpcklwd", MX, EM, XX },
- { "punpckldq", MX, EM, XX },
- { "packsswb", MX, EM, XX },
- { "pcmpgtb", MX, EM, XX },
- { "pcmpgtw", MX, EM, XX },
- { "pcmpgtd", MX, EM, XX },
- { "packuswb", MX, EM, XX },
+ { "punpcklbw", MX, EM, XX },
+ { "punpcklwd", MX, EM, XX },
+ { "punpckldq", MX, EM, XX },
+ { "packsswb", MX, EM, XX },
+ { "pcmpgtb", MX, EM, XX },
+ { "pcmpgtw", MX, EM, XX },
+ { "pcmpgtd", MX, EM, XX },
+ { "packuswb", MX, EM, XX },
/* 68 */
- { "punpckhbw", MX, EM, XX },
- { "punpckhwd", MX, EM, XX },
- { "punpckhdq", MX, EM, XX },
- { "packssdw", MX, EM, XX },
+ { "punpckhbw", MX, EM, XX },
+ { "punpckhwd", MX, EM, XX },
+ { "punpckhdq", MX, EM, XX },
+ { "packssdw", MX, EM, XX },
{ PREGRP26 },
{ PREGRP24 },
- { "movd", MX, Ed, XX },
+ { "movd", MX, Ed, XX },
{ PREGRP19 },
/* 70 */
{ PREGRP22 },
{ GRP10 },
{ GRP11 },
{ GRP12 },
- { "pcmpeqb", MX, EM, XX },
- { "pcmpeqw", MX, EM, XX },
- { "pcmpeqd", MX, EM, XX },
- { "emms", XX, XX, XX },
+ { "pcmpeqb", MX, EM, XX },
+ { "pcmpeqw", MX, EM, XX },
+ { "pcmpeqd", MX, EM, XX },
+ { "emms", XX, XX, XX },
/* 78 */
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
{ PREGRP23 },
{ PREGRP20 },
/* 80 */
- { "jo", Jv, XX, XX },
- { "jno", Jv, XX, XX },
- { "jb", Jv, XX, XX },
- { "jae", Jv, XX, XX },
- { "je", Jv, XX, XX },
- { "jne", Jv, XX, XX },
- { "jbe", Jv, XX, XX },
- { "ja", Jv, XX, XX },
+ { "joH", Jv, XX, cond_jump_flag },
+ { "jnoH", Jv, XX, cond_jump_flag },
+ { "jbH", Jv, XX, cond_jump_flag },
+ { "jaeH", Jv, XX, cond_jump_flag },
+ { "jeH", Jv, XX, cond_jump_flag },
+ { "jneH", Jv, XX, cond_jump_flag },
+ { "jbeH", Jv, XX, cond_jump_flag },
+ { "jaH", Jv, XX, cond_jump_flag },
/* 88 */
- { "js", Jv, XX, XX },
- { "jns", Jv, XX, XX },
- { "jp", Jv, XX, XX },
- { "jnp", Jv, XX, XX },
- { "jl", Jv, XX, XX },
- { "jge", Jv, XX, XX },
- { "jle", Jv, XX, XX },
- { "jg", Jv, XX, XX },
+ { "jsH", Jv, XX, cond_jump_flag },
+ { "jnsH", Jv, XX, cond_jump_flag },
+ { "jpH", Jv, XX, cond_jump_flag },
+ { "jnpH", Jv, XX, cond_jump_flag },
+ { "jlH", Jv, XX, cond_jump_flag },
+ { "jgeH", Jv, XX, cond_jump_flag },
+ { "jleH", Jv, XX, cond_jump_flag },
+ { "jgH", Jv, XX, cond_jump_flag },
/* 90 */
- { "seto", Eb, XX, XX },
- { "setno", Eb, XX, XX },
- { "setb", Eb, XX, XX },
- { "setae", Eb, XX, XX },
- { "sete", Eb, XX, XX },
- { "setne", Eb, XX, XX },
- { "setbe", Eb, XX, XX },
- { "seta", Eb, XX, XX },
+ { "seto", Eb, XX, XX },
+ { "setno", Eb, XX, XX },
+ { "setb", Eb, XX, XX },
+ { "setae", Eb, XX, XX },
+ { "sete", Eb, XX, XX },
+ { "setne", Eb, XX, XX },
+ { "setbe", Eb, XX, XX },
+ { "seta", Eb, XX, XX },
/* 98 */
- { "sets", Eb, XX, XX },
- { "setns", Eb, XX, XX },
- { "setp", Eb, XX, XX },
- { "setnp", Eb, XX, XX },
- { "setl", Eb, XX, XX },
- { "setge", Eb, XX, XX },
- { "setle", Eb, XX, XX },
- { "setg", Eb, XX, XX },
+ { "sets", Eb, XX, XX },
+ { "setns", Eb, XX, XX },
+ { "setp", Eb, XX, XX },
+ { "setnp", Eb, XX, XX },
+ { "setl", Eb, XX, XX },
+ { "setge", Eb, XX, XX },
+ { "setle", Eb, XX, XX },
+ { "setg", Eb, XX, XX },
/* a0 */
- { "push", fs, XX, XX },
- { "pop", fs, XX, XX },
- { "cpuid", XX, XX, XX },
- { "bt", Ev, Gv, XX },
- { "shld", Ev, Gv, Ib },
- { "shld", Ev, Gv, CL },
- { "(bad)", XX, XX, XX },
- { "(bad)", XX, XX, XX },
+ { "pushT", fs, XX, XX },
+ { "popT", fs, XX, XX },
+ { "cpuid", XX, XX, XX },
+ { "btS", Ev, Gv, XX },
+ { "shldS", Ev, Gv, Ib },
+ { "shldS", Ev, Gv, CL },
+ { "(bad)", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
/* a8 */
- { "push", gs, XX, XX },
- { "pop", gs, XX, XX },
- { "rsm" , XX, XX, XX},
- { "bts", Ev, Gv, XX },
- { "shrd", Ev, Gv, Ib },
- { "shrd", Ev, Gv, CL },
+ { "pushT", gs, XX, XX },
+ { "popT", gs, XX, XX },
+ { "rsm", XX, XX, XX },
+ { "btsS", Ev, Gv, XX },
+ { "shrdS", Ev, Gv, Ib },
+ { "shrdS", Ev, Gv, CL },
{ GRP13 },
- { "imul", Gv, Ev, XX },
+ { "imulS", Gv, Ev, XX },
/* b0 */
- { "cmpxchg", Eb, Gb, XX },
- { "cmpxchg", Ev, Gv, XX },
- { "lss", Gv, Mp, XX },
- { "btr", Ev, Gv, XX },
- { "lfs", Gv, Mp, XX },
- { "lgs", Gv, Mp, XX },
- { "movzx", Gv, Eb, XX },
- { "movzx", Gv, Ew, XX },
+ { "cmpxchgB", Eb, Gb, XX },
+ { "cmpxchgS", Ev, Gv, XX },
+ { "lssS", Gv, Mp, XX },
+ { "btrS", Ev, Gv, XX },
+ { "lfsS", Gv, Mp, XX },
+ { "lgsS", Gv, Mp, XX },
+ { "movz{bR|x|bR|x}", Gv, Eb, XX },
+ { "movz{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movzww ! */
/* b8 */
- { "(bad)", XX, XX, XX },
- { "ud2b", XX, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "ud2b", XX, XX, XX },
{ GRP8 },
- { "btc", Ev, Gv, XX },
- { "bsf", Gv, Ev, XX },
- { "bsr", Gv, Ev, XX },
- { "movsx", Gv, Eb, XX },
- { "movsx", Gv, Ew, XX },
+ { "btcS", Ev, Gv, XX },
+ { "bsfS", Gv, Ev, XX },
+ { "bsrS", Gv, Ev, XX },
+ { "movs{bR|x|bR|x}", Gv, Eb, XX },
+ { "movs{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movsww ! */
/* c0 */
- { "xadd", Eb, Gb, XX },
- { "xadd", Ev, Gv, XX },
+ { "xaddB", Eb, Gb, XX },
+ { "xaddS", Ev, Gv, XX },
{ PREGRP1 },
- { "movnti", Ev, Gv, XX },
- { "pinsrw", MX, Ed, Ib },
- { "pextrw", Gd, MS, Ib },
- { "shufpX", XM, EX, Ib },
+ { "movntiS", Ev, Gv, XX },
+ { "pinsrw", MX, Ed, Ib },
+ { "pextrw", Gd, MS, Ib },
+ { "shufpX", XM, EX, Ib },
{ GRP9 },
/* c8 */
- { "bswap", RMeAX, XX, XX }, /* bswap doesn't support 16 bit regs */
- { "bswap", RMeCX, XX, XX },
- { "bswap", RMeDX, XX, XX },
- { "bswap", RMeBX, XX, XX },
- { "bswap", RMeSP, XX, XX },
- { "bswap", RMeBP, XX, XX },
- { "bswap", RMeSI, XX, XX },
- { "bswap", RMeDI, XX, XX },
+ { "bswap", RMeAX, XX, XX },
+ { "bswap", RMeCX, XX, XX },
+ { "bswap", RMeDX, XX, XX },
+ { "bswap", RMeBX, XX, XX },
+ { "bswap", RMeSP, XX, XX },
+ { "bswap", RMeBP, XX, XX },
+ { "bswap", RMeSI, XX, XX },
+ { "bswap", RMeDI, XX, XX },
/* d0 */
- { "(bad)", XX, XX, XX },
- { "psrlw", MX, EM, XX },
- { "psrld", MX, EM, XX },
- { "psrlq", MX, EM, XX },
- { "paddq", MX, EM, XX },
- { "pmullw", MX, EM, XX },
+ { "(bad)", XX, XX, XX },
+ { "psrlw", MX, EM, XX },
+ { "psrld", MX, EM, XX },
+ { "psrlq", MX, EM, XX },
+ { "paddq", MX, EM, XX },
+ { "pmullw", MX, EM, XX },
{ PREGRP21 },
- { "pmovmskb", Gd, MS, XX },
+ { "pmovmskb", Gd, MS, XX },
/* d8 */
- { "psubusb", MX, EM, XX },
- { "psubusw", MX, EM, XX },
- { "pminub", MX, EM, XX },
- { "pand", MX, EM, XX },
- { "paddusb", MX, EM, XX },
- { "paddusw", MX, EM, XX },
- { "pmaxub", MX, EM, XX },
- { "pandn", MX, EM, XX },
+ { "psubusb", MX, EM, XX },
+ { "psubusw", MX, EM, XX },
+ { "pminub", MX, EM, XX },
+ { "pand", MX, EM, XX },
+ { "paddusb", MX, EM, XX },
+ { "paddusw", MX, EM, XX },
+ { "pmaxub", MX, EM, XX },
+ { "pandn", MX, EM, XX },
/* e0 */
- { "pavgb", MX, EM, XX },
- { "psraw", MX, EM, XX },
- { "psrad", MX, EM, XX },
- { "pavgw", MX, EM, XX },
- { "pmulhuw", MX, EM, XX },
- { "pmulhw", MX, EM, XX },
+ { "pavgb", MX, EM, XX },
+ { "psraw", MX, EM, XX },
+ { "psrad", MX, EM, XX },
+ { "pavgw", MX, EM, XX },
+ { "pmulhuw", MX, EM, XX },
+ { "pmulhw", MX, EM, XX },
{ PREGRP15 },
{ PREGRP25 },
/* e8 */
- { "psubsb", MX, EM, XX },
- { "psubsw", MX, EM, XX },
- { "pminsw", MX, EM, XX },
- { "por", MX, EM, XX },
- { "paddsb", MX, EM, XX },
- { "paddsw", MX, EM, XX },
- { "pmaxsw", MX, EM, XX },
- { "pxor", MX, EM, XX },
+ { "psubsb", MX, EM, XX },
+ { "psubsw", MX, EM, XX },
+ { "pminsw", MX, EM, XX },
+ { "por", MX, EM, XX },
+ { "paddsb", MX, EM, XX },
+ { "paddsw", MX, EM, XX },
+ { "pmaxsw", MX, EM, XX },
+ { "pxor", MX, EM, XX },
/* f0 */
- { "(bad)", XX, XX, XX },
- { "psllw", MX, EM, XX },
- { "pslld", MX, EM, XX },
- { "psllq", MX, EM, XX },
- { "pmuludq", MX, EM, XX },
- { "pmaddwd", MX, EM, XX },
- { "psadbw", MX, EM, XX },
+ { "(bad)", XX, XX, XX },
+ { "psllw", MX, EM, XX },
+ { "pslld", MX, EM, XX },
+ { "psllq", MX, EM, XX },
+ { "pmuludq", MX, EM, XX },
+ { "pmaddwd", MX, EM, XX },
+ { "psadbw", MX, EM, XX },
{ PREGRP18 },
/* f8 */
- { "psubb", MX, EM, XX },
- { "psubw", MX, EM, XX },
- { "psubd", MX, EM, XX },
- { "psubq", MX, EM, XX },
- { "paddb", MX, EM, XX },
- { "paddw", MX, EM, XX },
- { "paddd", MX, EM, XX },
- { "(bad)", XX, XX, XX }
+ { "psubb", MX, EM, XX },
+ { "psubw", MX, EM, XX },
+ { "psubd", MX, EM, XX },
+ { "psubq", MX, EM, XX },
+ { "paddb", MX, EM, XX },
+ { "paddw", MX, EM, XX },
+ { "paddd", MX, EM, XX },
+ { "(bad)", XX, XX, XX }
};
static const unsigned char onebyte_has_modrm[256] = {
@@ -2286,37 +1125,70 @@ static int mod;
static int rm;
static int reg;
static unsigned char need_modrm;
-static void oappend PARAMS ((const char *s));
/* If we are accessing mod/rm/reg without need_modrm set, then the
values are stale. Hitting this abort likely indicates that you
need to update onebyte_has_modrm or twobyte_has_modrm. */
#define MODRM_CHECK if (!need_modrm) abort ()
-static const char *names64[] = {
- "%rax","%rcx","%rdx","%rbx", "%rsp","%rbp","%rsi","%rdi",
+static const char **names64;
+static const char **names32;
+static const char **names16;
+static const char **names8;
+static const char **names8rex;
+static const char **names_seg;
+static const char **index16;
+
+static const char *intel_names64[] = {
+ "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
+};
+static const char *intel_names32[] = {
+ "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
+ "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
+};
+static const char *intel_names16[] = {
+ "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
+ "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
+};
+static const char *intel_names8[] = {
+ "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
+};
+static const char *intel_names8rex[] = {
+ "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
+ "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
+};
+static const char *intel_names_seg[] = {
+ "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
+};
+static const char *intel_index16[] = {
+ "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
+};
+
+static const char *att_names64[] = {
+ "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
};
-static const char *names32[] = {
- "%eax","%ecx","%edx","%ebx", "%esp","%ebp","%esi","%edi",
+static const char *att_names32[] = {
+ "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
"%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
};
-static const char *names16[] = {
- "%ax","%cx","%dx","%bx","%sp","%bp","%si","%di",
+static const char *att_names16[] = {
+ "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
"%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
};
-static const char *names8[] = {
- "%al","%cl","%dl","%bl","%ah","%ch","%dh","%bh",
+static const char *att_names8[] = {
+ "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
};
-static const char *names8rex[] = {
- "%al","%cl","%dl","%bl","%spl", "%bpl", "%sil", "%dil",
+static const char *att_names8rex[] = {
+ "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
};
-static const char *names_seg[] = {
- "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
+static const char *att_names_seg[] = {
+ "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
};
-static const char *index16[] = {
- "%bx,%si","%bx,%di","%bp,%si","%bp,%di","%si","%di","%bp","%bx"
+static const char *att_index16[] = {
+ "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
};
static const struct dis386 grps[][8] = {
@@ -2425,10 +1297,10 @@ static const struct dis386 grps[][8] = {
{ "(bad)", Eb, XX, XX },
{ "notA", Eb, XX, XX },
{ "negA", Eb, XX, XX },
- { "mulB", AL, Eb, XX },
- { "imulB", AL, Eb, XX },
- { "divB", AL, Eb, XX },
- { "idivB", AL, Eb, XX }
+ { "mulA", Eb, XX, XX }, /* Don't print the implicit %al register, */
+ { "imulA", Eb, XX, XX }, /* to distinguish these opcodes from other */
+ { "divA", Eb, XX, XX }, /* mul/imul opcodes. Do the same for div */
+ { "idivA", Eb, XX, XX } /* and idiv for consistency. */
},
/* GRP3S */
{
@@ -2436,10 +1308,10 @@ static const struct dis386 grps[][8] = {
{ "(bad)", XX, XX, XX },
{ "notQ", Ev, XX, XX },
{ "negQ", Ev, XX, XX },
- { "mulS", eAX, Ev, XX },
- { "imulS", eAX, Ev, XX },
- { "divS", eAX, Ev, XX },
- { "idivS", eAX, Ev, XX },
+ { "mulQ", Ev, XX, XX }, /* Don't print the implicit register. */
+ { "imulQ", Ev, XX, XX },
+ { "divQ", Ev, XX, XX },
+ { "idivQ", Ev, XX, XX },
},
/* GRP4 */
{
@@ -2456,11 +1328,11 @@ static const struct dis386 grps[][8] = {
{
{ "incQ", Ev, XX, XX },
{ "decQ", Ev, XX, XX },
- { "callI", indirEv, XX, XX },
- { "lcallI", indirEv, XX, XX },
- { "jmpI", indirEv, XX, XX },
- { "ljmpI", indirEv, XX, XX },
- { "pushT", Ev, XX, XX },
+ { "callT", indirEv, XX, XX },
+ { "lcallT", indirEv, XX, XX },
+ { "jmpT", indirEv, XX, XX },
+ { "ljmpT", indirEv, XX, XX },
+ { "pushU", Ev, XX, XX },
{ "(bad)", XX, XX, XX },
},
/* GRP6 */
@@ -2476,14 +1348,14 @@ static const struct dis386 grps[][8] = {
},
/* GRP7 */
{
- { "sgdt", Ew, XX, XX },
- { "sidt", Ew, XX, XX },
- { "lgdt", Ew, XX, XX },
- { "lidt", Ew, XX, XX },
- { "smsw", Ew, XX, XX },
- { "(bad)", XX, XX, XX },
- { "lmsw", Ew, XX, XX },
- { "invlpg", Ew, XX, XX },
+ { "sgdtQ", M, XX, XX },
+ { "sidtQ", M, XX, XX },
+ { "lgdtQ", M, XX, XX },
+ { "lidtQ", M, XX, XX },
+ { "smsw", Ew, XX, XX },
+ { "(bad)", XX, XX, XX },
+ { "lmsw", Ew, XX, XX },
+ { "invlpg", Ew, XX, XX },
},
/* GRP8 */
{
@@ -2550,7 +1422,7 @@ static const struct dis386 grps[][8] = {
{ "lfence", None, XX, XX },
{ "mfence", None, XX, XX },
{ "sfence", None, XX, XX },
- /* FIXME: the sfence with memory operand is clflush! */
+ /* FIXME: the sfence with memory operand is clflush! */
},
/* GRP14 */
{
@@ -2574,7 +1446,6 @@ static const struct dis386 grps[][8] = {
{ "(bad)", XX, XX, XX },
{ "(bad)", XX, XX, XX },
}
-
};
static const struct dis386 prefix_user_table[][4] = {
@@ -2587,7 +1458,7 @@ static const struct dis386 prefix_user_table[][4] = {
},
/* PREGRP1 */
{
- { "", XM, EX, OPSIMD }, /* See OP_SIMD_SUFFIX */
+ { "", XM, EX, OPSIMD }, /* See OP_SIMD_SUFFIX. */
{ "", XM, EX, OPSIMD },
{ "", XM, EX, OPSIMD },
{ "", XM, EX, OPSIMD },
@@ -2769,6 +1640,13 @@ static const struct dis386 prefix_user_table[][4] = {
},
};
+static const struct dis386 x86_64_table[][2] = {
+ {
+ { "arpl", Ew, Gw, XX },
+ { "movs{||lq|xd}", Gv, Ed, XX },
+ },
+};
+
#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
static void
@@ -2940,10 +1818,9 @@ prefix_name (pref, sizeflag)
static char op1out[100], op2out[100], op3out[100];
static int op_ad, op_index[3];
-static unsigned int op_address[3];
-static unsigned int op_riprel[3];
+static bfd_vma op_address[3];
+static bfd_vma op_riprel[3];
static bfd_vma start_pc;
-
/*
* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
@@ -2954,9 +1831,6 @@ static bfd_vma start_pc;
* The function returns the length of this instruction in bytes.
*/
-static int print_insn_i386
- PARAMS ((bfd_vma pc, disassemble_info *info));
-
static char intel_syntax;
static char open_char;
static char close_char;
@@ -2969,6 +1843,13 @@ print_insn_i386_att (pc, info)
disassemble_info *info;
{
intel_syntax = 0;
+ names64 = att_names64;
+ names32 = att_names32;
+ names16 = att_names16;
+ names8 = att_names8;
+ names8rex = att_names8rex;
+ names_seg = att_names_seg;
+ index16 = att_index16;
open_char = '(';
close_char = ')';
separator_char = ',';
@@ -2983,6 +1864,13 @@ print_insn_i386_intel (pc, info)
disassemble_info *info;
{
intel_syntax = 1;
+ names64 = intel_names64;
+ names32 = intel_names32;
+ names16 = intel_names16;
+ names8 = intel_names8;
+ names8rex = intel_names8rex;
+ names_seg = intel_names_seg;
+ index16 = intel_index16;
open_char = '[';
close_char = ']';
separator_char = '+';
@@ -3015,7 +1903,7 @@ print_insn_i386 (pc, info)
|| info->mach == bfd_mach_x86_64
|| info->mach == bfd_mach_i386_i386_intel_syntax
|| info->mach == bfd_mach_x86_64_intel_syntax)
- sizeflag = AFLAG|DFLAG;
+ sizeflag = AFLAG | DFLAG;
else if (info->mach == bfd_mach_i386_i8086)
sizeflag = 0;
else
@@ -3092,25 +1980,13 @@ print_insn_i386 (pc, info)
if (*codep == 0x0f)
{
FETCH_DATA (info, codep + 2);
- if (intel_syntax)
- dp = &dis386_twobyte_intel[*++codep];
- else
- dp = &dis386_twobyte_att[*++codep];
+ dp = &dis386_twobyte[*++codep];
need_modrm = twobyte_has_modrm[*codep];
uses_SSE_prefix = twobyte_uses_SSE_prefix[*codep];
}
else
{
- if (intel_syntax)
- if (mode_64bit)
- dp = &dis386_64_intel[*codep];
- else
- dp = &dis386_intel[*codep];
- else
- if (mode_64bit)
- dp = &disx86_64_att[*codep];
- else
- dp = &dis386_att[*codep];
+ dp = &dis386[*codep];
need_modrm = onebyte_has_modrm[*codep];
uses_SSE_prefix = 0;
}
@@ -3135,7 +2011,7 @@ print_insn_i386 (pc, info)
if (prefixes & PREFIX_ADDR)
{
sizeflag ^= AFLAG;
- if (dp->bytemode2 != loop_jcxz_mode)
+ if (dp->bytemode3 != loop_jcxz_mode || intel_syntax)
{
if (sizeflag & AFLAG)
oappend ("addr32 ");
@@ -3148,7 +2024,9 @@ print_insn_i386 (pc, info)
if (!uses_SSE_prefix && (prefixes & PREFIX_DATA))
{
sizeflag ^= DFLAG;
- if (dp->bytemode2 == cond_jump_mode && dp->bytemode1 == v_mode)
+ if (dp->bytemode3 == cond_jump_mode
+ && dp->bytemode1 == v_mode
+ && !intel_syntax)
{
if (sizeflag & DFLAG)
oappend ("data32 ");
@@ -3158,20 +2036,6 @@ print_insn_i386 (pc, info)
}
}
- if (dp->bytemode2 == cond_jump_mode || dp->bytemode2 == loop_jcxz_mode)
- {
- if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS)
- {
- oappend ("cs ");
- used_prefixes |= PREFIX_CS;
- }
- if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
- {
- oappend ("ds ");
- used_prefixes |= PREFIX_DS;
- }
- }
-
if (need_modrm)
{
FETCH_DATA (info, codep + 1);
@@ -3189,52 +2053,59 @@ print_insn_i386 (pc, info)
int index;
if (dp->name == NULL)
{
- switch(dp->bytemode2)
+ switch (dp->bytemode1)
{
- case USE_GROUPS:
- dp = &grps[dp->bytemode1][reg];
- break;
- case USE_PREFIX_USER_TABLE:
- index = 0;
- used_prefixes |= (prefixes & PREFIX_REPZ);
- if (prefixes & PREFIX_REPZ)
- index = 1;
- else
- {
- used_prefixes |= (prefixes & PREFIX_DATA);
- if (prefixes & PREFIX_DATA)
- index = 2;
- else
- {
- used_prefixes |= (prefixes & PREFIX_REPNZ);
- if (prefixes & PREFIX_REPNZ)
- index = 3;
- }
- }
- dp = &prefix_user_table[dp->bytemode1][index];
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
- }
- }
-
- putop (dp->name, sizeflag);
+ case USE_GROUPS:
+ dp = &grps[dp->bytemode2][reg];
+ break;
+
+ case USE_PREFIX_USER_TABLE:
+ index = 0;
+ used_prefixes |= (prefixes & PREFIX_REPZ);
+ if (prefixes & PREFIX_REPZ)
+ index = 1;
+ else
+ {
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ if (prefixes & PREFIX_DATA)
+ index = 2;
+ else
+ {
+ used_prefixes |= (prefixes & PREFIX_REPNZ);
+ if (prefixes & PREFIX_REPNZ)
+ index = 3;
+ }
+ }
+ dp = &prefix_user_table[dp->bytemode2][index];
+ break;
- obufp = op1out;
- op_ad = 2;
- if (dp->op1)
- (*dp->op1)(dp->bytemode1, sizeflag);
+ case X86_64_SPECIAL:
+ dp = &x86_64_table[dp->bytemode2][mode_64bit];
+ break;
- obufp = op2out;
- op_ad = 1;
- if (dp->op2)
- (*dp->op2)(dp->bytemode2, sizeflag);
+ default:
+ oappend (INTERNAL_DISASSEMBLER_ERROR);
+ break;
+ }
+ }
- obufp = op3out;
- op_ad = 0;
- if (dp->op3)
- (*dp->op3)(dp->bytemode3, sizeflag);
+ if (putop (dp->name, sizeflag) == 0)
+ {
+ obufp = op1out;
+ op_ad = 2;
+ if (dp->op1)
+ (*dp->op1) (dp->bytemode1, sizeflag);
+
+ obufp = op2out;
+ op_ad = 1;
+ if (dp->op2)
+ (*dp->op2) (dp->bytemode2, sizeflag);
+
+ obufp = op3out;
+ op_ad = 0;
+ if (dp->op3)
+ (*dp->op3) (dp->bytemode3, sizeflag);
+ }
}
/* See if any prefixes were not used. If so, print the first one
@@ -3321,132 +2192,57 @@ print_insn_i386 (pc, info)
return codep - inbuf;
}
-static const char *float_mem_att[] = {
- /* d8 */
- "fadds",
- "fmuls",
- "fcoms",
- "fcomps",
- "fsubs",
- "fsubrs",
- "fdivs",
- "fdivrs",
- /* d9 */
- "flds",
- "(bad)",
- "fsts",
- "fstps",
- "fldenv",
- "fldcw",
- "fNstenv",
- "fNstcw",
- /* da */
- "fiaddl",
- "fimull",
- "ficoml",
- "ficompl",
- "fisubl",
- "fisubrl",
- "fidivl",
- "fidivrl",
- /* db */
- "fildl",
- "(bad)",
- "fistl",
- "fistpl",
- "(bad)",
- "fldt",
- "(bad)",
- "fstpt",
- /* dc */
- "faddl",
- "fmull",
- "fcoml",
- "fcompl",
- "fsubl",
- "fsubrl",
- "fdivl",
- "fdivrl",
- /* dd */
- "fldl",
- "(bad)",
- "fstl",
- "fstpl",
- "frstor",
- "(bad)",
- "fNsave",
- "fNstsw",
- /* de */
- "fiadd",
- "fimul",
- "ficom",
- "ficomp",
- "fisub",
- "fisubr",
- "fidiv",
- "fidivr",
- /* df */
- "fild",
- "(bad)",
- "fist",
- "fistp",
- "fbld",
- "fildll",
- "fbstp",
- "fistpll",
-};
-
-static const char *float_mem_intel[] = {
+static const char *float_mem[] = {
/* d8 */
- "fadd",
- "fmul",
- "fcom",
- "fcomp",
- "fsub",
- "fsubr",
- "fdiv",
- "fdivr",
+ "fadd{s||s|}",
+ "fmul{s||s|}",
+ "fcom{s||s|}",
+ "fcomp{s||s|}",
+ "fsub{s||s|}",
+ "fsubr{s||s|}",
+ "fdiv{s||s|}",
+ "fdivr{s||s|}",
/* d9 */
- "fld",
+ "fld{s||s|}",
"(bad)",
- "fst",
- "fstp",
+ "fst{s||s|}",
+ "fstp{s||s|}",
"fldenv",
"fldcw",
"fNstenv",
"fNstcw",
/* da */
- "fiadd",
- "fimul",
- "ficom",
- "ficomp",
- "fisub",
- "fisubr",
- "fidiv",
- "fidivr",
+ "fiadd{l||l|}",
+ "fimul{l||l|}",
+ "ficom{l||l|}",
+ "ficomp{l||l|}",
+ "fisub{l||l|}",
+ "fisubr{l||l|}",
+ "fidiv{l||l|}",
+ "fidivr{l||l|}",
/* db */
- "fild",
+ "fild{l||l|}",
"(bad)",
- "fist",
- "fistp",
+ "fist{l||l|}",
+ "fistp{l||l|}",
"(bad)",
- "fld",
+ "fld{t||t|}",
"(bad)",
- "fstp",
+ "fstp{t||t|}",
/* dc */
- "fadd",
- "fmul",
- "fcom",
- "fcomp",
- "fsub",
- "fsubr",
- "fdiv",
- "fdivr",
+ "fadd{l||l|}",
+ "fmul{l||l|}",
+ "fcom{l||l|}",
+ "fcomp{l||l|}",
+ "fsub{l||l|}",
+ "fsubr{l||l|}",
+ "fdiv{l||l|}",
+ "fdivr{l||l|}",
/* dd */
- "fld",
+ "fld{l||l|}",
"(bad)",
- "fst",
- "fstp",
+ "fst{l||l|}",
+ "fstp{l||l|}",
"frstor",
"(bad)",
"fNsave",
@@ -3466,7 +2262,7 @@ static const char *float_mem_intel[] = {
"fist",
"fistp",
"fbld",
- "fild",
+ "fild{ll||ll|}",
"fbstp",
"fistpll",
};
@@ -3589,7 +2385,6 @@ static const struct dis386 float_reg[][8] = {
},
};
-
static char *fgrps[][8] = {
/* d9_2 0 */
{
@@ -3649,10 +2444,7 @@ dofloat (sizeflag)
if (mod != 3)
{
- if (intel_syntax)
- putop (float_mem_intel[(floatop - 0xd8 ) * 8 + reg], sizeflag);
- else
- putop (float_mem_att[(floatop - 0xd8 ) * 8 + reg], sizeflag);
+ putop (float_mem[(floatop - 0xd8) * 8 + reg], sizeflag);
obufp = op1out;
if (floatop == 0xdb)
OP_E (x_mode, sizeflag);
@@ -3662,7 +2454,7 @@ dofloat (sizeflag)
OP_E (v_mode, sizeflag);
return;
}
- /* skip mod/rm byte */
+ /* Skip mod/rm byte. */
MODRM_CHECK;
codep++;
@@ -3671,7 +2463,7 @@ dofloat (sizeflag)
{
putop (fgrps[dp->bytemode1][rm], sizeflag);
- /* instruction fnstsw is only one with strange arg */
+ /* Instruction fnstsw is only one with strange arg. */
if (floatop == 0xdf && codep[-1] == 0xe0)
strcpy (op1out, names16[0]);
}
@@ -3681,40 +2473,38 @@ dofloat (sizeflag)
obufp = op1out;
if (dp->op1)
- (*dp->op1)(dp->bytemode1, sizeflag);
+ (*dp->op1) (dp->bytemode1, sizeflag);
obufp = op2out;
if (dp->op2)
- (*dp->op2)(dp->bytemode2, sizeflag);
+ (*dp->op2) (dp->bytemode2, sizeflag);
}
}
-/* ARGSUSED */
static void
-OP_ST (ignore, sizeflag)
- int ignore ATTRIBUTE_UNUSED;
+OP_ST (bytemode, sizeflag)
+ int bytemode ATTRIBUTE_UNUSED;
int sizeflag ATTRIBUTE_UNUSED;
{
oappend ("%st");
}
-/* ARGSUSED */
static void
-OP_STi (ignore, sizeflag)
- int ignore ATTRIBUTE_UNUSED;
+OP_STi (bytemode, sizeflag)
+ int bytemode ATTRIBUTE_UNUSED;
int sizeflag ATTRIBUTE_UNUSED;
{
sprintf (scratchbuf, "%%st(%d)", rm);
- oappend (scratchbuf);
+ oappend (scratchbuf + intel_syntax);
}
-
-/* capital letters in template are macros */
-static void
+/* Capital letters in template are macros. */
+static int
putop (template, sizeflag)
const char *template;
int sizeflag;
{
const char *p;
+ int alt;
for (p = template; *p; p++)
{
@@ -3723,6 +2513,38 @@ putop (template, sizeflag)
default:
*obufp++ = *p;
break;
+ case '{':
+ alt = 0;
+ if (intel_syntax)
+ alt += 1;
+ if (mode_64bit)
+ alt += 2;
+ while (alt != 0)
+ {
+ while (*++p != '|')
+ {
+ if (*p == '}')
+ {
+ /* Alternative not valid. */
+ strcpy (obuf, "(bad)");
+ obufp = obuf + 5;
+ return 1;
+ }
+ else if (*p == '\0')
+ abort ();
+ }
+ alt--;
+ }
+ break;
+ case '|':
+ while (*++p != '}')
+ {
+ if (*p == '\0')
+ abort ();
+ }
+ break;
+ case '}':
+ break;
case 'A':
if (intel_syntax)
break;
@@ -3747,6 +2569,8 @@ putop (template, sizeflag)
used_prefixes |= (prefixes & PREFIX_ADDR);
break;
case 'F':
+ if (intel_syntax)
+ break;
if ((prefixes & PREFIX_ADDR)
#ifdef SUFFIX_ALWAYS
|| (sizeflag & SUFFIX_ALWAYS)
@@ -3760,25 +2584,19 @@ putop (template, sizeflag)
used_prefixes |= (prefixes & PREFIX_ADDR);
}
break;
- case 'I':
+ case 'H':
if (intel_syntax)
break;
- if (mode_64bit)
- *obufp++ = 'q';
- else
+ if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
+ || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
{
- if ((prefixes & PREFIX_DATA)
-#ifdef SUFFIX_ALWAYS
- || (sizeflag & SUFFIX_ALWAYS)
-#endif
- )
- {
- if (sizeflag & DFLAG)
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
+ used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
+ *obufp++ = ',';
+ *obufp++ = 'p';
+ if (prefixes & PREFIX_DS)
+ *obufp++ = 't';
+ else
+ *obufp++ = 'n';
}
break;
case 'L':
@@ -3798,10 +2616,19 @@ putop (template, sizeflag)
case 'O':
USED_REX (REX_MODE64);
if (rex & REX_MODE64)
- *obufp++ = 'o';
+ *obufp++ = 'o';
else
*obufp++ = 'd';
break;
+ case 'T':
+ if (intel_syntax)
+ break;
+ if (mode_64bit)
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
case 'P':
if (intel_syntax)
break;
@@ -3825,6 +2652,15 @@ putop (template, sizeflag)
}
}
break;
+ case 'U':
+ if (intel_syntax)
+ break;
+ if (mode_64bit)
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
case 'Q':
if (intel_syntax)
break;
@@ -3898,24 +2734,6 @@ putop (template, sizeflag)
}
#endif
break;
- case 'T':
- if (intel_syntax)
- break;
- if (mode_64bit)
- *obufp++ = 'q';
- else if (mod != 3
-#ifdef SUFFIX_ALWAYS
- || (sizeflag & SUFFIX_ALWAYS)
-#endif
- )
- {
- if (sizeflag & DFLAG)
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
case 'X':
if (prefixes & PREFIX_DATA)
*obufp++ = 'd';
@@ -3965,6 +2783,7 @@ putop (template, sizeflag)
}
}
*obufp = 0;
+ return 0;
}
static void
@@ -3980,33 +2799,33 @@ append_seg ()
{
if (prefixes & PREFIX_CS)
{
- oappend ("%cs:");
used_prefixes |= PREFIX_CS;
+ oappend ("%cs:" + intel_syntax);
}
if (prefixes & PREFIX_DS)
{
- oappend ("%ds:");
used_prefixes |= PREFIX_DS;
+ oappend ("%ds:" + intel_syntax);
}
if (prefixes & PREFIX_SS)
{
- oappend ("%ss:");
used_prefixes |= PREFIX_SS;
+ oappend ("%ss:" + intel_syntax);
}
if (prefixes & PREFIX_ES)
{
- oappend ("%es:");
used_prefixes |= PREFIX_ES;
+ oappend ("%es:" + intel_syntax);
}
if (prefixes & PREFIX_FS)
{
- oappend ("%fs:");
used_prefixes |= PREFIX_FS;
+ oappend ("%fs:" + intel_syntax);
}
if (prefixes & PREFIX_GS)
{
- oappend ("%gs:");
used_prefixes |= PREFIX_GS;
+ oappend ("%gs:" + intel_syntax);
}
}
@@ -4035,7 +2854,7 @@ print_operand_value (buf, hex, disp)
buf[0] = '0';
buf[1] = 'x';
sprintf_vma (tmp, disp);
- for (i = 0; tmp[i] == '0' && tmp[i+1]; i++);
+ for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
strcpy (buf + 2, tmp + i);
}
else
@@ -4047,7 +2866,7 @@ print_operand_value (buf, hex, disp)
{
*(buf++) = '-';
v = -disp;
- /* Check for possible overflow on 0x8000000000000000 */
+ /* Check for possible overflow on 0x8000000000000000. */
if (v < 0)
{
strcpy (buf, "9223372036854775808");
@@ -4064,7 +2883,7 @@ print_operand_value (buf, hex, disp)
tmp[29] = 0;
while (v)
{
- tmp[28-i] = (v % 10) + '0';
+ tmp[28 - i] = (v % 10) + '0';
v /= 10;
i++;
}
@@ -4092,7 +2911,7 @@ OP_E (bytemode, sizeflag)
if (rex & REX_EXTZ)
add += 8;
- /* skip mod/rm byte */
+ /* Skip mod/rm byte. */
MODRM_CHECK;
codep++;
@@ -4133,10 +2952,10 @@ OP_E (bytemode, sizeflag)
used_prefixes |= (prefixes & PREFIX_DATA);
break;
case 0:
- if ( !(codep[-2] == 0xAE && codep[-1] == 0xF8 /* sfence */)
+ if (!(codep[-2] == 0xAE && codep[-1] == 0xF8 /* sfence */)
&& !(codep[-2] == 0xAE && codep[-1] == 0xF0 /* mfence */)
&& !(codep[-2] == 0xAE && codep[-1] == 0xe8 /* lfence */))
- BadOp(); /* bad sfence,lea,lds,les,lfs,lgs,lss modrm */
+ BadOp (); /* bad sfence,lea,lds,les,lfs,lgs,lss modrm */
break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
@@ -4261,10 +3080,12 @@ OP_E (bytemode, sizeflag)
*obufp++ = separator_char;
*obufp = '\0';
}
- sprintf (scratchbuf, "%s", mode_64bit ? names64[index] : names32[index]);
+ sprintf (scratchbuf, "%s",
+ mode_64bit ? names64[index] : names32[index]);
}
else
- sprintf (scratchbuf, ",%s", mode_64bit ? names64[index] : names32[index]);
+ sprintf (scratchbuf, ",%s",
+ mode_64bit ? names64[index] : names32[index]);
oappend (scratchbuf);
}
if (!intel_syntax
@@ -4282,9 +3103,15 @@ OP_E (bytemode, sizeflag)
if (intel_syntax)
if (mod != 0 || (base & 7) == 5)
{
- /* Don't print zero displacements */
+ /* Don't print zero displacements. */
if (disp != 0)
{
+ if ((bfd_signed_vma) disp > 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+
print_operand_value (scratchbuf, 0, disp);
oappend (scratchbuf);
}
@@ -4302,7 +3129,7 @@ OP_E (bytemode, sizeflag)
;
else
{
- oappend (names_seg[3]);
+ oappend (names_seg[ds_reg - es_reg]);
oappend (":");
}
print_operand_value (scratchbuf, 1, disp);
@@ -4399,23 +3226,24 @@ OP_G (bytemode, sizeflag)
static bfd_vma
get64 ()
{
- unsigned int a = 0;
- unsigned int b = 0;
- bfd_vma x = 0;
-
+ bfd_vma x;
#ifdef BFD64
+ unsigned int a;
+ unsigned int b;
+
FETCH_DATA (the_info, codep + 8);
a = *codep++ & 0xff;
a |= (*codep++ & 0xff) << 8;
a |= (*codep++ & 0xff) << 16;
a |= (*codep++ & 0xff) << 24;
- b |= (*codep++ & 0xff);
+ b = *codep++ & 0xff;
b |= (*codep++ & 0xff) << 8;
b |= (*codep++ & 0xff) << 16;
b |= (*codep++ & 0xff) << 24;
x = a + ((bfd_vma) b << 32);
#else
- abort();
+ abort ();
+ x = 0;
#endif
return x;
}
@@ -4462,12 +3290,21 @@ get16 ()
static void
set_op (op, riprel)
- unsigned int op;
+ bfd_vma op;
int riprel;
{
op_index[op_ad] = op_ad;
- op_address[op_ad] = op;
- op_riprel[op_ad] = riprel;
+ if (mode_64bit)
+ {
+ op_address[op_ad] = op;
+ op_riprel[op_ad] = riprel;
+ }
+ else
+ {
+ /* Mask to get a 32-bit address. */
+ op_address[op_ad] = op & 0xffffffff;
+ op_riprel[op_ad] = riprel & 0xffffffff;
+ }
}
static void
@@ -4484,7 +3321,10 @@ OP_REG (code, sizeflag)
switch (code)
{
case indir_dx_reg:
- s = "(%dx)";
+ if (intel_syntax)
+ s = "[dx]";
+ else
+ s = "(%dx)";
break;
case ax_reg: case cx_reg: case dx_reg: case bx_reg:
case sp_reg: case bp_reg: case si_reg: case di_reg:
@@ -4502,6 +3342,15 @@ OP_REG (code, sizeflag)
else
s = names8[code - al_reg];
break;
+ case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
+ case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
+ if (mode_64bit)
+ {
+ s = names64[code - rAX_reg + add];
+ break;
+ }
+ code += eAX_reg - rAX_reg;
+ /* Fall through. */
case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
USED_REX (REX_MODE64);
@@ -4513,10 +3362,6 @@ OP_REG (code, sizeflag)
s = names16[code - eAX_reg + add];
used_prefixes |= (prefixes & PREFIX_DATA);
break;
- case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
- case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
- s = names64[code - rAX_reg + add];
- break;
default:
s = INTERNAL_DISASSEMBLER_ERROR;
break;
@@ -4534,7 +3379,10 @@ OP_IMREG (code, sizeflag)
switch (code)
{
case indir_dx_reg:
- s = "(%dx)";
+ if (intel_syntax)
+ s = "[dx]";
+ else
+ s = "(%dx)";
break;
case ax_reg: case cx_reg: case dx_reg: case bx_reg:
case sp_reg: case bp_reg: case si_reg: case di_reg:
@@ -4586,8 +3434,12 @@ OP_I (bytemode, sizeflag)
mask = 0xff;
break;
case q_mode:
- op = get32s ();
- break;
+ if (mode_64bit)
+ {
+ op = get32s ();
+ break;
+ }
+ /* Fall through. */
case v_mode:
USED_REX (REX_MODE64);
if (rex & REX_MODE64)
@@ -4615,8 +3467,8 @@ OP_I (bytemode, sizeflag)
op &= mask;
scratchbuf[0] = '$';
- print_operand_value (scratchbuf + !intel_syntax, 1, op);
- oappend (scratchbuf);
+ print_operand_value (scratchbuf + 1, 1, op);
+ oappend (scratchbuf + intel_syntax);
scratchbuf[0] = '\0';
}
@@ -4628,6 +3480,12 @@ OP_I64 (bytemode, sizeflag)
bfd_signed_vma op;
bfd_signed_vma mask = -1;
+ if (!mode_64bit)
+ {
+ OP_I (bytemode, sizeflag);
+ return;
+ }
+
switch (bytemode)
{
case b_mode:
@@ -4662,8 +3520,8 @@ OP_I64 (bytemode, sizeflag)
op &= mask;
scratchbuf[0] = '$';
- print_operand_value (scratchbuf + !intel_syntax, 1, op);
- oappend (scratchbuf);
+ print_operand_value (scratchbuf + 1, 1, op);
+ oappend (scratchbuf + intel_syntax);
scratchbuf[0] = '\0';
}
@@ -4696,7 +3554,7 @@ OP_sI (bytemode, sizeflag)
else
{
mask = 0xffffffff;
- op = get16();
+ op = get16 ();
if ((op & 0x8000) != 0)
op -= 0x10000;
}
@@ -4715,7 +3573,7 @@ OP_sI (bytemode, sizeflag)
scratchbuf[0] = '$';
print_operand_value (scratchbuf + 1, 1, op);
- oappend (scratchbuf);
+ oappend (scratchbuf + intel_syntax);
}
static void
@@ -4724,7 +3582,7 @@ OP_J (bytemode, sizeflag)
int sizeflag;
{
bfd_vma disp;
- int mask = -1;
+ bfd_vma mask = -1;
switch (bytemode)
{
@@ -4740,7 +3598,7 @@ OP_J (bytemode, sizeflag)
else
{
disp = get16 ();
- /* for some reason, a data16 prefix on a jump instruction
+ /* For some reason, a data16 prefix on a jump instruction
means that the pc is masked to 16 bits after the
displacement is added! */
mask = 0xffff;
@@ -4756,20 +3614,14 @@ OP_J (bytemode, sizeflag)
oappend (scratchbuf);
}
-/* ARGSUSED */
static void
OP_SEG (dummy, sizeflag)
int dummy ATTRIBUTE_UNUSED;
int sizeflag ATTRIBUTE_UNUSED;
{
- static char *sreg[] = {
- "%es","%cs","%ss","%ds","%fs","%gs","%?","%?",
- };
-
- oappend (sreg[reg]);
+ oappend (names_seg[reg]);
}
-/* ARGSUSED */
static void
OP_DIR (dummy, sizeflag)
int dummy ATTRIBUTE_UNUSED;
@@ -4788,14 +3640,16 @@ OP_DIR (dummy, sizeflag)
seg = get16 ();
}
used_prefixes |= (prefixes & PREFIX_DATA);
- sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
+ if (intel_syntax)
+ sprintf (scratchbuf, "0x%x,0x%x", seg, offset);
+ else
+ sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
oappend (scratchbuf);
}
-/* ARGSUSED */
static void
-OP_OFF (ignored, sizeflag)
- int ignored ATTRIBUTE_UNUSED;
+OP_OFF (bytemode, sizeflag)
+ int bytemode ATTRIBUTE_UNUSED;
int sizeflag;
{
bfd_vma off;
@@ -4812,31 +3666,37 @@ OP_OFF (ignored, sizeflag)
if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
| PREFIX_ES | PREFIX_FS | PREFIX_GS)))
{
- oappend (names_seg[3]);
+ oappend (names_seg[ds_reg - es_reg]);
oappend (":");
}
}
print_operand_value (scratchbuf, 1, off);
oappend (scratchbuf);
}
-/* ARGSUSED */
+
static void
-OP_OFF64 (ignored, sizeflag)
- int ignored ATTRIBUTE_UNUSED;
+OP_OFF64 (bytemode, sizeflag)
+ int bytemode ATTRIBUTE_UNUSED;
int sizeflag ATTRIBUTE_UNUSED;
{
bfd_vma off;
+ if (!mode_64bit)
+ {
+ OP_OFF (bytemode, sizeflag);
+ return;
+ }
+
append_seg ();
- off = get64();
+ off = get64 ();
if (intel_syntax)
{
if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
| PREFIX_ES | PREFIX_FS | PREFIX_GS)))
{
- oappend (names_seg[3]);
+ oappend (names_seg[ds_reg - es_reg]);
oappend (":");
}
}
@@ -4850,7 +3710,11 @@ ptr_reg (code, sizeflag)
int sizeflag;
{
const char *s;
- oappend ("(");
+ if (intel_syntax)
+ oappend ("[");
+ else
+ oappend ("(");
+
USED_REX (REX_MODE64);
if (rex & REX_MODE64)
s = names64[code - eAX_reg];
@@ -4859,7 +3723,10 @@ ptr_reg (code, sizeflag)
else
s = names16[code - eAX_reg];
oappend (s);
- oappend (")");
+ if (intel_syntax)
+ oappend ("]");
+ else
+ oappend (")");
}
static void
@@ -4867,7 +3734,7 @@ OP_ESreg (code, sizeflag)
int code;
int sizeflag;
{
- oappend ("%es:");
+ oappend ("%es:" + intel_syntax);
ptr_reg (code, sizeflag);
}
@@ -4884,11 +3751,10 @@ OP_DSreg (code, sizeflag)
| PREFIX_FS
| PREFIX_GS)) == 0)
prefixes |= PREFIX_DS;
- append_seg();
+ append_seg ();
ptr_reg (code, sizeflag);
}
-/* ARGSUSED */
static void
OP_C (dummy, sizeflag)
int dummy ATTRIBUTE_UNUSED;
@@ -4898,11 +3764,10 @@ OP_C (dummy, sizeflag)
USED_REX (REX_EXTX);
if (rex & REX_EXTX)
add = 8;
- sprintf (scratchbuf, "%%cr%d", reg+add);
- oappend (scratchbuf);
+ sprintf (scratchbuf, "%%cr%d", reg + add);
+ oappend (scratchbuf + intel_syntax);
}
-/* ARGSUSED */
static void
OP_D (dummy, sizeflag)
int dummy ATTRIBUTE_UNUSED;
@@ -4912,18 +3777,20 @@ OP_D (dummy, sizeflag)
USED_REX (REX_EXTX);
if (rex & REX_EXTX)
add = 8;
- sprintf (scratchbuf, "%%db%d", reg+add);
+ if (intel_syntax)
+ sprintf (scratchbuf, "db%d", reg + add);
+ else
+ sprintf (scratchbuf, "%%db%d", reg + add);
oappend (scratchbuf);
}
-/* ARGSUSED */
static void
OP_T (dummy, sizeflag)
int dummy ATTRIBUTE_UNUSED;
int sizeflag ATTRIBUTE_UNUSED;
{
sprintf (scratchbuf, "%%tr%d", reg);
- oappend (scratchbuf);
+ oappend (scratchbuf + intel_syntax);
}
static void
@@ -4934,12 +3801,12 @@ OP_Rd (bytemode, sizeflag)
if (mod == 3)
OP_E (bytemode, sizeflag);
else
- BadOp();
+ BadOp ();
}
static void
-OP_MMX (ignore, sizeflag)
- int ignore ATTRIBUTE_UNUSED;
+OP_MMX (bytemode, sizeflag)
+ int bytemode ATTRIBUTE_UNUSED;
int sizeflag ATTRIBUTE_UNUSED;
{
int add = 0;
@@ -4951,7 +3818,7 @@ OP_MMX (ignore, sizeflag)
sprintf (scratchbuf, "%%xmm%d", reg + add);
else
sprintf (scratchbuf, "%%mm%d", reg + add);
- oappend (scratchbuf);
+ oappend (scratchbuf + intel_syntax);
}
static void
@@ -4964,7 +3831,7 @@ OP_XMM (bytemode, sizeflag)
if (rex & REX_EXTX)
add = 8;
sprintf (scratchbuf, "%%xmm%d", reg + add);
- oappend (scratchbuf);
+ oappend (scratchbuf + intel_syntax);
}
static void
@@ -4982,7 +3849,7 @@ OP_EM (bytemode, sizeflag)
if (rex & REX_EXTZ)
add = 8;
- /* skip mod/rm byte */
+ /* Skip mod/rm byte. */
MODRM_CHECK;
codep++;
used_prefixes |= (prefixes & PREFIX_DATA);
@@ -4990,7 +3857,7 @@ OP_EM (bytemode, sizeflag)
sprintf (scratchbuf, "%%xmm%d", rm + add);
else
sprintf (scratchbuf, "%%mm%d", rm + add);
- oappend (scratchbuf);
+ oappend (scratchbuf + intel_syntax);
}
static void
@@ -5008,11 +3875,11 @@ OP_EX (bytemode, sizeflag)
if (rex & REX_EXTZ)
add = 8;
- /* skip mod/rm byte */
+ /* Skip mod/rm byte. */
MODRM_CHECK;
codep++;
sprintf (scratchbuf, "%%xmm%d", rm + add);
- oappend (scratchbuf);
+ oappend (scratchbuf + intel_syntax);
}
static void
@@ -5023,7 +3890,7 @@ OP_MS (bytemode, sizeflag)
if (mod == 3)
OP_EM (bytemode, sizeflag);
else
- BadOp();
+ BadOp ();
}
static void
@@ -5034,7 +3901,7 @@ OP_XS (bytemode, sizeflag)
if (mod == 3)
OP_EX (bytemode, sizeflag);
else
- BadOp();
+ BadOp ();
}
static const char *Suffix3DNow[] = {
@@ -5115,7 +3982,7 @@ OP_3DNowSuffix (bytemode, sizeflag)
/* AMD 3DNow! instructions are specified by an opcode suffix in the
place where an 8-bit immediate would normally go. ie. the last
byte of the instruction. */
- obufp = obuf + strlen(obuf);
+ obufp = obuf + strlen (obuf);
mnemonic = Suffix3DNow[*codep++ & 0xff];
if (mnemonic)
oappend (mnemonic);
@@ -5127,12 +3994,11 @@ OP_3DNowSuffix (bytemode, sizeflag)
we have a bad opcode. This necessitates some cleaning up. */
op1out[0] = '\0';
op2out[0] = '\0';
- BadOp();
+ BadOp ();
}
}
-
-static const char *simd_cmp_op [] = {
+static const char *simd_cmp_op[] = {
"eq",
"lt",
"le",
@@ -5151,7 +4017,7 @@ OP_SIMD_Suffix (bytemode, sizeflag)
unsigned int cmp_type;
FETCH_DATA (the_info, codep + 1);
- obufp = obuf + strlen(obuf);
+ obufp = obuf + strlen (obuf);
cmp_type = *codep++ & 0xff;
if (cmp_type < 8)
{
@@ -5181,7 +4047,7 @@ OP_SIMD_Suffix (bytemode, sizeflag)
/* We have a bad extension byte. Clean up. */
op1out[0] = '\0';
op2out[0] = '\0';
- BadOp();
+ BadOp ();
}
}
@@ -5194,17 +4060,19 @@ SIMD_Fixup (extrachar, sizeflag)
forms of these instructions. */
if (mod == 3)
{
- char *p = obuf + strlen(obuf);
- *(p+1) = '\0';
- *p = *(p-1);
- *(p-1) = *(p-2);
- *(p-2) = *(p-3);
- *(p-3) = extrachar;
+ char *p = obuf + strlen (obuf);
+ *(p + 1) = '\0';
+ *p = *(p - 1);
+ *(p - 1) = *(p - 2);
+ *(p - 2) = *(p - 3);
+ *(p - 3) = extrachar;
}
}
-static void BadOp (void)
+static void
+BadOp (void)
{
- codep = insn_codep + 1; /* throw away prefixes and 1st. opcode byte */
+ /* Throw away prefixes and 1st. opcode byte. */
+ codep = insn_codep + 1;
oappend ("(bad)");
}
diff --git a/contrib/binutils/opcodes/ia64-asmtab.c b/contrib/binutils/opcodes/ia64-asmtab.c
index 03ec73c..45f60eb 100644
--- a/contrib/binutils/opcodes/ia64-asmtab.c
+++ b/contrib/binutils/opcodes/ia64-asmtab.c
@@ -4185,403 +4185,403 @@ completer_table[] = {
static const struct ia64_main_table
main_table[] = {
- { 5, 1, 1, 0x00000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, },
- { 5, 1, 1, 0x08000000ull, 0xf8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 1, },
- { 5, 7, 1, 0x00000000ull, 0x00000000ull, { 23, 65, 26, 0, 0 }, 0x0, 2, },
- { 5, 7, 1, 0x00000000ull, 0x00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 3, },
- { 6, 1, 1, 0x00000000ull, 0x00000000ull, { 23, 65, 26, 0, 0 }, 0x0, 4, },
- { 7, 1, 1, 0x40000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 5, },
- { 7, 1, 1, 0x00000000ull, 0x00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 6, },
- { 8, 1, 1, 0x00000000ull, 0x00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 7, },
- { 9, 3, 1, 0x00000000ull, 0x00000000ull, { 23, 2, 51, 52, 53 }, 0x221, 8, },
- { 10, 1, 1, 0x60000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 9, },
- { 10, 1, 1, 0x60000000ull, 0xf8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 10, },
- { 11, 1, 1, 0x68000000ull, 0xf8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 11, },
- { 11, 1, 1, 0x68000000ull, 0xf8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 12, },
- { 14, 4, 0, 0x00000000ull, 0xf80011ffull, { 15, 0, 0, 0, 0 }, 0x40, 814, },
- { 14, 4, 0, 0x00000000ull, 0xf80011c0ull, { 15, 0, 0, 0, 0 }, 0x0, 680, },
- { 14, 4, 0, 0x00000000ull, 0xf80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 681, },
- { 14, 4, 0, 0x08000100ull, 0xf80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 1843, },
- { 14, 4, 0, 0x08000100ull, 0xf80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 1844, },
- { 14, 4, 1, 0x00000000ull, 0x00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 437, },
- { 14, 4, 1, 0x00000000ull, 0x00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 438, },
- { 14, 4, 0, 0x00000000ull, 0x000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 835, },
- { 14, 4, 0, 0x00000000ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 682, },
- { 14, 4, 0, 0x00000000ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 683, },
- { 14, 4, 0, 0x00000080ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x210, 2479, },
- { 14, 4, 0, 0x00000080ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x250, 2480, },
- { 14, 4, 0, 0x00000140ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x30, 445, },
- { 14, 4, 0, 0x00000140ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x70, 446, },
- { 14, 4, 0, 0x00000180ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x230, 443, },
- { 14, 4, 0, 0x00000180ull, 0x000011c0ull, { 80, 0, 0, 0, 0 }, 0x270, 444, },
- { 14, 4, 1, 0x00000000ull, 0x00001000ull, { 14, 80, 0, 0, 0 }, 0x0, 439, },
- { 14, 4, 1, 0x00000000ull, 0x00001000ull, { 14, 80, 0, 0, 0 }, 0x40, 440, },
- { 15, 4, 0, 0x00000000ull, 0xf8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 393, },
- { 15, 5, 0, 0x00000000ull, 0xf8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 806, },
- { 15, 2, 0, 0x00000000ull, 0xf8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 949, },
- { 15, 3, 0, 0x00000000ull, 0xf8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 1038, },
- { 15, 6, 0, 0x00000000ull, 0xf8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 2483, },
- { 15, 7, 0, 0x00000000ull, 0x00000000ull, { 64, 0, 0, 0, 0 }, 0x0, 15, },
- { 16, 6, 0, 0x00000000ull, 0x000011ffull, { 81, 0, 0, 0, 0 }, 0x40, 868, },
- { 16, 6, 0, 0x00000000ull, 0x000011c0ull, { 81, 0, 0, 0, 0 }, 0x0, 684, },
- { 16, 6, 0, 0x00000000ull, 0x000011c0ull, { 81, 0, 0, 0, 0 }, 0x40, 685, },
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+ { 133, 3, 2, 0x000000d048000000ull, 0x000001fff8000000ull, { 17, 18, 32, 5, 0 }, 0x400, 90, },
+ { 134, 3, 2, 0x000000c0c8000000ull, 0x000001fff8000000ull, { 17, 18, 32, 0, 0 }, 0x0, 91, },
+ { 134, 3, 2, 0x000000d0c8000000ull, 0x000001fff8000000ull, { 17, 18, 32, 5, 0 }, 0x400, 92, },
+ { 135, 3, 2, 0x000000c088000000ull, 0x000001fff8000000ull, { 17, 18, 32, 0, 0 }, 0x0, 93, },
+ { 135, 3, 2, 0x000000d088000000ull, 0x000001fff8000000ull, { 17, 18, 32, 4, 0 }, 0x400, 94, },
+ { 136, 3, 1, 0x000000c080000000ull, 0x000001fff8000000ull, { 17, 32, 0, 0, 0 }, 0x0, 95, },
+ { 136, 3, 1, 0x000000d080000000ull, 0x000001fff8000000ull, { 17, 32, 24, 0, 0 }, 0x400, 96, },
+ { 136, 3, 1, 0x000000e080000000ull, 0x000001eff0000000ull, { 17, 32, 61, 0, 0 }, 0x400, 97, },
+ { 139, 3, 0, 0x000000cb00000000ull, 0x000001fff8000000ull, { 32, 0, 0, 0, 0 }, 0x0, 98, },
+ { 139, 3, 0, 0x000000db00000000ull, 0x000001fff8000000ull, { 32, 24, 0, 0, 0 }, 0x400, 99, },
+ { 139, 3, 0, 0x000000eb00000000ull, 0x000001eff0000000ull, { 32, 61, 0, 0, 0 }, 0x400, 100, },
+ { 140, 3, 0, 0x0000000050000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x21, 101, },
+ { 148, 3, 0, 0x0000000110000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 102, },
+ { 149, 2, 1, 0x000000e880000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 1820, },
+ { 150, 2, 1, 0x000000ea80000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 1821, },
+ { 151, 2, 1, 0x000000f880000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 1822, },
+ { 152, 1, 1, 0x0000010800000000ull, 0x000001fff80fe000ull, { 23, 25, 0, 0, 0 }, 0x0, 103, },
+ { 152, 1, 1, 0x0000010800000000ull, 0x000001ee07f00000ull, { 23, 62, 0, 0, 0 }, 0x40, 104, },
+ { 152, 1, 1, 0x0000012000000000ull, 0x000001e000300000ull, { 23, 65, 0, 0, 0 }, 0x40, 105, },
+ { 152, 5, 1, 0x0000000080000000ull, 0x000001e3f8000000ull, { 17, 19, 0, 0, 0 }, 0xc0, 106, },
+ { 152, 2, 1, 0x0000000e00100000ull, 0x000001ee00f00000ull, { 14, 24, 0, 0, 0 }, 0x40, 107, },
+ { 152, 2, 1, 0x0000000e00000000ull, 0x000001ee00f00000ull, { 14, 24, 77, 0, 0 }, 0x0, 2368, },
+ { 152, 2, 1, 0x0000000188000000ull, 0x000001eff8000000ull, { 23, 15, 0, 0, 0 }, 0x0, 109, },
+ { 152, 2, 1, 0x0000000600000000ull, 0x000001ee00000000ull, { 8, 24, 63, 0, 0 }, 0x0, 110, },
+ { 152, 2, 1, 0x0000000400000000ull, 0x000001ee00000000ull, { 9, 67, 0, 0, 0 }, 0x0, 111, },
+ { 152, 2, 1, 0x0000000180000000ull, 0x000001eff8000000ull, { 23, 7, 0, 0, 0 }, 0x0, 112, },
+ { 152, 2, 1, 0x0000000198000000ull, 0x000001eff8000000ull, { 23, 8, 0, 0, 0 }, 0x0, 113, },
+ { 152, 2, 1, 0x0000000150000000ull, 0x000001eff8000000ull, { 13, 24, 0, 0, 0 }, 0x0, 953, },
+ { 152, 2, 1, 0x0000000050000000ull, 0x000001eff8000000ull, { 13, 54, 0, 0, 0 }, 0x0, 954, },
+ { 152, 2, 1, 0x0000000190000000ull, 0x000001eff8000000ull, { 23, 13, 0, 0, 0 }, 0x0, 955, },
+ { 152, 3, 1, 0x0000000140000000ull, 0x000001eff8000000ull, { 13, 54, 0, 0, 0 }, 0x0, 1041, },
+ { 152, 3, 1, 0x0000002150000000ull, 0x000001eff8000000ull, { 13, 24, 0, 0, 0 }, 0x0, 1042, },
+ { 152, 3, 1, 0x0000002110000000ull, 0x000001eff8000000ull, { 23, 13, 0, 0, 0 }, 0x0, 1043, },
+ { 152, 3, 1, 0x0000002160000000ull, 0x000001eff8000000ull, { 16, 24, 0, 0, 0 }, 0x8, 114, },
+ { 152, 3, 1, 0x0000002120000000ull, 0x000001eff8000000ull, { 23, 16, 0, 0, 0 }, 0x8, 115, },
+ { 152, 3, 1, 0x0000002168000000ull, 0x000001eff8000000ull, { 11, 24, 0, 0, 0 }, 0x8, 116, },
+ { 152, 3, 1, 0x0000002148000000ull, 0x000001eff8000000ull, { 12, 24, 0, 0, 0 }, 0x0, 117, },
+ { 152, 3, 1, 0x0000002128000000ull, 0x000001eff8000000ull, { 23, 10, 0, 0, 0 }, 0x8, 118, },
+ { 152, 3, 1, 0x0000002108000000ull, 0x000001eff8000000ull, { 23, 12, 0, 0, 0 }, 0x0, 119, },
+ { 152, 3, 1, 0x0000002000000000ull, 0x000001eff8000000ull, { 37, 24, 0, 0, 0 }, 0x8, 120, },
+ { 152, 3, 1, 0x0000002008000000ull, 0x000001eff8000000ull, { 28, 24, 0, 0, 0 }, 0x8, 121, },
+ { 152, 3, 1, 0x0000002010000000ull, 0x000001eff8000000ull, { 31, 24, 0, 0, 0 }, 0x8, 122, },
+ { 152, 3, 1, 0x0000002018000000ull, 0x000001eff8000000ull, { 34, 24, 0, 0, 0 }, 0x8, 123, },
+ { 152, 3, 1, 0x0000002020000000ull, 0x000001eff8000000ull, { 35, 24, 0, 0, 0 }, 0x8, 124, },
+ { 152, 3, 1, 0x0000002028000000ull, 0x000001eff8000000ull, { 36, 24, 0, 0, 0 }, 0x8, 125, },
+ { 152, 3, 1, 0x0000002030000000ull, 0x000001eff8000000ull, { 33, 24, 0, 0, 0 }, 0x8, 126, },
+ { 152, 3, 1, 0x0000002080000000ull, 0x000001eff8000000ull, { 23, 37, 0, 0, 0 }, 0x8, 127, },
+ { 152, 3, 1, 0x0000002088000000ull, 0x000001eff8000000ull, { 23, 28, 0, 0, 0 }, 0x8, 128, },
+ { 152, 3, 1, 0x0000002090000000ull, 0x000001eff8000000ull, { 23, 31, 0, 0, 0 }, 0x8, 129, },
+ { 152, 3, 1, 0x0000002098000000ull, 0x000001eff8000000ull, { 23, 34, 0, 0, 0 }, 0x8, 130, },
+ { 152, 3, 1, 0x00000020a0000000ull, 0x000001eff8000000ull, { 23, 35, 0, 0, 0 }, 0x8, 131, },
+ { 152, 3, 1, 0x00000020a8000000ull, 0x000001eff8000000ull, { 23, 36, 0, 0, 0 }, 0x0, 132, },
+ { 152, 3, 1, 0x00000020b0000000ull, 0x000001eff8000000ull, { 23, 33, 0, 0, 0 }, 0x8, 133, },
+ { 152, 3, 1, 0x00000020b8000000ull, 0x000001eff8000000ull, { 23, 27, 0, 0, 0 }, 0x0, 134, },
+ { 152, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 23, 13, 0, 0, 0 }, 0x0, 135, },
+ { 152, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 13, 54, 0, 0, 0 }, 0x0, 136, },
+ { 152, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 13, 24, 0, 0, 0 }, 0x0, 137, },
+ { 153, 6, 1, 0x000000c000000000ull, 0x000001e000100000ull, { 23, 69, 0, 0, 0 }, 0x0, 138, },
+ { 154, 2, 1, 0x000000eca0000000ull, 0x000001fff0000000ull, { 23, 24, 73, 0, 0 }, 0x0, 139, },
+ { 155, 2, 1, 0x000000eea0000000ull, 0x000001fff0000000ull, { 23, 24, 74, 0, 0 }, 0x0, 140, },
+ { 165, 4, 0, 0x0000004000000000ull, 0x000001e1f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 394, },
+ { 165, 5, 0, 0x0000000008000000ull, 0x000001e3f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 807, },
+ { 165, 2, 0, 0x0000000008000000ull, 0x000001eff8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 956, },
+ { 165, 3, 0, 0x0000000008000000ull, 0x000001eff8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 1044, },
+ { 165, 6, 0, 0x0000000008000000ull, 0x000001eff8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 2484, },
+ { 165, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 64, 0, 0, 0, 0 }, 0x0, 141, },
+ { 172, 1, 1, 0x0000010070000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 142, },
+ { 172, 1, 1, 0x0000010170000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 143, },
+ { 175, 2, 1, 0x000000ea00000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 2467, },
+ { 176, 2, 1, 0x000000f820000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 2370, },
+ { 177, 1, 1, 0x0000010400000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 144, },
+ { 178, 1, 1, 0x0000010600000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 145, },
+ { 179, 1, 1, 0x0000011400000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 146, },
+ { 180, 1, 1, 0x0000010450000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 147, },
+ { 181, 1, 1, 0x0000010650000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 148, },
+ { 182, 1, 1, 0x0000010470000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 149, },
+ { 183, 1, 1, 0x0000010670000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 150, },
+ { 184, 1, 1, 0x0000010520000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 794, },
+ { 185, 1, 1, 0x0000010720000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 795, },
+ { 186, 1, 1, 0x0000011520000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 796, },
+ { 187, 2, 1, 0x000000e850000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 2384, },
+ { 188, 2, 1, 0x000000ea70000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 151, },
+ { 189, 2, 1, 0x000000e810000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 2385, },
+ { 190, 2, 1, 0x000000ea30000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 152, },
+ { 191, 2, 1, 0x000000ead0000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 1823, },
+ { 192, 2, 1, 0x000000e230000000ull, 0x000001ff30000000ull, { 23, 24, 25, 41, 0 }, 0x0, 153, },
+ { 193, 2, 1, 0x000000e690000000ull, 0x000001fff0000000ull, { 23, 25, 0, 0, 0 }, 0x0, 154, },
+ { 195, 3, 1, 0x00000021c0000000ull, 0x000001eff8000000ull, { 23, 25, 24, 0, 0 }, 0x0, 1824, },
+ { 195, 3, 1, 0x00000020c0000000ull, 0x000001eff8000000ull, { 23, 25, 48, 0, 0 }, 0x0, 1825, },
+ { 195, 3, 0, 0x0000002188000000ull, 0x000001eff8000000ull, { 25, 48, 0, 0, 0 }, 0x0, 1847, },
+ { 196, 2, 1, 0x000000e8b0000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 155, },
+ { 197, 2, 1, 0x000000e240000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 156, },
+ { 197, 2, 1, 0x000000ee50000000ull, 0x000001fff0000000ull, { 23, 24, 38, 0, 0 }, 0x0, 157, },
+ { 198, 2, 1, 0x000000f040000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 158, },
+ { 198, 2, 1, 0x000000fc50000000ull, 0x000001fff0000000ull, { 23, 24, 38, 0, 0 }, 0x0, 159, },
+ { 199, 1, 1, 0x0000010680000000ull, 0x000001ffe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 160, },
+ { 200, 2, 1, 0x000000e220000000ull, 0x000001fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 161, },
+ { 200, 2, 1, 0x000000e630000000ull, 0x000001fff0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 162, },
+ { 201, 2, 1, 0x000000f020000000ull, 0x000001fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 163, },
+ { 201, 2, 1, 0x000000f430000000ull, 0x000001fff0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 164, },
+ { 202, 1, 1, 0x00000106c0000000ull, 0x000001ffe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 165, },
+ { 203, 1, 1, 0x0000010420000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 166, },
+ { 204, 1, 1, 0x0000010620000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 167, },
+ { 205, 1, 1, 0x0000011420000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 168, },
+ { 206, 3, 0, 0x0000002048000000ull, 0x000001eff8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 984, },
+ { 206, 3, 0, 0x0000002050000000ull, 0x000001eff8000000ull, { 25, 24, 0, 0, 0 }, 0xc, 895, },
+ { 206, 3, 0, 0x00000021a0000000ull, 0x000001eff8000000ull, { 25, 0, 0, 0, 0 }, 0x8, 777, },
+ { 207, 3, 0, 0x0000002060000000ull, 0x000001eff8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 703, },
+ { 212, 4, 0, 0x0000000040000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x22c, 169, },
+ { 213, 3, 0, 0x0000000038000000ull, 0x000001ee78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 170, },
+ { 214, 3, 0, 0x0000000028000000ull, 0x000001ee78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 171, },
+ { 223, 3, 1, 0x000000c708000000ull, 0x000001ffc8000000ull, { 17, 24, 0, 0, 0 }, 0x0, 2295, },
+ { 224, 2, 1, 0x000000a600000000ull, 0x000001ee04000000ull, { 23, 24, 44, 0, 0 }, 0x140, 172, },
+ { 224, 2, 1, 0x000000f240000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 173, },
+ { 225, 1, 1, 0x0000010080000000ull, 0x000001efe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 174, },
+ { 226, 1, 1, 0x00000100c0000000ull, 0x000001efe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 175, },
+ { 227, 2, 1, 0x000000a400000000ull, 0x000001ee00002000ull, { 23, 25, 75, 0, 0 }, 0x140, 2391, },
+ { 227, 2, 1, 0x000000f220000000ull, 0x000001fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 177, },
+ { 228, 2, 1, 0x000000ac00000000ull, 0x000001ee00000000ull, { 23, 24, 25, 43, 0 }, 0x0, 178, },
+ { 233, 3, 0, 0x0000000180000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 705, },
+ { 234, 3, 0, 0x0000000030000000ull, 0x000001ee78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 179, },
+ { 236, 3, 1, 0x0000008c00000000ull, 0x000001fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 180, },
+ { 236, 3, 1, 0x000000ac00000000ull, 0x000001eff0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 181, },
+ { 237, 3, 1, 0x0000008c40000000ull, 0x000001fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 182, },
+ { 237, 3, 1, 0x000000ac40000000ull, 0x000001eff0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 183, },
+ { 238, 3, 1, 0x0000008c80000000ull, 0x000001fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 184, },
+ { 238, 3, 1, 0x000000ac80000000ull, 0x000001eff0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 185, },
+ { 239, 3, 1, 0x0000008cc0000000ull, 0x000001fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 186, },
+ { 239, 3, 1, 0x000000acc0000000ull, 0x000001eff0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 187, },
+ { 240, 3, 1, 0x000000cec0000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 2298, },
+ { 240, 3, 1, 0x000000eec0000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 2299, },
+ { 241, 3, 1, 0x000000cc40000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 188, },
+ { 241, 3, 1, 0x000000ec40000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 189, },
+ { 242, 3, 1, 0x000000ccc0000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 190, },
+ { 242, 3, 1, 0x000000ecc0000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 191, },
+ { 243, 3, 1, 0x000000cc00000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 192, },
+ { 243, 3, 1, 0x000000ec00000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 193, },
+ { 244, 3, 1, 0x000000cc80000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 194, },
+ { 244, 3, 1, 0x000000ec80000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 195, },
+ { 245, 1, 1, 0x0000010028000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 196, },
+ { 245, 1, 1, 0x0000010020000000ull, 0x000001eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 197, },
+ { 245, 1, 1, 0x0000010128000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 198, },
+ { 246, 3, 0, 0x0000000020000000ull, 0x000001ee78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 199, },
+ { 247, 2, 1, 0x00000000a0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 200, },
+ { 248, 2, 1, 0x00000000a8000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 201, },
+ { 249, 2, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 202, },
+ { 250, 3, 0, 0x0000000198000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 959, },
+ { 251, 3, 1, 0x00000020f8000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 203, },
+ { 252, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 21, 22, 25, 75, 0 }, 0x0, 2489, },
+ { 252, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 21, 25, 75, 0 }, 0x40, 1724, },
+ { 253, 3, 1, 0x00000020d0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 204, },
+ { 254, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 21, 22, 25, 0, 0 }, 0x0, 2491, },
+ { 254, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 21, 25, 0, 0 }, 0x40, 1726, },
+ { 255, 3, 1, 0x00000020f0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 205, },
+ { 257, 3, 1, 0x00000020d8000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 206, },
+ { 261, 2, 1, 0x000000e840000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 942, },
+ { 262, 2, 1, 0x000000ea40000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 943, },
+ { 263, 2, 1, 0x000000f840000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 944, },
+ { 271, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 207, },
+ { 272, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 208, },
+ { 273, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 209, },
+ { 274, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 210, },
+ { 276, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 988, },
+ { 276, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 1036, },
+ { 277, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 989, },
+ { 278, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 211, },
+ { 278, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 212, },
+ { 281, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 213, },
+ { 282, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 214, },
+ { 283, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 215, },
};
static const char dis_table[] = {
diff --git a/contrib/binutils/opcodes/sh-dis.c b/contrib/binutils/opcodes/sh-dis.c
index c4e960c..7091afc 100644
--- a/contrib/binutils/opcodes/sh-dis.c
+++ b/contrib/binutils/opcodes/sh-dis.c
@@ -1,5 +1,6 @@
/* Disassemble SH instructions.
- Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
+ Copyright 1993, 1994, 1995, 1997, 1998, 2000
+ Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -15,8 +16,8 @@ You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-#include "sysdep.h"
#include <stdio.h>
+#include "sysdep.h"
#define STATIC_TABLE
#define DEFINE_TABLE
@@ -34,22 +35,22 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
{
int n;
- fprintf_fn (stream,"%s\t", op->name);
+ fprintf_fn (stream, "%s\t", op->name);
for (n = 0; n < 2; n++)
{
switch (op->arg[n])
{
case A_IND_N:
- fprintf_fn (stream, "@r%d", rn);
+ fprintf_fn (stream, "@r%d", rn);
break;
case A_INC_N:
- fprintf_fn (stream, "@r%d+", rn);
+ fprintf_fn (stream, "@r%d+", rn);
break;
case A_PMOD_N:
- fprintf_fn (stream, "@r%d+r8", rn);
+ fprintf_fn (stream, "@r%d+r8", rn);
break;
case A_PMODY_N:
- fprintf_fn (stream, "@r%d+r9", rn);
+ fprintf_fn (stream, "@r%d+r9", rn);
break;
case DSP_REG_M:
fprintf_fn (stream, "a%c", '0' + rm);
@@ -64,7 +65,7 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
abort ();
}
if (n == 0)
- fprintf_fn (stream, ",");
+ fprintf_fn (stream, ",");
}
}
@@ -72,6 +73,7 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
nibbles of the insn, i.e. field a and the bit that indicates if
a parallel processing insn follows.
Return nonzero if a field b of a parallel processing insns follows. */
+
static void
print_insn_ddt (insn, info)
int insn;
@@ -97,19 +99,20 @@ print_insn_ddt (insn, info)
{
static sh_opcode_info *first_movx, *first_movy;
sh_opcode_info *opx, *opy;
- int insn_x, insn_y;
+ unsigned int insn_x, insn_y;
if (! first_movx)
{
- for (first_movx = sh_table; first_movx->nibbles[1] != MOVX; )
+ for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
first_movx++;
- for (first_movy = first_movx; first_movy->nibbles[1] != MOVY; )
+ for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
first_movy++;
}
insn_x = (insn >> 2) & 0xb;
if (insn_x)
{
- for (opx = first_movx; opx->nibbles[2] != insn_x; ) opx++;
+ for (opx = first_movx; opx->nibbles[2] != insn_x;)
+ opx++;
print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
fprintf_fn, stream);
}
@@ -118,7 +121,8 @@ print_insn_ddt (insn, info)
{
if (insn_x)
fprintf_fn (stream, "\t");
- for (opy = first_movy; opy->nibbles[2] != insn_y; ) opy++;
+ for (opy = first_movy; opy->nibbles[2] != insn_y;)
+ opy++;
print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
fprintf_fn, stream);
}
@@ -174,12 +178,12 @@ print_insn_ppi (field_b, info)
int field_b;
struct disassemble_info *info;
{
- static char *sx_tab[] = {"x0","x1","a0","a1"};
- static char *sy_tab[] = {"y0","y1","m0","m1"};
+ static char *sx_tab[] = { "x0", "x1", "a0", "a1" };
+ static char *sy_tab[] = { "y0", "y1", "m0", "m1" };
fprintf_ftype fprintf_fn = info->fprintf_func;
void *stream = info->stream;
- int nib1, nib2, nib3;
- char *dc;
+ unsigned int nib1, nib2, nib3;
+ char *dc = NULL;
sh_opcode_info *op;
if ((field_b & 0xe800) == 0)
@@ -192,10 +196,10 @@ print_insn_ppi (field_b, info)
}
if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
{
- static char *du_tab[] = {"x0","y0","a0","a1"};
- static char *se_tab[] = {"x0","x1","y0","a1"};
- static char *sf_tab[] = {"y0","y1","x0","a1"};
- static char *sg_tab[] = {"m0","m1","a0","a1"};
+ static char *du_tab[] = { "x0", "y0", "a0", "a1" };
+ static char *se_tab[] = { "x0", "x1", "y0", "a1" };
+ static char *sf_tab[] = { "y0", "y1", "x0", "a1" };
+ static char *sg_tab[] = { "m0", "m1", "a0", "a1" };
if (field_b & 0x2000)
{
@@ -243,11 +247,11 @@ print_insn_ppi (field_b, info)
int n;
fprintf_fn (stream, "%s%s\t", dc, op->name);
- for (n = 0; n < 3 && op->arg[n] != A_END; n++)
+ for (n = 0; n < 3 && op->arg[n] != A_END; n++)
{
if (n && op->arg[1] != A_END)
fprintf_fn (stream, ",");
- switch (op->arg[n])
+ switch (op->arg[n])
{
case DSP_REG_N:
print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
@@ -262,7 +266,7 @@ print_insn_ppi (field_b, info)
fprintf_fn (stream, "mach");
break;
case A_MACL:
- fprintf_fn (stream ,"macl");
+ fprintf_fn (stream, "macl");
break;
default:
abort ();
@@ -275,7 +279,7 @@ print_insn_ppi (field_b, info)
fprintf_fn (stream, ".word 0x%x", field_b);
}
-static int
+static int
print_insn_shx (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
@@ -285,7 +289,7 @@ print_insn_shx (memaddr, info)
unsigned char insn[2];
unsigned char nibs[4];
int status;
- bfd_vma relmask = ~ (bfd_vma) 0;
+ bfd_vma relmask = ~(bfd_vma) 0;
sh_opcode_info *op;
int target_arch;
@@ -318,13 +322,13 @@ print_insn_shx (memaddr, info)
status = info->read_memory_func (memaddr, insn, 2, info);
- if (status != 0)
+ if (status != 0)
{
info->memory_error_func (status, memaddr, info);
return -1;
}
- if (info->flags & LITTLE_BIT)
+ if (info->flags & LITTLE_BIT)
{
nibs[0] = (insn[1] >> 4) & 0xf;
nibs[1] = insn[1] & 0xf;
@@ -332,7 +336,7 @@ print_insn_shx (memaddr, info)
nibs[2] = (insn[0] >> 4) & 0xf;
nibs[3] = insn[0] & 0xf;
}
- else
+ else
{
nibs[0] = (insn[0] >> 4) & 0xf;
nibs[1] = insn[0] & 0xf;
@@ -349,13 +353,13 @@ print_insn_shx (memaddr, info)
status = info->read_memory_func (memaddr + 2, insn, 2, info);
- if (status != 0)
+ if (status != 0)
{
info->memory_error_func (status, memaddr + 2, info);
return -1;
}
- if (info->flags & LITTLE_BIT)
+ if (info->flags & LITTLE_BIT)
field_b = insn[1] << 8 | insn[0];
else
field_b = insn[0] << 8 | insn[1];
@@ -367,7 +371,7 @@ print_insn_shx (memaddr, info)
print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
return 2;
}
- for (op = sh_table; op->name; op++)
+ for (op = sh_table; op->name; op++)
{
int n;
int imm = 0;
@@ -383,7 +387,7 @@ print_insn_shx (memaddr, info)
{
int i = op->nibbles[n];
- if (i < 16)
+ if (i < 16)
{
if (nibs[n] == i)
continue;
@@ -392,10 +396,10 @@ print_insn_shx (memaddr, info)
switch (i)
{
case BRANCH_8:
- imm = (nibs[2] << 4) | (nibs[3]);
+ imm = (nibs[2] << 4) | (nibs[3]);
if (imm & 0x80)
imm |= ~0xff;
- imm = ((char)imm) * 2 + 4 ;
+ imm = ((char) imm) * 2 + 4;
goto ok;
case BRANCH_12:
imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
@@ -403,37 +407,37 @@ print_insn_shx (memaddr, info)
imm |= ~0xfff;
imm = imm * 2 + 4;
goto ok;
- case IMM_4:
+ case IMM0_4:
+ case IMM1_4:
imm = nibs[3];
goto ok;
- case IMM_4BY2:
- imm = nibs[3] <<1;
+ case IMM0_4BY2:
+ case IMM1_4BY2:
+ imm = nibs[3] << 1;
goto ok;
- case IMM_4BY4:
- imm = nibs[3] <<2;
+ case IMM0_4BY4:
+ case IMM1_4BY4:
+ imm = nibs[3] << 2;
goto ok;
- case IMM_8:
+ case IMM0_8:
+ case IMM1_8:
imm = (nibs[2] << 4) | nibs[3];
goto ok;
case PCRELIMM_8BY2:
- imm = ((nibs[2] << 4) | nibs[3]) <<1;
- relmask = ~ (bfd_vma) 1;
+ imm = ((nibs[2] << 4) | nibs[3]) << 1;
+ relmask = ~(bfd_vma) 1;
goto ok;
case PCRELIMM_8BY4:
- imm = ((nibs[2] << 4) | nibs[3]) <<2;
- relmask = ~ (bfd_vma) 3;
- goto ok;
- case IMM_8BY2:
- imm = ((nibs[2] << 4) | nibs[3]) <<1;
+ imm = ((nibs[2] << 4) | nibs[3]) << 2;
+ relmask = ~(bfd_vma) 3;
goto ok;
- case IMM_8BY4:
- imm = ((nibs[2] << 4) | nibs[3]) <<2;
+ case IMM0_8BY2:
+ case IMM1_8BY2:
+ imm = ((nibs[2] << 4) | nibs[3]) << 1;
goto ok;
- case DISP_8:
- imm = (nibs[2] << 4) | (nibs[3]);
- goto ok;
- case DISP_4:
- imm = nibs[3];
+ case IMM0_8BY4:
+ case IMM1_8BY4:
+ imm = ((nibs[2] << 4) | nibs[3]) << 2;
goto ok;
case REG_N:
rn = nibs[n];
@@ -447,33 +451,34 @@ print_insn_shx (memaddr, info)
break;
case REG_B:
rb = nibs[n] & 0x07;
- break;
+ break;
case SDT_REG_N:
/* sh-dsp: single data transfer. */
rn = nibs[n];
if ((rn & 0xc) != 4)
goto fail;
rn = rn & 0x3;
- rn |= (rn & 2) << 1;
+ rn |= (!(rn & 2)) << 2;
break;
case PPI:
+ case REPEAT:
goto fail;
default:
- abort();
+ abort ();
}
}
ok:
- fprintf_fn (stream,"%s\t", op->name);
+ fprintf_fn (stream, "%s\t", op->name);
disp_pc = 0;
- for (n = 0; n < 3 && op->arg[n] != A_END; n++)
+ for (n = 0; n < 3 && op->arg[n] != A_END; n++)
{
if (n && op->arg[1] != A_END)
fprintf_fn (stream, ",");
- switch (op->arg[n])
+ switch (op->arg[n])
{
case A_IMM:
- fprintf_fn (stream, "#%d", (char)(imm));
+ fprintf_fn (stream, "#%d", (char) (imm));
break;
case A_R0:
fprintf_fn (stream, "r0");
@@ -482,34 +487,34 @@ print_insn_shx (memaddr, info)
fprintf_fn (stream, "r%d", rn);
break;
case A_INC_N:
- fprintf_fn (stream, "@r%d+", rn);
+ fprintf_fn (stream, "@r%d+", rn);
break;
case A_DEC_N:
- fprintf_fn (stream, "@-r%d", rn);
+ fprintf_fn (stream, "@-r%d", rn);
break;
case A_IND_N:
- fprintf_fn (stream, "@r%d", rn);
+ fprintf_fn (stream, "@r%d", rn);
break;
case A_DISP_REG_N:
- fprintf_fn (stream, "@(%d,r%d)", imm, rn);
+ fprintf_fn (stream, "@(%d,r%d)", imm, rn);
break;
case A_PMOD_N:
- fprintf_fn (stream, "@r%d+r8", rn);
+ fprintf_fn (stream, "@r%d+r8", rn);
break;
case A_REG_M:
fprintf_fn (stream, "r%d", rm);
break;
case A_INC_M:
- fprintf_fn (stream, "@r%d+", rm);
+ fprintf_fn (stream, "@r%d+", rm);
break;
case A_DEC_M:
- fprintf_fn (stream, "@-r%d", rm);
+ fprintf_fn (stream, "@-r%d", rm);
break;
case A_IND_M:
- fprintf_fn (stream, "@r%d", rm);
+ fprintf_fn (stream, "@r%d", rm);
break;
case A_DISP_REG_M:
- fprintf_fn (stream, "@(%d,r%d)", imm, rm);
+ fprintf_fn (stream, "@(%d,r%d)", imm, rm);
break;
case A_REG_B:
fprintf_fn (stream, "r%d_bank", rb);
@@ -521,12 +526,12 @@ print_insn_shx (memaddr, info)
break;
case A_IND_R0_REG_N:
fprintf_fn (stream, "@(r0,r%d)", rn);
- break;
+ break;
case A_IND_R0_REG_M:
fprintf_fn (stream, "@(r0,r%d)", rm);
- break;
+ break;
case A_DISP_GBR:
- fprintf_fn (stream, "@(%d,gbr)",imm);
+ fprintf_fn (stream, "@(%d,gbr)", imm);
break;
case A_R0_GBR:
fprintf_fn (stream, "@(r0,gbr)");
@@ -584,7 +589,7 @@ print_insn_shx (memaddr, info)
fprintf_fn (stream, "mach");
break;
case A_MACL:
- fprintf_fn (stream ,"macl");
+ fprintf_fn (stream, "macl");
break;
case A_PR:
fprintf_fn (stream, "pr");
@@ -607,7 +612,6 @@ print_insn_shx (memaddr, info)
fprintf_fn (stream, "xd%d", rn & ~1);
break;
}
- d_reg_n:
case D_REG_N:
fprintf_fn (stream, "dr%d", rn);
break;
@@ -632,16 +636,16 @@ print_insn_shx (memaddr, info)
fprintf_fn (stream, "fr0");
break;
case V_REG_N:
- fprintf_fn (stream, "fv%d", rn*4);
+ fprintf_fn (stream, "fv%d", rn * 4);
break;
case V_REG_M:
- fprintf_fn (stream, "fv%d", rm*4);
+ fprintf_fn (stream, "fv%d", rm * 4);
break;
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
default:
- abort();
+ abort ();
}
}
@@ -654,7 +658,7 @@ print_insn_shx (memaddr, info)
if (!(info->flags & 1)
&& (op->name[0] == 'j'
|| (op->name[0] == 'b'
- && (op->name[1] == 'r'
+ && (op->name[1] == 'r'
|| op->name[1] == 's'))
|| (op->name[0] == 'r' && op->name[1] == 't')
|| (op->name[0] == 'b' && op->name[2] == '.')))
@@ -673,7 +677,7 @@ print_insn_shx (memaddr, info)
int size;
bfd_byte bytes[4];
- if (relmask == ~ (bfd_vma) 1)
+ if (relmask == ~(bfd_vma) 1)
size = 2;
else
size = 4;
@@ -709,7 +713,7 @@ print_insn_shx (memaddr, info)
return 2;
}
-int
+int
print_insn_shl (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
@@ -721,7 +725,7 @@ print_insn_shl (memaddr, info)
return r;
}
-int
+int
print_insn_sh (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
diff --git a/contrib/binutils/opcodes/sh-opc.h b/contrib/binutils/opcodes/sh-opc.h
index 38bfbcd..4128c08 100644
--- a/contrib/binutils/opcodes/sh-opc.h
+++ b/contrib/binutils/opcodes/sh-opc.h
@@ -1,5 +1,6 @@
/* Definitions for SH opcodes.
- Copyright (C) 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
+ Copyright 1993, 1994, 1995, 1997, 1999, 2000
+ Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -39,16 +40,20 @@ typedef enum {
REG_B,
BRANCH_12,
BRANCH_8,
- DISP_8,
- DISP_4,
- IMM_4,
- IMM_4BY2,
- IMM_4BY4,
+ IMM0_4,
+ IMM0_4BY2,
+ IMM0_4BY4,
+ IMM1_4,
+ IMM1_4BY2,
+ IMM1_4BY4,
PCRELIMM_8BY2,
PCRELIMM_8BY4,
- IMM_8,
- IMM_8BY2,
- IMM_8BY4,
+ IMM0_8,
+ IMM0_8BY2,
+ IMM0_8BY4,
+ IMM1_8,
+ IMM1_8BY2,
+ IMM1_8BY4,
PPI,
NOPX,
NOPY,
@@ -58,7 +63,8 @@ typedef enum {
PMUL,
PPI3,
PDC,
- PPIC
+ PPIC,
+ REPEAT
} sh_nibble_type;
typedef enum {
@@ -68,6 +74,7 @@ typedef enum {
A_DEC_M,
A_DEC_N,
A_DISP_GBR,
+ A_PC,
A_DISP_PC,
A_DISP_REG_M,
A_DISP_REG_N,
@@ -164,7 +171,7 @@ typedef struct {
sh_opcode_info sh_table[] = {
-/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}, arch_sh1_up},
+/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up},
/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up},
@@ -172,11 +179,11 @@ sh_opcode_info sh_table[] = {
/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up},
-/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}, arch_sh1_up},
+/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up},
/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up},
-/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}, arch_sh1_up},
+/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up},
/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up},
@@ -200,7 +207,7 @@ sh_opcode_info sh_table[] = {
/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up},
-/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}, arch_sh1_up},
+/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up},
/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up},
@@ -276,9 +283,9 @@ sh_opcode_info sh_table[] = {
/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up},
-/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_BDISP8},{HEX_8,HEX_E,BRANCH_8}, arch_sh_dsp_up},
+/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
-/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_BDISP8},{HEX_8,HEX_C,BRANCH_8}, arch_sh_dsp_up},
+/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},
/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up},
@@ -328,7 +335,7 @@ sh_opcode_info sh_table[] = {
/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
-/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}, arch_sh1_up},
+/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up},
/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up},
@@ -338,9 +345,9 @@ sh_opcode_info sh_table[] = {
/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up},
-/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}, arch_sh1_up},
+/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up},
-/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}, arch_sh1_up},
+/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up},
/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up},
@@ -348,11 +355,11 @@ sh_opcode_info sh_table[] = {
/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up},
-/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}, arch_sh1_up},
+/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up},
-/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}, arch_sh1_up},
+/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up},
-/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}, arch_sh1_up},
+/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up},
/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up},
@@ -360,9 +367,9 @@ sh_opcode_info sh_table[] = {
/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up},
-/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}, arch_sh1_up},
+/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up},
-/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}, arch_sh1_up},
+/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up},
/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up},
@@ -372,7 +379,7 @@ sh_opcode_info sh_table[] = {
/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up},
-/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}, arch_sh1_up},
+/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up},
/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up},
@@ -380,9 +387,9 @@ sh_opcode_info sh_table[] = {
/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up},
-/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}, arch_sh1_up},
+/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up},
-/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}, arch_sh1_up},
+/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up},
/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up},
@@ -392,9 +399,9 @@ sh_opcode_info sh_table[] = {
/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up},
-/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}, arch_sh1_up},
+/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up},
-/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}, arch_sh1_up},
+/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_up},
@@ -424,11 +431,11 @@ sh_opcode_info sh_table[] = {
/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_up},
-/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}, arch_sh1_up},
+/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up},
-/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}, arch_sh1_up},
+/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_up},
@@ -449,7 +456,11 @@ sh_opcode_info sh_table[] = {
/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
-/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM_8}, arch_sh_dsp_up},
+/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up},
+
+/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
+
+/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_up},
@@ -513,7 +524,7 @@ sh_opcode_info sh_table[] = {
/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_up},
-/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh4_up},
+/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_up},
@@ -577,19 +588,19 @@ sh_opcode_info sh_table[] = {
/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up},
-/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}, arch_sh1_up},
+/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up},
-/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}, arch_sh1_up},
+/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up},
/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up},
-/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}, arch_sh1_up},
+/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up},
-/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}, arch_sh1_up},
+/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up},
/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up},
-/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}, arch_sh1_up},
+/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up},
/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up},
@@ -609,33 +620,33 @@ sh_opcode_info sh_table[] = {
/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up},
-/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up},
+/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up},
-/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up},
+/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up},
-/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up},
+/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
-/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up},
+/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up},
/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up},
-/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up},
+/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up},
-/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up},
+/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
-/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up},
+/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up},
-/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up},
+/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up},
/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up},
-/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up},
+/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
-/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
+/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up},
-/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
+/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up},
-/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
+/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up},
/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
@@ -667,22 +678,22 @@ sh_opcode_info sh_table[] = {
{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */
{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_8,HEX_8}, arch_sh_dsp_up},
-/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
-{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up},
/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_8}, arch_sh_dsp_up},
+/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
+{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up},
/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_8}, arch_sh_dsp_up},
{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
-/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up},
/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
{"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up},
-/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
+/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up},
/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
{"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up},
+/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
@@ -695,10 +706,10 @@ sh_opcode_info sh_table[] = {
{"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up},
/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */
{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
-/* 10011001xxyynnnn pinc <DSP_REG_X>,<DSP_REG_N> */
-{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up},
/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */
{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
+/* 10011001xxyynnnn pinc <DSP_REG_X>,<DSP_REG_N> */
+{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up},
/* 10111001xxyynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9}, arch_sh_dsp_up},
/* 10001101xxyynnnn pclr <DSP_REG_N> */
@@ -709,10 +720,10 @@ sh_opcode_info sh_table[] = {
{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D}, arch_sh_dsp_up},
/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */
{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
-/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */
-{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */
{"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up},
+/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */
+{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */
{"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up},
/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */
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