diff options
Diffstat (limited to 'contrib/binutils/opcodes/arm-dis.c')
| -rw-r--r-- | contrib/binutils/opcodes/arm-dis.c | 469 |
1 files changed, 327 insertions, 142 deletions
diff --git a/contrib/binutils/opcodes/arm-dis.c b/contrib/binutils/opcodes/arm-dis.c index f3785f2..e918daf 100644 --- a/contrib/binutils/opcodes/arm-dis.c +++ b/contrib/binutils/opcodes/arm-dis.c @@ -1,24 +1,24 @@ /* Instruction printing code for the ARM - Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) Modification by James G. Smith (jsmith@cygnus.co.uk) -This file is part of libopcodes. + This file is part of libopcodes. -This program is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2 of the License, or (at your option) -any later version. + This program is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sysdep.h" #include "dis-asm.h" @@ -27,6 +27,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "coff/internal.h" #include "libcoff.h" #include "opintl.h" +#include "safe-ctype.h" /* FIXME: This shouldn't be done here. */ #include "elf-bfd.h" @@ -70,7 +71,21 @@ static arm_regname regnames[] = { "atpcs", "Select register names used in the ATPCS", { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, { "special-atpcs", "Select special register names used in the ATPCS", - { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, + { "iwmmxt_regnames", "Select register names used on the Intel Wireless MMX technology coprocessor", + { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"}}, + { "iwmmxt_Cregnames", "Select control register names used on the Intel Wireless MMX technology coprocessor", + {"wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"}} +}; + +static char * iwmmxt_wwnames[] = +{"b", "h", "w", "d"}; + +static char * iwmmxt_wwssnames[] = +{"b", "bus", "b", "bss", + "h", "hus", "h", "hss", + "w", "wus", "w", "wss", + "d", "dus", "d", "dss" }; /* Default to GCC register name set. */ @@ -79,25 +94,34 @@ static unsigned int regname_selected = 1; #define NUM_ARM_REGNAMES NUM_ELEM (regnames) #define arm_regnames regnames[regname_selected].reg_names -static boolean force_thumb = false; +static bfd_boolean force_thumb = FALSE; static char * arm_fp_const[] = {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; -static char * arm_shift[] = +static char * arm_shift[] = {"lsl", "lsr", "asr", "ror"}; /* Forward declarations. */ -static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); -static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)); -static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); -static void parse_disassembler_options PARAMS ((char *)); -static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean)); -int get_arm_regname_num_options (void); -int set_arm_regname_option (int option); -int get_arm_regnames (int option, const char **setname, - const char **setdescription, - const char ***register_names); +static void arm_decode_shift + PARAMS ((long, fprintf_ftype, void *)); +static int print_insn_arm + PARAMS ((bfd_vma, struct disassemble_info *, long)); +static int print_insn_thumb + PARAMS ((bfd_vma, struct disassemble_info *, long)); +static void parse_disassembler_options + PARAMS ((char *)); +static int print_insn + PARAMS ((bfd_vma, struct disassemble_info *, bfd_boolean)); +static int set_iwmmxt_regnames + PARAMS ((void)); + +int get_arm_regname_num_options + PARAMS ((void)); +int set_arm_regname_option + PARAMS ((int)); +int get_arm_regnames + PARAMS ((int, const char **, const char **, const char ***)); /* Functions. */ int @@ -135,14 +159,14 @@ arm_decode_shift (given, func, stream) void * stream; { func (stream, "%s", arm_regnames[given & 0xf]); - + if ((given & 0xff0) != 0) { if ((given & 0x10) == 0) { int amount = (given & 0xf80) >> 7; int shift = (given & 0x60) >> 5; - + if (amount == 0) { if (shift == 3) @@ -150,10 +174,10 @@ arm_decode_shift (given, func, stream) func (stream, ", rrx"); return; } - + amount = 32; } - + func (stream, ", %s #%d", arm_shift[shift], amount); } else @@ -162,25 +186,49 @@ arm_decode_shift (given, func, stream) } } +static int +set_iwmmxt_regnames () +{ + const char * setname; + const char * setdesc; + const char ** regnames; + int iwmmxt_regnames = 0; + int num_regnames = get_arm_regname_num_options (); + + get_arm_regnames (iwmmxt_regnames, &setname, + &setdesc, ®names); + while ((strcmp ("iwmmxt_regnames", setname)) + && (iwmmxt_regnames < num_regnames)) + get_arm_regnames (++iwmmxt_regnames, &setname, &setdesc, ®names); + + return iwmmxt_regnames; +} + /* Print one instruction from PC on INFO->STREAM. Return the size of the instruction (always 4 on ARM). */ static int print_insn_arm (pc, info, given) - bfd_vma pc; - struct disassemble_info * info; - long given; + bfd_vma pc; + struct disassemble_info *info; + long given; { - struct arm_opcode * insn; - void * stream = info->stream; - fprintf_ftype func = info->fprintf_func; + const struct arm_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + static int iwmmxt_regnames = 0; for (insn = arm_opcodes; insn->assembler; insn++) { + if (insn->value == FIRST_IWMMXT_INSN + && info->mach != bfd_mach_arm_XScale + && info->mach != bfd_mach_arm_iWMMXt) + insn = insn + IWMMXT_INSN_COUNT; + if ((given & insn->mask) == insn->value) { char * c; - + for (c = insn->assembler; *c; c++) { if (*c == '%') @@ -196,14 +244,14 @@ print_insn_arm (pc, info, given) && ((given & 0x02000000) == 0)) { int offset = given & 0xfff; - + func (stream, "[pc"); - + if (given & 0x01000000) { if ((given & 0x00800000) == 0) offset = - offset; - + /* Pre-indexed. */ func (stream, ", #%d]", offset); @@ -224,13 +272,13 @@ print_insn_arm (pc, info, given) /* ie ignore the offset. */ offset = pc + 8; } - + func (stream, "\t; "); info->print_address_func (offset, info); } else { - func (stream, "[%s", + func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) { @@ -238,7 +286,7 @@ print_insn_arm (pc, info, given) { int offset = given & 0xfff; if (offset) - func (stream, ", %s#%d", + func (stream, ", #%s%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); } @@ -250,7 +298,7 @@ print_insn_arm (pc, info, given) arm_decode_shift (given, func, stream); } - func (stream, "]%s", + func (stream, "]%s", ((given & 0x00200000) != 0) ? "!" : ""); } else @@ -259,16 +307,16 @@ print_insn_arm (pc, info, given) { int offset = given & 0xfff; if (offset) - func (stream, "], %s#%d", + func (stream, "], #%s%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); - else + else func (stream, "]"); } else { func (stream, "], %s", - (((given & 0x00800000) == 0) + (((given & 0x00800000) == 0) ? "-" : "")); arm_decode_shift (given, func, stream); } @@ -281,18 +329,18 @@ print_insn_arm (pc, info, given) { /* PC relative with immediate offset. */ int offset = ((given & 0xf00) >> 4) | (given & 0xf); - + if ((given & 0x00800000) == 0) offset = -offset; - + func (stream, "[pc, #%d]\t; ", offset); - + (*info->print_address_func) (offset + pc + 8, info); } else { - func (stream, "[%s", + func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) { @@ -302,7 +350,7 @@ print_insn_arm (pc, info, given) /* Immediate. */ int offset = ((given & 0xf00) >> 4) | (given & 0xf); if (offset) - func (stream, ", %s#%d", + func (stream, ", #%s%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); } @@ -315,7 +363,7 @@ print_insn_arm (pc, info, given) arm_regnames[given & 0xf]); } - func (stream, "]%s", + func (stream, "]%s", ((given & 0x00200000) != 0) ? "!" : ""); } else @@ -326,10 +374,10 @@ print_insn_arm (pc, info, given) /* Immediate. */ int offset = ((given & 0xf00) >> 4) | (given & 0xf); if (offset) - func (stream, "], %s#%d", + func (stream, "], #%s%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); - else + else func (stream, "]"); } else @@ -343,7 +391,7 @@ print_insn_arm (pc, info, given) } } break; - + case 'b': (*info->print_address_func) (BDISP (given) * 4 + pc + 8, info); @@ -397,11 +445,13 @@ print_insn_arm (pc, info, given) case 'A': func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) + + if ((given & (1 << 24)) != 0) { int offset = given & 0xff; + if (offset) - func (stream, ", %s#%d]%s", + func (stream, ", #%s%d]%s", ((given & 0x00800000) == 0 ? "-" : ""), offset * 4, ((given & 0x00200000) != 0 ? "!" : "")); @@ -411,12 +461,18 @@ print_insn_arm (pc, info, given) else { int offset = given & 0xff; - if (offset) - func (stream, "], %s#%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); + + func (stream, "]"); + + if (given & (1 << 21)) + { + if (offset) + func (stream, ", #%s%d", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * 4); + } else - func (stream, "]"); + func (stream, ", {%d}", offset); } break; @@ -425,7 +481,7 @@ print_insn_arm (pc, info, given) { bfd_vma address; bfd_vma offset = 0; - + if (given & 0x00800000) /* Is signed, hi bits should be ones. */ offset = (-1) ^ 0x00ffffff; @@ -434,7 +490,7 @@ print_insn_arm (pc, info, given) offset += given & 0x00ffffff; offset <<= 2; address = offset + pc + 8; - + if (given & 0x01000000) /* H bit allows addressing to 2-byte boundaries. */ address += 2; @@ -490,7 +546,7 @@ print_insn_arm (pc, info, given) func (stream, "3"); } break; - + case 'P': switch (given & 0x00080080) { @@ -542,7 +598,7 @@ print_insn_arm (pc, info, given) } break; - case '0': case '1': case '2': case '3': case '4': + case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { int bitstart = *c++ - '0'; @@ -554,44 +610,54 @@ print_insn_arm (pc, info, given) { case '-': c++; - + while (*c >= '0' && *c <= '9') bitend = (bitend * 10) + *c++ - '0'; - + if (!bitend) abort (); - + switch (*c) { case 'r': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "%s", arm_regnames[reg]); } break; case 'd': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "%d", reg); } break; - case 'x': + case 'W': { long reg; reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "%d", reg + 1); + } + break; + case 'x': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "0x%08x", reg); - + /* Some SWI instructions have special meanings. */ if ((given & 0x0fffffff) == 0x0FF00000) @@ -603,20 +669,20 @@ print_insn_arm (pc, info, given) case 'X': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "%01x", reg & 0xf); } break; case 'f': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + if (reg > 7) func (stream, "#%s", arm_fp_const[reg & 7]); @@ -624,6 +690,63 @@ print_insn_arm (pc, info, given) func (stream, "f%d", reg); } break; + + case 'w': + { + long reg; + + if (bitstart != bitend) + { + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + if (bitend - bitstart == 1) + func (stream, "%s", iwmmxt_wwnames[reg]); + else + func (stream, "%s", iwmmxt_wwssnames[reg]); + } + else + { + reg = (((given >> 8) & 0x1) | + ((given >> 22) & 0x1)); + func (stream, "%s", iwmmxt_wwnames[reg]); + } + } + break; + + case 'g': + { + long reg; + int current_regnames; + + if (! iwmmxt_regnames) + iwmmxt_regnames = set_iwmmxt_regnames (); + current_regnames = set_arm_regname_option + (iwmmxt_regnames); + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "%s", arm_regnames[reg]); + set_arm_regname_option (current_regnames); + } + break; + + case 'G': + { + long reg; + int current_regnames; + + if (! iwmmxt_regnames) + iwmmxt_regnames = set_iwmmxt_regnames (); + current_regnames = set_arm_regname_option + (iwmmxt_regnames + 1); + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "%s", arm_regnames[reg]); + set_arm_regname_option (current_regnames); + } + break; + default: abort (); } @@ -677,7 +800,7 @@ print_insn_arm (pc, info, given) } break; - + default: abort (); } @@ -729,6 +852,54 @@ print_insn_arm (pc, info, given) } break; + case 'L': + switch (given & 0x00400100) + { + case 0x00000000: func (stream, "b"); break; + case 0x00400000: func (stream, "h"); break; + case 0x00000100: func (stream, "w"); break; + case 0x00400100: func (stream, "d"); break; + default: + break; + } + break; + + case 'Z': + { + int value; + /* given (20, 23) | given (0, 3) */ + value = ((given >> 16) & 0xf0) | (given & 0xf); + func (stream, "%d", value); + } + break; + + case 'l': + /* This is like the 'A' operator, except that if + the width field "M" is zero, then the offset is + *not* multiplied by four. */ + { + int offset = given & 0xff; + int multiplier = (given & 0x00000100) ? 4 : 1; + + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + + if (offset) + { + if ((given & 0x01000000) != 0) + func (stream, ", #%s%d]%s", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * multiplier, + ((given & 0x00200000) != 0 ? "!" : "")); + else + func (stream, "], #%s%d", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * multiplier); + } + else + func (stream, "]"); + } + break; + default: abort (); } @@ -748,13 +919,13 @@ print_insn_arm (pc, info, given) static int print_insn_thumb (pc, info, given) - bfd_vma pc; - struct disassemble_info * info; - long given; + bfd_vma pc; + struct disassemble_info *info; + long given; { - struct thumb_opcode * insn; - void * stream = info->stream; - fprintf_ftype func = info->fprintf_func; + const struct thumb_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; for (insn = thumb_opcodes; insn->assembler; insn++) { @@ -766,7 +937,7 @@ print_insn_thumb (pc, info, given) if (!*c) /* Check for empty (not NULL) assembler string. */ { long offset; - + info->bytes_per_chunk = 4; info->bytes_per_line = 4; @@ -788,16 +959,16 @@ print_insn_thumb (pc, info, given) { info->bytes_per_chunk = 2; info->bytes_per_line = 4; - + given &= 0xffff; - + for (; *c; c++) { if (*c == '%') { int domaskpc = 0; int domasklr = 0; - + switch (*++c) { case '%': @@ -807,11 +978,11 @@ print_insn_thumb (pc, info, given) case 'S': { long reg; - + reg = (given >> 3) & 0x7; if (given & (1 << 6)) reg += 8; - + func (stream, "%s", arm_regnames[reg]); } break; @@ -819,11 +990,11 @@ print_insn_thumb (pc, info, given) case 'D': { long reg; - + reg = given & 0x7; if (given & (1 << 7)) reg += 8; - + func (stream, "%s", arm_regnames[reg]); } break; @@ -845,9 +1016,9 @@ print_insn_thumb (pc, info, given) { int started = 0; int reg; - + func (stream, "{"); - + /* It would be nice if we could spot ranges, and generate the rS-rE format: */ for (reg = 0; (reg < 8); reg++) @@ -879,12 +1050,12 @@ print_insn_thumb (pc, info, given) break; - case '0': case '1': case '2': case '3': case '4': + case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { int bitstart = *c++ - '0'; int bitend = 0; - + while (*c >= '0' && *c <= '9') bitstart = (bitstart * 10) + *c++ - '0'; @@ -893,7 +1064,7 @@ print_insn_thumb (pc, info, given) case '-': { long reg; - + c++; while (*c >= '0' && *c <= '9') bitend = (bitend * 10) + *c++ - '0'; @@ -984,6 +1155,23 @@ print_insn_thumb (pc, info, given) abort (); } +/* Disallow mapping symbols ($a, $b, $d, $t etc) from + being displayed in symbol relative addresses. */ + +bfd_boolean +arm_symbol_is_valid (asymbol * sym, + struct disassemble_info * info ATTRIBUTE_UNUSED) +{ + const char * name; + + if (sym == NULL) + return FALSE; + + name = bfd_asymbol_name (sym); + + return (name && *name != '$'); +} + /* Parse an individual disassembler option. */ void @@ -992,59 +1180,56 @@ parse_arm_disassembler_option (option) { if (option == NULL) return; - + if (strneq (option, "reg-names-", 10)) { int i; - + option += 10; for (i = NUM_ARM_REGNAMES; i--;) - if (streq (option, regnames[i].name)) + if (strneq (option, regnames[i].name, strlen (regnames[i].name))) { regname_selected = i; break; } - + if (i < 0) + /* XXX - should break 'option' at following delimiter. */ fprintf (stderr, _("Unrecognised register name set: %s\n"), option); } - else if (streq (option, "force-thumb")) + else if (strneq (option, "force-thumb", 11)) force_thumb = 1; - else if (streq (option, "no-force-thumb")) + else if (strneq (option, "no-force-thumb", 14)) force_thumb = 0; else + /* XXX - should break 'option' at following delimiter. */ fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); - + return; } -/* Parse the string of disassembler options, spliting it at whitespaces. */ +/* Parse the string of disassembler options, spliting it at whitespaces + or commas. (Whitespace separators supported for backwards compatibility). */ static void parse_disassembler_options (options) char * options; { - char * space; - if (options == NULL) return; - do + while (*options) { - space = strchr (options, ' '); - - if (space) - { - * space = '\0'; - parse_arm_disassembler_option (options); - * space = ' '; - options = space + 1; - } - else - parse_arm_disassembler_option (options); + parse_arm_disassembler_option (options); + + /* Skip forward to next seperator. */ + while ((*options) && (! ISSPACE (*options)) && (*options != ',')) + ++ options; + /* Skip forward past seperators. */ + while (ISSPACE (*options) || (*options == ',')) + ++ options; } - while (space); } /* NOTE: There are no checks in these routines that @@ -1054,7 +1239,7 @@ static int print_insn (pc, info, little) bfd_vma pc; struct disassemble_info * info; - boolean little; + bfd_boolean little; { unsigned char b[4]; long given; @@ -1064,19 +1249,19 @@ print_insn (pc, info, little) if (info->disassembler_options) { parse_disassembler_options (info->disassembler_options); - + /* To avoid repeated parsing of these options, we remove them here. */ info->disassembler_options = NULL; } - + is_thumb = force_thumb; - + if (!is_thumb && info->symbols != NULL) { if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) { coff_symbol_type * cs; - + cs = coffsymbol (*info->symbols); is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT || cs->native->u.syment.n_sclass == C_THUMBSTAT @@ -1088,14 +1273,14 @@ print_insn (pc, info, little) { elf_symbol_type * es; unsigned int type; - + es = *(elf_symbol_type **)(info->symbols); type = ELF_ST_TYPE (es->internal_elf_sym.st_info); - + is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); } } - + info->bytes_per_chunk = 4; info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; @@ -1105,17 +1290,17 @@ print_insn (pc, info, little) if (status != 0 && is_thumb) { info->bytes_per_chunk = 2; - + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); b[3] = b[2] = 0; } - + if (status != 0) { info->memory_error_func (status, pc, info); return -1; } - + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); } else @@ -1127,13 +1312,13 @@ print_insn (pc, info, little) info->memory_error_func (status, pc, info); return -1; } - + if (is_thumb) { if (pc & 0x2) { given = (b[2] << 8) | b[3]; - + status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); if (status != 0) @@ -1141,7 +1326,7 @@ print_insn (pc, info, little) info->memory_error_func (status, pc + 4, info); return -1; } - + given |= (b[0] << 24) | (b[1] << 16); } else @@ -1150,7 +1335,7 @@ print_insn (pc, info, little) else given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); } - + if (info->flags & INSN_HAS_RELOC) /* If the instruction has a reloc associated with it, then the offset field in the instruction will actually be the @@ -1158,7 +1343,7 @@ print_insn (pc, info, little) In such cases, we can ignore the pc when computing addresses, since the addend is not currently pc-relative. */ pc = 0; - + if (is_thumb) status = print_insn_thumb (pc, info, given); else @@ -1172,7 +1357,7 @@ print_insn_big_arm (pc, info) bfd_vma pc; struct disassemble_info * info; { - return print_insn (pc, info, false); + return print_insn (pc, info, FALSE); } int @@ -1180,7 +1365,7 @@ print_insn_little_arm (pc, info) bfd_vma pc; struct disassemble_info * info; { - return print_insn (pc, info, true); + return print_insn (pc, info, TRUE); } void @@ -1191,7 +1376,7 @@ print_arm_disassembler_options (FILE * stream) fprintf (stream, _("\n\ The following ARM specific disassembler options are supported for use with\n\ the -M switch:\n")); - + for (i = NUM_ARM_REGNAMES; i--;) fprintf (stream, " reg-names-%s %*c%s\n", regnames[i].name, |
