diff options
Diffstat (limited to 'contrib/binutils/include/opcode')
20 files changed, 2912 insertions, 1988 deletions
diff --git a/contrib/binutils/include/opcode/ChangeLog b/contrib/binutils/include/opcode/ChangeLog index 6c50775..689e278 100644 --- a/contrib/binutils/include/opcode/ChangeLog +++ b/contrib/binutils/include/opcode/ChangeLog @@ -1,13 +1,665 @@ -2004-04-08 Alan Modra <amodra@bigpond.net.au> +2006-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> - Apply from mainline. - 2004-03-12 Jakub Jelinek <jakub@redhat.com> - * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. + * cr16.h: New file for CR16 target. + +2007-05-02 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (PPC_OPERAND_PLUS1): Update comment. + +2007-04-23 Nathan Sidwell <nathan@codesourcery.com> + + * m68k.h (mcfisa_c): New. + (mcfusp, mcf_mask): Adjust. + +2007-04-20 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". + (num_powerpc_operands): Declare. + (PPC_OPERAND_SIGNED et al): Redefine as hex. + (PPC_OPERAND_PLUS1): Define. + +2007-03-21 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (REX_MODE64): Renamed to ... + (REX_W): This. + (REX_EXTX): Renamed to ... + (REX_R): This. + (REX_EXTY): Renamed to ... + (REX_X): This. + (REX_EXTZ): Renamed to ... + (REX_B): This. + +2007-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h: Add entries from config/tc-i386.h and move tables + to opcodes/i386-opc.h. + +2007-03-13 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (FloatDR): Removed. + (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. + +2007-03-01 Alan Modra <amodra@bigpond.net.au> + + * spu-insns.h: Add soma double-float insns. + +2007-02-20 Thiemo Seufer <ths@mips.com> + Chao-Ying Fu <fu@mips.com> + + * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. + (INSN_DSPR2): Add flag for DSP R2 instructions. + (M_BALIGN): New macro. + +2007-02-14 Alan Modra <amodra@bigpond.net.au> + + * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm + and Seg3ShortFrom with Shortform. + +2007-02-11 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/4027 + * i386.h (i386_optab): Put the real "test" before the pseudo + one. + +2007-01-08 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (m68010up): OR fido_a. + +2006-12-25 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (fido_a): New. + +2006-12-24 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, + mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined + values. + +2006-11-08 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. + +2006-10-31 Mei Ligang <ligang@sunnorth.com.cn> + + * score-inst.h (enum score_insn_type): Add Insn_internal. + +2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> + Yukishige Shibata <shibata@rd.scei.sony.co.jp> + Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> + Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> + Alan Modra <amodra@bigpond.net.au> + + * spu-insns.h: New file. + * spu.h: New file. + +2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> + + * ppc.h (PPC_OPCODE_CELL): Define. + +2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + + * i386.h : Modify opcode to support for the change in POPCNT opcode + in amdfam10 architecture. + +2006-09-28 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h: Replace CpuMNI with CpuSSSE3. + +2006-09-26 Mark Shinwell <shinwell@codesourcery.com> + Joseph Myers <joseph@codesourcery.com> + Ian Lance Taylor <ian@wasabisystems.com> + Ben Elliston <bje@wasabisystems.com> + + * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. + +2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> + + * score-datadep.h: New file. + * score-inst.h: New file. + +2006-07-14 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, + movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, + movdq2q and movq2dq. + +2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + Michael Meissner <michael.meissner@amd.com> + + * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). + +2006-06-12 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Add "nop" with memory reference. + +2006-06-12 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Update comment for 64bit NOP. + +2006-06-06 Ben Elliston <bje@au.ibm.com> + Anton Blanchard <anton@samba.org> + + * ppc.h (PPC_OPCODE_POWER6): Define. + Adjust whitespace. + +2006-06-05 Thiemo Seufer <ths@mips.com> + + * mips.h: Improve description of MT flags. + +2006-05-25 Richard Sandiford <richard@codesourcery.com> + + * m68k.h (mcf_mask): Define. + +2006-05-05 Thiemo Seufer <ths@mips.com> + David Ung <davidu@mips.com> + + * mips.h (enum): Add macro M_CACHE_AB. + +2006-05-04 Thiemo Seufer <ths@mips.com> + Nigel Stephens <nigel@mips.com> + David Ung <davidu@mips.com> + + * mips.h: Add INSN_SMARTMIPS define. + +2006-04-30 Thiemo Seufer <ths@mips.com> + David Ung <davidu@mips.com> + + * mips.h: Defines udi bits and masks. Add description of + characters which may appear in the args field of udi + instructions. + +2006-04-26 Thiemo Seufer <ths@networkno.de> + + * mips.h: Improve comments describing the bitfield instruction + fields. + +2006-04-26 Julian Brown <julian@codesourcery.com> + + * arm.h (FPU_VFP_EXT_V3): Define constant. + (FPU_NEON_EXT_V1): Likewise. + (FPU_VFP_HARD): Update. + (FPU_VFP_V3): Define macro. + (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. + +2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> + + * avr.h (AVR_ISA_PWMx): New. + +2006-03-28 Nathan Sidwell <nathan@codesourcery.com> + + * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, + cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, + cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, + cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, + cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. + +2006-03-10 Paul Brook <paul@codesourcery.com> + + * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. + +2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come + first. Correct mask of bb "B" opcode. + +2006-02-27 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Support Intel Merom New Instructions. + +2006-02-24 Paul Brook <paul@codesourcery.com> + + * arm.h: Add V7 feature bits. + +2006-02-23 H.J. Lu <hongjiu.lu@intel.com> + + * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. + +2006-01-31 Paul Brook <paul@codesourcery.com> + Richard Earnshaw <rearnsha@arm.com> + + * arm.h: Use ARM_CPU_FEATURE. + (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. + (arm_feature_set): Change to a structure. + (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, + ARM_FEATURE): New macros. + +2005-12-07 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) + (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. + (ADD_PC_INCR_OPCODE): Don't define. + +2005-12-06 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/1874 + * i386.h (i386_optab): Add 64bit support for monitor and mwait. + +2005-11-14 David Ung <davidu@mips.com> + + * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore + instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for + save/restore encoding of the args field. + +2005-10-28 Dave Brolley <brolley@redhat.com> + + Contribute the following changes: + 2005-02-16 Dave Brolley <brolley@redhat.com> + + * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename + cgen_isa_mask_* to cgen_bitset_*. + * cgen.h: Likewise. + + 2003-10-21 Richard Sandiford <rsandifo@redhat.com> + + * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. + (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". + (CGEN_CPU_TABLE): Make isas a ponter. + + 2003-09-29 Dave Brolley <brolley@redhat.com> + + * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. + (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. + (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. + + 2002-12-13 Dave Brolley <brolley@redhat.com> + + * cgen.h (symcat.h): #include it. + (cgen-bitset.h): #include it. + (CGEN_ATTR_VALUE_TYPE): Now a union. + (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. + (CGEN_ATTR_ENTRY): 'value' now unsigned. + (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). + * cgen-bitset.h: New file. + +2005-09-30 Catherine Moore <clm@cm00re.com> + + * bfin.h: New file. + +2005-10-24 Jan Beulich <jbeulich@novell.com> + + * ia64.h (enum ia64_opnd): Move memory operand out of set of + indirect operands. + +2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. + Add FLAG_STRICT to pa10 ftest opcode. + +2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h (pa_opcodes): Remove lha entries. + +2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h (FLAG_STRICT): Revise comment. + (pa_opcode): Revise ordering rules. Add/move strict pa10 variants + before corresponding pa11 opcodes. Add strict pa10 register-immediate + entries for "fdc". + +2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. + +2005-09-06 Chao-ying Fu <fu@mips.com> + + * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, + OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New + define. + Document !, $, *, &, g, +t, +T operand formats for MT instructions. + (INSN_ASE_MASK): Update to include INSN_MT. + (INSN_MT): New define for MT ASE. + +2005-08-25 Chao-ying Fu <fu@mips.com> + + * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, + OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, + OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, + OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, + OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. + Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP + instructions. + (INSN_DSP): New define for DSP ASE. + +2005-08-18 Alan Modra <amodra@bigpond.net.au> + + * a29k.h: Delete. + +2005-08-15 Daniel Jacobowitz <dan@codesourcery.com> + + * ppc.h (PPC_OPCODE_E300): Define. + +2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. + +2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + PR gas/336 + * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb + and pitlb. + +2005-07-27 Jan Beulich <jbeulich@novell.com> + + * i386.h (i386_optab): Add comment to movd. Use LongMem for all + movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. + Add movq-s as 64-bit variants of movd-s. + +2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h: Fix punctuation in comment. + + * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for + implicit space-register addressing. Set space-register bits on opcodes + using implicit space-register addressing. Add various missing pa20 + long-immediate opcodes. Remove various opcodes using implicit 3-bit + space-register addressing. Use "fE" instead of "fe" in various + fstw opcodes. + +2005-07-18 Jan Beulich <jbeulich@novell.com> + + * i386.h (i386_optab): Operands of aam and aad are unsigned. + +2007-07-15 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Support Intel VMX Instructions. + +2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. + +2005-07-05 Jan Beulich <jbeulich@novell.com> + + * i386.h (i386_optab): Add new insns. + +2005-07-01 Nick Clifton <nickc@redhat.com> + + * sparc.h: Add typedefs to structure declarations. + +2005-06-20 H.J. Lu <hongjiu.lu@intel.com> + + PR 1013 + * i386.h (i386_optab): Update comments for 64bit addressing on + mov. Allow 64bit addressing for mov and movq. + +2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, + respectively, in various floating-point load and store patterns. + +2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> + + * hppa.h (FLAG_STRICT): Correct comment. + (pa_opcodes): Update load and store entries to allow both PA 1.X and + PA 2.0 mneumonics when equivalent. Entries with cache control + completers now require PA 1.1. Adjust whitespace. + +2005-05-19 Anton Blanchard <anton@samba.org> + + * ppc.h (PPC_OPCODE_POWER5): Define. + +2005-05-10 Nick Clifton <nickc@redhat.com> + + * Update the address and phone number of the FSF organization in + the GPL notices in the following files: + a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, + crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, + i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, + mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, + pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, + tic54x.h, tic80.h, v850.h, vax.h + +2005-05-09 Jan Beulich <jbeulich@novell.com> + + * i386.h (i386_optab): Add ht and hnt. + +2005-04-18 Mark Kettenis <kettenis@gnu.org> + + * i386.h: Insert hyphens into selected VIA PadLock extensions. + Add xcrypt-ctr. Provide aliases without hyphens. + +2005-04-13 H.J. Lu <hongjiu.lu@intel.com> + + Moved from ../ChangeLog + + 2005-04-12 Paul Brook <paul@codesourcery.com> + * m88k.h: Rename psr macros to avoid conflicts. + + 2005-03-12 Zack Weinberg <zack@codesourcery.com> + * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. + Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, + and ARM_ARCH_V6ZKT2. + + 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> + * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. + Remove redundant instruction types. + (struct argument): X_op - new field. + (struct cst4_entry): Remove. + (no_op_insn): Declare. + + 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> + * crx.h (enum argtype): Rename types, remove unused types. + + 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> + * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. + (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. + (enum operand_type): Rearrange operands, edit comments. + replace us<N> with ui<N> for unsigned immediate. + replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped + displacements (respectively). + replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. + (instruction type): Add NO_TYPE_INS. + (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. + (operand_entry): New field - 'flags'. + (operand flags): New. + + 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> + * crx.h (operand_type): Remove redundant types i3, i4, + i5, i8, i12. + Add new unsigned immediate types us3, us4, us5, us16. + +2005-04-12 Mark Kettenis <kettenis@gnu.org> + + * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and + adjust them accordingly. + +2005-04-01 Jan Beulich <jbeulich@novell.com> + + * i386.h (i386_optab): Add rdtscp. + +2005-03-29 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Don't allow the `l' suffix for moving + between memory and segment register. Allow movq for moving between + general-purpose register and segment register. + +2005-02-09 Jan Beulich <jbeulich@novell.com> + + PR gas/707 + * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and + FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and + fnstsw. + +2006-02-07 Nathan Sidwell <nathan@codesourcery.com> + + * m68k.h (m68008, m68ec030, m68882): Remove. + (m68k_mask): New. + (cpu_m68k, cpu_cf): New. + (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, + mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. + +2005-01-25 Alexandre Oliva <aoliva@redhat.com> + + 2004-11-10 Alexandre Oliva <aoliva@redhat.com> + * cgen.h (enum cgen_parse_operand_type): Add + CGEN_PARSE_OPERAND_SYMBOLIC. + +2005-01-21 Fred Fish <fnf@specifixinc.com> + + * mips.h: Change INSN_ALIAS to INSN2_ALIAS. + Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. + Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. + +2005-01-19 Fred Fish <fnf@specifixinc.com> + + * mips.h (struct mips_opcode): Add new pinfo2 member. + (INSN_ALIAS): New define for opcode table entries that are + specific instances of another entry, such as 'move' for an 'or' + with a zero operand. + (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. + (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. + +2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> + + * mips.h (CPU_RM9000): Define. + (OPCODE_IS_MEMBER): Handle CPU_RM9000. + +2004-11-25 Jan Beulich <jbeulich@novell.com> + + * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves + to/from test registers are illegal in 64-bit mode. Add missing + NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix + (previously one had to explicitly encode a rex64 prefix). Re-enable + lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings + support it there. Add cmpxchg16b as per Intel's 64-bit documentation. + +2004-11-23 Jan Beulich <jbeulich@novell.com> + + * i386.h (i386_optab): paddq and psubq, even in their MMX form, are + available only with SSE2. Change the MMX additions introduced by SSE + and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A + instructions by their now designated identifier (since combining i686 + and 3DNow! does not really imply 3DNow!A). + +2004-11-19 Alan Modra <amodra@bigpond.net.au> + + * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, + struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. + +2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> + Vineet Sharma <vineets@noida.hcltech.com> + + * maxq.h: New file: Disassembly information for the maxq port. + +2004-11-05 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Put back "movzb". + +2004-11-04 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (enum cris_insn_version_usage): Tweak formatting and + comments. Remove member cris_ver_sim. Add members + cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, + cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. + (struct cris_support_reg, struct cris_cond15): New types. + (cris_conds15): Declare. + (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) + (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) + (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. + (NOP_Z_BITS): Define in terms of NOP_OPCODE. + (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and + SIZE_FIELD_UNSIGNED. + +2004-11-04 Jan Beulich <jbeulich@novell.com> + + * i386.h (sldx_Suf): Remove. + (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. + (q_FP): Define, implying no REX64. + (x_FP, sl_FP): Imply FloatMF. + (i386_optab): Split reg and mem forms of moving from segment registers + so that the memory forms can ignore the 16-/32-bit operand size + distinction. Adjust a few others for Intel mode. Remove *FP uses from + all non-floating-point instructions. Unite 32- and 64-bit forms of + movsx, movzx, and movd. Adjust floating point operations for the above + changes to the *FP macros. Add DefaultSize to floating point control + insns operating on larger memory ranges. Remove left over comments + hinting at certain insns being Intel-syntax ones where the ones + actually meant are already gone. + +2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> + + * crx.h: Add COPS_REG_INS - Coprocessor Special register + instruction type. + +2004-09-30 Paul Brook <paul@codesourcery.com> + + * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. + (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. + +2004-09-11 Theodore A. Roth <troth@openavr.org> + + * avr.h: Add support for + atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. + +2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> + + * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. + +2004-08-24 Dmitry Diky <diwil@spec.ru> + + * msp430.h (msp430_opc): Add new instructions. + (msp430_rcodes): Declare new instructions. + (msp430_hcodes): Likewise.. + +2004-08-13 Nick Clifton <nickc@redhat.com> + + PR/301 + * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX + processors. + +2004-08-30 Michal Ludvig <mludvig@suse.cz> + + * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. + +2004-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. + +2004-07-21 Jan Beulich <jbeulich@novell.com> + + * i386.h: Adjust instruction descriptions to better match the + specification. + +2004-07-16 Richard Earnshaw <rearnsha@arm.com> + + * arm.h: Remove all old content. Replace with architecture defines + from gas/config/tc-arm.c. + +2004-07-09 Andreas Schwab <schwab@suse.de> + + * m68k.h: Fix comment. + +2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> + + * crx.h: New file. + +2004-06-24 Alan Modra <amodra@bigpond.net.au> + + * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. + +2004-05-24 Peter Barada <peter@the-baradas.com> + + * m68k.h: Add 'size' to m68k_opcode. + +2004-05-05 Peter Barada <peter@the-baradas.com> + + * m68k.h: Switch from ColdFire chip name to core variant. + +2004-04-22 Peter Barada <peter@the-baradas.com> + + * m68k.h: Add mcfmac/mcfemac definitions. Update operand + descriptions for new EMAC cases. + Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly + handle Motorola MAC syntax. + Allow disassembly of ColdFire V4e object files. 2004-03-16 Alan Modra <amodra@bigpond.net.au> * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. +2004-03-12 Jakub Jelinek <jakub@redhat.com> + + * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. + 2004-03-12 Michal Ludvig <mludvig@suse.cz> * i386.h (i386_optab): Added xstore as an alias for xstorerng. diff --git a/contrib/binutils/include/opcode/ChangeLog-9103 b/contrib/binutils/include/opcode/ChangeLog-9103 index 0cdb1f3..9a04bf5 100644 --- a/contrib/binutils/include/opcode/ChangeLog-9103 +++ b/contrib/binutils/include/opcode/ChangeLog-9103 @@ -1,3 +1,22 @@ +2005-04-13 H.J. Lu <hongjiu.lu@intel.com> + + 2003-11-18 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + * mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB. + + 2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com> + * tic4x.h: Namespace cleanup. Replace s/c4x/tic4x + + 2002-11-16 Klee Dienes <kdienes@apple.com> + * m88k.h (INSTAB): Remove 'next' field. + (instruction): Remove definition; replace with extern declaration + and mark as const. + + 2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + * tic4x.h: New file. + + 2002-07-25 Richard Sandiford <rsandifo@redhat.com> + * mips.h (CPU_R2000): Remove. + 2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com> Bernardo Innocenti <bernie@develer.com> diff --git a/contrib/binutils/include/opcode/alpha.h b/contrib/binutils/include/opcode/alpha.h index efe1626..22c85a1 100644 --- a/contrib/binutils/include/opcode/alpha.h +++ b/contrib/binutils/include/opcode/alpha.h @@ -17,7 +17,7 @@ the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #ifndef OPCODE_ALPHA_H #define OPCODE_ALPHA_H diff --git a/contrib/binutils/include/opcode/arc.h b/contrib/binutils/include/opcode/arc.h index 629979d..8ddcf54 100644 --- a/contrib/binutils/include/opcode/arc.h +++ b/contrib/binutils/include/opcode/arc.h @@ -18,8 +18,8 @@ You should have received a copy of the GNU General Public License along with GAS or GDB; see the file COPYING. If not, write to - the Free Software Foundation, 59 Temple Place - Suite 330, Boston, - MA 02111-1307, USA. */ + the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ /* List of the various cpu types. diff --git a/contrib/binutils/include/opcode/arm.h b/contrib/binutils/include/opcode/arm.h index 99bb9a6..24a89cf 100644 --- a/contrib/binutils/include/opcode/arm.h +++ b/contrib/binutils/include/opcode/arm.h @@ -1,294 +1,197 @@ -/* ARM opcode list. - Copyright 1989, 1991 Free Software Foundation, Inc. - -This file is part of GDB and GAS. - -GDB and GAS are free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB and GAS are distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB or GAS; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* types of instruction (encoded in bits 26 and 27 of the instruction) */ - -#define TYPE_ARITHMETIC 0 -#define TYPE_LDR_STR 1 -#define TYPE_BLOCK_BRANCH 2 -#define TYPE_SWI 3 - -/* bit 25 decides whether an instruction is a block move or a branch */ -#define SUBTYPE_BLOCK 0 -#define SUBTYPE_BRANCH 1 - -/* codes to distinguish the arithmetic instructions */ - -#define OPCODE_AND 0 -#define OPCODE_EOR 1 -#define OPCODE_SUB 2 -#define OPCODE_RSB 3 -#define OPCODE_ADD 4 -#define OPCODE_ADC 5 -#define OPCODE_SBC 6 -#define OPCODE_RSC 7 -#define OPCODE_TST 8 -#define OPCODE_TEQ 9 -#define OPCODE_CMP 10 -#define OPCODE_CMN 11 -#define OPCODE_ORR 12 -#define OPCODE_MOV 13 -#define OPCODE_BIC 14 -#define OPCODE_MVN 15 - -/* condition codes */ - -#define COND_EQ 0 -#define COND_NE 1 -#define COND_CS 2 -#define COND_CC 3 -#define COND_MI 4 -#define COND_PL 5 -#define COND_VS 6 -#define COND_VC 7 -#define COND_HI 8 -#define COND_LS 9 -#define COND_GE 10 -#define COND_LT 11 -#define COND_GT 12 -#define COND_LE 13 -#define COND_AL 14 -#define COND_NV 15 - -/* Describes the format of an ARM machine instruction */ - -struct generic_fmt { - unsigned rest :25; /* the rest of the instruction */ - unsigned subtype :1; /* used to decide between block and branch */ - unsigned type :2; /* one of TYPE_* */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct arith_fmt { - unsigned operand2 :12; /* #nn or rn or rn shift #m or rn shift rm */ - unsigned dest :4; /* place where the answer goes */ - unsigned operand1 :4; /* first operand to instruction */ - unsigned set :1; /* == 1 means set processor flags */ - unsigned opcode :4; /* one of OPCODE_* defined above */ - unsigned immed :1; /* operand2 is an immediate value */ - unsigned type :2; /* == TYPE_ARITHMETIC */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct ldr_str_fmt { - unsigned offset :12; /* #nn or rn or rn shift #m */ - unsigned reg :4; /* destination for LDR, source for STR */ - unsigned base :4; /* base register */ - unsigned is_load :1; /* == 1 for LDR */ - unsigned writeback :1; /* == 1 means write back (base+offset) into base */ - unsigned byte :1; /* == 1 means byte access else word */ - unsigned up :1; /* == 1 means add offset else subtract it */ - unsigned pre_index :1; /* == 1 means [a,b] form else [a],b form */ - unsigned immed :1; /* == 0 means immediate offset */ - unsigned type :2; /* == TYPE_LDR_STR */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct block_fmt { - unsigned mask :16; /* register mask */ - unsigned base :4; /* register used as base of move */ - unsigned is_load :1; /* == 1 for LDM */ - unsigned writeback :1; /* == 1 means update base after move */ - unsigned set :1; /* == 1 means set flags in pc if included in mask */ - unsigned increment :1; /* == 1 means increment base register */ - unsigned before :1; /* == 1 means inc/dec before each move */ - unsigned is_block :1; /* == SUBTYPE_BLOCK */ - unsigned type :2; /* == TYPE_BLOCK_BRANCH */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct branch_fmt { - unsigned dest :24; /* destination of the branch */ - unsigned link :1; /* branch with link (function call) */ - unsigned is_branch :1; /* == SUBTYPE_BRANCH */ - unsigned type :2; /* == TYPE_BLOCK_BRANCH */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -#define ROUND_N 0 -#define ROUND_P 1 -#define ROUND_M 2 -#define ROUND_Z 3 - -#define FLOAT2_MVF 0 -#define FLOAT2_MNF 1 -#define FLOAT2_ABS 2 -#define FLOAT2_RND 3 -#define FLOAT2_SQT 4 -#define FLOAT2_LOG 5 -#define FLOAT2_LGN 6 -#define FLOAT2_EXP 7 -#define FLOAT2_SIN 8 -#define FLOAT2_COS 9 -#define FLOAT2_TAN 10 -#define FLOAT2_ASN 11 -#define FLOAT2_ACS 12 -#define FLOAT2_ATN 13 - -#define FLOAT3_ADF 0 -#define FLOAT3_MUF 1 -#define FLOAT3_SUF 2 -#define FLOAT3_RSF 3 -#define FLOAT3_DVF 4 -#define FLOAT3_RDF 5 -#define FLOAT3_POW 6 -#define FLOAT3_RPW 7 -#define FLOAT3_RMF 8 -#define FLOAT3_FML 9 -#define FLOAT3_FDV 10 -#define FLOAT3_FRD 11 -#define FLOAT3_POL 12 - -struct float2_fmt { - unsigned operand2 :3; /* second operand */ - unsigned immed :1; /* == 1 if second operand is a constant */ - unsigned pad1 :1; /* == 0 */ - unsigned rounding :2; /* ROUND_* */ - unsigned is_double :1; /* == 1 if precision is double (only if not extended) */ - unsigned pad2 :4; /* == 1 */ - unsigned dest :3; /* destination */ - unsigned is_2_op :1; /* == 1 if 2 operand ins */ - unsigned operand1 :3; /* first operand (only of is_2_op == 0) */ - unsigned is_extended :1; /* == 1 if precision is extended */ - unsigned opcode :4; /* FLOAT2_* or FLOAT3_* depending on is_2_op */ - unsigned must_be_2 :2; /* == 2 */ - unsigned type :2; /* == TYPE_SWI */ - unsigned cond :4; /* COND_* */ -}; - -struct swi_fmt { - unsigned argument :24; /* argument to SWI (syscall number) */ - unsigned must_be_3 :2; /* == 3 */ - unsigned type :2; /* == TYPE_SWI */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -union insn_fmt { - struct generic_fmt generic; - struct arith_fmt arith; - struct ldr_str_fmt ldr_str; - struct block_fmt block; - struct branch_fmt branch; - struct swi_fmt swi; - unsigned long ins; -}; - -struct opcode { - unsigned long value, mask; /* recognise instruction if (op&mask)==value */ - char *assembler; /* how to disassemble this instruction */ -}; - -/* format of the assembler string : - - %% % - %<bitfield>d print the bitfield in decimal - %<bitfield>x print the bitfield in hex - %<bitfield>r print as an ARM register - %<bitfield>f print a floating point constant if >7 else an fp register - %c print condition code (always bits 28-31) - %P print floating point precision in arithmetic insn - %Q print floating point precision in ldf/stf insn - %R print floating point rounding mode - %<bitnum>'c print specified char iff bit is one - %<bitnum>`c print specified char iff bit is zero - %<bitnum>?ab print a if bit is one else print b - %p print 'p' iff bits 12-15 are 15 - %o print operand2 (immediate or register + shift) - %a print address for ldr/str instruction - %b print branch destination - %A print address for ldc/stc/ldf/stf instruction - %m print register mask for ldm/stm instruction -*/ - -static struct opcode opcodes[] = { - /* ARM instructions */ - 0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r", - 0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r", - 0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o", - 0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o", - 0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o", - 0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o", - 0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o", - 0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o", - 0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o", - 0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o", - 0x01000000, 0x0de00000, "tst%c%p %16-19r, %o", - 0x01200000, 0x0de00000, "teq%c%p %16-19r, %o", - 0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o", - 0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o", - 0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o", - 0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o", - 0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o", - 0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o", - 0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a", - 0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a", - 0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m", - 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^", - 0x0a000000, 0x0e000000, "b%c%24'l %b", - 0x0f000000, 0x0f000000, "swi%c %0-23x", - /* Floating point coprocessor instructions */ - 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f", - 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f", - 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f", - 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f", - 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f", - 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f", - 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f", - 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f", - 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f", - 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f", - 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f", - 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f", - 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f", - 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f", - 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f", - 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f", - 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f", - 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r", - 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f", - 0x0e200110, 0x0fff0fff, "wfs%c %12-15r", - 0x0e300110, 0x0fff0fff, "rfs%c %12-15r", - 0x0e400110, 0x0fff0fff, "wfc%c %12-15r", - 0x0e500110, 0x0fff0fff, "rfc%c %12-15r", - 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f", - 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f", - 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f", - 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f", - 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A", - 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A", - /* Generic coprocessor instructions */ - 0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}", - 0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", - 0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", - 0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A", - 0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A", - /* the rest */ - 0x00000000, 0x00000000, "undefined instruction %0-31x", -}; -#define N_OPCODES (sizeof opcodes / sizeof opcodes[0]) +/* ARM assembler/disassembler support. + Copyright 2004 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + GDB and GAS are free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 1, or (at + your option) any later version. + + GDB and GAS are distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GDB or GAS; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +/* The following bitmasks control CPU extensions: */ +#define ARM_EXT_V1 0x00000001 /* All processors (core set). */ +#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ +#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ +#define ARM_EXT_V3 0x00000008 /* MSR MRS. */ +#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ +#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ +#define ARM_EXT_V4T 0x00000040 /* Thumb. */ +#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ +#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ +#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ +#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ +#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ +#define ARM_EXT_V6 0x00001000 /* ARM V6. */ +#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ +#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */ +#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ +#define ARM_EXT_DIV 0x00010000 /* Integer division. */ +/* The 'M' in Arm V7M stands for Microcontroller. + On earlier architecture variants it stands for Multiply. */ +#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ +#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ +#define ARM_EXT_V7 0x00080000 /* Arm V7. */ +#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ +#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ +#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ + +/* Co-processor space extensions. */ +#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ +#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ +#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ +#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ + +#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ +#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ +#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ +#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ +#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ +#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ +#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ +#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ +#define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */ +#define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */ + +/* Architectures are the sum of the base and extensions. The ARM ARM (rev E) + defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, + ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add + three more to cover cores prior to ARM6. Finally, there are cores which + implement further extensions in the co-processor space. */ +#define ARM_AEXT_V1 ARM_EXT_V1 +#define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) +#define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) +#define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) +#define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) +#define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) +#define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) +#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) +#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) +#define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) +#define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) +#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) +#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) +#define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) +#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) +#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) +#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) +#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) +#define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z) +#define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z) +#define ARM_AEXT_V6T2 (ARM_AEXT_V6 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM) +#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) +#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z) +#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z) +#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7) +#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) +#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) +#define ARM_AEXT_NOTM \ + (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM) +#define ARM_AEXT_V7M \ + ((ARM_AEXT_V7_ARM | ARM_EXT_V7M | ARM_EXT_DIV) & ~(ARM_AEXT_NOTM)) +#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) + +/* Processors with specific extensions in the co-processor space. */ +#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) +#define ARM_ARCH_IWMMXT \ + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) +#define ARM_ARCH_IWMMXT2 \ + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) + +#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) +#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) +#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) +#define FPU_VFP_V3 (FPU_VFP_V2 | FPU_VFP_EXT_V3) +#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ + | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1) +#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) + +/* Deprecated */ +#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) + +#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) +#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) + +#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) +#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) +#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) +#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) +#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) +#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ + ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) +#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) + +#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) + +#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) + +#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) +#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) +#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) +#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) +#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) +#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) +#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) +#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) +#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) +#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) +#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) +#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) +#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) +#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) +#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) +#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) +#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) +#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) +#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) +#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) +#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) +#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) +#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) +#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) +#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) +#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) +#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) +#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) + +/* Some useful combinations: */ +#define ARM_ARCH_NONE ARM_FEATURE (0, 0) +#define FPU_NONE ARM_FEATURE (0, 0) +#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ +#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) +#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) + +/* There are too many feature bits to fit in a single word, so use a + structure. For simplicity we put all core features in one word and + everything else in the other. */ +typedef struct +{ + unsigned long core; + unsigned long coproc; +} arm_feature_set; + +#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ + (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) + +#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ + do { \ + (TARG).core = (F1).core | (F2).core; \ + (TARG).coproc = (F1).coproc | (F2).coproc; \ + } while (0) + +#define ARM_CLEAR_FEATURE(TARG,F1,F2) \ + do { \ + (TARG).core = (F1).core &~ (F2).core; \ + (TARG).coproc = (F1).coproc &~ (F2).coproc; \ + } while (0) + +#define ARM_FEATURE(core, coproc) {(core), (coproc)} diff --git a/contrib/binutils/include/opcode/cgen.h b/contrib/binutils/include/opcode/cgen.h index 16366fd..e8fd5d3 100644 --- a/contrib/binutils/include/opcode/cgen.h +++ b/contrib/binutils/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. @@ -17,11 +17,13 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #ifndef CGEN_H #define CGEN_H +#include "symcat.h" +#include "cgen-bitset.h" /* ??? This file requires bfd.h but only to get bfd_vma. Seems like an awful lot to require just to get such a fundamental type. Perhaps the definition of bfd_vma can be moved outside of bfd.h. @@ -107,7 +109,13 @@ typedef struct cgen_cpu_desc *CGEN_CPU_DESC; /* Type of attribute values. */ -typedef int CGEN_ATTR_VALUE_TYPE; +typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE; +typedef int CGEN_ATTR_VALUE_ENUM_TYPE; +typedef union +{ + CGEN_ATTR_VALUE_BITSET_TYPE bitset; + CGEN_ATTR_VALUE_ENUM_TYPE nonbitset; +} CGEN_ATTR_VALUE_TYPE; /* Struct to record attribute information. */ @@ -153,7 +161,9 @@ struct { unsigned int bool; \ #define CGEN_ATTR_VALUE(obj, attr_table, attr) \ ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ - : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET])) + : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset)) +#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \ + ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset) /* Attribute name/value tables. These are used to assist parsing of descriptions at run-time. */ @@ -161,7 +171,7 @@ struct { unsigned int bool; \ typedef struct { const char * name; - CGEN_ATTR_VALUE_TYPE value; + unsigned value; } CGEN_ATTR_ENTRY; /* For each domain (ifld,hw,operand,insn), list of attributes. */ @@ -369,7 +379,8 @@ enum cgen_parse_operand_type { CGEN_PARSE_OPERAND_INIT, CGEN_PARSE_OPERAND_INTEGER, - CGEN_PARSE_OPERAND_ADDRESS + CGEN_PARSE_OPERAND_ADDRESS, + CGEN_PARSE_OPERAND_SYMBOLIC }; /* Values for indicating what was parsed. */ @@ -964,6 +975,7 @@ typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; typedef enum cgen_insn_attr { CGEN_INSN_ALIAS = 0 } CGEN_INSN_ATTR; +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS)) #endif /* This struct defines each entry in the instruction table. */ @@ -1015,6 +1027,8 @@ typedef struct /* Return value of attribute ATTR in INSN. */ #define CGEN_INSN_ATTR_VALUE(insn, attr) \ CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) +#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \ + CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) } CGEN_IBASE; /* Return non-zero if INSN is the "invalid" insn marker. */ @@ -1178,10 +1192,9 @@ typedef struct cgen_cpu_desc /* Bitmap of selected machine(s) (a la BFD machine number). */ int machs; - /* Bitmap of selected isa(s). - ??? Simultaneous multiple isas might not make sense, but it's not (yet) - precluded. */ - int isas; + /* Bitmap of selected isa(s). */ + CGEN_BITSET *isas; +#define CGEN_CPU_ISAS(cd) ((cd)->isas) /* Current endian. */ enum cgen_endian endian; diff --git a/contrib/binutils/include/opcode/convex.h b/contrib/binutils/include/opcode/convex.h index ccf5568..7843dce 100644 --- a/contrib/binutils/include/opcode/convex.h +++ b/contrib/binutils/include/opcode/convex.h @@ -15,7 +15,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #define xxx 0 #define rrr 1 diff --git a/contrib/binutils/include/opcode/cr16.h b/contrib/binutils/include/opcode/cr16.h new file mode 100644 index 0000000..b7e3be5 --- /dev/null +++ b/contrib/binutils/include/opcode/cr16.h @@ -0,0 +1,437 @@ +/* cr16.h -- Header file for CR16 opcode and register tables. + Copyright 2007 Free Software Foundation, Inc. + Contributed by M R Swami Reddy + + This file is part of GAS, GDB and the GNU binutils. + + GAS, GDB, and GNU binutils is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2, or (at your + option) any later version. + + GAS, GDB, and GNU binutils are distributed in the hope that they will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _CR16_H_ +#define _CR16_H_ + +/* CR16 core Registers : + The enums are used as indices to CR16 registers table (cr16_regtab). + Therefore, order MUST be preserved. */ + +typedef enum + { + /* 16-bit general purpose registers. */ + r0, r1, r2, r3, + r4, r5, r6, r7, + r8, r9, r10, r11, + r12_L = 12, r13_L = 13, ra = 14, sp_L = 15, + + /* 32-bit general purpose registers. */ + r12 = 12, r13 = 13, r14 = 14, r15 = 15, + era = 14, sp = 15, RA, + + /* Not a register. */ + nullregister, + MAX_REG + } +reg; + +/* CR16 processor registers and special registers : + The enums are used as indices to CR16 processor registers table + (cr16_pregtab). Therefore, order MUST be preserved. */ + +typedef enum + { + /* processor registers. */ + dbs = MAX_REG, + dsr, dcrl, dcrh, + car0l, car0h, car1l, car1h, + cfg, psr, intbasel, intbaseh, + ispl, isph, uspl, usph, + dcr = dcrl, + car0 = car0l, + car1 = car1l, + intbase = intbasel, + isp = ispl, + usp = uspl, + /* Not a processor register. */ + nullpregister = usph + 1, + MAX_PREG + } +preg; + +/* CR16 Register types. */ + +typedef enum + { + CR16_R_REGTYPE, /* r<N> */ + CR16_RP_REGTYPE, /* reg pair */ + CR16_P_REGTYPE /* Processor register */ + } +reg_type; + +/* CR16 argument types : + The argument types correspond to instructions operands + + Argument types : + r - register + rp - register pair + c - constant + i - immediate + idxr - index with register + idxrp - index with register pair + rbase - register base + rpbase - register pair base + pr - processor register */ + +typedef enum + { + arg_r, + arg_c, + arg_cr, + arg_crp, + arg_ic, + arg_icr, + arg_idxr, + arg_idxrp, + arg_rbase, + arg_rpbase, + arg_rp, + arg_pr, + arg_prp, + arg_cc, + arg_ra, + /* Not an argument. */ + nullargs + } +argtype; + +/* CR16 operand types:The operand types correspond to instructions operands.*/ + +typedef enum + { + dummy, + /* N-bit signed immediate. */ + imm3, imm4, imm5, imm6, imm16, imm20, imm32, + /* N-bit unsigned immediate. */ + uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, + /* N-bit signed displacement. */ + disps5, disps17, disps25, + /* N-bit unsigned displacement. */ + dispe9, + /* N-bit absolute address. */ + abs20, abs24, + /* Register relative. */ + rra, rbase, rbase_disps20, rbase_dispe20, + /* Register pair relative. */ + rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16, + rpbase_disps20, rpbase_dispe20, + /* Register index. */ + rindex7_abs20, rindex8_abs20, + /* Register pair index. */ + rpindex_disps0, rpindex_disps14, rpindex_disps20, + /* register. */ + regr, + /* register pair. */ + regp, + /* processor register. */ + pregr, + /* processor register 32 bit. */ + pregrp, + /* condition code - 4 bit. */ + cc, + /* Not an operand. */ + nulloperand, + /* Maximum supported operand. */ + MAX_OPRD + } +operand_type; + +/* CR16 instruction types. */ + +#define NO_TYPE_INS 0 +#define ARITH_INS 1 +#define LD_STOR_INS 2 +#define BRANCH_INS 3 +#define ARITH_BYTE_INS 4 +#define SHIFT_INS 5 +#define BRANCH_NEQ_INS 6 +#define LD_STOR_INS_INC 7 +#define STOR_IMM_INS 8 +#define CSTBIT_INS 9 + +/* Maximum value supported for instruction types. */ +#define CR16_INS_MAX (1 << 4) +/* Mask to record an instruction type. */ +#define CR16_INS_MASK (CR16_INS_MAX - 1) +/* Return instruction type, given instruction's attributes. */ +#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK) + +/* Indicates whether this instruction has a register list as parameter. */ +#define REG_LIST CR16_INS_MAX + +/* The operands in binary and assembly are placed in reverse order. + load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ +#define REVERSE_MATCH (1 << 5) + +/* Printing formats, where the instruction prefix isn't consecutive. */ +#define FMT_1 (1 << 9) /* 0xF0F00000 */ +#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ +#define FMT_3 (1 << 11) /* 0xFFF00F00 */ +#define FMT_4 (1 << 12) /* 0xFFF0F000 */ +#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ +#define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) + +/* Indicates whether this instruction can be relaxed. */ +#define RELAXABLE (1 << 14) + +/* Indicates that instruction uses user registers (and not + general-purpose registers) as operands. */ +#define USER_REG (1 << 15) + + +/* Instruction shouldn't allow 'sp' usage. */ +#define NO_SP (1 << 17) + +/* Instruction shouldn't allow to push a register which is used as a rptr. */ +#define NO_RPTR (1 << 18) + +/* Maximum operands per instruction. */ +#define MAX_OPERANDS 5 +/* Maximum register name length. */ +#define MAX_REGNAME_LEN 10 +/* Maximum instruction length. */ +#define MAX_INST_LEN 256 + + +/* Values defined for the flags field of a struct operand_entry. */ + +/* Operand must be an unsigned number. */ +#define OP_UNSIGNED (1 << 0) +/* Operand must be a signed number. */ +#define OP_SIGNED (1 << 1) +/* Operand must be a negative number. */ +#define OP_NEG (1 << 2) +/* A special load/stor 4-bit unsigned displacement operand. */ +#define OP_DEC (1 << 3) +/* Operand must be an even number. */ +#define OP_EVEN (1 << 4) +/* Operand is shifted right. */ +#define OP_SHIFT (1 << 5) +/* Operand is shifted right and decremented. */ +#define OP_SHIFT_DEC (1 << 6) +/* Operand has reserved escape sequences. */ +#define OP_ESC (1 << 7) +/* Operand must be a ABS20 number. */ +#define OP_ABS20 (1 << 8) +/* Operand must be a ABS24 number. */ +#define OP_ABS24 (1 << 9) +/* Operand has reserved escape sequences type 1. */ +#define OP_ESC1 (1 << 10) + +/* Single operand description. */ + +typedef struct + { + /* Operand type. */ + operand_type op_type; + /* Operand location within the opcode. */ + unsigned int shift; + } +operand_desc; + +/* Instruction data structure used in instruction table. */ + +typedef struct + { + /* Name. */ + const char *mnemonic; + /* Size (in words). */ + unsigned int size; + /* Constant prefix (matched by the disassembler). */ + unsigned long match; /* ie opcode */ + /* Match size (in bits). */ + /* MASK: if( (i & match_bits) == match ) then match */ + int match_bits; + /* Attributes. */ + unsigned int flags; + /* Operands (always last, so unreferenced operands are initialized). */ + operand_desc operands[MAX_OPERANDS]; + } +inst; + +/* Data structure for a single instruction's arguments (Operands). */ + +typedef struct + { + /* Register or base register. */ + reg r; + /* Register pair register. */ + reg rp; + /* Index register. */ + reg i_r; + /* Processor register. */ + preg pr; + /* Processor register. 32 bit */ + preg prp; + /* Constant/immediate/absolute value. */ + long constant; + /* CC code. */ + unsigned int cc; + /* Scaled index mode. */ + unsigned int scale; + /* Argument type. */ + argtype type; + /* Size of the argument (in bits) required to represent. */ + int size; + /* The type of the expression. */ + unsigned char X_op; + } +argument; + +/* Internal structure to hold the various entities + corresponding to the current assembling instruction. */ + +typedef struct + { + /* Number of arguments. */ + int nargs; + /* The argument data structure for storing args (operands). */ + argument arg[MAX_OPERANDS]; +/* The following fields are required only by CR16-assembler. */ +#ifdef TC_CR16 + /* Expression used for setting the fixups (if any). */ + expressionS exp; + bfd_reloc_code_real_type rtype; +#endif /* TC_CR16 */ + /* Instruction size (in bytes). */ + int size; + } +ins; + +/* Structure to hold information about predefined operands. */ + +typedef struct + { + /* Size (in bits). */ + unsigned int bit_size; + /* Argument type. */ + argtype arg_type; + /* One bit syntax flags. */ + int flags; + } +operand_entry; + +/* Structure to hold trap handler information. */ + +typedef struct + { + /* Trap name. */ + char *name; + /* Index in dispatch table. */ + unsigned int entry; + } +trap_entry; + +/* Structure to hold information about predefined registers. */ + +typedef struct + { + /* Name (string representation). */ + char *name; + /* Value (enum representation). */ + union + { + /* Register. */ + reg reg_val; + /* processor register. */ + preg preg_val; + } value; + /* Register image. */ + int image; + /* Register type. */ + reg_type type; + } +reg_entry; + +/* CR16 opcode table. */ +extern const inst cr16_instruction[]; +extern const unsigned int cr16_num_opcodes; +#define NUMOPCODES cr16_num_opcodes + +/* CR16 operands table. */ +extern const operand_entry cr16_optab[]; + +/* CR16 registers table. */ +extern const reg_entry cr16_regtab[]; +extern const unsigned int cr16_num_regs; +#define NUMREGS cr16_num_regs + +/* CR16 register pair table. */ +extern const reg_entry cr16_regptab[]; +extern const unsigned int cr16_num_regps; +#define NUMREGPS cr16_num_regps + +/* CR16 processor registers table. */ +extern const reg_entry cr16_pregtab[]; +extern const unsigned int cr16_num_pregs; +#define NUMPREGS cr16_num_pregs + +/* CR16 processor registers - 32 bit table. */ +extern const reg_entry cr16_pregptab[]; +extern const unsigned int cr16_num_pregps; +#define NUMPREGPS cr16_num_pregps + +/* CR16 trap/interrupt table. */ +extern const trap_entry cr16_traps[]; +extern const unsigned int cr16_num_traps; +#define NUMTRAPS cr16_num_traps + +/* CR16 CC - codes bit table. */ +extern const char * cr16_b_cond_tab[]; +extern const unsigned int cr16_num_cc; +#define NUMCC cr16_num_cc; + + +/* Table of instructions with no operands. */ +extern const char * cr16_no_op_insn[]; + +/* Current instruction we're assembling. */ +extern const inst *instruction; + +/* A macro for representing the instruction "constant" opcode, that is, + the FIXED part of the instruction. The "constant" opcode is represented + as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) + over that range. */ +#define BIN(OPC,SHIFT) (OPC << SHIFT) + +/* Is the current instruction type is TYPE ? */ +#define IS_INSN_TYPE(TYPE) \ + (CR16_INS_TYPE (instruction->flags) == TYPE) + +/* Is the current instruction mnemonic is MNEMONIC ? */ +#define IS_INSN_MNEMONIC(MNEMONIC) \ + (strcmp (instruction->mnemonic, MNEMONIC) == 0) + +/* Does the current instruction has register list ? */ +#define INST_HAS_REG_LIST \ + (instruction->flags & REG_LIST) + + +/* Utility macros for string comparison. */ +#define streq(a, b) (strcmp (a, b) == 0) +#define strneq(a, b, c) (strncmp (a, b, c) == 0) + +/* Long long type handling. */ +/* Replace all appearances of 'long long int' with LONGLONG. */ +typedef long long int LONGLONG; +typedef unsigned long long ULONGLONG; + +#endif /* _CR16_H_ */ diff --git a/contrib/binutils/include/opcode/i386.h b/contrib/binutils/include/opcode/i386.h index 5e3673e..4fe769a 100644 --- a/contrib/binutils/include/opcode/i386.h +++ b/contrib/binutils/include/opcode/i386.h @@ -1,23 +1,23 @@ -/* opcode/i386.h -- Intel 80386 opcode table +/* opcode/i386.h -- Intel 80386 opcode macros Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004 + 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. -This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. + This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived ix86 Unix assemblers, generate floating point instructions with @@ -31,7 +31,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ This happens with all the non-commutative arithmetic floating point operations with two register operands, where the source register is - %st, and destination register is %st(i). See FloatDR below. + %st, and destination register is %st(i). The affected opcode map is dceX, dcfX, deeX, defX. */ @@ -48,1551 +48,68 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define OLDGCC_COMPAT SYSV386_COMPAT #endif -static const template i386_optab[] = { - -#define X None -#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf) -#define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) -#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf) -#define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf) -#define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf) -#define wlq_Suf (No_bSuf|No_sSuf|No_xSuf) -#define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) -#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf) -#define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) -#define sldx_Suf (No_bSuf|No_wSuf|No_qSuf) -#define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) -#define bwlq_Suf (No_sSuf|No_xSuf) -#define FP (NoSuf|IgnoreSize) -#define l_FP (l_Suf|IgnoreSize) -#define x_FP (x_Suf|IgnoreSize) -#define sl_FP (sl_Suf|IgnoreSize) -#if SYSV386_COMPAT -/* Someone forgot that the FloatR bit reverses the operation when not - equal to the FloatD bit. ie. Changing only FloatD results in the - destination being swapped *and* the direction being reversed. */ -#define FloatDR FloatD -#else -#define FloatDR (FloatD|FloatR) -#endif - -/* Move instructions. */ #define MOV_AX_DISP32 0xa0 -/* In the 64bit mode the short form mov immediate is redefined to have - 64bit displacement value. */ -{ "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, -{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -/* In the 64bit mode the short form mov immediate is redefined to have - 64bit displacement value. */ -{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } }, -{ "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } }, -{ "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, -/* The segment register moves accept WordReg so that a segment register - can be copied to a 32 bit register, and vice versa, without using a - size prefix. When moving to a 32 bit register, the upper 16 bits - are set to an implementation defined value (on the Pentium Pro, - the implementation defined value is zero). */ -{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } }, -{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } }, -{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } }, -{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } }, -/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit - mode they are 64bit.*/ -{ "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, -{ "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, -{ "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, - -/* Move with sign extend. */ -/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid - conflict with the "movs" string move instruction. */ -{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, -{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, -{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} }, -{"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} }, -{"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, -/* Intel Syntax next 5 insns */ -{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -{"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, -{"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, - -/* Move with zero extend. */ -{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -/* These instructions are not particulary usefull, since the zero extend - 32->64 is implicit, but we can encode them. */ -{"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, -/* Intel Syntax next 4 insns */ -{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -/* These instructions are not particulary usefull, since the zero extend - 32->64 is implicit, but we can encode them. */ -{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, - -/* Push instructions. */ -{"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, -{"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, -{"push", 1, 0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, -{"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, -/* In 64bit mode, the operand size is implicitly 64bit. */ -{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } }, -{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, -{"push", 1, 0x06, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, -{"push", 1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, - -{"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, - -/* Pop instructions. */ -{"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, -{"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, #define POP_SEG_SHORT 0x07 -{"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, -{"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, -/* In 64bit mode, the operand size is implicitly 64bit. */ -{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } }, -{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } }, -{"pop", 1, 0x07, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, -{"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, - -{"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, - -/* Exchange instructions. - xchg commutes: we allow both operand orders. - - In the 64bit code, xchg eax, eax is reused for new nop instruction. - */ -{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } }, -{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } }, -{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, - -/* In/out from ports. */ -{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, -{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, -{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, -{"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, -{"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } }, -{"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, -{"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, -{"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, - -/* Load effective address. */ -{"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, - -/* Load segment registers from memory. */ -{"lds", 2, 0xc5, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, -{"les", 2, 0xc4, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lfs", 2, 0x0fb4, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lgs", 2, 0x0fb5, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lss", 2, 0x0fb2, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, - -/* Flags register instructions. */ -{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, -{"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} }, -{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, -{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, -{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, -{"lahf", 0, 0x9f, X, CpuNo64,NoSuf, { 0, 0, 0} }, -{"sahf", 0, 0x9e, X, CpuNo64,NoSuf, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"popf", 0, 0x9d, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, -{"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, -{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, -{"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, - -/* Arithmetic. */ -{"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} }, -{"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} }, -{"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, -{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -/* clr with 1 operand is really xor with 2 operands. */ -{"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, - -{"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} }, -{"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} }, -{"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} }, -{"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} }, -{"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} }, -{"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} }, -{"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} }, -{"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} }, - -/* Conversion insns. */ -/* Intel naming */ -{"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, -{"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, -/* AT&T naming */ -{"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, -{"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, - -/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are - expanding 64-bit multiplies, and *cannot* be selected to accomplish - 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) - These multiplies can only be selected with single operand forms. */ -{"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, -{"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} }, -/* imul with 2 operands mimics imul with 3 by putting the register in - both i.rm.reg & i.rm.regmem fields. regKludge enables this - transformation. */ -{"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, -{"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} }, - -{"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, -{"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, - -{"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, -{"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, -{"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, - -{"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, -{"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, -{"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, - -/* Control transfer instructions. */ -{"call", 1, 0xe8, X, 0, wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, -{"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} }, -/* Intel Syntax */ -{"call", 2, 0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, -/* Intel Syntax */ -{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, -{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, -{"lcall", 1, 0xff, 3, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, -{"lcall", 1, 0xff, 3, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64,{ WordMem|JumpAbsolute, 0, 0} }, - #define JUMP_PC_RELATIVE 0xeb -{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -/* Intel Syntax */ -{"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -/* Intel Syntax */ -{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} }, -{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"ljmp", 1, 0xff, 5, CpuNo64, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, -{"ljmp", 1, 0xff, 5, Cpu64, q_Suf|Modrm|NoRex64, { WordMem|JumpAbsolute, 0, 0} }, - -{"ret", 0, 0xc3, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, -{"ret", 1, 0xc2, X, CpuNo64,wlq_Suf|DefaultSize, { Imm16, 0, 0} }, -{"ret", 0, 0xc3, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"ret", 1, 0xc2, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, -{"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, -{"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} }, -{"enter", 2, 0xc8, X, Cpu186, wlq_Suf|DefaultSize, { Imm16, Imm8, 0} }, -{"leave", 0, 0xc9, X, Cpu186, wlq_Suf|DefaultSize, { 0, 0, 0} }, - -/* Conditional jumps. */ -{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, - -/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ -{"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} }, -{"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, -{"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, -{"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} }, - -/* The loop instructions also use the address size prefix to select - %cx rather than %ecx for the loop count, so the `w' form of these - instructions emit an address size prefix rather than a data size - prefix. */ -{"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, - -/* Set byte on flag instructions. */ -{"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, - -/* String manipulation. */ -{"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, -{"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, -{"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, -{"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, -{"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, -{"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, -{"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, -{"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, -{"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, -{"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, -{"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, -{"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, -{"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, -{"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, -{"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} }, -{"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} }, - -/* Bit manipulation. */ -{"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, - -/* Interrupts & op. sys insns. */ -/* See gas/config/tc-i386.c for conversion of 'int $3' into the special - int 3 insn. */ -#define INT_OPCODE 0xcd +#define INT_OPCODE 0xcd #define INT3_OPCODE 0xcc -{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, -{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, -{"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} }, -{"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, -/* i386sl, i486sl, later 486, and Pentium. */ -{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, - -{"bound", 2, 0x62, X, Cpu186, wlq_Suf|Modrm, { WordReg, WordMem, 0} }, - -{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, -/* nop is actually 'xchgl %eax, %eax'. */ -{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, - -/* Protection control. */ -{"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, -{"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"lgdt", 1, 0x0f01, 2, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, -{"lidt", 1, 0x0f01, 3, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, -{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, - -{"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, -{"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, - -{"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, - -/* Floating point instructions. */ - -/* load */ -{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fld", 1, 0xd9, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -/* Intel Syntax */ -{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -/* Intel Syntax */ -{"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} }, - -/* store (no pop) */ -{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fst", 1, 0xd9, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -{"fist", 1, 0xdf, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, - -/* store (with pop) */ -{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fstp", 1, 0xd9, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -/* Intel Syntax */ -{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -/* Intel Syntax */ -{"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} }, - -/* exchange %st<n> with %st0 */ -{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fxch %st(1) */ -{"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} }, - -/* comparison (without pop) */ -{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fcom %st(1) */ -{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, -{"fcom", 1, 0xd8, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -{"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, - -/* comparison (with pop) */ -{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fcomp %st(1) */ -{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, -{"fcomp", 1, 0xd8, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -{"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, - -/* unordered comparison (with pop) */ -{"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fucom %st(1) */ -{"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} }, -{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fucomp %st(1) */ -{"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} }, -{"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} }, - -{"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} }, -{"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} }, - -/* load constants into %st0 */ -{"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} }, -{"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} }, -{"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} }, -{"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} }, -{"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} }, -{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, -{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, - -/* arithmetic */ - -/* add */ -{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, -/* alias for fadd %st(i), %st */ -{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for faddp */ -{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fadd", 1, 0xd8, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fiadd", 1, 0xde, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, - -{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for faddp %st, %st(1) */ -{"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} }, -{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, - -/* subtract */ -{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fsubp */ -{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, -#endif - -/* subtract reverse */ -{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fsubrp */ -{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, -#endif - -/* multiply */ -{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, -{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fmulp */ -{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, - -{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} }, -{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, - -/* divide */ -{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fdivp */ -{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, -#endif - -/* divide reverse */ -{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fdivrp */ -{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, -#endif - -{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} }, -{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} }, -{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} }, -{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} }, -{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} }, -{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} }, -{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} }, -{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} }, -{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} }, -{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} }, -{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} }, -{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} }, -{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} }, -{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} }, -{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} }, -{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} }, -{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} }, -{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} }, - -/* processor control */ -{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, -{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, -{"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} }, -{"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, -{"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, -{"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} }, -{"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, -{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, -{"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} }, -{"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, -{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, -{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, -{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, -/* Short forms of fldenv, fstenv use data size prefix. */ -{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, -{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, -{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, -{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, -{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, -{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, - -{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* P6:free st(i), pop st */ -{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} }, +/* The opcode for the fwait instruction, which disassembler treats as a + prefix when it can. */ #define FWAIT_OPCODE 0x9b -{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} }, - -/* Opcode prefixes; we allow them as separate insns too. */ - #define ADDR_PREFIX_OPCODE 0x67 -{"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, #define DATA_PREFIX_OPCODE 0x66 -{"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, #define LOCK_PREFIX_OPCODE 0xf0 -{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define CS_PREFIX_OPCODE 0x2e -{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define DS_PREFIX_OPCODE 0x3e -{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define ES_PREFIX_OPCODE 0x26 -{"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define FS_PREFIX_OPCODE 0x64 -{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, #define GS_PREFIX_OPCODE 0x65 -{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, #define SS_PREFIX_OPCODE 0x36 -{"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define REPNE_PREFIX_OPCODE 0xf2 #define REPE_PREFIX_OPCODE 0xf3 -{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, - -/* 486 extensions. */ - -{"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } }, -{"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, -{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, -{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} }, - -/* 586 and late 486 extensions. */ -{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, - -/* Pentium extensions. */ -{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} }, - -/* Pentium II/Pentium Pro extensions. */ -{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, -{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, -{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, -{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, -{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, -/* official undefined instr. */ -{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, -/* alias for ud2 */ -{"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, -/* 2nd. official undefined instr. */ -{"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} }, - -{"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, - -{"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, - -{"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, - -/* Pentium4 extensions. */ - -{"movnti", 2, 0x0fc3, X, CpuP4, FP|Modrm, { WordReg, WordMem, 0 } }, -{"clflush", 1, 0x0fae, 7, CpuP4, FP|Modrm, { ByteMem, 0, 0 } }, -{"lfence", 0, 0x0fae, 0xe8, CpuP4, FP|ImmExt, { 0, 0, 0 } }, -{"mfence", 0, 0x0fae, 0xf0, CpuP4, FP|ImmExt, { 0, 0, 0 } }, -{"pause", 0, 0xf390, X, CpuP4, FP, { 0, 0, 0 } }, - -/* MMX/SSE2 instructions. */ - -{"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } }, -{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, -{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg32|LLongMem, RegXMM, 0 } }, -{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg32|LLongMem, 0 } }, -/* Real MMX instructions. */ -{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, -{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, -{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, -/* In the 64bit mode the short form mov immediate is redefined to have - 64bit displacement value. */ -{"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, -{"movq", 2, 0xf30f7e,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movq", 2, 0x660fd6,X,CpuSSE2,FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, -{"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, -{"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, -/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit - mode they are 64bit.*/ -{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, -{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, -{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddb", 2, 0x660ffc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddw", 2, 0x660ffd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddd", 2, 0x660ffe,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddq", 2, 0x0fd4, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"paddq", 2, 0x660fd4,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsb", 2, 0x660fec,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsw", 2, 0x660fed,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusb", 2, 0x660fdc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusw", 2, 0x660fdd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pand", 2, 0x660fdb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pandn", 2, 0x660fdf,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhw", 2, 0x660fe5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmullw", 2, 0x660fd5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"por", 2, 0x660feb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x660ff1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psllw", 2, 0x660f71,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pslld", 2, 0x660ff2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"pslld", 2, 0x660f72,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllq", 2, 0x660ff3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psllq", 2, 0x660f73,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psraw", 2, 0x660fe1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psraw", 2, 0x660f71,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrad", 2, 0x660fe2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrad", 2, 0x660f72,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlw", 2, 0x660fd1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlw", 2, 0x660f71,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrld", 2, 0x660fd2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrld", 2, 0x660f72,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlq", 2, 0x660fd3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlq", 2, 0x660f73,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubb", 2, 0x660ff8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubw", 2, 0x660ff9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubd", 2, 0x660ffa,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubq", 2, 0x0ffb, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"psubq", 2, 0x660ffb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsb", 2, 0x660fe8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsw", 2, 0x660fe9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusb", 2, 0x660fd8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusw", 2, 0x660fd9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pxor", 2, 0x660fef,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* PIII Katmai New Instructions / SIMD instructions. */ - -{"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, -{"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, -{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, -{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, -{"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, -{"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } }, -{"movntdq", 2, 0x660fe7, X, CpuSSE2,FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, -{"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pextrw", 3, 0x0fc5, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } }, -{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } }, -{"pinsrw", 3, 0x0fc4, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, -{"pinsrw", 3, 0x660fc4, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, -{"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmaxsw", 2, 0x660fee, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmaxub", 2, 0x660fde, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmovmskb", 2, 0x0fd7, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } }, -{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, -{"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"psadbw", 2, 0x660ff6, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, -{"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"sfence", 0, 0x0fae, 0xf8, CpuSSE, FP|ImmExt, { 0, 0, 0 } }, -{"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, -{"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* SSE-2 instructions. */ - -{"addpd", 2, 0x660f58, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addsd", 2, 0xf20f58, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"andnpd", 2, 0x660f55, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"andpd", 2, 0x660f54, X, CpuSSE2, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -/* Intel mode string compare. */ -{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, -{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, -{"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, -{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, -{"divpd", 2, 0x660f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"divsd", 2, 0xf20f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"maxpd", 2, 0x660f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maxsd", 2, 0xf20f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"minpd", 2, 0x660f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"minsd", 2, 0xf20f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"movapd", 2, 0x660f28, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movapd", 2, 0x660f29, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movhpd", 2, 0x660f16, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movhpd", 2, 0x660f17, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movlpd", 2, 0x660f12, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, -/* Intel mode string move. */ -{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, -{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, -{"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movupd", 2, 0x660f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"mulpd", 2, 0x660f59, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mulsd", 2, 0xf20f59, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"orpd", 2, 0x660f56, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"shufpd", 3, 0x660fc6, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"sqrtpd", 2, 0x660f51, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"subpd", 2, 0x660f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"subsd", 2, 0xf20f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"ucomisd", 2, 0x660f2e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"unpckhpd", 2, 0x660f15, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"unpcklpd", 2, 0x660f14, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"xorpd", 2, 0x660f57, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, -{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movdqa", 2, 0x660f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movdqa", 2, 0x660f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movdqu", 2, 0xf30f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movdqu", 2, 0xf30f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegMMX, 0 } }, -{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, FP|Modrm, { RegMMX|InvMem, RegXMM, 0 } }, -{"pmuludq", 2, 0x0ff4, X, CpuSSE2, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmuludq", 2, 0x660ff4, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"pshufd", 3, 0x660f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pshufhw", 3, 0xf30f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pshuflw", 3, 0xf20f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pslldq", 2, 0x660f73, 7, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrldq", 2, 0x660f73, 3, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, -{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* Prescott New Instructions. */ - -{"addsubpd", 2, 0x660fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addsubps", 2, 0xf20fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -/* Intel Syntax */ -{"fisttpd", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, -{"fisttpq", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, -{"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, -{"haddpd", 2, 0x660f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"haddps", 2, 0xf20f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"hsubpd", 2, 0x660f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"hsubps", 2, 0xf20f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"lddqu", 2, 0xf20ff0, X, CpuPNI, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"monitor", 0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { 0, 0, 0} }, -/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */ -{"monitor", 3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { Reg32, Reg32, Reg32} }, -{"movddup", 2, 0xf20f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movshdup", 2, 0xf30f16, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movsldup", 2, 0xf30f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mwait", 0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { 0, 0, 0} }, -/* Need to ensure only "mwait %eax,%ecx" is accepted. */ -{"mwait", 2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { Reg32, Reg32, 0} }, - -/* AMD 3DNow! instructions. */ - -{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, -{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, -{"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } }, -{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -/* AMD extensions. */ -{"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} }, -{"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} }, -{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, +#define TWO_BYTE_OPCODE_ESCAPE 0x0f +#define NOP_OPCODE (char) 0x90 -/* VIA PadLock extensions. */ -{"xstorerng", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, -{"xcryptecb", 0, 0xf30fa7c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, -{"xcryptcbc", 0, 0xf30fa7d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, -{"xcryptcfb", 0, 0xf30fa7e0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, -{"xcryptofb", 0, 0xf30fa7e8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, -/* alias for xstorerng */ -{"xstore", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +/* register numbers */ +#define EBP_REG_NUM 5 +#define ESP_REG_NUM 4 -/* sentinel */ -{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } -}; -#undef X -#undef NoSuf -#undef b_Suf -#undef w_Suf -#undef l_Suf -#undef q_Suf -#undef x_Suf -#undef bw_Suf -#undef bl_Suf -#undef wl_Suf -#undef wlq_Suf -#undef sl_Suf -#undef bwl_Suf -#undef bwlq_Suf -#undef FP -#undef l_FP -#undef x_FP -#undef sl_FP +/* modrm_byte.regmem for twobyte escape */ +#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM +/* index_base_byte.index for no index register addressing */ +#define NO_INDEX_REGISTER ESP_REG_NUM +/* index_base_byte.base for no base register addressing */ +#define NO_BASE_REGISTER EBP_REG_NUM +#define NO_BASE_REGISTER_16 6 -#define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ +/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ +#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ +#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) +/* x86-64 extension prefix. */ +#define REX_OPCODE 0x40 -/* 386 register table. */ +/* Indicates 64 bit operand size. */ +#define REX_W 8 +/* High extension to reg field of modrm byte. */ +#define REX_R 4 +/* High extension to SIB index field. */ +#define REX_X 2 +/* High extension to base field of modrm or SIB, or reg field of opcode. */ +#define REX_B 1 -static const reg_entry i386_regtab[] = { - /* make %st first as we test for it */ - {"st", FloatReg|FloatAcc, 0, 0}, - /* 8 bit regs */ -#define REGNAM_AL 1 /* Entry in i386_regtab. */ - {"al", Reg8|Acc, 0, 0}, - {"cl", Reg8|ShiftCount, 0, 1}, - {"dl", Reg8, 0, 2}, - {"bl", Reg8, 0, 3}, - {"ah", Reg8, 0, 4}, - {"ch", Reg8, 0, 5}, - {"dh", Reg8, 0, 6}, - {"bh", Reg8, 0, 7}, - {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */ - {"cxl", Reg8, RegRex64, 1}, - {"dxl", Reg8, RegRex64, 2}, - {"bxl", Reg8, RegRex64, 3}, - {"spl", Reg8, RegRex64, 4}, - {"bpl", Reg8, RegRex64, 5}, - {"sil", Reg8, RegRex64, 6}, - {"dil", Reg8, RegRex64, 7}, - {"r8b", Reg8, RegRex64|RegRex, 0}, - {"r9b", Reg8, RegRex64|RegRex, 1}, - {"r10b", Reg8, RegRex64|RegRex, 2}, - {"r11b", Reg8, RegRex64|RegRex, 3}, - {"r12b", Reg8, RegRex64|RegRex, 4}, - {"r13b", Reg8, RegRex64|RegRex, 5}, - {"r14b", Reg8, RegRex64|RegRex, 6}, - {"r15b", Reg8, RegRex64|RegRex, 7}, - /* 16 bit regs */ -#define REGNAM_AX 25 - {"ax", Reg16|Acc, 0, 0}, - {"cx", Reg16, 0, 1}, - {"dx", Reg16|InOutPortReg, 0, 2}, - {"bx", Reg16|BaseIndex, 0, 3}, - {"sp", Reg16, 0, 4}, - {"bp", Reg16|BaseIndex, 0, 5}, - {"si", Reg16|BaseIndex, 0, 6}, - {"di", Reg16|BaseIndex, 0, 7}, - {"r8w", Reg16, RegRex, 0}, - {"r9w", Reg16, RegRex, 1}, - {"r10w", Reg16, RegRex, 2}, - {"r11w", Reg16, RegRex, 3}, - {"r12w", Reg16, RegRex, 4}, - {"r13w", Reg16, RegRex, 5}, - {"r14w", Reg16, RegRex, 6}, - {"r15w", Reg16, RegRex, 7}, - /* 32 bit regs */ -#define REGNAM_EAX 41 - {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot */ - {"ecx", Reg32|BaseIndex, 0, 1}, - {"edx", Reg32|BaseIndex, 0, 2}, - {"ebx", Reg32|BaseIndex, 0, 3}, - {"esp", Reg32, 0, 4}, - {"ebp", Reg32|BaseIndex, 0, 5}, - {"esi", Reg32|BaseIndex, 0, 6}, - {"edi", Reg32|BaseIndex, 0, 7}, - {"r8d", Reg32|BaseIndex, RegRex, 0}, - {"r9d", Reg32|BaseIndex, RegRex, 1}, - {"r10d", Reg32|BaseIndex, RegRex, 2}, - {"r11d", Reg32|BaseIndex, RegRex, 3}, - {"r12d", Reg32|BaseIndex, RegRex, 4}, - {"r13d", Reg32|BaseIndex, RegRex, 5}, - {"r14d", Reg32|BaseIndex, RegRex, 6}, - {"r15d", Reg32|BaseIndex, RegRex, 7}, - {"rax", Reg64|BaseIndex|Acc, 0, 0}, - {"rcx", Reg64|BaseIndex, 0, 1}, - {"rdx", Reg64|BaseIndex, 0, 2}, - {"rbx", Reg64|BaseIndex, 0, 3}, - {"rsp", Reg64, 0, 4}, - {"rbp", Reg64|BaseIndex, 0, 5}, - {"rsi", Reg64|BaseIndex, 0, 6}, - {"rdi", Reg64|BaseIndex, 0, 7}, - {"r8", Reg64|BaseIndex, RegRex, 0}, - {"r9", Reg64|BaseIndex, RegRex, 1}, - {"r10", Reg64|BaseIndex, RegRex, 2}, - {"r11", Reg64|BaseIndex, RegRex, 3}, - {"r12", Reg64|BaseIndex, RegRex, 4}, - {"r13", Reg64|BaseIndex, RegRex, 5}, - {"r14", Reg64|BaseIndex, RegRex, 6}, - {"r15", Reg64|BaseIndex, RegRex, 7}, - /* segment registers */ - {"es", SReg2, 0, 0}, - {"cs", SReg2, 0, 1}, - {"ss", SReg2, 0, 2}, - {"ds", SReg2, 0, 3}, - {"fs", SReg3, 0, 4}, - {"gs", SReg3, 0, 5}, - /* control registers */ - {"cr0", Control, 0, 0}, - {"cr1", Control, 0, 1}, - {"cr2", Control, 0, 2}, - {"cr3", Control, 0, 3}, - {"cr4", Control, 0, 4}, - {"cr5", Control, 0, 5}, - {"cr6", Control, 0, 6}, - {"cr7", Control, 0, 7}, - {"cr8", Control, RegRex, 0}, - {"cr9", Control, RegRex, 1}, - {"cr10", Control, RegRex, 2}, - {"cr11", Control, RegRex, 3}, - {"cr12", Control, RegRex, 4}, - {"cr13", Control, RegRex, 5}, - {"cr14", Control, RegRex, 6}, - {"cr15", Control, RegRex, 7}, - /* debug registers */ - {"db0", Debug, 0, 0}, - {"db1", Debug, 0, 1}, - {"db2", Debug, 0, 2}, - {"db3", Debug, 0, 3}, - {"db4", Debug, 0, 4}, - {"db5", Debug, 0, 5}, - {"db6", Debug, 0, 6}, - {"db7", Debug, 0, 7}, - {"db8", Debug, RegRex, 0}, - {"db9", Debug, RegRex, 1}, - {"db10", Debug, RegRex, 2}, - {"db11", Debug, RegRex, 3}, - {"db12", Debug, RegRex, 4}, - {"db13", Debug, RegRex, 5}, - {"db14", Debug, RegRex, 6}, - {"db15", Debug, RegRex, 7}, - {"dr0", Debug, 0, 0}, - {"dr1", Debug, 0, 1}, - {"dr2", Debug, 0, 2}, - {"dr3", Debug, 0, 3}, - {"dr4", Debug, 0, 4}, - {"dr5", Debug, 0, 5}, - {"dr6", Debug, 0, 6}, - {"dr7", Debug, 0, 7}, - {"dr8", Debug, RegRex, 0}, - {"dr9", Debug, RegRex, 1}, - {"dr10", Debug, RegRex, 2}, - {"dr11", Debug, RegRex, 3}, - {"dr12", Debug, RegRex, 4}, - {"dr13", Debug, RegRex, 5}, - {"dr14", Debug, RegRex, 6}, - {"dr15", Debug, RegRex, 7}, - /* test registers */ - {"tr0", Test, 0, 0}, - {"tr1", Test, 0, 1}, - {"tr2", Test, 0, 2}, - {"tr3", Test, 0, 3}, - {"tr4", Test, 0, 4}, - {"tr5", Test, 0, 5}, - {"tr6", Test, 0, 6}, - {"tr7", Test, 0, 7}, - /* mmx and simd registers */ - {"mm0", RegMMX, 0, 0}, - {"mm1", RegMMX, 0, 1}, - {"mm2", RegMMX, 0, 2}, - {"mm3", RegMMX, 0, 3}, - {"mm4", RegMMX, 0, 4}, - {"mm5", RegMMX, 0, 5}, - {"mm6", RegMMX, 0, 6}, - {"mm7", RegMMX, 0, 7}, - {"xmm0", RegXMM, 0, 0}, - {"xmm1", RegXMM, 0, 1}, - {"xmm2", RegXMM, 0, 2}, - {"xmm3", RegXMM, 0, 3}, - {"xmm4", RegXMM, 0, 4}, - {"xmm5", RegXMM, 0, 5}, - {"xmm6", RegXMM, 0, 6}, - {"xmm7", RegXMM, 0, 7}, - {"xmm8", RegXMM, RegRex, 0}, - {"xmm9", RegXMM, RegRex, 1}, - {"xmm10", RegXMM, RegRex, 2}, - {"xmm11", RegXMM, RegRex, 3}, - {"xmm12", RegXMM, RegRex, 4}, - {"xmm13", RegXMM, RegRex, 5}, - {"xmm14", RegXMM, RegRex, 6}, - {"xmm15", RegXMM, RegRex, 7}, - /* no type will make this register rejected for all purposes except - for addressing. This saves creating one extra type for RIP. */ - {"rip", BaseIndex, 0, 0} -}; +/* max operands per insn */ +#define MAX_OPERANDS 4 -static const reg_entry i386_float_regtab[] = { - {"st(0)", FloatReg|FloatAcc, 0, 0}, - {"st(1)", FloatReg, 0, 1}, - {"st(2)", FloatReg, 0, 2}, - {"st(3)", FloatReg, 0, 3}, - {"st(4)", FloatReg, 0, 4}, - {"st(5)", FloatReg, 0, 5}, - {"st(6)", FloatReg, 0, 6}, - {"st(7)", FloatReg, 0, 7} -}; +/* max immediates per insn (lcall, ljmp, insertq, extrq) */ +#define MAX_IMMEDIATE_OPERANDS 2 -#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ +/* max memory refs per insn (string ops) */ +#define MAX_MEMORY_OPERANDS 2 -/* segment stuff */ -static const seg_entry cs = { "cs", 0x2e }; -static const seg_entry ds = { "ds", 0x3e }; -static const seg_entry ss = { "ss", 0x36 }; -static const seg_entry es = { "es", 0x26 }; -static const seg_entry fs = { "fs", 0x64 }; -static const seg_entry gs = { "gs", 0x65 }; +/* max size of insn mnemonics. */ +#define MAX_MNEM_SIZE 16 -/* end of opcode/i386.h */ +/* max size of register name in insn mnemonics. */ +#define MAX_REG_NAME_SIZE 8 diff --git a/contrib/binutils/include/opcode/ia64.h b/contrib/binutils/include/opcode/ia64.h index 0d33fc6..447e50e 100644 --- a/contrib/binutils/include/opcode/ia64.h +++ b/contrib/binutils/include/opcode/ia64.h @@ -1,6 +1,7 @@ /* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998, 1999, 2002 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ + Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006 + Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ #ifndef opcode_ia64_h #define opcode_ia64_h @@ -75,13 +76,15 @@ enum ia64_opnd IA64_OPND_R3, /* third register # */ IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ + /* memory operands: */ + IA64_OPND_MR3, /* memory at addr of third register # */ + /* indirect operands: */ IA64_OPND_CPUID_R3, /* cpuid[reg] */ IA64_OPND_DBR_R3, /* dbr[reg] */ IA64_OPND_DTR_R3, /* dtr[reg] */ IA64_OPND_ITR_R3, /* itr[reg] */ IA64_OPND_IBR_R3, /* ibr[reg] */ - IA64_OPND_MR3, /* memory at addr of third register # */ IA64_OPND_MSR_R3, /* msr[reg] */ IA64_OPND_PKR_R3, /* pkr[reg] */ IA64_OPND_PMC_R3, /* pmc[reg] */ @@ -100,6 +103,7 @@ enum ia64_opnd IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ + IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ IA64_OPND_SOF, /* 8-bit stack frame size */ diff --git a/contrib/binutils/include/opcode/mips.h b/contrib/binutils/include/opcode/mips.h index 1544854..2d321c8 100644 --- a/contrib/binutils/include/opcode/mips.h +++ b/contrib/binutils/include/opcode/mips.h @@ -171,6 +171,8 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US #define OP_MASK_WRDSP 0x3f #define OP_SH_RDDSP 16 #define OP_MASK_RDDSP 0x3f +#define OP_SH_BP 11 +#define OP_MASK_BP 0x3 /* MIPS MT ASE */ #define OP_SH_MT_U 5 @@ -205,6 +207,16 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US #define MDMX_FMTSEL_VEC_QH 0x15 #define MDMX_FMTSEL_VEC_OB 0x16 +/* UDI */ +#define OP_SH_UDI1 6 +#define OP_MASK_UDI1 0x1f +#define OP_SH_UDI2 6 +#define OP_MASK_UDI2 0x3ff +#define OP_SH_UDI3 6 +#define OP_MASK_UDI3 0x7fff +#define OP_SH_UDI4 6 +#define OP_MASK_UDI4 0xfffff + /* This structure holds information for a particular instruction. */ struct mips_opcode @@ -273,19 +285,20 @@ struct mips_opcode "y" 10 bit signed const (OP_*_CODE2) "z" must be zero register "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) - "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). + "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes + LSB (OP_*_SHAMT). Enforces: 0 <= pos < 32. - "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). + "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. - "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). + "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. (Also used by "dext" w/ different limits, but limits for that are checked by the M_DEXT macro.) - "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). + "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). Enforces: 32 <= pos < 64. - "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). + "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). Requires that "+A" or "+E" occur first to set position. Enforces: 32 < (pos+size) <= 64. "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). @@ -334,6 +347,7 @@ struct mips_opcode "Z" MDMX source register (OP_*_FT) DSP ASE usage: + "2" 2 bit unsigned immediate for byte align (OP_*_BP) "3" 3 bit unsigned immediate (OP_*_SA3) "4" 4 bit unsigned immediate (OP_*_SA4) "5" 8 bit unsigned immediate (OP_*_IMM8) @@ -347,14 +361,20 @@ struct mips_opcode "@" 10 bit signed immediate (OP_*_IMM10) MT ASE usage: - "!" 1 bit immediate at bit 5 - "$" 1 bit immediate at bit 4 + "!" 1 bit usermode flag (OP_*_MT_U) + "$" 1 bit load high flag (OP_*_MT_H) "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) "+t" 5 bit coprocessor 0 destination register (OP_*_RT) "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only + UDI immediates: + "+1" UDI immediate bits 6-10 + "+2" UDI immediate bits 6-15 + "+3" UDI immediate bits 6-20 + "+4" UDI immediate bits 6-25 + Other: "()" parens surrounding optional value "," separates operands @@ -362,13 +382,14 @@ struct mips_opcode "+" Start of extension sequence. Characters used so far, for quick reference when adding more: - "34567890" + "234567890" "%[]<>(),+:'@!$*&^~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklopqrstuvwxyz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: + "1234" "ABCDEFGHIT" "t" */ @@ -472,16 +493,15 @@ struct mips_opcode #define INSN_ISA64R2 0x00000100 /* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x0400f000 +#define INSN_ASE_MASK 0x3c00f000 /* DSP ASE */ #define INSN_DSP 0x00001000 +#define INSN_DSP64 0x00002000 /* MIPS 16 ASE */ -#define INSN_MIPS16 0x00002000 +#define INSN_MIPS16 0x00004000 /* MIPS-3D ASE */ -#define INSN_MIPS3D 0x00004000 -/* MDMX ASE */ -#define INSN_MDMX 0x00008000 +#define INSN_MIPS3D 0x00008000 /* Chip specific instructions. These are bitmasks. */ @@ -505,8 +525,15 @@ struct mips_opcode #define INSN_5400 0x01000000 /* NEC VR5500 instruction. */ #define INSN_5500 0x02000000 + +/* MDMX ASE */ +#define INSN_MDMX 0x04000000 /* MT ASE */ -#define INSN_MT 0x04000000 +#define INSN_MT 0x08000000 +/* SmartMIPS ASE */ +#define INSN_SMARTMIPS 0x10000000 +/* DSP R2 ASE */ +#define INSN_DSPR2 0x20000000 /* Cavium Networks Octeon instruction. */ #define INSN_OCTEON 0x08000000 @@ -595,6 +622,7 @@ enum M_ADD_I, M_ADDU_I, M_AND_I, + M_BALIGN, M_BEQ, M_BEQ_I, M_BEQL_I, @@ -633,6 +661,7 @@ enum M_BNE, M_BNE_I, M_BNEL_I, + M_CACHE_AB, M_DABS, M_DADD_I, M_DADDU_I, diff --git a/contrib/binutils/include/opcode/np1.h b/contrib/binutils/include/opcode/np1.h index c3f7e29..ebe37f5 100644 --- a/contrib/binutils/include/opcode/np1.h +++ b/contrib/binutils/include/opcode/np1.h @@ -15,7 +15,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GDB; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ struct gld_opcode { diff --git a/contrib/binutils/include/opcode/pn.h b/contrib/binutils/include/opcode/pn.h index 8c427a2..f8d474f 100644 --- a/contrib/binutils/include/opcode/pn.h +++ b/contrib/binutils/include/opcode/pn.h @@ -15,7 +15,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GDB; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ struct gld_opcode { diff --git a/contrib/binutils/include/opcode/ppc.h b/contrib/binutils/include/opcode/ppc.h index d55caa7..6771856 100644 --- a/contrib/binutils/include/opcode/ppc.h +++ b/contrib/binutils/include/opcode/ppc.h @@ -1,6 +1,6 @@ /* ppc.h -- Header file for PowerPC opcode table - Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004 - Free Software Foundation, Inc. + Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, + 2007 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -17,7 +17,7 @@ the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #ifndef PPC_H #define PPC_H @@ -134,6 +134,18 @@ extern const int powerpc_num_opcodes; /* Opcode is supported by machine check APU. */ #define PPC_OPCODE_RFMCI 0x800000 +/* Opcode is only supported by Power5 architecture. */ +#define PPC_OPCODE_POWER5 0x1000000 + +/* Opcode is supported by PowerPC e300 family. */ +#define PPC_OPCODE_E300 0x2000000 + +/* Opcode is only supported by Power6 architecture. */ +#define PPC_OPCODE_POWER6 0x4000000 + +/* Opcode is only supported by PowerPC Cell family. */ +#define PPC_OPCODE_CELL 0x8000000 + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -141,20 +153,21 @@ extern const int powerpc_num_opcodes; struct powerpc_operand { - /* The number of bits in the operand. */ - int bits; + /* A bitmask of bits in the operand. */ + unsigned int bitm; - /* How far the operand is left shifted in the instruction. */ + /* How far the operand is left shifted in the instruction. + -1 to indicate that BITM and SHIFT cannot be used to determine + where the operand goes in the insn. */ int shift; /* Insertion function. This is used by the assembler. To insert an operand value into an instruction, check this field. If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; + i |= (op & o->bitm) << o->shift; (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). + this structure, and op is the operand value). If this field is not NULL, then simply call it with the instruction and the operand value. It will return the new value @@ -170,12 +183,11 @@ struct powerpc_operand extract this operand type from an instruction, check this field. If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & PPC_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; + op = (i >> o->shift) & o->bitm; + if ((o->flags & PPC_OPERAND_SIGNED) != 0) + sign_extend (op); (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). + is the result). If this field is not NULL, then simply call it with the instruction value. It will return the value of the operand. If @@ -193,17 +205,18 @@ struct powerpc_operand the operands field of the powerpc_opcodes table. */ extern const struct powerpc_operand powerpc_operands[]; +extern const unsigned int num_powerpc_operands; /* Values defined for the flags field of a struct powerpc_operand. */ /* This operand takes signed values. */ -#define PPC_OPERAND_SIGNED (01) +#define PPC_OPERAND_SIGNED (0x1) /* This operand takes signed values, but also accepts a full positive range of values when running in 32 bit mode. That is, if bits is 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, this flag is ignored. */ -#define PPC_OPERAND_SIGNOPT (02) +#define PPC_OPERAND_SIGNOPT (0x2) /* This operand does not actually exist in the assembler input. This is used to support extended mnemonics such as mr, for which two @@ -211,14 +224,14 @@ extern const struct powerpc_operand powerpc_operands[]; insert function with any op value. The disassembler should call the extract function, ignore the return value, and check the value placed in the valid argument. */ -#define PPC_OPERAND_FAKE (04) +#define PPC_OPERAND_FAKE (0x4) /* The next operand should be wrapped in parentheses rather than separated from this one by a comma. This is used for the load and store instructions which want their operands to look like reg,displacement(reg) */ -#define PPC_OPERAND_PARENS (010) +#define PPC_OPERAND_PARENS (0x8) /* This operand may use the symbolic names for the CR fields, which are @@ -227,34 +240,34 @@ extern const struct powerpc_operand powerpc_operands[]; cr4 4 cr5 5 cr6 6 cr7 7 These may be combined arithmetically, as in cr2*4+gt. These are only supported on the PowerPC, not the POWER. */ -#define PPC_OPERAND_CR (020) +#define PPC_OPERAND_CR (0x10) /* This operand names a register. The disassembler uses this to print register names with a leading 'r'. */ -#define PPC_OPERAND_GPR (040) +#define PPC_OPERAND_GPR (0x20) /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ -#define PPC_OPERAND_GPR_0 (0100) +#define PPC_OPERAND_GPR_0 (0x40) /* This operand names a floating point register. The disassembler prints these with a leading 'f'. */ -#define PPC_OPERAND_FPR (0200) +#define PPC_OPERAND_FPR (0x80) /* This operand is a relative branch displacement. The disassembler prints these symbolically if possible. */ -#define PPC_OPERAND_RELATIVE (0400) +#define PPC_OPERAND_RELATIVE (0x100) /* This operand is an absolute branch address. The disassembler prints these symbolically if possible. */ -#define PPC_OPERAND_ABSOLUTE (01000) +#define PPC_OPERAND_ABSOLUTE (0x200) /* This operand is optional, and is zero if omitted. This is used for - the optional BF and L fields in the comparison instructions. The + example, in the optional BF field in the comparison instructions. The assembler must count the number of operands remaining on the line, and the number of operands remaining for the opcode, and decide whether this operand is present or not. The disassembler should print this operand out only if it is not zero. */ -#define PPC_OPERAND_OPTIONAL (02000) +#define PPC_OPERAND_OPTIONAL (0x400) /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand is omitted, then for the next operand use this operand value plus @@ -262,24 +275,27 @@ extern const struct powerpc_operand powerpc_operands[]; hack is needed because the Power rotate instructions can take either 4 or 5 operands. The disassembler should print this operand out regardless of the PPC_OPERAND_OPTIONAL field. */ -#define PPC_OPERAND_NEXT (04000) +#define PPC_OPERAND_NEXT (0x800) /* This operand should be regarded as a negative number for the purposes of overflow checking (i.e., the normal most negative number is disallowed and one more than the normal most positive number is allowed). This flag will only be set for a signed operand. */ -#define PPC_OPERAND_NEGATIVE (010000) +#define PPC_OPERAND_NEGATIVE (0x1000) /* This operand names a vector unit register. The disassembler prints these with a leading 'v'. */ -#define PPC_OPERAND_VR (020000) +#define PPC_OPERAND_VR (0x2000) /* This operand is for the DS field in a DS form instruction. */ -#define PPC_OPERAND_DS (040000) +#define PPC_OPERAND_DS (0x4000) /* This operand is for the DQ field in a DQ form instruction. */ -#define PPC_OPERAND_DQ (0100000) +#define PPC_OPERAND_DQ (0x8000) + +/* Valid range of operand is 0..n rather than 0..n-1. */ +#define PPC_OPERAND_PLUS1 (0x10000) /* The POWER and PowerPC assemblers use a few macros. We keep them with the operands table for simplicity. The macro table is an diff --git a/contrib/binutils/include/opcode/s390.h b/contrib/binutils/include/opcode/s390.h index f582a4e..ae039ef 100644 --- a/contrib/binutils/include/opcode/s390.h +++ b/contrib/binutils/include/opcode/s390.h @@ -1,5 +1,5 @@ /* s390.h -- Header file for S390 opcode table - Copyright 2000, 2001 Free Software Foundation, Inc. + Copyright 2000, 2001, 2003 Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). This file is part of BFD, the Binary File Descriptor library. @@ -16,8 +16,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ #ifndef S390_H #define S390_H @@ -35,7 +35,9 @@ enum s390_opcode_cpu_val S390_OPCODE_G5 = 0, S390_OPCODE_G6, S390_OPCODE_Z900, - S390_OPCODE_Z990 + S390_OPCODE_Z990, + S390_OPCODE_Z9_109, + S390_OPCODE_Z9_EC }; /* The opcode table is an array of struct s390_opcode. */ @@ -138,4 +140,8 @@ extern const struct s390_operand s390_operands[]; /* This operand is a length. */ #define S390_OPERAND_LENGTH 0x200 -#endif /* S390_H */ +/* This operand is optional. Only a single operand at the end of + the instruction may be optional. */ +#define S390_OPERAND_OPTIONAL 0x400 + + #endif /* S390_H */ diff --git a/contrib/binutils/include/opcode/score-datadep.h b/contrib/binutils/include/opcode/score-datadep.h new file mode 100644 index 0000000..8ef35ad --- /dev/null +++ b/contrib/binutils/include/opcode/score-datadep.h @@ -0,0 +1,282 @@ +/* score-datadep.h -- Score Instructions data dependency table + Copyright 2006 Free Software Foundation, Inc. + Contributed by: + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#ifndef SCORE_DATA_DEPENDENCY_H +#define SCORE_DATA_DEPENDENCY_H + +#define INSN_NAME_LEN 16 + +enum insn_type_for_dependency +{ + D_pce, + D_cond_br, + D_cond_mv, + D_cached, + D_cachei, + D_ldst, + D_ldcombine, + D_mtcr, + D_mfcr, + D_mfsr, + D_mftlb, + D_mtptlb, + D_mtrtlb, + D_stlb, + D_all_insn +}; + +struct insn_to_dependency +{ + char *insn_name; + enum insn_type_for_dependency type; +}; + +struct data_dependency +{ + enum insn_type_for_dependency pre_insn_type; + char pre_reg[6]; + enum insn_type_for_dependency cur_insn_type; + char cur_reg[6]; + int bubblenum_7; + int bubblenum_5; + int warn_or_error; /* warning - 0; error - 1 */ +}; + +static const struct insn_to_dependency insn_to_dependency_table[] = +{ + /* pce instruction. */ + {"pce", D_pce}, + /* conditional branch instruction. */ + {"bcs", D_cond_br}, + {"bcc", D_cond_br}, + {"bgtu", D_cond_br}, + {"bleu", D_cond_br}, + {"beq", D_cond_br}, + {"bne", D_cond_br}, + {"bgt", D_cond_br}, + {"ble", D_cond_br}, + {"bge", D_cond_br}, + {"blt", D_cond_br}, + {"bmi", D_cond_br}, + {"bpl", D_cond_br}, + {"bvs", D_cond_br}, + {"bvc", D_cond_br}, + {"bcsl", D_cond_br}, + {"bccl", D_cond_br}, + {"bgtul", D_cond_br}, + {"bleul", D_cond_br}, + {"beql", D_cond_br}, + {"bnel", D_cond_br}, + {"bgtl", D_cond_br}, + {"blel", D_cond_br}, + {"bgel", D_cond_br}, + {"bltl", D_cond_br}, + {"bmil", D_cond_br}, + {"bpll", D_cond_br}, + {"bvsl", D_cond_br}, + {"bvcl", D_cond_br}, + {"bcs!", D_cond_br}, + {"bcc!", D_cond_br}, + {"bgtu!", D_cond_br}, + {"bleu!", D_cond_br}, + {"beq!", D_cond_br}, + {"bne!", D_cond_br}, + {"bgt!", D_cond_br}, + {"ble!", D_cond_br}, + {"bge!", D_cond_br}, + {"blt!", D_cond_br}, + {"bmi!", D_cond_br}, + {"bpl!", D_cond_br}, + {"bvs!", D_cond_br}, + {"bvc!", D_cond_br}, + {"brcs", D_cond_br}, + {"brcc", D_cond_br}, + {"brgtu", D_cond_br}, + {"brleu", D_cond_br}, + {"breq", D_cond_br}, + {"brne", D_cond_br}, + {"brgt", D_cond_br}, + {"brle", D_cond_br}, + {"brge", D_cond_br}, + {"brlt", D_cond_br}, + {"brmi", D_cond_br}, + {"brpl", D_cond_br}, + {"brvs", D_cond_br}, + {"brvc", D_cond_br}, + {"brcsl", D_cond_br}, + {"brccl", D_cond_br}, + {"brgtul", D_cond_br}, + {"brleul", D_cond_br}, + {"breql", D_cond_br}, + {"brnel", D_cond_br}, + {"brgtl", D_cond_br}, + {"brlel", D_cond_br}, + {"brgel", D_cond_br}, + {"brltl", D_cond_br}, + {"brmil", D_cond_br}, + {"brpll", D_cond_br}, + {"brvsl", D_cond_br}, + {"brvcl", D_cond_br}, + {"brcs!", D_cond_br}, + {"brcc!", D_cond_br}, + {"brgtu!", D_cond_br}, + {"brleu!", D_cond_br}, + {"breq!", D_cond_br}, + {"brne!", D_cond_br}, + {"brgt!", D_cond_br}, + {"brle!", D_cond_br}, + {"brge!", D_cond_br}, + {"brlt!", D_cond_br}, + {"brmi!", D_cond_br}, + {"brpl!", D_cond_br}, + {"brvs!", D_cond_br}, + {"brvc!", D_cond_br}, + {"brcsl!", D_cond_br}, + {"brccl!", D_cond_br}, + {"brgtul!", D_cond_br}, + {"brleul!", D_cond_br}, + {"breql!", D_cond_br}, + {"brnel!", D_cond_br}, + {"brgtl!", D_cond_br}, + {"brlel!", D_cond_br}, + {"brgel!", D_cond_br}, + {"brltl!", D_cond_br}, + {"brmil!", D_cond_br}, + {"brpll!", D_cond_br}, + {"brvsl!", D_cond_br}, + {"brvcl!", D_cond_br}, + /* conditional move instruction. */ + {"mvcs", D_cond_mv}, + {"mvcc", D_cond_mv}, + {"mvgtu", D_cond_mv}, + {"mvleu", D_cond_mv}, + {"mveq", D_cond_mv}, + {"mvne", D_cond_mv}, + {"mvgt", D_cond_mv}, + {"mvle", D_cond_mv}, + {"mvge", D_cond_mv}, + {"mvlt", D_cond_mv}, + {"mvmi", D_cond_mv}, + {"mvpl", D_cond_mv}, + {"mvvs", D_cond_mv}, + {"mvvc", D_cond_mv}, + /* move spectial instruction. */ + {"mtcr", D_mtcr}, + {"mftlb", D_mftlb}, + {"mtptlb", D_mtptlb}, + {"mtrtlb", D_mtrtlb}, + {"stlb", D_stlb}, + {"mfcr", D_mfcr}, + {"mfsr", D_mfsr}, + /* cache instruction. */ + {"cache 8", D_cached}, + {"cache 9", D_cached}, + {"cache 10", D_cached}, + {"cache 11", D_cached}, + {"cache 12", D_cached}, + {"cache 13", D_cached}, + {"cache 14", D_cached}, + {"cache 24", D_cached}, + {"cache 26", D_cached}, + {"cache 27", D_cached}, + {"cache 29", D_cached}, + {"cache 30", D_cached}, + {"cache 31", D_cached}, + {"cache 0", D_cachei}, + {"cache 1", D_cachei}, + {"cache 2", D_cachei}, + {"cache 3", D_cachei}, + {"cache 4", D_cachei}, + {"cache 16", D_cachei}, + {"cache 17", D_cachei}, + /* load/store instruction. */ + {"lb", D_ldst}, + {"lbu", D_ldst}, + {"lbu!", D_ldst}, + {"lbup!", D_ldst}, + {"lh", D_ldst}, + {"lhu", D_ldst}, + {"lh!", D_ldst}, + {"lhp!", D_ldst}, + {"lw", D_ldst}, + {"lw!", D_ldst}, + {"lwp!", D_ldst}, + {"sb", D_ldst}, + {"sb!", D_ldst}, + {"sbp!", D_ldst}, + {"sh", D_ldst}, + {"sh!", D_ldst}, + {"shp!", D_ldst}, + {"sw", D_ldst}, + {"sw!", D_ldst}, + {"swp!", D_ldst}, + {"alw", D_ldst}, + {"asw", D_ldst}, + {"push!", D_ldst}, + {"pushhi!", D_ldst}, + {"pop!", D_ldst}, + {"pophi!", D_ldst}, + {"ldc1", D_ldst}, + {"ldc2", D_ldst}, + {"ldc3", D_ldst}, + {"stc1", D_ldst}, + {"stc2", D_ldst}, + {"stc3", D_ldst}, + {"scb", D_ldst}, + {"scw", D_ldst}, + {"sce", D_ldst}, + /* load combine instruction. */ + {"lcb", D_ldcombine}, + {"lcw", D_ldcombine}, + {"lce", D_ldcombine}, +}; + +static const struct data_dependency data_dependency_table[] = +{ + /* Condition register. */ + {D_mtcr, "cr1", D_pce, "", 2, 1, 1}, + {D_mtcr, "cr1", D_cond_br, "", 1, 0, 1}, + {D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1}, + /* Status regiser. */ + {D_mtcr, "cr0", D_all_insn, "", 5, 4, 0}, + /* CCR regiser. */ + {D_mtcr, "cr4", D_all_insn, "", 6, 5, 0}, + /* EntryHi/EntryLo register. */ + {D_mftlb, "", D_mtptlb, "", 1, 1, 1}, + {D_mftlb, "", D_mtrtlb, "", 1, 1, 1}, + {D_mftlb, "", D_stlb, "", 1, 1,1}, + {D_mftlb, "", D_mfcr, "cr11", 1, 1, 1}, + {D_mftlb, "", D_mfcr, "cr12", 1, 1, 1}, + /* Index register. */ + {D_stlb, "", D_mtptlb, "", 1, 1, 1}, + {D_stlb, "", D_mftlb, "", 1, 1, 1}, + {D_stlb, "", D_mfcr, "cr8", 2, 2, 1}, + /* Cache. */ + {D_cached, "", D_ldst, "", 1, 1, 0}, + {D_cached, "", D_ldcombine, "", 1, 1, 0}, + {D_cachei, "", D_all_insn, "", 5, 4, 0}, + /* Load combine. */ + {D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1}, +}; + +#endif diff --git a/contrib/binutils/include/opcode/score-inst.h b/contrib/binutils/include/opcode/score-inst.h new file mode 100644 index 0000000..e87794f --- /dev/null +++ b/contrib/binutils/include/opcode/score-inst.h @@ -0,0 +1,507 @@ +/* score-inst.h -- Score Instructions Table + Copyright 2006 Free Software Foundation, Inc. + Contributed by: + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef SCORE_INST_H +#define SCORE_INST_H + +#define LDST_UNALIGN_MASK 0x0000007f +#define UA_LCB 0x00000060 +#define UA_LCW 0x00000062 +#define UA_LCE 0x00000066 +#define UA_SCB 0x00000068 +#define UA_SCW 0x0000006a +#define UA_SCE 0x0000006e +#define UA_LL 0x0000000c +#define UA_SC 0x0000000e +#define LDST16_RR_MASK 0x0000000f +#define N16_LW 8 +#define N16_LH 9 +#define N16_POP 10 +#define N16_LBU 11 +#define N16_SW 12 +#define N16_SH 13 +#define N16_PUSH 14 +#define N16_SB 15 +#define LDST16_RI_MASK 0x7007 +#define N16_LWP 0x7000 +#define N16_LHP 0x7001 +#define N16_LBUP 0x7003 +#define N16_SWP 0x7004 +#define N16_SHP 0x7005 +#define N16_SBP 0x7007 +#define N16_LIU 0x5000 + +#define OPC_PSEUDOLDST_MASK 0x00000007 + +enum +{ + INSN_LW = 0, + INSN_LH = 1, + INSN_LHU = 2, + INSN_LB = 3, + INSN_SW = 4, + INSN_SH = 5, + INSN_LBU = 6, + INSN_SB = 7, +}; + +/* Sub opcdoe opcode. */ +enum +{ + INSN16_LBU = 11, + INSN16_LH = 9, + INSN16_LW = 8, + INSN16_SB = 15, + INSN16_SH = 13, + INSN16_SW = 12, +}; + +enum +{ + LDST_NOUPDATE = 0, + LDST_PRE = 1, + LDST_POST = 2, +}; + +enum score_insn_type +{ + Rd_I4, + Rd_I5, + Rd_rvalueBP_I5, + Rd_lvalueBP_I5, + Rd_Rs_I5, + x_Rs_I5, + x_I5_x, + Rd_I8, + Rd_Rs_I14, + I15, + Rd_I16, + Rd_rvalueRs_SI10, + Rd_lvalueRs_SI10, + Rd_rvalueRs_preSI12, + Rd_rvalueRs_postSI12, + Rd_lvalueRs_preSI12, + Rd_lvalueRs_postSI12, + Rd_Rs_SI14, + Rd_rvalueRs_SI15, + Rd_lvalueRs_SI15, + Rd_SI16, + PC_DISP8div2, + PC_DISP11div2, + PC_DISP19div2, + PC_DISP24div2, + Rd_Rs_Rs, + x_Rs_x, + x_Rs_Rs, + Rd_Rs_x, + Rd_x_Rs, + Rd_x_x, + Rd_Rs, + Rd_HighRs, + Rd_lvalueRs, + Rd_rvalueRs, + Rd_lvalue32Rs, + Rd_rvalue32Rs, + x_Rs, + NO_OPD, + NO16_OPD, + OP5_rvalueRs_SI15, + I5_Rs_Rs_I5_OP5, + x_rvalueRs_post4, + Rd_rvalueRs_post4, + Rd_x_I5, + Rd_lvalueRs_post4, + x_lvalueRs_post4, + Rd_LowRs, + Rd_Rs_Rs_imm, + Insn_Type_PCE, + Insn_Type_SYN, + Insn_GP, + Insn_PIC, + Insn_internal, +}; + +enum score_data_type +{ + _IMM4 = 0, + _IMM5, + _IMM8, + _IMM14, + _IMM15, + _IMM16, + _SIMM10 = 6, + _SIMM12, + _SIMM14, + _SIMM15, + _SIMM16, + _SIMM14_NEG = 11, + _IMM16_NEG, + _SIMM16_NEG, + _IMM20, + _IMM25, + _DISP8div2 = 16, + _DISP11div2, + _DISP19div2, + _DISP24div2, + _VALUE, + _VALUE_HI16, + _VALUE_LO16, + _VALUE_LDST_LO16 = 23, + _SIMM16_LA, + _IMM5_RSHIFT_1, + _IMM5_RSHIFT_2, + _SIMM16_LA_POS, + _IMM5_RANGE_8_31, + _IMM10_RSHIFT_2, + _GP_IMM15 = 30, + _GP_IMM14 = 31, + _SIMM16_pic = 42, /* Index in score_df_range. */ + _IMM16_LO16_pic = 43, + _IMM16_pic = 44, +}; + +#define REG_TMP 1 + +#define OP_REG_TYPE (1 << 6) +#define OP_IMM_TYPE (1 << 7) +#define OP_SH_REGD (OP_REG_TYPE |20) +#define OP_SH_REGS1 (OP_REG_TYPE |15) +#define OP_SH_REGS2 (OP_REG_TYPE |10) +#define OP_SH_I (OP_IMM_TYPE | 1) +#define OP_SH_RI15 (OP_IMM_TYPE | 0) +#define OP_SH_I12 (OP_IMM_TYPE | 3) +#define OP_SH_DISP24 (OP_IMM_TYPE | 1) +#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15) +#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1) +#define OP_SH_I5 (OP_IMM_TYPE |10) +#define OP_SH_I10 (OP_IMM_TYPE | 5) +#define OP_SH_COPID (OP_IMM_TYPE | 5) +#define OP_SH_TRAPI5 (OP_IMM_TYPE |15) +#define OP_SH_I15 (OP_IMM_TYPE |10) + +#define OP16_SH_REGD (OP_REG_TYPE | 8) +#define OP16_SH_REGS1 (OP_REG_TYPE | 4) +#define OP16_SH_I45 (OP_IMM_TYPE | 3) +#define OP16_SH_I8 (OP_IMM_TYPE | 0) +#define OP16_SH_DISP8 (OP_IMM_TYPE | 0) +#define OP16_SH_DISP11 (OP_IMM_TYPE | 1) + +struct datafield_range +{ + int data_type; + int bits; + int range[2]; +}; + +struct datafield_range score_df_range[] = +{ + {_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */ + {_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */ + {_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */ + {_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */ + {_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */ + {_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */ + {_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */ + {_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */ + {_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */ + {_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */ + {_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ + {_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */ + {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */ + {_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ + {_IMM20, 20, {0, (1 << 20) - 1}}, + {_IMM25, 25, {0, (1 << 25) - 1}}, + {_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */ + {_DISP11div2, 11, {0, 0}}, + {_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */ + {_DISP24div2, 24, {0, 0}}, + {_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}}, + {_VALUE_HI16, 16, {0, (1 << 16) - 1}}, + {_VALUE_LO16, 16, {0, (1 << 16) - 1}}, + {_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}}, + {_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ + {_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */ + {_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */ + {_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */ + {_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */ + {_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */ + {_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */ + {_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */ + {_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */ + {_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */ + {_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */ + {_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */ + {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ + {_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ + {_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */ + {_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */ + {_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */ + {_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */ + {_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ + {_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ + {_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */ +}; + +struct shift_bitmask +{ + int opd_type; + int opd_num; + struct datafield_range *df_range; + int sh[4]; + long fieldbits[4]; +}; + +struct shift_bitmask score_sh_bits_map[] = +{ + { + Rd_I4, 2, &score_df_range[_IMM4], + {OP16_SH_REGD, OP16_SH_I45, 0, 0}, + {0xf, 0xf, 0, 0}, + }, + { + Rd_I5, 2, &score_df_range[_IMM5], + {OP16_SH_REGD, OP16_SH_I45, 0, 0}, + {0xf, 0x1f, 0, 0}, + }, + { + Rd_rvalueBP_I5, 2, &score_df_range[_IMM5], + {OP16_SH_REGD, OP16_SH_I45, 0, 0}, + {0xf, 0x1f, 0, 0}, + }, + { + Rd_lvalueBP_I5, 2, &score_df_range[_IMM5], + {OP16_SH_REGD, OP16_SH_I45, 0, 0}, + {0xf, 0x1f, 0, 0}, + }, + { + Rd_Rs_I5, 3, &score_df_range[_IMM5], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0}, + {0x1f, 0x1f, 0x1f, 0}, + }, + { + x_Rs_I5, 2, &score_df_range[_IMM5], + {OP_SH_REGS1, OP_SH_I5, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + x_I5_x, 1, &score_df_range[_IMM5], + {OP_SH_TRAPI5, 0, 0, 0}, + {0x1f, 0, 0, 0}, + }, + { + Rd_I8, 2, &score_df_range[_IMM8], + {OP16_SH_REGD, OP16_SH_I8, 0, 0}, + {0xf, 0xff, 0, 0}, + }, + { + Rd_Rs_I14, 3, &score_df_range[_IMM14], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0}, + {0x1f, 0x1f, 0x3fff, 0}, + }, + { + I15, 1, &score_df_range[_IMM15], + {OP_SH_I15, 0, 0, 0}, + {0x7fff, 0, 0, 0}, + }, + { + Rd_I16, 2, &score_df_range[_IMM16], + {OP_SH_REGD, OP_SH_I, 0, 0}, + {0x1f, 0xffff, 0, 0}, + }, + { + Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0}, + {0x1f, 0x1f, 0x3ff, 0}, + }, + { + Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0}, + {0x1f, 0x1f, 0x3ff, 0}, + }, + { + Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, + {0xf, 0xf, 0xfff, 0}, + }, + { + Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, + {0xf, 0xf, 0xfff, 0}, + }, + { + Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, + {0xf, 0xf, 0xfff, 0}, + }, + { + Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, + {0xf, 0xf, 0xfff, 0}, + }, + { + Rd_Rs_SI14, 3, &score_df_range[_SIMM14], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0}, + {0x1f, 0x1f, 0x3fff, 0}, + }, + { + Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0}, + {0x1f, 0x1f, 0x7fff, 0}, + }, + { + Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0}, + {0x1f, 0x1f, 0x7fff, 0}, + }, + { + Rd_SI16, 2, &score_df_range[_SIMM16], + {OP_SH_REGD, OP_SH_I, 0, 0}, + {0x1f, 0xffff, 0, 0}, + }, + { + PC_DISP8div2, 1, &score_df_range[_DISP8div2], + {OP16_SH_DISP8, 0, 0, 0}, + {0xff, 0, 0, 0}, + }, + { + PC_DISP11div2, 1, &score_df_range[_DISP11div2], + {OP16_SH_DISP11, 0, 0, 0}, + {0x7ff, 0, 0, 0}, + }, + { + PC_DISP19div2, 2, &score_df_range[_DISP19div2], + {OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0}, + {0x3ff, 0x1ff, 0, 0}, + }, + { + PC_DISP24div2, 1, &score_df_range[_DISP24div2], + {OP_SH_DISP24, 0, 0, 0}, + {0xffffff, 0, 0, 0}, + }, + { + Rd_Rs_Rs, 3, NULL, + {OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0}, + {0x1f, 0x1f, 0x1f, 0} + }, + { + Rd_Rs_x, 2, NULL, + {OP_SH_REGD, OP_SH_REGS1, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + Rd_x_Rs, 2, NULL, + {OP_SH_REGD, OP_SH_REGS2, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + Rd_x_x, 1, NULL, + {OP_SH_REGD, 0, 0, 0}, + {0x1f, 0, 0, 0}, + }, + { + x_Rs_Rs, 2, NULL, + {OP_SH_REGS1, OP_SH_REGS2, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + x_Rs_x, 1, NULL, + {OP_SH_REGS1, 0, 0, 0}, + {0x1f, 0, 0, 0}, + }, + { + Rd_Rs, 2, NULL, + {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, + {0xf, 0xf, 0, 0}, + }, + { + Rd_HighRs, 2, NULL, + {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, + {0xf, 0xf, 0x1f, 0}, + }, + { + Rd_rvalueRs, 2, NULL, + {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, + {0xf, 0xf, 0, 0}, + }, + { + Rd_lvalueRs, 2, NULL, + {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, + {0xf, 0xf, 0, 0} + }, + { + Rd_lvalue32Rs, 2, NULL, + {OP_SH_REGD, OP_SH_REGS1, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + Rd_rvalue32Rs, 2, NULL, + {OP_SH_REGD, OP_SH_REGS1, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + x_Rs, 1, NULL, + {OP16_SH_REGS1, 0, 0, 0}, + {0xf, 0, 0, 0}, + }, + { + NO_OPD, 0, NULL, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + }, + { + NO16_OPD, 0, NULL, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + }, +}; + +struct asm_opcode +{ + /* Instruction name. */ + const char *template; + + /* Instruction Opcode. */ + unsigned long value; + + /* Instruction bit mask. */ + unsigned long bitmask; + + /* Relax instruction opcode. 0x8000 imply no relaxation. */ + unsigned long relax_value; + + /* Instruction type. */ + enum score_insn_type type; + + /* Function to call to parse args. */ + void (*parms) (char *); +}; + +enum insn_class +{ + INSN_CLASS_16, + INSN_CLASS_32, + INSN_CLASS_PCE, + INSN_CLASS_SYN +}; + +#endif diff --git a/contrib/binutils/include/opcode/sparc.h b/contrib/binutils/include/opcode/sparc.h index c336493..9e238be 100644 --- a/contrib/binutils/include/opcode/sparc.h +++ b/contrib/binutils/include/opcode/sparc.h @@ -1,24 +1,24 @@ /* Definitions for opcode table for the sparc. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, - 2003 Free Software Foundation, Inc. + 2003, 2005 Free Software Foundation, Inc. -This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and -the GNU Binutils. + This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and + the GNU Binutils. -GAS/GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GAS/GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. -GAS/GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GAS/GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with GAS or GDB; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GAS or GDB; see the file COPYING. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ #include "ansidecl.h" @@ -37,17 +37,18 @@ Boston, MA 02111-1307, USA. */ The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. Don't change this without updating sparc-opc.c. */ -enum sparc_opcode_arch_val { +enum sparc_opcode_arch_val +{ SPARC_OPCODE_ARCH_V6 = 0, SPARC_OPCODE_ARCH_V7, SPARC_OPCODE_ARCH_V8, SPARC_OPCODE_ARCH_SPARCLET, SPARC_OPCODE_ARCH_SPARCLITE, - /* v9 variants must appear last */ + /* V9 variants must appear last. */ SPARC_OPCODE_ARCH_V9, - SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */ - SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */ - SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ + SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ + SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ + SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ }; /* The highest architecture in the table. */ @@ -62,14 +63,15 @@ enum sparc_opcode_arch_val { /* Table of cpu variants. */ -struct sparc_opcode_arch { +typedef struct sparc_opcode_arch +{ const char *name; /* Mask of sparc_opcode_arch_val's supported. EG: For v7 this would be (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). These are short's because sparc_opcode.architecture is. */ short supported; -}; +} sparc_opcode_arch; extern const struct sparc_opcode_arch sparc_opcode_archs[]; @@ -82,44 +84,43 @@ extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); /* Non-zero if ARCH1 conflicts with ARCH2. IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ -(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ - != SPARC_OPCODE_SUPPORTED (ARCH1)) \ - && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ + (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ + != SPARC_OPCODE_SUPPORTED (ARCH1)) \ + && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ != SPARC_OPCODE_SUPPORTED (ARCH2))) /* Structure of an opcode table entry. */ -struct sparc_opcode { +typedef struct sparc_opcode +{ const char *name; - unsigned long match; /* Bits that must be set. */ - unsigned long lose; /* Bits that must not be set. */ + unsigned long match; /* Bits that must be set. */ + unsigned long lose; /* Bits that must not be set. */ const char *args; - /* This was called "delayed" in versions before the flags. */ + /* This was called "delayed" in versions before the flags. */ char flags; short architecture; /* Bitmask of sparc_opcode_arch_val's. */ -}; - -#define F_DELAYED 1 /* Delayed branch */ -#define F_ALIAS 2 /* Alias for a "real" instruction */ -#define F_UNBR 4 /* Unconditional branch */ -#define F_CONDBR 8 /* Conditional branch */ -#define F_JSR 16 /* Subroutine call */ -#define F_FLOAT 32 /* Floating point instruction (not a branch) */ -#define F_FBR 64 /* Floating point branch */ +} sparc_opcode; + +#define F_DELAYED 1 /* Delayed branch. */ +#define F_ALIAS 2 /* Alias for a "real" instruction. */ +#define F_UNBR 4 /* Unconditional branch. */ +#define F_CONDBR 8 /* Conditional branch. */ +#define F_JSR 16 /* Subroutine call. */ +#define F_FLOAT 32 /* Floating point instruction (not a branch). */ +#define F_FBR 64 /* Floating point branch. */ /* FIXME: Add F_ANACHRONISTIC flag for v9. */ -/* - -All sparc opcodes are 32 bits, except for the `set' instruction (really a -macro), which is 64 bits. It is handled as a special case. +/* All sparc opcodes are 32 bits, except for the `set' instruction (really a + macro), which is 64 bits. It is handled as a special case. -The match component is a mask saying which bits must match a particular -opcode in order for an instruction to be an instance of that opcode. + The match component is a mask saying which bits must match a particular + opcode in order for an instruction to be an instance of that opcode. -The args component is a string containing one character for each operand of the -instruction. + The args component is a string containing one character for each operand of the + instruction. -Kinds of operands: + Kinds of operands: # Number used by optimizer. It is ignored. 1 rs1 register. 2 rs2 register. @@ -187,37 +188,35 @@ Kinds of operands: _ Ancillary state register in rd (v9a) / Ancillary state register in rs1 (v9a) -The following chars are unused: (note: ,[] are used as punctuation) -[45] - -*/ - -#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ -#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ -#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ -#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ -#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ -#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ -#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ -#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ -#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ -#define F1(x) (OP(x)) -#define DISP30(x) ((x)&0x3fffffff) -#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ -#define RS2(x) ((x)&0x1f) /* rs2 field */ -#define SIMM13(x) ((x)&0x1fff) /* simm13 field */ -#define RD(x) (((x)&0x1f) << 25) /* destination register field */ -#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ -#define ASI_RS2(x) (SIMM13(x)) -#define MEMBAR(x) ((x)&0x7f) -#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ - -#define ANNUL (1<<29) -#define BPRED (1<<19) /* v9 */ -#define IMMED F3I(1) -#define RD_G0 RD(~0) -#define RS1_G0 RS1(~0) -#define RS2_G0 RS2(~0) + The following chars are unused: (note: ,[] are used as punctuation) + [45]. */ + +#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ +#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ +#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ +#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ +#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ +#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ +#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ +#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ +#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ +#define F1(x) (OP (x)) +#define DISP30(x) ((x) & 0x3fffffff) +#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ +#define RS2(x) ((x) & 0x1f) /* Rs2 field. */ +#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ +#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ +#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ +#define ASI_RS2(x) (SIMM13 (x)) +#define MEMBAR(x) ((x) & 0x7f) +#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ + +#define ANNUL (1 << 29) +#define BPRED (1 << 19) /* V9. */ +#define IMMED F3I (1) +#define RD_G0 RD (~0) +#define RS1_G0 RS1 (~0) +#define RS2_G0 RS2 (~0) extern const struct sparc_opcode sparc_opcodes[]; extern const int sparc_num_opcodes; @@ -231,11 +230,8 @@ extern const char *sparc_decode_prefetch (int); extern int sparc_encode_sparclet_cpreg (const char *); extern const char *sparc_decode_sparclet_cpreg (int); -/* - * Local Variables: - * fill-column: 131 - * comment-column: 0 - * End: - */ +/* Local Variables: + fill-column: 131 + comment-column: 0 + End: */ -/* end of sparc.h */ diff --git a/contrib/binutils/include/opcode/spu-insns.h b/contrib/binutils/include/opcode/spu-insns.h new file mode 100644 index 0000000..237d8ab --- /dev/null +++ b/contrib/binutils/include/opcode/spu-insns.h @@ -0,0 +1,417 @@ +/* SPU ELF support for BFD. + + Copyright 2006, 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* SPU Opcode Table + +-=-=-= FORMAT =-=-=- + + +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ +RRR | op | RC | RB | RA | RT | RI7 | op | I7 | RA | RT | + +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ + 0 3 1 1 2 3 0 1 1 2 3 + 0 7 4 1 0 7 4 1 + + +-----------+--------+-------+-------+ +---------+----------+-------+-------+ +RI8 | op | I8 | RA | RT | RI10 | op | I10 | RA | RT | + +-----------+--------+-------+-------+ +---------+----------+-------+-------+ + 0 9 1 2 3 0 7 1 2 3 + 7 4 1 7 4 1 + + +----------+-----------------+-------+ +--------+-------------------+-------+ +RI16 | op | I16 | RT | RI18 | op | I18 | RT | + +----------+-----------------+-------+ +--------+-------------------+-------+ + 0 8 2 3 0 6 2 3 + 4 1 4 1 + + +------------+-------+-------+-------+ +-------+--+-----------------+-------+ +RR | op | RB | RA | RT | LBT | op |RO| I16 | RO | + +------------+-------+-------+-------+ +-------+--+-----------------+-------+ + 0 1 1 2 3 0 6 8 2 3 + 0 7 4 1 4 1 + + +------------+----+--+-------+-------+ + LBTI | op | // |RO| RA | RO | + +------------+----+--+-------+-------+ + 0 1 1 1 2 3 + 0 5 7 4 1 + +-=-=-= OPCODE =-=-=- + +OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this +case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700, +since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000. + +-=-=-= ASM_FORMAT =-=-=- + +RRR category RI7 category + ASM_RRR mnemonic RC, RA, RB, RT ASM_RI4 mnemonic RT, RA, I4 + ASM_RI7 mnemonic RT, RA, I7 + +RI8 category RI10 category + ASM_RUI8 mnemonic RT, RA, UI8 ASM_AI10 mnemonic RA, I10 + ASM_RI10 mnemonic RT, RA, R10 + ASM_RI10IDX mnemonic RT, I10(RA) + +RI16 category RI18 category + ASM_I16W mnemonic I16W ASM_RI18 mnemonic RT, I18 + ASM_RI16 mnemonic RT, I16 + ASM_RI16W mnemonic RT, I16W + +RR category LBT category + ASM_MFSPR mnemonic RT, SA ASM_LBT mnemonic brinst, brtarg + ASM_MTSPR mnemonic SA, RT + ASM_NOOP mnemonic LBTI category + ASM_RA mnemonic RA ASM_LBTI mnemonic brinst, RA + ASM_RAB mnemonic RA, RB + ASM_RDCH mnemonic RT, CA + ASM_RR mnemonic RT, RA, RB + ASM_RT mnemonic RT + ASM_RTA mnemonic RT, RA + ASM_WRCH mnemonic CA, RT + +Note that RRR instructions have the names for RC and RT reversed from +what's in the ISA, in order to put RT in the same position it appears +for other formats. + +-=-=-= DEPENDENCY =-=-=- + +DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target. +The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits. +If the digit is 0, this means the corresponding register is not used in the instruction. +If the digit is 1, this means the corresponding register is used as a source in the instruction. +If the digit is 2, this means the corresponding register is used as a target in the instruction. +If the digit is 3, this means the corresponding register is used as both source and target in the instruction. +For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are +used as sources and RT is the target. + +-=-=-= PIPE =-=-=- + +This field shows which execution pipe is used for the instruction + +pipe0 execution pipelines: + FP6 SP floating pipeline + FP7 integer operations executed in SP floating pipeline + FPD DP floating pipeline + FX2 FXU pipeline + FX3 Rotate/Shift pipeline + FXB Byte pipeline + NOP No pipeline + +pipe1 execution pipelines: + BR Branch pipeline + LNOP No pipeline + LS Load/Store pipeline + SHUF Shuffle pipeline + SPR SPR/CH pipeline + +*/ + +#define _A0() {0} +#define _A1(a) {1,a} +#define _A2(a,b) {2,a,b} +#define _A3(a,b,c) {3,a,b,c} +#define _A4(a,b,c,d) {4,a,b,c,d} + +/* TAG FORMAT OPCODE MNEMONIC ASM_FORMAT DEPENDENCY PIPE COMMENT */ +/* 0[RC][RB][RA][RT] */ +/* 1:src, 2:target */ + +APUOP(M_BR, RI16, 0x190, "br", _A1(A_R18), 00000, BR) /* BRel IP<-IP+I16 */ +APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */ +APUOP(M_BRA, RI16, 0x180, "bra", _A1(A_S18), 00000, BR) /* BRAbs IP<-I16 */ +APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */ +APUOP(M_FSMBI, RI16, 0x194, "fsmbi", _A2(A_T,A_X16), 00002, SHUF) /* FormSelMask%I RT<-fsm(I16) */ +APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */ +APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */ +APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */ +APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */ +APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */ +APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */ +APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */ +APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */ +APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ +APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ +APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ +APUOP(M_HBRA, LBT, 0x080, "hbra", _A2(A_S11,A_S18), 00000, LS) /* HBRA BTB[B9]<-M[I16] */ +APUOP(M_HBRR, LBT, 0x090, "hbrr", _A2(A_S11,A_R18), 00000, LS) /* HBRR BTB[B9]<-M[IP+I16] */ +APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */ +APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */ +APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */ +APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */ +APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */ +APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */ +APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ +APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ +APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10] */ +APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */ +APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ +APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ +APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */ +APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ +APUOP(M_HBR, LBTI, 0x1ac, "hbr", _A2(A_S11I,A_A), 00010, LS) /* HBR BTB[B9]<-M[Ra] */ +APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */ +APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */ +APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ +APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ +APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ +APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ +APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ +APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ +APUOP(M_CBD, RI7, 0x1f4, "cbd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_CHD, RI7, 0x1f5, "chd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_CWD, RI7, 0x1f6, "cwd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_CDD, RI7, 0x1f7, "cdd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_ROTQBII, RI7, 0x1f8, "rotqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* ROTQBII RT<-RA<<<I7 */ +APUOP(M_ROTQBYI, RI7, 0x1fc, "rotqbyi", _A3(A_T,A_A,A_S7N), 00012, SHUF) /* ROTQBYI RT<-RA<<<(I7*8) */ +APUOP(M_ROTQMBII, RI7, 0x1f9, "rotqmbii", _A3(A_T,A_A,A_S3), 00012, SHUF) /* ROTQMBII RT<-RA<<I7 */ +APUOP(M_ROTQMBYI, RI7, 0x1fd, "rotqmbyi", _A3(A_T,A_A,A_S6), 00012, SHUF) /* ROTQMBYI RT<-RA<<I7 */ +APUOP(M_SHLQBII, RI7, 0x1fb, "shlqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* SHLQBII RT<-RA<<I7 */ +APUOP(M_SHLQBYI, RI7, 0x1ff, "shlqbyi", _A3(A_T,A_A,A_U5), 00012, SHUF) /* SHLQBYI RT<-RA<<I7 */ +APUOP(M_STQD, RI10, 0x120, "stqd", _A4(A_T,A_S14,A_P,A_A), 00011, LS) /* SToreQDisp M[Ra+I10]<-RT */ +APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ +APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ +APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOP(M_CBX, RR, 0x1d4, "cbx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ +APUOP(M_CHX, RR, 0x1d5, "chx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ +APUOP(M_CWX, RR, 0x1d6, "cwx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ +APUOP(M_CDX, RR, 0x1d7, "cdx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ +APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */ +APUOP(M_ROTQBI, RR, 0x1d8, "rotqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBI RT<-RA<<<Rb */ +APUOP(M_ROTQMBI, RR, 0x1d9, "rotqmbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBI RT<-RA<<Rb */ +APUOP(M_SHLQBI, RR, 0x1db, "shlqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBI RT<-RA<<Rb */ +APUOP(M_ROTQBY, RR, 0x1dc, "rotqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBY RT<-RA<<<(Rb*8) */ +APUOP(M_ROTQMBY, RR, 0x1dd, "rotqmby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBY RT<-RA<<Rb */ +APUOP(M_SHLQBY, RR, 0x1df, "shlqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBY RT<-RA<<Rb */ +APUOP(M_ROTQBYBI, RR, 0x1cc, "rotqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBYBI RT<-RA<<Rb */ +APUOP(M_ROTQMBYBI, RR, 0x1cd, "rotqmbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBYBI RT<-RA<<Rb */ +APUOP(M_SHLQBYBI, RR, 0x1cf, "shlqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBYBI RT<-RA<<Rb */ +APUOP(M_STQX, RR, 0x144, "stqx", _A3(A_T,A_A,A_B), 00111, LS) /* SToreQindeX M[Ra+Rb]<-RT */ +APUOP(M_SHUFB, RRR, 0x580, "shufb", _A4(A_C,A_A,A_B,A_T), 02111, SHUF) /* SHUFfleBytes RC<-f(RA,RB,RT) */ +APUOP(M_IL, RI16, 0x204, "il", _A2(A_T,A_S16), 00002, FX2) /* ImmLoad RT<-sxt(I16) */ +APUOP(M_ILH, RI16, 0x20c, "ilh", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadH RT<-I16 */ +APUOP(M_ILHU, RI16, 0x208, "ilhu", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadHUpper RT<-I16<<16 */ +APUOP(M_ILA, RI18, 0x210, "ila", _A2(A_T,A_U18), 00002, FX2) /* ImmLoadAddr RT<-zxt(I18) */ +APUOP(M_NOP, RR, 0x201, "nop", _A1(A_T), 00000, NOP) /* XNOP no_operation */ +APUOP(M_NOP2, RR, 0x201, "nop", _A0(), 00000, NOP) /* XNOP no_operation */ +APUOP(M_IOHL, RI16, 0x304, "iohl", _A2(A_T,A_X16), 00003, FX2) /* AddImmeXt RT<-RT+sxt(I16) */ +APUOP(M_ANDBI, RI10, 0x0b0, "andbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* AND%I RT<-RA&I10 */ +APUOP(M_ANDHI, RI10, 0x0a8, "andhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */ +APUOP(M_ANDI, RI10, 0x0a0, "andi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */ +APUOP(M_ORBI, RI10, 0x030, "orbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* OR%I RT<-RA|I10 */ +APUOP(M_ORHI, RI10, 0x028, "orhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */ +APUOP(M_ORI, RI10, 0x020, "ori", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */ +APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */ +APUOP(M_XORBI, RI10, 0x230, "xorbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* XOR%I RT<-RA^I10 */ +APUOP(M_XORHI, RI10, 0x228, "xorhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */ +APUOP(M_XORI, RI10, 0x220, "xori", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */ +APUOP(M_AHI, RI10, 0x0e8, "ahi", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */ +APUOP(M_AI, RI10, 0x0e0, "ai", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */ +APUOP(M_SFHI, RI10, 0x068, "sfhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */ +APUOP(M_SFI, RI10, 0x060, "sfi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */ +APUOP(M_CGTBI, RI10, 0x270, "cgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CGT%I RT<-(RA>I10) */ +APUOP(M_CGTHI, RI10, 0x268, "cgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ +APUOP(M_CGTI, RI10, 0x260, "cgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ +APUOP(M_CLGTBI, RI10, 0x2f0, "clgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ +APUOP(M_CLGTHI, RI10, 0x2e8, "clgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ +APUOP(M_CLGTI, RI10, 0x2e0, "clgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ +APUOP(M_CEQBI, RI10, 0x3f0, "ceqbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ +APUOP(M_CEQHI, RI10, 0x3e8, "ceqhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ +APUOP(M_CEQI, RI10, 0x3e0, "ceqi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ +APUOP(M_HGTI, RI10, 0x278, "hgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ +APUOP(M_HGTI2, RI10, 0x278, "hgti", _A2(A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ +APUOP(M_HLGTI, RI10, 0x2f8, "hlgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ +APUOP(M_HLGTI2, RI10, 0x2f8, "hlgti", _A2(A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ +APUOP(M_HEQI, RI10, 0x3f8, "heqi", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ +APUOP(M_HEQI2, RI10, 0x3f8, "heqi", _A2(A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ +APUOP(M_MPYI, RI10, 0x3a0, "mpyi", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYI RT<-RA*I10 */ +APUOP(M_MPYUI, RI10, 0x3a8, "mpyui", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYUI RT<-RA*I10 */ +APUOP(M_CFLTS, RI8, 0x3b0, "cflts", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTS RT<-int(RA,I8) */ +APUOP(M_CFLTU, RI8, 0x3b2, "cfltu", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTU RT<-int(RA,I8) */ +APUOP(M_CSFLT, RI8, 0x3b4, "csflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CSFLT RT<-flt(RA,I8) */ +APUOP(M_CUFLT, RI8, 0x3b6, "cuflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CUFLT RT<-flt(RA,I8) */ +APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */ +APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */ +APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */ +APUOP(M_FSCRWR, RR, 0x3ba, "fscrwr", _A2(A_T,A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ +APUOP(M_FSCRWR2, RR, 0x3ba, "fscrwr", _A1(A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ +APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */ +APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */ +APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */ +APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */ +APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */ +APUOP(M_ROTI, RI7, 0x078, "roti", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */ +APUOP(M_ROTMI, RI7, 0x079, "rotmi", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROT%MI RT<-RA<<I7 */ +APUOP(M_ROTMAI, RI7, 0x07a, "rotmai", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */ +APUOP(M_SHLI, RI7, 0x07b, "shli", _A3(A_T,A_A,A_U6), 00012, FX3) /* SHL%I RT<-RA<<I7 */ +APUOP(M_ROTHI, RI7, 0x07c, "rothi", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */ +APUOP(M_ROTHMI, RI7, 0x07d, "rothmi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROT%MI RT<-RA<<I7 */ +APUOP(M_ROTMAHI, RI7, 0x07e, "rotmahi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */ +APUOP(M_SHLHI, RI7, 0x07f, "shlhi", _A3(A_T,A_A,A_U5), 00012, FX3) /* SHL%I RT<-RA<<I7 */ +APUOP(M_A, RR, 0x0c0, "a", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ +APUOP(M_AH, RR, 0x0c8, "ah", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ +APUOP(M_SF, RR, 0x040, "sf", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ +APUOP(M_SFH, RR, 0x048, "sfh", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ +APUOP(M_CGT, RR, 0x240, "cgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ +APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ +APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ +APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ +APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ +APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ +APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ +APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ +APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ +APUOP(M_HGT, RR, 0x258, "hgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ +APUOP(M_HGT2, RR, 0x258, "hgt", _A2(A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ +APUOP(M_HLGT, RR, 0x2d8, "hlgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ +APUOP(M_HLGT2, RR, 0x2d8, "hlgt", _A2(A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ +APUOP(M_HEQ, RR, 0x3d8, "heq", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ +APUOP(M_HEQ2, RR, 0x3d8, "heq", _A2(A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ +APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */ +APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */ +APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA<RB) */ +APUOP(M_FCMGT, RR, 0x2ca, "fcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMGT RT<-(|RA|<|RB|) */ +APUOP(M_AND, RR, 0x0c1, "and", _A3(A_T,A_A,A_B), 00112, FX2) /* AND RT<-RA&RB */ +APUOP(M_NAND, RR, 0x0c9, "nand", _A3(A_T,A_A,A_B), 00112, FX2) /* NAND RT<-!(RA&RB) */ +APUOP(M_OR, RR, 0x041, "or", _A3(A_T,A_A,A_B), 00112, FX2) /* OR RT<-RA|RB */ +APUOP(M_NOR, RR, 0x049, "nor", _A3(A_T,A_A,A_B), 00112, FX2) /* NOR RT<-!(RA&RB) */ +APUOP(M_XOR, RR, 0x241, "xor", _A3(A_T,A_A,A_B), 00112, FX2) /* XOR RT<-RA^RB */ +APUOP(M_EQV, RR, 0x249, "eqv", _A3(A_T,A_A,A_B), 00112, FX2) /* EQuiValent RT<-!(RA^RB) */ +APUOP(M_ANDC, RR, 0x2c1, "andc", _A3(A_T,A_A,A_B), 00112, FX2) /* ANDComplement RT<-RA&!RB */ +APUOP(M_ORC, RR, 0x2c9, "orc", _A3(A_T,A_A,A_B), 00112, FX2) /* ORComplement RT<-RA|!RB */ +APUOP(M_ABSDB, RR, 0x053, "absdb", _A3(A_T,A_A,A_B), 00112, FXB) /* ABSoluteDiff RT<-|RA-RB| */ +APUOP(M_AVGB, RR, 0x0d3, "avgb", _A3(A_T,A_A,A_B), 00112, FXB) /* AVG% RT<-(RA+RB+1)/2 */ +APUOP(M_SUMB, RR, 0x253, "sumb", _A3(A_T,A_A,A_B), 00112, FXB) /* SUM% RT<-f(RA,RB) */ +APUOP(M_DFA, RR, 0x2cc, "dfa", _A3(A_T,A_A,A_B), 00112, FPD) /* DFAdd RT<-RA+RB */ +APUOP(M_DFM, RR, 0x2ce, "dfm", _A3(A_T,A_A,A_B), 00112, FPD) /* DFMul RT<-RA*RB */ +APUOP(M_DFS, RR, 0x2cd, "dfs", _A3(A_T,A_A,A_B), 00112, FPD) /* DFSub RT<-RA-RB */ +APUOP(M_FA, RR, 0x2c4, "fa", _A3(A_T,A_A,A_B), 00112, FP6) /* FAdd RT<-RA+RB */ +APUOP(M_FM, RR, 0x2c6, "fm", _A3(A_T,A_A,A_B), 00112, FP6) /* FMul RT<-RA*RB */ +APUOP(M_FS, RR, 0x2c5, "fs", _A3(A_T,A_A,A_B), 00112, FP6) /* FSub RT<-RA-RB */ +APUOP(M_MPY, RR, 0x3c4, "mpy", _A3(A_T,A_A,A_B), 00112, FP7) /* MPY RT<-RA*RB */ +APUOP(M_MPYH, RR, 0x3c5, "mpyh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYH RT<-(RAh*RB)<<16 */ +APUOP(M_MPYHH, RR, 0x3c6, "mpyhh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHH RT<-RAh*RBh */ +APUOP(M_MPYHHU, RR, 0x3ce, "mpyhhu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHHU RT<-RAh*RBh */ +APUOP(M_MPYS, RR, 0x3c7, "mpys", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYS RT<-(RA*RB)>>16 */ +APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */ +APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */ +APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ +APUOP(M_ROTM, RR, 0x059, "rotm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ +APUOP(M_ROTMA, RR, 0x05a, "rotma", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ +APUOP(M_SHL, RR, 0x05b, "shl", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ +APUOP(M_ROTH, RR, 0x05c, "roth", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ +APUOP(M_ROTHM, RR, 0x05d, "rothm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ +APUOP(M_ROTMAH, RR, 0x05e, "rotmah", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ +APUOP(M_SHLH, RR, 0x05f, "shlh", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ +APUOP(M_MPYHHA, RR, 0x346, "mpyhha", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHA RT<-RAh*RBh+RT */ +APUOP(M_MPYHHAU, RR, 0x34e, "mpyhhau", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHAU RT<-RAh*RBh+RT */ +APUOP(M_DFMA, RR, 0x35c, "dfma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMAdd RT<-RT+RA*RB */ +APUOP(M_DFMS, RR, 0x35d, "dfms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMSub RT<-RA*RB-RT */ +APUOP(M_DFNMS, RR, 0x35e, "dfnms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMSub RT<-RT-RA*RB */ +APUOP(M_DFNMA, RR, 0x35f, "dfnma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMAdd RT<-(-RT)-RA*RB */ +APUOP(M_FMA, RRR, 0x700, "fma", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMAdd RC<-RT+RA*RB */ +APUOP(M_FMS, RRR, 0x780, "fms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMSub RC<-RA*RB-RT */ +APUOP(M_FNMS, RRR, 0x680, "fnms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FNMSub RC<-RT-RA*RB */ +APUOP(M_MPYA, RRR, 0x600, "mpya", _A4(A_C,A_A,A_B,A_T), 02111, FP7) /* MPYA RC<-RA*RB+RT */ +APUOP(M_SELB, RRR, 0x400, "selb", _A4(A_C,A_A,A_B,A_T), 02111, FX2) /* SELectBits RC<-RA&RT|RB&!RT */ +/* for system function call, this uses op-code of mtspr */ +APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */ +/* +pseudo instruction: +system call +value of I9 operation +0 halt +1 rt[0] = open(MEM[ra[0]], ra[1]) +2 rt[0] = close(ra[0]) +3 rt[0] = read(ra[0], MEM[ra[1]], ra[2]) +4 rt[0] = write(ra[0], MEM[ra[1]], ra[2]) +5 printf(MEM[ra[0]], ra[1], ra[2], ra[3]) +42 rt[0] = clock() +52 rt[0] = lseek(ra0, ra1, ra2) + +*/ + + +/* new multiprecision add/sub */ +APUOP(M_ADDX, RR, 0x340, "addx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ +APUOP(M_CG, RR, 0x0c2, "cg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ +APUOP(M_CGX, RR, 0x342, "cgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ +APUOP(M_SFX, RR, 0x341, "sfx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ +APUOP(M_BG, RR, 0x042, "bg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ +APUOP(M_BGX, RR, 0x343, "bgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ + +/* + +The following ops are a subset of above except with feature bits set. +Feature bits are bits 11-17 of the instruction: + + 11 - C & P feature bit + 12 - disable interrupts + 13 - enable interrupts + +*/ +APUOPFB(M_BID, RR, 0x1a8, 0x20, "bid", _A1(A_A), 00010, BR) /* BI IP<-RA */ +APUOPFB(M_BIE, RR, 0x1a8, 0x10, "bie", _A1(A_A), 00010, BR) /* BI IP<-RA */ +APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ +APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ +APUOPFB(M_IRETD, RR, 0x1aa, 0x20, "iretd", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ +APUOPFB(M_IRETD2, RR, 0x1aa, 0x20, "iretd", _A0(), 00010, BR) /* IRET IP<-SRR0 */ +APUOPFB(M_IRETE, RR, 0x1aa, 0x10, "irete", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ +APUOPFB(M_IRETE2, RR, 0x1aa, 0x10, "irete", _A0(), 00010, BR) /* IRET IP<-SRR0 */ +APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ +APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ +APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ +APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ +APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ +APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ +APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOPFB(M_SYNCC, RR, 0x002, 0x40, "syncc", _A0(), 00000, BR) /* SYNCC flush_pipe */ +APUOPFB(M_HBRP, LBTI, 0x1ac, 0x40, "hbrp", _A0(), 00010, LS) /* HBR BTB[B9]<-M[Ra] */ + +/* Synonyms required by the AS manual. */ +APUOP(M_LR, RI10, 0x020, "lr", _A2(A_T,A_A), 00012, FX2) /* OR%I RT<-RA|I10 */ +APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ +APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ +APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ +APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ +APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ +APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ +APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ + +/* New soma double-float insns. */ +APUOP(M_DFCEQ, RR, 0x3c3, "dfceq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCEQ RT<-(RA=RB) */ +APUOP(M_DFCMEQ, RR, 0x3cb, "dfcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMEQ RT<-(|RA|=|RB|) */ +APUOP(M_DFCGT, RR, 0x2c3, "dfcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCGT RT<-(RA>RB) */ +APUOP(M_DFCMGT, RR, 0x2cb, "dfcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMGT RT<-(|RA|>|RB|) */ +APUOP(M_DFTSV, RI7, 0x3bf, "dftsv", _A3(A_T,A_A,A_U7), 00012, FX2) /* DFTSV RT<-testspecial(RA,I7) */ + +#undef _A0 +#undef _A1 +#undef _A2 +#undef _A3 +#undef _A4 diff --git a/contrib/binutils/include/opcode/spu.h b/contrib/binutils/include/opcode/spu.h new file mode 100644 index 0000000..975b1fd --- /dev/null +++ b/contrib/binutils/include/opcode/spu.h @@ -0,0 +1,126 @@ +/* SPU ELF support for BFD. + + Copyright 2006 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* These two enums are from rel_apu/common/spu_asm_format.h */ +/* definition of instruction format */ +typedef enum { + RRR, + RI18, + RI16, + RI10, + RI8, + RI7, + RR, + LBT, + LBTI, + IDATA, + UNKNOWN_IFORMAT +} spu_iformat; + +/* These values describe assembly instruction arguments. They indicate + * how to encode, range checking and which relocation to use. */ +typedef enum { + A_T, /* register at pos 0 */ + A_A, /* register at pos 7 */ + A_B, /* register at pos 14 */ + A_C, /* register at pos 21 */ + A_S, /* special purpose register at pos 7 */ + A_H, /* channel register at pos 7 */ + A_P, /* parenthesis, this has to separate regs from immediates */ + A_S3, + A_S6, + A_S7N, + A_S7, + A_U7A, + A_U7B, + A_S10B, + A_S10, + A_S11, + A_S11I, + A_S14, + A_S16, + A_S18, + A_R18, + A_U3, + A_U5, + A_U6, + A_U7, + A_U14, + A_X16, + A_U18, + A_MAX +} spu_aformat; + +enum spu_insns { +#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + TAG, +#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + TAG, +#include "opcode/spu-insns.h" +#undef APUOP +#undef APUOPFB + M_SPU_MAX +}; + +struct spu_opcode +{ + spu_iformat insn_type; + unsigned int opcode; + char *mnemonic; + int arg[5]; +}; + +#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size)) +#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1)) + +#define DECODE_INSN_RT(insn) (insn & 0x7f) +#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f) +#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f) +#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f) + +#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14) +#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14) + +/* For branching, immediate loads, hbr and lqa/stqa. */ +#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7) +#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7) + +/* for stop */ +#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0) + +/* For ila */ +#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7) +#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7) + +/* For rotate and shift and generate control mask */ +#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14) +#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14) + +/* For float <-> int conversion */ +#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14) +#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14) + +/* For hbr */ +#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) +#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) +#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) +#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) + |
