diff options
Diffstat (limited to 'contrib/binutils/include/opcode')
-rw-r--r-- | contrib/binutils/include/opcode/ChangeLog | 275 | ||||
-rw-r--r-- | contrib/binutils/include/opcode/alpha.h | 8 | ||||
-rw-r--r-- | contrib/binutils/include/opcode/arc.h | 6 | ||||
-rw-r--r-- | contrib/binutils/include/opcode/cgen.h | 57 | ||||
-rw-r--r-- | contrib/binutils/include/opcode/i386.h | 9 | ||||
-rw-r--r-- | contrib/binutils/include/opcode/ppc.h | 19 |
6 files changed, 299 insertions, 75 deletions
diff --git a/contrib/binutils/include/opcode/ChangeLog b/contrib/binutils/include/opcode/ChangeLog index 9e40d0c..dcde56b 100644 --- a/contrib/binutils/include/opcode/ChangeLog +++ b/contrib/binutils/include/opcode/ChangeLog @@ -1,26 +1,152 @@ -2001-06-11 Alan Modra <amodra@bigpond.net.au> +2002-01-22 Graydon Hoare <graydon@redhat.com> - Merge from mainline. - 2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - * mips.h (CPU_R12000): Define. + * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. + (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. - 2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - * mips.h (INSN_ISA_MASK): Define. +2002-01-21 Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at> - 2001-03-21 Kazu Hirata <kazu@hxi.com> - * h8300.h: Fix formatting. + * h8300.h: Comment typo fix. - 2001-02-28 Igor Shevlyakov <igor@windriver.com> - * m68k.h: new defines for Coldfire V4. Update mcf to know - about mcf5407. +2002-01-03 matthew green <mrg@redhat.com> - 2001-02-10 Nick Clifton <nickc@redhat.com> - * mips.h: Remove extraneous whitespace. Formating change to allow - for future contribution. + * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. + (PPC_OPCODE_BOOKE64): Likewise. + +Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com) + + * hppa.h (call, ret): Move to end of table. + (addb, addib): PA2.0 variants should have been PA2.0W. + (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler + happy. + (fldw, fldd, fstw, fstd, bb): Likewise. + (short loads/stores): Tweak format specifier slightly to keep + disassembler happy. + (indexed loads/stores): Likewise. + (absolute loads/stores): Likewise. + +2001-12-04 Alexandre Oliva <aoliva@redhat.com> + + * d10v.h (OPERAND_NOSP): New macro. + +2001-11-29 Alexandre Oliva <aoliva@redhat.com> + + * d10v.h (OPERAND_SP): New macro. + +2001-11-15 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * tic54x.h: Revise opcode layout; don't really need a separate + structure for parallel opcodes. + +2001-11-13 Zack Weinberg <zack@codesourcery.com> + Alan Modra <amodra@bigpond.net.au> + + * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to + accept WordReg. + +2001-11-04 Chris Demetriou <cgd@broadcom.com> + + * mips.h (OPCODE_IS_MEMBER): Remove extra space. + +2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> + + * mmix.h: New file. + +2001-10-18 Chris Demetriou <cgd@broadcom.com> + + * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end + of the expression, to make source code merging easier. + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips.h: Sort coprocessor instruction argument characters + in comment, add a few more words of description for "H". + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips.h (INSN_SB1): New cpu-specific instruction bit. + (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 + if cpu is CPU_SB1. + +2001-10-17 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. + +2001-10-12 matthew green <mrg@redhat.com> + + * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New + opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403 + instructions, respectively. + +2001-09-27 Nick Clifton <nickc@cambridge.redhat.com> + + * v850.h: Remove spurious comment. + +2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> + + * h8300.h: Fix compile time warning messages + +2001-09-04 Richard Henderson <rth@redhat.com> + + * alpha.h (struct alpha_operand): Pack elements into bitfields. + +2001-08-31 Eric Christopher <echristo@redhat.com> + + * mips.h: Remove CPU_MIPS32_4K. + +2001-08-27 Torbjorn Granlund <tege@swox.com> + + * ppc.h (PPC_OPERAND_DS): Define. + +2001-08-25 Andreas Jaeger <aj@suse.de> + + * d30v.h: Fix declaration of reg_name_cnt. + + * d10v.h: Fix declaration of d10v_reg_name_cnt. + + * arc.h: Add prototypes from opcodes/arc-opc.c. -2001-06-07 Alan Modra <amodra@bigpond.net.au> +2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - * Many files: Update copyright notices. + * mips.h (INSN_10000): Define. + (OPCODE_IS_MEMBER): Check for INSN_10000. + +2001-08-10 Alan Modra <amodra@one.net.au> + + * ppc.h: Revert 2001-08-08. + +2001-08-08 Alan Modra <amodra@one.net.au> + + 1999-10-25 Torbjorn Granlund <tege@swox.com> + * ppc.h (struct powerpc_operand): New field `reloc'. + +2001-07-11 Frank Ch. Eigler <fche@redhat.com> + + * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. + (cgen_cpu_desc): Ditto. + +2001-07-07 Ben Elliston <bje@redhat.com> + + * m88k.h: Clean up and reformat. Remove unused code. + +2001-06-14 Geoffrey Keating <geoffk@redhat.com> + + * cgen.h (cgen_keyword): Add nonalpha_chars field. + +2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (CPU_R12000): Define. + +2001-05-23 John Healy <jhealy@redhat.com> + + * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48. + +2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips.h (INSN_ISA_MASK): Define. 2001-05-12 Alan Modra <amodra@one.net.au> @@ -33,11 +159,24 @@ * i386.h (i386_optab): Move InvMem to first operand of pmovmskb and pextrw to swap reg/rm assignments. +2001-04-05 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (enum cris_insn_version_usage): Correct comment for + cris_ver_v3p. + 2001-03-24 Alan Modra <alan@linuxcare.com.au> * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq". Add InvMem to first operand of "maskmovdqu". +2001-03-22 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (ADD_PC_INCR_OPCODE): New macro. + +2001-03-21 Kazu Hirata <kazu@hxi.com> + + * h8300.h: Fix formatting. + 2001-03-22 Alan Modra <alan@linuxcare.com.au> * i386.h (i386_optab): Add paddq, psubq. @@ -46,11 +185,35 @@ * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define. -Mon Feb 12 17:39:31 CET 2001 Jan Hubicka <jh@suse.cz> +2001-02-28 Igor Shevlyakov <igor@windriver.com> + + * m68k.h: new defines for Coldfire V4. Update mcf to know + about mcf5407. + +2001-02-18 lars brinkhoff <lars@nocrew.org> + + * pdp11.h: New file. + +2001-02-12 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): SSE integer converison instructions have 64bit versions on x86-64. +2001-02-10 Nick Clifton <nickc@redhat.com> + + * mips.h: Remove extraneous whitespace. Formating change to allow + for future contribution. + +2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390.h: New file. + +2001-02-02 Patrick Macdonald <patrickm@redhat.com> + + * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. + (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. + (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. + 2001-01-24 Karsten Keil <kkeil@suse.de> * i386.h (i386_optab): Fix swapgs @@ -62,7 +225,7 @@ Mon Feb 12 17:39:31 CET 2001 Jan Hubicka <jh@suse.cz> (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. Remove duplicate "ldw j(s,b),x". Sort some entries. -Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> +2001-01-13 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Fix pusha and ret templates. @@ -117,7 +280,7 @@ Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field. - + 2000-12-12 Nick Clifton <nickc@redhat.com> * mips.h: Fix formatting. @@ -142,7 +305,7 @@ Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> (ISA_UNKNOWN): New constant to indicate unknown ISA. (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, ISA_MIPS32): New constants, defined to be the mask of INSN_* - constants available at that ISA level. + constants available at that ISA level. (CPU_UNKNOWN): New constant to indicate unknown CPU. (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, define it with a unique value. @@ -150,7 +313,7 @@ Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> constant meanings. * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New - definitions. + definitions. * mips.h (CPU_SB1): New constant. @@ -164,21 +327,21 @@ Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. 2000-09-13 Anders Norlander <anorland@acc.umu.se> - + * mips.h: Use defines instead of hard-coded processor numbers. (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, - CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, + CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, CPU_4KC, CPU_4KM, CPU_4KP): Define.. (OPCODE_IS_MEMBER): Use new defines. - (OP_MASK_SEL, OP_SH_SEL): Define. + (OP_MASK_SEL, OP_SH_SEL): Define. (OP_MASK_CODE20, OP_SH_CODE20): Define. - Add 'P' to used characters. - Use 'H' for coprocessor select field. + Add 'P' to used characters. + Use 'H' for coprocessor select field. Use 'm' for 20 bit breakpoint code. - Document new arg characters and add to used characters. - (INSN_MIPS32): New define for MIPS32 extensions. - (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. + Document new arg characters and add to used characters. + (INSN_MIPS32): New define for MIPS32 extensions. + (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. 2000-09-05 Alan Modra <alan@linuxcare.com.au> @@ -358,7 +521,7 @@ Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. (CGEN_CPU_TABLE): flags: new field. Add prototypes for new functions. - + 2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> * i386.h: Add some more UNIXWARE_COMPAT comments. @@ -476,7 +639,7 @@ Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) * hppa.h (pa_opcodes): Use 'fX' for first register operand - in xmpyu. + in xmpyu. * hppa.h (pa_opcodes): Fix mask for probe and probei. @@ -562,7 +725,7 @@ Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. - * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, + * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. 1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> @@ -590,7 +753,7 @@ Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) * hppa.h (pa_opcodes): Move integer arithmetic instructions after - integer logical instructions. + integer logical instructions. 1999-05-28 Linus Nordberg <linus.nordberg@canit.se> @@ -607,7 +770,7 @@ Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) - * hppa.h (pa_opcodes): Add second entry for "comb", "comib", + * hppa.h (pa_opcodes): Add second entry for "comb", "comib", "addb", and "addib" to be used by the disassembler. 1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> @@ -718,7 +881,7 @@ Sat Feb 13 14:13:44 1999 Richard Henderson <rth@cygnus.com> (CGEN_INSN_ATTR): New type. Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> - + * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define. (x_FP, d_FP, dls_FP, sldx_FP): Define. Change *Suf definitions to include x and d suffixes. @@ -741,7 +904,7 @@ Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT, CGEN_MODE_UINT. -Sat Jan 16 01:29:25 1999 Jeffrey A Law (law@cygnus.com) +1999-01-16 Jeffrey A Law (law@cygnus.com) * hppa.h (bv): Fix mask. @@ -759,16 +922,16 @@ Sat Jan 16 01:29:25 1999 Jeffrey A Law (law@cygnus.com) Wed Dec 9 10:38:48 1998 David Taylor <taylor@texas.cygnus.com> The following is part of a change made by Edith Epstein - <eepstein@sophia.cygnus.com> as part of a project to merge in - changes by HP; HP did not create ChangeLog entries. + <eepstein@sophia.cygnus.com> as part of a project to merge in + changes by HP; HP did not create ChangeLog entries. * hppa.h (completer_chars): list of chars to not put a space - after. + after. Sun Dec 6 13:21:34 1998 Ian Lance Taylor <ian@cygnus.com> * i386.h (i386_optab): Permit w suffix on processor control and - status word instructions. + status word instructions. 1998-11-30 Doug Evans <devans@casey.cygnus.com> @@ -829,7 +992,7 @@ Fri Oct 9 13:38:13 1998 Doug Evans <devans@seba.cygnus.com> Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com) * hppa.h: Add "fid". - + Sun Oct 4 21:00:00 1998 Alan Modra <alan@spri.levels.unisa.edu.au> From Robert Andrew Dale <rob@nb.net> @@ -883,7 +1046,7 @@ Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com) * mn10300.h: Add "machine" field for instructions. (MN103, AM30): Define machine types. - + Fri Jun 19 16:09:09 1998 Alan Modra <alan@spri.levels.unisa.edu.au> * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor. @@ -1488,9 +1651,9 @@ Mon Nov 4 12:52:48 1996 Jeffrey A Law (law@cygnus.com) Fri Nov 1 10:31:02 1996 Richard Henderson <rth@tamu.edu> * alpha.h: Don't include "bfd.h"; private relocation types are now - negative to minimize problems with shared libraries. Organize - instruction subsets by AMASK extensions and PALcode - implementation. + negative to minimize problems with shared libraries. Organize + instruction subsets by AMASK extensions and PALcode + implementation. (struct alpha_operand): Move flags slot for better packing. Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com) @@ -1543,9 +1706,9 @@ Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com) Thu Aug 22 16:51:25 1996 J.T. Conklin <jtc@rtl.cygnus.com> * v850.h (v850_operands): Add insert and extract fields, pointers - to functions used to handle unusual operand encoding. + to functions used to handle unusual operand encoding. (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC, - V850_OPERAND_SIGNED): Defined. + V850_OPERAND_SIGNED): Defined. Wed Aug 21 17:45:10 1996 J.T. Conklin <jtc@rtl.cygnus.com> @@ -1559,11 +1722,11 @@ Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com> Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk> * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM, - OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, - OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, - OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, - OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): - Defined. + OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, + OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, + OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, + OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): + Defined. Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) @@ -1573,7 +1736,7 @@ Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) Thu Aug 15 13:11:46 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * d10v.h: Add some additional defines to support the - assembler in determining which operations can be done in parallel. + assembler in determining which operations can be done in parallel. Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com) @@ -1589,7 +1752,7 @@ Fri Jul 26 11:47:10 1996 Martin M. Hunt <hunt@pizza.cygnus.com> Thu Jul 25 12:06:22 1996 Martin M. Hunt <hunt@pizza.cygnus.com> * d10v.h: Changes for divs, parallel-only instructions, and - signed numbers. + signed numbers. Mon Jul 22 11:21:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com> @@ -1611,7 +1774,7 @@ Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com) Wed Jul 3 14:30:12 1996 J.T. Conklin <jtc@rtl.cygnus.com> - * m68k.h (mcf5200): New macro. + * m68k.h (mcf5200): New macro. Document names of coldfire control registers. Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com) @@ -1761,7 +1924,7 @@ Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com) Mon Oct 23 11:09:16 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific - instructions. + instructions. Mon Oct 16 10:28:15 1995 Michael Meissner <meissner@tiktok.cygnus.com> diff --git a/contrib/binutils/include/opcode/alpha.h b/contrib/binutils/include/opcode/alpha.h index 6f31e9a..487b696 100644 --- a/contrib/binutils/include/opcode/alpha.h +++ b/contrib/binutils/include/opcode/alpha.h @@ -81,16 +81,16 @@ extern const unsigned alpha_num_opcodes; struct alpha_operand { /* The number of bits in the operand. */ - int bits; + unsigned int bits : 5; /* How far the operand is left shifted in the instruction. */ - int shift; + unsigned int shift : 5; /* The default relocation type for this operand. */ - int default_reloc; + signed int default_reloc : 16; /* One bit syntax flags. */ - unsigned flags; + unsigned int flags : 16; /* Insertion function. This is used by the assembler. To insert an operand value into an instruction, check this field. diff --git a/contrib/binutils/include/opcode/arc.h b/contrib/binutils/include/opcode/arc.h index 81e5bd8..b137840 100644 --- a/contrib/binutils/include/opcode/arc.h +++ b/contrib/binutils/include/opcode/arc.h @@ -313,3 +313,9 @@ const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value)); int arc_opcode_supported PARAMS ((const struct arc_opcode *)); int arc_opval_supported PARAMS ((const struct arc_operand_value *)); +int arc_limm_fixup_adjust PARAMS ((arc_insn)); +int arc_insn_is_j PARAMS ((arc_insn)); +int arc_insn_not_jl PARAMS ((arc_insn)); +int arc_operand_type PARAMS ((int)); +struct arc_operand_value *get_ext_suffix PARAMS ((char *)); +int arc_get_noshortcut_flag PARAMS ((void)); diff --git a/contrib/binutils/include/opcode/cgen.h b/contrib/binutils/include/opcode/cgen.h index 8cf3123..e603b55 100644 --- a/contrib/binutils/include/opcode/cgen.h +++ b/contrib/binutils/include/opcode/cgen.h @@ -199,6 +199,8 @@ typedef struct { const char *bfd_name; /* one of enum mach_attr */ int num; + /* parameter from mach->cpu */ + unsigned int insn_chunk_bitsize; } CGEN_MACH; /* Parse result (also extraction result). @@ -513,6 +515,11 @@ typedef struct cgen_keyword /* Pointer to null keyword "" entry if present. */ const CGEN_KEYWORD_ENTRY *null_entry; + + /* String containing non-alphanumeric characters used + in keywords. + At present, the highest number of entries used is 1. */ + char nonalpha_chars[8]; } CGEN_KEYWORD; /* Structure used for searching. */ @@ -602,6 +609,23 @@ enum cgen_operand_type { CGEN_OPERAND_MAX }; /* "nil" indicator for the operand instance table */ #define CGEN_OPERAND_NIL CGEN_OPERAND_MAX +/* A tree of these structs represents the multi-ifield + structure of an operand's hw-index value, if it exists. */ + +struct cgen_ifld; + +typedef struct cgen_maybe_multi_ifield +{ + int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); + n: indexed by array of more cgen_maybe_multi_ifields. */ + union + { + struct cgen_maybe_multi_ifield * multi; + struct cgen_ifld * leaf; + } val; +} +CGEN_MAYBE_MULTI_IFLD; + /* This struct defines each entry in the operand table. */ typedef struct @@ -630,6 +654,11 @@ typedef struct May be unused for a modifier. */ unsigned char length; + /* The (possibly-multi) ifield used as an index for this operand, if it + is indexed by a field at all. This substitutes / extends the start and + length fields above, but unsure at this time whether they are used + anywhere. */ + CGEN_MAYBE_MULTI_IFLD index_fields; #if 0 /* ??? Interesting idea but relocs tend to get too complicated, and ABI dependent, for simple table lookups to work. */ /* Ideally this would be the internal (external?) reloc type. */ @@ -736,25 +765,21 @@ typedef struct the data is recorded in the parse/insert/extract/print switch statements. */ /* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_SYNTAX_BYTES 40 +#define CGEN_MAX_SYNTAX_ELEMENTS 48 /* A target may know its own precise maximum. Assert that it falls below the above limit. */ -#ifdef CGEN_ACTUAL_MAX_SYNTAX_BYTES -#if CGEN_ACTUAL_MAX_SYNTAX_BYTES > CGEN_MAX_SYNTAX_BYTES -#error "CGEN_ACTUAL_MAX_SYNTAX_BYTES too high - enlarge CGEN_MAX_SYNTAX_BYTES" +#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS +#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS +#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" #endif #endif -#if !defined(MAX_OPERANDS) || MAX_OPERANDS <= 127 -typedef unsigned char CGEN_SYNTAX_CHAR_TYPE; -#else typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; -#endif typedef struct { - CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_BYTES]; + CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; } CGEN_SYNTAX; #define CGEN_SYNTAX_STRING(syn) (syn->syntax) @@ -1006,6 +1031,11 @@ struct cgen_insn const CGEN_IBASE *base; const CGEN_OPCODE *opcode; const CGEN_OPINST *opinst; + + /* Regex to disambiguate overloaded opcodes */ + void *rx; +#define CGEN_INSN_RX(insn) ((insn)->rx) +#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) }; /* Instruction lists. @@ -1165,6 +1195,10 @@ typedef struct cgen_cpu_desc lazily fetch the data from there. */ unsigned int word_bitsize; + /* Instruction chunk size (in bits), for purposes of endianness + conversion. */ + unsigned int insn_chunk_bitsize; + /* Indicator if sizes are unknown. This is used by default_insn_bitsize,base_insn_bitsize if there is a difference between the selected isa's. */ @@ -1357,6 +1391,11 @@ extern void CGEN_SYM (cpu_close) PARAMS ((CGEN_CPU_DESC)); extern void CGEN_SYM (init_opcode_table) PARAMS ((CGEN_CPU_DESC cd_)); +/* build the insn selection regex. + called by init_opcode_table */ + +extern char * CGEN_SYM(build_insn_regex) PARAMS ((CGEN_INSN *insn_)); + /* Initialize the ibld table for use. Called by init_asm/init_dis. */ diff --git a/contrib/binutils/include/opcode/i386.h b/contrib/binutils/include/opcode/i386.h index 38de44a..571990e 100644 --- a/contrib/binutils/include/opcode/i386.h +++ b/contrib/binutils/include/opcode/i386.h @@ -553,9 +553,12 @@ static const template i386_optab[] = { {"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, {"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, {"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, {"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, diff --git a/contrib/binutils/include/opcode/ppc.h b/contrib/binutils/include/opcode/ppc.h index d23e1c6..dc3983e 100644 --- a/contrib/binutils/include/opcode/ppc.h +++ b/contrib/binutils/include/opcode/ppc.h @@ -1,5 +1,5 @@ /* ppc.h -- Header file for PowerPC opcode table - Copyright 1994, 1995, 1999, 2000 Free Software Foundation, Inc. + Copyright 1994, 1995, 1999, 2000, 2001 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -89,7 +89,16 @@ extern const int powerpc_num_opcodes; #define PPC_OPCODE_64_BRIDGE (0400) /* Opcode is supported by Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC (01000) +#define PPC_OPCODE_ALTIVEC (01000) + +/* Opcode is supported by PowerPC 403 processor. */ +#define PPC_OPCODE_403 (02000) + +/* Opcode is supported by PowerPC BookE processor. */ +#define PPC_OPCODE_BOOKE (04000) + +/* Opcode is only supported by 64-bit PowerPC BookE processor. */ +#define PPC_OPCODE_BOOKE64 (010000) /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -121,6 +130,7 @@ struct powerpc_operand operand value is legal, *ERRMSG will be unchanged (most operands can accept any value). */ unsigned long (*insert) PARAMS ((unsigned long instruction, long op, + int dialect, const char **errmsg)); /* Extraction function. This is used by the disassembler. To @@ -140,7 +150,8 @@ struct powerpc_operand non-zero if this operand type can not actually be extracted from this operand (i.e., the instruction does not match). If the operand is valid, *INVALID will not be changed. */ - long (*extract) PARAMS ((unsigned long instruction, int *invalid)); + long (*extract) PARAMS ((unsigned long instruction, int dialect, + int *invalid)); /* One bit syntax flags. */ unsigned long flags; @@ -229,6 +240,8 @@ extern const struct powerpc_operand powerpc_operands[]; prints these with a leading 'v'. */ #define PPC_OPERAND_VR (010000) +/* This operand is for the DS field in a DS form instruction. */ +#define PPC_OPERAND_DS (020000) /* The POWER and PowerPC assemblers use a few macros. We keep them with the operands table for simplicity. The macro table is an |