97 files changed, 43981 insertions, 16031 deletions

diff --git a/contrib/binutils/gas/ChangeLog b/contrib/binutils/gas/ChangeLog
index 1723944..704e6f9 100644
--- a/contrib/binutils/gas/ChangeLog
+++ b/contrib/binutils/gas/ChangeLog
@@ -1,758 +1,1294 @@
-2006-07-19  Mat Hostetter  <mat@lcs.mit.edu>
+2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 
-	* symbols.c (report_op_error): Fix pasto.  Don't use as_bad_where
-	when file and line unknown.
+	* config/tc-m68k.c (m68k_ip): Add j & K operand types.
+	(install_operand): Add E encoding.
+	(md_begin): Check and skip initial '.' arg character.
+	(get_num): Add 0..511 case.
 
-2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
+2007-07-03  Alan Modra  <amodra@bigpond.net.au>
 
-	* po/Make-in (pdf, ps): New dummy targets.
+	PR 4713
+	* config/obj-elf.c (elf_ecoff_set_ext): Make static when OBJ_MAYBE_ELF.
+	* config/obj-elf.h (obj_ecoff_set_ext): Comment.
 
-2006-06-02  Joseph S. Myers  <joseph@codesourcery.com>
+2007-07-03  Mikkel Lauritsen  <renard@nospam.dk>
 
-	* doc/Makefile.am (TEXI2DVI): Define.
+	PR 4722
+	* app.c (do_scrub_chars <state 5>): Check for output buffer full
+	after memcpy.
+
+2007-07-02  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-mips.c (s_dtprelword, s_dtpreldword,
+	s_dtprel_internal): New.
+	(mips_pseudo_table): Add .dtprelword and .dtpreldword.
+	(md_apply_fix): Handle BFD_RELOC_MIPS_TLS_DTPREL32 and
+	BFD_RELOC_MIPS_TLS_DTPREL64.
+
+2007-07-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* aclocal.m4: Regenerate.
+	* config.in: Regenerate.
 	* doc/Makefile.in: Regenerate.
-	* doc/c-arc.texi: Fix typo.
+	* po/POTFILES.in: Regenerate.
+	* po/gas.pot: Regenerate.
 
-2006-05-30  Nick Clifton  <nickc@redhat.com>
+2007-07-02  Alan Modra  <amodra@bigpond.net.au>
 
-	* po/es.po: Updated Spanish translation.
+	* config/tc-ppc.c (ppc_pe_section): Comment out code assigning
+	coff section flag values to bfd section flag.
 
-2006-05-25  Nathan Sidwell  <nathan@codesourcery.com>
+2007-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* gas/config/tc-m68k.c (m68k_init_arch): Move checking of
-	cfloat/m68881 to correct architecture before using it.
+	* aclocal.m4: Regenerated.
+	* doc/Makefile.in: Likewise.
+	* Makefile.in: Likewise.
 
-2006-05-16  Nick Clifton  <nickc@redhat.com>
+2007-06-29  Joseph Myers  <joseph@codesourcery.com>
 
-	* Import these patches from the mainline:
+	* as.c (main): Only call create_obj_attrs_section if IS_ELF.
 
-	2006-05-16  Bjoern Haase  <bjoern.m.haase@web.de>
+2007-06-29  Joseph Myers  <joseph@codesourcery.com>
 
-        * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
-	constant values.
+	* as.c (create_obj_attrs_section): New.
+	(main): Call create_obj_attrs_section for ELF.
+	* read.c (s_gnu_attribute, skip_whitespace, skip_past_char,
+	skip_past_comma, s_vendor_attribute): New.
+	(potable): Add gnu_attribute for ELF.
+	* read.h (s_vendor_attribute): Declare.
+	* config/tc-arm.c (s_arm_eabi_attribute): Replace by wrapper
+	round s_vendor_attribute.
+	(aeabi_set_public_attributes): Update for new attributes
+	interfaces.
+	(arm_md_end): Remove attributes contents setting now done
+	generically.
 
-	2006-05-05  Bjoern Haase  <bjoern.m.haase@web.de>
+2007-06-29  M R Swami Reddy  <MR.Swami.Redd@nsc.com>
 
-	* gas/config/tc-avr.h (TC_VALIDATE_FIX): Define.  Disable fixups
-	for PMEM related expressions.
+	* Makefile.am: Add CR16 related entry.
+	* Makefile.in: Regenerate.
+	* config/tc-cr16.h: New file
+	* config/tc-cr16.c: New file
+	* doc/c-cr16.texi: New file for cr16 
+	* doc/all.texi: Entry for cr16 
+	* doc/Makefile.am: Added c-cr16.texi
+	* doc/Makefile.in: Regenerate 
+	* doc/as.texinfo: Entry for CR16 target
+	* NEWS: Announce the support for the new target.
 
-2006-05-11  Thiemo Seufer  <ths@mips.com>
+2007-06-26  Paul Brook  <paul@codesourcery.com>
 
-	* config/tc-mips.c (append_insn): Don't check the range of j or
-	jal addresses.
+	* config/tc-arm.c (parse_operands): Accept generic coprocessor regs
+	for OP_RVC.
+	(reg_names): Add fpinst, pfinst2, mvfr0 and mvfr1.
 
-2006-05-10  Alan Modra  <amodra@bigpond.net.au>
+2007-06-25  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
-	of list rather than beginning.
+	* config/tc-i386.c (process_operands): Replace regKludge
+	with RegKludge.
 
-2006-05-10  Alan Modra  <amodra@bigpond.net.au>
+2007-06-25  Richard Sandiford  <richard@codesourcery.com>
 
-	* write.c (relax_segment): Add pass count arg.  Don't error on
-	negative org/space on first two passes.
-	(relax_seg_info): New struct.
-	(relax_seg, write_object_file): Adjust.
-	* write.h (relax_segment): Update prototype.
+	* config/tc-mips.h (TC_SYMFIELD_TYPE): New.
+	* config/tc-mips.c (append_insn): Record which symbols have
+	R_MIPS16_26 relocations against them.
+	(mips_fix_adjustable): Don't reduce relocations against such symbols.
 
-2006-05-02  Joseph Myers  <joseph@codesourcery.com>
+2007-06-22  Sterling Augustine  <sterling@tensilica.com>
 
-	* config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
-	here.
-	(md_apply_fix3): Multiply offset by 4 here for
-	BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
+	* config/tc-xtensa.c (xg_assembly_relax): Comment termination rules.
+	(frag_format_size): Handle RELAX_IMMED_STEP3.
+	(xtensa_relax_frag, md_convert_frag): Likewise.
+	* config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_IMMED_STEP3.
+	(RELAX_IMMED_MAXSTEPS): Adjust.
+	* config/xtensa-relax.c (widen_spec_list): Add transitions from
+	wide branches to branch-over-jumps.
+	(build_transition): Handle wide branches in transition patterns.
+	
+2007-06-22  H.J. Lu  <hongjiu.lu@intel.com>
 
-2006-05-02  Daniel Jacobowitz  <dan@codesourcery.com>
+	* config/tc-i386.c (disp_size): New.
+	(imm_size): Likewise.
+	(output_disp): Use disp_size and imm_size.
+	(output_imm): Use imm_size.
 
-	* doc/Makefile.am (AM_MAKEINFOFLAGS): New.
-	(TEXI2POD): Use AM_MAKEINFOFLAGS.
-	(asconfig.texi): Don't set top_srcdir.
-	* doc/as.texinfo: Don't use top_srcdir.
-	* aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
+2007-06-19  Sterling Augustine  <sterling@tensilica.com>
 
-2006-05-02  Paul Brook  <paul@codesourcery.com>
+	* config/tc-xtensa.h (struct xtensa_frag_type): Update comment about
+	use of literal_frag field.
+	* config/tc-xtensa.c (xtensa_mark_literal_pool_location): Record frag
+	in the literal_frag field.
+	(xtensa_move_literals): Use it here instead of searching.  Update
+	literal_frag field with new value.
 
-	* config/tc-arm.c (arm_optimize_expr): New function.
-	* config/tc-arm.h (md_optimize_expr): Define
-	(arm_optimize_expr): Add prototype.
-	(TC_FORCE_RELOCATION_SUB_SAME): Define.
+2007-06-14  Paul Brook  <paul@codesourcery.com>
 
-2006-05-01  James Lemke  <jwlemke@wasabisystems.com>
+	* config/tc-arm.c (do_t_mov_cmp): Handle shift by register and
+	narrow shift by immediate.
 
-	* subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
+2007-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 
-2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+	* Makefile.am (ACLOCAL_AMFLAGS): Add -I ../config -I ../bfd.
 
-	* config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
-	syntax instead of hardcoded opcodes with ".w18" suffixes.
-	(wide_branch_opcode): New.
-	(build_transition): Use it to check for wide branch opcodes with
-	either ".w18" or ".w15" suffixes.
+	* acinclude.m4: Don't include m4 files.
+	(BFD_BINARY_FOPEN): Removed.
+	Remove libtool kludge.
 
-2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+	* Makefile.in: Regenerated.
+	* doc/Makefile.in: Likewise.
+	* aclocal.m4: Likewise.
+	* configure: Likewise.
 
-	* config/tc-xtensa.c (xtensa_create_literal_symbol,
-	xg_assemble_literal, xg_assemble_literal_space): Do not set the
-	frag's is_literal flag.
+2007-06-11  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+	
+	* config/tc-xtensa.c (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to...
+	(XTENSA_PROP_NO_TRANSFORM): ...this.
+	(frag_flags_struct): Move is_no_transform out of the insn sub-struct.
+	(xtensa_mark_frags_for_org): New.
+	(xtensa_handle_align): Set RELAX_ORG frag subtype for rs_org.
+	(xtensa_post_relax_hook): Call xtensa_mark_frags_for_org.
+	(get_frag_property_flags): Adjust reference to is_no_transform flag.
+	(xtensa_frag_flags_combinable): Likewise.
+	(frag_flags_to_number): Likewise.  Use XTENSA_PROP_NO_TRANSFORM.
+	* config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_ORG.
+	
+2007-06-06  Paul Brook  <paul@codesourcery.com>
 
-2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+	* config/tc-arm.c (s_align): Pad code sections appropriately.
 
-	* config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
+2007-06-05  Paul Brook  <paul@codesourcery.com>
 
-2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
+	* config/tc-arm.c (insns): Correct Thumb-2 ldrd/strd opcodes.
 
-	* po/POTFILES.in: Regenerated.
+2007-06-05  Nick Clifton  <nickc@redhat.com>
 
-2006-04-14  Sterling Augustine  <sterling@tensilica.com>
+	PR gas/4587
+	* config/tc-sparc.c (sparc_ip): Terminate tls_ops array.
 
-	* config/tc-xtensa.c (emit_single_op): Do not relax MOVI
-	instructions when such transformations have been disabled.
+2007-06-05  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-10  Sterling Augustine  <sterling@tensilica.com>
+	* config/tc-spu.c (spu_cons): Use deferred_expression.  Handle
+	number@ppu.
+	(tc_gen_reloc): Abort if neither addsy or subsy is set.
+	(md_apply_fix): Don't attempt to resolve SPU_PPU relocs.
+	* config/tc-spu.h (md_operand): Handle @ppu without sym.
 
-	* config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
-	symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
-	(xtensa_fix_close_loop_end_frags): Use the recorded values instead of
-	decoding the loop instructions.  Remove current_offset variable.
-	(xtensa_fix_short_loop_frags): Likewise.
-	(min_bytes_to_other_loop_end): Remove current_offset argument.
+2007-05-31  Paul Brook  <paul@codesourcery.com>
 
-2006-04-09  Arnold Metselaar  <arnold.metselaar@planet.nl>
+	* config/tc-arm.c (insns): Allow strex on M profile cores.
 
-	* config/tc-z80.c (z80_optimize_expr): Removed; redundant since 2006-04-04.
-	* config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
+2007-05-29  David S. Miller  <davem@davemloft.net>
+	    Jakub Jelinek  <jakub@redhat.com>
 
-2006-04-07  Joerg Wunsch <j.gnu@uriah.heep.sax.de>
+	PR gas/4558
+	* config/tc-sparc.c (md_apply_fix): Fix relocation overflow checks
+	for BFD_RELOC_SPARC_WDISP16 and BFD_RELOC_SPARC_WDISP19.
 
-	* gas/config/tc-avr.c (mcu_types): Add support for attiny261,
-	attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
-	attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
-	atmega644, atmega329, atmega3290, atmega649, atmega6490,
-	atmega406, atmega640, atmega1280, atmega1281, at90can32,
-	at90can64, at90usb646, at90usb647, at90usb1286 and
-	at90usb1287.
-	Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
+2007-05-29  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+	* config/tc-spu.h: Wrap in #ifndef/#endif.  Delete coff macros.
 
-	* config/tc-arm.c (parse_operands): Set default error message.
+2007-05-29  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+	* config/tc-ppc.c: Convert to ISO C.
+	* config/tc-ppc.c: Likewise.
 
-	* config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
+2007-05-29  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+	* write.h (EXEC_MACHINE_TYPE): Delete.
+	(string_byte_count, section_alignment): Delete.
 
-	* config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
+2007-05-28  Nathan Sidwell  <nathan@codesourcery.com>
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+	* app.c (do_scrub_chars): Cope with \ at end of buffer.
 
-	* config/tc-arm.c (THUMB2_LOAD_BIT): Define.
-	(move_or_literal_pool): Handle Thumb-2 instructions.
-	(do_t_ldst): Call move_or_literal_pool for =N addressing modes.
+2007-05-26  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-07  Alan Modra  <amodra@bigpond.net.au>
+	* config/tc-ppc.c (ppc_insert_operand): Truncate sign bits in
+	top 32 bits of 64 bit value if so doing results in passing
+	range check.  Rewrite sign extension fudges similarly.  Enable
+	fudges for powerpc64 too.  Report user value if range check
+	fails rather than fudged value.  Negate PPC_OPERAND_NEGATIVE
+	range rather than value, also to report user value on failure.
 
-	PR 2512.
-	* config/tc-i386.c (match_template): Move 64-bit operand tests
-	inside loop.
+2007-03-25  Paul Brook  <paul@codesourcery.com>
 
-2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
+	* config/tc-arm.c (T2_SUBS_PC_LR): Define.
+	(do_t_add_sub): Correctly encode subs pc, lr, #const.
+	(do_t_mov_cmp): Correctly encode movs pc, lr.
 
-	* po/Make-in: Add install-html target.
-	* Makefile.am: Add install-html and install-html-recursive targets.
-	* Makefile.in: Regenerate.
-	* configure.in: AC_SUBST datarootdir, docdir, htmldir.
+2007-05-24  Steve Ellcey  <sje@cup.hp.com>
+
+	* Makefile.in: Regnerate.
 	* configure: Regenerate.
-	* doc/Makefile.am: Add install-html and install-html-am targets.
+	* aclocal.m4: Regenerate.
 	* doc/Makefile.in: Regenerate.
 
-2006-04-06  Alan Modra  <amodra@bigpond.net.au>
+2007-05-22  Bob Wilson  <bob.wilson@acm.org>
+	
+	* doc/c-xtensa.texi (Xtensa Automatic Alignment): Remove statements
+	and index entries about automatic alignment of ENTRY instructions.
+	
+2007-05-22  Nick Clifton  <nickc@redhat.com>
+
+	* doc/as.texinfo: Use @copying around the copyright notice.
+
+2007-05-18  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-mips.c (s_mipsset): Use generic s_set for directives
+	containing a comma.
+
+2007-05-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/4517
+	2003-06-05  Michal Ludvig  <mludvig@suse.cz>
+	* doc/as.texinfo: Document new directives: .cfi_restore, 
+	.cfi_undefined, .cfi_same_value, .cfi_return_column, 
+	.cfi_remember_state and .cfi_restore_state.
+
+2007-05-17  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (md_apply_fix): Show value of out of range
+	fixups in error message.
+	(md_conver_frag_1): Propagate the fix source location and use
+	as_bad_where rather than fatal, for better error messages.
+
+2007-05-16  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (v7m_psrs): Add uppercase PSR names and xpsr.
+
+2007-05-15  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* app.c (do_scrub_chars): Don't damage \@ pseudo-variables.
+
+2007-05-15  Vincent Riviere  <vincent.riviere@freesbee.fr>	
+
+	PR gas/3041
+	* config/tc-m68k.c (relaxable_symbol): Make sure that the correct
+	addend is stored for relocs against weak symbols.
+	(md_apply_fix): So not loose track of addend for relocs against
+	weak symbols.
+
+2007-05-14  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (md_parse_option): Fix parsing of -O option.
+
+2007-05-14  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (data_op2, validate_immediate): Fix bug for
+	addri, addri.c, subi, and subi.c when immediate number is hex.
+	(score_insns): Remove subis and subis.c.
+	(do_sub_rdi16): Delete.
+	
+2007-05-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.c (md_pseudo_table): Add int, long, quad.  Call
+	spu_cons for word.
+	(md_assemble): Tidy use of insn.flag.
+	(get_imm): Likewise.  Handle uppercase input too.
+	(spu_cons): New function.
+	* config/tc-spu.h (tc_fix_adjustable): Don't adjust SPU_PPU relocs.
+	(TC_FORCE_RELOCATION): Don't resolve them either.
+
+2007-05-05  Mark Shinwell  <shinwell@codesourcery.com>
+ 
+	* config/tc-arm.c (md_apply_fix): Generate more accurate
+	diagnostic when 8-bit immediate range is exceeded for
+	BFD_RELOC_ARM_OFFSET_IMM8.
+
+2007-05-04  Alan Modra  <amodra@bigpond.net.au>
+
+	PR gas/4460
+	* config/tc-i386.c (lex_got): Don't replace the reloc token with
+	a space if we already have a space.
+
+2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Don't explicitly check
+	suffix for crc32 in Intel mode.
+	(process_suffix): Issue an error for crc32 if the operand size
+	is ambiguous.
+
+2007-05-03  Vincent Riviere  <vincent.riviere@freesbee.fr>
+	    Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3041
+	* config/tc-m68k.c (relaxable_symbol): Do not relax weak symbols.
+	(tc_gen_reloc): Adjust the addend of relocs against weak symbols.
+	(md_apply_fix): Put zero values into the frags referencing weak
+	symbols.
+
+2007-05-02  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 4448
+	* config/tc-ppc.c (ppc_insert_operand): Don't increase min for
+	PPC_OPERAND_PLUS1.
+
+2007-05-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Check suffix for crc32 in
+	Intel mdoe.
+	(process_suffix): Default the suffix of 8bit crc32 to
+	BYTE_MNEM_SUFFIX.
+	(check_byte_reg): Skip check for 8bit crc32.
+
+2007-04-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_assemble): Use register_prefix in
+	error/warning message.
+	(check_byte_reg): Likewise.
+	(check_long_reg): Likewise.
+	(check_qword_reg): Likewise.
+	(check_word_reg): Likewise.
+	(process_operands): Likewise.
+
+2007-04-30  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 4436
+	* config/tc-ppc.c (ppc_insert_operand): Disable range check if
+	min > max.
+
+2007-04-28  Thiemo Seufer  <ths@networkno.de>
+
+	* config/tc-mips.c: Fix comment.
+
+2007-04-26  Anatoly Sokolov <aesok@post.ru>
+
+	* config/tc-avr.c (mcu_types): Add support for atmega8hva and
+	atmega16hva devices. Move at90usb82 device to 'avr5' architecture.
+	* doc/c-avr.texi: Document new devices.
+
+2007-04-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (mcf54455_ctrl): New.
+	(HAVE_LONG_DISP, HAVE_LONG_CALL, HAVE_LONG_COND): New.
+	(m68k_archs): Add isac.
+	(m68k_cpus): Add 54455 family.
+	(m68k_ip): Split Bg into Bb, Bs, Bg.
+	(m68k_elf_final_processing): Add ISA_C.
+	* doc/c-m68k.texi (M680x0 Options): Add isac.
 
-	* frags.c (frag_offset_fixed_p): Reinitialise offset before
-	second scan.
+2007-04-22  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-05  Richard Sandiford  <richard@codesourcery.com>
-	    Daniel Jacobowitz  <dan@codesourcery.com>
+	* read.c (read_a_source_file): Skip multiple spaces to
+	cover hack in mmix md_start_line_hook which overwrites a
+	colon with a space.  Delete sermon and needless assertion.
 
-	* config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
-	(GOTT_BASE, GOTT_INDEX): New.
-	(tc_gen_reloc): Don't alter relocations against GOTT_BASE and
-	GOTT_INDEX when generating VxWorks PIC.
-	* configure.tgt (sparc*-*-vxworks*): Remove this special case;
-	use the generic *-*-vxworks* stanza instead.
+2007-04-21  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-04  Alan Modra  <amodra@bigpond.net.au>
+	* config/atof-vax.c (atof_vax_sizeof): Change return type to unsigned.
+	(md_atof): Make number_of_chars unsigned.  Revert last change.
+	* config/tc-or32.c (md_apply_fix): Delete bogus assertions.
+	* config/tc-sh.c (sh_optimize_expr): Only define for OBJ_ELF.
+	* config/tc-sh.h (md_optimize_expr): Likewise.
+	* config/tc-sh64.c (shmedia_md_pcrel_from_section): Delete bogus
+	assertion.
+	* config/tc-xtensa.c (convert_frag_immed_finish_loop): Likewise.
 
-	PR 997
-	* frags.c (frag_offset_fixed_p): New function.
-	* frags.h (frag_offset_fixed_p): Declare.
-	* expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
-	(resolve_expression): Likewise.
+2007-04-21  Nick Clifton  <nickc@redhat.com>
 
-2006-04-03  Sterling Augustine  <sterling@tensilica.com>
+	* config/atof-vax.c (md_atof): Fix comparison inside know().
 
-	* config/tc-xtensa.c (init_op_placement_info_table): Check for formats
-	of the same length but different numbers of slots.
+	* config/tc-ia64.c (emit_one_bundle): Fix typo.
 
-2006-03-30  Andreas Schwab  <schwab@suse.de>
+2007-04-21  Alan Modra  <amodra@bigpond.net.au>
 
-	* configure.in: Fix help string for --enable-targets option.
+	* expr.c (expr): Assert on rankarg, not rank which can be unsigned.
+	* read.c (read_a_source_file): Remove buffer_limit[-1] assertion.
+	Don't skip over NUL char.
+	(pseudo_set): Set X_op for registers to O_register.
+	* symbols.c (symbol_clone): Remove assertion that sym is defined.
+	(resolve_symbol_value): Resolve O_register symbols.
+	* config/tc-i386.c (parse_real_register): Don't use i386_float_regtab.
+	Instead find st(0) by hash lookup.
+	* config/tc-ppc.c (ppc_macro): Warning fix.
+
+	* as.h (ENABLE_CHECKING): Default define to 0.
+	(know): Assert if ENABLE_CHECKING.
+	(struct relax_type): Remove superfluous declaration.
+	* configure.in (--enable-checking): New.
 	* configure: Regenerate.
+	* config.in: Regenerate.
+	* config/tc-ppc.c (ppc_setup_opcodes): Do checks when ENABLE_CHECKING.
+	Check for duplicate powerpc_operands entries.
+
+2007-04-20  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (mcf5253_ctrl): New.
+	(mcf52223_ctrl): New.
+	(m68k_cpus): Add 5253, 52221, 52223.
+
+	* config/m68k-parse.h (RAMBAR_ALT): New.
+	* config/tc-m68k.c (mcf5206_ctrl, mcf5307_ctrl): New.
+	(mcf_ctrl, mcf5208_ctrl, mcf5210a_ctrl, mcf5213_ctrl, mcf52235_ctrl,
+	mcf5225_ctrl, mcf5235_ctrl, mcf5271_ctrl, mcf5275_ctrl,
+	mcf5282_ctrl, mcf5329_ctrl, mcf5373_ctrl, mcfv4e_ctrl,
+	mcf5475_ctrl, mcf5485_ctrl): Add RAMBAR synonym for
+	RAMBAR1.
+	(mcf5272_ctrl): Add RAMBAR0, replace add RAMBAR with RAMBAR_ALT.
+	(m68k_cpus): Adjust 5206, 5206e & 5307 entries.
+	(m68k_ip) <Case J>: Detect when RAMBAR_ALT should be used.  Add it
+	to control register mapping.
+
+2007-04-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* messages.c (as_internal_value_out_of_range): Fix typo in
+	error message.  Return after printing domain error.
+	* config/tc-ppc.c (ppc_insert_operand): Preserve low zero bits
+	in max when shifting right.
+
+2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 
-2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
-
-	* gas/config/tc-m68k.c (find_cf_chip): Merge into ...
-	(m68k_ip): ... here.  Use for all chips.  Protect against buffer
-	overrun and avoid excessive copying.
-
-	* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
-	m68020_control_regs, m68040_control_regs, m68060_control_regs,
-	mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
-	mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
-	mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
-	(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
-	mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl, 
-	mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
-	mcf5282_ctrl, mcfv4e_ctrl): ... these.
-	(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
-	(struct m68k_cpu): Change chip field to control_regs.
-	(current_chip): Remove.
-	(control_regs): New.
-	(m68k_archs, m68k_extensions): Adjust.
-	(m68k_cpus): Reorder to be in cpu number order.  Adjust.
-	(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
-	(find_cf_chip): Reimplement for new organization of cpu table.
-	(select_control_regs): Remove.
-	(mri_chip): Adjust.
-	(struct save_opts): Save control regs, not chip.
-	(s_save, s_restore): Adjust.
-	(m68k_lookup_cpu): Give deprecated warning when necessary.
-	(m68k_init_arch): Adjust.
-	(md_show_usage): Adjust for new cpu table organization.
-
-2006-03-25  Bernd Schmidt  <bernd.schmidt@analog.com>
-
-	* config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
-	* config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
-	* config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
-	"elf/bfin.h".
-	(GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
-	(any_gotrel): New rule.
-	(got): Use it, and create Expr_Node_GOT_Reloc nodes.
-	* config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
-	"elf/bfin.h".
-	(DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
-	(bfin_pic_ptr): New function.
-	(md_pseudo_table): Add it for ".picptr".
-	(OPTION_FDPIC): New macro.
-	(md_longopts): Add -mfdpic.
-	(md_parse_option): Handle it.
-	(md_begin): Set BFD flags.
-	(md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
-	(bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
-	us for GOT relocs.
-	* Makefile.am (bfin-parse.o): Update dependencies.
-	(DEPTC_bfin_elf): Likewise.
+	* messages.c (as_internal_value_out_of_range): Extend to report
+	errors for values with invalid low bits set.
+	* config/tc-ppc.c (ppc_setup_opcodes): Check powerpc_operands bitm
+	fields.  Check that operands and opcode fields are disjoint.
+	(ppc_insert_operand): Check operands using mask rather than bit
+	count.   Check low bits too.  Handle PPC_OPERAND_PLUS1.  Adjust
+	insertion code.
+	(md_apply_fix): Adjust for struct powerpc_operand change.
+
+2007-04-19  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_assemble): Only allow 16-bit instructions on
+	Thumb-1.  Add sanity check for bogus relaxations.
+
+2007-04-19  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Allow rsb and rsbs on Thumb-1.
+
+2007-04-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
 	* Makefile.in: Regenerate.
 
-2006-03-25  Richard Sandiford  <richard@codesourcery.com>
+2007-04-19  Nathan Froyd <froydnj@codesourcery.com>
 
-	* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
-	mcfemac instead of mcfmac.
+	* doc/c-ppc.texi (PowerPC-Opts): Document -me500, -me500x2, -mspe.
 
-2006-03-22  Richard Sandiford  <richard@codesourcery.com>
-	    Daniel Jacobowitz  <dan@codesourcery.com>
-	    Phil Edwards  <phil@codesourcery.com>
-	    Zack Weinberg  <zack@codesourcery.com>
-	    Mark Mitchell  <mark@codesourcery.com>
-	    Nathan Sidwell  <nathan@codesourcery.com>
+2007-04-18  H.J. Lu <hongjiu.lu@intel.com>
+
+	* doc/c-i386.texi; Document .ssse3, .sse4.1, .sse4.2 and .sse4.
+
+2007-04-18  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Add .sse4.2 and .sse4.
+	(match_template): Handle operand size for crc32 in SSE4.2.
+	(process_suffix): Handle operand type for crc32 in SSE4.2.
+	(output_insn): Support SSE4.2.
+
+2007-04-18  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Add .sse4.1.
+	(process_operands): Adjust implicit operand for blendvpd,
+	blendvps and pblendvb in SSE4.1.
+	(output_insn): Support SSE4.1.
+
+2007-04-18  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_t_rsb): Use 16-bit encoding when possible.
+
+2007-04-16  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* config/tc-sh.c (sh_handle_align):  Call as_bad_where instead
+	of as_warn_where for misaligned data.
+
+2007-04-15  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* config/tc-sh.c (align_test_frag_offset_fixed_p): Handle
+	rs_fill frags.
+
+2007-04-14  Steve Ellcey  <sje@cup.hp.com>
+
+	* Makefile.am: Add ACLOCAL_AMFLAGS.
+	* Makefile.in: Regenerate.
 
-	* config/tc-mips.c (mips_target_format): Handle vxworks targets.
-	(md_begin): Complain about -G being used for PIC.  Don't change
-	the text, data and bss alignments on VxWorks.
-	(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
-	generating VxWorks PIC.
-	(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
-	(macro): Likewise, but do not treat la $25 specially for
-	VxWorks PIC, and do not handle jal.
-	(OPTION_MVXWORKS_PIC): New macro.
-	(md_longopts): Add -mvxworks-pic.
-	(md_parse_option): Don't complain about using PIC and -G together here.
-	Handle OPTION_MVXWORKS_PIC.
-	(md_estimate_size_before_relax): Always use the first relaxation
-	sequence on VxWorks.
-	* config/tc-mips.h (VXWORKS_PIC): New.
+2007-04-14  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 
-2006-03-21  Paul Brook  <paul@codesourcery.com>
+	* config/tc-sh.c (align_test_frag_offset_fixed_p): New.
+	(sh_optimize_expr): Likewise.
+	* config/tc-sh.h (md_optimize_expr): Define.
+	(sh_optimize_expr): Prototype.
 
-	* config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
+2007-04-06  Matt Thomas  <matt@netbsd.org>
 
-2006-03-21  Sterling Augustine  <sterling@tensilica.com>
+	* config/tc-vax.c (vax_cons): Added to support %pcrel{8,16,32}(exp)
+	to emit pcrel relocations by DWARF2 in non-code sections.  Borrowed
+	heavily from tc-sparc.c.  (vax_cons_fix_new): Likewise.
 
-	* config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
-	(xtensa_setup_hw_workarounds): Set this new flag for older hardware.
-	(get_loop_align_size): New.
-	(xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
-	(xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
-	(get_text_align_power): Rewrite to handle inputs in the range 2-8.
-	(get_noop_aligned_address): Use get_loop_align_size.
-	(get_aligned_diff): Likewise.
+2007-04-04  Kazu Hirata  <kazu@codesourcery.com>
 
-2006-03-21  Paul Brook  <paul@codesourcery.com>
+	* config/tc-m68k.c (HAVE_LONG_BRANCH): Add fido_a.
 
-	* config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
+2007-04-04  Paul Brook  <paul@codesourcery.com>
 
-2006-03-20  Paul Brook  <paul@codesourcery.com>
+	* config/tc-arm.c (do_neon_ext): Enforce immediate range.
+	(insns): Use I15 for vext.
 
-	* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
-	(do_t_branch): Encode branches inside IT blocks as unconditional.
-	(do_t_cps): New function.
-	(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
-	do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
-	(opcode_lookup): Allow conditional suffixes on all instructions in
-	Thumb mode.
-	(md_assemble): Advance condexec state before checking for errors.
-	(insns): Use do_t_cps.
+2007-04-04  Paul Brook  <paul@codesourcery.com>
 
-2006-03-20  Paul Brook  <paul@codesourcery.com>
+	* configure.tgt: Loosen checks for arm uclinux eabi targets.
 
-	* config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
-	outputting the insn.
+2007-04-02  Sterling Augustine  <sterling@tensilica.com>
 
-2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+	* config/tc-xtensa.c (xtensa_flush_pending_output): Check
+	outputting_stabs_line_debug.
 
-	* config/tc-vax.c: Update copyright year.
-	* config/tc-vax.h: Likewise.
+2007-03-26  Anatoly Sokolov <aesok@post.ru>
 
-2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+	* config/tc-avr.c (mcu_types): Add support for at90pwm1, at90usb82,
+	at90usb162, atmega325p, atmega329p, atmega3250p and atmega3290p
+	devices.
+	* doc/c-avr.texi: Document new devices.
 
-	* config/tc-vax.c (md_chars_to_number): Used only locally, so
-	make it static.
-	* config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
+2007-04-02  Richard Sandiford  <richard@codesourcery.com>
 
-2006-03-17  Paul Brook  <paul@codesourcery.com>
+	* doc/as.texinfo: Add -mvxworks-pic to the list of MIPS options.
+	* doc/c-mips.texi (-KPIC, -mvxworks-pic): Document.
+	* config/tc-mips.c (md_show_usage): Mention -mvxworks-pic.
 
-	* config/tc-arm.c (insns): Add ldm and stm.
+2007-03-30  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
 
-2006-03-17  Ben Elliston  <bje@au.ibm.com>
+	* config/tc-xtensa.c (xtensa_move_labels): Remove loops_ok argument.
+	Do not check is_loop_target flag.
+	(xtensa_frob_label): Adjust calls to xtensa_move_labels.
+	(xg_assemble_vliw_tokens): Likewise.  Also avoid calling
+	xtensa_move_labels for alignment of loop opcodes.
+	
+2007-03-30  H.J. Lu  <hongjiu.lu@intel.com>
 
-	PR gas/2446
-	* doc/as.texinfo (Ident): Document this directive more thoroughly.
+	* config/tc-i386.c (process_suffix): Reindent a bit.
 
-2006-03-16  Paul Brook  <paul@codesourcery.com>
+2007-03-30  Paul Brook  <paul@codesourcery.com>
 
-	* config/tc-arm.c (insns): Add "svc".
+	* config/tc-arm.c (encode_thumb2_ldmstm): New function.
+	(do_t_ldmstm): Generate 16-bit push/pop.  Use encode_thumb2_ldmstm.
+	(do_t_push_pop):  Use encode_thumb2_ldmstm.
 
-2006-03-13  Bob Wilson  <bob.wilson@acm.org>
+2007-03-29  DJ Delorie  <dj@redhat.com>
 
-	* config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
-	flag and avoid double underscore prefixes.
+	* config/tc-m32c.c (rl_for, relaxable): Protect argument.
+	(md_relax_table): Add entries for ADJNZ macros.
+	(M32C_Macros): Add ADJNZ macros.
+	(subtype_mappings): Add entries for ADJNZ macros.
+	(insn_to_subtype): Check for adjnz and sbjnz insns.
+	(md_estimate_size_before_relax): Pass insn to insn_to_subtype.
+	(md_convert_frag): Convert adjnz and sbjnz.
 
-2006-03-10  Paul Brook  <paul@codesourcery.com>
+2007-03-29  Nick Clifton  <nickc@redhat.com>
 
-	* config/tc-arm.c (md_begin): Handle EABIv5.
-	(arm_eabis): Add EF_ARM_EABI_VER5.
-	* doc/c-arm.texi: Document -meabi=5.
+	* itbl-ops.c (itbl_entry): Remove unnecessary and excessively long
+	initialization.
+	* itbl-ops.h (enum e_processor): Initialise the e_nprocs field
+	using ITBL_NUMBER_OF_PROCESSORS.
+	* itbl-parse.y (yyerror): Remove use of redundant macro PARAMS.
 
-2006-03-10  Ben Elliston  <bje@au.ibm.com>
+2007-03-28  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* app.c (do_scrub_chars): Simplify string handling.
+	* config/tc-i386.c (build_modrm_byte): For instructions with 2
+	register operands, encode destination in i.rm.regmem if its
+	RegMem bit is set.
 
-2006-03-07  Richard Sandiford  <richard@codesourcery.com>
-	    Daniel Jacobowitz  <dan@codesourcery.com>
-	    Zack Weinberg  <zack@codesourcery.com>
-	    Nathan Sidwell  <nathan@codesourcery.com>
-	    Paul Brook  <paul@codesourcery.com>
-	    Ricardo Anguiano  <anguiano@codesourcery.com>
+2007-03-28  Richard Sandiford  <richard@codesourcery.com>
 	    Phil Edwards  <phil@codesourcery.com>
 
-	* config/tc-arm.c (md_apply_fix): Install a value of zero into a
-	BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
-	R_ARM_ABS12 reloc.
-	(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
-	relocs, but adjust by md_pcrel_from_section.  Create R_ARM_ABS12
-	relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
-
-2006-03-06  Bob Wilson  <bob.wilson@acm.org>
-
-	* config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
-	even when using the text-section-literals option.
-
-2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
-
-	* config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
-	and cf.
-	(m68k_ip): <case 'J'> Check we have some control regs.
-	(md_parse_option): Allow raw arch switch.
-	(m68k_init_arch): Better detection of arch/cpu mismatch.  Detect
-	whether 68881 or cfloat was meant by -mfloat.
-	(md_show_usage): Adjust extension display.
-	(m68k_elf_final_processing): Adjust.
-
-2006-03-03  Bjoern Haase  <bjoern.m.haase@web.de>
-
-	* config/tc-avr.c (avr_mod_hash_value): New function.
-	(md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
-	BFD_RELOC_MS8_LDI for hlo8() and hhi8() 
-	(md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
-	instead of int avr_ldi_expression: use avr_mod_hash_value instead
-	of (int).
-	(tc_gen_reloc): Handle substractions of symbols, if possible do
-	fixups, abort otherwise.	
-	* config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
-	tc_fix_adjustable): Define.
+	* doc/as.texinfo: Put the contents after the title page rather
+	than at the end of the document.
+
+2007-03-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* NEWS: Mention ".reloc".
+
+2007-03-26  Sterling Augustine  <sterling@tensilica.com>
 	
-2006-03-02  James E Wilson  <wilson@specifix.com>
+	* config/tc-xtensa.c (xg_translate_idioms): Allow assembly idioms
+	in FLIX instructions.
+	
+2007-03-26  Julian Brown  <julian@codesourcery.com>
 
-	* config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
-	change the template, then clear md.slot[curr].end_of_insn_group.
+	* config/tc-arm.c (arm_it): Add immisfloat field.
+	(parse_qfloat_immediate): Disallow integer syntax for floating-point
+	immediates. Fix hex immediates, handle 0.0 and -0.0 specially.
+	(parse_neon_mov): Set immisfloat bit for operand if it parsed as a
+	float.
+	(neon_cmode_for_move_imm): Reject non-float immediates for float
+	operands.
+	(neon_move_immediate): Pass immisfloat bit to neon_cmode_for_move_imm.
 
-2006-02-28  Jan Beulich  <jbeulich@novell.com>
+2007-03-26  Julian Brown  <julian@codesourcery.com>
 
-	* macro.c (get_any_string): Don't insert quotes for <>-quoted input.
+	* doc/c-arm.texi: Add documentation for .dn/.qn directives.
 
-2006-02-28  Jan Beulich  <jbeulich@novell.com>
+2007-03-26  Alan Modra  <amodra@bigpond.net.au>
 
-	PR/1070
-	* macro.c (getstring): Don't treat parentheses special anymore.
-	(get_any_string): Don't consider '(' and ')' as quoting anymore.
-	Special-case '(', ')', '[', and ']' when dealing with non-quoting
-	characters.
+	* doc/as.texinfo (Reloc): Document.
+	* read.c (potable): Add "reloc".
+	(s_reloc): New function.
+	* write.c (reloc_list): New global var.
+	(resolve_reloc_expr_symbols): New function.
+	(write_object_file): Call it.
+	(write_relocs): Process reloc_list.
+	* write.h (struct reloc_list): New.
+	(reloc_list): Declare.
 
-2006-02-28  Mat <mat@csail.mit.edu>
+2007-03-24  Paul Brook  <paul@codesourcery.com>
 
-	* dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
+	* config/tc-arm.c (do_t_ldmstm): Error on Thumb-2 addressing modes.
 
-2006-02-27  Jakub Jelinek  <jakub@redhat.com>
+2007-03-24  Paul Brook  <paul@codesourcery.com>
+	Mark Shinwell  <shinwell@codesourcery.com>
 
-	* dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
-	field.
-	(CFI_signal_frame): Define.
-	(cfi_pseudo_table): Add .cfi_signal_frame.
-	(dot_cfi): Handle CFI_signal_frame.
-	(output_cie): Handle cie->signal_frame.
-	(select_cie_for_fde): Don't share CIE if signal_frame flag is
-	different.  Copy signal_frame from FDE to newly created CIE.
-	* doc/as.texinfo: Document .cfi_signal_frame.
+	* config/tc-arm.c (operand_parse_code): Add OP_oRRw.
+	(parse_operands): Don't expect comma if first operand missing.
+	Handle OP_oRRw.
+	(do_srs): Encode register number, checking it is r13.  Update comment.
+	(insns): Update SRS entries to take a register.
 
-2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
+2007-03-23  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* doc/Makefile.am: Add html target.
-	* doc/Makefile.in: Regenerate.
-	* po/Make-in: Add html target.
-
-2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
-
-	* config/tc-i386.c (output_insn): Support Intel Merom New
-	Instructions.
-
-	* config/tc-i386.h (CpuMNI): New.
-	(CpuUnknownFlags): Add CpuMNI.
-
-2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
-
-	* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
-	(hpriv_reg_table): New table for hyperprivileged registers.
-	(sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
-	register encoding.
-
-2006-02-24  DJ Delorie  <dj@redhat.com>
-
-	* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
-	(tc_gen_reloc): Don't define.
-	* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
-	(OPTION_LINKRELAX): New.
-	(md_longopts): Add it.
-	(m32c_relax): New.
-	(md_parse_options): Set it.
-	(md_assemble): Emit relaxation relocs as needed.
-	(md_convert_frag): Emit relaxation relocs as needed.
-	(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
-	(m32c_apply_fix): New.
-	(tc_gen_reloc): New.
-	(m32c_force_relocation): Force out jump relocs when relaxing.
-	(m32c_fix_adjustable): Return false if relaxing.
-
-2006-02-24  Paul Brook  <paul@codesourcery.com>
-
-	* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
-	arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
-	(struct asm_barrier_opt): Define.
-	(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
-	(parse_psr): Accept V7M psr names.
-	(parse_barrier): New function.
-	(enum operand_parse_code): Add OP_oBARRIER.
-	(parse_operands): Implement OP_oBARRIER.
-	(do_barrier): New function.
-	(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
-	(do_t_cpsi): Add V7M restrictions.
-	(do_t_mrs, do_t_msr): Validate V7M variants.
-	(md_assemble): Check for NULL variants.
-	(v7m_psrs, barrier_opt_names): New tables.
-	(insns): Add V7 instructions.  Mark V6 instructions absent from V7M.
-	(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
-	(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
-	(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
-	(struct cpu_arch_ver_table): Define.
-	(cpu_arch_ver): New.
-	(aeabi_set_public_attributes): Use cpu_arch_ver.  Set
-	Tag_CPU_arch_profile.
-	* doc/c-arm.texi: Document new cpu and arch options.
-
-2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
-
-2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* config/tc-ia64.c: Update copyright years.
-
-2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* config/tc-ia64.c (specify_resource): Add the rule 17 from
-	SDM 2.2.
-
-2005-02-22  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (do_pld): Remove incorrect write to
-	inst.instruction.
-	(encode_thumb32_addr_mode): Use correct operand.
-
-2006-02-21  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
-
-2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
-            Anil Paranjape   <anilp1@kpitcummins.com>
-            Shilin Shakti    <shilins@kpitcummins.com>
-
-	* Makefile.am: Add xc16x related entry.
+	* config/tc-i386.c (md_begin): Allow '.' in mnemonic.
+
+2007-03-23  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Turn CBZ instructions that
+	attempt to jump to the next instruction into NOPs.
+
+2007-03-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.c: Don't include opcode/spu.h.
+	(md_assemble): Set tc_fix_data.insn_tag and arg_format.
+	(md_apply_fix): Adjust.
+	* config/tc-spu.h: Include opcode/spu.h.
+	(struct tc_fix_info): New.
+	(TC_FIX_TYPE, TC_INIT_FIX_DATA): Adjust.
+	(TC_FORCE_RELOCATION): Define.
+
+2007-03-22  Joseph Myers  <joseph@codesourcery.com>
+
+	* doc/as.texinfo: Include VERSION_PACKAGE when reporting version.
+
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (process_suffix): Check 0x90 instead of
+	xchg for xchg %rax,%rax.
+
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Replace REX_MODE64, REX_EXTX, REX_EXTY
+	and REX_EXTZ with REX_W, REX_R, REX_X and REX_B respectively.
+
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/4218
+	* config/tc-i386.c (match_template): Properly handle 64bit mode
+	"xchg %eax, %eax".
+
+2007-03-21  Anton Ertl  <anton@mips.complang.tuw>
+
+	PR gas/4124
+	* config/tc-alpha.c (emit_ustX): Fix ustq code generation.
+
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am: Run dep-am.
+	* Makefile.in: Regenerated.
+
+	* config/tc-i386.c: Don't include "opcodes/i386-opc.h".
+
+	* config/tc-i386.h: Include "opcodes/i386-opc.h".
+	(NOP_OPCODE): Removed.
+	(template): Likewise.
+
+2007-03-21  Andreas Schwab  <schwab@suse.de>
+
+	* config/tc-i386.h (NOP_OPCODE): Restore.
+
+2007-03-18  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (do_mul): Don't warn about overlapping
+	Rd and Rm operands when assembling for v6 or above.
+	Correctly capitalize register names in the messages.
+	(do_mlas): Likewise.  Delete spurious blank line.
+
+2007-03-16  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-m68k.c (m68k_cpus): Add an entry for fidoa.
+
+2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_begin): Use i386_regtab_size to scan 
+	i386_regtab.
+	(parse_register): Use i386_regtab_size instead of ARRAY_SIZE
+	on i386_regtab.
+
+2007-03-15  Alexandre Oliva  <aoliva@redhat.com>
+
+	PR gas/4184
+	* app.c (do_scrub_chars): PUT after setting states.
+
+2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerated.
+
+	* config/tc-i386.c: Include "opcodes/i386-opc.h" instead of
+	"opcode/i386.h".
+	(md_begin): Check reg_name != NULL for the last entry in
+	i386_regtab.
+
+	* config/tc-i386.h: Move many entries to opcode/i386.h and
+	opcodes/i386-opc.h.
+
+	* configure.in (need_opcodes): Set true for i386.
+	* configure: Regenerated.
+
+2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am (REPORT_BUGS_TO): Removed.
+	(INCLUDES): Remove -DREPORT_BUGS_TO.
+	* Makefile.in: Regenerated.
+
+	* configure.in (--with-bugurl): Removed.
+	* configure: Regenerated.
+
+	* doc/Makefile.am (as_TEXINFOS): Remove gasver.texi.
+	(AM_MAKEINFOFLAGS): Add -I ../../bfd/doc.
+	(TEXI2DVI): Likewise.
+	(gasver.texi): Removed.
+	(MOSTLYCLEANFILES): Remove gasver.texi.
+	(as.1): Don't depend on gasver.texi.
+	* doc/Makefile.in: Regenerated.
+
+	* doc/as.texi: Include bfdver.texi instead of gasver.texi.
+
+2007-03-14  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-arm.c (arm_copy_symbol_attributes): New.
+	* config/tc-arm.h (arm_copy_symbol_attributes): Declare.
+	(TC_COPY_SYMBOL_ATTRIBUTES): Define.
+	* gas/symbols.c (copy_symbol_attributes): Use
+	TC_COPY_SYMBOL_ATTRIBUTES.
+
+2007-03-14  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (T16_32_TAB): Fix dec_sp encoding.
+
+2007-03-14  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 4029
+	* write.c (relax_segment): Insert extra alignment padding
+	to break infinite relax loop when given impossible
+	gcc_except_table assembly.
+
+2007-03-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_assemble): Use Opcode_XXX instead of XXX
+	on i.tm.base_opcode.
+	(match_template): Likewise.
+	(process_operands): Use ~0x3 mask to match MOV_AX_DISP32.
+
+	* config/tc-i386.h (Opcode_D): New.
+	(Opcode_FloatR): Likewise.
+	(Opcode_FloatD): Likewise.
+	(D): Redefined.
+	(W): Likewise.
+	(FloatMF): Likewise.
+	(FloatR): Likewise.
+	(FloatD): Likewise.
+
+2007-03-09  Alexandre Oliva  <aoliva@redhat.com>
+
+	* app.c (do_scrub_chars): Recognize comments after # line "file".
+	* read.c (get_linefile_number): New.
+	(s_app_line): Accept ill-formed .linefile lines as comments.
+
+2007-03-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-i386.h (WORKING_DOT_WORD): Define.
+
+2007-03-09  Alexandre Oliva  <aoliva@redhat.com>
+
+	* app.c (do_scrub_chars): Turn #<line>"file"flags into .linefile.
+	* as.h (new_logical_line_flags): New.
+	* input-scrub.c (new_logical_line): Turned into wrapper for...
+	(new_logical_line_flags): this.  Handle flags.
+	* read.c (potable): Add linefile.  Adjust appline argument.
+	(s_app_file): Fake .appfiles no more.
+	(s_app_line): For .linefile, accept file name and flags.
+
+2007-03-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* symbols.c (symbol_relc_make_sym): Comment typo fixes.
+
+2007-03-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
 	* Makefile.in: Regenerate.
-	* configure.in: Added xc16x related entry.
-	* configure: Regenerate.
-	* config/tc-xc16x.h: New file
-	* config/tc-xc16x.c: New file
-	* doc/c-xc16x.texi: New file for xc16x
-	* doc/all.texi: Entry for xc16x
-	* doc/Makefile.texi: Added c-xc16x.texi 
-	* NEWS: Announce the support for the new target.
+	* po/POTFILES.in: Regenerate.
 
-2006-02-16  Nick Hudson  <nick.hudson@dsl.pipex.com>
+2007-03-07  Joseph Myers  <joseph@codesourcery.com>
 
-	* configure.tgt: set emulation for mips-*-netbsd*
+	* configure.in (REPORT_BUGS_TEXI): Define to Texinfo version of
+	bug-reporting URL.
+	* doc/Makefile.am (gasver.texi): Define BUGURL.
+	* doc/as.texinfo: Use BUGURL.
+	* Makefile.in, configure, doc/Makefile.in: Regenerate.
 
-2006-02-14  Jakub Jelinek  <jakub@redhat.com>
+2007-03-06  Andreas Krebbel  <krebbel1@de.ibm.com>
 
-	* config.in: Rebuilt.
+	* config/tc-s390.c (md_parse_option): z9-ec option added.
 
-2006-02-13  Bob Wilson  <bob.wilson@acm.org>
+2007-03-02  Paul Brook  <paul@codesourcery.com>
 
-	* config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
-	from 1, not 0, in error messages.
-	(md_assemble): Simplify special-case check for ENTRY instructions.
-	(tinsn_has_invalid_symbolic_operands): Do not include opcode and
-	operand in error message.
+	* config/tc-arm.c (relax_immediate): Always return positive values.
+	(relaxed_symbol_addr): New function.
+	(relax_adr, relax_branch): Use it.
+	(arm_relax_frag): Pass strect argument.  Adjust infinite loop check.
 
-2006-02-13  Joseph S. Myers  <joseph@codesourcery.com>
+2007-03-01  Joseph Myers  <joseph@codesourcery.com>
 
-	* configure.tgt (arm-*-linux-gnueabi*): Change to
-	arm-*-linux-*eabi*.
+	* as.c (parse_args): Update copyright date.
 
-2006-02-10  Nick Clifton  <nickc@redhat.com>
+2007-02-28  Nathan Sidwell  <nathan@codesourcery.com>
 
-	* config/tc-crx.c (check_range): Ensure that the sign bit of a
-	32-bit value is propagated into the upper bits of a 64-bit long.
+	* configure.tgt (sh-*-uclinux, sh[12]-*-uclinux): Specify as elf.
 
-	* config/tc-arc.c (init_opcode_tables): Fix cast.
-	(arc_extoper, md_operand): Likewise.
+2007-02-28  Nick Clifton  <nickc@redhat.com>
 
-2006-02-09  David Heine  <dlheine@tensilica.com>
+	PR gas/3797
+	* config/tc-d10v.c (do_assemble): Do not generate error messages,
+	just return -1 whenever a problem is encountered.
+	(md_assemble): If do_assemble returns -1 generate a non-fatal
+	error message and return.
 
-	* config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
-	each relaxation step.
+	PR gas/2623
+	* config/tc-msp430.c (line_separator_char): Change to '{'.
 
-2006-02-09  Eric Botcazou  <ebotcazou@libertysurf.fr>
-	
-	* configure.in (CHECK_DECLS): Add vsnprintf.
+2007-02-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-m68hc11.c (fixup24): Correct fixup size.
+	(build_jump_insn): Likewise.
+	(build_insn): Likewise.
+	(s_m68hc11_relax): Likewise.
+
+2007-02-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-elf.c (elf_frob_file): frag_wane any new frags.
+
+2007-02-25  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (do_vfp_nsyn_pop): Use fldmias/fldmiad.
+
+2007-02-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-mn10300.c (md_convert_frag): Correct fixup size.
+	(md_assemble): Likewise.
+
+2007-02-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.c (size_seg): Always clear SEC_RELOC here.
+	(install_reloc): New function, extracted from..
+	(write_relocs): ..here.  Combine RELOC_EXPANSION_POSSIBLE code
+	with !RELOC_EXPANSION_POSSIBLE code.  Don't add fr_offset when
+	testing frag size.  Set SEC_RELOC here.
+
+2007-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 4082
+	* config/tc-avr.h (TC_FX_SIZE_SLACK): Define.
+
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+
+	* doc/c-mips.texi: Document 74kc, 74kf, 74kx.
+
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): Add 74K configurations.
+
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+            Chao-Ying Fu  <fu@mips.com>
+
+	* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
+	ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
+	(macro_build): Add case '2'.
+	(macro): Expand M_BALIGN to nop, packrl.ph or balign.
+	(validate_mips_insn): Add support for balign instruction.
+	(mips_ip): Handle DSP R2 instructions. Support balign instruction.
+	(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
+	md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
+	command line options.
+	(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
+	(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
+	* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
+	.set dspr2, .set nodspr2.
+
+2007-02-20  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (mcf5210a_ctrl, mcf52235_ctrl, mcf5225_ctrl): New.
+	(m68k_cpus): Add 5210a..5211a, 52230..52235 5224..5225.
+
+2007-02-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.c (TC_FX_SIZE_SLACK): Define.
+	(write_relocs): Reinstate check for fixup within frag.
+	* config/tc-bfin.h (TC_FX_SIZE_SLACK): Define.
+	* config/tc-h8300.h (TC_FX_SIZE_SLACK): Define.
+	* config/tc-mmix.h (TC_FX_SIZE_SLACK): Define.
+	* config/tc-sh.h (TC_FX_SIZE_SLACK): Define.
+	* config/tc-xstormy16.h (TC_FX_SIZE_SLACK): Define.
+
+2007-02-17  Mark Mitchell  <mark@codesourcery.com>
+            Nathan Sidwell  <nathan@codesourcery.com>
+            Vladimir Prus  <vladimir@codesourcery.com
+            Joseph Myers  <joseph@codesourcery.com>
+
+	* configure.in (--with-bugurl): New option.
+	* configure: Regenerate.
+	* dep-in.sed: Remove bin-bugs.h.
+	* Makefile.am (REPORT_BUGS_TO): Define.
+	(INCLUDES): Define REPORT_BUGS_TO.
+	(DEP_INCLUDES): Likewise.
+	($(OBJS)): No longer depend on bin-bugs.h.
+	* Makefile.in: Regenerate.
+	* doc/Makefile.in: Regenerate.
+	* as.c (show_usage): Don't print empty REPORT_BUGS_TO.
+	* as.h: Remove include of bin-bugs.h.
+
+2007-02-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.c: White space fixes.
+	(fixup_segment): Move symbol_mri_common_p adjustments..
+	(write_relocs): ..and symbol_equated_reloc_p adjustments..
+	(adjust_reloc_syms): ..to here.
+
+2007-02-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* subsegs.c (subseg_change, subseg_get): Use xcalloc rather than
+	xmalloc, memset.  Don't bother assigning NULL to known zero mem.
+	(subseg_set_rest): Remove unnecessary cast.
+	* write.c: Include libbfd.h.  Replace PTR with void * throughout.
+	Remove unnecessary forward declarations and casts.
+	(set_symtab): Delete extern bfd_alloc.
+	(fixup_segment): Move.
+
+2007-02-15  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/m68k-parse.h (m68k_register): Add ROMBAR0, ASID.
+	* config/tc-m68k.c (mcfv4e_ctrl): Add ColdFire specific names.
+	(mcf5475_ctrl, mcf5485_ctrl): New.
+	(m68k_cpus): Use mcf5485_ctrl and mcf5485_ctrl for those families.
+	(m68k_ip): Add ASID, MMUBAR, ROMBAR0 handling.
+	(init_table): Add asid, mmubar, adjust rombar0.
+
+2007-02-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-i386.h (Seg2ShortForm, Seg3ShortForm): Delete.
+	* config/tc-i386.c: Wrap overly long lines, whitespace fixes.
+	(process_operands): Move old Seg2ShortForm and Seg3ShortForm
+	code, and test for these insns using a combination of
+	opcode_modifier and operand_types.
+
+2007-02-07  Paul Brook  <paul@codesourcery.com>
+
+	* configure.tgt: Add arm*-*-uclinux-*eabi.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+	    Richard Sandiford  <rsandifo@redhat.com>
+	    DJ Delorie  <dj@redhat.com>
+	    Stan Cox  <scox@redhat.com>
+	    Jim Blandy  <jimb@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    Jim Wilson  <wilson@redhat.com>
+	    Frank Ch. Eigler  <fche@redhat.com>
+	    Graydon Hoare  <graydon@redhat.com>
+	    Ben Elliston  <bje@redhat.com>
+	    John Healy  <jhealy@redhat.com>
+	    Richard Henderson  <rth@redhat.com>
+
+	* Makefile.am (CPU_TYPES): Add mep.
+	(TARGET_CPU_CFILES): Add tc-mep.c.
+	(TARGET_CPU_HFILES): Add tc-mep.h.
+	(DEPTC_mep_elf): New variable.
+	(DEPTC_mep_coff): Likewise.
+	(DEPOBJ_mep_coff, DEPOBJ_mep_elf, DEP_mep_coff, DEP_mep_elf): Likewise.
+	* configure.in: Support mep.
+	* configure.tgt: Likewise.
+	* config/tc-mep.c: New file.
+	* config/obj-elf.c: New file.
+	* config/tc-mep.c: New file.
+	* config/tc-mep.h: New file.
+	* testsuite/gas/mep: New testsuite with content.
+	* Makefile.in: Regenerate.
 	* configure: Regenerate.
-	* messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
-	include/declare here, but...
-	* as.h: Move code detecting VARARGS idiom to the top.
-	(errno.h, stdarg.h, varargs.h, va_list): ...here.
-	(vsnprintf): Declare if not already declared.
-
-2006-02-08  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* as.c (close_output_file): New.
-	(main): Register close_output_file with xatexit before
-	dump_statistics. Don't call output_file_close.
-
-2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
-
-	* config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
-	mcf5329_control_regs): New.
-	(not_current_architecture, selected_arch, selected_cpu): New.
-	(m68k_archs, m68k_extensions): New.
-	(archs): Renamed to ...
-	(m68k_cpus): ... here.  Adjust.
-	(n_arches): Remove.
-	(md_pseudo_table): Add arch and cpu directives.
-	(find_cf_chip, m68k_ip): Adjust table scanning.
-	(no_68851, no_68881): Remove.
-	(md_assemble): Lazily initialize.
-	(select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
-	(md_init_after_args): Move functionality to m68k_init_arch.
-	(mri_chip): Adjust table scanning.
-	(md_parse_option): Reimplement 'm' processing to add -march & -mcpu
-	options with saner parsing.
-	(m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
-	m68k_init_arch): New.
-	(s_m68k_cpu, s_m68k_arch): New.
-	(md_show_usage): Adjust.
-	(m68k_elf_final_processing): Set CF EF flags.
-	* config/tc-m68k.h (m68k_init_after_args): Remove.
-	(tc_init_after_args): Remove.
-	* doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
-	(M68k-Directives): Document .arch and .cpu directives.
-
-2006-02-05  Arnold Metselaar  <arnold.metselaar@planet.nl>
-
-	* config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as 
-	synonyms for equ and defl. 
-	(z80_cons_fix_new): New function.
-	(emit_byte): Disallow relative jumps to absolute locations.
-	(emit_data): Only handle defb, prototype changed, because defb is 
-	now handled as pseudo-op rather than an instruction.
-	(instab): Entries for defb,defw,db,dw moved from here...
-	(md_pseudo_table): ... to here, use generic cons() for defw,dw. 
-	Add entries for def24,def32,d24,d32.
-	(md_assemble): Improved error handling.
-	(md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
-	* config/tc-z80.h (TC_CONS_FIX_NEW): Define.
-	(z80_cons_fix_new): Declare.
-	* doc/c-z80.texi (defb, db): Mention warning on overflow. 
-	(def24,d24,def32,d32): New pseudo-ops.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+
+	* cgen.c (gas_cgen_install_complex_reloc): Removed.
+	(complex_reloc_installation_howto): Removed.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+	    Graydon Hoare  <graydon@redhat.com>
+	    DJ Delorie  <dj@redhat.com>
+	    Catherine Moore  <clm@redhat.com>
+	    Michael Chastain  <chastain@redhat.com>
+	    Frank Ch. Eigler  <fche@redhat.com>
+
+	* symbols.c (use_complex_relocs_for): New, to decide
+	when to use complex relocs. Add signed RELC support.
+	(resolve_symbol_value): Call use_complex_relocs_for. Unconditionally
+	encode expression symbols as mangled complex relocation symbols (when
+	compiled with -DOBJ_COMPLEX_RELOC).
+	(symbol_relc_make_sym,value,expr): New traversal/conversion routines.
+	* cgen.c (gas_cgen_md_apply_fix3):  Only set signed_p if RELC. Call
+	encode_addend with new args. Modify to get start, length from
+	ifield whenever it is set. Also change condition on which
+	self-describing relocs are encoded. Add hook into
+	gas_cgen_encode_addend.
+	(queue_fixup_recursively): Add signed RELC support. Change from masked
+	expr to trunc flag. Restore assignment of sub-field value to
+	temporary in fixups array. Reflect changed meaning of last arg to
+	queue_fixup_recursively.
+	(fixup): Add cgen_maybe_multi_ifield member.
+	(make_right_shifted_expr): New function.
+	(queue_fixup): Change to recursive function that fragments
+	fixups if operand has a multi-ifield.
+	(gas_cgen_parse_operand): Add RELC code to wrap expressions in
+	symbols, call weak_operand_overflow_check, and fragment call
+	queue_fixup with operand fields.
+	(gas_cgen_finish_insn) Modify to manage ifield pointer.
+	(weak_operand_overflow_check): New function to try to select
+	insns correctly.
+	(gas_cgen_encode_addend): New function for relc.
+	(gas_cgen_install_complex_reloc): Likewise.
+	(gas_cgen_tc_gen_reloc): Add hook into gas_cgen_install_complex_reloc.
+	* write.h (struct fix): Add msb_field_p to fx_cgen sub-struct. Add
+	cgen_maybe_multi_ifield field to fx_cgen substructure.
+	* cgen.h (GAS_CGEN_MAX_FIXUPS): Bump from 3 up to 32.
+	* symbols.h (symbol_relc_make_sym,value,expr): New prototypes.
+	
+2007-02-03  DJ Delorie  <dj@delorie.com>
+
+	* config/tc-m32c.c (m32c_cons_fix_new): New.  Added to support 3
+	byte relocs.
+	* config/tc-m32c.h (TC_CONS_FIX_NEW): Define.
+	(m32c_cons_fix_new): Prototype.
+
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+	
+	* config/tc-xtensa.c (xg_build_to_insn): Use tinsn_init.
+	(xg_expand_assembly_insn, istack_push_space, istack_pop): Likewise.
 	
-2006-02-02  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
-
-2005-02-02  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
-	T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
-	T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
-	T2_OPCODE_RSB): Define.
-	(thumb32_negate_data_op): New function.
-	(md_apply_fix): Use it.
-
-2006-01-31  Bob Wilson  <bob.wilson@acm.org>
-
-	* config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
-	fields.
-	* config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
-	* config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
-	subtracted symbols.
-	(relaxation_requirements): Add pfinish_frag argument and use it to
-	replace setting tinsn->record_fix fields.
-	(xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
-	and vinsn_to_insnbuf.  Remove references to record_fix and
-	slot_sub_symbols fields.
-	(xtensa_mark_narrow_branches): Delete unused code.
-	(is_narrow_branch_guaranteed_in_range): Handle expr that is not just
-	a symbol.
-	(convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
-	record_fix fields.
-	(tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
-	(vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
-	of the record_fix field.  Simplify error messages for unexpected
-	symbolic operands.
-	(set_expr_symbol_offset_diff): Delete.
-
-2006-01-31  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
-
-2006-01-31  Paul Brook  <paul@codesourcery.com>
-	Richard Earnshaw <rearnsha@arm.com>
-
-	* config/tc-arm.c: Use arm_feature_set.
-	(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
-	arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
-	fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
-	New variables.
-	(insns): Use them.
-	(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
-	md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
-	arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
-	s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
-	feature flags.
-	(arm_legacy_option_table, arm_option_cpu_value_table): New types.
-	(arm_opts): Move old cpu/arch options from here...
-	(arm_legacy_opts): ... to here.
-	(md_parse_option): Search arm_legacy_opts.
-	(arm_cpus, arm_archs, arm_extensions, arm_fpus)
-	(arm_float_abis, arm_eabis): Make const.
-
-2006-01-25  Bob Wilson  <bob.wilson@acm.org>
-
-	* config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
-
-2006-01-21  Jie Zhang  <jie.zhang@analog.com>
-
-	* config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
-	in load immediate intruction.
-
-2006-01-21  Jie Zhang  <jie.zhang@analog.com>
-
-	* config/bfin-parse.y (value_match): Use correct conversion
-	specifications in template string for __FILE__ and __LINE__.
-	(binary): Ditto.
-	(unary): Ditto.
-
-2006-01-18  Alexandre Oliva  <aoliva@redhat.com>
-
-	Introduce TLS descriptors for i386 and x86_64.
-	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
-	BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
-	BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
-	(optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
-	BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
-	displacement bits.
-	(build_modrm_byte): Set up zero modrm for TLS desc calls.
-	(lex_got): Handle @tlsdesc and @tlscall.
-	(md_apply_fix, tc_gen_reloc): Handle the new relocations.
-
-2006-01-11  Nick Clifton  <nickc@redhat.com>
-
-	Fixes for building on 64-bit hosts:
-	* config/tc-avr.c (mod_index): New union to allow conversion
-	between pointers and integers.
-	(md_begin, avr_ldi_expression): Use it.
-	* config/tc-i370.c (md_assemble): Add cast for argument to print
-	statement.
-	* config/tc-tic54x.c (subsym_substitute): Likewise.
-	* config/tc-mn10200.c (md_assemble): Use a union to convert the
-	opindex field of fr_cgen structure into a pointer so that it can
-	be stored in a frag.
-	* config/tc-mn10300.c (md_assemble): Likewise.
-	* config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
-	types.
-	* config/tc-v850.c: Replace uses of (int) casts with correct
-	types.
-
-2006-01-09  H.J. Lu  <hongjiu.lu@intel.com>
-
-	PR gas/2117
-	* symbols.c (snapshot_symbol): Don't change a defined symbol.
-
-2006-01-03  Hans-Peter Nilsson  <hp@bitrange.com>
-
-	PR gas/2101
-	* config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
-	a local-label reference.
-
-For older changes see ChangeLog-2005
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (SUFFIX_MAP, suffix_relocs): New.
+	(xtensa_elf_suffix): Use suffix_relocs instead of local mapping table.
+	(map_suffix_reloc_to_operator): New.
+	(map_operator_to_reloc): New.
+	(expression_maybe_register): Fix incorrect test of return value from
+	xtensa_elf_suffix.  Rearrange to use map_suffix_reloc_to_operator.
+	(xg_assemble_literal, convert_frag_immed): Use map_operator_to_reloc.
+
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-istack.h (struct tinsn_struct): Delete fixup field.
+	(tinsn_get_tok): Delete prototype.
+	* config/tc-xtensa.c (tinsn_get_tok): Delete.
+	
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.h (struct build_instr): Delete id field.
+	* config/xtensa-relax.c (widen_spec_list): Remove zeros from LITERAL
+	and LABEL tokens.
+	(append_literal_op, append_label_op): Remove litnum/labnum arguments;
+	set op_data fields to zero.
+	(parse_id_constant): Delete.
+	(build_transition): Remove code to handle numbered literals and labels.
+
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.c (build_transition): Remove code after as_fatal.
+	(build_transition_table): Likewise.
+
+2007-02-01  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_add_opcode_fix, md_apply_fix): Delete use of
+	fx_tcbit.
+	* config/tc-xtensa.h (TC_FORCE_RELOCATION_LOCAL): Remove.
+
+2007-02-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.h (struct fix <fx_pcrel_adjust, fx_size>): Move.
+	(struct fix <fx_plt>): Rename to tcbit2.
+	* write.c (fix_new_internal): Adjust.
+	(TC_FORCE_RELOCATION_LOCAL): Don't test fx_plt.
+	* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-cris.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-i960.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-sh.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-sh64.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-sparc.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-msp430.c (msp430_force_relocation_local): Likewise.
+	* config/tc-ia64.c (emit_one_bundle): Don't set fx_plt.
+	* config/tc-ia64.h (TC_FORCE_RELOCATION_LOCAL): Don't test fx_plt.
+	Instead, compare fx_r_type.
+	* config/tc-xtensa.c (xg_add_opcode_fix, md_apply_fix): Use
+	fx_tcbit in place of fx_plt.
+	* config/tc-xtensa.h (TC_FORCE_RELOCATION_LOCAL): Define.
+	* doc/internals.texi (TC_FORCE_RELOCATION_LOCAL): Remove reference
+	to fx_plt.
+
+2007-01-30  Nick Clifton  <nickc@redhat.com>
+
+	* as.c (main): Mark symbols created via the --defsym command line
+	option as volatile so that they can be overridden later on by a
+	.set directive.  This maintains compatibility with the behaviour
+	of earlier versions of the assembler.
+	* doc/as.texinfo (--defsym): Document that the defined symbol's
+	value can be overridden via a .set directive.
+
+2007-01-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (swap_imm_operands): Renamed to ...
+	(swap_2_operands): This.  Take 2 ints.
+	(md_assemble): Updated.
+	(swap_operands): Call swap_2_operands to swap 2 operands.
+
+2007-01-24  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.c (md_pseudo_table): Add .3byte.
+
+2007-01-22  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3871
+	* tc-score.c: Remove unnecessary uses of _().
+	Make the err_msg[] a file level local array in order to save
+	storage space.
+	Remove unnecessary sprintf()s.
+
+2007-01-18  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	PR gas/3871
+	* config/tc-score.c : Using _() for const string.
+	Do not assign inst.error with a local string pointer.
+	(md_section_align): Pad section.
+	
+2007-01-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (build_modrm_byte): Check number of operands
+	when procssing memory/register operand.
+
+2007-01-12  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3856
+	* macro.c (expand_irp): Do not ignore spaces inside quoted
+	strings.
+
+2007-01-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.h (TC_RELOC_RTSYM_LOC_FIXUP): Delete.
+	* config/tc-m32r.h (TC_RELOC_RTSYM_LOC_FIXUP): Delete.
+	* config/tc-mn10300.h (TC_RELOC_RTSYM_LOC_FIXUP): Delete.
+	(TC_FORCE_RELOCATION): Define.
+	(TC_FORCE_RELOCATION_LOCAL): Define.
+	* config/tc-mn10300.c (mn10300_fix_adjustable): Adjust.
+
+2007-01-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* input-file.c (input_file_open): Check fgets return.
+
+2007-01-11  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_t_add_sub): Use Rd and Rs.
+
+2007-01-11  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3707
+	* config/tc-arm.c (md_begin): Cope with an NULL mcpu_fpu_opt
+	variable.
+
+	* config/tc-mcore.c (md_number_to_chars): Use
+	number_to_chars_{big|little}endian.
+
+2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-m68k.c (m68k_archs, m68k_cpus): Treat Fido as an
+	architecture by itself.
+	(m68k_ip): Don't issue a warning for tbl instructions on fido.
+	(m68k_elf_final_processing): Treat Fido as an architecture by
+	itself.
+
+2007-01-08  Kai Tietz	<kai.tietz@onevision.com>
+
+	* configure.tgt: Renamed target x86_64-*-mingw64 to x86_64-*-mingw*
+
+2007-01-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (set_intel_syntax): Update set_intel_syntax
+	depending on allow_naked_reg.
+
+2007-01-04  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_cpsi): Set mmod bit for 2 argument form.
+
+2007-01-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/3830
+	* config/tc-i386.c (register_prefix): New.
+	(set_intel_syntax): Set set_intel_syntax to "" if register
+	prefix isn't needed.
+	(check_byte_reg): Use register_prefix for error message.
+	(check_long_reg): Likewise.
+	(check_qword_reg): Likewise.
+	(check_word_reg): Likewise.
+
+2006-01-04  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (do_neon_shl_imm): Swap rN, rM.
+	(do_neon_qshl_imm): Likewise.
+	(do_neon_rshl): New function. Handle rounding variants of
+	v{q}shl-by-register.
+	(insns): Use do_neon_rshl for vrshl, vqrshl.
+
+2007-01-04  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (NEON_ENC_TAB): Fix encoding of vclt, vcle, vaclt
+	and vacle.
+
+2007-01-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (swap_operands): Remove branches.
+
+2007-01-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Update copyright year.
+	* config/tc-i386.h: Likewise.
+
+2007-01-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (smallest_imm_type): Return unsigned int
+	instead of int.
+
+2007-01-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Convert to ISO C90 formatting
+	* config/tc-i386.h: Likewise.
+
+2007-01-03  David Daney  <ddaney@avtrex.com>
+
+	* config/tc-mips.c (md_show_usage):  Clean up -mno-shared
+	documentation.
+
+For older changes see ChangeLog-2006
 
 Local Variables:
 mode: change-log
diff --git a/contrib/binutils/gas/ChangeLog-2006 b/contrib/binutils/gas/ChangeLog-2006
new file mode 100644
index 0000000..dc933e5
--- /dev/null
+++ b/contrib/binutils/gas/ChangeLog-2006
@@ -0,0 +1,2756 @@
+2006-12-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (ShiftCount): Fix a comment typo.
+
+2006-12-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_show_usage): Mention --32/--64.
+
+2006-12-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (build_modrm_byte): Handle shift count
+	register with 3 operands.
+
+2006-12-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (process_operands): Check i.reg_operands
+	and increment i.operands when adding a register operand.
+	(build_modrm_byte): Fix 4 operand instruction handling.
+
+2006-12-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (disp_expressions): Use MAX_MEMORY_OPERANDS
+	for array size instead of 2.
+	(im_expressions): Use MAX_IMMEDIATE_OPERANDS for for array size
+	instead of 2.
+	(i386_immediate): Update immediate operand overflow error
+	message.
+	(i386_displacement): Check displacement operand overflow.
+
+2006-12-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Document tc-i386.c, not i386.c.
+
+2006-12-27  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/m68k-parse.h (m68k_register): Add CAC and MBB.
+	* config/tc-m68k.c (fido_ctrl): New.
+	(m68k_archs): Use fido_ctrl for -mfidoa.
+	(m68k_cpus): Use fido_ctrl on fido-*-*.
+	(m68k_ip): Add support for CAC and MBB.
+	(init_table): Add CAC and MBB.
+
+2006-12-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (i386_immediate): Remove prototype.
+
+2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-m68k.c (cpu_of_arch): Add fido.
+	(m68k_archs, m68k_cpu): Add entries for fido.
+	(m68k_elf_final_processing): Handle EF_M68K_CPU32_FIDO_A.
+
+2006-12-25  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (build_lw_pic): Rename as build_lwst_pic.
+	Delete the code handling large constant for PIC.
+	Modify some comments.
+	(score_relax_frag): Decrease insn_addr in certain situation.
+	(s_score_cprestore): Change .cprestore syntax from ".cprestore offset" 
+	to ".cprestore reg, offset".
+	
+2006-12-23  Kazu Hirata  <kazu@codesourcery.com>
+
+	* configure.tgt: Recognize fido.
+
+2006-12-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Add a blank line bewteen function bodies.
+
+2006-12-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (build_modrm_byte): Reformat to 72 columns.
+
+2006-12-14  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* Makefile.am (YFLAGS): Define.
+	* Makefile.in: Regenerated.
+
+2006-12-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Simplify 3 and 4 operand
+	match.
+
+2006-12-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (build_modrm_byte): Set the Operand_PCrel
+	bit only.
+
+2006-12-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Use a for loop to set
+	operand_types array.
+
+2006-12-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/3712
+	* config/tc-i386.c (match_template): Use MAX_OPERANDS for the
+	number of operands. Issue an error if MAX_OPERANDS != 4. Add
+	the 4th operand check.
+
+2006-12-13  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_arch_option_table): Add v7-{a,r,m}.
+	* doc/c-arm.texi: Fix spelling of ARMv7 profile variants.
+
+2006-12-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (WordMem): Document it for 64 bit memory
+	reference.
+
+2006-12-12  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* doc/Makefile.am (as_TEXINFOS): Set.
+	(as.info as.dvi as.html): Delete rule.
+	* doc/Makefile.in: Regenerated.
+
+2006-12-11  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* configure.in: Define GENINSRC_NEVER.
+	* doc/Makefile.am (as.info): Remove srcdir prefix.
+	(MAINTAINERCLEANFILES): Add info file.
+	(DISTCLEANFILES): Pretend to add info file.
+	* po/Make-in (.po.gmo): Put gmo files in objdir.
+	* configure, Makefile.in, doc/Makefile.in: Regenerated.
+
+2006-12-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (template): Use MAX_OPERANDS instead of 4
+	for operand_types array.
+
+2006-12-08  Christian Groessler  <chris@groessler.org>
+
+	* config/tc-z8k.c (whatreg): Add comment describing function.
+	Return NULL if symbol name characters follow the register number.
+	(parse_reg): Use NULL instead of 0 for pointer values.  Stop
+	processing if whatreg returned NULL.
+
+2006-12-07  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-m68k.c: Update uses of EF_M68K_*.
+
+2006-12-06  H.J. Lu <hjl@gnu.org>
+
+	* config/tc-i386.h: Change the prefix order to SEG_PREFIX,
+	ADDR_PREFIX, DATA_PREFIX, LOCKREP_PREFIX.
+
+2006-12-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR gas/3607
+	* subsegs.c (subseg_set_rest): Clear frch_cfi_data field.
+
+2006-12-01  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_force_relocation): Return 1 for relocs against
+	function symbols.
+
+2006-11-29  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_is_eabi): New function.
+	* config/tc-arm.h (arm_is_eabi): New prototype.
+	(THUMB_IS_FUNC): Use ELF function type for EABI objects.
+	* doc/c-arm.texi (.thumb_func): Update documentation.
+
+2006-11-29  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_vfp_sp_const, do_vfp_dp_const): Fix operans
+	encoding.
+
+2006-11-27  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (xtensa_sanity_check): Check for RELAX_IMMED
+	as the first slot_subtype, not the frag subtype.
+
+2006-11-27  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (XSHAL_ABI): Add default definition.
+	(directive_state): Disable scheduling by default.
+	(xtensa_add_config_info): New.
+	(xtensa_end): Call xtensa_add_config_info.
+
+2006-11-27  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/tc-sparc.c (tc_gen_reloc): Turn aligned relocs into
+	their unaligned counterparts in debugging sections.
+
+2006-11-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.c (md_pseudo_table): Add eqv and .eqv.
+
+2006-11-22  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-arm.h (md_cons_align): Define.
+	(mapping_state): New prototype.
+	* config/tc-arm.c (mapping_state): Make global.
+
+2006-11-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-elf.c (obj_elf_version): Use memcpy rather than strcpy.
+
+2006-11-16  Mei ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (score_relax_frag): If next frag contains 32 bit
+	branch instruction, handle it specially.
+	(score_insns): Modify 32 bit branch instruction.
+
+2006-11-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* symbols.c (resolve_symbol_value): Formatting.
+
+2006-11-15  Jan Beulich  <jbeulich@novell.com>
+
+	PR/3469
+	* symbols.c (symbol_clone): Mark symbol ending up not on symbol
+	chain by linking it to itself.
+	(resolve_symbol_value): Also check symbol_shadow_p().
+	(symbol_shadow_p): New.
+	* symbols.h (symbol_shadow_p): Declare.
+
+2006-11-12  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (do_t_czb): Rename to do_t_cbz.
+	(insns): Adjust accordingly.
+	(md_apply_fix): Alter comments to use CBZ instead of CZB.
+
+2006-11-10  Pedro Alves <pedro_alves@portugalmail.pt>
+
+	* config/tc-arm.c (arm_fix_adjustable) [OBJ_COFF]: Delete.
+	(arm_fix_adjustable) [OBJ_ELF]: Use it on coff targets too.
+
+2006-11-10  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3456:
+	* config/obj-elf.c (obj_elf_version): Do not include the name
+	field's padding in the namesz value.
+
+2006-11-09  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c: Fix outdated comment.
+
+2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (CpuPNI): Removed.
+	(CpuUnknownFlags): Replace CpuPNI with CpuSSE3.
+	* config/tc-i386.c (md_assemble): Likewise.
+
+2006-11-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* symbols.c (symbol_create, symbol_clone): Don't set udata.p.
+
+2006-11-06  David Daney  <ddaney@avtrex.com>
+
+	* config/tc-mips.c (pic_need_relax): Return true for section symbols.
+
+2006-11-06  Thiemo Seufer  <ths@mips.com>
+
+	* doc/c-mips.texi (-march): Document sb1a.
+
+2006-11-06  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): Remove 24k/24ke aliases.
+	34k always has DSP ASE.
+
+2006-11-03  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (md_pcrel_from_section): Disallow PC relative
+	MIPS16 instructions referencing other sections, unless they are
+	external branches.
+
+2006-11-03  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): The 25Kf is a MIPS64
+	release 1 CPU.
+
+2006-11-03  Jakub Jelinek  <jakub@redhat.com>
+
+	* dw2gencfi.c (struct fde_entry): Add per_encoding, lsda_encoding,
+	personality and lsda.
+	(struct cie_entry): Add per_encoding, lsda_encoding and personality.
+	(alloc_fde_entry): Initialize per_encoding and lsda_encoding.
+	(cfi_pseudo_table): Handle .cfi_personality and .cfi_lsda.
+	(dot_cfi_personality, dot_cfi_lsda, encoding_size): New functions.
+	(output_cie): Output personality including its encoding and LSDA encoding.
+	(output_fde): Output LSDA.
+	(select_cie_for_fde): Don't share CIE if personality, its encoding or
+	LSDA encoding are different.  Copy the 3 fields from fde_entry to
+	cie_entry.
+	* doc/as.texinfo (.cfi_personality, .cfi_lsda): Document.
+
+	* subsegs.h (struct frchain): Add frch_cfi_data field.
+	* dw2gencfi.c: Include subsegs.h.
+	(cur_fde_data, last_address, cur_cfa_offset, cfa_save_stack): Removed.
+	(struct frch_cfi_data): New type.
+	(unused_cfi_data): New variable.
+	(alloc_fde_entry): Move cur_fde_data, last_address, cur_cfa_offset
+	and cfa_save_stack static vars into a structure pointed from
+	each frchain.
+	(alloc_cfi_insn_data, cfi_new_fde, cfi_end_fde, cfi_set_return_column,
+	cfi_add_advance_loc, cfi_add_CFA_def_cfa, cfi_add_CFA_def_cfa_offset,
+	cfi_add_CFA_remember_state, cfi_add_CFA_restore_state, dot_cfi,
+	dot_cfi_escape, dot_cfi_startproc, dot_cfi_endproc, cfi_finish):
+	Likewise.
+
+2006-11-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-h8300.c (build_bytes): Fix const warning.
+
+2006-11-01  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* tc-score.c (do16_rdrs): Handle not! instruction especially.
+
+2006-10-31  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_adjust_symtab): Don't use STT_ARM_16BIT
+	for EABIv4.
+
+2006-10-31  Paul Brook  <paul@codesourcery.com>
+
+	gas/
+	* config/tc-arm.c (object_arch): New variable.
+	(s_arm_object_arch): New function.
+	(md_pseudo_table): Add object_arch.
+	(aeabi_set_public_attributes): Obey object_arch.
+	* doc/c-arm.texi: Document .object_arch.
+
+2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* tc-score.c (data_op2): Check invalid operands.
+	(my_get_expression): Const operand of some instructions can not be
+	symbol in assembly.
+	(get_insn_class_from_type): Handle instruction type Insn_internal.
+	(do_macro_ldst_label): Modify inst.type.
+	(Insn_PIC): Delete.
+	(data_op2): The immediate value in lw is 15 bit signed.
+
+2006-10-29  Randolph Chung  <tausq@debian.org>
+
+	* config/tc-hppa.c (hppa_cfi_frame_initial_instructions)
+	(hppa_regname_to_dw2regnum): New funcions.
+	* config/tc-hppa.h [OBJ_ELF] (TARGET_USE_CFIPOP): Define.
+	(tc_cfi_frame_initial_instructions)
+	(tc_regname_to_dw2regnum): Define.
+	(hppa_cfi_frame_initial_instructions)
+	(hppa_regname_to_dw2regnum): Declare.
+	(DWARF2_LINE_MIN_INSN_LENGTH, DWARF2_DEFAULT_RETURN_COLUMN)
+	(DWARF2_CIE_DATA_ALIGNMENT): Define.
+
+2006-10-29  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-spu.c (md_assemble): Cast printf string size parameter
+	to int in order to avoid a compiler warning.
+
+2006-10-27  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* config/tc-sh.c (md_assemble): Define size of branches.
+
+2006-10-26  Ben Elliston  <bje@au.ibm.com>
+
+	* dw2gencfi.c (cfi_add_CFA_offset):
+	Assert DWARF2_CIE_DATA_ALIGNMENT is non-zero.
+
+	* write.c (chain_frchains_together_1): Assert that this function
+	never returns a pointer to the auto variable `dummy'.
+
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.c: New file.
+	* config/tc-spu.h: New file.
+	* configure.tgt: Add SPU support.
+	* Makefile.am: Likewise.  Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2006-10-25  Ben Elliston  <bje@au.ibm.com>
+
+	* expr.c (expr): Replace O_add case in switch (op_left) explaining
+	why it can never occur.
+
+2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+	* doc/c-ppc.texi (-mcell): Document.
+	* config/tc-ppc.c (parse_cpu): Parse -mcell.
+	(md_show_usage): Document -mcell.
+
+2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
+
+	* doc/c-i386.texi : Document amdfam10,.sse4a and .abm in cpu_type.
+
+2006-10-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-m68hc11.c (md_assemble): Quiet warning.
+
+2006-10-19  Mike Frysinger  <vapier@gentoo.org>
+
+	* config/tc-i386.c (md_parse_option): Use CONST_STRNEQ.
+	(x86_64_section_letter): Likewise.
+
+2006-10-19  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (build_relax_frag): Compute correct
+	tc_frag_data.fixp.
+
+2006-10-18  Roy Marples  <uberlord@gentoo.org>
+
+	* config/tc-sparc.c (md_parse_option): Treat any target starting with
+	elf32-sparc as a viable target for the -32 switch and any target
+	starting with elf64-sparc as a viable target for the -64 switch.
+	(sparc_target_format): For 64-bit ELF flavoured output use
+	ELF_TARGET_FORMAT64 while for 32-bit ELF flavoured output use
+	ELF_TARGET_FORMAT.
+	* config/tc-sparc.h (ELF_TARGET_FORMAT, ELF_TARGET_FORMAT64): Define.
+
+2006-10-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* configure: Regenerated.
+
+2006-10-16  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* input-scrub.c (input_scrub_next_buffer): Use TC_EOL_IN_INSN
+	in addition to testing for '\n'.
+	(TC_EOL_IN_INSN): Provide a default definition if necessary.
+
+2006-10-13  Sterling Augstine  <sterling@tensilica.com>
+
+	* dwarf2dbg.c (out_debug_info): Use TC_DWARF2_EMIT_OFFSET to emit
+	a disjoint DW_AT range.
+
+2006-10-13  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (md_show_usage): Print -KPIC option usage.
+
+2006-10-08  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_big_immediate): 64-bit host fix.
+	(parse_operands): Use parse_big_immediate for OP_NILO.
+	(neon_cmode_for_logic_imm): Try smaller element sizes.
+	(neon_cmode_for_move_imm): Ditto.
+	(do_neon_logic): Handle .i64 pseudo-op.
+
+2006-09-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/POTFILES.in: Regenerate.
+
+2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (CpuMNI): Renamed to ...
+	(CpuSSSE3): This.
+	(CpuUnknownFlags): Updated.
+	(processor_type): Replace PROCESSOR_YONAH with PROCESSOR_CORE
+	and PROCESSOR_MEROM with PROCESSOR_CORE2.
+	* config/tc-i386.c: Updated.
+	* doc/c-i386.texi: Likewise.
+
+	* config/tc-i386.c (cpu_arch): Add ".ssse3", "core" and "core2".
+
+2006-09-28  Bridge Wu  <mingqiao.wu@gmail.com>
+
+	* config/tc-arm.c (md_apply_fix): Do not clear write_back bit.
+
+2006-09-27  Nick Clifton  <nickc@redhat.com>
+
+	* output-file.c (output_file_close): Prevent an infinite loop
+	reporting that stdoutput could not be closed.
+
+2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
+            Joseph Myers  <joseph@codesourcery.com>
+            Ian Lance Taylor  <ian@wasabisystems.com>
+            Ben Elliston  <bje@wasabisystems.com>
+
+	* config/tc-arm.c (arm_cext_iwmmxt2): New.
+	(enum operand_parse_code): New code OP_RIWR_I32z.
+	(parse_operands): Handle OP_RIWR_I32z.
+	(do_iwmmxt_wmerge): New function.
+	(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
+	a register.
+	(do_iwmmxt_wrwrwr_or_imm5): New function.
+	(insns): Mark instructions as RIWR_I32z as appropriate.
+	Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
+	waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
+	wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
+	wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
+	(md_begin): Handle IWMMXT2.
+	(arm_cpus): Add iwmmxt2.
+	(arm_extensions): Likewise.
+	(arm_archs): Likewise.
+
+2006-09-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/as.texinfo (Overview): Revise description of --keep-locals.
+	Add xref to "Symbol Names".
+	(L): Refer to "local symbols" instead of "local labels".  Move
+	definition to "Symbol Names" section; add xref to that section.
+	(Symbol Names): Use "Local Symbol Names" section to define local
+	symbols.  Add "Local Labels" heading for description of temporary
+	forward/backward labels, and refer to those as "local labels".
+
+2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/3235
+	* config/tc-i386.c (match_template): Check address size prefix
+	to turn Disp64/Disp32/Disp16 operand into Disp32/Disp16/Disp32
+	operand.
+
+2006-09-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (ppc_symbol_chars): Remove '+' and '-'.
+
+2006-09-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* as.h (as_perror): Delete declaration.
+	* gdbinit.in (as_perror): Delete breakpoint.
+	* messages.c (as_perror): Delete function.
+	* doc/internals.texi: Remove as_perror description.
+	* listing.c (listing_print: Don't use as_perror.
+	* output-file.c (output_file_create, output_file_close): Likewise.
+	* symbols.c (symbol_create, symbol_clone): Likewise.
+	* write.c (write_contents): Likewise.
+	* config/obj-som.c (obj_som_version, obj_som_copyright): Likewise.
+	* config/tc-tic54x.c (tic54x_mlib): Likewise.
+
+2006-09-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (md_section_align): Don't round up address for ELF.
+	(ppc_handle_align): New function.
+	* config/tc-ppc.h (HANDLE_ALIGN): Use ppc_handle_align.
+	(SUB_SEGMENT_ALIGN): Define as zero.
+
+2006-09-20  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/as.texinfo: Fix cross reference usage, typos and grammar.
+	(Overview): Skip cross reference in man page.
+
+2006-09-20  Kai Tietz  <Kai.Tietz@onevision.com>
+
+	* configure.in: Add new target x86_64-pc-mingw64.
+	* configure: Regenerate.
+	* configure.tgt: Add new target x86_64-pc-mingw64.
+	* config/obj-coff.h: Add handling for TE_PEP target specific code
+	and definitions.
+	* config/tc-i386.c: Add new targets.
+	(md_parse_option): Add targets to OPTION_64.
+	(x86_64_target_format): Add new method for setup proper default
+	target cpu mode.
+	* config/te-pep.h: Add new target definition header.
+	(TE_PEP): New macro: Identifies new target architecture.
+	(COFF_WITH_pex64): Set proper includes in bfd.
+	* NEWS: Mention new target.
+
+2006-09-18  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* config/bfin-parse.y (binary): Change sub of const to add of negated
+	const.
+
+2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c: New file.
+	* config/tc-score.h: Newf file.
+	* configure.tgt: Add Score target.
+	* Makefile.am: Add Score files.
+	* Makefile.in: Regenerate.
+	* NEWS: Mention new target support.
+
+2006-09-16  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_unwind_movsp): Add offset argument.
+	* doc/c-arm.texi (movsp): Document offset argument.
+
+2006-09-16  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (thumb32_negate_data_op): Consistently use
+	unsigned int to avoid 64-bit host problems.
+
+2006-09-15  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* config/bfin-parse.y (binary): Do some more constant folding for
+	additions.
+
+2006-09-13  Jan Beulich  <jbeulich@novell.com>
+
+	* input-file.c (input_file_give_next_buffer): Demote as_bad to
+	as_warn.
+
+2006-09-13  Alan Modra  <amodra@bigpond.net.au>
+
+	PR gas/3165
+	* config/tc-sh (DWARF2_CIE_DATA_ALIGNMENT): Wrap negative number
+	in parens.
+
+2006-09-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* input-file.c (input_file_open): Replace as_perror with as_bad
+	so that gas exits with error on file errors.  Correct error
+	message.
+	(input_file_get, input_file_give_next_buffer): Likewise.
+	* input-file.h: Update comment.
+
+2006-09-11  Tomas Frydrych  <dr.tomas@yahoo.co.uk>
+
+	PR gas/3172
+	* config/tc-arm.c (parse_typed_reg_or_scalar): Accept wCg class
+	registers as a sub-class of wC registers.
+
+2006-09-11  Alan Modra  <amodra@bigpond.net.au>
+
+	PR gas/3165
+	* config/tc-mips.h (enum dwarf2_format): Forward declare.
+	(DWARF2_CIE_DATA_ALIGNMENT): Wrap negative number in parens.
+	* config/tc-alpha.h (DWARF2_CIE_DATA_ALIGNMENT): Likewise.
+	* config/tc-arm.h (DWARF2_CIE_DATA_ALIGNMENT): Likewise.
+
+2006-09-08  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3129
+	* doc/as.texinfo (Macro): Improve documentation about separating
+	macro arguments from following text.
+
+2006-09-08  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Allow ARM IT pseudo-insn on all cores.
+
+2006-09-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_operands): Mark operand as present.
+
+2006-09-04  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_neon_dyadic_if_i): Remove.
+	(do_neon_dyadic_if_i_d): Avoid setting U bit.
+	(do_neon_mac_maybe_scalar): Ditto.
+	(do_neon_dyadic_narrow): Force operand type to NT_integer.
+	(insns): Remove out of date comments.
+
+2006-08-29  Nick Clifton  <nickc@redhat.com>
+
+	* read.c (s_align): Initialize the 'stopc' variable to prevent
+	compiler complaints about it being used without being
+	initialized.
+	(s_comm_internal, s_mri_common, s_fail, s_globl, s_space,
+	s_float_space, s_struct, cons_worker, equals): Likewise.
+
+2006-08-29  Malcolm Parsons  <malcolm.parsons@gmail.com>
+
+	* ecoff.c (ecoff_directive_val): Fix message typo.
+	* config/tc-ns32k.c (convert_iif): Likewise.
+	* config/tc-sh64.c (shmedia_check_limits): Likewise.
+
+2006-08-25  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_mark_literal_pool_location): Do not check
+	the state of the absolute_literals directive.  Remove align frag at
+	the start of the literal pool position.
+
+2006-08-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/c-xtensa.texi: Add @group commands in examples.
+
+2006-08-24  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (FINI_LITERAL_SECTION_NAME): Delete.
+	(INIT_LITERAL_SECTION_NAME): Delete.
+	(lit_state struct): Remove segment names, init_lit_seg, and
+	fini_lit_seg.  Add lit_prefix and current_text_seg.
+	(init_literal_head_h, init_literal_head): Delete.
+	(fini_literal_head_h, fini_literal_head): Delete.
+	(xtensa_begin_directive): Move argument parsing to
+	xtensa_literal_prefix function.
+	(xtensa_end_directive): Deallocate lit_prefix field of lit_state.
+	(xtensa_literal_prefix): Parse the directive argument here and
+	record it in the lit_prefix field.  Remove code to derive literal
+	section names.
+	(linkonce_len): New.
+	(get_is_linkonce_section): Use linkonce_len.  Check for any
+	".gnu.linkonce.*" section, not just text sections.
+	(md_begin): Remove initialization of deleted lit_state fields.
+	(xtensa_reorder_segments, xtensa_post_relax_hook): Remove references
+	to init_literal_head and fini_literal_head.
+	(xtensa_move_literals): Likewise.  Skip literals for .init and .fini
+	when traversing literal_head list.
+	(match_section_group): New.
+	(cache_literal_section): Rewrite to determine the literal section
+	name on the fly, create the section and return it.
+	(xtensa_switch_to_literal_fragment): Adjust for cache_literal_section.
+	(xtensa_switch_to_non_abs_literal_fragment): Likewise.
+	(xtensa_create_property_segments, xtensa_create_xproperty_segments):
+	Use xtensa_get_property_section from bfd.
+	(retrieve_xtensa_section): Delete.
+	* doc/c-xtensa.texi (Xtensa Options): Fix --text-section-literals
+	description to refer to plural literal sections and add xref to
+	the Literal Directive section.
+	(Literal Directive): Describe new rules for deriving literal section
+	names.  Add footnote for special case of .init/.fini with
+	--text-section-literals.
+	(Literal Prefix Directive): Replace old naming rules with xref to the
+	Literal Directive section.
+
+2006-08-21  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_unwind_save_mmxwr): Correct condition for
+	merging with previous long opcode.
+
+2006-08-22  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* Makefile.am (TARG_ENV_HFILES): Add te-wince-pe.h.
+	* Makefile.in: Regenerate.
+	* config/tc-arm.h [TARGET_FORMAT]: ARM wince bfd names were
+	renamed. Adjust.
+
+2006-08-16  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (md_assemble): Improve diagnostic when attempting
+	to use ARM instructions on non-ARM-supporting cores.
+	(autoselect_thumb_from_cpu_variant): New function. Switch on Thumb
+	mode automatically based on cpu variant.
+	(md_begin): Call above function.
+
+2006-08-16  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (opcode_lookup): Allow Neon type suffixes to be
+	recognized in non-unified syntax mode.
+
+2006-08-15  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* configure.tgt: Handle mips*-sde-elf*.
+
+2006-08-12  Thiemo Seufer  <ths@networkno.de>
+
+	* config/tc-mips.c (mips16_ip): Fix argument register handling
+	for restore instruction.
+
+2006-08-08  Bob Wilson  <bob.wilson@acm.org>
+
+	* dwarf2dbg.c (DWARF2_USE_FIXED_ADVANCE_PC): New.
+	(out_sleb128): New.
+	(out_fixed_inc_line_addr): New.
+	(process_entries): Use out_fixed_inc_line_addr when
+	DWARF2_USE_FIXED_ADVANCE_PC is set.
+	* config/tc-xtensa.h (DWARF2_USE_FIXED_ADVANCE_PC): Define.
+
+2006-08-08  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-sh.c (sh_frob_section): Canonicalize pointers to local
+	vs full symbols so that we never have more than one pointer value
+	for any given symbol in our symbol table.
+
+2006-08-08  Sterling Augustine  <sterling@tensilica.com>
+
+	* dwarf2dbg.c (out_debug_info): Add new parameter ranges_seg
+	and emit DW_AT_ranges when code in compilation unit is not
+	contiguous.
+	(out_debug_abbrev): Emit DW_AT_ranges abbreviation if code in
+	is not contiguous.
+	(dwarf2_finish): Create and pass ranges_seg to out_debug_info.
+	(out_debug_ranges): New function to emit .debug_ranges section
+	when code is not contiguous.
+
+2006-08-08  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (WARN_DEPRECATED): Enable.
+
+2006-08-05  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* config/tc-arm.c: Move "dwarf2dbg.h" inclusion out of OBJ_ELF
+	only block.
+	(pe_directive_secrel) [TE_PE]: New function.
+	(md_pseudo_table) [!OBJ_ELF]: Handle 2byte, 4byte, 8byte, file,
+	loc, loc_mark_labels.
+	[TE_PE]: Handle secrel32.
+	(output_relax_insn): Remove OBJ_ELF around dwarf2_emit_insn
+	call.
+	(output_inst): Remove OBJ_ELF around dwarf2_emit_insn call.
+	(arm_frob_label): Remove OBJ_ELF around dwarf2_emit_label call.
+	(md_section_align): Only round section sizes here for AOUT
+	targets.
+	(tc_arm_regname_to_dw2regnum): Move out for OBJ_ELF only block.
+	(tc_pe_dwarf2_emit_offset): New function.
+	(md_apply_fix) [TE_PE]: Handle BFD_RELOC_32_SECREL.
+	(cons_fix_new_arm): Handle O_secrel.
+	* config/tc-arm.h : Move DWARF2_LINE_MIN_INSN_LENGTH,
+	DWARF2_DEFAULT_RETURN_COLUMN and DWARF2_CIE_DATA_ALIGNMENT out
+	of OBJ_ELF only block.
+	[TE_PE]: Define O_secrel, TC_DWARF2_EMIT_OFFSET, and declare
+	tc_pe_dwarf2_emit_offset.
+
+2006-08-04  Richard Sandiford  <richard@codesourcery.com>
+
+	* config/tc-sh.c (apply_full_field_fix): New function.
+	(md_apply_fix): Use it instead of md_number_to_chars.  Do not fill
+	in fx_addnumber for BFD_RELOC_32_PLT_PCREL.
+	(tc_gen_reloc): Use fx_addnumber rather than 0 as the default case.
+	* config/tc-sh.h (TARGET_FORMAT): Override for TE_VXWORKS.
+
+2006-08-03  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/2991
+	* config.in: Regenerate.
+
+2006-08-03  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-arm.c (parse_operands): Handle invalid register name
+	for OP_RIWR_RIWC.
+
+2006-08-03  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-arm.c (enum operand_parse_code): Add OP_RIWC_RIWG.
+	(parse_operands): Handle it.
+	(insns): Use it for tmcr and tmrc.
+
+2006-08-02  Petr Salinger  <Petr.Salinger@seznam.cz>
+
+	PR binutils/2983
+	* config/tc-i386.c (md_parse_option): Treat any target starting
+	with elf64_x86_64 as a viable target for the -64 switch.
+	(i386_target_format): For 64-bit ELF flavoured output use
+	ELF_TARGET_FORMAT64.
+	* config/tc-i386.h (ELF_TARGET_FORMAT64): Define.
+
+2006-08-02  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/2991
+	* acinclude.m4 (BFD_BINARY_FOPEN): Import this function from
+	bfd/aclocal.m4.
+	* configure.in: Run BFD_BINARY_FOPEN.
+	* configure: Regenerate.
+	* as.h: Look at USE_BINARY_FOPEN to decide which fopen-*.h header
+	file to include.
+
+2006-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_assemble): Don't update
+	cpu_arch_isa_flags.
+
+2006-08-01  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (md_section_align): Check ELF-ness at runtime.
+
+2006-08-01  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (macro_build_lui): Fix comment formatting.
+	(md_apply_fix): Likewise. Unify handling of BFD_RELOC_RVA,
+	BFD_RELOC_32 and BFD_RELOC_16.
+	(s_align, s_cpload, s_cplocal, s_cprestore, s_mips_stab,
+	md_convert_frag, md_obj_end): Fix comment formatting.
+
+2006-07-31  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (md_apply_fix, tc_gen_reloc): Remove special
+	handling for BFD_RELOC_MIPS16_JMP.
+
+2006-07-24  Andreas Schwab  <schwab@suse.de>
+
+	PR/2756
+	* read.c (read_a_source_file): Ignore unknown text after line
+	comment character.  Fix misleading comment.
+
+2006-07-24  Ralk Wildenhues  <Ralf.Wildenhues@gmx.de>
+
+	* doc/all.texi, doc/as.texinfo, doc/c-arc.texi, doc/c-arm.texi,
+	doc/c-avr.texi, doc/c-bfin.texi, doc/c-i386.texi,
+	doc/c-i960.texi, doc/c-m32r.texi, doc/c-m68k.texi,
+	doc/c-mmix.texi, doc/c-pdp11.texi, doc/c-ppc.texi,
+	doc/c-tic54x.texi, doc/c-v850.texi, doc/c-xtensa.texi,
+	doc/c-z80.texi, doc/internals.texi: Fix some typos.
+
+2006-07-21  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-sh.c (md_longopts): Add -EL and -EB for use by the
+	linker testsuite.
+
+2006-07-20  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* config/tc-mips.c (md_parse_option): Don't infer optimisation
+	options from debug options.
+
+2006-07-20  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_fix_adjustable): Handle BFD_RELOC_MIPS16_JMP.
+	(tc_gen_reloc): Handle mips16 jumps to section symbol offsets.
+
+2006-07-19  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Fix rbit Arm opcode.
+
+2006-07-18  Paul Brook  <paul@codesourcery.com>
+
+	* tc-arm.c (do_t_add_sub): Use addw/subw when source is PC.
+	(md_convert_frag): Use correct reloc for add_pc.  Use
+	BFD_RELOC_ARM_T32_ADD_IMM for normal add/sum.
+	(md_apply_fix): Handle BFD_RELOC_ARM_T32_ADD_IMM.
+	(arm_force_relocation): Handle BFD_RELOC_ARM_T32_ADD_IMM.
+
+2006-07-17  Mat Hostetter  <mat@lcs.mit.edu>
+
+	* symbols.c (report_op_error): Fix pasto.  Don't use as_bad_where
+	when file and line unknown.
+
+2006-07-17  Thiemo Seufer  <ths@mips.com>
+
+	* read.c (s_struct): Use IS_ELF.
+	* config/tc-mips.c (md_begin, mips16_mark_labels, mips_ip,
+	md_parse_option, s_change_sec, pic_need_relax, mips_fix_adjustable,
+	tc_gen_reloc, mips_frob_file_after_relocs, s_mips_end, s_mips_frame,
+	s_mips_mask): Likewise.
+
+2006-07-16  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* read.c (s_struct): Handle ELF section changing.
+	* config/tc-mips.c (s_align): Leave enabling auto-align to the
+	generic code.
+	(s_change_sec): Try section changing only if we output ELF.
+
+2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
+	CpuAmdFam10.
+	(smallest_imm_type): Remove Cpu086.
+	(i386_target_format): Likewise.
+
+	* config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
+	Update CpuXXX.
+
+2006-07-13 Dwarakanath Rajagopal	<dwarak.rajagopal@amd.com>
+	   Michael Meissner		<michael.meissner@amd.com>
+
+	* config/tc-i386.h (PROCESSOR_AMDFAM10): New processor_type.
+	(CpuSSE4a, CpuABM, CpuAmdFam10): New Cpu directives.
+	* config/tc-i386.c (cpu_arch): Add support for AmdFam10
+	architecture.
+	(i386_align_code): Ditto.
+	(md_assemble_code): Add support for insertq/extrq instructions,
+	swapping as needed for intel syntax.
+	(swap_imm_operands): New function to swap immediate operands.
+	(swap_operands): Deal with 4 operand instructions.
+	(build_modrm_byte): Add support for insertq instruction.
+
+2006-07-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (Size64): Fix a typo in comment.
+
+2006-07-12  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-sh.c (md_apply_fix): Do not allow the generic code in
+	fixup_segment() to repeat a range check on a value that has
+	already been checked here.
+
+2006-07-07  James E Wilson  <wilson@specifix.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): Add sb1a.
+
+2006-07-06  Mohammed Adnène Trojette  <adn@diwi.org>
+	    Nick Clifton  <nickc@redhat.com>
+
+	PR binutils/2877
+	* doc/as.texi: Fix spelling typo: branchs => branches.
+	* doc/c-m68hc11.texi: Likewise.
+	* config/tc-m68hc11.c: Likewise.
+	Support old spelling of command line switch for backwards
+	compatibility.
+
+2006-07-04  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (s_is_linkonce): New function.
+	(mips16_mark_labels): Don't adjust mips16 symbol addresses for
+	weak, external, and linkonce symbols.
+	(pic_need_relax): Use s_is_linkonce.
+
+2006-06-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* doc/as.texinfo (Org): Remove space.
+	(P2align): Add "@var{abs-expr},".
+
+2006-06-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch_tune_set): New.
+	(cpu_arch_isa): Likewise.
+	(i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
+	nops with short or long nop sequences based on -march=/.arch
+	and -mtune=.
+	(set_cpu_arch): Set cpu_arch_isa.  If cpu_arch_tune_set is 0,
+	set cpu_arch_tune and cpu_arch_tune_flags.
+	(md_parse_option): For -march=, set cpu_arch_isa and set
+	cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
+	0.  Set cpu_arch_tune_set to 1 for -mtune=.
+	(i386_target_format): Don't set cpu_arch_tune.
+
+2006-06-23  Nigel Stephens  <nigel@mips.com>
+
+	* config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
+	generated .sbss.* and .gnu.linkonce.sb.*.
+
+2006-06-23  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
+	label_list.
+	* config/tc-mips.c (label_list): Define per-segment label_list.
+	(mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
+	append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
+	mips_from_file_after_relocs, mips_define_label): Use per-segment
+	label_list.
+
+2006-06-22  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
+	(append_insn): Use it.
+	(md_apply_fix): Whitespace formatting.
+	(md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
+	mips16_extended_frag): Remove register specifier.
+	(md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
+	constants.
+
+2006-06-21  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New.  Parse
+	a directive saving VFP registers for ARMv6 or later.
+	(s_arm_unwind_save): Add parameter arch_v6 and call
+	s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
+	appropriate.
+	(md_pseudo_table): Add entry for new "vsave" directive.
+	* doc/c-arm.texi: Correct error in example for "save"
+	directive (fstmdf -> fstmdx).  Also document "vsave" directive.
+
+2006-06-18  Joerg Wunsch <j.gnu@uriah.heep.sax.de>
+	    Anatoly Sokolov <aesok@post.ru>
+
+	* config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
+	and atmega644p devices. Rename atmega164/atmega324 devices to
+	atmega164p/atmega324p.
+	* doc/c-avr.texi: Document new mcu and arch options.
+
+2006-06-17  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (enum parse_operand_result): Move outside of
+	#ifdef OBJ_ELF so that non-ELF targeted ARM ports can build.
+
+2006-06-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (processor_type): New.
+	(arch_entry): Add type.
+
+	* config/tc-i386.c (cpu_arch_tune): New.
+	(cpu_arch_tune_flags): Likewise.
+	(cpu_arch_isa_flags): Likewise.
+	(cpu_arch): Updated.
+	(set_cpu_arch): Also update cpu_arch_isa_flags.
+	(md_assemble): Update cpu_arch_isa_flags.
+	(OPTION_MARCH): New.
+	(OPTION_MTUNE): Likewise.
+	(md_longopts): Add -march= and -mtune=.
+	(md_parse_option): Support -march= and -mtune=.
+	(md_show_usage): Add -march=CPU/-mtune=CPU.
+	(i386_target_format): Also update cpu_arch_isa_flags,
+	cpu_arch_tune and cpu_arch_tune_flags.
+
+	* doc/as.texinfo: Add -march=CPU/-mtune=CPU.
+
+	* doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
+
+2006-06-15  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (enum parse_operand_result): New.
+	(struct group_reloc_table_entry): New.
+	(enum group_reloc_type): New.
+	(group_reloc_table): New array.
+	(find_group_reloc_table_entry): New function.
+	(parse_shifter_operand_group_reloc): New function.
+	(parse_address_main): New function, incorporating code
+	from the old parse_address function.  To be used via...
+	(parse_address): wrapper for parse_address_main; and
+	(parse_address_group_reloc): new function, likewise.
+	(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
+	OP_ADDRGLDRS, OP_ADDRGLDC.
+	(parse_operands): Support for these new operand codes.
+	New macro po_misc_or_fail_no_backtrack.
+	(encode_arm_cp_address): Preserve group relocations.
+	(insns): Modify to use the above operand codes where group
+	relocations are permitted.
+	(md_apply_fix): Handle the group relocations
+	ALU_PC_G0_NC through LDC_SB_G2.
+	(tc_gen_reloc): Likewise.
+	(arm_force_relocation): Leave group relocations for the linker.
+	(arm_fix_adjustable): Likewise.
+
+2006-06-15  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
+	(do_neon_ldr_str): Always defer to VFP encoding routines, which handle
+	relocs properly.
+
+2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (process_suffix): Don't add rex64 for
+	"xchg %rax,%rax".
+
+2006-06-09  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_ip): Maintain argument count.
+
+2006-06-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-iq2000.c: Include sb.h.
+
+2006-06-08  Nigel Stephens  <nigel@mips.com>
+
+	* config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
+	aliases for better compatibility with SGI tools.
+
+2006-06-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.
+	* Makefile.am (GASLIBS): Expand @BFDLIB@.
+	(BFDVER_H): Delete.
+	(OBJS): Expand @ALL_OBJ_DEPS@.  Depend on all fopen-*.h variants.
+	(obj-aout.o): Depend on $(DEP_@target_get_type@_aout)
+	(obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly.
+	Run "make dep-am".
+	* dep-in.sed: Don't substitute bfdver.h.  Do remove symcat.h.
+	* Makefile.in: Regenerate.
+	* doc/Makefile.in: Regenerate.
+	* configure: Regenerate.
+
+2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
+
+	* po/Make-in (pdf, ps): New dummy targets.
+
+2006-06-07  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (stdarg.h): include.
+	(arm_it): Add uncond_value field. Add isvec and issingle to operand
+	array.
+	(arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
+	REG_TYPE_NSDQ (single, double or quad vector reg).
+	(reg_expected_msgs): Update.
+	(BAD_FPU): Add macro for unsupported FPU instruction error.
+	(parse_neon_type): Support 'd' as an alias for .f64.
+	(parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
+	sets of registers.
+	(parse_vfp_reg_list): Don't update first arg on error.
+	(parse_neon_mov): Support extra syntax for VFP moves.
+	(operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
+	OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
+	(parse_operands): Support isvec, issingle operands fields, new parse
+	codes above.
+	(do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
+	msr variants.
+	(do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
+	(NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
+	(NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
+	(NEON_SHAPE_DEF): New macro. Define table of possible instruction
+	shapes.
+	(neon_shape): Redefine in terms of above.
+	(neon_shape_class): New enumeration, table of shape classes.
+	(neon_shape_el): New enumeration. One element of a shape.
+	(neon_shape_el_size): Register widths of above, where appropriate.
+	(neon_shape_info): New struct. Info for shape table.
+	(neon_shape_tab): New array.
+	(neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
+	(neon_check_shape): Rewrite as...
+	(neon_select_shape): New function to classify instruction shapes,
+	driven by new table neon_shape_tab array.
+	(neon_quad): New function. Return 1 if shape should set Q flag in
+	instructions (or equivalent), 0 otherwise.
+	(type_chk_of_el_type): Support F64.
+	(el_type_of_type_chk): Likewise.
+	(neon_check_type): Add support for VFP type checking (VFP data
+	elements fill their containing registers).
+	(do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
+	in thumb mode for VFP instructions.
+	(do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
+	and encode the current instruction as if it were that opcode.
+	(try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
+	arguments, call function in PFN.
+	(do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
+	(do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
+	(do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
+	(do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
+	(do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
+	Redirect Neon-syntax VFP instructions to VFP instruction handlers.
+	(do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
+	(do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
+	(neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
+	(do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
+	(do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
+	(do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
+	(do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
+	(do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
+	(do_neon_swp): Use neon_select_shape not neon_check_shape. Use
+	neon_quad.
+	(vfp_or_neon_is_neon): New function. Call if a mnemonic shared
+	between VFP and Neon turns out to belong to Neon. Perform
+	architecture check and fill in condition field if appropriate.
+	(do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
+	(do_neon_cvt): Add support for VFP variants of instructions.
+	(neon_cvt_flavour): Extend to cover VFP conversions.
+	(do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
+	vmov variants.
+	(do_neon_ldr_str): Handle single-precision VFP load/store.
+	(do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
+	NS_NULL not NS_IGNORE.
+	(opcode_tag): Add OT_csuffixF for operands which either take a
+	conditional suffix, or have 0xF in the condition field.
+	(md_assemble): Add support for OT_csuffixF.
+	(NCE): Replace macro with...
+	(NCE_tag, NCE, NCEF): New macros.
+	(nCE): Replace macro with...
+	(nCE_tag, nCE, nCEF): New macros.
+	(insns): Add support for VFP insns or VFP versions of insns msr,
+	mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
+	vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
+	vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
+	VFP/Neon insns together.
+
+2006-06-07  Alan Modra  <amodra@bigpond.net.au>
+	    Ladislav Michl  <ladis@linux-mips.org>
+
+	* app.c: Don't include headers already included by as.h.
+	* as.c: Likewise.
+	* atof-generic.c: Likewise.
+	* cgen.c: Likewise.
+	* dwarf2dbg.c: Likewise.
+	* expr.c: Likewise.
+	* input-file.c: Likewise.
+	* input-scrub.c: Likewise.
+	* macro.c: Likewise.
+	* output-file.c: Likewise.
+	* read.c: Likewise.
+	* sb.c: Likewise.
+	* config/bfin-lex.l: Likewise.
+	* config/obj-coff.h: Likewise.
+	* config/obj-elf.h: Likewise.
+	* config/obj-som.h: Likewise.
+	* config/tc-arc.c: Likewise.
+	* config/tc-arm.c: Likewise.
+	* config/tc-avr.c: Likewise.
+	* config/tc-bfin.c: Likewise.
+	* config/tc-cris.c: Likewise.
+	* config/tc-d10v.c: Likewise.
+	* config/tc-d30v.c: Likewise.
+	* config/tc-dlx.h: Likewise.
+	* config/tc-fr30.c: Likewise.
+	* config/tc-frv.c: Likewise.
+	* config/tc-h8300.c: Likewise.
+	* config/tc-hppa.c: Likewise.
+	* config/tc-i370.c: Likewise.
+	* config/tc-i860.c: Likewise.
+	* config/tc-i960.c: Likewise.
+	* config/tc-ip2k.c: Likewise.
+	* config/tc-iq2000.c: Likewise.
+	* config/tc-m32c.c: Likewise.
+	* config/tc-m32r.c: Likewise.
+	* config/tc-maxq.c: Likewise.
+	* config/tc-mcore.c: Likewise.
+	* config/tc-mips.c: Likewise.
+	* config/tc-mmix.c: Likewise.
+	* config/tc-mn10200.c: Likewise.
+	* config/tc-mn10300.c: Likewise.
+	* config/tc-msp430.c: Likewise.
+	* config/tc-mt.c: Likewise.
+	* config/tc-ns32k.c: Likewise.
+	* config/tc-openrisc.c: Likewise.
+	* config/tc-ppc.c: Likewise.
+	* config/tc-s390.c: Likewise.
+	* config/tc-sh.c: Likewise.
+	* config/tc-sh64.c: Likewise.
+	* config/tc-sparc.c: Likewise.
+	* config/tc-tic30.c: Likewise.
+	* config/tc-tic4x.c: Likewise.
+	* config/tc-tic54x.c: Likewise.
+	* config/tc-v850.c: Likewise.
+	* config/tc-vax.c: Likewise.
+	* config/tc-xc16x.c: Likewise.
+	* config/tc-xstormy16.c: Likewise.
+	* config/tc-xtensa.c: Likewise.
+	* config/tc-z80.c: Likewise.
+	* config/tc-z8k.c: Likewise.
+	* macro.h: Don't include sb.h or ansidecl.h.
+	* sb.h: Don't include stdio.h or ansidecl.h.
+	* cond.c: Include sb.h.
+	* itbl-lex.l: Include as.h instead of other system headers.
+	* itbl-parse.y: Likewise.
+	* itbl-ops.c: Similarly.
+	* itbl-ops.h: Don't include as.h or ansidecl.h.
+	* config/bfin-defs.h: Don't include bfd.h or as.h.
+	* config/bfin-parse.y: Include as.h instead of other system headers.
+
+2006-06-06  Ben Elliston  <bje@au.ibm.com>
+	    Anton Blanchard  <anton@samba.org>
+
+	* config/tc-ppc.c (parse_cpu): Handle "-mpower6".
+	(md_show_usage): Document it.
+	(ppc_setup_opcodes): Test power6 opcode flag bits.
+	* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
+
+2006-06-06  Thiemo Seufer  <ths@mips.com>
+            Chao-ying Fu  <fu@mips.com>
+
+	* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
+	(CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
+	(macro_build): Update comment.
+	(mips_ip): Allow DSP64 instructions for MIPS64R2.
+	(mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
+	CPU_HAS_MDMX.
+	(mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
+	MIPS_CPU_ASE_MDMX flags for sb1.
+
+2006-06-05  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
+	appropriate.
+	(mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
+	(mips_ip): Make overflowed/underflowed constant arguments in DSP
+	and MT instructions a fatal error. Use INSERT_OPERAND where
+	appropriate. Improve warnings for break and wait code overflows.
+	Use symbolic constant of OP_MASK_COPZ.
+	(mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
+
+2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* po/Make-in (top_builddir): Define.
+
+2006-06-02  Joseph S. Myers  <joseph@codesourcery.com>
+
+	* doc/Makefile.am (TEXI2DVI): Define.
+	* doc/Makefile.in: Regenerate.
+	* doc/c-arc.texi: Fix typo.
+
+2006-06-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-ieee.c: Delete.
+	* config/obj-ieee.h: Delete.
+	* Makefile.am (OBJ_FORMATS): Remove ieee.
+	(OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
+	(obj-ieee.o): Remove rule.
+	* Makefile.in: Regenerate.
+	* configure.in (atof): Remove tahoe.
+	(OBJ_MAYBE_IEEE): Don't define.
+	* configure: Regenerate.
+	* config.in: Regenerate.
+	* doc/Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
+	and LIBINTL_DEP everywhere.
+	(INTLLIBS): Remove.
+	(INCLUDES, DEP_INCLUDES): Use @INCINTL@.
+	* acinclude.m4: Include new gettext macros.
+	* configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
+	Remove local code for po/Makefile.
+	* Makefile.in, configure, doc/Makefile.in: Regenerated.
+
+2006-05-30  Nick Clifton  <nickc@redhat.com>
+
+	* po/es.po: Updated Spanish translation.
+
+2006-05-06  Denis Chertykov  <denisc@overta.ru>
+
+	* doc/c-avr.texi: New file.
+	* doc/Makefile.am (CPU_DOCS): Add c-avr.texi
+	* doc/all.texi: Set AVR
+	* doc/as.texinfo: Include c-avr.texi
+
+2006-05-28  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (check_macfunc): Loose the condition of
+	calling check_multiply_halfregs ().
+
+2006-05-25  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (asm_1): Better check and deal with
+	vector and scalar Multiply 16-Bit Operands instructions.
+
+2006-05-24  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-hppa.c: Convert to ISO C90 format.
+	* config/tc-hppa.h: Likewise.
+
+2006-05-24  Carlos O'Donell  <carlos@systemhalted.org>
+	    Randolph Chung  <randolph@tausq.org>
+
+	* config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
+	is_tls_ieoff, is_tls_leoff): Define.
+	(fix_new_hppa): Handle TLS.
+	(cons_fix_new_hppa): Likewise.
+	(pa_ip): Likewise.
+	(md_apply_fix): Handle TLS relocs.
+	* config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
+
+2006-05-24  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
+
+2006-05-23  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	[ gas/ChangeLog ]
+	* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
+	(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
+	ISA_HAS_MXHC1): New macros.
+	(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
+	ISA_HAS_64BIT_REGS.  Formatting fixes.  Improved comments.
+	(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
+	(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
+	MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
+	(mips_after_parse_args): Change default handling of float register
+	size to account for 32bit code with 64bit FP. Better sanity checking
+	of ISA/ASE/ABI option combinations.
+	(s_mipsset): Support switching of GPR and FPR sizes via
+	.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
+	options.
+	(mips_elf_final_processing): We should record the use of 64bit FP
+	registers in 32bit code but we don't, because ELF header flags are
+	a scarce ressource.
+	(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
+	extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
+	24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
+	(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
+	* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
+	missing -march options. Document .set arch=CPU. Move .set smartmips
+	to ASE page. Use @code for .set FOO examples.
+
+2006-05-23  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/tc-bfin.c (bfin_start_line_hook): Bump line counters
+	if needed.
+
+2006-05-23  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-defs.h (bfin_equals): Remove declaration.
+	* config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
+	* config/tc-bfin.c (bfin_name_is_register): Remove.
+	(bfin_equals): Remove.
+	* config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
+	(bfin_name_is_register): Remove declaration.
+
+2006-05-19  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
+	(mips_oddfpreg_ok): New function.
+	(mips_ip): Use it.
+
+2006-05-19  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
+	* config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
+	ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
+	(regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
+	RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
+	RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
+	FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
+	N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
+	SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
+	MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
+	reg_names_o32, reg_names_n32n64): Define register classes.
+	(reg_lookup): New function, use register classes.
+	(md_begin): Reserve register names in the symbol table. Simplify
+	OBJ_ELF defines.
+	(mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
+	Use reg_lookup.
+	(mips16_ip): Use reg_lookup.
+	(tc_get_register): Likewise.
+	(tc_mips_regname_to_dw2regnum): New function.
+
+2006-05-19  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
+	Un-constify string argument.
+	* config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
+	Likewise.
+
+2006-05-19  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/config/tc-m68k.c (m68k_init_arch): Move checking of
+	cfloat/m68881 to correct architecture before using it.
+
+2006-05-16  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
+	constant values.
+
+2006-05-15  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_adjust_symtab): Use
+	bfd_is_arm_special_symbol_name.
+
+2006-05-15  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
+	xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
+	xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
+	Handle errors from calls to xtensa_opcode_is_* functions.
+
+2006-05-14  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (macro_build): Test for currently active
+	mips16 option.
+	(mips16_ip): Reject invalid opcodes.
+
+2006-05-11  Carlos O'Donell  <carlos@codesourcery.com>
+
+	* doc/as.texinfo: Rename "Index" to "AS Index",
+	and "ABORT" to "ABORT (COFF)".
+
+2006-05-11  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_half): New function.
+	(operand_parse_code): Remove OP_Iffff.  Add OP_HALF.
+	(parse_operands): Ditto.
+	(do_mov16): Reject invalid relocations.
+	(do_t_mov16): Ditto.  Use Thumb reloc numbers.
+	(insns): Replace Iffff with HALF.
+	(md_apply_fix): Add MOVW and MOVT relocs.
+	(tc_gen_reloc): Ditto.
+	* doc/c-arm.texi: Document relocation operators
+
+2006-05-11  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
+
+2006-05-11  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (append_insn): Don't check the range of j or
+	jal addresses.
+
+2006-05-11  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* config/tc-arm.c (md_pcrel_from_section): Force a bias for
+	relocs against external symbols for WinCE targets.
+	(md_apply_fix): Likewise.
+
+2006-05-09  David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (append_insn): Only warn about an out-of-range
+	j or jal address.
+
+2006-05-09  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups
+	against symbols which are not going to be placed into the symbol
+	table.
+
+2006-05-09  Ben Elliston  <bje@au.ibm.com>
+
+	* expr.c (operand): Remove `if (0 && ..)' statement and
+	subsequently unused target_op label.  Collapse `if (1 || ..)'
+	statement.
+	* app.c (do_scrub_chars): Remove unused case 0, as it is handled
+	separately above the switch.
+
+2006-05-08  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/2623
+	* config/tc-msp430.c (line_separator_character): Define as |.
+
+2006-05-08  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
+	(mips_opts): Likewise.
+	(file_ase_smartmips): New variable.
+	(ISA_HAS_ROR): SmartMIPS implements rotate instructions.
+	(macro_build): Handle SmartMIPS instructions.
+	(mips_ip): Likewise.
+	(md_longopts): Add argument handling for smartmips.
+	(md_parse_options, mips_after_parse_args): Likewise.
+	(s_mipsset): Add .set smartmips support.
+	(md_show_usage): Document -msmartmips/-mno-smartmips.
+	* doc/as.texinfo: Document -msmartmips/-mno-smartmips and
+	.set smartmips.
+	* doc/c-mips.texi: Likewise.
+
+2006-05-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.c (relax_segment): Add pass count arg.  Don't error on
+	negative org/space on first two passes.
+	(relax_seg_info): New struct.
+	(relax_seg, write_object_file): Adjust.
+	* write.h (relax_segment): Update prototype.
+
+2006-05-05  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
+	checking.
+	(do_neon_mov): Enable several VMOV variants for VFP. Add suitable
+	architecture version checks.
+	(insns): Allow overlapping instructions to be used in VFP mode.
+
+2006-05-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2598
+	* config/obj-elf.c (obj_elf_change_section): Allow user
+	specified SHF_ALPHA_GPREL.
+
+2006-05-05  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* gas/config/tc-avr.h (TC_VALIDATE_FIX): Define.  Disable fixups
+	for PMEM related expressions.
+
+2006-05-05  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/2582
+	* dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro.  Handles the
+	insertion of a directory separator character into a string at a
+	given offset.  Uses heuristics to decide when to use a backslash
+	character rather than a forward-slash character.
+	(dwarf2_directive_loc): Use the macro.
+	(out_debug_info): Likewise.
+
+2006-05-05  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (macro_build): Add case 'k' to handle cache
+	instruction.
+	(macro): Add new case M_CACHE_AB.
+
+2006-05-04  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
+	(opcode_lookup): Issue a warning for opcode with
+	OT_cinfix3_deprecated.  Otherwise treat OT_cinfix3_deprecated
+	identical to OT_cinfix3.
+	(TxC3w, TC3w, tC3w): New.
+	(insns): Use tC3w and TC3w for comparison instructions with
+	's' suffix.
+
+2006-05-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* subsegs.h (struct frchain): Delete frch_seg.
+	(frchain_root): Delete.
+	(seg_info): Define as macro.
+	* subsegs.c (frchain_root): Delete.
+	(abs_seg_info, und_seg_info, absolute_frchain): Delete.
+	(subsegs_begin, subseg_change): Adjust for above.
+	(subseg_set_rest): Likewise.  Add new frchain structs to seginfo
+	rather than to one big list.
+	(subseg_get): Don't special case abs, und sections.
+	(subseg_new, subseg_force_new): Don't set frchainP here.
+	(seg_info): Delete.
+	(subsegs_print_statistics): Adjust frag chain control list traversal.
+	* debug.c (dmp_frags):  Likewise.
+	* dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
+	at frchain_root.  Make use of known frchain ordering.
+	(last_frag_for_seg): Likewise.
+	(get_frag_fix): Likewise.  Add seg param.
+	(process_entries, out_debug_aranges): Adjust get_frag_fix calls.
+	* write.c (chain_frchains_together_1): Adjust for struct frchain.
+	(SUB_SEGMENT_ALIGN): Likewise.
+	(subsegs_finish): Adjust frchain list traversal.
+	* config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
+	(xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
+	(xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
+	(xtensa_fix_b_j_loop_end_frags): Likewise.
+	(xtensa_fix_close_loop_end_frags): Likewise.
+	(xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
+	(retrieve_segment_info): Delete frch_seg initialisation.
+
+2006-05-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
+	* config/obj-elf.h (obj_sec_set_private_data): Delete.
+	* config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
+	* config/tc-mn10300.c (tc_gen_reloc): Likewise.
+
+2006-05-02  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
+	here.
+	(md_apply_fix3): Multiply offset by 4 here for
+	BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
+
+2006-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+	    Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (output_invalid_buf): Change size for
+	unsigned char.
+	* config/tc-tic30.c (output_invalid_buf): Likewise.
+
+	* config/tc-i386.c (output_invalid): Cast none-ascii char to
+	unsigned char.
+	* config/tc-tic30.c (output_invalid): Likewise.
+
+2006-05-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* doc/Makefile.am (AM_MAKEINFOFLAGS): New.
+	(TEXI2POD): Use AM_MAKEINFOFLAGS.
+	(asconfig.texi): Don't set top_srcdir.
+	* doc/as.texinfo: Don't use top_srcdir.
+	* aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
+
+2006-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (output_invalid_buf): Change size to 16.
+	* config/tc-tic30.c (output_invalid_buf): Likewise.
+
+	* config/tc-i386.c (output_invalid): Use snprintf instead of
+	sprintf.
+	* config/tc-ia64.c (declare_register_set): Likewise.
+	(emit_one_bundle): Likewise.
+	(check_dependencies): Likewise.
+	* config/tc-tic30.c (output_invalid): Likewise.
+
+2006-05-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_optimize_expr): New function.
+	* config/tc-arm.h (md_optimize_expr): Define
+	(arm_optimize_expr): Add prototype.
+	(TC_FORCE_RELOCATION_SUB_SAME): Define.
+
+2006-05-02  Ben Elliston  <bje@au.ibm.com>
+
+	* config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
+	field unsigned.
+
+	* sb.h (sb_list_vector): Move to sb.c.
+	* sb.c (free_list): Use type of sb_list_vector directly.
+	(sb_build): Fix off-by-one error in assertion about `size'.
+
+2006-05-01  Ben Elliston  <bje@au.ibm.com>
+
+	* listing.c (listing_listing): Remove useless loop.
+	* macro.c (macro_expand): Remove is_positional local variable.
+	* read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
+	and simplify surrounding expressions, where possible.
+	(assign_symbol): Likewise.
+	(s_weakref): Likewise.
+	* symbols.c (colon): Likewise.
+
+2006-05-01  James Lemke  <jwlemke@wasabisystems.com>
+
+	* subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
+
+2006-04-30  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (validate_mips_insn): Handling of udi cases.
+	(mips_immed): New table that records various handling of udi
+	instruction patterns.
+	(mips_ip): Adds udi handling.
+
+2006-04-28  Alan Modra  <amodra@bigpond.net.au>
+
+	* dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
+	of list rather than beginning.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
+	(is_quarter_float): Rename from above. Simplify slightly.
+	(parse_qfloat_immediate): Parse a "quarter precision" floating-point
+	number.
+	(parse_neon_mov): Parse floating-point constants.
+	(neon_qfloat_bits): Fix encoding.
+	(neon_cmode_for_move_imm): Tweak to use floating-point encoding in
+	preference to integer encoding when using the F32 type.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
+	zero-initialising structures containing it will lead to invalid types).
+	(arm_it): Add vectype to each operand.
+	(NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
+	defined field.
+	(neon_typed_alias): New structure. Extra information for typed
+	register aliases.
+	(reg_entry): Add neon type info field.
+	(arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
+	Break out alternative syntax for coprocessor registers, etc. into...
+	(arm_reg_alt_syntax): New function. Alternate syntax handling broken
+	out from arm_reg_parse.
+	(parse_neon_type): Move. Return SUCCESS/FAIL.
+	(first_error): New function. Call to ensure first error which occurs is
+	reported.
+	(parse_neon_operand_type): Parse exactly one type.
+	(NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
+	(parse_typed_reg_or_scalar): New function. Handle core of both
+	arm_typed_reg_parse and parse_scalar.
+	(arm_typed_reg_parse): Parse a register with an optional type.
+	(NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
+	result.
+	(parse_scalar): Parse a Neon scalar with optional type.
+	(parse_reg_list): Use first_error.
+	(parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
+	(neon_alias_types_same): New function. Return true if two (alias) types
+	are the same.
+	(parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
+	of elements.
+	(insert_reg_alias): Return new reg_entry not void.
+	(insert_neon_reg_alias): New function. Insert type/index information as
+	well as register for alias.
+	(create_neon_reg_alias): New function. Parse .dn/.qn directives and
+	make typed register aliases accordingly.
+	(s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
+	of line.
+	(s_unreq): Delete type information if present.
+	(s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
+	(s_arm_unwind_save_mmxwcg): Likewise.
+	(s_arm_unwind_movsp): Likewise.
+	(s_arm_unwind_setfp): Likewise.
+	(parse_shift): Likewise.
+	(parse_shifter_operand): Likewise.
+	(parse_address): Likewise.
+	(parse_tb): Likewise.
+	(tc_arm_regname_to_dw2regnum): Likewise.
+	(md_pseudo_table): Add dn, qn.
+	(parse_neon_mov): Handle typed operands.
+	(parse_operands): Likewise.
+	(neon_type_mask): Add N_SIZ.
+	(N_ALLMODS): New macro.
+	(neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
+	(el_type_of_type_chk): Add some safeguards.
+	(modify_types_allowed): Fix logic bug.
+	(neon_check_type): Handle operands with types.
+	(neon_three_same): Remove redundant optional arg handling.
+	(do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
+	(do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
+	(do_neon_step): Adjust accordingly.
+	(neon_cmode_for_logic_imm): Use first_error.
+	(do_neon_bitfield): Call neon_check_type.
+	(neon_dyadic): Rename to...
+	(neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
+	to allow modification of type of the destination.
+	(do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
+	(do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
+	(do_neon_compare): Make destination be an untyped bitfield.
+	(neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
+	(neon_mul_mac): Return early in case of errors.
+	(neon_move_immediate): Use first_error.
+	(neon_mac_reg_scalar_long): Fix type to include scalar.
+	(do_neon_dup): Likewise.
+	(do_neon_mov): Likewise (in several places).
+	(do_neon_tbl_tbx): Fix type.
+	(do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
+	(do_neon_ld_dup): Exit early in case of errors and/or use
+	first_error.
+	(opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
+	Handle .dn/.qn directives.
+	(REGDEF): Add zero for reg_entry neon field.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (limits.h): Include.
+	(fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
+	(fpu_vfp_v3_or_neon_ext): Declare constants.
+	(neon_el_type): New enumeration of types for Neon vector elements.
+	(neon_type_el): New struct. Define type and size of a vector element.
+	(NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
+	instruction.
+	(neon_type): Define struct. The type of an instruction.
+	(arm_it): Add 'vectype' for the current instruction.
+	(isscalar, immisalign, regisimm, isquad): New predicates for operands.
+	(vfp_sp_reg_pos): Rename to...
+	(vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
+	tags.
+	(arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
+	(Neon D or Q register).
+	(reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
+	register.
+	(GE_OPT_PREFIX_BIG): Define constant, for use in...
+	(my_get_expression): Allow above constant as argument to accept
+	64-bit constants with optional prefix.
+	(arm_reg_parse): Add extra argument to return the specific type of
+	register in when either a D or Q register (REG_TYPE_NDQ) is
+	requested. Can be NULL.
+	(parse_scalar): New function. Parse Neon scalar (vector reg and index).
+	(parse_reg_list): Update for new arm_reg_parse args.
+	(parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
+	(parse_neon_el_struct_list): New function. Parse element/structure
+	register lists for VLD<n>/VST<n> instructions.
+	(s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
+	(s_arm_unwind_save_mmxwr): Likewise.
+	(s_arm_unwind_save_mmxwcg): Likewise.
+	(s_arm_unwind_movsp): Likewise.
+	(s_arm_unwind_setfp): Likewise.
+	(parse_big_immediate): New function. Parse an immediate, which may be
+	64 bits wide. Put results in inst.operands[i].
+	(parse_shift): Update for new arm_reg_parse args.
+	(parse_address): Likewise. Add parsing of alignment specifiers.
+	(parse_neon_mov): Parse the operands of a VMOV instruction.
+	(operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
+	OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
+	OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
+	OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
+	(parse_operands): Handle new codes above.
+	(encode_arm_vfp_sp_reg): Rename to...
+	(encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
+	selected VFP version only supports D0-D15.
+	(do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
+	(do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
+	(do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
+	(do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
+	encode_arm_vfp_reg name, and allow 32 D regs.
+	(do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
+	(do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
+	regs.
+	(do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
+	(do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
+	constant-load and conversion insns introduced with VFPv3.
+	(neon_tab_entry): New struct.
+	(NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
+	those which are the targets of pseudo-instructions.
+	(neon_opc): Enumerate opcodes, use as indices into...
+	(neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
+	(NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
+	(NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
+	(NEON_ENC_DUP): Define meaningful helper macros to look up values in
+	neon_enc_tab.
+	(neon_shape): Enumerate shapes (permitted register widths, etc.) for
+	Neon instructions.
+	(neon_type_mask): New. Compact type representation for type checking.
+	(N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
+	permitted type combinations.
+	(N_IGNORE_TYPE): New macro.
+	(neon_check_shape): New function. Check an instruction shape for
+	multiple alternatives. Return the specific shape for the current
+	instruction.
+	(neon_modify_type_size): New function. Modify a vector type and size,
+	depending on the bit mask in argument 1.
+	(neon_type_promote): New function. Convert a given "key" type (of an
+	operand) into the correct type for a different operand, based on a bit
+	mask.
+	(type_chk_of_el_type): New function. Convert a type and size into the
+	compact representation used for type checking.
+	(el_type_of_type_ckh): New function. Reverse of above (only when a
+	single bit is set in the bit mask).
+	(modify_types_allowed): New function. Alter a mask of allowed types
+	based on a bit mask of modifications.
+	(neon_check_type): New function. Check the type of the current
+	instruction against the variable argument list. The "key" type of the
+	instruction is returned.
+	(neon_dp_fixup): New function. Fill in and modify instruction bits for
+	a Neon data-processing instruction depending on whether we're in ARM
+	mode or Thumb-2 mode.
+	(neon_logbits): New function.
+	(neon_three_same, neon_two_same, do_neon_dyadic_i_su)
+	(do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
+	(do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
+	(neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
+	(neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
+	(do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
+	(do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
+	(do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
+	(do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
+	(neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
+	(do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
+	(do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
+	(do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
+	(do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
+	(do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
+	(neon_move_immediate, do_neon_mvn, neon_mixed_length)
+	(do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
+	(do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
+	(do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
+	(do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
+	(do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
+	(do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
+	(do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
+	(neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
+	(do_neon_ldx_stx): New functions. Neon bit encoding and encoding
+	helpers.
+	(parse_neon_type): New function. Parse Neon type specifier.
+	(opcode_lookup): Allow parsing of Neon type specifiers.
+	(REGNUM2, REGSETH, REGSET2): New macros.
+	(reg_names): Add new VFPv3 and Neon registers.
+	(NUF, nUF, NCE, nCE): New macros for opcode table.
+	(insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
+	fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
+	fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
+	Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
+	vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
+	vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
+	vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
+	vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr,  v{r}sra, vsli,
+	vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
+	vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
+	vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
+	vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
+	vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
+	vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
+	fto[us][lh][sd].
+	(tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
+	(arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
+	(arm_option_cpu_value): Add vfp3 and neon.
+	(aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
+	VFPv1 attribute.
+
+2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
+	syntax instead of hardcoded opcodes with ".w18" suffixes.
+	(wide_branch_opcode): New.
+	(build_transition): Use it to check for wide branch opcodes with
+	either ".w18" or ".w15" suffixes.
+
+2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_create_literal_symbol,
+	xg_assemble_literal, xg_assemble_literal_space): Do not set the
+	frag's is_literal flag.
+
+2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
+
+2006-04-23  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
+	config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
+	config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
+	config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
+	config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
+
+2005-04-20  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
+	all targets.
+	(md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
+
+2006-04-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am (CPU_TYPES): Add maxq and mt.  Sort.
+	(CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
+	Make some cpus unsupported on ELF.  Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2006-04-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* configure.in (--enable-targets): Indent help message.
+	* configure: Regenerate.
+
+2006-04-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2533
+	* config/tc-i386.c (i386_immediate): Check illegal immediate
+	register operand.
+
+2006-04-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-i386.c: Formatting.
+	(output_disp, output_imm): ISO C90 params.
+
+	* frags.c (frag_offset_fixed_p): Constify args.
+	* frags.h (frag_offset_fixed_p): Ditto.
+
+	* config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
+	(COFF_MAGIC): Delete.
+
+	* config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
+
+2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* po/POTFILES.in: Regenerated.
+
+2006-04-16  Mark Mitchell  <mark@codesourcery.com>
+
+	* doc/as.texinfo: Mention that some .type syntaxes are not
+	supported on all architectures.
+
+2006-04-14  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (emit_single_op): Do not relax MOVI
+	instructions when such transformations have been disabled.
+
+2006-04-10  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
+	symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
+	(xtensa_fix_close_loop_end_frags): Use the recorded values instead of
+	decoding the loop instructions.  Remove current_offset variable.
+	(xtensa_fix_short_loop_frags): Likewise.
+	(min_bytes_to_other_loop_end): Remove current_offset argument.
+
+2006-04-09  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* config/tc-z80.c (z80_optimize_expr): Removed.
+	* config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
+
+2006-04-07  Joerg Wunsch <j.gnu@uriah.heep.sax.de>
+
+	* gas/config/tc-avr.c (mcu_types): Add support for attiny261,
+	attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
+	attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
+	atmega644, atmega329, atmega3290, atmega649, atmega6490,
+	atmega406, atmega640, atmega1280, atmega1281, at90can32,
+	at90can64, at90usb646, at90usb647, at90usb1286 and
+	at90usb1287.
+	Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_operands): Set default error message.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (THUMB2_LOAD_BIT): Define.
+	(move_or_literal_pool): Handle Thumb-2 instructions.
+	(do_t_ldst): Call move_or_literal_pool for =N addressing modes.
+
+2006-04-07  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 2512.
+	* config/tc-i386.c (match_template): Move 64-bit operand tests
+	inside loop.
+
+2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
+
+	* po/Make-in: Add install-html target.
+	* Makefile.am: Add install-html and install-html-recursive targets.
+	* Makefile.in: Regenerate.
+	* configure.in: AC_SUBST datarootdir, docdir, htmldir.
+	* configure: Regenerate.
+	* doc/Makefile.am: Add install-html and install-html-am targets.
+	* doc/Makefile.in: Regenerate.
+
+2006-04-06  Alan Modra  <amodra@bigpond.net.au>
+
+	* frags.c (frag_offset_fixed_p): Reinitialise offset before
+	second scan.
+
+2006-04-05  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
+	(GOTT_BASE, GOTT_INDEX): New.
+	(tc_gen_reloc): Don't alter relocations against GOTT_BASE and
+	GOTT_INDEX when generating VxWorks PIC.
+	* configure.tgt (sparc*-*-vxworks*): Remove this special case;
+	use the generic *-*-vxworks* stanza instead.
+
+2006-04-04  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 997
+	* frags.c (frag_offset_fixed_p): New function.
+	* frags.h (frag_offset_fixed_p): Declare.
+	* expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
+	(resolve_expression): Likewise.
+
+2006-04-03  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (init_op_placement_info_table): Check for formats
+	of the same length but different numbers of slots.
+
+2006-03-30  Andreas Schwab  <schwab@suse.de>
+
+	* configure.in: Fix help string for --enable-targets option.
+	* configure: Regenerate.
+
+2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/config/tc-m68k.c (find_cf_chip): Merge into ...
+	(m68k_ip): ... here.  Use for all chips.  Protect against buffer
+	overrun and avoid excessive copying.
+
+	* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
+	m68020_control_regs, m68040_control_regs, m68060_control_regs,
+	mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
+	mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
+	mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
+	(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
+	mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
+	mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
+	mcf5282_ctrl, mcfv4e_ctrl): ... these.
+	(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
+	(struct m68k_cpu): Change chip field to control_regs.
+	(current_chip): Remove.
+	(control_regs): New.
+	(m68k_archs, m68k_extensions): Adjust.
+	(m68k_cpus): Reorder to be in cpu number order.  Adjust.
+	(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
+	(find_cf_chip): Reimplement for new organization of cpu table.
+	(select_control_regs): Remove.
+	(mri_chip): Adjust.
+	(struct save_opts): Save control regs, not chip.
+	(s_save, s_restore): Adjust.
+	(m68k_lookup_cpu): Give deprecated warning when necessary.
+	(m68k_init_arch): Adjust.
+	(md_show_usage): Adjust for new cpu table organization.
+
+2006-03-25  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
+	* config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
+	* config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
+	"elf/bfin.h".
+	(GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
+	(any_gotrel): New rule.
+	(got): Use it, and create Expr_Node_GOT_Reloc nodes.
+	* config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
+	"elf/bfin.h".
+	(DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
+	(bfin_pic_ptr): New function.
+	(md_pseudo_table): Add it for ".picptr".
+	(OPTION_FDPIC): New macro.
+	(md_longopts): Add -mfdpic.
+	(md_parse_option): Handle it.
+	(md_begin): Set BFD flags.
+	(md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
+	(bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
+	us for GOT relocs.
+	* Makefile.am (bfin-parse.o): Update dependencies.
+	(DEPTC_bfin_elf): Likewise.
+	* Makefile.in: Regenerate.
+
+2006-03-25  Richard Sandiford  <richard@codesourcery.com>
+
+	* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
+	mcfemac instead of mcfmac.
+
+2006-03-23  Michael Matz  <matz@suse.de>
+
+	* config/tc-i386.c (type_names): Correct placement of 'static'.
+	(reloc): Map some more relocs to their 64 bit counterpart when
+	size is 8.
+	(output_insn): Work around breakage if DEBUG386 is defined.
+	(output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
+	needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
+	BFD_RELOC_X86_64_GOTPC32.  Also x86-64 handles pcrel addressing
+	different from i386.
+	(output_imm): Ditto.
+	(lex_got): Recognize @PLTOFF and @GOTPLT.  Make @GOT accept also
+	Imm64.
+	(md_convert_frag): Jumps can now be larger than 2GB away, error
+	out in that case.
+	(tc_gen_reloc): New relocs are passed through.  BFD_RELOC_64
+	and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
+
+2006-03-22  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Phil Edwards  <phil@codesourcery.com>
+	    Zack Weinberg  <zack@codesourcery.com>
+	    Mark Mitchell  <mark@codesourcery.com>
+	    Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-mips.c (mips_target_format): Handle vxworks targets.
+	(md_begin): Complain about -G being used for PIC.  Don't change
+	the text, data and bss alignments on VxWorks.
+	(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
+	generating VxWorks PIC.
+	(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
+	(macro): Likewise, but do not treat la $25 specially for
+	VxWorks PIC, and do not handle jal.
+	(OPTION_MVXWORKS_PIC): New macro.
+	(md_longopts): Add -mvxworks-pic.
+	(md_parse_option): Don't complain about using PIC and -G together here.
+	Handle OPTION_MVXWORKS_PIC.
+	(md_estimate_size_before_relax): Always use the first relaxation
+	sequence on VxWorks.
+	* config/tc-mips.h (VXWORKS_PIC): New.
+
+2006-03-21  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
+
+2006-03-21  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
+	(xtensa_setup_hw_workarounds): Set this new flag for older hardware.
+	(get_loop_align_size): New.
+	(xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
+	(xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
+	(get_text_align_power): Rewrite to handle inputs in the range 2-8.
+	(get_noop_aligned_address): Use get_loop_align_size.
+	(get_aligned_diff): Likewise.
+
+2006-03-21  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
+
+2006-03-20  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
+	(do_t_branch): Encode branches inside IT blocks as unconditional.
+	(do_t_cps): New function.
+	(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
+	do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
+	(opcode_lookup): Allow conditional suffixes on all instructions in
+	Thumb mode.
+	(md_assemble): Advance condexec state before checking for errors.
+	(insns): Use do_t_cps.
+
+2006-03-20  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
+	outputting the insn.
+
+2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+
+	* config/tc-vax.c: Update copyright year.
+	* config/tc-vax.h: Likewise.
+
+2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+
+	* config/tc-vax.c (md_chars_to_number): Used only locally, so
+	make it static.
+	* config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
+
+2006-03-17  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Add ldm and stm.
+
+2006-03-17  Ben Elliston  <bje@au.ibm.com>
+
+	PR gas/2446
+	* doc/as.texinfo (Ident): Document this directive more thoroughly.
+
+2006-03-16  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Add "svc".
+
+2006-03-13  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
+	flag and avoid double underscore prefixes.
+
+2006-03-10  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_begin): Handle EABIv5.
+	(arm_eabis): Add EF_ARM_EABI_VER5.
+	* doc/c-arm.texi: Document -meabi=5.
+
+2006-03-10  Ben Elliston  <bje@au.ibm.com>
+
+	* app.c (do_scrub_chars): Simplify string handling.
+
+2006-03-07  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Zack Weinberg  <zack@codesourcery.com>
+	    Nathan Sidwell  <nathan@codesourcery.com>
+	    Paul Brook  <paul@codesourcery.com>
+	    Ricardo Anguiano  <anguiano@codesourcery.com>
+	    Phil Edwards  <phil@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Install a value of zero into a
+	BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
+	R_ARM_ABS12 reloc.
+	(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
+	relocs, but adjust by md_pcrel_from_section.  Create R_ARM_ABS12
+	relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
+
+2006-03-06  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
+	even when using the text-section-literals option.
+
+2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
+	and cf.
+	(m68k_ip): <case 'J'> Check we have some control regs.
+	(md_parse_option): Allow raw arch switch.
+	(m68k_init_arch): Better detection of arch/cpu mismatch.  Detect
+	whether 68881 or cfloat was meant by -mfloat.
+	(md_show_usage): Adjust extension display.
+	(m68k_elf_final_processing): Adjust.
+
+2006-03-03  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* config/tc-avr.c (avr_mod_hash_value): New function.
+	(md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
+	BFD_RELOC_MS8_LDI for hlo8() and hhi8()
+	(md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
+	instead of int avr_ldi_expression: use avr_mod_hash_value instead
+	of (int).
+	(tc_gen_reloc): Handle substractions of symbols, if possible do
+	fixups, abort otherwise.
+	* config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
+	tc_fix_adjustable): Define.
+
+2006-03-02  James E Wilson  <wilson@specifix.com>
+
+	* config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
+	change the template, then clear md.slot[curr].end_of_insn_group.
+
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
+
+	* macro.c (get_any_string): Don't insert quotes for <>-quoted input.
+
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
+
+	PR/1070
+	* macro.c (getstring): Don't treat parentheses special anymore.
+	(get_any_string): Don't consider '(' and ')' as quoting anymore.
+	Special-case '(', ')', '[', and ']' when dealing with non-quoting
+	characters.
+
+2006-02-28  Mat <mat@csail.mit.edu>
+
+	* dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
+
+2006-02-27  Jakub Jelinek  <jakub@redhat.com>
+
+	* dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
+	field.
+	(CFI_signal_frame): Define.
+	(cfi_pseudo_table): Add .cfi_signal_frame.
+	(dot_cfi): Handle CFI_signal_frame.
+	(output_cie): Handle cie->signal_frame.
+	(select_cie_for_fde): Don't share CIE if signal_frame flag is
+	different.  Copy signal_frame from FDE to newly created CIE.
+	* doc/as.texinfo: Document .cfi_signal_frame.
+
+2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
+
+	* doc/Makefile.am: Add html target.
+	* doc/Makefile.in: Regenerate.
+	* po/Make-in: Add html target.
+
+2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (output_insn): Support Intel Merom New
+	Instructions.
+
+	* config/tc-i386.h (CpuMNI): New.
+	(CpuUnknownFlags): Add CpuMNI.
+
+2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
+
+	* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
+	(hpriv_reg_table): New table for hyperprivileged registers.
+	(sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
+	register encoding.
+
+2006-02-24  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
+	(tc_gen_reloc): Don't define.
+	* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
+	(OPTION_LINKRELAX): New.
+	(md_longopts): Add it.
+	(m32c_relax): New.
+	(md_parse_options): Set it.
+	(md_assemble): Emit relaxation relocs as needed.
+	(md_convert_frag): Emit relaxation relocs as needed.
+	(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
+	(m32c_apply_fix): New.
+	(tc_gen_reloc): New.
+	(m32c_force_relocation): Force out jump relocs when relaxing.
+	(m32c_fix_adjustable): Return false if relaxing.
+
+2006-02-24  Paul Brook  <paul@codesourcery.com>
+
+	* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
+	arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
+	(struct asm_barrier_opt): Define.
+	(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
+	(parse_psr): Accept V7M psr names.
+	(parse_barrier): New function.
+	(enum operand_parse_code): Add OP_oBARRIER.
+	(parse_operands): Implement OP_oBARRIER.
+	(do_barrier): New function.
+	(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
+	(do_t_cpsi): Add V7M restrictions.
+	(do_t_mrs, do_t_msr): Validate V7M variants.
+	(md_assemble): Check for NULL variants.
+	(v7m_psrs, barrier_opt_names): New tables.
+	(insns): Add V7 instructions.  Mark V6 instructions absent from V7M.
+	(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
+	(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
+	(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
+	(struct cpu_arch_ver_table): Define.
+	(cpu_arch_ver): New.
+	(aeabi_set_public_attributes): Use cpu_arch_ver.  Set
+	Tag_CPU_arch_profile.
+	* doc/c-arm.texi: Document new cpu and arch options.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c: Update copyright years.
+
+2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (specify_resource): Add the rule 17 from
+	SDM 2.2.
+
+2005-02-22  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_pld): Remove incorrect write to
+	inst.instruction.
+	(encode_thumb32_addr_mode): Use correct operand.
+
+2006-02-21  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
+
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+	* Makefile.am: Add xc16x related entry.
+	* Makefile.in: Regenerate.
+	* configure.in: Added xc16x related entry.
+	* configure: Regenerate.
+	* config/tc-xc16x.h: New file
+	* config/tc-xc16x.c: New file
+	* doc/c-xc16x.texi: New file for xc16x
+	* doc/all.texi: Entry for xc16x
+	* doc/Makefile.texi: Added c-xc16x.texi
+	* NEWS: Announce the support for the new target.
+
+2006-02-16  Nick Hudson  <nick.hudson@dsl.pipex.com>
+
+	* configure.tgt: set emulation for mips-*-netbsd*
+
+2006-02-14  Jakub Jelinek  <jakub@redhat.com>
+
+	* config.in: Rebuilt.
+
+2006-02-13  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
+	from 1, not 0, in error messages.
+	(md_assemble): Simplify special-case check for ENTRY instructions.
+	(tinsn_has_invalid_symbolic_operands): Do not include opcode and
+	operand in error message.
+
+2006-02-13  Joseph S. Myers  <joseph@codesourcery.com>
+
+	* configure.tgt (arm-*-linux-gnueabi*): Change to
+	arm-*-linux-*eabi*.
+
+2006-02-10  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-crx.c (check_range): Ensure that the sign bit of a
+	32-bit value is propagated into the upper bits of a 64-bit long.
+
+	* config/tc-arc.c (init_opcode_tables): Fix cast.
+	(arc_extoper, md_operand): Likewise.
+
+2006-02-09  David Heine  <dlheine@tensilica.com>
+
+	* config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
+	each relaxation step.
+
+2006-02-09  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* configure.in (CHECK_DECLS): Add vsnprintf.
+	* configure: Regenerate.
+	* messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
+	include/declare here, but...
+	* as.h: Move code detecting VARARGS idiom to the top.
+	(errno.h, stdarg.h, varargs.h, va_list): ...here.
+	(vsnprintf): Declare if not already declared.
+
+2006-02-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* as.c (close_output_file): New.
+	(main): Register close_output_file with xatexit before
+	dump_statistics. Don't call output_file_close.
+
+2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
+	mcf5329_control_regs): New.
+	(not_current_architecture, selected_arch, selected_cpu): New.
+	(m68k_archs, m68k_extensions): New.
+	(archs): Renamed to ...
+	(m68k_cpus): ... here.  Adjust.
+	(n_arches): Remove.
+	(md_pseudo_table): Add arch and cpu directives.
+	(find_cf_chip, m68k_ip): Adjust table scanning.
+	(no_68851, no_68881): Remove.
+	(md_assemble): Lazily initialize.
+	(select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
+	(md_init_after_args): Move functionality to m68k_init_arch.
+	(mri_chip): Adjust table scanning.
+	(md_parse_option): Reimplement 'm' processing to add -march & -mcpu
+	options with saner parsing.
+	(m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
+	m68k_init_arch): New.
+	(s_m68k_cpu, s_m68k_arch): New.
+	(md_show_usage): Adjust.
+	(m68k_elf_final_processing): Set CF EF flags.
+	* config/tc-m68k.h (m68k_init_after_args): Remove.
+	(tc_init_after_args): Remove.
+	* doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
+	(M68k-Directives): Document .arch and .cpu directives.
+
+2006-02-05  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
+	synonyms for equ and defl.
+	(z80_cons_fix_new): New function.
+	(emit_byte): Disallow relative jumps to absolute locations.
+	(emit_data): Only handle defb, prototype changed, because defb is
+	now handled as pseudo-op rather than an instruction.
+	(instab): Entries for defb,defw,db,dw moved from here...
+	(md_pseudo_table): ... to here, use generic cons() for defw,dw.
+	Add entries for def24,def32,d24,d32.
+	(md_assemble): Improved error handling.
+	(md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
+	* config/tc-z80.h (TC_CONS_FIX_NEW): Define.
+	(z80_cons_fix_new): Declare.
+	* doc/c-z80.texi (defb, db): Mention warning on overflow.
+	(def24,d24,def32,d32): New pseudo-ops.
+
+2006-02-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
+
+2005-02-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
+	T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
+	T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
+	T2_OPCODE_RSB): Define.
+	(thumb32_negate_data_op): New function.
+	(md_apply_fix): Use it.
+
+2006-01-31  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
+	fields.
+	* config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
+	* config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
+	subtracted symbols.
+	(relaxation_requirements): Add pfinish_frag argument and use it to
+	replace setting tinsn->record_fix fields.
+	(xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
+	and vinsn_to_insnbuf.  Remove references to record_fix and
+	slot_sub_symbols fields.
+	(xtensa_mark_narrow_branches): Delete unused code.
+	(is_narrow_branch_guaranteed_in_range): Handle expr that is not just
+	a symbol.
+	(convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
+	record_fix fields.
+	(tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
+	(vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
+	of the record_fix field.  Simplify error messages for unexpected
+	symbolic operands.
+	(set_expr_symbol_offset_diff): Delete.
+
+2006-01-31  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
+
+2006-01-31  Paul Brook  <paul@codesourcery.com>
+	Richard Earnshaw <rearnsha@arm.com>
+
+	* config/tc-arm.c: Use arm_feature_set.
+	(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
+	arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
+	fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
+	New variables.
+	(insns): Use them.
+	(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
+	md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
+	arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
+	s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
+	feature flags.
+	(arm_legacy_option_table, arm_option_cpu_value_table): New types.
+	(arm_opts): Move old cpu/arch options from here...
+	(arm_legacy_opts): ... to here.
+	(md_parse_option): Search arm_legacy_opts.
+	(arm_cpus, arm_archs, arm_extensions, arm_fpus)
+	(arm_float_abis, arm_eabis): Make const.
+
+2006-01-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
+
+2006-01-21  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
+	in load immediate intruction.
+
+2006-01-21  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (value_match): Use correct conversion
+	specifications in template string for __FILE__ and __LINE__.
+	(binary): Ditto.
+	(unary): Ditto.
+
+2006-01-18  Alexandre Oliva  <aoliva@redhat.com>
+
+	Introduce TLS descriptors for i386 and x86_64.
+	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
+	BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
+	BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
+	(optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
+	BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
+	displacement bits.
+	(build_modrm_byte): Set up zero modrm for TLS desc calls.
+	(lex_got): Handle @tlsdesc and @tlscall.
+	(md_apply_fix, tc_gen_reloc): Handle the new relocations.
+
+2006-01-11  Nick Clifton  <nickc@redhat.com>
+
+	Fixes for building on 64-bit hosts:
+	* config/tc-avr.c (mod_index): New union to allow conversion
+	between pointers and integers.
+	(md_begin, avr_ldi_expression): Use it.
+	* config/tc-i370.c (md_assemble): Add cast for argument to print
+	statement.
+	* config/tc-tic54x.c (subsym_substitute): Likewise.
+	* config/tc-mn10200.c (md_assemble): Use a union to convert the
+	opindex field of fr_cgen structure into a pointer so that it can
+	be stored in a frag.
+	* config/tc-mn10300.c (md_assemble): Likewise.
+	* config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
+	types.
+	* config/tc-v850.c: Replace uses of (int) casts with correct
+	types.
+
+2006-01-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2117
+	* symbols.c (snapshot_symbol): Don't change a defined symbol.
+
+2006-01-03  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	PR gas/2101
+	* config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
+	a local-label reference.
+
+For older changes see ChangeLog-2005
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/contrib/binutils/gas/Makefile.am b/contrib/binutils/gas/Makefile.am
index 08b9842..6704236 100644
--- a/contrib/binutils/gas/Makefile.am
+++ b/contrib/binutils/gas/Makefile.am
@@ -1,9 +1,7 @@
 ## Process this file with automake to generate Makefile.in
 
-## Work around apparent automake bug.
-INTLLIBS = @INTLLIBS@
-
 AUTOMAKE_OPTIONS = 1.8 cygnus dejagnu
+ACLOCAL_AMFLAGS = -I .. -I ../config -I ../bfd
 
 SUBDIRS = doc po
 # Automake should figure this out on its own.  It doesn't, because
@@ -15,6 +13,10 @@ tooldir = $(exec_prefix)/$(target_alias)
 YACC = `if [ -f ../bison/bison ] ; then echo ../bison/bison -y -L../bison/bison ; else echo @YACC@ ; fi`
 LEX = `if [ -f ../flex/flex ] ; then echo ../flex/flex ; else echo @LEX@ ; fi`
 
+# We have to set this, because autoconf 2.59 does not substitute YFLAGS.
+# Autoconf 2.61 does, so this can be removed when we upgrade.
+YFLAGS =
+
 WARN_CFLAGS = @WARN_CFLAGS@
 NO_WERROR = @NO_WERROR@
 AM_CFLAGS = $(WARN_CFLAGS)
@@ -33,7 +35,7 @@ ATOF_TARG_C = $(srcdir)/config/atof-@atof@.c
 ATOF_TARG_O = atof-@atof@.o
 
 # use @target_cpu_type@ for refering to configured target name
-IT_HDRS=itbl-parse.h $(srcdir)/itbl-ops.h 
+IT_HDRS=itbl-parse.h $(srcdir)/itbl-ops.h
 IT_SRCS=itbl-parse.c itbl-lex.c $(srcdir)/itbl-ops.c
 IT_DEPS=$(srcdir)/itbl-parse.y $(srcdir)/itbl-lex.l $(srcdir)/config/itbl-@target_cpu_type@.h
 IT_OBJS=itbl-parse.o itbl-lex.o itbl-ops.o
@@ -46,6 +48,7 @@ CPU_TYPES = \
 	arm \
 	avr \
 	bfin \
+	cr16 \
 	cris \
 	crx \
 	d10v \
@@ -55,22 +58,25 @@ CPU_TYPES = \
 	frv \
 	h8300 \
 	hppa \
-	ia64 \
 	i370 \
 	i386 \
 	i860 \
 	i960 \
+	ia64 \
 	ip2k \
 	m32c \
 	m32r \
 	m68hc11 \
 	m68k \
+	maxq \
 	mcore \
+	mep \
 	mips \
 	mmix \
 	mn10200 \
 	mn10300 \
 	msp430 \
+	mt \
 	ns32k \
 	openrisc \
 	or32 \
@@ -78,16 +84,18 @@ CPU_TYPES = \
 	pj \
 	ppc \
 	s390 \
+	score \
 	sh \
 	sh64 \
 	sparc \
+	spu \
 	tic30 \
 	tic4x \
 	tic54x \
-	vax \
 	v850 \
-	xstormy16 \
+	vax \
 	xc16x \
+	xstormy16 \
 	xtensa \
 	z80 \
 	z8k
@@ -100,8 +108,7 @@ OBJ_FORMATS = \
 	coff \
 	ecoff \
 	elf \
-	evax \
-	ieee
+	evax
 
 # This is an sh case which sets valid according to whether the CPU
 # type in the shell variable c and the OS type in the shell variable o
@@ -116,16 +123,20 @@ CPU_OBJ_VALID = \
 	  arm | cris | i386 | m68k | ns32k | pdp11 | sparc | tic30 | vax) \
 	    valid=yes ;; \
 	  esac ;; \
-	coff) valid=yes; \
+	coff) \
 	  case $$c in \
-	  cris | i860 | mmix | sh64) \
-	    valid= ;; \
+	  arm | h8300 | i386 | i960 | m68k | maxq | mcore | mips | or32 \
+		| ppc | sh | sparc | tic* | xscale | z80 | z8k) \
+	    valid=yes ;; \
 	  esac ;; \
 	ecoff) \
 	  case $$c in \
 	  mips | alpha) valid=yes ;; \
 	  esac ;; \
-	elf) valid=yes ;; \
+	elf) valid=yes ; \
+	  case $$c in \
+	  maxq | ns32k | tic* | z80 | z8k) valid= ;; \
+	  esac ;; \
 	evax) \
 	  case $$c in \
 	  alpha) valid=yes ;; \
@@ -230,6 +241,7 @@ TARGET_CPU_CFILES = \
 	config/tc-arm.c \
 	config/tc-avr.c \
 	config/tc-bfin.c \
+	config/tc-cr16.c \
 	config/tc-cris.c \
 	config/tc-crx.c \
 	config/tc-d10v.c \
@@ -250,6 +262,7 @@ TARGET_CPU_CFILES = \
 	config/tc-m68hc11.c \
 	config/tc-m68k.c \
 	config/tc-mcore.c \
+	config/tc-mep.c \
 	config/tc-mips.c \
 	config/tc-mmix.c \
 	config/tc-mn10200.c \
@@ -262,9 +275,11 @@ TARGET_CPU_CFILES = \
 	config/tc-pj.c \
 	config/tc-ppc.c \
 	config/tc-s390.c \
+	config/tc-score.c \
 	config/tc-sh.c \
 	config/tc-sh64.c \
 	config/tc-sparc.c \
+	config/tc-spu.c \
 	config/tc-tic30.c \
 	config/tc-tic54x.c \
 	config/tc-vax.c \
@@ -281,6 +296,7 @@ TARGET_CPU_HFILES = \
 	config/tc-arm.h \
 	config/tc-avr.h \
 	config/tc-bfin.h \
+	config/tc-cr16.h \
 	config/tc-cris.h \
 	config/tc-crx.h \
 	config/tc-d10v.h \
@@ -301,6 +317,7 @@ TARGET_CPU_HFILES = \
 	config/tc-m68hc11.h \
 	config/tc-m68k.h \
 	config/tc-mcore.h \
+	config/tc-mep.h \
 	config/tc-mips.h \
 	config/tc-mmix.h \
 	config/tc-mn10200.h \
@@ -313,9 +330,11 @@ TARGET_CPU_HFILES = \
 	config/tc-pj.h \
 	config/tc-ppc.h \
 	config/tc-s390.h \
+	config/tc-score.h \
 	config/tc-sh.h \
 	config/tc-sh64.h \
 	config/tc-sparc.h \
+	config/tc-spu.h \
 	config/tc-tic30.h \
 	config/tc-tic54x.h \
 	config/tc-vax.h \
@@ -334,7 +353,6 @@ OBJ_FORMAT_CFILES = \
 	config/obj-ecoff.c \
 	config/obj-elf.c \
 	config/obj-evax.c \
-	config/obj-ieee.c \
 	config/obj-som.c
 
 OBJ_FORMAT_HFILES = \
@@ -343,7 +361,6 @@ OBJ_FORMAT_HFILES = \
 	config/obj-ecoff.h \
 	config/obj-elf.h \
 	config/obj-evax.h \
-	config/obj-ieee.h \
 	config/obj-som.h
 
 # Emulation header files in config
@@ -381,7 +398,8 @@ TARG_ENV_HFILES = \
 	config/te-sun3.h \
 	config/te-svr4.h \
 	config/te-symbian.h \
-	config/te-tmips.h
+	config/te-tmips.h \
+	config/te-wince-pe.h
 
 # Multi files in config
 
@@ -464,13 +482,18 @@ INCDIR = $(BASEDIR)/include
 # Both . and srcdir are used, in that order,
 # so that tm.h and config.h will be found in the compilation
 # subdirectory rather than in the source directory.
-INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config -I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) -I$(srcdir)/../intl -I../intl -DLOCALEDIR="\"$(datadir)/locale\""
+INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config \
+	-I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) @INCINTL@ \
+	-DLOCALEDIR="\"$(datadir)/locale\""
 
 # This should be parallel to INCLUDES, but should replace $(srcdir)
 # with $${srcdir}, and should work in a subdirectory.  This is used
 # when building dependencies, because the dependency building is done
 # in a subdirectory.
-DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd -I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. -I$${srcdir}/../bfd -I$${srcdir}/../intl -I../../intl -DLOCALEDIR="\"$(datadir)/locale\""
+DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd \
+	-I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. \
+	-I$${srcdir}/../bfd @INCINTL@ \
+	-DLOCALEDIR="\"$(datadir)/locale\""
 
 DEP_FLAGS = -DOBJ_MAYBE_ELF \
 	-I. -I.. -I$${srcdir} -I../../bfd $(DEP_INCLUDES)
@@ -478,25 +501,22 @@ DEP_FLAGS = -DOBJ_MAYBE_ELF \
 # How to link with both our special library facilities
 # and the system's installed libraries.
 
-GASLIBS = @OPCODES_LIB@ @BFDLIB@ ../libiberty/libiberty.a
+GASLIBS = @OPCODES_LIB@ ../bfd/libbfd.la ../libiberty/libiberty.a
 
 # Files to be copied away after each stage in building.
 STAGESTUFF = *.o $(noinst_PROGRAMS)
 
-BFDVER_H = @BFDVER_H@
-
-$(OBJS): @ALL_OBJ_DEPS@
-
 as_new_SOURCES = $(GAS_CFILES)
 as_new_LDADD = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
-	$(extra_objects) $(GASLIBS) $(INTLLIBS) $(LIBM)
+	$(extra_objects) $(GASLIBS) $(LIBINTL) $(LIBM)
 as_new_DEPENDENCIES = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
-	$(extra_objects) $(GASLIBS) $(INTLDEPS)
+	$(extra_objects) $(GASLIBS) $(LIBINTL_DEP)
 
 # Stuff that every object file depends upon.  If anything is removed
 # from this list, remove it from dep-in.sed as well.
-$(OBJS): $(INCDIR)/bin-bugs.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
-	$(INCDIR)/progress.h $(INCDIR)/fopen-same.h \
+$(OBJS): ../bfd/bfd.h $(INCDIR)/symcat.h \
+	$(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h $(INCDIR)/progress.h \
+	$(INCDIR)/fopen-same.h $(INCDIR)/fopen-bin.h $(INCDIR)/fopen-vms.h \
 	$(OBJ_FORMAT_H) $(TARG_CPU_H) $(TARG_ENV_H) \
 	as.h asintl.h bignum.h bit_fix.h config.h emul.h expr.h flonum.h \
 	frags.h hash.h listing.h obj.h read.h symbols.h tc.h write.h
@@ -540,18 +560,16 @@ ecoff.o : ecoff.c ecoff.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
 # We need all these explicit rules for the multi stuff.  Because of
 # these rules, we don't need one for OBJ_FORMAT_O.
 
-obj-aout.o : $(srcdir)/config/obj-aout.c
+obj-aout.o : $(srcdir)/config/obj-aout.c $(DEP_@target_cpu_type@_aout)
 	$(COMPILE) -c $(srcdir)/config/obj-aout.c
-obj-coff.o: $(srcdir)/config/obj-coff.c
+obj-coff.o: $(srcdir)/config/obj-coff.c $(DEP_@target_cpu_type@_coff)
 	$(COMPILE) -c $(srcdir)/config/obj-coff.c
-obj-ecoff.o : $(srcdir)/config/obj-ecoff.c
+obj-ecoff.o : $(srcdir)/config/obj-ecoff.c $(DEP_@target_cpu_type@_ecoff)
 	$(COMPILE) -c $(srcdir)/config/obj-ecoff.c
-obj-elf.o : $(srcdir)/config/obj-elf.c
+obj-elf.o : $(srcdir)/config/obj-elf.c $(DEP_@target_cpu_type@_elf)
 	$(COMPILE) -c $(srcdir)/config/obj-elf.c
 obj-evax.o : $(srcdir)/config/obj-evax.c
 	$(COMPILE) -c $(srcdir)/config/obj-evax.c
-obj-ieee.o : $(srcdir)/config/obj-ieee.c
-	$(COMPILE) -c $(srcdir)/config/obj-ieee.c
 obj-multi.o : $(srcdir)/config/obj-multi.c
 	$(COMPILE) -c $(srcdir)/config/obj-multi.c
 obj-som.o : $(srcdir)/config/obj-som.c
@@ -602,7 +620,7 @@ m68k-parse.c: $(srcdir)/config/m68k-parse.y
 	  rm -f m68k-parse.y; \
 	else true; fi
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 m68k-parse.o: m68k-parse.c $(srcdir)/config/m68k-parse.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
@@ -629,12 +647,12 @@ bfin-lex.o: bfin-lex.c bfin-parse.h $(srcdir)/config/bfin-defs.h
 itbl-lex.c: $(srcdir)/itbl-lex.l
 
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 itbl-lex.o: itbl-lex.c itbl-parse.h $(srcdir)/itbl-lex.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 itbl-parse.o: itbl-parse.c itbl-parse.h $(srcdir)/itbl-ops.h $(srcdir)/itbl-lex.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
@@ -988,582 +1006,443 @@ dep-am: DEP
 .PHONY: dep dep-in dep-am
 
 AMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-DEPTC_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
-DEPTC_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
-DEPTC_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h \
+DEPTC_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
   subsegs.h $(INCDIR)/obstack.h struc-symbol.h ecoff.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h $(INCDIR)/opcode/alpha.h \
-  $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
-DEPTC_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
-  $(srcdir)/config/tc-alpha.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+  $(INCDIR)/opcode/alpha.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
+DEPTC_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h subsegs.h \
+  $(INCDIR)/obstack.h struc-symbol.h ecoff.h $(INCDIR)/coff/sym.h \
+  $(INCDIR)/coff/ecoff.h $(INCDIR)/opcode/alpha.h $(INCDIR)/elf/alpha.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
   $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
-DEPTC_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h \
+  subsegs.h $(INCDIR)/obstack.h struc-symbol.h ecoff.h \
+  $(INCDIR)/opcode/alpha.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
+DEPTC_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
+  struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
   $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
-DEPTC_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
-  $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arm.h
-DEPTC_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h
-DEPTC_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arm.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
+DEPTC_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  dwarf2dbg.h
+DEPTC_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/avr.h
-DEPTC_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  dwarf2dbg.h
+DEPTC_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h dwarf2dbg.h
+DEPTC_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/avr.h
-DEPTC_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h dwarf2dbg.h \
-  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/bfin-aux.h $(INCDIR)/opcode/bfin.h \
-  $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
-DEPTC_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h struc-symbol.h $(srcdir)/config/bfin-defs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(srcdir)/config/bfin-aux.h \
-  $(INCDIR)/opcode/bfin.h $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
-DEPTC_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
+DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  struc-symbol.h $(srcdir)/config/bfin-defs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h $(INCDIR)/elf/bfin.h \
+  $(INCDIR)/elf/reloc-macros.h $(srcdir)/config/bfin-aux.h \
+  $(srcdir)/config/bfin-defs.h $(INCDIR)/opcode/bfin.h
+DEPTC_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/cr16.h \
+  $(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/cris.h \
+  dwarf2dbg.h
+DEPTC_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/cris.h dwarf2dbg.h
-DEPTC_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/cris.h
-DEPTC_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h $(INCDIR)/opcode/crx.h $(INCDIR)/elf/crx.h \
-  $(INCDIR)/elf/reloc-macros.h
-DEPTC_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/crx.h \
+DEPTC_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/crx.h \
   $(INCDIR)/elf/crx.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/d10v.h \
   $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_d10v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/d10v.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_d30v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d30v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/d30v.h
-DEPTC_d30v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
+  dwarf2dbg.h $(srcdir)/config/tc-dlx.h $(INCDIR)/opcode/dlx.h
+DEPTC_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/d30v.h
-DEPTC_dlx_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/dlx.h
-DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-dlx.h dwarf2dbg.h $(INCDIR)/opcode/dlx.h
-DEPTC_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/fr30-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/fr30-opc.h cgen.h
-DEPTC_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/fr30-opc.h \
-  cgen.h
-DEPTC_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(srcdir)/../opcodes/fr30-opc.h cgen.h
+DEPTC_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h subsegs.h \
+  $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/frv-opc.h \
   cgen.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/frv-opc.h cgen.h $(BFDDIR)/libbfd.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
-  $(INCDIR)/opcode/h8300.h $(INCDIR)/safe-ctype.h
-DEPTC_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/h8300.h \
+DEPTC_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/opcode/h8300.h $(INCDIR)/safe-ctype.h
+DEPTC_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/h8300.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/h8.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
-DEPTC_hppa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+DEPTC_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/hppa.h \
-  dwarf2dbg.h
-DEPTC_ia64_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
-  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h
-DEPTC_ia64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/safe-ctype.h dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h
-DEPTC_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i370.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h $(INCDIR)/opcode/i370.h
-DEPTC_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h dwarf2dbg.h
+DEPTC_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h $(INCDIR)/opcode/i370.h $(INCDIR)/elf/i370.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
+DEPTC_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
-  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
-  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i860.h $(INCDIR)/elf/i860.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
-DEPTC_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+DEPTC_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i960.h
-DEPTC_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/ip2k-opc.h \
-  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
-DEPTC_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
+DEPTC_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
+DEPTC_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h
+DEPTC_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/ip2k-opc.h cgen.h $(INCDIR)/elf/ip2k.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/ip2k-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
   $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
-DEPTC_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32c-opc.h \
-  $(srcdir)/../opcodes/cgen-types.h $(srcdir)/../opcodes/cgen-ops.h \
-  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/m32c.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/m32c-opc.h $(srcdir)/../opcodes/cgen-types.h \
-  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/m32c.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32r-desc.h \
+DEPTC_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/m32c-opc.h \
+  $(srcdir)/../opcodes/cgen-types.h ../bfd/bfd_stdint.h \
+  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h
+DEPTC_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
   $(srcdir)/../opcodes/m32r-opc.h cgen.h $(INCDIR)/elf/m32r.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
-  cgen.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h \
-  $(INCDIR)/elf/m68hc11.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/m68hc11.h $(INCDIR)/elf/m68hc11.h \
+DEPTC_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h $(INCDIR)/elf/m68hc11.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h subsegs.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+DEPTC_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
   $(srcdir)/config/m68k-parse.h
-DEPTC_m68k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
-  subsegs.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/m68k.h $(srcdir)/config/m68k-parse.h
-DEPTC_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h subsegs.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+DEPTC_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+  $(srcdir)/config/m68k-parse.h
+DEPTC_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
   $(srcdir)/config/m68k-parse.h $(INCDIR)/elf/m68k.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
+DEPTC_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/opcode/maxq.h
+DEPTC_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/mcore-opc.h $(INCDIR)/safe-ctype.h
+DEPTC_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+DEPTC_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h ecoff.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
-DEPTC_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mep-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/mep-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h \
+  $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h
+DEPTC_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h itbl-ops.h \
   dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h \
-  $(INCDIR)/elf/reloc-macros.h
-DEPTC_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
+DEPTC_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h
+DEPTC_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h \
+  itbl-ops.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(srcdir)/config/obj-elf.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
-DEPTC_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
+DEPTC_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/mmix.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/mn10200.h
-DEPTC_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/obstack.h
+DEPTC_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/mn10200.h
-DEPTC_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/mn10300.h \
-  dwarf2dbg.h
-DEPTC_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/mn10300.h
-DEPTC_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/msp430.h $(INCDIR)/safe-ctype.h dwarf2dbg.h
-DEPTC_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
-DEPTC_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ns32k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ns32k.h \
+DEPTC_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/mn10300.h dwarf2dbg.h
+DEPTC_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h
+DEPTC_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mt-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/mt-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mt.h $(INCDIR)/elf/reloc-macros.h \
+  $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+DEPTC_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ns32k.h \
   $(INCDIR)/obstack.h
-DEPTC_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
-DEPTC_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/openrisc-opc.h \
-  cgen.h
-DEPTC_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+DEPTC_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
   dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/openrisc-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/openrisc-opc.h cgen.h
-DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/openrisc-opc.h \
+  cgen.h
+DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
+  dwarf2dbg.h $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-or32.h dwarf2dbg.h $(INCDIR)/opcode/or32.h \
-  $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
-DEPTC_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pdp11.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/pdp11.h
-DEPTC_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
-DEPTC_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/pj.h
-DEPTC_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
-DEPTC_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+DEPTC_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
+DEPTC_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
+DEPTC_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/opcode/ppc.h
+DEPTC_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h
-DEPTC_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h \
-  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
-  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
-  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
-DEPTC_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h $(INCDIR)/elf/sh.h \
-  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
-DEPTC_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
+  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
+DEPTC_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/opcode/s390.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/score-inst.h $(INCDIR)/opcode/score-datadep.h \
+  struc-symbol.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h
+DEPTC_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h subsegs.h \
+  $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
   $(srcdir)/config/tc-sh.c subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/sh-opc.h struc-symbol.h dwarf2dbg.h \
+  $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-DEPTC_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
+DEPTC_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-DEPTC_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sparc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
-DEPTC_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
-DEPTC_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic30.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
-DEPTC_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
-DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/tic4x.h \
-  subsegs.h $(INCDIR)/obstack.h
-DEPTC_tic4x_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-tic4x.h dwarf2dbg.h $(INCDIR)/opcode/tic4x.h \
-  subsegs.h $(INCDIR)/obstack.h
-DEPTC_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h sb.h macro.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h $(INCDIR)/opcode/tic54x.h
-DEPTC_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/safe-ctype.h sb.h macro.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/tic54x.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h
+DEPTC_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/spu-insns.h
+DEPTC_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/tic30.h
+DEPTC_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/tic30.h
+DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/opcode/tic4x.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/obstack.h
+DEPTC_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
-  $(BFDDIR)/libcoff.h
-DEPTC_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/vax.h
-DEPTC_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
-  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/safe-ctype.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  sb.h macro.h subsegs.h $(INCDIR)/obstack.h struc-symbol.h \
+  $(INCDIR)/opcode/tic54x.h $(srcdir)/config/obj-coff.h
+DEPTC_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/v850.h \
+  dwarf2dbg.h
+DEPTC_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/vax.h
-DEPTC_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h \
-  subsegs.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
+DEPTC_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
+  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/vax.h
-DEPTC_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/v850.h dwarf2dbg.h
-DEPTC_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+DEPTC_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/v850.h
-DEPTC_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/xstormy16-opc.h \
-  cgen.h
-DEPTC_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(srcdir)/../opcodes/xc16x-opc.h cgen.h dwarf2dbg.h \
+  $(INCDIR)/elf/xc16x.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
   dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xstormy16-opc.h cgen.h
-DEPTC_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xc16x-opc.h cgen.h
-DEPTC_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h sb.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/xstormy16-opc.h \
+  cgen.h
+DEPTC_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h sb.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/config/tc-xtensa.h subsegs.h $(INCDIR)/obstack.h \
   $(srcdir)/config/xtensa-relax.h $(srcdir)/config/xtensa-istack.h \
-  dwarf2dbg.h struc-symbol.h
-DEPTC_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h
-DEPTC_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h
-DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
-DEPTC_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
+  dwarf2dbg.h struc-symbol.h $(INCDIR)/xtensa-config.h
+DEPTC_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPTC_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/../opcodes/z8k-opc.h
 DEPTC_hppa_som = $(srcdir)/config/tc-hppa.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h \
   $(BFDDIR)/som.h
@@ -1572,483 +1451,364 @@ DEPTC_i386_multi = $(DEPTC_i386_aout) $(DEPTC_i386_coff) \
 DEPTC_mips_multi = $(DEPTC_mips_coff) $(DEPTC_mips_ecoff) \
   $(DEPTC_mips_elf)
 DEPTC_cris_multi = $(DEPTC_cris_aout) $(DEPTC_cris_elf)
-DEPOBJ_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(BFDDIR)/libecoff.h
-DEPOBJ_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
+DEPOBJ_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(BFDDIR)/libecoff.h
+DEPOBJ_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
-DEPOBJ_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
-  $(srcdir)/config/tc-alpha.h
-DEPOBJ_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
+DEPOBJ_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h
+DEPOBJ_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_d10v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_d30v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d30v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_d30v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_dlx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-dlx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_dlx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_dlx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_hppa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_ia64_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
-  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_ia64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i370.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/i370.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
+DEPOBJ_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
-DEPOBJ_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
+DEPOBJ_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_m68k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(BFDDIR)/libecoff.h
-DEPOBJ_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/mep.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(BFDDIR)/libecoff.h
+DEPOBJ_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
   dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ns32k.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_or32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/ppc.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
+DEPOBJ_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_or32_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_or32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pdp11.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h subsegs.h \
   $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sparc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic30.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_tic4x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_tic4x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h \
+DEPOBJ_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
   dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 DEPOBJ_hppa_som = $(srcdir)/config/obj-som.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(BFDDIR)/som.h \
   $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
@@ -2057,354 +1817,309 @@ DEPOBJ_i386_multi = $(DEPOBJ_i386_aout) $(DEPOBJ_i386_coff) \
 DEPOBJ_mips_multi = $(DEPOBJ_mips_coff) $(DEPOBJ_mips_ecoff) \
   $(DEPOBJ_mips_elf)
 DEPOBJ_cris_multi = $(DEPOBJ_cris_aout) $(DEPOBJ_cris_elf)
-DEP_alpha_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-alpha.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
 DEP_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
-DEP_alpha_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h
+DEP_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h
 DEP_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h
-DEP_arc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_arc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h
+DEP_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_arm_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h
-DEP_avr_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-avr.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_avr_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h
-DEP_bfin_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-bfin.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h
+DEP_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_cris_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h
-DEP_crx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-crx.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_crx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h
-DEP_d10v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d10v.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_d10v_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h
-DEP_d30v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d30v.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_d30v_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h
-DEP_dlx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  dwarf2dbg.h
-DEP_fr30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-fr30.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h
-DEP_frv_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-frv.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_frv_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h
+DEP_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h
+DEP_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h
+DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h
 DEP_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h
-DEP_hppa_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-hppa.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_hppa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
-  $(INCDIR)/elf/reloc-macros.h
-DEP_ia64_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/symcat.h $(INCDIR)/elf/ia64.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_ia64_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h
-DEP_i370_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i370.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_i370_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h
+DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+DEP_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+  $(INCDIR)/elf/reloc-macros.h
+DEP_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_i386_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h
-DEP_i860_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h
-DEP_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_i960_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h
-DEP_ip2k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ip2k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h
-DEP_m32c_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32c.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h
-DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+DEP_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h
+DEP_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
-DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h
-DEP_m68hc11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68hc11.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h
+DEP_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h
+DEP_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h
+DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
 DEP_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
+DEP_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+DEP_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
-DEP_mips_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h
-DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h
-DEP_mn10200_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10200.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h
-DEP_mn10300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10300.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h
-DEP_msp430_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-msp430.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h
+DEP_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h
+DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_ns32k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ns32k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_ns32k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h
-DEP_openrisc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-openrisc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  dwarf2dbg.h
+DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+  dwarf2dbg.h $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_or32_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
+DEP_or32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h
 DEP_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_pdp11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pdp11.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h
-DEP_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_pj_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h
+DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h
-DEP_s390_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-s390.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
-DEP_s390_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h
+DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h
+DEP_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_sh_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h
-DEP_sh64_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h
+DEP_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h
 DEP_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+DEP_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h
 DEP_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_tic30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h \
-  $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_tic4x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h \
-  $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_tic54x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h
 DEP_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_vax_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-vax.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_vax_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h
-DEP_v850_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/symcat.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_v850_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
-DEP_xstormy16_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-xstormy16.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  dwarf2dbg.h
-DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h 
-DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h
+DEP_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  dwarf2dbg.h $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h
 DEP_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_z80_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_z8k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_hppa_som = $(BFDDIR)/som.h
 DEP_i386_multi = $(DEP_i386_aout) $(DEP_i386_coff) \
   $(DEP_i386_elf)
@@ -2413,66 +2128,52 @@ DEP_mips_multi = $(DEP_mips_coff) $(DEP_mips_ecoff) \
 DEP_cris_multi = $(DEP_cris_aout) $(DEP_cris_elf)
 BMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING ABOVE.
 #MKDEP    DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-app.o: app.c $(INCDIR)/symcat.h
-as.o: as.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  output-file.h sb.h macro.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(BFDVER_H)
-atof-generic.o: atof-generic.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h
-cond.o: cond.c $(INCDIR)/symcat.h macro.h sb.h $(INCDIR)/obstack.h
-depend.o: depend.c $(INCDIR)/symcat.h
-dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/elf/dwarf2.h
-dw2gencfi.o: dw2gencfi.c $(INCDIR)/symcat.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
-ecoff.o: ecoff.c $(INCDIR)/symcat.h ecoff.h
-ehopt.o: ehopt.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
+app.o: app.c
+as.o: as.c subsegs.h $(INCDIR)/obstack.h output-file.h \
+  sb.h macro.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  ../bfd/bfdver.h
+atof-generic.o: atof-generic.c $(INCDIR)/safe-ctype.h
+cond.o: cond.c sb.h macro.h $(INCDIR)/obstack.h
+depend.o: depend.c
+dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/safe-ctype.h dwarf2dbg.h \
+  $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/elf/dwarf2.h
-expr.o: expr.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h
-flonum-copy.o: flonum-copy.c $(INCDIR)/symcat.h
+dw2gencfi.o: dw2gencfi.c dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  subsegs.h $(INCDIR)/obstack.h
+ecoff.o: ecoff.c ecoff.h
+ehopt.o: ehopt.c subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/dwarf2.h
+expr.o: expr.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h
+flonum-copy.o: flonum-copy.c
 flonum-konst.o: flonum-konst.c
 flonum-mult.o: flonum-mult.c
-frags.o: frags.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-hash.o: hash.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h
-input-file.o: input-file.c $(INCDIR)/symcat.h input-file.h \
-  $(INCDIR)/safe-ctype.h
-input-scrub.o: input-scrub.c $(INCDIR)/symcat.h input-file.h \
-  sb.h
-listing.o: listing.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
-  $(INCDIR)/safe-ctype.h input-file.h subsegs.h
-literal.o: literal.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-macro.o: macro.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  sb.h macro.h
-messages.o: messages.c $(INCDIR)/symcat.h
-output-file.o: output-file.c $(INCDIR)/symcat.h output-file.h
-read.o: read.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h sb.h macro.h ecoff.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-sb.o: sb.c sb.h $(INCDIR)/symcat.h
-stabs.o: stabs.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
-  subsegs.h ecoff.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
-subsegs.o: subsegs.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-symbols.o: symbols.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h subsegs.h struc-symbol.h
-write.o: write.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  output-file.h dwarf2dbg.h
-itbl-ops.o: itbl-ops.c itbl-ops.h $(INCDIR)/symcat.h
-e-crisaout.o: $(srcdir)/config/e-crisaout.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-criself.o: $(srcdir)/config/e-criself.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386aout.o: $(srcdir)/config/e-i386aout.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386coff.o: $(srcdir)/config/e-i386coff.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386elf.o: $(srcdir)/config/e-i386elf.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-mipsecoff.o: $(srcdir)/config/e-mipsecoff.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-mipself.o: $(srcdir)/config/e-mipself.c $(INCDIR)/symcat.h \
-  emul-target.h
+frags.o: frags.c subsegs.h $(INCDIR)/obstack.h
+hash.o: hash.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h
+input-file.o: input-file.c input-file.h $(INCDIR)/safe-ctype.h
+input-scrub.o: input-scrub.c input-file.h sb.h
+listing.o: listing.c $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  input-file.h subsegs.h
+literal.o: literal.c subsegs.h $(INCDIR)/obstack.h
+macro.o: macro.c $(INCDIR)/safe-ctype.h sb.h macro.h
+messages.o: messages.c
+output-file.o: output-file.c output-file.h
+read.o: read.c $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  sb.h macro.h ecoff.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+sb.o: sb.c sb.h
+stabs.o: stabs.c $(INCDIR)/obstack.h subsegs.h ecoff.h \
+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
+subsegs.o: subsegs.c subsegs.h $(INCDIR)/obstack.h
+symbols.o: symbols.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+  subsegs.h struc-symbol.h
+write.o: write.c subsegs.h $(INCDIR)/obstack.h output-file.h \
+  dwarf2dbg.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+itbl-ops.o: itbl-ops.c itbl-ops.h
+e-crisaout.o: $(srcdir)/config/e-crisaout.c emul-target.h
+e-criself.o: $(srcdir)/config/e-criself.c emul-target.h
+e-i386aout.o: $(srcdir)/config/e-i386aout.c emul-target.h
+e-i386coff.o: $(srcdir)/config/e-i386coff.c emul-target.h
+e-i386elf.o: $(srcdir)/config/e-i386elf.c emul-target.h
+e-mipsecoff.o: $(srcdir)/config/e-mipsecoff.c emul-target.h
+e-mipself.o: $(srcdir)/config/e-mipself.c emul-target.h
 $(OBJS): $(DEP_@target_cpu_type@_@obj_format@)
 $(TARG_CPU_O): $(DEPTC_@target_cpu_type@_@obj_format@)
 $(OBJ_FORMAT_O): $(DEPOBJ_@target_cpu_type@_@obj_format@)
diff --git a/contrib/binutils/gas/Makefile.in b/contrib/binutils/gas/Makefile.in
index 4cc485f..6a43cca 100644
--- a/contrib/binutils/gas/Makefile.in
+++ b/contrib/binutils/gas/Makefile.in
@@ -51,9 +51,16 @@ DIST_COMMON = $(srcdir)/../config.guess $(srcdir)/../config.sub NEWS \
 	$(srcdir)/../config.sub
 subdir = .
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/acinclude.m4 \
-	$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../libtool.m4 \
-	$(top_srcdir)/../gettext.m4 $(top_srcdir)/configure.in
+am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
+	$(top_srcdir)/../bfd/warning.m4 \
+	$(top_srcdir)/../config/depstand.m4 \
+	$(top_srcdir)/../config/gettext-sister.m4 \
+	$(top_srcdir)/../config/lead-dot.m4 \
+	$(top_srcdir)/../config/nls.m4 $(top_srcdir)/../config/po.m4 \
+	$(top_srcdir)/../config/progtest.m4 \
+	$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
+	$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
+	$(top_srcdir)/acinclude.m4 $(top_srcdir)/configure.in
 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
 	$(ACLOCAL_M4)
 am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
@@ -78,7 +85,7 @@ am__DEPENDENCIES_1 = tc-@target_cpu_type@.o
 am__DEPENDENCIES_2 = obj-@obj_format@.o
 am__DEPENDENCIES_3 = atof-@atof@.o
 am__DEPENDENCIES_4 =
-am__DEPENDENCIES_5 = ../libiberty/libiberty.a
+am__DEPENDENCIES_5 = ../bfd/libbfd.la ../libiberty/libiberty.a
 am_itbl_test_OBJECTS = itbl-parse.$(OBJEXT) itbl-lex.$(OBJEXT)
 itbl_test_OBJECTS = $(am_itbl_test_OBJECTS)
 itbl_test_DEPENDENCIES = itbl-tops.o itbl-test.o $(am__DEPENDENCIES_5)
@@ -88,11 +95,11 @@ depcomp =
 am__depfiles_maybe =
 COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
 	$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
-LTCOMPILE = $(LIBTOOL) --mode=compile $(CC) $(DEFS) \
+LTCOMPILE = $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) \
 	$(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \
 	$(AM_CFLAGS) $(CFLAGS)
 CCLD = $(CC)
-LINK = $(LIBTOOL) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
+LINK = $(LIBTOOL) --tag=CC --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
 	$(AM_LDFLAGS) $(LDFLAGS) -o $@
 LEXCOMPILE = $(LEX) $(LFLAGS) $(AM_LFLAGS)
 LTLEXCOMPILE = $(LIBTOOL) --mode=compile $(LEX) $(LFLAGS) $(AM_LFLAGS)
@@ -114,16 +121,14 @@ DEJATOOL = $(PACKAGE)
 RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir
 ACLOCAL = @ACLOCAL@
 ALLOCA = @ALLOCA@
-ALL_OBJ_DEPS = @ALL_OBJ_DEPS@
 AMDEP_FALSE = @AMDEP_FALSE@
 AMDEP_TRUE = @AMDEP_TRUE@
 AMTAR = @AMTAR@
+AR = @AR@
 AUTOCONF = @AUTOCONF@
 AUTOHEADER = @AUTOHEADER@
 AUTOMAKE = @AUTOMAKE@
 AWK = @AWK@
-BFDLIB = @BFDLIB@
-BFDVER_H = @BFDVER_H@
 CATALOGS = @CATALOGS@
 CATOBJEXT = @CATOBJEXT@
 CC = @CC@
@@ -135,29 +140,32 @@ CYGPATH_W = @CYGPATH_W@
 DATADIRNAME = @DATADIRNAME@
 DEFS = @DEFS@
 DEPDIR = @DEPDIR@
+DUMPBIN = @DUMPBIN@
 ECHO_C = @ECHO_C@
 ECHO_N = @ECHO_N@
 ECHO_T = @ECHO_T@
 EGREP = @EGREP@
 EXEEXT = @EXEEXT@
+FGREP = @FGREP@
 GDBINIT = @GDBINIT@
-GMOFILES = @GMOFILES@
+GENCAT = @GENCAT@
+GENINSRC_NEVER_FALSE = @GENINSRC_NEVER_FALSE@
+GENINSRC_NEVER_TRUE = @GENINSRC_NEVER_TRUE@
 GMSGFMT = @GMSGFMT@
-GT_NO = @GT_NO@
-GT_YES = @GT_YES@
-INCLUDE_LOCALE_H = @INCLUDE_LOCALE_H@
+GREP = @GREP@
+INCINTL = @INCINTL@
 INSTALL_DATA = @INSTALL_DATA@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_SCRIPT = @INSTALL_SCRIPT@
 INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
 INSTOBJEXT = @INSTOBJEXT@
-INTLDEPS = @INTLDEPS@
-INTLLIBS = @INTLLIBS@
-INTLOBJS = @INTLOBJS@
+LD = @LD@
 LDFLAGS = @LDFLAGS@
 LEX = `if [ -f ../flex/flex ] ; then echo ../flex/flex ; else echo @LEX@ ; fi`
 LEXLIB = @LEXLIB@
 LEX_OUTPUT_ROOT = @LEX_OUTPUT_ROOT@
+LIBINTL = @LIBINTL@
+LIBINTL_DEP = @LIBINTL_DEP@
 LIBM = @LIBM@
 LIBOBJS = @LIBOBJS@
 LIBS = @LIBS@
@@ -170,6 +178,8 @@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@
 MAKEINFO = @MAKEINFO@
 MKINSTALLDIRS = @MKINSTALLDIRS@
 MSGFMT = @MSGFMT@
+MSGMERGE = @MSGMERGE@
+NM = @NM@
 NO_WERROR = @NO_WERROR@
 OBJEXT = @OBJEXT@
 OPCODES_LIB = @OPCODES_LIB@
@@ -180,19 +190,20 @@ PACKAGE_STRING = @PACKAGE_STRING@
 PACKAGE_TARNAME = @PACKAGE_TARNAME@
 PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
-POFILES = @POFILES@
 POSUB = @POSUB@
 RANLIB = @RANLIB@
+SED = @SED@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
-USE_INCLUDED_LIBINTL = @USE_INCLUDED_LIBINTL@
 USE_NLS = @USE_NLS@
 VERSION = @VERSION@
 WARN_CFLAGS = @WARN_CFLAGS@
 XGETTEXT = @XGETTEXT@
 YACC = `if [ -f ../bison/bison ] ; then echo ../bison/bison -y -L../bison/bison ; else echo @YACC@ ; fi`
+ac_ct_AR = @ac_ct_AR@
 ac_ct_CC = @ac_ct_CC@
+ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
 ac_ct_RANLIB = @ac_ct_RANLIB@
 ac_ct_STRIP = @ac_ct_STRIP@
 am__fastdepCC_FALSE = @am__fastdepCC_FALSE@
@@ -225,10 +236,10 @@ includedir = @includedir@
 infodir = @infodir@
 install_sh = @install_sh@
 install_tooldir = @install_tooldir@
-l = @l@
 libdir = @libdir@
 libexecdir = @libexecdir@
 localstatedir = @localstatedir@
+lt_ECHO = @lt_ECHO@
 mandir = @mandir@
 mkdir_p = @mkdir_p@
 obj_format = @obj_format@
@@ -246,11 +257,16 @@ target_os = @target_os@
 target_vendor = @target_vendor@
 te_file = @te_file@
 AUTOMAKE_OPTIONS = 1.8 cygnus dejagnu
+ACLOCAL_AMFLAGS = -I .. -I ../config -I ../bfd
 SUBDIRS = doc po
 # Automake should figure this out on its own.  It doesn't, because
 # of the "cygnus" option.  But distclean still wants it.
 DIST_SUBDIRS = $(SUBDIRS)
 tooldir = $(exec_prefix)/$(target_alias)
+
+# We have to set this, because autoconf 2.59 does not substitute YFLAGS.
+# Autoconf 2.61 does, so this can be removed when we upgrade.
+YFLAGS = 
 AM_CFLAGS = $(WARN_CFLAGS)
 MKDEP = gcc -MM
 TARG_CPU = @target_cpu_type@
@@ -265,7 +281,7 @@ ATOF_TARG_C = $(srcdir)/config/atof-@atof@.c
 ATOF_TARG_O = atof-@atof@.o
 
 # use @target_cpu_type@ for refering to configured target name
-IT_HDRS = itbl-parse.h $(srcdir)/itbl-ops.h 
+IT_HDRS = itbl-parse.h $(srcdir)/itbl-ops.h
 IT_SRCS = itbl-parse.c itbl-lex.c $(srcdir)/itbl-ops.c
 IT_DEPS = $(srcdir)/itbl-parse.y $(srcdir)/itbl-lex.l $(srcdir)/config/itbl-@target_cpu_type@.h
 IT_OBJS = itbl-parse.o itbl-lex.o itbl-ops.o
@@ -277,6 +293,7 @@ CPU_TYPES = \
 	arm \
 	avr \
 	bfin \
+	cr16 \
 	cris \
 	crx \
 	d10v \
@@ -286,22 +303,25 @@ CPU_TYPES = \
 	frv \
 	h8300 \
 	hppa \
-	ia64 \
 	i370 \
 	i386 \
 	i860 \
 	i960 \
+	ia64 \
 	ip2k \
 	m32c \
 	m32r \
 	m68hc11 \
 	m68k \
+	maxq \
 	mcore \
+	mep \
 	mips \
 	mmix \
 	mn10200 \
 	mn10300 \
 	msp430 \
+	mt \
 	ns32k \
 	openrisc \
 	or32 \
@@ -309,16 +329,18 @@ CPU_TYPES = \
 	pj \
 	ppc \
 	s390 \
+	score \
 	sh \
 	sh64 \
 	sparc \
+	spu \
 	tic30 \
 	tic4x \
 	tic54x \
-	vax \
 	v850 \
-	xstormy16 \
+	vax \
 	xc16x \
+	xstormy16 \
 	xtensa \
 	z80 \
 	z8k
@@ -331,8 +353,7 @@ OBJ_FORMATS = \
 	coff \
 	ecoff \
 	elf \
-	evax \
-	ieee
+	evax
 
 
 # This is an sh case which sets valid according to whether the CPU
@@ -347,16 +368,20 @@ CPU_OBJ_VALID = \
 	  arm | cris | i386 | m68k | ns32k | pdp11 | sparc | tic30 | vax) \
 	    valid=yes ;; \
 	  esac ;; \
-	coff) valid=yes; \
+	coff) \
 	  case $$c in \
-	  cris | i860 | mmix | sh64) \
-	    valid= ;; \
+	  arm | h8300 | i386 | i960 | m68k | maxq | mcore | mips | or32 \
+		| ppc | sh | sparc | tic* | xscale | z80 | z8k) \
+	    valid=yes ;; \
 	  esac ;; \
 	ecoff) \
 	  case $$c in \
 	  mips | alpha) valid=yes ;; \
 	  esac ;; \
-	elf) valid=yes ;; \
+	elf) valid=yes ; \
+	  case $$c in \
+	  maxq | ns32k | tic* | z80 | z8k) valid= ;; \
+	  esac ;; \
 	evax) \
 	  case $$c in \
 	  alpha) valid=yes ;; \
@@ -459,6 +484,7 @@ TARGET_CPU_CFILES = \
 	config/tc-arm.c \
 	config/tc-avr.c \
 	config/tc-bfin.c \
+	config/tc-cr16.c \
 	config/tc-cris.c \
 	config/tc-crx.c \
 	config/tc-d10v.c \
@@ -479,6 +505,7 @@ TARGET_CPU_CFILES = \
 	config/tc-m68hc11.c \
 	config/tc-m68k.c \
 	config/tc-mcore.c \
+	config/tc-mep.c \
 	config/tc-mips.c \
 	config/tc-mmix.c \
 	config/tc-mn10200.c \
@@ -491,9 +518,11 @@ TARGET_CPU_CFILES = \
 	config/tc-pj.c \
 	config/tc-ppc.c \
 	config/tc-s390.c \
+	config/tc-score.c \
 	config/tc-sh.c \
 	config/tc-sh64.c \
 	config/tc-sparc.c \
+	config/tc-spu.c \
 	config/tc-tic30.c \
 	config/tc-tic54x.c \
 	config/tc-vax.c \
@@ -510,6 +539,7 @@ TARGET_CPU_HFILES = \
 	config/tc-arm.h \
 	config/tc-avr.h \
 	config/tc-bfin.h \
+	config/tc-cr16.h \
 	config/tc-cris.h \
 	config/tc-crx.h \
 	config/tc-d10v.h \
@@ -530,6 +560,7 @@ TARGET_CPU_HFILES = \
 	config/tc-m68hc11.h \
 	config/tc-m68k.h \
 	config/tc-mcore.h \
+	config/tc-mep.h \
 	config/tc-mips.h \
 	config/tc-mmix.h \
 	config/tc-mn10200.h \
@@ -542,9 +573,11 @@ TARGET_CPU_HFILES = \
 	config/tc-pj.h \
 	config/tc-ppc.h \
 	config/tc-s390.h \
+	config/tc-score.h \
 	config/tc-sh.h \
 	config/tc-sh64.h \
 	config/tc-sparc.h \
+	config/tc-spu.h \
 	config/tc-tic30.h \
 	config/tc-tic54x.h \
 	config/tc-vax.h \
@@ -563,7 +596,6 @@ OBJ_FORMAT_CFILES = \
 	config/obj-ecoff.c \
 	config/obj-elf.c \
 	config/obj-evax.c \
-	config/obj-ieee.c \
 	config/obj-som.c
 
 OBJ_FORMAT_HFILES = \
@@ -572,7 +604,6 @@ OBJ_FORMAT_HFILES = \
 	config/obj-ecoff.h \
 	config/obj-elf.h \
 	config/obj-evax.h \
-	config/obj-ieee.h \
 	config/obj-som.h
 
 
@@ -610,7 +641,8 @@ TARG_ENV_HFILES = \
 	config/te-sun3.h \
 	config/te-svr4.h \
 	config/te-symbian.h \
-	config/te-tmips.h
+	config/te-tmips.h \
+	config/te-wince-pe.h
 
 
 # Multi files in config
@@ -681,29 +713,36 @@ INCDIR = $(BASEDIR)/include
 # Both . and srcdir are used, in that order,
 # so that tm.h and config.h will be found in the compilation
 # subdirectory rather than in the source directory.
-INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config -I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) -I$(srcdir)/../intl -I../intl -DLOCALEDIR="\"$(datadir)/locale\""
+INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config \
+	-I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) @INCINTL@ \
+	-DLOCALEDIR="\"$(datadir)/locale\""
+
 
 # This should be parallel to INCLUDES, but should replace $(srcdir)
 # with $${srcdir}, and should work in a subdirectory.  This is used
 # when building dependencies, because the dependency building is done
 # in a subdirectory.
-DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd -I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. -I$${srcdir}/../bfd -I$${srcdir}/../intl -I../../intl -DLOCALEDIR="\"$(datadir)/locale\""
+DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd \
+	-I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. \
+	-I$${srcdir}/../bfd @INCINTL@ \
+	-DLOCALEDIR="\"$(datadir)/locale\""
+
 DEP_FLAGS = -DOBJ_MAYBE_ELF \
 	-I. -I.. -I$${srcdir} -I../../bfd $(DEP_INCLUDES)
 
 
 # How to link with both our special library facilities
 # and the system's installed libraries.
-GASLIBS = @OPCODES_LIB@ @BFDLIB@ ../libiberty/libiberty.a
+GASLIBS = @OPCODES_LIB@ ../bfd/libbfd.la ../libiberty/libiberty.a
 
 # Files to be copied away after each stage in building.
 STAGESTUFF = *.o $(noinst_PROGRAMS)
 as_new_SOURCES = $(GAS_CFILES)
 as_new_LDADD = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
-	$(extra_objects) $(GASLIBS) $(INTLLIBS) $(LIBM)
+	$(extra_objects) $(GASLIBS) $(LIBINTL) $(LIBM)
 
 as_new_DEPENDENCIES = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
-	$(extra_objects) $(GASLIBS) $(INTLDEPS)
+	$(extra_objects) $(GASLIBS) $(LIBINTL_DEP)
 
 EXPECT = expect
 RUNTEST = runtest
@@ -729,687 +768,520 @@ DEP_FILE_DEPS = $(CFILES) $(HFILES) $(TARGET_CPU_CFILES) \
 
 CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in $(srcdir)/configure.tgt
 AMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-DEPTC_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
+DEPTC_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  subsegs.h $(INCDIR)/obstack.h struc-symbol.h ecoff.h \
+  $(INCDIR)/opcode/alpha.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 
-DEPTC_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+DEPTC_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h subsegs.h \
+  $(INCDIR)/obstack.h struc-symbol.h ecoff.h $(INCDIR)/coff/sym.h \
+  $(INCDIR)/coff/ecoff.h $(INCDIR)/opcode/alpha.h $(INCDIR)/elf/alpha.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
   $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 
-DEPTC_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h \
+DEPTC_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h \
   subsegs.h $(INCDIR)/obstack.h struc-symbol.h ecoff.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h $(INCDIR)/opcode/alpha.h \
-  $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
-
-DEPTC_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
-  $(srcdir)/config/tc-alpha.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
+  $(INCDIR)/opcode/alpha.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 
-DEPTC_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
+  struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
   $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
 
-DEPTC_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
-  $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  dwarf2dbg.h
 
-DEPTC_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arm.h
+DEPTC_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  dwarf2dbg.h
 
-DEPTC_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h
+DEPTC_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h dwarf2dbg.h
 
-DEPTC_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
+DEPTC_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arm.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+  $(INCDIR)/opcode/avr.h
 
-DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/avr.h
+DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  struc-symbol.h $(srcdir)/config/bfin-defs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h $(INCDIR)/elf/bfin.h \
+  $(INCDIR)/elf/reloc-macros.h $(srcdir)/config/bfin-aux.h \
+  $(srcdir)/config/bfin-defs.h $(INCDIR)/opcode/bfin.h
+
+DEPTC_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/cr16.h \
+  $(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/avr.h
+DEPTC_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/cris.h \
+  dwarf2dbg.h
 
-DEPTC_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h dwarf2dbg.h \
-  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/bfin-aux.h $(INCDIR)/opcode/bfin.h \
-  $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
-
-DEPTC_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h struc-symbol.h $(srcdir)/config/bfin-defs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(srcdir)/config/bfin-aux.h \
-  $(INCDIR)/opcode/bfin.h $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
-
-DEPTC_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
+DEPTC_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/cris.h dwarf2dbg.h
 
-DEPTC_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/cris.h
-
-DEPTC_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h $(INCDIR)/opcode/crx.h $(INCDIR)/elf/crx.h \
-  $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/crx.h \
+DEPTC_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/crx.h \
   $(INCDIR)/elf/crx.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/d10v.h \
   $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_d10v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/d10v.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_d30v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d30v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/d30v.h
 
-DEPTC_d30v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/d30v.h
-
-DEPTC_dlx_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/dlx.h
-
-DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-dlx.h dwarf2dbg.h $(INCDIR)/opcode/dlx.h
-
-DEPTC_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/fr30-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/fr30-opc.h cgen.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
+  dwarf2dbg.h $(srcdir)/config/tc-dlx.h $(INCDIR)/opcode/dlx.h
 
-DEPTC_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/fr30-opc.h \
-  cgen.h
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(srcdir)/../opcodes/fr30-opc.h cgen.h
 
-DEPTC_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \
+DEPTC_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h subsegs.h \
+  $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/frv-opc.h \
   cgen.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/frv-opc.h cgen.h $(BFDDIR)/libbfd.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
-  $(INCDIR)/opcode/h8300.h $(INCDIR)/safe-ctype.h
+DEPTC_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/opcode/h8300.h $(INCDIR)/safe-ctype.h
 
-DEPTC_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/h8300.h \
+DEPTC_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/h8300.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/h8.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
-
-DEPTC_hppa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+DEPTC_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/hppa.h \
-  dwarf2dbg.h
-
-DEPTC_ia64_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
-  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h
+  subsegs.h $(INCDIR)/obstack.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h dwarf2dbg.h
 
-DEPTC_ia64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/safe-ctype.h dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h
-
-DEPTC_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i370.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h $(INCDIR)/opcode/i370.h
-
-DEPTC_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h $(INCDIR)/opcode/i370.h $(INCDIR)/elf/i370.h \
   $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
-  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
-  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i860.h $(INCDIR)/elf/i860.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
-
-DEPTC_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+DEPTC_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i960.h
 
-DEPTC_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/ip2k-opc.h \
-  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+DEPTC_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
 
-DEPTC_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
+DEPTC_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h
+
+DEPTC_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/ip2k-opc.h cgen.h $(INCDIR)/elf/ip2k.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/ip2k-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
   $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
 
-DEPTC_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32c-opc.h \
-  $(srcdir)/../opcodes/cgen-types.h $(srcdir)/../opcodes/cgen-ops.h \
-  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/m32c.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/safe-ctype.h
-
-DEPTC_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
+DEPTC_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/m32c-opc.h $(srcdir)/../opcodes/cgen-types.h \
-  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/m32c.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/safe-ctype.h
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/m32c-opc.h \
+  $(srcdir)/../opcodes/cgen-types.h ../bfd/bfd_stdint.h \
+  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h
 
-DEPTC_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32r-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+DEPTC_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
   $(srcdir)/../opcodes/m32r-opc.h cgen.h $(INCDIR)/elf/m32r.h \
   $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
-  cgen.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h \
-  $(INCDIR)/elf/m68hc11.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/m68hc11.h $(INCDIR)/elf/m68hc11.h \
+DEPTC_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h $(INCDIR)/elf/m68hc11.h \
   $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h subsegs.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+DEPTC_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
   $(srcdir)/config/m68k-parse.h
 
-DEPTC_m68k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
-  subsegs.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/m68k.h $(srcdir)/config/m68k-parse.h
+DEPTC_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+  $(srcdir)/config/m68k-parse.h
 
-DEPTC_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h subsegs.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+DEPTC_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
   $(srcdir)/config/m68k-parse.h $(INCDIR)/elf/m68k.h \
   $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
-  $(INCDIR)/safe-ctype.h
+DEPTC_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/opcode/maxq.h
 
-DEPTC_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
+DEPTC_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/mcore-opc.h $(INCDIR)/safe-ctype.h
+
+DEPTC_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+DEPTC_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h ecoff.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mep-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/mep-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h \
+  $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h
 
-DEPTC_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h itbl-ops.h \
   dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h \
-  $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/elf/external.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
-DEPTC_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
+DEPTC_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h
+
+DEPTC_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h \
+  itbl-ops.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(srcdir)/config/obj-elf.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
-DEPTC_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
+DEPTC_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/mmix.h \
-  $(INCDIR)/safe-ctype.h
-
-DEPTC_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/mn10200.h
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/obstack.h
 
-DEPTC_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/mn10200.h
 
-DEPTC_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/mn10300.h \
-  dwarf2dbg.h
-
-DEPTC_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/mn10300.h
-
-DEPTC_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/msp430.h $(INCDIR)/safe-ctype.h dwarf2dbg.h
+DEPTC_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/mn10300.h dwarf2dbg.h
 
-DEPTC_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
-  $(INCDIR)/safe-ctype.h
+DEPTC_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h
 
-DEPTC_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
+DEPTC_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mt-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/mt-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mt.h $(INCDIR)/elf/reloc-macros.h \
+  $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
 
-DEPTC_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ns32k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ns32k.h \
+DEPTC_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ns32k.h \
   $(INCDIR)/obstack.h
 
-DEPTC_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
-
-DEPTC_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/openrisc-opc.h \
-  cgen.h
-
-DEPTC_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+DEPTC_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
   dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/openrisc-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/openrisc-opc.h cgen.h
-
-DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h \
-  $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/openrisc-opc.h \
+  cgen.h
 
-DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-or32.h dwarf2dbg.h $(INCDIR)/opcode/or32.h \
-  $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
+DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
+  dwarf2dbg.h $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h \
+  $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pdp11.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/pdp11.h
 
-DEPTC_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
+DEPTC_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
 
-DEPTC_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/pj.h
+DEPTC_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
 
-DEPTC_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
+DEPTC_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/opcode/ppc.h
 
-DEPTC_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+DEPTC_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h
-
-DEPTC_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h \
-  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
 
-DEPTC_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
-  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/opcode/s390.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
-  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
+DEPTC_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/score-inst.h $(INCDIR)/opcode/score-datadep.h \
+  struc-symbol.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h
 
-DEPTC_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h $(INCDIR)/elf/sh.h \
-  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
+DEPTC_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
-DEPTC_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
+DEPTC_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h subsegs.h \
+  $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+
+DEPTC_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
   $(srcdir)/config/tc-sh.c subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/sh-opc.h struc-symbol.h dwarf2dbg.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+  $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
-DEPTC_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
-DEPTC_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sparc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
+DEPTC_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
-DEPTC_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
-
-DEPTC_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic30.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
+  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h
 
-DEPTC_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
+DEPTC_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/spu-insns.h
 
-DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/tic4x.h \
-  subsegs.h $(INCDIR)/obstack.h
+DEPTC_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/tic30.h
 
-DEPTC_tic4x_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-tic4x.h dwarf2dbg.h $(INCDIR)/opcode/tic4x.h \
-  subsegs.h $(INCDIR)/obstack.h
+DEPTC_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/tic30.h
 
-DEPTC_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h sb.h macro.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h $(INCDIR)/opcode/tic54x.h
+DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/opcode/tic4x.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/obstack.h
 
-DEPTC_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/safe-ctype.h sb.h macro.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/tic54x.h $(srcdir)/config/obj-coff.h \
+DEPTC_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
-  $(BFDDIR)/libcoff.h
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  sb.h macro.h subsegs.h $(INCDIR)/obstack.h struc-symbol.h \
+  $(INCDIR)/opcode/tic54x.h $(srcdir)/config/obj-coff.h
 
-DEPTC_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/vax.h
+DEPTC_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/v850.h \
+  dwarf2dbg.h
 
-DEPTC_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
-  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/safe-ctype.h \
+DEPTC_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/vax.h
 
-DEPTC_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h \
-  subsegs.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
+DEPTC_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
+  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/vax.h
 
-DEPTC_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/v850.h dwarf2dbg.h
-
-DEPTC_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+DEPTC_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/v850.h
-
-DEPTC_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/xstormy16-opc.h \
-  cgen.h
+  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(srcdir)/../opcodes/xc16x-opc.h cgen.h dwarf2dbg.h \
+  $(INCDIR)/elf/xc16x.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+DEPTC_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
   dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xstormy16-opc.h cgen.h
-
-DEPTC_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xc16x-opc.h cgen.h
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/xstormy16-opc.h \
+  cgen.h
 
-DEPTC_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h sb.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h sb.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/config/tc-xtensa.h subsegs.h $(INCDIR)/obstack.h \
   $(srcdir)/config/xtensa-relax.h $(srcdir)/config/xtensa-istack.h \
-  dwarf2dbg.h struc-symbol.h
-
-DEPTC_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h
-
-DEPTC_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h
+  dwarf2dbg.h struc-symbol.h $(INCDIR)/xtensa-config.h
 
-DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
+DEPTC_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPTC_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
+DEPTC_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/../opcodes/z8k-opc.h
 
 DEPTC_hppa_som = $(srcdir)/config/tc-hppa.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h \
@@ -1422,588 +1294,439 @@ DEPTC_mips_multi = $(DEPTC_mips_coff) $(DEPTC_mips_ecoff) \
   $(DEPTC_mips_elf)
 
 DEPTC_cris_multi = $(DEPTC_cris_aout) $(DEPTC_cris_elf)
-DEPOBJ_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(BFDDIR)/libecoff.h
 
-DEPOBJ_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(BFDDIR)/libecoff.h
+DEPOBJ_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/aout/aout64.h
 
-DEPOBJ_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h \
+DEPOBJ_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h
+DEPOBJ_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
-  $(srcdir)/config/tc-alpha.h
+DEPOBJ_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
+DEPOBJ_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
+DEPOBJ_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_d10v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h \
+DEPOBJ_dlx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_d30v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d30v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_d30v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h \
+DEPOBJ_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_dlx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-dlx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_dlx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
+DEPOBJ_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
+DEPOBJ_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/i370.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
+DEPOBJ_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_hppa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
+DEPOBJ_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ia64_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
-  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_ia64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h \
+DEPOBJ_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i370.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+DEPOBJ_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+DEPOBJ_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
+DEPOBJ_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
+DEPOBJ_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
+DEPOBJ_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-
-DEPOBJ_m68k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h \
+DEPOBJ_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(BFDDIR)/libecoff.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
+DEPOBJ_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/mep.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
+DEPOBJ_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(BFDDIR)/libecoff.h
 
-DEPOBJ_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ns32k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+DEPOBJ_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
   dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_or32_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_or32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_or32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pdp11.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/ppc.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+DEPOBJ_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
+DEPOBJ_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
+DEPOBJ_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h subsegs.h \
   $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-
-DEPOBJ_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sparc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-
-DEPOBJ_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic30.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_tic4x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_tic4x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
+DEPOBJ_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+DEPOBJ_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
+DEPOBJ_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  $(INCDIR)/aout/aout64.h
-
-DEPOBJ_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
+DEPOBJ_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
   dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
+
+DEPOBJ_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 
 DEPOBJ_hppa_som = $(srcdir)/config/obj-som.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(BFDDIR)/som.h \
@@ -2016,458 +1739,385 @@ DEPOBJ_mips_multi = $(DEPOBJ_mips_coff) $(DEPOBJ_mips_ecoff) \
   $(DEPOBJ_mips_elf)
 
 DEPOBJ_cris_multi = $(DEPOBJ_cris_aout) $(DEPOBJ_cris_elf)
-DEP_alpha_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-alpha.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
 DEP_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
-DEP_alpha_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h
+DEP_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h
 
 DEP_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h
-DEP_arc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_arc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h
+DEP_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_arm_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_avr_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-avr.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h
 
-DEP_avr_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h
+DEP_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_bfin_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-bfin.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h
+DEP_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
-DEP_cris_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h
-
-DEP_crx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-crx.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_crx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h
-
-DEP_d10v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d10v.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_d10v_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h
-
-DEP_d30v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d30v.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_d30v_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h
+DEP_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_dlx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  dwarf2dbg.h
+DEP_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h
 
-DEP_fr30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-fr30.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h
 
-DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h
+DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_frv_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-frv.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_frv_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h
+DEP_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h
 
 DEP_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h
-
-DEP_hppa_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-hppa.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_hppa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
-  $(INCDIR)/elf/reloc-macros.h
-
-DEP_ia64_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/symcat.h $(INCDIR)/elf/ia64.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_ia64_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h
+DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
 
-DEP_i370_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i370.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+  $(INCDIR)/elf/reloc-macros.h
 
-DEP_i370_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h
+DEP_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_i386_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h
+DEP_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_i860_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h
+DEP_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_i960_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h
-
-DEP_ip2k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ip2k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 
-DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h
-
-DEP_m32c_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32c.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h
 
-DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h
+DEP_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h
 
-DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h
+DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_m68hc11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68hc11.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h
+DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
 
 DEP_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
+DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
+
+DEP_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h
+DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+
+DEP_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
-DEP_mips_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h
-
-DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h
-
-DEP_mn10200_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10200.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h
 
-DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h
+DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_mn10300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10300.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h
+DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_msp430_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-msp430.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h
+DEP_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
-DEP_ns32k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ns32k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_ns32k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h
-
-DEP_openrisc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-openrisc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  dwarf2dbg.h
+DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+  dwarf2dbg.h $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
 
-DEP_or32_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  dwarf2dbg.h
+DEP_or32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h
 
 DEP_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
-DEP_pdp11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pdp11.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h
-
-DEP_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_pj_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h
+DEP_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
 
-DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h
+DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h
 
-DEP_s390_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-s390.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_s390_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h
+DEP_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_sh_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h
+DEP_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h
 
-DEP_sh64_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h
+DEP_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h
 
 DEP_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h
+DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+
+DEP_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h
 
 DEP_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_tic30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h \
-  $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_tic4x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h \
-  $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_tic54x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h
+DEP_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h
 
 DEP_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
-DEP_vax_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-vax.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_vax_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h
-
-DEP_v850_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/symcat.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_v850_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
-
-DEP_xstormy16_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-xstormy16.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  dwarf2dbg.h
+DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h 
+DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  dwarf2dbg.h $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h
+DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h
 
 DEP_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_z80_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_z8k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_hppa_som = $(BFDDIR)/som.h
 DEP_i386_multi = $(DEP_i386_aout) $(DEP_i386_coff) \
@@ -2489,15 +2139,15 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__confi
 	@for dep in $?; do \
 	  case '$(am__configure_deps)' in \
 	    *$$dep*) \
-	      echo ' cd $(srcdir) && $(AUTOMAKE) --foreign '; \
-	      cd $(srcdir) && $(AUTOMAKE) --foreign  \
+	      echo ' cd $(srcdir) && $(AUTOMAKE) --cygnus '; \
+	      cd $(srcdir) && $(AUTOMAKE) --cygnus  \
 		&& exit 0; \
 	      exit 1;; \
 	  esac; \
 	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  Makefile'; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus  Makefile'; \
 	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --foreign  Makefile
+	  $(AUTOMAKE) --cygnus  Makefile
 .PRECIOUS: Makefile
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	@case '$?' in \
@@ -2856,12 +2506,11 @@ po/POTFILES.in: @MAINT@ Makefile
 diststuff: $(EXTRA_DIST) info
 all: info
 
-$(OBJS): @ALL_OBJ_DEPS@
-
 # Stuff that every object file depends upon.  If anything is removed
 # from this list, remove it from dep-in.sed as well.
-$(OBJS): $(INCDIR)/bin-bugs.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
-	$(INCDIR)/progress.h $(INCDIR)/fopen-same.h \
+$(OBJS): ../bfd/bfd.h $(INCDIR)/symcat.h \
+	$(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h $(INCDIR)/progress.h \
+	$(INCDIR)/fopen-same.h $(INCDIR)/fopen-bin.h $(INCDIR)/fopen-vms.h \
 	$(OBJ_FORMAT_H) $(TARG_CPU_H) $(TARG_ENV_H) \
 	as.h asintl.h bignum.h bit_fix.h config.h emul.h expr.h flonum.h \
 	frags.h hash.h listing.h obj.h read.h symbols.h tc.h write.h
@@ -2901,18 +2550,16 @@ ecoff.o : ecoff.c ecoff.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
 # We need all these explicit rules for the multi stuff.  Because of
 # these rules, we don't need one for OBJ_FORMAT_O.
 
-obj-aout.o : $(srcdir)/config/obj-aout.c
+obj-aout.o : $(srcdir)/config/obj-aout.c $(DEP_@target_cpu_type@_aout)
 	$(COMPILE) -c $(srcdir)/config/obj-aout.c
-obj-coff.o: $(srcdir)/config/obj-coff.c
+obj-coff.o: $(srcdir)/config/obj-coff.c $(DEP_@target_cpu_type@_coff)
 	$(COMPILE) -c $(srcdir)/config/obj-coff.c
-obj-ecoff.o : $(srcdir)/config/obj-ecoff.c
+obj-ecoff.o : $(srcdir)/config/obj-ecoff.c $(DEP_@target_cpu_type@_ecoff)
 	$(COMPILE) -c $(srcdir)/config/obj-ecoff.c
-obj-elf.o : $(srcdir)/config/obj-elf.c
+obj-elf.o : $(srcdir)/config/obj-elf.c $(DEP_@target_cpu_type@_elf)
 	$(COMPILE) -c $(srcdir)/config/obj-elf.c
 obj-evax.o : $(srcdir)/config/obj-evax.c
 	$(COMPILE) -c $(srcdir)/config/obj-evax.c
-obj-ieee.o : $(srcdir)/config/obj-ieee.c
-	$(COMPILE) -c $(srcdir)/config/obj-ieee.c
 obj-multi.o : $(srcdir)/config/obj-multi.c
 	$(COMPILE) -c $(srcdir)/config/obj-multi.c
 obj-som.o : $(srcdir)/config/obj-som.c
@@ -2959,7 +2606,7 @@ m68k-parse.c: $(srcdir)/config/m68k-parse.y
 	  rm -f m68k-parse.y; \
 	else true; fi
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 m68k-parse.o: m68k-parse.c $(srcdir)/config/m68k-parse.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
@@ -2986,12 +2633,12 @@ bfin-lex.o: bfin-lex.c bfin-parse.h $(srcdir)/config/bfin-defs.h
 itbl-lex.c: $(srcdir)/itbl-lex.l
 
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 itbl-lex.o: itbl-lex.c itbl-parse.h $(srcdir)/itbl-lex.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 itbl-parse.o: itbl-parse.c itbl-parse.h $(srcdir)/itbl-ops.h $(srcdir)/itbl-lex.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
@@ -3319,66 +2966,52 @@ dep-am: DEP
 # ANYTHING CHANGED OR ADDED BETWEEN THE WARNING LINES MAY GO AWAY.
 .PHONY: dep dep-in dep-am
 #MKDEP    DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-app.o: app.c $(INCDIR)/symcat.h
-as.o: as.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  output-file.h sb.h macro.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(BFDVER_H)
-atof-generic.o: atof-generic.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h
-cond.o: cond.c $(INCDIR)/symcat.h macro.h sb.h $(INCDIR)/obstack.h
-depend.o: depend.c $(INCDIR)/symcat.h
-dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/elf/dwarf2.h
-dw2gencfi.o: dw2gencfi.c $(INCDIR)/symcat.h dw2gencfi.h \
+app.o: app.c
+as.o: as.c subsegs.h $(INCDIR)/obstack.h output-file.h \
+  sb.h macro.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  ../bfd/bfdver.h
+atof-generic.o: atof-generic.c $(INCDIR)/safe-ctype.h
+cond.o: cond.c sb.h macro.h $(INCDIR)/obstack.h
+depend.o: depend.c
+dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/safe-ctype.h dwarf2dbg.h \
+  $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/elf/dwarf2.h
-ecoff.o: ecoff.c $(INCDIR)/symcat.h ecoff.h
-ehopt.o: ehopt.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/elf/dwarf2.h
-expr.o: expr.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h
-flonum-copy.o: flonum-copy.c $(INCDIR)/symcat.h
+dw2gencfi.o: dw2gencfi.c dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  subsegs.h $(INCDIR)/obstack.h
+ecoff.o: ecoff.c ecoff.h
+ehopt.o: ehopt.c subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/dwarf2.h
+expr.o: expr.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h
+flonum-copy.o: flonum-copy.c
 flonum-konst.o: flonum-konst.c
 flonum-mult.o: flonum-mult.c
-frags.o: frags.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-hash.o: hash.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h
-input-file.o: input-file.c $(INCDIR)/symcat.h input-file.h \
-  $(INCDIR)/safe-ctype.h
-input-scrub.o: input-scrub.c $(INCDIR)/symcat.h input-file.h \
-  sb.h
-listing.o: listing.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
-  $(INCDIR)/safe-ctype.h input-file.h subsegs.h
-literal.o: literal.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-macro.o: macro.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  sb.h macro.h
-messages.o: messages.c $(INCDIR)/symcat.h
-output-file.o: output-file.c $(INCDIR)/symcat.h output-file.h
-read.o: read.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h sb.h macro.h ecoff.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-sb.o: sb.c sb.h $(INCDIR)/symcat.h
-stabs.o: stabs.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
-  subsegs.h ecoff.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
-subsegs.o: subsegs.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-symbols.o: symbols.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h subsegs.h struc-symbol.h
-write.o: write.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  output-file.h dwarf2dbg.h
-itbl-ops.o: itbl-ops.c itbl-ops.h $(INCDIR)/symcat.h
-e-crisaout.o: $(srcdir)/config/e-crisaout.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-criself.o: $(srcdir)/config/e-criself.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386aout.o: $(srcdir)/config/e-i386aout.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386coff.o: $(srcdir)/config/e-i386coff.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386elf.o: $(srcdir)/config/e-i386elf.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-mipsecoff.o: $(srcdir)/config/e-mipsecoff.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-mipself.o: $(srcdir)/config/e-mipself.c $(INCDIR)/symcat.h \
-  emul-target.h
+frags.o: frags.c subsegs.h $(INCDIR)/obstack.h
+hash.o: hash.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h
+input-file.o: input-file.c input-file.h $(INCDIR)/safe-ctype.h
+input-scrub.o: input-scrub.c input-file.h sb.h
+listing.o: listing.c $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  input-file.h subsegs.h
+literal.o: literal.c subsegs.h $(INCDIR)/obstack.h
+macro.o: macro.c $(INCDIR)/safe-ctype.h sb.h macro.h
+messages.o: messages.c
+output-file.o: output-file.c output-file.h
+read.o: read.c $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  sb.h macro.h ecoff.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+sb.o: sb.c sb.h
+stabs.o: stabs.c $(INCDIR)/obstack.h subsegs.h ecoff.h \
+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
+subsegs.o: subsegs.c subsegs.h $(INCDIR)/obstack.h
+symbols.o: symbols.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+  subsegs.h struc-symbol.h
+write.o: write.c subsegs.h $(INCDIR)/obstack.h output-file.h \
+  dwarf2dbg.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+itbl-ops.o: itbl-ops.c itbl-ops.h
+e-crisaout.o: $(srcdir)/config/e-crisaout.c emul-target.h
+e-criself.o: $(srcdir)/config/e-criself.c emul-target.h
+e-i386aout.o: $(srcdir)/config/e-i386aout.c emul-target.h
+e-i386coff.o: $(srcdir)/config/e-i386coff.c emul-target.h
+e-i386elf.o: $(srcdir)/config/e-i386elf.c emul-target.h
+e-mipsecoff.o: $(srcdir)/config/e-mipsecoff.c emul-target.h
+e-mipself.o: $(srcdir)/config/e-mipself.c emul-target.h
 $(OBJS): $(DEP_@target_cpu_type@_@obj_format@)
 $(TARG_CPU_O): $(DEPTC_@target_cpu_type@_@obj_format@)
 $(OBJ_FORMAT_O): $(DEPOBJ_@target_cpu_type@_@obj_format@)
diff --git a/contrib/binutils/gas/NEWS b/contrib/binutils/gas/NEWS
index 4b4d029..bf278ef 100644
--- a/contrib/binutils/gas/NEWS
+++ b/contrib/binutils/gas/NEWS
@@ -1,4 +1,12 @@
 -*- text -*-
+* Support for the National Semiconductor CR16 target has been added.
+
+* Added gas .reloc pseudo.  This is a low-level interface for creating
+  relocations.
+
+* Add support for x86_64 PE+ target.
+
+* Add support for Score target.
 
 * Support for the Infineon XC16X has been added by KPIT Cummins Infosystems.
 
diff --git a/contrib/binutils/gas/acinclude.m4 b/contrib/binutils/gas/acinclude.m4
index 0946e72..fa4c1bc 100644
--- a/contrib/binutils/gas/acinclude.m4
+++ b/contrib/binutils/gas/acinclude.m4
@@ -1,5 +1,3 @@
-sinclude(../bfd/warning.m4)
-
 dnl GAS_CHECK_DECL_NEEDED(name, typedefname, typedef, headers)
 AC_DEFUN([GAS_CHECK_DECL_NEEDED],[
 AC_MSG_CHECKING(whether declaration is required for $1)
@@ -56,19 +54,3 @@ for _gas_uniq_i in _gas_uniq_dummy [$]_gas_uniq_list ; do
 done
 $1=[$]_gas_uniq_newlist
 ])dnl
-
-sinclude(../libtool.m4)
-dnl The lines below arrange for aclocal not to bring libtool.m4
-dnl AM_PROG_LIBTOOL into aclocal.m4, while still arranging for automake
-dnl to add a definition of LIBTOOL to Makefile.in.
-ifelse(yes,no,[
-AC_DEFUN([AM_PROG_LIBTOOL],)
-AC_DEFUN([AC_CHECK_LIBM],)
-AC_SUBST(LIBTOOL)
-])
-
-sinclude(../gettext.m4)
-ifelse(yes,no,[
-AC_DEFUN([CY_WITH_NLS],)
-AC_SUBST(INTLLIBS)
-])
diff --git a/contrib/binutils/gas/aclocal.m4 b/contrib/binutils/gas/aclocal.m4
index cd42673..1182e36 100644
--- a/contrib/binutils/gas/aclocal.m4
+++ b/contrib/binutils/gas/aclocal.m4
@@ -480,27 +480,6 @@ AC_DEFUN([AM_PROG_INSTALL_SH],
 install_sh=${install_sh-"$am_aux_dir/install-sh"}
 AC_SUBST(install_sh)])
 
-# Copyright (C) 2003, 2005  Free Software Foundation, Inc.
-#
-# This file is free software; the Free Software Foundation
-# gives unlimited permission to copy and/or distribute it,
-# with or without modifications, as long as this notice is preserved.
-
-# serial 2
-
-# Check whether the underlying file-system supports filenames
-# with a leading dot.  For instance MS-DOS doesn't.
-AC_DEFUN([AM_SET_LEADING_DOT],
-[rm -rf .tst 2>/dev/null
-mkdir .tst 2>/dev/null
-if test -d .tst; then
-  am__leading_dot=.
-else
-  am__leading_dot=_
-fi
-rmdir .tst 2>/dev/null
-AC_SUBST([am__leading_dot])])
-
 # Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2005
 # Free Software Foundation, Inc.
 #
@@ -910,4 +889,16 @@ AC_SUBST([am__tar])
 AC_SUBST([am__untar])
 ]) # _AM_PROG_TAR
 
+m4_include([../bfd/acinclude.m4])
+m4_include([../bfd/warning.m4])
+m4_include([../config/depstand.m4])
+m4_include([../config/gettext-sister.m4])
+m4_include([../config/lead-dot.m4])
+m4_include([../config/nls.m4])
+m4_include([../config/po.m4])
+m4_include([../config/progtest.m4])
+m4_include([../libtool.m4])
+m4_include([../ltoptions.m4])
+m4_include([../ltsugar.m4])
+m4_include([../ltversion.m4])
 m4_include([acinclude.m4])
diff --git a/contrib/binutils/gas/app.c b/contrib/binutils/gas/app.c
index 275ad68..e5f1778 100644
--- a/contrib/binutils/gas/app.c
+++ b/contrib/binutils/gas/app.c
@@ -1,6 +1,6 @@
 /* This is the Assembler Pre-Processor
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003
+   1999, 2000, 2001, 2002, 2003, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -21,13 +21,12 @@
    02110-1301, USA.  */
 
 /* Modified by Allen Wirfs-Brock, Instantiations Inc 2/90.  */
-/* App, the assembler pre-processor.  This pre-processor strips out excess
-   spaces, turns single-quoted characters into a decimal constant, and turns
-   # <number> <filename> <garbage> into a .line <number>\n.file <filename>
-   pair.  This needs better error-handling.  */
+/* App, the assembler pre-processor.  This pre-processor strips out
+   excess spaces, turns single-quoted characters into a decimal
+   constant, and turns the # in # <number> <filename> <garbage> into a
+   .linefile.  This needs better error-handling.  */
 
-#include <stdio.h>
-#include "as.h"			/* For BAD_CASE() only.  */
+#include "as.h"
 
 #if (__STDC__ != 1)
 #ifndef const
@@ -352,11 +351,11 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	  1: After first whitespace on line (flush more white)
 	  2: After first non-white (opcode) on line (keep 1white)
 	  3: after second white on line (into operands) (flush white)
-	  4: after putting out a .line, put out digits
+	  4: after putting out a .linefile, put out digits
 	  5: parsing a string, then go to old-state
 	  6: putting out \ escape in a "d string.
-	  7: After putting out a .appfile, put out string.
-	  8: After putting out a .appfile string, flush until newline.
+	  7: no longer used
+	  8: no longer used
 	  9: After seeing symbol char in state 3 (keep 1white after symchar)
 	 10: After seeing whitespace in state 9 (keep white before symchar)
 	 11: After seeing a symbol character in state 0 (eg a label definition)
@@ -511,14 +510,10 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 		ch = GET ();
 	      if (ch == '"')
 		{
-		  UNGET (ch);
-		  if (scrub_m68k_mri)
-		    out_string = "\n\tappfile ";
-		  else
-		    out_string = "\n\t.appfile ";
-		  old_state = 7;
-		  state = -1;
-		  PUT (*out_string++);
+		  quotechar = ch;
+		  state = 5;
+		  old_state = 3;
+		  PUT (ch);
 		}
 	      else
 		{
@@ -555,6 +550,8 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 		memcpy (to, from, len);
 		to += len;
 		from += len;
+		if (to >= toend)
+		  goto tofull;
 	      }
 	  }
 
@@ -639,24 +636,6 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	  PUT (ch);
 	  continue;
 
-	case 7:
-	  ch = GET ();
-	  quotechar = ch;
-	  state = 5;
-	  old_state = 8;
-	  PUT (ch);
-	  continue;
-
-	case 8:
-	  do
-	    ch = GET ();
-	  while (ch != '\n' && ch != EOF);
-	  if (ch == EOF)
-	    goto fromeof;
-	  state = 0;
-	  PUT (ch);
-	  continue;
-
 #ifdef DOUBLEBAR_PARALLEL
 	case 13:
 	  ch = GET ();
@@ -888,9 +867,6 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 
 	  switch (state)
 	    {
-	    case 0:
-	      state++;
-	      goto recycle;	/* Punted leading sp */
 	    case 1:
 	      /* We can arrive here if we leave a leading whitespace
 		 character at the beginning of a line.  */
@@ -1200,9 +1176,9 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	      old_state = 4;
 	      state = -1;
 	      if (scrub_m68k_mri)
-		out_string = "\tappline ";
+		out_string = "\tlinefile ";
 	      else
-		out_string = "\t.appline ";
+		out_string = "\t.linefile ";
 	      PUT (*out_string++);
 	      break;
 	    }
@@ -1245,6 +1221,15 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	  if ((symver_state != NULL) && (*symver_state == 0))
 	    goto de_fault;
 #endif
+
+#ifdef TC_ARM
+	  /* For the ARM, care is needed not to damage occurrences of \@
+	     by stripping the @ onwards.  Yuck.  */
+	  if (to > tostart && *(to - 1) == '\\')
+	    /* Do not treat the @ as a start-of-comment.  */
+	    goto de_fault;
+#endif
+
 #ifdef WARN_COMMENTS
 	  if (!found_comment)
 	    as_where (&found_comment_file, &found_comment);
@@ -1377,7 +1362,15 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 		     the space.  We don't have enough information to
 		     make the right choice, so here we are making the
 		     choice which is more likely to be correct.  */
-		  PUT (' ');
+		  if (to + 1 >= toend)
+		    {
+		      /* If we're near the end of the buffer, save the
+		         character for the next time round.  Otherwise
+		         we'll lose our state.  */
+		      UNGET (ch);
+		      goto tofull;
+		    }
+		  *to++ = ' ';
 		}
 
 	      state = 3;
diff --git a/contrib/binutils/gas/as.c b/contrib/binutils/gas/as.c
index 727a1dd..b05f9d5 100644
--- a/contrib/binutils/gas/as.c
+++ b/contrib/binutils/gas/as.c
@@ -1,6 +1,6 @@
 /* as.c - GAS main program.
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -31,8 +31,6 @@
   	Since no-one else says they will support them in future: I
    don't support them now.  */
 
-#include "ansidecl.h"
-
 #define COMMON
 
 #include "as.h"
@@ -42,7 +40,6 @@
 #include "macro.h"
 #include "dwarf2dbg.h"
 #include "dw2gencfi.h"
-#include "hash.h"
 #include "bfdver.h"
 
 #ifdef HAVE_ITBL_CPU
@@ -352,7 +349,9 @@ Options:\n\
   md_show_usage (stream);
 
   fputc ('\n', stream);
-  fprintf (stream, _("Report bugs to %s\n"), REPORT_BUGS_TO);
+
+  if (REPORT_BUGS_TO[0] && stream == stdout)
+    fprintf (stream, _("Report bugs to %s\n"), REPORT_BUGS_TO);
 }
 
 /* Since it is easy to do here we interpret the special arg "-"
@@ -591,7 +590,7 @@ parse_args (int * pargc, char *** pargv)
 	case OPTION_VERSION:
 	  /* This output is intended to follow the GNU standards document.  */
 	  printf (_("GNU assembler %s\n"), BFD_VERSION_STRING);
-	  printf (_("Copyright 2005 Free Software Foundation, Inc.\n"));
+	  printf (_("Copyright 2007 Free Software Foundation, Inc.\n"));
 	  printf (_("\
 This program is free software; you may redistribute it under the terms of\n\
 the GNU General Public License.  This program has absolutely no warranty.\n"));
@@ -1032,6 +1031,33 @@ perform_an_assembly_pass (int argc, char ** argv)
     read_a_source_file ("");
 }
 
+#ifdef OBJ_ELF
+static void
+create_obj_attrs_section (void)
+{
+  segT s;
+  char *p;
+  addressT addr;
+  offsetT size;
+  const char *name;
+
+  size = bfd_elf_obj_attr_size (stdoutput);
+  if (size)
+    {
+      name = get_elf_backend_data (stdoutput)->obj_attrs_section;
+      if (!name)
+	name = ".gnu.attributes";
+      s = subseg_new (name, 0);
+      elf_section_type (s)
+	= get_elf_backend_data (stdoutput)->obj_attrs_section_type;
+      bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
+      addr = frag_now_fix ();
+      p = frag_more (size);
+      bfd_elf_set_obj_attr_contents (stdoutput, (bfd_byte *)p, size);
+    }
+}
+#endif
+
 
 int
 main (int argc, char ** argv)
@@ -1125,6 +1151,11 @@ main (int argc, char ** argv)
 
       sym = symbol_new (defsyms->name, absolute_section, defsyms->value,
 			&zero_address_frag);
+      /* Make symbols defined on the command line volatile, so that they
+	 can be redefined inside a source file.  This makes this assembler's
+	 behaviour compatible with earlier versions, but it may not be
+	 completely intuitive.  */
+      S_SET_VOLATILE (sym);
       symbol_table_insert (sym);
       next = defsyms->next;
       free (defsyms);
@@ -1142,6 +1173,11 @@ main (int argc, char ** argv)
   md_end ();
 #endif
 
+#ifdef OBJ_ELF
+  if (IS_ELF)
+    create_obj_attrs_section ();
+#endif
+
 #if defined OBJ_ELF || defined OBJ_MAYBE_ELF
   if ((flag_execstack || flag_noexecstack)
       && OUTPUT_FLAVOR == bfd_target_elf_flavour)
diff --git a/contrib/binutils/gas/as.h b/contrib/binutils/gas/as.h
index 2f92c2e..4ea63ab 100644
--- a/contrib/binutils/gas/as.h
+++ b/contrib/binutils/gas/as.h
@@ -1,6 +1,6 @@
 /* as.h - global header file
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -37,7 +37,6 @@
    If TEST is #defined, then we are testing a module: #define COMMON as "".  */
 
 #include "config.h"
-#include "bin-bugs.h"
 
 /* This is the code recommended in the autoconf documentation, almost
    verbatim.  If it doesn't work for you, let me know, and notify
@@ -210,7 +209,7 @@ extern int vsnprintf(char *, size_t, const char *, va_list);
 #endif /* __FILE__ */
 
 #ifndef FOPEN_WB
-#if defined GO32 || defined __MINGW32__
+#ifdef USE_BINARY_FOPEN
 #include "fopen-bin.h"
 #else
 #include "fopen-same.h"
@@ -259,7 +258,11 @@ typedef addressT valueT;
 #endif
 /* COMMON now defined */
 
-#ifdef DEBUG
+#ifndef ENABLE_CHECKING
+#define ENABLE_CHECKING 0
+#endif
+
+#if ENABLE_CHECKING || defined (DEBUG)
 #ifndef know
 #define know(p) assert(p)	/* Verify our assumptions!  */
 #endif /* not yet defined */
@@ -544,7 +547,6 @@ void   cond_finish_check (int);
 void   cond_exit_macro (int);
 int    seen_at_least_1_file (void);
 void   app_pop (char *);
-void   as_perror (const char *, const char *);
 void   as_where (char **, unsigned int *);
 void   bump_line_counters (void);
 void   do_scrub_begin (int);
@@ -552,6 +554,7 @@ void   input_scrub_begin (void);
 void   input_scrub_close (void);
 void   input_scrub_end (void);
 int    new_logical_line (char *, int);
+int    new_logical_line_flags (char *, int, int);
 void   subsegs_begin (void);
 void   subseg_change (segT, int);
 segT   subseg_new (const char *, subsegT);
@@ -567,7 +570,6 @@ segT   subseg_get (const char *, int);
 struct expressionS;
 struct fix;
 typedef struct symbol symbolS;
-struct relax_type;
 typedef struct frag fragS;
 
 /* literal.c */
diff --git a/contrib/binutils/gas/atof-generic.c b/contrib/binutils/gas/atof-generic.c
index 6a5c2f1..3021c4c 100644
--- a/contrib/binutils/gas/atof-generic.c
+++ b/contrib/binutils/gas/atof-generic.c
@@ -1,6 +1,6 @@
 /* atof_generic.c - turn a string of digits into a Flonum
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1998, 1999, 2000,
-   2001, 2003, 2005 Free Software Foundation, Inc.
+   2001, 2003, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,8 +19,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <string.h>
-
 #include "as.h"
 #include "safe-ctype.h"
 
diff --git a/contrib/binutils/gas/cgen.c b/contrib/binutils/gas/cgen.c
index 363c05e..5b0694b 100644
--- a/contrib/binutils/gas/cgen.c
+++ b/contrib/binutils/gas/cgen.c
@@ -1,6 +1,6 @@
 /* GAS interface for targets using CGEN: Cpu tools GENerator.
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
-   Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+   2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,16 +19,34 @@
    Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #include <setjmp.h>
-#include "ansidecl.h"
-#include "libiberty.h"
-#include "bfd.h"
+#include "as.h"
 #include "symcat.h"
 #include "cgen-desc.h"
-#include "as.h"
 #include "subsegs.h"
 #include "cgen.h"
 #include "dwarf2dbg.h"
 
+#include "symbols.h"
+#include "struc-symbol.h"
+
+#ifdef OBJ_COMPLEX_RELC
+static expressionS * make_right_shifted_expr
+  (expressionS *, const int, const int);
+
+static unsigned long gas_cgen_encode_addend
+  (const unsigned long, const unsigned long, const unsigned long, \
+   const unsigned long, const unsigned long, const unsigned long, \
+   const unsigned long);
+
+static char * weak_operand_overflow_check
+  (const expressionS *, const CGEN_OPERAND *);
+
+static void queue_fixup_recursively
+  (const int, const int, expressionS *, \
+   const CGEN_MAYBE_MULTI_IFLD *, const int, const int);
+
+static int rightshift = 0;
+#endif
 static void queue_fixup (int, int, expressionS *);
 
 /* Opcode table descriptor, must be set by md_begin.  */
@@ -66,6 +84,8 @@ struct fixup
   int opindex;
   int opinfo;
   expressionS exp;
+  struct cgen_maybe_multi_ifield * field;
+  int msb_field_p;
 };
 
 static struct fixup fixups[GAS_CGEN_MAX_FIXUPS];
@@ -249,6 +269,8 @@ gas_cgen_record_fixup (frag, where, insn, length, operand, opinfo, symbol, offse
 		     + (int) operand->type));
   fixP->fx_cgen.insn = insn;
   fixP->fx_cgen.opinfo = opinfo;
+  fixP->fx_cgen.field = NULL;
+  fixP->fx_cgen.msb_field_p = 0;
 
   return fixP;
 }
@@ -287,10 +309,26 @@ gas_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
 			 + (int) operand->type));
   fixP->fx_cgen.insn = insn;
   fixP->fx_cgen.opinfo = opinfo;
+  fixP->fx_cgen.field = NULL;
+  fixP->fx_cgen.msb_field_p = 0;
 
   return fixP;
 }
 
+#ifdef OBJ_COMPLEX_RELC
+static symbolS *
+expr_build_binary (operatorT op, symbolS * s1, symbolS * s2)
+{
+  expressionS e;
+
+  e.X_op = op;
+  e.X_add_symbol = s1;
+  e.X_op_symbol = s2;
+  e.X_add_number = 0;
+  return make_expr_symbol (& e);
+}
+#endif
+
 /* Used for communication between the next two procedures.  */
 static jmp_buf expr_jmp_buf;
 static int expr_jmp_buf_p;
@@ -308,7 +346,12 @@ static int expr_jmp_buf_p;
 
 const char *
 gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
+
+#ifdef OBJ_COMPLEX_RELC
+     CGEN_CPU_DESC cd;
+#else
      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+#endif
      enum cgen_parse_operand_type want;
      const char **strP;
      int opindex;
@@ -329,6 +372,13 @@ gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
   const char *errmsg;
   expressionS exp;
 
+#ifdef OBJ_COMPLEX_RELC
+  volatile int              signed_p = 0;
+  symbolS *                 stmp = NULL;
+  bfd_reloc_code_real_type  reloc_type;
+  const CGEN_OPERAND *      operand;
+  fixS                      dummy_fixup;
+#endif
   if (want == CGEN_PARSE_OPERAND_INIT)
     {
       gas_cgen_init_parse ();
@@ -386,9 +436,82 @@ gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
       break;
     de_fault:
     default:
+#ifdef OBJ_COMPLEX_RELC
+      /* Look up operand, check to see if there's an obvious
+	 overflow (this helps disambiguate some insn parses).  */
+      operand = cgen_operand_lookup_by_num (cd, opindex);
+      errmsg = weak_operand_overflow_check (& exp, operand);
+
+      if (! errmsg)
+	{
+	  /* Fragment the expression as necessary, and queue a reloc.  */
+	  memset (& dummy_fixup, 0, sizeof (fixS));
+
+	  reloc_type = md_cgen_lookup_reloc (0, operand, & dummy_fixup);
+
+	  if (exp.X_op == O_symbol
+	      && reloc_type == BFD_RELOC_RELC
+	      && exp.X_add_symbol->sy_value.X_op == O_constant
+	      && exp.X_add_symbol->bsym->section != expr_section
+	      && exp.X_add_symbol->bsym->section != absolute_section
+	      && exp.X_add_symbol->bsym->section != undefined_section)
+	    {
+	      /* Local labels will have been (eagerly) turned into constants
+		 by now, due to the inappropriately deep insight of the
+		 expression parser.  Unfortunately make_expr_symbol
+		 prematurely dives into the symbol evaluator, and in this
+		 case it gets a bad answer, so we manually create the
+		 expression symbol we want here.  */
+	      stmp = symbol_create (FAKE_LABEL_NAME, expr_section, 0,
+				    & zero_address_frag);
+	      symbol_set_value_expression (stmp, & exp);
+	    } 
+	  else 
+	    stmp = make_expr_symbol (& exp);
+
+	  /* If this is a pc-relative RELC operand, we
+	     need to subtract "." from the expression.  */	  
+ 	  if (reloc_type == BFD_RELOC_RELC
+	      && CGEN_OPERAND_ATTR_VALUE (operand, CGEN_OPERAND_PCREL_ADDR))
+ 	    stmp = expr_build_binary (O_subtract, stmp, expr_build_dot ()); 
+
+	  /* FIXME: this is not a perfect heuristic for figuring out
+	     whether an operand is signed: it only works when the operand
+	     is an immediate. it's not terribly likely that any other
+	     values will be signed relocs, but it's possible. */
+	  if (operand && (operand->hw_type == HW_H_SINT))
+	    signed_p = 1;
+	  
+	  if (stmp->bsym && (stmp->bsym->section == expr_section))
+	    {
+	      if (signed_p)
+		stmp->bsym->flags |= BSF_SRELC;
+	      else
+		stmp->bsym->flags |= BSF_RELC;
+	    }
+	  
+	  /* Now package it all up for the fixup emitter.  */
+	  exp.X_op = O_symbol;
+	  exp.X_op_symbol = 0;
+	  exp.X_add_symbol = stmp;
+	  exp.X_add_number = 0;
+	      
+	  /* Re-init rightshift quantity, just in case.  */
+	  rightshift = operand->length;
+	  queue_fixup_recursively (opindex, opinfo_1, & exp,  
+				   (reloc_type == BFD_RELOC_RELC) ?
+				   & (operand->index_fields) : 0,
+				   signed_p, -1);
+	}
+      * resultP = errmsg
+	? CGEN_PARSE_OPERAND_RESULT_ERROR
+	: CGEN_PARSE_OPERAND_RESULT_QUEUED;
+      *valueP = 0;
+#else
       queue_fixup (opindex, opinfo_1, &exp);
       *valueP = 0;
       *resultP = CGEN_PARSE_OPERAND_RESULT_QUEUED;
+#endif      
       break;
     }
 
@@ -556,6 +679,8 @@ gas_cgen_finish_insn (insn, buf, length, relax_p, result)
 				       insn, length, operand,
 				       fixups[i].opinfo,
 				       &fixups[i].exp);
+      fixP->fx_cgen.field = fixups[i].field;
+      fixP->fx_cgen.msb_field_p = fixups[i].msb_field_p;
       if (result)
 	result->fixups[i] = fixP;
     }
@@ -567,6 +692,167 @@ gas_cgen_finish_insn (insn, buf, length, relax_p, result)
     }
 }
 
+#ifdef OBJ_COMPLEX_RELC
+/* Queue many fixups, recursively. If the field is a multi-ifield,
+   repeatedly queue its sub-parts, right shifted to fit into the field (we
+   assume here multi-fields represent a left-to-right, MSB0-LSB0
+   reading). */
+
+static void
+queue_fixup_recursively (const int                      opindex,
+			 const int                      opinfo,
+			 expressionS *                  expP,
+			 const CGEN_MAYBE_MULTI_IFLD *  field,
+			 const int                      signed_p,
+			 const int                      part_of_multi)
+{
+  if (field && field->count)
+    {
+      int i;
+  
+      for (i = 0; i < field->count; ++ i)
+	queue_fixup_recursively (opindex, opinfo, expP, 
+				 & (field->val.multi[i]), signed_p, i);
+    }
+  else
+    {
+      expressionS * new_exp = expP;
+
+#ifdef DEBUG
+      printf ("queueing fixup for field %s\n",
+	      (field ? field->val.leaf->name : "??"));
+      print_symbol_value (expP->X_add_symbol);
+#endif
+      if (field && part_of_multi != -1)
+	{
+	  rightshift -= field->val.leaf->length;
+
+	  /* Shift reloc value by number of bits remaining after this
+	     field.  */
+	  if (rightshift)
+	    new_exp = make_right_shifted_expr (expP, rightshift, signed_p);	  
+	}
+      
+      /* Truncate reloc values to length, *after* leftmost one.  */
+      fixups[num_fixups].msb_field_p = (part_of_multi <= 0);
+      fixups[num_fixups].field = (CGEN_MAYBE_MULTI_IFLD *) field;
+      
+      queue_fixup (opindex, opinfo, new_exp);
+    }
+}
+
+/* Encode the self-describing RELC reloc format's addend.  */
+
+static unsigned long 
+gas_cgen_encode_addend (const unsigned long start,    /* in bits */
+			const unsigned long len,      /* in bits */
+			const unsigned long oplen,    /* in bits */
+			const unsigned long wordsz,   /* in bytes */
+			const unsigned long chunksz,  /* in bytes */
+			const unsigned long signed_p,
+			const unsigned long trunc_p)
+{
+  unsigned long res = 0L;
+
+  res |= start    & 0x3F;
+  res |= (oplen   & 0x3F) << 6;
+  res |= (len     & 0x3F) << 12;
+  res |= (wordsz  & 0xF)  << 18;
+  res |= (chunksz & 0xF)  << 22;
+  res |= (CGEN_INSN_LSB0_P ? 1 : 0) << 27;
+  res |= signed_p << 28;
+  res |= trunc_p << 29;
+
+  return res;
+}
+
+/* Purpose: make a weak check that the expression doesn't overflow the
+   operand it's to be inserted into.
+
+   Rationale: some insns used to use %operators to disambiguate during a
+   parse. when these %operators are translated to expressions by the macro
+   expander, the ambiguity returns. we attempt to disambiguate by field
+   size.
+   
+   Method: check to see if the expression's top node is an O_and operator,
+   and the mask is larger than the operand length. This would be an
+   overflow, so signal it by returning an error string. Any other case is
+   ambiguous, so we assume it's OK and return NULL.  */
+
+static char *
+weak_operand_overflow_check (const expressionS *  exp,
+			     const CGEN_OPERAND * operand)
+{
+  const unsigned long len = operand->length;
+  unsigned long mask;
+  unsigned long opmask = (((1L << (len - 1)) - 1) << 1) | 1;
+
+  if (!exp)
+    return NULL;
+
+  if (exp->X_op != O_bit_and)
+    {
+      /* Check for implicit overflow flag.  */
+      if (CGEN_OPERAND_ATTR_VALUE 
+	  (operand, CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW))
+	return _("a reloc on this operand implies an overflow");
+      return NULL;
+    }
+  
+  mask = exp->X_add_number;
+
+  if (exp->X_add_symbol &&
+      exp->X_add_symbol->sy_value.X_op == O_constant)
+    mask |= exp->X_add_symbol->sy_value.X_add_number;
+
+  if (exp->X_op_symbol &&
+      exp->X_op_symbol->sy_value.X_op == O_constant)
+    mask |= exp->X_op_symbol->sy_value.X_add_number;
+
+  /* Want to know if mask covers more bits than opmask. 
+     this is the same as asking if mask has any bits not in opmask,
+     or whether (mask & ~opmask) is nonzero.  */
+  if (mask && (mask & ~opmask))
+    {
+#ifdef DEBUG
+      printf ("overflow: (mask = %8.8x, ~opmask = %8.8x, AND = %8.8x)\n",
+	      mask, ~opmask, (mask & ~opmask));
+#endif
+      return _("operand mask overflow");
+    }
+
+  return NULL;  
+}
+
+
+static expressionS *
+make_right_shifted_expr (expressionS * exp,
+			 const int     amount,
+			 const int     signed_p)
+{
+  symbolS * stmp = 0;
+  expressionS * new_exp;
+
+  stmp = expr_build_binary (O_right_shift, 
+			    make_expr_symbol (exp),
+			    expr_build_uconstant (amount));
+  
+  if (signed_p)
+    stmp->bsym->flags |= BSF_SRELC;
+  else
+    stmp->bsym->flags |= BSF_RELC;
+  
+  /* Then wrap that in a "symbol expr" for good measure.  */
+  new_exp = xmalloc (sizeof (expressionS));
+  memset (new_exp, 0, sizeof (expressionS));
+  new_exp->X_op = O_symbol;
+  new_exp->X_op_symbol = 0;
+  new_exp->X_add_symbol = stmp;
+  new_exp->X_add_number = 0;
+  
+  return new_exp;
+}
+#endif
 /* Apply a fixup to the object code.  This is called for all the
    fixups we generated by the call to fix_new_exp, above.  In the call
    above we used a reloc code which was the largest legal reloc code
@@ -605,6 +891,30 @@ gas_cgen_md_apply_fix (fixP, valP, seg)
       bfd_reloc_code_real_type reloc_type;
       CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
       const CGEN_INSN *insn = fixP->fx_cgen.insn;
+      int start;
+      int length;
+      int signed_p = 0;
+
+      if (fixP->fx_cgen.field)
+	{	      
+	  /* Use the twisty little pointer path
+	     back to the ifield if it exists.  */
+	  start = fixP->fx_cgen.field->val.leaf->start;
+	  length = fixP->fx_cgen.field->val.leaf->length;
+	}
+      else
+	{
+	  /* Or the far less useful operand-size guesstimate.  */
+	  start = operand->start;
+	  length = operand->length;
+	}
+
+      /* FIXME: this is not a perfect heuristic for figuring out
+         whether an operand is signed: it only works when the operand
+         is an immediate. it's not terribly likely that any other
+         values will be signed relocs, but it's possible. */
+      if (operand && (operand->hw_type == HW_H_SINT))
+        signed_p = 1;
 
       /* If the reloc has been fully resolved finish the operand here.  */
       /* FIXME: This duplicates the capabilities of code in BFD.  */
@@ -647,6 +957,18 @@ gas_cgen_md_apply_fix (fixP, valP, seg)
 	 partial_inplace == false.  */
 
       reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+#ifdef OBJ_COMPLEX_RELC
+      if (reloc_type == BFD_RELOC_RELC)
+	{
+	  /* Change addend to "self-describing" form,
+	     for BFD to handle in the linker.  */
+	  value = gas_cgen_encode_addend (start, operand->length,
+					  length, fixP->fx_size, 
+					  cd->insn_chunk_bitsize / 8, 
+					  signed_p, 
+					  ! (fixP->fx_cgen.msb_field_p));
+	}
+#endif
 
       if (reloc_type != BFD_RELOC_NONE)
 	fixP->fx_r_type = reloc_type;
@@ -702,7 +1024,6 @@ gas_cgen_tc_gen_reloc (section, fixP)
      fixS *     fixP;
 {
   arelent *reloc;
-
   reloc = (arelent *) xmalloc (sizeof (arelent));
 
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
@@ -740,3 +1061,4 @@ gas_cgen_begin ()
   else
     cgen_clear_signed_overflow_ok (gas_cgen_cpu_desc);
 }
+
diff --git a/contrib/binutils/gas/cond.c b/contrib/binutils/gas/cond.c
index d6c32ac..d76e4d9 100644
--- a/contrib/binutils/gas/cond.c
+++ b/contrib/binutils/gas/cond.c
@@ -1,6 +1,6 @@
 /* cond.c - conditional assembly pseudo-ops, and .include
    Copyright 1990, 1991, 1992, 1993, 1995, 1997, 1998, 2000, 2001, 2002,
-   2003 Free Software Foundation, Inc.
+   2003, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -20,6 +20,7 @@
    02110-1301, USA.  */
 
 #include "as.h"
+#include "sb.h"
 #include "macro.h"
 
 #include "obstack.h"
diff --git a/contrib/binutils/gas/config.in b/contrib/binutils/gas/config.in
index b15d802..20d5df9 100644
--- a/contrib/binutils/gas/config.in
+++ b/contrib/binutils/gas/config.in
@@ -29,7 +29,11 @@
 /* Supported emulations. */
 #undef EMULATIONS
 
-/* Define to 1 if NLS is requested */
+/* Define if you want run-time sanity checks. */
+#undef ENABLE_CHECKING
+
+/* Define to 1 if translation of program messages to the user's native
+   language is requested. */
 #undef ENABLE_NLS
 
 /* Define to 1 if you have `alloca', as a function or macro. */
@@ -39,12 +43,6 @@
    */
 #undef HAVE_ALLOCA_H
 
-/* Define to 1 if you have the <argz.h> header file. */
-#undef HAVE_ARGZ_H
-
-/* Define to 1 if you have the `dcgettext' function. */
-#undef HAVE_DCGETTEXT
-
 /* Is the prototype for getopt in <unistd.h> in the expected format? */
 #undef HAVE_DECL_GETOPT
 
@@ -52,60 +50,24 @@
    don't. */
 #undef HAVE_DECL_VSNPRINTF
 
+/* Define to 1 if you have the <dlfcn.h> header file. */
+#undef HAVE_DLFCN_H
+
 /* Define to 1 if you have the <errno.h> header file. */
 #undef HAVE_ERRNO_H
 
-/* Define to 1 if you have the `getcwd' function. */
-#undef HAVE_GETCWD
-
-/* Define to 1 if you have the `getpagesize' function. */
-#undef HAVE_GETPAGESIZE
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext. */
-#undef HAVE_GETTEXT
-
 /* Define to 1 if you have the <inttypes.h> header file. */
 #undef HAVE_INTTYPES_H
 
-/* Define if your locale.h file contains LC_MESSAGES. */
-#undef HAVE_LC_MESSAGES
-
-/* Define to 1 if you have the <limits.h> header file. */
-#undef HAVE_LIMITS_H
-
-/* Define to 1 if you have the <locale.h> header file. */
-#undef HAVE_LOCALE_H
-
-/* Define to 1 if you have the <malloc.h> header file. */
-#undef HAVE_MALLOC_H
-
 /* Define to 1 if you have the <memory.h> header file. */
 #undef HAVE_MEMORY_H
 
-/* Define to 1 if you have a working `mmap' system call. */
-#undef HAVE_MMAP
-
-/* Define to 1 if you have the `munmap' function. */
-#undef HAVE_MUNMAP
-
-/* Define to 1 if you have the <nl_types.h> header file. */
-#undef HAVE_NL_TYPES_H
-
-/* Define to 1 if you have the `putenv' function. */
-#undef HAVE_PUTENV
-
 /* Define to 1 if you have the `remove' function. */
 #undef HAVE_REMOVE
 
 /* Define to 1 if you have the `sbrk' function. */
 #undef HAVE_SBRK
 
-/* Define to 1 if you have the `setenv' function. */
-#undef HAVE_SETENV
-
-/* Define to 1 if you have the `setlocale' function. */
-#undef HAVE_SETLOCALE
-
 /* Define to 1 if you have the <stdarg.h> header file. */
 #undef HAVE_STDARG_H
 
@@ -115,24 +77,12 @@
 /* Define to 1 if you have the <stdlib.h> header file. */
 #undef HAVE_STDLIB_H
 
-/* Define if you have the stpcpy function */
-#undef HAVE_STPCPY
-
-/* Define to 1 if you have the `strcasecmp' function. */
-#undef HAVE_STRCASECMP
-
-/* Define to 1 if you have the `strchr' function. */
-#undef HAVE_STRCHR
-
 /* Define to 1 if you have the <strings.h> header file. */
 #undef HAVE_STRINGS_H
 
 /* Define to 1 if you have the <string.h> header file. */
 #undef HAVE_STRING_H
 
-/* Define to 1 if you have the <sys/param.h> header file. */
-#undef HAVE_SYS_PARAM_H
-
 /* Define to 1 if you have the <sys/stat.h> header file. */
 #undef HAVE_SYS_STAT_H
 
@@ -145,24 +95,16 @@
 /* Define to 1 if you have the `unlink' function. */
 #undef HAVE_UNLINK
 
-/* Define to 1 if you have the <values.h> header file. */
-#undef HAVE_VALUES_H
-
 /* Define to 1 if you have the <varargs.h> header file. */
 #undef HAVE_VARARGS_H
 
-/* Define to 1 if you have the `__argz_count' function. */
-#undef HAVE___ARGZ_COUNT
-
-/* Define to 1 if you have the `__argz_next' function. */
-#undef HAVE___ARGZ_NEXT
-
-/* Define to 1 if you have the `__argz_stringify' function. */
-#undef HAVE___ARGZ_STRINGIFY
-
 /* Using i386 COFF? */
 #undef I386COFF
 
+/* Define to the sub-directory in which libtool stores uninstalled libraries.
+   */
+#undef LT_OBJDIR
+
 /* Using m68k COFF? */
 #undef M68KCOFF
 
@@ -217,9 +159,6 @@
 /* generic support? */
 #undef OBJ_MAYBE_GENERIC
 
-/* IEEE support? */
-#undef OBJ_MAYBE_IEEE
-
 /* SOM support? */
 #undef OBJ_MAYBE_SOM
 
@@ -282,6 +221,9 @@
 /* Target vendor. */
 #undef TARGET_VENDOR
 
+/* Use b modifier when opening binary files? */
+#undef USE_BINARY_FOPEN
+
 /* Use emulation support? */
 #undef USE_EMULATIONS
 
@@ -302,17 +244,8 @@
    `char[]'. */
 #undef YYTEXT_POINTER
 
-/* Define to empty if `const' does not conform to ANSI C. */
-#undef const
-
 /* Define to `__inline__' or `__inline' if that's what the C compiler
    calls it, or to nothing if 'inline' is not supported under any name.  */
 #ifndef __cplusplus
 #undef inline
 #endif
-
-/* Define to `long' if <sys/types.h> does not define. */
-#undef off_t
-
-/* Define to `unsigned' if <sys/types.h> does not define. */
-#undef size_t
diff --git a/contrib/binutils/gas/config/atof-vax.c b/contrib/binutils/gas/config/atof-vax.c
index 75756904..fe9f8b9 100644
--- a/contrib/binutils/gas/config/atof-vax.c
+++ b/contrib/binutils/gas/config/atof-vax.c
@@ -1,5 +1,5 @@
 /* atof_vax.c - turn a Flonum into a VAX floating point number
-   Copyright 1987, 1992, 1993, 1995, 1997, 1999, 2000, 2005
+   Copyright 1987, 1992, 1993, 1995, 1997, 1999, 2000, 2005, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -35,7 +35,7 @@ int flonum_gen2vax (int, FLONUM_TYPE *, LITTLENUM_TYPE *);
 
 /* Number of chars in flonum type 'letter'.  */
 
-static int
+static unsigned int
 atof_vax_sizeof (int letter)
 {
   int return_value;
@@ -395,7 +395,7 @@ md_atof (int what_statement_type,
 {
   LITTLENUM_TYPE words[MAXIMUM_NUMBER_OF_LITTLENUMS];
   char kind_of_float;
-  int number_of_chars;
+  unsigned int number_of_chars;
   LITTLENUM_TYPE *littlenumP;
 
   switch (what_statement_type)
diff --git a/contrib/binutils/gas/config/obj-coff.c b/contrib/binutils/gas/config/obj-coff.c
index a5a76ff..1ac8a13 100644
--- a/contrib/binutils/gas/config/obj-coff.c
+++ b/contrib/binutils/gas/config/obj-coff.c
@@ -1026,7 +1026,7 @@ weak_name2altname (const char * name)
 }
 
 /* Return the name of the weak symbol corresponding to an
-   alterate symbol.  */
+   alternate symbol.  */
 
 static const char *
 weak_altname2name (const char * name)
@@ -1579,7 +1579,7 @@ obj_coff_section (int ignore ATTRIBUTE_UNUSED)
 		  if (! load_removed)
 		    flags |= SEC_LOAD;
 		  /* Note - the READONLY flag is set here, even for the 'x'
-		     attrbiute in order to be compatible with the MSVC
+		     attribute in order to be compatible with the MSVC
 		     linker.  */
 		  if (! readonly_removed)
 		    flags |= SEC_READONLY;
diff --git a/contrib/binutils/gas/config/obj-coff.h b/contrib/binutils/gas/config/obj-coff.h
index 6fcbc9f..d2b2125 100644
--- a/contrib/binutils/gas/config/obj-coff.h
+++ b/contrib/binutils/gas/config/obj-coff.h
@@ -1,6 +1,6 @@
 /* coff object file format
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS.
@@ -27,8 +27,6 @@
 
 #include "targ-cpu.h"
 
-#include "bfd.h"
-
 /* This internal_lineno crap is to stop namespace pollution from the
    bfd internal coff headerfile.  */
 #define internal_lineno bfd_internal_lineno
@@ -57,16 +55,30 @@
 #endif
 
 #ifdef TC_I386
+#ifndef TE_PEP
+#include "coff/x86_64.h"
+#else
 #include "coff/i386.h"
+#endif
 
 #ifdef TE_PE
+#ifdef TE_PEP
+extern const char *   x86_64_target_format (void);
+#define TARGET_FORMAT x86_64_target_format ()
+#define COFF_TARGET_FORMAT "pe-x86-64"
+#else
 #define TARGET_FORMAT "pe-i386"
 #endif
+#endif
 
 #ifndef TARGET_FORMAT
+#ifdef TE_PEP
+#define TARGET_FORMAT "coff-x86-64"
+#else
 #define TARGET_FORMAT "coff-i386"
 #endif
 #endif
+#endif
 
 #ifdef TC_M68K
 #include "coff/m68k.h"
diff --git a/contrib/binutils/gas/config/obj-elf.c b/contrib/binutils/gas/config/obj-elf.c
index f922149..2f93990 100644
--- a/contrib/binutils/gas/config/obj-elf.c
+++ b/contrib/binutils/gas/config/obj-elf.c
@@ -1,6 +1,7 @@
 /* ELF object file format
    Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004, 2005, 2006, 2007
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -57,6 +58,10 @@
 #include "elf/x86-64.h"
 #endif
 
+#ifdef TC_MEP
+#include "elf/mep.h"
+#endif
+
 static void obj_elf_line (int);
 static void obj_elf_size (int);
 static void obj_elf_type (int);
@@ -632,6 +637,11 @@ obj_elf_change_section (const char *name,
 	  else if (attr == SHF_EXECINSTR
 		   && strcmp (name, ".note.GNU-stack") == 0)
 	    override = TRUE;
+#ifdef TC_ALPHA
+	  /* A section on Alpha may have SHF_ALPHA_GPREL.  */
+	  else if ((attr & ~ssect->attr) == SHF_ALPHA_GPREL)
+	    override = TRUE;
+#endif
 	  else
 	    {
 	      if (group_name == NULL)
@@ -1414,11 +1424,12 @@ obj_elf_version (int ignore ATTRIBUTE_UNUSED)
   Elf_Internal_Note i_note;
   Elf_External_Note e_note;
   asection *note_secp = NULL;
-  int len;
 
   SKIP_WHITESPACE ();
   if (*input_line_pointer == '\"')
     {
+      unsigned int len;
+
       ++input_line_pointer;	/* -> 1st char of string.  */
       name = input_line_pointer;
 
@@ -1429,19 +1440,19 @@ obj_elf_version (int ignore ATTRIBUTE_UNUSED)
       *(input_line_pointer - 1) = '\0';
       *input_line_pointer = c;
 
-      /* create the .note section */
-
+      /* Create the .note section.  */
       note_secp = subseg_new (".note", 0);
       bfd_set_section_flags (stdoutput,
 			     note_secp,
 			     SEC_HAS_CONTENTS | SEC_READONLY);
 
-      /* process the version string */
-
-      len = strlen (name);
+      /* Process the version string.  */
+      len = strlen (name) + 1;
 
-      i_note.namesz = ((len + 1) + 3) & ~3; /* round this to word boundary */
-      i_note.descsz = 0;	/* no description */
+      /* PR 3456: Although the name field is padded out to an 4-byte
+	 boundary, the namesz field should not be adjusted.  */
+      i_note.namesz = len;
+      i_note.descsz = 0;	/* No description.  */
       i_note.type = NT_VERSION;
       p = frag_more (sizeof (e_note.namesz));
       md_number_to_chars (p, i_note.namesz, sizeof (e_note.namesz));
@@ -1449,17 +1460,16 @@ obj_elf_version (int ignore ATTRIBUTE_UNUSED)
       md_number_to_chars (p, i_note.descsz, sizeof (e_note.descsz));
       p = frag_more (sizeof (e_note.type));
       md_number_to_chars (p, i_note.type, sizeof (e_note.type));
-      p = frag_more (len + 1);
-      strcpy (p, name);
+      p = frag_more (len);
+      memcpy (p, name, len);
 
       frag_align (2, 0, 0);
 
       subseg_set (seg, subseg);
     }
   else
-    {
-      as_bad (_("expected quoted string"));
-    }
+    as_bad (_("expected quoted string"));
+
   demand_empty_rest_of_line ();
 }
 
@@ -1684,6 +1694,9 @@ adjust_stab_sections (bfd *abfd, asection *sec, void *xxx ATTRIBUTE_UNUSED)
    this at the moment, so we do it ourselves.  We save the information
    in the symbol.  */
 
+#ifdef OBJ_MAYBE_ELF
+static
+#endif
 void
 elf_ecoff_set_ext (symbolS *sym, struct ecoff_extr *ext)
 {
@@ -1978,6 +1991,7 @@ elf_frob_file (void)
       bfd_set_section_size (stdoutput, s, size);
       s->contents = (unsigned char *) frag_more (size);
       frag_now->fr_fix = frag_now_fix_octets ();
+      frag_wane (frag_now);
     }
 
 #ifdef elf_tc_final_processing
diff --git a/contrib/binutils/gas/config/obj-elf.h b/contrib/binutils/gas/config/obj-elf.h
index 7ff9ef0..29356ab 100644
--- a/contrib/binutils/gas/config/obj-elf.h
+++ b/contrib/binutils/gas/config/obj-elf.h
@@ -1,6 +1,6 @@
 /* ELF object file format.
    Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-   2002, 2003, 2004 Free Software Foundation, Inc.
+   2002, 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -34,8 +34,6 @@
 #define OUTPUT_FLAVOR bfd_target_elf_flavour
 #endif
 
-#include "bfd.h"
-
 #define BYTES_IN_WORD 4		/* for now */
 #include "bfd/elf-bfd.h"
 
@@ -83,15 +81,13 @@ struct elf_obj_sy
 #define OBJ_SYMFIELD_TYPE struct elf_obj_sy
 
 /* Symbol fields used by the ELF back end.  */
-#define ELF_TARGET_SYMBOL_FIELDS int local:1;
+#define ELF_TARGET_SYMBOL_FIELDS unsigned int local:1;
 
 /* Don't change this; change ELF_TARGET_SYMBOL_FIELDS instead.  */
 #ifndef TARGET_SYMBOL_FIELDS
 #define TARGET_SYMBOL_FIELDS ELF_TARGET_SYMBOL_FIELDS
 #endif
 
-/* #include "targ-cpu.h" */
-
 #ifndef FALSE
 #define FALSE 0
 #define TRUE  !FALSE
@@ -134,13 +130,6 @@ int elf_s_get_other (symbolS *);
 
 extern asection *gdb_section;
 
-#ifndef obj_sec_set_private_data
-#define obj_sec_set_private_data(B, S) \
-  if (! BFD_SEND ((B), _new_section_hook, ((B), (S)))) \
-    as_fatal (_("can't allocate ELF private section data: %s"),	\
-	      bfd_errmsg (bfd_get_error ()))
-#endif
-
 #ifndef obj_frob_file
 #define obj_frob_file  elf_frob_file
 #endif
@@ -247,6 +236,7 @@ extern void elf_pop_insert (void);
 #endif
 
 #ifndef OBJ_MAYBE_ELF
+/* If OBJ_MAYBE_ELF then obj-multi.h will define obj_ecoff_set_ext.  */
 #define obj_ecoff_set_ext elf_ecoff_set_ext
 struct ecoff_extr;
 extern void elf_ecoff_set_ext (symbolS *, struct ecoff_extr *);
diff --git a/contrib/binutils/gas/config/obj-ieee.c b/contrib/binutils/gas/config/obj-ieee.c
deleted file mode 100644
index bac4675..0000000
--- a/contrib/binutils/gas/config/obj-ieee.c
+++ /dev/null
@@ -1,613 +0,0 @@
-/* obj-format for ieee-695 records.
-   Copyright 1991, 1992, 1993, 1994, 1997, 2000, 2001, 2002, 2003, 2005
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-   02110-1301, USA.  */
-
-/* Created by Steve Chamberlain <steve@cygnus.com>.  */
-
-/* This will hopefully become the port through which bfd and gas talk,
-   for the moment, only ieee is known to work well.  */
-
-#include "bfd.h"
-#include "as.h"
-#include "subsegs.h"
-#include "output-file.h"
-#include "frags.h"
-
-bfd *abfd;
-
-/* How many addresses does the .align take?  */
-
-static relax_addressT
-relax_align (address, alignment)
-     /* Address now.  */
-     register relax_addressT address;
-
-     /* Alignment (binary).  */
-     register long alignment;
-{
-  relax_addressT mask;
-  relax_addressT new_address;
-
-  mask = ~((~0) << alignment);
-  new_address = (address + mask) & (~mask);
-  return (new_address - address);
-}
-
-/* Calculate the size of the frag chain
-   and create a bfd section to contain all of it.  */
-
-static void
-size_section (abfd, idx)
-     bfd *abfd;
-     unsigned int idx;
-{
-  asection *sec;
-  unsigned int size = 0;
-  fragS *frag = segment_info[idx].frag_root;
-
-  while (frag)
-    {
-      if (frag->fr_address != size)
-	{
-	  printf (_("Out of step\n"));
-	  size = frag->fr_address;
-	}
-      size += frag->fr_fix;
-      switch (frag->fr_type)
-	{
-	case rs_fill:
-	case rs_org:
-	  size += frag->fr_offset * frag->fr_var;
-	  break;
-	case rs_align:
-	case rs_align_code:
-	  {
-	    addressT off;
-
-	    off = relax_align (size, frag->fr_offset);
-	    if (frag->fr_subtype != 0 && off > frag->fr_subtype)
-	      off = 0;
-	    size += off;
-	  }
-	}
-      frag = frag->fr_next;
-    }
-  if (size)
-    {
-      char *name = segment_info[idx].name;
-
-      if (name == (char *) NULL)
-	name = ".data";
-
-      segment_info[idx].user_stuff =
-	(char *) (sec = bfd_make_section (abfd, name));
-      /* Make it output through itself.  */
-      sec->output_section = sec;
-      sec->flags |= SEC_HAS_CONTENTS;
-      bfd_set_section_size (abfd, sec, size);
-    }
-}
-
-/* Run through a frag chain and write out the data to go with it.  */
-
-static void
-fill_section (abfd, idx)
-     bfd *abfd;
-     unsigned int idx;
-{
-  asection *sec = segment_info[idx].user_stuff;
-
-  if (sec)
-    {
-      fragS *frag = segment_info[idx].frag_root;
-      unsigned int offset = 0;
-      while (frag)
-	{
-	  unsigned int fill_size;
-	  unsigned int count;
-	  switch (frag->fr_type)
-	    {
-	    case rs_fill:
-	    case rs_align:
-	    case rs_org:
-	      if (frag->fr_fix)
-		{
-		  bfd_set_section_contents (abfd,
-					    sec,
-					    frag->fr_literal,
-					    frag->fr_address,
-					    frag->fr_fix);
-		}
-	      offset += frag->fr_fix;
-	      fill_size = frag->fr_var;
-	      if (fill_size)
-		{
-		  unsigned int off = frag->fr_fix;
-		  for (count = frag->fr_offset; count; count--)
-		    {
-		      bfd_set_section_contents (abfd, sec,
-						frag->fr_literal +
-						frag->fr_fix,
-						frag->fr_address + off,
-						fill_size);
-		      off += fill_size;
-		    }
-		}
-	      break;
-	    default:
-	      abort ();
-	    }
-	  frag = frag->fr_next;
-	}
-    }
-}
-
-/* Count the relocations in a chain.  */
-
-static unsigned int
-count_entries_in_chain (idx)
-     unsigned int idx;
-{
-  unsigned int nrelocs;
-  fixS *fixup_ptr;
-
-  /* Count the relocations.  */
-  fixup_ptr = segment_info[idx].fix_root;
-  nrelocs = 0;
-  while (fixup_ptr != (fixS *) NULL)
-    {
-      fixup_ptr = fixup_ptr->fx_next;
-      nrelocs++;
-    }
-  return nrelocs;
-}
-
-/* Output all the relocations for a section.  */
-
-void
-do_relocs_for (idx)
-     unsigned int idx;
-{
-  unsigned int nrelocs;
-  arelent **reloc_ptr_vector;
-  arelent *reloc_vector;
-  asymbol **ptrs;
-  asection *section = (asection *) (segment_info[idx].user_stuff);
-  unsigned int i;
-  fixS *from;
-
-  if (section)
-    {
-      nrelocs = count_entries_in_chain (idx);
-
-      reloc_ptr_vector =
-	(arelent **) malloc ((nrelocs + 1) * sizeof (arelent *));
-      reloc_vector = (arelent *) malloc (nrelocs * sizeof (arelent));
-      ptrs = (asymbol **) malloc (nrelocs * sizeof (asymbol *));
-      from = segment_info[idx].fix_root;
-      for (i = 0; i < nrelocs; i++)
-	{
-	  arelent *to = reloc_vector + i;
-	  asymbol *s;
-	  reloc_ptr_vector[i] = to;
-	  to->howto = (reloc_howto_type *) (from->fx_r_type);
-
-	  s = &(from->fx_addsy->sy_symbol.sy);
-	  to->address = ((char *) (from->fx_frag->fr_address +
-				   from->fx_where))
-	    - ((char *) (&(from->fx_frag->fr_literal)));
-	  to->addend = from->fx_offset;
-	  /* If we know the symbol which we want to relocate to, turn
-	     this reloaction into a section relative.
-
-	     If this relocation is pcrelative, and we know the
-	     destination, we still want to keep the relocation - since
-	     the linker might relax some of the bytes, but it stops
-	     being pc relative and turns into an absolute relocation.  */
-	  if (s)
-	    {
-	      if ((s->flags & BSF_UNDEFINED) == 0)
-		{
-		  to->section = s->section;
-
-		  /* We can refer directly to the value field here,
-		     rather than using S_GET_VALUE, because this is
-		     only called after do_symbols, which sets up the
-		     value field.  */
-		  to->addend += s->value;
-
-		  to->sym_ptr_ptr = 0;
-		  if (to->howto->pcrel_offset)
-		    /* This is a pcrel relocation, the addend should
-		       be adjusted.  */
-		    to->addend -= to->address + 1;
-		}
-	      else
-		{
-		  to->section = 0;
-		  *ptrs = &(from->fx_addsy->sy_symbol.sy);
-		  to->sym_ptr_ptr = ptrs;
-
-		  if (to->howto->pcrel_offset)
-		    /* This is a pcrel relocation, the addend should
-		       be adjusted.  */
-		    to->addend -= to->address - 1;
-		}
-	    }
-	  else
-	    to->section = 0;
-
-	  ptrs++;
-	  from = from->fx_next;
-	}
-
-      /* Attach to the section.  */
-      section->orelocation = reloc_ptr_vector;
-      section->reloc_count = nrelocs;
-      section->flags |= SEC_LOAD;
-    }
-}
-
-/* Do the symbols.  */
-
-static void
-do_symbols (abfd)
-     bfd *abfd;
-{
-  extern symbolS *symbol_rootP;
-  symbolS *ptr;
-  asymbol **symbol_ptr_vec;
-  asymbol *symbol_vec;
-  unsigned int count = 0;
-  unsigned int index;
-
-  for (ptr = symbol_rootP;
-       ptr != (symbolS *) NULL;
-       ptr = ptr->sy_next)
-    {
-      if (SEG_NORMAL (ptr->sy_symbol.seg))
-	{
-	  ptr->sy_symbol.sy.section =
-	    (asection *) (segment_info[ptr->sy_symbol.seg].user_stuff);
-	  S_SET_VALUE (ptr, S_GET_VALUE (ptr));
-	  if (ptr->sy_symbol.sy.flags == 0)
-	    ptr->sy_symbol.sy.flags = BSF_LOCAL;
-	}
-      else
-	{
-	  switch (ptr->sy_symbol.seg)
-	    {
-	    case SEG_ABSOLUTE:
-	      ptr->sy_symbol.sy.flags |= BSF_ABSOLUTE;
-	      ptr->sy_symbol.sy.section = 0;
-	      break;
-	    case SEG_UNKNOWN:
-	      ptr->sy_symbol.sy.flags = BSF_UNDEFINED;
-	      ptr->sy_symbol.sy.section = 0;
-	      break;
-	    default:
-	      abort ();
-	    }
-	}
-      ptr->sy_symbol.sy.value = S_GET_VALUE (ptr);
-      count++;
-    }
-  symbol_ptr_vec = (asymbol **) malloc ((count + 1) * sizeof (asymbol *));
-
-  index = 0;
-  for (ptr = symbol_rootP;
-       ptr != (symbolS *) NULL;
-       ptr = ptr->sy_next)
-    {
-      symbol_ptr_vec[index] = &(ptr->sy_symbol.sy);
-      index++;
-    }
-  symbol_ptr_vec[index] = 0;
-  abfd->outsymbols = symbol_ptr_vec;
-  abfd->symcount = count;
-}
-
-/* The generic as->bfd converter. Other backends may have special case
-   code.  */
-
-void
-bfd_as_write_hook ()
-{
-  int i;
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    size_section (abfd, i);
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    fill_section (abfd, i);
-
-  do_symbols (abfd);
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    do_relocs_for (i);
-}
-
-S_SET_SEGMENT (x, y)
-     symbolS *x;
-     int y;
-{
-  x->sy_symbol.seg = y;
-}
-
-S_IS_DEFINED (x)
-     symbolS *x;
-{
-  if (SEG_NORMAL (x->sy_symbol.seg))
-    {
-      return 1;
-    }
-  switch (x->sy_symbol.seg)
-    {
-    case SEG_UNKNOWN:
-      return 0;
-    default:
-      abort ();
-    }
-}
-
-S_IS_EXTERNAL (x)
-{
-  abort ();
-}
-
-S_GET_DESC (x)
-{
-  abort ();
-}
-
-S_GET_SEGMENT (x)
-     symbolS *x;
-{
-  return x->sy_symbol.seg;
-}
-
-S_SET_EXTERNAL (x)
-     symbolS *x;
-{
-  x->sy_symbol.sy.flags |= BSF_GLOBAL | BSF_EXPORT;
-}
-
-S_SET_NAME (x, y)
-     symbolS *x;
-     char *y;
-{
-  x->sy_symbol.sy.name = y;
-}
-
-S_GET_OTHER (x)
-{
-  abort ();
-}
-
-S_IS_DEBUG (x)
-{
-  abort ();
-}
-
-#ifndef segment_name
-char *
-segment_name ()
-{
-  abort ();
-}
-#endif
-
-void
-obj_read_begin_hook ()
-{
-}
-
-static void
-obj_ieee_section (ignore)
-     int ignore;
-{
-  extern char *input_line_pointer;
-  extern char is_end_of_line[];
-  char *p = input_line_pointer;
-  char *s = p;
-  int i;
-
-  /* Look up the name, if it doesn't exist, make it.  */
-  while (*p && *p != ' ' && *p != ',' && !is_end_of_line[*p])
-    {
-      p++;
-    }
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      if (segment_info[i].hadone)
-	{
-	  if (strncmp (segment_info[i].name, s, p - s) == 0)
-	    goto ok;
-	}
-      else
-	break;
-    }
-  if (i == SEG_UNKNOWN)
-    {
-      as_bad (_("too many sections"));
-      return;
-    }
-
-  segment_info[i].hadone = 1;
-  segment_info[i].name = malloc (p - s + 1);
-  memcpy (segment_info[i].name, s, p - s);
-  segment_info[i].name[p - s] = 0;
-ok:
-  subseg_set (i, 0);
-  while (!is_end_of_line[*p])
-    p++;
-  input_line_pointer = p;
-}
-
-const pseudo_typeS obj_pseudo_table[] =
-{
-  {"section", obj_ieee_section, 0},
-  {"data.b" , cons            , 1},
-  {"data.w" , cons            , 2},
-  {"data.l" , cons            , 4},
-  {"export" , s_globl         , 0},
-  {"option" , s_ignore        , 0},
-  {"end"    , s_ignore        , 0},
-  {"import" , s_ignore        , 0},
-  {"sdata"  , stringer        , 0},
-  0,
-};
-
-void
-obj_symbol_new_hook (symbolP)
-     symbolS *symbolP;
-{
-  symbolP->sy_symbol.sy.the_bfd = abfd;
-}
-
-#if 1
-
-#ifndef SUB_SEGMENT_ALIGN
-#ifdef HANDLE_ALIGN
-/* The last subsegment gets an alignment corresponding to the alignment
-   of the section.  This allows proper nop-filling at the end of
-   code-bearing sections.  */
-#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN)					\
-  (!(FRCHAIN)->frch_next || (FRCHAIN)->frch_next->frch_seg != (SEG)	\
-   ? get_recorded_alignment (SEG) : 0)
-#else
-#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 2
-#endif
-#endif
-
-extern void
-write_object_file ()
-{
-  int i;
-  struct frchain *frchain_ptr;
-  struct frag *frag_ptr;
-
-  abfd = bfd_openw (out_file_name, "ieee");
-
-  if (abfd == 0)
-    {
-      as_perror (_("FATAL: Can't create %s"), out_file_name);
-      exit (EXIT_FAILURE);
-    }
-  bfd_set_format (abfd, bfd_object);
-  bfd_set_arch_mach (abfd, bfd_arch_h8300, 0);
-  subseg_set (1, 0);
-  subseg_set (2, 0);
-  subseg_set (3, 0);
-
-  /* Run through all the sub-segments and align them up.  Also
-     close any open frags.  We tack a .fill onto the end of the
-     frag chain so that any .align's size can be worked by looking
-     at the next frag.  */
-  for (frchain_ptr = frchain_root;
-       frchain_ptr != (struct frchain *) NULL;
-       frchain_ptr = frchain_ptr->frch_next)
-    {
-      int alignment;
-
-      subseg_set (frchain_ptr->frch_seg, frchain_ptr->frch_subseg);
-
-      alignment = SUB_SEGMENT_ALIGN (now_seg, frchain_ptr)
-
-#ifdef md_do_align
-      md_do_align (alignment, (char *) NULL, 0, 0, alignment_done);
-#endif
-      if (subseg_text_p (now_seg))
-	frag_align_code (alignment, 0);
-      else
-	frag_align (alignment, 0, 0);
-
-#ifdef md_do_align
-    alignment_done:
-#endif
-
-      frag_wane (frag_now);
-      frag_now->fr_fix = 0;
-      know (frag_now->fr_next == NULL);
-    }
-
-  /* Now build one big frag chain for each segment, linked through
-     fr_next.  */
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      fragS **prev_frag_ptr_ptr;
-      struct frchain *next_frchain_ptr;
-
-      segment_info[i].frag_root = segment_info[i].frchainP->frch_root;
-    }
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    relax_segment (segment_info[i].frag_root, i);
-
-  /* Relaxation has completed.  Freeze all syms.  */
-  finalize_syms = 1;
-
-  /* Now the addresses of the frags are correct within the segment.  */
-
-  bfd_as_write_hook ();
-  bfd_close (abfd);
-}
-
-#endif
-
-H_SET_TEXT_SIZE (a, b)
-{
-  abort ();
-}
-
-H_GET_TEXT_SIZE ()
-{
-  abort ();
-}
-
-H_SET_BSS_SIZE ()
-{
-  abort ();
-}
-
-H_SET_STRING_SIZE ()
-{
-  abort ();
-}
-
-H_SET_RELOCATION_SIZE ()
-{
-  abort ();
-}
-
-H_SET_MAGIC_NUMBER ()
-{
-  abort ();
-}
-
-H_GET_FILE_SIZE ()
-{
-  abort ();
-}
-
-H_GET_TEXT_RELOCATION_SIZE ()
-{
-  abort ();
-}
diff --git a/contrib/binutils/gas/config/obj-ieee.h b/contrib/binutils/gas/config/obj-ieee.h
deleted file mode 100644
index 2965429..0000000
--- a/contrib/binutils/gas/config/obj-ieee.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* This file is obj-ieee.h
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2000, 2002, 2003
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-   02110-1301, USA.  */
-
-#include "bfd.h"
-
-typedef struct
-{
-  asymbol sy;
-  int seg;
-}
-obj_symbol_type;
-
-#define S_GET_NAME(s) (((s)->sy_symbol.sy.name))
-
-/* Return true for symbols that should not be reduced to section
-   symbols or eliminated from expressions, because they may be
-   overridden by the linker.  */
-#define S_FORCE_RELOC(s, strict) (!SEG_NORMAL (x->sy_symbol.seg))
-
-typedef struct
-  {
-    int x;
-  }
-object_headers;
-
-int lineno_rootP;
-
-#define IEEE_STYLE
diff --git a/contrib/binutils/gas/config/tc-alpha.c b/contrib/binutils/gas/config/tc-alpha.c
index 3765b08..e8f0bad 100644
--- a/contrib/binutils/gas/config/tc-alpha.c
+++ b/contrib/binutils/gas/config/tc-alpha.c
@@ -1,6 +1,6 @@
 /* tc-alpha.c - Processor-specific code for the DEC Alpha AXP CPU.
    Copyright 1989, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
    Contributed by Carnegie Mellon University, 1993.
    Written by Alessandro Forin, based on earlier gas-1.38 target CPU files.
    Modified by Ken Raeburn for gas-2.x and ECOFF support.
@@ -2383,15 +2383,15 @@ emit_ustX (const expressionS *tok,
   newtok[2] = newtok[0];
   assemble_tokens ("or", newtok, 3, 1);
 
-  /* Emit "stq_u $t9, 0($at)".  */
-  set_tok_reg (newtok[0], AXP_REG_T9);
-  set_tok_const (newtok[1], 0);
-  set_tok_preg (newtok[2], AXP_REG_AT);
-  assemble_tokens ("stq_u", newtok, 3, 1);
-
   /* Emit "stq_u $t10, size-1($at)".  */
   set_tok_reg (newtok[0], AXP_REG_T10);
   set_tok_const (newtok[1], (1 << lgsize) - 1);
+  set_tok_preg (newtok[2], AXP_REG_AT);
+  assemble_tokens ("stq_u", newtok, 3, 1);
+
+  /* Emit "stq_u $t9, 0($at)".  */
+  set_tok_reg (newtok[0], AXP_REG_T9);
+  set_tok_const (newtok[1], 0);
   assemble_tokens ("stq_u", newtok, 3, 1);
 }
 
diff --git a/contrib/binutils/gas/config/tc-alpha.h b/contrib/binutils/gas/config/tc-alpha.h
index 42e004e..d28ab9f 100644
--- a/contrib/binutils/gas/config/tc-alpha.h
+++ b/contrib/binutils/gas/config/tc-alpha.h
@@ -1,6 +1,6 @@
 /* This file is tc-alpha.h
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   2005
+   2005, 2006
    Free Software Foundation, Inc.
    Written by Ken Raeburn <raeburn@cygnus.com>.
 
@@ -180,4 +180,4 @@ extern void alpha_cfi_frame_initial_instructions (void);
 
 #define DWARF2_LINE_MIN_INSN_LENGTH	4
 #define DWARF2_DEFAULT_RETURN_COLUMN	26
-#define DWARF2_CIE_DATA_ALIGNMENT	-8
+#define DWARF2_CIE_DATA_ALIGNMENT	(-8)
diff --git a/contrib/binutils/gas/config/tc-arc.c b/contrib/binutils/gas/config/tc-arc.c
index 525b540..490f327 100644
--- a/contrib/binutils/gas/config/tc-arc.c
+++ b/contrib/binutils/gas/config/tc-arc.c
@@ -20,8 +20,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <stdio.h>
-#include "libiberty.h"
 #include "as.h"
 #include "struc-symbol.h"
 #include "safe-ctype.h"
diff --git a/contrib/binutils/gas/config/tc-arm.c b/contrib/binutils/gas/config/tc-arm.c
index ae420b3..683e6ee 100644
--- a/contrib/binutils/gas/config/tc-arm.c
+++ b/contrib/binutils/gas/config/tc-arm.c
@@ -1,6 +1,6 @@
 /* tc-arm.c -- Assemble for the ARM
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005
+   2004, 2005, 2006
    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
 	Modified by David Taylor (dtaylor@armltd.co.uk)
@@ -25,28 +25,24 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <string.h>
+#include <limits.h>
+#include <stdarg.h>
 #define	 NO_RELOC 0
 #include "as.h"
 #include "safe-ctype.h"
-
-/* Need TARGET_CPU.  */
-#include "config.h"
 #include "subsegs.h"
 #include "obstack.h"
-#include "symbols.h"
-#include "listing.h"
 
 #include "opcode/arm.h"
 
 #ifdef OBJ_ELF
 #include "elf/arm.h"
-#include "dwarf2dbg.h"
 #include "dw2gencfi.h"
 #endif
 
-/* XXX Set this to 1 after the next binutils release.  */
-#define WARN_DEPRECATED 0
+#include "dwarf2dbg.h"
+
+#define WARN_DEPRECATED 1
 
 #ifdef OBJ_ELF
 /* Must be at least the size of the largest unwind opcode (currently two).  */
@@ -90,6 +86,15 @@ static unsigned int marked_pr_dependency = 0;
 
 #endif /* OBJ_ELF */
 
+/* Results from operand parsing worker functions.  */
+
+typedef enum
+{
+  PARSE_OPERAND_SUCCESS,
+  PARSE_OPERAND_FAIL,
+  PARSE_OPERAND_FAIL_NO_BACKTRACK
+} parse_operand_result;
+
 enum arm_float_abi
 {
   ARM_FLOAT_ABI_HARD,
@@ -150,11 +155,14 @@ static const arm_feature_set *mcpu_fpu_opt = NULL;
 static const arm_feature_set *march_cpu_opt = NULL;
 static const arm_feature_set *march_fpu_opt = NULL;
 static const arm_feature_set *mfpu_opt = NULL;
+static const arm_feature_set *object_arch = NULL;
 
 /* Constants for known architecture features.  */
 static const arm_feature_set fpu_default = FPU_DEFAULT;
 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
+static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
+static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
@@ -194,6 +202,8 @@ static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
 
+static const arm_feature_set arm_cext_iwmmxt2 =
+  ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
 static const arm_feature_set arm_cext_iwmmxt =
   ARM_FEATURE (0, ARM_CEXT_IWMMXT);
 static const arm_feature_set arm_cext_xscale =
@@ -206,6 +216,10 @@ static const arm_feature_set fpu_vfp_ext_v1xd =
   ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
+static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
+static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
+static const arm_feature_set fpu_vfp_v3_or_neon_ext =
+  ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
 
 static int mfloat_abi_opt = -1;
 /* Record user cpu selection for object attributes.  */
@@ -218,6 +232,12 @@ static int meabi_flags = EABI_DEFAULT;
 # else
 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
 # endif
+
+bfd_boolean
+arm_is_eabi(void)
+{
+  return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
+}
 #endif
 
 #ifdef OBJ_ELF
@@ -256,6 +276,31 @@ static int thumb_mode = 0;
 
 static bfd_boolean unified_syntax = FALSE;
 
+enum neon_el_type
+{
+  NT_invtype,
+  NT_untyped,
+  NT_integer,
+  NT_float,
+  NT_poly,
+  NT_signed,
+  NT_unsigned
+};
+
+struct neon_type_el
+{
+  enum neon_el_type type;
+  unsigned size;
+};
+
+#define NEON_MAX_TYPE_ELS 4
+
+struct neon_type
+{
+  struct neon_type_el el[NEON_MAX_TYPE_ELS];
+  unsigned elems;
+};
+
 struct arm_it
 {
   const char *	error;
@@ -263,6 +308,11 @@ struct arm_it
   int		size;
   int		size_req;
   int		cond;
+  /* "uncond_value" is set to the value in place of the conditional field in
+     unconditional versions of the instruction, or -1 if nothing is
+     appropriate.  */
+  int		uncond_value;
+  struct neon_type vectype;
   /* Set to the opcode if the instruction needs relaxation.
      Zero if the instruction is not relaxed.  */
   unsigned long	relax;
@@ -277,9 +327,19 @@ struct arm_it
   {
     unsigned reg;
     signed int imm;
+    struct neon_type_el vectype;
     unsigned present	: 1;  /* Operand present.  */
     unsigned isreg	: 1;  /* Operand was a register.  */
     unsigned immisreg	: 1;  /* .imm field is a second register.  */
+    unsigned isscalar   : 1;  /* Operand is a (Neon) scalar.  */
+    unsigned immisalign : 1;  /* Immediate is an alignment specifier.  */
+    unsigned immisfloat : 1;  /* Immediate was parsed as a float.  */
+    /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
+       instructions. This allows us to disambiguate ARM <-> vector insns.  */
+    unsigned regisimm   : 1;  /* 64-bit immediate, reg forms high 32 bits.  */
+    unsigned isvec      : 1;  /* Is a single, double or quad VFP/Neon reg.  */
+    unsigned isquad     : 1;  /* Operand is Neon quad-precision register.  */
+    unsigned issingle   : 1;  /* Operand is VFP single-precision register.  */
     unsigned hasreloc	: 1;  /* Operand has relocation suffix.  */
     unsigned writeback	: 1;  /* Operand has trailing !  */
     unsigned preind	: 1;  /* Preindexed address.  */
@@ -355,9 +415,10 @@ struct reloc_entry
   bfd_reloc_code_real_type reloc;
 };
 
-enum vfp_sp_reg_pos
+enum vfp_reg_pos
 {
-  VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
+  VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
+  VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
 };
 
 enum vfp_ldstm_type
@@ -365,6 +426,17 @@ enum vfp_ldstm_type
   VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
 };
 
+/* Bits for DEFINED field in neon_typed_alias.  */
+#define NTA_HASTYPE  1
+#define NTA_HASINDEX 2
+
+struct neon_typed_alias
+{
+  unsigned char defined;
+  unsigned char index;
+  struct neon_type_el eltype;
+};
+
 /* ARM register categories.  This includes coprocessor numbers and various
    architecture extensions' registers.	*/
 enum arm_reg_type
@@ -375,6 +447,10 @@ enum arm_reg_type
   REG_TYPE_FN,
   REG_TYPE_VFS,
   REG_TYPE_VFD,
+  REG_TYPE_NQ,
+  REG_TYPE_VFSD,
+  REG_TYPE_NDQ,
+  REG_TYPE_NSDQ,
   REG_TYPE_VFC,
   REG_TYPE_MVF,
   REG_TYPE_MVD,
@@ -388,13 +464,17 @@ enum arm_reg_type
   REG_TYPE_XSCALE,
 };
 
-/* Structure for a hash table entry for a register.  */
+/* Structure for a hash table entry for a register.
+   If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
+   information which states whether a vector type or index is specified (for a
+   register alias created with .dn or .qn). Otherwise NEON should be NULL.  */
 struct reg_entry
 {
-  const char   *name;
-  unsigned char number;
-  unsigned char type;
-  unsigned char builtin;
+  const char        *name;
+  unsigned char      number;
+  unsigned char      type;
+  unsigned char      builtin;
+  struct neon_typed_alias *neon;
 };
 
 /* Diagnostics used when we don't get a register of the expected type.	*/
@@ -405,7 +485,11 @@ const char *const reg_expected_msgs[] =
   N_("co-processor register expected"),
   N_("FPA register expected"),
   N_("VFP single precision register expected"),
-  N_("VFP double precision register expected"),
+  N_("VFP/Neon double precision register expected"),
+  N_("Neon quad precision register expected"),
+  N_("VFP single or double precision register expected"),
+  N_("Neon double or quad precision register expected"),
+  N_("VFP single, double or Neon quad precision register expected"),
   N_("VFP system register expected"),
   N_("Maverick MVF register expected"),
   N_("Maverick MVD register expected"),
@@ -465,11 +549,14 @@ struct asm_opcode
 #define INDEX_UP	0x00800000
 #define WRITE_BACK	0x00200000
 #define LDM_TYPE_2_OR_3	0x00400000
+#define CPSI_MMOD	0x00020000
 
 #define LITERAL_MASK	0xf000f000
 #define OPCODE_MASK	0xfe1fffff
 #define V4_STR_BIT	0x00000020
 
+#define T2_SUBS_PC_LR	0xf3de8f00
+
 #define DATA_OP_SHIFT	21
 
 #define T2_OPCODE_MASK	0xfe1fffff
@@ -571,6 +658,7 @@ struct asm_opcode
 #define BAD_ADDR_MODE   _("instruction does not accept this addressing mode");
 #define BAD_BRANCH	_("branch must be last instruction in IT block")
 #define BAD_NOT_IT	_("instruction not allowed in IT block")
+#define BAD_FPU		_("selected FPU does not support instruction")
 
 static struct hash_control *arm_ops_hsh;
 static struct hash_control *arm_cond_hsh;
@@ -691,6 +779,9 @@ static int in_my_get_expression = 0;
 #define GE_NO_PREFIX 0
 #define GE_IMM_PREFIX 1
 #define GE_OPT_PREFIX 2
+/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
+   immediates, as can be used in Neon VMVN and VMOV immediate instructions.  */
+#define GE_OPT_PREFIX_BIG 3
 
 static int
 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
@@ -700,7 +791,8 @@ my_get_expression (expressionS * ep, char ** str, int prefix_mode)
 
   /* In unified syntax, all prefixes are optional.  */
   if (unified_syntax)
-    prefix_mode = GE_OPT_PREFIX;
+    prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
+                  : GE_OPT_PREFIX;
 
   switch (prefix_mode)
     {
@@ -714,6 +806,7 @@ my_get_expression (expressionS * ep, char ** str, int prefix_mode)
       (*str)++;
       break;
     case GE_OPT_PREFIX:
+    case GE_OPT_PREFIX_BIG:
       if (is_immediate_prefix (**str))
 	(*str)++;
       break;
@@ -755,11 +848,12 @@ my_get_expression (expressionS * ep, char ** str, int prefix_mode)
   /* Get rid of any bignums now, so that we don't generate an error for which
      we can't establish a line number later on.	 Big numbers are never valid
      in instructions, which is where this routine is always called.  */
-  if (ep->X_op == O_big
-      || (ep->X_add_symbol
-	  && (walk_no_bignums (ep->X_add_symbol)
-	      || (ep->X_op_symbol
-		  && walk_no_bignums (ep->X_op_symbol)))))
+  if (prefix_mode != GE_OPT_PREFIX_BIG
+      && (ep->X_op == O_big
+          || (ep->X_add_symbol
+	      && (walk_no_bignums (ep->X_add_symbol)
+	          || (ep->X_op_symbol
+		      && walk_no_bignums (ep->X_op_symbol))))))
     {
       inst.error = _("invalid constant");
       *str = input_line_pointer;
@@ -939,18 +1033,10 @@ arm_reg_parse_multi (char **ccp)
   return reg;
 }
 
-/* As above, but the register must be of type TYPE, and the return
-   value is the register number or FAIL.  */
-
 static int
-arm_reg_parse (char **ccp, enum arm_reg_type type)
+arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
+                    enum arm_reg_type type)
 {
-  char *start = *ccp;
-  struct reg_entry *reg = arm_reg_parse_multi (ccp);
-
-  if (reg && reg->type == type)
-    return reg->number;
-
   /* Alternative syntaxes are accepted for a few register classes.  */
   switch (type)
     {
@@ -982,10 +1068,354 @@ arm_reg_parse (char **ccp, enum arm_reg_type type)
       break;
     }
 
+  return FAIL;
+}
+
+/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
+   return value is the register number or FAIL.  */
+
+static int
+arm_reg_parse (char **ccp, enum arm_reg_type type)
+{
+  char *start = *ccp;
+  struct reg_entry *reg = arm_reg_parse_multi (ccp);
+  int ret;
+
+  /* Do not allow a scalar (reg+index) to parse as a register.  */
+  if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
+    return FAIL;
+
+  if (reg && reg->type == type)
+    return reg->number;
+
+  if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
+    return ret;
+
   *ccp = start;
   return FAIL;
 }
 
+/* Parse a Neon type specifier. *STR should point at the leading '.'
+   character. Does no verification at this stage that the type fits the opcode
+   properly. E.g.,
+
+     .i32.i32.s16
+     .s32.f32
+     .u16
+
+   Can all be legally parsed by this function.
+
+   Fills in neon_type struct pointer with parsed information, and updates STR
+   to point after the parsed type specifier. Returns SUCCESS if this was a legal
+   type, FAIL if not.  */
+
+static int
+parse_neon_type (struct neon_type *type, char **str)
+{
+  char *ptr = *str;
+
+  if (type)
+    type->elems = 0;
+
+  while (type->elems < NEON_MAX_TYPE_ELS)
+    {
+      enum neon_el_type thistype = NT_untyped;
+      unsigned thissize = -1u;
+
+      if (*ptr != '.')
+	break;
+
+      ptr++;
+
+      /* Just a size without an explicit type.  */
+      if (ISDIGIT (*ptr))
+	goto parsesize;
+
+      switch (TOLOWER (*ptr))
+	{
+	case 'i': thistype = NT_integer; break;
+	case 'f': thistype = NT_float; break;
+	case 'p': thistype = NT_poly; break;
+	case 's': thistype = NT_signed; break;
+	case 'u': thistype = NT_unsigned; break;
+        case 'd':
+          thistype = NT_float;
+          thissize = 64;
+          ptr++;
+          goto done;
+	default:
+	  as_bad (_("unexpected character `%c' in type specifier"), *ptr);
+	  return FAIL;
+	}
+
+      ptr++;
+
+      /* .f is an abbreviation for .f32.  */
+      if (thistype == NT_float && !ISDIGIT (*ptr))
+	thissize = 32;
+      else
+	{
+	parsesize:
+	  thissize = strtoul (ptr, &ptr, 10);
+
+	  if (thissize != 8 && thissize != 16 && thissize != 32
+              && thissize != 64)
+            {
+              as_bad (_("bad size %d in type specifier"), thissize);
+	      return FAIL;
+	    }
+	}
+
+      done:
+      if (type)
+        {
+          type->el[type->elems].type = thistype;
+	  type->el[type->elems].size = thissize;
+	  type->elems++;
+	}
+    }
+
+  /* Empty/missing type is not a successful parse.  */
+  if (type->elems == 0)
+    return FAIL;
+
+  *str = ptr;
+
+  return SUCCESS;
+}
+
+/* Errors may be set multiple times during parsing or bit encoding
+   (particularly in the Neon bits), but usually the earliest error which is set
+   will be the most meaningful. Avoid overwriting it with later (cascading)
+   errors by calling this function.  */
+
+static void
+first_error (const char *err)
+{
+  if (!inst.error)
+    inst.error = err;
+}
+
+/* Parse a single type, e.g. ".s32", leading period included.  */
+static int
+parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
+{
+  char *str = *ccp;
+  struct neon_type optype;
+
+  if (*str == '.')
+    {
+      if (parse_neon_type (&optype, &str) == SUCCESS)
+        {
+          if (optype.elems == 1)
+            *vectype = optype.el[0];
+          else
+            {
+              first_error (_("only one type should be specified for operand"));
+              return FAIL;
+            }
+        }
+      else
+        {
+          first_error (_("vector type expected"));
+          return FAIL;
+        }
+    }
+  else
+    return FAIL;
+  
+  *ccp = str;
+  
+  return SUCCESS;
+}
+
+/* Special meanings for indices (which have a range of 0-7), which will fit into
+   a 4-bit integer.  */
+
+#define NEON_ALL_LANES		15
+#define NEON_INTERLEAVE_LANES	14
+
+/* Parse either a register or a scalar, with an optional type. Return the
+   register number, and optionally fill in the actual type of the register
+   when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
+   type/index information in *TYPEINFO.  */
+
+static int
+parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
+                           enum arm_reg_type *rtype,
+                           struct neon_typed_alias *typeinfo)
+{
+  char *str = *ccp;
+  struct reg_entry *reg = arm_reg_parse_multi (&str);
+  struct neon_typed_alias atype;
+  struct neon_type_el parsetype;
+
+  atype.defined = 0;
+  atype.index = -1;
+  atype.eltype.type = NT_invtype;
+  atype.eltype.size = -1;
+
+  /* Try alternate syntax for some types of register. Note these are mutually
+     exclusive with the Neon syntax extensions.  */
+  if (reg == NULL)
+    {
+      int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
+      if (altreg != FAIL)
+        *ccp = str;
+      if (typeinfo)
+        *typeinfo = atype;
+      return altreg;
+    }
+
+  /* Undo polymorphism when a set of register types may be accepted.  */
+  if ((type == REG_TYPE_NDQ
+       && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
+      || (type == REG_TYPE_VFSD
+          && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
+      || (type == REG_TYPE_NSDQ
+          && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
+              || reg->type == REG_TYPE_NQ))
+      || (type == REG_TYPE_MMXWC
+	  && (reg->type == REG_TYPE_MMXWCG)))
+    type = reg->type;
+
+  if (type != reg->type)
+    return FAIL;
+
+  if (reg->neon)
+    atype = *reg->neon;
+  
+  if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
+    {
+      if ((atype.defined & NTA_HASTYPE) != 0)
+        {
+          first_error (_("can't redefine type for operand"));
+          return FAIL;
+        }
+      atype.defined |= NTA_HASTYPE;
+      atype.eltype = parsetype;
+    }
+    
+  if (skip_past_char (&str, '[') == SUCCESS)
+    {
+      if (type != REG_TYPE_VFD)
+        {
+          first_error (_("only D registers may be indexed"));
+          return FAIL;
+        }
+    
+      if ((atype.defined & NTA_HASINDEX) != 0)
+        {
+          first_error (_("can't change index for operand"));
+          return FAIL;
+        }
+
+      atype.defined |= NTA_HASINDEX;
+
+      if (skip_past_char (&str, ']') == SUCCESS)
+        atype.index = NEON_ALL_LANES;
+      else
+        {
+          expressionS exp;
+
+          my_get_expression (&exp, &str, GE_NO_PREFIX);
+
+          if (exp.X_op != O_constant)
+            {
+              first_error (_("constant expression required"));
+              return FAIL;
+            }
+
+          if (skip_past_char (&str, ']') == FAIL)
+            return FAIL;
+
+          atype.index = exp.X_add_number;
+        }
+    }
+  
+  if (typeinfo)
+    *typeinfo = atype;
+  
+  if (rtype)
+    *rtype = type;
+  
+  *ccp = str;
+  
+  return reg->number;
+}
+
+/* Like arm_reg_parse, but allow allow the following extra features:
+    - If RTYPE is non-zero, return the (possibly restricted) type of the
+      register (e.g. Neon double or quad reg when either has been requested).
+    - If this is a Neon vector type with additional type information, fill
+      in the struct pointed to by VECTYPE (if non-NULL).
+   This function will fault on encountering a scalar.
+*/
+
+static int
+arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
+                     enum arm_reg_type *rtype, struct neon_type_el *vectype)
+{
+  struct neon_typed_alias atype;
+  char *str = *ccp;
+  int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
+
+  if (reg == FAIL)
+    return FAIL;
+
+  /* Do not allow a scalar (reg+index) to parse as a register.  */
+  if ((atype.defined & NTA_HASINDEX) != 0)
+    {
+      first_error (_("register operand expected, but got scalar"));
+      return FAIL;
+    }
+
+  if (vectype)
+    *vectype = atype.eltype;
+
+  *ccp = str;
+
+  return reg;
+}
+
+#define NEON_SCALAR_REG(X)	((X) >> 4)
+#define NEON_SCALAR_INDEX(X)	((X) & 15)
+
+/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
+   have enough information to be able to do a good job bounds-checking. So, we
+   just do easy checks here, and do further checks later.  */
+
+static int
+parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
+{
+  int reg;
+  char *str = *ccp;
+  struct neon_typed_alias atype;
+  
+  reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
+  
+  if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
+    return FAIL;
+  
+  if (atype.index == NEON_ALL_LANES)
+    {
+      first_error (_("scalar must have an index"));
+      return FAIL;
+    }
+  else if (atype.index >= 64 / elsize)
+    {
+      first_error (_("scalar index out of range"));
+      return FAIL;
+    }
+  
+  if (type)
+    *type = atype.eltype;
+  
+  *ccp = str;
+  
+  return reg * 16 + atype.index;
+}
+
 /* Parse an ARM register list.  Returns the bitmask, or FAIL.  */
 static long
 parse_reg_list (char ** strp)
@@ -1011,7 +1441,7 @@ parse_reg_list (char ** strp)
 
 	      if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
 		{
-		  inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
+		  first_error (_(reg_expected_msgs[REG_TYPE_RN]));
 		  return FAIL;
 		}
 
@@ -1021,7 +1451,7 @@ parse_reg_list (char ** strp)
 
 		  if (reg <= cur_reg)
 		    {
-		      inst.error = _("bad range in register list");
+		      first_error (_("bad range in register list"));
 		      return FAIL;
 		    }
 
@@ -1052,7 +1482,7 @@ parse_reg_list (char ** strp)
 
 	  if (*str++ != '}')
 	    {
-	      inst.error = _("missing `}'");
+	      first_error (_("missing `}'"));
 	      return FAIL;
 	    }
 	}
@@ -1111,55 +1541,117 @@ parse_reg_list (char ** strp)
   return range;
 }
 
+/* Types of registers in a list.  */
+
+enum reg_list_els
+{
+  REGLIST_VFP_S,
+  REGLIST_VFP_D,
+  REGLIST_NEON_D
+};
+
 /* Parse a VFP register list.  If the string is invalid return FAIL.
    Otherwise return the number of registers, and set PBASE to the first
-   register.  Double precision registers are matched if DP is nonzero.	*/
+   register.  Parses registers of type ETYPE.
+   If REGLIST_NEON_D is used, several syntax enhancements are enabled:
+     - Q registers can be used to specify pairs of D registers
+     - { } can be omitted from around a singleton register list
+         FIXME: This is not implemented, as it would require backtracking in
+         some cases, e.g.:
+           vtbl.8 d3,d4,d5
+         This could be done (the meaning isn't really ambiguous), but doesn't
+         fit in well with the current parsing framework.
+     - 32 D registers may be used (also true for VFPv3).
+   FIXME: Types are ignored in these register lists, which is probably a
+   bug.  */
 
 static int
-parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
+parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
 {
+  char *str = *ccp;
   int base_reg;
   int new_base;
-  int regtype;
-  int max_regs;
+  enum arm_reg_type regtype = 0;
+  int max_regs = 0;
   int count = 0;
   int warned = 0;
   unsigned long mask = 0;
   int i;
 
-  if (**str != '{')
-    return FAIL;
+  if (*str != '{')
+    {
+      inst.error = _("expecting {");
+      return FAIL;
+    }
 
-  (*str)++;
+  str++;
 
-  if (dp)
+  switch (etype)
     {
+    case REGLIST_VFP_S:
+      regtype = REG_TYPE_VFS;
+      max_regs = 32;
+      break;
+    
+    case REGLIST_VFP_D:
       regtype = REG_TYPE_VFD;
-      max_regs = 16;
+      break;
+    
+    case REGLIST_NEON_D:
+      regtype = REG_TYPE_NDQ;
+      break;
     }
-  else
+
+  if (etype != REGLIST_VFP_S)
     {
-      regtype = REG_TYPE_VFS;
-      max_regs = 32;
+      /* VFPv3 allows 32 D registers.  */
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
+        {
+          max_regs = 32;
+          if (thumb_mode)
+            ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
+                                    fpu_vfp_ext_v3);
+          else
+            ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
+                                    fpu_vfp_ext_v3);
+        }
+      else
+        max_regs = 16;
     }
 
   base_reg = max_regs;
 
   do
     {
-      new_base = arm_reg_parse (str, regtype);
+      int setmask = 1, addregs = 1;
+
+      new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
+
       if (new_base == FAIL)
 	{
-	  inst.error = gettext (reg_expected_msgs[regtype]);
+	  first_error (_(reg_expected_msgs[regtype]));
 	  return FAIL;
 	}
+ 
+      if (new_base >= max_regs)
+        {
+          first_error (_("register out of range in list"));
+          return FAIL;
+        }
+ 
+      /* Note: a value of 2 * n is returned for the register Q<n>.  */
+      if (regtype == REG_TYPE_NQ)
+        {
+          setmask = 3;
+          addregs = 2;
+        }
 
       if (new_base < base_reg)
 	base_reg = new_base;
 
-      if (mask & (1 << new_base))
+      if (mask & (setmask << new_base))
 	{
-	  inst.error = _("invalid register list");
+	  first_error (_("invalid register list"));
 	  return FAIL;
 	}
 
@@ -1169,43 +1661,53 @@ parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
 	  warned = 1;
 	}
 
-      mask |= 1 << new_base;
-      count++;
+      mask |= setmask << new_base;
+      count += addregs;
 
-      if (**str == '-') /* We have the start of a range expression */
+      if (*str == '-') /* We have the start of a range expression */
 	{
 	  int high_range;
 
-	  (*str)++;
+	  str++;
 
-	  if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
+	  if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
+              == FAIL)
 	    {
 	      inst.error = gettext (reg_expected_msgs[regtype]);
 	      return FAIL;
 	    }
 
+          if (high_range >= max_regs)
+            {
+              first_error (_("register out of range in list"));
+              return FAIL;
+            }
+
+          if (regtype == REG_TYPE_NQ)
+            high_range = high_range + 1;
+
 	  if (high_range <= new_base)
 	    {
 	      inst.error = _("register range not in ascending order");
 	      return FAIL;
 	    }
 
-	  for (new_base++; new_base <= high_range; new_base++)
+	  for (new_base += addregs; new_base <= high_range; new_base += addregs)
 	    {
-	      if (mask & (1 << new_base))
+	      if (mask & (setmask << new_base))
 		{
 		  inst.error = _("invalid register list");
 		  return FAIL;
 		}
 
-	      mask |= 1 << new_base;
-	      count++;
+	      mask |= setmask << new_base;
+	      count += addregs;
 	    }
 	}
     }
-  while (skip_past_comma (str) != FAIL);
+  while (skip_past_comma (&str) != FAIL);
 
-  (*str)++;
+  str++;
 
   /* Sanity check -- should have raised a parse error above.  */
   if (count == 0 || count > max_regs)
@@ -1224,9 +1726,204 @@ parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
 	}
     }
 
+  *ccp = str;
+
   return count;
 }
 
+/* True if two alias types are the same.  */
+
+static int
+neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
+{
+  if (!a && !b)
+    return 1;
+    
+  if (!a || !b)
+    return 0;
+
+  if (a->defined != b->defined)
+    return 0;
+  
+  if ((a->defined & NTA_HASTYPE) != 0
+      && (a->eltype.type != b->eltype.type
+          || a->eltype.size != b->eltype.size))
+    return 0;
+
+  if ((a->defined & NTA_HASINDEX) != 0
+      && (a->index != b->index))
+    return 0;
+  
+  return 1;
+}
+
+/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
+   The base register is put in *PBASE.
+   The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
+   the return value.
+   The register stride (minus one) is put in bit 4 of the return value.
+   Bits [6:5] encode the list length (minus one).
+   The type of the list elements is put in *ELTYPE, if non-NULL.  */
+
+#define NEON_LANE(X)		((X) & 0xf)
+#define NEON_REG_STRIDE(X)	((((X) >> 4) & 1) + 1)
+#define NEON_REGLIST_LENGTH(X)	((((X) >> 5) & 3) + 1)
+
+static int
+parse_neon_el_struct_list (char **str, unsigned *pbase,
+                           struct neon_type_el *eltype)
+{
+  char *ptr = *str;
+  int base_reg = -1;
+  int reg_incr = -1;
+  int count = 0;
+  int lane = -1;
+  int leading_brace = 0;
+  enum arm_reg_type rtype = REG_TYPE_NDQ;
+  int addregs = 1;
+  const char *const incr_error = "register stride must be 1 or 2";
+  const char *const type_error = "mismatched element/structure types in list";
+  struct neon_typed_alias firsttype;
+  
+  if (skip_past_char (&ptr, '{') == SUCCESS)
+    leading_brace = 1;
+  
+  do
+    {
+      struct neon_typed_alias atype;
+      int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
+
+      if (getreg == FAIL)
+        {
+          first_error (_(reg_expected_msgs[rtype]));
+          return FAIL;
+        }
+      
+      if (base_reg == -1)
+        {
+          base_reg = getreg;
+          if (rtype == REG_TYPE_NQ)
+            {
+              reg_incr = 1;
+              addregs = 2;
+            }
+          firsttype = atype;
+        }
+      else if (reg_incr == -1)
+        {
+          reg_incr = getreg - base_reg;
+          if (reg_incr < 1 || reg_incr > 2)
+            {
+              first_error (_(incr_error));
+              return FAIL;
+            }
+        }
+      else if (getreg != base_reg + reg_incr * count)
+        {
+          first_error (_(incr_error));
+          return FAIL;
+        }
+
+      if (!neon_alias_types_same (&atype, &firsttype))
+        {
+          first_error (_(type_error));
+          return FAIL;
+        }
+      
+      /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
+         modes.  */
+      if (ptr[0] == '-')
+        {
+          struct neon_typed_alias htype;
+          int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
+          if (lane == -1)
+            lane = NEON_INTERLEAVE_LANES;
+          else if (lane != NEON_INTERLEAVE_LANES)
+            {
+              first_error (_(type_error));
+              return FAIL;
+            }
+          if (reg_incr == -1)
+            reg_incr = 1;
+          else if (reg_incr != 1)
+            {
+              first_error (_("don't use Rn-Rm syntax with non-unit stride"));
+              return FAIL;
+            }
+          ptr++;
+          hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
+          if (hireg == FAIL)
+            {
+              first_error (_(reg_expected_msgs[rtype]));
+              return FAIL;
+            }
+          if (!neon_alias_types_same (&htype, &firsttype))
+            {
+              first_error (_(type_error));
+              return FAIL;
+            }
+          count += hireg + dregs - getreg;
+          continue;
+        }
+      
+      /* If we're using Q registers, we can't use [] or [n] syntax.  */
+      if (rtype == REG_TYPE_NQ)
+        {
+          count += 2;
+          continue;
+        }
+      
+      if ((atype.defined & NTA_HASINDEX) != 0)
+        {
+          if (lane == -1)
+            lane = atype.index;
+          else if (lane != atype.index)
+            {
+              first_error (_(type_error));
+              return FAIL;
+            }
+        }
+      else if (lane == -1)
+        lane = NEON_INTERLEAVE_LANES;
+      else if (lane != NEON_INTERLEAVE_LANES)
+        {
+          first_error (_(type_error));
+          return FAIL;
+        }
+      count++;
+    }
+  while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
+  
+  /* No lane set by [x]. We must be interleaving structures.  */
+  if (lane == -1)
+    lane = NEON_INTERLEAVE_LANES;
+  
+  /* Sanity check.  */
+  if (lane == -1 || base_reg == -1 || count < 1 || count > 4
+      || (count > 1 && reg_incr == -1))
+    {
+      first_error (_("error parsing element/structure list"));
+      return FAIL;
+    }
+
+  if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
+    {
+      first_error (_("expected }"));
+      return FAIL;
+    }
+  
+  if (reg_incr == -1)
+    reg_incr = 1;
+
+  if (eltype)
+    *eltype = firsttype.eltype;
+
+  *pbase = base_reg;
+  *str = ptr;
+  
+  return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
+}
+
 /* Parse an explicit relocation suffix on an expression.  This is
    either nothing, or a word in parentheses.  Note that if !OBJ_ELF,
    arm_reloc_hsh contains no entries, so this function can only
@@ -1258,7 +1955,7 @@ parse_reloc (char **str)
 
 /* Directives: register aliases.  */
 
-static void
+static struct reg_entry *
 insert_reg_alias (char *str, int number, int type)
 {
   struct reg_entry *new;
@@ -1274,7 +1971,7 @@ insert_reg_alias (char *str, int number, int type)
       else if (new->number != number || new->type != type)
 	as_warn (_("ignoring redefinition of register alias '%s'"), str);
 
-      return;
+      return 0;
     }
 
   name = xstrdup (str);
@@ -1284,9 +1981,31 @@ insert_reg_alias (char *str, int number, int type)
   new->number = number;
   new->type = type;
   new->builtin = FALSE;
+  new->neon = NULL;
 
   if (hash_insert (arm_reg_hsh, name, (PTR) new))
     abort ();
+  
+  return new;
+}
+
+static void
+insert_neon_reg_alias (char *str, int number, int type,
+                       struct neon_typed_alias *atype)
+{
+  struct reg_entry *reg = insert_reg_alias (str, number, type);
+  
+  if (!reg)
+    {
+      first_error (_("attempt to redefine typed alias"));
+      return;
+    }
+  
+  if (atype)
+    {
+      reg->neon = xmalloc (sizeof (struct neon_typed_alias));
+      *reg->neon = *atype;
+    }
 }
 
 /* Look for the .req directive.	 This is of the form:
@@ -1354,6 +2073,148 @@ create_register_alias (char * newname, char *p)
   return 1;
 }
 
+/* Create a Neon typed/indexed register alias using directives, e.g.:
+     X .dn d5.s32[1]
+     Y .qn 6.s16
+     Z .dn d7
+     T .dn Z[0]
+   These typed registers can be used instead of the types specified after the
+   Neon mnemonic, so long as all operands given have types. Types can also be
+   specified directly, e.g.:
+     vadd d0.s32, d1.s32, d2.s32
+*/
+
+static int
+create_neon_reg_alias (char *newname, char *p)
+{
+  enum arm_reg_type basetype;
+  struct reg_entry *basereg;
+  struct reg_entry mybasereg;
+  struct neon_type ntype;
+  struct neon_typed_alias typeinfo;
+  char *namebuf, *nameend;
+  int namelen;
+  
+  typeinfo.defined = 0;
+  typeinfo.eltype.type = NT_invtype;
+  typeinfo.eltype.size = -1;
+  typeinfo.index = -1;
+  
+  nameend = p;
+  
+  if (strncmp (p, " .dn ", 5) == 0)
+    basetype = REG_TYPE_VFD;
+  else if (strncmp (p, " .qn ", 5) == 0)
+    basetype = REG_TYPE_NQ;
+  else
+    return 0;
+  
+  p += 5;
+  
+  if (*p == '\0')
+    return 0;
+  
+  basereg = arm_reg_parse_multi (&p);
+
+  if (basereg && basereg->type != basetype)
+    {
+      as_bad (_("bad type for register"));
+      return 0;
+    }
+
+  if (basereg == NULL)
+    {
+      expressionS exp;
+      /* Try parsing as an integer.  */
+      my_get_expression (&exp, &p, GE_NO_PREFIX);
+      if (exp.X_op != O_constant)
+        {
+          as_bad (_("expression must be constant"));
+          return 0;
+        }
+      basereg = &mybasereg;
+      basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
+                                                  : exp.X_add_number;
+      basereg->neon = 0;
+    }
+
+  if (basereg->neon)
+    typeinfo = *basereg->neon;
+
+  if (parse_neon_type (&ntype, &p) == SUCCESS)
+    {
+      /* We got a type.  */
+      if (typeinfo.defined & NTA_HASTYPE)
+        {
+          as_bad (_("can't redefine the type of a register alias"));
+          return 0;
+        }
+      
+      typeinfo.defined |= NTA_HASTYPE;
+      if (ntype.elems != 1)
+        {
+          as_bad (_("you must specify a single type only"));
+          return 0;
+        }
+      typeinfo.eltype = ntype.el[0];
+    }
+  
+  if (skip_past_char (&p, '[') == SUCCESS)
+    {
+      expressionS exp;
+      /* We got a scalar index.  */
+    
+      if (typeinfo.defined & NTA_HASINDEX)
+        {
+          as_bad (_("can't redefine the index of a scalar alias"));
+          return 0;
+        }
+    
+      my_get_expression (&exp, &p, GE_NO_PREFIX);
+    
+      if (exp.X_op != O_constant)
+        {
+          as_bad (_("scalar index must be constant"));
+          return 0;
+        }
+      
+      typeinfo.defined |= NTA_HASINDEX;
+      typeinfo.index = exp.X_add_number;
+    
+      if (skip_past_char (&p, ']') == FAIL)
+        {
+          as_bad (_("expecting ]"));
+          return 0;
+        }
+    }
+
+  namelen = nameend - newname;
+  namebuf = alloca (namelen + 1);
+  strncpy (namebuf, newname, namelen);
+  namebuf[namelen] = '\0';
+  
+  insert_neon_reg_alias (namebuf, basereg->number, basetype,
+                         typeinfo.defined != 0 ? &typeinfo : NULL);
+    
+  /* Insert name in all uppercase.  */
+  for (p = namebuf; *p; p++)
+    *p = TOUPPER (*p);
+  
+  if (strncmp (namebuf, newname, namelen))
+    insert_neon_reg_alias (namebuf, basereg->number, basetype,
+                           typeinfo.defined != 0 ? &typeinfo : NULL);
+  
+  /* Insert name in all lowercase.  */
+  for (p = namebuf; *p; p++)
+    *p = TOLOWER (*p);
+  
+  if (strncmp (namebuf, newname, namelen))
+    insert_neon_reg_alias (namebuf, basereg->number, basetype,
+                           typeinfo.defined != 0 ? &typeinfo : NULL);
+  
+  return 1;
+}
+
 /* Should never be called, as .req goes between the alias and the
    register name, not at the beginning of the line.  */
 static void
@@ -1362,6 +2223,18 @@ s_req (int a ATTRIBUTE_UNUSED)
   as_bad (_("invalid syntax for .req directive"));
 }
 
+static void
+s_dn (int a ATTRIBUTE_UNUSED)
+{
+  as_bad (_("invalid syntax for .dn directive"));
+}
+
+static void
+s_qn (int a ATTRIBUTE_UNUSED)
+{
+  as_bad (_("invalid syntax for .qn directive"));
+}
+
 /* The .unreq directive deletes an alias which was previously defined
    by .req.  For example:
 
@@ -1399,6 +2272,8 @@ s_unreq (int a ATTRIBUTE_UNUSED)
 	{
 	  hash_delete (arm_reg_hsh, name);
 	  free ((char *) reg->name);
+          if (reg->neon)
+            free (reg->neon);
 	  free (reg);
 	}
     }
@@ -1417,7 +2292,7 @@ s_unreq (int a ATTRIBUTE_UNUSED)
 
 static enum mstate mapstate = MAP_UNDEFINED;
 
-static void
+void
 mapping_state (enum mstate state)
 {
   symbolS * symbolP;
@@ -1738,6 +2613,7 @@ static void
 s_align (int unused ATTRIBUTE_UNUSED)
 {
   int temp;
+  bfd_boolean fill_p;
   long temp_fill;
   long max_alignment = 15;
 
@@ -1754,16 +2630,25 @@ s_align (int unused ATTRIBUTE_UNUSED)
     {
       input_line_pointer++;
       temp_fill = get_absolute_expression ();
+      fill_p = TRUE;
     }
   else
-    temp_fill = 0;
+    {
+      fill_p = FALSE;
+      temp_fill = 0;
+    }
 
   if (!temp)
     temp = 2;
 
   /* Only make a frag if we HAVE to.  */
   if (temp && !need_pass_2)
-    frag_align (temp, (int) temp_fill, 0);
+    {
+      if (!fill_p && subseg_text_p (now_seg))
+	frag_align_code (temp, 0);
+      else
+	frag_align (temp, (int) temp_fill, 0);
+    }
   demand_empty_rest_of_line ();
 
   record_alignment (now_seg, temp);
@@ -2414,7 +3299,57 @@ s_arm_unwind_save_fpa (int reg)
 }
 
 
-/* Parse a directive saving VFP registers.  */
+/* Parse a directive saving VFP registers for ARMv6 and above.  */
+
+static void
+s_arm_unwind_save_vfp_armv6 (void)
+{
+  int count;
+  unsigned int start;
+  valueT op;
+  int num_vfpv3_regs = 0;
+  int num_regs_below_16;
+
+  count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
+  if (count == FAIL)
+    {
+      as_bad (_("expected register list"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  demand_empty_rest_of_line ();
+
+  /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
+     than FSTMX/FLDMX-style ones).  */
+
+  /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31.  */
+  if (start >= 16)
+    num_vfpv3_regs = count;
+  else if (start + count > 16)
+    num_vfpv3_regs = start + count - 16;
+
+  if (num_vfpv3_regs > 0)
+    {
+      int start_offset = start > 16 ? start - 16 : 0;
+      op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
+      add_unwind_opcode (op, 2);
+    }
+
+  /* Generate opcode for registers numbered in the range 0 .. 15.  */
+  num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
+  assert (num_regs_below_16 + num_vfpv3_regs == count);
+  if (num_regs_below_16 > 0)
+    {
+      op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
+      add_unwind_opcode (op, 2);
+    }
+
+  unwind.frame_size += count * 8;
+}
+
+
+/* Parse a directive saving VFP registers for pre-ARMv6.  */
 
 static void
 s_arm_unwind_save_vfp (void)
@@ -2423,7 +3358,7 @@ s_arm_unwind_save_vfp (void)
   unsigned int reg;
   valueT op;
 
-  count = parse_vfp_reg_list (&input_line_pointer, &reg, 1);
+  count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
   if (count == FAIL)
     {
       as_bad (_("expected register list"));
@@ -2502,7 +3437,7 @@ s_arm_unwind_save_mmxwr (void)
 
   demand_empty_rest_of_line ();
 
-  /* Generate any deferred opcodes becuuse we're going to be looking at
+  /* Generate any deferred opcodes because we're going to be looking at
      the list.	*/
   flush_pending_unwind ();
 
@@ -2538,7 +3473,7 @@ s_arm_unwind_save_mmxwr (void)
 
 	      op = 0xffff << (reg - 1);
 	      if (reg > 0
-		  || ((mask & op) == (1u << (reg - 1))))
+		  && ((mask & op) == (1u << (reg - 1))))
 		{
 		  op = (1 << (reg + i + 1)) - 1;
 		  op &= ~((1 << reg) - 1);
@@ -2635,7 +3570,7 @@ s_arm_unwind_save_mmxwcg (void)
 
   demand_empty_rest_of_line ();
 
-  /* Generate any deferred opcodes becuuse we're going to be looking at
+  /* Generate any deferred opcodes because we're going to be looking at
      the list.	*/
   flush_pending_unwind ();
 
@@ -2652,10 +3587,11 @@ error:
 }
 
 
-/* Parse an unwind_save directive.  */
+/* Parse an unwind_save directive.
+   If the argument is non-zero, this is a .vsave directive.  */
 
 static void
-s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
+s_arm_unwind_save (int arch_v6)
 {
   char *peek;
   struct reg_entry *reg;
@@ -2692,7 +3628,12 @@ s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
       return;
 
     case REG_TYPE_RN:	  s_arm_unwind_save_core ();   return;
-    case REG_TYPE_VFD:	   s_arm_unwind_save_vfp ();	return;
+    case REG_TYPE_VFD:
+      if (arch_v6)
+        s_arm_unwind_save_vfp_armv6 ();
+      else
+        s_arm_unwind_save_vfp ();
+      return;
     case REG_TYPE_MMXWR:  s_arm_unwind_save_mmxwr ();  return;
     case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
 
@@ -2710,6 +3651,7 @@ s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
 {
   int reg;
   valueT op;
+  int offset;
 
   reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
   if (reg == FAIL)
@@ -2718,6 +3660,16 @@ s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
       ignore_rest_of_line ();
       return;
     }
+
+  /* Optional constant.	 */
+  if (skip_past_comma (&input_line_pointer) != FAIL)
+    {
+      if (immediate_for_directive (&offset) == FAIL)
+	return;
+    }
+  else
+    offset = 0;
+
   demand_empty_rest_of_line ();
 
   if (reg == REG_SP || reg == REG_PC)
@@ -2735,7 +3687,7 @@ s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
 
   /* Record the information for later.	*/
   unwind.fp_reg = reg;
-  unwind.fp_offset = unwind.frame_size;
+  unwind.fp_offset = unwind.frame_size - offset;
   unwind.sp_restored = 1;
 }
 
@@ -2818,7 +3770,7 @@ static void
 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
 {
   expressionS exp;
-  /* This is an arbitary limit.	 */
+  /* This is an arbitrary limit.	 */
   unsigned char op[16];
   int count;
 
@@ -2877,90 +3829,36 @@ s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
 static void
 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
 {
-  expressionS exp;
-  bfd_boolean is_string;
-  int tag;
-  unsigned int i = 0;
-  char *s = NULL;
-  char saved_char;
+  s_vendor_attribute (OBJ_ATTR_PROC);
+}
+#endif /* OBJ_ELF */
 
-  expression (& exp);
-  if (exp.X_op != O_constant)
-    goto bad;
+static void s_arm_arch (int);
+static void s_arm_object_arch (int);
+static void s_arm_cpu (int);
+static void s_arm_fpu (int);
 
-  tag = exp.X_add_number;
-  if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
-    is_string = 1;
-  else
-    is_string = 0;
+#ifdef TE_PE
 
-  if (skip_past_comma (&input_line_pointer) == FAIL)
-    goto bad;
-  if (tag == 32 || !is_string)
-    {
-      expression (& exp);
-      if (exp.X_op != O_constant)
-	{
-	  as_bad (_("expected numeric constant"));
-	  ignore_rest_of_line ();
-	  return;
-	}
-      i = exp.X_add_number;
-    }
-  if (tag == Tag_compatibility
-      && skip_past_comma (&input_line_pointer) == FAIL)
-    {
-      as_bad (_("expected comma"));
-      ignore_rest_of_line ();
-      return;
-    }
-  if (is_string)
-    {
-      skip_whitespace(input_line_pointer);
-      if (*input_line_pointer != '"')
-	goto bad_string;
-      input_line_pointer++;
-      s = input_line_pointer;
-      while (*input_line_pointer && *input_line_pointer != '"')
-	input_line_pointer++;
-      if (*input_line_pointer != '"')
-	goto bad_string;
-      saved_char = *input_line_pointer;
-      *input_line_pointer = 0;
-    }
-  else
-    {
-      s = NULL;
-      saved_char = 0;
-    }
-  
-  if (tag == Tag_compatibility)
-    elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
-  else if (is_string)
-    elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
-  else
-    elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
+static void
+pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 
+{
+  expressionS exp;
 
-  if (s)
+  do
     {
-      *input_line_pointer = saved_char;
-      input_line_pointer++;
+      expression (&exp);
+      if (exp.X_op == O_symbol)
+	exp.X_op = O_secrel;
+
+      emit_expr (&exp, 4);
     }
+  while (*input_line_pointer++ == ',');
+
+  input_line_pointer--;
   demand_empty_rest_of_line ();
-  return;
-bad_string:
-  as_bad (_("bad string constant"));
-  ignore_rest_of_line ();
-  return;
-bad:
-  as_bad (_("expected <tag> , <value>"));
-  ignore_rest_of_line ();
 }
-
-static void s_arm_arch (int);
-static void s_arm_cpu (int);
-static void s_arm_fpu (int);
-#endif /* OBJ_ELF */
+#endif /* TE_PE */
 
 /* This table describes all the machine specific pseudo-ops the assembler
    has to support.  The fields are:
@@ -2972,6 +3870,9 @@ const pseudo_typeS md_pseudo_table[] =
 {
   /* Never called because '.req' does not start a line.	 */
   { "req",	   s_req,	  0 },
+  /* Following two are likewise never called.  */
+  { "dn",	   s_dn,          0 },
+  { "qn",          s_qn,          0 },
   { "unreq",	   s_unreq,	  0 },
   { "bss",	   s_bss,	  0 },
   { "align",	   s_align,	  0 },
@@ -2985,6 +3886,10 @@ const pseudo_typeS md_pseudo_table[] =
   { "ltorg",	   s_ltorg,	  0 },
   { "pool",	   s_ltorg,	  0 },
   { "syntax",	   s_syntax,	  0 },
+  { "cpu",	   s_arm_cpu,	  0 },
+  { "arch",	   s_arm_arch,	  0 },
+  { "object_arch", s_arm_object_arch,	0 },
+  { "fpu",	   s_arm_fpu,	  0 },
 #ifdef OBJ_ELF
   { "word",	   s_arm_elf_cons, 4 },
   { "long",	   s_arm_elf_cons, 4 },
@@ -2996,20 +3901,30 @@ const pseudo_typeS md_pseudo_table[] =
   { "personalityindex",	s_arm_unwind_personalityindex, 0 },
   { "handlerdata",	s_arm_unwind_handlerdata, 0 },
   { "save",		s_arm_unwind_save,	0 },
+  { "vsave",		s_arm_unwind_save,	1 },
   { "movsp",		s_arm_unwind_movsp,	0 },
   { "pad",		s_arm_unwind_pad,	0 },
   { "setfp",		s_arm_unwind_setfp,	0 },
   { "unwind_raw",	s_arm_unwind_raw,	0 },
-  { "cpu",		s_arm_cpu,		0 },
-  { "arch",		s_arm_arch,		0 },
-  { "fpu",		s_arm_fpu,		0 },
   { "eabi_attribute",	s_arm_eabi_attribute,	0 },
 #else
   { "word",	   cons, 4},
+
+  /* These are used for dwarf.  */
+  {"2byte", cons, 2},
+  {"4byte", cons, 4},
+  {"8byte", cons, 8},
+  /* These are used for dwarf2.  */
+  { "file", (void (*) (int)) dwarf2_directive_file, 0 },
+  { "loc",  dwarf2_directive_loc,  0 },
+  { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
 #endif
   { "extend",	   float_cons, 'x' },
   { "ldouble",	   float_cons, 'x' },
   { "packed",	   float_cons, 'p' },
+#ifdef TE_PE
+  {"secrel32", pe_directive_secrel, 0},
+#endif
   { 0, 0, 0 }
 };
 
@@ -3043,6 +3958,58 @@ parse_immediate (char **str, int *val, int min, int max,
   return SUCCESS;
 }
 
+/* Less-generic immediate-value read function with the possibility of loading a
+   big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
+   instructions. Puts the result directly in inst.operands[i].  */
+
+static int
+parse_big_immediate (char **str, int i)
+{
+  expressionS exp;
+  char *ptr = *str;
+
+  my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
+
+  if (exp.X_op == O_constant)
+    {
+      inst.operands[i].imm = exp.X_add_number & 0xffffffff;
+      /* If we're on a 64-bit host, then a 64-bit number can be returned using
+	 O_constant.  We have to be careful not to break compilation for
+	 32-bit X_add_number, though.  */
+      if ((exp.X_add_number & ~0xffffffffl) != 0)
+	{
+          /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4.  */
+	  inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
+	  inst.operands[i].regisimm = 1;
+	}
+    }
+  else if (exp.X_op == O_big
+           && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
+           && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
+    {
+      unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
+      /* Bignums have their least significant bits in
+         generic_bignum[0]. Make sure we put 32 bits in imm and
+         32 bits in reg,  in a (hopefully) portable way.  */
+      assert (parts != 0);
+      inst.operands[i].imm = 0;
+      for (j = 0; j < parts; j++, idx++)
+        inst.operands[i].imm |= generic_bignum[idx]
+                                << (LITTLENUM_NUMBER_OF_BITS * j);
+      inst.operands[i].reg = 0;
+      for (j = 0; j < parts; j++, idx++)
+        inst.operands[i].reg |= generic_bignum[idx]
+                                << (LITTLENUM_NUMBER_OF_BITS * j);
+      inst.operands[i].regisimm = 1;
+    }
+  else
+    return FAIL;
+  
+  *str = ptr;
+
+  return SUCCESS;
+}
+
 /* Returns the pseudo-register number of an FPA immediate constant,
    or FAIL if there isn't a valid constant here.  */
 
@@ -3134,6 +4101,80 @@ parse_fpa_immediate (char ** str)
   return FAIL;
 }
 
+/* Returns 1 if a number has "quarter-precision" float format
+   0baBbbbbbc defgh000 00000000 00000000.  */
+
+static int
+is_quarter_float (unsigned imm)
+{
+  int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
+  return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
+}
+
+/* Parse an 8-bit "quarter-precision" floating point number of the form:
+   0baBbbbbbc defgh000 00000000 00000000.
+   The zero and minus-zero cases need special handling, since they can't be
+   encoded in the "quarter-precision" float format, but can nonetheless be
+   loaded as integer constants.  */
+
+static unsigned
+parse_qfloat_immediate (char **ccp, int *immed)
+{
+  char *str = *ccp;
+  char *fpnum;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  int found_fpchar = 0;
+  
+  skip_past_char (&str, '#');
+  
+  /* We must not accidentally parse an integer as a floating-point number. Make
+     sure that the value we parse is not an integer by checking for special
+     characters '.' or 'e'.
+     FIXME: This is a horrible hack, but doing better is tricky because type
+     information isn't in a very usable state at parse time.  */
+  fpnum = str;
+  skip_whitespace (fpnum);
+
+  if (strncmp (fpnum, "0x", 2) == 0)
+    return FAIL;
+  else
+    {
+      for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
+        if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
+          {
+            found_fpchar = 1;
+            break;
+          }
+
+      if (!found_fpchar)
+        return FAIL;
+    }
+  
+  if ((str = atof_ieee (str, 's', words)) != NULL)
+    {
+      unsigned fpword = 0;
+      int i;
+      
+      /* Our FP word must be 32 bits (single-precision FP).  */
+      for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
+        {
+          fpword <<= LITTLENUM_NUMBER_OF_BITS;
+          fpword |= words[i];
+        }
+      
+      if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
+        *immed = fpword;
+      else
+        return FAIL;
+
+      *ccp = str;
+      
+      return SUCCESS;
+    }
+  
+  return FAIL;
+}
+
 /* Shift operands.  */
 enum shift_kind
 {
@@ -3317,6 +4358,168 @@ parse_shifter_operand (char **str, int i)
   return SUCCESS;
 }
 
+/* Group relocation information.  Each entry in the table contains the
+   textual name of the relocation as may appear in assembler source
+   and must end with a colon.
+   Along with this textual name are the relocation codes to be used if
+   the corresponding instruction is an ALU instruction (ADD or SUB only),
+   an LDR, an LDRS, or an LDC.  */
+
+struct group_reloc_table_entry
+{
+  const char *name;
+  int alu_code;
+  int ldr_code;
+  int ldrs_code;
+  int ldc_code;
+};
+
+typedef enum
+{
+  /* Varieties of non-ALU group relocation.  */
+
+  GROUP_LDR,
+  GROUP_LDRS,
+  GROUP_LDC
+} group_reloc_type;
+
+static struct group_reloc_table_entry group_reloc_table[] =
+  { /* Program counter relative: */
+    { "pc_g0_nc",
+      BFD_RELOC_ARM_ALU_PC_G0_NC,	/* ALU */
+      0,				/* LDR */
+      0,				/* LDRS */
+      0 },				/* LDC */
+    { "pc_g0",
+      BFD_RELOC_ARM_ALU_PC_G0,		/* ALU */
+      BFD_RELOC_ARM_LDR_PC_G0,		/* LDR */
+      BFD_RELOC_ARM_LDRS_PC_G0,		/* LDRS */
+      BFD_RELOC_ARM_LDC_PC_G0 },	/* LDC */
+    { "pc_g1_nc",
+      BFD_RELOC_ARM_ALU_PC_G1_NC,	/* ALU */
+      0,				/* LDR */
+      0,				/* LDRS */
+      0 },				/* LDC */
+    { "pc_g1",
+      BFD_RELOC_ARM_ALU_PC_G1,		/* ALU */
+      BFD_RELOC_ARM_LDR_PC_G1, 		/* LDR */
+      BFD_RELOC_ARM_LDRS_PC_G1,		/* LDRS */
+      BFD_RELOC_ARM_LDC_PC_G1 },	/* LDC */
+    { "pc_g2",
+      BFD_RELOC_ARM_ALU_PC_G2,		/* ALU */
+      BFD_RELOC_ARM_LDR_PC_G2,		/* LDR */
+      BFD_RELOC_ARM_LDRS_PC_G2,		/* LDRS */
+      BFD_RELOC_ARM_LDC_PC_G2 },	/* LDC */
+    /* Section base relative */
+    { "sb_g0_nc",
+      BFD_RELOC_ARM_ALU_SB_G0_NC,	/* ALU */
+      0,				/* LDR */
+      0,				/* LDRS */
+      0 },				/* LDC */
+    { "sb_g0",
+      BFD_RELOC_ARM_ALU_SB_G0,		/* ALU */
+      BFD_RELOC_ARM_LDR_SB_G0,		/* LDR */
+      BFD_RELOC_ARM_LDRS_SB_G0,		/* LDRS */
+      BFD_RELOC_ARM_LDC_SB_G0 },	/* LDC */
+    { "sb_g1_nc",
+      BFD_RELOC_ARM_ALU_SB_G1_NC,	/* ALU */
+      0,				/* LDR */
+      0,				/* LDRS */
+      0 },				/* LDC */
+    { "sb_g1",
+      BFD_RELOC_ARM_ALU_SB_G1,		/* ALU */
+      BFD_RELOC_ARM_LDR_SB_G1, 		/* LDR */
+      BFD_RELOC_ARM_LDRS_SB_G1,		/* LDRS */
+      BFD_RELOC_ARM_LDC_SB_G1 },	/* LDC */
+    { "sb_g2",
+      BFD_RELOC_ARM_ALU_SB_G2,		/* ALU */
+      BFD_RELOC_ARM_LDR_SB_G2,		/* LDR */
+      BFD_RELOC_ARM_LDRS_SB_G2,		/* LDRS */
+      BFD_RELOC_ARM_LDC_SB_G2 }	};	/* LDC */
+
+/* Given the address of a pointer pointing to the textual name of a group
+   relocation as may appear in assembler source, attempt to find its details
+   in group_reloc_table.  The pointer will be updated to the character after
+   the trailing colon.  On failure, FAIL will be returned; SUCCESS
+   otherwise.  On success, *entry will be updated to point at the relevant
+   group_reloc_table entry. */
+
+static int
+find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
+{
+  unsigned int i;
+  for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
+    {
+      int length = strlen (group_reloc_table[i].name);
+
+      if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
+          (*str)[length] == ':')
+        {
+          *out = &group_reloc_table[i];
+          *str += (length + 1);
+          return SUCCESS;
+        }
+    }
+
+  return FAIL;
+}
+
+/* Parse a <shifter_operand> for an ARM data processing instruction
+   (as for parse_shifter_operand) where group relocations are allowed:
+
+      #<immediate>
+      #<immediate>, <rotate>
+      #:<group_reloc>:<expression>
+      <Rm>
+      <Rm>, <shift>
+
+   where <group_reloc> is one of the strings defined in group_reloc_table.
+   The hashes are optional.
+
+   Everything else is as for parse_shifter_operand.  */
+
+static parse_operand_result
+parse_shifter_operand_group_reloc (char **str, int i)
+{
+  /* Determine if we have the sequence of characters #: or just :
+     coming next.  If we do, then we check for a group relocation.
+     If we don't, punt the whole lot to parse_shifter_operand.  */
+
+  if (((*str)[0] == '#' && (*str)[1] == ':')
+      || (*str)[0] == ':')
+    {
+      struct group_reloc_table_entry *entry;
+
+      if ((*str)[0] == '#')
+        (*str) += 2;
+      else
+        (*str)++;
+
+      /* Try to parse a group relocation.  Anything else is an error.  */
+      if (find_group_reloc_table_entry (str, &entry) == FAIL)
+        {
+          inst.error = _("unknown group relocation");
+          return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+        }
+
+      /* We now have the group relocation table entry corresponding to
+         the name in the assembler source.  Next, we parse the expression.  */
+      if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
+        return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+
+      /* Record the relocation type (always the ALU variant here).  */
+      inst.reloc.type = entry->alu_code;
+      assert (inst.reloc.type != 0);
+
+      return PARSE_OPERAND_SUCCESS;
+    }
+  else
+    return parse_shifter_operand (str, i) == SUCCESS
+           ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
+
+  /* Never reached.  */
+}
+
 /* Parse all forms of an ARM address expression.  Information is written
    to inst.operands[i] and/or inst.reloc.
 
@@ -3349,8 +4552,9 @@ parse_shifter_operand (char **str, int i)
   It is the caller's responsibility to check for addressing modes not
   supported by the instruction, and to set inst.reloc.type.  */
 
-static int
-parse_address (char **str, int i)
+static parse_operand_result
+parse_address_main (char **str, int i, int group_relocations,
+                    group_reloc_type group_type)
 {
   char *p = *str;
   int reg;
@@ -3368,16 +4572,16 @@ parse_address (char **str, int i)
       /* else a load-constant pseudo op, no special treatment needed here */
 
       if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
-	return FAIL;
+	return PARSE_OPERAND_FAIL;
 
       *str = p;
-      return SUCCESS;
+      return PARSE_OPERAND_SUCCESS;
     }
 
   if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
     {
       inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
-      return FAIL;
+      return PARSE_OPERAND_FAIL;
     }
   inst.operands[i].reg = reg;
   inst.operands[i].isreg = 1;
@@ -3396,8 +4600,25 @@ parse_address (char **str, int i)
 
 	  if (skip_past_comma (&p) == SUCCESS)
 	    if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
-	      return FAIL;
+	      return PARSE_OPERAND_FAIL;
 	}
+      else if (skip_past_char (&p, ':') == SUCCESS)
+        {
+          /* FIXME: '@' should be used here, but it's filtered out by generic
+             code before we get to see it here. This may be subject to
+             change.  */
+          expressionS exp;
+          my_get_expression (&exp, &p, GE_NO_PREFIX);
+          if (exp.X_op != O_constant)
+            {
+              inst.error = _("alignment must be constant");
+              return PARSE_OPERAND_FAIL;
+            }
+          inst.operands[i].imm = exp.X_add_number << 8;
+          inst.operands[i].immisalign = 1;
+          /* Alignments are not pre-indexes.  */
+          inst.operands[i].preind = 0;
+        }
       else
 	{
 	  if (inst.operands[i].negative)
@@ -3405,15 +4626,68 @@ parse_address (char **str, int i)
 	      inst.operands[i].negative = 0;
 	      p--;
 	    }
-	  if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
-	    return FAIL;
+
+	  if (group_relocations &&
+              ((*p == '#' && *(p + 1) == ':') || *p == ':'))
+
+	    {
+	      struct group_reloc_table_entry *entry;
+
+              /* Skip over the #: or : sequence.  */
+              if (*p == '#')
+                p += 2;
+              else
+                p++;
+
+	      /* Try to parse a group relocation.  Anything else is an
+                 error.  */
+	      if (find_group_reloc_table_entry (&p, &entry) == FAIL)
+		{
+		  inst.error = _("unknown group relocation");
+		  return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+		}
+
+	      /* We now have the group relocation table entry corresponding to
+		 the name in the assembler source.  Next, we parse the
+                 expression.  */
+	      if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
+		return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+
+	      /* Record the relocation type.  */
+              switch (group_type)
+                {
+                  case GROUP_LDR:
+	            inst.reloc.type = entry->ldr_code;
+                    break;
+
+                  case GROUP_LDRS:
+	            inst.reloc.type = entry->ldrs_code;
+                    break;
+
+                  case GROUP_LDC:
+	            inst.reloc.type = entry->ldc_code;
+                    break;
+
+                  default:
+                    assert (0);
+                }
+
+              if (inst.reloc.type == 0)
+		{
+		  inst.error = _("this group relocation is not allowed on this instruction");
+		  return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+		}
+            }
+          else
+	    if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
+	      return PARSE_OPERAND_FAIL;
 	}
     }
 
   if (skip_past_char (&p, ']') == FAIL)
     {
       inst.error = _("']' expected");
-      return FAIL;
+      return PARSE_OPERAND_FAIL;
     }
 
   if (skip_past_char (&p, '!') == SUCCESS)
@@ -3426,20 +4700,20 @@ parse_address (char **str, int i)
 	  /* [Rn], {expr} - unindexed, with option */
 	  if (parse_immediate (&p, &inst.operands[i].imm,
 			       0, 255, TRUE) == FAIL)
-	    return FAIL;
+	    return PARSE_OPERAND_FAIL;
 
 	  if (skip_past_char (&p, '}') == FAIL)
 	    {
 	      inst.error = _("'}' expected at end of 'option' field");
-	      return FAIL;
+	      return PARSE_OPERAND_FAIL;
 	    }
 	  if (inst.operands[i].preind)
 	    {
 	      inst.error = _("cannot combine index with option");
-	      return FAIL;
+	      return PARSE_OPERAND_FAIL;
 	    }
 	  *str = p;
-	  return SUCCESS;
+	  return PARSE_OPERAND_SUCCESS;
 	}
       else
 	{
@@ -3449,7 +4723,7 @@ parse_address (char **str, int i)
 	  if (inst.operands[i].preind)
 	    {
 	      inst.error = _("cannot combine pre- and post-indexing");
-	      return FAIL;
+	      return PARSE_OPERAND_FAIL;
 	    }
 
 	  if (*p == '+') p++;
@@ -3457,12 +4731,17 @@ parse_address (char **str, int i)
 
 	  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
 	    {
-	      inst.operands[i].imm = reg;
+              /* We might be using the immediate for alignment already. If we
+                 are, OR the register number into the low-order bits.  */
+              if (inst.operands[i].immisalign)
+	        inst.operands[i].imm |= reg;
+              else
+                inst.operands[i].imm = reg;
 	      inst.operands[i].immisreg = 1;
 
 	      if (skip_past_comma (&p) == SUCCESS)
 		if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
-		  return FAIL;
+		  return PARSE_OPERAND_FAIL;
 	    }
 	  else
 	    {
@@ -3472,7 +4751,7 @@ parse_address (char **str, int i)
 		  p--;
 		}
 	      if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
-		return FAIL;
+		return PARSE_OPERAND_FAIL;
 	    }
 	}
     }
@@ -3486,6 +4765,59 @@ parse_address (char **str, int i)
       inst.reloc.exp.X_add_number = 0;
     }
   *str = p;
+  return PARSE_OPERAND_SUCCESS;
+}
+
+static int
+parse_address (char **str, int i)
+{
+  return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
+         ? SUCCESS : FAIL;
+}
+
+static parse_operand_result
+parse_address_group_reloc (char **str, int i, group_reloc_type type)
+{
+  return parse_address_main (str, i, 1, type);
+}
+
+/* Parse an operand for a MOVW or MOVT instruction.  */
+static int
+parse_half (char **str)
+{
+  char * p;
+  
+  p = *str;
+  skip_past_char (&p, '#');
+  if (strncasecmp (p, ":lower16:", 9) == 0) 
+    inst.reloc.type = BFD_RELOC_ARM_MOVW;
+  else if (strncasecmp (p, ":upper16:", 9) == 0)
+    inst.reloc.type = BFD_RELOC_ARM_MOVT;
+
+  if (inst.reloc.type != BFD_RELOC_UNUSED)
+    {
+      p += 9;
+      skip_whitespace(p);
+    }
+
+  if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
+    return FAIL;
+
+  if (inst.reloc.type == BFD_RELOC_UNUSED)
+    {
+      if (inst.reloc.exp.X_op != O_constant)
+	{
+	  inst.error = _("constant expression expected");
+	  return FAIL;
+	}
+      if (inst.reloc.exp.X_add_number < 0
+	  || inst.reloc.exp.X_add_number > 0xffff)
+	{
+	  inst.error = _("immediate value out of range");
+	  return FAIL;
+	}
+    }
+  *str = p;
   return SUCCESS;
 }
 
@@ -3752,6 +5084,228 @@ parse_tb (char **str)
   return SUCCESS;
 }
 
+/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
+   information on the types the operands can take and how they are encoded.
+   Up to four operands may be read; this function handles setting the
+   ".present" field for each read operand itself.
+   Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
+   else returns FAIL.  */
+
+static int
+parse_neon_mov (char **str, int *which_operand)
+{
+  int i = *which_operand, val;
+  enum arm_reg_type rtype;
+  char *ptr = *str;
+  struct neon_type_el optype;
+  
+  if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
+    {
+      /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>.  */
+      inst.operands[i].reg = val;
+      inst.operands[i].isscalar = 1;
+      inst.operands[i].vectype = optype;
+      inst.operands[i++].present = 1;
+
+      if (skip_past_comma (&ptr) == FAIL)
+        goto wanted_comma;
+      
+      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
+        goto wanted_arm;
+      
+      inst.operands[i].reg = val;
+      inst.operands[i].isreg = 1;
+      inst.operands[i].present = 1;
+    }
+  else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
+           != FAIL)
+    {
+      /* Cases 0, 1, 2, 3, 5 (D only).  */
+      if (skip_past_comma (&ptr) == FAIL)
+        goto wanted_comma;
+      
+      inst.operands[i].reg = val;
+      inst.operands[i].isreg = 1;
+      inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
+      inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
+      inst.operands[i].isvec = 1;
+      inst.operands[i].vectype = optype;
+      inst.operands[i++].present = 1;
+
+      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
+        {
+          /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
+             Case 13: VMOV <Sd>, <Rm>  */
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i].present = 1;
+
+          if (rtype == REG_TYPE_NQ)
+            {
+              first_error (_("can't use Neon quad register here"));
+              return FAIL;
+            }
+          else if (rtype != REG_TYPE_VFS)
+            {
+              i++;
+              if (skip_past_comma (&ptr) == FAIL)
+                goto wanted_comma;
+              if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
+                goto wanted_arm;
+              inst.operands[i].reg = val;
+              inst.operands[i].isreg = 1;
+              inst.operands[i].present = 1;
+            }
+        }
+      else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
+          /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
+             Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
+             Case 10: VMOV.F32 <Sd>, #<imm>
+             Case 11: VMOV.F64 <Dd>, #<imm>  */
+        inst.operands[i].immisfloat = 1;
+      else if (parse_big_immediate (&ptr, i) == SUCCESS)
+          /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
+             Case 3: VMOV<c><q>.<dt> <Dd>, #<imm>  */
+        ;
+      else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
+                                           &optype)) != FAIL)
+        {
+          /* Case 0: VMOV<c><q> <Qd>, <Qm>
+             Case 1: VMOV<c><q> <Dd>, <Dm>
+             Case 8: VMOV.F32 <Sd>, <Sm>
+             Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm>  */
+
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
+          inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
+          inst.operands[i].isvec = 1;
+          inst.operands[i].vectype = optype;
+          inst.operands[i].present = 1;
+          
+          if (skip_past_comma (&ptr) == SUCCESS)
+            {
+              /* Case 15.  */
+              i++;
+
+              if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
+                goto wanted_arm;
+
+              inst.operands[i].reg = val;
+              inst.operands[i].isreg = 1;
+              inst.operands[i++].present = 1;
+              
+              if (skip_past_comma (&ptr) == FAIL)
+                goto wanted_comma;
+              
+              if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
+                goto wanted_arm;
+              
+              inst.operands[i].reg = val;
+              inst.operands[i].isreg = 1;
+              inst.operands[i++].present = 1;
+            }
+        }
+      else
+        {
+          first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
+          return FAIL;
+        }
+    }
+  else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
+    {
+      /* Cases 6, 7.  */
+      inst.operands[i].reg = val;
+      inst.operands[i].isreg = 1;
+      inst.operands[i++].present = 1;
+      
+      if (skip_past_comma (&ptr) == FAIL)
+        goto wanted_comma;
+      
+      if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
+        {
+          /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]>  */
+          inst.operands[i].reg = val;
+          inst.operands[i].isscalar = 1;
+          inst.operands[i].present = 1;
+          inst.operands[i].vectype = optype;
+        }
+      else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
+        {
+          /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm>  */
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i++].present = 1;
+          
+          if (skip_past_comma (&ptr) == FAIL)
+            goto wanted_comma;
+          
+          if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
+              == FAIL)
+            {
+              first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
+              return FAIL;
+            }
+
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i].isvec = 1;
+          inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
+          inst.operands[i].vectype = optype;
+          inst.operands[i].present = 1;
+          
+          if (rtype == REG_TYPE_VFS)
+            {
+              /* Case 14.  */
+              i++;
+              if (skip_past_comma (&ptr) == FAIL)
+                goto wanted_comma;
+              if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
+                                              &optype)) == FAIL)
+                {
+                  first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
+                  return FAIL;
+                }
+              inst.operands[i].reg = val;
+              inst.operands[i].isreg = 1;
+              inst.operands[i].isvec = 1;
+              inst.operands[i].issingle = 1;
+              inst.operands[i].vectype = optype;
+              inst.operands[i].present = 1;
+            }
+        }
+      else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
+               != FAIL)
+        {
+          /* Case 13.  */
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i].isvec = 1;
+          inst.operands[i].issingle = 1;
+          inst.operands[i].vectype = optype;
+          inst.operands[i++].present = 1;
+        }
+    }
+  else
+    {
+      first_error (_("parse error"));
+      return FAIL;
+    }
+
+  /* Successfully parsed the operands. Update args.  */
+  *which_operand = i;
+  *str = ptr;
+  return SUCCESS;
+
+  wanted_comma:
+  first_error (_("expected comma"));
+  return FAIL;
+  
+  wanted_arm:
+  first_error (_(reg_expected_msgs[REG_TYPE_RN]));
+  return FAIL;
+}
+
 /* Matcher codes for parse_operands.  */
 enum operand_parse_code
 {
@@ -3765,7 +5319,13 @@ enum operand_parse_code
   OP_RCN,	/* Coprocessor register */
   OP_RF,	/* FPA register */
   OP_RVS,	/* VFP single precision register */
-  OP_RVD,	/* VFP double precision register */
+  OP_RVD,	/* VFP double precision register (0..15) */
+  OP_RND,       /* Neon double precision register (0..31) */
+  OP_RNQ,	/* Neon quad precision register */
+  OP_RVSD,	/* VFP single or double precision register */
+  OP_RNDQ,      /* Neon double or quad precision register */
+  OP_RNSDQ,	/* Neon single, double or quad precision register */
+  OP_RNSC,      /* Neon scalar D[X] */
   OP_RVC,	/* VFP control register */
   OP_RMF,	/* Maverick F register */
   OP_RMD,	/* Maverick D register */
@@ -3781,16 +5341,36 @@ enum operand_parse_code
   OP_REGLST,	/* ARM register list */
   OP_VRSLST,	/* VFP single-precision register list */
   OP_VRDLST,	/* VFP double-precision register list */
-
+  OP_VRSDLST,   /* VFP single or double-precision register list (& quad) */
+  OP_NRDLST,    /* Neon double-precision register list (d0-d31, qN aliases) */
+  OP_NSTRLST,   /* Neon element/structure list */
+
+  OP_NILO,      /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...)  */
+  OP_RNDQ_I0,   /* Neon D or Q reg, or immediate zero.  */
+  OP_RVSD_I0,	/* VFP S or D reg, or immediate zero.  */
+  OP_RR_RNSC,   /* ARM reg or Neon scalar.  */
+  OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar.  */
+  OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar.  */
+  OP_RND_RNSC,  /* Neon D reg, or Neon scalar.  */
+  OP_VMOV,      /* Neon VMOV operands.  */
+  OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN.  */
+  OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift.  */
+  OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2.  */
+
+  OP_I0,        /* immediate zero */
   OP_I7,	/* immediate value 0 .. 7 */
   OP_I15,	/*		   0 .. 15 */
   OP_I16,	/*		   1 .. 16 */
+  OP_I16z,      /*                 0 .. 16 */
   OP_I31,	/*		   0 .. 31 */
   OP_I31w,	/*		   0 .. 31, optional trailing ! */
   OP_I32,	/*		   1 .. 32 */
+  OP_I32z,	/*		   0 .. 32 */
+  OP_I63,	/*		   0 .. 63 */
   OP_I63s,	/*		 -64 .. 63 */
+  OP_I64,	/*		   1 .. 64 */
+  OP_I64z,	/*		   0 .. 64 */
   OP_I255,	/*		   0 .. 255 */
-  OP_Iffff,	/*		   0 .. 65535 */
 
   OP_I4b,	/* immediate, prefix optional, 1 .. 4 */
   OP_I7b,	/*			       0 .. 7 */
@@ -3798,10 +5378,15 @@ enum operand_parse_code
   OP_I31b,	/*			       0 .. 31 */
 
   OP_SH,	/* shifter operand */
+  OP_SHG,	/* shifter operand with possible group relocation */
   OP_ADDR,	/* Memory address expression (any mode) */
+  OP_ADDRGLDR,	/* Mem addr expr (any mode) with possible LDR group reloc */
+  OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
+  OP_ADDRGLDC,  /* Mem addr expr (any mode) with possible LDC group reloc */
   OP_EXP,	/* arbitrary expression */
   OP_EXPi,	/* same, with optional immediate prefix */
   OP_EXPr,	/* same, with optional relocation suffix */
+  OP_HALF,	/* 0 .. 65535 or low/high reloc.  */
 
   OP_CPSF,	/* CPS flags */
   OP_ENDI,	/* Endianness specifier */
@@ -3809,20 +5394,30 @@ enum operand_parse_code
   OP_COND,	/* conditional code */
   OP_TB,	/* Table branch.  */
 
+  OP_RVC_PSR,	/* CPSR/SPSR mask for msr, or VFP control register.  */
+  OP_APSR_RR,   /* ARM register or "APSR_nzcv".  */
+
   OP_RRnpc_I0,	/* ARM register or literal 0 */
   OP_RR_EXr,	/* ARM register or expression with opt. reloc suff. */
   OP_RR_EXi,	/* ARM register or expression with imm prefix */
   OP_RF_IF,	/* FPA register or immediate */
   OP_RIWR_RIWC, /* iWMMXt R or C reg */
+  OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
 
   /* Optional operands.	 */
   OP_oI7b,	 /* immediate, prefix optional, 0 .. 7 */
   OP_oI31b,	 /*				0 .. 31 */
+  OP_oI32b,      /*                             1 .. 32 */
   OP_oIffffb,	 /*				0 .. 65535 */
   OP_oI255c,	 /*	  curly-brace enclosed, 0 .. 255 */
 
   OP_oRR,	 /* ARM register */
   OP_oRRnpc,	 /* ARM register, not the PC */
+  OP_oRRw,	 /* ARM register, not r15, optional trailing ! */
+  OP_oRND,       /* Optional Neon double precision register */
+  OP_oRNQ,       /* Optional Neon quad precision register */
+  OP_oRNDQ,      /* Optional Neon double or quad precision register */
+  OP_oRNSDQ,	 /* Optional single, double or quad precision vector register */
   OP_oSHll,	 /* LSL immediate */
   OP_oSHar,	 /* ASR immediate */
   OP_oSHllar,	 /* LSL or ASR immediate */
@@ -3843,30 +5438,44 @@ parse_operands (char *str, const unsigned char *pattern)
   char *backtrack_pos = 0;
   const char *backtrack_error = 0;
   int i, val, backtrack_index = 0;
+  enum arm_reg_type rtype;
+  parse_operand_result result;
 
 #define po_char_or_fail(chr) do {		\
   if (skip_past_char (&str, chr) == FAIL)	\
     goto bad_args;				\
 } while (0)
 
-#define po_reg_or_fail(regtype) do {			\
-  val = arm_reg_parse (&str, regtype);			\
-  if (val == FAIL)					\
-    {							\
-      inst.error = _(reg_expected_msgs[regtype]);	\
-      goto failure;					\
-    }							\
-  inst.operands[i].reg = val;				\
-  inst.operands[i].isreg = 1;				\
+#define po_reg_or_fail(regtype) do {				\
+  val = arm_typed_reg_parse (&str, regtype, &rtype,		\
+  			     &inst.operands[i].vectype);	\
+  if (val == FAIL)						\
+    {								\
+      first_error (_(reg_expected_msgs[regtype]));		\
+      goto failure;						\
+    }								\
+  inst.operands[i].reg = val;					\
+  inst.operands[i].isreg = 1;					\
+  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\
+  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);		\
+  inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\
+                            || rtype == REG_TYPE_VFD		\
+                            || rtype == REG_TYPE_NQ);		\
 } while (0)
 
-#define po_reg_or_goto(regtype, label) do {	\
-  val = arm_reg_parse (&str, regtype);		\
-  if (val == FAIL)				\
-    goto label;					\
-						\
-  inst.operands[i].reg = val;			\
-  inst.operands[i].isreg = 1;			\
+#define po_reg_or_goto(regtype, label) do {			\
+  val = arm_typed_reg_parse (&str, regtype, &rtype,		\
+                             &inst.operands[i].vectype);	\
+  if (val == FAIL)						\
+    goto label;							\
+								\
+  inst.operands[i].reg = val;					\
+  inst.operands[i].isreg = 1;					\
+  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\
+  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);		\
+  inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\
+                            || rtype == REG_TYPE_VFD		\
+                            || rtype == REG_TYPE_NQ);		\
 } while (0)
 
 #define po_imm_or_fail(min, max, popt) do {			\
@@ -3875,11 +5484,27 @@ parse_operands (char *str, const unsigned char *pattern)
   inst.operands[i].imm = val;					\
 } while (0)
 
+#define po_scalar_or_goto(elsz, label) do {			\
+  val = parse_scalar (&str, elsz, &inst.operands[i].vectype);	\
+  if (val == FAIL)						\
+    goto label;							\
+  inst.operands[i].reg = val;					\
+  inst.operands[i].isscalar = 1;				\
+} while (0)
+
 #define po_misc_or_fail(expr) do {		\
   if (expr)					\
     goto failure;				\
 } while (0)
 
+#define po_misc_or_fail_no_backtrack(expr) do {	\
+  result = expr;				\
+  if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
+    backtrack_pos = 0;				\
+  if (result != PARSE_OPERAND_SUCCESS)		\
+    goto failure;				\
+} while (0)
+
   skip_whitespace (str);
 
   for (i = 0; upat[i] != OP_stop; i++)
@@ -3893,7 +5518,7 @@ parse_operands (char *str, const unsigned char *pattern)
 	  backtrack_index = i;
 	}
 
-      if (i > 0)
+      if (i > 0 && (i > 1 || inst.operands[0].present))
 	po_char_or_fail (',');
 
       switch (upat[i])
@@ -3908,7 +5533,15 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_RF:    po_reg_or_fail (REG_TYPE_FN);	  break;
 	case OP_RVS:   po_reg_or_fail (REG_TYPE_VFS);	  break;
 	case OP_RVD:   po_reg_or_fail (REG_TYPE_VFD);	  break;
-	case OP_RVC:   po_reg_or_fail (REG_TYPE_VFC);	  break;
+        case OP_oRND:
+	case OP_RND:   po_reg_or_fail (REG_TYPE_VFD);	  break;
+	case OP_RVC:
+	  po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
+	  break;
+	  /* Also accept generic coprocessor regs for unknown registers.  */
+	  coproc_reg:
+	  po_reg_or_fail (REG_TYPE_CN);
+	  break;
 	case OP_RMF:   po_reg_or_fail (REG_TYPE_MVF);	  break;
 	case OP_RMD:   po_reg_or_fail (REG_TYPE_MVD);	  break;
 	case OP_RMFX:  po_reg_or_fail (REG_TYPE_MVFX);	  break;
@@ -3919,6 +5552,126 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_RIWC:  po_reg_or_fail (REG_TYPE_MMXWC);	  break;
 	case OP_RIWG:  po_reg_or_fail (REG_TYPE_MMXWCG);  break;
 	case OP_RXA:   po_reg_or_fail (REG_TYPE_XSCALE);  break;
+        case OP_oRNQ:
+	case OP_RNQ:   po_reg_or_fail (REG_TYPE_NQ);      break;
+        case OP_oRNDQ:
+	case OP_RNDQ:  po_reg_or_fail (REG_TYPE_NDQ);     break;
+        case OP_RVSD:  po_reg_or_fail (REG_TYPE_VFSD);    break;
+        case OP_oRNSDQ:
+        case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ);    break;
+
+        /* Neon scalar. Using an element size of 8 means that some invalid
+           scalars are accepted here, so deal with those in later code.  */
+        case OP_RNSC:  po_scalar_or_goto (8, failure);    break;
+
+        /* WARNING: We can expand to two operands here. This has the potential
+           to totally confuse the backtracking mechanism! It will be OK at
+           least as long as we don't try to use optional args as well,
+           though.  */
+        case OP_NILO:
+          {
+            po_reg_or_goto (REG_TYPE_NDQ, try_imm);
+	    inst.operands[i].present = 1;
+            i++;
+            skip_past_comma (&str);
+            po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
+            break;
+            one_reg_only:
+            /* Optional register operand was omitted. Unfortunately, it's in
+               operands[i-1] and we need it to be in inst.operands[i]. Fix that
+               here (this is a bit grotty).  */
+            inst.operands[i] = inst.operands[i-1];
+            inst.operands[i-1].present = 0;
+            break;
+            try_imm:
+	    /* There's a possibility of getting a 64-bit immediate here, so
+	       we need special handling.  */
+	    if (parse_big_immediate (&str, i) == FAIL)
+	      {
+		inst.error = _("immediate value is out of range");
+		goto failure;
+	      }
+          }
+          break;
+
+        case OP_RNDQ_I0:
+          {
+            po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
+            break;
+            try_imm0:
+            po_imm_or_fail (0, 0, TRUE);
+          }
+          break;
+
+        case OP_RVSD_I0:
+          po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
+          break;
+
+        case OP_RR_RNSC:
+          {
+            po_scalar_or_goto (8, try_rr);
+            break;
+            try_rr:
+            po_reg_or_fail (REG_TYPE_RN);
+          }
+          break;
+
+        case OP_RNSDQ_RNSC:
+          {
+            po_scalar_or_goto (8, try_nsdq);
+            break;
+            try_nsdq:
+            po_reg_or_fail (REG_TYPE_NSDQ);
+          }
+          break;
+
+        case OP_RNDQ_RNSC:
+          {
+            po_scalar_or_goto (8, try_ndq);
+            break;
+            try_ndq:
+            po_reg_or_fail (REG_TYPE_NDQ);
+          }
+          break;
+
+        case OP_RND_RNSC:
+          {
+            po_scalar_or_goto (8, try_vfd);
+            break;
+            try_vfd:
+            po_reg_or_fail (REG_TYPE_VFD);
+          }
+          break;
+
+        case OP_VMOV:
+          /* WARNING: parse_neon_mov can move the operand counter, i. If we're
+             not careful then bad things might happen.  */
+          po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
+          break;
+
+        case OP_RNDQ_IMVNb:
+          {
+            po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm);
+            break;
+            try_mvnimm:
+            /* There's a possibility of getting a 64-bit immediate here, so
+               we need special handling.  */
+            if (parse_big_immediate (&str, i) == FAIL)
+              {
+                inst.error = _("immediate value is out of range");
+                goto failure;
+              }
+          }
+          break;
+
+        case OP_RNDQ_I63b:
+          {
+            po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
+            break;
+            try_shimm:
+            po_imm_or_fail (0, 63, TRUE);
+          }
+          break;
 
 	case OP_RRnpcb:
 	  po_char_or_fail ('[');
@@ -3927,6 +5680,7 @@ parse_operands (char *str, const unsigned char *pattern)
 	  break;
 
 	case OP_RRw:
+	case OP_oRRw:
 	  po_reg_or_fail (REG_TYPE_RN);
 	  if (skip_past_char (&str, '!') == SUCCESS)
 	    inst.operands[i].writeback = 1;
@@ -3936,11 +5690,15 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_I7:	 po_imm_or_fail (  0,	   7, FALSE);	break;
 	case OP_I15:	 po_imm_or_fail (  0,	  15, FALSE);	break;
 	case OP_I16:	 po_imm_or_fail (  1,	  16, FALSE);	break;
+        case OP_I16z:	 po_imm_or_fail (  0,     16, FALSE);   break;
 	case OP_I31:	 po_imm_or_fail (  0,	  31, FALSE);	break;
 	case OP_I32:	 po_imm_or_fail (  1,	  32, FALSE);	break;
+        case OP_I32z:	 po_imm_or_fail (  0,     32, FALSE);   break;
 	case OP_I63s:	 po_imm_or_fail (-64,	  63, FALSE);	break;
+        case OP_I63:	 po_imm_or_fail (  0,     63, FALSE);   break;
+        case OP_I64:	 po_imm_or_fail (  1,     64, FALSE);   break;
+        case OP_I64z:	 po_imm_or_fail (  0,     64, FALSE);   break;
 	case OP_I255:	 po_imm_or_fail (  0,	 255, FALSE);	break;
-	case OP_Iffff:	 po_imm_or_fail (  0, 0xffff, FALSE);	break;
 
 	case OP_I4b:	 po_imm_or_fail (  1,	   4, TRUE);	break;
 	case OP_oI7b:
@@ -3948,6 +5706,7 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_I15b:	 po_imm_or_fail (  0,	  15, TRUE);	break;
 	case OP_oI31b:
 	case OP_I31b:	 po_imm_or_fail (  0,	  31, TRUE);	break;
+        case OP_oI32b:   po_imm_or_fail (  1,     32, TRUE);    break;
 	case OP_oIffffb: po_imm_or_fail (  0, 0xffff, TRUE);	break;
 
 	  /* Immediate variants */
@@ -4005,6 +5764,11 @@ parse_operands (char *str, const unsigned char *pattern)
 	    }
 	  break;
 
+	  /* Operand for MOVW or MOVT.  */
+	case OP_HALF:
+	  po_misc_or_fail (parse_half (&str));
+	  break;
+
 	  /* Register or expression */
 	case OP_RR_EXr:	  po_reg_or_goto (REG_TYPE_RN, EXPr); break;
 	case OP_RR_EXi:	  po_reg_or_goto (REG_TYPE_RN, EXPi); break;
@@ -4027,13 +5791,17 @@ parse_operands (char *str, const unsigned char *pattern)
 	  inst.operands[i].isreg = 1;
 	  break;
 
+	case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
+	I32z:		  po_imm_or_fail (0, 32, FALSE);	  break;
+
 	  /* Two kinds of register */
 	case OP_RIWR_RIWC:
 	  {
 	    struct reg_entry *rege = arm_reg_parse_multi (&str);
-	    if (rege->type != REG_TYPE_MMXWR
-		&& rege->type != REG_TYPE_MMXWC
-		&& rege->type != REG_TYPE_MMXWCG)
+	    if (!rege
+		|| (rege->type != REG_TYPE_MMXWR
+		    && rege->type != REG_TYPE_MMXWC
+		    && rege->type != REG_TYPE_MMXWCG))
 	      {
 		inst.error = _("iWMMXt data or control register expected");
 		goto failure;
@@ -4043,6 +5811,21 @@ parse_operands (char *str, const unsigned char *pattern)
 	  }
 	  break;
 
+	case OP_RIWC_RIWG:
+	  {
+	    struct reg_entry *rege = arm_reg_parse_multi (&str);
+	    if (!rege
+		|| (rege->type != REG_TYPE_MMXWC
+		    && rege->type != REG_TYPE_MMXWCG))
+	      {
+		inst.error = _("iWMMXt control register expected");
+		goto failure;
+	      }
+	    inst.operands[i].reg = rege->number;
+	    inst.operands[i].isreg = 1;
+	  }
+	  break;
+
 	  /* Misc */
 	case OP_CPSF:	 val = parse_cps_flags (&str);		break;
 	case OP_ENDI:	 val = parse_endian_specifier (&str);	break;
@@ -4051,6 +5834,41 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_COND:	 val = parse_cond (&str);		break;
 	case OP_oBARRIER:val = parse_barrier (&str);		break;
 
+        case OP_RVC_PSR:
+          po_reg_or_goto (REG_TYPE_VFC, try_psr);
+          inst.operands[i].isvec = 1;  /* Mark VFP control reg as vector.  */
+          break;
+          try_psr:
+          val = parse_psr (&str);
+          break;
+
+        case OP_APSR_RR:
+          po_reg_or_goto (REG_TYPE_RN, try_apsr);
+          break;
+          try_apsr:
+          /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
+             instruction).  */
+          if (strncasecmp (str, "APSR_", 5) == 0)
+            {
+              unsigned found = 0;
+              str += 5;
+              while (found < 15)
+                switch (*str++)
+                  {
+                  case 'c': found = (found & 1) ? 16 : found | 1; break;
+                  case 'n': found = (found & 2) ? 16 : found | 2; break;
+                  case 'z': found = (found & 4) ? 16 : found | 4; break;
+                  case 'v': found = (found & 8) ? 16 : found | 8; break;
+                  default: found = 16;
+                  }
+              if (found != 15)
+                goto failure;
+              inst.operands[i].isvec = 1;
+            }
+          else
+            goto failure;
+          break;
+
 	case OP_TB:
 	  po_misc_or_fail (parse_tb (&str));
 	  break;
@@ -4066,22 +5884,65 @@ parse_operands (char *str, const unsigned char *pattern)
 	  break;
 
 	case OP_VRSLST:
-	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
+	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
 	  break;
 
 	case OP_VRDLST:
-	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
+	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
 	  break;
 
+        case OP_VRSDLST:
+          /* Allow Q registers too.  */
+          val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
+                                    REGLIST_NEON_D);
+          if (val == FAIL)
+            {
+              inst.error = NULL;
+              val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
+                                        REGLIST_VFP_S);
+              inst.operands[i].issingle = 1;
+            }
+          break;
+
+        case OP_NRDLST:
+          val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
+                                    REGLIST_NEON_D);
+          break;
+
+	case OP_NSTRLST:
+          val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
+                                           &inst.operands[i].vectype);
+          break;
+
 	  /* Addressing modes */
 	case OP_ADDR:
 	  po_misc_or_fail (parse_address (&str, i));
 	  break;
 
+	case OP_ADDRGLDR:
+	  po_misc_or_fail_no_backtrack (
+            parse_address_group_reloc (&str, i, GROUP_LDR));
+	  break;
+
+	case OP_ADDRGLDRS:
+	  po_misc_or_fail_no_backtrack (
+            parse_address_group_reloc (&str, i, GROUP_LDRS));
+	  break;
+
+	case OP_ADDRGLDC:
+	  po_misc_or_fail_no_backtrack (
+            parse_address_group_reloc (&str, i, GROUP_LDC));
+	  break;
+
 	case OP_SH:
 	  po_misc_or_fail (parse_shifter_operand (&str, i));
 	  break;
 
+	case OP_SHG:
+	  po_misc_or_fail_no_backtrack (
+            parse_shifter_operand_group_reloc (&str, i));
+	  break;
+
 	case OP_oSHll:
 	  po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
 	  break;
@@ -4107,6 +5968,7 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_RRnpc:
 	case OP_RRnpcb:
 	case OP_RRw:
+	case OP_oRRw:
 	case OP_RRnpc_I0:
 	  if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
 	    inst.error = BAD_PC;
@@ -4116,11 +5978,15 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_ENDI:
 	case OP_oROR:
 	case OP_PSR:
+        case OP_RVC_PSR:
 	case OP_COND:
 	case OP_oBARRIER:
 	case OP_REGLST:
 	case OP_VRSLST:
 	case OP_VRDLST:
+        case OP_VRSDLST:
+        case OP_NRDLST:
+        case OP_NSTRLST:
 	  if (val == FAIL)
 	    goto failure;
 	  inst.operands[i].imm = val;
@@ -4178,6 +6044,7 @@ parse_operands (char *str, const unsigned char *pattern)
 #undef po_reg_or_fail
 #undef po_reg_or_goto
 #undef po_imm_or_fail
+#undef po_scalar_or_fail
 
 /* Shorthand macro for instruction encoding functions issuing errors.  */
 #define constraint(expr, err) do {		\
@@ -4236,11 +6103,30 @@ encode_thumb32_immediate (unsigned int val)
 
   return FAIL;
 }
-/* Encode a VFP SP register number into inst.instruction.  */
+/* Encode a VFP SP or DP register number into inst.instruction.  */
 
 static void
-encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
-{
+encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
+{
+  if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
+      && reg > 15)
+    {
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
+        {
+          if (thumb_mode)
+            ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
+                                    fpu_vfp_ext_v3);
+          else
+            ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
+                                    fpu_vfp_ext_v3);
+        }
+      else
+        {
+          first_error (_("D register out of range for selected VFP version"));
+          return;
+        }
+    }
+
   switch (pos)
     {
     case VFP_REG_Sd:
@@ -4255,6 +6141,18 @@ encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
       inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
       break;
 
+    case VFP_REG_Dd:
+      inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
+      break;
+    
+    case VFP_REG_Dn:
+      inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
+      break;
+    
+    case VFP_REG_Dm:
+      inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
+      break;
+
     default:
       abort ();
     }
@@ -4399,7 +6297,8 @@ encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
    into a coprocessor load/store instruction.  If wb_ok is false,
    reject use of writeback; if unind_ok is false, reject use of
    unindexed addressing.  If reloc_override is not 0, use it instead
-   of BFD_ARM_CP_OFF_IMM.  */
+   of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
+   (in which case it is preserved).  */
 
 static int
 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
@@ -4441,10 +6340,16 @@ encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
 
   if (reloc_override)
     inst.reloc.type = reloc_override;
-  else if (thumb_mode)
-    inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
-  else
-    inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
+  else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
+            || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
+           && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
+    {
+      if (thumb_mode)
+        inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
+      else
+        inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
+    }
+
   return SUCCESS;
 }
 
@@ -4570,7 +6475,7 @@ static void
 do_rd_rm_rn (void)
 {
   unsigned Rn = inst.operands[2].reg;
-  /* Enforce resutrictions on SWP instruction.  */
+  /* Enforce restrictions on SWP instruction.  */
   if ((inst.instruction & 0x0fbfffff) == 0x01000090)
     constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
 		_("Rn must not overlap other operands"));
@@ -4894,7 +6799,11 @@ static void
 do_cpsi (void)
 {
   inst.instruction |= inst.operands[0].imm << 6;
-  inst.instruction |= inst.operands[1].imm;
+  if (inst.operands[1].present)
+    {
+      inst.instruction |= CPSI_MMOD;
+      inst.instruction |= inst.operands[1].imm;
+    }
 }
 
 static void
@@ -5112,17 +7021,16 @@ do_lstc (void)
 static void
 do_mlas (void)
 {
-  /* This restriction does not apply to mls (nor to mla in v6, but
-     that's hard to detect at present).	 */
+  /* This restriction does not apply to mls (nor to mla in v6 or later).  */
   if (inst.operands[0].reg == inst.operands[1].reg
+      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
       && !(inst.instruction & 0x00400000))
-    as_tsktsk (_("rd and rm should be different in mla"));
+    as_tsktsk (_("Rd and Rm should be different in mla"));
 
   inst.instruction |= inst.operands[0].reg << 16;
   inst.instruction |= inst.operands[1].reg;
   inst.instruction |= inst.operands[2].reg << 8;
   inst.instruction |= inst.operands[3].reg << 12;
-
 }
 
 static void
@@ -5136,15 +7044,62 @@ do_mov (void)
 static void
 do_mov16 (void)
 {
+  bfd_vma imm;
+  bfd_boolean top;
+
+  top = (inst.instruction & 0x00400000) != 0;
+  constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
+	      _(":lower16: not allowed this instruction"));
+  constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
+	      _(":upper16: not allowed instruction"));
   inst.instruction |= inst.operands[0].reg << 12;
-  /* The value is in two pieces: 0:11, 16:19.  */
-  inst.instruction |= (inst.operands[1].imm & 0x00000fff);
-  inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
+  if (inst.reloc.type == BFD_RELOC_UNUSED)
+    {
+      imm = inst.reloc.exp.X_add_number;
+      /* The value is in two pieces: 0:11, 16:19.  */
+      inst.instruction |= (imm & 0x00000fff);
+      inst.instruction |= (imm & 0x0000f000) << 4;
+    }
+}
+
+static void do_vfp_nsyn_opcode (const char *);
+
+static int
+do_vfp_nsyn_mrs (void)
+{
+  if (inst.operands[0].isvec)
+    {
+      if (inst.operands[1].reg != 1)
+        first_error (_("operand 1 must be FPSCR"));
+      memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
+      memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
+      do_vfp_nsyn_opcode ("fmstat");
+    }
+  else if (inst.operands[1].isvec)
+    do_vfp_nsyn_opcode ("fmrx");
+  else
+    return FAIL;
+    
+  return SUCCESS;
+}
+
+static int
+do_vfp_nsyn_msr (void)
+{
+  if (inst.operands[0].isvec)
+    do_vfp_nsyn_opcode ("fmxr");
+  else
+    return FAIL;
+
+  return SUCCESS;
 }
 
 static void
 do_mrs (void)
 {
+  if (do_vfp_nsyn_mrs () == SUCCESS)
+    return;
+
   /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all.  */
   constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
 	      != (PSR_c|PSR_f),
@@ -5160,6 +7115,9 @@ do_mrs (void)
 static void
 do_msr (void)
 {
+  if (do_vfp_nsyn_msr () == SUCCESS)
+    return;
+
   inst.instruction |= inst.operands[0].imm;
   if (inst.operands[1].isreg)
     inst.instruction |= inst.operands[1].reg;
@@ -5180,8 +7138,9 @@ do_mul (void)
   inst.instruction |= inst.operands[1].reg;
   inst.instruction |= inst.operands[2].reg << 8;
 
-  if (inst.operands[0].reg == inst.operands[1].reg)
-    as_tsktsk (_("rd and rm should be different in mul"));
+  if (inst.operands[0].reg == inst.operands[1].reg
+      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
+    as_tsktsk (_("Rd and Rm should be different in mul"));
 }
 
 /* Long Multiply Parser
@@ -5447,13 +7406,25 @@ do_smul (void)
   inst.instruction |= inst.operands[2].reg << 8;
 }
 
-/* ARM V6 srs (argument parse).	 */
+/* ARM V6 srs (argument parse).  The variable fields in the encoding are
+   the same for both ARM and Thumb-2.  */
 
 static void
 do_srs (void)
 {
-  inst.instruction |= inst.operands[0].imm;
-  if (inst.operands[0].writeback)
+  int reg;
+
+  if (inst.operands[0].present)
+    {
+      reg = inst.operands[0].reg;
+      constraint (reg != 13, _("SRS base register must be r13"));
+    }
+  else
+    reg = 13;
+
+  inst.instruction |= reg << 16;
+  inst.instruction |= inst.operands[1].imm;
+  if (inst.operands[0].writeback || inst.operands[1].writeback)
     inst.instruction |= WRITE_BACK;
 }
 
@@ -5542,43 +7513,43 @@ do_sxth (void)
 static void
 do_vfp_sp_monadic (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
 }
 
 static void
 do_vfp_sp_dyadic (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
-  encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
+  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
 }
 
 static void
 do_vfp_sp_compare_z (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
 }
 
 static void
 do_vfp_dp_sp_cvt (void)
 {
-  inst.instruction |= inst.operands[0].reg << 12;
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
 }
 
 static void
 do_vfp_sp_dp_cvt (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
-  inst.instruction |= inst.operands[1].reg;
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
 }
 
 static void
 do_vfp_reg_from_sp (void)
 {
   inst.instruction |= inst.operands[0].reg << 12;
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
 }
 
 static void
@@ -5588,13 +7559,13 @@ do_vfp_reg2_from_sp2 (void)
 	      _("only two consecutive VFP SP registers allowed here"));
   inst.instruction |= inst.operands[0].reg << 12;
   inst.instruction |= inst.operands[1].reg << 16;
-  encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
 }
 
 static void
 do_vfp_sp_from_reg (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
   inst.instruction |= inst.operands[1].reg << 12;
 }
 
@@ -5603,7 +7574,7 @@ do_vfp_sp2_from_reg2 (void)
 {
   constraint (inst.operands[0].imm != 2,
 	      _("only two consecutive VFP SP registers allowed here"));
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
   inst.instruction |= inst.operands[1].reg << 12;
   inst.instruction |= inst.operands[2].reg << 16;
 }
@@ -5611,14 +7582,14 @@ do_vfp_sp2_from_reg2 (void)
 static void
 do_vfp_sp_ldst (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
   encode_arm_cp_address (1, FALSE, TRUE, 0);
 }
 
 static void
 do_vfp_dp_ldst (void)
 {
-  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
   encode_arm_cp_address (1, FALSE, TRUE, 0);
 }
 
@@ -5632,7 +7603,7 @@ vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
     constraint (ldstm_type != VFP_LDSTMIA,
 		_("this addressing mode requires base-register writeback"));
   inst.instruction |= inst.operands[0].reg << 16;
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
   inst.instruction |= inst.operands[1].imm;
 }
 
@@ -5648,7 +7619,7 @@ vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
 		_("this addressing mode requires base-register writeback"));
 
   inst.instruction |= inst.operands[0].reg << 16;
-  inst.instruction |= inst.operands[1].reg << 12;
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
 
   count = inst.operands[1].imm << 1;
   if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
@@ -5692,6 +7663,103 @@ do_vfp_xp_ldstmdb (void)
 {
   vfp_dp_ldstm (VFP_LDSTMDBX);
 }
+
+static void
+do_vfp_dp_rd_rm (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
+}
+
+static void
+do_vfp_dp_rn_rd (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
+}
+
+static void
+do_vfp_dp_rd_rn (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
+}
+
+static void
+do_vfp_dp_rd_rn_rm (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
+  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
+}
+
+static void
+do_vfp_dp_rd (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+}
+
+static void
+do_vfp_dp_rm_rd_rn (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
+}
+
+/* VFPv3 instructions.  */
+static void
+do_vfp_sp_const (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
+  inst.instruction |= (inst.operands[1].imm & 0x0f);
+}
+
+static void
+do_vfp_dp_const (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
+  inst.instruction |= (inst.operands[1].imm & 0x0f);
+}
+
+static void
+vfp_conv (int srcsize)
+{
+  unsigned immbits = srcsize - inst.operands[1].imm;
+  inst.instruction |= (immbits & 1) << 5;
+  inst.instruction |= (immbits >> 1);
+}
+
+static void
+do_vfp_sp_conv_16 (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  vfp_conv (16);
+}
+
+static void
+do_vfp_dp_conv_16 (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  vfp_conv (16);
+}
+
+static void
+do_vfp_sp_conv_32 (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  vfp_conv (32);
+}
+
+static void
+do_vfp_dp_conv_32 (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  vfp_conv (32);
+}
+
 
 /* FPA instructions.  Also in a logical order.	*/
 
@@ -5740,6 +7808,7 @@ do_fpa_ldmstm (void)
 
   encode_arm_cp_address (2, TRUE, TRUE, 0);
 }
+
 
 /* iWMMXt instructions: strictly in alphabetical order.	 */
 
@@ -5790,6 +7859,15 @@ do_iwmmxt_waligni (void)
 }
 
 static void
+do_iwmmxt_wmerge (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  inst.instruction |= inst.operands[3].imm << 21;
+}
+
+static void
 do_iwmmxt_wmov (void)
 {
   /* WMOV rD, rN is an alias for WOR rD, rN, rN.  */
@@ -5828,7 +7906,23 @@ static void
 do_iwmmxt_wldstd (void)
 {
   inst.instruction |= inst.operands[0].reg << 12;
-  encode_arm_cp_address (1, TRUE, FALSE, 0);
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
+      && inst.operands[1].immisreg)
+    {
+      inst.instruction &= ~0x1a000ff;
+      inst.instruction |= (0xf << 28);
+      if (inst.operands[1].preind)
+	inst.instruction |= PRE_INDEX;
+      if (!inst.operands[1].negative)
+	inst.instruction |= INDEX_UP;
+      if (inst.operands[1].writeback)
+	inst.instruction |= WRITE_BACK;
+      inst.instruction |= inst.operands[1].reg << 16;
+      inst.instruction |= inst.reloc.exp.X_add_number << 4;
+      inst.instruction |= inst.operands[1].imm;
+    }
+  else
+    encode_arm_cp_address (1, TRUE, FALSE, 0);
 }
 
 static void
@@ -5848,6 +7942,56 @@ do_iwmmxt_wzero (void)
   inst.instruction |= inst.operands[0].reg << 12;
   inst.instruction |= inst.operands[0].reg << 16;
 }
+
+static void
+do_iwmmxt_wrwrwr_or_imm5 (void)
+{
+  if (inst.operands[2].isreg)
+    do_rd_rn_rm ();
+  else {
+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
+		_("immediate operand requires iWMMXt2"));
+    do_rd_rn ();
+    if (inst.operands[2].imm == 0)
+      {
+	switch ((inst.instruction >> 20) & 0xf)
+	  {
+	  case 4:
+	  case 5:
+	  case 6:
+	  case 7: 
+	    /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16.  */
+	    inst.operands[2].imm = 16;
+	    inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
+	    break;
+	  case 8:
+	  case 9:
+	  case 10:
+	  case 11:
+	    /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32.  */
+	    inst.operands[2].imm = 32;
+	    inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
+	    break;
+	  case 12:
+	  case 13:
+	  case 14:
+	  case 15:
+	    {
+	      /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn.  */
+	      unsigned long wrn;
+	      wrn = (inst.instruction >> 16) & 0xf;
+	      inst.instruction &= 0xff0fff0f;
+	      inst.instruction |= wrn;
+	      /* Bail out here; the instruction is now assembled.  */
+	      return;
+	    }
+	  }
+      }
+    /* Map 32 -> 0, etc.  */
+    inst.operands[2].imm &= 0x1f;
+    inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
+  }
+}
 
 /* Cirrus Maverick instructions.  Simple 2-, 3-, and 4-register
    operations first, then control, shift, and load/store.  */
@@ -6082,7 +8226,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
   X(cpsie, b660, f3af8400),			\
   X(cpsid, b670, f3af8600),			\
   X(cpy,   4600, ea4f0000),			\
-  X(dec_sp,80dd, f1bd0d00),			\
+  X(dec_sp,80dd, f1ad0d00),			\
   X(eor,   4040, ea800000),			\
   X(eors,  4040, ea900000),			\
   X(inc_sp,00dd, f10d0d00),			\
@@ -6200,13 +8344,13 @@ do_t_add_sub (void)
 	narrow = (current_it_mask != 0);
       if (!inst.operands[2].isreg)
 	{
+	  int add;
+
+	  add = (inst.instruction == T_MNEM_add
+		 || inst.instruction == T_MNEM_adds);
 	  opcode = 0;
 	  if (inst.size_req != 4)
 	    {
-	      int add;
-
-	      add = (inst.instruction == T_MNEM_add
-		     || inst.instruction == T_MNEM_adds);
 	      /* Attempt to use a narrow opcode, with relaxation if
 	         appropriate.  */
 	      if (Rd == REG_SP && Rs == REG_SP && !flags)
@@ -6236,12 +8380,38 @@ do_t_add_sub (void)
 	  if (inst.size_req == 4
 	      || (inst.size_req != 2 && !opcode))
 	    {
-	      /* ??? Convert large immediates to addw/subw.  */
-	      inst.instruction = THUMB_OP32 (inst.instruction);
-	      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
-	      inst.instruction |= inst.operands[0].reg << 8;
-	      inst.instruction |= inst.operands[1].reg << 16;
-	      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	      if (Rd == REG_PC)
+		{
+		  constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
+			     _("only SUBS PC, LR, #const allowed"));
+		  constraint (inst.reloc.exp.X_op != O_constant,
+			      _("expression too complex"));
+		  constraint (inst.reloc.exp.X_add_number < 0
+			      || inst.reloc.exp.X_add_number > 0xff,
+			     _("immediate value out of range"));
+		  inst.instruction = T2_SUBS_PC_LR
+				     | inst.reloc.exp.X_add_number;
+		  inst.reloc.type = BFD_RELOC_UNUSED;
+		  return;
+		}
+	      else if (Rs == REG_PC)
+		{
+		  /* Always use addw/subw.  */
+		  inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
+		  inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
+		}
+	      else
+		{
+		  inst.instruction = THUMB_OP32 (inst.instruction);
+		  inst.instruction = (inst.instruction & 0xe1ffffff)
+				     | 0x10000000;
+		  if (flags)
+		    inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+		  else
+		    inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
+		}
+	      inst.instruction |= Rd << 8;
+	      inst.instruction |= Rs << 16;
 	    }
 	}
       else
@@ -6807,7 +8977,7 @@ do_t_cpy (void)
 }
 
 static void
-do_t_czb (void)
+do_t_cbz (void)
 {
   constraint (current_it_mask, BAD_NOT_IT);
   constraint (inst.operands[0].reg > 7, BAD_HIREG);
@@ -6871,6 +9041,68 @@ do_t_it (void)
   inst.instruction |= cond << 4;
 }
 
+/* Helper function used for both push/pop and ldm/stm.  */
+static void
+encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
+{
+  bfd_boolean load;
+
+  load = (inst.instruction & (1 << 20)) != 0;
+
+  if (mask & (1 << 13))
+    inst.error =  _("SP not allowed in register list");
+  if (load)
+    {
+      if (mask & (1 << 14)
+	  && mask & (1 << 15))
+	inst.error = _("LR and PC should not both be in register list");
+
+      if ((mask & (1 << base)) != 0
+	  && writeback)
+	as_warn (_("base register should not be in register list "
+		   "when written back"));
+    }
+  else
+    {
+      if (mask & (1 << 15))
+	inst.error = _("PC not allowed in register list");
+
+      if (mask & (1 << base))
+	as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
+    }
+
+  if ((mask & (mask - 1)) == 0)
+    {
+      /* Single register transfers implemented as str/ldr.  */
+      if (writeback)
+	{
+	  if (inst.instruction & (1 << 23))
+	    inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
+	  else
+	    inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
+	}
+      else
+	{
+	  if (inst.instruction & (1 << 23))
+	    inst.instruction = 0x00800000; /* ia -> [base] */
+	  else
+	    inst.instruction = 0x00000c04; /* db -> [base, #-4] */
+	}
+
+      inst.instruction |= 0xf8400000;
+      if (load)
+	inst.instruction |= 0x00100000;
+
+      mask = ffs(mask) - 1;
+      mask <<= 12;
+    }
+  else if (writeback)
+    inst.instruction |= WRITE_BACK;
+
+  inst.instruction |= mask;
+  inst.instruction |= base << 16;
+}
+
 static void
 do_t_ldmstm (void)
 {
@@ -6882,60 +9114,60 @@ do_t_ldmstm (void)
 
   if (unified_syntax)
     {
+      bfd_boolean narrow;
+      unsigned mask;
+
+      narrow = FALSE;
       /* See if we can use a 16-bit instruction.  */
       if (inst.instruction < 0xffff /* not ldmdb/stmdb */
 	  && inst.size_req != 4
-	  && inst.operands[0].reg <= 7
-	  && !(inst.operands[1].imm & ~0xff)
-	  && (inst.instruction == T_MNEM_stmia
-	      ? inst.operands[0].writeback
-	      : (inst.operands[0].writeback
-		 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
-	{
-	  if (inst.instruction == T_MNEM_stmia
-	      && (inst.operands[1].imm & (1 << inst.operands[0].reg))
-	      && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
-	    as_warn (_("value stored for r%d is UNPREDICTABLE"),
-		     inst.operands[0].reg);
-
-	  inst.instruction = THUMB_OP16 (inst.instruction);
-	  inst.instruction |= inst.operands[0].reg << 8;
-	  inst.instruction |= inst.operands[1].imm;
-	}
-      else
+	  && !(inst.operands[1].imm & ~0xff))
 	{
-	  if (inst.operands[1].imm & (1 << 13))
-	    as_warn (_("SP should not be in register list"));
-	  if (inst.instruction == T_MNEM_stmia)
+	  mask = 1 << inst.operands[0].reg;
+
+	  if (inst.operands[0].reg <= 7
+	      && (inst.instruction == T_MNEM_stmia
+		  ? inst.operands[0].writeback
+		  : (inst.operands[0].writeback
+		     == !(inst.operands[1].imm & mask))))
 	    {
-	      if (inst.operands[1].imm & (1 << 15))
-		as_warn (_("PC should not be in register list"));
-	      if (inst.operands[1].imm & (1 << inst.operands[0].reg))
+	      if (inst.instruction == T_MNEM_stmia
+		  && (inst.operands[1].imm & mask)
+		  && (inst.operands[1].imm & (mask - 1)))
 		as_warn (_("value stored for r%d is UNPREDICTABLE"),
 			 inst.operands[0].reg);
+
+	      inst.instruction = THUMB_OP16 (inst.instruction);
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      inst.instruction |= inst.operands[1].imm;
+	      narrow = TRUE;
 	    }
-	  else
+	  else if (inst.operands[0] .reg == REG_SP
+		   && inst.operands[0].writeback)
 	    {
-	      if (inst.operands[1].imm & (1 << 14)
-		  && inst.operands[1].imm & (1 << 15))
-		as_warn (_("LR and PC should not both be in register list"));
-	      if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
-		  && inst.operands[0].writeback)
-		as_warn (_("base register should not be in register list "
-			   "when written back"));
+	      inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
+					     ? T_MNEM_push : T_MNEM_pop);
+	      inst.instruction |= inst.operands[1].imm;
+	      narrow = TRUE;
 	    }
+	}
+
+      if (!narrow)
+	{
 	  if (inst.instruction < 0xffff)
 	    inst.instruction = THUMB_OP32 (inst.instruction);
-	  inst.instruction |= inst.operands[0].reg << 16;
-	  inst.instruction |= inst.operands[1].imm;
-	  if (inst.operands[0].writeback)
-	    inst.instruction |= WRITE_BACK;
+
+	  encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
+			       inst.operands[0].writeback);
 	}
     }
   else
     {
       constraint (inst.operands[0].reg > 7
 		  || (inst.operands[1].imm & ~0xff), BAD_HIREG);
+      constraint (inst.instruction != T_MNEM_ldmia
+		  && inst.instruction != T_MNEM_stmia,
+		  _("Thumb-2 instruction only valid in unified syntax"));
       if (inst.instruction == T_MNEM_stmia)
 	{
 	  if (!inst.operands[0].writeback)
@@ -7209,6 +9441,16 @@ do_t_mov_cmp (void)
 	  || inst.operands[1].shifted)
 	narrow = FALSE;
 
+      /* MOVS PC, LR is encoded as SUBS PC, LR, #0.  */
+      if (opcode == T_MNEM_movs && inst.operands[1].isreg
+	  && !inst.operands[1].shifted
+	  && inst.operands[0].reg == REG_PC
+	  && inst.operands[1].reg == REG_LR)
+	{
+	  inst.instruction = T2_SUBS_PC_LR;
+	  return;
+	}
+
       if (!inst.operands[1].isreg)
 	{
 	  /* Immediate operand.  */
@@ -7231,11 +9473,98 @@ do_t_mov_cmp (void)
 	      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
 	    }
 	}
+      else if (inst.operands[1].shifted && inst.operands[1].immisreg
+	       && (inst.instruction == T_MNEM_mov
+		   || inst.instruction == T_MNEM_movs))
+	{
+	  /* Register shifts are encoded as separate shift instructions.  */
+	  bfd_boolean flags = (inst.instruction == T_MNEM_movs);
+
+	  if (current_it_mask)
+	    narrow = !flags;
+	  else
+	    narrow = flags;
+
+	  if (inst.size_req == 4)
+	    narrow = FALSE;
+
+	  if (!low_regs || inst.operands[1].imm > 7)
+	    narrow = FALSE;
+
+	  if (inst.operands[0].reg != inst.operands[1].reg)
+	    narrow = FALSE;
+
+	  switch (inst.operands[1].shift_kind)
+	    {
+	    case SHIFT_LSL:
+	      opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
+	      break;
+	    case SHIFT_ASR:
+	      opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
+	      break;
+	    case SHIFT_LSR:
+	      opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
+	      break;
+	    case SHIFT_ROR:
+	      opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
+	      break;
+	    default:
+	      abort();
+	    }
+
+	  inst.instruction = opcode;
+	  if (narrow)
+	    {
+	      inst.instruction |= inst.operands[0].reg;
+	      inst.instruction |= inst.operands[1].imm << 3;
+	    }
+	  else
+	    {
+	      if (flags)
+		inst.instruction |= CONDS_BIT;
+
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      inst.instruction |= inst.operands[1].reg << 16;
+	      inst.instruction |= inst.operands[1].imm;
+	    }
+	}
       else if (!narrow)
 	{
-	  inst.instruction = THUMB_OP32 (inst.instruction);
-	  inst.instruction |= inst.operands[0].reg << r0off;
-	  encode_thumb32_shifted_operand (1);
+	  /* Some mov with immediate shift have narrow variants.
+	     Register shifts are handled above.  */
+	  if (low_regs && inst.operands[1].shifted
+	      && (inst.instruction == T_MNEM_mov
+		  || inst.instruction == T_MNEM_movs))
+	    {
+	      if (current_it_mask)
+		narrow = (inst.instruction == T_MNEM_mov);
+	      else
+		narrow = (inst.instruction == T_MNEM_movs);
+	    }
+
+	  if (narrow)
+	    {
+	      switch (inst.operands[1].shift_kind)
+		{
+		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
+		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
+		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
+		default: narrow = FALSE; break;
+		}
+	    }
+
+	  if (narrow)
+	    {
+	      inst.instruction |= inst.operands[0].reg;
+	      inst.instruction |= inst.operands[1].reg << 3;
+	      inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
+	    }
+	  else
+	    {
+	      inst.instruction = THUMB_OP32 (inst.instruction);
+	      inst.instruction |= inst.operands[0].reg << r0off;
+	      encode_thumb32_shifted_operand (1);
+	    }
 	}
       else
 	switch (inst.instruction)
@@ -7310,11 +9639,30 @@ do_t_mov_cmp (void)
 static void
 do_t_mov16 (void)
 {
+  bfd_vma imm;
+  bfd_boolean top;
+
+  top = (inst.instruction & 0x00800000) != 0;
+  if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
+    {
+      constraint (top, _(":lower16: not allowed this instruction"));
+      inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
+    }
+  else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
+    {
+      constraint (!top, _(":upper16: not allowed this instruction"));
+      inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
+    }
+
   inst.instruction |= inst.operands[0].reg << 8;
-  inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
-  inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
-  inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
-  inst.instruction |= (inst.operands[1].imm & 0x00ff);
+  if (inst.reloc.type == BFD_RELOC_UNUSED)
+    {
+      imm = inst.reloc.exp.X_add_number;
+      inst.instruction |= (imm & 0xf000) << 4;
+      inst.instruction |= (imm & 0x0800) << 15;
+      inst.instruction |= (imm & 0x0700) << 4;
+      inst.instruction |= (imm & 0x00ff);
+    }
 }
 
 static void
@@ -7388,6 +9736,10 @@ static void
 do_t_mrs (void)
 {
   int flags;
+
+  if (do_vfp_nsyn_mrs () == SUCCESS)
+    return;
+
   flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
   if (flags == 0)
     {
@@ -7415,6 +9767,9 @@ do_t_msr (void)
 {
   int flags;
 
+  if (do_vfp_nsyn_msr () == SUCCESS)
+    return;
+
   constraint (!inst.operands[1].isreg,
 	      _("Thumb encoding does not support an immediate here"));
   flags = inst.operands[0].imm;
@@ -7589,7 +9944,7 @@ do_t_push_pop (void)
 
   mask = inst.operands[0].imm;
   if ((mask & ~0xff) == 0)
-    inst.instruction = THUMB_OP16 (inst.instruction);
+    inst.instruction = THUMB_OP16 (inst.instruction) | mask;
   else if ((inst.instruction == T_MNEM_push
 	    && (mask & ~0xff) == 1 << REG_LR)
 	   || (inst.instruction == T_MNEM_pop
@@ -7597,43 +9952,18 @@ do_t_push_pop (void)
     {
       inst.instruction = THUMB_OP16 (inst.instruction);
       inst.instruction |= THUMB_PP_PC_LR;
-      mask &= 0xff;
+      inst.instruction |= mask & 0xff;
     }
   else if (unified_syntax)
     {
-      if (mask & (1 << 13))
-	inst.error =  _("SP not allowed in register list");
-      if (inst.instruction == T_MNEM_push)
-	{
-	  if (mask & (1 << 15))
-	    inst.error = _("PC not allowed in register list");
-	}
-      else
-	{
-	  if (mask & (1 << 14)
-	      && mask & (1 << 15))
-	    inst.error = _("LR and PC should not both be in register list");
-	}
-      if ((mask & (mask - 1)) == 0)
-	{
-	  /* Single register push/pop implemented as str/ldr.  */
-	  if (inst.instruction == T_MNEM_push)
-	    inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
-	  else
-	    inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
-	  mask = ffs(mask) - 1;
-	  mask <<= 12;
-	}
-      else
-	inst.instruction = THUMB_OP32 (inst.instruction);
+      inst.instruction = THUMB_OP32 (inst.instruction);
+      encode_thumb2_ldmstm(13, mask, TRUE);
     }
   else
     {
       inst.error = _("invalid register list to push/pop instruction");
       return;
     }
-
-  inst.instruction |= mask;
 }
 
 static void
@@ -7678,8 +10008,37 @@ do_t_rsb (void)
   inst.instruction |= Rs << 16;
   if (!inst.operands[2].isreg)
     {
-      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
-      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+      bfd_boolean narrow;
+
+      if ((inst.instruction & 0x00100000) != 0)
+	narrow = (current_it_mask == 0);
+      else
+	narrow = (current_it_mask != 0);
+
+      if (Rd > 7 || Rs > 7)
+	narrow = FALSE;
+
+      if (inst.size_req == 4 || !unified_syntax)
+	narrow = FALSE;
+
+      if (inst.reloc.exp.X_op != O_constant
+	  || inst.reloc.exp.X_add_number != 0)
+	narrow = FALSE;
+
+      /* Turn rsb #0 into 16-bit neg.  We should probably do this via
+         relaxation, but it doesn't seem worth the hassle.  */
+      if (narrow)
+	{
+	  inst.reloc.type = BFD_RELOC_UNUSED;
+	  inst.instruction = THUMB_OP16 (T_MNEM_negs);
+	  inst.instruction |= Rs << 3;
+	  inst.instruction |= Rd;
+	}
+      else
+	{
+	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
     }
   else
     encode_thumb32_shifted_operand (2);
@@ -7997,6 +10356,3387 @@ do_t_usat16 (void)
   inst.instruction |= inst.operands[1].imm;
   inst.instruction |= inst.operands[2].reg << 16;
 }
+
+/* Neon instruction encoder helpers.  */
+  
+/* Encodings for the different types for various Neon opcodes.  */
+
+/* An "invalid" code for the following tables.  */
+#define N_INV -1u
+
+struct neon_tab_entry
+{
+  unsigned integer;
+  unsigned float_or_poly;
+  unsigned scalar_or_imm;
+};
+  
+/* Map overloaded Neon opcodes to their respective encodings.  */
+#define NEON_ENC_TAB					\
+  X(vabd,	0x0000700, 0x1200d00, N_INV),		\
+  X(vmax,	0x0000600, 0x0000f00, N_INV),		\
+  X(vmin,	0x0000610, 0x0200f00, N_INV),		\
+  X(vpadd,	0x0000b10, 0x1000d00, N_INV),		\
+  X(vpmax,	0x0000a00, 0x1000f00, N_INV),		\
+  X(vpmin,	0x0000a10, 0x1200f00, N_INV),		\
+  X(vadd,	0x0000800, 0x0000d00, N_INV),		\
+  X(vsub,	0x1000800, 0x0200d00, N_INV),		\
+  X(vceq,	0x1000810, 0x0000e00, 0x1b10100),	\
+  X(vcge,	0x0000310, 0x1000e00, 0x1b10080),	\
+  X(vcgt,	0x0000300, 0x1200e00, 0x1b10000),	\
+  /* Register variants of the following two instructions are encoded as
+     vcge / vcgt with the operands reversed. */  	\
+  X(vclt,	0x0000300, 0x1200e00, 0x1b10200),	\
+  X(vcle,	0x0000310, 0x1000e00, 0x1b10180),	\
+  X(vmla,	0x0000900, 0x0000d10, 0x0800040),	\
+  X(vmls,	0x1000900, 0x0200d10, 0x0800440),	\
+  X(vmul,	0x0000910, 0x1000d10, 0x0800840),	\
+  X(vmull,	0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float.  */ \
+  X(vmlal,	0x0800800, N_INV,     0x0800240),	\
+  X(vmlsl,	0x0800a00, N_INV,     0x0800640),	\
+  X(vqdmlal,	0x0800900, N_INV,     0x0800340),	\
+  X(vqdmlsl,	0x0800b00, N_INV,     0x0800740),	\
+  X(vqdmull,	0x0800d00, N_INV,     0x0800b40),	\
+  X(vqdmulh,    0x0000b00, N_INV,     0x0800c40),	\
+  X(vqrdmulh,   0x1000b00, N_INV,     0x0800d40),	\
+  X(vshl,	0x0000400, N_INV,     0x0800510),	\
+  X(vqshl,	0x0000410, N_INV,     0x0800710),	\
+  X(vand,	0x0000110, N_INV,     0x0800030),	\
+  X(vbic,	0x0100110, N_INV,     0x0800030),	\
+  X(veor,	0x1000110, N_INV,     N_INV),		\
+  X(vorn,	0x0300110, N_INV,     0x0800010),	\
+  X(vorr,	0x0200110, N_INV,     0x0800010),	\
+  X(vmvn,	0x1b00580, N_INV,     0x0800030),	\
+  X(vshll,	0x1b20300, N_INV,     0x0800a10), /* max shift, immediate.  */ \
+  X(vcvt,       0x1b30600, N_INV,     0x0800e10), /* integer, fixed-point.  */ \
+  X(vdup,       0xe800b10, N_INV,     0x1b00c00), /* arm, scalar.  */ \
+  X(vld1,       0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup.  */ \
+  X(vst1,	0x0000000, 0x0800000, N_INV),		\
+  X(vld2,	0x0200100, 0x0a00100, 0x0a00d00),	\
+  X(vst2,	0x0000100, 0x0800100, N_INV),		\
+  X(vld3,	0x0200200, 0x0a00200, 0x0a00e00),	\
+  X(vst3,	0x0000200, 0x0800200, N_INV),		\
+  X(vld4,	0x0200300, 0x0a00300, 0x0a00f00),	\
+  X(vst4,	0x0000300, 0x0800300, N_INV),		\
+  X(vmovn,	0x1b20200, N_INV,     N_INV),		\
+  X(vtrn,	0x1b20080, N_INV,     N_INV),		\
+  X(vqmovn,	0x1b20200, N_INV,     N_INV),		\
+  X(vqmovun,	0x1b20240, N_INV,     N_INV),		\
+  X(vnmul,      0xe200a40, 0xe200b40, N_INV),		\
+  X(vnmla,      0xe000a40, 0xe000b40, N_INV),		\
+  X(vnmls,      0xe100a40, 0xe100b40, N_INV),		\
+  X(vcmp,	0xeb40a40, 0xeb40b40, N_INV),		\
+  X(vcmpz,	0xeb50a40, 0xeb50b40, N_INV),		\
+  X(vcmpe,	0xeb40ac0, 0xeb40bc0, N_INV),		\
+  X(vcmpez,     0xeb50ac0, 0xeb50bc0, N_INV)
+
+enum neon_opc
+{
+#define X(OPC,I,F,S) N_MNEM_##OPC
+NEON_ENC_TAB
+#undef X
+};
+
+static const struct neon_tab_entry neon_enc_tab[] =
+{
+#define X(OPC,I,F,S) { (I), (F), (S) }
+NEON_ENC_TAB
+#undef X
+};
+
+#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
+#define NEON_ENC_ARMREG(X)  (neon_enc_tab[(X) & 0x0fffffff].integer)
+#define NEON_ENC_POLY(X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
+#define NEON_ENC_FLOAT(X)   (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
+#define NEON_ENC_SCALAR(X)  (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
+#define NEON_ENC_IMMED(X)   (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
+#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
+#define NEON_ENC_LANE(X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
+#define NEON_ENC_DUP(X)     (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
+#define NEON_ENC_SINGLE(X) \
+  ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
+#define NEON_ENC_DOUBLE(X) \
+  ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
+
+/* Define shapes for instruction operands. The following mnemonic characters
+   are used in this table:
+
+     F - VFP S<n> register
+     D - Neon D<n> register
+     Q - Neon Q<n> register
+     I - Immediate
+     S - Scalar
+     R - ARM register
+     L - D<n> register list
+   
+   This table is used to generate various data:
+     - enumerations of the form NS_DDR to be used as arguments to
+       neon_select_shape.
+     - a table classifying shapes into single, double, quad, mixed.
+     - a table used to drive neon_select_shape.
+*/
+
+#define NEON_SHAPE_DEF			\
+  X(3, (D, D, D), DOUBLE),		\
+  X(3, (Q, Q, Q), QUAD),		\
+  X(3, (D, D, I), DOUBLE),		\
+  X(3, (Q, Q, I), QUAD),		\
+  X(3, (D, D, S), DOUBLE),		\
+  X(3, (Q, Q, S), QUAD),		\
+  X(2, (D, D), DOUBLE),			\
+  X(2, (Q, Q), QUAD),			\
+  X(2, (D, S), DOUBLE),			\
+  X(2, (Q, S), QUAD),			\
+  X(2, (D, R), DOUBLE),			\
+  X(2, (Q, R), QUAD),			\
+  X(2, (D, I), DOUBLE),			\
+  X(2, (Q, I), QUAD),			\
+  X(3, (D, L, D), DOUBLE),		\
+  X(2, (D, Q), MIXED),			\
+  X(2, (Q, D), MIXED),			\
+  X(3, (D, Q, I), MIXED),		\
+  X(3, (Q, D, I), MIXED),		\
+  X(3, (Q, D, D), MIXED),		\
+  X(3, (D, Q, Q), MIXED),		\
+  X(3, (Q, Q, D), MIXED),		\
+  X(3, (Q, D, S), MIXED),		\
+  X(3, (D, Q, S), MIXED),		\
+  X(4, (D, D, D, I), DOUBLE),		\
+  X(4, (Q, Q, Q, I), QUAD),		\
+  X(2, (F, F), SINGLE),			\
+  X(3, (F, F, F), SINGLE),		\
+  X(2, (F, I), SINGLE),			\
+  X(2, (F, D), MIXED),			\
+  X(2, (D, F), MIXED),			\
+  X(3, (F, F, I), MIXED),		\
+  X(4, (R, R, F, F), SINGLE),		\
+  X(4, (F, F, R, R), SINGLE),		\
+  X(3, (D, R, R), DOUBLE),		\
+  X(3, (R, R, D), DOUBLE),		\
+  X(2, (S, R), SINGLE),			\
+  X(2, (R, S), SINGLE),			\
+  X(2, (F, R), SINGLE),			\
+  X(2, (R, F), SINGLE)
+
+#define S2(A,B)		NS_##A##B
+#define S3(A,B,C)	NS_##A##B##C
+#define S4(A,B,C,D)	NS_##A##B##C##D
+
+#define X(N, L, C) S##N L
+
+enum neon_shape
+{
+  NEON_SHAPE_DEF,
+  NS_NULL
+};
+
+#undef X
+#undef S2
+#undef S3
+#undef S4
+
+enum neon_shape_class
+{
+  SC_SINGLE,
+  SC_DOUBLE,
+  SC_QUAD,
+  SC_MIXED
+};
+
+#define X(N, L, C) SC_##C
+
+static enum neon_shape_class neon_shape_class[] =
+{
+  NEON_SHAPE_DEF
+};
+
+#undef X
+
+enum neon_shape_el
+{
+  SE_F,
+  SE_D,
+  SE_Q,
+  SE_I,
+  SE_S,
+  SE_R,
+  SE_L
+};
+
+/* Register widths of above.  */
+static unsigned neon_shape_el_size[] =
+{
+  32,
+  64,
+  128,
+  0,
+  32,
+  32,
+  0
+};
+
+struct neon_shape_info
+{
+  unsigned els;
+  enum neon_shape_el el[NEON_MAX_TYPE_ELS];
+};
+
+#define S2(A,B)		{ SE_##A, SE_##B }
+#define S3(A,B,C)	{ SE_##A, SE_##B, SE_##C }
+#define S4(A,B,C,D)	{ SE_##A, SE_##B, SE_##C, SE_##D }
+
+#define X(N, L, C) { N, S##N L }
+
+static struct neon_shape_info neon_shape_tab[] =
+{
+  NEON_SHAPE_DEF
+};
+
+#undef X
+#undef S2
+#undef S3
+#undef S4
+
+/* Bit masks used in type checking given instructions.
+  'N_EQK' means the type must be the same as (or based on in some way) the key
+   type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
+   set, various other bits can be set as well in order to modify the meaning of
+   the type constraint.  */
+
+enum neon_type_mask
+{
+  N_S8   = 0x000001,
+  N_S16  = 0x000002,
+  N_S32  = 0x000004,
+  N_S64  = 0x000008,
+  N_U8   = 0x000010,
+  N_U16  = 0x000020,
+  N_U32  = 0x000040,
+  N_U64  = 0x000080,
+  N_I8   = 0x000100,
+  N_I16  = 0x000200,
+  N_I32  = 0x000400,
+  N_I64  = 0x000800,
+  N_8    = 0x001000,
+  N_16   = 0x002000,
+  N_32   = 0x004000,
+  N_64   = 0x008000,
+  N_P8   = 0x010000,
+  N_P16  = 0x020000,
+  N_F32  = 0x040000,
+  N_F64  = 0x080000,
+  N_KEY  = 0x100000, /* key element (main type specifier).  */
+  N_EQK  = 0x200000, /* given operand has the same type & size as the key.  */
+  N_VFP  = 0x400000, /* VFP mode: operand size must match register width.  */
+  N_DBL  = 0x000001, /* if N_EQK, this operand is twice the size.  */
+  N_HLF  = 0x000002, /* if N_EQK, this operand is half the size.  */
+  N_SGN  = 0x000004, /* if N_EQK, this operand is forced to be signed.  */
+  N_UNS  = 0x000008, /* if N_EQK, this operand is forced to be unsigned.  */
+  N_INT  = 0x000010, /* if N_EQK, this operand is forced to be integer.  */
+  N_FLT  = 0x000020, /* if N_EQK, this operand is forced to be float.  */
+  N_SIZ  = 0x000040, /* if N_EQK, this operand is forced to be size-only.  */
+  N_UTYP = 0,
+  N_MAX_NONSPECIAL = N_F64
+};
+
+#define N_ALLMODS  (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
+
+#define N_SU_ALL   (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
+#define N_SU_32    (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
+#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
+#define N_SUF_32   (N_SU_32 | N_F32)
+#define N_I_ALL    (N_I8 | N_I16 | N_I32 | N_I64)
+#define N_IF_32    (N_I8 | N_I16 | N_I32 | N_F32)
+
+/* Pass this as the first type argument to neon_check_type to ignore types
+   altogether.  */
+#define N_IGNORE_TYPE (N_KEY | N_EQK)
+
+/* Select a "shape" for the current instruction (describing register types or
+   sizes) from a list of alternatives. Return NS_NULL if the current instruction
+   doesn't fit. For non-polymorphic shapes, checking is usually done as a
+   function of operand parsing, so this function doesn't need to be called.
+   Shapes should be listed in order of decreasing length.  */
+
+static enum neon_shape
+neon_select_shape (enum neon_shape shape, ...)
+{
+  va_list ap;
+  enum neon_shape first_shape = shape;
+
+  /* Fix missing optional operands. FIXME: we don't know at this point how
+     many arguments we should have, so this makes the assumption that we have
+     > 1. This is true of all current Neon opcodes, I think, but may not be
+     true in the future.  */
+  if (!inst.operands[1].present)
+    inst.operands[1] = inst.operands[0];
+
+  va_start (ap, shape);
+  
+  for (; shape != NS_NULL; shape = va_arg (ap, int))
+    {
+      unsigned j;
+      int matches = 1;
+
+      for (j = 0; j < neon_shape_tab[shape].els; j++)
+        {
+          if (!inst.operands[j].present)
+            {
+              matches = 0;
+              break;
+            }
+
+          switch (neon_shape_tab[shape].el[j])
+            {
+            case SE_F:
+              if (!(inst.operands[j].isreg
+                    && inst.operands[j].isvec
+                    && inst.operands[j].issingle
+                    && !inst.operands[j].isquad))
+                matches = 0;
+              break;
+
+            case SE_D:
+              if (!(inst.operands[j].isreg
+                    && inst.operands[j].isvec
+                    && !inst.operands[j].isquad
+                    && !inst.operands[j].issingle))
+                matches = 0;
+              break;
+
+            case SE_R:
+              if (!(inst.operands[j].isreg
+                    && !inst.operands[j].isvec))
+                matches = 0;
+              break;
+
+            case SE_Q:
+              if (!(inst.operands[j].isreg
+                    && inst.operands[j].isvec
+                    && inst.operands[j].isquad
+                    && !inst.operands[j].issingle))
+                matches = 0;
+              break;
+
+            case SE_I:
+              if (!(!inst.operands[j].isreg
+                    && !inst.operands[j].isscalar))
+                matches = 0;
+              break;
+
+            case SE_S:
+              if (!(!inst.operands[j].isreg
+                    && inst.operands[j].isscalar))
+                matches = 0;
+              break;
+
+            case SE_L:
+              break;
+            }
+        }
+      if (matches)
+        break;
+    }
+  
+  va_end (ap);
+
+  if (shape == NS_NULL && first_shape != NS_NULL)
+    first_error (_("invalid instruction shape"));
+
+  return shape;
+}
+
+/* True if SHAPE is predominantly a quadword operation (most of the time, this
+   means the Q bit should be set).  */
+
+static int
+neon_quad (enum neon_shape shape)
+{
+  return neon_shape_class[shape] == SC_QUAD;
+}
+
+static void
+neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
+                       unsigned *g_size)
+{
+  /* Allow modification to be made to types which are constrained to be
+     based on the key element, based on bits set alongside N_EQK.  */
+  if ((typebits & N_EQK) != 0)
+    {
+      if ((typebits & N_HLF) != 0)
+	*g_size /= 2;
+      else if ((typebits & N_DBL) != 0)
+	*g_size *= 2;
+      if ((typebits & N_SGN) != 0)
+	*g_type = NT_signed;
+      else if ((typebits & N_UNS) != 0)
+        *g_type = NT_unsigned;
+      else if ((typebits & N_INT) != 0)
+        *g_type = NT_integer;
+      else if ((typebits & N_FLT) != 0)
+        *g_type = NT_float;
+      else if ((typebits & N_SIZ) != 0)
+        *g_type = NT_untyped;
+    }
+}
+  
+/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
+   operand type, i.e. the single type specified in a Neon instruction when it
+   is the only one given.  */
+
+static struct neon_type_el
+neon_type_promote (struct neon_type_el *key, unsigned thisarg)
+{
+  struct neon_type_el dest = *key;
+  
+  assert ((thisarg & N_EQK) != 0);
+  
+  neon_modify_type_size (thisarg, &dest.type, &dest.size);
+
+  return dest;
+}
+
+/* Convert Neon type and size into compact bitmask representation.  */
+
+static enum neon_type_mask
+type_chk_of_el_type (enum neon_el_type type, unsigned size)
+{
+  switch (type)
+    {
+    case NT_untyped:
+      switch (size)
+        {
+        case 8:  return N_8;
+        case 16: return N_16;
+        case 32: return N_32;
+        case 64: return N_64;
+        default: ;
+        }
+      break;
+
+    case NT_integer:
+      switch (size)
+        {
+        case 8:  return N_I8;
+        case 16: return N_I16;
+        case 32: return N_I32;
+        case 64: return N_I64;
+        default: ;
+        }
+      break;
+
+    case NT_float:
+      switch (size)
+        {
+        case 32: return N_F32;
+        case 64: return N_F64;
+        default: ;
+        }
+      break;
+
+    case NT_poly:
+      switch (size)
+        {
+        case 8:  return N_P8;
+        case 16: return N_P16;
+        default: ;
+        }
+      break;
+
+    case NT_signed:
+      switch (size)
+        {
+        case 8:  return N_S8;
+        case 16: return N_S16;
+        case 32: return N_S32;
+        case 64: return N_S64;
+        default: ;
+        }
+      break;
+
+    case NT_unsigned:
+      switch (size)
+        {
+        case 8:  return N_U8;
+        case 16: return N_U16;
+        case 32: return N_U32;
+        case 64: return N_U64;
+        default: ;
+        }
+      break;
+
+    default: ;
+    }
+  
+  return N_UTYP;
+}
+
+/* Convert compact Neon bitmask type representation to a type and size. Only
+   handles the case where a single bit is set in the mask.  */
+
+static int
+el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
+                     enum neon_type_mask mask)
+{
+  if ((mask & N_EQK) != 0)
+    return FAIL;
+
+  if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
+    *size = 8;
+  else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
+    *size = 16;
+  else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
+    *size = 32;
+  else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
+    *size = 64;
+  else
+    return FAIL;
+
+  if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
+    *type = NT_signed;
+  else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
+    *type = NT_unsigned;
+  else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
+    *type = NT_integer;
+  else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
+    *type = NT_untyped;
+  else if ((mask & (N_P8 | N_P16)) != 0)
+    *type = NT_poly;
+  else if ((mask & (N_F32 | N_F64)) != 0)
+    *type = NT_float;
+  else
+    return FAIL;
+  
+  return SUCCESS;
+}
+
+/* Modify a bitmask of allowed types. This is only needed for type
+   relaxation.  */
+
+static unsigned
+modify_types_allowed (unsigned allowed, unsigned mods)
+{
+  unsigned size;
+  enum neon_el_type type;
+  unsigned destmask;
+  int i;
+  
+  destmask = 0;
+  
+  for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
+    {
+      if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS)
+        {
+          neon_modify_type_size (mods, &type, &size);
+          destmask |= type_chk_of_el_type (type, size);
+        }
+    }
+  
+  return destmask;
+}
+
+/* Check type and return type classification.
+   The manual states (paraphrase): If one datatype is given, it indicates the
+   type given in:
+    - the second operand, if there is one
+    - the operand, if there is no second operand
+    - the result, if there are no operands.
+   This isn't quite good enough though, so we use a concept of a "key" datatype
+   which is set on a per-instruction basis, which is the one which matters when
+   only one data type is written.
+   Note: this function has side-effects (e.g. filling in missing operands). All
+   Neon instructions should call it before performing bit encoding.  */
+
+static struct neon_type_el
+neon_check_type (unsigned els, enum neon_shape ns, ...)
+{
+  va_list ap;
+  unsigned i, pass, key_el = 0;
+  unsigned types[NEON_MAX_TYPE_ELS];
+  enum neon_el_type k_type = NT_invtype;
+  unsigned k_size = -1u;
+  struct neon_type_el badtype = {NT_invtype, -1};
+  unsigned key_allowed = 0;
+
+  /* Optional registers in Neon instructions are always (not) in operand 1.
+     Fill in the missing operand here, if it was omitted.  */
+  if (els > 1 && !inst.operands[1].present)
+    inst.operands[1] = inst.operands[0];
+
+  /* Suck up all the varargs.  */
+  va_start (ap, ns);
+  for (i = 0; i < els; i++)
+    {
+      unsigned thisarg = va_arg (ap, unsigned);
+      if (thisarg == N_IGNORE_TYPE)
+        {
+          va_end (ap);
+          return badtype;
+        }
+      types[i] = thisarg;
+      if ((thisarg & N_KEY) != 0)
+        key_el = i;
+    }
+  va_end (ap);
+
+  if (inst.vectype.elems > 0)
+    for (i = 0; i < els; i++)
+      if (inst.operands[i].vectype.type != NT_invtype)
+        {
+          first_error (_("types specified in both the mnemonic and operands"));
+          return badtype;
+        }
+
+  /* Duplicate inst.vectype elements here as necessary.
+     FIXME: No idea if this is exactly the same as the ARM assembler,
+     particularly when an insn takes one register and one non-register
+     operand. */
+  if (inst.vectype.elems == 1 && els > 1)
+    {
+      unsigned j;
+      inst.vectype.elems = els;
+      inst.vectype.el[key_el] = inst.vectype.el[0];
+      for (j = 0; j < els; j++)
+        if (j != key_el)
+          inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
+                                                  types[j]);
+    }
+  else if (inst.vectype.elems == 0 && els > 0)
+    {
+      unsigned j;
+      /* No types were given after the mnemonic, so look for types specified
+         after each operand. We allow some flexibility here; as long as the
+         "key" operand has a type, we can infer the others.  */
+      for (j = 0; j < els; j++)
+        if (inst.operands[j].vectype.type != NT_invtype)
+          inst.vectype.el[j] = inst.operands[j].vectype;
+
+      if (inst.operands[key_el].vectype.type != NT_invtype)
+        {
+          for (j = 0; j < els; j++)
+            if (inst.operands[j].vectype.type == NT_invtype)
+              inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
+                                                      types[j]);
+        }
+      else
+        {
+          first_error (_("operand types can't be inferred"));
+          return badtype;
+        }
+    }
+  else if (inst.vectype.elems != els)
+    {
+      first_error (_("type specifier has the wrong number of parts"));
+      return badtype;
+    }
+
+  for (pass = 0; pass < 2; pass++)
+    {
+      for (i = 0; i < els; i++)
+        {
+          unsigned thisarg = types[i];
+          unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
+            ? modify_types_allowed (key_allowed, thisarg) : thisarg;
+          enum neon_el_type g_type = inst.vectype.el[i].type;
+          unsigned g_size = inst.vectype.el[i].size;
+
+          /* Decay more-specific signed & unsigned types to sign-insensitive
+	     integer types if sign-specific variants are unavailable.  */
+          if ((g_type == NT_signed || g_type == NT_unsigned)
+	      && (types_allowed & N_SU_ALL) == 0)
+	    g_type = NT_integer;
+
+          /* If only untyped args are allowed, decay any more specific types to
+	     them. Some instructions only care about signs for some element
+	     sizes, so handle that properly.  */
+          if ((g_size == 8 && (types_allowed & N_8) != 0)
+	      || (g_size == 16 && (types_allowed & N_16) != 0)
+	      || (g_size == 32 && (types_allowed & N_32) != 0)
+	      || (g_size == 64 && (types_allowed & N_64) != 0))
+	    g_type = NT_untyped;
+
+          if (pass == 0)
+            {
+              if ((thisarg & N_KEY) != 0)
+                {
+                  k_type = g_type;
+                  k_size = g_size;
+                  key_allowed = thisarg & ~N_KEY;
+                }
+            }
+          else
+            {
+              if ((thisarg & N_VFP) != 0)
+                {
+                  enum neon_shape_el regshape = neon_shape_tab[ns].el[i];
+                  unsigned regwidth = neon_shape_el_size[regshape], match;
+
+                  /* In VFP mode, operands must match register widths. If we
+                     have a key operand, use its width, else use the width of
+                     the current operand.  */
+                  if (k_size != -1u)
+                    match = k_size;
+                  else
+                    match = g_size;
+
+                  if (regwidth != match)
+                    {
+                      first_error (_("operand size must match register width"));
+                      return badtype;
+                    }
+                }
+            
+              if ((thisarg & N_EQK) == 0)
+                {
+                  unsigned given_type = type_chk_of_el_type (g_type, g_size);
+
+                  if ((given_type & types_allowed) == 0)
+                    {
+	              first_error (_("bad type in Neon instruction"));
+	              return badtype;
+                    }
+                }
+              else
+                {
+                  enum neon_el_type mod_k_type = k_type;
+                  unsigned mod_k_size = k_size;
+                  neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
+                  if (g_type != mod_k_type || g_size != mod_k_size)
+                    {
+                      first_error (_("inconsistent types in Neon instruction"));
+                      return badtype;
+                    }
+                }
+            }
+        }
+    }
+
+  return inst.vectype.el[key_el];
+}
+
+/* Neon-style VFP instruction forwarding.  */
+
+/* Thumb VFP instructions have 0xE in the condition field.  */
+
+static void
+do_vfp_cond_or_thumb (void)
+{
+  if (thumb_mode)
+    inst.instruction |= 0xe0000000;
+  else
+    inst.instruction |= inst.cond << 28;
+}
+
+/* Look up and encode a simple mnemonic, for use as a helper function for the
+   Neon-style VFP syntax.  This avoids duplication of bits of the insns table,
+   etc.  It is assumed that operand parsing has already been done, and that the
+   operands are in the form expected by the given opcode (this isn't necessarily
+   the same as the form in which they were parsed, hence some massaging must
+   take place before this function is called).
+   Checks current arch version against that in the looked-up opcode.  */
+
+static void
+do_vfp_nsyn_opcode (const char *opname)
+{
+  const struct asm_opcode *opcode;
+  
+  opcode = hash_find (arm_ops_hsh, opname);
+
+  if (!opcode)
+    abort ();
+
+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
+                thumb_mode ? *opcode->tvariant : *opcode->avariant),
+              _(BAD_FPU));
+
+  if (thumb_mode)
+    {
+      inst.instruction = opcode->tvalue;
+      opcode->tencode ();
+    }
+  else
+    {
+      inst.instruction = (inst.cond << 28) | opcode->avalue;
+      opcode->aencode ();
+    }
+}
+
+static void
+do_vfp_nsyn_add_sub (enum neon_shape rs)
+{
+  int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
+
+  if (rs == NS_FFF)
+    {
+      if (is_add)
+        do_vfp_nsyn_opcode ("fadds");
+      else
+        do_vfp_nsyn_opcode ("fsubs");
+    }
+  else
+    {
+      if (is_add)
+        do_vfp_nsyn_opcode ("faddd");
+      else
+        do_vfp_nsyn_opcode ("fsubd");
+    }
+}
+
+/* Check operand types to see if this is a VFP instruction, and if so call
+   PFN ().  */
+
+static int
+try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
+{
+  enum neon_shape rs;
+  struct neon_type_el et;
+
+  switch (args)
+    {
+    case 2:
+      rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
+      et = neon_check_type (2, rs,
+        N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      break;
+    
+    case 3:
+      rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
+      et = neon_check_type (3, rs,
+        N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      break;
+
+    default:
+      abort ();
+    }
+
+  if (et.type != NT_invtype)
+    {
+      pfn (rs);
+      return SUCCESS;
+    }
+  else
+    inst.error = NULL;
+
+  return FAIL;
+}
+
+static void
+do_vfp_nsyn_mla_mls (enum neon_shape rs)
+{
+  int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
+  
+  if (rs == NS_FFF)
+    {
+      if (is_mla)
+        do_vfp_nsyn_opcode ("fmacs");
+      else
+        do_vfp_nsyn_opcode ("fmscs");
+    }
+  else
+    {
+      if (is_mla)
+        do_vfp_nsyn_opcode ("fmacd");
+      else
+        do_vfp_nsyn_opcode ("fmscd");
+    }
+}
+
+static void
+do_vfp_nsyn_mul (enum neon_shape rs)
+{
+  if (rs == NS_FFF)
+    do_vfp_nsyn_opcode ("fmuls");
+  else
+    do_vfp_nsyn_opcode ("fmuld");
+}
+
+static void
+do_vfp_nsyn_abs_neg (enum neon_shape rs)
+{
+  int is_neg = (inst.instruction & 0x80) != 0;
+  neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
+
+  if (rs == NS_FF)
+    {
+      if (is_neg)
+        do_vfp_nsyn_opcode ("fnegs");
+      else
+        do_vfp_nsyn_opcode ("fabss");
+    }
+  else
+    {
+      if (is_neg)
+        do_vfp_nsyn_opcode ("fnegd");
+      else
+        do_vfp_nsyn_opcode ("fabsd");
+    }
+}
+
+/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
+   insns belong to Neon, and are handled elsewhere.  */
+
+static void
+do_vfp_nsyn_ldm_stm (int is_dbmode)
+{
+  int is_ldm = (inst.instruction & (1 << 20)) != 0;
+  if (is_ldm)
+    {
+      if (is_dbmode)
+        do_vfp_nsyn_opcode ("fldmdbs");
+      else
+        do_vfp_nsyn_opcode ("fldmias");
+    }
+  else
+    {
+      if (is_dbmode)
+        do_vfp_nsyn_opcode ("fstmdbs");
+      else
+        do_vfp_nsyn_opcode ("fstmias");
+    }
+}
+
+static void
+do_vfp_nsyn_sqrt (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
+  neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      
+  if (rs == NS_FF)
+    do_vfp_nsyn_opcode ("fsqrts");
+  else
+    do_vfp_nsyn_opcode ("fsqrtd");
+}
+
+static void
+do_vfp_nsyn_div (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
+  neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
+    N_F32 | N_F64 | N_KEY | N_VFP);
+  
+  if (rs == NS_FFF)
+    do_vfp_nsyn_opcode ("fdivs");
+  else
+    do_vfp_nsyn_opcode ("fdivd");
+}
+
+static void
+do_vfp_nsyn_nmul (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
+  neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
+    N_F32 | N_F64 | N_KEY | N_VFP);
+  
+  if (rs == NS_FFF)
+    {
+      inst.instruction = NEON_ENC_SINGLE (inst.instruction);
+      do_vfp_sp_dyadic ();
+    }
+  else
+    {
+      inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
+      do_vfp_dp_rd_rn_rm ();
+    }
+  do_vfp_cond_or_thumb ();
+}
+
+static void
+do_vfp_nsyn_cmp (void)
+{
+  if (inst.operands[1].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
+      neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      
+      if (rs == NS_FF)
+        {
+          inst.instruction = NEON_ENC_SINGLE (inst.instruction);
+          do_vfp_sp_monadic ();
+        }
+      else
+        {
+          inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
+          do_vfp_dp_rd_rm ();
+        }
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
+      neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
+
+      switch (inst.instruction & 0x0fffffff)
+        {
+        case N_MNEM_vcmp:
+          inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
+          break;
+        case N_MNEM_vcmpe:
+          inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
+          break;
+        default:
+          abort ();
+        }
+     
+      if (rs == NS_FI)
+        {
+          inst.instruction = NEON_ENC_SINGLE (inst.instruction);
+          do_vfp_sp_compare_z ();
+        }
+      else
+        {
+          inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
+          do_vfp_dp_rd ();
+        }
+    }
+  do_vfp_cond_or_thumb ();
+}
+
+static void
+nsyn_insert_sp (void)
+{
+  inst.operands[1] = inst.operands[0];
+  memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
+  inst.operands[0].reg = 13;
+  inst.operands[0].isreg = 1;
+  inst.operands[0].writeback = 1;
+  inst.operands[0].present = 1;
+}
+
+static void
+do_vfp_nsyn_push (void)
+{
+  nsyn_insert_sp ();
+  if (inst.operands[1].issingle)
+    do_vfp_nsyn_opcode ("fstmdbs");
+  else
+    do_vfp_nsyn_opcode ("fstmdbd");
+}
+
+static void
+do_vfp_nsyn_pop (void)
+{
+  nsyn_insert_sp ();
+  if (inst.operands[1].issingle)
+    do_vfp_nsyn_opcode ("fldmias");
+  else
+    do_vfp_nsyn_opcode ("fldmiad");
+}
+
+/* Fix up Neon data-processing instructions, ORing in the correct bits for
+   ARM mode or Thumb mode and moving the encoded bit 24 to bit 28.  */
+
+static unsigned
+neon_dp_fixup (unsigned i)
+{
+  if (thumb_mode)
+    {
+      /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode.  */
+      if (i & (1 << 24))
+        i |= 1 << 28;
+      
+      i &= ~(1 << 24);
+      
+      i |= 0xef000000;
+    }
+  else
+    i |= 0xf2000000;
+  
+  return i;
+}
+
+/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
+   (0, 1, 2, 3).  */
+
+static unsigned
+neon_logbits (unsigned x)
+{
+  return ffs (x) - 4;
+}
+
+#define LOW4(R) ((R) & 0xf)
+#define HI1(R) (((R) >> 4) & 1)
+
+/* Encode insns with bit pattern:
+
+  |28/24|23|22 |21 20|19 16|15 12|11    8|7|6|5|4|3  0|
+  |  U  |x |D  |size | Rn  | Rd  |x x x x|N|Q|M|x| Rm |
+  
+  SIZE is passed in bits. -1 means size field isn't changed, in case it has a
+  different meaning for some instruction.  */
+
+static void
+neon_three_same (int isquad, int ubit, int size)
+{
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (inst.operands[2].reg);
+  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+  inst.instruction |= (isquad != 0) << 6;
+  inst.instruction |= (ubit != 0) << 24;
+  if (size != -1)
+    inst.instruction |= neon_logbits (size) << 20;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+/* Encode instructions of the form:
+
+  |28/24|23|22|21 20|19 18|17 16|15 12|11      7|6|5|4|3  0|
+  |  U  |x |D |x  x |size |x  x | Rd  |x x x x x|Q|M|x| Rm |
+
+  Don't write size if SIZE == -1.  */
+
+static void
+neon_two_same (int qbit, int ubit, int size)
+{
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg);
+  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+  inst.instruction |= (qbit != 0) << 6;
+  inst.instruction |= (ubit != 0) << 24;
+
+  if (size != -1)
+    inst.instruction |= neon_logbits (size) << 18;
+
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+/* Neon instruction encoders, in approximate order of appearance.  */
+
+static void
+do_neon_dyadic_i_su (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_SU_32 | N_KEY);
+  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+}
+
+static void
+do_neon_dyadic_i64_su (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_SU_ALL | N_KEY);
+  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+}
+
+static void
+neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
+                unsigned immbits)
+{
+  unsigned size = et.size >> 3;
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg);
+  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+  inst.instruction |= (isquad != 0) << 6;
+  inst.instruction |= immbits << 16;
+  inst.instruction |= (size >> 3) << 7;
+  inst.instruction |= (size & 0x7) << 19;
+  if (write_ubit)
+    inst.instruction |= (uval != 0) << 24;
+
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_shl_imm (void)
+{
+  if (!inst.operands[2].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
+      unsigned int tmp;
+
+      /* VSHL/VQSHL 3-register variants have syntax such as:
+           vshl.xx Dd, Dm, Dn
+         whereas other 3-register operations encoded by neon_three_same have
+         syntax like:
+           vadd.xx Dd, Dn, Dm
+         (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
+         here.  */
+      tmp = inst.operands[2].reg;
+      inst.operands[2].reg = inst.operands[1].reg;
+      inst.operands[1].reg = tmp;
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+    }
+}
+
+static void
+do_neon_qshl_imm (void)
+{
+  if (!inst.operands[2].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
+
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
+                      inst.operands[2].imm);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
+      unsigned int tmp;
+
+      /* See note in do_neon_shl_imm.  */
+      tmp = inst.operands[2].reg;
+      inst.operands[2].reg = inst.operands[1].reg;
+      inst.operands[1].reg = tmp;
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+    }
+}
+
+static void
+do_neon_rshl (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_SU_ALL | N_KEY);
+  unsigned int tmp;
+
+  tmp = inst.operands[2].reg;
+  inst.operands[2].reg = inst.operands[1].reg;
+  inst.operands[1].reg = tmp;
+  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+}
+
+static int
+neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
+{
+  /* Handle .I8 pseudo-instructions.  */
+  if (size == 8)
+    {
+      /* Unfortunately, this will make everything apart from zero out-of-range.
+         FIXME is this the intended semantics? There doesn't seem much point in
+         accepting .I8 if so.  */
+      immediate |= immediate << 8;
+      size = 16;
+    }
+
+  if (size >= 32)
+    {
+      if (immediate == (immediate & 0x000000ff))
+	{
+	  *immbits = immediate;
+	  return 0x1;
+	}
+      else if (immediate == (immediate & 0x0000ff00))
+	{
+	  *immbits = immediate >> 8;
+	  return 0x3;
+	}
+      else if (immediate == (immediate & 0x00ff0000))
+	{
+	  *immbits = immediate >> 16;
+	  return 0x5;
+	}
+      else if (immediate == (immediate & 0xff000000))
+	{
+	  *immbits = immediate >> 24;
+	  return 0x7;
+	}
+      if ((immediate & 0xffff) != (immediate >> 16))
+	goto bad_immediate;
+      immediate &= 0xffff;
+    }
+
+  if (immediate == (immediate & 0x000000ff))
+    {
+      *immbits = immediate;
+      return 0x9;
+    }
+  else if (immediate == (immediate & 0x0000ff00))
+    {
+      *immbits = immediate >> 8;
+      return 0xb;
+    }
+
+  bad_immediate:
+  first_error (_("immediate value out of range"));
+  return FAIL;
+}
+
+/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
+   A, B, C, D.  */
+
+static int
+neon_bits_same_in_bytes (unsigned imm)
+{
+  return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
+         && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
+         && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
+         && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
+}
+
+/* For immediate of above form, return 0bABCD.  */
+
+static unsigned
+neon_squash_bits (unsigned imm)
+{
+  return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
+         | ((imm & 0x01000000) >> 21);
+}
+
+/* Compress quarter-float representation to 0b...000 abcdefgh.  */
+
+static unsigned
+neon_qfloat_bits (unsigned imm)
+{
+  return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
+}
+
+/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
+   the instruction. *OP is passed as the initial value of the op field, and
+   may be set to a different value depending on the constant (i.e.
+   "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
+   MVN).  If the immediate looks like a repeated parttern then also
+   try smaller element sizes.  */
+
+static int
+neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
+			 unsigned *immbits, int *op, int size,
+			 enum neon_el_type type)
+{
+  /* Only permit float immediates (including 0.0/-0.0) if the operand type is
+     float.  */
+  if (type == NT_float && !float_p)
+    return FAIL;
+
+  if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
+    {
+      if (size != 32 || *op == 1)
+        return FAIL;
+      *immbits = neon_qfloat_bits (immlo);
+      return 0xf;
+    }
+
+  if (size == 64)
+    {
+      if (neon_bits_same_in_bytes (immhi)
+	  && neon_bits_same_in_bytes (immlo))
+	{
+	  if (*op == 1)
+	    return FAIL;
+	  *immbits = (neon_squash_bits (immhi) << 4)
+		     | neon_squash_bits (immlo);
+	  *op = 1;
+	  return 0xe;
+	}
+
+      if (immhi != immlo)
+	return FAIL;
+    }
+
+  if (size >= 32)
+    {
+      if (immlo == (immlo & 0x000000ff))
+	{
+	  *immbits = immlo;
+	  return 0x0;
+	}
+      else if (immlo == (immlo & 0x0000ff00))
+	{
+	  *immbits = immlo >> 8;
+	  return 0x2;
+	}
+      else if (immlo == (immlo & 0x00ff0000))
+	{
+	  *immbits = immlo >> 16;
+	  return 0x4;
+	}
+      else if (immlo == (immlo & 0xff000000))
+	{
+	  *immbits = immlo >> 24;
+	  return 0x6;
+	}
+      else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
+	{
+	  *immbits = (immlo >> 8) & 0xff;
+	  return 0xc;
+	}
+      else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
+	{
+	  *immbits = (immlo >> 16) & 0xff;
+	  return 0xd;
+	}
+
+      if ((immlo & 0xffff) != (immlo >> 16))
+	return FAIL;
+      immlo &= 0xffff;
+    }
+
+  if (size >= 16)
+    {
+      if (immlo == (immlo & 0x000000ff))
+	{
+	  *immbits = immlo;
+	  return 0x8;
+	}
+      else if (immlo == (immlo & 0x0000ff00))
+	{
+	  *immbits = immlo >> 8;
+	  return 0xa;
+	}
+
+      if ((immlo & 0xff) != (immlo >> 8))
+	return FAIL;
+      immlo &= 0xff;
+    }
+
+  if (immlo == (immlo & 0x000000ff))
+    {
+      /* Don't allow MVN with 8-bit immediate.  */
+      if (*op == 1)
+	return FAIL;
+      *immbits = immlo;
+      return 0xe;
+    }
+
+  return FAIL;
+}
+
+/* Write immediate bits [7:0] to the following locations:
+
+  |28/24|23     19|18 16|15                    4|3     0|
+  |  a  |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
+
+  This function is used by VMOV/VMVN/VORR/VBIC.  */
+
+static void
+neon_write_immbits (unsigned immbits)
+{
+  inst.instruction |= immbits & 0xf;
+  inst.instruction |= ((immbits >> 4) & 0x7) << 16;
+  inst.instruction |= ((immbits >> 7) & 0x1) << 24;
+}
+
+/* Invert low-order SIZE bits of XHI:XLO.  */
+
+static void
+neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
+{
+  unsigned immlo = xlo ? *xlo : 0;
+  unsigned immhi = xhi ? *xhi : 0;
+
+  switch (size)
+    {
+    case 8:
+      immlo = (~immlo) & 0xff;
+      break;
+
+    case 16:
+      immlo = (~immlo) & 0xffff;
+      break;
+
+    case 64:
+      immhi = (~immhi) & 0xffffffff;
+      /* fall through.  */
+
+    case 32:
+      immlo = (~immlo) & 0xffffffff;
+      break;
+
+    default:
+      abort ();
+    }
+
+  if (xlo)
+    *xlo = immlo;
+
+  if (xhi)
+    *xhi = immhi;
+}
+
+static void
+do_neon_logic (void)
+{
+  if (inst.operands[2].present && inst.operands[2].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+      neon_check_type (3, rs, N_IGNORE_TYPE);
+      /* U bit and size field were set as part of the bitmask.  */
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_three_same (neon_quad (rs), 0, -1);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs,
+        N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
+      enum neon_opc opcode = inst.instruction & 0x0fffffff;
+      unsigned immbits;
+      int cmode;
+      
+      if (et.type == NT_invtype)
+        return;
+      
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+
+      immbits = inst.operands[1].imm;
+      if (et.size == 64)
+	{
+	  /* .i64 is a pseudo-op, so the immediate must be a repeating
+	     pattern.  */
+	  if (immbits != (inst.operands[1].regisimm ?
+			  inst.operands[1].reg : 0))
+	    {
+	      /* Set immbits to an invalid constant.  */
+	      immbits = 0xdeadbeef;
+	    }
+	}
+
+      switch (opcode)
+        {
+        case N_MNEM_vbic:
+          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
+          break;
+        
+        case N_MNEM_vorr:
+          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
+          break;
+        
+        case N_MNEM_vand:
+          /* Pseudo-instruction for VBIC.  */
+          neon_invert_size (&immbits, 0, et.size);
+          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
+          break;
+        
+        case N_MNEM_vorn:
+          /* Pseudo-instruction for VORR.  */
+          neon_invert_size (&immbits, 0, et.size);
+          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
+          break;
+        
+        default:
+          abort ();
+        }
+
+      if (cmode == FAIL)
+        return;
+
+      inst.instruction |= neon_quad (rs) << 6;
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= cmode << 8;
+      neon_write_immbits (immbits);
+      
+      inst.instruction = neon_dp_fixup (inst.instruction);
+    }
+}
+
+static void
+do_neon_bitfield (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  neon_check_type (3, rs, N_IGNORE_TYPE);
+  neon_three_same (neon_quad (rs), 0, -1);
+}
+
+static void
+neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
+                  unsigned destbits)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
+                                            types | N_KEY);
+  if (et.type == NT_float)
+    {
+      inst.instruction = NEON_ENC_FLOAT (inst.instruction);
+      neon_three_same (neon_quad (rs), 0, -1);
+    }
+  else
+    {
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
+    }
+}
+
+static void
+do_neon_dyadic_if_su (void)
+{
+  neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
+}
+
+static void
+do_neon_dyadic_if_su_d (void)
+{
+  /* This version only allow D registers, but that constraint is enforced during
+     operand parsing so we don't need to do anything extra here.  */
+  neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
+}
+
+static void
+do_neon_dyadic_if_i_d (void)
+{
+  /* The "untyped" case can't happen. Do this to stop the "U" bit being
+     affected if we specify unsigned args.  */
+  neon_dyadic_misc (NT_untyped, N_IF_32, 0);
+}
+
+enum vfp_or_neon_is_neon_bits
+{
+  NEON_CHECK_CC = 1,
+  NEON_CHECK_ARCH = 2
+};
+
+/* Call this function if an instruction which may have belonged to the VFP or
+   Neon instruction sets, but turned out to be a Neon instruction (due to the
+   operand types involved, etc.). We have to check and/or fix-up a couple of
+   things:
+
+     - Make sure the user hasn't attempted to make a Neon instruction
+       conditional.
+     - Alter the value in the condition code field if necessary.
+     - Make sure that the arch supports Neon instructions.
+
+   Which of these operations take place depends on bits from enum
+   vfp_or_neon_is_neon_bits.
+
+   WARNING: This function has side effects! If NEON_CHECK_CC is used and the
+   current instruction's condition is COND_ALWAYS, the condition field is
+   changed to inst.uncond_value. This is necessary because instructions shared
+   between VFP and Neon may be conditional for the VFP variants only, and the
+   unconditional Neon version must have, e.g., 0xF in the condition field.  */
+
+static int
+vfp_or_neon_is_neon (unsigned check)
+{
+  /* Conditions are always legal in Thumb mode (IT blocks).  */
+  if (!thumb_mode && (check & NEON_CHECK_CC))
+    {
+      if (inst.cond != COND_ALWAYS)
+        {
+          first_error (_(BAD_COND));
+          return FAIL;
+        }
+      if (inst.uncond_value != -1)
+        inst.instruction |= inst.uncond_value << 28;
+    }
+  
+  if ((check & NEON_CHECK_ARCH)
+      && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
+    {
+      first_error (_(BAD_FPU));
+      return FAIL;
+    }
+  
+  return SUCCESS;
+}
+
+static void
+do_neon_addsub_if_i (void)
+{
+  if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
+    return;
+
+  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+    return;
+
+  /* The "untyped" case can't happen. Do this to stop the "U" bit being
+     affected if we specify unsigned args.  */
+  neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
+}
+
+/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
+   result to be:
+     V<op> A,B     (A is operand 0, B is operand 2)
+   to mean:
+     V<op> A,B,A
+   not:
+     V<op> A,B,B
+   so handle that case specially.  */
+
+static void
+neon_exchange_operands (void)
+{
+  void *scratch = alloca (sizeof (inst.operands[0]));
+  if (inst.operands[1].present)
+    {
+      /* Swap operands[1] and operands[2].  */
+      memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
+      inst.operands[1] = inst.operands[2];
+      memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
+    }
+  else
+    {
+      inst.operands[1] = inst.operands[2];
+      inst.operands[2] = inst.operands[0];
+    }
+}
+
+static void
+neon_compare (unsigned regtypes, unsigned immtypes, int invert)
+{
+  if (inst.operands[2].isreg)
+    {
+      if (invert)
+        neon_exchange_operands ();
+      neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs,
+        N_EQK | N_SIZ, immtypes | N_KEY);
+
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= LOW4 (inst.operands[1].reg);
+      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+      inst.instruction |= neon_quad (rs) << 6;
+      inst.instruction |= (et.type == NT_float) << 10;
+      inst.instruction |= neon_logbits (et.size) << 18;
+      
+      inst.instruction = neon_dp_fixup (inst.instruction);
+    }
+}
+
+static void
+do_neon_cmp (void)
+{
+  neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
+}
+
+static void
+do_neon_cmp_inv (void)
+{
+  neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
+}
+
+static void
+do_neon_ceq (void)
+{
+  neon_compare (N_IF_32, N_IF_32, FALSE);
+}
+
+/* For multiply instructions, we have the possibility of 16-bit or 32-bit
+   scalars, which are encoded in 5 bits, M : Rm.
+   For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
+   M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
+   index in M.  */
+
+static unsigned
+neon_scalar_for_mul (unsigned scalar, unsigned elsize)
+{
+  unsigned regno = NEON_SCALAR_REG (scalar);
+  unsigned elno = NEON_SCALAR_INDEX (scalar);
+
+  switch (elsize)
+    {
+    case 16:
+      if (regno > 7 || elno > 3)
+        goto bad_scalar;
+      return regno | (elno << 3);
+    
+    case 32:
+      if (regno > 15 || elno > 1)
+        goto bad_scalar;
+      return regno | (elno << 4);
+
+    default:
+    bad_scalar:
+      first_error (_("scalar out of range for multiply instruction"));
+    }
+
+  return 0;
+}
+
+/* Encode multiply / multiply-accumulate scalar instructions.  */
+
+static void
+neon_mul_mac (struct neon_type_el et, int ubit)
+{
+  unsigned scalar;
+
+  /* Give a more helpful error message if we have an invalid type.  */
+  if (et.type == NT_invtype)
+    return;
+  
+  scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (scalar);
+  inst.instruction |= HI1 (scalar) << 5;
+  inst.instruction |= (et.type == NT_float) << 8;
+  inst.instruction |= neon_logbits (et.size) << 20;
+  inst.instruction |= (ubit != 0) << 24;
+
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_mac_maybe_scalar (void)
+{
+  if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
+    return;
+
+  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+    return;
+
+  if (inst.operands[2].isscalar)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
+      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
+      neon_mul_mac (et, neon_quad (rs));
+    }
+  else
+    {
+      /* The "untyped" case can't happen.  Do this to stop the "U" bit being
+	 affected if we specify unsigned args.  */
+      neon_dyadic_misc (NT_untyped, N_IF_32, 0);
+    }
+}
+
+static void
+do_neon_tst (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
+  neon_three_same (neon_quad (rs), 0, et.size);
+}
+
+/* VMUL with 3 registers allows the P8 type. The scalar version supports the
+   same types as the MAC equivalents. The polynomial type for this instruction
+   is encoded the same as the integer type.  */
+
+static void
+do_neon_mul (void)
+{
+  if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
+    return;
+
+  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+    return;
+
+  if (inst.operands[2].isscalar)
+    do_neon_mac_maybe_scalar ();
+  else
+    neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
+}
+
+static void
+do_neon_qdmulh (void)
+{
+  if (inst.operands[2].isscalar)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
+      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
+      neon_mul_mac (et, neon_quad (rs));
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      /* The U bit (rounding) comes from bit mask.  */
+      neon_three_same (neon_quad (rs), 0, et.size);
+    }
+}
+
+static void
+do_neon_fcmp_absolute (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
+  /* Size field comes from bit mask.  */
+  neon_three_same (neon_quad (rs), 1, -1);
+}
+
+static void
+do_neon_fcmp_absolute_inv (void)
+{
+  neon_exchange_operands ();
+  do_neon_fcmp_absolute ();
+}
+
+static void
+do_neon_step (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
+  neon_three_same (neon_quad (rs), 0, -1);
+}
+
+static void
+do_neon_abs_neg (void)
+{
+  enum neon_shape rs;
+  struct neon_type_el et;
+  
+  if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
+    return;
+
+  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+    return;
+
+  rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
+  
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg);
+  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+  inst.instruction |= neon_quad (rs) << 6;
+  inst.instruction |= (et.type == NT_float) << 10;
+  inst.instruction |= neon_logbits (et.size) << 18;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_sli (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  constraint (imm < 0 || (unsigned)imm >= et.size,
+              _("immediate out of range for insert"));
+  neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
+}
+
+static void
+do_neon_sri (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range for insert"));
+  neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
+}
+
+static void
+do_neon_qshlu_imm (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  constraint (imm < 0 || (unsigned)imm >= et.size,
+              _("immediate out of range for shift"));
+  /* Only encodes the 'U present' variant of the instruction.
+     In this case, signed types have OP (bit 8) set to 0.
+     Unsigned types have OP set to 1.  */
+  inst.instruction |= (et.type == NT_unsigned) << 8;
+  /* The rest of the bits are the same as other immediate shifts.  */
+  neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
+}
+
+static void
+do_neon_qmovn (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_DQ,
+    N_EQK | N_HLF, N_SU_16_64 | N_KEY);
+  /* Saturating move where operands can be signed or unsigned, and the
+     destination has the same signedness.  */
+  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+  if (et.type == NT_unsigned)
+    inst.instruction |= 0xc0;
+  else
+    inst.instruction |= 0x80;
+  neon_two_same (0, 1, et.size / 2);
+}
+
+static void
+do_neon_qmovun (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_DQ,
+    N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
+  /* Saturating move with unsigned results. Operands must be signed.  */
+  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+  neon_two_same (0, 1, et.size / 2);
+}
+
+static void
+do_neon_rshift_sat_narrow (void)
+{
+  /* FIXME: Types for narrowing. If operands are signed, results can be signed
+     or unsigned. If operands are unsigned, results must also be unsigned.  */
+  struct neon_type_el et = neon_check_type (2, NS_DQI,
+    N_EQK | N_HLF, N_SU_16_64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  /* This gets the bounds check, size encoding and immediate bits calculation
+     right.  */
+  et.size /= 2;
+  
+  /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
+     VQMOVN.I<size> <Dd>, <Qm>.  */
+  if (imm == 0)
+    {
+      inst.operands[2].present = 0;
+      inst.instruction = N_MNEM_vqmovn;
+      do_neon_qmovn ();
+      return;
+    }
+  
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range"));
+  neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
+}
+
+static void
+do_neon_rshift_sat_narrow_u (void)
+{
+  /* FIXME: Types for narrowing. If operands are signed, results can be signed
+     or unsigned. If operands are unsigned, results must also be unsigned.  */
+  struct neon_type_el et = neon_check_type (2, NS_DQI,
+    N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  /* This gets the bounds check, size encoding and immediate bits calculation
+     right.  */
+  et.size /= 2;
+
+  /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
+     VQMOVUN.I<size> <Dd>, <Qm>.  */
+  if (imm == 0)
+    {
+      inst.operands[2].present = 0;
+      inst.instruction = N_MNEM_vqmovun;
+      do_neon_qmovun ();
+      return;
+    }
+
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range"));
+  /* FIXME: The manual is kind of unclear about what value U should have in
+     VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
+     must be 1.  */
+  neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
+}
+
+static void
+do_neon_movn (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_DQ,
+    N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
+  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+  neon_two_same (0, 1, et.size / 2);
+}
+
+static void
+do_neon_rshift_narrow (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_DQI,
+    N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  /* This gets the bounds check, size encoding and immediate bits calculation
+     right.  */
+  et.size /= 2;
+  
+  /* If immediate is zero then we are a pseudo-instruction for
+     VMOVN.I<size> <Dd>, <Qm>  */
+  if (imm == 0)
+    {
+      inst.operands[2].present = 0;
+      inst.instruction = N_MNEM_vmovn;
+      do_neon_movn ();
+      return;
+    }
+  
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range for narrowing operation"));
+  neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
+}
+
+static void
+do_neon_shll (void)
+{
+  /* FIXME: Type checking when lengthening.  */
+  struct neon_type_el et = neon_check_type (2, NS_QDI,
+    N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
+  unsigned imm = inst.operands[2].imm;
+
+  if (imm == et.size)
+    {
+      /* Maximum shift variant.  */
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= LOW4 (inst.operands[1].reg);
+      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+      inst.instruction |= neon_logbits (et.size) << 18;
+      
+      inst.instruction = neon_dp_fixup (inst.instruction);
+    }
+  else
+    {
+      /* A more-specific type check for non-max versions.  */
+      et = neon_check_type (2, NS_QDI,
+        N_EQK | N_DBL, N_SU_32 | N_KEY);
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
+    }
+}
+
+/* Check the various types for the VCVT instruction, and return which version
+   the current instruction is.  */
+
+static int
+neon_cvt_flavour (enum neon_shape rs)
+{
+#define CVT_VAR(C,X,Y)							\
+  et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y));	\
+  if (et.type != NT_invtype)						\
+    {									\
+      inst.error = NULL;						\
+      return (C);							\
+    }
+  struct neon_type_el et;
+  unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
+                        || rs == NS_FF) ? N_VFP : 0;
+  /* The instruction versions which take an immediate take one register
+     argument, which is extended to the width of the full register. Thus the
+     "source" and "destination" registers must have the same width.  Hack that
+     here by making the size equal to the key (wider, in this case) operand.  */
+  unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
+  
+  CVT_VAR (0, N_S32, N_F32);
+  CVT_VAR (1, N_U32, N_F32);
+  CVT_VAR (2, N_F32, N_S32);
+  CVT_VAR (3, N_F32, N_U32);
+  
+  whole_reg = N_VFP;
+  
+  /* VFP instructions.  */
+  CVT_VAR (4, N_F32, N_F64);
+  CVT_VAR (5, N_F64, N_F32);
+  CVT_VAR (6, N_S32, N_F64 | key);
+  CVT_VAR (7, N_U32, N_F64 | key);
+  CVT_VAR (8, N_F64 | key, N_S32);
+  CVT_VAR (9, N_F64 | key, N_U32);
+  /* VFP instructions with bitshift.  */
+  CVT_VAR (10, N_F32 | key, N_S16);
+  CVT_VAR (11, N_F32 | key, N_U16);
+  CVT_VAR (12, N_F64 | key, N_S16);
+  CVT_VAR (13, N_F64 | key, N_U16);
+  CVT_VAR (14, N_S16, N_F32 | key);
+  CVT_VAR (15, N_U16, N_F32 | key);
+  CVT_VAR (16, N_S16, N_F64 | key);
+  CVT_VAR (17, N_U16, N_F64 | key);
+  
+  return -1;
+#undef CVT_VAR
+}
+
+/* Neon-syntax VFP conversions.  */
+
+static void
+do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
+{
+  const char *opname = 0;
+  
+  if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
+    {
+      /* Conversions with immediate bitshift.  */
+      const char *enc[] =
+        {
+          "ftosls",
+          "ftouls",
+          "fsltos",
+          "fultos",
+          NULL,
+          NULL,
+          "ftosld",
+          "ftould",
+          "fsltod",
+          "fultod",
+          "fshtos",
+          "fuhtos",
+          "fshtod",
+          "fuhtod",
+          "ftoshs",
+          "ftouhs",
+          "ftoshd",
+          "ftouhd"
+        };
+
+      if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
+        {
+          opname = enc[flavour];
+          constraint (inst.operands[0].reg != inst.operands[1].reg,
+                      _("operands 0 and 1 must be the same register"));
+          inst.operands[1] = inst.operands[2];
+          memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
+        }
+    }
+  else
+    {
+      /* Conversions without bitshift.  */
+      const char *enc[] =
+        {
+          "ftosis",
+          "ftouis",
+          "fsitos",
+          "fuitos",
+          "fcvtsd",
+          "fcvtds",
+          "ftosid",
+          "ftouid",
+          "fsitod",
+          "fuitod"
+        };
+
+      if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
+        opname = enc[flavour];
+    }
+
+  if (opname)
+    do_vfp_nsyn_opcode (opname);
+}
+
+static void
+do_vfp_nsyn_cvtz (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
+  int flavour = neon_cvt_flavour (rs);
+  const char *enc[] =
+    {
+      "ftosizs",
+      "ftouizs",
+      NULL,
+      NULL,
+      NULL,
+      NULL,
+      "ftosizd",
+      "ftouizd"
+    };
+
+  if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
+    do_vfp_nsyn_opcode (enc[flavour]);
+}
+
+static void
+do_neon_cvt (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
+    NS_FD, NS_DF, NS_FF, NS_NULL);
+  int flavour = neon_cvt_flavour (rs);
+
+  /* VFP rather than Neon conversions.  */
+  if (flavour >= 4)
+    {
+      do_vfp_nsyn_cvt (rs, flavour);
+      return;
+    }
+
+  switch (rs)
+    {
+    case NS_DDI:
+    case NS_QQI:
+      {
+        if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+          return;
+
+        /* Fixed-point conversion with #0 immediate is encoded as an
+           integer conversion.  */
+        if (inst.operands[2].present && inst.operands[2].imm == 0)
+          goto int_encode;
+        unsigned immbits = 32 - inst.operands[2].imm;
+        unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
+        inst.instruction = NEON_ENC_IMMED (inst.instruction);
+        if (flavour != -1)
+          inst.instruction |= enctab[flavour];
+        inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+        inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+        inst.instruction |= LOW4 (inst.operands[1].reg);
+        inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+        inst.instruction |= neon_quad (rs) << 6;
+        inst.instruction |= 1 << 21;
+        inst.instruction |= immbits << 16;
+
+        inst.instruction = neon_dp_fixup (inst.instruction);
+      }
+      break;
+
+    case NS_DD:
+    case NS_QQ:
+    int_encode:
+      {
+        unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
+
+        inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+
+        if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+          return;
+
+        if (flavour != -1)
+          inst.instruction |= enctab[flavour];
+
+        inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+        inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+        inst.instruction |= LOW4 (inst.operands[1].reg);
+        inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+        inst.instruction |= neon_quad (rs) << 6;
+        inst.instruction |= 2 << 18;
+
+        inst.instruction = neon_dp_fixup (inst.instruction);
+      }
+    break;
+
+    default:
+      /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32).  */
+      do_vfp_nsyn_cvt (rs, flavour);
+    }
+}
+
+static void
+neon_move_immediate (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
+  unsigned immlo, immhi = 0, immbits;
+  int op, cmode, float_p;
+
+  constraint (et.type == NT_invtype,
+              _("operand size must be specified for immediate VMOV"));
+
+  /* We start out as an MVN instruction if OP = 1, MOV otherwise.  */
+  op = (inst.instruction & (1 << 5)) != 0;
+
+  immlo = inst.operands[1].imm;
+  if (inst.operands[1].regisimm)
+    immhi = inst.operands[1].reg;
+
+  constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
+              _("immediate has bits set outside the operand size"));
+
+  float_p = inst.operands[1].immisfloat;
+
+  if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
+                                        et.size, et.type)) == FAIL)
+    {
+      /* Invert relevant bits only.  */
+      neon_invert_size (&immlo, &immhi, et.size);
+      /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
+         with one or the other; those cases are caught by
+         neon_cmode_for_move_imm.  */
+      op = !op;
+      if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
+					    &op, et.size, et.type)) == FAIL)
+        {
+          first_error (_("immediate out of range"));
+          return;
+        }
+    }
+
+  inst.instruction &= ~(1 << 5);
+  inst.instruction |= op << 5;
+
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= neon_quad (rs) << 6;
+  inst.instruction |= cmode << 8;
+
+  neon_write_immbits (immbits);
+}
+
+static void
+do_neon_mvn (void)
+{
+  if (inst.operands[1].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+      
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= LOW4 (inst.operands[1].reg);
+      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+      inst.instruction |= neon_quad (rs) << 6;
+    }
+  else
+    {
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      neon_move_immediate ();
+    }
+
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+/* Encode instructions of form:
+
+  |28/24|23|22|21 20|19 16|15 12|11    8|7|6|5|4|3  0|
+  |  U  |x |D |size | Rn  | Rd  |x x x x|N|x|M|x| Rm |
+
+*/
+
+static void
+neon_mixed_length (struct neon_type_el et, unsigned size)
+{
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (inst.operands[2].reg);
+  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+  inst.instruction |= (et.type == NT_unsigned) << 24;
+  inst.instruction |= neon_logbits (size) << 20;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_dyadic_long (void)
+{
+  /* FIXME: Type checking for lengthening op.  */
+  struct neon_type_el et = neon_check_type (3, NS_QDD,
+    N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
+  neon_mixed_length (et, et.size);
+}
+
+static void
+do_neon_abal (void)
+{
+  struct neon_type_el et = neon_check_type (3, NS_QDD,
+    N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
+  neon_mixed_length (et, et.size);
+}
+
+static void
+neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
+{
+  if (inst.operands[2].isscalar)
+    {
+      struct neon_type_el et = neon_check_type (3, NS_QDS,
+        N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
+      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
+      neon_mul_mac (et, et.type == NT_unsigned);
+    }
+  else
+    {
+      struct neon_type_el et = neon_check_type (3, NS_QDD,
+        N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_mixed_length (et, et.size);
+    }
+}
+
+static void
+do_neon_mac_maybe_scalar_long (void)
+{
+  neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
+}
+
+static void
+do_neon_dyadic_wide (void)
+{
+  struct neon_type_el et = neon_check_type (3, NS_QQD,
+    N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
+  neon_mixed_length (et, et.size);
+}
+
+static void
+do_neon_dyadic_narrow (void)
+{
+  struct neon_type_el et = neon_check_type (3, NS_QDD,
+    N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
+  /* Operand sign is unimportant, and the U bit is part of the opcode,
+     so force the operand type to integer.  */
+  et.type = NT_integer;
+  neon_mixed_length (et, et.size / 2);
+}
+
+static void
+do_neon_mul_sat_scalar_long (void)
+{
+  neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
+}
+
+static void
+do_neon_vmull (void)
+{
+  if (inst.operands[2].isscalar)
+    do_neon_mac_maybe_scalar_long ();
+  else
+    {
+      struct neon_type_el et = neon_check_type (3, NS_QDD,
+        N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
+      if (et.type == NT_poly)
+        inst.instruction = NEON_ENC_POLY (inst.instruction);
+      else
+        inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      /* For polynomial encoding, size field must be 0b00 and the U bit must be
+         zero. Should be OK as-is.  */
+      neon_mixed_length (et, et.size);
+    }
+}
+
+static void
+do_neon_ext (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+  unsigned imm = (inst.operands[3].imm * et.size) / 8;
+  constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (inst.operands[2].reg);
+  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+  inst.instruction |= neon_quad (rs) << 6;
+  inst.instruction |= imm << 8;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_rev (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_KEY);
+  unsigned op = (inst.instruction >> 7) & 3;
+  /* N (width of reversed regions) is encoded as part of the bitmask. We
+     extract it here to check the elements to be reversed are smaller.
+     Otherwise we'd get a reserved instruction.  */
+  unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
+  assert (elsize != 0);
+  constraint (et.size >= elsize,
+              _("elements must be smaller than reversal region"));
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_dup (void)
+{
+  if (inst.operands[1].isscalar)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs,
+        N_EQK, N_8 | N_16 | N_32 | N_KEY);
+      unsigned sizebits = et.size >> 3;
+      unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
+      int logsize = neon_logbits (et.size);
+      unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
+
+      if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
+        return;
+
+      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= LOW4 (dm);
+      inst.instruction |= HI1 (dm) << 5;
+      inst.instruction |= neon_quad (rs) << 6;
+      inst.instruction |= x << 17;
+      inst.instruction |= sizebits << 16;
+      
+      inst.instruction = neon_dp_fixup (inst.instruction);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs,
+        N_8 | N_16 | N_32 | N_KEY, N_EQK);
+      /* Duplicate ARM register to lanes of vector.  */
+      inst.instruction = NEON_ENC_ARMREG (inst.instruction);
+      switch (et.size)
+        {
+        case 8:  inst.instruction |= 0x400000; break;
+        case 16: inst.instruction |= 0x000020; break;
+        case 32: inst.instruction |= 0x000000; break;
+        default: break;
+        }
+      inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 7;
+      inst.instruction |= neon_quad (rs) << 21;
+      /* The encoding for this instruction is identical for the ARM and Thumb
+         variants, except for the condition field.  */
+      do_vfp_cond_or_thumb ();
+    }
+}
+
+/* VMOV has particularly many variations. It can be one of:
+     0. VMOV<c><q> <Qd>, <Qm>
+     1. VMOV<c><q> <Dd>, <Dm>
+   (Register operations, which are VORR with Rm = Rn.)
+     2. VMOV<c><q>.<dt> <Qd>, #<imm>
+     3. VMOV<c><q>.<dt> <Dd>, #<imm>
+   (Immediate loads.)
+     4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
+   (ARM register to scalar.)
+     5. VMOV<c><q> <Dm>, <Rd>, <Rn>
+   (Two ARM registers to vector.)
+     6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
+   (Scalar to ARM register.)
+     7. VMOV<c><q> <Rd>, <Rn>, <Dm>
+   (Vector to two ARM registers.)
+     8. VMOV.F32 <Sd>, <Sm>
+     9. VMOV.F64 <Dd>, <Dm>
+   (VFP register moves.)
+    10. VMOV.F32 <Sd>, #imm
+    11. VMOV.F64 <Dd>, #imm
+   (VFP float immediate load.)
+    12. VMOV <Rd>, <Sm>
+   (VFP single to ARM reg.)
+    13. VMOV <Sd>, <Rm>
+   (ARM reg to VFP single.)
+    14. VMOV <Rd>, <Re>, <Sn>, <Sm>
+   (Two ARM regs to two VFP singles.)
+    15. VMOV <Sd>, <Se>, <Rn>, <Rm>
+   (Two VFP singles to two ARM regs.)
+  
+   These cases can be disambiguated using neon_select_shape, except cases 1/9
+   and 3/11 which depend on the operand type too.
+   
+   All the encoded bits are hardcoded by this function.
+   
+   Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
+   Cases 5, 7 may be used with VFPv2 and above.
+   
+   FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
+   can specify a type where it doesn't make sense to, and is ignored).
+*/
+
+static void
+do_neon_mov (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
+    NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
+    NS_NULL);
+  struct neon_type_el et;
+  const char *ldconst = 0;
+
+  switch (rs)
+    {
+    case NS_DD:  /* case 1/9.  */
+      et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
+      /* It is not an error here if no type is given.  */
+      inst.error = NULL;
+      if (et.type == NT_float && et.size == 64)
+        {
+          do_vfp_nsyn_opcode ("fcpyd");
+          break;
+        }
+      /* fall through.  */
+
+    case NS_QQ:  /* case 0/1.  */
+      {
+        if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+          return;
+        /* The architecture manual I have doesn't explicitly state which
+           value the U bit should have for register->register moves, but
+           the equivalent VORR instruction has U = 0, so do that.  */
+        inst.instruction = 0x0200110;
+        inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+        inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+        inst.instruction |= LOW4 (inst.operands[1].reg);
+        inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+        inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+        inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+        inst.instruction |= neon_quad (rs) << 6;
+
+        inst.instruction = neon_dp_fixup (inst.instruction);
+      }
+      break;
+        
+    case NS_DI:  /* case 3/11.  */
+      et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
+      inst.error = NULL;
+      if (et.type == NT_float && et.size == 64)
+        {
+          /* case 11 (fconstd).  */
+          ldconst = "fconstd";
+          goto encode_fconstd;
+        }
+      /* fall through.  */
+
+    case NS_QI:  /* case 2/3.  */
+      if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+        return;
+      inst.instruction = 0x0800010;
+      neon_move_immediate ();
+      inst.instruction = neon_dp_fixup (inst.instruction);
+      break;
+    
+    case NS_SR:  /* case 4.  */
+      {
+        unsigned bcdebits = 0;
+        struct neon_type_el et = neon_check_type (2, NS_NULL,
+          N_8 | N_16 | N_32 | N_KEY, N_EQK);
+        int logsize = neon_logbits (et.size);
+        unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
+        unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
+
+        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
+                    _(BAD_FPU));
+        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
+                    && et.size != 32, _(BAD_FPU));
+        constraint (et.type == NT_invtype, _("bad type for scalar"));
+        constraint (x >= 64 / et.size, _("scalar index out of range"));
+
+        switch (et.size)
+          {
+          case 8:  bcdebits = 0x8; break;
+          case 16: bcdebits = 0x1; break;
+          case 32: bcdebits = 0x0; break;
+          default: ;
+          }
+
+        bcdebits |= x << logsize;
+
+        inst.instruction = 0xe000b10;
+        do_vfp_cond_or_thumb ();
+        inst.instruction |= LOW4 (dn) << 16;
+        inst.instruction |= HI1 (dn) << 7;
+        inst.instruction |= inst.operands[1].reg << 12;
+        inst.instruction |= (bcdebits & 3) << 5;
+        inst.instruction |= (bcdebits >> 2) << 21;
+      }
+      break;
+    
+    case NS_DRR:  /* case 5 (fmdrr).  */
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
+                  _(BAD_FPU));
+
+      inst.instruction = 0xc400b10;
+      do_vfp_cond_or_thumb ();
+      inst.instruction |= LOW4 (inst.operands[0].reg);
+      inst.instruction |= HI1 (inst.operands[0].reg) << 5;
+      inst.instruction |= inst.operands[1].reg << 12;
+      inst.instruction |= inst.operands[2].reg << 16;
+      break;
+    
+    case NS_RS:  /* case 6.  */
+      {
+        struct neon_type_el et = neon_check_type (2, NS_NULL,
+          N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
+        unsigned logsize = neon_logbits (et.size);
+        unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
+        unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
+        unsigned abcdebits = 0;
+
+        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
+                    _(BAD_FPU));
+        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
+                    && et.size != 32, _(BAD_FPU));
+        constraint (et.type == NT_invtype, _("bad type for scalar"));
+        constraint (x >= 64 / et.size, _("scalar index out of range"));
+
+        switch (et.size)
+          {
+          case 8:  abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
+          case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
+          case 32: abcdebits = 0x00; break;
+          default: ;
+          }
+
+        abcdebits |= x << logsize;
+        inst.instruction = 0xe100b10;
+        do_vfp_cond_or_thumb ();
+        inst.instruction |= LOW4 (dn) << 16;
+        inst.instruction |= HI1 (dn) << 7;
+        inst.instruction |= inst.operands[0].reg << 12;
+        inst.instruction |= (abcdebits & 3) << 5;
+        inst.instruction |= (abcdebits >> 2) << 21;
+      }
+      break;
+    
+    case NS_RRD:  /* case 7 (fmrrd).  */
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
+                  _(BAD_FPU));
+
+      inst.instruction = 0xc500b10;
+      do_vfp_cond_or_thumb ();
+      inst.instruction |= inst.operands[0].reg << 12;
+      inst.instruction |= inst.operands[1].reg << 16;
+      inst.instruction |= LOW4 (inst.operands[2].reg);
+      inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+      break;
+    
+    case NS_FF:  /* case 8 (fcpys).  */
+      do_vfp_nsyn_opcode ("fcpys");
+      break;
+    
+    case NS_FI:  /* case 10 (fconsts).  */
+      ldconst = "fconsts";
+      encode_fconstd:
+      if (is_quarter_float (inst.operands[1].imm))
+        {
+          inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
+          do_vfp_nsyn_opcode (ldconst);
+        }
+      else
+        first_error (_("immediate out of range"));
+      break;
+    
+    case NS_RF:  /* case 12 (fmrs).  */
+      do_vfp_nsyn_opcode ("fmrs");
+      break;
+    
+    case NS_FR:  /* case 13 (fmsr).  */
+      do_vfp_nsyn_opcode ("fmsr");
+      break;
+    
+    /* The encoders for the fmrrs and fmsrr instructions expect three operands
+       (one of which is a list), but we have parsed four.  Do some fiddling to
+       make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
+       expect.  */
+    case NS_RRFF:  /* case 14 (fmrrs).  */
+      constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
+                  _("VFP registers must be adjacent"));
+      inst.operands[2].imm = 2;
+      memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
+      do_vfp_nsyn_opcode ("fmrrs");
+      break;
+    
+    case NS_FFRR:  /* case 15 (fmsrr).  */
+      constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
+                  _("VFP registers must be adjacent"));
+      inst.operands[1] = inst.operands[2];
+      inst.operands[2] = inst.operands[3];
+      inst.operands[0].imm = 2;
+      memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
+      do_vfp_nsyn_opcode ("fmsrr");
+      break;
+    
+    default:
+      abort ();
+    }
+}
+
+static void
+do_neon_rshift_round_imm (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
+  int imm = inst.operands[2].imm;
+
+  /* imm == 0 case is encoded as VMOV for V{R}SHR.  */
+  if (imm == 0)
+    {
+      inst.operands[2].present = 0;
+      do_neon_mov ();
+      return;
+    }
+
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range for shift"));
+  neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
+                  et.size - imm);
+}
+
+static void
+do_neon_movl (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_QD,
+    N_EQK | N_DBL, N_SU_32 | N_KEY);
+  unsigned sizebits = et.size >> 3;
+  inst.instruction |= sizebits << 19;
+  neon_two_same (0, et.type == NT_unsigned, -1);
+}
+
+static void
+do_neon_trn (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_KEY);
+  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_zip_uzp (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_KEY);
+  if (rs == NS_DD && et.size == 32)
+    {
+      /* Special case: encode as VTRN.32 <Dd>, <Dm>.  */
+      inst.instruction = N_MNEM_vtrn;
+      do_neon_trn ();
+      return;
+    }
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_sat_abs_neg (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_pair_long (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
+  /* Unsigned is encoded in OP field (bit 7) for these instruction.  */
+  inst.instruction |= (et.type == NT_unsigned) << 7;
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_recip_est (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
+  inst.instruction |= (et.type == NT_float) << 8;
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_cls (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_clz (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_cnt (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK | N_INT, N_8 | N_KEY);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_swp (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  neon_two_same (neon_quad (rs), 1, -1);
+}
+
+static void
+do_neon_tbl_tbx (void)
+{
+  unsigned listlenbits;
+  neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
+  
+  if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
+    {
+      first_error (_("bad list length for table lookup"));
+      return;
+    }
+  
+  listlenbits = inst.operands[1].imm - 1;
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (inst.operands[2].reg);
+  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+  inst.instruction |= listlenbits << 8;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_ldm_stm (void)
+{
+  /* P, U and L bits are part of bitmask.  */
+  int is_dbmode = (inst.instruction & (1 << 24)) != 0;
+  unsigned offsetbits = inst.operands[1].imm * 2;
+
+  if (inst.operands[1].issingle)
+    {
+      do_vfp_nsyn_ldm_stm (is_dbmode);
+      return;
+    }
+
+  constraint (is_dbmode && !inst.operands[0].writeback,
+              _("writeback (!) must be used for VLDMDB and VSTMDB"));
+
+  constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
+              _("register list must contain at least 1 and at most 16 "
+                "registers"));
+
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[0].writeback << 21;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 22;
+
+  inst.instruction |= offsetbits;
+  
+  do_vfp_cond_or_thumb ();
+}
+
+static void
+do_neon_ldr_str (void)
+{
+  int is_ldr = (inst.instruction & (1 << 20)) != 0;
+  
+  if (inst.operands[0].issingle)
+    {
+      if (is_ldr)
+        do_vfp_nsyn_opcode ("flds");
+      else
+        do_vfp_nsyn_opcode ("fsts");
+    }
+  else
+    {
+      if (is_ldr)
+        do_vfp_nsyn_opcode ("fldd");
+      else
+        do_vfp_nsyn_opcode ("fstd");
+    }
+}
+
+/* "interleave" version also handles non-interleaving register VLD1/VST1
+   instructions.  */
+
+static void
+do_neon_ld_st_interleave (void)
+{
+  struct neon_type_el et = neon_check_type (1, NS_NULL,
+                                            N_8 | N_16 | N_32 | N_64);
+  unsigned alignbits = 0;
+  unsigned idx;
+  /* The bits in this table go:
+     0: register stride of one (0) or two (1)
+     1,2: register list length, minus one (1, 2, 3, 4).
+     3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
+     We use -1 for invalid entries.  */
+  const int typetable[] =
+    {
+      0x7,  -1, 0xa,  -1, 0x6,  -1, 0x2,  -1, /* VLD1 / VST1.  */
+       -1,  -1, 0x8, 0x9,  -1,  -1, 0x3,  -1, /* VLD2 / VST2.  */
+       -1,  -1,  -1,  -1, 0x4, 0x5,  -1,  -1, /* VLD3 / VST3.  */
+       -1,  -1,  -1,  -1,  -1,  -1, 0x0, 0x1  /* VLD4 / VST4.  */
+    };
+  int typebits;
+
+  if (et.type == NT_invtype)
+    return;
+
+  if (inst.operands[1].immisalign)
+    switch (inst.operands[1].imm >> 8)
+      {
+      case 64: alignbits = 1; break;
+      case 128:
+        if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
+          goto bad_alignment;
+        alignbits = 2;
+        break;
+      case 256:
+        if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
+          goto bad_alignment;
+        alignbits = 3;
+        break;
+      default:
+      bad_alignment:
+        first_error (_("bad alignment"));
+        return;
+      }
+
+  inst.instruction |= alignbits << 4;
+  inst.instruction |= neon_logbits (et.size) << 6;
+
+  /* Bits [4:6] of the immediate in a list specifier encode register stride
+     (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
+     VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
+     up the right value for "type" in a table based on this value and the given
+     list style, then stick it back.  */
+  idx = ((inst.operands[0].imm >> 4) & 7)
+        | (((inst.instruction >> 8) & 3) << 3);
+
+  typebits = typetable[idx];
+  
+  constraint (typebits == -1, _("bad list type for instruction"));
+
+  inst.instruction &= ~0xf00;
+  inst.instruction |= typebits << 8;
+}
+
+/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
+   *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
+   otherwise. The variable arguments are a list of pairs of legal (size, align)
+   values, terminated with -1.  */
+
+static int
+neon_alignment_bit (int size, int align, int *do_align, ...)
+{
+  va_list ap;
+  int result = FAIL, thissize, thisalign;
+    
+  if (!inst.operands[1].immisalign)
+    {
+      *do_align = 0;
+      return SUCCESS;
+    }
+      
+  va_start (ap, do_align);
+
+  do
+    {
+      thissize = va_arg (ap, int);
+      if (thissize == -1)
+        break;
+      thisalign = va_arg (ap, int);
+
+      if (size == thissize && align == thisalign)
+        result = SUCCESS;
+    }
+  while (result != SUCCESS);
+
+  va_end (ap);
+
+  if (result == SUCCESS)
+    *do_align = 1;
+  else
+    first_error (_("unsupported alignment for instruction"));
+    
+  return result;
+}
+
+static void
+do_neon_ld_st_lane (void)
+{
+  struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
+  int align_good, do_align = 0;
+  int logsize = neon_logbits (et.size);
+  int align = inst.operands[1].imm >> 8;
+  int n = (inst.instruction >> 8) & 3;
+  int max_el = 64 / et.size;
+  
+  if (et.type == NT_invtype)
+    return;
+  
+  constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
+              _("bad list length"));
+  constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
+              _("scalar index out of range"));
+  constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
+              && et.size == 8,
+              _("stride of 2 unavailable when element size is 8"));
+  
+  switch (n)
+    {
+    case 0:  /* VLD1 / VST1.  */
+      align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
+                                       32, 32, -1);
+      if (align_good == FAIL)
+        return;
+      if (do_align)
+        {
+          unsigned alignbits = 0;
+          switch (et.size)
+            {
+            case 16: alignbits = 0x1; break;
+            case 32: alignbits = 0x3; break;
+            default: ;
+            }
+          inst.instruction |= alignbits << 4;
+        }
+      break;
+
+    case 1:  /* VLD2 / VST2.  */
+      align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
+                                       32, 64, -1);
+      if (align_good == FAIL)
+        return;
+      if (do_align)
+        inst.instruction |= 1 << 4;
+      break;
+
+    case 2:  /* VLD3 / VST3.  */
+      constraint (inst.operands[1].immisalign,
+                  _("can't use alignment with this instruction"));
+      break;
+
+    case 3:  /* VLD4 / VST4.  */
+      align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
+                                       16, 64, 32, 64, 32, 128, -1);
+      if (align_good == FAIL)
+        return;
+      if (do_align)
+        {
+          unsigned alignbits = 0;
+          switch (et.size)
+            {
+            case 8:  alignbits = 0x1; break;
+            case 16: alignbits = 0x1; break;
+            case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
+            default: ;
+            }
+          inst.instruction |= alignbits << 4;
+        }
+      break;
+
+    default: ;
+    }
+
+  /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32.  */
+  if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
+    inst.instruction |= 1 << (4 + logsize);
+      
+  inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
+  inst.instruction |= logsize << 10;
+}
+
+/* Encode single n-element structure to all lanes VLD<n> instructions.  */
+
+static void
+do_neon_ld_dup (void)
+{
+  struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
+  int align_good, do_align = 0;
+
+  if (et.type == NT_invtype)
+    return;
+
+  switch ((inst.instruction >> 8) & 3)
+    {
+    case 0:  /* VLD1.  */
+      assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
+      align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
+                                       &do_align, 16, 16, 32, 32, -1);
+      if (align_good == FAIL)
+        return;
+      switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
+        {
+        case 1: break;
+        case 2: inst.instruction |= 1 << 5; break;
+        default: first_error (_("bad list length")); return;
+        }
+      inst.instruction |= neon_logbits (et.size) << 6;
+      break;
+
+    case 1:  /* VLD2.  */
+      align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
+                                       &do_align, 8, 16, 16, 32, 32, 64, -1);
+      if (align_good == FAIL)
+        return;
+      constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
+                  _("bad list length"));
+      if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
+        inst.instruction |= 1 << 5;
+      inst.instruction |= neon_logbits (et.size) << 6;
+      break;
+
+    case 2:  /* VLD3.  */
+      constraint (inst.operands[1].immisalign,
+                  _("can't use alignment with this instruction"));
+      constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
+                  _("bad list length"));
+      if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
+        inst.instruction |= 1 << 5;
+      inst.instruction |= neon_logbits (et.size) << 6;
+      break;
+
+    case 3:  /* VLD4.  */
+      {
+        int align = inst.operands[1].imm >> 8;
+        align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
+                                         16, 64, 32, 64, 32, 128, -1);
+        if (align_good == FAIL)
+          return;
+        constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
+                    _("bad list length"));
+        if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
+          inst.instruction |= 1 << 5;
+        if (et.size == 32 && align == 128)
+          inst.instruction |= 0x3 << 6;
+        else
+          inst.instruction |= neon_logbits (et.size) << 6;
+      }
+      break;
+
+    default: ;
+    }
+
+  inst.instruction |= do_align << 4;
+}
+
+/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
+   apart from bits [11:4].  */
+
+static void
+do_neon_ldx_stx (void)
+{
+  switch (NEON_LANE (inst.operands[0].imm))
+    {
+    case NEON_INTERLEAVE_LANES:
+      inst.instruction = NEON_ENC_INTERLV (inst.instruction);
+      do_neon_ld_st_interleave ();
+      break;
+    
+    case NEON_ALL_LANES:
+      inst.instruction = NEON_ENC_DUP (inst.instruction);
+      do_neon_ld_dup ();
+      break;
+    
+    default:
+      inst.instruction = NEON_ENC_LANE (inst.instruction);
+      do_neon_ld_st_lane ();
+    }
+
+  /* L bit comes from bit mask.  */
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= inst.operands[1].reg << 16;
+  
+  if (inst.operands[1].postind)
+    {
+      int postreg = inst.operands[1].imm & 0xf;
+      constraint (!inst.operands[1].immisreg,
+                  _("post-index must be a register"));
+      constraint (postreg == 0xd || postreg == 0xf,
+                  _("bad register for post-index"));
+      inst.instruction |= postreg;
+    }
+  else if (inst.operands[1].writeback)
+    {
+      inst.instruction |= 0xd;
+    }
+  else
+    inst.instruction |= 0xf; 
+  
+  if (thumb_mode)
+    inst.instruction |= 0xf9000000;
+  else
+    inst.instruction |= 0xf4000000;
+}
+
 
 /* Overall per-instruction processing.	*/
 
@@ -8045,11 +13785,9 @@ output_relax_insn (void)
   symbolS *sym;
   int offset;
 
-#ifdef OBJ_ELF
   /* The size of the instruction is unknown, so tie the debug info to the
      start of the instruction.  */
   dwarf2_emit_insn (0);
-#endif
 
   switch (inst.reloc.exp.X_op)
     {
@@ -8117,9 +13855,7 @@ output_inst (const char * str)
 		 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
 		 inst.reloc.type);
 
-#ifdef OBJ_ELF
   dwarf2_emit_insn (inst.size);
-#endif
 }
 
 /* Tag values used in struct asm_opcode's tag field.  */
@@ -8130,9 +13866,14 @@ enum opcode_tag
   OT_unconditionalF,	/* Instruction cannot be conditionalized
 			   and carries 0xF in its ARM condition field.  */
   OT_csuffix,		/* Instruction takes a conditional suffix.  */
+  OT_csuffixF,		/* Some forms of the instruction take a conditional
+                           suffix, others place 0xF where the condition field
+                           would be.  */
   OT_cinfix3,		/* Instruction takes a conditional infix,
 			   beginning at character index 3.  (In
 			   unified mode, it becomes a suffix.)  */
+  OT_cinfix3_deprecated, /* The same as OT_cinfix3.  This is used for
+			    tsts, cmps, cmns, and teqs. */
   OT_cinfix3_legacy,	/* Legacy instruction takes a conditional infix at
 			   character index 3, even in unified mode.  Used for
 			   legacy instructions where suffix and infix forms
@@ -8211,27 +13952,46 @@ opcode_lookup (char **str)
   const struct asm_opcode *opcode;
   const struct asm_cond *cond;
   char save[2];
+  bfd_boolean neon_supported;
+  
+  neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1);
 
   /* Scan up to the end of the mnemonic, which must end in white space,
-     '.' (in unified mode only), or end of string.  */
+     '.' (in unified mode, or for Neon instructions), or end of string.  */
   for (base = end = *str; *end != '\0'; end++)
-    if (*end == ' ' || (unified_syntax && *end == '.'))
+    if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.'))
       break;
 
   if (end == base)
     return 0;
 
-  /* Handle a possible width suffix.  */
+  /* Handle a possible width suffix and/or Neon type suffix.  */
   if (end[0] == '.')
     {
-      if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
+      int offset = 2;
+      
+      /* The .w and .n suffixes are only valid if the unified syntax is in
+         use.  */
+      if (unified_syntax && end[1] == 'w')
 	inst.size_req = 4;
-      else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
+      else if (unified_syntax && end[1] == 'n')
 	inst.size_req = 2;
       else
-	return 0;
+        offset = 0;
+
+      inst.vectype.elems = 0;
 
-      *str = end + 2;
+      *str = end + offset;
+
+      if (end[offset] == '.')      
+	{
+	  /* See if we have a Neon type suffix (possible in either unified or
+             non-unified ARM syntax mode).  */
+          if (parse_neon_type (&inst.vectype, str) == FAIL)
+	    return 0;
+        }
+      else if (end[offset] != '\0' && end[offset] != ' ')
+        return 0;
     }
   else
     *str = end;
@@ -8276,12 +14036,14 @@ opcode_lookup (char **str)
 	  break;
 
 	case OT_cinfix3:
+	case OT_cinfix3_deprecated:
 	case OT_odd_infix_unc:
 	  if (!unified_syntax)
 	    return 0;
 	  /* else fall through */
 
 	case OT_csuffix:
+        case OT_csuffixF:
 	case OT_csuf_or_in3:
 	  inst.cond = cond->value;
 	  return opcode;
@@ -8322,11 +14084,16 @@ opcode_lookup (char **str)
   memmove (affix + 2, affix, (end - affix) - 2);
   memcpy (affix, save, 2);
 
-  if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3
-		 || opcode->tag == OT_cinfix3_legacy))
+  if (opcode
+      && (opcode->tag == OT_cinfix3
+	  || opcode->tag == OT_cinfix3_deprecated
+	  || opcode->tag == OT_csuf_or_in3
+	  || opcode->tag == OT_cinfix3_legacy))
     {
       /* step CM */
-      if (unified_syntax && opcode->tag == OT_cinfix3)
+      if (unified_syntax
+	  && (opcode->tag == OT_cinfix3
+	      || opcode->tag == OT_cinfix3_deprecated))
 	as_warn (_("conditional infixes are deprecated in unified syntax"));
 
       inst.cond = cond->value;
@@ -8357,13 +14124,21 @@ md_assemble (char *str)
   if (!opcode)
     {
       /* It wasn't an instruction, but it might be a register alias of
-	 the form alias .req reg.  */
-      if (!create_register_alias (str, p))
+	 the form alias .req reg, or a Neon .dn/.qn directive.  */
+      if (!create_register_alias (str, p)
+          && !create_neon_reg_alias (str, p))
 	as_bad (_("bad instruction `%s'"), str);
 
       return;
     }
 
+  if (opcode->tag == OT_cinfix3_deprecated)
+    as_warn (_("s suffix on comparison instruction is deprecated"));
+
+  /* The value which unconditional instructions should have in place of the
+     condition field.  */
+  inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
+
   if (thumb_mode)
     {
       arm_feature_set variant;
@@ -8387,6 +14162,14 @@ md_assemble (char *str)
 	  return;
 	}
 
+      if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
+	{
+	  /* Implicit require narrow instructions on Thumb-1.  This avoids
+	     relaxation accidentally introducing Thumb-2 instructions.  */
+	  if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
+	    inst.size_req = 2;
+	}
+
       /* Check conditional suffixes.  */
       if (current_it_mask)
 	{
@@ -8428,10 +14211,15 @@ md_assemble (char *str)
 	      return;
 	    }
 	}
+
+      /* Something has gone badly wrong if we try to relax a fixed size
+         instruction.  */
+      assert (inst.size_req == 0 || !inst.relax);
+
       ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
 			      *opcode->tvariant);
       /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
-	 set those bits when Thumb-2 32-bit instuctions are seen.  ie.
+	 set those bits when Thumb-2 32-bit instructions are seen.  ie.
 	 anything other than bl/blx.
 	 This is overly pessimistic for relaxable instructions.  */
       if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
@@ -8439,7 +14227,7 @@ md_assemble (char *str)
 	ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
 				arm_ext_v6t2);
     }
-  else
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
     {
       /* Check that this instruction is supported for this CPU.  */
       if (!opcode->avariant ||
@@ -8472,6 +14260,12 @@ md_assemble (char *str)
 	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
 				*opcode->avariant);
     }
+  else
+    {
+      as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
+		"-- `%s'"), str);
+      return;
+    }
   output_inst (str);
 }
 
@@ -8537,9 +14331,7 @@ arm_frob_label (symbolS * sym)
       label_is_thumb_function_name = FALSE;
     }
 
-#ifdef OBJ_ELF
   dwarf2_emit_label (sym);
-#endif
 }
 
 int
@@ -8573,13 +14365,24 @@ arm_canonicalize_symbol_name (char * name)
    should appear in both upper and lowercase variants.	Some registers
    also have mixed-case names.	*/
 
-#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
+#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
+#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
 #define REGSET(p,t) \
   REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
   REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
   REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
   REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
+#define REGSETH(p,t) \
+  REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
+  REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
+  REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
+  REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
+#define REGSET2(p,t) \
+  REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
+  REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
+  REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
+  REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
 
 static const struct reg_entry reg_names[] =
 {
@@ -8618,24 +14421,24 @@ static const struct reg_entry reg_names[] =
   REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
 
   /* VFP SP registers.	*/
-  REGSET(s,VFS),
-  REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
-  REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
-  REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
-  REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
-
-  REGSET(S,VFS),
-  REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
-  REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
-  REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
-  REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
+  REGSET(s,VFS),  REGSET(S,VFS),
+  REGSETH(s,VFS), REGSETH(S,VFS),
 
   /* VFP DP Registers.	*/
-  REGSET(d,VFD), REGSET(D,VFS),
+  REGSET(d,VFD),  REGSET(D,VFD),
+  /* Extra Neon DP registers.  */
+  REGSETH(d,VFD), REGSETH(D,VFD),
+
+  /* Neon QP registers.  */
+  REGSET2(q,NQ),  REGSET2(Q,NQ),
 
   /* VFP control registers.  */
   REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
   REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
+  REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
+  REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
+  REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
+  REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
 
   /* Maverick DSP coprocessor registers.  */
   REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
@@ -8752,20 +14555,21 @@ static const struct asm_psr psrs[] =
 /* Table of V7M psr names.  */
 static const struct asm_psr v7m_psrs[] =
 {
-  {"apsr",	0 },
-  {"iapsr",	1 },
-  {"eapsr",	2 },
-  {"psr",	3 },
-  {"ipsr",	5 },
-  {"epsr",	6 },
-  {"iepsr",	7 },
-  {"msp",	8 },
-  {"psp",	9 },
-  {"primask",	16},
-  {"basepri",	17},
-  {"basepri_max", 18},
-  {"faultmask",	19},
-  {"control",	20}
+  {"apsr",	  0 }, {"APSR",		0 },
+  {"iapsr",	  1 }, {"IAPSR",	1 },
+  {"eapsr",	  2 }, {"EAPSR",	2 },
+  {"psr",	  3 }, {"PSR",		3 },
+  {"xpsr",	  3 }, {"XPSR",		3 }, {"xPSR",	  3 },
+  {"ipsr",	  5 }, {"IPSR",		5 },
+  {"epsr",	  6 }, {"EPSR",		6 },
+  {"iepsr",	  7 }, {"IEPSR",	7 },
+  {"msp",	  8 }, {"MSP",		8 },
+  {"psp",	  9 }, {"PSP",		9 },
+  {"primask",	  16}, {"PRIMASK",	16},
+  {"basepri",	  17}, {"BASEPRI",	17},
+  {"basepri_max", 18}, {"BASEPRI_MAX",	18},
+  {"faultmask",	  19}, {"FAULTMASK",	19},
+  {"control",	  20}, {"CONTROL",	20}
 };
 
 /* Table of all shift-in-operand names.	 */
@@ -8858,10 +14662,17 @@ static struct asm_barrier_opt barrier_opt_names[] =
 #define TxC3(mnem, op, top, nops, ops, ae, te) \
   { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
     THUMB_VARIANT, do_##ae, do_##te }
+#define TxC3w(mnem, op, top, nops, ops, ae, te) \
+  { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
+    THUMB_VARIANT, do_##ae, do_##te }
 #define TC3(mnem, aop, top, nops, ops, ae, te) \
        TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
+#define TC3w(mnem, aop, top, nops, ops, ae, te) \
+       TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
 #define tC3(mnem, aop, top, nops, ops, ae, te) \
        TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
+#define tC3w(mnem, aop, top, nops, ops, ae, te) \
+       TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
 
 /* Mnemonic with a conditional infix in an unusual place.  Each and every variant has to
    appear in the condition table.  */
@@ -8970,6 +14781,42 @@ static struct asm_barrier_opt barrier_opt_names[] =
 #define UF(mnem, op, nops, ops, ae)	\
   { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
 
+/* Neon data-processing. ARM versions are unconditional with cond=0xf.
+   The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
+   use the same encoding function for each.  */
+#define NUF(mnem, op, nops, ops, enc)					\
+  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op,		\
+    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
+
+/* Neon data processing, version which indirects through neon_enc_tab for
+   the various overloaded versions of opcodes.  */
+#define nUF(mnem, op, nops, ops, enc)					\
+  { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op,	\
+    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
+
+/* Neon insn with conditional suffix for the ARM version, non-overloaded
+   version.  */
+#define NCE_tag(mnem, op, nops, ops, enc, tag)				\
+  { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT,		\
+    THUMB_VARIANT, do_##enc, do_##enc }
+
+#define NCE(mnem, op, nops, ops, enc)					\
+  NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
+
+#define NCEF(mnem, op, nops, ops, enc)					\
+  NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
+
+/* Neon insn with conditional suffix for the ARM version, overloaded types.  */
+#define nCE_tag(mnem, op, nops, ops, enc, tag)				\
+  { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op,		\
+    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
+
+#define nCE(mnem, op, nops, ops, enc)					\
+  nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
+
+#define nCEF(mnem, op, nops, ops, enc)					\
+  nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
+
 #define do_0 0
 
 /* Thumb-only, unconditional.  */
@@ -8985,8 +14832,8 @@ static const struct asm_opcode insns[] =
  tC3(eors,	0300000, eors,	   3, (RR, oRR, SH), arit, t_arit3c),
  tCE(sub,	0400000, sub,	   3, (RR, oRR, SH), arit, t_add_sub),
  tC3(subs,	0500000, subs,	   3, (RR, oRR, SH), arit, t_add_sub),
- tCE(add,	0800000, add,	   3, (RR, oRR, SH), arit, t_add_sub),
- tC3(adds,	0900000, adds,	   3, (RR, oRR, SH), arit, t_add_sub),
+ tCE(add,	0800000, add,	   3, (RR, oRR, SHG), arit, t_add_sub),
+ tC3(adds,	0900000, adds,	   3, (RR, oRR, SHG), arit, t_add_sub),
  tCE(adc,	0a00000, adc,	   3, (RR, oRR, SH), arit, t_arit3c),
  tC3(adcs,	0b00000, adcs,	   3, (RR, oRR, SH), arit, t_arit3c),
  tCE(sbc,	0c00000, sbc,	   3, (RR, oRR, SH), arit, t_arit3),
@@ -9000,13 +14847,13 @@ static const struct asm_opcode insns[] =
     for setting PSR flag bits.  They are obsolete in V6 and do not
     have Thumb equivalents. */
  tCE(tst,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
- tC3(tsts,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
+ tC3w(tsts,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
   CL(tstp,	110f000,     	   2, (RR, SH),      cmp),
  tCE(cmp,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
- tC3(cmps,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
+ tC3w(cmps,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
   CL(cmpp,	150f000,     	   2, (RR, SH),      cmp),
  tCE(cmn,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
- tC3(cmns,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
+ tC3w(cmns,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
   CL(cmnp,	170f000,     	   2, (RR, SH),      cmp),
 
  tCE(mov,	1a00000, mov,	   2, (RR, SH),      mov,  t_mov_cmp),
@@ -9014,10 +14861,10 @@ static const struct asm_opcode insns[] =
  tCE(mvn,	1e00000, mvn,	   2, (RR, SH),      mov,  t_mvn_tst),
  tC3(mvns,	1f00000, mvns,	   2, (RR, SH),      mov,  t_mvn_tst),
 
- tCE(ldr,	4100000, ldr,	   2, (RR, ADDR),    ldst, t_ldst),
- tC3(ldrb,	4500000, ldrb,	   2, (RR, ADDR),    ldst, t_ldst),
- tCE(str,	4000000, str,	   2, (RR, ADDR),    ldst, t_ldst),
- tC3(strb,	4400000, strb,	   2, (RR, ADDR),    ldst, t_ldst),
+ tCE(ldr,	4100000, ldr,	   2, (RR, ADDRGLDR),ldst, t_ldst),
+ tC3(ldrb,	4500000, ldrb,	   2, (RR, ADDRGLDR),ldst, t_ldst),
+ tCE(str,	4000000, str,	   2, (RR, ADDRGLDR),ldst, t_ldst),
+ tC3(strb,	4400000, strb,	   2, (RR, ADDRGLDR),ldst, t_ldst),
 
  tCE(stm,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
  tC3(stmia,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
@@ -9050,6 +14897,10 @@ static const struct asm_opcode insns[] =
  tCE(push,	92d0000, push,     1, (REGLST),	     push_pop, t_push_pop),
  tCE(pop,	8bd0000, pop,	   1, (REGLST),	     push_pop, t_push_pop),
 
+ /* These may simplify to neg.  */
+ TCE(rsb,	0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
+ TC3(rsbs,	0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
+
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6
  TCE(cpy,       1a00000, 4600,     2, (RR, RR),      rd_rm, t_cpy),
@@ -9057,10 +14908,8 @@ static const struct asm_opcode insns[] =
  /* V1 instructions with no Thumb analogue prior to V6T2.  */
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
- TCE(rsb,	0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
- TC3(rsbs,	0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
  TCE(teq,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
- TC3(teqs,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
+ TC3w(teqs,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
   CL(teqp,	130f000,           2, (RR, SH),      cmp),
 
  TC3(ldrt,	4300000, f8500e00, 2, (RR, ADDR),    ldstt, t_ldstt),
@@ -9101,10 +14950,10 @@ static const struct asm_opcode insns[] =
 
   /* Generic coprocessor instructions.	*/
  TCE(cdp,	e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
- TCE(ldc,	c100000, ec100000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
- TC3(ldcl,	c500000, ec500000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
- TCE(stc,	c000000, ec000000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
- TC3(stcl,	c400000, ec400000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
+ TCE(ldc,	c100000, ec100000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
+ TC3(ldcl,	c500000, ec500000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
+ TCE(stc,	c000000, ec000000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
+ TC3(stcl,	c400000, ec400000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
  TCE(mcr,	e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
  TCE(mrc,	e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
 
@@ -9115,8 +14964,8 @@ static const struct asm_opcode insns[] =
 
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v3	/* ARM 6 Status register instructions.	*/
- TCE(mrs,	10f0000, f3ef8000, 2, (RR, PSR),     mrs, t_mrs),
- TCE(msr,	120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
+ TCE(mrs,	10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
+ TCE(msr,	120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
 
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v3m	 /* ARM 7M long multiplies.  */
@@ -9133,12 +14982,12 @@ static const struct asm_opcode insns[] =
 #define ARM_VARIANT &arm_ext_v4	/* ARM Architecture 4.	*/
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v4t
- tC3(ldrh,	01000b0, ldrh,     2, (RR, ADDR), ldstv4, t_ldst),
- tC3(strh,	00000b0, strh,     2, (RR, ADDR), ldstv4, t_ldst),
- tC3(ldrsh,	01000f0, ldrsh,    2, (RR, ADDR), ldstv4, t_ldst),
- tC3(ldrsb,	01000d0, ldrsb,    2, (RR, ADDR), ldstv4, t_ldst),
- tCM(ld,sh,	01000f0, ldrsh,    2, (RR, ADDR), ldstv4, t_ldst),
- tCM(ld,sb,	01000d0, ldrsb,    2, (RR, ADDR), ldstv4, t_ldst),
+ tC3(ldrh,	01000b0, ldrh,     2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tC3(strh,	00000b0, strh,     2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tC3(ldrsh,	01000f0, ldrsh,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tC3(ldrsb,	01000d0, ldrsb,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tCM(ld,sh,	01000f0, ldrsh,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tCM(ld,sb,	01000d0, ldrsb,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
 
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v4t_5
@@ -9159,10 +15008,10 @@ static const struct asm_opcode insns[] =
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
  TCE(clz,	16f0f10, fab0f080, 2, (RRnpc, RRnpc),		        rd_rm,  t_clz),
- TUF(ldc2,	c100000, fc100000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
- TUF(ldc2l,	c500000, fc500000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
- TUF(stc2,	c000000, fc000000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
- TUF(stc2l,	c400000, fc400000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
+ TUF(ldc2,	c100000, fc100000, 3, (RCP, RCN, ADDRGLDC),	        lstc,	lstc),
+ TUF(ldc2l,	c500000, fc500000, 3, (RCP, RCN, ADDRGLDC),		        lstc,	lstc),
+ TUF(stc2,	c000000, fc000000, 3, (RCP, RCN, ADDRGLDC),	        lstc,	lstc),
+ TUF(stc2l,	c400000, fc400000, 3, (RCP, RCN, ADDRGLDC),		        lstc,	lstc),
  TUF(cdp2,	e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
  TUF(mcr2,	e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
  TUF(mrc2,	e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
@@ -9198,8 +15047,8 @@ static const struct asm_opcode insns[] =
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v5e /*  ARM Architecture 5TE.  */
  TUF(pld,	450f000, f810f000, 1, (ADDR),		     pld,  t_pld),
- TC3(ldrd,	00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
- TC3(strd,	00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
+ TC3(ldrd,	00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
+ TC3(strd,	00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
 
  TCE(mcrr,	c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TCE(mrrc,	c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
@@ -9226,6 +15075,7 @@ static const struct asm_opcode insns[] =
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
  TCE(ldrex,	1900f9f, e8500f00, 2, (RRnpc, ADDR),		  ldrex, t_ldrex),
+ TCE(strex,	1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR),	   strex,  t_strex),
  TUF(mcrr2,	c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TUF(mrrc2,	c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
 
@@ -9309,12 +15159,11 @@ static const struct asm_opcode insns[] =
  TCE(smuadx,	700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
  TCE(smusd,	700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
  TCE(smusdx,	700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
- TUF(srsia,	8cd0500, e980c000, 1, (I31w),			   srs,  srs),
-  UF(srsib,	9cd0500,           1, (I31w),			   srs),
-  UF(srsda,	84d0500,	   1, (I31w),			   srs),
- TUF(srsdb,	94d0500, e800c000, 1, (I31w),			   srs,  srs),
+ TUF(srsia,	8c00500, e980c000, 2, (oRRw, I31w),		   srs,  srs),
+  UF(srsib,	9c00500,           2, (oRRw, I31w),		   srs),
+  UF(srsda,	8400500,	   2, (oRRw, I31w),		   srs),
+ TUF(srsdb,	9400500, e800c000, 2, (oRRw, I31w),		   srs,  srs),
  TCE(ssat16,	6a00f30, f3200000, 3, (RRnpc, I16, RRnpc),	   ssat16, t_ssat16),
- TCE(strex,	1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR),	   strex,  t_strex),
  TCE(umaal,	0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,  t_mlal),
  TCE(usad8,	780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc),	   smul,   t_simd),
  TCE(usada8,	7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla,   t_mla),
@@ -9354,18 +15203,20 @@ static const struct asm_opcode insns[] =
  TCE(ubfx,	7e00050, f3c00000, 4, (RR, RR, I31, I32),	   bfx, t_bfx),
 
  TCE(mls,	0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
- TCE(movw,	3000000, f2400000, 2, (RRnpc, Iffff),		    mov16, t_mov16),
- TCE(movt,	3400000, f2c00000, 2, (RRnpc, Iffff),		    mov16, t_mov16),
- TCE(rbit,	3ff0f30, fa90f0a0, 2, (RR, RR),			    rd_rm, t_rbit),
+ TCE(movw,	3000000, f2400000, 2, (RRnpc, HALF),		    mov16, t_mov16),
+ TCE(movt,	3400000, f2c00000, 2, (RRnpc, HALF),		    mov16, t_mov16),
+ TCE(rbit,	6ff0f30, fa90f0a0, 2, (RR, RR),			    rd_rm, t_rbit),
 
  TC3(ldrht,	03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
  TC3(ldrsht,	03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
  TC3(ldrsbt,	03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
  TC3(strht,	02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
 
-  UT(cbnz,      b900,    2, (RR, EXP), t_czb),
-  UT(cbz,       b100,    2, (RR, EXP), t_czb),
- /* ARM does not really have an IT instruction.  */
+  UT(cbnz,      b900,    2, (RR, EXP), t_cbz),
+  UT(cbz,       b100,    2, (RR, EXP), t_cbz),
+ /* ARM does not really have an IT instruction, so always allow it.  */
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v1
  TUE(it,        0, bf08, 1, (COND),    it, t_it),
  TUE(itt,       0, bf0c, 1, (COND),    it, t_it),
  TUE(ite,       0, bf04, 1, (COND),    it, t_it),
@@ -9415,15 +15266,15 @@ static const struct asm_opcode insns[] =
  cCE(wfc,	e400110, 1, (RR),	     rd),
  cCE(rfc,	e500110, 1, (RR),	     rd),
 
- cCL(ldfs,	c100100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(ldfd,	c108100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(ldfe,	c500100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(ldfp,	c508100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(ldfs,	c100100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(ldfd,	c108100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(ldfe,	c500100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(ldfp,	c508100, 2, (RF, ADDRGLDC),  rd_cpaddr),
 
- cCL(stfs,	c000100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(stfd,	c008100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(stfe,	c400100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(stfp,	c408100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(stfs,	c000100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(stfd,	c008100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(stfe,	c400100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(stfp,	c408100, 2, (RF, ADDRGLDC),  rd_cpaddr),
 
  cCL(mvfs,	e008100, 2, (RF, RF_IF),     rd_rm),
  cCL(mvfsp,	e008120, 2, (RF, RF_IF),     rd_rm),
@@ -9866,8 +15717,8 @@ static const struct asm_opcode insns[] =
  cCE(fmxr,	ee00a10, 2, (RVC, RR),	      rn_rd),
 
   /* Memory operations.	 */
- cCE(flds,	d100a00, 2, (RVS, ADDR),      vfp_sp_ldst),
- cCE(fsts,	d000a00, 2, (RVS, ADDR),      vfp_sp_ldst),
+ cCE(flds,	d100a00, 2, (RVS, ADDRGLDC),  vfp_sp_ldst),
+ cCE(fsts,	d000a00, 2, (RVS, ADDRGLDC),  vfp_sp_ldst),
  cCE(fldmias,	c900a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
  cCE(fldmfds,	c900a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
  cCE(fldmdbs,	d300a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
@@ -9910,13 +15761,13 @@ static const struct asm_opcode insns[] =
 #undef ARM_VARIANT
 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision).  */
   /* Moves and type conversions.  */
- cCE(fcpyd,	eb00b40, 2, (RVD, RVD),	      rd_rm),
+ cCE(fcpyd,	eb00b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
  cCE(fcvtds,	eb70ac0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
  cCE(fcvtsd,	eb70bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
- cCE(fmdhr,	e200b10, 2, (RVD, RR),	      rn_rd),
- cCE(fmdlr,	e000b10, 2, (RVD, RR),	      rn_rd),
- cCE(fmrdh,	e300b10, 2, (RR, RVD),	      rd_rn),
- cCE(fmrdl,	e100b10, 2, (RR, RVD),	      rd_rn),
+ cCE(fmdhr,	e200b10, 2, (RVD, RR),	      vfp_dp_rn_rd),
+ cCE(fmdlr,	e000b10, 2, (RVD, RR),	      vfp_dp_rn_rd),
+ cCE(fmrdh,	e300b10, 2, (RR, RVD),	      vfp_dp_rd_rn),
+ cCE(fmrdl,	e100b10, 2, (RR, RVD),	      vfp_dp_rd_rn),
  cCE(fsitod,	eb80bc0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
  cCE(fuitod,	eb80b40, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
  cCE(ftosid,	ebd0b40, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
@@ -9925,8 +15776,8 @@ static const struct asm_opcode insns[] =
  cCE(ftouizd,	ebc0bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
 
   /* Memory operations.	 */
- cCE(fldd,	d100b00, 2, (RVD, ADDR),      vfp_dp_ldst),
- cCE(fstd,	d000b00, 2, (RVD, ADDR),      vfp_dp_ldst),
+ cCE(fldd,	d100b00, 2, (RVD, ADDRGLDC),  vfp_dp_ldst),
+ cCE(fstd,	d000b00, 2, (RVD, ADDRGLDC),  vfp_dp_ldst),
  cCE(fldmiad,	c900b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
  cCE(fldmfdd,	c900b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
  cCE(fldmdbd,	d300b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
@@ -9937,34 +15788,347 @@ static const struct asm_opcode insns[] =
  cCE(fstmfdd,	d200b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
 
   /* Monadic operations.  */
- cCE(fabsd,	eb00bc0, 2, (RVD, RVD),	      rd_rm),
- cCE(fnegd,	eb10b40, 2, (RVD, RVD),	      rd_rm),
- cCE(fsqrtd,	eb10bc0, 2, (RVD, RVD),	      rd_rm),
+ cCE(fabsd,	eb00bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
+ cCE(fnegd,	eb10b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
+ cCE(fsqrtd,	eb10bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
 
   /* Dyadic operations.	 */
- cCE(faddd,	e300b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fsubd,	e300b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fmuld,	e200b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fdivd,	e800b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fmacd,	e000b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fmscd,	e100b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fnmuld,	e200b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fnmacd,	e000b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fnmscd,	e100b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(faddd,	e300b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fsubd,	e300b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fmuld,	e200b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fdivd,	e800b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fmacd,	e000b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fmscd,	e100b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fnmuld,	e200b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fnmacd,	e000b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fnmscd,	e100b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
 
   /* Comparisons.  */
- cCE(fcmpd,	eb40b40, 2, (RVD, RVD),	      rd_rm),
- cCE(fcmpzd,	eb50b40, 1, (RVD),	      rd),
- cCE(fcmped,	eb40bc0, 2, (RVD, RVD),	      rd_rm),
- cCE(fcmpezd,	eb50bc0, 1, (RVD),	      rd),
+ cCE(fcmpd,	eb40b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
+ cCE(fcmpzd,	eb50b40, 1, (RVD),	      vfp_dp_rd),
+ cCE(fcmped,	eb40bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
+ cCE(fcmpezd,	eb50bc0, 1, (RVD),	      vfp_dp_rd),
 
 #undef ARM_VARIANT
 #define ARM_VARIANT &fpu_vfp_ext_v2
  cCE(fmsrr,	c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
  cCE(fmrrs,	c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
- cCE(fmdrr,	c400b10, 3, (RVD, RR, RR),    rm_rd_rn),
- cCE(fmrrd,	c500b10, 3, (RR, RR, RVD),    rd_rn_rm),
+ cCE(fmdrr,	c400b10, 3, (RVD, RR, RR),    vfp_dp_rm_rd_rn),
+ cCE(fmrrd,	c500b10, 3, (RR, RR, RVD),    vfp_dp_rd_rn_rm),
+
+/* Instructions which may belong to either the Neon or VFP instruction sets.
+   Individual encoder functions perform additional architecture checks.  */
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_ext_v1xd
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_vfp_ext_v1xd
+  /* These mnemonics are unique to VFP.  */
+ NCE(vsqrt,     0,       2, (RVSD, RVSD),       vfp_nsyn_sqrt),
+ NCE(vdiv,      0,       3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
+ nCE(vnmul,     vnmul,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
+ nCE(vnmla,     vnmla,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
+ nCE(vnmls,     vnmls,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
+ nCE(vcmp,      vcmp,    2, (RVSD, RVSD_I0),    vfp_nsyn_cmp),
+ nCE(vcmpe,     vcmpe,   2, (RVSD, RVSD_I0),    vfp_nsyn_cmp),
+ NCE(vpush,     0,       1, (VRSDLST),          vfp_nsyn_push),
+ NCE(vpop,      0,       1, (VRSDLST),          vfp_nsyn_pop),
+ NCE(vcvtz,     0,       2, (RVSD, RVSD),       vfp_nsyn_cvtz),
+
+  /* Mnemonics shared by Neon and VFP.  */
+ nCEF(vmul,     vmul,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
+ nCEF(vmla,     vmla,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
+ nCEF(vmls,     vmls,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
+
+ nCEF(vadd,     vadd,    3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
+ nCEF(vsub,     vsub,    3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
+
+ NCEF(vabs,     1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
+ NCEF(vneg,     1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
+
+ NCE(vldm,      c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vldmia,    c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vldmdb,    d100b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vstm,      c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vstmia,    c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vstmdb,    d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vldr,      d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
+ NCE(vstr,      d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
+
+ nCEF(vcvt,     vcvt,    3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
+
+  /* NOTE: All VMOV encoding is special-cased!  */
+ NCE(vmov,      0,       1, (VMOV), neon_mov),
+ NCE(vmovq,     0,       1, (VMOV), neon_mov),
 
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_neon_ext_v1
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_neon_ext_v1
+  /* Data processing with three registers of the same length.  */
+  /* integer ops, valid types S8 S16 S32 U8 U16 U32.  */
+ NUF(vaba,      0000710, 3, (RNDQ, RNDQ,  RNDQ), neon_dyadic_i_su),
+ NUF(vabaq,     0000710, 3, (RNQ,  RNQ,   RNQ),  neon_dyadic_i_su),
+ NUF(vhadd,     0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
+ NUF(vhaddq,    0000000, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
+ NUF(vrhadd,    0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
+ NUF(vrhaddq,   0000100, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
+ NUF(vhsub,     0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
+ NUF(vhsubq,    0000200, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
+  /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64.  */
+ NUF(vqadd,     0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
+ NUF(vqaddq,    0000010, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i64_su),
+ NUF(vqsub,     0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
+ NUF(vqsubq,    0000210, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i64_su),
+ NUF(vrshl,     0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
+ NUF(vrshlq,    0000500, 3, (RNQ,  oRNQ,  RNQ),  neon_rshl),
+ NUF(vqrshl,    0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
+ NUF(vqrshlq,   0000510, 3, (RNQ,  oRNQ,  RNQ),  neon_rshl),
+  /* If not immediate, fall back to neon_dyadic_i64_su.
+     shl_imm should accept I8 I16 I32 I64,
+     qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64.  */
+ nUF(vshl,      vshl,    3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
+ nUF(vshlq,     vshl,    3, (RNQ,  oRNQ,  RNDQ_I63b), neon_shl_imm),
+ nUF(vqshl,     vqshl,   3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
+ nUF(vqshlq,    vqshl,   3, (RNQ,  oRNQ,  RNDQ_I63b), neon_qshl_imm),
+  /* Logic ops, types optional & ignored.  */
+ nUF(vand,      vand,    2, (RNDQ, NILO),        neon_logic),
+ nUF(vandq,     vand,    2, (RNQ,  NILO),        neon_logic),
+ nUF(vbic,      vbic,    2, (RNDQ, NILO),        neon_logic),
+ nUF(vbicq,     vbic,    2, (RNQ,  NILO),        neon_logic),
+ nUF(vorr,      vorr,    2, (RNDQ, NILO),        neon_logic),
+ nUF(vorrq,     vorr,    2, (RNQ,  NILO),        neon_logic),
+ nUF(vorn,      vorn,    2, (RNDQ, NILO),        neon_logic),
+ nUF(vornq,     vorn,    2, (RNQ,  NILO),        neon_logic),
+ nUF(veor,      veor,    3, (RNDQ, oRNDQ, RNDQ), neon_logic),
+ nUF(veorq,     veor,    3, (RNQ,  oRNQ,  RNQ),  neon_logic),
+  /* Bitfield ops, untyped.  */
+ NUF(vbsl,      1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
+ NUF(vbslq,     1100110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
+ NUF(vbit,      1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
+ NUF(vbitq,     1200110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
+ NUF(vbif,      1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
+ NUF(vbifq,     1300110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
+  /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32.  */
+ nUF(vabd,      vabd,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
+ nUF(vabdq,     vabd,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
+ nUF(vmax,      vmax,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
+ nUF(vmaxq,     vmax,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
+ nUF(vmin,      vmin,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
+ nUF(vminq,     vmin,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
+  /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
+     back to neon_dyadic_if_su.  */
+ nUF(vcge,      vcge,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
+ nUF(vcgeq,     vcge,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp),
+ nUF(vcgt,      vcgt,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
+ nUF(vcgtq,     vcgt,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp),
+ nUF(vclt,      vclt,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
+ nUF(vcltq,     vclt,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp_inv),
+ nUF(vcle,      vcle,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
+ nUF(vcleq,     vcle,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp_inv),
+  /* Comparison. Type I8 I16 I32 F32.  */
+ nUF(vceq,      vceq,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
+ nUF(vceqq,     vceq,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_ceq),
+  /* As above, D registers only.  */
+ nUF(vpmax,     vpmax,   3, (RND, oRND, RND), neon_dyadic_if_su_d),
+ nUF(vpmin,     vpmin,   3, (RND, oRND, RND), neon_dyadic_if_su_d),
+  /* Int and float variants, signedness unimportant.  */
+ nUF(vmlaq,     vmla,    3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mac_maybe_scalar),
+ nUF(vmlsq,     vmls,    3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mac_maybe_scalar),
+ nUF(vpadd,     vpadd,   3, (RND,  oRND,  RND),       neon_dyadic_if_i_d),
+  /* Add/sub take types I8 I16 I32 I64 F32.  */
+ nUF(vaddq,     vadd,    3, (RNQ,  oRNQ,  RNQ),  neon_addsub_if_i),
+ nUF(vsubq,     vsub,    3, (RNQ,  oRNQ,  RNQ),  neon_addsub_if_i),
+  /* vtst takes sizes 8, 16, 32.  */
+ NUF(vtst,      0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
+ NUF(vtstq,     0000810, 3, (RNQ,  oRNQ,  RNQ),  neon_tst),
+  /* VMUL takes I8 I16 I32 F32 P8.  */
+ nUF(vmulq,     vmul,     3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mul),
+  /* VQD{R}MULH takes S16 S32.  */
+ nUF(vqdmulh,   vqdmulh,  3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
+ nUF(vqdmulhq,  vqdmulh,  3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qdmulh),
+ nUF(vqrdmulh,  vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
+ nUF(vqrdmulhq, vqrdmulh, 3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qdmulh),
+ NUF(vacge,     0000e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
+ NUF(vacgeq,    0000e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute),
+ NUF(vacgt,     0200e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
+ NUF(vacgtq,    0200e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute),
+ NUF(vaclt,     0200e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
+ NUF(vacltq,    0200e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute_inv),
+ NUF(vacle,     0000e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
+ NUF(vacleq,    0000e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute_inv),
+ NUF(vrecps,    0000f10,  3, (RNDQ, oRNDQ, RNDQ), neon_step),
+ NUF(vrecpsq,   0000f10,  3, (RNQ,  oRNQ,  RNQ),  neon_step),
+ NUF(vrsqrts,   0200f10,  3, (RNDQ, oRNDQ, RNDQ), neon_step),
+ NUF(vrsqrtsq,  0200f10,  3, (RNQ,  oRNQ,  RNQ),  neon_step),
+
+  /* Two address, int/float. Types S8 S16 S32 F32.  */
+ NUF(vabsq,     1b10300, 2, (RNQ,  RNQ),      neon_abs_neg),
+ NUF(vnegq,     1b10380, 2, (RNQ,  RNQ),      neon_abs_neg),
+
+  /* Data processing with two registers and a shift amount.  */
+  /* Right shifts, and variants with rounding.
+     Types accepted S8 S16 S32 S64 U8 U16 U32 U64.  */
+ NUF(vshr,      0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
+ NUF(vshrq,     0800010, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
+ NUF(vrshr,     0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
+ NUF(vrshrq,    0800210, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
+ NUF(vsra,      0800110, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
+ NUF(vsraq,     0800110, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
+ NUF(vrsra,     0800310, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
+ NUF(vrsraq,    0800310, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
+  /* Shift and insert. Sizes accepted 8 16 32 64.  */
+ NUF(vsli,      1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
+ NUF(vsliq,     1800510, 3, (RNQ,  oRNQ,  I63), neon_sli),
+ NUF(vsri,      1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
+ NUF(vsriq,     1800410, 3, (RNQ,  oRNQ,  I64), neon_sri),
+  /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64.  */
+ NUF(vqshlu,    1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
+ NUF(vqshluq,   1800610, 3, (RNQ,  oRNQ,  I63), neon_qshlu_imm),
+  /* Right shift immediate, saturating & narrowing, with rounding variants.
+     Types accepted S16 S32 S64 U16 U32 U64.  */
+ NUF(vqshrn,    0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
+ NUF(vqrshrn,   0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
+  /* As above, unsigned. Types accepted S16 S32 S64.  */
+ NUF(vqshrun,   0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
+ NUF(vqrshrun,  0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
+  /* Right shift narrowing. Types accepted I16 I32 I64.  */
+ NUF(vshrn,     0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
+ NUF(vrshrn,    0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
+  /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant.  */
+ nUF(vshll,     vshll,   3, (RNQ, RND, I32),  neon_shll),
+  /* CVT with optional immediate for fixed-point variant.  */
+ nUF(vcvtq,     vcvt,    3, (RNQ, RNQ, oI32b), neon_cvt),
+
+ nUF(vmvn,      vmvn,    2, (RNDQ, RNDQ_IMVNb), neon_mvn),
+ nUF(vmvnq,     vmvn,    2, (RNQ,  RNDQ_IMVNb), neon_mvn),
+
+  /* Data processing, three registers of different lengths.  */
+  /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32.  */
+ NUF(vabal,     0800500, 3, (RNQ, RND, RND),  neon_abal),
+ NUF(vabdl,     0800700, 3, (RNQ, RND, RND),  neon_dyadic_long),
+ NUF(vaddl,     0800000, 3, (RNQ, RND, RND),  neon_dyadic_long),
+ NUF(vsubl,     0800200, 3, (RNQ, RND, RND),  neon_dyadic_long),
+  /* If not scalar, fall back to neon_dyadic_long.
+     Vector types as above, scalar types S16 S32 U16 U32.  */
+ nUF(vmlal,     vmlal,   3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
+ nUF(vmlsl,     vmlsl,   3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
+  /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32.  */
+ NUF(vaddw,     0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
+ NUF(vsubw,     0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
+  /* Dyadic, narrowing insns. Types I16 I32 I64.  */
+ NUF(vaddhn,    0800400, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
+ NUF(vraddhn,   1800400, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
+ NUF(vsubhn,    0800600, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
+ NUF(vrsubhn,   1800600, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
+  /* Saturating doubling multiplies. Types S16 S32.  */
+ nUF(vqdmlal,   vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
+ nUF(vqdmlsl,   vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
+ nUF(vqdmull,   vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
+  /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
+     S16 S32 U16 U32.  */
+ nUF(vmull,     vmull,   3, (RNQ, RND, RND_RNSC), neon_vmull),
+
+  /* Extract. Size 8.  */
+ NUF(vext,      0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
+ NUF(vextq,     0b00000, 4, (RNQ,  oRNQ,  RNQ,  I15), neon_ext),
+
+  /* Two registers, miscellaneous.  */
+  /* Reverse. Sizes 8 16 32 (must be < size in opcode).  */
+ NUF(vrev64,    1b00000, 2, (RNDQ, RNDQ),     neon_rev),
+ NUF(vrev64q,   1b00000, 2, (RNQ,  RNQ),      neon_rev),
+ NUF(vrev32,    1b00080, 2, (RNDQ, RNDQ),     neon_rev),
+ NUF(vrev32q,   1b00080, 2, (RNQ,  RNQ),      neon_rev),
+ NUF(vrev16,    1b00100, 2, (RNDQ, RNDQ),     neon_rev),
+ NUF(vrev16q,   1b00100, 2, (RNQ,  RNQ),      neon_rev),
+  /* Vector replicate. Sizes 8 16 32.  */
+ nCE(vdup,      vdup,    2, (RNDQ, RR_RNSC),  neon_dup),
+ nCE(vdupq,     vdup,    2, (RNQ,  RR_RNSC),  neon_dup),
+  /* VMOVL. Types S8 S16 S32 U8 U16 U32.  */
+ NUF(vmovl,     0800a10, 2, (RNQ, RND),       neon_movl),
+  /* VMOVN. Types I16 I32 I64.  */
+ nUF(vmovn,     vmovn,   2, (RND, RNQ),       neon_movn),
+  /* VQMOVN. Types S16 S32 S64 U16 U32 U64.  */
+ nUF(vqmovn,    vqmovn,  2, (RND, RNQ),       neon_qmovn),
+  /* VQMOVUN. Types S16 S32 S64.  */
+ nUF(vqmovun,   vqmovun, 2, (RND, RNQ),       neon_qmovun),
+  /* VZIP / VUZP. Sizes 8 16 32.  */
+ NUF(vzip,      1b20180, 2, (RNDQ, RNDQ),     neon_zip_uzp),
+ NUF(vzipq,     1b20180, 2, (RNQ,  RNQ),      neon_zip_uzp),
+ NUF(vuzp,      1b20100, 2, (RNDQ, RNDQ),     neon_zip_uzp),
+ NUF(vuzpq,     1b20100, 2, (RNQ,  RNQ),      neon_zip_uzp),
+  /* VQABS / VQNEG. Types S8 S16 S32.  */
+ NUF(vqabs,     1b00700, 2, (RNDQ, RNDQ),     neon_sat_abs_neg),
+ NUF(vqabsq,    1b00700, 2, (RNQ,  RNQ),      neon_sat_abs_neg),
+ NUF(vqneg,     1b00780, 2, (RNDQ, RNDQ),     neon_sat_abs_neg),
+ NUF(vqnegq,    1b00780, 2, (RNQ,  RNQ),      neon_sat_abs_neg),
+  /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32.  */
+ NUF(vpadal,    1b00600, 2, (RNDQ, RNDQ),     neon_pair_long),
+ NUF(vpadalq,   1b00600, 2, (RNQ,  RNQ),      neon_pair_long),
+ NUF(vpaddl,    1b00200, 2, (RNDQ, RNDQ),     neon_pair_long),
+ NUF(vpaddlq,   1b00200, 2, (RNQ,  RNQ),      neon_pair_long),
+  /* Reciprocal estimates. Types U32 F32.  */
+ NUF(vrecpe,    1b30400, 2, (RNDQ, RNDQ),     neon_recip_est),
+ NUF(vrecpeq,   1b30400, 2, (RNQ,  RNQ),      neon_recip_est),
+ NUF(vrsqrte,   1b30480, 2, (RNDQ, RNDQ),     neon_recip_est),
+ NUF(vrsqrteq,  1b30480, 2, (RNQ,  RNQ),      neon_recip_est),
+  /* VCLS. Types S8 S16 S32.  */
+ NUF(vcls,      1b00400, 2, (RNDQ, RNDQ),     neon_cls),
+ NUF(vclsq,     1b00400, 2, (RNQ,  RNQ),      neon_cls),
+  /* VCLZ. Types I8 I16 I32.  */
+ NUF(vclz,      1b00480, 2, (RNDQ, RNDQ),     neon_clz),
+ NUF(vclzq,     1b00480, 2, (RNQ,  RNQ),      neon_clz),
+  /* VCNT. Size 8.  */
+ NUF(vcnt,      1b00500, 2, (RNDQ, RNDQ),     neon_cnt),
+ NUF(vcntq,     1b00500, 2, (RNQ,  RNQ),      neon_cnt),
+  /* Two address, untyped.  */
+ NUF(vswp,      1b20000, 2, (RNDQ, RNDQ),     neon_swp),
+ NUF(vswpq,     1b20000, 2, (RNQ,  RNQ),      neon_swp),
+  /* VTRN. Sizes 8 16 32.  */
+ nUF(vtrn,      vtrn,    2, (RNDQ, RNDQ),     neon_trn),
+ nUF(vtrnq,     vtrn,    2, (RNQ,  RNQ),      neon_trn),
+
+  /* Table lookup. Size 8.  */
+ NUF(vtbl,      1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
+ NUF(vtbx,      1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
+  /* Neon element/structure load/store.  */
+ nUF(vld1,      vld1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vst1,      vst1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vld2,      vld2,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vst2,      vst2,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vld3,      vld3,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vst3,      vst3,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vld4,      vld4,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vst4,      vst4,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_vfp_ext_v3
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_ext_v3
+ cCE(fconsts,   eb00a00, 2, (RVS, I255),      vfp_sp_const),
+ cCE(fconstd,   eb00b00, 2, (RVD, I255),      vfp_dp_const),
+ cCE(fshtos,    eba0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
+ cCE(fshtod,    eba0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
+ cCE(fsltos,    eba0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
+ cCE(fsltod,    eba0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
+ cCE(fuhtos,    ebb0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
+ cCE(fuhtod,    ebb0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
+ cCE(fultos,    ebb0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
+ cCE(fultod,    ebb0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
+ cCE(ftoshs,    ebe0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
+ cCE(ftoshd,    ebe0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
+ cCE(ftosls,    ebe0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
+ cCE(ftosld,    ebe0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
+ cCE(ftouhs,    ebf0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
+ cCE(ftouhd,    ebf0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
+ cCE(ftouls,    ebf0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
+ cCE(ftould,    ebf0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
+
+#undef THUMB_VARIANT
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions.	 */
  cCE(mia,	e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
@@ -9996,7 +16160,7 @@ static const struct asm_opcode insns[] =
  cCE(tinsrb,	e600010, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
  cCE(tinsrh,	e600050, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
  cCE(tinsrw,	e600090, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
- cCE(tmcr,	e000110, 2, (RIWC, RR),		    rn_rd),
+ cCE(tmcr,	e000110, 2, (RIWC_RIWG, RR),	    rn_rd),
  cCE(tmcrr,	c400000, 3, (RIWR, RR, RR),	    rm_rd_rn),
  cCE(tmia,	e200010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
  cCE(tmiaph,	e280010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
@@ -10007,7 +16171,7 @@ static const struct asm_opcode insns[] =
  cCE(tmovmskb,	e100030, 2, (RR, RIWR),		    rd_rn),
  cCE(tmovmskh,	e500030, 2, (RR, RIWR),		    rd_rn),
  cCE(tmovmskw,	e900030, 2, (RR, RIWR),		    rd_rn),
- cCE(tmrc,	e100110, 2, (RR, RIWC),		    rd_rn),
+ cCE(tmrc,	e100110, 2, (RR, RIWC_RIWG),	    rd_rn),
  cCE(tmrrc,	c500000, 3, (RR, RR, RIWR),	    rd_rn_rm),
  cCE(torcb,	e13f150, 1, (RR),		    iwmmxt_tandorc),
  cCE(torch,	e53f150, 1, (RR),		    iwmmxt_tandorc),
@@ -10078,34 +16242,34 @@ static const struct asm_opcode insns[] =
  cCE(wpackwus,	e900080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wpackdss,	ef00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wpackdus,	ed00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
- cCE(wrorh,	e700040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrorh,	e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wrorhg,	e700148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wrorw,	eb00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrorw,	eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wrorwg,	eb00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wrord,	ef00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrord,	ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wrordg,	ef00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
  cCE(wsadb,	e000120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wsadbz,	e100120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wsadh,	e400120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wsadhz,	e500120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wshufh,	e0001e0, 3, (RIWR, RIWR, I255),	    iwmmxt_wshufh),
- cCE(wsllh,	e500040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsllh,	e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsllhg,	e500148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsllw,	e900040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsllw,	e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsllwg,	e900148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wslld,	ed00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wslld,	ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wslldg,	ed00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrah,	e400040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrah,	e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrahg,	e400148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsraw,	e800040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsraw,	e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrawg,	e800148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrad,	ec00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrad,	ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsradg,	ec00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrlh,	e600040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrlh,	e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrlhg,	e600148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrlw,	ea00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrlw,	ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrlwg,	ea00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrld,	ee00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrld,	ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrldg,	ee00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
  cCE(wstrb,	c000000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
  cCE(wstrh,	c400000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
@@ -10142,15 +16306,75 @@ static const struct asm_opcode insns[] =
  cCE(wzero,	e300000, 1, (RIWR),		    iwmmxt_wzero),
 
 #undef ARM_VARIANT
+#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2.  */
+ cCE(torvscb,   e13f190, 1, (RR),		    iwmmxt_tandorc),
+ cCE(torvsch,   e53f190, 1, (RR),		    iwmmxt_tandorc),
+ cCE(torvscw,   e93f190, 1, (RR),		    iwmmxt_tandorc),
+ cCE(wabsb,     e2001c0, 2, (RIWR, RIWR),           rd_rn),
+ cCE(wabsh,     e6001c0, 2, (RIWR, RIWR),           rd_rn),
+ cCE(wabsw,     ea001c0, 2, (RIWR, RIWR),           rd_rn),
+ cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddhc,    e600180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddwc,    ea00180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wavg4,	e400000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wavg4r,    e500000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddsn,   ee00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddsx,   eb00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddun,   ec00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddux,   e900100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmerge,    e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
+ cCE(wmiabb,    e0000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiabt,    e1000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiatb,    e2000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiatt,    e3000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiabbn,   e4000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiabtn,   e5000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiatbn,   e6000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiattn,   e7000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbb,   e800120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbt,   e900120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawtb,   ea00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawtt,   eb00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbbn,  ec00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbtn,  ed00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawtbn,  ee00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawttn,  ef00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulsmr,   ef00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulumr,   ed00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwumr,  ec000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwsmr,  ee000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwum,   ed000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwsm,   ef000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwl,    eb000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabb,   e8000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabt,   e9000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiatb,   ea000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiatt,   eb000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabbn,  ec000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabtn,  ed000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiatbn,  ee000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiattn,  ef000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulm,    e100080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulmr,   e300080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulwm,   ec000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulwmr,  ee000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+
+#undef ARM_VARIANT
 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions.	*/
- cCE(cfldrs,	c100400, 2, (RMF, ADDR),	      rd_cpaddr),
- cCE(cfldrd,	c500400, 2, (RMD, ADDR),	      rd_cpaddr),
- cCE(cfldr32,	c100500, 2, (RMFX, ADDR),	      rd_cpaddr),
- cCE(cfldr64,	c500500, 2, (RMDX, ADDR),	      rd_cpaddr),
- cCE(cfstrs,	c000400, 2, (RMF, ADDR),	      rd_cpaddr),
- cCE(cfstrd,	c400400, 2, (RMD, ADDR),	      rd_cpaddr),
- cCE(cfstr32,	c000500, 2, (RMFX, ADDR),	      rd_cpaddr),
- cCE(cfstr64,	c400500, 2, (RMDX, ADDR),	      rd_cpaddr),
+ cCE(cfldrs,	c100400, 2, (RMF, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfldrd,	c500400, 2, (RMD, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfldr32,	c100500, 2, (RMFX, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfldr64,	c500500, 2, (RMDX, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfstrs,	c000400, 2, (RMF, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfstrd,	c400400, 2, (RMD, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfstr32,	c000500, 2, (RMFX, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfstr64,	c400500, 2, (RMDX, ADDRGLDC),	      rd_cpaddr),
  cCE(cfmvsr,	e000450, 2, (RMF, RR),		      rn_rd),
  cCE(cfmvrs,	e100450, 2, (RR, RMF),		      rd_rn),
  cCE(cfmvdlr,	e000410, 2, (RMD, RR),		      rn_rd),
@@ -10235,6 +16459,10 @@ static const struct asm_opcode insns[] =
 #undef UE
 #undef UF
 #undef UT
+#undef NUF
+#undef nUF
+#undef NCE
+#undef nCE
 #undef OPS0
 #undef OPS1
 #undef OPS2
@@ -10428,7 +16656,10 @@ md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
 	  insn = THUMB_OP32 (opcode);
 	  insn |= (old_op & 0xf0) << 4;
 	  put_thumb32_insn (buf, insn);
-	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	  if (opcode == T_MNEM_add_pc)
+	    reloc_type = BFD_RELOC_ARM_T32_IMM12;
+	  else
+	    reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
 	}
       else
 	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
@@ -10445,7 +16676,10 @@ md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
 	  insn |= (old_op & 0xf0) << 4;
 	  insn |= (old_op & 0xf) << 16;
 	  put_thumb32_insn (buf, insn);
-	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	  if (insn & (1 << 20))
+	    reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
+	  else
+	    reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
 	}
       else
 	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
@@ -10479,16 +16713,42 @@ relax_immediate (fragS *fragp, int size, int shift)
   offset = fragp->fr_offset;
   /* Force misaligned offsets to 32-bit variant.  */
   if (offset & low)
-    return -4;
+    return 4;
   if (offset & ~mask)
     return 4;
   return 2;
 }
 
+/* Get the address of a symbol during relaxation.  */
+static addressT
+relaxed_symbol_addr(fragS *fragp, long stretch)
+{
+  fragS *sym_frag;
+  addressT addr;
+  symbolS *sym;
+
+  sym = fragp->fr_symbol;
+  sym_frag = symbol_get_frag (sym);
+  know (S_GET_SEGMENT (sym) != absolute_section
+	|| sym_frag == &zero_address_frag);
+  addr = S_GET_VALUE (sym) + fragp->fr_offset;
+
+  /* If frag has yet to be reached on this pass, assume it will
+     move by STRETCH just as we did.  If this is not so, it will
+     be because some frag between grows, and that will force
+     another pass.  */
+
+  if (stretch != 0
+      && sym_frag->relax_marker != fragp->relax_marker)
+    addr += stretch;
+
+  return addr;
+}
+
 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
    load.  */
 static int
-relax_adr (fragS *fragp, asection *sec)
+relax_adr (fragS *fragp, asection *sec, long stretch)
 {
   addressT addr;
   offsetT val;
@@ -10498,14 +16758,12 @@ relax_adr (fragS *fragp, asection *sec)
       || sec != S_GET_SEGMENT (fragp->fr_symbol))
     return 4;
 
-  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  val = relaxed_symbol_addr(fragp, stretch);
   addr = fragp->fr_address + fragp->fr_fix;
   addr = (addr + 4) & ~3;
-  /* Fix the insn as the 4-byte version if the target address is not
-     sufficiently aligned.  This is prevents an infinite loop when two
-     instructions have contradictory range/alignment requirements.  */
+  /* Force misaligned targets to 32-bit variant.  */
   if (val & 3)
-    return -4;
+    return 4;
   val -= addr;
   if (val < 0 || val > 1020)
     return 4;
@@ -10532,7 +16790,7 @@ relax_addsub (fragS *fragp, asection *sec)
    size of the offset field in the narrow instruction.  */
 
 static int
-relax_branch (fragS *fragp, asection *sec, int bits)
+relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
 {
   addressT addr;
   offsetT val;
@@ -10543,7 +16801,7 @@ relax_branch (fragS *fragp, asection *sec, int bits)
       || sec != S_GET_SEGMENT (fragp->fr_symbol))
     return 4;
 
-  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  val = relaxed_symbol_addr(fragp, stretch);
   addr = fragp->fr_address + fragp->fr_fix + 4;
   val -= addr;
 
@@ -10559,7 +16817,7 @@ relax_branch (fragS *fragp, asection *sec, int bits)
    the current size of the frag should change.  */
 
 int
-arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
+arm_relax_frag (asection *sec, fragS *fragp, long stretch)
 {
   int oldsize;
   int newsize;
@@ -10568,7 +16826,7 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
   switch (fragp->fr_subtype)
     {
     case T_MNEM_ldr_pc2:
-      newsize = relax_adr(fragp, sec);
+      newsize = relax_adr(fragp, sec, stretch);
       break;
     case T_MNEM_ldr_pc:
     case T_MNEM_ldr_sp:
@@ -10588,7 +16846,7 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
       newsize = relax_immediate(fragp, 5, 0);
       break;
     case T_MNEM_adr:
-      newsize = relax_adr(fragp, sec);
+      newsize = relax_adr(fragp, sec, stretch);
       break;
     case T_MNEM_mov:
     case T_MNEM_movs:
@@ -10597,10 +16855,10 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
       newsize = relax_immediate(fragp, 8, 0);
       break;
     case T_MNEM_b:
-      newsize = relax_branch(fragp, sec, 11);
+      newsize = relax_branch(fragp, sec, 11, stretch);
       break;
     case T_MNEM_bcond:
-      newsize = relax_branch(fragp, sec, 8);
+      newsize = relax_branch(fragp, sec, 8, stretch);
       break;
     case T_MNEM_add_sp:
     case T_MNEM_add_pc:
@@ -10619,14 +16877,18 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
     default:
       abort();
     }
-  if (newsize < 0)
+
+  fragp->fr_var = newsize;
+  /* Freeze wide instructions that are at or before the same location as
+     in the previous pass.  This avoids infinite loops.
+     Don't freeze them unconditionally because targets may be artificialy
+     misaligned by the expansion of preceeding frags.  */
+  if (stretch <= 0 && newsize > 2)
     {
-      fragp->fr_var = -newsize;
       md_convert_frag (sec->owner, sec, fragp);
       frag_wane(fragp);
-      return -(newsize + oldsize);
     }
-  fragp->fr_var = newsize;
+
   return newsize - oldsize;
 }
 
@@ -10636,12 +16898,22 @@ valueT
 md_section_align (segT	 segment ATTRIBUTE_UNUSED,
 		  valueT size)
 {
-#ifdef OBJ_ELF
-  return size;
-#else
-  /* Round all sects to multiple of 4.	*/
-  return (size + 3) & ~3;
+#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
+  if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
+    {
+      /* For a.out, force the section size to be aligned.  If we don't do
+	 this, BFD will align it for us, but it will not write out the
+	 final bytes of the section.  This may be a bug in BFD, but it is
+	 easier to fix it here since that is how the other a.out targets
+	 work.  */
+      int align;
+
+      align = bfd_get_section_alignment (stdoutput, segment);
+      size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
+    }
 #endif
+
+  return size;
 }
 
 /* This is called from HANDLE_ALIGN in write.c.	 Fill in the contents
@@ -10893,7 +17165,7 @@ finish_unwind_opcodes (void)
 
   if (unwind.fp_used)
     {
-      /* Adjust sp as neccessary.  */
+      /* Adjust sp as necessary.  */
       unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
       flush_pending_unwind ();
 
@@ -11141,12 +17413,22 @@ create_unwind_entry (int have_data)
   return 0;
 }
 
+
+/* Initialize the DWARF-2 unwind information for this procedure.  */
+
+void
+tc_arm_frame_initial_instructions (void)
+{
+  cfi_add_CFA_def_cfa (REG_SP, 0);
+}
+#endif /* OBJ_ELF */
+
 /* Convert REGNAME to a DWARF-2 register number.  */
 
 int
-tc_arm_regname_to_dw2regnum (const char *regname)
+tc_arm_regname_to_dw2regnum (char *regname)
 {
-  int reg = arm_reg_parse ((char **) &regname, REG_TYPE_RN);
+  int reg = arm_reg_parse (&regname, REG_TYPE_RN);
 
   if (reg == FAIL)
     return -1;
@@ -11154,15 +17436,18 @@ tc_arm_regname_to_dw2regnum (const char *regname)
   return reg;
 }
 
-/* Initialize the DWARF-2 unwind information for this procedure.  */
-
+#ifdef TE_PE
 void
-tc_arm_frame_initial_instructions (void)
+tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
 {
-  cfi_add_CFA_def_cfa (REG_SP, 0);
-}
-#endif /* OBJ_ELF */
+  expressionS expr;
 
+  expr.X_op = O_secrel;
+  expr.X_add_symbol = symbol;
+  expr.X_add_number = 0;
+  emit_expr (&expr, size);
+}
+#endif
 
 /* MD interface: Symbol and relocation handling.  */
 
@@ -11179,10 +17464,16 @@ md_pcrel_from_section (fixS * fixP, segT seg)
 
   /* If this is pc-relative and we are going to emit a relocation
      then we just want to put out any pipeline compensation that the linker
-     will need.  Otherwise we want to use the calculated base.  */
+     will need.  Otherwise we want to use the calculated base.
+     For WinCE we skip the bias for externals as well, since this
+     is how the MS ARM-CE assembler behaves and we want to be compatible.  */
   if (fixP->fx_pcrel 
       && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
-	  || arm_force_relocation (fixP)))
+	  || (arm_force_relocation (fixP)
+#ifdef TE_WINCE
+	      && !S_IS_EXTERNAL (fixP->fx_addsy)
+#endif
+	      )))
     base = 0;
 
   switch (fixP->fx_r_type)
@@ -11219,6 +17510,17 @@ md_pcrel_from_section (fixS * fixP, segT seg)
     case BFD_RELOC_ARM_PCREL_BLX:
     case BFD_RELOC_ARM_PLT32:
 #ifdef TE_WINCE
+      /* When handling fixups immediately, because we have already 
+         discovered the value of a symbol, or the address of the frag involved
+	 we must account for the offset by +8, as the OS loader will never see the reloc.
+         see fixup_segment() in write.c
+         The S_IS_EXTERNAL test handles the case of global symbols.
+         Those need the calculated base, not just the pipe compensation the linker will need.  */
+      if (fixP->fx_pcrel
+	  && fixP->fx_addsy != NULL
+	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+	  && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
+	return base + 8;
       return base;
 #else
       return base + 8;
@@ -11406,11 +17708,11 @@ negate_data_op (unsigned long * instruction,
 /* Like negate_data_op, but for Thumb-2.   */
 
 static unsigned int
-thumb32_negate_data_op (offsetT *instruction, offsetT value)
+thumb32_negate_data_op (offsetT *instruction, unsigned int value)
 {
   int op, new_inst;
   int rd;
-  offsetT negated, inverted;
+  unsigned int negated, inverted;
 
   negated = encode_thumb32_immediate (-value);
   inverted = encode_thumb32_immediate (~value);
@@ -11471,7 +17773,7 @@ thumb32_negate_data_op (offsetT *instruction, offsetT value)
       return FAIL;
     }
 
-  if (value == FAIL)
+  if (value == (unsigned int)FAIL)
     return FAIL;
 
   *instruction &= T2_OPCODE_MASK;
@@ -11528,6 +17830,7 @@ md_apply_fix (fixS *	fixP,
   assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
 
   /* Note whether this will delete the relocation.  */
+
   if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
     fixP->fx_done = 1;
 
@@ -11676,7 +17979,7 @@ md_apply_fix (fixS *	fixP,
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("invalid literal constant: pool needs to be closer"));
 	  else
-	    as_bad (_("bad immediate value for half-word offset (%ld)"),
+	    as_bad (_("bad immediate value for 8-bit offset (%ld)"),
 		    (long) value);
 	  break;
 	}
@@ -11835,6 +18138,7 @@ md_apply_fix (fixS *	fixP,
       break;
 
     case BFD_RELOC_ARM_T32_IMMEDIATE:
+    case BFD_RELOC_ARM_T32_ADD_IMM:
     case BFD_RELOC_ARM_T32_IMM12:
     case BFD_RELOC_ARM_T32_ADD_PC12:
       /* We claim that this fixup has been processed here,
@@ -11855,15 +18159,21 @@ md_apply_fix (fixS *	fixP,
       newval <<= 16;
       newval |= md_chars_to_number (buf+2, THUMB_SIZE);
 
-      /* FUTURE: Implement analogue of negate_data_op for T32.  */
-      if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
+      newimm = FAIL;
+      if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
+	  || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
 	{
 	  newimm = encode_thumb32_immediate (value);
 	  if (newimm == (unsigned int) FAIL)
 	    newimm = thumb32_negate_data_op (&newval, value);
 	}
-      else
+      if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
+	  && newimm == (unsigned int) FAIL)
 	{
+	  /* Turn add/sum into addw/subw.  */
+	  if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
+	    newval = (newval & 0xfeffffff) | 0x02000000;
+
 	  /* 12 bit immediate for addw/subw.  */
 	  if (value < 0)
 	    {
@@ -11977,18 +18287,34 @@ md_apply_fix (fixS *	fixP,
 	}
       break;
 
-    case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
-      /* CZB can only branch forward.  */
-      if (value & ~0x7e)
-	as_bad_where (fixP->fx_file, fixP->fx_line,
-		      _("branch out of range"));
+    case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
+      /* CBZ can only branch forward.  */
 
-      if (fixP->fx_done || !seg->use_rela_p)
+      /* Attempts to use CBZ to branch to the next instruction
+         (which, strictly speaking, are prohibited) will be turned into
+         no-ops.
+
+	 FIXME: It may be better to remove the instruction completely and
+	 perform relaxation.  */
+      if (value == -2)
 	{
 	  newval = md_chars_to_number (buf, THUMB_SIZE);
-	  newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
+	  newval = 0xbf00; /* NOP encoding T1 */
 	  md_number_to_chars (buf, newval, THUMB_SIZE);
 	}
+      else
+	{
+	  if (value & ~0x7e)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+		          _("branch out of range"));
+
+          if (fixP->fx_done || !seg->use_rela_p)
+	    {
+	      newval = md_chars_to_number (buf, THUMB_SIZE);
+	      newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
+	      md_number_to_chars (buf, newval, THUMB_SIZE);
+	    }
+	}
       break;
 
     case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch.	*/
@@ -12129,8 +18455,15 @@ md_apply_fix (fixS *	fixP,
     case BFD_RELOC_ARM_ROSEGREL32:
     case BFD_RELOC_ARM_SBREL32:
     case BFD_RELOC_32_PCREL:
+#ifdef TE_PE
+    case BFD_RELOC_32_SECREL:
+#endif
       if (fixP->fx_done || !seg->use_rela_p)
-	md_number_to_chars (buf, value, 4);
+#ifdef TE_WINCE
+	/* For WinCE we only do this for pcrel fixups.  */
+	if (fixP->fx_done || fixP->fx_pcrel)
+#endif
+	  md_number_to_chars (buf, value, 4);
       break;
 
 #ifdef OBJ_ELF
@@ -12165,8 +18498,6 @@ md_apply_fix (fixS *	fixP,
 	newval = get_thumb32_insn (buf);
       newval &= 0xff7fff00;
       newval |= (value >> 2) | (sign ? INDEX_UP : 0);
-      if (value == 0)
-	newval &= ~WRITE_BACK;
       if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
 	  || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
 	md_number_to_chars (buf, newval, INSN_SIZE);
@@ -12358,6 +18689,216 @@ md_apply_fix (fixS *	fixP,
       fixP->fx_done = 0;
       return;
 
+    case BFD_RELOC_ARM_MOVW:
+    case BFD_RELOC_ARM_MOVT:
+    case BFD_RELOC_ARM_THUMB_MOVW:
+    case BFD_RELOC_ARM_THUMB_MOVT:
+      if (fixP->fx_done || !seg->use_rela_p)
+	{
+	  /* REL format relocations are limited to a 16-bit addend.  */
+	  if (!fixP->fx_done)
+	    {
+	      if (value < -0x1000 || value > 0xffff)
+		  as_bad_where (fixP->fx_file, fixP->fx_line,
+				_("offset too big"));
+	    }
+	  else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
+		   || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
+	    {
+	      value >>= 16;
+	    }
+
+	  if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
+	      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
+	    {
+	      newval = get_thumb32_insn (buf);
+	      newval &= 0xfbf08f00;
+	      newval |= (value & 0xf000) << 4;
+	      newval |= (value & 0x0800) << 15;
+	      newval |= (value & 0x0700) << 4;
+	      newval |= (value & 0x00ff);
+	      put_thumb32_insn (buf, newval);
+	    }
+	  else
+	    {
+	      newval = md_chars_to_number (buf, 4);
+	      newval &= 0xfff0f000;
+	      newval |= value & 0x0fff;
+	      newval |= (value & 0xf000) << 4;
+	      md_number_to_chars (buf, newval, 4);
+	    }
+	}
+      return;
+
+   case BFD_RELOC_ARM_ALU_PC_G0_NC:
+   case BFD_RELOC_ARM_ALU_PC_G0:
+   case BFD_RELOC_ARM_ALU_PC_G1_NC:
+   case BFD_RELOC_ARM_ALU_PC_G1:
+   case BFD_RELOC_ARM_ALU_PC_G2:
+   case BFD_RELOC_ARM_ALU_SB_G0_NC:
+   case BFD_RELOC_ARM_ALU_SB_G0:
+   case BFD_RELOC_ARM_ALU_SB_G1_NC:
+   case BFD_RELOC_ARM_ALU_SB_G1:
+   case BFD_RELOC_ARM_ALU_SB_G2:
+     assert (!fixP->fx_done);
+     if (!seg->use_rela_p)
+       {
+         bfd_vma insn;
+         bfd_vma encoded_addend;
+         bfd_vma addend_abs = abs (value);
+
+         /* Check that the absolute value of the addend can be
+            expressed as an 8-bit constant plus a rotation.  */
+         encoded_addend = encode_arm_immediate (addend_abs);
+         if (encoded_addend == (unsigned int) FAIL)
+	   as_bad_where (fixP->fx_file, fixP->fx_line,
+	                 _("the offset 0x%08lX is not representable"),
+                         (unsigned long) addend_abs);
+
+         /* Extract the instruction.  */
+         insn = md_chars_to_number (buf, INSN_SIZE);
+
+         /* If the addend is positive, use an ADD instruction.
+            Otherwise use a SUB.  Take care not to destroy the S bit.  */
+         insn &= 0xff1fffff;
+         if (value < 0)
+           insn |= 1 << 22;
+         else
+           insn |= 1 << 23;
+
+         /* Place the encoded addend into the first 12 bits of the
+            instruction.  */
+         insn &= 0xfffff000;
+         insn |= encoded_addend;
+   
+         /* Update the instruction.  */  
+         md_number_to_chars (buf, insn, INSN_SIZE);
+       }
+     break;
+
+    case BFD_RELOC_ARM_LDR_PC_G0:
+    case BFD_RELOC_ARM_LDR_PC_G1:
+    case BFD_RELOC_ARM_LDR_PC_G2:
+    case BFD_RELOC_ARM_LDR_SB_G0:
+    case BFD_RELOC_ARM_LDR_SB_G1:
+    case BFD_RELOC_ARM_LDR_SB_G2:
+      assert (!fixP->fx_done);
+      if (!seg->use_rela_p)
+        {
+          bfd_vma insn;
+          bfd_vma addend_abs = abs (value);
+
+          /* Check that the absolute value of the addend can be
+             encoded in 12 bits.  */
+          if (addend_abs >= 0x1000)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+	  	          _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
+                          (unsigned long) addend_abs);
+
+          /* Extract the instruction.  */
+          insn = md_chars_to_number (buf, INSN_SIZE);
+
+          /* If the addend is negative, clear bit 23 of the instruction.
+             Otherwise set it.  */
+          if (value < 0)
+            insn &= ~(1 << 23);
+          else
+            insn |= 1 << 23;
+
+          /* Place the absolute value of the addend into the first 12 bits
+             of the instruction.  */
+          insn &= 0xfffff000;
+          insn |= addend_abs;
+    
+          /* Update the instruction.  */  
+          md_number_to_chars (buf, insn, INSN_SIZE);
+        }
+      break;
+
+    case BFD_RELOC_ARM_LDRS_PC_G0:
+    case BFD_RELOC_ARM_LDRS_PC_G1:
+    case BFD_RELOC_ARM_LDRS_PC_G2:
+    case BFD_RELOC_ARM_LDRS_SB_G0:
+    case BFD_RELOC_ARM_LDRS_SB_G1:
+    case BFD_RELOC_ARM_LDRS_SB_G2:
+      assert (!fixP->fx_done);
+      if (!seg->use_rela_p)
+        {
+          bfd_vma insn;
+          bfd_vma addend_abs = abs (value);
+
+          /* Check that the absolute value of the addend can be
+             encoded in 8 bits.  */
+          if (addend_abs >= 0x100)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+	  	          _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
+                          (unsigned long) addend_abs);
+
+          /* Extract the instruction.  */
+          insn = md_chars_to_number (buf, INSN_SIZE);
+
+          /* If the addend is negative, clear bit 23 of the instruction.
+             Otherwise set it.  */
+          if (value < 0)
+            insn &= ~(1 << 23);
+          else
+            insn |= 1 << 23;
+
+          /* Place the first four bits of the absolute value of the addend
+             into the first 4 bits of the instruction, and the remaining
+             four into bits 8 .. 11.  */
+          insn &= 0xfffff0f0;
+          insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
+    
+          /* Update the instruction.  */  
+          md_number_to_chars (buf, insn, INSN_SIZE);
+        }
+      break;
+
+    case BFD_RELOC_ARM_LDC_PC_G0:
+    case BFD_RELOC_ARM_LDC_PC_G1:
+    case BFD_RELOC_ARM_LDC_PC_G2:
+    case BFD_RELOC_ARM_LDC_SB_G0:
+    case BFD_RELOC_ARM_LDC_SB_G1:
+    case BFD_RELOC_ARM_LDC_SB_G2:
+      assert (!fixP->fx_done);
+      if (!seg->use_rela_p)
+        {
+          bfd_vma insn;
+          bfd_vma addend_abs = abs (value);
+
+          /* Check that the absolute value of the addend is a multiple of
+             four and, when divided by four, fits in 8 bits.  */
+          if (addend_abs & 0x3)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+	  	          _("bad offset 0x%08lX (must be word-aligned)"),
+                          (unsigned long) addend_abs);
+
+          if ((addend_abs >> 2) > 0xff)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+	  	          _("bad offset 0x%08lX (must be an 8-bit number of words)"),
+                          (unsigned long) addend_abs);
+
+          /* Extract the instruction.  */
+          insn = md_chars_to_number (buf, INSN_SIZE);
+
+          /* If the addend is negative, clear bit 23 of the instruction.
+             Otherwise set it.  */
+          if (value < 0)
+            insn &= ~(1 << 23);
+          else
+            insn |= 1 << 23;
+
+          /* Place the addend (divided by four) into the first eight
+             bits of the instruction.  */
+          insn &= 0xfffffff0;
+          insn |= addend_abs >> 2;
+    
+          /* Update the instruction.  */  
+          md_number_to_chars (buf, insn, INSN_SIZE);
+        }
+      break;
+
     case BFD_RELOC_UNUSED:
     default:
       as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -12412,6 +18953,34 @@ tc_gen_reloc (asection *section, fixS *fixp)
 	  break;
 	}
 
+    case BFD_RELOC_ARM_MOVW:
+      if (fixp->fx_pcrel)
+	{
+	  code = BFD_RELOC_ARM_MOVW_PCREL;
+	  break;
+	}
+
+    case BFD_RELOC_ARM_MOVT:
+      if (fixp->fx_pcrel)
+	{
+	  code = BFD_RELOC_ARM_MOVT_PCREL;
+	  break;
+	}
+
+    case BFD_RELOC_ARM_THUMB_MOVW:
+      if (fixp->fx_pcrel)
+	{
+	  code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
+	  break;
+	}
+
+    case BFD_RELOC_ARM_THUMB_MOVT:
+      if (fixp->fx_pcrel)
+	{
+	  code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
+	  break;
+	}
+
     case BFD_RELOC_NONE:
     case BFD_RELOC_ARM_PCREL_BRANCH:
     case BFD_RELOC_ARM_PCREL_BLX:
@@ -12425,6 +18994,9 @@ tc_gen_reloc (asection *section, fixS *fixp)
     case BFD_RELOC_THUMB_PCREL_BLX:
     case BFD_RELOC_VTABLE_ENTRY:
     case BFD_RELOC_VTABLE_INHERIT:
+#ifdef TE_PE
+    case BFD_RELOC_32_SECREL:
+#endif
       code = fixp->fx_r_type;
       break;
 
@@ -12449,6 +19021,34 @@ tc_gen_reloc (asection *section, fixS *fixp)
     case BFD_RELOC_ARM_TLS_LDO32:
     case BFD_RELOC_ARM_PCREL_CALL:
     case BFD_RELOC_ARM_PCREL_JUMP:
+    case BFD_RELOC_ARM_ALU_PC_G0_NC:
+    case BFD_RELOC_ARM_ALU_PC_G0:
+    case BFD_RELOC_ARM_ALU_PC_G1_NC:
+    case BFD_RELOC_ARM_ALU_PC_G1:
+    case BFD_RELOC_ARM_ALU_PC_G2:
+    case BFD_RELOC_ARM_LDR_PC_G0:
+    case BFD_RELOC_ARM_LDR_PC_G1:
+    case BFD_RELOC_ARM_LDR_PC_G2:
+    case BFD_RELOC_ARM_LDRS_PC_G0:
+    case BFD_RELOC_ARM_LDRS_PC_G1:
+    case BFD_RELOC_ARM_LDRS_PC_G2:
+    case BFD_RELOC_ARM_LDC_PC_G0:
+    case BFD_RELOC_ARM_LDC_PC_G1:
+    case BFD_RELOC_ARM_LDC_PC_G2:
+    case BFD_RELOC_ARM_ALU_SB_G0_NC:
+    case BFD_RELOC_ARM_ALU_SB_G0:
+    case BFD_RELOC_ARM_ALU_SB_G1_NC:
+    case BFD_RELOC_ARM_ALU_SB_G1:
+    case BFD_RELOC_ARM_ALU_SB_G2:
+    case BFD_RELOC_ARM_LDR_SB_G0:
+    case BFD_RELOC_ARM_LDR_SB_G1:
+    case BFD_RELOC_ARM_LDR_SB_G2:
+    case BFD_RELOC_ARM_LDRS_SB_G0:
+    case BFD_RELOC_ARM_LDRS_SB_G1:
+    case BFD_RELOC_ARM_LDRS_SB_G2:
+    case BFD_RELOC_ARM_LDC_SB_G0:
+    case BFD_RELOC_ARM_LDC_SB_G1:
+    case BFD_RELOC_ARM_LDC_SB_G2:
       code = fixp->fx_r_type;
       break;
 
@@ -12579,6 +19179,14 @@ cons_fix_new_arm (fragS *	frag,
       break;
     }
 
+#ifdef TE_PE
+  if (exp->X_op == O_secrel)
+  {
+    exp->X_op = O_symbol;
+    type = BFD_RELOC_32_SECREL;
+  }
+#endif
+
   fix_new_exp (frag, where, (int) size, exp, pcrel, type);
 }
 
@@ -12612,34 +19220,31 @@ arm_force_relocation (struct fix * fixp)
   if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
       || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
       || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
+      || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
       || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
       || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
       || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
     return 0;
 
-  return generic_force_reloc (fixp);
-}
-
-#ifdef OBJ_COFF
-/* This is a little hack to help the gas/arm/adrl.s test.  It prevents
-   local labels from being added to the output symbol table when they
-   are used with the ADRL pseudo op.  The ADRL relocation should always
-   be resolved before the binbary is emitted, so it is safe to say that
-   it is adjustable.  */
+  /* Always leave these relocations for the linker.  */
+  if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
+       && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
+      || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
+    return 1;
 
-bfd_boolean
-arm_fix_adjustable (fixS * fixP)
-{
-  if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
+  /* Always generate relocations against function symbols.  */
+  if (fixp->fx_r_type == BFD_RELOC_32
+      && fixp->fx_addsy
+      && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
     return 1;
-  return 0;
+
+  return generic_force_reloc (fixp);
 }
-#endif
 
-#ifdef OBJ_ELF
-/* Relocations against Thumb function names must be left unadjusted,
-   so that the linker can use this information to correctly set the
-   bottom bit of their addresses.  The MIPS version of this function
+#if defined (OBJ_ELF) || defined (OBJ_COFF)
+/* Relocations against function names must be left unadjusted,
+   so that the linker can use this information to generate interworking
+   stubs.  The MIPS version of this function
    also prevents relocations that are mips-16 specific, but I do not
    know why it does this.
 
@@ -12656,6 +19261,10 @@ arm_fix_adjustable (fixS * fixP)
   if (fixP->fx_addsy == NULL)
     return 1;
 
+  /* Preserve relocations against symbols with function type.  */
+  if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
+    return 0;
+
   if (THUMB_IS_FUNC (fixP->fx_addsy)
       && fixP->fx_subsy == NULL)
     return 0;
@@ -12677,8 +19286,17 @@ arm_fix_adjustable (fixS * fixP)
       || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
     return 0;
 
+  /* Similarly for group relocations.  */
+  if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
+       && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
+      || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
+    return 0;
+
   return 1;
 }
+#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
+
+#ifdef OBJ_ELF
 
 const char *
 elf32_arm_target_format (void)
@@ -12789,14 +19407,15 @@ arm_adjust_symtab (void)
 	  elf_sym = elf_symbol (symbol_get_bfdsym (sym));
 	  bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
 
-	  if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
+	  if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
+		BFD_ARM_SPECIAL_SYM_TYPE_ANY))
 	    {
 	      /* If it's a .thumb_func, declare it as so,
 		 otherwise tag label as .code 16.  */
 	      if (THUMB_IS_FUNC (sym))
 		elf_sym->internal_elf_sym.st_info =
 		  ELF_ST_INFO (bind, STT_ARM_TFUNC);
-	      else
+	      else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
 		elf_sym->internal_elf_sym.st_info =
 		  ELF_ST_INFO (bind, STT_ARM_16BIT);
 	    }
@@ -12817,6 +19436,16 @@ set_constant_flonums (void)
       abort ();
 }
 
+/* Auto-select Thumb mode if it's the only available instruction set for the
+   given architecture.  */
+
+static void
+autoselect_thumb_from_cpu_variant (void)
+{
+  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
+    opcode_select (16);
+}
+
 void
 md_begin (void)
 {
@@ -12894,9 +19523,9 @@ md_begin (void)
 
   if (!mfpu_opt)
     {
-      if (!mcpu_cpu_opt)
+      if (mcpu_cpu_opt != NULL)
 	mfpu_opt = &fpu_default;
-      else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
+      else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
 	mfpu_opt = &fpu_arch_vfp_v2;
       else
 	mfpu_opt = &fpu_arch_fpa;
@@ -12917,6 +19546,8 @@ md_begin (void)
 
   ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
 
+  autoselect_thumb_from_cpu_variant ();
+
   arm_arch_used = thumb_arch_used = arm_arch_none;
 
 #if defined OBJ_COFF || defined OBJ_ELF
@@ -12992,7 +19623,9 @@ md_begin (void)
 #endif
 
   /* Record the CPU type as well.  */
-  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
+    mach = bfd_mach_arm_iWMMXt2;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
     mach = bfd_mach_arm_iWMMXt;
   else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
     mach = bfd_mach_arm_XScale;
@@ -13362,13 +19995,16 @@ static const struct arm_cpu_option_table arm_cpus[] =
   {"arm1156t2f-s",	ARM_ARCH_V6T2,	 FPU_ARCH_VFP_V2, NULL},
   {"arm1176jz-s",	ARM_ARCH_V6ZK,	 FPU_NONE,	  NULL},
   {"arm1176jzf-s",	ARM_ARCH_V6ZK,	 FPU_ARCH_VFP_V2, NULL},
-  {"cortex-a8",		ARM_ARCH_V7A,	 FPU_ARCH_VFP_V2, NULL},
+  {"cortex-a8",		ARM_ARCH_V7A,	 ARM_FEATURE(0, FPU_VFP_V3
+                                                        | FPU_NEON_EXT_V1),
+                                                          NULL},
   {"cortex-r4",		ARM_ARCH_V7R,	 FPU_NONE,	  NULL},
   {"cortex-m3",		ARM_ARCH_V7M,	 FPU_NONE,	  NULL},
   /* ??? XSCALE is really an architecture.  */
   {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
   /* ??? iwmmxt is not a processor.  */
   {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
+  {"iwmmxt2",		ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
   {"i80200",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
   /* Maverick */
   {"ep9312",	ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
@@ -13413,11 +20049,17 @@ static const struct arm_arch_option_table arm_archs[] =
   {"armv6zt2",		ARM_ARCH_V6ZT2,	 FPU_ARCH_VFP},
   {"armv6zkt2",		ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
   {"armv7",		ARM_ARCH_V7,	 FPU_ARCH_VFP},
+  /* The official spelling of the ARMv7 profile variants is the dashed form.
+     Accept the non-dashed form for compatibility with old toolchains.  */
   {"armv7a",		ARM_ARCH_V7A,	 FPU_ARCH_VFP},
   {"armv7r",		ARM_ARCH_V7R,	 FPU_ARCH_VFP},
   {"armv7m",		ARM_ARCH_V7M,	 FPU_ARCH_VFP},
+  {"armv7-a",		ARM_ARCH_V7A,	 FPU_ARCH_VFP},
+  {"armv7-r",		ARM_ARCH_V7R,	 FPU_ARCH_VFP},
+  {"armv7-m",		ARM_ARCH_V7M,	 FPU_ARCH_VFP},
   {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP},
   {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
+  {"iwmmxt2",		ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
   {NULL,		ARM_ARCH_NONE,	 ARM_ARCH_NONE}
 };
 
@@ -13433,6 +20075,7 @@ static const struct arm_option_cpu_value_table arm_extensions[] =
   {"maverick",		ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
   {"xscale",		ARM_FEATURE (0, ARM_CEXT_XSCALE)},
   {"iwmmxt",		ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
+  {"iwmmxt2",		ARM_FEATURE (0, ARM_CEXT_IWMMXT2)},
   {NULL,		ARM_ARCH_NONE}
 };
 
@@ -13452,6 +20095,7 @@ static const struct arm_option_cpu_value_table arm_fpus[] =
   {"softvfp+vfp",	FPU_ARCH_VFP_V2},
   {"vfp",		FPU_ARCH_VFP_V2},
   {"vfp9",		FPU_ARCH_VFP_V2},
+  {"vfp3",              FPU_ARCH_VFP_V3},
   {"vfp10",		FPU_ARCH_VFP_V2},
   {"vfp10-r0",		FPU_ARCH_VFP_V1},
   {"vfpxd",		FPU_ARCH_VFP_V1xD},
@@ -13460,6 +20104,7 @@ static const struct arm_option_cpu_value_table arm_fpus[] =
   {"arm1136jfs",	FPU_ARCH_VFP_V2},
   {"arm1136jf-s",	FPU_ARCH_VFP_V2},
   {"maverick",		FPU_ARCH_MAVERICK},
+  {"neon",              FPU_ARCH_VFP_V3_PLUS_NEON_V1},
   {NULL,		ARM_ARCH_NONE}
 };
 
@@ -13855,7 +20500,13 @@ aeabi_set_public_attributes (void)
   ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
   ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
   ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
-  
+  /*Allow the user to override the reported architecture.  */
+  if (object_arch)
+    {
+      ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
+      ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
+    }
+
   tmp = flags;
   arch = 0;
   for (p = cpu_arch_ver; p->val; p++)
@@ -13881,57 +20532,56 @@ aeabi_set_public_attributes (void)
 	  for (i = 0; p[i]; i++)
 	    p[i] = TOUPPER (p[i]);
 	}
-      elf32_arm_add_eabi_attr_string (stdoutput, 5, p);
+      bfd_elf_add_proc_attr_string (stdoutput, 5, p);
     }
   /* Tag_CPU_arch.  */
-  elf32_arm_add_eabi_attr_int (stdoutput, 6, arch);
+  bfd_elf_add_proc_attr_int (stdoutput, 6, arch);
   /* Tag_CPU_arch_profile.  */
   if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
-    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'A');
+    bfd_elf_add_proc_attr_int (stdoutput, 7, 'A');
   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
-    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'R');
+    bfd_elf_add_proc_attr_int (stdoutput, 7, 'R');
   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
-    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'M');
+    bfd_elf_add_proc_attr_int (stdoutput, 7, 'M');
   /* Tag_ARM_ISA_use.  */
   if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
-    elf32_arm_add_eabi_attr_int (stdoutput, 8, 1);
+    bfd_elf_add_proc_attr_int (stdoutput, 8, 1);
   /* Tag_THUMB_ISA_use.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
-    elf32_arm_add_eabi_attr_int (stdoutput, 9,
+    bfd_elf_add_proc_attr_int (stdoutput, 9,
 	ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
   /* Tag_VFP_arch.  */
-  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v2)
-      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v2))
-    elf32_arm_add_eabi_attr_int (stdoutput, 10, 2);
-  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v1)
-	   || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v1))
-    elf32_arm_add_eabi_attr_int (stdoutput, 10, 1);
+  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
+      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3))
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 3);
+  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2)
+           || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2))
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 2);
+  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1)
+           || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1)
+           || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd)
+           || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd))
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 1);
   /* Tag_WMMX_arch.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
       || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
-    elf32_arm_add_eabi_attr_int (stdoutput, 11, 1);
+    bfd_elf_add_proc_attr_int (stdoutput, 11, 1);
+  /* Tag_NEON_arch.  */
+  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1)
+      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1))
+    bfd_elf_add_proc_attr_int (stdoutput, 12, 1);
 }
 
-/* Add the .ARM.attributes section.  */
+/* Add the default contents for the .ARM.attributes section.  */
 void
 arm_md_end (void)
 {
-  segT s;
-  char *p;
-  addressT addr;
-  offsetT size;
-  
   if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
     return;
 
   aeabi_set_public_attributes ();
-  size = elf32_arm_eabi_attr_size (stdoutput);
-  s = subseg_new (".ARM.attributes", 0);
-  bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
-  addr = frag_now_fix ();
-  p = frag_more (size);
-  elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size);
 }
+#endif /* OBJ_ELF */
 
 
 /* Parse a .cpu directive.  */
@@ -14009,6 +20659,37 @@ s_arm_arch (int ignored ATTRIBUTE_UNUSED)
 }
 
 
+/* Parse a .object_arch directive.  */
+
+static void
+s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
+{
+  const struct arm_arch_option_table *opt;
+  char saved_char;
+  char *name;
+
+  name = input_line_pointer;
+  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+    input_line_pointer++;
+  saved_char = *input_line_pointer;
+  *input_line_pointer = 0;
+
+  /* Skip the first "all" entry.  */
+  for (opt = arm_archs + 1; opt->name != NULL; opt++)
+    if (streq (opt->name, name))
+      {
+	object_arch = &opt->value;
+	*input_line_pointer = saved_char;
+	demand_empty_rest_of_line ();
+	return;
+      }
+
+  as_bad (_("unknown architecture `%s'\n"), name);
+  *input_line_pointer = saved_char;
+  ignore_rest_of_line ();
+}
+
+
 /* Parse a .fpu directive.  */
 
 static void
@@ -14038,5 +20719,10 @@ s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
   *input_line_pointer = saved_char;
   ignore_rest_of_line ();
 }
-#endif /* OBJ_ELF */
 
+/* Copy symbol information.  */
+void
+arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
+{
+  ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
+}
diff --git a/contrib/binutils/gas/config/tc-arm.h b/contrib/binutils/gas/config/tc-arm.h
index f261577..d6dee9b 100644
--- a/contrib/binutils/gas/config/tc-arm.h
+++ b/contrib/binutils/gas/config/tc-arm.h
@@ -1,6 +1,6 @@
 /* This file is tc-arm.h
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004 Free Software Foundation, Inc.
+   2004, 2005, 2006, 2007 Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
 	Modified by David Taylor (dtaylor@armltd.co.uk)
 
@@ -66,6 +66,8 @@ struct fix;
 # if defined TE_PE
 #  if defined TE_EPOC
 #   define TARGET_FORMAT (target_big_endian ? "epoc-pe-arm-big" : "epoc-pe-arm-little")
+#  elif defined TE_WINCE
+#   define TARGET_FORMAT (target_big_endian ? "pe-arm-wince-big" : "pe-arm-wince-little")
 #  else
 #   define TARGET_FORMAT (target_big_endian ? "pe-arm-big" : "pe-arm-little")
 #  endif
@@ -98,6 +100,7 @@ extern int arm_optimize_expr (expressionS *, operatorT, expressionS *);
 #ifdef OBJ_ELF
 #define md_end arm_md_end
 extern void arm_md_end (void);
+bfd_boolean arm_is_eabi (void);
 #endif
 
 /* NOTE: The fake label creation in stabs.c:s_stab_generic() has
@@ -120,12 +123,30 @@ extern void arm_md_end (void);
 
 #define ARM_IS_THUMB(s)		(ARM_GET_FLAG (s) & ARM_FLAG_THUMB)
 #define ARM_IS_INTERWORK(s)	(ARM_GET_FLAG (s) & ARM_FLAG_INTERWORK)
+#ifdef OBJ_ELF
+
+/* For ELF objects THUMB_IS_FUNC is inferred from
+   ARM_IS_TUMB and the function type.  */
+#define THUMB_IS_FUNC(s) \
+  ((arm_is_eabi () \
+    && (ARM_IS_THUMB (s)) \
+    && (symbol_get_bfdsym (s)->flags & BSF_FUNCTION)) \
+   || (ARM_GET_FLAG (s) & THUMB_FLAG_FUNC))
+
+#else
 #define THUMB_IS_FUNC(s)	(ARM_GET_FLAG (s) & THUMB_FLAG_FUNC)
+#endif
 
 #define ARM_SET_THUMB(s,t)      ((t) ? ARM_SET_FLAG (s, ARM_FLAG_THUMB)     : ARM_RESET_FLAG (s, ARM_FLAG_THUMB))
 #define ARM_SET_INTERWORK(s,t)  ((t) ? ARM_SET_FLAG (s, ARM_FLAG_INTERWORK) : ARM_RESET_FLAG (s, ARM_FLAG_INTERWORK))
 #define THUMB_SET_FUNC(s,t)     ((t) ? ARM_SET_FLAG (s, THUMB_FLAG_FUNC)    : ARM_RESET_FLAG (s, THUMB_FLAG_FUNC))
 
+void arm_copy_symbol_attributes (symbolS *, symbolS *);
+#ifndef TC_COPY_SYMBOL_ATTRIBUTES
+#define TC_COPY_SYMBOL_ATTRIBUTES(DEST, SRC) \
+  (arm_copy_symbol_attributes (DEST, SRC))
+#endif
+
 #define TC_START_LABEL(C,STR)            (c == ':' || (c == '/' && arm_data_in_code ()))
 #define tc_canonicalize_symbol_name(str) arm_canonicalize_symbol_name (str);
 #define obj_adjust_symtab() 		 arm_adjust_symtab ()
@@ -146,7 +167,6 @@ extern void arm_md_end (void);
 
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   (!(FIX)->fx_pcrel					\
-   || (FIX)->fx_plt					\
    || (FIX)->fx_r_type == BFD_RELOC_ARM_GOT32		\
    || (FIX)->fx_r_type == BFD_RELOC_32			\
    || TC_FORCE_RELOCATION (FIX))
@@ -175,14 +195,27 @@ extern void arm_md_end (void);
       goto LABEL;								\
     }
 
+#define DWARF2_LINE_MIN_INSN_LENGTH 	2
+
+/* The lr register is r14.  */
+#define DWARF2_DEFAULT_RETURN_COLUMN  14
+
+/* Registers are generally saved at negative offsets to the CFA.  */
+#define DWARF2_CIE_DATA_ALIGNMENT     (-4)
+
 #ifdef OBJ_ELF
-# define DWARF2_LINE_MIN_INSN_LENGTH 	2
 # define obj_frob_symbol(sym, punt)	armelf_frob_symbol ((sym), & (punt))
 # define md_elf_section_change_hook()	arm_elf_change_section ()
 # define md_elf_section_type(str, len)	arm_elf_section_type (str, len)
 # define GLOBAL_OFFSET_TABLE_NAME	"_GLOBAL_OFFSET_TABLE_"
 # define TC_SEGMENT_INFO_TYPE 		struct arm_segment_info_type
 
+/* This is not really an alignment operation, but it's something we
+   need to do at the same time: whenever we are figuring out the
+   alignment for data, we should check whether a $d symbol is
+   necessary.  */
+# define md_cons_align(nbytes)		mapping_state (MAP_DATA)
+
 enum mstate
 {
   MAP_UNDEFINED = 0, /* Must be zero, for seginfo in new sections.  */
@@ -191,6 +224,8 @@ enum mstate
   MAP_THUMB
 };
 
+void mapping_state (enum mstate);
+
 struct arm_segment_info_type
 {
   enum mstate mapstate;
@@ -200,12 +235,6 @@ struct arm_segment_info_type
 /* We want .cfi_* pseudo-ops for generating unwind info.  */
 #define TARGET_USE_CFIPOP              1
 
-/* The lr register is r14.  */
-#define DWARF2_DEFAULT_RETURN_COLUMN  14
-
-/* Registers are generally saved at negative offsets to the CFA.  */
-#define DWARF2_CIE_DATA_ALIGNMENT     -4
-
 /* CFI hooks.  */
 #define tc_regname_to_dw2regnum            tc_arm_regname_to_dw2regnum
 #define tc_cfi_frame_initial_instructions  tc_arm_frame_initial_instructions
@@ -244,5 +273,14 @@ extern void arm_init_frag (struct frag *);
 extern void arm_handle_align (struct frag *);
 extern bfd_boolean arm_fix_adjustable (struct fix *);
 extern int arm_elf_section_type (const char *, size_t);
-extern int tc_arm_regname_to_dw2regnum (const char *regname);
+extern int tc_arm_regname_to_dw2regnum (char *regname);
 extern void tc_arm_frame_initial_instructions (void);
+
+#ifdef TE_PE
+
+#define O_secrel O_md1
+
+#define TC_DWARF2_EMIT_OFFSET  tc_pe_dwarf2_emit_offset
+void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
+
+#endif /* TE_PE */
diff --git a/contrib/binutils/gas/config/tc-cr16.c b/contrib/binutils/gas/config/tc-cr16.c
new file mode 100644
index 0000000..2c4c6a4
--- /dev/null
+++ b/contrib/binutils/gas/config/tc-cr16.c
@@ -0,0 +1,2444 @@
+/* tc-cr16.c -- Assembler code for the CR16 CPU core.
+   Copyright 2007 Free Software Foundation, Inc.
+
+   Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "dwarf2dbg.h"
+#include "opcode/cr16.h"
+#include "elf/cr16.h"
+
+
+/* Word is considered here as a 16-bit unsigned short int.  */
+#define WORD_SHIFT  16
+
+/* Register is 2-byte size.  */
+#define REG_SIZE   2
+
+/* Maximum size of a single instruction (in words).  */
+#define INSN_MAX_SIZE   3
+
+/* Maximum bits which may be set in a `mask16' operand.  */
+#define MAX_REGS_IN_MASK16  8
+
+/* Assign a number NUM, shifted by SHIFT bytes, into a location
+   pointed by index BYTE of array 'output_opcode'.  */
+#define CR16_PRINT(BYTE, NUM, SHIFT)   output_opcode[BYTE] |= (NUM << SHIFT)
+
+/* Operand errors.  */
+typedef enum
+  {
+    OP_LEGAL = 0,       /* Legal operand.  */
+    OP_OUT_OF_RANGE,    /* Operand not within permitted range.  */
+    OP_NOT_EVEN         /* Operand is Odd number, should be even.  */
+  }
+op_err;
+
+/* Opcode mnemonics hash table.  */
+static struct hash_control *cr16_inst_hash;
+/* CR16 registers hash table.  */
+static struct hash_control *reg_hash;
+/* CR16 register pair hash table.  */
+static struct hash_control *regp_hash;
+/* CR16 processor registers hash table.  */
+static struct hash_control *preg_hash;
+/* CR16 processor registers 32 bit hash table.  */
+static struct hash_control *pregp_hash;
+/* Current instruction we're assembling.  */
+const inst *instruction;
+
+
+static int code_label = 0;
+
+/* Global variables.  */
+
+/* Array to hold an instruction encoding.  */
+long output_opcode[2];
+
+/* Nonzero means a relocatable symbol.  */
+int relocatable;
+
+/* A copy of the original instruction (used in error messages).  */
+char ins_parse[MAX_INST_LEN];
+
+/* The current processed argument number.  */
+int cur_arg_num;
+
+/* Generic assembler global variables which must be defined by all targets.  */
+
+/* Characters which always start a comment.  */
+const char comment_chars[] = "#";
+
+/* Characters which start a comment at the beginning of a line.  */
+const char line_comment_chars[] = "#";
+
+/* This array holds machine specific line separator characters.  */
+const char line_separator_chars[] = ";";
+
+/* Chars that can be used to separate mant from exp in floating point nums.  */
+const char EXP_CHARS[] = "eE";
+
+/* Chars that mean this number is a floating point constant as in 0f12.456  */
+const char FLT_CHARS[] = "f'";
+
+/* Target-specific multicharacter options, not const-declared at usage.  */
+const char *md_shortopts = "";
+struct option md_longopts[] =
+{
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+static void
+l_cons (int nbytes)
+{
+  int c;
+  expressionS exp;
+
+#ifdef md_flush_pending_output
+    md_flush_pending_output ();
+#endif
+
+  if (is_it_end_of_statement ())
+    {
+      demand_empty_rest_of_line ();
+      return;
+    }
+
+#ifdef TC_ADDRESS_BYTES
+  if (nbytes == 0)
+    nbytes = TC_ADDRESS_BYTES ();
+#endif
+
+#ifdef md_cons_align
+  md_cons_align (nbytes);
+#endif
+
+  c = 0;
+  do
+    {
+      unsigned int bits_available = BITS_PER_CHAR * nbytes;
+      char *hold = input_line_pointer;
+
+      expression (&exp);
+
+      if (*input_line_pointer == ':')
+	{
+	  /* Bitfields.  */
+	  long value = 0;
+
+	  for (;;)
+	    {
+	      unsigned long width;
+
+	      if (*input_line_pointer != ':')
+		{
+		  input_line_pointer = hold;
+		  break;
+		}
+	      if (exp.X_op == O_absent)
+		{
+		  as_warn (_("using a bit field width of zero"));
+		  exp.X_add_number = 0;
+		  exp.X_op = O_constant;
+		}
+
+	      if (exp.X_op != O_constant)
+		{
+		  *input_line_pointer = '\0';
+		  as_bad (_("field width \"%s\" too complex for a bitfield"), hold);
+		  *input_line_pointer = ':';
+		  demand_empty_rest_of_line ();
+		  return;
+		}
+
+	      if ((width = exp.X_add_number) >
+		  (unsigned int)(BITS_PER_CHAR * nbytes))
+		{
+		  as_warn (_("field width %lu too big to fit in %d bytes: truncated to %d bits"), width, nbytes, (BITS_PER_CHAR * nbytes));
+		  width = BITS_PER_CHAR * nbytes;
+		}                   /* Too big.  */
+
+
+	      if (width > bits_available)
+		{
+		  /* FIXME-SOMEDAY: backing up and reparsing is wasteful.  */
+		  input_line_pointer = hold;
+		  exp.X_add_number = value;
+		  break;
+		}
+
+	      /* Skip ':'.  */
+	      hold = ++input_line_pointer;
+
+	      expression (&exp);
+	      if (exp.X_op != O_constant)
+		{
+		  char cache = *input_line_pointer;
+
+		  *input_line_pointer = '\0';
+		  as_bad (_("field value \"%s\" too complex for a bitfield"), hold);
+		  *input_line_pointer = cache;
+		  demand_empty_rest_of_line ();
+		  return;
+		}
+
+	      value |= ((~(-1 << width) & exp.X_add_number)
+			<< ((BITS_PER_CHAR * nbytes) - bits_available));
+
+	      if ((bits_available -= width) == 0
+		  || is_it_end_of_statement ()
+		  || *input_line_pointer != ',')
+		break;
+
+	      hold = ++input_line_pointer;
+	      expression (&exp);
+	    }
+
+	  exp.X_add_number = value;
+	  exp.X_op = O_constant;
+	  exp.X_unsigned = 1;
+	}
+
+      if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
+	code_label = 1;
+      emit_expr (&exp, (unsigned int) nbytes);
+      ++c;
+      if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
+	{
+	  input_line_pointer +=3;
+	  break;
+	}
+    }
+  while ((*input_line_pointer++ == ','));
+
+  /* Put terminator back into stream.  */
+  input_line_pointer--;
+
+  demand_empty_rest_of_line ();
+}
+
+
+/* This table describes all the machine specific pseudo-ops
+   the assembler has to support.  The fields are:
+   *** Pseudo-op name without dot.
+   *** Function to call to execute this pseudo-op.
+   *** Integer arg to pass to the function.  */
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  /* In CR16 machine, align is in bytes (not a ptwo boundary).  */
+  {"align", s_align_bytes, 0},
+  {"long", l_cons,  4 },
+  {0, 0, 0}
+};
+
+/* CR16 relaxation table.  */
+const relax_typeS md_relax_table[] =
+{
+  /* bCC  */
+  {0xfa, -0x100, 2, 1},                 /*  8 */
+  {0xfffe, -0x10000, 4, 2},             /* 16 */
+  {0xfffffe, -0x1000000, 6, 0},         /* 24 */
+};
+
+/* Return the bit size for a given operand.  */
+
+static int
+get_opbits (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return cr16_optab[op].bit_size;
+
+  return 0;
+}
+
+/* Return the argument type of a given operand.  */
+
+static argtype
+get_optype (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return cr16_optab[op].arg_type;
+  else
+    return nullargs;
+}
+
+/* Return the flags of a given operand.  */
+
+static int
+get_opflags (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return cr16_optab[op].flags;
+
+  return 0;
+}
+
+/* Get the cc code.  */
+
+static int
+get_cc (char *cc_name)
+{
+   unsigned int i;
+
+   for (i = 0; i < cr16_num_cc; i++)
+     if (strcmp (cc_name, cr16_b_cond_tab[i]) == 0)
+       return i;
+
+   return -1;
+}
+
+/* Get the core processor register 'reg_name'.  */
+
+static reg
+get_register (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (reg_hash, reg_name);
+
+  if (reg != NULL)
+    return reg->value.reg_val;
+
+  return nullregister;
+}
+/* Get the core processor register-pair 'reg_name'.  */
+
+static reg
+get_register_pair (char *reg_name)
+{
+  const reg_entry *reg;
+  char tmp_rp[16]="\0";
+
+  /* Add '(' and ')' to the reg pair, if its not present.  */
+  if (reg_name[0] != '(') 
+    {
+      tmp_rp[0] = '(';
+      strcat (tmp_rp, reg_name);
+      strcat (tmp_rp,")");
+      reg = (const reg_entry *) hash_find (regp_hash, tmp_rp);
+    }
+  else
+    reg = (const reg_entry *) hash_find (regp_hash, reg_name);
+
+  if (reg != NULL)
+    return reg->value.reg_val;
+
+  return nullregister;
+} 
+
+/* Get the index register 'reg_name'.  */
+
+static reg
+get_index_register (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (reg_hash, reg_name);
+
+  if ((reg != NULL)
+      && ((reg->value.reg_val == 12) || (reg->value.reg_val == 13)))
+    return reg->value.reg_val;
+
+  return nullregister;
+}
+/* Get the core processor index register-pair 'reg_name'.  */
+
+static reg
+get_index_register_pair (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (regp_hash, reg_name);
+
+  if (reg != NULL)
+    {
+      if ((reg->value.reg_val != 1) || (reg->value.reg_val != 7)
+	  || (reg->value.reg_val != 9) || (reg->value.reg_val > 10))
+	return reg->value.reg_val;
+
+      as_bad (_("Unknown register pair - index relative mode: `%d'"), reg->value.reg_val);
+    }
+
+  return nullregister;
+}
+
+/* Get the processor register 'preg_name'.  */
+
+static preg
+get_pregister (char *preg_name)
+{
+  const reg_entry *preg;
+
+  preg = (const reg_entry *) hash_find (preg_hash, preg_name);
+
+  if (preg != NULL)
+    return preg->value.preg_val;
+
+  return nullpregister;
+}
+
+/* Get the processor register 'preg_name 32 bit'.  */
+
+static preg
+get_pregisterp (char *preg_name)
+{
+  const reg_entry *preg;
+
+  preg = (const reg_entry *) hash_find (pregp_hash, preg_name);
+
+  if (preg != NULL)
+    return preg->value.preg_val;
+
+  return nullpregister;
+}
+
+
+/* Round up a section size to the appropriate boundary.  */
+
+valueT
+md_section_align (segT seg, valueT val)
+{
+  /* Round .text section to a multiple of 2.  */
+  if (seg == text_section)
+    return (val + 1) & ~1;
+  return val;
+}
+
+/* Parse an operand that is machine-specific (remove '*').  */
+
+void
+md_operand (expressionS * exp)
+{
+  char c = *input_line_pointer;
+
+  switch (c)
+    {
+    case '*':
+      input_line_pointer++;
+      expression (exp);
+      break;
+    default:
+      break;
+    }
+}
+
+/* Reset global variables before parsing a new instruction.  */
+
+static void
+reset_vars (char *op)
+{
+  cur_arg_num = relocatable = 0;
+  memset (& output_opcode, '\0', sizeof (output_opcode));
+
+  /* Save a copy of the original OP (used in error messages).  */
+  strncpy (ins_parse, op, sizeof ins_parse - 1);
+  ins_parse [sizeof ins_parse - 1] = 0;
+}
+
+/* This macro decides whether a particular reloc is an entry in a
+   switch table.  It is used when relaxing, because the linker needs
+   to know about all such entries so that it can adjust them if
+   necessary.  */
+
+#define SWITCH_TABLE(fix)                                  \
+  (   (fix)->fx_addsy != NULL                              \
+   && (fix)->fx_subsy != NULL                              \
+   && S_GET_SEGMENT ((fix)->fx_addsy) ==                   \
+      S_GET_SEGMENT ((fix)->fx_subsy)                      \
+   && S_GET_SEGMENT (fix->fx_addsy) != undefined_section   \
+   && (   (fix)->fx_r_type == BFD_RELOC_CR16_NUM8          \
+       || (fix)->fx_r_type == BFD_RELOC_CR16_NUM16         \
+       || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32         \
+       || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32a))
+
+/* See whether we need to force a relocation into the output file.
+   This is used to force out switch and PC relative relocations when
+   relaxing.  */
+
+int
+cr16_force_relocation (fixS *fix)
+{
+  /* REVISIT: Check if the "SWITCH_TABLE (fix)" should be added
+     if (generic_force_reloc (fix) || SWITCH_TABLE (fix))  */
+  if (generic_force_reloc (fix))
+    return 1;
+
+  return 0;
+}
+
+/* Record a fixup for a cons expression.  */
+
+void
+cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp)
+{
+  int rtype;
+  switch (len)
+    {
+    default: rtype = BFD_RELOC_NONE; break;
+    case 1: rtype = BFD_RELOC_CR16_NUM8 ; break;
+    case 2: rtype = BFD_RELOC_CR16_NUM16; break;
+    case 4:
+      if (code_label)
+	{
+	  rtype = BFD_RELOC_CR16_NUM32a;
+	  code_label = 0;
+	}
+      else
+	rtype = BFD_RELOC_CR16_NUM32;
+      break;
+    }
+
+  fix_new_exp (frag, offset, len, exp, 0, rtype);
+}
+
+/* Generate a relocation entry for a fixup.  */
+
+arelent *
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
+{
+  arelent * reloc;
+
+  reloc = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr  = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
+  reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
+  reloc->addend = fixP->fx_offset;
+
+  if (fixP->fx_subsy != NULL)
+    {
+      if (SWITCH_TABLE (fixP))
+        {
+          /* Keep the current difference in the addend.  */
+          reloc->addend = (S_GET_VALUE (fixP->fx_addsy)
+                           - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset);
+
+          switch (fixP->fx_r_type)
+            {
+	    case BFD_RELOC_CR16_NUM8:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM8;
+	      break;
+	    case BFD_RELOC_CR16_NUM16:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM16;
+	      break;
+	    case BFD_RELOC_CR16_NUM32:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM32;
+	      break;
+	    case BFD_RELOC_CR16_NUM32a:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM32a;
+	      break;
+	    default:
+	      abort ();
+	      break;
+            }
+        }
+      else
+        {
+          /* We only resolve difference expressions in the same section.  */
+          as_bad_where (fixP->fx_file, fixP->fx_line,
+                        _("can't resolve `%s' {%s section} - `%s' {%s section}"),
+                        fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
+                        segment_name (fixP->fx_addsy
+                                      ? S_GET_SEGMENT (fixP->fx_addsy)
+                                      : absolute_section),
+                        S_GET_NAME (fixP->fx_subsy),
+                        segment_name (S_GET_SEGMENT (fixP->fx_addsy)));
+        }
+    }
+
+  assert ((int) fixP->fx_r_type > 0);
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
+
+  if (reloc->howto == NULL)
+    {
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+                    _("internal error: reloc %d (`%s') not supported by object file format"),
+                    fixP->fx_r_type,
+                    bfd_get_reloc_code_name (fixP->fx_r_type));
+      return NULL;
+    }
+  assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
+
+  return reloc;
+}
+
+/* Prepare machine-dependent frags for relaxation.  */
+
+int
+md_estimate_size_before_relax (fragS *fragp, asection *seg)
+{
+  /* If symbol is undefined or located in a different section,
+     select the largest supported relocation.  */
+  relax_substateT subtype;
+  relax_substateT rlx_state[] = {0, 2};
+
+  for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2)
+    {
+      if (fragp->fr_subtype == rlx_state[subtype]
+          && (!S_IS_DEFINED (fragp->fr_symbol)
+              || seg != S_GET_SEGMENT (fragp->fr_symbol)))
+        {
+          fragp->fr_subtype = rlx_state[subtype + 1];
+          break;
+        }
+    }
+
+  if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table))
+    abort ();
+
+  return md_relax_table[fragp->fr_subtype].rlx_length;
+}
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP)
+{
+  /* 'opcode' points to the start of the instruction, whether
+     we need to change the instruction's fixed encoding.  */
+  bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
+
+  subseg_change (sec, 0);
+
+  fix_new (fragP, fragP->fr_fix,
+           bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)),
+           fragP->fr_symbol, fragP->fr_offset, 1, reloc);
+  fragP->fr_var = 0;
+  fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length;
+}
+
+/* Process machine-dependent command line options.  Called once for
+   each option on the command line that the machine-independent part of
+   GAS does not understand.  */
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Machine-dependent usage-output.  */
+
+void
+md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
+{
+  return;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type TYPE, and store the appropriate bytes in *LITP.  The number
+   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
+   returned, or NULL on OK.  */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  int i;
+  LITTLENUM_TYPE words[4];
+  char *t;
+
+  switch (type)
+    {
+      case 'f':
+        prec = 2;
+        break;
+
+      case 'd':
+        prec = 4;
+        break;
+
+      default:
+        *sizeP = 0;
+        return _("bad call to md_atof");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * 2;
+
+  if (! target_big_endian)
+    {
+      for (i = prec - 1; i >= 0; i--)
+        {
+          md_number_to_chars (litP, (valueT) words[i], 2);
+          litP += 2;
+        }
+    }
+  else
+    {
+      for (i = 0; i < prec; i++)
+        {
+          md_number_to_chars (litP, (valueT) words[i], 2);
+          litP += 2;
+        }
+    }
+
+  return NULL;
+}
+
+/* Apply a fixS (fixup of an instruction or data that we didn't have
+   enough info to complete immediately) to the data in a frag.
+   Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
+   relaxation of debug sections, this function is called only when
+   fixuping relocations of debug sections.  */
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+{
+  valueT val = * valP;
+  char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
+  fixP->fx_offset = 0;
+
+  switch (fixP->fx_r_type)
+    {
+      case BFD_RELOC_CR16_NUM8:
+        bfd_put_8 (stdoutput, (unsigned char) val, buf);
+        break;
+      case BFD_RELOC_CR16_NUM16:
+        bfd_put_16 (stdoutput, val, buf);
+        break;
+      case BFD_RELOC_CR16_NUM32:
+        bfd_put_32 (stdoutput, val, buf);
+        break;
+      case BFD_RELOC_CR16_NUM32a:
+        bfd_put_32 (stdoutput, val, buf);
+        break;
+      default:
+        /* We shouldn't ever get here because linkrelax is nonzero.  */
+        abort ();
+        break;
+    }
+
+  fixP->fx_done = 0;
+
+  if (fixP->fx_addsy == NULL
+      && fixP->fx_pcrel == 0)
+    fixP->fx_done = 1;
+
+  if (fixP->fx_pcrel == 1
+      && fixP->fx_addsy != NULL
+      && S_GET_SEGMENT (fixP->fx_addsy) == seg)
+    fixP->fx_done = 1;
+}
+
+/* The location from which a PC relative jump should be calculated,
+   given a PC relative reloc.  */
+
+long
+md_pcrel_from (fixS *fixp)
+{
+  return fixp->fx_frag->fr_address + fixp->fx_where;
+}
+
+static void
+initialise_reg_hash_table (struct hash_control ** hash_table,
+			   const reg_entry * register_table,
+			   const unsigned int num_entries)
+{
+  const reg_entry * reg;
+  const char *hashret;
+
+  if ((* hash_table = hash_new ()) == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  for (reg = register_table;
+       reg < (register_table + num_entries);
+       reg++)
+    {
+      hashret = hash_insert (* hash_table, reg->name, (char *) reg);
+      if (hashret)
+	as_fatal (_("Internal Error:  Can't hash %s: %s"),
+		  reg->name, hashret);
+    }
+}
+
+/* This function is called once, at assembler startup time.  This should
+   set up all the tables, etc that the MD part of the assembler needs.  */
+
+void
+md_begin (void)
+{
+  int i = 0;
+
+  /* Set up a hash table for the instructions.  */
+  if ((cr16_inst_hash = hash_new ()) == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  while (cr16_instruction[i].mnemonic != NULL)
+    {
+      const char *hashret;
+      const char *mnemonic = cr16_instruction[i].mnemonic;
+
+      hashret = hash_insert (cr16_inst_hash, mnemonic,
+			     (char *)(cr16_instruction + i));
+
+      if (hashret != NULL && *hashret != '\0')
+        as_fatal (_("Can't hash `%s': %s\n"), cr16_instruction[i].mnemonic,
+                  *hashret == 0 ? _("(unknown reason)") : hashret);
+
+      /* Insert unique names into hash table.  The CR16 instruction set
+         has many identical opcode names that have different opcodes based
+         on the operands.  This hash table then provides a quick index to
+         the first opcode with a particular name in the opcode table.  */
+      do
+        {
+          ++i;
+        }
+      while (cr16_instruction[i].mnemonic != NULL
+             && streq (cr16_instruction[i].mnemonic, mnemonic));
+    }
+
+  /* Initialize reg_hash hash table.  */
+  initialise_reg_hash_table (& reg_hash, cr16_regtab, NUMREGS);
+  /* Initialize regp_hash hash table.  */
+  initialise_reg_hash_table (& regp_hash, cr16_regptab, NUMREGPS);
+  /* Initialize preg_hash hash table.  */
+  initialise_reg_hash_table (& preg_hash, cr16_pregtab, NUMPREGS);
+  /* Initialize pregp_hash hash table.  */
+  initialise_reg_hash_table (& pregp_hash, cr16_pregptab, NUMPREGPS);
+
+  /*  Set linkrelax here to avoid fixups in most sections.  */
+  linkrelax = 1;
+}
+
+/* Process constants (immediate/absolute)
+   and labels (jump targets/Memory locations).  */
+
+static void
+process_label_constant (char *str, ins * cr16_ins)
+{
+  char *saved_input_line_pointer;
+  int symbol_with_at = 0;
+  int symbol_with_s = 0;
+  int symbol_with_m = 0;
+  int symbol_with_l = 0;
+  argument *cur_arg = cr16_ins->arg + cur_arg_num;  /* Current argument.  */
+
+  saved_input_line_pointer = input_line_pointer;
+  input_line_pointer = str;
+
+  expression (&cr16_ins->exp);
+
+  switch (cr16_ins->exp.X_op)
+    {
+    case O_big:
+    case O_absent:
+      /* Missing or bad expr becomes absolute 0.  */
+      as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
+	      str);
+      cr16_ins->exp.X_op = O_constant;
+      cr16_ins->exp.X_add_number = 0;
+      cr16_ins->exp.X_add_symbol = NULL;
+      cr16_ins->exp.X_op_symbol = NULL;
+      /* Fall through.  */
+
+    case O_constant:
+      cur_arg->X_op = O_constant;
+      cur_arg->constant = cr16_ins->exp.X_add_number;
+      break;
+
+    case O_symbol:
+    case O_subtract:
+    case O_add:
+      cur_arg->X_op = O_symbol;
+      cr16_ins->rtype = BFD_RELOC_NONE;
+      relocatable = 1;
+
+      if (strneq (input_line_pointer, "@c", 2))
+	symbol_with_at = 1;
+
+      if (strneq (input_line_pointer, "@l", 2)
+	  || strneq (input_line_pointer, ":l", 2))
+	symbol_with_l = 1;
+
+      if (strneq (input_line_pointer, "@m", 2)
+	  || strneq (input_line_pointer, ":m", 2))
+	symbol_with_m = 1;
+
+      if (strneq (input_line_pointer, "@s", 2)
+	  || strneq (input_line_pointer, ":s", 2))
+	symbol_with_s = 1;
+
+      switch (cur_arg->type)
+        {
+	case arg_cr:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    {
+	      if (cur_arg->size == 20)
+		cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
+	      else
+		cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
+	    }
+	  break;
+
+	case arg_crp:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    switch (instruction->size)
+	      {
+	      case 1:
+		switch (cur_arg->size)
+		  {
+		  case 0:
+		    cr16_ins->rtype = BFD_RELOC_CR16_REGREL0;
+		    break;
+		  case 4:
+		    if (IS_INSN_MNEMONIC ("loadb") || IS_INSN_MNEMONIC ("storb"))
+		      cr16_ins->rtype = BFD_RELOC_CR16_REGREL4;
+		    else
+		      cr16_ins->rtype = BFD_RELOC_CR16_REGREL4a;
+		    break;
+		  default: break;
+		  }
+		break;
+	      case 2:
+		cr16_ins->rtype = BFD_RELOC_CR16_REGREL16;
+		break;
+	      case 3:
+		if (cur_arg->size == 20)
+		  cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
+		else
+		  cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
+		break;
+	      default:
+		break;
+	      }
+	  break;
+
+	case arg_idxr:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
+	  break;
+
+	case arg_idxrp:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    switch (instruction->size)
+	      {
+	      case 1: cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; break;
+	      case 2: cr16_ins->rtype = BFD_RELOC_CR16_REGREL14; break;
+	      case 3: cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; break;
+	      default: break;
+	      }
+	  break;
+
+	case arg_c:
+	  if (IS_INSN_MNEMONIC ("bal"))
+	    cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
+	  else if (IS_INSN_TYPE (BRANCH_INS))
+	    {
+	      if (symbol_with_s)
+		cr16_ins->rtype = BFD_RELOC_CR16_DISP8;
+	      else if (symbol_with_m)
+		cr16_ins->rtype = BFD_RELOC_CR16_DISP16;
+	      else
+		cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
+	    }
+	  else if (IS_INSN_TYPE (STOR_IMM_INS) || IS_INSN_TYPE (LD_STOR_INS)
+		   || IS_INSN_TYPE (CSTBIT_INS))
+	    {
+	      if (symbol_with_s)
+		as_bad (_("operand %d: illegal use expression: `%s`"), cur_arg_num + 1, str);
+	      if (symbol_with_m)
+		cr16_ins->rtype = BFD_RELOC_CR16_ABS20;
+	      else /* Default to (symbol_with_l) */
+		cr16_ins->rtype = BFD_RELOC_CR16_ABS24;
+	    }
+	  else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
+	    cr16_ins->rtype = BFD_RELOC_CR16_DISP4;
+          break;
+
+        case arg_ic:
+          if (IS_INSN_TYPE (ARITH_INS))
+            {
+              if (symbol_with_s)
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM4;
+              else if (symbol_with_m)
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM20;
+              else if (symbol_with_at)
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM32a;
+              else /* Default to (symbol_with_l) */
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM32;
+            }
+          else if (IS_INSN_TYPE (ARITH_BYTE_INS))
+	    {
+	      cr16_ins->rtype = BFD_RELOC_CR16_IMM16;
+	    }
+          break;
+        default:
+          break;
+	}
+      break;
+
+    default:
+      cur_arg->X_op = cr16_ins->exp.X_op;
+      break;
+    }
+
+  input_line_pointer = saved_input_line_pointer;
+  return;
+}
+
+/* Retrieve the opcode image of a given register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getreg_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+  int is_procreg = 0; /* Nonzero means argument should be processor reg.  */
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = cr16_regtab + r;
+  else /* Register not found.  */
+    {
+      as_bad (_("Unknown register: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register is illegal.  */
+#define IMAGE_ERR \
+  as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                            \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_R_REGTYPE:
+      if (! is_procreg)
+	return reg->image;
+      else
+	IMAGE_ERR;
+
+    case CR16_P_REGTYPE:
+      return reg->image;
+      break;
+
+    default:
+      IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Parsing different types of operands
+   -> constants             Immediate/Absolute/Relative numbers
+   -> Labels                Relocatable symbols
+   -> (reg pair base)       Register pair base
+   -> (rbase)               Register base
+   -> disp(rbase)           Register relative
+   -> [rinx]disp(reg pair)  Register index with reg pair mode
+   -> disp(rbase,ridx,scl)  Register index mode.  */
+
+static void
+set_operand (char *operand, ins * cr16_ins)
+{
+  char *operandS; /* Pointer to start of sub-opearand.  */
+  char *operandE; /* Pointer to end of sub-opearand.  */
+
+  argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument.  */
+
+  /* Initialize pointers.  */
+  operandS = operandE = operand;
+
+  switch (cur_arg->type)
+    {
+    case arg_ic:    /* Case $0x18.  */
+      operandS++;
+    case arg_c:     /* Case 0x18.  */
+      /* Set constant.  */
+      process_label_constant (operandS, cr16_ins);
+
+      if (cur_arg->type != arg_ic)
+        cur_arg->type = arg_c;
+      break;
+
+    case arg_icr:   /* Case $0x18(r1).  */
+      operandS++;
+    case arg_cr:    /* Case 0x18(r1).   */
+      /* Set displacement constant.  */
+      while (*operandE != '(')
+        operandE++;
+      *operandE = '\0';
+      process_label_constant (operandS, cr16_ins);
+      operandS = operandE;
+    case arg_rbase: /* Case (r1) or (r1,r0).  */
+      operandS++;
+      /* Set register base.  */
+      while (*operandE != ')')
+        operandE++;
+      *operandE = '\0';
+      if ((cur_arg->r = get_register (operandS)) == nullregister)
+         as_bad (_("Illegal register `%s' in Instruction `%s'"),
+              operandS, ins_parse);
+
+      /* set the arg->rp, if reg is "r12" or "r13" or "14" or "15" */
+      if ((cur_arg->type != arg_rbase)
+	  && ((getreg_image (cur_arg->r) == 12)
+	      || (getreg_image (cur_arg->r) == 13)
+	      || (getreg_image (cur_arg->r) == 14)
+	      || (getreg_image (cur_arg->r) == 15)))
+         {
+           cur_arg->type = arg_crp;
+           cur_arg->rp = cur_arg->r;
+         }
+      break;
+
+    case arg_crp:    /* Case 0x18(r1,r0).   */
+      /* Set displacement constant.  */
+      while (*operandE != '(')
+        operandE++;
+      *operandE = '\0';
+      process_label_constant (operandS, cr16_ins);
+      operandS = operandE;
+      operandS++;
+      /* Set register pair base.  */
+      while (*operandE != ')')
+        operandE++;
+      *operandE = '\0';
+      if ((cur_arg->rp = get_register_pair (operandS)) == nullregister)
+         as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
+              operandS, ins_parse);
+      break;
+
+    case arg_idxr:
+      /* Set register pair base.  */
+      if ((strchr (operandS,'(') != NULL))
+        {
+         while ((*operandE != '(') && (! ISSPACE (*operandE)))
+           operandE++;
+         if ((cur_arg->rp = get_index_register_pair (operandE)) == nullregister)
+              as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
+                            operandS, ins_parse);
+         *operandE++ = '\0';
+         cur_arg->type = arg_idxrp;
+        }
+      else
+	cur_arg->rp = -1;
+
+       operandE = operandS;
+      /* Set displacement constant.  */
+      while (*operandE != ']')
+        operandE++;
+      process_label_constant (++operandE, cr16_ins);
+      *operandE++ = '\0';
+      operandE = operandS;
+
+      /* Set index register .  */
+      operandS = strchr (operandE,'[');
+      if (operandS != NULL)
+        { /* Eliminate '[', detach from rest of operand.  */
+          *operandS++ = '\0';
+
+          operandE = strchr (operandS, ']');
+
+          if (operandE == NULL)
+            as_bad (_("unmatched '['"));
+          else
+            { /* Eliminate ']' and make sure it was the last thing
+                 in the string.  */
+              *operandE = '\0';
+              if (*(operandE + 1) != '\0')
+                as_bad (_("garbage after index spec ignored"));
+            }
+        }
+
+      if ((cur_arg->i_r = get_index_register (operandS)) == nullregister)
+        as_bad (_("Illegal register `%s' in Instruction `%s'"),
+                operandS, ins_parse);
+      *operandE = '\0';
+      *operandS = '\0';
+      break;
+
+    default:
+      break;
+    }
+}
+
+/* Parse a single operand.
+   operand - Current operand to parse.
+   cr16_ins - Current assembled instruction.  */
+
+static void
+parse_operand (char *operand, ins * cr16_ins)
+{
+  int ret_val;
+  argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument.  */
+
+  /* Initialize the type to NULL before parsing.  */
+  cur_arg->type = nullargs;
+
+  /* Check whether this is a condition code .  */
+  if ((IS_INSN_MNEMONIC ("b")) && ((ret_val = get_cc (operand)) != -1))
+    {
+      cur_arg->type = arg_cc;
+      cur_arg->cc = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether this is a general processor register.  */
+  if ((ret_val = get_register (operand)) != nullregister)
+    {
+      cur_arg->type = arg_r;
+      cur_arg->r = ret_val;
+      cur_arg->X_op = 0;
+      return;
+    }
+
+  /* Check whether this is a general processor register pair.  */
+  if ((operand[0] == '(')
+      && ((ret_val = get_register_pair (operand)) != nullregister))
+    {
+      cur_arg->type = arg_rp;
+      cur_arg->rp = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether the operand is a processor register.
+     For "lprd" and "sprd" instruction, only 32 bit
+     processor registers used.  */
+  if (!(IS_INSN_MNEMONIC ("lprd") || (IS_INSN_MNEMONIC ("sprd")))
+      && ((ret_val = get_pregister (operand)) != nullpregister))
+    {
+      cur_arg->type = arg_pr;
+      cur_arg->pr = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether this is a processor register - 32 bit.  */
+  if ((ret_val = get_pregisterp (operand)) != nullpregister)
+    {
+      cur_arg->type = arg_prp;
+      cur_arg->prp = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Deal with special characters.  */
+  switch (operand[0])
+    {
+    case '$':
+      if (strchr (operand, '(') != NULL)
+	cur_arg->type = arg_icr;
+      else
+	cur_arg->type = arg_ic;
+      goto set_params;
+      break;
+
+    case '(':
+      cur_arg->type = arg_rbase;
+      goto set_params;
+      break;
+
+    case '[':
+      cur_arg->type = arg_idxr;
+      goto set_params;
+      break;
+
+    default:
+      break;
+    }
+
+  if (strchr (operand, '(') != NULL)
+    {
+      if (strchr (operand, ',') != NULL
+          && (strchr (operand, ',') > strchr (operand, '(')))
+        cur_arg->type = arg_crp;
+      else
+        cur_arg->type = arg_cr;
+    }
+  else
+    cur_arg->type = arg_c;
+
+/* Parse an operand according to its type.  */
+ set_params:
+  cur_arg->constant = 0;
+  set_operand (operand, cr16_ins);
+}
+
+/* Parse the various operands. Each operand is then analyzed to fillup
+   the fields in the cr16_ins data structure.  */
+
+static void
+parse_operands (ins * cr16_ins, char *operands)
+{
+  char *operandS;            /* Operands string.  */
+  char *operandH, *operandT; /* Single operand head/tail pointers.  */
+  int allocated = 0;         /* Indicates a new operands string was allocated.*/
+  char *operand[MAX_OPERANDS];/* Separating the operands.  */
+  int op_num = 0;             /* Current operand number we are parsing.  */
+  int bracket_flag = 0;       /* Indicates a bracket '(' was found.  */
+  int sq_bracket_flag = 0;    /* Indicates a square bracket '[' was found.  */
+
+  /* Preprocess the list of registers, if necessary.  */
+  operandS = operandH = operandT = operands;
+
+  while (*operandT != '\0')
+    {
+      if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1)
+        {
+          *operandT++ = '\0';
+          operand[op_num++] = strdup (operandH);
+          operandH = operandT;
+          continue;
+        }
+
+      if (*operandT == ' ')
+        as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse);
+
+      if (*operandT == '(')
+        bracket_flag = 1;
+      else if (*operandT == '[')
+        sq_bracket_flag = 1;
+
+      if (*operandT == ')')
+        {
+          if (bracket_flag)
+            bracket_flag = 0;
+          else
+            as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+        }
+      else if (*operandT == ']')
+        {
+          if (sq_bracket_flag)
+            sq_bracket_flag = 0;
+          else
+            as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+        }
+
+      if (bracket_flag == 1 && *operandT == ')')
+        bracket_flag = 0;
+      else if (sq_bracket_flag == 1 && *operandT == ']')
+        sq_bracket_flag = 0;
+
+      operandT++;
+    }
+
+  /* Adding the last operand.  */
+  operand[op_num++] = strdup (operandH);
+  cr16_ins->nargs = op_num;
+
+  /* Verifying correct syntax of operands (all brackets should be closed).  */
+  if (bracket_flag || sq_bracket_flag)
+    as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+
+  /* Now we parse each operand separately.  */
+  for (op_num = 0; op_num < cr16_ins->nargs; op_num++)
+    {
+      cur_arg_num = op_num;
+      parse_operand (operand[op_num], cr16_ins);
+      free (operand[op_num]);
+    }
+
+  if (allocated)
+    free (operandS);
+}
+
+/* Get the trap index in dispatch table, given its name.
+   This routine is used by assembling the 'excp' instruction.  */
+
+static int
+gettrap (char *s)
+{
+  const trap_entry *trap;
+
+  for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
+    if (strcasecmp (trap->name, s) == 0)
+      return trap->entry;
+
+  /* To make compatable with CR16 4.1 tools, the below 3-lines of
+   * code added. Refer: Development Tracker item #123 */
+  for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
+    if (trap->entry  == (unsigned int) atoi (s))
+      return trap->entry;
+
+  as_bad (_("Unknown exception: `%s'"), s);
+  return 0;
+}
+
+/* Top level module where instruction parsing starts.
+   cr16_ins - data structure holds some information.
+   operands - holds the operands part of the whole instruction.  */
+
+static void
+parse_insn (ins *insn, char *operands)
+{
+  int i;
+
+  /* Handle instructions with no operands.  */
+  for (i = 0; cr16_no_op_insn[i] != NULL; i++)
+  {
+    if (streq (cr16_no_op_insn[i], instruction->mnemonic))
+    {
+      insn->nargs = 0;
+      return;
+    }
+  }
+
+  /* Handle 'excp' instructions.  */
+  if (IS_INSN_MNEMONIC ("excp"))
+    {
+      insn->nargs = 1;
+      insn->arg[0].type = arg_ic;
+      insn->arg[0].constant = gettrap (operands);
+      insn->arg[0].X_op = O_constant;
+      return;
+    }
+
+  if (operands != NULL)
+    parse_operands (insn, operands);
+}
+
+/* bCC instruction requires special handling.  */
+static char *
+get_b_cc (char * op)
+{
+  unsigned int i;
+  char op1[5];
+
+  for (i = 1; i < strlen (op); i++)
+     op1[i-1] = op[i];
+
+  op1[i-1] = '\0';
+
+  for (i = 0; i < cr16_num_cc ; i++)
+    if (streq (op1, cr16_b_cond_tab[i]))
+      return (char *) cr16_b_cond_tab[i];
+
+   return NULL;
+}
+
+/* bCC instruction requires special handling.  */
+static int
+is_bcc_insn (char * op)
+{
+  if (!(streq (op, "bal") || streq (op, "beq0b") || streq (op, "bnq0b")
+	|| streq (op, "beq0w") || streq (op, "bnq0w")))
+    if ((op[0] == 'b') && (get_b_cc (op) != NULL))
+      return 1;
+  return 0;
+}
+
+/* Cinv instruction requires special handling.  */
+
+static int
+check_cinv_options (char * operand)
+{
+  char *p = operand;
+  int i_used = 0, u_used = 0, d_used = 0;
+
+  while (*++p != ']')
+    {
+      if (*p == ',' || *p == ' ')
+        continue;
+
+      else if (*p == 'i')
+        i_used = 1;
+      else if (*p == 'u')
+        u_used = 1;
+      else if (*p == 'd')
+        d_used = 1;
+      else
+        as_bad (_("Illegal `cinv' parameter: `%c'"), *p);
+    }
+
+  return 0;
+}
+
+/* Retrieve the opcode image of a given register pair.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getregp_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = cr16_regptab + r;
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown register pair: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define RPAIR_IMAGE_ERR \
+  as_bad (_("Illegal register pair (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                                 \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_RP_REGTYPE:
+      return reg->image;
+    default:
+      RPAIR_IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Retrieve the opcode image of a given index register pair.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getidxregp_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = cr16_regptab + r;
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown register pair: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define IDX_RPAIR_IMAGE_ERR \
+  as_bad (_("Illegal index register pair (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                                       \
+
+  if (reg->type == CR16_RP_REGTYPE)
+    {
+      switch (reg->image)
+	{
+	case 0:  return 0; break;
+	case 2:  return 1; break;
+	case 4:  return 2; break;
+	case 6:  return 3; break;
+	case 8:  return 4; break;
+	case 10: return 5; break;
+	case 3:  return 6; break;
+	case 5:  return 7; break;
+	default:
+	  break;
+	}
+    }
+
+  IDX_RPAIR_IMAGE_ERR;
+  return 0;
+}
+
+/* Retrieve the opcode image of a given processort register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+static int
+getprocreg_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_PREG)
+    reg = &cr16_pregtab[r - MAX_REG];
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown processor register : `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define PROCREG_IMAGE_ERR \
+  as_bad (_("Illegal processor register (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                                      \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_P_REGTYPE:
+      return reg->image;
+    default:
+      PROCREG_IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Retrieve the opcode image of a given processort register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+static int
+getprocregp_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+  int pregptab_disp = 0;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_PREG)
+    {
+      r = r - MAX_REG;
+      switch (r)
+        {
+	case 4: pregptab_disp = 1;  break;
+	case 6: pregptab_disp = 2;  break;
+	case 8:
+	case 9:
+	case 10:
+	  pregptab_disp = 3;  break;
+	case 12:
+	  pregptab_disp = 4;  break;
+	case 14:
+	  pregptab_disp = 5;  break;
+	default: break;
+        }
+      reg = &cr16_pregptab[r - pregptab_disp];
+    }
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown processor register (32 bit) : `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define PROCREGP_IMAGE_ERR \
+  as_bad (_("Illegal 32 bit - processor register (`%s') in Instruction: `%s'"),\
+            reg_name, ins_parse);                                              \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_P_REGTYPE:
+      return reg->image;
+    default:
+      PROCREGP_IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Routine used to represent integer X using NBITS bits.  */
+
+static long
+getconstant (long x, int nbits)
+{
+  /* The following expression avoids overflow if
+     'nbits' is the number of bits in 'bfd_vma'.  */
+  return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1));
+}
+
+/* Print a constant value to 'output_opcode':
+   ARG holds the operand's type and value.
+   SHIFT represents the location of the operand to be print into.
+   NBITS determines the size (in bits) of the constant.  */
+
+static void
+print_constant (int nbits, int shift, argument *arg)
+{
+  unsigned long mask = 0;
+
+  long constant = getconstant (arg->constant, nbits);
+
+  switch (nbits)
+    {
+    case 32:
+    case 28:
+      /* mask the upper part of the constant, that is, the bits
+	 going to the lowest byte of output_opcode[0].
+	 The upper part of output_opcode[1] is always filled,
+	 therefore it is always masked with 0xFFFF.  */
+      mask = (1 << (nbits - 16)) - 1;
+      /* Divide the constant between two consecutive words :
+	 0        1         2         3
+	 +---------+---------+---------+---------+
+	 |         | X X X X | x X x X |         |
+	 +---------+---------+---------+---------+
+	 output_opcode[0]    output_opcode[1]     */
+
+      CR16_PRINT (0, (constant >> WORD_SHIFT) & mask, 0);
+      CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+      break;
+
+    case 21:
+      if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS))) nbits = 20;
+    case 24:
+    case 22:
+    case 20:
+      /* mask the upper part of the constant, that is, the bits
+	 going to the lowest byte of output_opcode[0].
+	 The upper part of output_opcode[1] is always filled,
+	 therefore it is always masked with 0xFFFF.  */
+      mask = (1 << (nbits - 16)) - 1;
+      /* Divide the constant between two consecutive words :
+	 0        1         2          3
+	 +---------+---------+---------+---------+
+	 |         | X X X X | - X - X |         |
+	 +---------+---------+---------+---------+
+	 output_opcode[0]    output_opcode[1]     */
+
+      if ((instruction->size > 2) && (shift == WORD_SHIFT))
+	{
+	  if (arg->type == arg_idxrp)
+	    {
+	      CR16_PRINT (0, ((constant >> WORD_SHIFT) & mask) << 8, 0);
+	      CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+	    }
+	  else
+	    {
+	      CR16_PRINT (0, (((((constant >> WORD_SHIFT) & mask) << 8) & 0x0f00) | ((((constant >> WORD_SHIFT) & mask) >> 4) & 0xf)),0);
+	      CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+	    }
+	}
+      else
+	CR16_PRINT (0, constant, shift);
+      break;
+
+    case 14:
+      if (arg->type == arg_idxrp)
+	{
+	  if (instruction->size == 2)
+	    {
+	      CR16_PRINT (0, ((constant)&0xf), shift);         // 0-3 bits
+	      CR16_PRINT (0, ((constant>>4)&0x3), (shift+20)); // 4-5 bits
+	      CR16_PRINT (0, ((constant>>6)&0x3), (shift+14)); // 6-7 bits
+	      CR16_PRINT (0, ((constant>>8)&0x3f), (shift+8)); // 8-13 bits
+	    }
+	  else
+	    CR16_PRINT (0, constant, shift);
+	}
+      break;
+
+    case 16:
+    case 12:
+      /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
+	 always filling the upper part of output_opcode[1]. If we mistakenly
+	 write it to output_opcode[0], the constant prefix (that is, 'match')
+	 will be overriden.
+	 0        1         2         3
+	 +---------+---------+---------+---------+
+	 | 'match' |         | X X X X |         |
+	 +---------+---------+---------+---------+
+	 output_opcode[0]    output_opcode[1]     */
+
+      if ((instruction->size > 2) && (shift == WORD_SHIFT))
+	CR16_PRINT (1, constant, WORD_SHIFT);
+      else
+	CR16_PRINT (0, constant, shift);
+      break;
+
+    case 8:
+      CR16_PRINT (0, ((constant/2)&0xf), shift);
+      CR16_PRINT (0, ((constant/2)>>4),  (shift+8));
+      break;
+
+    default:
+      CR16_PRINT (0, constant,  shift);
+      break;
+    }
+}
+
+/* Print an operand to 'output_opcode', which later on will be
+   printed to the object file:
+   ARG holds the operand's type, size and value.
+   SHIFT represents the printing location of operand.
+   NBITS determines the size (in bits) of a constant operand.  */
+
+static void
+print_operand (int nbits, int shift, argument *arg)
+{
+  switch (arg->type)
+    {
+    case arg_cc:
+      CR16_PRINT (0, arg->cc, shift);
+      break;
+
+    case arg_r:
+      CR16_PRINT (0, getreg_image (arg->r), shift);
+      break;
+
+    case arg_rp:
+      CR16_PRINT (0, getregp_image (arg->rp), shift);
+      break;
+
+    case arg_pr:
+      CR16_PRINT (0, getprocreg_image (arg->pr), shift);
+      break;
+
+    case arg_prp:
+      CR16_PRINT (0, getprocregp_image (arg->prp), shift);
+      break;
+
+    case arg_idxrp:
+      /*    16      12      8    6      0
+            +-----------------------------+
+            | r_index | disp  | rp_base   |
+            +-----------------------------+          */
+
+      if (instruction->size == 3)
+	{
+	  CR16_PRINT (0, getidxregp_image (arg->rp), 0);
+	  if (getreg_image (arg->i_r) == 12)
+	    CR16_PRINT (0, 0, 3);
+	  else
+	    CR16_PRINT (0, 1, 3);
+	}
+      else
+	{
+	  CR16_PRINT (0, getidxregp_image (arg->rp), 16);
+	  if (getreg_image (arg->i_r) == 12)
+	    CR16_PRINT (0, 0, 19);
+	  else
+	    CR16_PRINT (0, 1, 19);
+	}
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_idxr:
+      if (getreg_image (arg->i_r) == 12)
+	if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
+	    || IS_INSN_MNEMONIC ("tbitb"))
+	  CR16_PRINT (0, 0, 23);
+	else CR16_PRINT (0, 0, 24);
+      else
+	if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
+	    || IS_INSN_MNEMONIC ("tbitb"))
+	  CR16_PRINT (0, 1, 23);
+	else CR16_PRINT (0, 1, 24);
+
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_ic:
+    case arg_c:
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_rbase:
+      CR16_PRINT (0, getreg_image (arg->r), shift);
+      break;
+
+    case arg_cr:
+      print_constant (nbits, shift , arg);
+      /* Add the register argument to the output_opcode.  */
+      CR16_PRINT (0, getreg_image (arg->r), (shift+16));
+      break;
+
+    case arg_crp:
+      print_constant (nbits, shift , arg);
+      if (instruction->size > 1)
+	CR16_PRINT (0, getregp_image (arg->rp), (shift + 16));
+      else if (IS_INSN_TYPE (LD_STOR_INS) || (IS_INSN_TYPE (CSTBIT_INS)))
+	{
+	  if (instruction->size == 2)
+	    CR16_PRINT (0, getregp_image (arg->rp), (shift - 8));
+	  else if (instruction->size == 1)
+	    CR16_PRINT (0, getregp_image (arg->rp), 16);
+	}
+      else
+	CR16_PRINT (0, getregp_image (arg->rp), shift);
+      break;
+
+    default:
+      break;
+    }
+}
+
+/* Retrieve the number of operands for the current assembled instruction.  */
+
+static int
+get_number_of_operands (void)
+{
+  int i;
+
+  for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
+    ;
+  return i;
+}
+
+/* Verify that the number NUM can be represented in BITS bits (that is,
+   within its permitted range), based on the instruction's FLAGS.
+   If UPDATE is nonzero, update the value of NUM if necessary.
+   Return OP_LEGAL upon success, actual error type upon failure.  */
+
+static op_err
+check_range (long *num, int bits, int unsigned flags, int update)
+{
+  long min, max;
+  int retval = OP_LEGAL;
+  long value = *num;
+
+  if (bits == 0 && value > 0) return OP_OUT_OF_RANGE;
+
+  /* For hosts witah longs bigger than 32-bits make sure that the top
+     bits of a 32-bit negative value read in by the parser are set,
+     so that the correct comparisons are made.  */
+  if (value & 0x80000000)
+    value |= (-1L << 31);
+
+
+  /* Verify operand value is even.  */
+  if (flags & OP_EVEN)
+    {
+      if (value % 2)
+        return OP_NOT_EVEN;
+    }
+
+  if (flags & OP_DEC)
+    {
+      value -= 1;
+      if (update)
+        *num = value;
+    }
+
+  if (flags & OP_SHIFT)
+    {
+      value >>= 1;
+      if (update)
+        *num = value;
+    }
+  else if (flags & OP_SHIFT_DEC)
+    {
+      value = (value >> 1) - 1;
+      if (update)
+        *num = value;
+    }
+
+  if (flags & OP_ABS20)
+    {
+      if (value > 0xEFFFF)
+        return OP_OUT_OF_RANGE;
+    }
+
+  if (flags & OP_ESC)
+    {
+      if (value == 0xB || value == 0x9)
+        return OP_OUT_OF_RANGE;
+      else if (value == -1)
+	{
+	  if (update)
+	    *num = 9;
+	  return retval;
+	}
+    }
+
+  if (flags & OP_ESC1)
+    {
+      if (value > 13)
+        return OP_OUT_OF_RANGE;
+    }
+
+   if (flags & OP_SIGNED)
+     {
+       max = (1 << (bits - 1)) - 1;
+       min = - (1 << (bits - 1));
+       if ((value > max) || (value < min))
+         retval = OP_OUT_OF_RANGE;
+     }
+   else if (flags & OP_UNSIGNED)
+     {
+       max = ((((1 << (bits - 1)) - 1) << 1) | 1);
+       min = 0;
+       if (((unsigned long) value > (unsigned long) max)
+            || ((unsigned long) value < (unsigned long) min))
+         retval = OP_OUT_OF_RANGE;
+     }
+   else if (flags & OP_NEG)
+     {
+       max = - 1;
+       min = - ((1 << (bits - 1))-1);
+       if ((value > max) || (value < min))
+         retval = OP_OUT_OF_RANGE;
+     }
+   return retval;
+}
+
+/* Bunch of error checkings.
+   The checks are made after a matching instruction was found.  */
+
+static void
+warn_if_needed (ins *insn)
+{
+  /* If the post-increment address mode is used and the load/store
+     source register is the same as rbase, the result of the
+     instruction is undefined.  */
+  if (IS_INSN_TYPE (LD_STOR_INS_INC))
+    {
+      /* Enough to verify that one of the arguments is a simple reg.  */
+      if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
+        if (insn->arg[0].r == insn->arg[1].r)
+          as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), insn->arg[0].r);
+    }
+
+  if (IS_INSN_MNEMONIC ("pop")
+      || IS_INSN_MNEMONIC ("push")
+      || IS_INSN_MNEMONIC ("popret"))
+    {
+      unsigned int count = insn->arg[0].constant, reg_val;
+
+      /* Check if count operand caused to save/retrive the RA twice
+	 to generate warning message.  */
+     if (insn->nargs > 2)
+       {
+         reg_val = getreg_image (insn->arg[1].r);
+
+         if (   ((reg_val == 9) &&  (count > 7))
+	     || ((reg_val == 10) && (count > 6))
+	     || ((reg_val == 11) && (count > 5))
+	     || ((reg_val == 12) && (count > 4))
+	     || ((reg_val == 13) && (count > 2))
+	     || ((reg_val == 14) && (count > 0)))
+           as_warn (_("RA register is saved twice."));
+
+         /* Check if the third operand is "RA" or "ra" */
+         if (!(((insn->arg[2].r) == ra) || ((insn->arg[2].r) == RA)))
+           as_bad (_("`%s' Illegal use of registers."), ins_parse);
+       }
+
+      if (insn->nargs > 1)
+       {
+         reg_val = getreg_image (insn->arg[1].r);
+
+         /* If register is a register pair ie r12/r13/r14 in operand1, then
+            the count constant should be validated.  */
+         if (((reg_val == 11) && (count > 7))
+	     || ((reg_val == 12) && (count > 6))
+	     || ((reg_val == 13) && (count > 4))
+	     || ((reg_val == 14) && (count > 2))
+	     || ((reg_val == 15) && (count > 0)))
+           as_bad (_("`%s' Illegal count-register combination."), ins_parse);
+       }
+     else
+       {
+         /* Check if the operand is "RA" or "ra" */
+         if (!(((insn->arg[0].r) == ra) || ((insn->arg[0].r) == RA)))
+           as_bad (_("`%s' Illegal use of register."), ins_parse);
+       }
+    }
+
+  /* Some instruction assume the stack pointer as rptr operand.
+     Issue an error when the register to be loaded is also SP.  */
+  if (instruction->flags & NO_SP)
+    {
+      if (getreg_image (insn->arg[1].r) == getreg_image (sp))
+        as_bad (_("`%s' has undefined result"), ins_parse);
+    }
+
+  /* If the rptr register is specified as one of the registers to be loaded,
+     the final contents of rptr are undefined. Thus, we issue an error.  */
+  if (instruction->flags & NO_RPTR)
+    {
+      if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
+        as_bad (_("Same src/dest register is used (`r%d'),result is undefined"),
+                  getreg_image (insn->arg[0].r));
+    }
+}
+
+/* In some cases, we need to adjust the instruction pointer although a
+   match was already found. Here, we gather all these cases.
+   Returns 1 if instruction pointer was adjusted, otherwise 0.  */
+
+static int
+adjust_if_needed (ins *insn ATTRIBUTE_UNUSED)
+{
+  int ret_value = 0;
+
+  if ((IS_INSN_TYPE (CSTBIT_INS)) || (IS_INSN_TYPE (LD_STOR_INS)))
+    {
+      if ((instruction->operands[0].op_type == abs24)
+           && ((insn->arg[0].constant) > 0xF00000))
+        {
+          insn->arg[0].constant &= 0xFFFFF;
+          instruction--;
+          ret_value = 1;
+        }
+    }
+
+  return ret_value;
+}
+
+/* Assemble a single instruction:
+   INSN is already parsed (that is, all operand values and types are set).
+   For instruction to be assembled, we need to find an appropriate template in
+   the instruction table, meeting the following conditions:
+    1: Has the same number of operands.
+    2: Has the same operand types.
+    3: Each operand size is sufficient to represent the instruction's values.
+   Returns 1 upon success, 0 upon failure.  */
+
+static int
+assemble_insn (char *mnemonic, ins *insn)
+{
+  /* Type of each operand in the current template.  */
+  argtype cur_type[MAX_OPERANDS];
+  /* Size (in bits) of each operand in the current template.  */
+  unsigned int cur_size[MAX_OPERANDS];
+  /* Flags of each operand in the current template.  */
+  unsigned int cur_flags[MAX_OPERANDS];
+  /* Instruction type to match.  */
+  unsigned int ins_type;
+  /* Boolean flag to mark whether a match was found.  */
+  int match = 0;
+  int i;
+  /* Nonzero if an instruction with same number of operands was found.  */
+  int found_same_number_of_operands = 0;
+  /* Nonzero if an instruction with same argument types was found.  */
+  int found_same_argument_types = 0;
+  /* Nonzero if a constant was found within the required range.  */
+  int found_const_within_range  = 0;
+  /* Argument number of an operand with invalid type.  */
+  int invalid_optype = -1;
+  /* Argument number of an operand with invalid constant value.  */
+  int invalid_const  = -1;
+  /* Operand error (used for issuing various constant error messages).  */
+  op_err op_error, const_err = OP_LEGAL;
+
+/* Retrieve data (based on FUNC) for each operand of a given instruction.  */
+#define GET_CURRENT_DATA(FUNC, ARRAY)                           \
+  for (i = 0; i < insn->nargs; i++)                             \
+    ARRAY[i] = FUNC (instruction->operands[i].op_type)
+
+#define GET_CURRENT_TYPE    GET_CURRENT_DATA (get_optype, cur_type)
+#define GET_CURRENT_SIZE    GET_CURRENT_DATA (get_opbits, cur_size)
+#define GET_CURRENT_FLAGS   GET_CURRENT_DATA (get_opflags, cur_flags)
+
+  /* Instruction has no operands -> only copy the constant opcode.   */
+  if (insn->nargs == 0)
+    {
+      output_opcode[0] = BIN (instruction->match, instruction->match_bits);
+      return 1;
+    }
+
+  /* In some case, same mnemonic can appear with different instruction types.
+     For example, 'storb' is supported with 3 different types :
+     LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
+     We assume that when reaching this point, the instruction type was
+     pre-determined. We need to make sure that the type stays the same
+     during a search for matching instruction.  */
+  ins_type = CR16_INS_TYPE (instruction->flags);
+
+  while (/* Check that match is still not found.  */
+         match != 1
+         /* Check we didn't get to end of table.  */
+         && instruction->mnemonic != NULL
+         /* Check that the actual mnemonic is still available.  */
+         && IS_INSN_MNEMONIC (mnemonic)
+         /* Check that the instruction type wasn't changed.  */
+         && IS_INSN_TYPE (ins_type))
+    {
+      /* Check whether number of arguments is legal.  */
+      if (get_number_of_operands () != insn->nargs)
+        goto next_insn;
+      found_same_number_of_operands = 1;
+
+      /* Initialize arrays with data of each operand in current template.  */
+      GET_CURRENT_TYPE;
+      GET_CURRENT_SIZE;
+      GET_CURRENT_FLAGS;
+
+      /* Check for type compatibility.  */
+      for (i = 0; i < insn->nargs; i++)
+        {
+          if (cur_type[i] != insn->arg[i].type)
+            {
+              if (invalid_optype == -1)
+                invalid_optype = i + 1;
+              goto next_insn;
+            }
+        }
+      found_same_argument_types = 1;
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+          /* If 'bal' instruction size is '2' and reg operand is not 'ra'
+             then goto next instruction.  */
+          if (IS_INSN_MNEMONIC ("bal") && (i == 0)
+	      && (instruction->size == 2) && (insn->arg[i].rp != 14))
+            goto next_insn;
+
+          /* If 'storb' instruction with 'sp' reg and 16-bit disp of
+           * reg-pair, leads to undifined trap, so this should use
+           * 20-bit disp of reg-pair.  */
+          if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2)
+	      && (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp))
+            goto next_insn;
+
+          /* Only check range - don't update the constant's value, since the
+             current instruction may not be the last we try to match.
+             The constant's value will be updated later, right before printing
+             it to the object file.  */
+          if ((insn->arg[i].X_op == O_constant)
+              && (op_error = check_range (&insn->arg[i].constant, cur_size[i],
+                                          cur_flags[i], 0)))
+            {
+              if (invalid_const == -1)
+                {
+                  invalid_const = i + 1;
+                  const_err = op_error;
+                }
+              goto next_insn;
+            }
+          /* For symbols, we make sure the relocation size (which was already
+             determined) is sufficient.  */
+          else if ((insn->arg[i].X_op == O_symbol)
+                   && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
+		       > cur_size[i]))
+                  goto next_insn;
+        }
+      found_const_within_range = 1;
+
+      /* If we got till here -> Full match is found.  */
+      match = 1;
+      break;
+
+/* Try again with next instruction.  */
+next_insn:
+      instruction++;
+    }
+
+  if (!match)
+    {
+      /* We haven't found a match - instruction can't be assembled.  */
+      if (!found_same_number_of_operands)
+        as_bad (_("Incorrect number of operands"));
+      else if (!found_same_argument_types)
+        as_bad (_("Illegal type of operand (arg %d)"), invalid_optype);
+      else if (!found_const_within_range)
+        {
+          switch (const_err)
+            {
+	    case OP_OUT_OF_RANGE:
+	      as_bad (_("Operand out of range (arg %d)"), invalid_const);
+	      break;
+	    case OP_NOT_EVEN:
+	      as_bad (_("Operand has odd displacement (arg %d)"), invalid_const);
+	      break;
+	    default:
+	      as_bad (_("Illegal operand (arg %d)"), invalid_const);
+	      break;
+            }
+        }
+
+       return 0;
+    }
+  else
+    /* Full match - print the encoding to output file.  */
+    {
+      /* Make further checkings (such that couldn't be made earlier).
+         Warn the user if necessary.  */
+      warn_if_needed (insn);
+
+      /* Check whether we need to adjust the instruction pointer.  */
+      if (adjust_if_needed (insn))
+        /* If instruction pointer was adjusted, we need to update
+           the size of the current template operands.  */
+        GET_CURRENT_SIZE;
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+          int j = instruction->flags & REVERSE_MATCH ?
+                  i == 0 ? 1 :
+                  i == 1 ? 0 : i :
+                  i;
+
+          /* This time, update constant value before printing it.  */
+            if ((insn->arg[j].X_op == O_constant)
+               && (check_range (&insn->arg[j].constant, cur_size[j],
+                                cur_flags[j], 1) != OP_LEGAL))
+              as_fatal (_("Illegal operand (arg %d)"), j+1);
+        }
+
+      /* First, copy the instruction's opcode.  */
+      output_opcode[0] = BIN (instruction->match, instruction->match_bits);
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+         /* For BAL (ra),disp17 instuction only. And also set the
+            DISP24a relocation type.  */
+         if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0)
+           {
+             insn->rtype = BFD_RELOC_CR16_DISP24a;
+             continue;
+           }
+          cur_arg_num = i;
+          print_operand (cur_size[i], instruction->operands[i].shift,
+                         &insn->arg[i]);
+        }
+    }
+
+  return 1;
+}
+
+/* Print the instruction.
+   Handle also cases where the instruction is relaxable/relocatable.  */
+
+static void
+print_insn (ins *insn)
+{
+  unsigned int i, j, insn_size;
+  char *this_frag;
+  unsigned short words[4];
+  int addr_mod;
+
+  /* Arrange the insn encodings in a WORD size array.  */
+  for (i = 0, j = 0; i < 2; i++)
+    {
+      words[j++] = (output_opcode[i] >> 16) & 0xFFFF;
+      words[j++] = output_opcode[i] & 0xFFFF;
+    }
+
+    insn_size = instruction->size;
+    this_frag = frag_more (insn_size * 2);
+
+    /* Handle relocation.  */
+    if ((relocatable) && (insn->rtype != BFD_RELOC_NONE))
+      {
+         reloc_howto_type *reloc_howto;
+         int size;
+
+         reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
+
+         if (!reloc_howto)
+           abort ();
+
+         size = bfd_get_reloc_size (reloc_howto);
+
+         if (size < 1 || size > 4)
+           abort ();
+
+         fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+                      size, &insn->exp, reloc_howto->pc_relative,
+                      insn->rtype);
+      }
+
+  /* Verify a 2-byte code alignment.  */
+  addr_mod = frag_now_fix () & 1;
+  if (frag_now->has_code && frag_now->insn_addr != addr_mod)
+    as_bad (_("instruction address is not a multiple of 2"));
+  frag_now->insn_addr = addr_mod;
+  frag_now->has_code = 1;
+
+  /* Write the instruction encoding to frag.  */
+  for (i = 0; i < insn_size; i++)
+    {
+      md_number_to_chars (this_frag, (valueT) words[i], 2);
+      this_frag += 2;
+    }
+}
+
+/* This is the guts of the machine-dependent assembler.  OP points to a
+   machine dependent instruction.  This function is supposed to emit
+   the frags/bytes it assembles to.  */
+
+void
+md_assemble (char *op)
+{
+  ins cr16_ins;
+  char *param, param1[32];
+  char c;
+
+  /* Reset global variables for a new instruction.  */
+  reset_vars (op);
+
+  /* Strip the mnemonic.  */
+  for (param = op; *param != 0 && !ISSPACE (*param); param++)
+    ;
+  c = *param;
+  *param++ = '\0';
+
+  /* bCC instuctions and adjust the mnemonic by adding extra white spaces.  */
+  if (is_bcc_insn (op))
+    {
+      strcpy (param1, get_b_cc (op));
+      op = "b";
+      strcat (param1,",");
+      strcat (param1, param);
+      param = (char *) &param1;
+    }
+
+  /* Checking the cinv options and adjust the mnemonic by removing the
+     extra white spaces.  */
+  if (streq ("cinv", op))
+    {
+     /* Validate the cinv options.  */
+      check_cinv_options (param);
+      strcat (op, param);
+    }
+
+  /* MAPPING - SHIFT INSN, if imm4/imm16 positive values
+     lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg
+     as CR16 core doesn't support lsh[b/w] right shift operaions.  */
+  if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op))
+      && (param [0] == '$'))
+    {
+      strcpy (param1, param);
+      /* Find the instruction.  */
+      instruction = (const inst *) hash_find (cr16_inst_hash, op);
+       parse_operands (&cr16_ins, param1);
+      if (((&cr16_ins)->arg[0].type == arg_ic)
+	  && ((&cr16_ins)->arg[0].constant >= 0))
+        {
+           if (streq ("lshb", op))
+	     op = "ashub";
+           else if (streq ("lshd", op))
+	     op = "ashud";
+	   else
+	     op = "ashuw";
+        }
+    }
+
+  /* Find the instruction.  */
+  instruction = (const inst *) hash_find (cr16_inst_hash, op);
+  if (instruction == NULL)
+    {
+      as_bad (_("Unknown opcode: `%s'"), op);
+      return;
+    }
+
+  /* Tie dwarf2 debug info to the address at the start of the insn.  */
+  dwarf2_emit_insn (0);
+
+  /* Parse the instruction's operands.  */
+  parse_insn (&cr16_ins, param);
+
+  /* Assemble the instruction - return upon failure.  */
+  if (assemble_insn (op, &cr16_ins) == 0)
+    return;
+
+  /* Print the instruction.  */
+  print_insn (&cr16_ins);
+}
diff --git a/contrib/binutils/gas/config/tc-cr16.h b/contrib/binutils/gas/config/tc-cr16.h
new file mode 100644
index 0000000..6d06151
--- /dev/null
+++ b/contrib/binutils/gas/config/tc-cr16.h
@@ -0,0 +1,73 @@
+/* tc-cr16.h -- Header file for tc-cr16.c, the CR16 GAS port.
+   Copyright 2007 Free Software Foundation, Inc.
+
+   Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef TC_CR16_H
+#define TC_CR16_H
+
+#define TC_CR16 1
+
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define TARGET_FORMAT "elf32-cr16"
+#define TARGET_ARCH   bfd_arch_cr16
+
+#define WORKING_DOT_WORD
+#define LOCAL_LABEL_PREFIX '.'
+
+#define md_undefined_symbol(s)  0
+#define md_number_to_chars      number_to_chars_littleendian
+
+/* We do relaxing in the assembler as well as the linker.  */
+extern const struct relax_type md_relax_table[];
+#define TC_GENERIC_RELAX_TABLE md_relax_table
+
+/* We do not want to adjust any relocations to make implementation of
+   linker relaxations easier.  */
+#define tc_fix_adjustable(fixP)  0
+
+/* We need to force out some relocations when relaxing.  */
+#define TC_FORCE_RELOCATION(FIXP) cr16_force_relocation (FIXP)
+extern int cr16_force_relocation (struct fix *);
+
+/* Fixup debug sections since we will never relax them.  */
+#define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_ALLOC)
+
+/* CR16 instructions, with operands included, are a multiple
+   of two bytes long.  */
+#define DWARF2_LINE_MIN_INSN_LENGTH 2
+
+extern void cr16_cons_fix_new (struct frag *, int, int, struct expressionS *);
+/* This is called by emit_expr when creating a reloc for a cons.
+   We could use the definition there, except that we want to handle 
+   the CR16 reloc type specially, rather than the BFD_RELOC type.  */
+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \
+  cr16_cons_fix_new (FRAG, OFF, LEN, EXP) 
+
+/* Give an error if a frag containing code is not aligned to a 2-byte 
+   boundary.  */
+#define md_frag_check(FRAGP) \
+  if ((FRAGP)->has_code                                                \
+      && (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 1) != 0)        \
+     as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line,                 \
+                  _("instruction address is not a multiple of 2"));
+
+#endif /* TC_CR16_H */
diff --git a/contrib/binutils/gas/config/tc-i386.c b/contrib/binutils/gas/config/tc-i386.c
index be384bc..296fdcd 100644
--- a/contrib/binutils/gas/config/tc-i386.c
+++ b/contrib/binutils/gas/config/tc-i386.c
@@ -1,6 +1,6 @@
-/* i386.c -- Assemble code for the Intel 80386
+/* tc-i386.c -- Assemble code for the Intel 80386
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004, 2005, 2006
+   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -32,7 +32,6 @@
 #include "subsegs.h"
 #include "dwarf2dbg.h"
 #include "dw2gencfi.h"
-#include "opcode/i386.h"
 #include "elf/x86-64.h"
 
 #ifndef REGISTER_WARNINGS
@@ -63,54 +62,39 @@
 #endif
 #endif
 
-static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
-static INLINE int fits_in_signed_byte PARAMS ((offsetT));
-static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
-static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
-static INLINE int fits_in_signed_word PARAMS ((offsetT));
-static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
-static INLINE int fits_in_signed_long PARAMS ((offsetT));
-static int smallest_imm_type PARAMS ((offsetT));
-static offsetT offset_in_range PARAMS ((offsetT, int));
-static int add_prefix PARAMS ((unsigned int));
-static void set_code_flag PARAMS ((int));
-static void set_16bit_gcc_code_flag PARAMS ((int));
-static void set_intel_syntax PARAMS ((int));
-static void set_cpu_arch PARAMS ((int));
+static void set_code_flag (int);
+static void set_16bit_gcc_code_flag (int);
+static void set_intel_syntax (int);
+static void set_cpu_arch (int);
 #ifdef TE_PE
-static void pe_directive_secrel PARAMS ((int));
+static void pe_directive_secrel (int);
 #endif
-static void signed_cons PARAMS ((int));
-static char *output_invalid PARAMS ((int c));
-static int i386_operand PARAMS ((char *operand_string));
-static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
-static const reg_entry *parse_register PARAMS ((char *reg_string,
-						char **end_op));
-static char *parse_insn PARAMS ((char *, char *));
-static char *parse_operands PARAMS ((char *, const char *));
-static void swap_operands PARAMS ((void));
-static void optimize_imm PARAMS ((void));
-static void optimize_disp PARAMS ((void));
-static int match_template PARAMS ((void));
-static int check_string PARAMS ((void));
-static int process_suffix PARAMS ((void));
-static int check_byte_reg PARAMS ((void));
-static int check_long_reg PARAMS ((void));
-static int check_qword_reg PARAMS ((void));
-static int check_word_reg PARAMS ((void));
-static int finalize_imm PARAMS ((void));
-static int process_operands PARAMS ((void));
-static const seg_entry *build_modrm_byte PARAMS ((void));
-static void output_insn PARAMS ((void));
-static void output_branch PARAMS ((void));
-static void output_jump PARAMS ((void));
-static void output_interseg_jump PARAMS ((void));
-static void output_imm PARAMS ((fragS *insn_start_frag,
-				offsetT insn_start_off));
-static void output_disp PARAMS ((fragS *insn_start_frag,
-				 offsetT insn_start_off));
+static void signed_cons (int);
+static char *output_invalid (int c);
+static int i386_operand (char *);
+static int i386_intel_operand (char *, int);
+static const reg_entry *parse_register (char *, char **);
+static char *parse_insn (char *, char *);
+static char *parse_operands (char *, const char *);
+static void swap_operands (void);
+static void swap_2_operands (int, int);
+static void optimize_imm (void);
+static void optimize_disp (void);
+static int match_template (void);
+static int check_string (void);
+static int process_suffix (void);
+static int check_byte_reg (void);
+static int check_long_reg (void);
+static int check_qword_reg (void);
+static int check_word_reg (void);
+static int finalize_imm (void);
+static int process_operands (void);
+static const seg_entry *build_modrm_byte (void);
+static void output_insn (void);
+static void output_imm (fragS *, offsetT);
+static void output_disp (fragS *, offsetT);
 #ifndef I386COFF
-static void s_bss PARAMS ((int));
+static void s_bss (int);
 #endif
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
 static void handle_large_common (int small ATTRIBUTE_UNUSED);
@@ -271,8 +255,9 @@ static i386_insn i;
 /* Possible templates for current insn.  */
 static const templates *current_templates;
 
-/* Per instruction expressionS buffers: 2 displacements & 2 immediate max.  */
-static expressionS disp_expressions[2], im_expressions[2];
+/* Per instruction expressionS buffers: max displacements & immediates.  */
+static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
+static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
 
 /* Current operand we are working on.  */
 static int this_operand;
@@ -305,6 +290,9 @@ static int intel_syntax = 0;
 /* 1 if register prefix % not required.  */
 static int allow_naked_reg = 0;
 
+/* Register prefix used for error message.  */
+static const char *register_prefix = "%";
+
 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
    leave, push, and pop instructions so that gcc has the same stack
    frame as in 32 bit mode.  */
@@ -323,6 +311,21 @@ static const char *cpu_sub_arch_name = NULL;
 /* CPU feature flags.  */
 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
 
+/* If we have selected a cpu we are generating instructions for.  */
+static int cpu_arch_tune_set = 0;
+
+/* Cpu we are generating instructions for.  */
+static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
+
+/* CPU feature flags of cpu we are generating instructions for.  */
+static unsigned int cpu_arch_tune_flags = 0;
+
+/* CPU instruction set architecture used.  */
+static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
+
+/* CPU feature flags of instruction set architecture used.  */
+static unsigned int cpu_arch_isa_flags = 0;
+
 /* If set, conditional jumps are not automatically promoted to handle
    larger than a byte offset.  */
 static unsigned int no_cond_jump_promotion = 0;
@@ -415,35 +418,106 @@ const relax_typeS md_relax_table[] =
   {0, 0, 4, 0}
 };
 
-static const arch_entry cpu_arch[] = {
-  {"i8086",	Cpu086 },
-  {"i186",	Cpu086|Cpu186 },
-  {"i286",	Cpu086|Cpu186|Cpu286 },
-  {"i386",	Cpu086|Cpu186|Cpu286|Cpu386 },
-  {"i486",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
-  {"i586",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
-  {"i686",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
-  {"pentium",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
-  {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
-  {"pentiumii",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
-  {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
-  {"pentium4",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
-  {"prescott",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
-  {"k6",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
-  {"k6_2",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
-  {"athlon",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
-  {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
-  {"opteron",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
-  {".mmx",	CpuMMX },
-  {".sse",	CpuMMX|CpuMMX2|CpuSSE },
-  {".sse2",	CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
-  {".sse3",	CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
-  {".3dnow",	CpuMMX|Cpu3dnow },
-  {".3dnowa",	CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
-  {".padlock",	CpuPadLock },
-  {".pacifica",	CpuSVME },
-  {".svme",	CpuSVME },
-  {NULL, 0 }
+static const arch_entry cpu_arch[] =
+{
+  {"generic32", PROCESSOR_GENERIC32,
+   Cpu186|Cpu286|Cpu386},
+  {"generic64", PROCESSOR_GENERIC64,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2},
+  {"i8086", PROCESSOR_UNKNOWN,
+   0},
+  {"i186", PROCESSOR_UNKNOWN,
+   Cpu186},
+  {"i286", PROCESSOR_UNKNOWN,
+   Cpu186|Cpu286},
+  {"i386", PROCESSOR_GENERIC32,
+   Cpu186|Cpu286|Cpu386},
+  {"i486", PROCESSOR_I486,
+   Cpu186|Cpu286|Cpu386|Cpu486},
+  {"i586", PROCESSOR_PENTIUM,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
+  {"i686", PROCESSOR_PENTIUMPRO,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
+  {"pentium", PROCESSOR_PENTIUM,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
+  {"pentiumpro",PROCESSOR_PENTIUMPRO,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
+  {"pentiumii",	PROCESSOR_PENTIUMPRO,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
+  {"pentiumiii",PROCESSOR_PENTIUMPRO,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
+  {"pentium4", PROCESSOR_PENTIUM4,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2},
+  {"prescott", PROCESSOR_NOCONA,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {"nocona", PROCESSOR_NOCONA,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {"yonah", PROCESSOR_CORE,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {"core", PROCESSOR_CORE,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {"merom", PROCESSOR_CORE2,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
+  {"core2", PROCESSOR_CORE2,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
+  {"k6", PROCESSOR_K6,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
+  {"k6_2", PROCESSOR_K6,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
+  {"athlon", PROCESSOR_ATHLON,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
+   |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
+  {"sledgehammer", PROCESSOR_K8,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
+   |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
+  {"opteron", PROCESSOR_K8,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
+   |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
+  {"k8", PROCESSOR_K8,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
+   |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
+  {"amdfam10", PROCESSOR_AMDFAM10,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
+   |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
+   |CpuABM},
+  {".mmx", PROCESSOR_UNKNOWN,
+   CpuMMX},
+  {".sse", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE},
+  {".sse2", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
+  {".sse3", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {".ssse3", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
+  {".sse4.1", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
+  {".sse4.2", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
+  {".sse4", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
+  {".3dnow", PROCESSOR_UNKNOWN,
+   CpuMMX|Cpu3dnow},
+  {".3dnowa", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
+  {".padlock", PROCESSOR_UNKNOWN,
+   CpuPadLock},
+  {".pacifica", PROCESSOR_UNKNOWN,
+   CpuSVME},
+  {".svme", PROCESSOR_UNKNOWN,
+   CpuSVME},
+  {".sse4a", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
+  {".abm", PROCESSOR_UNKNOWN,
+   CpuABM}
 };
 
 const pseudo_typeS md_pseudo_table[] =
@@ -473,7 +547,7 @@ const pseudo_typeS md_pseudo_table[] =
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
   {"largecomm", handle_large_common, 0},
 #else
-  {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
+  {"file", (void (*) (int)) dwarf2_directive_file, 0},
   {"loc", dwarf2_directive_loc, 0},
   {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
 #endif
@@ -493,9 +567,7 @@ static struct hash_control *op_hash;
 static struct hash_control *reg_hash;
 
 void
-i386_align_code (fragP, count)
-     fragS *fragP;
-     int count;
+i386_align_code (fragS *fragP, int count)
 {
   /* Various efficient no-op patterns for aligning code labels.
      Note: Don't try to assemble the instructions in the comments.
@@ -503,7 +575,7 @@ i386_align_code (fragP, count)
   static const char f32_1[] =
     {0x90};					/* nop			*/
   static const char f32_2[] =
-    {0x89,0xf6};				/* movl %esi,%esi	*/
+    {0x66,0x90};				/* xchg %ax,%ax */
   static const char f32_3[] =
     {0x8d,0x76,0x00};				/* leal 0(%esi),%esi	*/
   static const char f32_4[] =
@@ -563,13 +635,141 @@ i386_align_code (fragP, count)
     f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
     f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
   };
+  /* nopl (%[re]ax) */
+  static const char alt_3[] =
+    {0x0f,0x1f,0x00};
+  /* nopl 0(%[re]ax) */
+  static const char alt_4[] =
+    {0x0f,0x1f,0x40,0x00};
+  /* nopl 0(%[re]ax,%[re]ax,1) */
+  static const char alt_5[] =
+    {0x0f,0x1f,0x44,0x00,0x00};
+  /* nopw 0(%[re]ax,%[re]ax,1) */
+  static const char alt_6[] =
+    {0x66,0x0f,0x1f,0x44,0x00,0x00};
+  /* nopl 0L(%[re]ax) */
+  static const char alt_7[] =
+    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
+  /* nopl 0L(%[re]ax,%[re]ax,1) */
+  static const char alt_8[] =
+    {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* nopw 0L(%[re]ax,%[re]ax,1) */
+  static const char alt_9[] =
+    {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_10[] =
+    {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_11[] =
+    {0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_12[] =
+    {0x66,
+     0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     data16
+     data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_13[] =
+    {0x66,
+     0x66,
+     0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     data16
+     data16
+     data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_14[] =
+    {0x66,
+     0x66,
+     0x66,
+     0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     data16
+     data16
+     data16
+     data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_15[] =
+    {0x66,
+     0x66,
+     0x66,
+     0x66,
+     0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* nopl 0(%[re]ax,%[re]ax,1)
+     nopw 0(%[re]ax,%[re]ax,1) */
+  static const char alt_short_11[] =
+    {0x0f,0x1f,0x44,0x00,0x00,
+     0x66,0x0f,0x1f,0x44,0x00,0x00};
+  /* nopw 0(%[re]ax,%[re]ax,1)
+     nopw 0(%[re]ax,%[re]ax,1) */
+  static const char alt_short_12[] =
+    {0x66,0x0f,0x1f,0x44,0x00,0x00,
+     0x66,0x0f,0x1f,0x44,0x00,0x00};
+  /* nopw 0(%[re]ax,%[re]ax,1)
+     nopl 0L(%[re]ax) */
+  static const char alt_short_13[] =
+    {0x66,0x0f,0x1f,0x44,0x00,0x00,
+     0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
+  /* nopl 0L(%[re]ax)
+     nopl 0L(%[re]ax) */
+  static const char alt_short_14[] =
+    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
+     0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
+  /* nopl 0L(%[re]ax)
+     nopl 0L(%[re]ax,%[re]ax,1) */
+  static const char alt_short_15[] =
+    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
+     0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  static const char *const alt_short_patt[] = {
+    f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
+    alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
+    alt_short_14, alt_short_15
+  };
+  static const char *const alt_long_patt[] = {
+    f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
+    alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
+    alt_long_14, alt_long_15
+  };
 
   if (count <= 0 || count > 15)
     return;
 
-  /* The recommended way to pad 64bit code is to use NOPs preceded by
-     maximally four 0x66 prefixes.  Balance the size of nops.  */
-  if (flag_code == CODE_64BIT)
+  /* We need to decide which NOP sequence to use for 32bit and
+     64bit. When -mtune= is used:
+
+     1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
+     f32_patt will be used.
+     2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
+     0x66 prefix will be used.
+     3. For PROCESSOR_CORE2, alt_long_patt will be used.
+     4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
+     PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
+     and PROCESSOR_GENERIC64, alt_short_patt will be used.
+
+     When -mtune= isn't used, alt_short_patt will be used if
+     cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
+
+     When -march= or .arch is used, we can't use anything beyond
+     cpu_arch_isa_flags.   */
+
+  if (flag_code == CODE_16BIT)
+    {
+      memcpy (fragP->fr_literal + fragP->fr_fix,
+	      f16_patt[count - 1], count);
+      if (count > 8)
+	/* Adjust jump offset.  */
+	fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
+    }
+  else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
     {
       int i;
       int nnops = (count + 3) / 4;
@@ -577,6 +777,8 @@ i386_align_code (fragP, count)
       int remains = count - nnops * len;
       int pos = 0;
 
+      /* The recommended way to pad 64bit code is to use NOPs preceded
+	 by maximally four 0x66 prefixes.  Balance the size of nops.  */
       for (i = 0; i < remains; i++)
 	{
 	  memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
@@ -591,57 +793,121 @@ i386_align_code (fragP, count)
 	}
     }
   else
-    if (flag_code == CODE_16BIT)
-      {
-	memcpy (fragP->fr_literal + fragP->fr_fix,
-		f16_patt[count - 1], count);
-	if (count > 8)
-	  /* Adjust jump offset.  */
-	  fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
-      }
-    else
+    {
+      const char *const *patt = NULL;
+
+      if (cpu_arch_isa == PROCESSOR_UNKNOWN)
+	{
+	  /* PROCESSOR_UNKNOWN means that all ISAs may be used.  */
+	  switch (cpu_arch_tune)
+	    {
+	    case PROCESSOR_UNKNOWN:
+	      /* We use cpu_arch_isa_flags to check if we SHOULD
+		 optimize for Cpu686.  */
+	      if ((cpu_arch_isa_flags & Cpu686) != 0)
+		patt = alt_short_patt;
+	      else
+		patt = f32_patt;
+	      break;
+	    case PROCESSOR_CORE2:
+	      patt = alt_long_patt;
+	      break;
+	    case PROCESSOR_PENTIUMPRO:
+	    case PROCESSOR_PENTIUM4:
+	    case PROCESSOR_NOCONA:
+	    case PROCESSOR_CORE:
+	    case PROCESSOR_K6:
+	    case PROCESSOR_ATHLON:
+	    case PROCESSOR_K8:
+	    case PROCESSOR_GENERIC64:
+	    case PROCESSOR_AMDFAM10:
+	      patt = alt_short_patt;
+	      break;
+	    case PROCESSOR_I486:
+	    case PROCESSOR_PENTIUM:
+	    case PROCESSOR_GENERIC32:
+	      patt = f32_patt;
+	      break;
+	    }
+	}
+      else
+	{
+	  switch (cpu_arch_tune)
+	    {
+	    case PROCESSOR_UNKNOWN:
+	      /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
+		 PROCESSOR_UNKNOWN.  */
+	      abort ();
+	      break;
+
+	    case PROCESSOR_I486:
+	    case PROCESSOR_PENTIUM:
+	    case PROCESSOR_PENTIUMPRO:
+	    case PROCESSOR_PENTIUM4:
+	    case PROCESSOR_NOCONA:
+	    case PROCESSOR_CORE:
+	    case PROCESSOR_K6:
+	    case PROCESSOR_ATHLON:
+	    case PROCESSOR_K8:
+	    case PROCESSOR_AMDFAM10:
+	    case PROCESSOR_GENERIC32:
+	      /* We use cpu_arch_isa_flags to check if we CAN optimize
+		 for Cpu686.  */
+	      if ((cpu_arch_isa_flags & Cpu686) != 0)
+		patt = alt_short_patt;
+	      else
+		patt = f32_patt;
+	      break;
+	    case PROCESSOR_CORE2:
+	      if ((cpu_arch_isa_flags & Cpu686) != 0)
+		patt = alt_long_patt;
+	      else
+		patt = f32_patt;
+	      break;
+	    case PROCESSOR_GENERIC64:
+	      patt = alt_short_patt;
+	      break;
+	    }
+	}
+
       memcpy (fragP->fr_literal + fragP->fr_fix,
-	      f32_patt[count - 1], count);
+	      patt[count - 1], count);
+    }
   fragP->fr_var = count;
 }
 
 static INLINE unsigned int
-mode_from_disp_size (t)
-     unsigned int t;
+mode_from_disp_size (unsigned int t)
 {
   return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
 }
 
 static INLINE int
-fits_in_signed_byte (num)
-     offsetT num;
+fits_in_signed_byte (offsetT num)
 {
   return (num >= -128) && (num <= 127);
 }
 
 static INLINE int
-fits_in_unsigned_byte (num)
-     offsetT num;
+fits_in_unsigned_byte (offsetT num)
 {
   return (num & 0xff) == num;
 }
 
 static INLINE int
-fits_in_unsigned_word (num)
-     offsetT num;
+fits_in_unsigned_word (offsetT num)
 {
   return (num & 0xffff) == num;
 }
 
 static INLINE int
-fits_in_signed_word (num)
-     offsetT num;
+fits_in_signed_word (offsetT num)
 {
   return (-32768 <= num) && (num <= 32767);
 }
+
 static INLINE int
-fits_in_signed_long (num)
-     offsetT num ATTRIBUTE_UNUSED;
+fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
 {
 #ifndef BFD64
   return 1;
@@ -650,9 +916,9 @@ fits_in_signed_long (num)
 	  || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
 #endif
 }				/* fits_in_signed_long() */
+
 static INLINE int
-fits_in_unsigned_long (num)
-     offsetT num ATTRIBUTE_UNUSED;
+fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
 {
 #ifndef BFD64
   return 1;
@@ -661,11 +927,10 @@ fits_in_unsigned_long (num)
 #endif
 }				/* fits_in_unsigned_long() */
 
-static int
-smallest_imm_type (num)
-     offsetT num;
+static unsigned int
+smallest_imm_type (offsetT num)
 {
-  if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
+  if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
     {
       /* This code is disabled on the 486 because all the Imm1 forms
 	 in the opcode table are slower on the i486.  They're the
@@ -689,9 +954,7 @@ smallest_imm_type (num)
 }
 
 static offsetT
-offset_in_range (val, size)
-     offsetT val;
-     int size;
+offset_in_range (offsetT val, int size)
 {
   addressT mask;
 
@@ -726,8 +989,7 @@ offset_in_range (val, size)
    class already exists, 1 if non rep/repne added, 2 if rep/repne
    added.  */
 static int
-add_prefix (prefix)
-     unsigned int prefix;
+add_prefix (unsigned int prefix)
 {
   int ret = 1;
   unsigned int q;
@@ -735,9 +997,9 @@ add_prefix (prefix)
   if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
       && flag_code == CODE_64BIT)
     {
-      if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
-	  || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
-	      && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
+      if ((i.prefix[REX_PREFIX] & prefix & REX_W)
+	  || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
+	      && (prefix & (REX_R | REX_X | REX_B))))
 	ret = 0;
       q = REX_PREFIX;
     }
@@ -794,8 +1056,7 @@ add_prefix (prefix)
 }
 
 static void
-set_code_flag (value)
-     int value;
+set_code_flag (int value)
 {
   flag_code = value;
   cpu_arch_flags &= ~(Cpu64 | CpuNo64);
@@ -812,8 +1073,7 @@ set_code_flag (value)
 }
 
 static void
-set_16bit_gcc_code_flag (new_code_flag)
-     int new_code_flag;
+set_16bit_gcc_code_flag (int new_code_flag)
 {
   flag_code = new_code_flag;
   cpu_arch_flags &= ~(Cpu64 | CpuNo64);
@@ -822,8 +1082,7 @@ set_16bit_gcc_code_flag (new_code_flag)
 }
 
 static void
-set_intel_syntax (syntax_flag)
-     int syntax_flag;
+set_intel_syntax (int syntax_flag)
 {
   /* Find out if register prefixing is specified.  */
   int ask_naked_reg = 0;
@@ -854,11 +1113,11 @@ set_intel_syntax (syntax_flag)
 
   identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
   identifier_chars['$'] = intel_syntax ? '$' : 0;
+  register_prefix = allow_naked_reg ? "" : "%";
 }
 
 static void
-set_cpu_arch (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
 {
   SKIP_WHITESPACE ();
 
@@ -866,9 +1125,9 @@ set_cpu_arch (dummy)
     {
       char *string = input_line_pointer;
       int e = get_symbol_end ();
-      int i;
+      unsigned int i;
 
-      for (i = 0; cpu_arch[i].name; i++)
+      for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
 	{
 	  if (strcmp (string, cpu_arch[i].name) == 0)
 	    {
@@ -877,7 +1136,15 @@ set_cpu_arch (dummy)
 		  cpu_arch_name = cpu_arch[i].name;
 		  cpu_sub_arch_name = NULL;
 		  cpu_arch_flags = (cpu_arch[i].flags
-				    | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
+				    | (flag_code == CODE_64BIT
+				       ? Cpu64 : CpuNo64));
+		  cpu_arch_isa = cpu_arch[i].type;
+		  cpu_arch_isa_flags = cpu_arch[i].flags;
+		  if (!cpu_arch_tune_set)
+		    {
+		      cpu_arch_tune = cpu_arch_isa;
+		      cpu_arch_tune_flags = cpu_arch_isa_flags;
+		    }
 		  break;
 		}
 	      if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
@@ -890,7 +1157,7 @@ set_cpu_arch (dummy)
 	      return;
 	    }
 	}
-      if (!cpu_arch[i].name)
+      if (i >= ARRAY_SIZE (cpu_arch))
 	as_bad (_("no such architecture: `%s'"), string);
 
       *input_line_pointer = e;
@@ -976,10 +1243,9 @@ md_begin ()
   reg_hash = hash_new ();
   {
     const reg_entry *regtab;
+    unsigned int regtab_size = i386_regtab_size;
 
-    for (regtab = i386_regtab;
-	 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
-	 regtab++)
+    for (regtab = i386_regtab; regtab_size--; regtab++)
       {
 	hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
 	if (hash_err)
@@ -1034,6 +1300,7 @@ md_begin ()
 #endif
     digit_chars['-'] = '-';
     mnemonic_chars['-'] = '-';
+    mnemonic_chars['.'] = '.';
     identifier_chars['_'] = '_';
     identifier_chars['.'] = '.';
 
@@ -1063,8 +1330,7 @@ md_begin ()
 }
 
 void
-i386_print_statistics (file)
-     FILE *file;
+i386_print_statistics (FILE *file)
 {
   hash_print_statistics (file, "i386 opcode", op_hash);
   hash_print_statistics (file, "i386 register", reg_hash);
@@ -1073,16 +1339,13 @@ i386_print_statistics (file)
 #ifdef DEBUG386
 
 /* Debugging routines for md_assemble.  */
-static void pi PARAMS ((char *, i386_insn *));
-static void pte PARAMS ((template *));
-static void pt PARAMS ((unsigned int));
-static void pe PARAMS ((expressionS *));
-static void ps PARAMS ((symbolS *));
+static void pte (template *);
+static void pt (unsigned int);
+static void pe (expressionS *);
+static void ps (symbolS *);
 
 static void
-pi (line, x)
-     char *line;
-     i386_insn *x;
+pi (char *line, i386_insn *x)
 {
   unsigned int i;
 
@@ -1097,10 +1360,10 @@ pi (line, x)
   fprintf (stdout, "  sib:  base %x  index %x  scale %x\n",
 	   x->sib.base, x->sib.index, x->sib.scale);
   fprintf (stdout, "  rex: 64bit %x  extX %x  extY %x  extZ %x\n",
-	   (x->rex & REX_MODE64) != 0,
-	   (x->rex & REX_EXTX) != 0,
-	   (x->rex & REX_EXTY) != 0,
-	   (x->rex & REX_EXTZ) != 0);
+	   (x->rex & REX_W) != 0,
+	   (x->rex & REX_R) != 0,
+	   (x->rex & REX_X) != 0,
+	   (x->rex & REX_B) != 0);
   for (i = 0; i < x->operands; i++)
     {
       fprintf (stdout, "    #%d:  ", i + 1);
@@ -1117,8 +1380,7 @@ pi (line, x)
 }
 
 static void
-pte (t)
-     template *t;
+pte (template *t)
 {
   unsigned int i;
   fprintf (stdout, " %d operands ", t->operands);
@@ -1139,8 +1401,7 @@ pte (t)
 }
 
 static void
-pe (e)
-     expressionS *e;
+pe (expressionS *e)
 {
   fprintf (stdout, "    operation     %d\n", e->X_op);
   fprintf (stdout, "    add_number    %ld (%lx)\n",
@@ -1160,8 +1421,7 @@ pe (e)
 }
 
 static void
-ps (s)
-     symbolS *s;
+ps (symbolS *s)
 {
   fprintf (stdout, "%s type %s%s",
 	   S_GET_NAME (s),
@@ -1226,9 +1486,9 @@ pt (t)
 
 static bfd_reloc_code_real_type
 reloc (unsigned int size,
-     int pcrel,
-     int sign,
-     bfd_reloc_code_real_type other)
+       int pcrel,
+       int sign,
+       bfd_reloc_code_real_type other)
 {
   if (other != NO_RELOC)
     {
@@ -1237,26 +1497,26 @@ reloc (unsigned int size,
       if (size == 8)
 	switch (other)
 	  {
-	    case BFD_RELOC_X86_64_GOT32:
-	      return BFD_RELOC_X86_64_GOT64;
-	      break;
-	    case BFD_RELOC_X86_64_PLTOFF64:
-	      return BFD_RELOC_X86_64_PLTOFF64;
-	      break;
-	    case BFD_RELOC_X86_64_GOTPC32:
-	      other = BFD_RELOC_X86_64_GOTPC64;
-	      break;
-	    case BFD_RELOC_X86_64_GOTPCREL:
-	      other = BFD_RELOC_X86_64_GOTPCREL64;
-	      break;
-	    case BFD_RELOC_X86_64_TPOFF32:
-	      other = BFD_RELOC_X86_64_TPOFF64;
-	      break;
-	    case BFD_RELOC_X86_64_DTPOFF32:
-	      other = BFD_RELOC_X86_64_DTPOFF64;
-	      break;
-	    default:
-	      break;
+	  case BFD_RELOC_X86_64_GOT32:
+	    return BFD_RELOC_X86_64_GOT64;
+	    break;
+	  case BFD_RELOC_X86_64_PLTOFF64:
+	    return BFD_RELOC_X86_64_PLTOFF64;
+	    break;
+	  case BFD_RELOC_X86_64_GOTPC32:
+	    other = BFD_RELOC_X86_64_GOTPC64;
+	    break;
+	  case BFD_RELOC_X86_64_GOTPCREL:
+	    other = BFD_RELOC_X86_64_GOTPCREL64;
+	    break;
+	  case BFD_RELOC_X86_64_TPOFF32:
+	    other = BFD_RELOC_X86_64_TPOFF64;
+	    break;
+	  case BFD_RELOC_X86_64_DTPOFF32:
+	    other = BFD_RELOC_X86_64_DTPOFF64;
+	    break;
+	  default:
+	    break;
 	  }
 
       /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless.  */
@@ -1275,7 +1535,7 @@ reloc (unsigned int size,
       else if ((reloc->complain_on_overflow == complain_overflow_signed
 		&& !sign)
 	       || (reloc->complain_on_overflow == complain_overflow_unsigned
-		&& sign > 0))
+		   && sign > 0))
 	as_bad (_("relocated field and relocation type differ in signedness"));
       else
 	return other;
@@ -1324,8 +1584,7 @@ reloc (unsigned int size,
    some cases we force the original symbol to be used.  */
 
 int
-tc_i386_fix_adjustable (fixP)
-     fixS *fixP ATTRIBUTE_UNUSED;
+tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
 {
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
   if (!IS_ELF)
@@ -1378,11 +1637,8 @@ tc_i386_fix_adjustable (fixP)
   return 1;
 }
 
-static int intel_float_operand PARAMS ((const char *mnemonic));
-
 static int
-intel_float_operand (mnemonic)
-     const char *mnemonic;
+intel_float_operand (const char *mnemonic)
 {
   /* Note that the value returned is meaningful only for opcodes with (memory)
      operands, hence the code here is free to improperly handle opcodes that
@@ -1465,16 +1721,29 @@ md_assemble (line)
   if (line == NULL)
     return;
 
+  /* The order of the immediates should be reversed
+     for 2 immediates extrq and insertq instructions */
+  if ((i.imm_operands == 2)
+      && ((strcmp (mnemonic, "extrq") == 0)
+	  || (strcmp (mnemonic, "insertq") == 0)))
+    {
+      swap_2_operands (0, 1);
+      /* "extrq" and insertq" are the only two instructions whose operands
+	 have to be reversed even though they have two immediate operands.
+      */
+      if (intel_syntax)
+	swap_operands ();
+    }
+
   /* Now we've parsed the mnemonic into a set of templates, and have the
      operands at hand.  */
 
   /* All intel opcodes have reversed operands except for "bound" and
      "enter".  We also don't reverse intersegment "jmp" and "call"
      instructions with 2 immediate operands so that the immediate segment
-     precedes the offset, as it does when in AT&T mode.  "enter" and the
-     intersegment "jmp" and "call" instructions are the only ones that
-     have two immediate operands.  */
-  if (intel_syntax && i.operands > 1
+     precedes the offset, as it does when in AT&T mode. */
+  if (intel_syntax
+      && i.operands > 1
       && (strcmp (mnemonic, "bound") != 0)
       && (strcmp (mnemonic, "invlpga") != 0)
       && !((i.types[0] & Imm) && (i.types[1] & Imm)))
@@ -1502,7 +1771,7 @@ md_assemble (line)
       /* Undo SYSV386_COMPAT brokenness when in Intel mode.  See i386.h  */
       if (SYSV386_COMPAT
 	  && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
-	i.tm.base_opcode ^= FloatR;
+	i.tm.base_opcode ^= Opcode_FloatR;
 
       /* Zap movzx and movsx suffix.  The suffix may have been set from
 	 "word ptr" or "byte ptr" on the source operand, but we'll use
@@ -1556,9 +1825,9 @@ md_assemble (line)
     {
       expressionS *exp;
 
-      if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
+      if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
 	{
-	  /* These Intel Prescott New Instructions have the fixed
+	  /* Streaming SIMD extensions 3 Instructions have the fixed
 	     operands with an opcode suffix which is coded in the same
 	     place as an 8-bit immediate field would be. Here we check
 	     those operands and remove them afterwards.  */
@@ -1566,8 +1835,11 @@ md_assemble (line)
 
 	  for (x = 0; x < i.operands; x++)
 	    if (i.op[x].regs->reg_num != x)
-	      as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
-			i.op[x].regs->reg_name, x + 1, i.tm.name);
+	      as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
+		      register_prefix,
+		      i.op[x].regs->reg_name,
+		      x + 1,
+		      i.tm.name);
 	  i.operands = 0;
  	}
 
@@ -1616,7 +1888,7 @@ md_assemble (line)
     }
 
   if ((i.tm.opcode_modifier & Rex64) != 0)
-    i.rex |= REX_MODE64;
+    i.rex |= REX_W;
 
   /* For 8 bit registers we need an empty rex prefix.  Also if the
      instruction already has a prefix, we need to convert old
@@ -1640,8 +1912,9 @@ md_assemble (line)
 	    {
 	      /* In case it is "hi" register, give up.  */
 	      if (i.op[x].regs->reg_num > 3)
-		as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
-			i.op[x].regs->reg_name);
+		as_bad (_("can't encode register '%s%s' in an "
+			  "instruction requiring REX prefix."),
+			register_prefix, i.op[x].regs->reg_name);
 
 	      /* Otherwise it is equivalent to the extended register.
 		 Since the encoding doesn't change this is merely
@@ -1660,9 +1933,7 @@ md_assemble (line)
 }
 
 static char *
-parse_insn (line, mnemonic)
-     char *line;
-     char *mnemonic;
+parse_insn (char *line, char *mnemonic)
 {
   char *l = line;
   char *token_start = l;
@@ -1832,9 +2103,9 @@ parse_insn (line, mnemonic)
     {
       if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
 	    & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
-	  supported |= 1;
+	supported |= 1;
       if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
-	  supported |= 2;
+	supported |= 2;
     }
   if (!(supported & 2))
     {
@@ -1867,7 +2138,7 @@ parse_insn (line, mnemonic)
       if (t >= current_templates->end)
 	{
 	  as_bad (_("expecting string instruction after `%s'"),
-	        expecting_string_instruction);
+		  expecting_string_instruction);
 	  return NULL;
 	}
       for (override.start = t; t < current_templates->end; ++t)
@@ -1881,9 +2152,7 @@ parse_insn (line, mnemonic)
 }
 
 static char *
-parse_operands (l, mnemonic)
-     char *l;
-     const char *mnemonic;
+parse_operands (char *l, const char *mnemonic)
 {
   char *token_start;
 
@@ -2001,24 +2270,12 @@ parse_operands (l, mnemonic)
 }
 
 static void
-swap_operands ()
+swap_2_operands (int xchg1, int xchg2)
 {
   union i386_op temp_op;
   unsigned int temp_type;
   enum bfd_reloc_code_real temp_reloc;
-  int xchg1 = 0;
-  int xchg2 = 0;
 
-  if (i.operands == 2)
-    {
-      xchg1 = 0;
-      xchg2 = 1;
-    }
-  else if (i.operands == 3)
-    {
-      xchg1 = 0;
-      xchg2 = 2;
-    }
   temp_type = i.types[xchg2];
   i.types[xchg2] = i.types[xchg1];
   i.types[xchg1] = temp_type;
@@ -2028,6 +2285,22 @@ swap_operands ()
   temp_reloc = i.reloc[xchg2];
   i.reloc[xchg2] = i.reloc[xchg1];
   i.reloc[xchg1] = temp_reloc;
+}
+
+static void
+swap_operands (void)
+{
+  switch (i.operands)
+    {
+    case 4:
+      swap_2_operands (1, i.operands - 2);
+    case 3:
+    case 2:
+      swap_2_operands (0, i.operands - 1);
+      break;
+    default:
+      abort ();
+    }
 
   if (i.mem_operands == 2)
     {
@@ -2041,7 +2314,7 @@ swap_operands ()
 /* Try to ensure constant immediates are represented in the smallest
    opcode possible.  */
 static void
-optimize_imm ()
+optimize_imm (void)
 {
   char guess_suffix = 0;
   int op;
@@ -2131,8 +2404,10 @@ optimize_imm ()
 	      unsigned int mask, allowed = 0;
 	      const template *t;
 
-	      for (t = current_templates->start; t < current_templates->end; ++t)
-	        allowed |= t->operand_types[op];
+	      for (t = current_templates->start;
+		   t < current_templates->end;
+		   ++t)
+		allowed |= t->operand_types[op];
 	      switch (guess_suffix)
 		{
 		case QWORD_MNEM_SUFFIX:
@@ -2151,8 +2426,8 @@ optimize_imm ()
 		  mask = 0;
 		  break;
 		}
-		if (mask & allowed)
-		  i.types[op] &= mask;
+	      if (mask & allowed)
+		i.types[op] &= mask;
 	    }
 	    break;
 	  }
@@ -2161,7 +2436,7 @@ optimize_imm ()
 
 /* Try to use the smallest displacement type too.  */
 static void
-optimize_disp ()
+optimize_disp (void)
 {
   int op;
 
@@ -2225,13 +2500,20 @@ optimize_disp ()
 }
 
 static int
-match_template ()
+match_template (void)
 {
   /* Points to template once we've found it.  */
   const template *t;
-  unsigned int overlap0, overlap1, overlap2;
+  unsigned int overlap0, overlap1, overlap2, overlap3;
   unsigned int found_reverse_match;
   int suffix_check;
+  unsigned int operand_types [MAX_OPERANDS];
+  int addr_prefix_disp;
+  unsigned int j;
+
+#if MAX_OPERANDS != 4
+# error "MAX_OPERANDS must be 4."
+#endif
 
 #define MATCH(overlap, given, template)				\
   ((overlap & ~JumpAbsolute)					\
@@ -2249,7 +2531,11 @@ match_template ()
   overlap0 = 0;
   overlap1 = 0;
   overlap2 = 0;
+  overlap3 = 0;
   found_reverse_match = 0;
+  for (j = 0; j < MAX_OPERANDS; j++)
+    operand_types [j] = 0;
+  addr_prefix_disp = -1;
   suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
 		  ? No_bSuf
 		  : (i.suffix == WORD_MNEM_SUFFIX
@@ -2265,6 +2551,8 @@ match_template ()
 
   for (t = current_templates->start; t < current_templates->end; t++)
     {
+      addr_prefix_disp = -1;
+
       /* Must have right number of operands.  */
       if (i.operands != t->operands)
 	continue;
@@ -2275,6 +2563,9 @@ match_template ()
 	       && (t->opcode_modifier & IgnoreSize)))
 	continue;
 
+      for (j = 0; j < MAX_OPERANDS; j++)
+	operand_types [j] = t->operand_types [j];
+
       /* In general, don't allow 64-bit operands in 32-bit mode.  */
       if (i.suffix == QWORD_MNEM_SUFFIX
 	  && flag_code != CODE_64BIT
@@ -2282,8 +2573,8 @@ match_template ()
 	      ? (!(t->opcode_modifier & IgnoreSize)
 		 && !intel_float_operand (t->name))
 	      : intel_float_operand (t->name) != 2)
-	  && (!(t->operand_types[0] & (RegMMX | RegXMM))
-	      || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
+	  && (!(operand_types[0] & (RegMMX | RegXMM))
+	      || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
 	  && (t->base_opcode != 0x0fc7
 	      || t->extension_opcode != 1 /* cmpxchg8b */))
 	continue;
@@ -2297,66 +2588,142 @@ match_template ()
 	  break;
 	}
 
-      overlap0 = i.types[0] & t->operand_types[0];
+      /* Address size prefix will turn Disp64/Disp32/Disp16 operand
+	 into Disp32/Disp16/Disp32 operand.  */
+      if (i.prefix[ADDR_PREFIX] != 0)
+	  {
+	    unsigned int DispOn = 0, DispOff = 0;
+
+	    switch (flag_code)
+	    {
+	    case CODE_16BIT:
+	      DispOn = Disp32;
+	      DispOff = Disp16;
+	      break;
+	    case CODE_32BIT:
+	      DispOn = Disp16;
+	      DispOff = Disp32;
+	      break;
+	    case CODE_64BIT:
+	      DispOn = Disp32;
+	      DispOff = Disp64;
+	      break;
+	    }
+
+	    for (j = 0; j < MAX_OPERANDS; j++)
+	      {
+		/* There should be only one Disp operand.  */
+		if ((operand_types[j] & DispOff))
+		  {
+		    addr_prefix_disp = j;
+		    operand_types[j] |= DispOn;
+		    operand_types[j] &= ~DispOff;
+		    break;
+		  }
+	      }
+	  }
+
+      overlap0 = i.types[0] & operand_types[0];
       switch (t->operands)
 	{
 	case 1:
-	  if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
+	  if (!MATCH (overlap0, i.types[0], operand_types[0]))
 	    continue;
 	  break;
 	case 2:
+	  /* xchg %eax, %eax is a special case. It is an aliase for nop
+	     only in 32bit mode and we can use opcode 0x90.  In 64bit
+	     mode, we can't use 0x90 for xchg %eax, %eax since it should
+	     zero-extend %eax to %rax.  */
+	  if (flag_code == CODE_64BIT
+	      && t->base_opcode == 0x90
+	      && i.types [0] == (Acc | Reg32)
+	      && i.types [1] == (Acc | Reg32))
+	    continue;
 	case 3:
-	  overlap1 = i.types[1] & t->operand_types[1];
-	  if (!MATCH (overlap0, i.types[0], t->operand_types[0])
-	      || !MATCH (overlap1, i.types[1], t->operand_types[1])
+	case 4:
+	  overlap1 = i.types[1] & operand_types[1];
+	  if (!MATCH (overlap0, i.types[0], operand_types[0])
+	      || !MATCH (overlap1, i.types[1], operand_types[1])
 	      /* monitor in SSE3 is a very special case.  The first
-		 register and the second register may have differnet
-		 sizes.  */
+		 register and the second register may have different
+		 sizes.  The same applies to crc32 in SSE4.2.  */
 	      || !((t->base_opcode == 0x0f01
 		    && t->extension_opcode == 0xc8)
+		   || t->base_opcode == 0xf20f38f1
 		   || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
-						 t->operand_types[0],
+						 operand_types[0],
 						 overlap1, i.types[1],
-						 t->operand_types[1])))
+						 operand_types[1])))
 	    {
 	      /* Check if other direction is valid ...  */
 	      if ((t->opcode_modifier & (D | FloatD)) == 0)
 		continue;
 
 	      /* Try reversing direction of operands.  */
-	      overlap0 = i.types[0] & t->operand_types[1];
-	      overlap1 = i.types[1] & t->operand_types[0];
-	      if (!MATCH (overlap0, i.types[0], t->operand_types[1])
-		  || !MATCH (overlap1, i.types[1], t->operand_types[0])
+	      overlap0 = i.types[0] & operand_types[1];
+	      overlap1 = i.types[1] & operand_types[0];
+	      if (!MATCH (overlap0, i.types[0], operand_types[1])
+		  || !MATCH (overlap1, i.types[1], operand_types[0])
 		  || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
-						 t->operand_types[1],
+						 operand_types[1],
 						 overlap1, i.types[1],
-						 t->operand_types[0]))
+						 operand_types[0]))
 		{
 		  /* Does not match either direction.  */
 		  continue;
 		}
 	      /* found_reverse_match holds which of D or FloatDR
 		 we've found.  */
-	      found_reverse_match = t->opcode_modifier & (D | FloatDR);
+	      if ((t->opcode_modifier & D))
+		found_reverse_match = Opcode_D;
+	      else if ((t->opcode_modifier & FloatD))
+		found_reverse_match = Opcode_FloatD;
+	      else
+		found_reverse_match = 0;
+	      if ((t->opcode_modifier & FloatR))
+		found_reverse_match |= Opcode_FloatR;
 	    }
-	  /* Found a forward 2 operand match here.  */
-	  else if (t->operands == 3)
+	  else
 	    {
-	      /* Here we make use of the fact that there are no
-		 reverse match 3 operand instructions, and all 3
-		 operand instructions only need to be checked for
-		 register consistency between operands 2 and 3.  */
-	      overlap2 = i.types[2] & t->operand_types[2];
-	      if (!MATCH (overlap2, i.types[2], t->operand_types[2])
-		  || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
-						 t->operand_types[1],
-						 overlap2, i.types[2],
-						 t->operand_types[2]))
+	      /* Found a forward 2 operand match here.  */
+	      switch (t->operands)
+		{
+		case 4:
+		  overlap3 = i.types[3] & operand_types[3];
+		case 3:
+		  overlap2 = i.types[2] & operand_types[2];
+		  break;
+		}
 
-		continue;
+	      switch (t->operands)
+		{
+		case 4:
+		  if (!MATCH (overlap3, i.types[3], operand_types[3])
+		      || !CONSISTENT_REGISTER_MATCH (overlap2,
+						     i.types[2],
+						     operand_types[2],
+						     overlap3,
+						     i.types[3],
+						     operand_types[3]))
+		    continue;
+		case 3:
+		  /* Here we make use of the fact that there are no
+		     reverse match 3 operand instructions, and all 3
+		     operand instructions only need to be checked for
+		     register consistency between operands 2 and 3.  */
+		  if (!MATCH (overlap2, i.types[2], operand_types[2])
+		      || !CONSISTENT_REGISTER_MATCH (overlap1,
+						     i.types[1],
+						     operand_types[1],
+						     overlap2,
+						     i.types[2],
+						     operand_types[2]))
+		    continue;
+		  break;
+		}
 	    }
-	  /* Found either forward/reverse 2 or 3 operand match here:
+	  /* Found either forward/reverse 2, 3 or 4 operand match here:
 	     slip through to break.  */
 	}
       if (t->cpu_flags & ~cpu_arch_flags)
@@ -2380,7 +2747,7 @@ match_template ()
     {
       if (!intel_syntax
 	  && ((i.types[0] & JumpAbsolute)
-	      != (t->operand_types[0] & JumpAbsolute)))
+	      != (operand_types[0] & JumpAbsolute)))
 	{
 	  as_warn (_("indirect %s without `*'"), t->name);
 	}
@@ -2396,6 +2763,11 @@ match_template ()
 
   /* Copy the template we found.  */
   i.tm = *t;
+
+  if (addr_prefix_disp != -1)
+    i.tm.operand_types[addr_prefix_disp]
+      = operand_types[addr_prefix_disp];
+
   if (found_reverse_match)
     {
       /* If we found a reverse match we must alter the opcode
@@ -2404,15 +2776,15 @@ match_template ()
 
       i.tm.base_opcode ^= found_reverse_match;
 
-      i.tm.operand_types[0] = t->operand_types[1];
-      i.tm.operand_types[1] = t->operand_types[0];
+      i.tm.operand_types[0] = operand_types[1];
+      i.tm.operand_types[1] = operand_types[0];
     }
 
   return 1;
 }
 
 static int
-check_string ()
+check_string (void)
 {
   int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
   if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
@@ -2465,19 +2837,44 @@ process_suffix (void)
 	{
 	  /* We take i.suffix from the last register operand specified,
 	     Destination register type is more significant than source
-	     register type.  */
-	  int op;
-
-	  for (op = i.operands; --op >= 0;)
-	    if ((i.types[op] & Reg)
-		&& !(i.tm.operand_types[op] & InOutPortReg))
-	      {
-		i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
-			    (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
-			    (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
+	     register type.  crc32 in SSE4.2 prefers source register
+	     type. */
+	  if (i.tm.base_opcode == 0xf20f38f1)
+	    {
+	      if ((i.types[0] & Reg))
+		i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
 			    LONG_MNEM_SUFFIX);
-		break;
-	      }
+	    }
+	  else if (i.tm.base_opcode == 0xf20f38f0)
+	    {
+	      if ((i.types[0] & Reg8))
+		i.suffix = BYTE_MNEM_SUFFIX;
+	    }
+
+	  if (!i.suffix)
+	    {
+	      int op;
+
+	      if (i.tm.base_opcode == 0xf20f38f1
+		  || i.tm.base_opcode == 0xf20f38f0)
+		{
+		  /* We have to know the operand size for crc32.  */
+		  as_bad (_("ambiguous memory operand size for `%s`"),
+			  i.tm.name);
+		  return 0;
+		}
+
+	      for (op = i.operands; --op >= 0;)
+		if ((i.types[op] & Reg)
+		    && !(i.tm.operand_types[op] & InOutPortReg))
+		  {
+		    i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
+				(i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
+				(i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
+				LONG_MNEM_SUFFIX);
+		    break;
+		  }
+	    }
 	}
       else if (i.suffix == BYTE_MNEM_SUFFIX)
 	{
@@ -2515,9 +2912,9 @@ process_suffix (void)
   else if (intel_syntax
 	   && !i.suffix
 	   && ((i.tm.operand_types[0] & JumpAbsolute)
-	    || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
-	    || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
-		&& i.tm.extension_opcode <= 3)))
+	       || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
+	       || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
+		   && i.tm.extension_opcode <= 3)))
     {
       switch (flag_code)
 	{
@@ -2544,19 +2941,20 @@ process_suffix (void)
 	{
 	  if (i.tm.opcode_modifier & W)
 	    {
-	      as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
+	      as_bad (_("no instruction mnemonic suffix given and "
+			"no register operands; can't size instruction"));
 	      return 0;
 	    }
 	}
       else
 	{
-	  unsigned int suffixes = ~i.tm.opcode_modifier
-				  & (No_bSuf
-				     | No_wSuf
-				     | No_lSuf
-				     | No_sSuf
-				     | No_xSuf
-				     | No_qSuf);
+	  unsigned int suffixes = (~i.tm.opcode_modifier
+				   & (No_bSuf
+				      | No_wSuf
+				      | No_lSuf
+				      | No_sSuf
+				      | No_xSuf
+				      | No_qSuf));
 
 	  if ((i.tm.opcode_modifier & W)
 	      || ((suffixes & (suffixes - 1))
@@ -2615,7 +3013,15 @@ process_suffix (void)
       if (i.suffix == QWORD_MNEM_SUFFIX
 	  && flag_code == CODE_64BIT
 	  && (i.tm.opcode_modifier & NoRex64) == 0)
-	i.rex |= REX_MODE64;
+	{
+	  /* Special case for xchg %rax,%rax.  It is NOP and doesn't
+	     need rex64.  */
+	  if (i.operands != 2
+	      || i.types [0] != (Acc | Reg64)
+	      || i.types [1] != (Acc | Reg64)
+	      || i.tm.base_opcode != 0x90)
+	    i.rex |= REX_W;
+	}
 
       /* Size floating point instruction.  */
       if (i.suffix == LONG_MNEM_SUFFIX)
@@ -2648,6 +3054,10 @@ check_byte_reg (void)
 	      || i.tm.base_opcode == 0xfbf))
 	continue;
 
+      /* crc32 doesn't generate this warning.  */
+      if (i.tm.base_opcode == 0xf20f38f0)
+	continue;
+
       if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
 	{
 	  /* Prohibit these changes in the 64bit mode, since the
@@ -2655,18 +3065,20 @@ check_byte_reg (void)
 	  if (flag_code == CODE_64BIT
 	      && (i.tm.operand_types[op] & InOutPortReg) == 0)
 	    {
-	      as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		      i.op[op].regs->reg_name,
+	      as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		      register_prefix, i.op[op].regs->reg_name,
 		      i.suffix);
 	      return 0;
 	    }
 #if REGISTER_WARNINGS
 	  if (!quiet_warnings
 	      && (i.tm.operand_types[op] & InOutPortReg) == 0)
-	    as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
+	    as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
+		     register_prefix,
 		     (i.op[op].regs + (i.types[op] & Reg16
 				       ? REGNAM_AL - REGNAM_AX
 				       : REGNAM_AL - REGNAM_EAX))->reg_name,
+		     register_prefix,
 		     i.op[op].regs->reg_name,
 		     i.suffix);
 #endif
@@ -2678,7 +3090,8 @@ check_byte_reg (void)
 			 | Control | Debug | Test
 			 | FloatReg | FloatAcc))
 	{
-	  as_bad (_("`%%%s' not allowed with `%s%c'"),
+	  as_bad (_("`%s%s' not allowed with `%s%c'"),
+		  register_prefix,
 		  i.op[op].regs->reg_name,
 		  i.tm.name,
 		  i.suffix);
@@ -2689,7 +3102,7 @@ check_byte_reg (void)
 }
 
 static int
-check_long_reg ()
+check_long_reg (void)
 {
   int op;
 
@@ -2699,7 +3112,8 @@ check_long_reg ()
     if ((i.types[op] & Reg8) != 0
 	&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
       {
-	as_bad (_("`%%%s' not allowed with `%s%c'"),
+	as_bad (_("`%s%s' not allowed with `%s%c'"),
+		register_prefix,
 		i.op[op].regs->reg_name,
 		i.tm.name,
 		i.suffix);
@@ -2714,15 +3128,17 @@ check_long_reg ()
 	   lowering is more complicated.  */
 	if (flag_code == CODE_64BIT)
 	  {
-	    as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		    i.op[op].regs->reg_name,
+	    as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		    register_prefix, i.op[op].regs->reg_name,
 		    i.suffix);
 	    return 0;
 	  }
 #if REGISTER_WARNINGS
 	else
-	  as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
+	  as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
+		   register_prefix,
 		   (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
+		   register_prefix,
 		   i.op[op].regs->reg_name,
 		   i.suffix);
 #endif
@@ -2731,8 +3147,8 @@ check_long_reg ()
     else if ((i.types[op] & Reg64) != 0
 	     && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
       {
-	as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		i.op[op].regs->reg_name,
+	as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		register_prefix, i.op[op].regs->reg_name,
 		i.suffix);
 	return 0;
       }
@@ -2740,7 +3156,7 @@ check_long_reg ()
 }
 
 static int
-check_qword_reg ()
+check_qword_reg (void)
 {
   int op;
 
@@ -2750,7 +3166,8 @@ check_qword_reg ()
     if ((i.types[op] & Reg8) != 0
 	&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
       {
-	as_bad (_("`%%%s' not allowed with `%s%c'"),
+	as_bad (_("`%s%s' not allowed with `%s%c'"),
+		register_prefix,
 		i.op[op].regs->reg_name,
 		i.tm.name,
 		i.suffix);
@@ -2763,8 +3180,8 @@ check_qword_reg ()
       {
 	/* Prohibit these changes in the 64bit mode, since the
 	   lowering is more complicated.  */
-	as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		i.op[op].regs->reg_name,
+	as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		register_prefix, i.op[op].regs->reg_name,
 		i.suffix);
 	return 0;
       }
@@ -2772,7 +3189,7 @@ check_qword_reg ()
 }
 
 static int
-check_word_reg ()
+check_word_reg (void)
 {
   int op;
   for (op = i.operands; --op >= 0;)
@@ -2781,7 +3198,8 @@ check_word_reg ()
     if ((i.types[op] & Reg8) != 0
 	&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
       {
-	as_bad (_("`%%%s' not allowed with `%s%c'"),
+	as_bad (_("`%s%s' not allowed with `%s%c'"),
+		register_prefix,
 		i.op[op].regs->reg_name,
 		i.tm.name,
 		i.suffix);
@@ -2796,15 +3214,17 @@ check_word_reg ()
 	   lowering is more complicated.  */
 	if (flag_code == CODE_64BIT)
 	  {
-	    as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		    i.op[op].regs->reg_name,
+	    as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		    register_prefix, i.op[op].regs->reg_name,
 		    i.suffix);
 	    return 0;
 	  }
 	else
 #if REGISTER_WARNINGS
-	  as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
+	  as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
+		   register_prefix,
 		   (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
+		   register_prefix,
 		   i.op[op].regs->reg_name,
 		   i.suffix);
 #endif
@@ -2813,7 +3233,7 @@ check_word_reg ()
 }
 
 static int
-finalize_imm ()
+finalize_imm (void)
 {
   unsigned int overlap0, overlap1, overlap2;
 
@@ -2844,7 +3264,8 @@ finalize_imm ()
 	  && overlap0 != Imm16 && overlap0 != Imm32S
 	  && overlap0 != Imm32 && overlap0 != Imm64)
 	{
-	  as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
+	  as_bad (_("no instruction mnemonic suffix given; "
+		    "can't determine immediate size"));
 	  return 0;
 	}
     }
@@ -2877,7 +3298,9 @@ finalize_imm ()
 	  && overlap1 != Imm16 && overlap1 != Imm32S
 	  && overlap1 != Imm32 && overlap1 != Imm64)
 	{
-	  as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
+	  as_bad (_("no instruction mnemonic suffix given; "
+		    "can't determine immediate size %x %c"),
+		  overlap1, i.suffix);
 	  return 0;
 	}
     }
@@ -2891,7 +3314,7 @@ finalize_imm ()
 }
 
 static int
-process_operands ()
+process_operands (void)
 {
   /* Default segment register this instruction will use for memory
      accesses.  0 means unknown.  This is only for optimizing out
@@ -2901,40 +3324,90 @@ process_operands ()
   /* The imul $imm, %reg instruction is converted into
      imul $imm, %reg, %reg, and the clr %reg instruction
      is converted into xor %reg, %reg.  */
-  if (i.tm.opcode_modifier & regKludge)
-    {
-      unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
-      /* Pretend we saw the extra register operand.  */
-      assert (i.op[first_reg_op + 1].regs == 0);
-      i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
-      i.types[first_reg_op + 1] = i.types[first_reg_op];
-      i.reg_operands = 2;
+  if (i.tm.opcode_modifier & RegKludge)
+    {
+       if ((i.tm.cpu_flags & CpuSSE4_1))
+	 {
+	   /* The first operand in instruction blendvpd, blendvps and
+	      pblendvb in SSE4.1 is implicit and must be xmm0.  */
+	   assert (i.operands == 3
+		   && i.reg_operands >= 2
+		   && i.types[0] == RegXMM);
+	   if (i.op[0].regs->reg_num != 0)
+	     {
+	       if (intel_syntax)
+		 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
+			 i.tm.name, register_prefix);
+	       else
+		 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
+			 i.tm.name, register_prefix);
+	       return 0;
+	     }
+	   i.op[0] = i.op[1];
+	   i.op[1] = i.op[2];
+	   i.types[0] = i.types[1];
+	   i.types[1] = i.types[2];
+	   i.operands--;
+	   i.reg_operands--;
+
+	   /* We need to adjust fields in i.tm since they are used by
+	      build_modrm_byte.  */
+	   i.tm.operand_types [0] = i.tm.operand_types [1];
+	   i.tm.operand_types [1] = i.tm.operand_types [2];
+	   i.tm.operands--;
+	 }
+       else
+	 {
+	   unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
+	   /* Pretend we saw the extra register operand.  */
+	   assert (i.reg_operands == 1
+		   && i.op[first_reg_op + 1].regs == 0);
+	   i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
+	   i.types[first_reg_op + 1] = i.types[first_reg_op];
+	   i.operands++;
+	   i.reg_operands++;
+	 }
     }
 
   if (i.tm.opcode_modifier & ShortForm)
     {
-      /* The register or float register operand is in operand 0 or 1.  */
-      unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
-      /* Register goes in low 3 bits of opcode.  */
-      i.tm.base_opcode |= i.op[op].regs->reg_num;
-      if ((i.op[op].regs->reg_flags & RegRex) != 0)
-	i.rex |= REX_EXTZ;
-      if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
+      if (i.types[0] & (SReg2 | SReg3))
 	{
-	  /* Warn about some common errors, but press on regardless.
-	     The first case can be generated by gcc (<= 2.8.1).  */
-	  if (i.operands == 2)
+	  if (i.tm.base_opcode == POP_SEG_SHORT
+	      && i.op[0].regs->reg_num == 1)
 	    {
-	      /* Reversed arguments on faddp, fsubp, etc.  */
-	      as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
-		       i.op[1].regs->reg_name,
-		       i.op[0].regs->reg_name);
+	      as_bad (_("you can't `pop %%cs'"));
+	      return 0;
 	    }
-	  else
+	  i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
+	  if ((i.op[0].regs->reg_flags & RegRex) != 0)
+	    i.rex |= REX_B;
+	}
+      else
+	{
+	  /* The register or float register operand is in operand 0 or 1.  */
+	  unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
+	  /* Register goes in low 3 bits of opcode.  */
+	  i.tm.base_opcode |= i.op[op].regs->reg_num;
+	  if ((i.op[op].regs->reg_flags & RegRex) != 0)
+	    i.rex |= REX_B;
+	  if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
 	    {
-	      /* Extraneous `l' suffix on fp insn.  */
-	      as_warn (_("translating to `%s %%%s'"), i.tm.name,
-		       i.op[0].regs->reg_name);
+	      /* Warn about some common errors, but press on regardless.
+		 The first case can be generated by gcc (<= 2.8.1).  */
+	      if (i.operands == 2)
+		{
+		  /* Reversed arguments on faddp, fsubp, etc.  */
+		  as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
+			   register_prefix, i.op[1].regs->reg_name,
+			   register_prefix, i.op[0].regs->reg_name);
+		}
+	      else
+		{
+		  /* Extraneous `l' suffix on fp insn.  */
+		  as_warn (_("translating to `%s %s%s'"), i.tm.name,
+			   register_prefix, i.op[0].regs->reg_name);
+		}
 	    }
 	}
     }
@@ -2946,19 +3419,7 @@ process_operands ()
 
       default_seg = build_modrm_byte ();
     }
-  else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
-    {
-      if (i.tm.base_opcode == POP_SEG_SHORT
-	  && i.op[0].regs->reg_num == 1)
-	{
-	  as_bad (_("you can't `pop %%cs'"));
-	  return 0;
-	}
-      i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
-      if ((i.op[0].regs->reg_flags & RegRex) != 0)
-	i.rex |= REX_EXTZ;
-    }
-  else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
+  else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
     {
       default_seg = &ds;
     }
@@ -2988,7 +3449,7 @@ process_operands ()
 }
 
 static const seg_entry *
-build_modrm_byte ()
+build_modrm_byte (void)
 {
   const seg_entry *default_seg = 0;
 
@@ -2997,11 +3458,33 @@ build_modrm_byte ()
   if (i.reg_operands == 2)
     {
       unsigned int source, dest;
-      source = ((i.types[0]
-		 & (Reg | RegMMX | RegXMM
-		    | SReg2 | SReg3
-		    | Control | Debug | Test))
-		? 0 : 1);
+
+      switch (i.operands)
+	{
+	case 2:
+	  source = 0;
+	  break;
+	case 3:
+	  /* When there are 3 operands, one of them may be immediate,
+	     which may be the first or the last operand.  Otherwise,
+	     the first operand must be shift count register (cl). */
+	  assert (i.imm_operands == 1
+		  || (i.imm_operands == 0
+		      && (i.types[0] & ShiftCount)));
+	  source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
+	  break;
+	case 4:
+	  /* When there are 4 operands, the first two must be immediate
+	     operands. The source operand will be the 3rd one.  */
+	  assert (i.imm_operands == 2
+		  && (i.types[0] & Imm)
+		  && (i.types[1] & Imm));
+	  source = 2;
+	  break;
+	default:
+	  abort ();
+	}
+
       dest = source + 1;
 
       i.rm.mode = 3;
@@ -3011,29 +3494,29 @@ build_modrm_byte ()
 	 destination operand, then we assume the source operand may
 	 sometimes be a memory operand and so we need to store the
 	 destination in the i.rm.reg field.  */
-      if ((i.tm.operand_types[dest] & AnyMem) == 0)
+      if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
 	{
 	  i.rm.reg = i.op[dest].regs->reg_num;
 	  i.rm.regmem = i.op[source].regs->reg_num;
 	  if ((i.op[dest].regs->reg_flags & RegRex) != 0)
-	    i.rex |= REX_EXTX;
+	    i.rex |= REX_R;
 	  if ((i.op[source].regs->reg_flags & RegRex) != 0)
-	    i.rex |= REX_EXTZ;
+	    i.rex |= REX_B;
 	}
       else
 	{
 	  i.rm.reg = i.op[source].regs->reg_num;
 	  i.rm.regmem = i.op[dest].regs->reg_num;
 	  if ((i.op[dest].regs->reg_flags & RegRex) != 0)
-	    i.rex |= REX_EXTZ;
+	    i.rex |= REX_B;
 	  if ((i.op[source].regs->reg_flags & RegRex) != 0)
-	    i.rex |= REX_EXTX;
+	    i.rex |= REX_R;
 	}
-      if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
+      if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
 	{
 	  if (!((i.types[0] | i.types[1]) & Control))
 	    abort ();
-	  i.rex &= ~(REX_EXTX | REX_EXTZ);
+	  i.rex &= ~(REX_R | REX_B);
 	  add_prefix (LOCK_PREFIX_OPCODE);
 	}
     }
@@ -3042,9 +3525,12 @@ build_modrm_byte ()
       if (i.mem_operands)
 	{
 	  unsigned int fake_zero_displacement = 0;
-	  unsigned int op = ((i.types[0] & AnyMem)
-			     ? 0
-			     : (i.types[1] & AnyMem) ? 1 : 2);
+	  unsigned int op;
+
+	  for (op = 0; op < i.operands; op++)
+	    if ((i.types[op] & AnyMem))
+	      break;
+	  assert (op < i.operands);
 
 	  default_seg = &ds;
 
@@ -3065,9 +3551,11 @@ build_modrm_byte ()
 		      i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
 		      i.sib.base = NO_BASE_REGISTER;
 		      i.sib.index = NO_INDEX_REGISTER;
-		      i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
+		      i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
+				     ? Disp32S : Disp32);
 		    }
-		  else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
+		  else if ((flag_code == CODE_16BIT)
+			   ^ (i.prefix[ADDR_PREFIX] != 0))
 		    {
 		      i.rm.regmem = NO_BASE_REGISTER_16;
 		      i.types[op] = Disp16;
@@ -3090,7 +3578,7 @@ build_modrm_byte ()
 		  else
 		    i.types[op] |= Disp32S;
 		  if ((i.index_reg->reg_flags & RegRex) != 0)
-		    i.rex |= REX_EXTY;
+		    i.rex |= REX_X;
 		}
 	    }
 	  /* RIP addressing for 64bit mode.  */
@@ -3099,7 +3587,7 @@ build_modrm_byte ()
 	      i.rm.regmem = NO_BASE_REGISTER;
 	      i.types[op] &= ~ Disp;
 	      i.types[op] |= Disp32S;
-	      i.flags[op] = Operand_PCrel;
+	      i.flags[op] |= Operand_PCrel;
 	      if (! i.disp_operands)
 		fake_zero_displacement = 1;
 	    }
@@ -3137,11 +3625,13 @@ build_modrm_byte ()
 	    {
 	      if (flag_code == CODE_64BIT
 		  && (i.types[op] & Disp))
-		i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
+		i.types[op] = ((i.types[op] & Disp8)
+			       | (i.prefix[ADDR_PREFIX] == 0
+				  ? Disp32S : Disp32));
 
 	      i.rm.regmem = i.base_reg->reg_num;
 	      if ((i.base_reg->reg_flags & RegRex) != 0)
-		i.rex |= REX_EXTZ;
+		i.rex |= REX_B;
 	      i.sib.base = i.base_reg->reg_num;
 	      /* x86-64 ignores REX prefix bit here to avoid decoder
 		 complications.  */
@@ -3178,7 +3668,7 @@ build_modrm_byte ()
 		  i.sib.index = i.index_reg->reg_num;
 		  i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
 		  if ((i.index_reg->reg_flags & RegRex) != 0)
-		    i.rex |= REX_EXTY;
+		    i.rex |= REX_X;
 		}
 
 	      if (i.disp_operands
@@ -3211,31 +3701,28 @@ build_modrm_byte ()
 	 registers are coded into the i.rm.reg field.  */
       if (i.reg_operands)
 	{
-	  unsigned int op =
-	    ((i.types[0]
-	      & (Reg | RegMMX | RegXMM
-		 | SReg2 | SReg3
-		 | Control | Debug | Test))
-	     ? 0
-	     : ((i.types[1]
-		 & (Reg | RegMMX | RegXMM
-		    | SReg2 | SReg3
-		    | Control | Debug | Test))
-		? 1
-		: 2));
+	  unsigned int op;
+
+	  for (op = 0; op < i.operands; op++)
+	    if ((i.types[op] & (Reg | RegMMX | RegXMM
+				| SReg2 | SReg3
+				| Control | Debug | Test)))
+	      break;
+	  assert (op < i.operands);
+
 	  /* If there is an extension opcode to put here, the register
 	     number must be put into the regmem field.  */
 	  if (i.tm.extension_opcode != None)
 	    {
 	      i.rm.regmem = i.op[op].regs->reg_num;
 	      if ((i.op[op].regs->reg_flags & RegRex) != 0)
-		i.rex |= REX_EXTZ;
+		i.rex |= REX_B;
 	    }
 	  else
 	    {
 	      i.rm.reg = i.op[op].regs->reg_num;
 	      if ((i.op[op].regs->reg_flags & RegRex) != 0)
-		i.rex |= REX_EXTX;
+		i.rex |= REX_R;
 	    }
 
 	  /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
@@ -3253,7 +3740,7 @@ build_modrm_byte ()
 }
 
 static void
-output_branch ()
+output_branch (void)
 {
   char *p;
   int code16;
@@ -3331,7 +3818,7 @@ output_branch ()
 }
 
 static void
-output_jump ()
+output_jump (void)
 {
   char *p;
   int size;
@@ -3397,7 +3884,7 @@ output_jump ()
 }
 
 static void
-output_interseg_jump ()
+output_interseg_jump (void)
 {
   char *p;
   int size;
@@ -3461,7 +3948,7 @@ output_interseg_jump ()
 }
 
 static void
-output_insn ()
+output_insn (void)
 {
   fragS *insn_start_frag;
   offsetT insn_start_off;
@@ -3488,10 +3975,12 @@ output_insn ()
       unsigned char *q;
       unsigned int prefix;
 
-      /* All opcodes on i386 have either 1 or 2 bytes.  Merom New
-	 Instructions have 3 bytes.  We may use one more higher byte
-	 to specify a prefix the instruction requires.  */
-      if ((i.tm.cpu_flags & CpuMNI) != 0)
+      /* All opcodes on i386 have either 1 or 2 bytes.  SSSE3 and
+	 SSE4 instructions have 3 bytes.  We may use one more higher
+	 byte to specify a prefix the instruction requires.  Exclude
+	 instructions which are in both SSE4 and ABM.  */
+      if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
+	  && (i.tm.cpu_flags & CpuABM) == 0)
 	{
 	  if (i.tm.base_opcode & 0xff000000)
 	    {
@@ -3504,7 +3993,7 @@ output_insn ()
 	  prefix = (i.tm.base_opcode >> 16) & 0xff;
 	  if ((i.tm.cpu_flags & CpuPadLock) != 0)
 	    {
-check_prefix:
+	    check_prefix:
 	      if (prefix != REPE_PREFIX_OPCODE
 		  || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
 		add_prefix (prefix);
@@ -3532,7 +4021,8 @@ check_prefix:
 	}
       else
 	{
-	  if ((i.tm.cpu_flags & CpuMNI) != 0)
+	  if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
+	      && (i.tm.cpu_flags & CpuABM) == 0)
 	    {
 	      p = frag_more (3);
 	      *p++ = (i.tm.base_opcode >> 16) & 0xff;
@@ -3586,10 +4076,42 @@ check_prefix:
 #endif /* DEBUG386  */
 }
 
+/* Return the size of the displacement operand N.  */
+
+static int
+disp_size (unsigned int n)
+{
+  int size = 4;
+  if (i.types[n] & (Disp8 | Disp16 | Disp64))
+    {
+      size = 2;
+      if (i.types[n] & Disp8)
+	size = 1;
+      if (i.types[n] & Disp64)
+	size = 8;
+    }
+  return size;
+}
+
+/* Return the size of the immediate operand N.  */
+
+static int
+imm_size (unsigned int n)
+{
+  int size = 4;
+  if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
+    {
+      size = 2;
+      if (i.types[n] & (Imm8 | Imm8S))
+	size = 1;
+      if (i.types[n] & Imm64)
+	size = 8;
+    }
+  return size;
+}
+
 static void
-output_disp (insn_start_frag, insn_start_off)
-    fragS *insn_start_frag;
-    offsetT insn_start_off;
+output_disp (fragS *insn_start_frag, offsetT insn_start_off)
 {
   char *p;
   unsigned int n;
@@ -3600,18 +4122,9 @@ output_disp (insn_start_frag, insn_start_off)
 	{
 	  if (i.op[n].disps->X_op == O_constant)
 	    {
-	      int size;
+	      int size = disp_size (n);
 	      offsetT val;
 
-	      size = 4;
-	      if (i.types[n] & (Disp8 | Disp16 | Disp64))
-		{
-		  size = 2;
-		  if (i.types[n] & Disp8)
-		    size = 1;
-		  if (i.types[n] & Disp64)
-		    size = 8;
-		}
 	      val = offset_in_range (i.op[n].disps->X_add_number,
 				     size);
 	      p = frag_more (size);
@@ -3620,45 +4133,32 @@ output_disp (insn_start_frag, insn_start_off)
 	  else
 	    {
 	      enum bfd_reloc_code_real reloc_type;
-	      int size = 4;
-	      int sign = 0;
+	      int size = disp_size (n);
+	      int sign = (i.types[n] & Disp32S) != 0;
 	      int pcrel = (i.flags[n] & Operand_PCrel) != 0;
 
+	      /* We can't have 8 bit displacement here.  */
+	      assert ((i.types[n] & Disp8) == 0);
+
 	      /* The PC relative address is computed relative
 		 to the instruction boundary, so in case immediate
 		 fields follows, we need to adjust the value.  */
 	      if (pcrel && i.imm_operands)
 		{
-		  int imm_size = 4;
 		  unsigned int n1;
+		  int sz = 0;
 
 		  for (n1 = 0; n1 < i.operands; n1++)
 		    if (i.types[n1] & Imm)
 		      {
-			if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
-			  {
-			    imm_size = 2;
-			    if (i.types[n1] & (Imm8 | Imm8S))
-			      imm_size = 1;
-			    if (i.types[n1] & Imm64)
-			      imm_size = 8;
-			  }
-			break;
+			/* Only one immediate is allowed for PC
+			   relative address.  */
+			assert (sz == 0);
+			sz = imm_size (n1);
+			i.op[n].disps->X_add_number -= sz;
 		      }
 		  /* We should find the immediate.  */
-		  if (n1 == i.operands)
-		    abort ();
-		  i.op[n].disps->X_add_number -= imm_size;
-		}
-
-	      if (i.types[n] & Disp32S)
-		sign = 1;
-
-	      if (i.types[n] & (Disp16 | Disp64))
-		{
-		  size = 2;
-		  if (i.types[n] & Disp64)
-		    size = 8;
+		  assert (sz != 0);
 		}
 
 	      p = frag_more (size);
@@ -3712,9 +4212,7 @@ output_disp (insn_start_frag, insn_start_off)
 }
 
 static void
-output_imm (insn_start_frag, insn_start_off)
-    fragS *insn_start_frag;
-    offsetT insn_start_off;
+output_imm (fragS *insn_start_frag, offsetT insn_start_off)
 {
   char *p;
   unsigned int n;
@@ -3725,18 +4223,9 @@ output_imm (insn_start_frag, insn_start_off)
 	{
 	  if (i.op[n].imms->X_op == O_constant)
 	    {
-	      int size;
+	      int size = imm_size (n);
 	      offsetT val;
 
-	      size = 4;
-	      if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
-		{
-		  size = 2;
-		  if (i.types[n] & (Imm8 | Imm8S))
-		    size = 1;
-		  else if (i.types[n] & Imm64)
-		    size = 8;
-		}
 	      val = offset_in_range (i.op[n].imms->X_add_number,
 				     size);
 	      p = frag_more (size);
@@ -3749,21 +4238,15 @@ output_imm (insn_start_frag, insn_start_off)
 		 non-absolute imms).  Try to support other
 		 sizes ...  */
 	      enum bfd_reloc_code_real reloc_type;
-	      int size = 4;
-	      int sign = 0;
+	      int size = imm_size (n);
+	      int sign;
 
 	      if ((i.types[n] & (Imm32S))
 		  && (i.suffix == QWORD_MNEM_SUFFIX
 		      || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
 		sign = 1;
-	      if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
-		{
-		  size = 2;
-		  if (i.types[n] & (Imm8 | Imm8S))
-		    size = 1;
-		  if (i.types[n] & Imm64)
-		    size = 8;
-		}
+	      else
+		sign = 0;
 
 	      p = frag_more (size);
 	      reloc_type = reloc (size, 0, sign, i.reloc[n]);
@@ -3857,10 +4340,8 @@ static enum bfd_reloc_code_real got_reloc = NO_RELOC;
 static int cons_sign = -1;
 
 void
-x86_cons_fix_new (fragS *frag,
-     unsigned int off,
-     unsigned int len,
-     expressionS *exp)
+x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
+		  expressionS *exp)
 {
   enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
 
@@ -3891,8 +4372,8 @@ x86_cons_fix_new (fragS *frag,
    input line.  Otherwise return NULL.  */
 static char *
 lex_got (enum bfd_reloc_code_real *reloc,
-     int *adjust,
-     unsigned int *types)
+	 int *adjust,
+	 unsigned int *types)
 {
   /* Some of the relocations depend on the size of what field is to
      be relocated.  But in our callers i386_immediate and i386_displacement
@@ -3904,23 +4385,57 @@ lex_got (enum bfd_reloc_code_real *reloc,
     const enum bfd_reloc_code_real rel[2];
     const unsigned int types64;
   } gotrel[] = {
-    { "PLTOFF",   { 0,                        BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
-    { "PLT",      { BFD_RELOC_386_PLT32,      BFD_RELOC_X86_64_PLT32    }, Imm32|Imm32S|Disp32 },
-    { "GOTPLT",   { 0,                        BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
-    { "GOTOFF",   { BFD_RELOC_386_GOTOFF,     BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
-    { "GOTPCREL", { 0,                        BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
-    { "TLSGD",    { BFD_RELOC_386_TLS_GD,     BFD_RELOC_X86_64_TLSGD    }, Imm32|Imm32S|Disp32 },
-    { "TLSLDM",   { BFD_RELOC_386_TLS_LDM,    0                         }, 0 },
-    { "TLSLD",    { 0,                        BFD_RELOC_X86_64_TLSLD    }, Imm32|Imm32S|Disp32 },
-    { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,  BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
-    { "TPOFF",    { BFD_RELOC_386_TLS_LE_32,  BFD_RELOC_X86_64_TPOFF32  }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
-    { "NTPOFF",   { BFD_RELOC_386_TLS_LE,     0                         }, 0 },
-    { "DTPOFF",   { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
-    { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,  0                         }, 0 },
-    { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,     0                         }, 0 },
-    { "GOT",      { BFD_RELOC_386_GOT32,      BFD_RELOC_X86_64_GOT32    }, Imm32|Imm32S|Disp32|Imm64 },
-    { "TLSDESC",  { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
-    { "TLSCALL",  { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
+    { "PLTOFF",   { 0,
+		    BFD_RELOC_X86_64_PLTOFF64 },
+      Imm64 },
+    { "PLT",      { BFD_RELOC_386_PLT32,
+		    BFD_RELOC_X86_64_PLT32    },
+      Imm32 | Imm32S | Disp32 },
+    { "GOTPLT",   { 0,
+		    BFD_RELOC_X86_64_GOTPLT64 },
+      Imm64 | Disp64 },
+    { "GOTOFF",   { BFD_RELOC_386_GOTOFF,
+		    BFD_RELOC_X86_64_GOTOFF64 },
+      Imm64 | Disp64 },
+    { "GOTPCREL", { 0,
+		    BFD_RELOC_X86_64_GOTPCREL },
+      Imm32 | Imm32S | Disp32 },
+    { "TLSGD",    { BFD_RELOC_386_TLS_GD,
+		    BFD_RELOC_X86_64_TLSGD    },
+      Imm32 | Imm32S | Disp32 },
+    { "TLSLDM",   { BFD_RELOC_386_TLS_LDM,
+		    0                         },
+      0 },
+    { "TLSLD",    { 0,
+		    BFD_RELOC_X86_64_TLSLD    },
+      Imm32 | Imm32S | Disp32 },
+    { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
+		    BFD_RELOC_X86_64_GOTTPOFF },
+      Imm32 | Imm32S | Disp32 },
+    { "TPOFF",    { BFD_RELOC_386_TLS_LE_32,
+		    BFD_RELOC_X86_64_TPOFF32  },
+      Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
+    { "NTPOFF",   { BFD_RELOC_386_TLS_LE,
+		    0                         },
+      0 },
+    { "DTPOFF",   { BFD_RELOC_386_TLS_LDO_32,
+		    BFD_RELOC_X86_64_DTPOFF32 },
+      Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
+    { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
+		    0                         },
+      0 },
+    { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
+		    0                         },
+      0 },
+    { "GOT",      { BFD_RELOC_386_GOT32,
+		    BFD_RELOC_X86_64_GOT32    },
+      Imm32 | Imm32S | Disp32 | Imm64 },
+    { "TLSDESC",  { BFD_RELOC_386_TLS_GOTDESC,
+		    BFD_RELOC_X86_64_GOTPC32_TLSDESC },
+      Imm32 | Imm32S | Disp32 },
+    { "TLSCALL",  { BFD_RELOC_386_TLS_DESC_CALL,
+		    BFD_RELOC_X86_64_TLSDESC_CALL },
+      Imm32 | Imm32S | Disp32 }
   };
   char *cp;
   unsigned int j;
@@ -3951,7 +4466,7 @@ lex_got (enum bfd_reloc_code_real *reloc,
 	      if (types)
 		{
 		  if (flag_code != CODE_64BIT)
-		    *types = Imm32|Disp32;
+		    *types = Imm32 | Disp32;
 		  else
 		    *types = gotrel[j].types64;
 		}
@@ -3959,9 +4474,6 @@ lex_got (enum bfd_reloc_code_real *reloc,
 	      if (GOT_symbol == NULL)
 		GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
 
-	      /* Replace the relocation token with ' ', so that
-		 errors like foo@GOTOFF1 will be detected.  */
-
 	      /* The length of the first part of our input line.  */
 	      first = cp - input_line_pointer;
 
@@ -3977,9 +4489,12 @@ lex_got (enum bfd_reloc_code_real *reloc,
 		 be necessary, but be safe.  */
 	      tmpbuf = xmalloc (first + second + 2);
 	      memcpy (tmpbuf, input_line_pointer, first);
-	      tmpbuf[first] = ' ';
-	      memcpy (tmpbuf + first + 1, past_reloc, second);
-	      tmpbuf[first + second + 1] = '\0';
+	      if (second != 0 && *past_reloc != ' ')
+		/* Replace the relocation token with ' ', so that
+		   errors like foo@GOTOFF1 will be detected.  */
+		tmpbuf[first++] = ' ';
+	      memcpy (tmpbuf + first, past_reloc, second);
+	      tmpbuf[first + second] = '\0';
 	      return tmpbuf;
 	    }
 
@@ -3994,9 +4509,7 @@ lex_got (enum bfd_reloc_code_real *reloc,
 }
 
 void
-x86_cons (exp, size)
-     expressionS *exp;
-     int size;
+x86_cons (expressionS *exp, int size)
 {
   if (size == 4 || (object_64bit && size == 8))
     {
@@ -4058,11 +4571,8 @@ pe_directive_secrel (dummy)
 }
 #endif
 
-static int i386_immediate PARAMS ((char *));
-
 static int
-i386_immediate (imm_start)
-     char *imm_start;
+i386_immediate (char *imm_start)
 {
   char *save_input_line_pointer;
   char *gotfree_input_line;
@@ -4072,7 +4582,8 @@ i386_immediate (imm_start)
 
   if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
     {
-      as_bad (_("only 1 or 2 immediate operands are allowed"));
+      as_bad (_("at most %d immediate operands are allowed"),
+	      MAX_IMMEDIATE_OPERANDS);
       return 0;
     }
 
@@ -4114,9 +4625,10 @@ i386_immediate (imm_start)
       /* Size it properly later.  */
       i.types[this_operand] |= Imm64;
       /* If BFD64, sign extend val.  */
-      if (!use_rela_relocations)
-	if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
-	  exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
+      if (!use_rela_relocations
+	  && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
+	exp->X_add_number
+	  = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
     }
 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
   else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
@@ -4131,6 +4643,11 @@ i386_immediate (imm_start)
       return 0;
     }
 #endif
+  else if (!intel_syntax && exp->X_op == O_register)
+    {
+      as_bad (_("illegal immediate register operand %s"), imm_start);
+      return 0;
+    }
   else
     {
       /* This is an address.  The size of the address will be
@@ -4143,11 +4660,8 @@ i386_immediate (imm_start)
   return 1;
 }
 
-static char *i386_scale PARAMS ((char *));
-
 static char *
-i386_scale (scale)
-     char *scale;
+i386_scale (char *scale)
 {
   offsetT val;
   char *save = input_line_pointer;
@@ -4194,12 +4708,8 @@ i386_scale (scale)
   return scale;
 }
 
-static int i386_displacement PARAMS ((char *, char *));
-
 static int
-i386_displacement (disp_start, disp_end)
-     char *disp_start;
-     char *disp_end;
+i386_displacement (char *disp_start, char *disp_end)
 {
   expressionS *exp;
   segT exp_seg = 0;
@@ -4208,6 +4718,13 @@ i386_displacement (disp_start, disp_end)
   int bigdisp, override;
   unsigned int types = Disp;
 
+  if (i.disp_operands == MAX_MEMORY_OPERANDS)
+    {
+      as_bad (_("at most %d displacement operands are allowed"),
+	      MAX_MEMORY_OPERANDS);
+      return 0;
+    }
+
   if ((i.types[this_operand] & JumpAbsolute)
       || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
     {
@@ -4224,9 +4741,9 @@ i386_displacement (disp_start, disp_end)
   if (flag_code == CODE_64BIT)
     {
       if (!bigdisp)
-	bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX)
-		  ? Disp16
-		  : Disp32S | Disp32;
+	bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
+		   ? Disp16
+		   : Disp32S | Disp32);
       else if (!override)
 	bigdisp = Disp64 | Disp32S | Disp32;
     }
@@ -4374,14 +4891,11 @@ i386_displacement (disp_start, disp_end)
   return 1;
 }
 
-static int i386_index_check PARAMS ((const char *));
-
 /* Make sure the memory operand we've been dealt is valid.
    Return 1 on success, 0 on a failure.  */
 
 static int
-i386_index_check (operand_string)
-     const char *operand_string;
+i386_index_check (const char *operand_string)
 {
   int ok;
 #if INFER_ADDR_PREFIX
@@ -4403,9 +4917,9 @@ i386_index_check (operand_string)
       else if (flag_code == CODE_64BIT)
 	RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
       else
-	RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
-		? Reg16
-		: Reg32;
+	RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
+		 ? Reg16
+		 : Reg32);
       if (!i.base_reg
 	  || !(i.base_reg->reg_type & Acc)
 	  || !(i.base_reg->reg_type & RegXX)
@@ -4414,17 +4928,17 @@ i386_index_check (operand_string)
 	ok = 0;
     }
   else if (flag_code == CODE_64BIT)
-     {
-       unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
-
-       if ((i.base_reg
-	    && ((i.base_reg->reg_type & RegXX) == 0)
-	    && (i.base_reg->reg_type != BaseIndex
-		|| i.index_reg))
-	   || (i.index_reg
-	       && ((i.index_reg->reg_type & (RegXX | BaseIndex))
-		   != (RegXX | BaseIndex))))
-	 ok = 0;
+    {
+      unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
+
+      if ((i.base_reg
+	   && ((i.base_reg->reg_type & RegXX) == 0)
+	   && (i.base_reg->reg_type != BaseIndex
+	       || i.index_reg))
+	  || (i.index_reg
+	      && ((i.index_reg->reg_type & (RegXX | BaseIndex))
+		  != (RegXX | BaseIndex))))
+	ok = 0;
     }
   else
     {
@@ -4466,8 +4980,9 @@ i386_index_check (operand_string)
 	     FIXME.  There doesn't seem to be any real need for separate
 	     Disp16 and Disp32 flags.  The same goes for Imm16 and Imm32.
 	     Removing them would probably clean up the code quite a lot.  */
-	  if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
-	     i.types[this_operand] ^= (Disp16 | Disp32);
+	  if (flag_code != CODE_64BIT
+	      && (i.types[this_operand] & (Disp16 | Disp32)))
+	    i.types[this_operand] ^= (Disp16 | Disp32);
 	  fudged = 1;
 	  goto tryprefix;
 	}
@@ -4487,8 +5002,7 @@ i386_index_check (operand_string)
    on error.  */
 
 static int
-i386_operand (operand_string)
-     char *operand_string;
+i386_operand (char *operand_string)
 {
   const reg_entry *r;
   char *end_op;
@@ -4646,7 +5160,8 @@ i386_operand (operand_string)
 	    ++base_string;
 
 	  if (*base_string == ','
-	      || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
+	      || ((i.base_reg = parse_register (base_string, &end_op))
+		  != NULL))
 	    {
 	      displacement_string_end = temp_string;
 
@@ -4666,7 +5181,8 @@ i386_operand (operand_string)
 		  if (is_space_char (*base_string))
 		    ++base_string;
 
-		  if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
+		  if ((i.index_reg = parse_register (base_string, &end_op))
+		      != NULL)
 		    {
 		      base_string = end_op;
 		      if (is_space_char (*base_string))
@@ -4679,7 +5195,8 @@ i386_operand (operand_string)
 			}
 		      else if (*base_string != ')')
 			{
-			  as_bad (_("expecting `,' or `)' after index register in `%s'"),
+			  as_bad (_("expecting `,' or `)' "
+				    "after index register in `%s'"),
 				  operand_string);
 			  return 0;
 			}
@@ -4703,21 +5220,24 @@ i386_operand (operand_string)
 			++base_string;
 		      if (*base_string != ')')
 			{
-			  as_bad (_("expecting `)' after scale factor in `%s'"),
+			  as_bad (_("expecting `)' "
+				    "after scale factor in `%s'"),
 				  operand_string);
 			  return 0;
 			}
 		    }
 		  else if (!i.index_reg)
 		    {
-		      as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
+		      as_bad (_("expecting index register or scale factor "
+				"after `,'; got '%c'"),
 			      *base_string);
 		      return 0;
 		    }
 		}
 	      else if (*base_string != ')')
 		{
-		  as_bad (_("expecting `,' or `)' after base register in `%s'"),
+		  as_bad (_("expecting `,' or `)' "
+			    "after base register in `%s'"),
 			  operand_string);
 		  return 0;
 		}
@@ -4933,7 +5453,8 @@ md_convert_frag (abfd, sec, fragP)
     {
       if (no_cond_jump_promotion
 	  && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
-	as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
+	as_warn_where (fragP->fr_file, fragP->fr_line,
+		       _("long jump required"));
 
       switch (fragP->fr_subtype)
 	{
@@ -4984,8 +5505,8 @@ md_convert_frag (abfd, sec, fragP)
   if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
       && object_64bit
       && ((addressT) (displacement_from_opcode_start - extension
-                      + ((addressT) 1 << 31))
-          > (((addressT) 2 << 31) - 1)))
+		      + ((addressT) 1 << 31))
+	  > (((addressT) 2 << 31) - 1)))
     {
       as_bad_where (fragP->fr_file, fragP->fr_line,
 		    _("jump target out of range"));
@@ -5250,16 +5771,17 @@ md_atof (type, litP, sizeP)
   return 0;
 }
 
-static char output_invalid_buf[8];
+static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
 
 static char *
-output_invalid (c)
-     int c;
+output_invalid (int c)
 {
   if (ISPRINT (c))
-    sprintf (output_invalid_buf, "'%c'", c);
+    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
+	      "'%c'", c);
   else
-    sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
+    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
+	      "(0x%x)", (unsigned char) c);
   return output_invalid_buf;
 }
 
@@ -5310,14 +5832,16 @@ parse_real_register (char *reg_string, char **end_op)
 	    ++s;
 	  if (*s >= '0' && *s <= '7')
 	    {
-	      r = &i386_float_regtab[*s - '0'];
+	      int fpr = *s - '0';
 	      ++s;
 	      if (is_space_char (*s))
 		++s;
 	      if (*s == ')')
 		{
 		  *end_op = s + 1;
-		  return r;
+		  r = hash_find (reg_hash, "st(0)");
+		  know (r);
+		  return r + fpr;
 		}
 	    }
 	  /* We have "%st(" then garbage.  */
@@ -5359,7 +5883,8 @@ parse_register (char *reg_string, char **end_op)
 	  const expressionS *e = symbol_get_value_expression (symbolP);
 
 	  know (e->X_op == O_register);
-	  know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
+	  know (e->X_add_number >= 0
+		&& (valueT) e->X_add_number < i386_regtab_size);
 	  r = i386_regtab + e->X_add_number;
 	  *end_op = input_line_pointer;
 	}
@@ -5417,22 +5942,27 @@ const char *md_shortopts = "qn";
 #define OPTION_32 (OPTION_MD_BASE + 0)
 #define OPTION_64 (OPTION_MD_BASE + 1)
 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
+#define OPTION_MARCH (OPTION_MD_BASE + 3)
+#define OPTION_MTUNE (OPTION_MD_BASE + 4)
 
-struct option md_longopts[] = {
+struct option md_longopts[] =
+{
   {"32", no_argument, NULL, OPTION_32},
-#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
   {"64", no_argument, NULL, OPTION_64},
 #endif
   {"divide", no_argument, NULL, OPTION_DIVIDE},
+  {"march", required_argument, NULL, OPTION_MARCH},
+  {"mtune", required_argument, NULL, OPTION_MTUNE},
   {NULL, no_argument, NULL, 0}
 };
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c, char *arg)
 {
+  unsigned int i;
+
   switch (c)
     {
     case 'n':
@@ -5462,14 +5992,18 @@ md_parse_option (c, arg)
       /* -s: On i386 Solaris, this tells the native assembler to use
 	 .stab instead of .stab.excl.  We always use .stab anyhow.  */
       break;
-
+#endif
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
     case OPTION_64:
       {
 	const char **list, **l;
 
 	list = bfd_target_list ();
 	for (l = list; *l != NULL; l++)
-	  if (strcmp (*l, "elf64-x86-64") == 0)
+	  if (CONST_STRNEQ (*l, "elf64-x86-64")
+	      || strcmp (*l, "coff-x86-64") == 0
+	      || strcmp (*l, "pe-x86-64") == 0
+	      || strcmp (*l, "pei-x86-64") == 0)
 	    {
 	      default_arch = "x86_64";
 	      break;
@@ -5502,6 +6036,44 @@ md_parse_option (c, arg)
 #endif
       break;
 
+    case OPTION_MARCH:
+      if (*arg == '.')
+	as_fatal (_("Invalid -march= option: `%s'"), arg);
+      for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
+	{
+	  if (strcmp (arg, cpu_arch [i].name) == 0)
+	    {
+	      cpu_arch_isa = cpu_arch[i].type;
+	      cpu_arch_isa_flags = cpu_arch[i].flags;
+	      if (!cpu_arch_tune_set)
+		{
+		  cpu_arch_tune = cpu_arch_isa;
+		  cpu_arch_tune_flags = cpu_arch_isa_flags;
+		}
+	      break;
+	    }
+	}
+      if (i >= ARRAY_SIZE (cpu_arch))
+	as_fatal (_("Invalid -march= option: `%s'"), arg);
+      break;
+
+    case OPTION_MTUNE:
+      if (*arg == '.')
+	as_fatal (_("Invalid -mtune= option: `%s'"), arg);
+      for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
+	{
+	  if (strcmp (arg, cpu_arch [i].name) == 0)
+	    {
+	      cpu_arch_tune_set = 1;
+	      cpu_arch_tune = cpu_arch [i].type;
+	      cpu_arch_tune_flags = cpu_arch[i].flags;
+	      break;
+	    }
+	}
+      if (i >= ARRAY_SIZE (cpu_arch))
+	as_fatal (_("Invalid -mtune= option: `%s'"), arg);
+      break;
+
     default:
       return 0;
     }
@@ -5525,6 +6097,10 @@ md_show_usage (stream)
   fprintf (stream, _("\
   -s                      ignored\n"));
 #endif
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
+  fprintf (stream, _("\
+  --32/--64               generate 32bit/64bit code\n"));
+#endif
 #ifdef SVR4_COMMENT_CHARS
   fprintf (stream, _("\
   --divide                do not treat `/' as a comment character\n"));
@@ -5532,7 +6108,32 @@ md_show_usage (stream)
   fprintf (stream, _("\
   --divide                ignored\n"));
 #endif
+  fprintf (stream, _("\
+  -march=CPU/-mtune=CPU   generate code/optimize for CPU, where CPU is one of:\n\
+                           i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
+                           core, core2, k6, athlon, k8, generic32, generic64\n"));
+
+}
+
+#if defined(TE_PEP)
+const char *
+x86_64_target_format (void)
+{
+  if (strcmp (default_arch, "x86_64") == 0)
+    {
+      set_code_flag (CODE_64BIT);
+      return COFF_TARGET_FORMAT;
+    }
+  else if (strcmp (default_arch, "i386") == 0)
+    {
+      set_code_flag (CODE_32BIT);
+      return "coff-i386";
+    }
+
+  as_fatal (_("Unknown architecture"));
+  return NULL;
 }
+#endif
 
 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
@@ -5540,12 +6141,28 @@ md_show_usage (stream)
 /* Pick the target format to use.  */
 
 const char *
-i386_target_format ()
+i386_target_format (void)
 {
   if (!strcmp (default_arch, "x86_64"))
-    set_code_flag (CODE_64BIT);
+    {
+      set_code_flag (CODE_64BIT);
+      if (cpu_arch_isa_flags == 0)
+	cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
+			     |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
+			     |CpuSSE|CpuSSE2;
+      if (cpu_arch_tune_flags == 0)
+	cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
+			      |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
+			      |CpuSSE|CpuSSE2;
+    }
   else if (!strcmp (default_arch, "i386"))
-    set_code_flag (CODE_32BIT);
+    {
+      set_code_flag (CODE_32BIT);
+      if (cpu_arch_isa_flags == 0)
+	cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
+      if (cpu_arch_tune_flags == 0)
+	cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
+    }
   else
     as_fatal (_("Unknown architecture"));
   switch (OUTPUT_FLAVOR)
@@ -5566,7 +6183,7 @@ i386_target_format ()
 	    object_64bit = 1;
 	    use_rela_relocations = 1;
 	  }
-	return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
+	return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
       }
 #endif
     default:
@@ -5578,7 +6195,8 @@ i386_target_format ()
 #endif /* OBJ_MAYBE_ more than one  */
 
 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
-void i386_elf_emit_arch_note ()
+void
+i386_elf_emit_arch_note (void)
 {
   if (IS_ELF && cpu_arch_name != NULL)
     {
@@ -5669,8 +6287,7 @@ md_section_align (segment, size)
    size, since the offset is always the last part of the insn.  */
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
 }
@@ -5678,8 +6295,7 @@ md_pcrel_from (fixP)
 #ifndef I386COFF
 
 static void
-s_bss (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_bss (int ignore ATTRIBUTE_UNUSED)
 {
   int temp;
 
@@ -5695,8 +6311,7 @@ s_bss (ignore)
 #endif
 
 void
-i386_validate_fix (fixp)
-     fixS *fixp;
+i386_validate_fix (fixS *fixp)
 {
   if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
     {
@@ -6045,8 +6660,8 @@ struct intel_parser_s
     int got_a_float;		/* Whether the operand is a float.  */
     int op_modifier;		/* Operand modifier.  */
     int is_mem;			/* 1 if operand is memory reference.  */
-    int in_offset;			/* >=1 if parsing operand of offset.  */
-    int in_bracket;			/* >=1 if parsing operand in brackets.  */
+    int in_offset;		/* >=1 if parsing operand of offset.  */
+    int in_bracket;		/* >=1 if parsing operand in brackets.  */
     const reg_entry *reg;	/* Last register reference found.  */
     char *disp;			/* Displacement string being built.  */
     char *next_operand;		/* Resume point when splitting operands.  */
@@ -6085,22 +6700,19 @@ static struct intel_token cur_token, prev_token;
 #define T_SHR		15
 
 /* Prototypes for intel parser functions.  */
-static int intel_match_token	PARAMS ((int code));
-static void intel_get_token	PARAMS ((void));
-static void intel_putback_token	PARAMS ((void));
-static int intel_expr		PARAMS ((void));
-static int intel_e04		PARAMS ((void));
-static int intel_e05		PARAMS ((void));
-static int intel_e06		PARAMS ((void));
-static int intel_e09		PARAMS ((void));
-static int intel_bracket_expr	PARAMS ((void));
-static int intel_e10		PARAMS ((void));
-static int intel_e11		PARAMS ((void));
+static int intel_match_token (int);
+static void intel_putback_token	(void);
+static void intel_get_token (void);
+static int intel_expr (void);
+static int intel_e04 (void);
+static int intel_e05 (void);
+static int intel_e06 (void);
+static int intel_e09 (void);
+static int intel_e10 (void);
+static int intel_e11 (void);
 
 static int
-i386_intel_operand (operand_string, got_a_float)
-     char *operand_string;
-     int got_a_float;
+i386_intel_operand (char *operand_string, int got_a_float)
 {
   int ret;
   char *p;
@@ -6190,7 +6802,7 @@ i386_intel_operand (operand_string, got_a_float)
 	ret = i386_immediate (intel_parser.disp);
 
       if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
-        ret = 0;
+	ret = 0;
       if (!ret || !intel_parser.next_operand)
 	break;
       intel_parser.op_string = intel_parser.next_operand;
@@ -6210,7 +6822,7 @@ i386_intel_operand (operand_string, got_a_float)
    expr'  cmpOp e04 expr'
 	| Empty  */
 static int
-intel_expr ()
+intel_expr (void)
 {
   /* XXX Implement the comparison operators.  */
   return intel_e04 ();
@@ -6221,7 +6833,7 @@ intel_expr ()
    e04'	addOp e05 e04'
 	| Empty  */
 static int
-intel_e04 ()
+intel_e04 (void)
 {
   int nregs = -1;
 
@@ -6250,7 +6862,7 @@ intel_e04 ()
    e05'	binOp e06 e05'
 	| Empty  */
 static int
-intel_e05 ()
+intel_e05 (void)
 {
   int nregs = ~NUM_ADDRESS_REGS;
 
@@ -6259,7 +6871,9 @@ intel_e05 ()
       if (!intel_e06())
 	return 0;
 
-      if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
+      if (cur_token.code == '&'
+	  || cur_token.code == '|'
+	  || cur_token.code == '^')
 	{
 	  char str[2];
 
@@ -6285,7 +6899,7 @@ intel_e05 ()
    e06'	mulOp e09 e06'
 	| Empty  */
 static int
-intel_e06 ()
+intel_e06 (void)
 {
   int nregs = ~NUM_ADDRESS_REGS;
 
@@ -6294,7 +6908,9 @@ intel_e06 ()
       if (!intel_e09())
 	return 0;
 
-      if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
+      if (cur_token.code == '*'
+	  || cur_token.code == '/'
+	  || cur_token.code == '%')
 	{
 	  char str[2];
 
@@ -6309,7 +6925,7 @@ intel_e06 ()
       else
 	break;
 
-     intel_match_token (cur_token.code);
+      intel_match_token (cur_token.code);
 
       if (nregs < 0)
 	nregs = ~nregs;
@@ -6331,7 +6947,7 @@ intel_e06 ()
 	| : e10 e09'
 	| Empty */
 static int
-intel_e09 ()
+intel_e09 (void)
 {
   int nregs = ~NUM_ADDRESS_REGS;
   int in_offset = 0;
@@ -6545,7 +7161,7 @@ intel_e09 ()
 }
 
 static int
-intel_bracket_expr ()
+intel_bracket_expr (void)
 {
   int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
   const char *start = intel_parser.op_string;
@@ -6581,7 +7197,7 @@ intel_bracket_expr ()
       intel_parser.op_modifier &= ~was_offset;
     }
   else
-      strcat (intel_parser.disp, "[");
+    strcat (intel_parser.disp, "[");
 
   /* Add a '+' to the displacement string if necessary.  */
   if (*intel_parser.disp != '\0'
@@ -6606,7 +7222,8 @@ intel_bracket_expr ()
 		/* Defer the warning until all of the operand was parsed.  */
 		intel_parser.is_mem = -1;
 	      else if (!quiet_warnings)
-		as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
+		as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
+			 len, start, len, start);
 	    }
 	}
       intel_parser.op_modifier |= was_offset;
@@ -6621,7 +7238,7 @@ intel_bracket_expr ()
    e10'	[ expr ] e10'
 	| Empty  */
 static int
-intel_e10 ()
+intel_e10 (void)
 {
   if (!intel_e11 ())
     return 0;
@@ -6651,7 +7268,7 @@ intel_e10 ()
 	| id
 	| constant  */
 static int
-intel_e11 ()
+intel_e11 (void)
 {
   switch (cur_token.code)
     {
@@ -6696,7 +7313,8 @@ intel_e11 ()
 	  {
 	    if (!(reg->reg_type & (SReg2 | SReg3)))
 	      {
-		as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
+		as_bad (_("`%s' is not a valid segment register"),
+			reg->reg_name);
 		return 0;
 	      }
 	    else if (i.seg[i.mem_operands])
@@ -6886,7 +7504,8 @@ intel_e11 ()
 	/* Get the next token to check for register scaling.  */
 	intel_match_token (cur_token.code);
 
-	/* Check if this constant is a scaling factor for an index register.  */
+	/* Check if this constant is a scaling factor for an
+	   index register.  */
 	if (cur_token.code == '*')
 	  {
 	    if (intel_match_token ('*') && cur_token.code == T_REG)
@@ -6895,14 +7514,17 @@ intel_e11 ()
 
 		if (!intel_parser.in_bracket)
 		  {
-		    as_bad (_("Register scaling only allowed in memory operands"));
+		    as_bad (_("Register scaling only allowed "
+			      "in memory operands"));
 		    return 0;
 		  }
 
-		if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
-		  reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
+		 /* Disallow things like [1*si].
+		    sp and esp are invalid as index.  */
+		if (reg->reg_type & Reg16)
+		  reg = i386_regtab + REGNAM_AX + 4;
 		else if (i.index_reg)
-		  reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
+		  reg = i386_regtab + REGNAM_EAX + 4;
 
 		/* The constant is followed by `* reg', so it must be
 		   a valid scale.  */
@@ -6952,8 +7574,7 @@ intel_e11 ()
 /* Match the given token against cur_token. If they match, read the next
    token from the operand string.  */
 static int
-intel_match_token (code)
-     int code;
+intel_match_token (int code)
 {
   if (cur_token.code == code)
     {
@@ -6969,7 +7590,7 @@ intel_match_token (code)
 
 /* Read a new token from intel_parser.op_string and store it in cur_token.  */
 static void
-intel_get_token ()
+intel_get_token (void)
 {
   char *end_op;
   const reg_entry *reg;
@@ -7154,7 +7775,7 @@ intel_get_token ()
 /* Put cur_token back into the token stream and make cur_token point to
    prev_token.  */
 static void
-intel_putback_token ()
+intel_putback_token (void)
 {
   if (cur_token.code != T_NIL)
     {
@@ -7170,7 +7791,7 @@ intel_putback_token ()
 }
 
 int
-tc_x86_regname_to_dw2regnum (const char *regname)
+tc_x86_regname_to_dw2regnum (char *regname)
 {
   unsigned int regnum;
   unsigned int regnames_count;
@@ -7281,16 +7902,16 @@ x86_64_section_letter (int letter, char **ptr_msg)
 	return SHF_X86_64_LARGE;
 
       *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
-     }
+    }
   else
-   *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
+    *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
   return -1;
 }
 
 int
 x86_64_section_word (char *str, size_t len)
 {
-  if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
+  if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
     return SHF_X86_64_LARGE;
 
   return -1;
diff --git a/contrib/binutils/gas/config/tc-i386.h b/contrib/binutils/gas/config/tc-i386.h
index 9851704..51638b0 100644
--- a/contrib/binutils/gas/config/tc-i386.h
+++ b/contrib/binutils/gas/config/tc-i386.h
@@ -1,6 +1,6 @@
 /* tc-i386.h -- Header file for tc-i386.c
    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2004, 2005
+   2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -23,6 +23,8 @@
 #ifndef TC_I386
 #define TC_I386 1
 
+#include "opcodes/i386-opc.h"
+
 struct fix;
 
 #define TARGET_BYTES_BIG_ENDIAN	0
@@ -55,6 +57,7 @@ extern unsigned long i386_mach (void);
 
 #ifdef TE_FreeBSD
 #define ELF_TARGET_FORMAT	"elf32-i386-freebsd"
+#define ELF_TARGET_FORMAT64	"elf64-x86-64-freebsd"
 #elif defined (TE_VXWORKS)
 #define ELF_TARGET_FORMAT	"elf32-i386-vxworks"
 #endif
@@ -63,9 +66,13 @@ extern unsigned long i386_mach (void);
 #define ELF_TARGET_FORMAT	"elf32-i386"
 #endif
 
+#ifndef ELF_TARGET_FORMAT64
+#define ELF_TARGET_FORMAT64	"elf64-x86-64"
+#endif
+
 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
-extern const char *i386_target_format PARAMS ((void));
+extern const char *i386_target_format (void);
 #define TARGET_FORMAT i386_target_format ()
 #else
 #ifdef OBJ_ELF
@@ -78,7 +85,7 @@ extern const char *i386_target_format PARAMS ((void));
 
 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
 #define md_end i386_elf_emit_arch_note
-extern void i386_elf_emit_arch_note PARAMS ((void));
+extern void i386_elf_emit_arch_note (void);
 #endif
 
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
@@ -91,18 +98,16 @@ extern const char extra_symbol_chars[];
 extern const char *i386_comment_chars;
 #define tc_comment_chars i386_comment_chars
 
-#define MAX_OPERANDS 3		/* max operands per insn */
-#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
-#define MAX_MEMORY_OPERANDS 2	/* max memory refs per insn (string ops) */
-
 /* Prefixes will be emitted in the order defined below.
    WAIT_PREFIX must be the first prefix since FWAIT is really is an
-   instruction, and so must come before any prefixes.  */
+   instruction, and so must come before any prefixes.
+   The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
+   LOCKREP_PREFIX.  */
 #define WAIT_PREFIX	0
-#define LOCKREP_PREFIX	1
+#define SEG_PREFIX	1
 #define ADDR_PREFIX	2
 #define DATA_PREFIX	3
-#define SEG_PREFIX	4
+#define LOCKREP_PREFIX	4
 #define REX_PREFIX	5       /* must come last.  */
 #define MAX_PREFIXES	6	/* max prefixes per opcode */
 
@@ -111,21 +116,6 @@ extern const char *i386_comment_chars;
 #define IMMEDIATE_PREFIX '$'
 #define ABSOLUTE_PREFIX '*'
 
-#define TWO_BYTE_OPCODE_ESCAPE 0x0f
-#define NOP_OPCODE (char) 0x90
-
-/* register numbers */
-#define EBP_REG_NUM 5
-#define ESP_REG_NUM 4
-
-/* modrm_byte.regmem for twobyte escape */
-#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
-/* index_base_byte.index for no index register addressing */
-#define NO_INDEX_REGISTER ESP_REG_NUM
-/* index_base_byte.base for no base register addressing */
-#define NO_BASE_REGISTER EBP_REG_NUM
-#define NO_BASE_REGISTER_16 6
-
 /* these are the instruction mnemonic suffixes.  */
 #define WORD_MNEM_SUFFIX  'w'
 #define BYTE_MNEM_SUFFIX  'b'
@@ -135,184 +125,8 @@ extern const char *i386_comment_chars;
 /* Intel Syntax */
 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 
-/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
-#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
-#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
-
 #define END_OF_INSN '\0'
 
-typedef struct
-{
-  /* instruction name sans width suffix ("mov" for movl insns) */
-  char *name;
-
-  /* how many operands */
-  unsigned int operands;
-
-  /* base_opcode is the fundamental opcode byte without optional
-     prefix(es).  */
-  unsigned int base_opcode;
-
-  /* extension_opcode is the 3 bit extension for group <n> insns.
-     This field is also used to store the 8-bit opcode suffix for the
-     AMD 3DNow! instructions.
-     If this template has no extension opcode (the usual case) use None */
-  unsigned int extension_opcode;
-#define None 0xffff		/* If no extension_opcode is possible.  */
-
-  /* cpu feature flags */
-  unsigned int cpu_flags;
-#define Cpu086		  0x1	/* Any old cpu will do, 0 does the same */
-#define Cpu186		  0x2	/* i186 or better required */
-#define Cpu286		  0x4	/* i286 or better required */
-#define Cpu386		  0x8	/* i386 or better required */
-#define Cpu486		 0x10	/* i486 or better required */
-#define Cpu586		 0x20	/* i585 or better required */
-#define Cpu686		 0x40	/* i686 or better required */
-#define CpuP4		 0x80	/* Pentium4 or better required */
-#define CpuK6		0x100	/* AMD K6 or better required*/
-#define CpuAthlon	0x200	/* AMD Athlon or better required*/
-#define CpuSledgehammer 0x400	/* Sledgehammer or better required */
-#define CpuMMX		0x800	/* MMX support required */
-#define CpuMMX2	       0x1000	/* extended MMX support (with SSE or 3DNow!Ext) required */
-#define CpuSSE	       0x2000	/* Streaming SIMD extensions required */
-#define CpuSSE2	       0x4000	/* Streaming SIMD extensions 2 required */
-#define Cpu3dnow       0x8000	/* 3dnow! support required */
-#define Cpu3dnowA     0x10000	/* 3dnow!Extensions support required */
-#define CpuSSE3	      0x20000	/* Streaming SIMD extensions 3 required */
-#define CpuPNI	      CpuSSE3	/* Prescott New Instructions required */
-#define CpuPadLock    0x40000	/* VIA PadLock required */
-#define CpuSVME	      0x80000	/* AMD Secure Virtual Machine Ext-s required */
-#define CpuVMX	     0x100000	/* VMX Instructions required */
-#define CpuMNI	     0x200000	/* Merom New Instructions required */
-
-  /* These flags are set by gas depending on the flag_code.  */
-#define Cpu64	     0x4000000   /* 64bit support required  */
-#define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
-
-  /* The default value for unknown CPUs - enable all features to avoid problems.  */
-#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
-	|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
-	|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME|CpuMNI)
-
-  /* the bits in opcode_modifier are used to generate the final opcode from
-     the base_opcode.  These bits also are used to detect alternate forms of
-     the same instruction */
-  unsigned int opcode_modifier;
-
-  /* opcode_modifier bits: */
-#define W		   0x1	/* set if operands can be words or dwords
-				   encoded the canonical way */
-#define D		   0x2	/* D = 0 if Reg --> Regmem;
-				   D = 1 if Regmem --> Reg:    MUST BE 0x2 */
-#define Modrm		   0x4
-#define FloatR		   0x8	/* src/dest swap for floats:   MUST BE 0x8 */
-#define ShortForm	  0x10	/* register is in low 3 bits of opcode */
-#define FloatMF		  0x20	/* FP insn memory format bit, sized by 0x4 */
-#define Jump		  0x40	/* special case for jump insns.  */
-#define JumpDword	  0x80  /* call and jump */
-#define JumpByte	 0x100  /* loop and jecxz */
-#define JumpInterSegment 0x200	/* special case for intersegment leaps/calls */
-#define FloatD		 0x400	/* direction for float insns:  MUST BE 0x400 */
-#define Seg2ShortForm	 0x800	/* encoding of load segment reg insns */
-#define Seg3ShortForm	0x1000	/* fs/gs segment register insns.  */
-#define Size16		0x2000	/* needs size prefix if in 32-bit mode */
-#define Size32		0x4000	/* needs size prefix if in 16-bit mode */
-#define Size64		0x8000	/* needs size prefix if in 16-bit mode */
-#define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
-#define DefaultSize    0x20000  /* default insn size depends on mode */
-#define No_bSuf	       0x40000	/* b suffix on instruction illegal */
-#define No_wSuf	       0x80000	/* w suffix on instruction illegal */
-#define No_lSuf	      0x100000 	/* l suffix on instruction illegal */
-#define No_sSuf	      0x200000	/* s suffix on instruction illegal */
-#define No_qSuf       0x400000  /* q suffix on instruction illegal */
-#define No_xSuf       0x800000  /* x suffix on instruction illegal */
-#define FWait	     0x1000000	/* instruction needs FWAIT */
-#define IsString     0x2000000	/* quick test for string instructions */
-#define regKludge    0x4000000	/* fake an extra reg operand for clr, imul */
-#define IsPrefix     0x8000000	/* opcode is a prefix */
-#define ImmExt	    0x10000000	/* instruction has extension in 8 bit imm */
-#define NoRex64	    0x20000000  /* instruction don't need Rex64 prefix.  */
-#define Rex64	    0x40000000  /* instruction require Rex64 prefix.  */
-#define Ugh	    0x80000000	/* deprecated fp insn, gets a warning */
-
-  /* operand_types[i] describes the type of operand i.  This is made
-     by OR'ing together all of the possible type masks.  (e.g.
-     'operand_types[i] = Reg|Imm' specifies that operand i can be
-     either a register or an immediate operand.  */
-  unsigned int operand_types[3];
-
-  /* operand_types[i] bits */
-  /* register */
-#define Reg8		   0x1	/* 8 bit reg */
-#define Reg16		   0x2	/* 16 bit reg */
-#define Reg32		   0x4	/* 32 bit reg */
-#define Reg64		   0x8	/* 64 bit reg */
-  /* immediate */
-#define Imm8		  0x10	/* 8 bit immediate */
-#define Imm8S		  0x20	/* 8 bit immediate sign extended */
-#define Imm16		  0x40	/* 16 bit immediate */
-#define Imm32		  0x80	/* 32 bit immediate */
-#define Imm32S		 0x100	/* 32 bit immediate sign extended */
-#define Imm64		 0x200	/* 64 bit immediate */
-#define Imm1		 0x400	/* 1 bit immediate */
-  /* memory */
-#define BaseIndex	 0x800
-  /* Disp8,16,32 are used in different ways, depending on the
-     instruction.  For jumps, they specify the size of the PC relative
-     displacement, for baseindex type instructions, they specify the
-     size of the offset relative to the base register, and for memory
-     offset instructions such as `mov 1234,%al' they specify the size of
-     the offset relative to the segment base.  */
-#define Disp8		0x1000	/* 8 bit displacement */
-#define Disp16		0x2000	/* 16 bit displacement */
-#define Disp32		0x4000	/* 32 bit displacement */
-#define Disp32S	        0x8000	/* 32 bit signed displacement */
-#define Disp64	       0x10000	/* 64 bit displacement */
-  /* specials */
-#define InOutPortReg   0x20000	/* register to hold in/out port addr = dx */
-#define ShiftCount     0x40000	/* register to hold shift cound = cl */
-#define Control	       0x80000	/* Control register */
-#define Debug	      0x100000	/* Debug register */
-#define Test	      0x200000	/* Test register */
-#define FloatReg      0x400000	/* Float register */
-#define FloatAcc      0x800000	/* Float stack top %st(0) */
-#define SReg2	     0x1000000	/* 2 bit segment register */
-#define SReg3	     0x2000000	/* 3 bit segment register */
-#define Acc	     0x4000000	/* Accumulator %al or %ax or %eax */
-#define JumpAbsolute 0x8000000
-#define RegMMX	    0x10000000	/* MMX register */
-#define RegXMM	    0x20000000	/* XMM registers in PIII */
-#define EsSeg	    0x40000000	/* String insn operand with fixed es segment */
-
-  /* InvMem is for instructions with a modrm byte that only allow a
-     general register encoding in the i.tm.mode and i.tm.regmem fields,
-     eg. control reg moves.  They really ought to support a memory form,
-     but don't, so we add an InvMem flag to the register operand to
-     indicate that it should be encoded in the i.tm.regmem field.  */
-#define InvMem	    0x80000000
-
-#define Reg	(Reg8|Reg16|Reg32|Reg64) /* gen'l register */
-#define WordReg (Reg16|Reg32|Reg64)
-#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
-#define Imm	(Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
-#define EncImm	(Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
-#define Disp	(Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
-#define AnyMem	(Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)	/* General memory */
-  /* The following aliases are defined because the opcode table
-     carefully specifies the allowed memory types for each instruction.
-     At the moment we can only tell a memory reference size by the
-     instruction suffix, so there's not much point in defining Mem8,
-     Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
-     the suffix directly to check memory operands.  */
-#define LLongMem AnyMem		/* 64 bits (or more) */
-#define LongMem AnyMem		/* 32 bit memory ref */
-#define ShortMem AnyMem		/* 16 bit memory ref */
-#define WordMem AnyMem		/* 16 or 32 bit memory ref */
-#define ByteMem AnyMem		/* 8 bit memory ref */
-}
-template;
-
 /*
   'templates' is for grouping together 'template' structures for opcodes
   of the same name.  This is only used for storing the insns in the grand
@@ -327,25 +141,6 @@ typedef struct
 }
 templates;
 
-/* these are for register name --> number & type hash lookup */
-typedef struct
-{
-  char *reg_name;
-  unsigned int reg_type;
-  unsigned int reg_flags;
-#define RegRex	    0x1  /* Extended register.  */
-#define RegRex64    0x2  /* Extended 8 bit register.  */
-  unsigned int reg_num;
-}
-reg_entry;
-
-typedef struct
-{
-  char *seg_name;
-  unsigned int seg_prefix;
-}
-seg_entry;
-
 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 typedef struct
 {
@@ -357,16 +152,6 @@ modrm_byte;
 
 /* x86-64 extension prefix.  */
 typedef int rex_byte;
-#define REX_OPCODE	0x40
-
-/* Indicates 64 bit operand size.  */
-#define REX_MODE64	8
-/* High extension to reg field of modrm byte.  */
-#define REX_EXTX	4
-/* High extension to SIB index field.  */
-#define REX_EXTY	2
-/* High extension to base field of modrm or SIB, or reg field of opcode.  */
-#define REX_EXTZ	1
 
 /* 386 opcode byte to code indirect addressing.  */
 typedef struct
@@ -377,11 +162,30 @@ typedef struct
 }
 sib_byte;
 
-/* x86 arch names and features */
+enum processor_type
+{
+  PROCESSOR_UNKNOWN,
+  PROCESSOR_I486,
+  PROCESSOR_PENTIUM,
+  PROCESSOR_PENTIUMPRO,
+  PROCESSOR_PENTIUM4,
+  PROCESSOR_NOCONA,
+  PROCESSOR_CORE,
+  PROCESSOR_CORE2,
+  PROCESSOR_K6,
+  PROCESSOR_ATHLON,
+  PROCESSOR_K8,
+  PROCESSOR_GENERIC32,
+  PROCESSOR_GENERIC64,
+  PROCESSOR_AMDFAM10
+};
+
+/* x86 arch names, types and features */
 typedef struct
 {
-  const char *name;	/* arch name */
-  unsigned int flags;	/* cpu feature flags */
+  const char *name;		/* arch name */
+  enum processor_type type;	/* arch type */
+  unsigned int flags;		/* cpu feature flags */
 }
 arch_entry;
 
@@ -393,22 +197,22 @@ arch_entry;
 
 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
-extern void x86_cons PARAMS ((expressionS *, int));
+extern void x86_cons (expressionS *, int);
 #endif
 
 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 extern void x86_cons_fix_new
-  PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
+  (fragS *, unsigned int, unsigned int, expressionS *);
 
 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 
 #define NO_RELOC BFD_RELOC_NONE
 
-void i386_validate_fix PARAMS ((struct fix *));
+void i386_validate_fix (struct fix *);
 #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
 
 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
-extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
+extern int tc_i386_fix_adjustable (struct fix *);
 
 /* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
@@ -432,7 +236,6 @@ extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
 
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   (!(FIX)->fx_pcrel					\
-   || (FIX)->fx_plt					\
    || (FIX)->fx_r_type == BFD_RELOC_386_PLT32		\
    || (FIX)->fx_r_type == BFD_RELOC_386_GOT32		\
    || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC		\
@@ -460,7 +263,7 @@ if ((n)									\
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 
-extern void i386_align_code PARAMS ((fragS *, int));
+extern void i386_align_code (fragS *, int);
 
 #define HANDLE_ALIGN(fragP)						\
 if (fragP->fr_type == rs_align_code) 					\
@@ -468,16 +271,18 @@ if (fragP->fr_type == rs_align_code) 					\
 			   - fragP->fr_address				\
 			   - fragP->fr_fix));
 
-void i386_print_statistics PARAMS ((FILE *));
+void i386_print_statistics (FILE *);
 #define tc_print_statistics i386_print_statistics
 
 #define md_number_to_chars number_to_chars_littleendian
 
 #ifdef SCO_ELF
 #define tc_init_after_args() sco_id ()
-extern void sco_id PARAMS ((void));
+extern void sco_id (void);
 #endif
 
+#define WORKING_DOT_WORD 1
+
 /* We want .cfi_* pseudo-ops for generating unwind info.  */
 #define TARGET_USE_CFIPOP 1
 
@@ -488,17 +293,17 @@ extern int x86_cie_data_alignment;
 #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
 
 #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
-extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
+extern int tc_x86_regname_to_dw2regnum (char *);
 
 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
-extern void tc_x86_frame_initial_instructions PARAMS ((void));
+extern void tc_x86_frame_initial_instructions (void);
 
 #define md_elf_section_type(str,len) i386_elf_section_type (str, len)
-extern int i386_elf_section_type PARAMS ((const char *, size_t len));
+extern int i386_elf_section_type (const char *, size_t);
 
 /* Support for SHF_X86_64_LARGE */
-extern int x86_64_section_word PARAMS ((char *, size_t));
-extern int x86_64_section_letter PARAMS ((int letter, char **ptr_msg));
+extern int x86_64_section_word (char *, size_t);
+extern int x86_64_section_letter (int, char **);
 #define md_elf_section_letter(LETTER, PTR_MSG)	x86_64_section_letter (LETTER, PTR_MSG)
 #define md_elf_section_word(STR, LEN)		x86_64_section_word (STR, LEN)
 
diff --git a/contrib/binutils/gas/config/tc-ia64.c b/contrib/binutils/gas/config/tc-ia64.c
index 426b60f..5ed9ba8 100644
--- a/contrib/binutils/gas/config/tc-ia64.c
+++ b/contrib/binutils/gas/config/tc-ia64.c
@@ -1,5 +1,5 @@
 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
@@ -5634,7 +5634,7 @@ declare_register_set (prefix, num_regs, base_regnum)
 
   for (i = 0; i < num_regs; ++i)
     {
-      sprintf (name, "%s%u", prefix, i);
+      snprintf (name, sizeof (name), "%s%u", prefix, i);
       declare_register (name, base_regnum + i);
     }
 }
@@ -6691,7 +6691,7 @@ emit_one_bundle ()
   int addr_mod;
 
   first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
-  know (first >= 0 & first < NUM_SLOTS);
+  know (first >= 0 && first < NUM_SLOTS);
   n = MIN (3, md.num_slots_in_use);
 
   /* Determine template: user user_template if specified, best match
@@ -6971,7 +6971,8 @@ emit_one_bundle ()
 	  else
 	    as_fatal ("emit_one_bundle: unexpected dynamic op");
 
-	  sprintf (mnemonic, "%s.%c", idesc->name, "?imbfxx"[insn_unit]);
+	  snprintf (mnemonic, sizeof (mnemonic), "%s.%c",
+		    idesc->name, "?imbfxx"[insn_unit]);
 	  opnd1 = idesc->operands[0];
 	  opnd2 = idesc->operands[1];
 	  ia64_free_opcode (idesc);
@@ -7066,7 +7067,6 @@ emit_one_bundle ()
 	  fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8,
 			     &ifix->expr, ifix->is_pcrel, ifix->code);
 	  fix->tc_fix_data.opnd = ifix->opnd;
-	  fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
 	  fix->fx_file = md.slot[curr].src_file;
 	  fix->fx_line = md.slot[curr].src_line;
 	}
@@ -10544,12 +10544,15 @@ check_dependencies (idesc)
 	      int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
 
 	      if (path != 0)
-		sprintf (pathmsg, " when entry is at label '%s'",
+		snprintf (pathmsg, sizeof (pathmsg),
+			  " when entry is at label '%s'",
 			 md.entry_labels[path - 1]);
 	      if (matchtype == 1 && rs->index >= 0)
-		sprintf (indexmsg, ", specific resource number is %d",
+		snprintf (indexmsg, sizeof (indexmsg),
+			  ", specific resource number is %d",
 			 rs->index);
-	      sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
+	      snprintf (msg, sizeof (msg),
+			"Use of '%s' %s %s dependency '%s' (%s)%s%s",
 		       idesc->name,
 		       (certain ? "violates" : "may violate"),
 		       dv_mode[dep->mode], dep->name,
@@ -11862,7 +11865,7 @@ struct alias
 {
   char *file;		/* The file where the directive is seen.  */
   unsigned int line;	/* The line number the directive is at.  */
-  const char *name;	/* The orignale name of the symbol.  */
+  const char *name;	/* The original name of the symbol.  */
 };
 
 /* Called for .alias and .secalias directives. If SECTION is 1, it is
diff --git a/contrib/binutils/gas/config/tc-ia64.h b/contrib/binutils/gas/config/tc-ia64.h
index c17494b..b851b9f 100644
--- a/contrib/binutils/gas/config/tc-ia64.h
+++ b/contrib/binutils/gas/config/tc-ia64.h
@@ -1,5 +1,5 @@
 /* tc-ia64.h -- Header file for tc-ia64.c.
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
    Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
@@ -315,5 +315,5 @@ typedef struct unwind_record
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   ((FIX)->fx_r_type != BFD_RELOC_UNUSED			\
    && (!(FIX)->fx_pcrel					\
-       || (FIX)->fx_plt					\
+       || (FIX)->fx_r_type == BFD_RELOC_IA64_PLTOFF22	\
        || TC_FORCE_RELOCATION (FIX)))
diff --git a/contrib/binutils/gas/config/tc-mep.c b/contrib/binutils/gas/config/tc-mep.c
new file mode 100644
index 0000000..b3b17d3
--- /dev/null
+++ b/contrib/binutils/gas/config/tc-mep.c
@@ -0,0 +1,1886 @@
+/* tc-mep.c -- Assembler for the Toshiba Media Processor.
+   Copyright (C) 2001, 2002, 2003, 2004, 2005 Free Software Foundation.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+#include <stdio.h>
+#include "as.h"
+#include "dwarf2dbg.h"
+#include "subsegs.h"
+#include "symcat.h"
+#include "opcodes/mep-desc.h"
+#include "opcodes/mep-opc.h"
+#include "cgen.h"
+#include "elf/common.h"
+#include "elf/mep.h"
+#include "libbfd.h"
+#include "xregex.h"
+
+/* Structure to hold all of the different components describing
+   an individual instruction.  */
+typedef struct
+{
+  const CGEN_INSN *	insn;
+  const CGEN_INSN *	orig_insn;
+  CGEN_FIELDS		fields;
+#if CGEN_INT_INSN_P
+  CGEN_INSN_INT         buffer [1];
+#define INSN_VALUE(buf) (*(buf))
+#else
+  unsigned char         buffer [CGEN_MAX_INSN_SIZE];
+#define INSN_VALUE(buf) (buf)
+#endif
+  char *		addr;
+  fragS *		frag;
+  int                   num_fixups;
+  fixS *                fixups [GAS_CGEN_MAX_FIXUPS];
+  int                   indices [MAX_OPERAND_INSTANCES];
+} mep_insn;
+
+static int mode = CORE; /* Start in core mode. */
+static int pluspresent = 0;
+static int allow_disabled_registers = 0;
+static int library_flag = 0;
+
+/* We're going to need to store all of the instructions along with
+   their fixups so that we can parallelization grouping rules. */
+
+static mep_insn saved_insns[MAX_SAVED_FIXUP_CHAINS];
+static int num_insns_saved = 0;
+
+const char comment_chars[]        = "#";
+const char line_comment_chars[]   = ";#";
+const char line_separator_chars[] = ";";
+const char EXP_CHARS[]            = "eE";
+const char FLT_CHARS[]            = "dD";
+
+static void mep_switch_to_vliw_mode (int);
+static void mep_switch_to_core_mode (int);
+static void mep_s_vtext (int);
+static void mep_noregerr (int);
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "word",	cons,	                        4 },
+  { "file",	(void (*) (int)) dwarf2_directive_file,   	0 },
+  { "loc",	dwarf2_directive_loc,   	0 },
+  { "vliw", 	mep_switch_to_vliw_mode,	0 },
+  { "core", 	mep_switch_to_core_mode,	0 },
+  { "vtext", 	mep_s_vtext,             	0 },
+  { "noregerr",	mep_noregerr,	             	0 },
+  { NULL, 	NULL,		        	0 }
+};
+
+/* Relocations against symbols are done in two
+   parts, with a HI relocation and a LO relocation.  Each relocation
+   has only 16 bits of space to store an addend.  This means that in
+   order for the linker to handle carries correctly, it must be able
+   to locate both the HI and the LO relocation.  This means that the
+   relocations must appear in order in the relocation table.
+
+   In order to implement this, we keep track of each unmatched HI
+   relocation.  We then sort them so that they immediately precede the
+   corresponding LO relocation. */
+
+struct mep_hi_fixup
+{
+  struct mep_hi_fixup * next;	/* Next HI fixup.  */
+  fixS * fixp;			/* This fixup.  */
+  segT seg;			/* The section this fixup is in.  */
+};
+
+/* The list of unmatched HI relocs.  */
+static struct mep_hi_fixup * mep_hi_fixup_list;
+
+
+#define OPTION_EB		(OPTION_MD_BASE + 0)
+#define OPTION_EL		(OPTION_MD_BASE + 1)
+#define OPTION_CONFIG		(OPTION_MD_BASE + 2)
+#define OPTION_AVERAGE		(OPTION_MD_BASE + 3)
+#define OPTION_NOAVERAGE	(OPTION_MD_BASE + 4)
+#define OPTION_MULT		(OPTION_MD_BASE + 5)
+#define OPTION_NOMULT		(OPTION_MD_BASE + 6)
+#define OPTION_DIV		(OPTION_MD_BASE + 7)
+#define OPTION_NODIV		(OPTION_MD_BASE + 8)
+#define OPTION_BITOPS		(OPTION_MD_BASE + 9)
+#define OPTION_NOBITOPS		(OPTION_MD_BASE + 10)
+#define OPTION_LEADZ		(OPTION_MD_BASE + 11)
+#define OPTION_NOLEADZ		(OPTION_MD_BASE + 12)
+#define OPTION_ABSDIFF		(OPTION_MD_BASE + 13)
+#define OPTION_NOABSDIFF	(OPTION_MD_BASE + 14)
+#define OPTION_MINMAX		(OPTION_MD_BASE + 15)
+#define OPTION_NOMINMAX		(OPTION_MD_BASE + 16)
+#define OPTION_CLIP		(OPTION_MD_BASE + 17)
+#define OPTION_NOCLIP		(OPTION_MD_BASE + 18)
+#define OPTION_SATUR		(OPTION_MD_BASE + 19)
+#define OPTION_NOSATUR		(OPTION_MD_BASE + 20)
+#define OPTION_COP32		(OPTION_MD_BASE + 21)
+#define OPTION_REPEAT		(OPTION_MD_BASE + 25)
+#define OPTION_NOREPEAT		(OPTION_MD_BASE + 26)
+#define OPTION_DEBUG		(OPTION_MD_BASE + 27)
+#define OPTION_NODEBUG		(OPTION_MD_BASE + 28)
+#define OPTION_LIBRARY		(OPTION_MD_BASE + 29)
+
+struct option md_longopts[] = {
+  { "EB",          no_argument, NULL, OPTION_EB},
+  { "EL",          no_argument, NULL, OPTION_EL},
+  { "mconfig",     required_argument, NULL, OPTION_CONFIG},
+  { "maverage",    no_argument, NULL, OPTION_AVERAGE},
+  { "mno-average", no_argument, NULL, OPTION_NOAVERAGE},
+  { "mmult",       no_argument, NULL, OPTION_MULT},
+  { "mno-mult",    no_argument, NULL, OPTION_NOMULT},
+  { "mdiv",        no_argument, NULL, OPTION_DIV},
+  { "mno-div",     no_argument, NULL, OPTION_NODIV},
+  { "mbitops",     no_argument, NULL, OPTION_BITOPS},
+  { "mno-bitops",  no_argument, NULL, OPTION_NOBITOPS},
+  { "mleadz",      no_argument, NULL, OPTION_LEADZ},
+  { "mno-leadz",   no_argument, NULL, OPTION_NOLEADZ},
+  { "mabsdiff",    no_argument, NULL, OPTION_ABSDIFF},
+  { "mno-absdiff", no_argument, NULL, OPTION_NOABSDIFF},
+  { "mminmax",     no_argument, NULL, OPTION_MINMAX},
+  { "mno-minmax",  no_argument, NULL, OPTION_NOMINMAX},
+  { "mclip",       no_argument, NULL, OPTION_CLIP},
+  { "mno-clip",    no_argument, NULL, OPTION_NOCLIP},
+  { "msatur",      no_argument, NULL, OPTION_SATUR},
+  { "mno-satur",   no_argument, NULL, OPTION_NOSATUR},
+  { "mcop32",	   no_argument, NULL, OPTION_COP32},
+  { "mdebug",      no_argument, NULL, OPTION_DEBUG},
+  { "mno-debug",   no_argument, NULL, OPTION_NODEBUG},
+  { "mlibrary",    no_argument, NULL, OPTION_LIBRARY},
+  { NULL, 0, NULL, 0 } };
+size_t md_longopts_size = sizeof (md_longopts);
+
+const char * md_shortopts = "";
+static int optbits = 0;
+static int optbitset = 0;
+
+int
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+{
+  int i, idx;
+  switch (c)
+    {
+    case OPTION_EB:
+      target_big_endian = 1;
+      break;
+    case OPTION_EL:
+      target_big_endian = 0;
+      break;
+    case OPTION_CONFIG:
+      idx = 0;
+      for (i=1; mep_config_map[i].name; i++)
+	if (strcmp (mep_config_map[i].name, arg) == 0)
+	  {
+	    idx = i;
+	    break;
+	  }
+      if (!idx)
+	{
+	  fprintf (stderr, "Error: unknown configuration %s\n", arg);
+	  return 0;
+	}
+      mep_config_index = idx;
+      target_big_endian = mep_config_map[idx].big_endian;
+      break;
+    case OPTION_AVERAGE:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
+      break;
+    case OPTION_NOAVERAGE:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_AVE_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
+      break;
+    case OPTION_MULT:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
+      break;
+    case OPTION_NOMULT:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_MUL_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
+      break;
+    case OPTION_DIV:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
+      break;
+    case OPTION_NODIV:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_DIV_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
+      break;
+    case OPTION_BITOPS:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
+      break;
+    case OPTION_NOBITOPS:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_BIT_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
+      break;
+    case OPTION_LEADZ:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
+      break;
+    case OPTION_NOLEADZ:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_LDZ_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
+      break;
+    case OPTION_ABSDIFF:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
+      break;
+    case OPTION_NOABSDIFF:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_ABS_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
+      break;
+    case OPTION_MINMAX:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
+      break;
+    case OPTION_NOMINMAX:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_MINMAX_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
+      break;
+    case OPTION_CLIP:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
+      break;
+    case OPTION_NOCLIP:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_CLIP_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
+      break;
+    case OPTION_SATUR:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
+      break;
+    case OPTION_NOSATUR:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_SAT_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
+      break;
+    case OPTION_COP32:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
+      break;
+    case OPTION_DEBUG:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
+      break;
+    case OPTION_NODEBUG:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_DEBUG_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
+      break;
+    case OPTION_LIBRARY:
+      library_flag = EF_MEP_LIBRARY;
+      break;
+    case OPTION_REPEAT:
+    case OPTION_NOREPEAT:
+      break;
+    default:
+      return 0;
+    }
+  return 1;
+}
+
+void
+md_show_usage (FILE *stream)
+{
+  fprintf (stream, _("MeP specific command line options:\n\
+  -EB                     assemble for a big endian system (default)\n\
+  -EL                     assemble for a little endian system\n\
+  -mconfig=<name>         specify a chip configuration to use\n\
+  -maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n\
+  -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n\
+  -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n\
+                          enable/disable the given opcodes\n\
+\n\
+  If -mconfig is given, the other -m options modify it.  Otherwise,\n\
+  if no -m options are given, all core opcodes are enabled;\n\
+  if any enabling -m options are given, only those are enabled;\n\
+  if only disabling -m options are given, only those are disabled.\n\
+"));
+  if (mep_config_map[1].name)
+    {
+      int i;
+      fprintf (stream, "  -mconfig=STR            specify the configuration to use\n");
+      fprintf (stream, "  Configurations:");
+      for (i=0; mep_config_map[i].name; i++)
+	fprintf (stream, " %s", mep_config_map[i].name);
+      fprintf (stream, "\n");
+    }
+}
+
+
+
+static void
+mep_check_for_disabled_registers (mep_insn *insn)
+{
+  static int initted = 0;
+  static int has_mul_div = 0;
+  static int has_cop = 0;
+  static int has_debug = 0;
+  unsigned int b, r;
+
+  if (allow_disabled_registers)
+    return;
+
+#if !CGEN_INT_INSN_P
+  if (target_big_endian)
+    b = insn->buffer[0] * 256 + insn->buffer[1];
+  else
+    b = insn->buffer[1] * 256 + insn->buffer[0];
+#else
+  b = insn->buffer[0];
+#endif
+
+  if ((b & 0xfffff00e) == 0x7008 /* stc */
+      || (b & 0xfffff00e) == 0x700a /* ldc */)
+    {
+      if (!initted)
+	{
+	  initted = 1;
+	  if ((MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_MUL_INSN))
+	      || (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)))
+	    has_mul_div = 1;
+	  if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN))
+	    has_debug = 1;
+	  if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_CP_INSN))
+	    has_cop = 1;
+	}
+
+      r = ((b & 0x00f0) >> 4) | ((b & 0x0001) << 4);
+      switch (r)
+	{
+	case 7: /* $hi */
+	case 8: /* $lo */
+	  if (!has_mul_div)
+	    as_bad ("$hi and $lo are disabled when MUL and DIV are off");
+	  break;
+	case 12: /* $mb0 */
+	case 13: /* $me0 */
+	case 14: /* $mb1 */
+	case 15: /* $me1 */
+	  if (!has_cop)
+	    as_bad ("$mb0, $me0, $mb1, and $me1 are disabled when COP is off");
+	  break;
+	case 24: /* $dbg */
+	case 25: /* $depc */
+	  if (!has_debug)
+	    as_bad ("$dbg and $depc are disabled when DEBUG is off");
+	  break;
+	}
+    }
+}
+
+static int
+mep_machine (void)
+{
+  switch (MEP_CPU)
+    {
+    default: break;
+    case EF_MEP_CPU_C2: return bfd_mach_mep;
+    case EF_MEP_CPU_C3: return bfd_mach_mep;
+    case EF_MEP_CPU_C4: return bfd_mach_mep;
+    case EF_MEP_CPU_H1: return bfd_mach_mep_h1;
+    }
+
+  return bfd_mach_mep;
+}
+
+/* The MeP version of the cgen parse_operand function.  The only difference
+   from the standard version is that we want to avoid treating '$foo' and
+   '($foo...)' as references to a symbol called '$foo'.  The chances are
+   that '$foo' is really a misspelt register.  */
+
+static const char *
+mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
+		   const char **strP, int opindex, int opinfo,
+		   enum cgen_parse_operand_result *resultP, bfd_vma *valueP)
+{
+  if (want == CGEN_PARSE_OPERAND_INTEGER || want == CGEN_PARSE_OPERAND_ADDRESS)
+    {
+      const char *next;
+
+      next = *strP;
+      while (*next == '(')
+	next++;
+      if (*next == '$')
+	return "Not a valid literal";
+    }
+  return gas_cgen_parse_operand (cd, want, strP, opindex, opinfo,
+				 resultP, valueP);
+}
+
+void
+md_begin ()
+{
+  /* Initialize the `cgen' interface.  */
+
+  /* If the user specifies no options, we default to allowing
+     everything.  If the user specifies any enabling options, we
+     default to allowing only what is specified.  If the user
+     specifies only disabling options, we only disable what is
+     specified.  If the user specifies options and a config, the
+     options modify the config.  */
+  if (optbits && mep_config_index == 0)
+    MEP_OMASK = optbits;
+  else
+    MEP_OMASK = (MEP_OMASK & ~optbitset) | optbits;
+
+  /* Set the machine number and endian.  */
+  gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
+					 CGEN_CPU_OPEN_ENDIAN,
+					 target_big_endian
+					 ? CGEN_ENDIAN_BIG
+					 : CGEN_ENDIAN_LITTLE,
+					 CGEN_CPU_OPEN_ISAS, 0,
+					 CGEN_CPU_OPEN_END);
+  mep_cgen_init_asm (gas_cgen_cpu_desc);
+
+  /* This is a callback from cgen to gas to parse operands.  */
+  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, mep_parse_operand);
+
+  /* Identify the architecture.  */
+  bfd_default_set_arch_mach (stdoutput, bfd_arch_mep, mep_machine ());
+
+  /* Store the configuration number and core.  */
+  bfd_set_private_flags (stdoutput, MEP_CPU | MEP_CONFIG | library_flag);
+
+  /* Initialize the array we'll be using to store fixups.  */
+  gas_cgen_initialize_saved_fixups_array();
+}
+
+/* Variant of mep_cgen_assemble_insn.  Assemble insn STR of cpu CD as a 
+   coprocessor instruction, if possible, into FIELDS, BUF, and INSN.  */
+
+static const CGEN_INSN *
+mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd,
+			    const char *str,
+			    CGEN_FIELDS *fields,
+			    CGEN_INSN_BYTES_PTR buf,
+			    const struct cgen_insn *pinsn)
+{
+  const char *start;
+  CGEN_INSN_LIST *ilist;
+  const char *errmsg = NULL;
+
+  /* The instructions are stored in hashed lists. */
+  ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc, 
+				CGEN_INSN_MNEMONIC (pinsn));
+
+  start = str;
+  for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+    {
+      const CGEN_INSN *insn = ilist->insn;
+      if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn), 
+		  CGEN_INSN_MNEMONIC (pinsn)) == 0
+	  && MEP_INSN_COP_P (ilist->insn)
+	  && mep_cgen_insn_supported (cd, insn))
+	{
+	  str = start;
+
+	  /* skip this insn if str doesn't look right lexically */
+	  if (CGEN_INSN_RX (insn) != NULL &&
+	      regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+	    continue;
+
+	  /* Allow parse/insert handlers to obtain length of insn.  */
+	  CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+	  errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+	  if (errmsg != NULL)
+	    continue;
+	  
+	  errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+					      (bfd_vma) 0);
+	  if (errmsg != NULL)
+	    continue;
+
+	  return insn;
+	}
+    }
+  return pinsn;
+}
+
+static void
+mep_save_insn (mep_insn insn)
+{
+  /* Consider change MAX_SAVED_FIXUP_CHAINS to MAX_PARALLEL_INSNS. */
+  if (num_insns_saved < 0 || num_insns_saved >= MAX_SAVED_FIXUP_CHAINS)
+    {
+      as_fatal("index into saved_insns[] out of bounds.");
+      return;
+    }
+  saved_insns[num_insns_saved] = insn;
+  gas_cgen_save_fixups(num_insns_saved);
+  num_insns_saved++;
+}
+
+static void
+mep_check_parallel32_scheduling (void)
+{
+  int insn0iscopro, insn1iscopro, insn0length, insn1length;
+
+  /* More than two instructions means that either someone is referring to
+     an internally parallel core or an internally parallel coprocessor,
+     neither of which are supported at this time.  */
+  if ( num_insns_saved > 2 )
+    as_fatal("Internally paralled cores and coprocessors not supported.");
+
+  /* If there are no insns saved, that's ok.  Just return.  This will
+     happen when mep_process_saved_insns is called when the end of the
+     source file is reached and there are no insns left to be processed.  */
+  if (num_insns_saved == 0)
+    return;
+
+  /* Check some of the attributes of the first insn.  */
+  insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
+  insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
+
+  if (num_insns_saved == 2)
+    {
+      /* Check some of the attributes of the first insn.  */
+      insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
+      insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
+
+      if ((insn0iscopro && !insn1iscopro)
+          || (insn1iscopro && !insn0iscopro))
+	{
+          /* We have one core and one copro insn.  If their sizes
+             add up to 32, then the combination is valid.  */
+	  if (insn0length + insn1length == 32)
+	    return;
+          else
+	    as_bad ("core and copro insn lengths must total 32 bits.");
+	}
+      else
+        as_bad ("vliw group must consist of 1 core and 1 copro insn."); 
+    }
+  else
+    {
+      /* If we arrive here, we have one saved instruction.  There are a
+	 number of possible cases:
+
+	 1.  The instruction is a 32 bit core or coprocessor insn and
+             can be executed by itself.  Valid.
+
+         2.  The instrucion is a core instruction for which a cop nop
+             exists.  In this case, insert the cop nop into the saved
+             insn array after the core insn and return.  Valid.
+
+         3.  The instruction is a coprocessor insn for which a core nop
+             exists.  In this case, move the coprocessor insn to the
+             second element of the array and put the nop in the first
+	     element then return.  Valid.
+
+         4. The instruction is a core or coprocessor instruction for
+            which there is no matching coprocessor or core nop to use
+	    to form a valid vliw insn combination.  In this case, we
+	    we have to abort.  */
+
+      if (insn0length > 32)
+	as_fatal ("Cannot use 48- or 64-bit insns with a 32 bit datapath.");
+
+      if (insn0length == 32)
+	return;
+
+      /* Insn is smaller than datapath.  If there are no matching
+         nops for this insn, then terminate assembly.  */
+      if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
+                                CGEN_INSN_VLIW32_NO_MATCHING_NOP))
+	as_fatal ("No valid nop.");
+
+      /* At this point we know that we have a single 16-bit insn that has 
+	 a matching nop.  We have to assemble it and put it into the saved 
+         insn and fixup chain arrays. */
+
+      if (insn0iscopro)
+	{
+          char *errmsg;
+          mep_insn insn;
+         
+          /* Move the insn and it's fixups to the second element of the
+             saved insns arrary and insert a 16 bit core nope into the
+             first element. */
+             insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
+                                                 &insn.fields, insn.buffer,
+                                                 &errmsg);
+             if (!insn.insn)
+               {
+                 as_bad ("%s", errmsg);
+                 return;
+               }
+
+             /* Move the insn in element 0 to element 1 and insert the
+                 nop into element 0.  Move the fixups in element 0 to
+                 element 1 and save the current fixups to element 0.  
+                 Really there aren't any fixups at this point because we're
+                 inserting a nop but we might as well be general so that
+                 if there's ever a need to insert a general insn, we'll
+                 have an example. */
+              saved_insns[1] = saved_insns[0];
+              saved_insns[0] = insn;
+              num_insns_saved++;
+              gas_cgen_swap_fixups (0);
+              gas_cgen_save_fixups (1);
+	}
+      else
+	{
+          char * errmsg;
+          mep_insn insn;
+	  int insn_num = saved_insns[0].insn->base->num;
+
+	  /* Use 32 bit branches and skip the nop.  */
+	  if (insn_num == MEP_INSN_BSR12
+	      || insn_num == MEP_INSN_BEQZ
+	      || insn_num == MEP_INSN_BNEZ)
+	    return;
+
+          /* Insert a 16-bit coprocessor nop.  Note that at the time */
+          /* this was done, no 16-bit coprocessor nop was defined.   */
+	  insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
+					      &insn.fields, insn.buffer,
+					      &errmsg);
+          if (!insn.insn)
+            {
+              as_bad ("%s", errmsg);
+              return;
+            }
+
+          /* Now put the insn and fixups into the arrays.  */
+          mep_save_insn (insn);
+	}
+    }
+}
+
+static void
+mep_check_parallel64_scheduling (void)
+{
+  int insn0iscopro, insn1iscopro, insn0length, insn1length;
+
+  /* More than two instructions means that someone is referring to an
+     internally parallel core or an internally parallel coprocessor.  */
+  /* These are not currently supported.  */
+  if (num_insns_saved > 2)
+    as_fatal ("Internally parallel cores of coprocessors not supported.");
+
+  /* If there are no insns saved, that's ok.  Just return.  This will
+     happen when mep_process_saved_insns is called when the end of the
+     source file is reached and there are no insns left to be processed.  */
+  if (num_insns_saved == 0)
+    return;
+
+  /* Check some of the attributes of the first insn.  */
+  insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
+  insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
+
+  if (num_insns_saved == 2)
+    {
+      /* Check some of the attributes of the first insn. */
+      insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
+      insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
+
+      if ((insn0iscopro && !insn1iscopro)
+	  || (insn1iscopro && !insn0iscopro))
+	{
+	  /* We have one core and one copro insn.  If their sizes
+	     add up to 64, then the combination is valid.  */
+	  if (insn0length + insn1length == 64)
+            return;
+	  else
+            as_bad ("core and copro insn lengths must total 64 bits.");
+	}
+      else
+        as_bad ("vliw group must consist of 1 core and 1 copro insn.");
+    }
+  else
+    {
+      /* If we arrive here, we have one saved instruction.  There are a
+	 number of possible cases:
+
+         1.  The instruction is a 64 bit coprocessor insn and can be
+             executed by itself.  Valid.
+
+         2.  The instrucion is a core instruction for which a cop nop
+             exists.  In this case, insert the cop nop into the saved
+             insn array after the core insn and return.  Valid.
+
+         3.  The instruction is a coprocessor insn for which a core nop
+             exists.  In this case, move the coprocessor insn to the
+             second element of the array and put the nop in the first
+             element then return.  Valid.
+
+         4.  The instruction is a core or coprocessor instruction for
+             which there is no matching coprocessor or core nop to use
+             to form a valid vliw insn combination.  In this case, we
+	     we have to abort.  */
+
+      /* If the insn is 64 bits long, it can run alone.  The size check
+	 is done indepependantly of whether the insn is core or copro
+	 in case 64 bit coprocessor insns are added later.  */
+      if (insn0length == 64)
+        return;
+
+      /* Insn is smaller than datapath.  If there are no matching
+	 nops for this insn, then terminate assembly.  */
+      if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
+				CGEN_INSN_VLIW64_NO_MATCHING_NOP))
+	as_fatal ("No valid nop.");
+
+      if (insn0iscopro)
+	{
+	  char *errmsg;
+	  mep_insn insn;
+          int i;
+
+          /* Initialize the insn buffer.  */
+          for (i = 0; i < 64; i++)
+             insn.buffer[i] = '\0';
+
+	  /* We have a coprocessor insn.  At this point in time there
+	     are is 32-bit core nop.  There is only a 16-bit core
+	     nop.  The idea is to allow for a relatively arbitrary
+	     coprocessor to be specified.  We aren't looking at
+	     trying to cover future changes in the core at this time
+	     since it is assumed that the core will remain fairly
+	     static.  If there ever are 32 or 48 bit core nops added,
+	     they will require entries below.  */
+
+	  if (insn0length == 48)
+	    {
+	      /* Move the insn and fixups to the second element of the
+		 arrays then assemble and insert a 16 bit core nop.  */
+	      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
+						  & insn.fields, insn.buffer,
+						  & errmsg);
+	    }
+          else
+            {
+              /* If this is reached, then we have a single coprocessor
+                 insn that is not 48 bits long, but for which the assembler
+                 thinks there is a matching core nop.  If a 32-bit core
+                 nop has been added, then make the necessary changes and
+                 handle its assembly and insertion here.  Otherwise,
+                 go figure out why either:
+              
+                 1. The assembler thinks that there is a 32-bit core nop
+                    to match a 32-bit coprocessor insn, or
+                 2. The assembler thinks that there is a 48-bit core nop
+                    to match a 16-bit coprocessor insn.  */
+
+              as_fatal ("Assembler expects a non-existent core nop.");
+            }
+
+	 if (!insn.insn)
+	   {
+	     as_bad ("%s", errmsg);
+	     return;
+	   }
+
+         /* Move the insn in element 0 to element 1 and insert the
+            nop into element 0.  Move the fixups in element 0 to
+            element 1 and save the current fixups to element 0. 
+	    Really there aren't any fixups at this point because we're
+	    inserting a nop but we might as well be general so that
+	    if there's ever a need to insert a general insn, we'll
+	    have an example. */
+
+         saved_insns[1] = saved_insns[0];
+         saved_insns[0] = insn;
+         num_insns_saved++;
+         gas_cgen_swap_fixups(0);
+         gas_cgen_save_fixups(1);
+
+	}
+      else
+	{
+	  char * errmsg;
+	  mep_insn insn;
+          int i;
+
+          /* Initialize the insn buffer */
+          for (i = 0; i < 64; i++)
+             insn.buffer[i] = '\0';
+
+	  /* We have a core insn.  We have to handle all possible nop
+	     lengths.  If a coprocessor doesn't have a nop of a certain
+	     length but there exists core insns that when combined with
+	      a nop of that length would fill the datapath, those core
+	      insns will be flagged with the VLIW_NO_CORRESPONDING_NOP
+	      attribute.  That will ensure that when used in a way that
+	      requires a nop to be inserted, assembly will terminate
+	      before reaching this section of code.  This guarantees
+	      that cases below which would result in the attempted
+	      insertion of nop that doesn't exist will never be entered.  */
+	  if (insn0length == 16)
+	    {
+	      /* Insert 48 bit coprocessor nop.          */
+	      /* Assemble it and put it into the arrays. */
+	      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop48",
+						  &insn.fields, insn.buffer,
+						  &errmsg);
+	    }
+	  else if (insn0length == 32)
+	    {
+	      /* Insert 32 bit coprocessor nop. */
+	      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop32",
+						  &insn.fields, insn.buffer,
+						  &errmsg);
+	    }
+	  else if (insn0length == 48)
+	    {
+	      /* Insert 16 bit coprocessor nop. */
+	      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
+						  &insn.fields, insn.buffer,
+						  &errmsg);
+	    }
+	  else
+	    /* Core insn has an invalid length.  Something has gone wrong. */
+	    as_fatal ("Core insn has invalid length!  Something is wrong!");
+
+	  if (!insn.insn)
+	    {
+	      as_bad ("%s", errmsg);
+	      return;
+	    }
+
+	  /* Now put the insn and fixups into the arrays.  */
+	  mep_save_insn (insn);
+	}
+    }
+}
+
+/* The scheduling functions are just filters for invalid combinations.
+   If there is a violation, they terminate assembly.  Otherise they
+   just fall through.  Succesful combinations cause no side effects
+   other than valid nop insertion.  */
+
+static void
+mep_check_parallel_scheduling (void)
+{
+  /* This is where we will eventually read the config information
+     and choose which scheduling checking function to call.  */   
+  if (MEP_VLIW64)
+    mep_check_parallel64_scheduling ();
+  else
+    mep_check_parallel32_scheduling ();
+}
+
+static void
+mep_process_saved_insns (void)
+{
+  int i;
+
+  gas_cgen_save_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
+
+  /* We have to check for valid scheduling here. */
+  mep_check_parallel_scheduling ();
+
+  /* If the last call didn't cause assembly to terminate, we have
+     a valid vliw insn/insn pair saved. Restore this instructions'
+     fixups and process the insns. */
+  for (i = 0;i<num_insns_saved;i++)
+    {
+      gas_cgen_restore_fixups (i);
+      gas_cgen_finish_insn (saved_insns[i].insn, saved_insns[i].buffer,
+			    CGEN_FIELDS_BITSIZE (& saved_insns[i].fields),
+			    1, NULL);
+    }
+  gas_cgen_restore_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
+
+  /* Clear the fixups and reset the number insn saved to 0. */
+  gas_cgen_initialize_saved_fixups_array ();
+  num_insns_saved = 0;
+  listing_prev_line ();
+}
+
+void
+md_assemble (char * str)
+{
+  static CGEN_BITSET* isas = NULL;
+  char * errmsg;
+
+  /* Initialize GAS's cgen interface for a new instruction.  */
+  gas_cgen_init_parse ();
+
+  /* There are two possible modes: core and vliw.  We have to assemble
+     differently for each.
+
+     Core Mode:  We assemble normally.  All instructions are on a
+                 single line and are made up of one mnemonic and one
+                 set of operands.
+     VLIW Mode:  Vliw combinations are indicated as follows:
+
+		       core insn
+		     + copro insn
+
+                 We want to handle the general case where more than
+                 one instruction can be preceeded by a +.  This will
+                 happen later if we add support for internally parallel
+                 coprocessors.  We'll make the parsing nice and general
+                 so that it can handle an arbitrary number of insns
+                 with leading +'s.  The actual checking for valid
+                 combinations is done elsewhere.  */
+
+  /* Initialize the isa to refer to the core.  */
+  if (isas == NULL)
+    isas = cgen_bitset_copy (& MEP_CORE_ISA);
+  else
+    {
+      cgen_bitset_clear (isas);
+      cgen_bitset_union (isas, & MEP_CORE_ISA, isas);
+    }
+  gas_cgen_cpu_desc->isas = isas;
+
+  if (mode == VLIW)
+    {
+      /* VLIW mode.  */
+
+      int thisInsnIsCopro = 0;
+      mep_insn insn;
+      int i;
+      
+      /* Initialize the insn buffer */
+	
+      if (! CGEN_INT_INSN_P)
+         for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
+            insn.buffer[i]='\0';
+
+      /* Can't tell core / copro insns apart at parse time! */
+      cgen_bitset_union (isas, & MEP_COP_ISA, isas);
+
+      /* Assemble the insn so we can examine its attributes. */
+      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, str,
+					  &insn.fields, insn.buffer,
+					  &errmsg);
+      if (!insn.insn)
+	{
+	  as_bad ("%s", errmsg);
+	  return;
+	}
+      mep_check_for_disabled_registers (&insn);
+
+      /* Check to see if it's a coprocessor instruction. */
+      thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
+
+      if (!thisInsnIsCopro)
+	{
+	  insn.insn = mep_cgen_assemble_cop_insn (gas_cgen_cpu_desc, str,
+						  &insn.fields, insn.buffer,
+						  insn.insn);
+	  thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
+	  mep_check_for_disabled_registers (&insn);
+	}
+
+      if (pluspresent)
+	{
+	  /* A plus was present. */
+	  /* Check for a + with a core insn and abort if found. */
+	  if (!thisInsnIsCopro)
+	    {
+	      as_fatal("A core insn cannot be preceeded by a +.\n");
+	      return;
+	    }
+
+	  if (num_insns_saved > 0)
+	    {
+	      /* There are insns in the queue. Add this one. */
+	      mep_save_insn (insn);
+	    }
+	  else
+	    {
+	      /* There are no insns in the queue and a plus is present.
+		 This is a syntax error.  Let's not tolerate this.
+		 We can relax this later if necessary.  */
+	      as_bad (_("Invalid use of parallelization operator."));
+	      return;
+	    }
+	}
+      else
+	{
+	  /* No plus was present. */
+	  if (num_insns_saved > 0)
+	    {
+	      /* There are insns saved and we came across an insn without a
+		 leading +.  That's the signal to process the saved insns
+		 before proceeding then treat the current insn as the first
+		 in a new vliw group.  */
+	      mep_process_saved_insns ();
+	      num_insns_saved = 0;
+	      /* mep_save_insn (insn); */
+	    }
+	  mep_save_insn (insn);
+#if 0
+	  else
+	    {
+
+              /* Core Insn. Add it to the beginning of the queue. */
+              mep_save_insn (insn);
+	      /* gas_cgen_save_fixups(num_insns_saved); */
+	    }
+#endif
+	}
+
+      pluspresent = 0;
+    }
+  else
+    {
+      /* Core mode.  */
+
+      /* Only single instructions are assembled in core mode. */
+      mep_insn insn;
+
+      /* If a leading '+' was present, issue an error.
+	 That's not allowed in core mode. */
+      if (pluspresent)
+	{
+	  as_bad (_("Leading plus sign not allowed in core mode"));
+	  return;
+	}
+
+      insn.insn = mep_cgen_assemble_insn
+	(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
+
+      if (!insn.insn)
+	{
+	  as_bad ("%s", errmsg);
+	  return;
+	}
+      gas_cgen_finish_insn (insn.insn, insn.buffer,
+			    CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
+      mep_check_for_disabled_registers (&insn);
+    }
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, segment);
+  return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Interface to relax_segment.  */
+
+
+const relax_typeS md_relax_table[] =
+{
+  /* The fields are:
+     1) most positive reach of this state,
+     2) most negative reach of this state,
+     3) how many bytes this mode will have in the variable part of the frag
+     4) which index into the table to try if we can't fit into this one.  */
+  /* Note that we use "beq" because "jmp" has a peculiarity - it cannot
+     jump to addresses with any bits 27..24 set.  So, we use beq as a
+     17-bit pc-relative branch to avoid using jmp, just in case.  */
+
+  /* 0 */ {     0,      0, 0, 0 }, /* unused */
+  /* 1 */ {     0,      0, 0, 0 }, /* marker for "don't know yet" */
+
+  /* 2 */ {  2047,  -2048, 0, 3 }, /* bsr12 */
+  /* 3 */ {     0,      0, 2, 0 }, /* bsr16 */
+
+  /* 4 */ {  2047,  -2048, 0, 5 }, /* bra */
+  /* 5 */ { 65535, -65536, 2, 6 }, /* beq $0,$0 */
+  /* 6 */ {     0,      0, 2, 0 }, /* jmp24 */
+
+  /* 7 */ { 65535, -65536, 0, 8 }, /* beqi */
+  /* 8 */ {     0,      0, 4, 0 }, /* bnei/jmp */
+
+  /* 9 */  {   127,   -128, 0, 10 }, /* beqz */
+  /* 10 */ { 65535, -65536, 2, 11 }, /* beqi */
+  /* 11 */ {     0,      0, 4,  0 }, /* bnei/jmp */
+
+  /* 12 */ { 65535, -65536, 0, 13 }, /* bnei */
+  /* 13 */ {     0,      0, 4,  0 }, /* beqi/jmp */
+
+  /* 14 */ {   127,   -128, 0, 15 }, /* bnez */
+  /* 15 */ { 65535, -65536, 2, 16 }, /* bnei */
+  /* 16 */ {     0,      0, 4,  0 },  /* beqi/jmp */
+
+  /* 17 */ { 65535, -65536, 0, 13 }, /* bgei */
+  /* 18 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* blti */
+  /* 20 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* bcpeq */
+  /* 20 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* bcpne */
+  /* 20 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* bcpat */
+  /* 20 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* bcpaf */
+  /* 20 */ {     0,      0, 4,  0 }
+};
+
+/* Pseudo-values for 64 bit "insns" which are combinations of two 32
+   bit insns.  */
+typedef enum {
+  MEP_PSEUDO64_NONE,
+  MEP_PSEUDO64_16BITCC,
+  MEP_PSEUDO64_32BITCC,
+} MepPseudo64Values;
+
+static struct {
+  int insn;
+  int growth;
+  int insn_for_extern;
+} subtype_mappings[] = {
+  { 0, 0, 0 },
+  { 0, 0, 0 },
+  { MEP_INSN_BSR12, 0, MEP_INSN_BSR24 },
+  { MEP_INSN_BSR24, 2, MEP_INSN_BSR24 },
+  { MEP_INSN_BRA,   0, MEP_INSN_BRA   },
+  { MEP_INSN_BEQ,   2, MEP_INSN_BEQ   },
+  { MEP_INSN_JMP,   2, MEP_INSN_JMP   },
+  { MEP_INSN_BEQI,  0, MEP_INSN_BEQI  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BEQZ,  0, MEP_INSN_BEQZ  },
+  { MEP_INSN_BEQI,  2, MEP_INSN_BEQI  },
+  { -1,             4, MEP_PSEUDO64_16BITCC },
+  { MEP_INSN_BNEI,  0, MEP_INSN_BNEI  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BNEZ,  0, MEP_INSN_BNEZ  },
+  { MEP_INSN_BNEI,  2, MEP_INSN_BNEI  },
+  { -1,             4, MEP_PSEUDO64_16BITCC },
+  { MEP_INSN_BGEI,  0, MEP_INSN_BGEI  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BLTI,  0, MEP_INSN_BLTI  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BCPEQ, 0, MEP_INSN_BCPEQ  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BCPNE, 0, MEP_INSN_BCPNE  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BCPAT, 0, MEP_INSN_BCPAT  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BCPAF, 0, MEP_INSN_BCPAF  },
+  { -1,             4, MEP_PSEUDO64_32BITCC }
+};
+#define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
+
+void
+mep_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
+{
+  symbolS *symbolP = fragP->fr_symbol;
+  if (symbolP && !S_IS_DEFINED (symbolP))
+    *aim = 0;
+  /* Adjust for MeP pcrel not being relative to the next opcode.  */
+  *aim += 2 + md_relax_table[this_state].rlx_length;
+}
+
+static int
+insn_to_subtype (int insn)
+{
+  unsigned int i;
+  for (i=0; i<NUM_MAPPINGS; i++)
+    if (insn == subtype_mappings[i].insn)
+      return i;
+  abort ();
+}
+
+/* Return an initial guess of the length by which a fragment must grow
+   to hold a branch to reach its destination.  Also updates fr_type
+   and fr_subtype as necessary.
+
+   Called just before doing relaxation.  Any symbol that is now
+   undefined will not become defined.  The guess for fr_var is
+   ACTUALLY the growth beyond fr_fix.  Whatever we do to grow fr_fix
+   or fr_var contributes to our returned value.  Although it may not
+   be explicit in the frag, pretend fr_var starts with a 0 value.  */
+
+int
+md_estimate_size_before_relax (fragS * fragP, segT segment)
+{
+  if (fragP->fr_subtype == 1)
+    fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
+
+  if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
+    {
+      int new_insn;
+
+      new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
+      fragP->fr_subtype = insn_to_subtype (new_insn);
+    }
+
+  if (MEP_VLIW && ! MEP_VLIW64
+      && (bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW))
+    {
+      /* Use 32 bit branches for vliw32 so the vliw word is not split.  */
+      switch (fragP->fr_cgen.insn->base->num)
+	{
+	case MEP_INSN_BSR12:
+	  fragP->fr_subtype = insn_to_subtype 
+	    (subtype_mappings[fragP->fr_subtype].insn_for_extern);
+	  break;
+	case MEP_INSN_BEQZ:
+	  fragP->fr_subtype ++;
+	  break;
+	case MEP_INSN_BNEZ:
+	  fragP->fr_subtype ++;
+	  break;
+	}
+    }
+
+  if (fragP->fr_cgen.insn->base
+      && fragP->fr_cgen.insn->base->num
+         != subtype_mappings[fragP->fr_subtype].insn)
+    {
+      int new_insn= subtype_mappings[fragP->fr_subtype].insn;
+      if (new_insn != -1)
+	{
+	  fragP->fr_cgen.insn = (fragP->fr_cgen.insn
+				 - fragP->fr_cgen.insn->base->num
+				 + new_insn);
+	}
+    }
+
+  return subtype_mappings[fragP->fr_subtype].growth;
+}
+
+/* *fragP has been relaxed to its final size, and now needs to have
+   the bytes inside it modified to conform to the new size.
+
+   Called after relaxation is finished.
+   fragP->fr_type == rs_machine_dependent.
+   fragP->fr_subtype is the subtype of what the address relaxed to.  */
+
+static int
+target_address_for (fragS *frag)
+{
+  int rv = frag->fr_offset;
+  symbolS *sym = frag->fr_symbol;
+
+  if (sym)
+    rv += S_GET_VALUE (sym);
+
+  return rv;
+}
+
+void
+md_convert_frag (bfd *abfd  ATTRIBUTE_UNUSED, 
+		 segT sec ATTRIBUTE_UNUSED,
+		 fragS *fragP)
+{
+  int addend, rn, bit = 0;
+  int operand;
+  int where = fragP->fr_opcode - fragP->fr_literal;
+  int e = target_big_endian ? 0 : 1;
+
+  addend = target_address_for (fragP) - (fragP->fr_address + where);
+
+  if (subtype_mappings[fragP->fr_subtype].insn == -1)
+    {
+      fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
+      switch (subtype_mappings[fragP->fr_subtype].insn_for_extern)
+	{
+	case MEP_PSEUDO64_16BITCC:
+	  fragP->fr_opcode[1^e] = ((fragP->fr_opcode[1^e] & 1) ^ 1) | 0x06;
+	  fragP->fr_opcode[2^e] = 0xd8;
+	  fragP->fr_opcode[3^e] = 0x08;
+	  fragP->fr_opcode[4^e] = 0;
+	  fragP->fr_opcode[5^e] = 0;
+	  where += 2;
+	  break;
+	case MEP_PSEUDO64_32BITCC:
+	  if (fragP->fr_opcode[0^e] & 0x10)
+	    fragP->fr_opcode[1^e] ^= 0x01;
+	  else
+	    fragP->fr_opcode[1^e] ^= 0x04;
+	  fragP->fr_opcode[2^e] = 0;
+	  fragP->fr_opcode[3^e] = 4;
+	  fragP->fr_opcode[4^e] = 0xd8;
+	  fragP->fr_opcode[5^e] = 0x08;
+	  fragP->fr_opcode[6^e] = 0;
+	  fragP->fr_opcode[7^e] = 0;
+	  where += 4;
+	  break;
+	default:
+	  abort ();
+	}
+      fragP->fr_cgen.insn = (fragP->fr_cgen.insn
+			     - fragP->fr_cgen.insn->base->num
+			     + MEP_INSN_JMP);
+      operand = MEP_OPERAND_PCABS24A2;
+    }
+  else
+    switch (fragP->fr_cgen.insn->base->num)
+      {
+      case MEP_INSN_BSR12:
+	fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
+	fragP->fr_opcode[1^e] = 0x01 | (addend & 0xfe);
+	operand = MEP_OPERAND_PCREL12A2;
+	break;
+
+      case MEP_INSN_BSR24:
+	fragP->fr_fix += 2;
+	fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
+	fragP->fr_opcode[1^e] = 0x09 | ((addend << 3) & 0xf0);
+	fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
+	fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
+	operand = MEP_OPERAND_PCREL24A2;
+	break;
+
+      case MEP_INSN_BRA:
+	fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
+	fragP->fr_opcode[1^e] = 0x00 | (addend & 0xfe);
+	operand = MEP_OPERAND_PCREL12A2;
+	break;
+
+      case MEP_INSN_BEQ:
+	/* The default relax_frag doesn't change the state if there is no
+	   growth, so we must manually handle converting out-of-range BEQ
+	   instructions to JMP.  */
+	if (addend <= 65535 && addend >= -65536)
+	  {
+	    fragP->fr_fix += 2;
+	    fragP->fr_opcode[0^e] = 0xe0;
+	    fragP->fr_opcode[1^e] = 0x01;
+	    fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
+	    fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
+	    operand = MEP_OPERAND_PCREL17A2;
+	    break;
+	  }
+	/* ...FALLTHROUGH... */
+
+      case MEP_INSN_JMP:
+	addend = target_address_for (fragP);
+	fragP->fr_fix += 2;
+	fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
+	fragP->fr_opcode[1^e] = 0x08 | ((addend << 3) & 0xf0);
+	fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
+	fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
+	operand = MEP_OPERAND_PCABS24A2;
+	break;
+
+      case MEP_INSN_BNEZ:
+	bit = 1;
+      case MEP_INSN_BEQZ:
+	fragP->fr_opcode[1^e] = bit | (addend & 0xfe);
+	operand = MEP_OPERAND_PCREL8A2;
+	break;
+
+      case MEP_INSN_BNEI:
+	bit = 4;
+      case MEP_INSN_BEQI:
+	if (subtype_mappings[fragP->fr_subtype].growth)
+	  {
+	    fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
+	    rn = fragP->fr_opcode[0^e] & 0x0f;
+	    fragP->fr_opcode[0^e] = 0xe0 | rn;
+	    fragP->fr_opcode[1^e] = bit;
+	  }
+	fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
+	fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
+	operand = MEP_OPERAND_PCREL17A2;
+	break;
+
+      case MEP_INSN_BLTI:
+      case MEP_INSN_BGEI:
+      case MEP_INSN_BCPEQ:
+      case MEP_INSN_BCPNE:
+      case MEP_INSN_BCPAT:
+      case MEP_INSN_BCPAF:
+	/* No opcode change needed, just operand.  */
+	fragP->fr_opcode[2^e] = (addend >> 9) & 0xff;
+	fragP->fr_opcode[3^e] = (addend >> 1) & 0xff;
+	operand = MEP_OPERAND_PCREL17A2;
+	break;
+
+      default:
+	abort ();
+      }
+
+  if (S_GET_SEGMENT (fragP->fr_symbol) != sec
+      || operand == MEP_OPERAND_PCABS24A2)
+    {
+      assert (fragP->fr_cgen.insn != 0);
+      gas_cgen_record_fixup (fragP,
+			     where,
+			     fragP->fr_cgen.insn,
+			     (fragP->fr_fix - where) * 8,
+			     cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+							 operand),
+			     fragP->fr_cgen.opinfo,
+			     fragP->fr_symbol, fragP->fr_offset);
+    }
+}
+
+
+/* Functions concerning relocs.  */
+
+void
+mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+{
+  /* If we already know the fixup value, adjust it in the same
+     way that the linker would have done.  */
+  if (fixP->fx_addsy == 0)
+    switch (fixP->fx_cgen.opinfo)
+      {
+      case BFD_RELOC_MEP_LOW16:
+	*valP = ((long)(*valP & 0xffff)) << 16 >> 16;
+	break;
+      case BFD_RELOC_MEP_HI16U:
+	*valP >>= 16;
+	break;
+      case BFD_RELOC_MEP_HI16S:
+	*valP = (*valP + 0x8000) >> 16;
+	break;
+      }
+
+  /* Now call cgen's md_aply_fix.  */
+  gas_cgen_md_apply_fix (fixP, valP, seg);
+}
+
+long
+md_pcrel_from_section (fixS *fixP, segT sec)
+{
+  if (fixP->fx_addsy != (symbolS *) NULL
+      && (! S_IS_DEFINED (fixP->fx_addsy)
+	  || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+    /* The symbol is undefined (or is defined but not in this section).
+       Let the linker figure it out.  */
+    return 0;
+
+  /* Return the address of the opcode - cgen adjusts for opcode size
+     itself, to be consistent with the disassembler, which must do
+     so.  */
+  return fixP->fx_where + fixP->fx_frag->fr_address;
+}
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
+   Returns BFD_RELOC_NONE if no reloc type can be found.
+   *FIXP may be modified if desired.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define MAP(n) case MEP_OPERAND_##n: return BFD_RELOC_MEP_##n;
+#else
+#define MAP(n) case MEP_OPERAND_/**/n: return BFD_RELOC_MEP_/**/n;
+#endif
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND *operand,
+		      fixS *fixP)
+{
+  enum bfd_reloc_code_real reloc = fixP->fx_cgen.opinfo;
+  static char printed[MEP_OPERAND_MAX] = { 0 };
+
+  /* If there's a reloc here, it's because the parser saw a %foo() and
+     is giving us the correct reloc to use, or because we converted to
+     a different size reloc below and want to avoid "converting" more
+     than once.  */
+  if (reloc && reloc != BFD_RELOC_NONE)
+    return reloc;
+
+  switch (operand->type)
+    {
+      MAP (PCREL8A2);	/* beqz */
+      MAP (PCREL12A2);	/* bsr16 */
+      MAP (PCREL17A2);	/* beqi */
+      MAP (PCREL24A2);	/* bsr24 */
+      MAP (PCABS24A2);	/* jmp */
+      MAP (UIMM24);	/* mov */
+      MAP (ADDR24A4);	/* sw/lw */
+
+    /* The rest of the relocs should be generated by the parser,
+       for things such as %tprel(), etc. */
+    case MEP_OPERAND_SIMM16:
+#ifdef OBJ_COMPLEX_RELC
+      /* coalescing this into RELOC_MEP_16 is actually a bug,
+	 since it's a signed operand. let the relc code handle it. */
+      return BFD_RELOC_RELC; 
+#endif
+
+    case MEP_OPERAND_UIMM16:
+    case MEP_OPERAND_SDISP16:
+    case MEP_OPERAND_CODE16:
+      fixP->fx_where += 2;
+      /* to avoid doing the above add twice */
+      fixP->fx_cgen.opinfo = BFD_RELOC_MEP_16;
+      return BFD_RELOC_MEP_16;
+
+    default:
+#ifdef OBJ_COMPLEX_RELC
+      /* this is not an error, yet. 
+	 pass it to the linker. */
+      return BFD_RELOC_RELC;
+#endif
+      if (printed[operand->type])
+	return BFD_RELOC_NONE;
+      printed[operand->type] = 1;
+
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+		    _("Don't know how to relocate plain operands of type %s"),
+		    operand->name);
+
+      /* Print some helpful hints for the user.  */
+      switch (operand->type)
+	{
+	case MEP_OPERAND_UDISP7:
+	case MEP_OPERAND_UDISP7A2:
+	case MEP_OPERAND_UDISP7A4:
+	  as_bad_where (fixP->fx_file, fixP->fx_line,
+			_("Perhaps you are missing %%tpoff()?"));
+	  break;
+	default:
+	  break;
+	}
+      return BFD_RELOC_NONE;
+    }
+}
+
+/* Called while parsing an instruction to create a fixup.
+   We need to check for HI16 relocs and queue them up for later sorting.  */
+
+fixS *
+mep_cgen_record_fixup_exp (fragS *frag,
+			   int where,
+			   const CGEN_INSN *insn,
+			   int length,
+			   const CGEN_OPERAND *operand,
+			   int opinfo,
+			   expressionS *exp)
+{
+  fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
+					   operand, opinfo, exp);
+  return fixP;
+}
+
+/* Return BFD reloc type from opinfo field in a fixS.
+   It's tricky using fx_r_type in mep_frob_file because the values
+   are BFD_RELOC_UNUSED + operand number.  */
+#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
+
+/* Sort any unmatched HI16 relocs so that they immediately precede
+   the corresponding LO16 reloc.  This is called before md_apply_fix and
+   tc_gen_reloc.  */
+
+void
+mep_frob_file ()
+{
+  struct mep_hi_fixup * l;
+
+  for (l = mep_hi_fixup_list; l != NULL; l = l->next)
+    {
+      segment_info_type * seginfo;
+      int pass;
+
+      assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_HI16
+	      || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_LO16);
+
+      /* Check quickly whether the next fixup happens to be a matching low.  */
+      if (l->fixp->fx_next != NULL
+	  && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_LO16
+	  && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
+	  && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
+	continue;
+
+      /* Look through the fixups for this segment for a matching
+         `low'.  When we find one, move the high just in front of it.
+         We do this in two passes.  In the first pass, we try to find
+         a unique `low'.  In the second pass, we permit multiple
+         high's relocs for a single `low'.  */
+      seginfo = seg_info (l->seg);
+      for (pass = 0; pass < 2; pass++)
+	{
+	  fixS * f;
+	  fixS * prev;
+
+	  prev = NULL;
+	  for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
+	    {
+	      /* Check whether this is a `low' fixup which matches l->fixp.  */
+	      if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_LO16
+		  && f->fx_addsy == l->fixp->fx_addsy
+		  && f->fx_offset == l->fixp->fx_offset
+		  && (pass == 1
+		      || prev == NULL
+		      || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_HI16)
+		      || prev->fx_addsy != f->fx_addsy
+		      || prev->fx_offset !=  f->fx_offset))
+		{
+		  fixS ** pf;
+
+		  /* Move l->fixp before f.  */
+		  for (pf = &seginfo->fix_root;
+		       * pf != l->fixp;
+		       pf = & (* pf)->fx_next)
+		    assert (* pf != NULL);
+
+		  * pf = l->fixp->fx_next;
+
+		  l->fixp->fx_next = f;
+		  if (prev == NULL)
+		    seginfo->fix_root = l->fixp;
+		  else
+		    prev->fx_next = l->fixp;
+
+		  break;
+		}
+
+	      prev = f;
+	    }
+
+	  if (f != NULL)
+	    break;
+
+	  if (pass == 1)
+	    as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
+			   _("Unmatched high relocation"));
+	}
+    }
+}
+
+/* See whether we need to force a relocation into the output file. */
+
+int
+mep_force_relocation (fixS *fixp)
+{
+  if (   fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+	 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+    return 1;
+
+  /* Allow branches to global symbols to be resolved at assembly time.
+     This is consistent with way relaxable branches are handled, since
+     branches to both global and local symbols are relaxed.  It also
+     corresponds to the assumptions made in md_pcrel_from_section.  */
+  return S_FORCE_RELOC (fixp->fx_addsy, !fixp->fx_pcrel);
+}
+
+/* Write a value out to the object file, using the appropriate endianness.  */
+
+void
+md_number_to_chars (char *buf, valueT val, int n)
+{
+  if (target_big_endian)
+    number_to_chars_bigendian (buf, val, n);
+  else
+    number_to_chars_littleendian (buf, val, n);
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type type, and store the appropriate bytes in *litP.  The number
+   of LITTLENUMS emitted is stored in *sizeP .  An error message is
+   returned, or NULL on OK. */
+
+/* Equal to MAX_PRECISION in atof-ieee.c */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int              i;
+  int              prec;
+  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
+  char *           t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+    /* FIXME: Some targets allow other format chars for bigger sizes here.  */
+    default:
+      *sizeP = 0;
+      return _("Bad call to md_atof()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  * sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+  for (i = 0; i < prec; i++)
+    {
+      md_number_to_chars (litP, (valueT) words[i],
+			  sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+
+  return 0;
+}
+
+
+bfd_boolean
+mep_fix_adjustable (fixS *fixP)
+{
+  bfd_reloc_code_real_type reloc_type;
+
+  if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+    {
+      const CGEN_INSN *insn = NULL;
+      int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
+      const CGEN_OPERAND *operand
+	= cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
+      reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+    }
+  else
+    reloc_type = fixP->fx_r_type;
+
+  if (fixP->fx_addsy == NULL)
+    return 1;
+
+  /* Prevent all adjustments to global symbols. */
+  if (S_IS_EXTERNAL (fixP->fx_addsy))
+    return 0;
+
+  if (S_IS_WEAK (fixP->fx_addsy))
+    return 0;
+
+  /* We need the symbol name for the VTABLE entries */
+  if (reloc_type == BFD_RELOC_VTABLE_INHERIT
+      || reloc_type == BFD_RELOC_VTABLE_ENTRY)
+    return 0;
+
+  return 1;
+}
+
+int
+mep_elf_section_letter (int letter, char **ptrmsg)
+{
+  if (letter == 'v')
+    return SHF_MEP_VLIW;
+
+  *ptrmsg = _("Bad .section directive: want a,v,w,x,M,S in string");
+  return 0;
+}
+
+flagword
+mep_elf_section_flags (flagword flags, int attr, int type ATTRIBUTE_UNUSED)
+{
+  if (attr & SHF_MEP_VLIW)
+    flags |= SEC_MEP_VLIW;
+  return flags;
+}
+
+/* In vliw mode, the default section is .vtext.  We have to be able
+   to switch into .vtext using only the .vtext directive.  */
+
+static segT
+mep_vtext_section (void)
+{
+  static segT vtext_section;
+
+  if (! vtext_section)
+    {
+      flagword applicable = bfd_applicable_section_flags (stdoutput);
+      vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
+      bfd_set_section_flags (stdoutput, vtext_section,
+			     applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
+					   | SEC_CODE | SEC_READONLY
+					   | SEC_MEP_VLIW));
+    }
+
+  return vtext_section;
+}
+
+static void
+mep_s_vtext (int ignore ATTRIBUTE_UNUSED)
+{
+  int temp;
+
+  /* Record previous_section and previous_subsection.  */
+  obj_elf_section_change_hook ();
+
+  temp = get_absolute_expression ();
+  subseg_set (mep_vtext_section (), (subsegT) temp);
+  demand_empty_rest_of_line ();
+}
+
+static void
+mep_switch_to_core_mode (int dummy ATTRIBUTE_UNUSED)
+{
+  mep_process_saved_insns ();
+  pluspresent = 0;
+  mode = CORE;
+}
+
+static void
+mep_switch_to_vliw_mode (int dummy ATTRIBUTE_UNUSED)
+{
+  if (! MEP_VLIW)
+    as_bad (_(".vliw unavailable when VLIW is disabled."));
+  mode = VLIW;
+  /* Switch into .vtext here too. */
+  /* mep_s_vtext(); */
+}
+
+/* This is an undocumented pseudo-op used to disable gas's
+   "disabled_registers" check.  Used for code which checks for those
+   registers at runtime.  */
+static void
+mep_noregerr (int i ATTRIBUTE_UNUSED)
+{
+  allow_disabled_registers = 1;
+}
+
+/* mep_unrecognized_line: This is called when a line that can't be parsed
+   is encountered.  We use it to check for a leading '+' sign which indicates
+   that the current instruction is a coprocessor instruction that is to be
+   parallelized with a previous core insn.  This function accepts the '+' and
+   rejects all other characters that might indicate garbage at the beginning
+   of the line.  The '+' character gets lost as the calling loop continues,
+   so we need to indicate that we saw it.  */
+
+int
+mep_unrecognized_line (int ch)
+{
+  switch (ch)
+    {
+    case '+':
+      pluspresent = 1;
+      return 1; /* '+' indicates an instruction to be parallelized. */
+    default:
+      return 0; /* If it's not a '+', the line can't be parsed. */
+    }
+}
+
+void
+mep_cleanup (void)
+{
+  /* Take care of any insns left to be parallelized when the file ends.
+     This is mainly here to handle the case where the file ends with an
+     insn preceeded by a + or the file ends unexpectedly.  */
+  if (mode == VLIW)
+    mep_process_saved_insns ();
+}
+
+int
+mep_flush_pending_output (void)
+{
+  if (mode == VLIW)
+    {
+      mep_process_saved_insns ();
+      pluspresent = 0;
+    }
+
+  return 1; 
+}
diff --git a/contrib/binutils/gas/config/tc-mep.h b/contrib/binutils/gas/config/tc-mep.h
new file mode 100644
index 0000000..1d48bd4
--- /dev/null
+++ b/contrib/binutils/gas/config/tc-mep.h
@@ -0,0 +1,119 @@
+/* tc-mep.h -- Header file for tc-mep.c.
+   Copyright (C) 2001, 2002, 2005 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA. */
+
+#define TC_MEP
+
+/* Support computed relocations.  */
+#define OBJ_COMPLEX_RELC
+
+/* Support many operands per instruction.  */
+#define GAS_CGEN_MAX_FIXUPS 10
+
+#define LISTING_HEADER "MEP GAS "
+
+/* The target BFD architecture.  */
+#define TARGET_ARCH bfd_arch_mep
+
+#define TARGET_FORMAT (target_big_endian ? "elf32-mep" : "elf32-mep-little")
+
+/* This is the default.  */
+#define TARGET_BYTES_BIG_ENDIAN 1
+
+/* Permit temporary numeric labels. */
+#define LOCAL_LABELS_FB 1
+
+/* .-foo gets turned into PC relative relocs.  */
+#define DIFF_EXPR_OK
+
+/* We don't need to handle .word strangely.  */
+#define WORKING_DOT_WORD
+
+/* Values passed to md_apply_fix don't include the symbol value.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+#define MD_APPLY_FIX
+#define md_apply_fix mep_apply_fix
+extern void mep_apply_fix (struct fix *, valueT *, segT);
+
+/* Call md_pcrel_from_section(), not md_pcrel_from().  */
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+#define tc_frob_file() mep_frob_file ()
+extern void mep_frob_file (void);
+
+#define tc_fix_adjustable(fixP) mep_fix_adjustable (fixP)
+extern bfd_boolean mep_fix_adjustable (struct fix *);
+
+/* After creating a fixup for an instruction operand, we need
+   to check for HI16 relocs and queue them up for later sorting.  */
+#define md_cgen_record_fixup_exp  mep_cgen_record_fixup_exp
+
+/* When relaxing, we need to emit various relocs we otherwise wouldn't.  */
+#define TC_FORCE_RELOCATION(fix) mep_force_relocation (fix)
+extern int mep_force_relocation (struct fix *);
+
+#define tc_gen_reloc gas_cgen_tc_gen_reloc
+
+extern void gas_cgen_md_operand (expressionS *);
+#define md_operand(x) gas_cgen_md_operand (x)
+
+#define md_flush_pending_output() mep_flush_pending_output()
+extern int mep_flush_pending_output(void);
+
+extern const struct relax_type md_relax_table[];
+#define TC_GENERIC_RELAX_TABLE md_relax_table
+
+/* Account for inserting a jmp after the insn.  */
+#define TC_CGEN_MAX_RELAX(insn, len) ((len) + 4)
+
+extern void mep_prepare_relax_scan (fragS *, offsetT *, relax_substateT);
+#define md_prepare_relax_scan(FRAGP, ADDR, AIM, STATE, TYPE) \
+	mep_prepare_relax_scan (FRAGP, &AIM, STATE)
+
+#define skip_whitespace(str) while (*(str) == ' ') ++(str)
+
+/* Support for core/vliw mode switching.  */
+#define CORE 0
+#define VLIW 1
+#define MAX_PARALLEL_INSNS 56 /* From email from Toshiba.  */
+#define VTEXT_SECTION_NAME ".vtext"
+
+/* Needed to process pending instructions when a label is encountered.  */
+#define TC_START_LABEL(ch, ptr)    ((ch == ':') && mep_flush_pending_output ())
+
+#define tc_unrecognized_line(c) mep_unrecognized_line (c)
+extern int mep_unrecognized_line (int);
+#define md_cleanup mep_cleanup
+extern void mep_cleanup (void);
+
+#define md_elf_section_letter		mep_elf_section_letter
+extern int mep_elf_section_letter (int, char **);
+#define md_elf_section_flags		mep_elf_section_flags
+extern flagword mep_elf_section_flags  (flagword, int, int);
+
+#define ELF_TC_SPECIAL_SECTIONS \
+  { VTEXT_SECTION_NAME, SHT_PROGBITS, SHF_ALLOC|SHF_EXECINSTR|SHF_MEP_VLIW },
+
+/* The values of the following enum are for use with parinsnum, which 
+   is a variable in md_assemble that keeps track of whether or not the
+   next instruction is expected to be the first or second instrucion in
+   a parallelization group.  */
+typedef enum exp_par_insn_{FIRST, SECOND} EXP_PAR_INSN;
diff --git a/contrib/binutils/gas/config/tc-mips.c b/contrib/binutils/gas/config/tc-mips.c
index dc5ff68..e97193f 100644
--- a/contrib/binutils/gas/config/tc-mips.c
+++ b/contrib/binutils/gas/config/tc-mips.c
@@ -1,6 +1,6 @@
 /* tc-mips.c -- assemble code for a MIPS chip.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005 Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006 Free Software Foundation, Inc.
    Contributed by the OSF and Ralph Campbell.
    Written by Keith Knowles and Ralph Campbell, working independently.
    Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
@@ -28,8 +28,6 @@
 #include "subsegs.h"
 #include "safe-ctype.h"
 
-#include <stdarg.h>
-
 #include "opcode/mips.h"
 #include "itbl-ops.h"
 #include "dwarf2dbg.h"
@@ -169,7 +167,7 @@ struct mips_cl_insn
   /* True if this entry cannot be moved from its current position.  */
   unsigned int fixed_p : 1;
 
-  /* True if this instruction occured in a .set noreorder block.  */
+  /* True if this instruction occurred in a .set noreorder block.  */
   unsigned int noreorder_p : 1;
 
   /* True for mips16 instructions that jump to an absolute address.  */
@@ -212,7 +210,9 @@ struct mips_set_options
      command line options, and based on the default architecture.  */
   int ase_mips3d;
   int ase_mdmx;
+  int ase_smartmips;
   int ase_dsp;
+  int ase_dspr2;
   int ase_mt;
   /* Whether we are assembling for the mips16 processor.  0 if we are
      not, 1 if we are, and -1 if the value has not been initialized.
@@ -264,7 +264,7 @@ static int file_mips_fp32 = -1;
 
 static struct mips_set_options mips_opts =
 {
-  ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
+  ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
 };
 
 /* These variables are filled in with the masks of registers used.
@@ -280,6 +280,11 @@ static int file_mips_isa = ISA_UNKNOWN;
    command line (e.g., by -march).  */
 static int file_ase_mips16;
 
+#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32		\
+			      || mips_opts.isa == ISA_MIPS32R2		\
+			      || mips_opts.isa == ISA_MIPS64		\
+			      || mips_opts.isa == ISA_MIPS64R2)
+
 /* True if -mips3d was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_mips3d;
@@ -288,14 +293,36 @@ static int file_ase_mips3d;
    command line (e.g., by -march).  */
 static int file_ase_mdmx;
 
+/* True if -msmartmips was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_smartmips;
+
+#define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32		\
+				|| mips_opts.isa == ISA_MIPS32R2)
+
 /* True if -mdsp was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_dsp;
 
+#define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2		\
+			      || mips_opts.isa == ISA_MIPS64R2)
+
+#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
+
+/* True if -mdspr2 was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_dspr2;
+
+#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2		\
+			        || mips_opts.isa == ISA_MIPS64R2)
+
 /* True if -mmt was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_mt;
 
+#define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2		\
+			     || mips_opts.isa == ISA_MIPS64R2)
+
 /* The argument of the -march= flag.  The architecture we are assembling.  */
 static int file_mips_arch = CPU_UNKNOWN;
 static const char *mips_arch_string;
@@ -312,47 +339,66 @@ static int mips_32bitmode = 0;
 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
 
 /* Likewise 64-bit registers.  */
-#define ABI_NEEDS_64BIT_REGS(ABI) \
-  ((ABI) == N32_ABI 		  \
-   || (ABI) == N64_ABI		  \
+#define ABI_NEEDS_64BIT_REGS(ABI)	\
+  ((ABI) == N32_ABI 			\
+   || (ABI) == N64_ABI			\
    || (ABI) == O64_ABI)
 
-/*  Return true if ISA supports 64 bit gp register instructions.  */
-#define ISA_HAS_64BIT_REGS(ISA) (    \
-   (ISA) == ISA_MIPS3                \
-   || (ISA) == ISA_MIPS4             \
-   || (ISA) == ISA_MIPS5             \
-   || (ISA) == ISA_MIPS64            \
-   || (ISA) == ISA_MIPS64R2          \
-   )
+/*  Return true if ISA supports 64 bit wide gp registers.  */
+#define ISA_HAS_64BIT_REGS(ISA)		\
+  ((ISA) == ISA_MIPS3			\
+   || (ISA) == ISA_MIPS4		\
+   || (ISA) == ISA_MIPS5		\
+   || (ISA) == ISA_MIPS64		\
+   || (ISA) == ISA_MIPS64R2)
+
+/*  Return true if ISA supports 64 bit wide float registers.  */
+#define ISA_HAS_64BIT_FPRS(ISA)		\
+  ((ISA) == ISA_MIPS3			\
+   || (ISA) == ISA_MIPS4		\
+   || (ISA) == ISA_MIPS5		\
+   || (ISA) == ISA_MIPS32R2		\
+   || (ISA) == ISA_MIPS64		\
+   || (ISA) == ISA_MIPS64R2)
 
 /* Return true if ISA supports 64-bit right rotate (dror et al.)
    instructions.  */
-#define ISA_HAS_DROR(ISA) (	\
-   (ISA) == ISA_MIPS64R2	\
-   )
+#define ISA_HAS_DROR(ISA)		\
+  ((ISA) == ISA_MIPS64R2)
 
 /* Return true if ISA supports 32-bit right rotate (ror et al.)
    instructions.  */
-#define ISA_HAS_ROR(ISA) (	\
-   (ISA) == ISA_MIPS32R2	\
-   || (ISA) == ISA_MIPS64R2	\
-   )
+#define ISA_HAS_ROR(ISA)		\
+  ((ISA) == ISA_MIPS32R2		\
+   || (ISA) == ISA_MIPS64R2		\
+   || mips_opts.ase_smartmips)
 
 /* Return true if ISA supports ins instructions. */
-#define ISA_HAS_INS(ISA) ( \
-  (ISA) == ISA_MIPS32R2    \
-  || (ISA) == ISA_MIPS64R2 \
-  )
+#define ISA_HAS_INS(ISA)		\
+  ((ISA) == ISA_MIPS32R2		\
+  || (ISA) == ISA_MIPS64R2)
+
+/* Return true if ISA supports single-precision floats in odd registers.  */
+#define ISA_HAS_ODD_SINGLE_FPR(ISA)	\
+  ((ISA) == ISA_MIPS32			\
+   || (ISA) == ISA_MIPS32R2		\
+   || (ISA) == ISA_MIPS64		\
+   || (ISA) == ISA_MIPS64R2)
+
+/* Return true if ISA supports move to/from high part of a 64-bit
+   floating-point register. */
+#define ISA_HAS_MXHC1(ISA)		\
+  ((ISA) == ISA_MIPS32R2		\
+   || (ISA) == ISA_MIPS64R2)
 
 #define HAVE_32BIT_GPRS		                   \
-    (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+    (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
 
 #define HAVE_32BIT_FPRS                            \
-    (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+    (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
 
-#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
-#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
+#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
+#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
 
 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
 
@@ -392,22 +438,6 @@ static int mips_32bitmode = 0;
    (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0		\
     || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
 
-/* Return true if the given CPU supports the MIPS3D ASE.  */
-#define CPU_HAS_MIPS3D(cpu)	((cpu) == CPU_SB1      \
-				 )
-
-/* Return true if the given CPU supports the MDMX ASE.  */
-#define CPU_HAS_MDMX(cpu)	(FALSE                 \
-				 )
-
-/* Return true if the given CPU supports the DSP ASE.  */
-#define CPU_HAS_DSP(cpu)	(FALSE                 \
-				 )
-
-/* Return true if the given CPU supports the MT ASE.  */
-#define CPU_HAS_MT(cpu)		(FALSE                 \
-				 )
-
 /* True if CPU has a dror instruction.  */
 #define CPU_HAS_DROR(CPU)	((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
 
@@ -501,7 +531,7 @@ static int mips_any_noreorder;
    an mfhi/mflo instruction is read in the next two instructions.  */
 static int mips_7000_hilo_fix;
 
-/* The size of the small data section.  */
+/* The size of objects in the small data section.  */
 static unsigned int g_switch_value = 8;
 /* Whether the -G option was used.  */
 static int g_switch_seen = 0;
@@ -1018,6 +1048,8 @@ static void s_cpsetup (int);
 static void s_cplocal (int);
 static void s_cprestore (int);
 static void s_cpreturn (int);
+static void s_dtprelword (int);
+static void s_dtpreldword (int);
 static void s_gpvalue (int);
 static void s_gpword (int);
 static void s_gpdword (int);
@@ -1043,11 +1075,19 @@ static int validate_mips_insn (const struct mips_opcode *);
 struct mips_cpu_info
 {
   const char *name;           /* CPU or ISA name.  */
-  int is_isa;                 /* Is this an ISA?  (If 0, a CPU.) */
+  int flags;                  /* ASEs available, or ISA flag.  */
   int isa;                    /* ISA level.  */
   int cpu;                    /* CPU number (default CPU if ISA).  */
 };
 
+#define MIPS_CPU_IS_ISA		0x0001	/* Is this an ISA?  (If 0, a CPU.) */
+#define MIPS_CPU_ASE_SMARTMIPS	0x0002	/* CPU implements SmartMIPS ASE */
+#define MIPS_CPU_ASE_DSP	0x0004	/* CPU implements DSP ASE */
+#define MIPS_CPU_ASE_MT		0x0008	/* CPU implements MT ASE */
+#define MIPS_CPU_ASE_MIPS3D	0x0010	/* CPU implements MIPS-3D ASE */
+#define MIPS_CPU_ASE_MDMX	0x0020	/* CPU implements MDMX ASE */
+#define MIPS_CPU_ASE_DSPR2	0x0040	/* CPU implements DSP R2 ASE */
+
 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
@@ -1067,8 +1107,7 @@ static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
    The following pseudo-ops from the Kane and Heinrich MIPS book are
    not MIPS CPU specific, but are also not specific to the object file
    format.  This file is probably the best place to define them, but
-   they are not currently supported: .asm0, .endr, .lab, .repeat,
-   .struct.  */
+   they are not currently supported: .asm0, .endr, .lab, .struct.  */
 
 static const pseudo_typeS mips_pseudo_table[] =
 {
@@ -1084,6 +1123,8 @@ static const pseudo_typeS mips_pseudo_table[] =
   {"cplocal", s_cplocal, 0},
   {"cprestore", s_cprestore, 0},
   {"cpreturn", s_cpreturn, 0},
+  {"dtprelword", s_dtprelword, 0},
+  {"dtpreldword", s_dtpreldword, 0},
   {"gpvalue", s_gpvalue, 0},
   {"gpword", s_gpword, 0},
   {"gpdword", s_gpdword, 0},
@@ -1098,6 +1139,8 @@ static const pseudo_typeS mips_pseudo_table[] =
   {"half", s_cons, 1},
   {"dword", s_cons, 3},
   {"weakext", s_mips_weakext, 0},
+  {"origin", s_org, 0},
+  {"repeat", s_rept, 0},
 
   /* These pseudo-ops are defined in read.c, but must be overridden
      here for one reason or another.  */
@@ -1161,8 +1204,8 @@ struct insn_label_list
   symbolS *label;
 };
 
-static struct insn_label_list *insn_labels;
 static struct insn_label_list *free_insn_labels;
+#define label_list tc_segment_info_data
 
 static void mips_clear_insn_labels (void);
 
@@ -1170,12 +1213,19 @@ static inline void
 mips_clear_insn_labels (void)
 {
   register struct insn_label_list **pl;
+  segment_info_type *si;
 
-  for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
-    ;
-  *pl = insn_labels;
-  insn_labels = NULL;
+  if (now_seg)
+    {
+      for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
+	;
+      
+      si = seg_info (now_seg);
+      *pl = si->label_list;
+      si->label_list = NULL;
+    }
 }
+
 
 static char *expr_end;
 
@@ -1418,13 +1468,302 @@ init_vr4120_conflicts (void)
 #undef CONFLICT
 }
 
-/* This function is called once, at assembler startup time.  It should
-   set up all the tables, etc. that the MD part of the assembler will need.  */
+struct regname {
+  const char *name;
+  unsigned int num;
+};
+
+#define RTYPE_MASK	0x1ff00
+#define RTYPE_NUM	0x00100
+#define RTYPE_FPU	0x00200
+#define RTYPE_FCC	0x00400
+#define RTYPE_VEC	0x00800
+#define RTYPE_GP	0x01000
+#define RTYPE_CP0	0x02000
+#define RTYPE_PC	0x04000
+#define RTYPE_ACC	0x08000
+#define RTYPE_CCC	0x10000
+#define RNUM_MASK	0x000ff
+#define RWARN		0x80000
+
+#define GENERIC_REGISTER_NUMBERS \
+    {"$0",	RTYPE_NUM | 0},  \
+    {"$1",	RTYPE_NUM | 1},  \
+    {"$2",	RTYPE_NUM | 2},  \
+    {"$3",	RTYPE_NUM | 3},  \
+    {"$4",	RTYPE_NUM | 4},  \
+    {"$5",	RTYPE_NUM | 5},  \
+    {"$6",	RTYPE_NUM | 6},  \
+    {"$7",	RTYPE_NUM | 7},  \
+    {"$8",	RTYPE_NUM | 8},  \
+    {"$9",	RTYPE_NUM | 9},  \
+    {"$10",	RTYPE_NUM | 10}, \
+    {"$11",	RTYPE_NUM | 11}, \
+    {"$12",	RTYPE_NUM | 12}, \
+    {"$13",	RTYPE_NUM | 13}, \
+    {"$14",	RTYPE_NUM | 14}, \
+    {"$15",	RTYPE_NUM | 15}, \
+    {"$16",	RTYPE_NUM | 16}, \
+    {"$17",	RTYPE_NUM | 17}, \
+    {"$18",	RTYPE_NUM | 18}, \
+    {"$19",	RTYPE_NUM | 19}, \
+    {"$20",	RTYPE_NUM | 20}, \
+    {"$21",	RTYPE_NUM | 21}, \
+    {"$22",	RTYPE_NUM | 22}, \
+    {"$23",	RTYPE_NUM | 23}, \
+    {"$24",	RTYPE_NUM | 24}, \
+    {"$25",	RTYPE_NUM | 25}, \
+    {"$26",	RTYPE_NUM | 26}, \
+    {"$27",	RTYPE_NUM | 27}, \
+    {"$28",	RTYPE_NUM | 28}, \
+    {"$29",	RTYPE_NUM | 29}, \
+    {"$30",	RTYPE_NUM | 30}, \
+    {"$31",	RTYPE_NUM | 31} 
+
+#define FPU_REGISTER_NAMES       \
+    {"$f0",	RTYPE_FPU | 0},  \
+    {"$f1",	RTYPE_FPU | 1},  \
+    {"$f2",	RTYPE_FPU | 2},  \
+    {"$f3",	RTYPE_FPU | 3},  \
+    {"$f4",	RTYPE_FPU | 4},  \
+    {"$f5",	RTYPE_FPU | 5},  \
+    {"$f6",	RTYPE_FPU | 6},  \
+    {"$f7",	RTYPE_FPU | 7},  \
+    {"$f8",	RTYPE_FPU | 8},  \
+    {"$f9",	RTYPE_FPU | 9},  \
+    {"$f10",	RTYPE_FPU | 10}, \
+    {"$f11",	RTYPE_FPU | 11}, \
+    {"$f12",	RTYPE_FPU | 12}, \
+    {"$f13",	RTYPE_FPU | 13}, \
+    {"$f14",	RTYPE_FPU | 14}, \
+    {"$f15",	RTYPE_FPU | 15}, \
+    {"$f16",	RTYPE_FPU | 16}, \
+    {"$f17",	RTYPE_FPU | 17}, \
+    {"$f18",	RTYPE_FPU | 18}, \
+    {"$f19",	RTYPE_FPU | 19}, \
+    {"$f20",	RTYPE_FPU | 20}, \
+    {"$f21",	RTYPE_FPU | 21}, \
+    {"$f22",	RTYPE_FPU | 22}, \
+    {"$f23",	RTYPE_FPU | 23}, \
+    {"$f24",	RTYPE_FPU | 24}, \
+    {"$f25",	RTYPE_FPU | 25}, \
+    {"$f26",	RTYPE_FPU | 26}, \
+    {"$f27",	RTYPE_FPU | 27}, \
+    {"$f28",	RTYPE_FPU | 28}, \
+    {"$f29",	RTYPE_FPU | 29}, \
+    {"$f30",	RTYPE_FPU | 30}, \
+    {"$f31",	RTYPE_FPU | 31}
+
+#define FPU_CONDITION_CODE_NAMES \
+    {"$fcc0",	RTYPE_FCC | 0},  \
+    {"$fcc1",	RTYPE_FCC | 1},  \
+    {"$fcc2",	RTYPE_FCC | 2},  \
+    {"$fcc3",	RTYPE_FCC | 3},  \
+    {"$fcc4",	RTYPE_FCC | 4},  \
+    {"$fcc5",	RTYPE_FCC | 5},  \
+    {"$fcc6",	RTYPE_FCC | 6},  \
+    {"$fcc7",	RTYPE_FCC | 7}
+
+#define COPROC_CONDITION_CODE_NAMES         \
+    {"$cc0",	RTYPE_FCC | RTYPE_CCC | 0}, \
+    {"$cc1",	RTYPE_FCC | RTYPE_CCC | 1}, \
+    {"$cc2",	RTYPE_FCC | RTYPE_CCC | 2}, \
+    {"$cc3",	RTYPE_FCC | RTYPE_CCC | 3}, \
+    {"$cc4",	RTYPE_FCC | RTYPE_CCC | 4}, \
+    {"$cc5",	RTYPE_FCC | RTYPE_CCC | 5}, \
+    {"$cc6",	RTYPE_FCC | RTYPE_CCC | 6}, \
+    {"$cc7",	RTYPE_FCC | RTYPE_CCC | 7}
+
+#define N32N64_SYMBOLIC_REGISTER_NAMES \
+    {"$a4",	RTYPE_GP | 8},  \
+    {"$a5",	RTYPE_GP | 9},  \
+    {"$a6",	RTYPE_GP | 10}, \
+    {"$a7",	RTYPE_GP | 11}, \
+    {"$ta0",	RTYPE_GP | 8},  /* alias for $a4 */ \
+    {"$ta1",	RTYPE_GP | 9},  /* alias for $a5 */ \
+    {"$ta2",	RTYPE_GP | 10}, /* alias for $a6 */ \
+    {"$ta3",	RTYPE_GP | 11}, /* alias for $a7 */ \
+    {"$t0",	RTYPE_GP | 12}, \
+    {"$t1",	RTYPE_GP | 13}, \
+    {"$t2",	RTYPE_GP | 14}, \
+    {"$t3",	RTYPE_GP | 15}
+
+#define O32_SYMBOLIC_REGISTER_NAMES \
+    {"$t0",	RTYPE_GP | 8},  \
+    {"$t1",	RTYPE_GP | 9},  \
+    {"$t2",	RTYPE_GP | 10}, \
+    {"$t3",	RTYPE_GP | 11}, \
+    {"$t4",	RTYPE_GP | 12}, \
+    {"$t5",	RTYPE_GP | 13}, \
+    {"$t6",	RTYPE_GP | 14}, \
+    {"$t7",	RTYPE_GP | 15}, \
+    {"$ta0",	RTYPE_GP | 12}, /* alias for $t4 */ \
+    {"$ta1",	RTYPE_GP | 13}, /* alias for $t5 */ \
+    {"$ta2",	RTYPE_GP | 14}, /* alias for $t6 */ \
+    {"$ta3",	RTYPE_GP | 15}  /* alias for $t7 */ 
+
+/* Remaining symbolic register names */
+#define SYMBOLIC_REGISTER_NAMES \
+    {"$zero",	RTYPE_GP | 0},  \
+    {"$at",	RTYPE_GP | 1},  \
+    {"$AT",	RTYPE_GP | 1},  \
+    {"$v0",	RTYPE_GP | 2},  \
+    {"$v1",	RTYPE_GP | 3},  \
+    {"$a0",	RTYPE_GP | 4},  \
+    {"$a1",	RTYPE_GP | 5},  \
+    {"$a2",	RTYPE_GP | 6},  \
+    {"$a3",	RTYPE_GP | 7},  \
+    {"$s0",	RTYPE_GP | 16}, \
+    {"$s1",	RTYPE_GP | 17}, \
+    {"$s2",	RTYPE_GP | 18}, \
+    {"$s3",	RTYPE_GP | 19}, \
+    {"$s4",	RTYPE_GP | 20}, \
+    {"$s5",	RTYPE_GP | 21}, \
+    {"$s6",	RTYPE_GP | 22}, \
+    {"$s7",	RTYPE_GP | 23}, \
+    {"$t8",	RTYPE_GP | 24}, \
+    {"$t9",	RTYPE_GP | 25}, \
+    {"$k0",	RTYPE_GP | 26}, \
+    {"$kt0",	RTYPE_GP | 26}, \
+    {"$k1",	RTYPE_GP | 27}, \
+    {"$kt1",	RTYPE_GP | 27}, \
+    {"$gp",	RTYPE_GP | 28}, \
+    {"$sp",	RTYPE_GP | 29}, \
+    {"$s8",	RTYPE_GP | 30}, \
+    {"$fp",	RTYPE_GP | 30}, \
+    {"$ra",	RTYPE_GP | 31}
+
+#define MIPS16_SPECIAL_REGISTER_NAMES \
+    {"$pc",	RTYPE_PC | 0}
+
+#define MDMX_VECTOR_REGISTER_NAMES \
+    /* {"$v0",	RTYPE_VEC | 0},  clash with REG 2 above */ \
+    /* {"$v1",	RTYPE_VEC | 1},  clash with REG 3 above */ \
+    {"$v2",	RTYPE_VEC | 2},  \
+    {"$v3",	RTYPE_VEC | 3},  \
+    {"$v4",	RTYPE_VEC | 4},  \
+    {"$v5",	RTYPE_VEC | 5},  \
+    {"$v6",	RTYPE_VEC | 6},  \
+    {"$v7",	RTYPE_VEC | 7},  \
+    {"$v8",	RTYPE_VEC | 8},  \
+    {"$v9",	RTYPE_VEC | 9},  \
+    {"$v10",	RTYPE_VEC | 10}, \
+    {"$v11",	RTYPE_VEC | 11}, \
+    {"$v12",	RTYPE_VEC | 12}, \
+    {"$v13",	RTYPE_VEC | 13}, \
+    {"$v14",	RTYPE_VEC | 14}, \
+    {"$v15",	RTYPE_VEC | 15}, \
+    {"$v16",	RTYPE_VEC | 16}, \
+    {"$v17",	RTYPE_VEC | 17}, \
+    {"$v18",	RTYPE_VEC | 18}, \
+    {"$v19",	RTYPE_VEC | 19}, \
+    {"$v20",	RTYPE_VEC | 20}, \
+    {"$v21",	RTYPE_VEC | 21}, \
+    {"$v22",	RTYPE_VEC | 22}, \
+    {"$v23",	RTYPE_VEC | 23}, \
+    {"$v24",	RTYPE_VEC | 24}, \
+    {"$v25",	RTYPE_VEC | 25}, \
+    {"$v26",	RTYPE_VEC | 26}, \
+    {"$v27",	RTYPE_VEC | 27}, \
+    {"$v28",	RTYPE_VEC | 28}, \
+    {"$v29",	RTYPE_VEC | 29}, \
+    {"$v30",	RTYPE_VEC | 30}, \
+    {"$v31",	RTYPE_VEC | 31}
+
+#define MIPS_DSP_ACCUMULATOR_NAMES \
+    {"$ac0",	RTYPE_ACC | 0}, \
+    {"$ac1",	RTYPE_ACC | 1}, \
+    {"$ac2",	RTYPE_ACC | 2}, \
+    {"$ac3",	RTYPE_ACC | 3}
+
+static const struct regname reg_names[] = {
+  GENERIC_REGISTER_NUMBERS,
+  FPU_REGISTER_NAMES,
+  FPU_CONDITION_CODE_NAMES,
+  COPROC_CONDITION_CODE_NAMES,
+
+  /* The $txx registers depends on the abi,
+     these will be added later into the symbol table from
+     one of the tables below once mips_abi is set after 
+     parsing of arguments from the command line. */
+  SYMBOLIC_REGISTER_NAMES,
+
+  MIPS16_SPECIAL_REGISTER_NAMES,
+  MDMX_VECTOR_REGISTER_NAMES,
+  MIPS_DSP_ACCUMULATOR_NAMES,
+  {0, 0}
+};
+
+static const struct regname reg_names_o32[] = {
+  O32_SYMBOLIC_REGISTER_NAMES,
+  {0, 0}
+};
+
+static const struct regname reg_names_n32n64[] = {
+  N32N64_SYMBOLIC_REGISTER_NAMES,
+  {0, 0}
+};
+
+static int
+reg_lookup (char **s, unsigned int types, unsigned int *regnop)
+{
+  symbolS *symbolP;
+  char *e;
+  char save_c;
+  int reg = -1;
+
+  /* Find end of name.  */
+  e = *s;
+  if (is_name_beginner (*e))
+    ++e;
+  while (is_part_of_name (*e))
+    ++e;
+
+  /* Terminate name.  */
+  save_c = *e;
+  *e = '\0';
+
+  /* Look for a register symbol.  */
+  if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
+    {
+      int r = S_GET_VALUE (symbolP);
+      if (r & types)
+	reg = r & RNUM_MASK;
+      else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
+	/* Convert GP reg $v0/1 to MDMX reg $v0/1!  */
+	reg = (r & RNUM_MASK) - 2;
+    }
+  /* Else see if this is a register defined in an itbl entry.  */
+  else if ((types & RTYPE_GP) && itbl_have_entries)
+    {
+      char *n = *s;
+      unsigned long r;
+
+      if (*n == '$')
+	++n;
+      if (itbl_get_reg_val (n, &r))
+	reg = r & RNUM_MASK;
+    }
+
+  /* Advance to next token if a register was recognised.  */
+  if (reg >= 0)
+    *s = e;
+  else if (types & RWARN)
+    as_warn ("Unrecognized register name `%s'", *s);
+
+  *e = save_c;
+  if (regnop)
+    *regnop = reg;
+  return reg >= 0;
+}
+
+/* This function is called once, at assembler startup time.  It should set up
+   all the tables, etc. that the MD part of the assembler will need.  */
 
 void
 md_begin (void)
 {
-  register const char *retval = NULL;
+  const char *retval = NULL;
   int i = 0;
   int broken = 0;
 
@@ -1506,46 +1845,20 @@ md_begin (void)
 
   /* We add all the general register names to the symbol table.  This
      helps us detect invalid uses of them.  */
-  for (i = 0; i < 32; i++)
-    {
-      char buf[5];
-
-      sprintf (buf, "$%d", i);
-      symbol_table_insert (symbol_new (buf, reg_section, i,
+  for (i = 0; reg_names[i].name; i++) 
+    symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
+				     reg_names[i].num, // & RNUM_MASK,
+				     &zero_address_frag));
+  if (HAVE_NEWABI)
+    for (i = 0; reg_names_n32n64[i].name; i++) 
+      symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
+				       reg_names_n32n64[i].num, // & RNUM_MASK,
 				       &zero_address_frag));
-    }
-  symbol_table_insert (symbol_new ("$ra", reg_section, RA,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$fp", reg_section, FP,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$sp", reg_section, SP,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$gp", reg_section, GP,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$at", reg_section, AT,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$pc", reg_section, -1,
-				   &zero_address_frag));
-
-  /* If we don't add these register names to the symbol table, they
-     may end up being added as regular symbols by operand(), and then
-     make it to the object file as undefined in case they're not
-     regarded as local symbols.  They're local in o32, since `$' is a
-     local symbol prefix, but not in n32 or n64.  */
-  for (i = 0; i < 8; i++)
-    {
-      char buf[6];
-
-      sprintf (buf, "$fcc%i", i);
-      symbol_table_insert (symbol_new (buf, reg_section, -1,
+  else
+    for (i = 0; reg_names_o32[i].name; i++) 
+      symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
+				       reg_names_o32[i].num, // & RNUM_MASK,
 				       &zero_address_frag));
-    }
 
   mips_no_prev_insn ();
 
@@ -1560,7 +1873,8 @@ md_begin (void)
 
   bfd_set_gp_size (stdoutput, g_switch_value);
 
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+#ifdef OBJ_ELF
+  if (IS_ELF)
     {
       /* On a native system other than VxWorks, sections must be aligned
 	 to 16 byte boundaries.  When configured for an embedded ELF
@@ -1598,9 +1912,7 @@ md_begin (void)
 	    bfd_set_section_flags (stdoutput, sec, flags);
 	    bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
 
-#ifdef OBJ_ELF
 	    mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
-#endif
 	  }
 	else
 	  {
@@ -1610,7 +1922,6 @@ md_begin (void)
 	    bfd_set_section_flags (stdoutput, sec, flags);
 	    bfd_set_section_alignment (stdoutput, sec, 3);
 
-#ifdef OBJ_ELF
 	    /* Set up the option header.  */
 	    {
 	      Elf_Internal_Options opthdr;
@@ -1627,7 +1938,6 @@ md_begin (void)
 
 	      mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
 	    }
-#endif
 	  }
 
 	if (ECOFF_DEBUGGING)
@@ -1637,8 +1947,7 @@ md_begin (void)
 					  SEC_HAS_CONTENTS | SEC_READONLY);
 	    (void) bfd_set_section_alignment (stdoutput, sec, 2);
 	  }
-#ifdef OBJ_ELF
-	else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
+	else if (mips_flag_pdr)
 	  {
 	    pdr_seg = subseg_new (".pdr", (subsegT) 0);
 	    (void) bfd_set_section_flags (stdoutput, pdr_seg,
@@ -1646,11 +1955,11 @@ md_begin (void)
 					  | SEC_DEBUGGING);
 	    (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
 	  }
-#endif
 
 	subseg_set (seg, subseg);
       }
     }
+#endif /* OBJ_ELF */
 
   if (! ECOFF_DEBUGGING)
     md_obj_begin ();
@@ -1849,10 +2158,11 @@ reg_needs_delay (unsigned int reg)
 static void
 mips_move_labels (void)
 {
+  segment_info_type *si = seg_info (now_seg);
   struct insn_label_list *l;
   valueT val;
 
-  for (l = insn_labels; l != NULL; l = l->next)
+  for (l = si->label_list; l != NULL; l = l->next)
     {
       assert (S_GET_SEGMENT (l->label) == now_seg);
       symbol_set_frag (l->label, frag_now);
@@ -1864,6 +2174,28 @@ mips_move_labels (void)
     }
 }
 
+static bfd_boolean
+s_is_linkonce (symbolS *sym, segT from_seg)
+{
+  bfd_boolean linkonce = FALSE;
+  segT symseg = S_GET_SEGMENT (sym);
+
+  if (symseg != from_seg && !S_IS_LOCAL (sym))
+    {
+      if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
+	linkonce = TRUE;
+#ifdef OBJ_ELF
+      /* The GNU toolchain uses an extension for ELF: a section
+	 beginning with the magic string .gnu.linkonce is a
+	 linkonce section.  */
+      if (strncmp (segment_name (symseg), ".gnu.linkonce",
+		   sizeof ".gnu.linkonce" - 1) == 0)
+	linkonce = TRUE;
+#endif
+    }
+  return linkonce;
+}
+
 /* Mark instruction labels in mips16 mode.  This permits the linker to
    handle them specially, such as generating jalx instructions when
    needed.  We also make them odd for the duration of the assembly, in
@@ -1875,21 +2207,29 @@ mips_move_labels (void)
 static void
 mips16_mark_labels (void)
 {
-  if (mips_opts.mips16)
-    {
-      struct insn_label_list *l;
-      valueT val;
+  segment_info_type *si = seg_info (now_seg);
+  struct insn_label_list *l;
 
-      for (l = insn_labels; l != NULL; l = l->next)
-	{
-#ifdef OBJ_ELF
-	  if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	    S_SET_OTHER (l->label, STO_MIPS16);
+  if (!mips_opts.mips16)
+    return;
+
+  for (l = si->label_list; l != NULL; l = l->next)
+   {
+      symbolS *label = l->label;
+
+#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
+      if (IS_ELF)
+	S_SET_OTHER (label, STO_MIPS16);
 #endif
-	  val = S_GET_VALUE (l->label);
-	  if ((val & 1) == 0)
-	    S_SET_VALUE (l->label, val + 1);
-	}
+      if ((S_GET_VALUE (label) & 1) == 0
+	/* Don't adjust the address if the label is global or weak, or
+	   in a link-once section, since we'll be emitting symbol reloc
+	   references to it which will be patched up by the linker, and
+	   the final value of the symbol may or may not be MIPS16.  */
+	  && ! S_IS_WEAK (label)
+	  && ! S_IS_EXTERNAL (label)
+	  && ! s_is_linkonce (label, now_seg))
+	S_SET_VALUE (label, S_GET_VALUE (label) | 1);
     }
 }
 
@@ -2214,9 +2554,10 @@ static void
 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	     bfd_reloc_code_real_type *reloc_type)
 {
-  register unsigned long prev_pinfo, pinfo;
+  unsigned long prev_pinfo, pinfo;
   relax_stateT prev_insn_frag_type = 0;
   bfd_boolean relaxed_branch = FALSE;
+  segment_info_type *si = seg_info (now_seg);
 
   /* Mark instruction labels in mips16 mode.  */
   mips16_mark_labels ();
@@ -2479,6 +2820,11 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 				     reloc_type[0] == BFD_RELOC_16_PCREL_S2,
 				     reloc_type[0]);
 
+	  /* Tag symbols that have a R_MIPS16_26 relocation against them.  */
+	  if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
+	      && ip->fixp[0]->fx_addsy)
+	    *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
+
 	  /* These relocations can have an addend that won't fit in
 	     4 octets for 64bit assembly.  */
 	  if (HAVE_64BIT_GPRS
@@ -2633,7 +2979,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 		 whether there is a label on this instruction.  If
 		 there are any branches to anything other than a
 		 label, users must use .set noreorder.  */
-	      || insn_labels != NULL
+	      || si->label_list != NULL
 	      /* If the previous instruction is in a variant frag
 		 other than this branch's one, we cannot do the swap.
 		 This does not apply to the mips16, which uses variant
@@ -2740,10 +3086,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      if (mips_opts.mips16
 		  && (pinfo & INSN_UNCOND_BRANCH_DELAY)
 		  && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
-		  && (mips_opts.isa == ISA_MIPS32
-		      || mips_opts.isa == ISA_MIPS32R2
-		      || mips_opts.isa == ISA_MIPS64
-		      || mips_opts.isa == ISA_MIPS64R2))
+		  && ISA_SUPPORTS_MIPS16E)
 		{
 		  /* Convert MIPS16 jr/jalr into a "compact" jump.  */
 		  ip->insn_opcode |= 0x0080;
@@ -3025,16 +3368,24 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
   assert (mo);
   assert (strcmp (name, mo->name) == 0);
 
-  /* Search until we get a match for NAME.  It is assumed here that
-     macros will never generate MDMX or MIPS-3D instructions.  */
-  while (strcmp (fmt, mo->args) != 0
-	 || mo->pinfo == INSN_MACRO
-	 || !OPCODE_IS_MEMBER (mo,
+  while (1)
+    {
+      /* Search until we get a match for NAME.  It is assumed here that
+	 macros will never generate MDMX, MIPS-3D, or MT instructions.  */
+      if (strcmp (fmt, mo->args) == 0
+	  && mo->pinfo != INSN_MACRO
+	  && OPCODE_IS_MEMBER (mo,
 			       (mips_opts.isa
-				| (file_ase_mips16 ? INSN_MIPS16 : 0)),
+				| (mips_opts.mips16 ? INSN_MIPS16 : 0)
+				| (mips_opts.ase_dsp ? INSN_DSP : 0)
+				| ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
+				   ? INSN_DSP64 : 0)
+				| (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
+				| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
 			       mips_opts.arch)
-	 || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
-    {
+	  && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0))
+	break;
+
       ++mo;
       assert (mo->name);
       assert (strcmp (name, mo->name) == 0);
@@ -3085,6 +3436,10 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	    }
 	  continue;
 
+	case '2':
+	  INSERT_OPERAND (BP, insn, va_arg (args, int));
+	  continue;
+
 	case 't':
 	case 'w':
 	case 'E':
@@ -3212,7 +3567,11 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	  continue;
 
 	case 'C':
-	  insn.insn_opcode |= va_arg (args, unsigned long);
+	  INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
+	  continue;
+
+	case 'k':
+	  INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
 	  continue;
 
 	default:
@@ -3296,7 +3655,7 @@ mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
 
 	    regno = va_arg (args, int);
 	    regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
-	    insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
+	    MIPS16_INSERT_OPERAND (REG32R, insn, regno);
 	  }
 	  continue;
 
@@ -3412,7 +3771,7 @@ macro_build_lui (expressionS *ep, int regnum)
 
   if (high_expr.X_op == O_constant)
     {
-      /* we can compute the instruction now without a relocation entry */
+      /* We can compute the instruction now without a relocation entry.  */
       high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
 				>> 16) & 0xffff;
       *r = BFD_RELOC_UNUSED;
@@ -4189,7 +4548,7 @@ add_got_offset_hilo (int dest, expressionS *local, int tmp)
 static void
 macro (struct mips_cl_insn *ip)
 {
-  register int treg, sreg, dreg, breg;
+  int treg, sreg, dreg, breg;
   int tempreg;
   int mask;
   int used_at = 0;
@@ -4309,6 +4668,22 @@ macro (struct mips_cl_insn *ip)
       macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
       break;
 
+    case M_BALIGN:
+      switch (imm_expr.X_add_number)
+	{
+	case 0:
+	  macro_build (NULL, "nop", "");
+	  break;
+	case 2:
+	  macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
+	  break;
+	default:
+	  macro_build (NULL, "balign", "t,s,2", treg, sreg,
+		       (int)imm_expr.X_add_number);
+	  break;
+	}
+      break;
+
     case M_BEQ_I:
       s = "beq";
       goto beq_i;
@@ -5849,6 +6224,9 @@ macro (struct mips_cl_insn *ip)
     case M_SCD_AB:
       s = "scd";
       goto st;
+    case M_CACHE_AB:
+      s = "cache";
+      goto st;
     case M_SDC1_AB:
       if (mips_opts.arch == CPU_R4650)
 	{
@@ -5895,6 +6273,8 @@ macro (struct mips_cl_insn *ip)
 	  || mask == M_L_DAB
 	  || mask == M_S_DAB)
 	fmt = "T,o(b)";
+      else if (mask == M_CACHE_AB)
+	fmt = "k,o(b)";
       else if (coproc)
 	fmt = "E,o(b)";
       else
@@ -6854,7 +7234,7 @@ macro (struct mips_cl_insn *ip)
 static void
 macro2 (struct mips_cl_insn *ip)
 {
-  register int treg, sreg, dreg, breg;
+  int treg, sreg, dreg, breg;
   int tempreg;
   int mask;
   int used_at;
@@ -7990,6 +8370,10 @@ validate_mips_insn (const struct mips_opcode *opc)
       case '+':
     	switch (c = *p++)
 	  {
+	  case '1': USE_BITS (OP_MASK_UDI1,     OP_SH_UDI1); 	break;
+	  case '2': USE_BITS (OP_MASK_UDI2,	OP_SH_UDI2); 	break;
+	  case '3': USE_BITS (OP_MASK_UDI3,	OP_SH_UDI3); 	break;
+	  case '4': USE_BITS (OP_MASK_UDI4,	OP_SH_UDI4); 	break;
 	  case 'A': USE_BITS (OP_MASK_SHAMT,	OP_SH_SHAMT);	break;
 	  case 'B': USE_BITS (OP_MASK_INSMSB,	OP_SH_INSMSB);	break;
 	  case 'C': USE_BITS (OP_MASK_EXTMSBD,	OP_SH_EXTMSBD);	break;
@@ -8065,6 +8449,7 @@ validate_mips_insn (const struct mips_opcode *opc)
       case '%': USE_BITS (OP_MASK_VECALIGN,	OP_SH_VECALIGN); break;
       case '[': break;
       case ']': break;
+      case '2': USE_BITS (OP_MASK_BP,		OP_SH_BP);	break;
       case '3': USE_BITS (OP_MASK_SA3,  	OP_SH_SA3);	break;
       case '4': USE_BITS (OP_MASK_SA4,  	OP_SH_SA4);	break;
       case '5': USE_BITS (OP_MASK_IMM8, 	OP_SH_IMM8);	break;
@@ -8096,6 +8481,62 @@ validate_mips_insn (const struct mips_opcode *opc)
   return 1;
 }
 
+/* UDI immediates.  */
+struct mips_immed {
+  char		type;
+  unsigned int	shift;
+  unsigned long	mask;
+  const char *	desc;
+};
+
+static const struct mips_immed mips_immed[] = {
+  { '1',	OP_SH_UDI1,	OP_MASK_UDI1,		0},
+  { '2',	OP_SH_UDI2,	OP_MASK_UDI2,		0},
+  { '3',	OP_SH_UDI3,	OP_MASK_UDI3,		0},
+  { '4',	OP_SH_UDI4,	OP_MASK_UDI4,		0},
+  { 0,0,0,0 }
+};
+
+/* Check whether an odd floating-point register is allowed.  */
+static int
+mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
+{
+  const char *s = insn->name;
+
+  if (insn->pinfo == INSN_MACRO)
+    /* Let a macro pass, we'll catch it later when it is expanded.  */
+    return 1;
+
+  if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
+    {
+      /* Allow odd registers for single-precision ops.  */
+      switch (insn->pinfo & (FP_S | FP_D))
+	{
+	case FP_S:
+	case 0:
+	  return 1;	/* both single precision - ok */
+	case FP_D:
+	  return 0;	/* both double precision - fail */
+	default:
+	  break;
+	}
+
+      /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand.  */
+      s = strchr (insn->name, '.');
+      if (argnum == 2)
+	s = s != NULL ? strchr (s + 1, '.') : NULL;
+      return (s != NULL && (s[1] == 'w' || s[1] == 's'));
+    } 
+
+  /* Single-precision coprocessor loads and moves are OK too.  */
+  if ((insn->pinfo & FP_S)
+      && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
+			 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
+    return 1;
+
+  return 0;
+}
+
 /* This routine assembles an instruction into its binary format.  As a
    side effect, it sets one of the global variables imm_reloc or
    offset_reloc to the type of relocation to do if one of the operands
@@ -8116,6 +8557,8 @@ mips_ip (char *str, struct mips_cl_insn *ip)
   char *s_reset;
   char save_c = 0;
   offsetT min_range, max_range;
+  int argnum;
+  unsigned int rtype;
 
   insn_error = NULL;
 
@@ -8176,11 +8619,18 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 
       if (OPCODE_IS_MEMBER (insn,
 			    (mips_opts.isa
+			     /* We don't check for mips_opts.mips16 here since
+			        we want to allow jalx if -mips16 was specified
+			        on the command line.  */
 			     | (file_ase_mips16 ? INSN_MIPS16 : 0)
 	      		     | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
 	      		     | (mips_opts.ase_dsp ? INSN_DSP : 0)
+	      		     | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
+				? INSN_DSP64 : 0)
+	      		     | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
 	      		     | (mips_opts.ase_mt ? INSN_MT : 0)
-			     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
+			     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
+			     | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
 			    mips_opts.arch))
 	ok = TRUE;
       else
@@ -8295,6 +8745,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 
       create_insn (ip, insn);
       insn_error = NULL;
+      argnum = 1;
       for (args = insn->args;; ++args)
 	{
 	  int is_mdmx;
@@ -8308,16 +8759,29 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		return;
 	      break;
 
+	    case '2': /* dsp 2-bit unsigned immediate in bit 11 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if ((unsigned long) imm_expr.X_add_number != 1
+		  && (unsigned long) imm_expr.X_add_number != 3)
+		{
+		  as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
+			  (unsigned long) imm_expr.X_add_number);
+		}
+	      INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
 	    case '3': /* dsp 3-bit unsigned immediate in bit 21 */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_SA3)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_SA3;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3;
+	      INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8327,11 +8791,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_SA4)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_SA4;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4;
+	      INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8341,11 +8804,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_IMM8)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_IMM8;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8;
+	      INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8355,11 +8817,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_RS)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_RS;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS;
+	      INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8370,7 +8831,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		{
 		  regno = s[3] - '0';
 		  s += 4;
-		  ip->insn_opcode |= regno << OP_SH_DSPACC;
+		  INSERT_OPERAND (DSPACC, *ip, regno);
 		  continue;
 		}
 	      else
@@ -8382,12 +8843,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_WRDSP,
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_WRDSP;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_WRDSP,
+			  (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP;
+	      INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8398,7 +8858,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		{
 		  regno = s[3] - '0';
 		  s += 4;
-		  ip->insn_opcode |= regno << OP_SH_DSPACC_S;
+		  INSERT_OPERAND (DSPACC_S, *ip, regno);
 		  continue;
 		}
 	      else
@@ -8413,13 +8873,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      if (imm_expr.X_add_number < min_range ||
 		  imm_expr.X_add_number > max_range)
 		{
-		  as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
-			   (long) min_range, (long) max_range,
-			   (long) imm_expr.X_add_number);
+		  as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
+			  (long) min_range, (long) max_range,
+			  (long) imm_expr.X_add_number);
 		}
-	      imm_expr.X_add_number &= OP_MASK_DSPSFT;
-	      ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
-				  << OP_SH_DSPSFT);
+	      INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8429,12 +8887,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_RDDSP,
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_RDDSP;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_RDDSP,
+			  (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP;
+	      INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8447,13 +8904,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      if (imm_expr.X_add_number < min_range ||
 		  imm_expr.X_add_number > max_range)
 		{
-		  as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
-			   (long) min_range, (long) max_range,
-			   (long) imm_expr.X_add_number);
+		  as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
+			  (long) min_range, (long) max_range,
+			  (long) imm_expr.X_add_number);
 		}
-	      imm_expr.X_add_number &= OP_MASK_DSPSFT_7;
-	      ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
-				  << OP_SH_DSPSFT_7);
+	      INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8466,41 +8921,33 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      if (imm_expr.X_add_number < min_range ||
 		  imm_expr.X_add_number > max_range)
 		{
-		  as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
-			   (long) min_range, (long) max_range,
-			   (long) imm_expr.X_add_number);
+		  as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
+			  (long) min_range, (long) max_range,
+			  (long) imm_expr.X_add_number);
 		}
-	      imm_expr.X_add_number &= OP_MASK_IMM10;
-	      ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
-				  << OP_SH_IMM10);
+	      INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
 
-            case '!': /* mt 1-bit unsigned immediate in bit 5 */
+            case '!': /* MT usermode flag bit.  */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_MT_U)
-		{
-		  as_warn (_("MT immediate not in range 0..%d (%lu)"),
-			   OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_MT_U;
-		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
+		as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
+			(unsigned long) imm_expr.X_add_number);
+	      INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
 
-            case '$': /* mt 1-bit unsigned immediate in bit 4 */
+            case '$': /* MT load high flag bit.  */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_MT_H)
-		{
-		  as_warn (_("MT immediate not in range 0..%d (%lu)"),
-			   OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_MT_H;
-		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
+		as_bad (_("MT load high bit not 0 or 1 (%lu)"),
+			(unsigned long) imm_expr.X_add_number);
+	      INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8511,7 +8958,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		{
 		  regno = s[3] - '0';
 		  s += 4;
-		  ip->insn_opcode |= regno << OP_SH_MTACC_T;
+		  INSERT_OPERAND (MTACC_T, *ip, regno);
 		  continue;
 		}
 	      else
@@ -8524,7 +8971,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		{
 		  regno = s[3] - '0';
 		  s += 4;
-		  ip->insn_opcode |= regno << OP_SH_MTACC_D;
+		  INSERT_OPERAND (MTACC_D, *ip, regno);
 		  continue;
 		}
 	      else
@@ -8532,6 +8979,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      break;
 
 	    case ',':
+	      ++argnum;
 	      if (*s++ == *args)
 		continue;
 	      s--;
@@ -8577,6 +9025,34 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	    case '+':		/* Opcode extension character.  */
 	      switch (*++args)
 		{
+		case '1':	/* UDI immediates.  */
+		case '2':
+		case '3':
+		case '4':
+		  {
+		    const struct mips_immed *imm = mips_immed;
+
+		    while (imm->type && imm->type != *args)
+		      ++imm;
+		    if (! imm->type)
+		      internalError ();
+		    my_getExpression (&imm_expr, s);
+		    check_absolute_expr (ip, &imm_expr);
+		    if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
+		      {
+		        as_warn (_("Illegal %s number (%lu, 0x%lx)"),
+				 imm->desc ? imm->desc : ip->insn_mo->name,
+				 (unsigned long) imm_expr.X_add_number,
+				 (unsigned long) imm_expr.X_add_number);
+			      imm_expr.X_add_number &= imm->mask;
+		      }
+		    ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
+					<< imm->shift);
+		    imm_expr.X_op = O_absent;
+		    s = expr_end;
+		  }
+		  continue;
+		  
 		case 'A':		/* ins/ext position, becomes LSB.  */
 		  limlo = 0;
 		  limhi = 31;
@@ -8683,11 +9159,11 @@ do_msbd:
 		  s = expr_end;
 		  continue;
 
-		case 'T': /* Coprocessor register */
+		case 'T': /* Coprocessor register.  */
 		  /* +T is for disassembly only; never match.  */
 		  break;
 
-		case 't': /* Coprocessor register number */
+		case 't': /* Coprocessor register number.  */
 		  if (s[0] == '$' && ISDIGIT (s[1]))
 		    {
 		      ++s;
@@ -8703,7 +9179,7 @@ do_msbd:
 			as_bad (_("Invalid register number (%d)"), regno);
 		      else
 			{
-			  ip->insn_opcode |= regno << OP_SH_RT;
+			  INSERT_OPERAND (RT, *ip, regno);
 			  continue;
 			}
 		    }
@@ -8794,8 +9270,9 @@ do_msbd:
 	    case 'c':		/* break code */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
-	      if ((unsigned long) imm_expr.X_add_number > 1023)
-		as_warn (_("Illegal break code (%lu)"),
+	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
+		as_warn (_("Code for %s not in range 0..1023 (%lu)"),
+			 ip->insn_mo->name,
 			 (unsigned long) imm_expr.X_add_number);
 	      INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
@@ -8805,8 +9282,9 @@ do_msbd:
 	    case 'q':		/* lower break code */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
-	      if ((unsigned long) imm_expr.X_add_number > 1023)
-		as_warn (_("Illegal lower break code (%lu)"),
+	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
+		as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
+			 ip->insn_mo->name,
 			 (unsigned long) imm_expr.X_add_number);
 	      INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
@@ -8834,7 +9312,8 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
-		as_warn (_("Illegal 20-bit code (%lu)"),
+		as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
+			 ip->insn_mo->name,
 			 (unsigned long) imm_expr.X_add_number);
 	      INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
@@ -8844,13 +9323,13 @@ do_msbd:
 	    case 'C':           /* Coprocessor code */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
-	      if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
+	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
 		{
 		  as_warn (_("Coproccesor code > 25 bits (%lu)"),
 			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= ((1 << 25) - 1);
+		  imm_expr.X_add_number &= OP_MASK_COPZ;
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number;
+	      INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8859,14 +9338,17 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
-		as_warn (_("Illegal 19-bit code (%lu)"),
-			 (unsigned long) imm_expr.X_add_number);
+		{
+		  as_warn (_("Illegal 19-bit code (%lu)"),
+			   (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_CODE19;
+		}
 	      INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
 
-	    case 'P':		/* Performance register */
+	    case 'P':		/* Performance register.  */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
@@ -8877,6 +9359,20 @@ do_msbd:
 	      s = expr_end;
 	      continue;
 
+	    case 'G':		/* Coprocessor destination register.  */
+	      if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
+		ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, &regno);
+	      else
+		ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
+	      INSERT_OPERAND (RD, *ip, regno);
+	      if (ok) 
+		{
+		  lastregno = regno;
+		  continue;
+		}
+	      else
+		break;
+
 	    case 'b':		/* base register */
 	    case 'd':		/* destination register */
 	    case 's':		/* source register */
@@ -8885,106 +9381,22 @@ do_msbd:
 	    case 'v':		/* both dest and source */
 	    case 'w':		/* both dest and target */
 	    case 'E':		/* coprocessor target register */
-	    case 'G':		/* coprocessor destination register */
 	    case 'K':		/* 'rdhwr' destination register */
 	    case 'x':		/* ignore register name */
 	    case 'z':		/* must be zero register */
 	    case 'U':           /* destination register (clo/clz).  */
 	    case 'g':		/* coprocessor destination register */
-	      s_reset = s;
-	      if (s[0] == '$')
+	      s_reset = s;	      
+	      if (*args == 'E' || *args == 'K')
+		ok = reg_lookup (&s, RTYPE_NUM, &regno);
+	      else
+		{
+		  ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
+		  if (regno == AT && ! mips_opts.noat)
+		    as_warn ("Used $at without \".set noat\"");
+		}
+	      if (ok)
 		{
-		  if (ISDIGIT (s[1]))
-		    {
-		      ++s;
-		      regno = 0;
-		      do
-			{
-			  regno *= 10;
-			  regno += *s - '0';
-			  ++s;
-			}
-		      while (ISDIGIT (*s));
-		      if (regno > 31)
-			as_bad (_("Invalid register number (%d)"), regno);
-		    }
-		  else if (*args == 'E' || *args == 'G' || *args == 'K')
-		    goto notreg;
-		  else
-		    {
-		      if (s[1] == 'r' && s[2] == 'a')
-			{
-			  s += 3;
-			  regno = RA;
-			}
-		      else if (s[1] == 'f' && s[2] == 'p')
-			{
-			  s += 3;
-			  regno = FP;
-			}
-		      else if (s[1] == 's' && s[2] == 'p')
-			{
-			  s += 3;
-			  regno = SP;
-			}
-		      else if (s[1] == 'g' && s[2] == 'p')
-			{
-			  s += 3;
-			  regno = GP;
-			}
-		      else if (s[1] == 'a' && s[2] == 't')
-			{
-			  s += 3;
-			  regno = AT;
-			}
-		      else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
-			{
-			  s += 4;
-			  regno = KT0;
-			}
-		      else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
-			{
-			  s += 4;
-			  regno = KT1;
-			}
-		      else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
-			{
-			  s += 5;
-			  regno = ZERO;
-			}
-		      else if (itbl_have_entries)
-			{
-			  char *p, *n;
-			  unsigned long r;
-
-			  p = s + 1; 	/* advance past '$' */
-			  n = itbl_get_field (&p);  /* n is name */
-
-			  /* See if this is a register defined in an
-			     itbl entry.  */
-			  if (itbl_get_reg_val (n, &r))
-			    {
-			      /* Get_field advances to the start of
-				 the next field, so we need to back
-				 rack to the end of the last field.  */
-			      if (p)
-				s = p - 1;
-			      else
-				s = strchr (s, '\0');
-			      regno = r;
-			    }
-			  else
-			    goto notreg;
-			}
-		      else
-			goto notreg;
-		    }
-		  if (regno == AT
-		      && ! mips_opts.noat
-		      && *args != 'E'
-		      && *args != 'G'
-		      && *args != 'K')
-		    as_warn (_("Used $at without \".set noat\""));
 		  c = *args;
 		  if (*s == ' ')
 		    ++s;
@@ -9050,7 +9462,6 @@ do_msbd:
 		  lastregno = regno;
 		  continue;
 		}
-	    notreg:
 	      switch (*args++)
 		{
 		case 'r':
@@ -9103,45 +9514,27 @@ do_msbd:
 	    case 'R':		/* floating point source register */
 	    case 'V':
 	    case 'W':
+	      rtype = RTYPE_FPU;
+	      if (is_mdmx
+		  || (mips_opts.ase_mdmx
+		      && (ip->insn_mo->pinfo & FP_D)
+		      && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
+						| INSN_COPROC_MEMORY_DELAY
+						| INSN_LOAD_COPROC_DELAY
+						| INSN_LOAD_MEMORY_DELAY
+						| INSN_STORE_MEMORY))))
+		rtype |= RTYPE_VEC;
 	      s_reset = s;
-             if (mips_opts.arch == CPU_OCTEON && octeon_error_on_unsupported)
-               {
-	         insn_error = "opcode not implemented in Octeon";
-                 return;
-               }
-	      /* Accept $fN for FP and MDMX register numbers, and in
-                 addition accept $vN for MDMX register numbers.  */
-	      if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
-		  || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
-		      && ISDIGIT (s[2])))
+	      if (mips_opts.arch == CPU_OCTEON && octeon_error_on_unsupported)
+		{
+		  insn_error = "opcode not implemented in Octeon";
+		  return;
+		}
+	      if (reg_lookup (&s, rtype, &regno))
 		{
-		  s += 2;
-		  regno = 0;
-		  do
-		    {
-		      regno *= 10;
-		      regno += *s - '0';
-		      ++s;
-		    }
-		  while (ISDIGIT (*s));
-
-		  if (regno > 31)
-		    as_bad (_("Invalid float register number (%d)"), regno);
-
 		  if ((regno & 1) != 0
 		      && HAVE_32BIT_FPRS
-		      && ! (strcmp (str, "mtc1") == 0
-			    || strcmp (str, "mfc1") == 0
-			    || strcmp (str, "lwc1") == 0
-			    || strcmp (str, "swc1") == 0
-			    || strcmp (str, "l.s") == 0
-			    || strcmp (str, "s.s") == 0
-			    || strcmp (str, "mftc1") == 0
-			    || strcmp (str, "mfthc1") == 0
-			    || strcmp (str, "cftc1") == 0
-			    || strcmp (str, "mttc1") == 0
-			    || strcmp (str, "mtthc1") == 0
-			    || strcmp (str, "cttc1") == 0))
+		      && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
 		    as_warn (_("Float register should be even, was %d"),
 			     regno);
 
@@ -9403,15 +9796,14 @@ do_msbd:
 			break;
 		      }
 		    new_seg = subseg_new (newname, (subsegT) 0);
-		    if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+		    if (IS_ELF)
 		      bfd_set_section_flags (stdoutput, new_seg,
 					     (SEC_ALLOC
 					      | SEC_LOAD
 					      | SEC_READONLY
 					      | SEC_DATA));
 		    frag_align (*args == 'l' ? 2 : 3, 0, 0);
-		    if (OUTPUT_FLAVOR == bfd_target_elf_flavour
-			&& strcmp (TARGET_OS, "elf") != 0)
+		    if (IS_ELF && strcmp (TARGET_OS, "elf") != 0)
 		      record_alignment (new_seg, 4);
 		    else
 		      record_alignment (new_seg, *args == 'l' ? 2 : 3);
@@ -9529,19 +9921,11 @@ do_msbd:
 
 	    case 'N':		/* 3 bit branch condition code */
 	    case 'M':		/* 3 bit compare condition code */
-	      if (strncmp (s, "$fcc", 4) != 0)
+	      rtype = RTYPE_CCC;
+	      if (ip->insn_mo->pinfo & (FP_D| FP_S))
+		rtype |= RTYPE_FCC;
+	      if (!reg_lookup (&s, rtype, &regno))
 		break;
-	      s += 4;
-	      regno = 0;
-	      do
-		{
-		  regno *= 10;
-		  regno += *s - '0';
-		  ++s;
-		}
-	      while (ISDIGIT (*s));
-	      if (regno > 7)
-		as_bad (_("Invalid condition code register $fcc%d"), regno);
 	      if ((strcmp(str + strlen(str) - 3, ".ps") == 0
 		   || strcmp(str + strlen(str) - 5, "any2f") == 0
 		   || strcmp(str + strlen(str) - 5, "any2t") == 0)
@@ -9708,8 +10092,38 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
   argsstart = s;
   for (;;)
     {
+      bfd_boolean ok;
+
       assert (strcmp (insn->name, str) == 0);
 
+      if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch))
+	ok = TRUE;
+      else
+	ok = FALSE;
+
+      if (! ok)
+	{
+	  if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
+	      && strcmp (insn->name, insn[1].name) == 0)
+	    {
+	      ++insn;
+	      continue;
+	    }
+	  else
+	    {
+	      if (!insn_error)
+		{
+		  static char buf[100];
+		  sprintf (buf,
+			   _("opcode not supported on this processor: %s (%s)"),
+			   mips_cpu_info_from_arch (mips_opts.arch)->name,
+			   mips_cpu_info_from_isa (mips_opts.isa)->name);
+		  insn_error = buf;
+		}
+	      return;
+	    }
+	}
+
       create_insn (ip, insn);
       imm_expr.X_op = O_absent;
       imm_reloc[0] = BFD_RELOC_UNUSED;
@@ -9822,70 +10236,19 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 	    case 'R':
 	    case 'X':
 	    case 'Y':
-	      if (s[0] != '$')
-		break;
-	      s_reset = s;
-	      if (ISDIGIT (s[1]))
-		{
-		  ++s;
-		  regno = 0;
-		  do
-		    {
-		      regno *= 10;
-		      regno += *s - '0';
-		      ++s;
-		    }
-		  while (ISDIGIT (*s));
-		  if (regno > 31)
-		    {
-		      as_bad (_("invalid register number (%d)"), regno);
-		      regno = 2;
-		    }
-		}
-	      else
+  	      s_reset = s;
+	      if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno))
 		{
-		  if (s[1] == 'r' && s[2] == 'a')
-		    {
-		      s += 3;
-		      regno = RA;
-		    }
-		  else if (s[1] == 'f' && s[2] == 'p')
-		    {
-		      s += 3;
-		      regno = FP;
-		    }
-		  else if (s[1] == 's' && s[2] == 'p')
-		    {
-		      s += 3;
-		      regno = SP;
-		    }
-		  else if (s[1] == 'g' && s[2] == 'p')
-		    {
-		      s += 3;
-		      regno = GP;
-		    }
-		  else if (s[1] == 'a' && s[2] == 't')
-		    {
-		      s += 3;
-		      regno = AT;
-		    }
-		  else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
-		    {
-		      s += 4;
-		      regno = KT0;
-		    }
-		  else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
-		    {
-		      s += 4;
-		      regno = KT1;
-		    }
-		  else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
+		  if (c == 'v' || c == 'w')
 		    {
-		      s += 5;
-		      regno = ZERO;
+		      if (c == 'v')
+			MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
+		      else
+			MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
+		      ++args;
+		      continue;
 		    }
-		  else
-		    break;
+		  break;
 		}
 
 	      if (*s == ' ')
@@ -10091,29 +10454,18 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 		  mask = 7 << 3;
 		while (*s != '\0')
 		  {
-		    int freg, reg1, reg2;
+		    unsigned int freg, reg1, reg2;
 
 		    while (*s == ' ' || *s == ',')
 		      ++s;
-		    if (*s != '$')
-		      {
-			as_bad (_("can't parse register list"));
-			break;
-		      }
-		    ++s;
-		    if (*s != 'f')
+		    if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
 		      freg = 0;
+		    else if (reg_lookup (&s, RTYPE_FPU, &reg1))
+		      freg = 1;
 		    else
 		      {
-			freg = 1;
-			++s;
-		      }
-		    reg1 = 0;
-		    while (ISDIGIT (*s))
-		      {
-			reg1 *= 10;
-			reg1 += *s - '0';
-			++s;
+			as_bad (_("can't parse register list"));
+			break;
 		      }
 		    if (*s == ' ')
 		      ++s;
@@ -10122,25 +10474,11 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 		    else
 		      {
 			++s;
-			if (*s != '$')
-			  break;
-			++s;
-			if (freg)
-			  {
-			    if (*s == 'f')
-			      ++s;
-			    else
-			      {
-				as_bad (_("invalid register list"));
-				break;
-			      }
-			  }
-			reg2 = 0;
-			while (ISDIGIT (*s))
+			if (!reg_lookup (&s, freg ? RTYPE_FPU 
+					 : (RTYPE_GP | RTYPE_NUM), &reg2))
 			  {
-			    reg2 *= 10;
-			    reg2 += *s - '0';
-			    ++s;
+			    as_bad (_("invalid register list"));
+			    break;
 			  }
 		      }
 		    if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
@@ -10205,46 +10543,33 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 			continue;
 		      }
 
-		    if (*s != '$')
+		    if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
 		      {
 			as_bad (_("can't parse register list"));
 			break;
 		      }
-		    ++s;
 
-		    reg1 = 0;
-		    while (ISDIGIT (*s))
-		      {
-			reg1 *= 10;
-			reg1 += *s - '0';
-			++s;
-		      }
-		    SKIP_SPACE_TABS (s);
+		    while (*s == ' ')
+		      ++s;
+
 		    if (*s != '-')
 		      reg2 = reg1;
 		    else
 		      {
 			++s;
-			if (*s != '$')
+			if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg2)
+			    || reg2 < reg1)
 			  {
 			    as_bad (_("can't parse register list"));
 			    break;
 			  }
-			++s;
-			reg2 = 0;
-			while (ISDIGIT (*s))
-			  {
-			    reg2 *= 10;
-			    reg2 += *s - '0';
-			    ++s;
-			  }
 		      }
 
 		    while (reg1 <= reg2)
 		      {
 			if (reg1 >= 4 && reg1 <= 7)
 			  {
-			    if (c == 'm' && !seen_framesz)
+			    if (!seen_framesz)
 				/* args $a0-$a3 */
 				args |= 1 << (reg1 - 4);
 			    else
@@ -10456,7 +10781,7 @@ mips16_immed (char *file, unsigned int line, int type, offsetT val,
 	      unsigned long *insn, bfd_boolean *use_extend,
 	      unsigned short *extend)
 {
-  register const struct mips16_immed_operand *op;
+  const struct mips16_immed_operand *op;
   int mintiny, maxtiny;
   bfd_boolean needext;
 
@@ -10866,9 +11191,17 @@ struct option md_longopts[] =
   {"mmt", no_argument, NULL, OPTION_MT},
 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
   {"mno-mt", no_argument, NULL, OPTION_NO_MT},
+#define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
+  {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
+#define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
+  {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
+#define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
+  {"mdspr2", no_argument, NULL, OPTION_DSPR2},
+#define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
+  {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
 
   /* Old-style architecture options.  Don't add more of these.  */
-#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
+#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
   {"m4650", no_argument, NULL, OPTION_M4650},
 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
@@ -11046,7 +11379,7 @@ md_parse_option (int c, char *arg)
       break;
 
     case 'O':
-      if (arg && arg[1] == '0')
+      if (arg && arg[0] == '0')
 	mips_optimize = 1;
       else
 	mips_optimize = 2;
@@ -11057,11 +11390,6 @@ md_parse_option (int c, char *arg)
 	mips_debug = 2;
       else
 	mips_debug = atoi (arg);
-      /* When the MIPS assembler sees -g or -g2, it does not do
-         optimizations which limit full symbolic debugging.  We take
-         that to be equivalent to -O0.  */
-      if (mips_debug == 2)
-	mips_optimize = 1;
       break;
 
     case OPTION_MIPS1:
@@ -11150,10 +11478,22 @@ md_parse_option (int c, char *arg)
 
     case OPTION_DSP:
       mips_opts.ase_dsp = 1;
+      mips_opts.ase_dspr2 = 0;
       break;
 
     case OPTION_NO_DSP:
       mips_opts.ase_dsp = 0;
+      mips_opts.ase_dspr2 = 0;
+      break;
+
+    case OPTION_DSPR2:
+      mips_opts.ase_dspr2 = 1;
+      mips_opts.ase_dsp = 1;
+      break;
+
+    case OPTION_NO_DSPR2:
+      mips_opts.ase_dspr2 = 0;
+      mips_opts.ase_dsp = 0;
       break;
 
     case OPTION_MT:
@@ -11182,6 +11522,14 @@ md_parse_option (int c, char *arg)
       mips_opts.ase_mips3d = 0;
       break;
 
+    case OPTION_SMARTMIPS:
+      mips_opts.ase_smartmips = 1;
+      break;
+
+    case OPTION_NO_SMARTMIPS:
+      mips_opts.ase_smartmips = 0;
+      break;
+
     case OPTION_FIX_VR4120:
       mips_fix_vr4120 = 1;
       break;
@@ -11227,7 +11575,7 @@ md_parse_option (int c, char *arg)
 	 select SVR4_PIC, and -non_shared to select no PIC.  This is
 	 intended to be compatible with Irix 5.  */
     case OPTION_CALL_SHARED:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-call_shared is supported only for ELF format"));
 	  return 0;
@@ -11237,7 +11585,7 @@ md_parse_option (int c, char *arg)
       break;
 
     case OPTION_NON_SHARED:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-non_shared is supported only for ELF format"));
 	  return 0;
@@ -11263,7 +11611,7 @@ md_parse_option (int c, char *arg)
       /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
 	 and -mabi=64.  */
     case OPTION_32:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-32 is supported for ELF format only"));
 	  return 0;
@@ -11272,7 +11620,7 @@ md_parse_option (int c, char *arg)
       break;
 
     case OPTION_N32:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-n32 is supported for ELF format only"));
 	  return 0;
@@ -11281,13 +11629,13 @@ md_parse_option (int c, char *arg)
       break;
 
     case OPTION_64:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-64 is supported for ELF format only"));
 	  return 0;
 	}
       mips_abi = N64_ABI;
-      if (! support_64bit_objects())
+      if (!support_64bit_objects())
 	as_fatal (_("No compiled in support for 64 bit object file format"));
       break;
 #endif /* OBJ_ELF */
@@ -11310,7 +11658,7 @@ md_parse_option (int c, char *arg)
 
 #ifdef OBJ_ELF
     case OPTION_MABI:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-mabi is supported for ELF format only"));
 	  return 0;
@@ -11482,14 +11830,43 @@ mips_after_parse_args (void)
 			|| !ISA_HAS_64BIT_REGS (mips_opts.isa));
     }
 
-  /* ??? GAS treats single-float processors as though they had 64-bit
-     float registers (although it complains when double-precision
-     instructions are used).  As things stand, saying they have 32-bit
-     registers would lead to spurious "register must be even" messages.
-     So here we assume float registers are always the same size as
-     integer ones, unless the user says otherwise.  */
-  if (file_mips_fp32 < 0)
-    file_mips_fp32 = file_mips_gp32;
+  switch (file_mips_fp32)
+    {
+    default:
+    case -1:
+      /* No user specified float register size.
+	 ??? GAS treats single-float processors as though they had 64-bit
+	 float registers (although it complains when double-precision
+	 instructions are used).  As things stand, saying they have 32-bit
+	 registers would lead to spurious "register must be even" messages.
+	 So here we assume float registers are never smaller than the
+	 integer ones.  */
+      if (file_mips_gp32 == 0)
+	/* 64-bit integer registers implies 64-bit float registers.  */
+	file_mips_fp32 = 0;
+      else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
+	       && ISA_HAS_64BIT_FPRS (mips_opts.isa))
+	/* -mips3d and -mdmx imply 64-bit float registers, if possible.  */
+	file_mips_fp32 = 0;
+      else
+	/* 32-bit float registers.  */
+	file_mips_fp32 = 1;
+      break;
+
+    /* The user specified the size of the float registers.  Check if it
+       agrees with the ABI and ISA.  */
+    case 0:
+      if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
+	as_bad (_("-mfp64 used with a 32-bit fpu"));
+      else if (ABI_NEEDS_32BIT_REGS (mips_abi)
+	       && !ISA_HAS_MXHC1 (mips_opts.isa))
+	as_warn (_("-mfp64 used with a 32-bit ABI"));
+      break;
+    case 1:
+      if (ABI_NEEDS_64BIT_REGS (mips_abi))
+	as_warn (_("-mfp32 used with a 64-bit ABI"));
+      break;
+    }
 
   /* End of GCC-shared inference code.  */
 
@@ -11508,19 +11885,51 @@ mips_after_parse_args (void)
   if (mips_opts.mips16 == -1)
     mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
   if (mips_opts.ase_mips3d == -1)
-    mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
+    mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
+			    && file_mips_fp32 == 0) ? 1 : 0;
+  if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
+    as_bad (_("-mfp32 used with -mips3d"));
+
   if (mips_opts.ase_mdmx == -1)
-    mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
+    mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
+			  && file_mips_fp32 == 0) ? 1 : 0;
+  if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
+    as_bad (_("-mfp32 used with -mdmx"));
+
+  if (mips_opts.ase_smartmips == -1)
+    mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
+  if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
+      as_warn ("%s ISA does not support SmartMIPS", 
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
+
   if (mips_opts.ase_dsp == -1)
-    mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
+    mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
+  if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
+      as_warn ("%s ISA does not support DSP ASE", 
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
+
+  if (mips_opts.ase_dspr2 == -1)
+    {
+      mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
+      mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
+    }
+  if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
+      as_warn ("%s ISA does not support DSP R2 ASE",
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
+
   if (mips_opts.ase_mt == -1)
-    mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
+    mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
+  if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
+      as_warn ("%s ISA does not support MT ASE",
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
 
   file_mips_isa = mips_opts.isa;
   file_ase_mips16 = mips_opts.mips16;
   file_ase_mips3d = mips_opts.ase_mips3d;
   file_ase_mdmx = mips_opts.ase_mdmx;
+  file_ase_smartmips = mips_opts.ase_smartmips;
   file_ase_dsp = mips_opts.ase_dsp;
+  file_ase_dspr2 = mips_opts.ase_dspr2;
   file_ase_mt = mips_opts.ase_mt;
   mips_opts.gp32 = file_mips_gp32;
   mips_opts.fp32 = file_mips_fp32;
@@ -11555,6 +11964,10 @@ md_pcrel_from (fixS *fixP)
       /* Return the address of the delay slot.  */
       return addr + 4;
     default:
+      /* We have no relocation type for PC relative MIPS16 instructions.  */
+      if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("PC relative MIPS16 instruction references a different section"));
       return addr;
     }
 }
@@ -11737,11 +12150,12 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	  || fixP->fx_r_type == BFD_RELOC_CTOR
 	  || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
 	  || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
-	  || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
+	  || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
+	  || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
 
   buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
 
-  assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
+  assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
 
   /* Don't treat parts of a composite relocation as done.  There are two
      reasons for this:
@@ -11753,13 +12167,15 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	 constants.  The easiest way of dealing with the pathological
 	 exceptions is to generate a relocation against STN_UNDEF and
 	 leave everything up to the linker.  */
-  if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0)
+  if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
     fixP->fx_done = 1;
 
   switch (fixP->fx_r_type)
     {
     case BFD_RELOC_MIPS_TLS_GD:
     case BFD_RELOC_MIPS_TLS_LDM:
+    case BFD_RELOC_MIPS_TLS_DTPREL32:
+    case BFD_RELOC_MIPS_TLS_DTPREL64:
     case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
     case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
     case BFD_RELOC_MIPS_TLS_GOTTPREL:
@@ -11798,14 +12214,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_MIPS16_GPREL:
     case BFD_RELOC_MIPS16_HI16:
     case BFD_RELOC_MIPS16_HI16_S:
-      /* Nothing needed to do. The value comes from the reloc entry */
-      break;
-
     case BFD_RELOC_MIPS16_JMP:
-      /* We currently always generate a reloc against a symbol, which
-         means that we don't want an addend even if the symbol is
-         defined.  */
-      *valP = 0;
+      /* Nothing needed to do.  The value comes from the reloc entry.  */
       break;
 
     case BFD_RELOC_64:
@@ -11833,18 +12243,12 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 
     case BFD_RELOC_RVA:
     case BFD_RELOC_32:
-      /* If we are deleting this reloc entry, we must fill in the
-	 value now.  This can happen if we have a .word which is not
-	 resolved when it appears but is later defined.   */
-      if (fixP->fx_done)
-	md_number_to_chars ((char *) buf, *valP, 4);
-      break;
-
     case BFD_RELOC_16:
       /* If we are deleting this reloc entry, we must fill in the
-         value now.  */
+	 value now.  This can happen if we have a .word which is not
+	 resolved when it appears but is later defined.  */
       if (fixP->fx_done)
-	md_number_to_chars ((char *) buf, *valP, 2);
+	md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
       break;
 
     case BFD_RELOC_LO16:
@@ -11869,15 +12273,13 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	as_bad_where (fixP->fx_file, fixP->fx_line,
 		      _("Branch to misaligned address (%lx)"), (long) *valP);
 
-      /*
-       * We need to save the bits in the instruction since fixup_segment()
-       * might be deleting the relocation entry (i.e., a branch within
-       * the current segment).
-       */
+      /* We need to save the bits in the instruction since fixup_segment()
+	 might be deleting the relocation entry (i.e., a branch within
+	 the current segment).  */
       if (! fixP->fx_done)
 	break;
 
-      /* update old instruction data */
+      /* Update old instruction data.  */
       if (target_big_endian)
 	insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
       else
@@ -11977,21 +12379,17 @@ mips_align (int to, int fill, symbolS *label)
 static void
 s_align (int x ATTRIBUTE_UNUSED)
 {
-  register int temp;
-  register long temp_fill;
+  int temp;
+  long temp_fill;
   long max_alignment = 15;
 
-  /*
-
-    o  Note that the assembler pulls down any immediately preceding label
+  /* o Note that the assembler pulls down any immediately preceding label
        to the aligned address.
-    o  It's not documented but auto alignment is reinstated by
+     o It's not documented but auto alignment is reinstated by
        a .align pseudo instruction.
-    o  Note also that after auto alignment is turned off the mips assembler
+     o Note also that after auto alignment is turned off the mips assembler
        issues an error on attempt to assemble an improperly aligned data item.
-       We don't.
-
-    */
+       We don't.  */
 
   temp = get_absolute_expression ();
   if (temp > max_alignment)
@@ -12010,9 +12408,11 @@ s_align (int x ATTRIBUTE_UNUSED)
     temp_fill = 0;
   if (temp)
     {
+      segment_info_type *si = seg_info (now_seg);
+      struct insn_label_list *l = si->label_list;
+      /* Auto alignment should be switched on by next section change.  */
       auto_align = 1;
-      mips_align (temp, (int) temp_fill,
-		  insn_labels != NULL ? insn_labels->label : NULL);
+      mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL);
     }
   else
     {
@@ -12034,7 +12434,8 @@ s_change_sec (int sec)
      as it would not be appropriate to use it in the section changing
      functions in read.c, since obj-elf.c intercepts those.  FIXME:
      This should be cleaner, somehow.  */
-  obj_elf_section_change_hook ();
+  if (IS_ELF)
+    obj_elf_section_change_hook ();
 #endif
 
   mips_emit_delays ();
@@ -12054,7 +12455,7 @@ s_change_sec (int sec)
     case 'r':
       seg = subseg_new (RDATA_SECTION_NAME,
 			(subsegT) get_absolute_expression ());
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+      if (IS_ELF)
 	{
 	  bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
 						  | SEC_READONLY | SEC_RELOC
@@ -12067,7 +12468,7 @@ s_change_sec (int sec)
 
     case 's':
       seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+      if (IS_ELF)
 	{
 	  bfd_set_section_flags (stdoutput, seg,
 				 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
@@ -12093,7 +12494,7 @@ s_change_section (int ignore ATTRIBUTE_UNUSED)
   int section_entry_size;
   int section_alignment;
 
-  if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+  if (!IS_ELF)
     return;
 
   section_name = input_line_pointer;
@@ -12138,7 +12539,7 @@ s_change_section (int ignore ATTRIBUTE_UNUSED)
 
      There's nothing really harmful in this, since bfd will correct
      SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file.  But it
-     means that, for backwards compatibiltiy, the special_section entries
+     means that, for backwards compatibility, the special_section entries
      for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
 
      Even so, we shouldn't force users of the MIPS .section syntax to
@@ -12165,9 +12566,11 @@ mips_enable_auto_align (void)
 static void
 s_cons (int log_size)
 {
+  segment_info_type *si = seg_info (now_seg);
+  struct insn_label_list *l = si->label_list;
   symbolS *label;
 
-  label = insn_labels != NULL ? insn_labels->label : NULL;
+  label = l != NULL ? l->label : NULL;
   mips_emit_delays ();
   if (log_size > 0 && auto_align)
     mips_align (log_size, 0, label);
@@ -12178,9 +12581,11 @@ s_cons (int log_size)
 static void
 s_float_cons (int type)
 {
+  segment_info_type *si = seg_info (now_seg);
+  struct insn_label_list *l = si->label_list;
   symbolS *label;
 
-  label = insn_labels != NULL ? insn_labels->label : NULL;
+  label = l != NULL ? l->label : NULL;
 
   mips_emit_delays ();
 
@@ -12367,12 +12772,43 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
     {
       mips_opts.nobopt = 1;
     }
+  else if (strcmp (name, "gp=default") == 0)
+    mips_opts.gp32 = file_mips_gp32;
+  else if (strcmp (name, "gp=32") == 0)
+    mips_opts.gp32 = 1;
+  else if (strcmp (name, "gp=64") == 0)
+    {
+      if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
+	as_warn ("%s isa does not support 64-bit registers",
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.gp32 = 0;
+    }
+  else if (strcmp (name, "fp=default") == 0)
+    mips_opts.fp32 = file_mips_fp32;
+  else if (strcmp (name, "fp=32") == 0)
+    mips_opts.fp32 = 1;
+  else if (strcmp (name, "fp=64") == 0)
+    {
+      if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
+	as_warn ("%s isa does not support 64-bit floating point registers",
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.fp32 = 0;
+    }
   else if (strcmp (name, "mips16") == 0
 	   || strcmp (name, "MIPS-16") == 0)
     mips_opts.mips16 = 1;
   else if (strcmp (name, "nomips16") == 0
 	   || strcmp (name, "noMIPS-16") == 0)
     mips_opts.mips16 = 0;
+  else if (strcmp (name, "smartmips") == 0)
+    {
+      if (!ISA_SUPPORTS_SMARTMIPS)
+	as_warn ("%s ISA does not support SmartMIPS ASE", 
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_smartmips = 1;
+    }
+  else if (strcmp (name, "nosmartmips") == 0)
+    mips_opts.ase_smartmips = 0;
   else if (strcmp (name, "mips3d") == 0)
     mips_opts.ase_mips3d = 1;
   else if (strcmp (name, "nomips3d") == 0)
@@ -12382,11 +12818,38 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
   else if (strcmp (name, "nomdmx") == 0)
     mips_opts.ase_mdmx = 0;
   else if (strcmp (name, "dsp") == 0)
-    mips_opts.ase_dsp = 1;
+    {
+      if (!ISA_SUPPORTS_DSP_ASE)
+	as_warn ("%s ISA does not support DSP ASE", 
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_dsp = 1;
+      mips_opts.ase_dspr2 = 0;
+    }
   else if (strcmp (name, "nodsp") == 0)
-    mips_opts.ase_dsp = 0;
+    {
+      mips_opts.ase_dsp = 0;
+      mips_opts.ase_dspr2 = 0;
+    }
+  else if (strcmp (name, "dspr2") == 0)
+    {
+      if (!ISA_SUPPORTS_DSPR2_ASE)
+	as_warn ("%s ISA does not support DSP R2 ASE",
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_dspr2 = 1;
+      mips_opts.ase_dsp = 1;
+    }
+  else if (strcmp (name, "nodspr2") == 0)
+    {
+      mips_opts.ase_dspr2 = 0;
+      mips_opts.ase_dsp = 0;
+    }
   else if (strcmp (name, "mt") == 0)
-    mips_opts.ase_mt = 1;
+    {
+      if (!ISA_SUPPORTS_MT_ASE)
+	as_warn ("%s ISA does not support MT ASE", 
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_mt = 1;
+    }
   else if (strcmp (name, "nomt") == 0)
     mips_opts.ase_mt = 0;
   else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
@@ -12497,6 +12960,14 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
     mips_opts.sym32 = TRUE;
   else if (strcmp (name, "nosym32") == 0)
     mips_opts.sym32 = FALSE;
+  else if (strchr (name, ','))
+    {
+      /* Generic ".set" directive; use the generic handler.  */
+      *input_line_pointer = ch;
+      input_line_pointer = name;
+      s_set (0);
+      return;
+    }
   else
     {
       as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
@@ -12604,8 +13075,7 @@ s_cpload (int ignore ATTRIBUTE_UNUSED)
 
    The -mno-shared option replaces the last three instructions with
 	lui	$gp,%hi(_gp)
-	addiu	$gp,$gp,%lo(_gp)
-   */
+	addiu	$gp,$gp,%lo(_gp)  */
 
 static void
 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
@@ -12707,7 +13177,7 @@ static void
 s_cplocal (int ignore ATTRIBUTE_UNUSED)
 {
   /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
-   .cplocal is ignored.  */
+     .cplocal is ignored.  */
   if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
     {
       s_ignore (0);
@@ -12756,8 +13226,8 @@ s_cprestore (int ignore ATTRIBUTE_UNUSED)
      ld		$gp, offset($sp)
 
    If a register $reg2 was given there, it results in:
-     daddu	$gp, $reg2, $0
- */
+     daddu	$gp, $reg2, $0  */
+
 static void
 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
 {
@@ -12789,6 +13259,52 @@ s_cpreturn (int ignore ATTRIBUTE_UNUSED)
   demand_empty_rest_of_line ();
 }
 
+/* Handle the .dtprelword and .dtpreldword pseudo-ops.  They generate
+   a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
+   use in DWARF debug information.  */
+
+static void
+s_dtprel_internal (size_t bytes)
+{
+  expressionS ex;
+  char *p;
+
+  expression (&ex);
+
+  if (ex.X_op != O_symbol)
+    {
+      as_bad (_("Unsupported use of %s"), (bytes == 8
+					   ? ".dtpreldword"
+					   : ".dtprelword"));
+      ignore_rest_of_line ();
+    }
+
+  p = frag_more (bytes);
+  md_number_to_chars (p, 0, bytes);
+  fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
+	       (bytes == 8
+		? BFD_RELOC_MIPS_TLS_DTPREL64
+		: BFD_RELOC_MIPS_TLS_DTPREL32));
+
+  demand_empty_rest_of_line ();
+}
+
+/* Handle .dtprelword.  */
+
+static void
+s_dtprelword (int ignore ATTRIBUTE_UNUSED)
+{
+  s_dtprel_internal (4);
+}
+
+/* Handle .dtpreldword.  */
+
+static void
+s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
+{
+  s_dtprel_internal (8);
+}
+
 /* Handle the .gpvalue pseudo-op.  This is used when generating NewABI PIC
    code.  It sets the offset to use in gp_rel relocations.  */
 
@@ -12814,6 +13330,8 @@ s_gpvalue (int ignore ATTRIBUTE_UNUSED)
 static void
 s_gpword (int ignore ATTRIBUTE_UNUSED)
 {
+  segment_info_type *si;
+  struct insn_label_list *l;
   symbolS *label;
   expressionS ex;
   char *p;
@@ -12825,7 +13343,9 @@ s_gpword (int ignore ATTRIBUTE_UNUSED)
       return;
     }
 
-  label = insn_labels != NULL ? insn_labels->label : NULL;
+  si = seg_info (now_seg);
+  l = si->label_list;
+  label = l != NULL ? l->label : NULL;
   mips_emit_delays ();
   if (auto_align)
     mips_align (2, 0, label);
@@ -12850,6 +13370,8 @@ s_gpword (int ignore ATTRIBUTE_UNUSED)
 static void
 s_gpdword (int ignore ATTRIBUTE_UNUSED)
 {
+  segment_info_type *si;
+  struct insn_label_list *l;
   symbolS *label;
   expressionS ex;
   char *p;
@@ -12861,7 +13383,9 @@ s_gpdword (int ignore ATTRIBUTE_UNUSED)
       return;
     }
 
-  label = insn_labels != NULL ? insn_labels->label : NULL;
+  si = seg_info (now_seg);
+  l = si->label_list;
+  label = l != NULL ? l->label : NULL;
   mips_emit_delays ();
   if (auto_align)
     mips_align (3, 0, label);
@@ -12943,8 +13467,7 @@ s_mips_stab (int type)
   s_stab (type);
 }
 
-/* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
- */
+/* Handle the .weakext pseudo-op as defined in Kane and Heinrich.  */
 
 static void
 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
@@ -12998,73 +13521,11 @@ s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
 int
 tc_get_register (int frame)
 {
-  int reg;
+  unsigned int reg;
 
   SKIP_WHITESPACE ();
-  if (*input_line_pointer++ != '$')
-    {
-      as_warn (_("expected `$'"));
-      reg = ZERO;
-    }
-  else if (ISDIGIT (*input_line_pointer))
-    {
-      reg = get_absolute_expression ();
-      if (reg < 0 || reg >= 32)
-	{
-	  as_warn (_("Bad register number"));
-	  reg = ZERO;
-	}
-    }
-  else
-    {
-      if (strncmp (input_line_pointer, "ra", 2) == 0)
-	{
-	  reg = RA;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "fp", 2) == 0)
-	{
-	  reg = FP;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "sp", 2) == 0)
-	{
-	  reg = SP;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "gp", 2) == 0)
-	{
-	  reg = GP;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "at", 2) == 0)
-	{
-	  reg = AT;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "kt0", 3) == 0)
-	{
-	  reg = KT0;
-	  input_line_pointer += 3;
-	}
-      else if (strncmp (input_line_pointer, "kt1", 3) == 0)
-	{
-	  reg = KT1;
-	  input_line_pointer += 3;
-	}
-      else if (strncmp (input_line_pointer, "zero", 4) == 0)
-	{
-	  reg = ZERO;
-	  input_line_pointer += 4;
-	}
-      else
-	{
-	  as_warn (_("Unrecognized register name"));
-	  reg = ZERO;
-	  while (ISALNUM(*input_line_pointer))
-	   input_line_pointer++;
-	}
-    }
+  if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
+    reg = 0;
   if (frame)
     {
       mips_frame_reg = reg != 0 ? reg : SP;
@@ -13079,16 +13540,17 @@ md_section_align (asection *seg, valueT addr)
 {
   int align = bfd_get_section_alignment (stdoutput, seg);
 
-#ifdef OBJ_ELF
-  /* We don't need to align ELF sections to the full alignment.
-     However, Irix 5 may prefer that we align them at least to a 16
-     byte boundary.  We don't bother to align the sections if we are
-     targeted for an embedded system.  */
-  if (strcmp (TARGET_OS, "elf") == 0)
-    return addr;
-  if (align > 4)
-    align = 4;
-#endif
+  if (IS_ELF)
+    {
+      /* We don't need to align ELF sections to the full alignment.
+	 However, Irix 5 may prefer that we align them at least to a 16
+	 byte boundary.  We don't bother to align the sections if we
+	 are targeted for an embedded system.  */
+      if (strcmp (TARGET_OS, "elf") == 0)
+        return addr;
+      if (align > 4)
+        align = 4;
+    }
 
   return ((addr + (1 << align) - 1) & (-1 << align));
 }
@@ -13154,6 +13616,8 @@ nopic_need_relax (symbolS *sym, int before_relaxing)
 	  change = (strcmp (segname, ".sdata") != 0
 		    && strcmp (segname, ".sbss") != 0
 		    && strncmp (segname, ".sdata.", 7) != 0
+		    && strncmp (segname, ".sbss.", 6) != 0
+		    && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
 		    && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
 	}
       return change;
@@ -13170,48 +13634,32 @@ static bfd_boolean
 pic_need_relax (symbolS *sym, asection *segtype)
 {
   asection *symsec;
-  bfd_boolean linkonce;
 
   /* Handle the case of a symbol equated to another symbol.  */
   while (symbol_equated_reloc_p (sym))
     {
       symbolS *n;
 
-      /* It's possible to get a loop here in a badly written
-	 program.  */
+      /* It's possible to get a loop here in a badly written program.  */
       n = symbol_get_value_expression (sym)->X_add_symbol;
       if (n == sym)
 	break;
       sym = n;
     }
 
-  symsec = S_GET_SEGMENT (sym);
-
-  /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
-  linkonce = FALSE;
-  if (symsec != segtype && ! S_IS_LOCAL (sym))
-    {
-      if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
-	  != 0)
-	linkonce = TRUE;
+  if (symbol_section_p (sym))
+    return TRUE;
 
-      /* The GNU toolchain uses an extension for ELF: a section
-	 beginning with the magic string .gnu.linkonce is a linkonce
-	 section.  */
-      if (strncmp (segment_name (symsec), ".gnu.linkonce",
-		   sizeof ".gnu.linkonce" - 1) == 0)
-	linkonce = TRUE;
-    }
+  symsec = S_GET_SEGMENT (sym);
 
   /* This must duplicate the test in adjust_reloc_syms.  */
   return (symsec != &bfd_und_section
 	  && symsec != &bfd_abs_section
-	  && ! bfd_is_com_section (symsec)
-	  && !linkonce
+	  && !bfd_is_com_section (symsec)
+	  && !s_is_linkonce (sym, segtype)
 #ifdef OBJ_ELF
 	  /* A global or weak symbol is treated as external.  */
-	  && (OUTPUT_FLAVOR != bfd_target_elf_flavour
-	      || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
+	  && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
 #endif
 	  );
 }
@@ -13224,7 +13672,7 @@ static int
 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
 {
   int type;
-  register const struct mips16_immed_operand *op;
+  const struct mips16_immed_operand *op;
   offsetT val;
   int mintiny, maxtiny;
   segT symsec;
@@ -13527,11 +13975,6 @@ md_estimate_size_before_relax (fragS *fragp, asection *segtype)
 int
 mips_fix_adjustable (fixS *fixp)
 {
-  /* Don't adjust MIPS16 jump relocations, so we don't have to worry
-     about the format of the offset in the .o file. */
-  if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
-    return 0;
-
   if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
     return 0;
@@ -13561,11 +14004,50 @@ mips_fix_adjustable (fixS *fixp)
     return 0;
 
 #ifdef OBJ_ELF
-  /* Don't adjust relocations against mips16 symbols, so that the linker
-     can find them if it needs to set up a stub.  */
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour
-      && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
-      && fixp->fx_subsy == NULL)
+  /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
+     to a floating-point stub.  The same is true for non-R_MIPS16_26
+     relocations against MIPS16 functions; in this case, the stub becomes
+     the function's canonical address.
+
+     Floating-point stubs are stored in unique .mips16.call.* or
+     .mips16.fn.* sections.  If a stub T for function F is in section S,
+     the first relocation in section S must be against F; this is how the
+     linker determines the target function.  All relocations that might
+     resolve to T must also be against F.  We therefore have the following
+     restrictions, which are given in an intentionally-redundant way:
+
+       1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
+	  symbols.
+
+       2. We cannot reduce a stub's relocations against non-MIPS16 symbols
+	  if that stub might be used.
+
+       3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
+	  symbols.
+
+       4. We cannot reduce a stub's relocations against MIPS16 symbols if
+	  that stub might be used.
+
+     There is a further restriction:
+
+       5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
+	  on targets with in-place addends; the relocation field cannot
+	  encode the low bit.
+
+     For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
+     against a MIPS16 symbol.
+
+     We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
+     relocation against some symbol R, no relocation against R may be
+     reduced.  (Note that this deals with (2) as well as (1) because
+     relocations against global symbols will never be reduced on ELF
+     targets.)  This approach is a little simpler than trying to detect
+     stub sections, and gives the "all or nothing" per-symbol consistency
+     that we have for MIPS16 symbols.  */
+  if (IS_ELF
+      && fixp->fx_subsy == NULL
+      && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
+	  || *symbol_get_tc (fixp->fx_addsy)))
     return 0;
 #endif
 
@@ -13595,7 +14077,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
       /* At this point, fx_addnumber is "symbol offset - pcrel address".
 	 Relocations want only the symbol offset.  */
       reloc->addend = fixp->fx_addnumber + reloc->address;
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  /* A gruesome hack which is a result of the gruesome gas
 	     reloc handling.  What's worse, for COFF (as opposed to
@@ -13694,7 +14176,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	  exp.X_add_number = fragp->fr_offset;
 
 	  fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-			      4, &exp, 1, BFD_RELOC_16_PCREL_S2);
+			      4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
 	  fixp->fx_file = fragp->fr_file;
 	  fixp->fx_line = fragp->fr_line;
 
@@ -13726,14 +14208,14 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 
 		case 0:
 		  /* bltz	0x04000000	bgez	0x04010000
-		     bltzal	0x04100000	bgezal	0x04110000 */
+		     bltzal	0x04100000	bgezal	0x04110000  */
 		  assert ((insn & 0xfc0e0000) == 0x04000000);
 		  insn ^= 0x00010000;
 		  break;
 
 		case 1:
 		  /* beq	0x10000000	bne	0x14000000
-		     blez	0x18000000	bgtz	0x1c000000 */
+		     blez	0x18000000	bgtz	0x1c000000  */
 		  insn ^= 0x04000000;
 		  break;
 
@@ -13747,8 +14229,8 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      /* Clear the and-link bit.  */
 	      assert ((insn & 0xfc1c0000) == 0x04100000);
 
-	      /* bltzal	0x04100000	bgezal	0x04110000
-		bltzall	0x04120000     bgezall	0x04130000 */
+	      /* bltzal		0x04100000	bgezal	0x04110000
+		 bltzall	0x04120000	bgezall	0x04130000  */
 	      insn &= ~0x00100000;
 	    }
 
@@ -13773,7 +14255,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	  md_number_to_chars ((char *) buf, insn, 4);
 	  buf += 4;
 
-	  /* Nop */
+	  /* nop */
 	  md_number_to_chars ((char *) buf, 0, 4);
 	  buf += 4;
 
@@ -13811,7 +14293,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      exp.X_add_number = fragp->fr_offset;
 
 	      fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-				  4, &exp, 0, BFD_RELOC_MIPS_JMP);
+				  4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
 	      fixp->fx_file = fragp->fr_file;
 	      fixp->fx_line = fragp->fr_line;
 
@@ -13833,7 +14315,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 		}
 
 	      fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-				  4, &exp, 0, BFD_RELOC_MIPS_GOT16);
+				  4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
 	      fixp->fx_file = fragp->fr_file;
 	      fixp->fx_line = fragp->fr_line;
 
@@ -13851,7 +14333,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
 
 	      fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-				  4, &exp, 0, BFD_RELOC_LO16);
+				  4, &exp, FALSE, BFD_RELOC_LO16);
 	      fixp->fx_file = fragp->fr_file;
 	      fixp->fx_line = fragp->fr_line;
 
@@ -13880,7 +14362,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
   if (RELAX_MIPS16_P (fragp->fr_subtype))
     {
       int type;
-      register const struct mips16_immed_operand *op;
+      const struct mips16_immed_operand *op;
       bfd_boolean small, ext;
       offsetT val;
       bfd_byte *buf;
@@ -14034,7 +14516,7 @@ mips_frob_file_after_relocs (void)
   asymbol **syms;
   unsigned int count, i;
 
-  if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+  if (!IS_ELF)
     return;
 
   syms = bfd_get_outsymbols (stdoutput);
@@ -14062,6 +14544,7 @@ mips_frob_file_after_relocs (void)
 void
 mips_define_label (symbolS *sym)
 {
+  segment_info_type *si = seg_info (now_seg);
   struct insn_label_list *l;
 
   if (free_insn_labels == NULL)
@@ -14073,8 +14556,8 @@ mips_define_label (symbolS *sym)
     }
 
   l->label = sym;
-  l->next = insn_labels;
-  insn_labels = l;
+  l->next = si->label_list;
+  si->label_list = l;
 
 #ifdef OBJ_ELF
   dwarf2_emit_label (sym);
@@ -14136,6 +14619,7 @@ mips_elf_final_processing (void)
   /* Set MIPS ELF flags for ASEs.  */
   /* We may need to define a new flag for DSP ASE, and set this flag when
      file_ase_dsp is true.  */
+  /* Same for DSP R2.  */
   /* We may need to define a new flag for MT ASE, and set this flag when
      file_ase_mt is true.  */
   if (file_ase_mips16)
@@ -14166,6 +14650,12 @@ mips_elf_final_processing (void)
 
   if (mips_32bitmode)
     elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
+
+#if 0 /* XXX FIXME */
+  /* 32 bit code with 64 bit FP registers.  */
+  if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
+    elf_elfheader (stdoutput)->e_flags |= ???;
+#endif
 }
 
 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
@@ -14226,7 +14716,7 @@ md_obj_begin (void)
 static void
 md_obj_end (void)
 {
-  /* check for premature end, nesting errors, etc */
+  /* Check for premature end, nesting errors, etc.  */
   if (cur_proc_ptr)
     as_warn (_("missing .end at end of assembly"));
 }
@@ -14383,8 +14873,7 @@ s_mips_end (int x ATTRIBUTE_UNUSED)
     }
 
   /* Generate a .pdr section.  */
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
-      && mips_flag_pdr)
+  if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
     {
       segT saved_seg = now_seg;
       subsegT saved_subseg = now_subseg;
@@ -14478,7 +14967,7 @@ static void
 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_ELF
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
+  if (IS_ELF && !ECOFF_DEBUGGING)
     {
       long val;
 
@@ -14521,7 +15010,7 @@ static void
 s_mips_mask (int reg_type)
 {
 #ifdef OBJ_ELF
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
+  if (IS_ELF && !ECOFF_DEBUGGING)
     {
       long mask, off;
 
@@ -14568,72 +15057,102 @@ s_mips_mask (int reg_type)
 static const struct mips_cpu_info mips_cpu_info_table[] =
 {
   /* Entries for generic ISAs */
-  { "mips1",          1,      ISA_MIPS1,      CPU_R3000 },
-  { "mips2",          1,      ISA_MIPS2,      CPU_R6000 },
-  { "mips3",          1,      ISA_MIPS3,      CPU_R4000 },
-  { "mips4",          1,      ISA_MIPS4,      CPU_R8000 },
-  { "mips5",          1,      ISA_MIPS5,      CPU_MIPS5 },
-  { "mips32",         1,      ISA_MIPS32,     CPU_MIPS32 },
-  { "mips32r2",       1,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "mips64",         1,      ISA_MIPS64,     CPU_MIPS64 },
-  { "mips64r2",       1,      ISA_MIPS64R2,   CPU_MIPS64R2 },
+  { "mips1",          MIPS_CPU_IS_ISA,		ISA_MIPS1,      CPU_R3000 },
+  { "mips2",          MIPS_CPU_IS_ISA,		ISA_MIPS2,      CPU_R6000 },
+  { "mips3",          MIPS_CPU_IS_ISA,		ISA_MIPS3,      CPU_R4000 },
+  { "mips4",          MIPS_CPU_IS_ISA,		ISA_MIPS4,      CPU_R8000 },
+  { "mips5",          MIPS_CPU_IS_ISA,		ISA_MIPS5,      CPU_MIPS5 },
+  { "mips32",         MIPS_CPU_IS_ISA,		ISA_MIPS32,     CPU_MIPS32 },
+  { "mips32r2",       MIPS_CPU_IS_ISA,		ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "mips64",         MIPS_CPU_IS_ISA,		ISA_MIPS64,     CPU_MIPS64 },
+  { "mips64r2",       MIPS_CPU_IS_ISA,		ISA_MIPS64R2,   CPU_MIPS64R2 },
 
   /* MIPS I */
-  { "r3000",          0,      ISA_MIPS1,      CPU_R3000 },
-  { "r2000",          0,      ISA_MIPS1,      CPU_R3000 },
-  { "r3900",          0,      ISA_MIPS1,      CPU_R3900 },
+  { "r3000",          0,			ISA_MIPS1,      CPU_R3000 },
+  { "r2000",          0,			ISA_MIPS1,      CPU_R3000 },
+  { "r3900",          0,			ISA_MIPS1,      CPU_R3900 },
 
   /* MIPS II */
-  { "r6000",          0,      ISA_MIPS2,      CPU_R6000 },
+  { "r6000",          0,			ISA_MIPS2,      CPU_R6000 },
 
   /* MIPS III */
-  { "r4000",          0,      ISA_MIPS3,      CPU_R4000 },
-  { "r4010",          0,      ISA_MIPS2,      CPU_R4010 },
-  { "vr4100",         0,      ISA_MIPS3,      CPU_VR4100 },
-  { "vr4111",         0,      ISA_MIPS3,      CPU_R4111 },
-  { "vr4120",         0,      ISA_MIPS3,      CPU_VR4120 },
-  { "vr4130",         0,      ISA_MIPS3,      CPU_VR4120 },
-  { "vr4181",         0,      ISA_MIPS3,      CPU_R4111 },
-  { "vr4300",         0,      ISA_MIPS3,      CPU_R4300 },
-  { "r4400",          0,      ISA_MIPS3,      CPU_R4400 },
-  { "r4600",          0,      ISA_MIPS3,      CPU_R4600 },
-  { "orion",          0,      ISA_MIPS3,      CPU_R4600 },
-  { "r4650",          0,      ISA_MIPS3,      CPU_R4650 },
+  { "r4000",          0,			ISA_MIPS3,      CPU_R4000 },
+  { "r4010",          0,			ISA_MIPS2,      CPU_R4010 },
+  { "vr4100",         0,			ISA_MIPS3,      CPU_VR4100 },
+  { "vr4111",         0,			ISA_MIPS3,      CPU_R4111 },
+  { "vr4120",         0,			ISA_MIPS3,      CPU_VR4120 },
+  { "vr4130",         0,			ISA_MIPS3,      CPU_VR4120 },
+  { "vr4181",         0,			ISA_MIPS3,      CPU_R4111 },
+  { "vr4300",         0,			ISA_MIPS3,      CPU_R4300 },
+  { "r4400",          0,			ISA_MIPS3,      CPU_R4400 },
+  { "r4600",          0,			ISA_MIPS3,      CPU_R4600 },
+  { "orion",          0,			ISA_MIPS3,      CPU_R4600 },
+  { "r4650",          0,			ISA_MIPS3,      CPU_R4650 },
 
   /* MIPS IV */
-  { "r8000",          0,      ISA_MIPS4,      CPU_R8000 },
-  { "r10000",         0,      ISA_MIPS4,      CPU_R10000 },
-  { "r12000",         0,      ISA_MIPS4,      CPU_R12000 },
-  { "vr5000",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "vr5400",         0,      ISA_MIPS4,      CPU_VR5400 },
-  { "vr5500",         0,      ISA_MIPS4,      CPU_VR5500 },
-  { "rm5200",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm5230",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm5231",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm5261",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm5721",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm7000",         0,      ISA_MIPS4,      CPU_RM7000 },
-  { "rm9000",         0,      ISA_MIPS4,      CPU_RM9000 },
+  { "r8000",          0,			ISA_MIPS4,      CPU_R8000 },
+  { "r10000",         0,			ISA_MIPS4,      CPU_R10000 },
+  { "r12000",         0,			ISA_MIPS4,      CPU_R12000 },
+  { "vr5000",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "vr5400",         0,			ISA_MIPS4,      CPU_VR5400 },
+  { "vr5500",         0,			ISA_MIPS4,      CPU_VR5500 },
+  { "rm5200",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm5230",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm5231",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm5261",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm5721",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm7000",         0,			ISA_MIPS4,      CPU_RM7000 },
+  { "rm9000",         0,			ISA_MIPS4,      CPU_RM9000 },
 
   /* MIPS 32 */
-  { "4kc",            0,      ISA_MIPS32,     CPU_MIPS32 },
-  { "4km",            0,      ISA_MIPS32,     CPU_MIPS32 },
-  { "4kp",            0,      ISA_MIPS32,     CPU_MIPS32 },
-
-  /* MIPS32 Release 2 */
-  { "m4k",            0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "24k",            0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "24kc",           0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "24kf",           0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "24kx",           0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "4kc",            0,			ISA_MIPS32,	CPU_MIPS32 },
+  { "4km",            0,			ISA_MIPS32,	CPU_MIPS32 },
+  { "4kp",            0,			ISA_MIPS32,	CPU_MIPS32 },
+  { "4ksc",           MIPS_CPU_ASE_SMARTMIPS,	ISA_MIPS32,	CPU_MIPS32 },
+
+  /* MIPS 32 Release 2 */
+  { "4kec",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "4kem",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "4kep",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "4ksd",           MIPS_CPU_ASE_SMARTMIPS,	ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "m4k",            0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "m4kp",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24kc",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24kf",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24kx",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  /* 24KE is a 24K with DSP ASE, other ASEs are optional.  */
+  { "24kec",          MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "24kef",          MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "24kex",          MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
+  /* 34K is a 24K with DSP and MT ASE, other ASEs are optional.  */
+  { "34kc",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "34kf",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "34kx",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  /* 74K with DSP and DSPR2 ASE, other ASEs are optional.  */
+  { "74kc",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "74kf",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "74kx",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
 
   /* MIPS 64 */
-  { "5kc",            0,      ISA_MIPS64,     CPU_MIPS64 },
-  { "5kf",            0,      ISA_MIPS64,     CPU_MIPS64 },
-  { "20kc",           0,      ISA_MIPS64,     CPU_MIPS64 },
+  { "5kc",            0,			ISA_MIPS64,	CPU_MIPS64 },
+  { "5kf",            0,			ISA_MIPS64,	CPU_MIPS64 },
+  { "20kc",           MIPS_CPU_ASE_MIPS3D,	ISA_MIPS64,	CPU_MIPS64 },
+  { "25kf",           MIPS_CPU_ASE_MIPS3D,	ISA_MIPS64,     CPU_MIPS64 },
+
+  /* MIPS 64 Release 2 */
 
   /* Broadcom SB-1 CPU core */
-  { "sb1",            0,      ISA_MIPS64,     CPU_SB1 },
+  { "sb1",            MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
+						ISA_MIPS64,	CPU_SB1 },
+  /* Broadcom SB-1A CPU core */
+  { "sb1a",           MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
+						ISA_MIPS64,	CPU_SB1 },
 
   /* Cavium Networks Octeon CPU core */
   { "octeon",         0,      ISA_MIPS64R2,   CPU_OCTEON },
@@ -14751,7 +15270,7 @@ mips_cpu_info_from_isa (int isa)
   int i;
 
   for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
-    if (mips_cpu_info_table[i].is_isa
+    if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
 	&& isa == mips_cpu_info_table[i].isa)
       return (&mips_cpu_info_table[i]);
 
@@ -14845,9 +15364,15 @@ MIPS options:\n\
 -mips16			generate mips16 instructions\n\
 -no-mips16		do not generate mips16 instructions\n"));
   fprintf (stream, _("\
+-msmartmips		generate smartmips instructions\n\
+-mno-smartmips		do not generate smartmips instructions\n"));  
+  fprintf (stream, _("\
 -mdsp			generate DSP instructions\n\
 -mno-dsp		do not generate DSP instructions\n"));
   fprintf (stream, _("\
+-mdspr2			generate DSP R2 instructions\n\
+-mno-dspr2		do not generate DSP R2 instructions\n"));
+  fprintf (stream, _("\
 -mmt			generate MT instructions\n\
 -mno-mt			do not generate MT instructions\n"));
   fprintf (stream, _("\
@@ -14855,7 +15380,6 @@ MIPS options:\n\
 -mfix-vr4130		work around VR4130 mflo/mfhi errata\n\
 -mgp32			use 32-bit GPRs, regardless of the chosen ISA\n\
 -mfp32			use 32-bit FPRs, regardless of the chosen ISA\n\
--mno-shared		optimize output for executables\n\
 -msym32			assume all symbols have 32-bit values\n\
 -O0			remove unneeded NOPs, do not swap branches\n\
 -O			remove unneeded NOPs and swap branches\n\
@@ -14865,11 +15389,12 @@ MIPS options:\n\
 #ifdef OBJ_ELF
   fprintf (stream, _("\
 -KPIC, -call_shared	generate SVR4 position independent code\n\
+-mvxworks-pic		generate VxWorks position independent code\n\
 -non_shared		do not generate position independent code\n\
 -xgot			assume a 32 bit GOT\n\
 -mpdr, -mno-pdr		enable/disable creation of .pdr sections\n\
 -mshared, -mno-shared   disable/enable .cpload optimization for\n\
-                        non-shared code\n\
+                        position dependent (non shared) code\n\
 -mabi=ABI		create ABI conformant object file for:\n"));
 
   first = 1;
@@ -14926,3 +15451,14 @@ mips_cfi_frame_initial_instructions (void)
   cfi_add_CFA_def_cfa_register (SP);
 }
 
+int
+tc_mips_regname_to_dw2regnum (char *regname)
+{
+  unsigned int regnum = -1;
+  unsigned int reg;
+
+  if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
+    regnum = reg;
+
+  return regnum;
+}
diff --git a/contrib/binutils/gas/config/tc-mips.h b/contrib/binutils/gas/config/tc-mips.h
index 5665d3d..117417c 100644
--- a/contrib/binutils/gas/config/tc-mips.h
+++ b/contrib/binutils/gas/config/tc-mips.h
@@ -1,6 +1,6 @@
 /* tc-mips.h -- header file for tc-mips.c.
-   Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, 2003, 2004
-   Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, 2003, 2004,
+   2005, 2006 Free Software Foundation, Inc.
    Contributed by the OSF and Ralph Campbell.
    Written by Keith Knowles and Ralph Campbell, working independently.
    Modified for ECOFF support by Ian Lance Taylor of Cygnus Support.
@@ -58,6 +58,12 @@ extern void mips_handle_align (struct frag *);
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE  (1 + 2)
 
+struct insn_label_list;
+#define TC_SEGMENT_INFO_TYPE struct insn_label_list *
+
+/* This field is nonzero if the symbol is the target of a MIPS16 jump.  */
+#define TC_SYMFIELD_TYPE int
+
 /* Tell assembler that we have an itbl_mips.h header file to include.  */
 #define HAVE_ITBL_CPU
 
@@ -149,6 +155,7 @@ extern void mips_emit_delays (void);
 extern void mips_enable_auto_align (void);
 #define md_elf_section_change_hook()	mips_enable_auto_align()
 
+enum dwarf2_format;
 extern enum dwarf2_format mips_dwarf2_format (void);
 #define DWARF2_FORMAT() mips_dwarf2_format ()
 
@@ -160,7 +167,10 @@ extern int mips_dwarf2_addr_size (void);
 #define tc_cfi_frame_initial_instructions mips_cfi_frame_initial_instructions
 extern void mips_cfi_frame_initial_instructions (void);
 
+#define tc_regname_to_dw2regnum tc_mips_regname_to_dw2regnum
+extern int tc_mips_regname_to_dw2regnum (char *regname);
+
 #define DWARF2_DEFAULT_RETURN_COLUMN 31
-#define DWARF2_CIE_DATA_ALIGNMENT -4
+#define DWARF2_CIE_DATA_ALIGNMENT (-4)
 
 #endif /* TC_MIPS */
diff --git a/contrib/binutils/gas/config/tc-ppc.c b/contrib/binutils/gas/config/tc-ppc.c
index d5bdb9e..a86a3be 100644
--- a/contrib/binutils/gas/config/tc-ppc.c
+++ b/contrib/binutils/gas/config/tc-ppc.c
@@ -1,6 +1,6 @@
 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005 Free Software Foundation, Inc.
+   2004, 2005, 2006, 2007 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
    This file is part of GAS, the GNU Assembler.
@@ -20,7 +20,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -85,67 +84,57 @@ static int set_target_endian = 0;
 
 static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
 
-static bfd_boolean register_name PARAMS ((expressionS *));
-static void ppc_set_cpu PARAMS ((void));
-static unsigned long ppc_insert_operand
-  PARAMS ((unsigned long insn, const struct powerpc_operand *operand,
-	   offsetT val, char *file, unsigned int line));
-static void ppc_macro PARAMS ((char *str, const struct powerpc_macro *macro));
-static void ppc_byte PARAMS ((int));
+static void ppc_macro (char *, const struct powerpc_macro *);
+static void ppc_byte (int);
 
 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
-static int ppc_is_toc_sym PARAMS ((symbolS *sym));
-static void ppc_tc PARAMS ((int));
-static void ppc_machine PARAMS ((int));
+static void ppc_tc (int);
+static void ppc_machine (int);
 #endif
 
 #ifdef OBJ_XCOFF
-static void ppc_comm PARAMS ((int));
-static void ppc_bb PARAMS ((int));
-static void ppc_bc PARAMS ((int));
-static void ppc_bf PARAMS ((int));
-static void ppc_biei PARAMS ((int));
-static void ppc_bs PARAMS ((int));
-static void ppc_eb PARAMS ((int));
-static void ppc_ec PARAMS ((int));
-static void ppc_ef PARAMS ((int));
-static void ppc_es PARAMS ((int));
-static void ppc_csect PARAMS ((int));
-static void ppc_change_csect PARAMS ((symbolS *, offsetT));
-static void ppc_function PARAMS ((int));
-static void ppc_extern PARAMS ((int));
-static void ppc_lglobl PARAMS ((int));
-static void ppc_section PARAMS ((int));
-static void ppc_named_section PARAMS ((int));
-static void ppc_stabx PARAMS ((int));
-static void ppc_rename PARAMS ((int));
-static void ppc_toc PARAMS ((int));
-static void ppc_xcoff_cons PARAMS ((int));
-static void ppc_vbyte PARAMS ((int));
+static void ppc_comm (int);
+static void ppc_bb (int);
+static void ppc_bc (int);
+static void ppc_bf (int);
+static void ppc_biei (int);
+static void ppc_bs (int);
+static void ppc_eb (int);
+static void ppc_ec (int);
+static void ppc_ef (int);
+static void ppc_es (int);
+static void ppc_csect (int);
+static void ppc_change_csect (symbolS *, offsetT);
+static void ppc_function (int);
+static void ppc_extern (int);
+static void ppc_lglobl (int);
+static void ppc_section (int);
+static void ppc_named_section (int);
+static void ppc_stabx (int);
+static void ppc_rename (int);
+static void ppc_toc (int);
+static void ppc_xcoff_cons (int);
+static void ppc_vbyte (int);
 #endif
 
 #ifdef OBJ_ELF
-static bfd_reloc_code_real_type ppc_elf_suffix PARAMS ((char **, expressionS *));
-static void ppc_elf_cons PARAMS ((int));
-static void ppc_elf_rdata PARAMS ((int));
-static void ppc_elf_lcomm PARAMS ((int));
-static void ppc_elf_validate_fix PARAMS ((fixS *, segT));
-static void ppc_apuinfo_section_add PARAMS ((unsigned int apu, unsigned int version));
+static void ppc_elf_cons (int);
+static void ppc_elf_rdata (int);
+static void ppc_elf_lcomm (int);
 #endif
 
 #ifdef TE_PE
-static void ppc_set_current_section PARAMS ((segT));
-static void ppc_previous PARAMS ((int));
-static void ppc_pdata PARAMS ((int));
-static void ppc_ydata PARAMS ((int));
-static void ppc_reldata PARAMS ((int));
-static void ppc_rdata PARAMS ((int));
-static void ppc_ualong PARAMS ((int));
-static void ppc_znop PARAMS ((int));
-static void ppc_pe_comm PARAMS ((int));
-static void ppc_pe_section PARAMS ((int));
-static void ppc_pe_function PARAMS ((int));
-static void ppc_pe_tocd PARAMS ((int));
+static void ppc_previous (int);
+static void ppc_pdata (int);
+static void ppc_ydata (int);
+static void ppc_reldata (int);
+static void ppc_rdata (int);
+static void ppc_ualong (int);
+static void ppc_znop (int);
+static void ppc_pe_comm (int);
+static void ppc_pe_section (int);
+static void ppc_pe_function (int);
+static void ppc_pe_tocd (int);
 #endif
 
 /* Generic assembler global variables which must be defined by all
@@ -183,11 +172,9 @@ const char EXP_CHARS[] = "eE";
    as in 0d1.0.  */
 const char FLT_CHARS[] = "dD";
 
-/* '+' and '-' can be used as postfix predicate predictors for conditional
-   branches.  So they need to be accepted as symbol characters.
-   Also, anything that can start an operand needs to be mentioned here,
+/* Anything that can start an operand needs to be mentioned here,
    to stop the input scrubber eating whitespace.  */
-const char ppc_symbol_chars[] = "+-%[";
+const char ppc_symbol_chars[] = "%[";
 
 /* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
 int ppc_cie_data_alignment;
@@ -567,14 +554,8 @@ static const struct pd_reg pre_defined_registers[] =
 /* Given NAME, find the register number associated with that name, return
    the integer value associated with the given name or -1 on failure.  */
 
-static int reg_name_search
-  PARAMS ((const struct pd_reg *, int, const char * name));
-
 static int
-reg_name_search (regs, regcount, name)
-     const struct pd_reg *regs;
-     int regcount;
-     const char *name;
+reg_name_search (const struct pd_reg *regs, int regcount, const char *name)
 {
   int middle, low, high;
   int cmp;
@@ -611,8 +592,7 @@ reg_name_search (regs, regcount, name)
  */
 
 static bfd_boolean
-register_name (expressionP)
-     expressionS *expressionP;
+register_name (expressionS *expressionP)
 {
   int reg_number;
   char *name;
@@ -679,9 +659,7 @@ static const struct pd_reg cr_names[] =
    expression.  */
 
 int
-ppc_parse_name (name, expr)
-     const char *name;
-     expressionS *expr;
+ppc_parse_name (const char *name, expressionS *expr)
 {
   int val;
 
@@ -917,6 +895,18 @@ parse_cpu (const char *arg)
 		 | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 		 | PPC_OPCODE_POWER5);
     }
+  else if (strcmp (arg, "power6") == 0)
+    {
+      ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
+		 | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+		 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6);
+    }
+  else if (strcmp (arg, "cell") == 0)
+    {
+      ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
+		 | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+		 | PPC_OPCODE_CELL);
+    }
   /* -mcom means assemble for the common intersection between Power
      and PowerPC.  At present, we just allow the union, rather
      than the intersection.  */
@@ -932,9 +922,7 @@ parse_cpu (const char *arg)
 }
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   switch (c)
     {
@@ -1088,8 +1076,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\
 PowerPC options:\n\
@@ -1112,6 +1099,8 @@ PowerPC options:\n\
 -mbooke, mbooke32	generate code for 32-bit PowerPC BookE\n\
 -mpower4		generate code for Power4 architecture\n\
 -mpower5		generate code for Power5 architecture\n\
+-mpower6		generate code for Power6 architecture\n\
+-mcell			generate code for Cell Broadband Engine architecture\n\
 -mcom			generate code Power/PowerPC common instructions\n\
 -many			generate code for any architecture (PWR/PWRX/PPC)\n"));
   fprintf (stream, _("\
@@ -1140,7 +1129,7 @@ PowerPC options:\n\
 /* Set ppc_cpu if it is not already set.  */
 
 static void
-ppc_set_cpu ()
+ppc_set_cpu (void)
 {
   const char *default_os  = TARGET_OS;
   const char *default_cpu = TARGET_CPU;
@@ -1168,7 +1157,7 @@ ppc_set_cpu ()
    are called well before md_begin, when the output file is opened.  */
 
 enum bfd_architecture
-ppc_arch ()
+ppc_arch (void)
 {
   const char *default_cpu = TARGET_CPU;
   ppc_set_cpu ();
@@ -1190,7 +1179,7 @@ ppc_arch ()
 }
 
 unsigned long
-ppc_mach ()
+ppc_mach (void)
 {
   if (ppc_obj64)
     return bfd_mach_ppc64;
@@ -1201,7 +1190,7 @@ ppc_mach ()
 }
 
 extern char*
-ppc_target_format ()
+ppc_target_format (void)
 {
 #ifdef OBJ_COFF
 #ifdef TE_PE
@@ -1233,11 +1222,11 @@ ppc_target_format ()
 static void
 ppc_setup_opcodes (void)
 {
-  register const struct powerpc_opcode *op;
+  const struct powerpc_opcode *op;
   const struct powerpc_opcode *op_end;
   const struct powerpc_macro *macro;
   const struct powerpc_macro *macro_end;
-  bfd_boolean dup_insn = FALSE;
+  bfd_boolean bad_insn = FALSE;
 
   if (ppc_hash != NULL)
     hash_die (ppc_hash);
@@ -1247,10 +1236,77 @@ ppc_setup_opcodes (void)
   /* Insert the opcodes into a hash table.  */
   ppc_hash = hash_new ();
 
+  if (ENABLE_CHECKING)
+    {
+      unsigned int i;
+
+      /* Check operand masks.  Code here and in the disassembler assumes
+	 all the 1's in the mask are contiguous.  */
+      for (i = 0; i < num_powerpc_operands; ++i)
+	{
+	  unsigned long mask = powerpc_operands[i].bitm;
+	  unsigned long right_bit;
+	  unsigned int j;
+
+	  right_bit = mask & -mask;
+	  mask += right_bit;
+	  right_bit = mask & -mask;
+	  if (mask != right_bit)
+	    {
+	      as_bad (_("powerpc_operands[%d].bitm invalid"), i);
+	      bad_insn = TRUE;
+	    }
+	  for (j = i + 1; j < num_powerpc_operands; ++j)
+	    if (memcmp (&powerpc_operands[i], &powerpc_operands[j],
+			sizeof (powerpc_operands[0])) == 0)
+	      {
+		as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
+			j, i);
+		bad_insn = TRUE;
+	      }
+	}
+    }
+
   op_end = powerpc_opcodes + powerpc_num_opcodes;
   for (op = powerpc_opcodes; op < op_end; op++)
     {
-      know ((op->opcode & op->mask) == op->opcode);
+      if (ENABLE_CHECKING)
+	{
+	  const unsigned char *o;
+	  unsigned long omask = op->mask;
+
+	  /* The mask had better not trim off opcode bits.  */
+	  if ((op->opcode & omask) != op->opcode)
+	    {
+	      as_bad (_("mask trims opcode bits for %s"),
+		      op->name);
+	      bad_insn = TRUE;
+	    }
+
+	  /* The operands must not overlap the opcode or each other.  */
+	  for (o = op->operands; *o; ++o)
+	    if (*o >= num_powerpc_operands)
+	      {
+		as_bad (_("operand index error for %s"),
+			op->name);
+		bad_insn = TRUE;
+	      }
+	    else
+	      {
+		const struct powerpc_operand *operand = &powerpc_operands[*o];
+		if (operand->shift >= 0)
+		  {
+		    unsigned long mask = operand->bitm << operand->shift;
+		    if (omask & mask)
+		      {
+			as_bad (_("operand %d overlap in %s"),
+				(int) (o - op->operands), op->name);
+			bad_insn = TRUE;
+		      }
+		    omask |= mask;
+		  }
+	      }
+	}
 
       if ((op->flags & ppc_cpu & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) != 0
 	  && ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
@@ -1270,11 +1326,14 @@ ppc_setup_opcodes (void)
 		  == (ppc_cpu & PPC_OPCODE_POWER4)))
 	  && ((op->flags & PPC_OPCODE_POWER5) == 0
 	      || ((op->flags & PPC_OPCODE_POWER5)
-		  == (ppc_cpu & PPC_OPCODE_POWER5))))
+		  == (ppc_cpu & PPC_OPCODE_POWER5)))
+	  && ((op->flags & PPC_OPCODE_POWER6) == 0
+	      || ((op->flags & PPC_OPCODE_POWER6)
+		  == (ppc_cpu & PPC_OPCODE_POWER6))))
 	{
 	  const char *retval;
 
-	  retval = hash_insert (ppc_hash, op->name, (PTR) op);
+	  retval = hash_insert (ppc_hash, op->name, (void *) op);
 	  if (retval != NULL)
 	    {
 	      /* Ignore Power duplicates for -m601.  */
@@ -1282,16 +1341,16 @@ ppc_setup_opcodes (void)
 		  && (op->flags & PPC_OPCODE_POWER) != 0)
 		continue;
 
-	      as_bad (_("Internal assembler error for instruction %s"),
+	      as_bad (_("duplicate instruction %s"),
 		      op->name);
-	      dup_insn = TRUE;
+	      bad_insn = TRUE;
 	    }
 	}
     }
 
   if ((ppc_cpu & PPC_OPCODE_ANY) != 0)
     for (op = powerpc_opcodes; op < op_end; op++)
-      hash_insert (ppc_hash, op->name, (PTR) op);
+      hash_insert (ppc_hash, op->name, (void *) op);
 
   /* Insert the macros into a hash table.  */
   ppc_macro_hash = hash_new ();
@@ -1303,16 +1362,16 @@ ppc_setup_opcodes (void)
 	{
 	  const char *retval;
 
-	  retval = hash_insert (ppc_macro_hash, macro->name, (PTR) macro);
+	  retval = hash_insert (ppc_macro_hash, macro->name, (void *) macro);
 	  if (retval != (const char *) NULL)
 	    {
-	      as_bad (_("Internal assembler error for macro %s"), macro->name);
-	      dup_insn = TRUE;
+	      as_bad (_("duplicate macro %s"), macro->name);
+	      bad_insn = TRUE;
 	    }
 	}
     }
 
-  if (dup_insn)
+  if (bad_insn)
     abort ();
 }
 
@@ -1321,7 +1380,7 @@ ppc_setup_opcodes (void)
    opened.  */
 
 void
-md_begin ()
+md_begin (void)
 {
   ppc_set_cpu ();
 
@@ -1364,7 +1423,7 @@ md_begin ()
 }
 
 void
-ppc_cleanup ()
+ppc_cleanup (void)
 {
 #ifdef OBJ_ELF
   if (ppc_apuinfo_list == NULL)
@@ -1426,54 +1485,60 @@ ppc_cleanup ()
 /* Insert an operand value into an instruction.  */
 
 static unsigned long
-ppc_insert_operand (insn, operand, val, file, line)
-     unsigned long insn;
-     const struct powerpc_operand *operand;
-     offsetT val;
-     char *file;
-     unsigned int line;
+ppc_insert_operand (unsigned long insn,
+		    const struct powerpc_operand *operand,
+		    offsetT val,
+		    char *file,
+		    unsigned int line)
 {
-  if (operand->bits != 32)
+  long min, max, right;
+
+  max = operand->bitm;
+  right = max & -max;
+  min = 0;
+
+  if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
     {
-      long min, max;
-      offsetT test;
+      if ((operand->flags & PPC_OPERAND_SIGNOPT) == 0)
+	max = (max >> 1) & -right;
+      min = ~max & -right;
+    }
 
-      if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
-	{
-	  if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0)
-	    max = (1 << operand->bits) - 1;
-	  else
-	    max = (1 << (operand->bits - 1)) - 1;
-	  min = - (1 << (operand->bits - 1));
+  if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
+    max++;
 
-	  if (!ppc_obj64)
-	    {
-	      /* Some people write 32 bit hex constants with the sign
-		 extension done by hand.  This shouldn't really be
-		 valid, but, to permit this code to assemble on a 64
-		 bit host, we sign extend the 32 bit value.  */
-	      if (val > 0
-		  && (val & (offsetT) 0x80000000) != 0
-		  && (val & (offsetT) 0xffffffff) == val)
-		{
-		  val -= 0x80000000;
-		  val -= 0x80000000;
-		}
-	    }
-	}
-      else
-	{
-	  max = (1 << operand->bits) - 1;
-	  min = 0;
-	}
+  if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
+    {
+      long tmp = min;
+      min = -max;
+      max = -tmp;
+    }
 
-      if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
-	test = - val;
-      else
-	test = val;
+  if (min <= max)
+    {
+      /* Some people write constants with the sign extension done by
+	 hand but only up to 32 bits.  This shouldn't really be valid,
+	 but, to permit this code to assemble on a 64-bit host, we
+	 sign extend the 32-bit value to 64 bits if so doing makes the
+	 value valid.  */
+      if (val > max
+	  && (offsetT) (val - 0x80000000 - 0x80000000) >= min
+	  && (offsetT) (val - 0x80000000 - 0x80000000) <= max
+	  && ((val - 0x80000000 - 0x80000000) & (right - 1)) == 0)
+	val = val - 0x80000000 - 0x80000000;
 
-      if (test < (offsetT) min || test > (offsetT) max)
-	as_bad_value_out_of_range (_("operand"), test, (offsetT) min, (offsetT) max, file, line);
+      /* Similarly, people write expressions like ~(1<<15), and expect
+	 this to be OK for a 32-bit unsigned value.  */
+      else if (val < min
+	       && (offsetT) (val + 0x80000000 + 0x80000000) >= min
+	       && (offsetT) (val + 0x80000000 + 0x80000000) <= max
+	       && ((val + 0x80000000 + 0x80000000) & (right - 1)) == 0)
+	val = val + 0x80000000 + 0x80000000;
+
+      else if (val < min
+	       || val > max
+	       || (val & (right - 1)) != 0)
+	as_bad_value_out_of_range (_("operand"), val, min, max, file, line);
     }
 
   if (operand->insert)
@@ -1486,8 +1551,7 @@ ppc_insert_operand (insn, operand, val, file, line)
 	as_bad_where (file, line, errmsg);
     }
   else
-    insn |= (((long) val & ((1 << operand->bits) - 1))
-	     << operand->shift);
+    insn |= ((long) val & operand->bitm) << operand->shift;
 
   return insn;
 }
@@ -1496,9 +1560,7 @@ ppc_insert_operand (insn, operand, val, file, line)
 #ifdef OBJ_ELF
 /* Parse @got, etc. and return the desired relocation.  */
 static bfd_reloc_code_real_type
-ppc_elf_suffix (str_p, exp_p)
-     char **str_p;
-     expressionS *exp_p;
+ppc_elf_suffix (char **str_p, expressionS *exp_p)
 {
   struct map_bfd {
     char *string;
@@ -1676,8 +1738,7 @@ ppc_elf_suffix (str_p, exp_p)
 /* Like normal .long/.short/.word, except support @got, etc.
    Clobbers input_line_pointer, checks end-of-line.  */
 static void
-ppc_elf_cons (nbytes)
-     register int nbytes;	/* 1=.byte, 2=.word, 4=.long, 8=.llong.  */
+ppc_elf_cons (int nbytes /* 1=.byte, 2=.word, 4=.long, 8=.llong */)
 {
   expressionS exp;
   bfd_reloc_code_real_type reloc;
@@ -1732,8 +1793,7 @@ ppc_elf_cons (nbytes)
 
 /* Solaris pseduo op to change to the .rodata section.  */
 static void
-ppc_elf_rdata (xxx)
-     int xxx;
+ppc_elf_rdata (int xxx)
 {
   char *save_line = input_line_pointer;
   static char section[] = ".rodata\n";
@@ -1747,14 +1807,13 @@ ppc_elf_rdata (xxx)
 
 /* Pseudo op to make file scope bss items.  */
 static void
-ppc_elf_lcomm (xxx)
-     int xxx ATTRIBUTE_UNUSED;
+ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED)
 {
-  register char *name;
-  register char c;
-  register char *p;
+  char *name;
+  char c;
+  char *p;
   offsetT size;
-  register symbolS *symbolP;
+  symbolS *symbolP;
   offsetT align;
   segT old_sec;
   int old_subsec;
@@ -1857,9 +1916,7 @@ ppc_elf_lcomm (xxx)
    fixups for word relocations in writable segments, so we can adjust
    them at runtime.  */
 static void
-ppc_elf_validate_fix (fixp, seg)
-     fixS *fixp;
-     segT seg;
+ppc_elf_validate_fix (fixS *fixp, segT seg)
 {
   if (fixp->fx_done || fixp->fx_pcrel)
     return;
@@ -1904,7 +1961,7 @@ ppc_elf_validate_fix (fixp, seg)
    function descriptor sym if the corresponding code sym is used.  */
 
 void
-ppc_frob_file_before_adjust ()
+ppc_frob_file_before_adjust (void)
 {
   symbolS *symp;
   asection *toc;
@@ -1987,8 +2044,7 @@ enum toc_size_qualifier
 };
 
 static int
-parse_toc_entry (toc_kind)
-     enum toc_size_qualifier *toc_kind;
+parse_toc_entry (enum toc_size_qualifier *toc_kind)
 {
   char *start;
   char *toc_spec;
@@ -2052,8 +2108,7 @@ parse_toc_entry (toc_kind)
 #ifdef OBJ_ELF
 #define APUID(a,v)	((((a) & 0xffff) << 16) | ((v) & 0xffff))
 static void
-ppc_apuinfo_section_add (apu, version)
-      unsigned int apu, version;
+ppc_apuinfo_section_add (unsigned int apu, unsigned int version)
 {
   unsigned int i;
 
@@ -2099,8 +2154,7 @@ struct ppc_fixup
 /* This routine is called for each instruction to be assembled.  */
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   char *s;
   const struct powerpc_opcode *opcode;
@@ -2724,16 +2778,14 @@ md_assemble (str)
    around operands here.  */
 
 static void
-ppc_macro (str, macro)
-     char *str;
-     const struct powerpc_macro *macro;
+ppc_macro (char *str, const struct powerpc_macro *macro)
 {
   char *operands[10];
   unsigned int count;
   char *s;
   unsigned int len;
   const char *format;
-  int arg;
+  unsigned int arg;
   char *send;
   char *complete;
 
@@ -2771,7 +2823,7 @@ ppc_macro (str, macro)
       else
 	{
 	  arg = strtol (format + 1, &send, 10);
-	  know (send != format && arg >= 0 && arg < count);
+	  know (send != format && arg < count);
 	  len += strlen (operands[arg]);
 	  format = send;
 	}
@@ -2802,9 +2854,7 @@ ppc_macro (str, macro)
 /* For ELF, add support for SHF_EXCLUDE and SHT_ORDERED.  */
 
 int
-ppc_section_letter (letter, ptr_msg)
-     int letter;
-     char **ptr_msg;
+ppc_section_letter (int letter, char **ptr_msg)
 {
   if (letter == 'e')
     return SHF_EXCLUDE;
@@ -2814,9 +2864,7 @@ ppc_section_letter (letter, ptr_msg)
 }
 
 int
-ppc_section_word (str, len)
-     char *str;
-     size_t len;
+ppc_section_word (char *str, size_t len)
 {
   if (len == 7 && strncmp (str, "exclude", 7) == 0)
     return SHF_EXCLUDE;
@@ -2825,9 +2873,7 @@ ppc_section_word (str, len)
 }
 
 int
-ppc_section_type (str, len)
-     char *str;
-     size_t len;
+ppc_section_type (char *str, size_t len)
 {
   if (len == 7 && strncmp (str, "ordered", 7) == 0)
     return SHT_ORDERED;
@@ -2836,10 +2882,7 @@ ppc_section_type (str, len)
 }
 
 int
-ppc_section_flags (flags, attr, type)
-     int flags;
-     int attr;
-     int type;
+ppc_section_flags (int flags, int attr, int type)
 {
   if (type == SHT_ORDERED)
     flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES;
@@ -2858,8 +2901,7 @@ ppc_section_flags (flags, attr, type)
    pseudo-op, but it can also take a single ASCII string.  */
 
 static void
-ppc_byte (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_byte (int ignore ATTRIBUTE_UNUSED)
 {
   if (*input_line_pointer != '\"')
     {
@@ -2903,8 +2945,7 @@ static bfd_boolean ppc_stab_symbol;
    aligns .comm and .lcomm to 4 bytes.  */
 
 static void
-ppc_comm (lcomm)
-     int lcomm;
+ppc_comm (int lcomm)
 {
   asection *current_seg = now_seg;
   subsegT current_subseg = now_subseg;
@@ -3058,8 +3099,7 @@ ppc_comm (lcomm)
    optional second argument is the alignment (the default is 2).  */
 
 static void
-ppc_csect (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_csect (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3094,9 +3134,7 @@ ppc_csect (ignore)
 /* Change to a different csect.  */
 
 static void
-ppc_change_csect (sym, align)
-     symbolS *sym;
-     offsetT align;
+ppc_change_csect (symbolS *sym, offsetT align)
 {
   if (S_IS_DEFINED (sym))
     subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg);
@@ -3196,8 +3234,7 @@ ppc_change_csect (sym, align)
    convenience of people who aren't used to XCOFF.  */
 
 static void
-ppc_section (type)
-     int type;
+ppc_section (int type)
 {
   const char *name;
   symbolS *sym;
@@ -3221,8 +3258,7 @@ ppc_section (type)
    we do permit the user to name the text or data section.  */
 
 static void
-ppc_named_section (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_named_section (int ignore ATTRIBUTE_UNUSED)
 {
   char *user_name;
   const char *real_name;
@@ -3256,8 +3292,7 @@ ppc_named_section (ignore)
 /* The .extern pseudo-op.  We create an undefined symbol.  */
 
 static void
-ppc_extern (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_extern (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3275,8 +3310,7 @@ ppc_extern (ignore)
 /* The .lglobl pseudo-op.  Keep the symbol in the symbol table.  */
 
 static void
-ppc_lglobl (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_lglobl (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3298,8 +3332,7 @@ ppc_lglobl (ignore)
    although I don't know why it bothers.  */
 
 static void
-ppc_rename (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_rename (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3334,8 +3367,7 @@ ppc_rename (ignore)
    always zero, and I am assuming it is the type.  */
 
 static void
-ppc_stabx (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_stabx (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   int len;
@@ -3461,8 +3493,7 @@ ppc_stabx (ignore)
    gets an aux entry like that used for a csect.  */
 
 static void
-ppc_function (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_function (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3555,8 +3586,7 @@ ppc_function (ignore)
 static symbolS *saved_bi_sym = 0;
 
 static void
-ppc_bf (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_bf (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3591,8 +3621,7 @@ ppc_bf (ignore)
    most recent ".bf" symbol.  */
 
 static void
-ppc_ef (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_ef (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3616,8 +3645,7 @@ ppc_ef (ignore)
    is encountered.  */
 
 static void
-ppc_biei (ei)
-     int ei;
+ppc_biei (int ei)
 {
   static symbolS *last_biei;
 
@@ -3671,8 +3699,7 @@ ppc_biei (ei)
    .bs symbol is the index of this csect symbol.  */
 
 static void
-ppc_bs (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_bs (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3707,8 +3734,7 @@ ppc_bs (ignore)
 /* The .es pseudo-op.  Generate a C_ESTART symbol named .es.  */
 
 static void
-ppc_es (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_es (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3732,8 +3758,7 @@ ppc_es (ignore)
    line number.  */
 
 static void
-ppc_bb (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_bb (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3759,8 +3784,7 @@ ppc_bb (ignore)
    line number.  */
 
 static void
-ppc_eb (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_eb (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3784,8 +3808,7 @@ ppc_eb (ignore)
    specified name.  */
 
 static void
-ppc_bc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_bc (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   int len;
@@ -3807,8 +3830,7 @@ ppc_bc (ignore)
 /* The .ec pseudo-op.  This just creates a C_ECOMM symbol.  */
 
 static void
-ppc_ec (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_ec (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3827,8 +3849,7 @@ ppc_ec (ignore)
 /* The .toc pseudo-op.  Switch to the .toc subsegment.  */
 
 static void
-ppc_toc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_toc (int ignore ATTRIBUTE_UNUSED)
 {
   if (ppc_toc_csect != (symbolS *) NULL)
     subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg);
@@ -3874,8 +3895,7 @@ ppc_toc (ignore)
    .short pseudo-op, and we want to be compatible.  */
 
 static void
-ppc_xcoff_cons (log_size)
-     int log_size;
+ppc_xcoff_cons (int log_size)
 {
   frag_align (log_size, 0, 0);
   record_alignment (now_seg, log_size);
@@ -3883,8 +3903,7 @@ ppc_xcoff_cons (log_size)
 }
 
 static void
-ppc_vbyte (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+ppc_vbyte (int dummy ATTRIBUTE_UNUSED)
 {
   expressionS exp;
   int byte_count;
@@ -3927,8 +3946,7 @@ ppc_vbyte (dummy)
    the first argument is simply ignored.  */
 
 static void
-ppc_tc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_tc (int ignore ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_XCOFF
 
@@ -4014,8 +4032,7 @@ ppc_tc (ignore)
 /* Pseudo-op .machine.  */
 
 static void
-ppc_machine (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_machine (int ignore ATTRIBUTE_UNUSED)
 {
   char *cpu_string;
 #define MAX_HISTORY 100
@@ -4078,8 +4095,7 @@ ppc_machine (ignore)
 /* See whether a symbol is in the TOC section.  */
 
 static int
-ppc_is_toc_sym (sym)
-     symbolS *sym;
+ppc_is_toc_sym (symbolS *sym)
 {
 #ifdef OBJ_XCOFF
   return symbol_get_tc (sym)->class == XMC_TC;
@@ -4100,8 +4116,7 @@ ppc_is_toc_sym (sym)
 
 /* Set the current section.  */
 static void
-ppc_set_current_section (new)
-     segT new;
+ppc_set_current_section (segT new)
 {
   ppc_previous_section = ppc_current_section;
   ppc_current_section = new;
@@ -4113,8 +4128,7 @@ ppc_set_current_section (new)
    warnings:  "No previous section"  */
 
 static void
-ppc_previous (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_previous (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *tmp;
 
@@ -4145,8 +4159,7 @@ ppc_previous (ignore)
    handling, debugging, etc.  */
 
 static void
-ppc_pdata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_pdata (int ignore ATTRIBUTE_UNUSED)
 {
   if (pdata_section == 0)
     {
@@ -4180,8 +4193,7 @@ ppc_pdata (ignore)
    debugging, etc.  */
 
 static void
-ppc_ydata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_ydata (int ignore ATTRIBUTE_UNUSED)
 {
   if (ydata_section == 0)
     {
@@ -4217,8 +4229,7 @@ ppc_ydata (ignore)
    function descriptors, etc.  */
 
 static void
-ppc_reldata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_reldata (int ignore ATTRIBUTE_UNUSED)
 {
   if (reldata_section == 0)
     {
@@ -4248,8 +4259,7 @@ ppc_reldata (ignore)
 	      3 - double word aligned (that would be 4 byte boundary)  */
 
 static void
-ppc_rdata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_rdata (int ignore ATTRIBUTE_UNUSED)
 {
   if (rdata_section == 0)
     {
@@ -4275,8 +4285,7 @@ ppc_rdata (ignore)
    warnings:  None  */
 
 static void
-ppc_ualong (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_ualong (int ignore ATTRIBUTE_UNUSED)
 {
   /* Try for long.  */
   cons (4);
@@ -4290,8 +4299,7 @@ ppc_ualong (ignore)
    warnings:  Missing symbol name  */
 
 static void
-ppc_znop (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_znop (int ignore ATTRIBUTE_UNUSED)
 {
   unsigned long insn;
   const struct powerpc_opcode *opcode;
@@ -4343,14 +4351,13 @@ ppc_znop (ignore)
    warnings:  */
 
 static void
-ppc_pe_comm (lcomm)
-     int lcomm;
+ppc_pe_comm (int lcomm)
 {
-  register char *name;
-  register char c;
-  register char *p;
+  char *name;
+  char c;
+  char *p;
   offsetT temp;
-  register symbolS *symbolP;
+  symbolS *symbolP;
   offsetT align;
 
   name = input_line_pointer;
@@ -4473,8 +4480,7 @@ ppc_pe_comm (lcomm)
  */
 
 void
-ppc_pe_section (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_pe_section (int ignore ATTRIBUTE_UNUSED)
 {
   /* Strip out the section name.  */
   char *section_name;
@@ -4562,7 +4568,7 @@ ppc_pe_section (ignore)
 		case 'R': /* Remove section at link time */
 		  flags |= SEC_NEVER_LOAD;
 		  break;
-
+#if IFLICT_BRAIN_DAMAGE
 		  /* Section Protection */
 		case 'r': /* section is readable */
 		  flags |= IMAGE_SCN_MEM_READ;
@@ -4606,7 +4612,7 @@ ppc_pe_section (ignore)
 		  flags |= IMAGE_SCN_ALIGN_64BYTES;
 		  align = 6;
 		  break;
-
+#endif
 		default:
 		  as_bad (_("unknown section attribute '%c'"),
 			  *input_line_pointer);
@@ -4632,12 +4638,10 @@ ppc_pe_section (ignore)
     }
 
   bfd_set_section_alignment (stdoutput, sec, align);
-
 }
 
 static void
-ppc_pe_function (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_pe_function (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -4659,8 +4663,7 @@ ppc_pe_function (ignore)
 }
 
 static void
-ppc_pe_tocd (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_pe_tocd (int ignore ATTRIBUTE_UNUSED)
 {
   if (tocdata_section == 0)
     {
@@ -4685,8 +4688,7 @@ ppc_pe_tocd (ignore)
 /* Don't adjust TOC relocs to use the section symbol.  */
 
 int
-ppc_pe_fix_adjustable (fix)
-     fixS *fix;
+ppc_pe_fix_adjustable (fixS *fix)
 {
   return fix->fx_r_type != BFD_RELOC_PPC_TOC16;
 }
@@ -4701,8 +4703,7 @@ ppc_pe_fix_adjustable (fix)
    any, to use square brackets, and to be in upper case.  */
 
 char *
-ppc_canonicalize_symbol_name (name)
-     char *name;
+ppc_canonicalize_symbol_name (char *name)
 {
   char *s;
 
@@ -4739,8 +4740,7 @@ ppc_canonicalize_symbol_name (name)
    called whenever a new symbol is created.  */
 
 void
-ppc_symbol_new_hook (sym)
-     symbolS *sym;
+ppc_symbol_new_hook (symbolS *sym)
 {
   struct ppc_tc_sy *tc;
   const char *s;
@@ -4828,8 +4828,7 @@ ppc_symbol_new_hook (sym)
    follows the csect symbol.  */
 
 void
-ppc_frob_label (sym)
-     symbolS *sym;
+ppc_frob_label (symbolS *sym)
 {
   if (ppc_current_csect != (symbolS *) NULL)
     {
@@ -4859,8 +4858,7 @@ static bfd_boolean ppc_saw_abs;
    symbol table.  */
 
 int
-ppc_frob_symbol (sym)
-     symbolS *sym;
+ppc_frob_symbol (symbolS *sym)
 {
   static symbolS *ppc_last_function;
   static symbolS *set_end;
@@ -5123,7 +5121,7 @@ ppc_frob_symbol (sym)
    absolute symbols.  */
 
 void
-ppc_adjust_symtab ()
+ppc_adjust_symtab (void)
 {
   symbolS *sym;
 
@@ -5169,8 +5167,7 @@ ppc_adjust_symtab ()
    turn.  */
 
 void
-ppc_frob_section (sec)
-     asection *sec;
+ppc_frob_section (asection *sec)
 {
   static bfd_vma vma = 0;
 
@@ -5187,10 +5184,7 @@ ppc_frob_section (sec)
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litp, sizep)
-     int type;
-     char *litp;
-     int *sizep;
+md_atof (int type, char *litp, int *sizep)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -5242,10 +5236,7 @@ md_atof (type, litp, sizep)
    endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
   if (target_big_endian)
     number_to_chars_bigendian (buf, val, n);
@@ -5256,21 +5247,22 @@ md_number_to_chars (buf, val, n)
 /* Align a section (I don't know why this is machine dependent).  */
 
 valueT
-md_section_align (seg, addr)
-     asection *seg;
-     valueT addr;
+md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr)
 {
+#ifdef OBJ_ELF
+  return addr;
+#else
   int align = bfd_get_section_alignment (stdoutput, seg);
 
   return ((addr + (1 << align) - 1) & (-1 << align));
+#endif
 }
 
 /* We don't have any form of relaxing.  */
 
 int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp ATTRIBUTE_UNUSED;
-     asection *seg ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
+			       asection *seg ATTRIBUTE_UNUSED)
 {
   abort ();
   return 0;
@@ -5279,10 +5271,9 @@ md_estimate_size_before_relax (fragp, seg)
 /* Convert a machine dependent frag.  We never generate these.  */
 
 void
-md_convert_frag (abfd, sec, fragp)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec ATTRIBUTE_UNUSED;
-     fragS *fragp ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec ATTRIBUTE_UNUSED,
+		 fragS *fragp ATTRIBUTE_UNUSED)
 {
   abort ();
 }
@@ -5290,8 +5281,7 @@ md_convert_frag (abfd, sec, fragp)
 /* We have no need to default values of symbols.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -5302,9 +5292,7 @@ md_undefined_symbol (name)
    given a PC relative reloc.  */
 
 long
-md_pcrel_from_section (fixp, sec)
-     fixS *fixp;
-     segT sec ATTRIBUTE_UNUSED;
+md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED)
 {
   return fixp->fx_frag->fr_address + fixp->fx_where;
 }
@@ -5317,8 +5305,7 @@ md_pcrel_from_section (fixp, sec)
    corresponding .tc symbol.  */
 
 int
-ppc_fix_adjustable (fix)
-     fixS *fix;
+ppc_fix_adjustable (fixS *fix)
 {
   valueT val = resolve_symbol_value (fix->fx_addsy);
   segT symseg = S_GET_SEGMENT (fix->fx_addsy);
@@ -5443,8 +5430,7 @@ ppc_fix_adjustable (fix)
    between two csects in the same section.  */
 
 int
-ppc_force_relocation (fix)
-     fixS *fix;
+ppc_force_relocation (fixS *fix)
 {
   /* At this point fix->fx_addsy should already have been converted to
      a csect symbol.  If the csect does not include the fragment, then
@@ -5469,8 +5455,7 @@ ppc_force_relocation (fix)
    will be emitted for a fixup.  */
 
 int
-ppc_force_relocation (fix)
-     fixS *fix;
+ppc_force_relocation (fixS *fix)
 {
   /* Branch prediction relocations must force a relocation, as must
      the vtable description relocs.  */
@@ -5495,8 +5480,7 @@ ppc_force_relocation (fix)
 }
 
 int
-ppc_fix_adjustable (fix)
-     fixS *fix;
+ppc_fix_adjustable (fixS *fix)
 {
   return (fix->fx_r_type != BFD_RELOC_16_GOTOFF
 	  && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF
@@ -5510,6 +5494,47 @@ ppc_fix_adjustable (fix)
 }
 #endif
 
+/* Implement HANDLE_ALIGN.  This writes the NOP pattern into an
+   rs_align_code frag.  */
+
+void
+ppc_handle_align (struct frag *fragP)
+{
+  valueT count = (fragP->fr_next->fr_address
+		  - (fragP->fr_address + fragP->fr_fix));
+
+  if (count != 0 && (count & 3) == 0)
+    {
+      char *dest = fragP->fr_literal + fragP->fr_fix;
+
+      fragP->fr_var = 4;
+      md_number_to_chars (dest, 0x60000000, 4);
+
+      if ((ppc_cpu & PPC_OPCODE_POWER6) != 0)
+	{
+	  /* For power6, we want the last nop to be a group terminating
+	     one, "ori 1,1,0".  Do this by inserting an rs_fill frag
+	     immediately after this one, with its address set to the last
+	     nop location.  This will automatically reduce the number of
+	     nops in the current frag by one.  */
+	  if (count > 4)
+	    {
+	      struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4);
+
+	      memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG);
+	      group_nop->fr_address = group_nop->fr_next->fr_address - 4;
+	      group_nop->fr_fix = 0;
+	      group_nop->fr_offset = 1;
+	      group_nop->fr_type = rs_fill;
+	      fragP->fr_next = group_nop;
+	      dest = group_nop->fr_literal;
+	    }
+
+	  md_number_to_chars (dest, 0x60210000, 4);
+	}
+    }
+}
+
 /* Apply a fixup to the object code.  This is called for all the
    fixups we generated by the call to fix_new_exp, above.  In the call
    above we used a reloc code which was the largest legal reloc code
@@ -5520,10 +5545,7 @@ ppc_fix_adjustable (fix)
    fixup.  */
 
 void
-md_apply_fix (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   valueT value = * valP;
 
@@ -5580,7 +5602,7 @@ md_apply_fix (fixP, valP, seg)
 	 csect.  Other usages, such as `.long sym', generate relocs.  This
 	 is the documented behaviour of non-TOC symbols.  */
       if ((operand->flags & PPC_OPERAND_PARENS) != 0
-	  && operand->bits == 16
+	  && (operand->bitm & 0xfff0) == 0xfff0
 	  && operand->shift == 0
 	  && (operand->insert == NULL || ppc_obj64)
 	  && fixP->fx_addsy != NULL
@@ -5618,11 +5640,11 @@ md_apply_fix (fixP, valP, seg)
 	 We are only prepared to turn a few of the operands into
 	 relocs.  */
       if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
-	  && operand->bits == 26
+	  && operand->bitm == 0x3fffffc
 	  && operand->shift == 0)
 	fixP->fx_r_type = BFD_RELOC_PPC_B26;
       else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
-	  && operand->bits == 16
+	  && operand->bitm == 0xfffc
 	  && operand->shift == 0)
 	{
 	  fixP->fx_r_type = BFD_RELOC_PPC_B16;
@@ -5633,11 +5655,11 @@ md_apply_fix (fixP, valP, seg)
 #endif
 	}
       else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
-	       && operand->bits == 26
+	       && operand->bitm == 0x3fffffc
 	       && operand->shift == 0)
 	fixP->fx_r_type = BFD_RELOC_PPC_BA26;
       else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
-	       && operand->bits == 16
+	       && operand->bitm == 0xfffc
 	       && operand->shift == 0)
 	{
 	  fixP->fx_r_type = BFD_RELOC_PPC_BA16;
@@ -5649,7 +5671,7 @@ md_apply_fix (fixP, valP, seg)
 	}
 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
       else if ((operand->flags & PPC_OPERAND_PARENS) != 0
-	       && operand->bits == 16
+	       && (operand->bitm & 0xfff0) == 0xfff0
 	       && operand->shift == 0)
 	{
 	  if (ppc_is_toc_sym (fixP->fx_addsy))
@@ -6047,9 +6069,7 @@ md_apply_fix (fixP, valP, seg)
 /* Generate a reloc for a fixup.  */
 
 arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
 
@@ -6072,13 +6092,13 @@ tc_gen_reloc (seg, fixp)
 }
 
 void
-ppc_cfi_frame_initial_instructions ()
+ppc_cfi_frame_initial_instructions (void)
 {
   cfi_add_CFA_def_cfa (1, 0);
 }
 
 int
-tc_ppc_regname_to_dw2regnum (const char *regname)
+tc_ppc_regname_to_dw2regnum (char *regname)
 {
   unsigned int regnum = -1;
   unsigned int i;
diff --git a/contrib/binutils/gas/config/tc-ppc.h b/contrib/binutils/gas/config/tc-ppc.h
index f7c2da6..1e85649 100644
--- a/contrib/binutils/gas/config/tc-ppc.h
+++ b/contrib/binutils/gas/config/tc-ppc.h
@@ -1,6 +1,6 @@
 /* tc-ppc.h -- Header file for tc-ppc.c.
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005 Free Software Foundation, Inc.
+   2004, 2005, 2006, 2007 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
    This file is part of GAS, the GNU Assembler.
@@ -42,15 +42,15 @@ struct fix;
 /* The target BFD architecture.  */
 #define TARGET_ARCH (ppc_arch ())
 #define TARGET_MACH (ppc_mach ())
-extern enum bfd_architecture ppc_arch PARAMS ((void));
-extern unsigned long ppc_mach PARAMS ((void));
+extern enum bfd_architecture ppc_arch (void);
+extern unsigned long ppc_mach (void);
 
 /* Whether or not the target is big endian */
 extern int target_big_endian;
 
 /* The target BFD format.  */
 #define TARGET_FORMAT (ppc_target_format ())
-extern char *ppc_target_format PARAMS ((void));
+extern char *ppc_target_format (void);
 
 /* Permit temporary numeric labels.  */
 #define LOCAL_LABELS_FB 1
@@ -78,31 +78,12 @@ extern char *ppc_target_format PARAMS ((void));
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE 4
 #define HANDLE_ALIGN(FRAGP)						\
-  if ((FRAGP)->fr_type == rs_align_code) 				\
-    {									\
-      valueT count = ((FRAGP)->fr_next->fr_address			\
-		      - ((FRAGP)->fr_address + (FRAGP)->fr_fix));	\
-      if (count != 0 && (count & 3) == 0)				\
-	{								\
-	  char *dest = (FRAGP)->fr_literal + (FRAGP)->fr_fix;		\
-									\
-	  (FRAGP)->fr_var = 4;						\
-	  if (target_big_endian)					\
-	    {								\
-	      *dest++ = 0x60;						\
-	      *dest++ = 0;						\
-	      *dest++ = 0;						\
-	      *dest++ = 0;						\
-	    }								\
-	  else								\
-	    {								\
-	      *dest++ = 0;						\
-	      *dest++ = 0;						\
-	      *dest++ = 0;						\
-	      *dest++ = 0x60;						\
-	    }								\
-	}								\
-    }
+  if ((FRAGP)->fr_type == rs_align_code)				\
+    ppc_handle_align (FRAGP);
+
+extern void ppc_handle_align (struct frag *);
+
+#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
 
 #define md_frag_check(FRAGP) \
   if ((FRAGP)->has_code							\
@@ -117,7 +98,7 @@ extern char *ppc_target_format PARAMS ((void));
 
 /* Don't adjust TOC relocs.  */
 #define tc_fix_adjustable(FIX) ppc_pe_fix_adjustable (FIX)
-extern int ppc_pe_fix_adjustable PARAMS ((struct fix *));
+extern int ppc_pe_fix_adjustable (struct fix *);
 
 #endif
 
@@ -165,31 +146,31 @@ struct ppc_tc_sy
 
 /* Canonicalize the symbol name.  */
 #define tc_canonicalize_symbol_name(name) ppc_canonicalize_symbol_name (name)
-extern char *ppc_canonicalize_symbol_name PARAMS ((char *));
+extern char *ppc_canonicalize_symbol_name (char *);
 
 /* Get the symbol class from the name.  */
 #define tc_symbol_new_hook(sym) ppc_symbol_new_hook (sym)
-extern void ppc_symbol_new_hook PARAMS ((symbolS *));
+extern void ppc_symbol_new_hook (symbolS *);
 
 /* Set the symbol class of a label based on the csect.  */
 #define tc_frob_label(sym) ppc_frob_label (sym)
-extern void ppc_frob_label PARAMS ((symbolS *));
+extern void ppc_frob_label (symbolS *);
 
 /* TOC relocs requires special handling.  */
 #define tc_fix_adjustable(FIX) ppc_fix_adjustable (FIX)
-extern int ppc_fix_adjustable PARAMS ((struct fix *));
+extern int ppc_fix_adjustable (struct fix *);
 
 /* We need to set the section VMA.  */
 #define tc_frob_section(sec) ppc_frob_section (sec)
-extern void ppc_frob_section PARAMS ((asection *));
+extern void ppc_frob_section (asection *);
 
 /* Finish up the symbol.  */
 #define tc_frob_symbol(sym, punt) punt = ppc_frob_symbol (sym)
-extern int ppc_frob_symbol PARAMS ((symbolS *));
+extern int ppc_frob_symbol (symbolS *);
 
 /* Finish up the entire symtab.  */
 #define tc_adjust_symtab() ppc_adjust_symtab ()
-extern void ppc_adjust_symtab PARAMS ((void));
+extern void ppc_adjust_symtab (void);
 
 /* We also need to copy, in particular, the class of the symbol,
    over what obj-coff would otherwise have copied.  */
@@ -211,10 +192,10 @@ extern const char       ppc_symbol_chars[];
 #ifdef OBJ_ELF
 
 /* Support for SHF_EXCLUDE and SHT_ORDERED */
-extern int ppc_section_letter PARAMS ((int, char **));
-extern int ppc_section_type PARAMS ((char *, size_t));
-extern int ppc_section_word PARAMS ((char *, size_t));
-extern int ppc_section_flags PARAMS ((int, int, int));
+extern int ppc_section_letter (int, char **);
+extern int ppc_section_type (char *, size_t);
+extern int ppc_section_word (char *, size_t);
+extern int ppc_section_flags (int, int, int);
 
 #define md_elf_section_letter(LETTER, PTR_MSG)	ppc_section_letter (LETTER, PTR_MSG)
 #define md_elf_section_type(STR, LEN)		ppc_section_type (STR, LEN)
@@ -226,40 +207,40 @@ extern const char *ppc_comment_chars;
 
 /* Keep relocations relative to the GOT, or non-PC relative.  */
 #define tc_fix_adjustable(FIX) ppc_fix_adjustable (FIX)
-extern int ppc_fix_adjustable PARAMS ((struct fix *));
+extern int ppc_fix_adjustable (struct fix *);
 
 /* Values passed to md_apply_fix don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #define tc_frob_file_before_adjust ppc_frob_file_before_adjust
-extern void ppc_frob_file_before_adjust PARAMS ((void));
+extern void ppc_frob_file_before_adjust (void);
 
 #endif /* OBJ_ELF */
 
 #if defined (OBJ_ELF) || defined (OBJ_XCOFF)
 #define TC_FORCE_RELOCATION(FIX) ppc_force_relocation (FIX)
-extern int ppc_force_relocation PARAMS ((struct fix *));
+extern int ppc_force_relocation (struct fix *);
 #endif
 
 /* call md_pcrel_from_section, not md_pcrel_from */
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+extern long md_pcrel_from_section (struct fix *, segT);
 
 #define md_parse_name(name, exp, mode, c) ppc_parse_name (name, exp)
-extern int ppc_parse_name PARAMS ((const char *, struct expressionS *));
+extern int ppc_parse_name (const char *, struct expressionS *);
 
 #define md_operand(x)
 
 #define md_cleanup() ppc_cleanup ()
- extern void ppc_cleanup PARAMS ((void));
+extern void ppc_cleanup (void);
 
 #define TARGET_USE_CFIPOP 1
 
 #define tc_cfi_frame_initial_instructions ppc_cfi_frame_initial_instructions
-extern void ppc_cfi_frame_initial_instructions PARAMS ((void));
+extern void ppc_cfi_frame_initial_instructions (void);
 
 #define tc_regname_to_dw2regnum tc_ppc_regname_to_dw2regnum
-extern int tc_ppc_regname_to_dw2regnum PARAMS ((const char *regname));
+extern int tc_ppc_regname_to_dw2regnum (char *);
 
 extern int ppc_cie_data_alignment;
 
diff --git a/contrib/binutils/gas/config/tc-s390.c b/contrib/binutils/gas/config/tc-s390.c
index 56b5b25..6ca31f7b 100644
--- a/contrib/binutils/gas/config/tc-s390.c
+++ b/contrib/binutils/gas/config/tc-s390.c
@@ -1,5 +1,5 @@
 /* tc-s390.c -- Assemble for the S390
-   Copyright 2000, 2001, 2002, 2003, 2004, 2005
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
    Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
 
@@ -20,7 +20,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -412,6 +411,8 @@ md_parse_option (c, arg)
 	    current_cpu = S390_OPCODE_Z990;
 	  else if (strcmp (arg + 5, "z9-109") == 0)
 	    current_cpu = S390_OPCODE_Z9_109;
+	  else if (strcmp (arg + 5, "z9-ec") == 0)
+	    current_cpu = S390_OPCODE_Z9_EC;
 	  else
 	    {
 	      as_bad (_("invalid switch -m%s"), arg);
@@ -2322,7 +2323,7 @@ s390_cfi_frame_initial_instructions ()
 }
 
 int
-tc_s390_regname_to_dw2regnum (const char *regname)
+tc_s390_regname_to_dw2regnum (char *regname)
 {
   int regnum = -1;
 
diff --git a/contrib/binutils/gas/config/tc-s390.h b/contrib/binutils/gas/config/tc-s390.h
index dbecfef..b387c3b 100644
--- a/contrib/binutils/gas/config/tc-s390.h
+++ b/contrib/binutils/gas/config/tc-s390.h
@@ -88,7 +88,7 @@ extern void s390_md_end PARAMS ((void));
 extern void s390_cfi_frame_initial_instructions PARAMS ((void));
 
 #define tc_regname_to_dw2regnum tc_s390_regname_to_dw2regnum
-extern int tc_s390_regname_to_dw2regnum PARAMS ((const char *regname));
+extern int tc_s390_regname_to_dw2regnum PARAMS ((char *regname));
 
 extern int s390_cie_data_alignment;
 
diff --git a/contrib/binutils/gas/config/tc-score.c b/contrib/binutils/gas/config/tc-score.c
new file mode 100644
index 0000000..fe45b00
--- /dev/null
+++ b/contrib/binutils/gas/config/tc-score.c
@@ -0,0 +1,6661 @@
+/* tc-score.c -- Assembler for Score
+   Copyright 2006 Free Software Foundation, Inc.
+   Contributed by:
+   Mei Ligang (ligang@sunnorth.com.cn)
+   Pei-Lin Tsai (pltsai@sunplus.com)
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "as.h"
+#include "config.h"
+#include "subsegs.h"
+#include "safe-ctype.h"
+#include "opcode/score-inst.h"
+#include "opcode/score-datadep.h"
+#include "struc-symbol.h"
+
+#ifdef OBJ_ELF
+#include "elf/score.h"
+#include "dwarf2dbg.h"
+#endif
+
+#define GP                     28
+#define PIC_CALL_REG           29
+#define MAX_LITERAL_POOL_SIZE  1024
+#define FAIL	               0x80000000
+#define SUCCESS         0
+#define INSN_SIZE       4
+#define INSN16_SIZE     2
+#define RELAX_INST_NUM  3
+
+/* For score5u : div/mul will pop warning message, mmu/alw/asw will pop error message.  */
+#define BAD_ARGS 	          _("bad arguments to instruction")
+#define BAD_PC 		          _("r15 not allowed here")
+#define BAD_COND 	          _("instruction is not conditional")
+#define ERR_NO_ACCUM	          _("acc0 expected")
+#define ERR_FOR_SCORE5U_MUL_DIV   _("div / mul are reserved instructions")
+#define ERR_FOR_SCORE5U_MMU       _("This architecture doesn't support mmu")
+#define ERR_FOR_SCORE5U_ATOMIC    _("This architecture doesn't support atomic instruction")
+#define LONG_LABEL_LEN            _("the label length is longer than 1024");
+#define BAD_SKIP_COMMA            BAD_ARGS
+#define BAD_GARBAGE               _("garbage following instruction");
+
+#define skip_whitespace(str)  while (*(str) == ' ') ++(str)
+
+/* The name of the readonly data section.  */
+#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
+			    ? ".data" \
+			    : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
+			    ? ".rdata" \
+			    : OUTPUT_FLAVOR == bfd_target_coff_flavour \
+			    ? ".rdata" \
+			    : OUTPUT_FLAVOR == bfd_target_elf_flavour \
+			    ? ".rodata" \
+			    : (abort (), ""))
+
+#define RELAX_ENCODE(old, new, type, reloc1, reloc2, opt) \
+  ((relax_substateT) \
+   (((old) << 23) \
+    | ((new) << 16) \
+    | ((type) << 9) \
+    | ((reloc1) << 5) \
+    | ((reloc2) << 1) \
+    | ((opt) ? 1 : 0)))
+
+#define RELAX_OLD(i)       (((i) >> 23) & 0x7f)
+#define RELAX_NEW(i)       (((i) >> 16) & 0x7f)
+#define RELAX_TYPE(i)      (((i) >> 9) & 0x7f)
+#define RELAX_RELOC1(i)    ((valueT) ((i) >> 5) & 0xf)
+#define RELAX_RELOC2(i)    ((valueT) ((i) >> 1) & 0xf)
+#define RELAX_OPT(i)       ((i) & 1)
+#define RELAX_OPT_CLEAR(i) ((i) & ~1)
+
+#define SET_INSN_ERROR(s) (inst.error = (s))
+#define INSN_IS_PCE_P(s)  (strstr (str, "||") != NULL)
+
+#define GET_INSN_CLASS(type) (get_insn_class_from_type (type))
+
+#define GET_INSN_SIZE(type) ((GET_INSN_CLASS (type) == INSN_CLASS_16) \
+                             ? INSN16_SIZE : INSN_SIZE)
+
+/* This array holds the chars that always start a comment.  If the
+   pre-processor is disabled, these aren't very useful.  */
+const char comment_chars[] = "#";
+const char line_comment_chars[] = "#";
+const char line_separator_chars[] = ";";
+
+/* Chars that can be used to separate mant from exp in floating point numbers.  */
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
+
+/* Used to contain constructed error messages.  */
+static char err_msg[255];
+
+fragS *score_fragp = 0;
+static int fix_data_dependency = 0;
+static int warn_fix_data_dependency = 1;
+static int score7 = 1;
+static int university_version = 0;
+
+static int in_my_get_expression = 0;
+
+#define USE_GLOBAL_POINTER_OPT 1
+#define SCORE_BI_ENDIAN
+
+/* Default, pop warning message when using r1.  */
+static int nor1 = 1;
+
+/* Default will do instruction relax, -O0 will set g_opt = 0.  */
+static unsigned int g_opt = 1;
+
+/* The size of the small data section.  */
+static unsigned int g_switch_value = 8;
+
+#ifdef OBJ_ELF
+/* Pre-defined "_GLOBAL_OFFSET_TABLE_"  */
+symbolS *GOT_symbol;
+#endif
+static segT pdr_seg;
+
+enum score_pic_level score_pic = NO_PIC;
+
+#define INSN_NAME_LEN 16
+struct score_it
+{
+  char name[INSN_NAME_LEN];
+  unsigned long instruction;
+  unsigned long relax_inst;
+  int size;
+  int relax_size;
+  enum score_insn_type type;
+  char str[MAX_LITERAL_POOL_SIZE];
+  const char *error;
+  int bwarn;
+  char reg[INSN_NAME_LEN];
+  struct
+  {
+    bfd_reloc_code_real_type type;
+    expressionS exp;
+    int pc_rel;
+  }reloc;
+};
+struct score_it inst;
+
+typedef struct proc
+{
+  symbolS *isym;
+  unsigned long reg_mask;
+  unsigned long reg_offset;
+  unsigned long fpreg_mask;
+  unsigned long leaf;
+  unsigned long frame_offset;
+  unsigned long frame_reg;
+  unsigned long pc_reg;
+}
+procS;
+
+static procS cur_proc;
+static procS *cur_proc_ptr;
+static int numprocs;
+
+#define SCORE7_PIPELINE 7
+#define SCORE5_PIPELINE 5
+static int vector_size = SCORE7_PIPELINE;
+struct score_it dependency_vector[SCORE7_PIPELINE];
+
+/* Relax will need some padding for alignment.  */
+#define RELAX_PAD_BYTE 3
+
+/* Number of littlenums required to hold an extended precision number.  For md_atof.  */
+#define NUM_FLOAT_VALS 8
+#define MAX_LITTLENUMS 6
+LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
+
+/* Structure for a hash table entry for a register.  */
+struct reg_entry
+{
+  const char *name;
+  int number;
+};
+
+static const struct reg_entry score_rn_table[] =
+{
+  {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
+  {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
+  {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
+  {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15},
+  {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19},
+  {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23},
+  {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27},
+  {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31},
+  {NULL, 0}
+};
+
+static const struct reg_entry score_srn_table[] =
+{
+  {"sr0", 0}, {"sr1", 1}, {"sr2", 2},
+  {NULL, 0}
+};
+
+static const struct reg_entry score_crn_table[] =
+{
+  {"cr0", 0}, {"cr1", 1}, {"cr2", 2}, {"cr3", 3},
+  {"cr4", 4}, {"cr5", 5}, {"cr6", 6}, {"cr7", 7},
+  {"cr8", 8}, {"cr9", 9}, {"cr10", 10}, {"cr11", 11},
+  {"cr12", 12}, {"cr13", 13}, {"cr14", 14}, {"cr15", 15},
+  {"cr16", 16}, {"cr17", 17}, {"cr18", 18}, {"cr19", 19},
+  {"cr20", 20}, {"cr21", 21}, {"cr22", 22}, {"cr23", 23},
+  {"cr24", 24}, {"cr25", 25}, {"cr26", 26}, {"cr27", 27},
+  {"cr28", 28}, {"cr29", 29}, {"cr30", 30}, {"cr31", 31},
+  {NULL, 0}
+};
+
+struct reg_map
+{
+  const struct reg_entry *names;
+  int max_regno;
+  struct hash_control *htab;
+  const char *expected;
+};
+
+struct reg_map all_reg_maps[] =
+{
+  {score_rn_table, 31, NULL, N_("S+core register expected")},
+  {score_srn_table, 2, NULL, N_("S+core special-register expected")},
+  {score_crn_table, 31, NULL, N_("S+core co-processor register expected")},
+};
+
+static struct hash_control *score_ops_hsh = NULL;
+
+static struct hash_control *dependency_insn_hsh = NULL;
+
+/* Enumeration matching entries in table above.  */
+enum score_reg_type
+{
+  REG_TYPE_SCORE = 0,
+#define REG_TYPE_FIRST REG_TYPE_SCORE
+  REG_TYPE_SCORE_SR = 1,
+  REG_TYPE_SCORE_CR = 2,
+  REG_TYPE_MAX = 3
+};
+
+typedef struct literalS
+{
+  struct expressionS exp;
+  struct score_it *inst;
+}
+literalT;
+
+literalT literals[MAX_LITERAL_POOL_SIZE];
+
+static void do_ldst_insn (char *);
+static void do_crdcrscrsimm5 (char *);
+static void do_ldst_unalign (char *);
+static void do_ldst_atomic (char *);
+static void do_ldst_cop (char *);
+static void do_macro_li_rdi32 (char *);
+static void do_macro_la_rdi32 (char *);
+static void do_macro_rdi32hi (char *);
+static void do_macro_rdi32lo (char *);
+static void do_macro_mul_rdrsrs (char *);
+static void do_macro_ldst_label (char *);
+static void do_branch (char *);
+static void do_jump (char *);
+static void do_empty (char *);
+static void do_rdrsrs (char *);
+static void do_rdsi16 (char *);
+static void do_rdrssi14 (char *);
+static void do_sub_rdsi16 (char *);
+static void do_sub_rdrssi14 (char *);
+static void do_rdrsi5 (char *);
+static void do_rdrsi14 (char *);
+static void do_rdi16 (char *);
+static void do_xrsi5 (char *);
+static void do_rdrs (char *);
+static void do_rdxrs (char *);
+static void do_rsrs (char *);
+static void do_rdcrs (char *);
+static void do_rdsrs (char *);
+static void do_rd (char *);
+static void do_rs (char *);
+static void do_i15 (char *);
+static void do_xi5x (char *);
+static void do_ceinst (char *);
+static void do_cache (char *);
+static void do16_rdrs (char *);
+static void do16_rs (char *);
+static void do16_xrs (char *);
+static void do16_mv_rdrs (char *);
+static void do16_hrdrs (char *);
+static void do16_rdhrs (char *);
+static void do16_rdi4 (char *);
+static void do16_rdi5 (char *);
+static void do16_xi5 (char *);
+static void do16_ldst_insn (char *);
+static void do16_ldst_imm_insn (char *);
+static void do16_push_pop (char *);
+static void do16_branch (char *);
+static void do16_jump (char *);
+static void do_rdi16_pic (char *);
+static void do_addi_s_pic (char *);
+static void do_addi_u_pic (char *);
+static void do_lw_pic (char *);
+
+static const struct asm_opcode score_ldst_insns[] = 
+{
+  {"lw",        0x20000000, 0x3e000000, 0x2008,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lw",        0x06000000, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lw",        0x0e000000, 0x3e000007, 0x200a,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"lh",        0x22000000, 0x3e000000, 0x2009,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lh",        0x06000001, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lh",        0x0e000001, 0x3e000007, 0x8000,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"lhu",       0x24000000, 0x3e000000, 0x8000,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lhu",       0x06000002, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lhu",       0x0e000002, 0x3e000007, 0x8000,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"lb",        0x26000000, 0x3e000000, 0x8000,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lb",        0x06000003, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lb",        0x0e000003, 0x3e000007, 0x8000,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"sw",        0x28000000, 0x3e000000, 0x200c,     Rd_lvalueRs_SI15,     do_ldst_insn},
+  {"sw",        0x06000004, 0x3e000007, 0x200e,     Rd_lvalueRs_preSI12,  do_ldst_insn},
+  {"sw",        0x0e000004, 0x3e000007, 0x8000,     Rd_lvalueRs_postSI12, do_ldst_insn},
+  {"sh",        0x2a000000, 0x3e000000, 0x200d,     Rd_lvalueRs_SI15,     do_ldst_insn},
+  {"sh",        0x06000005, 0x3e000007, 0x8000,     Rd_lvalueRs_preSI12,  do_ldst_insn},
+  {"sh",        0x0e000005, 0x3e000007, 0x8000,     Rd_lvalueRs_postSI12, do_ldst_insn},
+  {"lbu",       0x2c000000, 0x3e000000, 0x200b,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lbu",       0x06000006, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lbu",       0x0e000006, 0x3e000007, 0x8000,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"sb",        0x2e000000, 0x3e000000, 0x200f,     Rd_lvalueRs_SI15,     do_ldst_insn},
+  {"sb",        0x06000007, 0x3e000007, 0x8000,     Rd_lvalueRs_preSI12,  do_ldst_insn},
+  {"sb",        0x0e000007, 0x3e000007, 0x8000,     Rd_lvalueRs_postSI12, do_ldst_insn},
+};
+
+static const struct asm_opcode score_insns[] = 
+{
+  {"abs",       0x3800000a, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"abs.s",     0x3800004b, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"add",       0x00000010, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"add.c",     0x00000011, 0x3e0003ff, 0x2000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"add.s",     0x38000048, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"addc",      0x00000012, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"addc.c",    0x00000013, 0x3e0003ff, 0x0009,     Rd_Rs_Rs,             do_rdrsrs},
+  {"addi",      0x02000000, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdsi16},
+  {"addi.c",    0x02000001, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdsi16},
+  {"addis",     0x0a000000, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdi16},
+  {"addis.c",   0x0a000001, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdi16},
+  {"addri",     0x10000000, 0x3e000001, 0x8000,     Rd_Rs_SI14,           do_rdrssi14},
+  {"addri.c",   0x10000001, 0x3e000001, 0x8000,     Rd_Rs_SI14,           do_rdrssi14},
+  {"addc!",     0x0009,     0x700f,     0x00000013, Rd_Rs,                do16_rdrs},
+  {"add!",      0x2000,     0x700f,     0x00000011, Rd_Rs,                do16_rdrs},
+  {"addei!",    0x6000    , 0x7087,     0x02000001, Rd_I4,                do16_rdi4},
+  {"subi",      0x02000000, 0x3e0e0001, 0x8000,     Rd_SI16,              do_sub_rdsi16},
+  {"subi.c",    0x02000001, 0x3e0e0001, 0x8000,     Rd_SI16,              do_sub_rdsi16},
+  {"subri",     0x10000000, 0x3e000001, 0x8000,     Rd_Rs_SI14,           do_sub_rdrssi14},
+  {"subri.c",   0x10000001, 0x3e000001, 0x8000,     Rd_Rs_SI14,           do_sub_rdrssi14},
+  {"and",       0x00000020, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"and.c",     0x00000021, 0x3e0003ff, 0x2004,     Rd_Rs_Rs,             do_rdrsrs},
+  {"andi",      0x02080000, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"andi.c",    0x02080001, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"andis",     0x0a080000, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"andis.c",   0x0a080001, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"andri",     0x18000000, 0x3e000001, 0x8000,     Rd_Rs_I14,            do_rdrsi14},
+  {"andri.c",   0x18000001, 0x3e000001, 0x8000,     Rd_Rs_I14,            do_rdrsi14},
+  {"and!",      0x2004,     0x700f,     0x00000021, Rd_Rs,                do16_rdrs},
+  {"bcs",       0x08000000, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bcc",       0x08000400, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bcnz",      0x08003800, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bcsl",      0x08000001, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bccl",      0x08000401, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bcnzl",     0x08003801, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bcs!",      0x4000,     0x7f00,     0x08000000, PC_DISP8div2,         do16_branch},
+  {"bcc!",      0x4100,     0x7f00,     0x08000400, PC_DISP8div2,         do16_branch},
+  {"bcnz!",     0x4e00,     0x7f00,     0x08003800, PC_DISP8div2,         do16_branch},
+  {"beq",       0x08001000, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"beql",      0x08001001, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"beq!",      0x4400,     0x7f00,     0x08001000, PC_DISP8div2,         do16_branch},
+  {"bgtu",      0x08000800, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bgt",       0x08001800, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bge",       0x08002000, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bgtul",     0x08000801, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bgtl",      0x08001801, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bgel",      0x08002001, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bgtu!",     0x4200,     0x7f00,     0x08000800, PC_DISP8div2,         do16_branch},
+  {"bgt!",      0x4600,     0x7f00,     0x08001800, PC_DISP8div2,         do16_branch},
+  {"bge!",      0x4800,     0x7f00,     0x08002000, PC_DISP8div2,         do16_branch},
+  {"bitclr.c",  0x00000029, 0x3e0003ff, 0x6004,     Rd_Rs_I5,             do_rdrsi5},
+  {"bitrev",    0x3800000c, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"bitset.c",  0x0000002b, 0x3e0003ff, 0x6005,     Rd_Rs_I5,             do_rdrsi5},
+  {"bittst.c",  0x0000002d, 0x3e0003ff, 0x6006,     x_Rs_I5,              do_xrsi5},
+  {"bittgl.c",  0x0000002f, 0x3e0003ff, 0x6007,     Rd_Rs_I5,             do_rdrsi5},
+  {"bitclr!",   0x6004,     0x7007,     0x00000029, Rd_I5,                do16_rdi5},
+  {"bitset!",   0x6005,     0x7007,     0x0000002b, Rd_I5,                do16_rdi5},
+  {"bittst!",   0x6006,     0x7007,     0x0000002d, Rd_I5,                do16_rdi5},
+  {"bittgl!",   0x6007,     0x7007,     0x0000002f, Rd_I5,                do16_rdi5},
+  {"bleu",      0x08000c00, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"ble",       0x08001c00, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"blt",       0x08002400, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bleul",     0x08000c01, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"blel",      0x08001c01, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bltl",      0x08002401, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bl",        0x08003c01, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bleu!",     0x4300,     0x7f00,     0x08000c00, PC_DISP8div2,         do16_branch},
+  {"ble!",      0x4700,     0x7f00,     0x08001c00, PC_DISP8div2,         do16_branch},
+  {"blt!",      0x4900,     0x7f00,     0x08002400, PC_DISP8div2,         do16_branch},
+  {"bmi",       0x08002800, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bmil",      0x08002801, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bmi!",      0x00004a00, 0x00007f00, 0x08002800, PC_DISP8div2,         do16_branch},
+  {"bne",       0x08001400, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bnel",      0x08001401, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bne!",      0x4500,     0x7f00,     0x08001400, PC_DISP8div2,         do16_branch},
+  {"bpl",       0x08002c00, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bpll",      0x08002c01, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bpl!",      0x4b00,     0x7f00,     0x08002c00, PC_DISP8div2,         do16_branch},
+  {"brcs",      0x00000008, 0x3e007fff, 0x0004,     x_Rs_x,               do_rs},
+  {"brcc",      0x00000408, 0x3e007fff, 0x0104,     x_Rs_x,               do_rs},
+  {"brgtu",     0x00000808, 0x3e007fff, 0x0204,     x_Rs_x,               do_rs},
+  {"brleu",     0x00000c08, 0x3e007fff, 0x0304,     x_Rs_x,               do_rs},
+  {"breq",      0x00001008, 0x3e007fff, 0x0404,     x_Rs_x,               do_rs},
+  {"brne",      0x00001408, 0x3e007fff, 0x0504,     x_Rs_x,               do_rs},
+  {"brgt",      0x00001808, 0x3e007fff, 0x0604,     x_Rs_x,               do_rs},
+  {"brle",      0x00001c08, 0x3e007fff, 0x0704,     x_Rs_x,               do_rs},
+  {"brge",      0x00002008, 0x3e007fff, 0x0804,     x_Rs_x,               do_rs},
+  {"brlt",      0x00002408, 0x3e007fff, 0x0904,     x_Rs_x,               do_rs},
+  {"brmi",      0x00002808, 0x3e007fff, 0x0a04,     x_Rs_x,               do_rs},
+  {"brpl",      0x00002c08, 0x3e007fff, 0x0b04,     x_Rs_x,               do_rs},
+  {"brvs",      0x00003008, 0x3e007fff, 0x0c04,     x_Rs_x,               do_rs},
+  {"brvc",      0x00003408, 0x3e007fff, 0x0d04,     x_Rs_x,               do_rs},
+  {"brcnz",     0x00003808, 0x3e007fff, 0x0e04,     x_Rs_x,               do_rs},
+  {"br",        0x00003c08, 0x3e007fff, 0x0f04,     x_Rs_x,               do_rs},
+  {"brcsl",     0x00000009, 0x3e007fff, 0x000c,     x_Rs_x,               do_rs},
+  {"brccl",     0x00000409, 0x3e007fff, 0x010c,     x_Rs_x,               do_rs},
+  {"brgtul",    0x00000809, 0x3e007fff, 0x020c,     x_Rs_x,               do_rs},
+  {"brleul",    0x00000c09, 0x3e007fff, 0x030c,     x_Rs_x,               do_rs},
+  {"breql",     0x00001009, 0x3e007fff, 0x040c,     x_Rs_x,               do_rs}, 
+  {"brnel",     0x00001409, 0x3e007fff, 0x050c,     x_Rs_x,               do_rs},
+  {"brgtl",     0x00001809, 0x3e007fff, 0x060c,     x_Rs_x,               do_rs},
+  {"brlel",     0x00001c09, 0x3e007fff, 0x070c,     x_Rs_x,               do_rs},
+  {"brgel",     0x00002009, 0x3e007fff, 0x080c,     x_Rs_x,               do_rs},
+  {"brltl",     0x00002409, 0x3e007fff, 0x090c,     x_Rs_x,               do_rs},
+  {"brmil",     0x00002809, 0x3e007fff, 0x0a0c,     x_Rs_x,               do_rs},
+  {"brpll",     0x00002c09, 0x3e007fff, 0x0b0c,     x_Rs_x,               do_rs},
+  {"brvsl",     0x00003009, 0x3e007fff, 0x0c0c,     x_Rs_x,               do_rs},
+  {"brvcl",     0x00003409, 0x3e007fff, 0x0d0c,     x_Rs_x,               do_rs},
+  {"brcnzl",    0x00003809, 0x3e007fff, 0x0e0c,     x_Rs_x,               do_rs},
+  {"brl",       0x00003c09, 0x3e007fff, 0x0f0c,     x_Rs_x,               do_rs},
+  {"brcs!",     0x0004,     0x7f0f,     0x00000008, x_Rs,                 do16_xrs},
+  {"brcc!",     0x0104,     0x7f0f,     0x00000408, x_Rs,                 do16_xrs},
+  {"brgtu!",    0x0204,     0x7f0f,     0x00000808, x_Rs,                 do16_xrs},
+  {"brleu!",    0x0304,     0x7f0f,     0x00000c08, x_Rs,                 do16_xrs},
+  {"breq!",     0x0404,     0x7f0f,     0x00001008, x_Rs,                 do16_xrs},
+  {"brne!",     0x0504,     0x7f0f,     0x00001408, x_Rs,                 do16_xrs},
+  {"brgt!",     0x0604,     0x7f0f,     0x00001808, x_Rs,                 do16_xrs},
+  {"brle!",     0x0704,     0x7f0f,     0x00001c08, x_Rs,                 do16_xrs},
+  {"brge!",     0x0804,     0x7f0f,     0x00002008, x_Rs,                 do16_xrs},
+  {"brlt!",     0x0904,     0x7f0f,     0x00002408, x_Rs,                 do16_xrs},
+  {"brmi!",     0x0a04,     0x7f0f,     0x00002808, x_Rs,                 do16_xrs},
+  {"brpl!",     0x0b04,     0x7f0f,     0x00002c08, x_Rs,                 do16_xrs},
+  {"brvs!",     0x0c04,     0x7f0f,     0x00003008, x_Rs,                 do16_xrs},
+  {"brvc!",     0x0d04,     0x7f0f,     0x00003408, x_Rs,                 do16_xrs},
+  {"brcnz!",    0x0e04,     0x7f0f,     0x00003808, x_Rs,                 do16_xrs},
+  {"br!",       0x0f04,     0x7f0f,     0x00003c08, x_Rs,                 do16_xrs},
+  {"brcsl!",    0x000c,     0x7f0f,     0x00000009, x_Rs,                 do16_xrs},
+  {"brccl!",    0x010c,     0x7f0f,     0x00000409, x_Rs,                 do16_xrs},
+  {"brgtul!",   0x020c,     0x7f0f,     0x00000809, x_Rs,                 do16_xrs},
+  {"brleul!",   0x030c,     0x7f0f,     0x00000c09, x_Rs,                 do16_xrs},
+  {"breql!",    0x040c,     0x7f0f,     0x00001009, x_Rs,                 do16_xrs},
+  {"brnel!",    0x050c,     0x7f0f,     0x00001409, x_Rs,                 do16_xrs},
+  {"brgtl!",    0x060c,     0x7f0f,     0x00001809, x_Rs,                 do16_xrs},
+  {"brlel!",    0x070c,     0x7f0f,     0x00001c09, x_Rs,                 do16_xrs},
+  {"brgel!",    0x080c,     0x7f0f,     0x00002009, x_Rs,                 do16_xrs},
+  {"brltl!",    0x090c,     0x7f0f,     0x00002409, x_Rs,                 do16_xrs},
+  {"brmil!",    0x0a0c,     0x7f0f,     0x00002809, x_Rs,                 do16_xrs},
+  {"brpll!",    0x0b0c,     0x7f0f,     0x00002c09, x_Rs,                 do16_xrs},
+  {"brvsl!",    0x0c0c,     0x7f0f,     0x00003009, x_Rs,                 do16_xrs},
+  {"brvcl!",    0x0d0c,     0x7f0f,     0x00003409, x_Rs,                 do16_xrs},
+  {"brcnzl!",   0x0e0c,     0x7f0f,     0x00003809, x_Rs,                 do16_xrs},
+  {"brl!",      0x0f0c,     0x7f0f,     0x00003c09, x_Rs,                 do16_xrs},
+  {"bvs",       0x08003000, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bvc",       0x08003400, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bvsl",      0x08003001, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bvcl",      0x08003401, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bvs!",      0x4c00,     0x7f00,     0x08003000, PC_DISP8div2,         do16_branch},
+  {"bvc!",      0x4d00,     0x7f00,     0x08003400, PC_DISP8div2,         do16_branch},
+  {"b!",        0x4f00,     0x7f00,     0x08003c00, PC_DISP8div2,         do16_branch},
+  {"b",         0x08003c00, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"cache",     0x30000000, 0x3ff00000, 0x8000,     OP5_rvalueRs_SI15,    do_cache},
+  {"ceinst",    0x38000000, 0x3e000000, 0x8000,     I5_Rs_Rs_I5_OP5,      do_ceinst},
+  {"clz",       0x3800000d, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"cmpteq.c",  0x00000019, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"cmptmi.c",  0x00100019, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"cmp.c",     0x00300019, 0x3ff003ff, 0x2003,     x_Rs_Rs,              do_rsrs},
+  {"cmpzteq.c", 0x0000001b, 0x3ff07fff, 0x8000,     x_Rs_x,               do_rs},
+  {"cmpztmi.c", 0x0010001b, 0x3ff07fff, 0x8000,     x_Rs_x,               do_rs},
+  {"cmpz.c",    0x0030001b, 0x3ff07fff, 0x8000,     x_Rs_x,               do_rs},
+  {"cmpi.c",    0x02040001, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdsi16},
+  {"cmp!",      0x2003,     0x700f,     0x00300019, Rd_Rs,                do16_rdrs},
+  {"cop1",      0x0c00000c, 0x3e00001f, 0x8000,     Rd_Rs_Rs_imm,         do_crdcrscrsimm5},
+  {"cop2",      0x0c000014, 0x3e00001f, 0x8000,     Rd_Rs_Rs_imm,         do_crdcrscrsimm5},
+  {"cop3",      0x0c00001c, 0x3e00001f, 0x8000,     Rd_Rs_Rs_imm,         do_crdcrscrsimm5},
+  {"drte",      0x0c0000a4, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"extsb",     0x00000058, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extsb.c",   0x00000059, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extsh",     0x0000005a, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extsh.c",   0x0000005b, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extzb",     0x0000005c, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extzb.c",   0x0000005d, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extzh",     0x0000005e, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extzh.c",   0x0000005f, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"jl",        0x04000001, 0x3e000001, 0x8000,     PC_DISP24div2,        do_jump},
+  {"jl!",       0x3001,     0x7001,     0x04000001, PC_DISP11div2,        do16_jump},
+  {"j!",        0x3000,     0x7001,     0x04000000, PC_DISP11div2,        do16_jump},
+  {"j",         0x04000000, 0x3e000001, 0x8000,     PC_DISP24div2,        do_jump},
+  {"lbu!",      0x200b,     0x0000700f, 0x2c000000, Rd_rvalueRs,          do16_ldst_insn},
+  {"lbup!",     0x7003,     0x7007,     0x2c000000, Rd_rvalueBP_I5,       do16_ldst_imm_insn},
+  {"alw",       0x0000000c, 0x3e0003ff, 0x8000,     Rd_rvalue32Rs,        do_ldst_atomic},
+  {"lcb",       0x00000060, 0x3e0003ff, 0x8000,     x_rvalueRs_post4,     do_ldst_unalign},
+  {"lcw",       0x00000062, 0x3e0003ff, 0x8000,     Rd_rvalueRs_post4,    do_ldst_unalign},
+  {"lce",       0x00000066, 0x3e0003ff, 0x8000,     Rd_rvalueRs_post4,    do_ldst_unalign},
+  {"ldc1",      0x0c00000a, 0x3e00001f, 0x8000,     Rd_rvalueRs_SI10,     do_ldst_cop},
+  {"ldc2",      0x0c000012, 0x3e00001f, 0x8000,     Rd_rvalueRs_SI10,     do_ldst_cop},
+  {"ldc3",      0x0c00001a, 0x3e00001f, 0x8000,     Rd_rvalueRs_SI10,     do_ldst_cop},
+  {"lh!",       0x2009,     0x700f,     0x22000000, Rd_rvalueRs,          do16_ldst_insn},
+  {"lhp!",      0x7001,     0x7007,     0x22000000, Rd_rvalueBP_I5,       do16_ldst_imm_insn},
+  {"ldi",       0x020c0000, 0x3e0e0000, 0x5000,     Rd_SI16,              do_rdsi16},
+  {"ldis",      0x0a0c0000, 0x3e0e0000, 0x8000,     Rd_I16,               do_rdi16},
+  {"ldiu!",     0x5000,     0x7000,     0x020c0000, Rd_I8,                do16_ldst_imm_insn},
+  {"lw!",       0x2008,     0x700f,     0x20000000, Rd_rvalueRs,          do16_ldst_insn},
+  {"lwp!",      0x7000,     0x7007,     0x20000000, Rd_rvalueBP_I5,       do16_ldst_imm_insn},
+  {"mfcel",     0x00000448, 0x3e007fff, 0x8000,     Rd_x_x,               do_rd},
+  {"mfcel!",    0x1001,     0x7f0f,     0x00000448, x_Rs,                 do16_rs},
+  {"mad",       0x38000000, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mad.f!",    0x1004,     0x700f,     0x38000080, Rd_Rs,                do16_rdrs},
+  {"madh",      0x38000203, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madh.fs",   0x380002c3, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madh.fs!",  0x100b,     0x700f,     0x380002c3, Rd_Rs,                do16_rdrs},
+  {"madl",      0x38000002, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madl.fs",   0x380000c2, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madl.fs!",  0x100a,     0x700f,     0x380000c2, Rd_Rs,                do16_rdrs},
+  {"madu",      0x38000020, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madu!",     0x1005,     0x700f,     0x38000020, Rd_Rs,                do16_rdrs},
+  {"mad.f",     0x38000080, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"max",       0x38000007, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"mazh",      0x38000303, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mazh.f",    0x38000383, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mazh.f!",   0x1009,     0x700f,     0x3800038c, Rd_Rs,                do16_rdrs},
+  {"mazl",      0x38000102, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mazl.f",    0x38000182, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mazl.f!",   0x1008,     0x700f,     0x38000182, Rd_Rs,                do16_rdrs},
+  {"mfceh",     0x00000848, 0x3e007fff, 0x8000,     Rd_x_x,               do_rd},
+  {"mfceh!",    0x1101,     0x7f0f,     0x00000848, x_Rs,                 do16_rs},
+  {"mfcehl",    0x00000c48, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mfsr",      0x00000050, 0x3e0003ff, 0x8000,     Rd_x_I5,              do_rdsrs},
+  {"mfcr",      0x0c000001, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfc1",      0x0c000009, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfc2",      0x0c000011, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfc3",      0x0c000019, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfcc1",     0x0c00000f, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfcc2",     0x0c000017, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfcc3",     0x0c00001f, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mhfl!",     0x0002,     0x700f,     0x00003c56, Rd_LowRs,             do16_hrdrs},
+  {"min",       0x38000006, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"mlfh!",     0x0001,     0x700f,     0x00003c56, Rd_HighRs,            do16_rdhrs},
+  {"msb",       0x38000001, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msb.f!",    0x1006,     0x700f,     0x38000081, Rd_Rs,                do16_rdrs},
+  {"msbh",      0x38000205, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbh.fs",   0x380002c5, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbh.fs!",  0x100f,     0x700f,     0x380002c5, Rd_Rs,                do16_rdrs},
+  {"msbl",      0x38000004, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbl.fs",   0x380000c4, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbl.fs!",  0x100e,     0x700f,     0x380000c4, Rd_Rs,                do16_rdrs},
+  {"msbu",      0x38000021, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbu!",     0x1007,     0x700f,     0x38000021, Rd_Rs,                do16_rdrs},
+  {"msb.f",     0x38000081, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszh",      0x38000305, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszh.f",    0x38000385, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszh.f!",   0x100d,     0x700f,     0x38000385, Rd_Rs,                do16_rdrs},
+  {"mszl",      0x38000104, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszl.f",    0x38000184, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszl.f!",   0x100c,     0x700f,     0x38000184, Rd_Rs,                do16_rdrs},
+  {"mtcel!",    0x1000,     0x7f0f,     0x0000044a, x_Rs,                 do16_rs},
+  {"mtcel",     0x0000044a, 0x3e007fff, 0x8000,     Rd_x_x,               do_rd},
+  {"mtceh",     0x0000084a, 0x3e007fff, 0x8000,     Rd_x_x,               do_rd},
+  {"mtceh!",    0x1100,     0x7f0f,     0x0000084a, x_Rs,                 do16_rs},
+  {"mtcehl",    0x00000c4a, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mtsr",      0x00000052, 0x3e0003ff, 0x8000,     x_Rs_I5,              do_rdsrs},
+  {"mtcr",      0x0c000000, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtc1",      0x0c000008, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtc2",      0x0c000010, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtc3",      0x0c000018, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtcc1",     0x0c00000e, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtcc2",     0x0c000016, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtcc3",     0x0c00001e, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mul.f!",    0x1002,     0x700f,     0x00000041, Rd_Rs,                do16_rdrs},
+  {"mulu!",     0x1003,     0x700f,     0x00000042, Rd_Rs,                do16_rdrs},
+  {"mvcs",      0x00000056, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvcc",      0x00000456, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvgtu",     0x00000856, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvleu",     0x00000c56, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mveq",      0x00001056, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvne",      0x00001456, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvgt",      0x00001856, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvle",      0x00001c56, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvge",      0x00002056, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvlt",      0x00002456, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvmi",      0x00002856, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvpl",      0x00002c56, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvvs",      0x00003056, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvvc",      0x00003456, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mv",        0x00003c56, 0x3e007fff, 0x0003,     Rd_Rs_x,              do_rdrs},
+  {"mv!",       0x0003,     0x700f,     0x00003c56, Rd_Rs,                do16_mv_rdrs},
+  {"neg",       0x0000001e, 0x3e0003ff, 0x8000,     Rd_x_Rs,              do_rdxrs},
+  {"neg.c",     0x0000001f, 0x3e0003ff, 0x2002,     Rd_x_Rs,              do_rdxrs},
+  {"neg!",      0x2002,     0x700f,     0x0000001f, Rd_Rs,                do16_rdrs},
+  {"nop",       0x00000000, 0x3e0003ff, 0x0000,     NO_OPD,               do_empty},
+  {"not",       0x00000024, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"not.c",     0x00000025, 0x3e0003ff, 0x2006,     Rd_Rs_x,              do_rdrs},
+  {"nop!",      0x0000,     0x700f,     0x00000000, NO16_OPD,               do_empty},
+  {"not!",      0x2006,     0x700f,     0x00000025, Rd_Rs,                do16_rdrs},
+  {"or",        0x00000022, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"or.c",      0x00000023, 0x3e0003ff, 0x2005,     Rd_Rs_Rs,             do_rdrsrs},
+  {"ori",       0x020a0000, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"ori.c",     0x020a0001, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"oris",      0x0a0a0000, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"oris.c",    0x0a0a0001, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"orri",      0x1a000000, 0x3e000001, 0x8000,     Rd_Rs_I14,            do_rdrsi14},
+  {"orri.c",    0x1a000001, 0x3e000001, 0x8000,     Rd_Rs_I14,            do_rdrsi14},
+  {"or!",       0x2005,     0x700f,     0x00000023, Rd_Rs,                do16_rdrs},
+  {"pflush",    0x0000000a, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"pop!",      0x200a,     0x700f,     0x0e000000, Rd_rvalueRs,          do16_push_pop},
+  {"push!",     0x200e,     0x700f,     0x06000004, Rd_lvalueRs,          do16_push_pop},
+  {"ror",       0x00000038, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"ror.c",     0x00000039, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rorc.c",    0x0000003b, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rol",       0x0000003c, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rol.c",     0x0000003d, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rolc.c",    0x0000003f, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rori",      0x00000078, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"rori.c",    0x00000079, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"roric.c",   0x0000007b, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"roli",      0x0000007c, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"roli.c",    0x0000007d, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"rolic.c",   0x0000007f, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"rte",       0x0c000084, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"sb!",       0x200f,     0x700f,     0x2e000000, Rd_lvalueRs,          do16_ldst_insn},
+  {"sbp!",      0x7007,     0x7007,     0x2e000000, Rd_lvalueBP_I5,       do16_ldst_imm_insn},
+  {"asw",       0x0000000e, 0x3e0003ff, 0x8000,     Rd_lvalue32Rs,        do_ldst_atomic},
+  {"scb",       0x00000068, 0x3e0003ff, 0x8000,     Rd_lvalueRs_post4,    do_ldst_unalign},
+  {"scw",       0x0000006a, 0x3e0003ff, 0x8000,     Rd_lvalueRs_post4,    do_ldst_unalign},
+  {"sce",       0x0000006e, 0x3e0003ff, 0x8000,     x_lvalueRs_post4,     do_ldst_unalign},
+  {"sdbbp",     0x00000006, 0x3e0003ff, 0x6002,     x_I5_x,               do_xi5x},
+  {"sdbbp!",    0x6002,     0x7007,     0x00000006, Rd_I5,                do16_xi5},
+  {"sh!",       0x200d,     0x700f,     0x2a000000, Rd_lvalueRs,          do16_ldst_insn},
+  {"shp!",      0x7005,     0x7007,     0x2a000000, Rd_lvalueBP_I5,       do16_ldst_imm_insn},
+  {"sleep",     0x0c0000c4, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"sll",       0x00000030, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sll.c",     0x00000031, 0x3e0003ff, 0x0008,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sll.s",     0x3800004e, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"slli",      0x00000070, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"slli.c",    0x00000071, 0x3e0003ff, 0x6001,     Rd_Rs_I5,             do_rdrsi5},
+  {"sll!",      0x0008,     0x700f,     0x00000031, Rd_Rs,                do16_rdrs},
+  {"slli!",     0x6001,     0x7007,     0x00000071, Rd_I5,                do16_rdi5},
+  {"srl",       0x00000034, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"srl.c",     0x00000035, 0x3e0003ff, 0x000a,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sra",       0x00000036, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sra.c",     0x00000037, 0x3e0003ff, 0x000b,     Rd_Rs_Rs,             do_rdrsrs},
+  {"srli",      0x00000074, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"srli.c",    0x00000075, 0x3e0003ff, 0x6003,     Rd_Rs_I5,             do_rdrsi5},
+  {"srai",      0x00000076, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"srai.c",    0x00000077, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"srl!",      0x000a,     0x700f,     0x00000035, Rd_Rs,                do16_rdrs},
+  {"sra!",      0x000b,     0x700f,     0x00000037, Rd_Rs,                do16_rdrs},
+  {"srli!",     0x6003,     0x7007,     0x00000075, Rd_Rs,                do16_rdi5},
+  {"stc1",      0x0c00000b, 0x3e00001f, 0x8000,     Rd_lvalueRs_SI10,     do_ldst_cop},
+  {"stc2",      0x0c000013, 0x3e00001f, 0x8000,     Rd_lvalueRs_SI10,     do_ldst_cop},
+  {"stc3",      0x0c00001b, 0x3e00001f, 0x8000,     Rd_lvalueRs_SI10,     do_ldst_cop},
+  {"sub",       0x00000014, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sub.c",     0x00000015, 0x3e0003ff, 0x2001,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sub.s",     0x38000049, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"subc",      0x00000016, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"subc.c",    0x00000017, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sub!",      0x2001,     0x700f,     0x00000015, Rd_Rs,                do16_rdrs},
+  {"subei!",    0x6080,     0x7087,     0x02000001, Rd_I4,                do16_rdi4},
+  {"sw!",       0x200c,     0x700f,     0x28000000, Rd_lvalueRs,          do16_ldst_insn},
+  {"swp!",      0x7004,     0x7007,     0x28000000, Rd_lvalueBP_I5,       do16_ldst_imm_insn},
+  {"syscall",   0x00000002, 0x3e0003ff, 0x8000,     I15,                  do_i15},
+  {"tcs",       0x00000054, 0x3e007fff, 0x0005,     NO_OPD,               do_empty},
+  {"tcc",       0x00000454, 0x3e007fff, 0x0105,     NO_OPD,               do_empty},
+  {"tcnz",      0x00003854, 0x3e007fff, 0x0e05,     NO_OPD,               do_empty},
+  {"tcs!",      0x0005,     0x7f0f,     0x00000054, NO16_OPD,             do_empty},
+  {"tcc!",      0x0105,     0x7f0f,     0x00000454, NO16_OPD,             do_empty},
+  {"tcnz!",     0x0e05,     0x7f0f,     0x00003854, NO16_OPD,             do_empty},
+  {"teq",       0x00001054, 0x3e007fff, 0x0405,     NO_OPD,               do_empty},
+  {"teq!",      0x0405,     0x7f0f,     0x00001054, NO16_OPD,             do_empty},
+  {"tgtu",      0x00000854, 0x3e007fff, 0x0205,     NO_OPD,               do_empty},
+  {"tgt",       0x00001854, 0x3e007fff, 0x0605,     NO_OPD,               do_empty},
+  {"tge",       0x00002054, 0x3e007fff, 0x0805,     NO_OPD,               do_empty},
+  {"tgtu!",     0x0205,     0x7f0f,     0x00000854, NO16_OPD,             do_empty},
+  {"tgt!",      0x0605,     0x7f0f,     0x00001854, NO16_OPD,             do_empty},
+  {"tge!",      0x0805,     0x7f0f,     0x00002054, NO16_OPD,             do_empty},
+  {"tleu",      0x00000c54, 0x3e007fff, 0x0305,     NO_OPD,               do_empty},
+  {"tle",       0x00001c54, 0x3e007fff, 0x0705,     NO_OPD,               do_empty},
+  {"tlt",       0x00002454, 0x3e007fff, 0x0905,     NO_OPD,               do_empty},
+  {"stlb",      0x0c000004, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"mftlb",     0x0c000024, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"mtptlb",    0x0c000044, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"mtrtlb",    0x0c000064, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"tleu!",     0x0305,     0x7f0f,     0x00000c54, NO16_OPD,             do_empty},
+  {"tle!",      0x0705,     0x7f0f,     0x00001c54, NO16_OPD,             do_empty},
+  {"tlt!",      0x0905,     0x7f0f,     0x00002454, NO16_OPD,             do_empty},
+  {"tmi",       0x00002854, 0x3e007fff, 0x0a05,     NO_OPD,               do_empty},
+  {"tmi!",      0x0a05,     0x7f0f,     0x00002854, NO16_OPD,             do_empty},
+  {"tne",       0x00001454, 0x3e007fff, 0x0505,     NO_OPD,               do_empty},
+  {"tne!",      0x0505,     0x7f0f,     0x00001454, NO16_OPD,             do_empty},
+  {"tpl",       0x00002c54, 0x3e007fff, 0x0b05,     NO_OPD,               do_empty},
+  {"tpl!",      0x0b05,     0x7f0f,     0x00002c54, NO16_OPD,             do_empty},
+  {"trapcs",    0x00000004, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapcc",    0x00000404, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapgtu",   0x00000804, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapleu",   0x00000c04, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapeq",    0x00001004, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapne",    0x00001404, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapgt",    0x00001804, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"traple",    0x00001c04, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapge",    0x00002004, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"traplt",    0x00002404, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapmi",    0x00002804, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trappl",    0x00002c04, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapvs",    0x00003004, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapvc",    0x00003404, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trap",      0x00003c04, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"tset",      0x00003c54, 0x3e007fff, 0x0f05,     NO_OPD,               do_empty},
+  {"tset!",     0x0f05,     0x00007f0f, 0x00003c54, NO16_OPD,             do_empty},
+  {"tvs",       0x00003054, 0x3e007fff, 0x0c05,     NO_OPD,               do_empty},
+  {"tvc",       0x00003454, 0x3e007fff, 0x0d05,     NO_OPD,               do_empty},
+  {"tvs!",      0x0c05,     0x7f0f,     0x00003054, NO16_OPD,             do_empty},
+  {"tvc!",      0x0d05,     0x7f0f,     0x00003454, NO16_OPD,             do_empty},
+  {"xor",       0x00000026, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"xor.c",     0x00000027, 0x3e0003ff, 0x2007,     Rd_Rs_Rs,             do_rdrsrs},
+  {"xor!",      0x2007,     0x700f,     0x00000027, Rd_Rs,                do16_rdrs},
+  /* Macro instruction.  */
+  {"li",        0x020c0000, 0x3e0e0000, 0x8000,     Insn_Type_SYN,        do_macro_li_rdi32},
+  /* la reg, imm32        -->(1)  ldi  reg, simm16
+                             (2)  ldis reg, %HI(imm32)        
+                                  ori  reg, %LO(imm32) 
+          
+     la reg, symbol       -->(1)  lis  reg, %HI(imm32)
+                                  ori  reg, %LO(imm32)  */
+  {"la",        0x020c0000, 0x3e0e0000, 0x8000,     Insn_Type_SYN,        do_macro_la_rdi32},
+  {"div",       0x00000044, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"divu",      0x00000046, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"rem",       0x00000044, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"remu",      0x00000046, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"mul",       0x00000040, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"mulu",      0x00000042, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"maz",       0x00000040, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"mazu",      0x00000042, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"mul.f",     0x00000041, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"maz.f",     0x00000041, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"lb",        INSN_LB,    0x00000000, 0x8000,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"lbu",       INSN_LBU,   0x00000000, 0x200b,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"lh",        INSN_LH,    0x00000000, 0x2009,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"lhu",       INSN_LHU,   0x00000000, 0x8000,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"lw",        INSN_LW,    0x00000000, 0x2008,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"sb",        INSN_SB,    0x00000000, 0x200f,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"sh",        INSN_SH,    0x00000000, 0x200d,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"sw",        INSN_SW,    0x00000000, 0x200c,     Insn_Type_SYN,        do_macro_ldst_label},
+  /* Assembler use internal.  */
+  {"ld_i32hi",  0x0a0c0000, 0x3e0e0000, 0x8000,     Insn_internal, do_macro_rdi32hi},
+  {"ld_i32lo",  0x020a0000, 0x3e0e0001, 0x8000,     Insn_internal, do_macro_rdi32lo},
+  {"ldis_pic",  0x0a0c0000, 0x3e0e0000, 0x5000,     Insn_internal, do_rdi16_pic},
+  {"addi_s_pic",0x02000000, 0x3e0e0001, 0x8000,     Insn_internal, do_addi_s_pic},
+  {"addi_u_pic",0x02000000, 0x3e0e0001, 0x8000,     Insn_internal, do_addi_u_pic},
+  {"lw_pic",    0x20000000, 0x3e000000, 0x8000,     Insn_internal, do_lw_pic},
+};
+
+/* Next free entry in the pool.  */
+int next_literal_pool_place = 0;
+
+/* Next literal pool number.  */
+int lit_pool_num = 1;
+symbolS *current_poolP = NULL;
+
+
+static int
+end_of_line (char *str)
+{
+  int retval = SUCCESS;
+
+  skip_whitespace (str);
+  if (*str != '\0')
+    {
+      retval = (int) FAIL;
+
+      if (!inst.error)
+        inst.error = BAD_GARBAGE;
+    }
+
+  return retval;
+}
+
+static int
+score_reg_parse (char **ccp, struct hash_control *htab)
+{
+  char *start = *ccp;
+  char c;
+  char *p;
+  struct reg_entry *reg;
+
+  p = start;
+  if (!ISALPHA (*p) || !is_name_beginner (*p))
+    return (int) FAIL;
+
+  c = *p++;
+
+  while (ISALPHA (c) || ISDIGIT (c) || c == '_')
+    c = *p++;
+
+  *--p = 0;
+  reg = (struct reg_entry *) hash_find (htab, start);
+  *p = c;
+
+  if (reg)
+    {
+      *ccp = p;
+      return reg->number;
+    }
+  return (int) FAIL;
+}
+
+/* If shift <= 0, only return reg.  */
+
+static int
+reg_required_here (char **str, int shift, enum score_reg_type reg_type)
+{
+  static char buff[MAX_LITERAL_POOL_SIZE];
+  int reg = (int) FAIL;
+  char *start = *str;
+
+  if ((reg = score_reg_parse (str, all_reg_maps[reg_type].htab)) != (int) FAIL)
+    {
+      if (reg_type == REG_TYPE_SCORE)
+        {
+          if ((reg == 1) && (nor1 == 1) && (inst.bwarn == 0))
+            {
+              as_warn (_("Using temp register(r1)"));
+              inst.bwarn = 1;
+            }
+        }
+      if (shift >= 0)
+	{
+          if (reg_type == REG_TYPE_SCORE_CR)
+	    strcpy (inst.reg, score_crn_table[reg].name);
+          else if (reg_type == REG_TYPE_SCORE_SR)
+	    strcpy (inst.reg, score_srn_table[reg].name);
+          else
+	    strcpy (inst.reg, "");
+
+          inst.instruction |= reg << shift;
+	}
+    }
+  else
+    {
+      *str = start;
+      sprintf (buff, _("register expected, not '%.100s'"), start);
+      inst.error = buff;
+    }
+
+  return reg;
+}
+
+static int
+skip_past_comma (char **str)
+{
+  char *p = *str;
+  char c;
+  int comma = 0;
+
+  while ((c = *p) == ' ' || c == ',')
+    {
+      p++;
+      if (c == ',' && comma++)
+        {
+          inst.error = BAD_SKIP_COMMA;
+          return (int) FAIL;
+        }
+    }
+
+  if ((c == '\0') || (comma == 0))
+    {
+      inst.error = BAD_SKIP_COMMA;
+      return (int) FAIL;
+    }
+
+  *str = p;
+  return comma ? SUCCESS : (int) FAIL;
+}
+
+static void
+do_rdrsrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      if ((((inst.instruction >> 15) & 0x10) == 0)
+          && (((inst.instruction >> 10) & 0x10) == 0)
+          && (((inst.instruction >> 20) & 0x10) == 0)
+          && (inst.relax_inst != 0x8000)
+          && (((inst.instruction >> 20) & 0xf) == ((inst.instruction >> 15) & 0xf)))
+        {
+          inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4)
+            | (((inst.instruction >> 15) & 0xf) << 8);
+          inst.relax_size = 2;
+        }
+      else
+        {
+          inst.relax_inst = 0x8000;
+        }
+    }
+}
+
+static int
+walk_no_bignums (symbolS * sp)
+{
+  if (symbol_get_value_expression (sp)->X_op == O_big)
+    return 1;
+
+  if (symbol_get_value_expression (sp)->X_add_symbol)
+    return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
+	    || (symbol_get_value_expression (sp)->X_op_symbol
+		&& walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));  
+
+  return 0;
+}
+
+static int
+my_get_expression (expressionS * ep, char **str)
+{
+  char *save_in;
+  segT seg;
+
+  save_in = input_line_pointer;
+  input_line_pointer = *str;
+  in_my_get_expression = 1;
+  seg = expression (ep);
+  in_my_get_expression = 0;
+
+  if (ep->X_op == O_illegal)
+    {
+      *str = input_line_pointer;
+      input_line_pointer = save_in;
+      inst.error = _("illegal expression");
+      return (int) FAIL;
+    }
+  /* Get rid of any bignums now, so that we don't generate an error for which
+     we can't establish a line number later on.  Big numbers are never valid
+     in instructions, which is where this routine is always called.  */
+  if (ep->X_op == O_big
+      || (ep->X_add_symbol
+          && (walk_no_bignums (ep->X_add_symbol)
+              || (ep->X_op_symbol && walk_no_bignums (ep->X_op_symbol)))))
+    {
+      inst.error = _("invalid constant");
+      *str = input_line_pointer;
+      input_line_pointer = save_in;
+      return (int) FAIL;
+    }
+
+  if ((ep->X_add_symbol != NULL)
+      && (inst.type != PC_DISP19div2)
+      && (inst.type != PC_DISP8div2)
+      && (inst.type != PC_DISP24div2)
+      && (inst.type != PC_DISP11div2)
+      && (inst.type != Insn_Type_SYN)
+      && (inst.type != Rd_rvalueRs_SI15)
+      && (inst.type != Rd_lvalueRs_SI15)
+      && (inst.type != Insn_internal))
+    {
+      inst.error = BAD_ARGS;
+      *str = input_line_pointer;
+      input_line_pointer = save_in;
+      return (int) FAIL;
+    }
+
+  *str = input_line_pointer;
+  input_line_pointer = save_in;
+  return SUCCESS;
+}
+
+/* Check if an immediate is valid.  If so, convert it to the right format.  */
+
+static int
+validate_immediate (int val, unsigned int data_type, int hex_p)
+{
+  switch (data_type)
+    {
+    case _VALUE_HI16:
+      {
+        int val_hi = ((val & 0xffff0000) >> 16);
+
+        if (score_df_range[data_type].range[0] <= val_hi
+            && val_hi <= score_df_range[data_type].range[1])
+	  return val_hi;
+      }
+      break;
+
+    case _VALUE_LO16:
+      {
+        int val_lo = (val & 0xffff);
+
+        if (score_df_range[data_type].range[0] <= val_lo
+            && val_lo <= score_df_range[data_type].range[1])
+	  return val_lo;
+      }
+      break;
+
+    case _VALUE:
+      return val;
+      break;
+
+    case _SIMM14:
+      if (hex_p == 1)
+        {
+          if (!(val >= -0x2000 && val <= 0x3fff))
+            {
+              return (int) FAIL;
+            }
+        }
+      else
+        {
+          if (!(val >= -8192 && val <= 8191))
+            {
+              return (int) FAIL;
+            }
+        }
+
+      return val;
+      break;
+
+    case _SIMM16_NEG:
+      if (hex_p == 1)
+        {
+          if (!(val >= -0x7fff && val <= 0xffff && val != 0x8000))
+            {
+              return (int) FAIL;
+            }
+        }
+      else
+        {
+          if (!(val >= -32767 && val <= 32768))
+            {
+              return (int) FAIL;
+            }
+        }
+
+      val = -val;
+      return val;
+      break;
+
+    default:
+      if (data_type == _SIMM14_NEG || data_type == _IMM16_NEG)
+	val = -val;
+
+      if (score_df_range[data_type].range[0] <= val
+          && val <= score_df_range[data_type].range[1])
+	return val;
+
+      break;
+    }
+
+  return (int) FAIL;
+}
+
+static int
+data_op2 (char **str, int shift, enum score_data_type data_type)
+{
+  int value;
+  char data_exp[MAX_LITERAL_POOL_SIZE];
+  char *dataptr;
+  int cnt = 0;
+  char *pp = NULL;
+
+  skip_whitespace (*str);
+  inst.error = NULL;
+  dataptr = * str;
+
+  /* Set hex_p to zero.  */
+  int hex_p = 0;
+
+  while ((*dataptr != '\0') && (*dataptr != '|') && (cnt <= MAX_LITERAL_POOL_SIZE))     /* 0x7c = ='|' */
+    {
+      data_exp[cnt] = *dataptr;
+      dataptr++;
+      cnt++;
+    }
+
+  data_exp[cnt] = '\0';
+  pp = (char *)&data_exp;
+
+  if (*dataptr == '|')          /* process PCE */
+    {
+      if (my_get_expression (&inst.reloc.exp, &pp) == (int) FAIL)
+        return (int) FAIL;
+      end_of_line (pp);
+      if (inst.error != 0)
+        return (int) FAIL;       /* to ouptut_inst to printf out the error */
+      *str = dataptr;
+    }
+  else                          /* process  16 bit */
+    {
+      if (my_get_expression (&inst.reloc.exp, str) == (int) FAIL)
+        {
+          return (int) FAIL;
+        }
+
+      dataptr = (char *)data_exp;
+      for (; *dataptr != '\0'; dataptr++)
+        {
+          *dataptr = TOLOWER (*dataptr);
+          if (*dataptr == '!' || *dataptr == ' ')
+            break;
+        }
+      dataptr = (char *)data_exp;
+
+      if ((dataptr != NULL)
+          && (((strstr (dataptr, "0x")) != NULL)
+              || ((strstr (dataptr, "0X")) != NULL)))
+        {
+          hex_p = 1;
+          if ((data_type != _SIMM16_LA)
+              && (data_type != _VALUE_HI16)
+              && (data_type != _VALUE_LO16)
+              && (data_type != _IMM16)
+              && (data_type != _IMM15)
+              && (data_type != _IMM14)
+              && (data_type != _IMM4)
+              && (data_type != _IMM5)
+              && (data_type != _IMM8)
+              && (data_type != _IMM5_RSHIFT_1)
+              && (data_type != _IMM5_RSHIFT_2)
+              && (data_type != _SIMM14)
+              && (data_type != _SIMM14_NEG)
+              && (data_type != _SIMM16_NEG)
+              && (data_type != _IMM10_RSHIFT_2)
+              && (data_type != _GP_IMM15))
+            {
+              data_type += 24;
+            }
+        }
+
+      if ((inst.reloc.exp.X_add_number == 0)
+          && (inst.type != Insn_Type_SYN)
+          && (inst.type != Rd_rvalueRs_SI15)
+          && (inst.type != Rd_lvalueRs_SI15)
+          && (inst.type != Insn_internal)
+          && (((*dataptr >= 'a') && (*dataptr <= 'z'))
+             || ((*dataptr == '0') && (*(dataptr + 1) == 'x') && (*(dataptr + 2) != '0'))
+             || ((*dataptr == '+') && (*(dataptr + 1) != '0'))
+             || ((*dataptr == '-') && (*(dataptr + 1) != '0'))))
+        {
+          inst.error = BAD_ARGS;
+          return (int) FAIL;
+        }
+    }
+
+  if ((inst.reloc.exp.X_add_symbol)
+      && ((data_type == _SIMM16)
+          || (data_type == _SIMM16_NEG)
+          || (data_type == _IMM16_NEG)
+          || (data_type == _SIMM14)
+          || (data_type == _SIMM14_NEG)
+          || (data_type == _IMM5)
+          || (data_type == _IMM14)
+          || (data_type == _IMM20)
+          || (data_type == _IMM16)
+          || (data_type == _IMM15)
+          || (data_type == _IMM4)))
+    {
+      inst.error = BAD_ARGS;
+      return (int) FAIL;
+    }
+
+  if (inst.reloc.exp.X_add_symbol)
+    {
+      switch (data_type)
+        {
+        case _SIMM16_LA:
+          return (int) FAIL;
+        case _VALUE_HI16:
+          inst.reloc.type = BFD_RELOC_HI16_S;
+          inst.reloc.pc_rel = 0;
+          break;
+        case _VALUE_LO16:
+          inst.reloc.type = BFD_RELOC_LO16;
+          inst.reloc.pc_rel = 0;
+          break;
+        case _GP_IMM15:
+          inst.reloc.type = BFD_RELOC_SCORE_GPREL15;
+          inst.reloc.pc_rel = 0;
+          break;
+        case _SIMM16_pic:
+        case _IMM16_LO16_pic:
+          inst.reloc.type = BFD_RELOC_SCORE_GOT_LO16;
+          inst.reloc.pc_rel = 0;
+          break;
+        default:
+          inst.reloc.type = BFD_RELOC_32;
+          inst.reloc.pc_rel = 0;
+          break;
+        }
+    }
+  else
+    {
+      if (data_type == _IMM16_pic)
+	{
+          inst.reloc.type = BFD_RELOC_SCORE_DUMMY_HI16;
+          inst.reloc.pc_rel = 0;
+	}
+
+      if (data_type == _SIMM16_LA && inst.reloc.exp.X_unsigned == 1)
+        {
+          value = validate_immediate (inst.reloc.exp.X_add_number, _SIMM16_LA_POS, hex_p);
+          if (value == (int) FAIL)       /* for advance to check if this is ldis */
+            if ((inst.reloc.exp.X_add_number & 0xffff) == 0)
+              {
+                inst.instruction |= 0x8000000;
+                inst.instruction |= ((inst.reloc.exp.X_add_number >> 16) << 1) & 0x1fffe;
+                return SUCCESS;
+              }
+        }
+      else
+        {
+          value = validate_immediate (inst.reloc.exp.X_add_number, data_type, hex_p);
+        }
+
+      if (value == (int) FAIL)
+        {
+          if ((data_type != _SIMM14_NEG) && (data_type != _SIMM16_NEG) && (data_type != _IMM16_NEG))
+            {
+              sprintf (err_msg,
+                       _("invalid constant: %d bit expression not in range %d..%d"),
+                       score_df_range[data_type].bits,
+                       score_df_range[data_type].range[0], score_df_range[data_type].range[1]);
+            }
+          else
+            {
+              sprintf (err_msg,
+                       _("invalid constant: %d bit expression not in range %d..%d"),
+                       score_df_range[data_type].bits,
+                       -score_df_range[data_type].range[1], -score_df_range[data_type].range[0]);
+            }
+
+          inst.error = err_msg;
+          return (int) FAIL;
+        }
+
+      if ((score_df_range[data_type].range[0] != 0) || (data_type == _IMM5_RANGE_8_31))
+        {
+          value &= (1 << score_df_range[data_type].bits) - 1;
+        }
+
+      inst.instruction |= value << shift;
+    }
+
+  if ((inst.instruction & 0xf0000000) == 0x30000000)
+    {
+      if ((((inst.instruction >> 20) & 0x1F) != 0)
+          && (((inst.instruction >> 20) & 0x1F) != 1)
+          && (((inst.instruction >> 20) & 0x1F) != 2)
+          && (((inst.instruction >> 20) & 0x1F) != 3)
+          && (((inst.instruction >> 20) & 0x1F) != 4)
+          && (((inst.instruction >> 20) & 0x1F) != 8)
+          && (((inst.instruction >> 20) & 0x1F) != 9)
+          && (((inst.instruction >> 20) & 0x1F) != 0xa)
+          && (((inst.instruction >> 20) & 0x1F) != 0xb)
+          && (((inst.instruction >> 20) & 0x1F) != 0xc)
+          && (((inst.instruction >> 20) & 0x1F) != 0xd)
+          && (((inst.instruction >> 20) & 0x1F) != 0xe)
+          && (((inst.instruction >> 20) & 0x1F) != 0x10)
+          && (((inst.instruction >> 20) & 0x1F) != 0x11)
+          && (((inst.instruction >> 20) & 0x1F) != 0x18)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1A)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1B)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1d)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1e)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1f))
+        {
+          inst.error = _("invalid constant: bit expression not defined");
+          return (int) FAIL;
+        }
+    }
+
+  return SUCCESS;
+}
+
+/* Handle addi/addi.c/addis.c/cmpi.c/addis.c/ldi.  */
+
+static void
+do_rdsi16 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 1, _SIMM16) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  /* ldi.  */
+  if ((inst.instruction & 0x20c0000) == 0x20c0000)
+    {
+      if ((((inst.instruction >> 20) & 0x10) == 0x10) || ((inst.instruction & 0x1fe00) != 0))
+        {
+          inst.relax_inst = 0x8000;
+        }
+      else
+        {
+          inst.relax_inst |= (inst.instruction >> 1) & 0xff;
+          inst.relax_inst |= (((inst.instruction >> 20) & 0xf) << 8);
+          inst.relax_size = 2;
+        }
+    }
+  else if (((inst.instruction >> 20) & 0x10) == 0x10)
+    {
+      inst.relax_inst = 0x8000;
+    }
+}
+
+/* Handle subi/subi.c.  */
+
+static void
+do_sub_rdsi16 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _SIMM16_NEG) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle addri/addri.c.  */
+
+static void
+do_rdrssi14 (char *str)         /* -(2^13)~((2^13)-1) */
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reg_required_here (&str, 15, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL)
+    data_op2 (&str, 1, _SIMM14);
+}
+
+/* Handle subri.c/subri.  */
+static void
+do_sub_rdrssi14 (char *str)     /* -(2^13)~((2^13)-1) */
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reg_required_here (&str, 15, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _SIMM14_NEG) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle bitclr.c/bitset.c/bittgl.c/slli.c/srai.c/srli.c/roli.c/rori.c/rolic.c.  */
+static void
+do_rdrsi5 (char *str)           /* 0~((2^14)-1) */
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 10, _IMM5) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((((inst.instruction >> 20) & 0x1f) == ((inst.instruction >> 15) & 0x1f))
+      && (inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0x1f) << 3) | (((inst.instruction >> 15) & 0xf) << 8);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+/* Handle andri/orri/andri.c/orri.c.  */
+
+static void
+do_rdrsi14 (char *str)          /* 0 ~ ((2^14)-1)  */
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reg_required_here (&str, 15, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _IMM14) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle bittst.c.  */
+static void
+do_xrsi5 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 10, _IMM5) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0x1f) << 3) | (((inst.instruction >> 15) & 0xf) << 8);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+/* Handle addis/andi/ori/andis/oris/ldis.  */
+static void
+do_rdi16 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 1, _IMM16) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+  /*
+  if (((inst.instruction & 0xa0dfffe) != 0xa0c0000) || ((((inst.instruction >> 20) & 0x1f) & 0x10) == 0x10))
+    inst.relax_inst = 0x8000;
+  else
+    inst.relax_size = 2;
+  */
+}
+
+static void
+do_macro_rdi32hi (char *str)
+{
+  skip_whitespace (str);
+
+  /* Do not handle end_of_line().  */
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL)
+    data_op2 (&str, 1, _VALUE_HI16);
+}
+
+static void
+do_macro_rdi32lo (char *str)
+{
+  skip_whitespace (str);
+
+  /* Do not handle end_of_line().  */
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL)
+    data_op2 (&str, 1, _VALUE_LO16);
+}
+
+/* Handle ldis_pic.  */
+
+static void
+do_rdi16_pic (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _IMM16_pic) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle addi_s_pic to generate R_SCORE_GOT_LO16 .  */
+
+static void
+do_addi_s_pic (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _SIMM16_pic) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle addi_u_pic to generate R_SCORE_GOT_LO16 .  */
+
+static void
+do_addi_u_pic (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _IMM16_LO16_pic) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle mfceh/mfcel/mtceh/mtchl.  */
+
+static void
+do_rd (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL)
+    end_of_line (str);
+}
+
+static void
+do_rs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 8) | (((inst.instruction >> 15) & 0xf) << 4);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+static void
+do_i15 (char *str)
+{
+  skip_whitespace (str);
+
+  if (data_op2 (&str, 10, _IMM15) != (int) FAIL)
+    end_of_line (str);
+}
+
+static void
+do_xi5x (char *str)
+{
+  skip_whitespace (str);
+
+  if (data_op2 (&str, 15, _IMM5) == (int) FAIL || end_of_line (str) == (int) FAIL)
+    return;
+
+  if (inst.relax_inst != 0x8000)
+    {
+      inst.relax_inst |= (((inst.instruction >> 15) & 0x1f) << 3);
+      inst.relax_size = 2;
+    }
+}
+
+static void
+do_rdrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if (inst.relax_inst != 0x8000)
+    {
+      if (((inst.instruction & 0x7f) == 0x56))  /* adjust mv -> mv! / mlfh! / mhfl! */
+        {
+          /* mlfh */
+          if ((((inst.instruction >> 15) & 0x10) != 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
+            {
+              inst.relax_inst = 0x00000001 | (((inst.instruction >> 15) & 0xf) << 4)
+                | (((inst.instruction >> 20) & 0xf) << 8);
+              inst.relax_size = 2;
+            }
+          /* mhfl */
+          else if ((((inst.instruction >> 15) & 0x10) == 0x0) && ((inst.instruction >> 20) & 0x10) != 0)
+            {
+              inst.relax_inst = 0x00000002 | (((inst.instruction >> 15) & 0xf) << 4)
+                | (((inst.instruction >> 20) & 0xf) << 8);
+              inst.relax_size = 2;
+            }
+          else if ((((inst.instruction >> 15) & 0x10) == 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
+            {
+              inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                | (((inst.instruction >> 20) & 0xf) << 8);
+              inst.relax_size = 2;
+            }
+          else
+            {
+              inst.relax_inst = 0x8000;
+            }
+        }
+      else if ((((inst.instruction >> 15) & 0x10) == 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
+        {
+          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+            | (((inst.instruction >> 20) & 0xf) << 8);
+          inst.relax_size = 2;
+        }
+      else
+        {
+          inst.relax_inst = 0x8000;
+        }
+    }
+}
+
+/* Handle mfcr/mtcr.  */
+static void
+do_rdcrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reg_required_here (&str, 15, REG_TYPE_SCORE_CR) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle mfsr/mtsr.  */
+
+static void
+do_rdsrs (char *str)
+{
+  skip_whitespace (str);
+
+  /* mfsr */
+  if ((inst.instruction & 0xff) == 0x50)
+    {
+      if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+          && skip_past_comma (&str) != (int) FAIL
+          && reg_required_here (&str, 10, REG_TYPE_SCORE_SR) != (int) FAIL)
+	end_of_line (str);
+    }
+  else
+    {
+      if (reg_required_here (&str, 15, REG_TYPE_SCORE) != (int) FAIL
+          && skip_past_comma (&str) != (int) FAIL)
+	reg_required_here (&str, 10, REG_TYPE_SCORE_SR);
+    }
+}
+
+/* Handle neg.  */
+
+static void
+do_rdxrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 10) & 0x10) == 0)
+      && (((inst.instruction >> 20) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4) | (((inst.instruction >> 20) & 0xf) << 8);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+/* Handle cmp.c/cmp<cond>.  */
+static void
+do_rsrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 20) & 0x1f) == 3)
+      && (((inst.instruction >> 10) & 0x10) == 0) && (((inst.instruction >> 15) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4) | (((inst.instruction >> 15) & 0xf) << 8);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+static void
+do_ceinst (char *str)
+{
+  char *strbak;
+
+  strbak = str;
+  skip_whitespace (str);
+
+  if (data_op2 (&str, 20, _IMM5) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 5, _IMM5) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 0, _IMM5) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      str = strbak;
+      if (data_op2 (&str, 0, _IMM25) == (int) FAIL)
+	return;
+    }
+}
+
+static int
+reglow_required_here (char **str, int shift)
+{
+  static char buff[MAX_LITERAL_POOL_SIZE];
+  int reg;
+  char *start = *str;
+
+  if ((reg = score_reg_parse (str, all_reg_maps[REG_TYPE_SCORE].htab)) != (int) FAIL)
+    {
+      if ((reg == 1) && (nor1 == 1) && (inst.bwarn == 0))
+        {
+          as_warn (_("Using temp register(r1)"));
+          inst.bwarn = 1;
+        }
+      if (reg < 16)
+        {
+          if (shift >= 0)
+            inst.instruction |= reg << shift;
+
+          return reg;
+        }
+    }
+
+  /* Restore the start point, we may have got a reg of the wrong class.  */
+  *str = start;
+  sprintf (buff, _("low register(r0-r15)expected, not '%.100s'"), start);
+  inst.error = buff;
+  return (int) FAIL;
+}
+
+/* Handle addc!/add!/and!/cmp!/neg!/not!/or!/sll!/srl!/sra!/xor!/sub!.  */
+static void
+do16_rdrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 8) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reglow_required_here (&str, 4) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      if ((inst.instruction & 0x700f) == 0x2003)        /* cmp!  */
+        {
+          inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 15)
+            | (((inst.instruction >> 4) & 0xf) << 10);
+        }
+      else if ((inst.instruction & 0x700f) == 0x2006)   /* not!  */
+	{
+	  inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+	    | (((inst.instruction >> 4) & 0xf) << 15);
+	}
+      else
+        {
+          inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+            | (((inst.instruction >> 8) & 0xf) << 15) | (((inst.instruction >> 4) & 0xf) << 10);
+        }
+      inst.relax_size = 4;
+    }
+}
+
+static void
+do16_rs (char *str)
+{
+  int rd = 0;
+
+  skip_whitespace (str);
+
+  if ((rd = reglow_required_here (&str, 4)) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      inst.relax_inst |= rd << 20;
+      inst.relax_size = 4;
+    }
+}
+
+/* Handle br!/brl!.  */
+static void
+do16_xrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 4) == (int) FAIL || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 10)
+                      | (((inst.instruction >> 4) & 0xf) << 15);
+      inst.relax_size = 4;
+    }
+}
+
+static int
+reghigh_required_here (char **str, int shift)
+{
+  static char buff[MAX_LITERAL_POOL_SIZE];
+  int reg;
+  char *start = *str;
+
+  if ((reg = score_reg_parse (str, all_reg_maps[REG_TYPE_SCORE].htab)) != (int) FAIL)
+    {
+      if (15 < reg && reg < 32)
+        {
+          if (shift >= 0)
+            inst.instruction |= (reg & 0xf) << shift;
+
+          return reg;
+        }
+    }
+
+  *str = start;
+  sprintf (buff, _("high register(r16-r31)expected, not '%.100s'"), start);
+  inst.error = buff;
+  return (int) FAIL;
+}
+
+/* Handle mhfl!.  */
+static void
+do16_hrdrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reghigh_required_here (&str, 8) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reglow_required_here (&str, 4) != (int) FAIL
+      && end_of_line (str) != (int) FAIL)
+    {
+      inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
+        | (((inst.instruction >> 4) & 0xf) << 15) | (0xf << 10);
+      inst.relax_size = 4;
+    }
+}
+
+/* Handle mlfh!.  */
+static void
+do16_rdhrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 8) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reghigh_required_here (&str, 4) != (int) FAIL
+      && end_of_line (str) != (int) FAIL)
+    {
+      inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+        | ((((inst.instruction >> 4) & 0xf) | 0x10) << 15) | (0xf << 10);
+      inst.relax_size = 4;
+    }
+}
+
+/* We need to be able to fix up arbitrary expressions in some statements.
+   This is so that we can handle symbols that are an arbitrary distance from
+   the pc.  The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
+   which returns part of an address in a form which will be valid for
+   a data instruction.  We do this by pushing the expression into a symbol
+   in the expr_section, and creating a fix for that.  */
+static fixS *
+fix_new_score (fragS * frag, int where, short int size, expressionS * exp, int pc_rel, int reloc)
+{
+  fixS *new_fix;
+
+  switch (exp->X_op)
+    {
+    case O_constant:
+    case O_symbol:
+    case O_add:
+    case O_subtract:
+      new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
+      break;
+    default:
+      new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, pc_rel, reloc);
+      break;
+    }
+  return new_fix;
+}
+
+static void
+init_dependency_vector (void)
+{
+  int i;
+
+  for (i = 0; i < vector_size; i++)
+    memset (&dependency_vector[i], '\0', sizeof (dependency_vector[i]));
+
+  return;
+}
+
+static enum insn_type_for_dependency
+dependency_type_from_insn (char *insn_name)
+{
+  char name[INSN_NAME_LEN];
+  const struct insn_to_dependency *tmp;
+
+  strcpy (name, insn_name);
+  tmp = (const struct insn_to_dependency *) hash_find (dependency_insn_hsh, name);
+
+  if (tmp)
+    return tmp->type;
+
+  return D_all_insn;
+}
+
+static int
+check_dependency (char *pre_insn, char *pre_reg,
+                  char *cur_insn, char *cur_reg, int *warn_or_error)
+{
+  int bubbles = 0;
+  unsigned int i;
+  enum insn_type_for_dependency pre_insn_type;
+  enum insn_type_for_dependency cur_insn_type;
+
+  pre_insn_type = dependency_type_from_insn (pre_insn);
+  cur_insn_type = dependency_type_from_insn (cur_insn);
+
+  for (i = 0; i < sizeof (data_dependency_table) / sizeof (data_dependency_table[0]); i++)
+    {
+      if ((pre_insn_type == data_dependency_table[i].pre_insn_type)
+          && (D_all_insn == data_dependency_table[i].cur_insn_type
+              || cur_insn_type == data_dependency_table[i].cur_insn_type)
+          && (strcmp (data_dependency_table[i].pre_reg, "") == 0
+              || strcmp (data_dependency_table[i].pre_reg, pre_reg) == 0)
+          && (strcmp (data_dependency_table[i].cur_reg, "") == 0
+              || strcmp (data_dependency_table[i].cur_reg, cur_reg) == 0))
+        {
+          bubbles = (score7) ? data_dependency_table[i].bubblenum_7 : data_dependency_table[i].bubblenum_5;
+          *warn_or_error = data_dependency_table[i].warn_or_error;
+          break;
+        }
+    }
+
+  return bubbles;
+}
+
+static void
+build_one_frag (struct score_it one_inst)
+{
+  char *p;
+  int relaxable_p = g_opt;
+  int relax_size = 0;
+
+  /* Start a new frag if frag_now is not empty.  */
+  if (frag_now_fix () != 0)
+    {
+      if (!frag_now->tc_frag_data.is_insn)
+	frag_wane (frag_now);
+
+      frag_new (0);
+    }
+  frag_grow (20);
+
+  p = frag_more (one_inst.size);
+  md_number_to_chars (p, one_inst.instruction, one_inst.size);
+
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (one_inst.size);
+#endif
+
+  relaxable_p &= (one_inst.relax_size != 0);
+  relax_size = relaxable_p ? one_inst.relax_size : 0;
+
+  p = frag_var (rs_machine_dependent, relax_size + RELAX_PAD_BYTE, 0,
+                RELAX_ENCODE (one_inst.size, one_inst.relax_size,
+                              one_inst.type, 0, 0, relaxable_p),
+                NULL, 0, NULL);
+
+  if (relaxable_p)
+    md_number_to_chars (p, one_inst.relax_inst, relax_size);
+}
+
+static void
+handle_dependency (struct score_it *theinst)
+{
+  int i;
+  int warn_or_error = 0;   /* warn - 0; error - 1  */
+  int bubbles = 0;
+  int remainder_bubbles = 0;
+  char cur_insn[INSN_NAME_LEN];
+  char pre_insn[INSN_NAME_LEN];
+  struct score_it nop_inst;
+  struct score_it pflush_inst;
+
+  nop_inst.instruction = 0x0000;
+  nop_inst.size = 2;
+  nop_inst.relax_inst = 0x80008000;
+  nop_inst.relax_size = 4;
+  nop_inst.type = NO16_OPD;
+
+  pflush_inst.instruction = 0x8000800a;
+  pflush_inst.size = 4;
+  pflush_inst.relax_inst = 0x8000;
+  pflush_inst.relax_size = 0;
+  pflush_inst.type = NO_OPD;
+
+  /* pflush will clear all data dependency.  */
+  if (strcmp (theinst->name, "pflush") == 0)
+    {
+      init_dependency_vector ();
+      return;
+    }
+
+  /* Push current instruction to dependency_vector[0].  */
+  for (i = vector_size - 1; i > 0; i--)
+    memcpy (&dependency_vector[i], &dependency_vector[i - 1], sizeof (dependency_vector[i]));
+
+  memcpy (&dependency_vector[0], theinst, sizeof (dependency_vector[i]));
+
+  /* There is no dependency between nop and any instruction.  */
+  if (strcmp (dependency_vector[0].name, "nop") == 0
+      || strcmp (dependency_vector[0].name, "nop!") == 0)
+    return;
+
+  /* "pce" is defined in insn_to_dependency_table.  */
+#define PCE_NAME "pce"
+
+  if (dependency_vector[0].type == Insn_Type_PCE)
+    strcpy (cur_insn, PCE_NAME);
+  else
+    strcpy (cur_insn, dependency_vector[0].name);
+
+  for (i = 1; i < vector_size; i++)
+    {
+      /* The element of dependency_vector is NULL.  */
+      if (dependency_vector[i].name[0] == '\0')
+	continue;
+
+      if (dependency_vector[i].type == Insn_Type_PCE)
+	strcpy (pre_insn, PCE_NAME);
+      else
+	strcpy (pre_insn, dependency_vector[i].name);
+
+      bubbles = check_dependency (pre_insn, dependency_vector[i].reg,
+                                  cur_insn, dependency_vector[0].reg, &warn_or_error);
+      remainder_bubbles = bubbles - i + 1;
+
+      if (remainder_bubbles > 0)
+        {
+          int j;
+
+          if (fix_data_dependency == 1)
+            {
+	      if (remainder_bubbles <= 2)
+		{
+		  if (warn_fix_data_dependency)
+		    as_warn (_("Fix data dependency: %s %s -- %s %s  (insert %d nop!/%d)"),
+			     dependency_vector[i].name, dependency_vector[i].reg,
+			     dependency_vector[0].name, dependency_vector[0].reg,
+			     remainder_bubbles, bubbles);
+
+                  for (j = (vector_size - 1); (j - remainder_bubbles) > 0; j--)
+		    memcpy (&dependency_vector[j], &dependency_vector[j - remainder_bubbles],
+			    sizeof (dependency_vector[j]));
+
+                  for (j = 1; j <= remainder_bubbles; j++)
+                    {
+                      memset (&dependency_vector[j], '\0', sizeof (dependency_vector[j]));
+		      /* Insert nop!.  */
+    		      build_one_frag (nop_inst);
+                    }
+		}
+	      else
+		{
+		  if (warn_fix_data_dependency)
+		    as_warn (_("Fix data dependency: %s %s -- %s %s  (insert 1 pflush/%d)"),
+			     dependency_vector[i].name, dependency_vector[i].reg,
+			     dependency_vector[0].name, dependency_vector[0].reg,
+			     bubbles);
+
+                  for (j = 1; j < vector_size; j++)
+		    memset (&dependency_vector[j], '\0', sizeof (dependency_vector[j]));
+
+                  /* Insert pflush.  */
+                  build_one_frag (pflush_inst);
+		}
+            }
+          else
+            {
+	      if (warn_or_error)
+		{
+                  as_bad (_("data dependency: %s %s -- %s %s  (%d/%d bubble)"),
+                           dependency_vector[i].name, dependency_vector[i].reg,
+                           dependency_vector[0].name, dependency_vector[0].reg,
+                           remainder_bubbles, bubbles);
+		}
+	      else
+		{
+                  as_warn (_("data dependency: %s %s -- %s %s  (%d/%d bubble)"),
+                           dependency_vector[i].name, dependency_vector[i].reg,
+                           dependency_vector[0].name, dependency_vector[0].reg,
+                           remainder_bubbles, bubbles);
+		}
+            }
+        }
+    }
+}
+
+static enum insn_class
+get_insn_class_from_type (enum score_insn_type type)
+{
+  enum insn_class retval = (int) FAIL;
+
+  switch (type)
+    {
+    case Rd_I4:
+    case Rd_I5:
+    case Rd_rvalueBP_I5:
+    case Rd_lvalueBP_I5:
+    case Rd_I8:
+    case PC_DISP8div2:
+    case PC_DISP11div2:
+    case Rd_Rs:
+    case Rd_HighRs:
+    case Rd_lvalueRs:
+    case Rd_rvalueRs:
+    case x_Rs:
+    case Rd_LowRs:
+    case NO16_OPD:
+      retval = INSN_CLASS_16;
+      break;
+    case Rd_Rs_I5:
+    case x_Rs_I5:
+    case x_I5_x:
+    case Rd_Rs_I14:
+    case I15:
+    case Rd_I16:
+    case Rd_SI16:
+    case Rd_rvalueRs_SI10:
+    case Rd_lvalueRs_SI10:
+    case Rd_rvalueRs_preSI12:
+    case Rd_rvalueRs_postSI12:
+    case Rd_lvalueRs_preSI12:
+    case Rd_lvalueRs_postSI12:
+    case Rd_Rs_SI14:
+    case Rd_rvalueRs_SI15:
+    case Rd_lvalueRs_SI15:
+    case PC_DISP19div2:
+    case PC_DISP24div2:
+    case Rd_Rs_Rs:
+    case x_Rs_x:
+    case x_Rs_Rs:
+    case Rd_Rs_x:
+    case Rd_x_Rs:
+    case Rd_x_x:
+    case OP5_rvalueRs_SI15:
+    case I5_Rs_Rs_I5_OP5:
+    case x_rvalueRs_post4:
+    case Rd_rvalueRs_post4:
+    case Rd_x_I5:
+    case Rd_lvalueRs_post4:
+    case x_lvalueRs_post4:
+    case Rd_Rs_Rs_imm:
+    case NO_OPD:
+    case Rd_lvalue32Rs:
+    case Rd_rvalue32Rs:
+    case Insn_GP:
+    case Insn_PIC:
+    case Insn_internal:
+      retval = INSN_CLASS_32;
+      break;
+    case Insn_Type_PCE:
+      retval = INSN_CLASS_PCE;
+      break;
+    case Insn_Type_SYN:
+      retval = INSN_CLASS_SYN;
+      break;
+    default:
+      abort ();
+      break;
+    }
+  return retval;
+}
+
+static unsigned long
+adjust_paritybit (unsigned long m_code, enum insn_class class)
+{
+  unsigned long result = 0;
+  unsigned long m_code_high = 0;
+  unsigned long m_code_low = 0;
+  unsigned long pb_high = 0;
+  unsigned long pb_low = 0;
+
+  if (class == INSN_CLASS_32)
+    {
+      pb_high = 0x80000000;
+      pb_low = 0x00008000;
+    }
+  else if (class == INSN_CLASS_16)
+    {
+      pb_high = 0;
+      pb_low = 0;
+    }
+  else if (class == INSN_CLASS_PCE)
+    {
+      pb_high = 0;
+      pb_low = 0x00008000;
+    }
+  else if (class == INSN_CLASS_SYN)
+    {
+      /* FIXME.  at this time, INSN_CLASS_SYN must be 32 bit, but, instruction type should
+         be changed if macro instruction has been expanded.  */
+      pb_high = 0x80000000;
+      pb_low = 0x00008000;
+    }
+  else
+    {
+      abort ();
+    }
+
+  m_code_high = m_code & 0x3fff8000;
+  m_code_low = m_code & 0x00007fff;
+  result = pb_high | (m_code_high << 1) | pb_low | m_code_low;
+  return result;
+
+}
+
+static void
+gen_insn_frag (struct score_it *part_1, struct score_it *part_2)
+{
+  char *p;
+  bfd_boolean pce_p = FALSE;
+  int relaxable_p = g_opt;
+  int relax_size = 0;
+  struct score_it *inst1 = part_1;
+  struct score_it *inst2 = part_2;
+  struct score_it backup_inst1;
+
+  pce_p = (inst2) ? TRUE : FALSE;
+  memcpy (&backup_inst1, inst1, sizeof (struct score_it));
+
+  /* Adjust instruction opcode and to be relaxed instruction opcode.  */
+  if (pce_p)
+    {
+      backup_inst1.instruction = ((backup_inst1.instruction & 0x7FFF) << 15)
+                                  | (inst2->instruction & 0x7FFF);
+      backup_inst1.instruction = adjust_paritybit (backup_inst1.instruction, INSN_CLASS_PCE);
+      backup_inst1.relax_inst = 0x8000;
+      backup_inst1.size = INSN_SIZE;
+      backup_inst1.relax_size = 0;
+      backup_inst1.type = Insn_Type_PCE;
+    }
+  else
+    {
+      backup_inst1.instruction = adjust_paritybit (backup_inst1.instruction,
+						   GET_INSN_CLASS (backup_inst1.type));
+    }
+
+  if (backup_inst1.relax_size != 0)
+    {
+      enum insn_class tmp;
+
+      tmp = (backup_inst1.size == INSN_SIZE) ? INSN_CLASS_16 : INSN_CLASS_32;
+      backup_inst1.relax_inst = adjust_paritybit (backup_inst1.relax_inst, tmp);
+    }
+
+  /* Check data dependency.  */
+  handle_dependency (&backup_inst1);
+
+  /* Start a new frag if frag_now is not empty and is not instruction frag, maybe it contains
+     data produced by .ascii etc.  Doing this is to make one instruction per frag.  */
+  if (frag_now_fix () != 0)
+    {
+      if (!frag_now->tc_frag_data.is_insn)
+	frag_wane (frag_now);
+
+      frag_new (0);
+    }
+
+  /* Here, we must call frag_grow in order to keep the instruction frag type is
+     rs_machine_dependent.
+     For, frag_var may change frag_now->fr_type to rs_fill by calling frag_grow which
+     acturally will call frag_wane.
+     Calling frag_grow first will create a new frag_now which free size is 20 that is enough
+     for frag_var.  */
+  frag_grow (20);
+
+  p = frag_more (backup_inst1.size);
+  md_number_to_chars (p, backup_inst1.instruction, backup_inst1.size);
+
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (backup_inst1.size);
+#endif
+
+  /* Generate fixup structure.  */
+  if (pce_p)
+    {
+      if (inst1->reloc.type != BFD_RELOC_NONE)
+	fix_new_score (frag_now, p - frag_now->fr_literal,
+		       inst1->size, &inst1->reloc.exp,
+		       inst1->reloc.pc_rel, inst1->reloc.type);
+
+      if (inst2->reloc.type != BFD_RELOC_NONE)
+	fix_new_score (frag_now, p - frag_now->fr_literal + 2,
+		       inst2->size, &inst2->reloc.exp, inst2->reloc.pc_rel, inst2->reloc.type);
+    }
+  else
+    {
+      if (backup_inst1.reloc.type != BFD_RELOC_NONE)
+	fix_new_score (frag_now, p - frag_now->fr_literal,
+		       backup_inst1.size, &backup_inst1.reloc.exp,
+		       backup_inst1.reloc.pc_rel, backup_inst1.reloc.type);
+    }
+
+  /* relax_size may be 2, 4, 12 or 0, 0 indicates no relaxation.  */
+  relaxable_p &= (backup_inst1.relax_size != 0);
+  relax_size = relaxable_p ? backup_inst1.relax_size : 0;
+
+  p = frag_var (rs_machine_dependent, relax_size + RELAX_PAD_BYTE, 0,
+                RELAX_ENCODE (backup_inst1.size, backup_inst1.relax_size,
+                              backup_inst1.type, 0, 0, relaxable_p),
+                backup_inst1.reloc.exp.X_add_symbol, 0, NULL);
+
+  if (relaxable_p)
+    md_number_to_chars (p, backup_inst1.relax_inst, relax_size);
+
+  memcpy (inst1, &backup_inst1, sizeof (struct score_it));
+}
+
+static void
+parse_16_32_inst (char *insnstr, bfd_boolean gen_frag_p)
+{
+  char c;
+  char *p;
+  char *operator = insnstr;
+  const struct asm_opcode *opcode;
+
+  /* Parse operator and operands.  */
+  skip_whitespace (operator);
+
+  for (p = operator; *p != '\0'; p++)
+    if ((*p == ' ') || (*p == '!'))
+      break;
+
+  if (*p == '!')
+    p++;
+
+  c = *p;
+  *p = '\0';
+
+  opcode = (const struct asm_opcode *) hash_find (score_ops_hsh, operator);
+  *p = c;
+
+  memset (&inst, '\0', sizeof (inst));
+  sprintf (inst.str, "%s", insnstr);
+  if (opcode)
+    {
+      inst.instruction = opcode->value;
+      inst.relax_inst = opcode->relax_value;
+      inst.type = opcode->type;
+      inst.size = GET_INSN_SIZE (inst.type);
+      inst.relax_size = 0;
+      inst.bwarn = 0;
+      sprintf (inst.name, "%s", opcode->template);
+      strcpy (inst.reg, "");
+      inst.error = NULL;
+      inst.reloc.type = BFD_RELOC_NONE;
+
+      (*opcode->parms) (p);
+
+      /* It indicates current instruction is a macro instruction if inst.bwarn equals -1.  */
+      if ((inst.bwarn != -1) && (!inst.error) && (gen_frag_p))
+	gen_insn_frag (&inst, NULL);
+    }
+  else
+    inst.error = _("unrecognized opcode");
+}
+
+static int
+append_insn (char *str, bfd_boolean gen_frag_p)
+{
+  int retval = SUCCESS;
+
+  parse_16_32_inst (str, gen_frag_p);
+
+  if (inst.error)
+    {
+      retval = (int) FAIL;
+      as_bad (_("%s -- `%s'"), inst.error, inst.str);
+      inst.error = NULL;
+    }
+
+  return retval;
+}
+
+/* Handle mv! reg_high, reg_low;
+          mv! reg_low, reg_high;
+          mv! reg_low, reg_low;  */
+static void
+do16_mv_rdrs (char *str)
+{
+  int reg_rd;
+  int reg_rs;
+  char *backupstr = NULL;
+
+  backupstr = str;
+  skip_whitespace (str);
+
+  if ((reg_rd = reg_required_here (&str, 8, REG_TYPE_SCORE)) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || (reg_rs = reg_required_here (&str, 4, REG_TYPE_SCORE)) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      /* Case 1 : mv! or mlfh!.  */
+      if (reg_rd < 16)
+        {
+          if (reg_rs < 16)
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                | (((inst.instruction >> 4) & 0xf) << 15) | (0xf << 10);
+              inst.relax_size = 4;
+            }
+          else
+            {
+              char append_str[MAX_LITERAL_POOL_SIZE];
+
+              sprintf (append_str, "mlfh! %s", backupstr);
+              if (append_insn (append_str, TRUE) == (int) FAIL)
+		return;
+              /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+              inst.bwarn = -1;
+            }
+        }
+      /* Case 2 : mhfl!.  */
+      else
+        {
+          if (reg_rs > 16)
+            {
+              SET_INSN_ERROR (BAD_ARGS);
+              return;
+            }
+          else
+            {
+              char append_str[MAX_LITERAL_POOL_SIZE];
+
+              sprintf (append_str, "mhfl! %s", backupstr);
+              if (append_insn (append_str, TRUE) == (int) FAIL)
+		return;
+
+              /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+              inst.bwarn = -1;
+            }
+        }
+    }
+}
+
+static void
+do16_rdi4 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 8) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 3, _IMM4) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      if (((inst.instruction >> 3) & 0x10) == 0)        /* for judge is addei or subei : bit 5 =0 : addei */
+        {
+          if (((inst.instruction >> 3) & 0xf) != 0xf)
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                | ((1 << ((inst.instruction >> 3) & 0xf)) << 1);
+              inst.relax_size = 4;
+            }
+          else
+            {
+              inst.relax_inst = 0x8000;
+            }
+        }
+      else
+        {
+          if (((inst.instruction >> 3) & 0xf) != 0xf)
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                | (((-(1 << ((inst.instruction >> 3) & 0xf))) & 0xffff) << 1);
+              inst.relax_size = 4;
+            }
+          else
+            {
+              inst.relax_inst = 0x8000;
+            }
+        }
+    }
+}
+
+static void
+do16_rdi5 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 8) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 3, _IMM5) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+  else
+    {
+      inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+        | (((inst.instruction >> 8) & 0xf) << 15) | (((inst.instruction >> 3) & 0x1f) << 10);
+      inst.relax_size = 4;
+    }
+}
+
+/* Handle sdbbp.  */
+static void
+do16_xi5 (char *str)
+{
+  skip_whitespace (str);
+
+  if (data_op2 (&str, 3, _IMM5) == (int) FAIL || end_of_line (str) == (int) FAIL)
+    return;
+  else
+    {
+      inst.relax_inst |= (((inst.instruction >> 3) & 0x1f) << 15);
+      inst.relax_size = 4;
+    }
+}
+
+/* Check that an immediate is word alignment or half word alignment.
+   If so, convert it to the right format.  */
+static int
+validate_immediate_align (int val, unsigned int data_type)
+{
+  if (data_type == _IMM5_RSHIFT_1)
+    {
+      if (val % 2)
+        {
+          inst.error = _("address offset must be half word alignment");
+          return (int) FAIL;
+        }
+    }
+  else if ((data_type == _IMM5_RSHIFT_2) || (data_type == _IMM10_RSHIFT_2))
+    {
+      if (val % 4)
+        {
+          inst.error = _("address offset must be word alignment");
+          return (int) FAIL;
+        }
+    }
+
+  return SUCCESS;
+}
+
+static int
+exp_ldst_offset (char **str, int shift, unsigned int data_type)
+{
+  char *dataptr;
+
+  dataptr = * str;
+
+  if ((*dataptr == '0') && (*(dataptr + 1) == 'x')
+      && (data_type != _SIMM16_LA)
+      && (data_type != _VALUE_HI16)
+      && (data_type != _VALUE_LO16)
+      && (data_type != _IMM16)
+      && (data_type != _IMM15)
+      && (data_type != _IMM14)
+      && (data_type != _IMM4)
+      && (data_type != _IMM5)
+      && (data_type != _IMM8)
+      && (data_type != _IMM5_RSHIFT_1)
+      && (data_type != _IMM5_RSHIFT_2)
+      && (data_type != _SIMM14_NEG)
+      && (data_type != _IMM10_RSHIFT_2))
+    {
+      data_type += 24;
+    }
+
+  if (my_get_expression (&inst.reloc.exp, str) == (int) FAIL)
+    return (int) FAIL;
+
+  if (inst.reloc.exp.X_op == O_constant)
+    {
+      /* Need to check the immediate align.  */
+      int value = validate_immediate_align (inst.reloc.exp.X_add_number, data_type);
+
+      if (value == (int) FAIL)
+	return (int) FAIL;
+
+      value = validate_immediate (inst.reloc.exp.X_add_number, data_type, 0);
+      if (value == (int) FAIL)
+        {
+          if (data_type < 30)
+            sprintf (err_msg,
+                     _("invalid constant: %d bit expression not in range %d..%d"),
+                     score_df_range[data_type].bits,
+                     score_df_range[data_type].range[0], score_df_range[data_type].range[1]);
+          else
+            sprintf (err_msg,
+                     _("invalid constant: %d bit expression not in range %d..%d"),
+                     score_df_range[data_type - 24].bits,
+                     score_df_range[data_type - 24].range[0], score_df_range[data_type - 24].range[1]);
+          inst.error = err_msg;
+          return (int) FAIL;
+        }
+
+      if (data_type == _IMM5_RSHIFT_1)
+        {
+          value >>= 1;
+        }
+      else if ((data_type == _IMM5_RSHIFT_2) || (data_type == _IMM10_RSHIFT_2))
+        {
+          value >>= 2;
+        }
+
+      if (score_df_range[data_type].range[0] != 0)
+        {
+          value &= (1 << score_df_range[data_type].bits) - 1;
+        }
+
+      inst.instruction |= value << shift;
+    }
+  else
+    {
+      inst.reloc.pc_rel = 0;
+    }
+
+  return SUCCESS;
+}
+
+static void
+do_ldst_insn (char *str)
+{
+  int pre_inc = 0;
+  int conflict_reg;
+  int value;
+  char * temp;
+  char *strbak;
+  char *dataptr;
+  int reg;
+  int ldst_idx = 0;
+
+  strbak = str;
+  skip_whitespace (str);
+
+  if (((conflict_reg = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  /* ld/sw rD, [rA, simm15]    ld/sw rD, [rA]+, simm12     ld/sw rD, [rA, simm12]+.  */
+  if (*str == '[')
+    {
+      str++;
+      skip_whitespace (str);
+
+      if ((reg = reg_required_here (&str, 15, REG_TYPE_SCORE)) == (int) FAIL)
+	return;
+
+      /* Conflicts can occur on stores as well as loads.  */
+      conflict_reg = (conflict_reg == reg);
+      skip_whitespace (str);
+      temp = str + 1;    /* The latter will process decimal/hex expression.  */
+
+      /* ld/sw rD, [rA]+, simm12    ld/sw rD, [rA]+.  */
+      if (*str == ']')
+        {
+          str++;
+          if (*str == '+')
+            {
+              str++;
+              /* ld/sw rD, [rA]+, simm12.  */
+              if (skip_past_comma (&str) == SUCCESS)
+                {
+                  if ((exp_ldst_offset (&str, 3, _SIMM12) == (int) FAIL)
+                      || (end_of_line (str) == (int) FAIL))
+		    return;
+
+                  if (conflict_reg)
+                    {
+                      unsigned int ldst_func = inst.instruction & OPC_PSEUDOLDST_MASK;
+
+                      if ((ldst_func == INSN_LH)
+                          || (ldst_func == INSN_LHU)
+                          || (ldst_func == INSN_LW)
+                          || (ldst_func == INSN_LB)
+                          || (ldst_func == INSN_LBU))
+                        {
+                          inst.error = _("register same as write-back base");
+                          return;
+                        }
+                    }
+
+                  ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+                  inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+                  inst.instruction |= score_ldst_insns[ldst_idx * 3 + LDST_POST].value;
+
+                  /* lw rD, [rA]+, 4 convert to pop rD, [rA].  */
+                  if ((inst.instruction & 0x3e000007) == 0x0e000000)
+                    {
+                      /* rs =  r0-r7, offset = 4 */
+                      if ((((inst.instruction >> 15) & 0x18) == 0)
+                          && (((inst.instruction >> 3) & 0xfff) == 4))
+                        {
+                          /* Relax to pophi.  */
+                          if ((((inst.instruction >> 20) & 0x10) == 0x10))
+                            {
+                              inst.relax_inst = 0x0000200a | (((inst.instruction >> 20) & 0xf)
+                                                              << 8) | 1 << 7 |
+                                (((inst.instruction >> 15) & 0x7) << 4);
+                            }
+                          /* Relax to pop.  */
+                          else
+                            {
+                              inst.relax_inst = 0x0000200a | (((inst.instruction >> 20) & 0xf)
+                                                              << 8) | 0 << 7 |
+                                (((inst.instruction >> 15) & 0x7) << 4);
+                            }
+                          inst.relax_size = 2;
+                        }
+                    }
+                  return;
+                }
+              /* ld/sw rD, [rA]+ convert to ld/sw rD, [rA, 0]+.  */
+              else
+                {
+                  SET_INSN_ERROR (NULL);
+                  if (end_of_line (str) == (int) FAIL)
+                    {
+                      return;
+                    }
+
+                  pre_inc = 1;
+                  value = validate_immediate (inst.reloc.exp.X_add_number, _SIMM12, 0);
+                  value &= (1 << score_df_range[_SIMM12].bits) - 1;
+                  ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+                  inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+                  inst.instruction |= score_ldst_insns[ldst_idx * 3 + pre_inc].value;
+                  inst.instruction |= value << 3;
+                  inst.relax_inst = 0x8000;
+                  return;
+                }
+            }
+          /* ld/sw rD, [rA] convert to ld/sw rD, [rA, simm15].  */
+          else
+            {
+              if (end_of_line (str) == (int) FAIL)
+		return;
+
+              ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+              inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+              inst.instruction |= score_ldst_insns[ldst_idx * 3 + LDST_NOUPDATE].value;
+
+              /* lbu rd, [rs] -> lbu! rd, [rs]  */
+              if (ldst_idx == INSN_LBU)
+                {
+                  inst.relax_inst = INSN16_LBU;
+                }
+              else if (ldst_idx == INSN_LH)
+                {
+                  inst.relax_inst = INSN16_LH;
+                }
+              else if (ldst_idx == INSN_LW)
+                {
+                  inst.relax_inst = INSN16_LW;
+                }
+              else if (ldst_idx == INSN_SB)
+                {
+                  inst.relax_inst = INSN16_SB;
+                }
+              else if (ldst_idx == INSN_SH)
+                {
+                  inst.relax_inst = INSN16_SH;
+                }
+              else if (ldst_idx == INSN_SW)
+                {
+                  inst.relax_inst = INSN16_SW;
+                }
+              else
+                {
+                  inst.relax_inst = 0x8000;
+                }
+
+              /* lw/lh/lbu/sw/sh/sb, offset = 0, relax to 16 bit instruction.  */
+              if ((ldst_idx == INSN_LBU)
+                  || (ldst_idx == INSN_LH)
+                  || (ldst_idx == INSN_LW)
+                  || (ldst_idx == INSN_SB) || (ldst_idx == INSN_SH) || (ldst_idx == INSN_SW))
+                {
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      inst.relax_inst |= (2 << 12) | (((inst.instruction >> 20) & 0xf) << 8) |
+                        (((inst.instruction >> 15) & 0xf) << 4);
+                      inst.relax_size = 2;
+                    }
+                }
+
+              return;
+            }
+        }
+      /* ld/sw rD, [rA, simm15]    ld/sw rD, [rA, simm12]+.  */
+      else
+        {
+          if (skip_past_comma (&str) == (int) FAIL)
+            {
+              inst.error = _("pre-indexed expression expected");
+              return;
+            }
+
+          if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL)
+	    return;
+
+          skip_whitespace (str);
+          if (*str++ != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+
+          skip_whitespace (str);
+          /* ld/sw rD, [rA, simm12]+.  */
+          if (*str == '+')
+            {
+              str++;
+              pre_inc = 1;
+              if (conflict_reg)
+                {
+                  unsigned int ldst_func = inst.instruction & OPC_PSEUDOLDST_MASK;
+
+                  if ((ldst_func == INSN_LH)
+                      || (ldst_func == INSN_LHU)
+                      || (ldst_func == INSN_LW)
+                      || (ldst_func == INSN_LB)
+                      || (ldst_func == INSN_LBU))
+                    {
+                      inst.error = _("register same as write-back base");
+                      return;
+                    }
+                }
+            }
+
+          if (end_of_line (str) == (int) FAIL)
+	    return;
+
+          if (inst.reloc.exp.X_op == O_constant)
+            {
+              int value;
+              unsigned int data_type;
+
+              if (pre_inc == 1)
+                data_type = _SIMM12;
+              else
+                data_type = _SIMM15;
+              dataptr = temp;
+
+              if ((*dataptr == '0') && (*(dataptr + 1) == 'x')
+                  && (data_type != _SIMM16_LA)
+                  && (data_type != _VALUE_HI16)
+                  && (data_type != _VALUE_LO16)
+                  && (data_type != _IMM16)
+                  && (data_type != _IMM15)
+                  && (data_type != _IMM14)
+                  && (data_type != _IMM4)
+                  && (data_type != _IMM5)
+                  && (data_type != _IMM8)
+                  && (data_type != _IMM5_RSHIFT_1)
+                  && (data_type != _IMM5_RSHIFT_2)
+                  && (data_type != _SIMM14_NEG)
+                  && (data_type != _IMM10_RSHIFT_2))
+                {
+                  data_type += 24;
+                }
+
+              value = validate_immediate (inst.reloc.exp.X_add_number, data_type, 0);
+              if (value == (int) FAIL)
+                {
+                  if (data_type < 30)
+                    sprintf (err_msg,
+                             _("invalid constant: %d bit expression not in range %d..%d"),
+                             score_df_range[data_type].bits,
+                             score_df_range[data_type].range[0], score_df_range[data_type].range[1]);
+                  else
+                    sprintf (err_msg,
+                             _("invalid constant: %d bit expression not in range %d..%d"),
+                             score_df_range[data_type - 24].bits,
+                             score_df_range[data_type - 24].range[0],
+                             score_df_range[data_type - 24].range[1]);
+                  inst.error = err_msg;
+                  return;
+                }
+
+              value &= (1 << score_df_range[data_type].bits) - 1;
+              ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+              inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+              inst.instruction |= score_ldst_insns[ldst_idx * 3 + pre_inc].value;
+              if (pre_inc == 1)
+                inst.instruction |= value << 3;
+              else
+                inst.instruction |= value;
+
+              /* lw rD, [rA, simm15]  */
+              if ((inst.instruction & 0x3e000000) == 0x20000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0)
+                      && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, lw -> lw!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, lw -> lwp!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x3) == 0)
+                               && ((inst.instruction & 0x7fff) < 128))
+                        {
+                          inst.relax_inst = 0x7000 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | (((inst.instruction & 0x7fff) >> 2) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* sw rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x28000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, sw -> sw!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, sw -> swp!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x3) == 0)
+                               && ((inst.instruction & 0x7fff) < 128))
+                        {
+                          inst.relax_inst = 0x7004 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | (((inst.instruction & 0x7fff) >> 2) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* sw rD, [rA, simm15]+    sw pre.  */
+              else if ((inst.instruction & 0x3e000007) == 0x06000004)
+                {
+                  /* rA is in [r0 - r7], and simm15 = -4.  */
+                  if ((((inst.instruction >> 15) & 0x18) == 0)
+                      && (((inst.instruction >> 3) & 0xfff) == 0xffc))
+                    {
+                      /* sw -> pushhi!.  */
+                      if ((((inst.instruction >> 20) & 0x10) == 0x10))
+                        {
+                          inst.relax_inst = 0x0000200e | (((inst.instruction >> 20) & 0xf) << 8)
+                            | 1 << 7 | (((inst.instruction >> 15) & 0x7) << 4);
+                          inst.relax_size = 2;
+                        }
+                      /* sw -> push!.  */
+                      else
+                        {
+                          inst.relax_inst = 0x0000200e | (((inst.instruction >> 20) & 0xf) << 8)
+                            | 0 << 7 | (((inst.instruction >> 15) & 0x7) << 4);
+                          inst.relax_size = 2;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* lh rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x22000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, lh -> lh!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, lh -> lhp!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x1) == 0)
+                               && ((inst.instruction & 0x7fff) < 64))
+                        {
+                          inst.relax_inst = 0x7001 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | (((inst.instruction & 0x7fff) >> 1) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* sh rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x2a000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, sh -> sh!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, sh -> shp!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x1) == 0)
+                               && ((inst.instruction & 0x7fff) < 64))
+                        {
+                          inst.relax_inst = 0x7005 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | (((inst.instruction & 0x7fff) >> 1) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* lbu rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x2c000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, lbu -> lbu!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, lbu -> lbup!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x7fff) < 32))
+                        {
+                          inst.relax_inst = 0x7003 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | ((inst.instruction & 0x7fff) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* sb rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x2e000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, sb -> sb!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, sb -> sb!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x7fff) < 32))
+                        {
+                          inst.relax_inst = 0x7007 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | ((inst.instruction & 0x7fff) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              else
+                {
+                  inst.relax_inst = 0x8000;
+                }
+
+              return;
+            }
+          else
+            {
+              /* FIXME: may set error, for there is no ld/sw rD, [rA, label] */
+              inst.reloc.pc_rel = 0;
+            }
+        }
+    }
+  else
+    {
+      inst.error = BAD_ARGS;
+    }
+}
+
+/* Handle cache.  */
+
+static void
+do_cache (char *str)
+{
+  skip_whitespace (str);
+
+  if ((data_op2 (&str, 20, _IMM5) == (int) FAIL) || (skip_past_comma (&str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+      int cache_op;
+
+      cache_op = (inst.instruction >> 20) & 0x1F;
+      sprintf (inst.name, "cache %d", cache_op);
+    }
+
+  if (*str == '[')
+    {
+      str++;
+      skip_whitespace (str);
+
+      if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL)
+	return;
+
+      skip_whitespace (str);
+
+      /* cache op, [rA]  */
+      if (skip_past_comma (&str) == (int) FAIL)
+        {
+          SET_INSN_ERROR (NULL);
+          if (*str != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+          str++;
+        }
+      /* cache op, [rA, simm15]  */
+      else
+        {
+          if (exp_ldst_offset (&str, 0, _SIMM15) == (int) FAIL)
+            {
+              return;
+            }
+
+          skip_whitespace (str);
+          if (*str++ != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+        }
+
+      if (end_of_line (str) == (int) FAIL)
+	return;
+    }
+  else
+    {
+      inst.error = BAD_ARGS;
+    }
+}
+
+static void
+do_crdcrscrsimm5 (char *str)
+{
+  char *strbak;
+
+  strbak = str;
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE_CR) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE_CR) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE_CR) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL)
+    {
+      str = strbak;
+      /* cop1 cop_code20.  */
+      if (data_op2 (&str, 5, _IMM20) == (int) FAIL)
+	return;
+    }
+  else
+    {
+      if (data_op2 (&str, 5, _IMM5) == (int) FAIL)
+	return;
+    }
+
+  end_of_line (str);
+}
+
+/* Handle ldc/stc.  */
+static void
+do_ldst_cop (char *str)
+{
+  skip_whitespace (str);
+
+  if ((reg_required_here (&str, 15, REG_TYPE_SCORE_CR) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  if (*str == '[')
+    {
+      str++;
+      skip_whitespace (str);
+
+      if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL)
+	return;
+
+      skip_whitespace (str);
+
+      if (*str++ != ']')
+        {
+          if (exp_ldst_offset (&str, 5, _IMM10_RSHIFT_2) == (int) FAIL)
+	    return;
+
+          skip_whitespace (str);
+          if (*str++ != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+        }
+
+      end_of_line (str);
+    }
+  else
+    inst.error = BAD_ARGS;
+}
+
+static void
+do16_ldst_insn (char *str)
+{
+  skip_whitespace (str);
+
+  if ((reglow_required_here (&str, 8) == (int) FAIL) || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  if (*str == '[')
+    {
+      int reg;
+
+      str++;
+      skip_whitespace (str);
+
+      if ((reg = reglow_required_here (&str, 4)) == (int) FAIL)
+	return;
+
+      skip_whitespace (str);
+      if (*str++ == ']')
+        {
+          if (end_of_line (str) == (int) FAIL)
+	    return;
+          else
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                              | (((inst.instruction >> 4) & 0xf) << 15);
+	      inst.relax_size = 4;
+            }
+        }
+      else
+        {
+          inst.error = _("missing ]");
+        }
+    }
+  else
+    {
+      inst.error = BAD_ARGS;
+    }
+}
+
+/* Handle lbup!/lhp!/ldiu!/lwp!/sbp!/shp!/swp!.  */
+static void
+do16_ldst_imm_insn (char *str)
+{
+  char data_exp[MAX_LITERAL_POOL_SIZE];
+  int reg_rd;
+  char *dataptr = NULL, *pp = NULL;
+  int cnt = 0;
+  int assign_data = (int) FAIL;
+  unsigned int ldst_func;
+
+  skip_whitespace (str);
+
+  if (((reg_rd = reglow_required_here (&str, 8)) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  skip_whitespace (str);
+  dataptr = str;
+
+  while ((*dataptr != '\0') && (*dataptr != '|') && (cnt <= MAX_LITERAL_POOL_SIZE))
+    {
+      data_exp[cnt] = *dataptr;
+      dataptr++;
+      cnt++;
+    }
+
+  data_exp[cnt] = '\0';
+  pp = &data_exp[0];
+
+  str = dataptr;
+
+  ldst_func = inst.instruction & LDST16_RI_MASK;
+  if (ldst_func == N16_LIU)
+    assign_data = exp_ldst_offset (&pp, 0, _IMM8);
+  else if (ldst_func == N16_LHP || ldst_func == N16_SHP)
+    assign_data = exp_ldst_offset (&pp, 3, _IMM5_RSHIFT_1);
+  else if (ldst_func == N16_LWP || ldst_func == N16_SWP)
+    assign_data = exp_ldst_offset (&pp, 3, _IMM5_RSHIFT_2);
+  else
+    assign_data = exp_ldst_offset (&pp, 3, _IMM5);
+
+  if ((assign_data == (int) FAIL) || (end_of_line (pp) == (int) FAIL))
+    return;
+  else
+    {
+      if ((inst.instruction & 0x7000) == N16_LIU)
+        {
+          inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20
+                          | ((inst.instruction & 0xff) << 1);
+        }
+      else if (((inst.instruction & 0x7007) == N16_LHP)
+               || ((inst.instruction & 0x7007) == N16_SHP))
+        {
+          inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
+                          | (((inst.instruction >> 3) & 0x1f) << 1);
+        }
+      else if (((inst.instruction & 0x7007) == N16_LWP)
+               || ((inst.instruction & 0x7007) == N16_SWP))
+        {
+          inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
+                          | (((inst.instruction >> 3) & 0x1f) << 2);
+        }
+      else if (((inst.instruction & 0x7007) == N16_LBUP)
+               || ((inst.instruction & 0x7007) == N16_SBP))
+        {
+          inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
+                          | (((inst.instruction >> 3) & 0x1f));
+        }
+
+      inst.relax_size = 4;
+    }
+}
+
+static void
+do16_push_pop (char *str)
+{
+  int reg_rd;
+  int H_bit_mask = 0;
+
+  skip_whitespace (str);
+  if (((reg_rd = reg_required_here (&str, 8, REG_TYPE_SCORE)) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  if (reg_rd >= 16)
+    H_bit_mask = 1;
+
+  /* reg_required_here will change bit 12 of opcode, so we must restore bit 12.  */
+  inst.instruction &= ~(1 << 12);
+
+  inst.instruction |= H_bit_mask << 7;
+
+  if (*str == '[')
+    {
+      int reg;
+
+      str++;
+      skip_whitespace (str);
+      if ((reg = reg_required_here (&str, 4, REG_TYPE_SCORE)) == (int) FAIL)
+	return;
+      else if (reg > 7)
+        {
+          if (!inst.error)
+	    inst.error = _("base register nums are over 3 bit");
+
+          return;
+        }
+
+      skip_whitespace (str);
+      if ((*str++ != ']') || (end_of_line (str) == (int) FAIL))
+        {
+          if (!inst.error)
+	    inst.error = _("missing ]");
+
+          return;
+        }
+
+      /* pop! */
+      if ((inst.instruction & 0xf) == 0xa)
+        {
+          if (H_bit_mask)
+            {
+              inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
+                                  | (((inst.instruction >> 4) & 0x7) << 15) | (4 << 3);
+            }
+          else
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                                  | (((inst.instruction >> 4) & 0x7) << 15) | (4 << 3);
+            }
+        }
+      /* push! */
+      else
+        {
+          if (H_bit_mask)
+            {
+              inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
+                                  | (((inst.instruction >> 4) & 0x7) << 15) | (((-4) & 0xfff) << 3);
+            }
+          else
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                                  | (((inst.instruction >> 4) & 0x7) << 15) | (((-4) & 0xfff) << 3);
+            }
+        }
+      inst.relax_size = 4;
+    }
+  else
+    {
+      inst.error = BAD_ARGS;
+    }
+}
+
+/* Handle lcb/lcw/lce/scb/scw/sce.  */
+static void
+do_ldst_unalign (char *str)
+{
+  int conflict_reg;
+
+  if (university_version == 1)
+    {
+      inst.error = ERR_FOR_SCORE5U_ATOMIC;
+      return;
+    }
+
+  skip_whitespace (str);
+
+  /* lcb/scb [rA]+.  */
+  if (*str == '[')
+    {
+      str++;
+      skip_whitespace (str);
+
+      if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL)
+	return;
+
+      if (*str++ == ']')
+        {
+          if (*str++ != '+')
+            {
+              inst.error = _("missing +");
+              return;
+            }
+        }
+      else
+        {
+          inst.error = _("missing ]");
+          return;
+        }
+
+      if (end_of_line (str) == (int) FAIL)
+	return;
+    }
+  /* lcw/lce/scb/sce rD, [rA]+.  */
+  else
+    {
+      if (((conflict_reg = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL)
+          || (skip_past_comma (&str) == (int) FAIL))
+        {
+          return;
+        }
+
+      skip_whitespace (str);
+      if (*str++ == '[')
+        {
+          int reg;
+
+          skip_whitespace (str);
+          if ((reg = reg_required_here (&str, 15, REG_TYPE_SCORE)) == (int) FAIL)
+            {
+              return;
+            }
+
+          /* Conflicts can occur on stores as well as loads.  */
+          conflict_reg = (conflict_reg == reg);
+          skip_whitespace (str);
+          if (*str++ == ']')
+            {
+              unsigned int ldst_func = inst.instruction & LDST_UNALIGN_MASK;
+
+              if (*str++ == '+')
+                {
+                  if (conflict_reg)
+                    {
+                      as_warn (_("%s register same as write-back base"),
+                               ((ldst_func & UA_LCE) || (ldst_func & UA_LCW)
+                                ? _("destination") : _("source")));
+                    }
+                }
+              else
+                {
+                  inst.error = _("missing +");
+                  return;
+                }
+
+              if (end_of_line (str) == (int) FAIL)
+		return;
+            }
+          else
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+        }
+      else
+        {
+          inst.error = BAD_ARGS;
+          return;
+        }
+    }
+}
+
+/* Handle alw/asw.  */
+static void
+do_ldst_atomic (char *str)
+{
+  if (university_version == 1)
+    {
+      inst.error = ERR_FOR_SCORE5U_ATOMIC;
+      return;
+    }
+
+  skip_whitespace (str);
+
+  if ((reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+
+      skip_whitespace (str);
+      if (*str++ == '[')
+        {
+          int reg;
+
+          skip_whitespace (str);
+          if ((reg = reg_required_here (&str, 15, REG_TYPE_SCORE)) == (int) FAIL)
+            {
+              return;
+            }
+
+          skip_whitespace (str);
+          if (*str++ != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+
+          end_of_line (str);
+        }
+      else
+	inst.error = BAD_ARGS;
+    }
+}
+
+static void
+build_relax_frag (struct score_it fix_insts[RELAX_INST_NUM], int fix_num ATTRIBUTE_UNUSED,
+                  struct score_it var_insts[RELAX_INST_NUM], int var_num,
+                  symbolS *add_symbol)
+{
+  int i;
+  char *p;
+  fixS *fixp = NULL;
+  fixS *cur_fixp = NULL;
+  long where;
+  struct score_it inst_main;
+
+  memcpy (&inst_main, &fix_insts[0], sizeof (struct score_it));
+
+  /* Adjust instruction opcode and to be relaxed instruction opcode.  */
+  inst_main.instruction = adjust_paritybit (inst_main.instruction, GET_INSN_CLASS (inst_main.type));
+  inst_main.type = Insn_PIC;
+
+  for (i = 0; i < var_num; i++)
+    {
+      inst_main.relax_size += var_insts[i].size;
+      var_insts[i].instruction = adjust_paritybit (var_insts[i].instruction,
+                                                   GET_INSN_CLASS (var_insts[i].type));
+    }
+
+  /* Check data dependency.  */
+  handle_dependency (&inst_main);
+
+  /* Start a new frag if frag_now is not empty.  */
+  if (frag_now_fix () != 0)
+    {
+      if (!frag_now->tc_frag_data.is_insn)
+	{
+          frag_wane (frag_now);
+	}
+      frag_new (0);
+    }
+  frag_grow (20);
+
+  /* Write fr_fix part.  */
+  p = frag_more (inst_main.size);
+  md_number_to_chars (p, inst_main.instruction, inst_main.size);
+
+  if (inst_main.reloc.type != BFD_RELOC_NONE)
+    fixp = fix_new_score (frag_now, p - frag_now->fr_literal, inst_main.size,
+			  &inst_main.reloc.exp, inst_main.reloc.pc_rel, inst_main.reloc.type);
+
+  frag_now->tc_frag_data.fixp = fixp;
+  cur_fixp = frag_now->tc_frag_data.fixp;
+
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (inst_main.size);
+#endif
+
+  where = p - frag_now->fr_literal + inst_main.size;
+  for (i = 0; i < var_num; i++)
+    {
+      if (i > 0)
+        where += var_insts[i - 1].size;
+
+      if (var_insts[i].reloc.type != BFD_RELOC_NONE)
+        {
+          fixp = fix_new_score (frag_now, where, var_insts[i].size,
+                                &var_insts[i].reloc.exp, var_insts[i].reloc.pc_rel,
+                                var_insts[i].reloc.type);
+          if (fixp)
+            {
+              if (cur_fixp)
+                {
+                  cur_fixp->fx_next = fixp;
+                  cur_fixp = cur_fixp->fx_next;
+                }
+              else
+                {
+                  frag_now->tc_frag_data.fixp = fixp;
+                  cur_fixp = frag_now->tc_frag_data.fixp;
+                }
+	    }
+        }
+    }
+
+  p = frag_var (rs_machine_dependent, inst_main.relax_size + RELAX_PAD_BYTE, 0,
+                RELAX_ENCODE (inst_main.size, inst_main.relax_size, inst_main.type,
+                0, inst_main.size, 0), add_symbol, 0, NULL);
+
+  /* Write fr_var part.
+     no calling gen_insn_frag, no fixS will be generated.  */
+  for (i = 0; i < var_num; i++)
+    {
+      md_number_to_chars (p, var_insts[i].instruction, var_insts[i].size);
+      p += var_insts[i].size;
+    }
+  /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+  inst.bwarn = -1;
+}
+
+/* Build a relax frag for la instruction when generating PIC,
+   external symbol first and local symbol second.  */
+
+static void
+build_la_pic (int reg_rd, expressionS exp)
+{
+  symbolS *add_symbol = exp.X_add_symbol;
+  offsetT add_number = exp.X_add_number;
+  struct score_it fix_insts[RELAX_INST_NUM];
+  struct score_it var_insts[RELAX_INST_NUM];
+  int fix_num = 0;
+  int var_num = 0;
+  char tmp[MAX_LITERAL_POOL_SIZE];
+  int r1_bak;
+
+  r1_bak = nor1;
+  nor1 = 0;
+
+  if (add_number == 0)
+    {
+      fix_num = 1;
+      var_num = 2;
+
+      /* For an external symbol, only one insn is generated; 
+         For a local symbol, two insns are generated.  */
+      /* Fix part
+         For an external symbol: lw rD, <sym>($gp)
+                                 (BFD_RELOC_SCORE_GOT15 or BFD_RELOC_SCORE_CALL15)  */
+      sprintf (tmp, "lw_pic r%d, %s", reg_rd, add_symbol->bsym->name);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      if (reg_rd == PIC_CALL_REG)
+        inst.reloc.type = BFD_RELOC_SCORE_CALL15;
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+	 For a local symbol :
+         lw rD, <sym>($gp)    (BFD_RELOC_SCORE_GOT15)
+	 addi rD, <sym>       (BFD_RELOC_GOT_LO16) */
+      inst.reloc.type = BFD_RELOC_SCORE_GOT15;
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      sprintf (tmp, "addi_s_pic r%d, %s", reg_rd, add_symbol->bsym->name);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&var_insts[1], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+    }
+  else if (add_number >= -0x8000 && add_number <= 0x7fff)
+    {
+      /* Insn 1: lw rD, <sym>($gp)    (BFD_RELOC_SCORE_GOT15)  */
+      sprintf (tmp, "lw_pic r%d, %s", reg_rd, add_symbol->bsym->name);
+      if (append_insn (tmp, TRUE) == (int) FAIL)
+	return;
+
+      /* Insn 2  */
+      fix_num = 1;
+      var_num = 1;
+      /* Fix part
+         For an external symbol: addi rD, <constant> */
+      sprintf (tmp, "addi r%d, %d", reg_rd, (int)add_number);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+ 	 For a local symbol: addi rD, <sym>+<constant>    (BFD_RELOC_GOT_LO16)  */
+      sprintf (tmp, "addi_s_pic r%d, %s + %d", reg_rd, add_symbol->bsym->name, (int)add_number);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+    }
+  else
+    {
+      int hi = (add_number >> 16) & 0x0000FFFF;
+      int lo = add_number & 0x0000FFFF;
+
+      /* Insn 1: lw rD, <sym>($gp)    (BFD_RELOC_SCORE_GOT15)  */
+      sprintf (tmp, "lw_pic r%d, %s", reg_rd, add_symbol->bsym->name);
+      if (append_insn (tmp, TRUE) == (int) FAIL)
+	return;
+
+      /* Insn 2  */
+      fix_num = 1;
+      var_num = 1;
+      /* Fix part
+	 For an external symbol: ldis r1, HI%<constant>  */
+      sprintf (tmp, "ldis r1, %d", hi);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+	 For a local symbol: ldis r1, HI%<constant>
+         but, if lo is outof 16 bit, make hi plus 1  */
+      if ((lo < -0x8000) || (lo > 0x7fff))
+	{
+	  hi += 1;
+	}
+      sprintf (tmp, "ldis_pic r1, %d", hi);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+
+      /* Insn 3  */
+      fix_num = 1;
+      var_num = 1;
+      /* Fix part
+	 For an external symbol: ori r1, LO%<constant>  */
+      sprintf (tmp, "ori r1, %d", lo);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+  	 For a local symbol: addi r1, <sym>+LO%<constant>    (BFD_RELOC_GOT_LO16)  */
+      sprintf (tmp, "addi_u_pic r1, %s + %d", add_symbol->bsym->name, lo);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+
+      /* Insn 4: add rD, rD, r1  */
+      sprintf (tmp, "add r%d, r%d, r1", reg_rd, reg_rd);
+      if (append_insn (tmp, TRUE) == (int) FAIL)
+	return;
+
+     /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+     inst.bwarn = -1;
+    }
+
+  nor1 = r1_bak;
+}
+
+/* Handle la.  */
+static void
+do_macro_la_rdi32 (char *str)
+{
+  int reg_rd;
+
+  skip_whitespace (str);
+  if ((reg_rd = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      char append_str[MAX_LITERAL_POOL_SIZE];
+      char *keep_data = str;
+
+      /* la rd, simm16.  */
+      if (data_op2 (&str, 1, _SIMM16_LA) != (int) FAIL)
+        {
+          end_of_line (str);
+          return;
+        }
+      /* la rd, imm32 or la rd, label.  */
+      else
+        {
+          SET_INSN_ERROR (NULL);
+          str = keep_data;
+          if ((data_op2 (&str, 1, _VALUE_HI16) == (int) FAIL)
+              || (end_of_line (str) == (int) FAIL))
+            {
+              return;
+            }
+          else
+            {
+              if ((score_pic == NO_PIC) || (!inst.reloc.exp.X_add_symbol))
+                {
+                  sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
+                  if (append_insn (append_str, TRUE) == (int) FAIL)
+		    return;
+
+                  sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
+                  if (append_insn (append_str, TRUE) == (int) FAIL)
+		    return;
+		}
+	      else
+		{
+		  assert (inst.reloc.exp.X_add_symbol);
+		  build_la_pic (reg_rd, inst.reloc.exp);
+		}
+
+              /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+              inst.bwarn = -1;
+            }
+        }
+    }
+}
+
+/* Handle li.  */
+static void
+do_macro_li_rdi32 (char *str){
+
+  int reg_rd;
+
+  skip_whitespace (str);
+  if ((reg_rd = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      char *keep_data = str;
+
+      /* li rd, simm16.  */
+      if (data_op2 (&str, 1, _SIMM16_LA) != (int) FAIL)
+        {
+          end_of_line (str);
+          return;
+        }
+      /* li rd, imm32.  */
+      else
+        {
+          char append_str[MAX_LITERAL_POOL_SIZE];
+
+          str = keep_data;
+
+          if ((data_op2 (&str, 1, _VALUE_HI16) == (int) FAIL)
+              || (end_of_line (str) == (int) FAIL))
+            {
+              return;
+            }
+          else if (inst.reloc.exp.X_add_symbol)
+            {
+              inst.error = _("li rd label isn't correct instruction form");
+              return;
+            }
+          else
+            {
+              sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
+
+              if (append_insn (append_str, TRUE) == (int) FAIL)
+		return;
+              else
+                {
+                  sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
+                  if (append_insn (append_str, TRUE) == (int) FAIL)
+		    return;
+
+                  /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+                  inst.bwarn = -1;
+                }
+            }
+        }
+    }
+}
+
+/* Handle mul/mulu/div/divu/rem/remu.  */
+static void
+do_macro_mul_rdrsrs (char *str)
+{
+  int reg_rd;
+  int reg_rs1;
+  int reg_rs2;
+  char *backupstr;
+  char append_str[MAX_LITERAL_POOL_SIZE];
+
+  if (university_version == 1)
+    as_warn ("%s", ERR_FOR_SCORE5U_MUL_DIV);
+
+  strcpy (append_str, str);
+  backupstr = append_str;
+  skip_whitespace (backupstr);
+  if (((reg_rd = reg_required_here (&backupstr, -1, REG_TYPE_SCORE)) == (int) FAIL)
+      || (skip_past_comma (&backupstr) == (int) FAIL)
+      || ((reg_rs1 = reg_required_here (&backupstr, -1, REG_TYPE_SCORE)) == (int) FAIL))
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+
+  if (skip_past_comma (&backupstr) == (int) FAIL)
+    {
+      /* rem/remu rA, rB is error format.  */
+      if (strcmp (inst.name, "rem") == 0 || strcmp (inst.name, "remu") == 0)
+        {
+          SET_INSN_ERROR (BAD_ARGS);
+        }
+      else
+        {
+          SET_INSN_ERROR (NULL);
+          do_rsrs (str);
+        }
+      return;
+    }
+  else
+    {
+      SET_INSN_ERROR (NULL);
+      if (((reg_rs2 = reg_required_here (&backupstr, -1, REG_TYPE_SCORE)) == (int) FAIL)
+          || (end_of_line (backupstr) == (int) FAIL))
+        {
+          return;
+        }
+      else
+        {
+          char append_str1[MAX_LITERAL_POOL_SIZE];
+
+          if (strcmp (inst.name, "rem") == 0)
+            {
+              sprintf (append_str, "mul r%d, r%d", reg_rs1, reg_rs2);
+              sprintf (append_str1, "mfceh  r%d", reg_rd);
+            }
+          else if (strcmp (inst.name, "remu") == 0)
+            {
+              sprintf (append_str, "mulu r%d, r%d", reg_rs1, reg_rs2);
+              sprintf (append_str1, "mfceh  r%d", reg_rd);
+            }
+          else
+            {
+              sprintf (append_str, "%s r%d, r%d", inst.name, reg_rs1, reg_rs2);
+              sprintf (append_str1, "mfcel  r%d", reg_rd);
+            }
+
+          /* Output mul/mulu or div/divu or rem/remu.  */
+          if (append_insn (append_str, TRUE) == (int) FAIL)
+	    return;
+
+          /* Output mfcel or mfceh.  */
+          if (append_insn (append_str1, TRUE) == (int) FAIL)
+	    return;
+
+          /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+          inst.bwarn = -1;
+        }
+    }
+}
+
+static void
+exp_macro_ldst_abs (char *str)
+{
+  int reg_rd;
+  char *backupstr, *tmp;
+  char append_str[MAX_LITERAL_POOL_SIZE];
+  char verifystr[MAX_LITERAL_POOL_SIZE];
+  struct score_it inst_backup;
+  int r1_bak = 0;
+
+  r1_bak = nor1;
+  nor1 = 0;
+  memcpy (&inst_backup, &inst, sizeof (struct score_it));
+
+  strcpy (verifystr, str);
+  backupstr = verifystr;
+  skip_whitespace (backupstr);
+  if ((reg_rd = reg_required_here (&backupstr, -1, REG_TYPE_SCORE)) == (int) FAIL)
+    return;
+
+  tmp = backupstr;
+  if (skip_past_comma (&backupstr) == (int) FAIL)
+    return;
+
+  backupstr = tmp;
+  sprintf (append_str, "li r1  %s", backupstr);
+  append_insn (append_str, TRUE);
+
+  memcpy (&inst, &inst_backup, sizeof (struct score_it));
+  sprintf (append_str, " r%d, [r1,0]", reg_rd);
+  do_ldst_insn (append_str);
+
+  nor1 = r1_bak;
+}
+
+static int
+nopic_need_relax (symbolS * sym, int before_relaxing)
+{
+  if (sym == NULL)
+    return 0;
+  else if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
+    {
+      const char *symname;
+      const char *segname;
+
+      /* Find out whether this symbol can be referenced off the $gp
+         register.  It can be if it is smaller than the -G size or if
+         it is in the .sdata or .sbss section.  Certain symbols can
+         not be referenced off the $gp, although it appears as though
+         they can.  */
+      symname = S_GET_NAME (sym);
+      if (symname != (const char *)NULL
+          && (strcmp (symname, "eprol") == 0
+              || strcmp (symname, "etext") == 0
+              || strcmp (symname, "_gp") == 0
+              || strcmp (symname, "edata") == 0
+              || strcmp (symname, "_fbss") == 0
+              || strcmp (symname, "_fdata") == 0
+              || strcmp (symname, "_ftext") == 0
+              || strcmp (symname, "end") == 0
+              || strcmp (symname, GP_DISP_LABEL) == 0))
+        {
+          return 1;
+        }
+      else if ((!S_IS_DEFINED (sym) || S_IS_COMMON (sym)) && (0
+      /* We must defer this decision until after the whole file has been read,
+         since there might be a .extern after the first use of this symbol.  */
+               || (before_relaxing
+                   && S_GET_VALUE (sym) == 0)
+               || (S_GET_VALUE (sym) != 0
+                   && S_GET_VALUE (sym) <= g_switch_value)))
+        {
+          return 0;
+        }
+
+      segname = segment_name (S_GET_SEGMENT (sym));
+      return (strcmp (segname, ".sdata") != 0
+	      && strcmp (segname, ".sbss") != 0
+	      && strncmp (segname, ".sdata.", 7) != 0
+	      && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
+    }
+  /* We are not optimizing for the $gp register.  */
+  else
+    return 1;
+}
+
+/* Build a relax frag for lw/st instruction when generating PIC,
+   external symbol first and local symbol second.  */
+
+static void
+build_lwst_pic (int reg_rd, expressionS exp, const char *insn_name)
+{
+  symbolS *add_symbol = exp.X_add_symbol;
+  int add_number = exp.X_add_number;
+  struct score_it fix_insts[RELAX_INST_NUM];
+  struct score_it var_insts[RELAX_INST_NUM];
+  int fix_num = 0;
+  int var_num = 0;
+  char tmp[MAX_LITERAL_POOL_SIZE];
+  int r1_bak;
+
+  r1_bak = nor1;
+  nor1 = 0;
+
+  if ((add_number == 0) || (add_number >= -0x8000 && add_number <= 0x7fff))
+    {
+      fix_num = 1;
+      var_num = 2;
+
+      /* For an external symbol, two insns are generated;
+         For a local symbol, three insns are generated.  */
+      /* Fix part
+         For an external symbol: lw rD, <sym>($gp)
+                                 (BFD_RELOC_SCORE_GOT15)  */
+      sprintf (tmp, "lw_pic r1, %s", add_symbol->bsym->name);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+        return;
+
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+	 For a local symbol :
+         lw rD, <sym>($gp)    (BFD_RELOC_SCORE_GOT15)
+	 addi rD, <sym>       (BFD_RELOC_GOT_LO16) */
+      inst.reloc.type = BFD_RELOC_SCORE_GOT15;
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      sprintf (tmp, "addi_s_pic r1, %s", add_symbol->bsym->name);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+        return;
+
+      memcpy (&var_insts[1], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+
+      /* Insn 2 or Insn 3: lw/st rD, [r1, constant]  */
+      sprintf (tmp, "%s r%d, [r1, %d]", insn_name, reg_rd, add_number);
+      if (append_insn (tmp, TRUE) == (int) FAIL)
+        return;
+
+      /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+      inst.bwarn = -1;
+    }
+  else
+    {
+      inst.error = _("PIC code offset overflow (max 16 signed bits)");
+      return;
+    }
+
+  nor1 = r1_bak;
+}
+
+static void
+do_macro_ldst_label (char *str)
+{
+  int i;
+  int ldst_gp_p = 0;
+  int reg_rd;
+  int r1_bak;
+  char *backup_str;
+  char *label_str;
+  char *absolute_value;
+  char append_str[3][MAX_LITERAL_POOL_SIZE];
+  char verifystr[MAX_LITERAL_POOL_SIZE];
+  struct score_it inst_backup;
+  struct score_it inst_expand[3];
+  struct score_it inst_main;
+
+  memcpy (&inst_backup, &inst, sizeof (struct score_it));
+  strcpy (verifystr, str);
+  backup_str = verifystr;
+
+  skip_whitespace (backup_str);
+  if ((reg_rd = reg_required_here (&backup_str, -1, REG_TYPE_SCORE)) == (int) FAIL)
+    return;
+
+  if (skip_past_comma (&backup_str) == (int) FAIL)
+    return;
+
+  label_str = backup_str;
+
+  /* Ld/st rD, [rA, imm]      ld/st rD, [rA]+, imm      ld/st rD, [rA, imm]+.  */
+  if (*backup_str == '[')
+    {
+      inst.type = Rd_rvalueRs_preSI12;
+      do_ldst_insn (str);
+      return;
+    }
+
+  /* Ld/st rD, imm.  */
+  absolute_value = backup_str;
+  inst.type = Rd_rvalueRs_SI15;
+  if ((my_get_expression (&inst.reloc.exp, &backup_str) == (int) FAIL)
+      || (validate_immediate (inst.reloc.exp.X_add_number, _VALUE, 0) == (int) FAIL)
+      || (end_of_line (backup_str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+      if (inst.reloc.exp.X_add_symbol == 0)
+        {
+          memcpy (&inst, &inst_backup, sizeof (struct score_it));
+          exp_macro_ldst_abs (str);
+          return;
+        }
+    }
+
+  /* Ld/st rD, label.  */
+  inst.type = Rd_rvalueRs_SI15;
+  backup_str = absolute_value;
+  if ((data_op2 (&backup_str, 1, _GP_IMM15) == (int) FAIL)
+      || (end_of_line (backup_str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+      if (inst.reloc.exp.X_add_symbol == 0)
+        {
+          if (!inst.error)
+	    inst.error = BAD_ARGS;
+
+          return;
+        }
+
+      if (score_pic == PIC)
+        {
+          int ldst_idx = 0;
+          ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+          build_lwst_pic (reg_rd, inst.reloc.exp, score_ldst_insns[ldst_idx * 3 + 0].template);
+          return;
+        }
+      else
+	{
+          if ((inst.reloc.exp.X_add_number <= 0x3fff)
+               && (inst.reloc.exp.X_add_number >= -0x4000)
+               && (!nopic_need_relax (inst.reloc.exp.X_add_symbol, 1)))
+	    {
+              int ldst_idx = 0;
+
+              /* Assign the real opcode.  */
+              ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+              inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+              inst.instruction |= score_ldst_insns[ldst_idx * 3 + 0].value;
+              inst.instruction |= reg_rd << 20;
+              inst.instruction |= GP << 15;
+              inst.relax_inst = 0x8000;
+              inst.relax_size = 0;
+              ldst_gp_p = 1;
+	    }
+	}
+    }
+
+  /* Backup inst.  */
+  memcpy (&inst_main, &inst, sizeof (struct score_it));
+  r1_bak = nor1;
+  nor1 = 0;
+
+  /* Determine which instructions should be output.  */
+  sprintf (append_str[0], "ld_i32hi r1, %s", label_str);
+  sprintf (append_str[1], "ld_i32lo r1, %s", label_str);
+  sprintf (append_str[2], "%s r%d, [r1, 0]", inst_backup.name, reg_rd);
+
+  /* Generate three instructions.
+     la r1, label
+     ld/st rd, [r1, 0]  */
+  for (i = 0; i < 3; i++)
+    {
+      if (append_insn (append_str[i], FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&inst_expand[i], &inst, sizeof (struct score_it));
+    }
+
+  if (ldst_gp_p)
+    {
+      char *p;
+
+      /* Adjust instruction opcode and to be relaxed instruction opcode.  */
+      inst_main.instruction = adjust_paritybit (inst_main.instruction, GET_INSN_CLASS (inst_main.type));
+      inst_main.relax_size = inst_expand[0].size + inst_expand[1].size + inst_expand[2].size;
+      inst_main.type = Insn_GP;
+
+      for (i = 0; i < 3; i++)
+	inst_expand[i].instruction = adjust_paritybit (inst_expand[i].instruction
+						       , GET_INSN_CLASS (inst_expand[i].type));
+
+      /* Check data dependency.  */
+      handle_dependency (&inst_main);
+
+      /* Start a new frag if frag_now is not empty.  */
+      if (frag_now_fix () != 0)
+        {
+          if (!frag_now->tc_frag_data.is_insn)
+	    frag_wane (frag_now);
+
+          frag_new (0);
+        }
+      frag_grow (20);
+
+      /* Write fr_fix part.  */
+      p = frag_more (inst_main.size);
+      md_number_to_chars (p, inst_main.instruction, inst_main.size);
+
+      if (inst_main.reloc.type != BFD_RELOC_NONE)
+        {
+          fix_new_score (frag_now, p - frag_now->fr_literal, inst_main.size,
+                         &inst_main.reloc.exp, inst_main.reloc.pc_rel, inst_main.reloc.type);
+        }
+
+#ifdef OBJ_ELF
+      dwarf2_emit_insn (inst_main.size);
+#endif
+
+      /* GP instruction can not do optimization, only can do relax between
+         1 instruction and 3 instructions.  */
+      p = frag_var (rs_machine_dependent, inst_main.relax_size + RELAX_PAD_BYTE, 0,
+                    RELAX_ENCODE (inst_main.size, inst_main.relax_size, inst_main.type, 0, 4, 0),
+                    inst_main.reloc.exp.X_add_symbol, 0, NULL);
+
+      /* Write fr_var part.
+         no calling gen_insn_frag, no fixS will be generated.  */
+      md_number_to_chars (p, inst_expand[0].instruction, inst_expand[0].size);
+      p += inst_expand[0].size;
+      md_number_to_chars (p, inst_expand[1].instruction, inst_expand[1].size);
+      p += inst_expand[1].size;
+      md_number_to_chars (p, inst_expand[2].instruction, inst_expand[2].size);
+    }
+  else
+    {
+      gen_insn_frag (&inst_expand[0], NULL);
+      gen_insn_frag (&inst_expand[1], NULL);
+      gen_insn_frag (&inst_expand[2], NULL);
+    }
+  nor1 = r1_bak;
+
+  /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+  inst.bwarn = -1;
+}
+
+static void
+do_lw_pic (char *str)
+{
+  int reg_rd;
+
+  skip_whitespace (str);
+  if (((reg_rd = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL)
+      || (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL)
+      || (end_of_line (str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+      if (inst.reloc.exp.X_add_symbol == 0)
+        {
+          if (!inst.error)
+	    inst.error = BAD_ARGS;
+
+          return;
+        }
+
+      inst.instruction |= GP << 15;
+      inst.reloc.type = BFD_RELOC_SCORE_GOT15;
+    }
+}
+
+static void
+do_empty (char *str)
+{
+  str = str;
+  if (university_version == 1)
+    {
+      if (((inst.instruction & 0x3e0003ff) == 0x0c000004)
+          || ((inst.instruction & 0x3e0003ff) == 0x0c000024)
+          || ((inst.instruction & 0x3e0003ff) == 0x0c000044)
+          || ((inst.instruction & 0x3e0003ff) == 0x0c000064))
+        {
+          inst.error = ERR_FOR_SCORE5U_MMU;
+          return;
+        }
+    }
+  if (end_of_line (str) == (int) FAIL)
+    return;
+
+  if (inst.relax_inst != 0x8000)
+    {
+      if (inst.type == NO_OPD)
+        {
+          inst.relax_size = 2;
+        }
+      else
+        {
+          inst.relax_size = 4;
+        }
+    }
+}
+
+static void
+do_jump (char *str)
+{
+  char *save_in;
+
+  skip_whitespace (str);
+  if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if (inst.reloc.exp.X_add_symbol == 0)
+    {
+      inst.error = _("lacking label  ");
+      return;
+    }
+
+  if (((inst.reloc.exp.X_add_number & 0xff000000) != 0)
+      && ((inst.reloc.exp.X_add_number & 0xff000000) != 0xff000000))
+    {
+      inst.error = _("invalid constant: 25 bit expression not in range -2^24..2^24");
+      return;
+    }
+
+  save_in = input_line_pointer;
+  input_line_pointer = str;
+  inst.reloc.type = BFD_RELOC_SCORE_JMP;
+  inst.reloc.pc_rel = 1;
+  input_line_pointer = save_in;
+}
+
+static void
+do16_jump (char *str)
+{
+  skip_whitespace (str);
+  if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else if (inst.reloc.exp.X_add_symbol == 0)
+    {
+      inst.error = _("lacking label  ");
+      return;
+    }
+  else if (((inst.reloc.exp.X_add_number & 0xfffff800) != 0)
+           && ((inst.reloc.exp.X_add_number & 0xfffff800) != 0xfffff800))
+    {
+      inst.error = _("invalid constant: 12 bit expression not in range -2^11..2^11");
+      return;
+    }
+
+  inst.reloc.type = BFD_RELOC_SCORE16_JMP;
+  inst.reloc.pc_rel = 1;
+}
+
+static void
+do_branch (char *str)
+{
+  unsigned long abs_value = 0;
+
+  if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else if (inst.reloc.exp.X_add_symbol == 0)
+    {
+      inst.error = _("lacking label  ");
+      return;
+    }
+  else if (((inst.reloc.exp.X_add_number & 0xff000000) != 0)
+           && ((inst.reloc.exp.X_add_number & 0xff000000) != 0xff000000))
+    {
+      inst.error = _("invalid constant: 20 bit expression not in range -2^19..2^19");
+      return;
+    }
+
+  inst.reloc.type = BFD_RELOC_SCORE_BRANCH;
+  inst.reloc.pc_rel = 1;
+
+  /* Branch 32  offset field : 20 bit, 16 bit branch offset field : 8 bit.  */
+  inst.instruction |= (inst.reloc.exp.X_add_number & 0x3fe) | ((inst.reloc.exp.X_add_number & 0xffc00) << 5);
+
+  /* Compute 16 bit branch instruction.  */
+  if ((inst.relax_inst != 0x8000) && (abs_value & 0xfffffe00) == 0)
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 8);
+      inst.relax_inst |= ((inst.reloc.exp.X_add_number >> 1) & 0xff);
+      inst.relax_size = 2;
+    }
+  else
+    {
+      inst.relax_inst = 0x8000;
+    }
+}
+
+static void
+do16_branch (char *str)
+{
+  if ((my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
+      || end_of_line (str) == (int) FAIL))
+    {
+      ;
+    }
+  else if (inst.reloc.exp.X_add_symbol == 0)
+    {
+      inst.error = _("lacking label");
+    }
+  else if (((inst.reloc.exp.X_add_number & 0xffffff00) != 0)
+           && ((inst.reloc.exp.X_add_number & 0xffffff00) != 0xffffff00))
+    {
+      inst.error = _("invalid constant: 9 bit expression not in range -2^8..2^8");
+    }
+  else
+    {
+      inst.reloc.type = BFD_RELOC_SCORE16_BRANCH;
+      inst.reloc.pc_rel = 1;
+      inst.instruction |= ((inst.reloc.exp.X_add_number >> 1) & 0xff);
+    }
+}
+
+/* Iterate over the base tables to create the instruction patterns.  */
+static void
+build_score_ops_hsh (void)
+{
+  unsigned int i;
+  static struct obstack insn_obstack;
+
+  obstack_begin (&insn_obstack, 4000);
+  for (i = 0; i < sizeof (score_insns) / sizeof (struct asm_opcode); i++)
+    {
+      const struct asm_opcode *insn = score_insns + i;
+      unsigned len = strlen (insn->template);
+      struct asm_opcode *new;
+      char *template;
+      new = obstack_alloc (&insn_obstack, sizeof (struct asm_opcode));
+      template = obstack_alloc (&insn_obstack, len + 1);
+
+      strcpy (template, insn->template);
+      new->template = template;
+      new->parms = insn->parms;
+      new->value = insn->value;
+      new->relax_value = insn->relax_value;
+      new->type = insn->type;
+      new->bitmask = insn->bitmask;
+      hash_insert (score_ops_hsh, new->template, (void *) new);
+    }
+}
+
+static void
+build_dependency_insn_hsh (void)
+{
+  unsigned int i;
+  static struct obstack dependency_obstack;
+
+  obstack_begin (&dependency_obstack, 4000);
+  for (i = 0; i < sizeof (insn_to_dependency_table) / sizeof (insn_to_dependency_table[0]); i++)
+    {
+      const struct insn_to_dependency *tmp = insn_to_dependency_table + i;
+      unsigned len = strlen (tmp->insn_name);
+      struct insn_to_dependency *new;
+
+      new = obstack_alloc (&dependency_obstack, sizeof (struct insn_to_dependency));
+      new->insn_name = obstack_alloc (&dependency_obstack, len + 1);
+
+      strcpy (new->insn_name, tmp->insn_name);
+      new->type = tmp->type;
+      hash_insert (dependency_insn_hsh, new->insn_name, (void *) new);
+    }
+}
+
+/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
+   for use in the a.out file, and stores them in the array pointed to by buf.
+   This knows about the endian-ness of the target machine and does
+   THE RIGHT THING, whatever it is.  Possible values for n are 1 (byte)
+   2 (short) and 4 (long)  Floating numbers are put out as a series of
+   LITTLENUMS (shorts, here at least).  */
+
+void
+md_number_to_chars (char *buf, valueT val, int n)
+{
+  if (target_big_endian)
+    number_to_chars_bigendian (buf, val, n);
+  else
+    number_to_chars_littleendian (buf, val, n);
+}
+
+static valueT
+md_chars_to_number (char *buf, int n)
+{
+  valueT result = 0;
+  unsigned char *where = (unsigned char *)buf;
+
+  if (target_big_endian)
+    {
+      while (n--)
+        {
+          result <<= 8;
+          result |= (*where++ & 255);
+        }
+    }
+  else
+    {
+      while (n--)
+        {
+          result <<= 8;
+          result |= (where[n] & 255);
+        }
+    }
+
+  return result;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type TYPE, and store the appropriate bytes in *LITP.  The number
+   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
+   returned, or NULL on OK.
+
+   Note that fp constants aren't represent in the normal way on the ARM.
+   In big endian mode, things are as expected.  However, in little endian
+   mode fp constants are big-endian word-wise, and little-endian byte-wise
+   within the words.  For example, (double) 1.1 in big endian mode is
+   the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
+   the byte sequence 99 99 f1 3f 9a 99 99 99.  */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  char *t;
+  int i;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+    case 'x':
+    case 'X':
+    case 'p':
+    case 'P':
+      prec = 6;
+      break;
+    default:
+      *sizeP = 0;
+      return _("bad call to MD_ATOF()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  *sizeP = prec * 2;
+
+  if (target_big_endian)
+    {
+      for (i = 0; i < prec; i++)
+        {
+          md_number_to_chars (litP, (valueT) words[i], 2);
+          litP += 2;
+        }
+    }
+  else
+    {
+      for (i = 0; i < prec; i += 2)
+        {
+          md_number_to_chars (litP, (valueT) words[i + 1], 2);
+          md_number_to_chars (litP + 2, (valueT) words[i], 2);
+          litP += 4;
+        }
+    }
+
+  return 0;
+}
+
+/* Return true if the given symbol should be considered local for PIC.  */
+
+static bfd_boolean
+pic_need_relax (symbolS *sym, asection *segtype)
+{
+  asection *symsec;
+  bfd_boolean linkonce;
+
+  /* Handle the case of a symbol equated to another symbol.  */
+  while (symbol_equated_reloc_p (sym))
+    {
+      symbolS *n;
+
+      /* It's possible to get a loop here in a badly written
+	 program.  */
+      n = symbol_get_value_expression (sym)->X_add_symbol;
+      if (n == sym)
+	break;
+      sym = n;
+    }
+
+  symsec = S_GET_SEGMENT (sym);
+
+  /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
+  linkonce = FALSE;
+  if (symsec != segtype && ! S_IS_LOCAL (sym))
+    {
+      if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) != 0)
+	linkonce = TRUE;
+
+      /* The GNU toolchain uses an extension for ELF: a section
+	  beginning with the magic string .gnu.linkonce is a linkonce
+	  section.  */
+      if (strncmp (segment_name (symsec), ".gnu.linkonce",
+		   sizeof ".gnu.linkonce" - 1) == 0)
+	linkonce = TRUE;
+    }
+
+  /* This must duplicate the test in adjust_reloc_syms.  */
+  return (symsec != &bfd_und_section
+	    && symsec != &bfd_abs_section
+	  && ! bfd_is_com_section (symsec)
+	    && !linkonce
+#ifdef OBJ_ELF
+	  /* A global or weak symbol is treated as external.  */
+	  && (OUTPUT_FLAVOR != bfd_target_elf_flavour
+	      || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
+#endif
+	  );
+}
+
+static int
+judge_size_before_relax (fragS * fragp, asection *sec)
+{
+  int change = 0;
+
+  if (score_pic == NO_PIC)
+    change = nopic_need_relax (fragp->fr_symbol, 0);
+  else
+    change = pic_need_relax (fragp->fr_symbol, sec);
+
+  if (change == 1)
+    {
+      /* Only at the first time determining whether GP instruction relax should be done,
+         return the difference between insntruction size and instruction relax size.  */
+      if (fragp->fr_opcode == NULL)
+	{
+	  fragp->fr_fix = RELAX_NEW (fragp->fr_subtype);
+	  fragp->fr_opcode = fragp->fr_literal + RELAX_RELOC1 (fragp->fr_subtype);
+          return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
+	}
+    }
+
+  return 0;
+}
+
+/* In this function, we determine whether GP instruction should do relaxation,
+   for the label being against was known now.
+   Doing this here but not in md_relax_frag() can induce iteration times
+   in stage of doing relax.  */
+int
+md_estimate_size_before_relax (fragS * fragp, asection * sec ATTRIBUTE_UNUSED)
+{
+  if ((RELAX_TYPE (fragp->fr_subtype) == Insn_GP)
+      || (RELAX_TYPE (fragp->fr_subtype) == Insn_PIC))
+    return judge_size_before_relax (fragp, sec);
+
+  return 0;
+}
+
+static int
+b32_relax_to_b16 (fragS * fragp)
+{
+  int grows = 0;
+  int relaxable_p = 0;
+  int old;
+  int new;
+  int frag_addr = fragp->fr_address + fragp->insn_addr;
+
+  addressT symbol_address = 0;
+  symbolS *s;
+  offsetT offset;
+  unsigned long value;
+  unsigned long abs_value;
+
+  /* FIXME : here may be able to modify better .
+     I don't know how to get the fragp's section ,
+     so in relax stage , it may be wrong to calculate the symbol's offset when the frag's section
+     is different from the symbol's.  */
+
+  old = RELAX_OLD (fragp->fr_subtype);
+  new = RELAX_NEW (fragp->fr_subtype);
+  relaxable_p = RELAX_OPT (fragp->fr_subtype);
+
+  s = fragp->fr_symbol;
+  /* b/bl immediate  */
+  if (s == NULL)
+    frag_addr = 0;
+  else
+    {
+      if (s->bsym != 0)
+	symbol_address = (addressT) s->sy_frag->fr_address;
+    }
+
+  value = md_chars_to_number (fragp->fr_literal, INSN_SIZE);
+
+  /* b 32's offset : 20 bit, b 16's tolerate field : 0xff.  */
+  offset = ((value & 0x3ff0000) >> 6) | (value & 0x3fe);
+  if ((offset & 0x80000) == 0x80000)
+    offset |= 0xfff00000;
+
+  abs_value = offset + symbol_address - frag_addr;
+  if ((abs_value & 0x80000000) == 0x80000000)
+    abs_value = 0xffffffff - abs_value + 1;
+
+  /* Relax branch 32 to branch 16.  */
+  if (relaxable_p && (s->bsym != NULL) && ((abs_value & 0xffffff00) == 0)
+      && (S_IS_DEFINED (s) && !S_IS_COMMON (s) && !S_IS_EXTERNAL (s)))
+    {
+      /* do nothing.  */
+    }
+  else
+    {
+      /* Branch 32 can not be relaxed to b 16, so clear OPT bit.  */
+      fragp->fr_opcode = NULL;
+      fragp->fr_subtype = RELAX_OPT_CLEAR (fragp->fr_subtype);
+    }
+
+  return grows;
+}
+
+/* Main purpose is to determine whether one frag should do relax.
+   frag->fr_opcode indicates this point.  */
+
+int
+score_relax_frag (asection * sec ATTRIBUTE_UNUSED, fragS * fragp, long stretch ATTRIBUTE_UNUSED)
+{
+  int grows = 0;
+  int insn_size;
+  int insn_relax_size;
+  int do_relax_p = 0;           /* Indicate doing relaxation for this frag.  */
+  int relaxable_p = 0;
+  bfd_boolean word_align_p = FALSE;
+  fragS *next_fragp;
+
+  /* If the instruction address is odd, make it half word align first.  */
+  if ((fragp->fr_address) % 2 != 0)
+    {
+      if ((fragp->fr_address + fragp->insn_addr) % 2 != 0)
+	{
+          fragp->insn_addr = 1;
+          grows += 1;
+	}
+    }
+
+  word_align_p = ((fragp->fr_address + fragp->insn_addr) % 4 == 0) ? TRUE : FALSE;
+
+  /* Get instruction size and relax size after the last relaxation.  */
+  if (fragp->fr_opcode)
+    {
+      insn_size = RELAX_NEW (fragp->fr_subtype);
+      insn_relax_size = RELAX_OLD (fragp->fr_subtype);
+    }
+  else
+    {
+      insn_size = RELAX_OLD (fragp->fr_subtype);
+      insn_relax_size = RELAX_NEW (fragp->fr_subtype);
+    }
+
+  /* Handle specially for GP instruction.  for, judge_size_before_relax() has already determine
+     whether the GP instruction should do relax.  */
+  if ((RELAX_TYPE (fragp->fr_subtype) == Insn_GP)
+      || (RELAX_TYPE (fragp->fr_subtype) == Insn_PIC))
+    {
+      if (!word_align_p)
+        {
+          if (fragp->insn_addr < 2)
+            {
+              fragp->insn_addr += 2;
+              grows += 2;
+            }
+          else
+            {
+              fragp->insn_addr -= 2;
+              grows -= 2;
+            }
+        }
+
+      if (fragp->fr_opcode)
+	fragp->fr_fix = RELAX_NEW (fragp->fr_subtype) + fragp->insn_addr;
+      else
+	fragp->fr_fix = RELAX_OLD (fragp->fr_subtype) + fragp->insn_addr;
+    }
+  else
+    {
+      if (RELAX_TYPE (fragp->fr_subtype) == PC_DISP19div2)
+	b32_relax_to_b16 (fragp);
+
+      relaxable_p = RELAX_OPT (fragp->fr_subtype);
+      next_fragp = fragp->fr_next;
+      while ((next_fragp) && (next_fragp->fr_type != rs_machine_dependent))
+	{
+          next_fragp = next_fragp->fr_next;
+	}
+
+      if (next_fragp)
+        {
+          int n_insn_size;
+          int n_relaxable_p = 0;
+
+          if (next_fragp->fr_opcode)
+            {
+              n_insn_size = RELAX_NEW (next_fragp->fr_subtype);
+            }
+          else
+            {
+              n_insn_size = RELAX_OLD (next_fragp->fr_subtype);
+            }
+
+          if (RELAX_TYPE (next_fragp->fr_subtype) == PC_DISP19div2)
+            b32_relax_to_b16 (next_fragp);
+          n_relaxable_p = RELAX_OPT (next_fragp->fr_subtype);
+
+          if (word_align_p)
+            {
+              if (insn_size == 4)
+                {
+                  /* 32 -> 16.  */
+                  if (relaxable_p && ((n_insn_size == 2) || n_relaxable_p))
+                    {
+                      grows -= 2;
+                      do_relax_p = 1;
+                    }
+                }
+              else if (insn_size == 2)
+                {
+                  /* 16 -> 32.  */
+                  if (relaxable_p && (((n_insn_size == 4) && !n_relaxable_p) || (n_insn_size > 4)))
+                    {
+                      grows += 2;
+                      do_relax_p = 1;
+                    }
+                }
+              else
+                {
+		  abort ();
+                }
+            }
+          else
+            {
+              if (insn_size == 4)
+                {
+                  /* 32 -> 16.  */
+                  if (relaxable_p)
+                    {
+                      grows -= 2;
+                      do_relax_p = 1;
+                    }
+                  /* Make the 32 bit insturction word align.  */
+                  else
+                    {
+                      fragp->insn_addr += 2;
+                      grows += 2;
+		    }
+                }
+              else if (insn_size == 2)
+                {
+                  /* Do nothing.  */
+                }
+              else
+                {
+		  abort ();
+                }
+            }
+        }
+      else
+        {
+	  /* Here, try best to do relax regardless fragp->fr_next->fr_type.  */
+          if (word_align_p == FALSE)
+            {
+              if (insn_size % 4 == 0)
+                {
+                  /* 32 -> 16.  */
+                  if (relaxable_p)
+                    {
+                      grows -= 2;
+                      do_relax_p = 1;
+                    }
+                  else
+                    {
+                      fragp->insn_addr += 2;
+                      grows += 2;
+                    }
+                }
+            }
+          else
+            {
+	      /* Do nothing.  */
+            }
+        }
+
+      /* fragp->fr_opcode indicates whether this frag should be relaxed.  */
+      if (do_relax_p)
+        {
+          if (fragp->fr_opcode)
+            {
+              fragp->fr_opcode = NULL;
+	      /* Guarantee estimate stage is correct.  */
+              fragp->fr_fix = RELAX_OLD (fragp->fr_subtype);
+              fragp->fr_fix += fragp->insn_addr;
+            }
+          else
+            {
+              fragp->fr_opcode = fragp->fr_literal + RELAX_RELOC1 (fragp->fr_subtype);
+	      /* Guarantee estimate stage is correct.  */
+              fragp->fr_fix = RELAX_NEW (fragp->fr_subtype);
+              fragp->fr_fix += fragp->insn_addr;
+            }
+        }
+      else
+	{
+          if (fragp->fr_opcode)
+            {
+	      /* Guarantee estimate stage is correct.  */
+              fragp->fr_fix = RELAX_NEW (fragp->fr_subtype);
+              fragp->fr_fix += fragp->insn_addr;
+            }
+          else
+            {
+	      /* Guarantee estimate stage is correct.  */
+              fragp->fr_fix = RELAX_OLD (fragp->fr_subtype);
+              fragp->fr_fix += fragp->insn_addr;
+            }
+	}
+    }
+
+  return grows;
+}
+
+void
+md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, fragS * fragp)
+{
+  int old;
+  int new;
+  char backup[20];
+  fixS *fixp;
+
+  old = RELAX_OLD (fragp->fr_subtype);
+  new = RELAX_NEW (fragp->fr_subtype);
+
+  /* fragp->fr_opcode indicates whether this frag should be relaxed.  */
+  if (fragp->fr_opcode == NULL)
+    {
+      memcpy (backup, fragp->fr_literal, old);
+      fragp->fr_fix = old;
+    }
+  else
+    {
+      memcpy (backup, fragp->fr_literal + old, new);
+      fragp->fr_fix = new;
+    }
+
+  fixp = fragp->tc_frag_data.fixp;
+  while (fixp && fixp->fx_frag == fragp && fixp->fx_where < old)
+    {
+      if (fragp->fr_opcode)
+	fixp->fx_done = 1;
+      fixp = fixp->fx_next;
+    }
+  while (fixp && fixp->fx_frag == fragp)
+    {
+      if (fragp->fr_opcode)
+	fixp->fx_where -= old + fragp->insn_addr;
+      else
+	fixp->fx_done = 1;
+      fixp = fixp->fx_next;
+    }
+
+  if (fragp->insn_addr)
+    {
+      md_number_to_chars (fragp->fr_literal, 0x0, fragp->insn_addr);
+    }
+  memcpy (fragp->fr_literal + fragp->insn_addr, backup, fragp->fr_fix);
+  fragp->fr_fix += fragp->insn_addr;
+}
+
+/* Implementation of md_frag_check.
+   Called after md_convert_frag().  */
+
+void
+score_frag_check (fragS * fragp ATTRIBUTE_UNUSED)
+{
+  know (fragp->insn_addr <= RELAX_PAD_BYTE);
+}
+
+bfd_boolean
+score_fix_adjustable (fixS * fixP)
+{
+  if (fixP->fx_addsy == NULL)
+    {
+      return 1;
+    }
+  else if (OUTPUT_FLAVOR == bfd_target_elf_flavour
+      && (S_IS_EXTERNAL (fixP->fx_addsy) || S_IS_WEAK (fixP->fx_addsy)))
+    {
+      return 0;
+    }
+  else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+    {
+      return 0;
+    }
+
+  return 1;
+}
+
+/* Implementation of TC_VALIDATE_FIX.
+   Called before md_apply_fix() and after md_convert_frag().  */
+void
+score_validate_fix (fixS *fixP)
+{
+  fixP->fx_where += fixP->fx_frag->insn_addr;
+}
+
+long
+md_pcrel_from (fixS * fixP)
+{
+  long retval = 0;
+
+  if (fixP->fx_addsy
+      && (S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
+      && (fixP->fx_subsy == NULL))
+    {
+      retval = 0;
+    }
+  else
+    {
+      retval = fixP->fx_where + fixP->fx_frag->fr_address;
+    }
+
+  return retval;
+}
+
+int
+score_force_relocation (struct fix *fixp)
+{
+  int retval = 0;
+
+  if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+      || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
+      || fixp->fx_r_type == BFD_RELOC_SCORE_JMP
+      || fixp->fx_r_type == BFD_RELOC_SCORE_BRANCH
+      || fixp->fx_r_type == BFD_RELOC_SCORE16_JMP
+      || fixp->fx_r_type == BFD_RELOC_SCORE16_BRANCH)
+    {
+      retval = 1;
+    }
+
+  return retval;
+}
+
+/* Round up a section size to the appropriate boundary.  */
+valueT
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, segment);
+
+  return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+{
+  offsetT value = *valP;
+  offsetT abs_value = 0;
+  offsetT newval;
+  offsetT content;
+  unsigned short HI, LO;
+
+  char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+  assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
+  if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
+    {
+      if (fixP->fx_r_type != BFD_RELOC_SCORE_DUMMY_HI16)
+        fixP->fx_done = 1;
+    }
+
+  /* If this symbol is in a different section then we need to leave it for
+     the linker to deal with.  Unfortunately, md_pcrel_from can't tell,
+     so we have to undo it's effects here.  */
+  if (fixP->fx_pcrel)
+    {
+      if (fixP->fx_addsy != NULL
+	  && S_IS_DEFINED (fixP->fx_addsy)
+	  && S_GET_SEGMENT (fixP->fx_addsy) != seg)
+	value += md_pcrel_from (fixP);
+    }
+
+  /* Remember value for emit_reloc.  */
+  fixP->fx_addnumber = value;
+
+  switch (fixP->fx_r_type)
+    {
+    case BFD_RELOC_HI16_S:
+      if (fixP->fx_done)
+        {                       /* For la rd, imm32.  */
+          newval = md_chars_to_number (buf, INSN_SIZE);
+          HI = (value) >> 16;   /* mul to 2, then take the hi 16 bit.  */
+          newval |= (HI & 0x3fff) << 1;
+          newval |= ((HI >> 14) & 0x3) << 16;
+          md_number_to_chars (buf, newval, INSN_SIZE);
+        }
+      break;
+    case BFD_RELOC_LO16:
+      if (fixP->fx_done)        /* For la rd, imm32.  */
+        {
+          newval = md_chars_to_number (buf, INSN_SIZE);
+          LO = (value) & 0xffff;
+          newval |= (LO & 0x3fff) << 1; /* 16 bit: imm -> 14 bit in lo, 2 bit in hi.  */
+          newval |= ((LO >> 14) & 0x3) << 16;
+          md_number_to_chars (buf, newval, INSN_SIZE);
+        }
+      break;
+    case BFD_RELOC_SCORE_JMP:
+      {
+        content = md_chars_to_number (buf, INSN_SIZE);
+        value = fixP->fx_offset;
+        content = (content & ~0x3ff7ffe) | ((value << 1) & 0x3ff0000) | (value & 0x7fff);
+        md_number_to_chars (buf, content, INSN_SIZE);
+      }
+      break;
+    case BFD_RELOC_SCORE_BRANCH:
+      if ((S_GET_SEGMENT (fixP->fx_addsy) != seg) || (fixP->fx_addsy != NULL && S_IS_EXTERNAL (fixP->fx_addsy)))
+        value = fixP->fx_offset;
+      else
+        fixP->fx_done = 1;
+
+      content = md_chars_to_number (buf, INSN_SIZE);
+      if ((fixP->fx_frag->fr_opcode != 0) && ((content & 0x80008000) != 0x80008000))
+        {
+          if ((value & 0x80000000) == 0x80000000)
+            abs_value = 0xffffffff - value + 1;
+          if ((abs_value & 0xffffff00) != 0)
+            {
+              as_bad_where (fixP->fx_file, fixP->fx_line,
+                            _(" branch relocation truncate (0x%x) [-2^8 ~ 2^8]"), (unsigned int)value);
+              return;
+            }
+          content = md_chars_to_number (buf, INSN16_SIZE);
+          content &= 0xff00;
+          content = (content & 0xff00) | ((value >> 1) & 0xff);
+          md_number_to_chars (buf, content, INSN16_SIZE);
+          fixP->fx_r_type = BFD_RELOC_SCORE16_BRANCH;
+          fixP->fx_size = 2;
+        }
+      else
+        {
+          if ((value & 0x80000000) == 0x80000000)
+            abs_value = 0xffffffff - value + 1;
+          if ((abs_value & 0xfff80000) != 0)
+            {
+              as_bad_where (fixP->fx_file, fixP->fx_line,
+                            _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19]"), (unsigned int)value);
+              return;
+            }
+          content = md_chars_to_number (buf, INSN_SIZE);
+          content &= 0xfc00fc01;
+          content = (content & 0xfc00fc01) | (value & 0x3fe) | ((value << 6) & 0x3ff0000);
+          md_number_to_chars (buf, content, INSN_SIZE);
+        }
+      break;
+    case BFD_RELOC_SCORE16_JMP:
+      content = md_chars_to_number (buf, INSN16_SIZE);
+      content &= 0xf001;
+      value = fixP->fx_offset & 0xfff;
+      content = (content & 0xfc01) | (value & 0xffe);
+      md_number_to_chars (buf, content, INSN16_SIZE);
+      break;
+    case BFD_RELOC_SCORE16_BRANCH:
+      content = md_chars_to_number (buf, INSN_SIZE);
+      if ((fixP->fx_frag->fr_opcode != 0) && ((content & 0x80008000) == 0x80008000))
+        {
+          if ((S_GET_SEGMENT (fixP->fx_addsy) != seg) ||
+              (fixP->fx_addsy != NULL && S_IS_EXTERNAL (fixP->fx_addsy)))
+            value = fixP->fx_offset;
+          else
+            fixP->fx_done = 1;
+          if ((value & 0x80000000) == 0x80000000)
+            abs_value = 0xffffffff - value + 1;
+          if ((abs_value & 0xfff80000) != 0)
+            {
+              as_bad_where (fixP->fx_file, fixP->fx_line,
+                            _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19]"), (unsigned int)value);
+              return;
+            }
+          content = md_chars_to_number (buf, INSN_SIZE);
+          content = (content & 0xfc00fc01) | (value & 0x3fe) | ((value << 6) & 0x3ff0000);
+          md_number_to_chars (buf, content, INSN_SIZE);
+          fixP->fx_r_type = BFD_RELOC_SCORE_BRANCH;
+          fixP->fx_size = 4;
+          break;
+        }
+      else
+        {
+          /* In differnt section.  */
+          if ((S_GET_SEGMENT (fixP->fx_addsy) != seg) ||
+              (fixP->fx_addsy != NULL && S_IS_EXTERNAL (fixP->fx_addsy)))
+            value = fixP->fx_offset;
+          else
+            fixP->fx_done = 1;
+
+          if ((value & 0x80000000) == 0x80000000)
+            abs_value = 0xffffffff - value + 1;
+          if ((abs_value & 0xffffff00) != 0)
+            {
+              as_bad_where (fixP->fx_file, fixP->fx_line,
+                            _(" branch relocation truncate (0x%x)  [-2^8 ~ 2^8]"), (unsigned int)value);
+              return;
+            }
+          content = md_chars_to_number (buf, INSN16_SIZE);
+          content = (content & 0xff00) | ((value >> 1) & 0xff);
+          md_number_to_chars (buf, content, INSN16_SIZE);
+          break;
+        }
+    case BFD_RELOC_8:
+      if (fixP->fx_done || fixP->fx_pcrel)
+	md_number_to_chars (buf, value, 1);
+#ifdef OBJ_ELF
+      else
+        {
+          value = fixP->fx_offset;
+          md_number_to_chars (buf, value, 1);
+        }
+#endif
+      break;
+
+    case BFD_RELOC_16:
+      if (fixP->fx_done || fixP->fx_pcrel)
+        md_number_to_chars (buf, value, 2);
+#ifdef OBJ_ELF
+      else
+        {
+          value = fixP->fx_offset;
+          md_number_to_chars (buf, value, 2);
+        }
+#endif
+      break;
+    case BFD_RELOC_RVA:
+    case BFD_RELOC_32:
+      if (fixP->fx_done || fixP->fx_pcrel)
+        md_number_to_chars (buf, value, 4);
+#ifdef OBJ_ELF
+      else
+        {
+          value = fixP->fx_offset;
+          md_number_to_chars (buf, value, 4);
+        }
+#endif
+      break;
+    case BFD_RELOC_VTABLE_INHERIT:
+      fixP->fx_done = 0;
+      if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy) && !S_IS_WEAK (fixP->fx_addsy))
+        S_SET_WEAK (fixP->fx_addsy);
+      break;
+    case BFD_RELOC_VTABLE_ENTRY:
+      fixP->fx_done = 0;
+      break;
+    case BFD_RELOC_SCORE_GPREL15:
+      content = md_chars_to_number (buf, INSN_SIZE);
+      if ((fixP->fx_frag->fr_opcode != 0) && ((content & 0xfc1c8000) != 0x94188000))
+        fixP->fx_r_type = BFD_RELOC_NONE;
+      fixP->fx_done = 0;
+      break;
+    case BFD_RELOC_SCORE_GOT15:
+    case BFD_RELOC_SCORE_DUMMY_HI16:
+    case BFD_RELOC_SCORE_GOT_LO16:
+    case BFD_RELOC_SCORE_CALL15:
+    case BFD_RELOC_GPREL32:
+      break;
+    case BFD_RELOC_NONE:
+    default:
+      as_bad_where (fixP->fx_file, fixP->fx_line, _("bad relocation fixup type (%d)"), fixP->fx_r_type);
+    }
+}
+
+/* Translate internal representation of relocation info to BFD target format.  */
+arelent **
+tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+{
+  static arelent *retval[MAX_RELOC_EXPANSION + 1];  /* MAX_RELOC_EXPANSION equals 2.  */
+  arelent *reloc;
+  bfd_reloc_code_real_type code;
+  char *type;
+  fragS *f;
+  symbolS *s;
+  expressionS e;
+
+  reloc = retval[0] = xmalloc (sizeof (arelent));
+  retval[1] = NULL;
+
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  reloc->addend = fixp->fx_offset;
+
+  /* If this is a variant frag, we may need to adjust the existing
+     reloc and generate a new one.  */
+  if (fixp->fx_frag->fr_opcode != NULL && (fixp->fx_r_type == BFD_RELOC_SCORE_GPREL15))
+    {
+      /* Update instruction imm bit.  */
+      offsetT newval;
+      unsigned short off;
+      char *buf;
+
+      buf = fixp->fx_frag->fr_literal + fixp->fx_frag->insn_addr;
+      newval = md_chars_to_number (buf, INSN_SIZE);
+      off = fixp->fx_offset >> 16;
+      newval |= (off & 0x3fff) << 1;
+      newval |= ((off >> 14) & 0x3) << 16;
+      md_number_to_chars (buf, newval, INSN_SIZE);
+
+      buf += INSN_SIZE;
+      newval = md_chars_to_number (buf, INSN_SIZE);
+      off = fixp->fx_offset & 0xffff;
+      newval |= ((off & 0x3fff) << 1);
+      newval |= (((off >> 14) & 0x3) << 16);
+      md_number_to_chars (buf, newval, INSN_SIZE);
+
+      retval[1] = xmalloc (sizeof (arelent));
+      retval[2] = NULL;
+      retval[1]->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+      *retval[1]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+      retval[1]->address = (reloc->address + RELAX_RELOC2 (fixp->fx_frag->fr_subtype));
+
+      f = fixp->fx_frag;
+      s = f->fr_symbol;
+      e = s->sy_value;
+
+      retval[1]->addend = 0;
+      retval[1]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
+      assert (retval[1]->howto != NULL);
+
+      fixp->fx_r_type = BFD_RELOC_HI16_S;
+    }
+
+  code = fixp->fx_r_type;
+  switch (fixp->fx_r_type)
+    {
+    case BFD_RELOC_32:
+      if (fixp->fx_pcrel)
+        {
+          code = BFD_RELOC_32_PCREL;
+          break;
+        }
+    case BFD_RELOC_HI16_S:
+    case BFD_RELOC_LO16:
+    case BFD_RELOC_SCORE_JMP:
+    case BFD_RELOC_SCORE_BRANCH:
+    case BFD_RELOC_SCORE16_JMP:
+    case BFD_RELOC_SCORE16_BRANCH:
+    case BFD_RELOC_VTABLE_ENTRY:
+    case BFD_RELOC_VTABLE_INHERIT:
+    case BFD_RELOC_SCORE_GPREL15:
+    case BFD_RELOC_SCORE_GOT15:
+    case BFD_RELOC_SCORE_DUMMY_HI16:
+    case BFD_RELOC_SCORE_GOT_LO16:
+    case BFD_RELOC_SCORE_CALL15:
+    case BFD_RELOC_GPREL32:
+    case BFD_RELOC_NONE:
+      code = fixp->fx_r_type;
+      break;
+    default:
+      type = _("<unknown>");
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+                    _("cannot represent %s relocation in this object file format"), type);
+      return NULL;
+    }
+
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
+  if (reloc->howto == NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+                    _("cannot represent %s relocation in this object file format1"),
+                    bfd_get_reloc_code_name (code));
+      return NULL;
+    }
+  /* HACK: Since arm ELF uses Rel instead of Rela, encode the
+     vtable entry to be used in the relocation's section offset.  */
+  if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+    reloc->address = fixp->fx_offset;
+
+  return retval;
+}
+
+void
+score_elf_final_processing (void)
+{
+  if (fix_data_dependency == 1)
+    {
+      elf_elfheader (stdoutput)->e_flags |= EF_SCORE_FIXDEP;
+    }
+  if (score_pic == PIC)
+    {
+      elf_elfheader (stdoutput)->e_flags |= EF_SCORE_PIC;
+    }
+}
+
+static void
+parse_pce_inst (char *insnstr)
+{
+  char c;
+  char *p;
+  char first[MAX_LITERAL_POOL_SIZE];
+  char second[MAX_LITERAL_POOL_SIZE];
+  struct score_it pec_part_1;
+
+  /* Get first part string of PCE.  */
+  p = strstr (insnstr, "||");
+  c = *p;
+  *p = '\0';
+  sprintf (first, "%s", insnstr);
+
+  /* Get second part string of PCE.  */
+  *p = c;
+  p += 2;
+  sprintf (second, "%s", p);
+
+  parse_16_32_inst (first, FALSE);
+  if (inst.error)
+    return;
+
+  memcpy (&pec_part_1, &inst, sizeof (inst));
+
+  parse_16_32_inst (second, FALSE);
+  if (inst.error)
+    return;
+
+  if (   ((pec_part_1.size == INSN_SIZE) && (inst.size == INSN_SIZE))
+      || ((pec_part_1.size == INSN_SIZE) && (inst.size == INSN16_SIZE))
+      || ((pec_part_1.size == INSN16_SIZE) && (inst.size == INSN_SIZE)))
+    {
+      inst.error = _("pce instruction error (16 bit || 16 bit)'");
+      sprintf (inst.str, insnstr);
+      return;
+    }
+
+  if (!inst.error)
+    gen_insn_frag (&pec_part_1, &inst);
+}
+
+void
+md_assemble (char *str)
+{
+  know (str);
+  know (strlen (str) < MAX_LITERAL_POOL_SIZE);
+
+  memset (&inst, '\0', sizeof (inst));
+  if (INSN_IS_PCE_P (str))
+    parse_pce_inst (str);
+  else
+    parse_16_32_inst (str, TRUE);
+
+  if (inst.error)
+    as_bad (_("%s -- `%s'"), inst.error, inst.str);
+}
+
+/* We handle all bad expressions here, so that we can report the faulty
+   instruction in the error message.  */
+void
+md_operand (expressionS * expr)
+{
+  if (in_my_get_expression)
+    {
+      expr->X_op = O_illegal;
+      if (inst.error == NULL)
+        {
+          inst.error = _("bad expression");
+        }
+    }
+}
+
+const char *md_shortopts = "nO::g::G:";
+
+#ifdef SCORE_BI_ENDIAN
+#define OPTION_EB             (OPTION_MD_BASE + 0)
+#define OPTION_EL             (OPTION_MD_BASE + 1)
+#else
+#if TARGET_BYTES_BIG_ENDIAN
+#define OPTION_EB             (OPTION_MD_BASE + 0)
+#else
+#define OPTION_EL             (OPTION_MD_BASE + 1)
+#endif
+#endif
+#define OPTION_FIXDD          (OPTION_MD_BASE + 2)
+#define OPTION_NWARN          (OPTION_MD_BASE + 3)
+#define OPTION_SCORE5         (OPTION_MD_BASE + 4)
+#define OPTION_SCORE5U        (OPTION_MD_BASE + 5)
+#define OPTION_SCORE7         (OPTION_MD_BASE + 6)
+#define OPTION_R1             (OPTION_MD_BASE + 7)
+#define OPTION_O0             (OPTION_MD_BASE + 8)
+#define OPTION_SCORE_VERSION  (OPTION_MD_BASE + 9)
+#define OPTION_PIC            (OPTION_MD_BASE + 10)
+
+struct option md_longopts[] =
+{
+#ifdef OPTION_EB
+  {"EB"     , no_argument, NULL, OPTION_EB},
+#endif
+#ifdef OPTION_EL
+  {"EL"     , no_argument, NULL, OPTION_EL},
+#endif
+  {"FIXDD"  , no_argument, NULL, OPTION_FIXDD},
+  {"NWARN"  , no_argument, NULL, OPTION_NWARN},
+  {"SCORE5" , no_argument, NULL, OPTION_SCORE5},
+  {"SCORE5U", no_argument, NULL, OPTION_SCORE5U},
+  {"SCORE7" , no_argument, NULL, OPTION_SCORE7},
+  {"USE_R1" , no_argument, NULL, OPTION_R1},
+  {"O0"     , no_argument, NULL, OPTION_O0},
+  {"V"      , no_argument, NULL, OPTION_SCORE_VERSION},
+  {"KPIC"   , no_argument, NULL, OPTION_PIC},
+  {NULL     , no_argument, NULL, 0}
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+int
+md_parse_option (int c, char *arg)
+{
+  switch (c)
+    {
+#ifdef OPTION_EB
+    case OPTION_EB:
+      target_big_endian = 1;
+      break;
+#endif
+#ifdef OPTION_EL
+    case OPTION_EL:
+      target_big_endian = 0;
+      break;
+#endif
+    case OPTION_FIXDD:
+      fix_data_dependency = 1;
+      break;
+    case OPTION_NWARN:
+      warn_fix_data_dependency = 0;
+      break;
+    case OPTION_SCORE5:
+      score7 = 0;
+      university_version = 0;
+      vector_size = SCORE5_PIPELINE;
+      break;
+    case OPTION_SCORE5U:
+      score7 = 0;
+      university_version = 1;
+      vector_size = SCORE5_PIPELINE;
+      break;
+    case OPTION_SCORE7:
+      score7 = 1;
+      university_version = 0;
+      vector_size = SCORE7_PIPELINE;
+      break;
+    case OPTION_R1:
+      nor1 = 0;
+      break;
+    case 'G':
+      g_switch_value = atoi (arg);
+      break;
+    case OPTION_O0:
+      g_opt = 0;
+      break;
+    case OPTION_SCORE_VERSION:
+      printf (_("Sunplus-v2-0-0-20060510\n"));
+      break;
+    case OPTION_PIC:
+      score_pic = PIC;
+      g_switch_value = 0;    /* Must set -G num as 0 to generate PIC code.  */
+      break;
+    default:
+      /* as_bad (_("unrecognized option `-%c%s'"), c, arg ? arg : "");  */
+      return 0;
+    }
+  return 1;
+}
+
+void
+md_show_usage (FILE * fp)
+{
+  fprintf (fp, _(" Score-specific assembler options:\n"));
+#ifdef OPTION_EB
+  fprintf (fp, _("\
+        -EB\t\tassemble code for a big-endian cpu\n"));
+#endif
+
+#ifdef OPTION_EL
+  fprintf (fp, _("\
+        -EL\t\tassemble code for a little-endian cpu\n"));
+#endif
+
+  fprintf (fp, _("\
+        -FIXDD\t\tassemble code for fix data dependency\n"));
+  fprintf (fp, _("\
+        -NWARN\t\tassemble code for no warning message for fix data dependency\n"));
+  fprintf (fp, _("\
+        -SCORE5\t\tassemble code for target is SCORE5\n"));
+  fprintf (fp, _("\
+        -SCORE5U\tassemble code for target is SCORE5U\n"));
+  fprintf (fp, _("\
+        -SCORE7\t\tassemble code for target is SCORE7, this is default setting\n"));
+  fprintf (fp, _("\
+        -USE_R1\t\tassemble code for no warning message when using temp register r1\n"));
+  fprintf (fp, _("\
+        -KPIC\t\tassemble code for PIC\n"));
+  fprintf (fp, _("\
+        -O0\t\tassembler will not perform any optimizations\n"));
+  fprintf (fp, _("\
+        -G gpnum\tassemble code for setting gpsize and default is 8 byte\n"));
+  fprintf (fp, _("\
+        -V \t\tSunplus release version \n"));
+}
+
+
+/* Pesudo handling functions.  */
+
+/* If we change section we must dump the literal pool first.  */
+static void
+s_score_bss (int ignore ATTRIBUTE_UNUSED)
+{
+  subseg_set (bss_section, (subsegT) get_absolute_expression ());
+  demand_empty_rest_of_line ();
+}
+
+static void
+s_score_text (int ignore)
+{
+  obj_elf_text (ignore);
+  record_alignment (now_seg, 2);
+}
+
+static void
+score_s_section (int ignore)
+{
+  obj_elf_section (ignore);
+  if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+    record_alignment (now_seg, 2);
+
+}
+
+static void
+s_change_sec (int sec)
+{
+  segT seg;
+
+#ifdef OBJ_ELF
+  /* The ELF backend needs to know that we are changing sections, so
+     that .previous works correctly.  We could do something like check
+     for an obj_section_change_hook macro, but that might be confusing
+     as it would not be appropriate to use it in the section changing
+     functions in read.c, since obj-elf.c intercepts those.  FIXME:
+     This should be cleaner, somehow.  */
+  obj_elf_section_change_hook ();
+#endif
+  switch (sec)
+    {
+    case 'r':
+      seg = subseg_new (RDATA_SECTION_NAME, (subsegT) get_absolute_expression ());
+      bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_RELOC | SEC_DATA));
+      if (strcmp (TARGET_OS, "elf") != 0)
+        record_alignment (seg, 4);
+      demand_empty_rest_of_line ();
+      break;
+    case 's':
+      seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
+      bfd_set_section_flags (stdoutput, seg, SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
+      if (strcmp (TARGET_OS, "elf") != 0)
+        record_alignment (seg, 4);
+      demand_empty_rest_of_line ();
+      break;
+    }
+}
+
+static void
+s_score_mask (int reg_type ATTRIBUTE_UNUSED)
+{
+  long mask, off;
+
+  if (cur_proc_ptr == (procS *) NULL)
+    {
+      as_warn (_(".mask outside of .ent"));
+      demand_empty_rest_of_line ();
+      return;
+    }
+  if (get_absolute_expression_and_terminator (&mask) != ',')
+    {
+      as_warn (_("Bad .mask directive"));
+      --input_line_pointer;
+      demand_empty_rest_of_line ();
+      return;
+    }
+  off = get_absolute_expression ();
+  cur_proc_ptr->reg_mask = mask;
+  cur_proc_ptr->reg_offset = off;
+  demand_empty_rest_of_line ();
+}
+
+static symbolS *
+get_symbol (void)
+{
+  int c;
+  char *name;
+  symbolS *p;
+
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  p = (symbolS *) symbol_find_or_make (name);
+  *input_line_pointer = c;
+  return p;
+}
+
+static long
+get_number (void)
+{
+  int negative = 0;
+  long val = 0;
+
+  if (*input_line_pointer == '-')
+    {
+      ++input_line_pointer;
+      negative = 1;
+    }
+  if (!ISDIGIT (*input_line_pointer))
+    as_bad (_("expected simple number"));
+  if (input_line_pointer[0] == '0')
+    {
+      if (input_line_pointer[1] == 'x')
+        {
+          input_line_pointer += 2;
+          while (ISXDIGIT (*input_line_pointer))
+            {
+              val <<= 4;
+              val |= hex_value (*input_line_pointer++);
+            }
+          return negative ? -val : val;
+        }
+      else
+        {
+          ++input_line_pointer;
+          while (ISDIGIT (*input_line_pointer))
+            {
+              val <<= 3;
+              val |= *input_line_pointer++ - '0';
+            }
+          return negative ? -val : val;
+        }
+    }
+  if (!ISDIGIT (*input_line_pointer))
+    {
+      printf (_(" *input_line_pointer == '%c' 0x%02x\n"), *input_line_pointer, *input_line_pointer);
+      as_warn (_("invalid number"));
+      return -1;
+    }
+  while (ISDIGIT (*input_line_pointer))
+    {
+      val *= 10;
+      val += *input_line_pointer++ - '0';
+    }
+  return negative ? -val : val;
+}
+
+/* The .aent and .ent directives.  */
+
+static void
+s_score_ent (int aent)
+{
+  symbolS *symbolP;
+  int maybe_text;
+
+  symbolP = get_symbol ();
+  if (*input_line_pointer == ',')
+    ++input_line_pointer;
+  SKIP_WHITESPACE ();
+  if (ISDIGIT (*input_line_pointer) || *input_line_pointer == '-')
+    get_number ();
+
+#ifdef BFD_ASSEMBLER
+  if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
+#else
+  if (now_seg != data_section && now_seg != bss_section)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
+#endif
+  if (!maybe_text)
+    as_warn (_(".ent or .aent not in text section."));
+  if (!aent && cur_proc_ptr)
+    as_warn (_("missing .end"));
+  if (!aent)
+    {
+      cur_proc_ptr = &cur_proc;
+      cur_proc_ptr->reg_mask = 0xdeadbeaf;
+      cur_proc_ptr->reg_offset = 0xdeadbeaf;
+      cur_proc_ptr->fpreg_mask = 0xdeafbeaf;
+      cur_proc_ptr->leaf = 0xdeafbeaf;
+      cur_proc_ptr->frame_offset = 0xdeafbeaf;
+      cur_proc_ptr->frame_reg = 0xdeafbeaf;
+      cur_proc_ptr->pc_reg = 0xdeafbeaf;
+      cur_proc_ptr->isym = symbolP;
+      symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
+      ++numprocs;
+      if (debug_type == DEBUG_STABS)
+        stabs_generate_asm_func (S_GET_NAME (symbolP), S_GET_NAME (symbolP));
+    }
+  demand_empty_rest_of_line ();
+}
+
+static void
+s_score_frame (int ignore ATTRIBUTE_UNUSED)
+{
+  char *backupstr;
+  char str[30];
+  long val;
+  int i = 0;
+
+  backupstr = input_line_pointer;
+
+#ifdef OBJ_ELF
+  if (cur_proc_ptr == (procS *) NULL)
+    {
+      as_warn (_(".frame outside of .ent"));
+      demand_empty_rest_of_line ();
+      return;
+    }
+  cur_proc_ptr->frame_reg = reg_required_here ((&backupstr), 0, REG_TYPE_SCORE);
+  SKIP_WHITESPACE ();
+  skip_past_comma (&backupstr);
+  while (*backupstr != ',')
+    {
+      str[i] = *backupstr;
+      i++;
+      backupstr++;
+    }
+  str[i] = '\0';
+  val = atoi (str);
+
+  SKIP_WHITESPACE ();
+  skip_past_comma (&backupstr);
+  cur_proc_ptr->frame_offset = val;
+  cur_proc_ptr->pc_reg = reg_required_here ((&backupstr), 0, REG_TYPE_SCORE);
+
+  SKIP_WHITESPACE ();
+  skip_past_comma (&backupstr);
+  i = 0;
+  while (*backupstr != '\n')
+    {
+      str[i] = *backupstr;
+      i++;
+      backupstr++;
+    }
+  str[i] = '\0';
+  val = atoi (str);
+  cur_proc_ptr->leaf = val;
+  SKIP_WHITESPACE ();
+  skip_past_comma (&backupstr);
+
+#endif /* OBJ_ELF */
+  while (input_line_pointer != backupstr)
+    input_line_pointer++;
+}
+
+/* The .end directive.  */
+static void
+s_score_end (int x ATTRIBUTE_UNUSED)
+{
+  symbolS *p;
+  int maybe_text;
+
+  /* Generate a .pdr section.  */
+  segT saved_seg = now_seg;
+  subsegT saved_subseg = now_subseg;
+  valueT dot;
+  expressionS exp;
+  char *fragp;
+
+  if (!is_end_of_line[(unsigned char)*input_line_pointer])
+    {
+      p = get_symbol ();
+      demand_empty_rest_of_line ();
+    }
+  else
+    p = NULL;
+
+#ifdef BFD_ASSEMBLER
+  if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
+#else
+  if (now_seg != data_section && now_seg != bss_section)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
+#endif
+
+  if (!maybe_text)
+    as_warn (_(".end not in text section"));
+  if (!cur_proc_ptr)
+    {
+      as_warn (_(".end directive without a preceding .ent directive."));
+      demand_empty_rest_of_line ();
+      return;
+    }
+  if (p != NULL)
+    {
+      assert (S_GET_NAME (p));
+      if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
+        as_warn (_(".end symbol does not match .ent symbol."));
+      if (debug_type == DEBUG_STABS)
+        stabs_generate_asm_endfunc (S_GET_NAME (p), S_GET_NAME (p));
+    }
+  else
+    as_warn (_(".end directive missing or unknown symbol"));
+
+  if ((cur_proc_ptr->reg_mask == 0xdeadbeaf) ||
+      (cur_proc_ptr->reg_offset == 0xdeadbeaf) ||
+      (cur_proc_ptr->leaf == 0xdeafbeaf) ||
+      (cur_proc_ptr->frame_offset == 0xdeafbeaf) ||
+      (cur_proc_ptr->frame_reg == 0xdeafbeaf) || (cur_proc_ptr->pc_reg == 0xdeafbeaf));
+
+  else
+    {
+      dot = frag_now_fix ();
+      assert (pdr_seg);
+      subseg_set (pdr_seg, 0);
+      /* Write the symbol.  */
+      exp.X_op = O_symbol;
+      exp.X_add_symbol = p;
+      exp.X_add_number = 0;
+      emit_expr (&exp, 4);
+      fragp = frag_more (7 * 4);
+      md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
+      md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
+      md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
+      md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->leaf, 4);
+      md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
+      md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
+      md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
+      subseg_set (saved_seg, saved_subseg);
+
+    }
+  cur_proc_ptr = NULL;
+}
+
+/* Handle the .set pseudo-op.  */
+static void
+s_score_set (int x ATTRIBUTE_UNUSED)
+{
+  int i = 0;
+  char name[MAX_LITERAL_POOL_SIZE];
+  char * orig_ilp = input_line_pointer;
+
+  while (!is_end_of_line[(unsigned char)*input_line_pointer])
+    {
+      name[i] = (char) * input_line_pointer;
+      i++;
+      ++input_line_pointer;
+    }
+
+  name[i] = '\0';
+
+  if (strcmp (name, "nwarn") == 0)
+    {
+      warn_fix_data_dependency = 0;
+    }
+  else if (strcmp (name, "fixdd") == 0)
+    {
+      fix_data_dependency = 1;
+    }
+  else if (strcmp (name, "nofixdd") == 0)
+    {
+      fix_data_dependency = 0;
+    }
+  else if (strcmp (name, "r1") == 0)
+    {
+      nor1 = 0;
+    }
+  else if (strcmp (name, "nor1") == 0)
+    {
+      nor1 = 1;
+    }
+  else if (strcmp (name, "optimize") == 0)
+    {
+      g_opt = 1;
+    }
+  else if (strcmp (name, "volatile") == 0)
+    {
+      g_opt = 0;
+    }
+  else if (strcmp (name, "pic") == 0)
+    {
+      score_pic = PIC;
+    }
+  else
+    {
+      input_line_pointer = orig_ilp;
+      s_set (0);
+    }
+}
+
+/* Handle the .cpload pseudo-op.  This is used when generating PIC code.  It sets the
+   $gp register for the function based on the function address, which is in the register
+   named in the argument. This uses a relocation against GP_DISP_LABEL, which is handled
+   specially by the linker.  The result is:
+   ldis gp, %hi(GP_DISP_LABEL)
+   ori  gp, %low(GP_DISP_LABEL)
+   add  gp, gp, .cpload argument
+   The .cpload argument is normally r29.  */
+
+static void
+s_score_cpload (int ignore ATTRIBUTE_UNUSED)
+{
+  int reg;
+  char insn_str[MAX_LITERAL_POOL_SIZE];
+
+  /* If we are not generating PIC code, .cpload is ignored.  */
+  if (score_pic == NO_PIC)
+    {
+      s_ignore (0);
+      return;
+    }
+
+  if ((reg = reg_required_here (&input_line_pointer, -1, REG_TYPE_SCORE)) == (int) FAIL)
+    return;
+
+  demand_empty_rest_of_line ();
+
+  sprintf (insn_str, "ld_i32hi r%d, %s", GP, GP_DISP_LABEL);
+  if (append_insn (insn_str, TRUE) == (int) FAIL)
+    return;
+
+  sprintf (insn_str, "ld_i32lo r%d, %s", GP, GP_DISP_LABEL);
+  if (append_insn (insn_str, TRUE) == (int) FAIL)
+    return;
+
+  sprintf (insn_str, "add r%d, r%d, r%d", GP, GP, reg);
+  if (append_insn (insn_str, TRUE) == (int) FAIL)
+    return;
+}
+
+/* Handle the .cprestore pseudo-op.  This stores $gp into a given
+   offset from $sp.  The offset is remembered, and after making a PIC
+   call $gp is restored from that location.  */
+
+static void
+s_score_cprestore (int ignore ATTRIBUTE_UNUSED)
+{
+  int reg;
+  int cprestore_offset;
+  char insn_str[MAX_LITERAL_POOL_SIZE];
+
+  /* If we are not generating PIC code, .cprestore is ignored.  */
+  if (score_pic == NO_PIC)
+    {
+      s_ignore (0);
+      return;
+    }
+
+  if ((reg = reg_required_here (&input_line_pointer, -1, REG_TYPE_SCORE)) == (int) FAIL
+      || skip_past_comma (&input_line_pointer) == (int) FAIL)
+    {
+      return;
+    }
+
+  cprestore_offset = get_absolute_expression ();
+
+  if (cprestore_offset <= 0x3fff)
+    {
+      sprintf (insn_str, "sw r%d, [r%d, %d]", GP, reg, cprestore_offset);
+      if (append_insn (insn_str, TRUE) == (int) FAIL)
+        return;
+    }
+  else
+    {
+      int r1_bak;
+
+      r1_bak = nor1;
+      nor1 = 0;
+
+      sprintf (insn_str, "li r1, %d", cprestore_offset);
+      if (append_insn (insn_str, TRUE) == (int) FAIL)
+        return;
+
+      sprintf (insn_str, "add r1, r1, r%d", reg);
+      if (append_insn (insn_str, TRUE) == (int) FAIL)
+        return;
+
+      sprintf (insn_str, "sw r%d, [r1]", GP);
+      if (append_insn (insn_str, TRUE) == (int) FAIL)
+        return;
+
+      nor1 = r1_bak;
+    }
+
+  demand_empty_rest_of_line ();
+}
+
+/* Handle the .gpword pseudo-op.  This is used when generating PIC
+   code.  It generates a 32 bit GP relative reloc.  */
+static void
+s_score_gpword (int ignore ATTRIBUTE_UNUSED)
+{
+  expressionS ex;
+  char *p;
+
+  /* When not generating PIC code, this is treated as .word.  */
+  if (score_pic == NO_PIC)
+    {
+      cons (4);
+      return;
+    }
+  expression (&ex);
+  if (ex.X_op != O_symbol || ex.X_add_number != 0)
+    {
+      as_bad (_("Unsupported use of .gpword"));
+      ignore_rest_of_line ();
+    }
+  p = frag_more (4);
+  md_number_to_chars (p, (valueT) 0, 4);
+  fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, BFD_RELOC_GPREL32);
+  demand_empty_rest_of_line ();
+}
+
+/* Handle the .cpadd pseudo-op.  This is used when dealing with switch
+   tables in PIC code.  */
+
+static void
+s_score_cpadd (int ignore ATTRIBUTE_UNUSED)
+{
+  int reg;
+  char insn_str[MAX_LITERAL_POOL_SIZE];
+
+  /* If we are not generating PIC code, .cpload is ignored.  */
+  if (score_pic == NO_PIC)
+    {
+      s_ignore (0);
+      return;
+    }
+
+  if ((reg = reg_required_here (&input_line_pointer, -1, REG_TYPE_SCORE)) == (int) FAIL)
+    {
+      return;
+    }
+  demand_empty_rest_of_line ();
+
+  /* Add $gp to the register named as an argument.  */
+  sprintf (insn_str, "add r%d, r%d, r%d", reg, reg, GP);
+  if (append_insn (insn_str, TRUE) == (int) FAIL)
+    return;
+}
+
+#ifndef TC_IMPLICIT_LCOMM_ALIGNMENT
+#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR)        	\
+    do								\
+    {                                                   	\
+    if ((SIZE) >= 8)                                      	\
+    (P2VAR) = 3;                                        	\
+    else if ((SIZE) >= 4)                                 	\
+    (P2VAR) = 2;                                        	\
+    else if ((SIZE) >= 2)                                 	\
+    (P2VAR) = 1;                                        	\
+    else                                                  	\
+    (P2VAR) = 0;                                        	\
+    }								\
+  while (0)
+#endif
+
+static void
+s_score_lcomm (int bytes_p)
+{
+  char *name;
+  char c;
+  char *p;
+  int temp;
+  symbolS *symbolP;
+  segT current_seg = now_seg;
+  subsegT current_subseg = now_subseg;
+  const int max_alignment = 15;
+  int align = 0;
+  segT bss_seg = bss_section;
+  int needs_align = 0;
+
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  p = input_line_pointer;
+  *p = c;
+
+  if (name == p)
+    {
+      as_bad (_("expected symbol name"));
+      discard_rest_of_line ();
+      return;
+    }
+
+  SKIP_WHITESPACE ();
+
+  /* Accept an optional comma after the name.  The comma used to be
+     required, but Irix 5 cc does not generate it.  */
+  if (*input_line_pointer == ',')
+    {
+      ++input_line_pointer;
+      SKIP_WHITESPACE ();
+    }
+
+  if (is_end_of_line[(unsigned char)*input_line_pointer])
+    {
+      as_bad (_("missing size expression"));
+      return;
+    }
+
+  if ((temp = get_absolute_expression ()) < 0)
+    {
+      as_warn (_("BSS length (%d) < 0 ignored"), temp);
+      ignore_rest_of_line ();
+      return;
+    }
+
+#if defined (TC_SCORE)
+  if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour || OUTPUT_FLAVOR == bfd_target_elf_flavour)
+    {
+      /* For Score and Alpha ECOFF or ELF, small objects are put in .sbss.  */
+      if ((unsigned)temp <= bfd_get_gp_size (stdoutput))
+        {
+          bss_seg = subseg_new (".sbss", 1);
+          seg_info (bss_seg)->bss = 1;
+#ifdef BFD_ASSEMBLER
+          if (!bfd_set_section_flags (stdoutput, bss_seg, SEC_ALLOC))
+            as_warn (_("error setting flags for \".sbss\": %s"), bfd_errmsg (bfd_get_error ()));
+#endif
+        }
+    }
+#endif
+
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer == ',')
+    {
+      ++input_line_pointer;
+      SKIP_WHITESPACE ();
+
+      if (is_end_of_line[(unsigned char)*input_line_pointer])
+        {
+          as_bad (_("missing alignment"));
+          return;
+        }
+      else
+        {
+          align = get_absolute_expression ();
+          needs_align = 1;
+        }
+    }
+
+  if (!needs_align)
+    {
+      TC_IMPLICIT_LCOMM_ALIGNMENT (temp, align);
+
+      /* Still zero unless TC_IMPLICIT_LCOMM_ALIGNMENT set it.  */
+      if (align)
+        record_alignment (bss_seg, align);
+    }
+
+  if (needs_align)
+    {
+      if (bytes_p)
+        {
+          /* Convert to a power of 2.  */
+          if (align != 0)
+            {
+              unsigned int i;
+
+              for (i = 0; align != 0; align >>= 1, ++i)
+                ;
+              align = i - 1;
+            }
+        }
+
+      if (align > max_alignment)
+        {
+          align = max_alignment;
+          as_warn (_("alignment too large; %d assumed"), align);
+        }
+      else if (align < 0)
+        {
+          align = 0;
+          as_warn (_("alignment negative; 0 assumed"));
+        }
+
+      record_alignment (bss_seg, align);
+    }
+  else
+    {
+      /* Assume some objects may require alignment on some systems.  */
+#if defined (TC_ALPHA) && ! defined (VMS)
+      if (temp > 1)
+        {
+          align = ffs (temp) - 1;
+          if (temp % (1 << align))
+            abort ();
+        }
+#endif
+    }
+
+  *p = 0;
+  symbolP = symbol_find_or_make (name);
+  *p = c;
+
+  if (
+#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT) \
+     || defined (OBJ_BOUT) || defined (OBJ_MAYBE_BOUT))
+#ifdef BFD_ASSEMBLER
+       (OUTPUT_FLAVOR != bfd_target_aout_flavour
+        || (S_GET_OTHER (symbolP) == 0 && S_GET_DESC (symbolP) == 0)) &&
+#else
+       (S_GET_OTHER (symbolP) == 0 && S_GET_DESC (symbolP) == 0) &&
+#endif
+#endif
+       (S_GET_SEGMENT (symbolP) == bss_seg || (!S_IS_DEFINED (symbolP) && S_GET_VALUE (symbolP) == 0)))
+    {
+      char *pfrag;
+
+      subseg_set (bss_seg, 1);
+
+      if (align)
+        frag_align (align, 0, 0);
+
+      /* Detach from old frag.  */
+      if (S_GET_SEGMENT (symbolP) == bss_seg)
+        symbol_get_frag (symbolP)->fr_symbol = NULL;
+
+      symbol_set_frag (symbolP, frag_now);
+      pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, (offsetT) temp, NULL);
+      *pfrag = 0;
+
+
+      S_SET_SEGMENT (symbolP, bss_seg);
+
+#ifdef OBJ_COFF
+      /* The symbol may already have been created with a preceding
+         ".globl" directive -- be careful not to step on storage class
+         in that case.  Otherwise, set it to static.  */
+      if (S_GET_STORAGE_CLASS (symbolP) != C_EXT)
+        {
+          S_SET_STORAGE_CLASS (symbolP, C_STAT);
+        }
+#endif /* OBJ_COFF */
+
+#ifdef S_SET_SIZE
+      S_SET_SIZE (symbolP, temp);
+#endif
+    }
+  else
+    as_bad (_("symbol `%s' is already defined"), S_GET_NAME (symbolP));
+
+  subseg_set (current_seg, current_subseg);
+
+  demand_empty_rest_of_line ();
+}
+
+static void
+insert_reg (const struct reg_entry *r, struct hash_control *htab)
+{
+  int i = 0;
+  int len = strlen (r->name) + 2;
+  char *buf = xmalloc (len);
+  char *buf2 = xmalloc (len);
+
+  strcpy (buf + i, r->name);
+  for (i = 0; buf[i]; i++)
+    {
+      buf2[i] = TOUPPER (buf[i]);
+    }
+  buf2[i] = '\0';
+
+  hash_insert (htab, buf, (void *) r);
+  hash_insert (htab, buf2, (void *) r);
+}
+
+static void
+build_reg_hsh (struct reg_map *map)
+{
+  const struct reg_entry *r;
+
+  if ((map->htab = hash_new ()) == NULL)
+    {
+      as_fatal (_("virtual memory exhausted"));
+    }
+  for (r = map->names; r->name != NULL; r++)
+    {
+      insert_reg (r, map->htab);
+    }
+}
+
+void
+md_begin (void)
+{
+  unsigned int i;
+  segT seg;
+  subsegT subseg;
+
+  if ((score_ops_hsh = hash_new ()) == NULL)
+    as_fatal (_("virtual memory exhausted"));
+
+  build_score_ops_hsh ();
+
+  if ((dependency_insn_hsh = hash_new ()) == NULL)
+    as_fatal (_("virtual memory exhausted"));
+
+  build_dependency_insn_hsh ();
+
+  for (i = (int)REG_TYPE_FIRST; i < (int)REG_TYPE_MAX; i++)
+    build_reg_hsh (all_reg_maps + i);
+
+  /* Initialize dependency vector.  */
+  init_dependency_vector ();
+
+  bfd_set_arch_mach (stdoutput, TARGET_ARCH, 0);
+  seg = now_seg;
+  subseg = now_subseg;
+  pdr_seg = subseg_new (".pdr", (subsegT) 0);
+  (void)bfd_set_section_flags (stdoutput, pdr_seg, SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
+  (void)bfd_set_section_alignment (stdoutput, pdr_seg, 2);
+  subseg_set (seg, subseg);
+
+  if (USE_GLOBAL_POINTER_OPT)
+    bfd_set_gp_size (stdoutput, g_switch_value);
+}
+
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  {"bss", s_score_bss, 0},
+  {"text", s_score_text, 0},
+  {"word", cons, 4},
+  {"long", cons, 4},
+  {"extend", float_cons, 'x'},
+  {"ldouble", float_cons, 'x'},
+  {"packed", float_cons, 'p'},
+  {"end", s_score_end, 0},
+  {"ent", s_score_ent, 0},
+  {"frame", s_score_frame, 0},
+  {"rdata", s_change_sec, 'r'},
+  {"sdata", s_change_sec, 's'},
+  {"set", s_score_set, 0},
+  {"mask", s_score_mask, 'R'},
+  {"dword", cons, 8},
+  {"lcomm", s_score_lcomm, 1},
+  {"section", score_s_section, 0},
+  {"cpload", s_score_cpload, 0},
+  {"cprestore", s_score_cprestore, 0},
+  {"gpword", s_score_gpword, 0},
+  {"cpadd", s_score_cpadd, 0},
+  {0, 0, 0}
+};
+
diff --git a/contrib/binutils/gas/config/tc-score.h b/contrib/binutils/gas/config/tc-score.h
new file mode 100644
index 0000000..2cd4039
--- /dev/null
+++ b/contrib/binutils/gas/config/tc-score.h
@@ -0,0 +1,83 @@
+/* tc-score.h -- Score specific file for assembler
+   Copyright 2006 Free Software Foundation, Inc.
+   Contributed by: 
+   Mei Ligang (ligang@sunnorth.com.cn)
+   Pei-Lin Tsai (pltsai@sunplus.com)
+ 
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef TC_SCORE
+#define TC_SCORE
+
+#define TARGET_ARCH 	            bfd_arch_score
+#define WORKING_DOT_WORD
+#define DIFF_EXPR_OK
+#define RELOC_EXPANSION_POSSIBLE
+#define MAX_RELOC_EXPANSION         2
+#define MAX_MEM_FOR_RS_ALIGN_CODE  (3 + 4)
+
+#define md_undefined_symbol(name)  NULL
+
+#define TARGET_FORMAT  (target_big_endian ? "elf32-bigscore" : "elf32-littlescore")
+
+#define md_relax_frag(segment, fragp, stretch)  score_relax_frag (segment, fragp, stretch)
+extern int score_relax_frag (asection *, struct frag *, long);
+
+#define md_frag_check(fragp)  score_frag_check (fragp)
+extern void score_frag_check (fragS *);
+
+#define TC_VALIDATE_FIX(FIXP, SEGTYPE, SKIP)  score_validate_fix (FIXP)
+extern void score_validate_fix (struct fix *);
+
+#define TC_FORCE_RELOCATION(FIXP)  score_force_relocation (FIXP)
+extern int score_force_relocation (struct fix *);
+
+#define tc_fix_adjustable(fixp)  score_fix_adjustable (fixp)
+extern bfd_boolean score_fix_adjustable (struct fix *);
+
+#define elf_tc_final_processing  score_elf_final_processing
+extern void score_elf_final_processing (void);
+
+struct score_tc_frag_data
+{
+  unsigned int is_insn;
+  struct fix *fixp;
+};
+
+#define TC_FRAG_TYPE struct score_tc_frag_data
+
+#define TC_FRAG_INIT(FRAGP) \
+  do \
+    { \
+      (FRAGP)->tc_frag_data.is_insn = (((FRAGP)->fr_type == rs_machine_dependent) ? 1 : 0); \
+    } \
+  while (0)
+
+#ifdef OBJ_ELF
+#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
+#else
+#define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_"
+#endif
+
+enum score_pic_level
+{
+  NO_PIC,
+  PIC
+};
+
+#endif /*TC_SCORE */
diff --git a/contrib/binutils/gas/config/tc-sparc.c b/contrib/binutils/gas/config/tc-sparc.c
index 10a1411..d4a409f 100644
--- a/contrib/binutils/gas/config/tc-sparc.c
+++ b/contrib/binutils/gas/config/tc-sparc.c
@@ -1,6 +1,6 @@
 /* tc-sparc.c -- Assemble for the SPARC
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
    This file is part of GAS, the GNU Assembler.
 
@@ -19,8 +19,6 @@
    to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
-
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -339,7 +337,7 @@ sparc_target_format ()
 #endif
 
 #ifdef OBJ_ELF
-  return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
+  return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
 #endif
 
   abort ();
@@ -547,12 +545,12 @@ md_parse_option (c, arg)
 	  {
 	    if (sparc_arch_size == 32)
 	      {
-		if (strcmp (*l, "elf32-sparc") == 0)
+		if (CONST_STRNEQ (*l, "elf32-sparc"))
 		  break;
 	      }
 	    else
 	      {
-		if (strcmp (*l, "elf64-sparc") == 0)
+		if (CONST_STRNEQ (*l, "elf64-sparc"))
 		  break;
 	      }
 	  }
@@ -1862,7 +1860,8 @@ sparc_ip (str, pinsn)
 	    case '\0':		/* End of args.  */
 	      if (s[0] == ',' && s[1] == '%')
 		{
-		  static const struct tls_ops {
+		  static const struct tls_ops
+		  {
 		    /* The name as it appears in assembler.  */
 		    char *name;
 		    /* strlen (name), precomputed for speed */
@@ -1871,7 +1870,9 @@ sparc_ip (str, pinsn)
 		    int reloc;
 		    /* 1 if call.  */
 		    int call;
-		  } tls_ops[] = {
+		  }
+		  tls_ops[] =
+		  {
 		    { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
 		    { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
 		    { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
@@ -1879,7 +1880,8 @@ sparc_ip (str, pinsn)
 		    { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
 		    { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
 		    { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
-		    { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }
+		    { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
+		    { NULL, 0, 0, 0 }
 		  };
 		  const struct tls_ops *o;
 		  char *s1;
@@ -3311,9 +3313,9 @@ md_apply_fix (fixP, valP, segment)
 	  break;
 
 	case BFD_RELOC_SPARC_WDISP16:
-	  /* FIXME: simplify.  */
-	  if (((val > 0) && (val & ~0x3fffc))
-	      || ((val < 0) && (~(val - 1) & ~0x3fffc)))
+	  if ((val & 3)
+	      || val >= 0x1fffc
+	      || val <= -(offsetT) 0x20008)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("relocation overflow"));
 	  /* FIXME: The +1 deserves a comment.  */
@@ -3322,9 +3324,9 @@ md_apply_fix (fixP, valP, segment)
 	  break;
 
 	case BFD_RELOC_SPARC_WDISP19:
-	  /* FIXME: simplify.  */
-	  if (((val > 0) && (val & ~0x1ffffc))
-	      || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
+	  if ((val & 3)
+	      || val >= 0xffffc
+	      || val <= -(offsetT) 0x100008)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("relocation overflow"));
 	  /* FIXME: The +1 deserves a comment.  */
@@ -3439,7 +3441,7 @@ md_apply_fix (fixP, valP, segment)
 
 arelent **
 tc_gen_reloc (section, fixp)
-     asection *section ATTRIBUTE_UNUSED;
+     asection *section;
      fixS *fixp;
 {
   static arelent *relocs[3];
@@ -3582,6 +3584,16 @@ tc_gen_reloc (section, fixp)
     }
 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT)  */
 
+  /* Nothing is aligned in DWARF debugging sections.  */
+  if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
+    switch (code)
+      {
+      case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
+      case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
+      case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
+      default: break;
+      }
+
   if (code == BFD_RELOC_SPARC_OLO10)
     reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
   else
@@ -4602,7 +4614,7 @@ sparc_cfi_frame_initial_instructions ()
 }
 
 int
-sparc_regname_to_dw2regnum (const char *regname)
+sparc_regname_to_dw2regnum (char *regname)
 {
   char *p, *q;
 
diff --git a/contrib/binutils/gas/config/tc-sparc.h b/contrib/binutils/gas/config/tc-sparc.h
index 14da16a..90c0e95 100644
--- a/contrib/binutils/gas/config/tc-sparc.h
+++ b/contrib/binutils/gas/config/tc-sparc.h
@@ -1,6 +1,7 @@
 /* tc-sparc.h - Macros and type defines for the sparc.
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
+   1999, 2000, 2001, 2002, 2003, 2005, 2007
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -31,6 +32,19 @@ struct frag;
 
 #define TARGET_ARCH bfd_arch_sparc
 
+#ifdef TE_FreeBSD
+#define ELF_TARGET_FORMAT	"elf32-sparc-freebsd"
+#define ELF64_TARGET_FORMAT	"elf64-sparc-freebsd"
+#endif
+
+#ifndef ELF_TARGET_FORMAT
+#define ELF_TARGET_FORMAT	"elf32-sparc"
+#endif
+
+#ifndef ELF64_TARGET_FORMAT
+#define ELF64_TARGET_FORMAT	"elf64-sparc"
+#endif
+
 extern const char *sparc_target_format PARAMS ((void));
 #define TARGET_FORMAT sparc_target_format ()
 
@@ -78,7 +92,6 @@ extern void sparc_handle_align PARAMS ((struct frag *));
 
 #define TC_FORCE_RELOCATION_LOCAL(FIX)		\
   (!(FIX)->fx_pcrel				\
-   || (FIX)->fx_plt				\
    || (sparc_pic_code				\
        && S_IS_EXTERNAL ((FIX)->fx_addsy))	\
    || TC_FORCE_RELOCATION (FIX))
@@ -171,7 +184,7 @@ extern void cons_fix_new_sparc
 extern void sparc_cfi_frame_initial_instructions PARAMS ((void));
 
 #define tc_regname_to_dw2regnum sparc_regname_to_dw2regnum
-extern int sparc_regname_to_dw2regnum PARAMS ((const char *regname));
+extern int sparc_regname_to_dw2regnum PARAMS ((char *regname));
 
 #define tc_cfi_emit_pcrel_expr sparc_cfi_emit_pcrel_expr
 extern void sparc_cfi_emit_pcrel_expr PARAMS ((expressionS *, unsigned int));
diff --git a/contrib/binutils/gas/config/tc-spu.c b/contrib/binutils/gas/config/tc-spu.c
new file mode 100644
index 0000000..ef801df
--- /dev/null
+++ b/contrib/binutils/gas/config/tc-spu.c
@@ -0,0 +1,1083 @@
+/* spu.c -- Assembler for the IBM Synergistic Processing Unit (SPU)
+
+   Copyright 2006, 2007 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "subsegs.h"
+#include "dwarf2dbg.h" 
+
+const struct spu_opcode spu_opcodes[] = {
+#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	{ MACFORMAT, (OPCODE) << (32-11), MNEMONIC, ASMFORMAT },
+#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	{ MACFORMAT, ((OPCODE) << (32-11)) | ((FB) << (32-18)), MNEMONIC, ASMFORMAT },
+#include "opcode/spu-insns.h"
+#undef APUOP
+#undef APUOPFB
+};
+
+static const int spu_num_opcodes =
+  sizeof (spu_opcodes) / sizeof (spu_opcodes[0]);
+
+#define MAX_RELOCS 2
+
+struct spu_insn
+{
+  unsigned int opcode;
+  expressionS exp[MAX_RELOCS];
+  int reloc_arg[MAX_RELOCS];
+  int flag[MAX_RELOCS];
+  enum spu_insns tag;
+};
+
+static const char *get_imm (const char *param, struct spu_insn *insn, int arg);
+static const char *get_reg (const char *param, struct spu_insn *insn, int arg,
+			    int accept_expr);
+static int calcop (struct spu_opcode *format, const char *param,
+		   struct spu_insn *insn);
+static void spu_cons (int);
+
+extern char *myname;
+static struct hash_control *op_hash = NULL;
+
+/* These bits should be turned off in the first address of every segment */
+int md_seg_align = 7;
+
+/* These chars start a comment anywhere in a source file (except inside
+   another comment */
+const char comment_chars[] = "#";
+
+/* These chars only start a comment at the beginning of a line.  */
+const char line_comment_chars[] = "#";
+
+/* gods own line continuation char */
+const char line_separator_chars[] = ";";
+
+/* Chars that can be used to separate mant from exp in floating point nums */
+const char EXP_CHARS[] = "eE";
+
+/* Chars that mean this number is a floating point constant */
+/* as in 0f123.456 */
+/* or    0H1.234E-12 (see exp chars above) */
+const char FLT_CHARS[] = "dDfF";
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  {"align", s_align_ptwo, 4},
+  {"bss", s_lcomm_bytes, 1},
+  {"def", s_set, 0},
+  {"dfloat", float_cons, 'd'},
+  {"ffloat", float_cons, 'f'},
+  {"global", s_globl, 0},
+  {"half", cons, 2},
+  {"int", spu_cons, 4},
+  {"long", spu_cons, 4},
+  {"quad", spu_cons, 8},
+  {"string", stringer, 1},
+  {"word", spu_cons, 4},
+  /* Force set to be treated as an instruction.  */
+  {"set", NULL, 0},
+  {".set", s_set, 0},
+  /* Likewise for eqv.  */
+  {"eqv", NULL, 0},
+  {".eqv", s_set, -1},
+  {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 }, 
+  {"loc", dwarf2_directive_loc, 0}, 
+  {0,0,0}
+};
+
+void
+md_begin (void)
+{
+  const char *retval = NULL;
+  int i;
+
+  /* initialize hash table */
+
+  op_hash = hash_new ();
+
+  /* loop until you see the end of the list */
+
+  for (i = 0; i < spu_num_opcodes; i++)
+    {
+      /* hash each mnemonic and record its position */
+
+      retval = hash_insert (op_hash, spu_opcodes[i].mnemonic, (PTR)&spu_opcodes[i]);
+
+      if (retval != NULL && strcmp (retval, "exists") != 0)
+	as_fatal (_("Can't hash instruction '%s':%s"),
+		  spu_opcodes[i].mnemonic, retval);
+    }
+}
+
+const char *md_shortopts = "";
+struct option md_longopts[] = {
+#define OPTION_APUASM (OPTION_MD_BASE)
+  {"apuasm", no_argument, NULL, OPTION_APUASM},
+#define OPTION_DD2 (OPTION_MD_BASE+1)
+  {"mdd2.0", no_argument, NULL, OPTION_DD2},
+#define OPTION_DD1 (OPTION_MD_BASE+2)
+  {"mdd1.0", no_argument, NULL, OPTION_DD1},
+#define OPTION_DD3 (OPTION_MD_BASE+3)
+  {"mdd3.0", no_argument, NULL, OPTION_DD3},
+  { NULL, no_argument, NULL, 0 }
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+/* When set (by -apuasm) our assembler emulates the behaviour of apuasm.
+ * e.g. don't add bias to float conversion and don't right shift
+ * immediate values. */
+static int emulate_apuasm;
+
+/* Use the dd2.0 instructions set.  The only differences are some new
+ * register names and the orx insn */
+static int use_dd2 = 1;
+
+int
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+{
+  switch (c)
+    {
+    case OPTION_APUASM:
+      emulate_apuasm = 1;
+      break;
+    case OPTION_DD3:
+      use_dd2 = 1;
+      break;
+    case OPTION_DD2:
+      use_dd2 = 1;
+      break;
+    case OPTION_DD1:
+      use_dd2 = 0;
+      break;
+    default:
+      return 0;
+    }
+  return 1;
+}
+
+void
+md_show_usage (FILE *stream)
+{
+  fputs (_("\
+SPU options:\n\
+  --apuasm		  emulate behaviour of apuasm\n"),
+	stream);
+}
+
+
+struct arg_encode {
+  int size;
+  int pos;
+  int rshift;
+  int lo, hi;
+  int wlo, whi;
+  bfd_reloc_code_real_type reloc;
+};
+
+static struct arg_encode arg_encode[A_MAX] = {
+  {  7,  0, 0,       0,    127,    0,   -1,  0 }, /* A_T */
+  {  7,  7, 0,       0,    127,    0,   -1,  0 }, /* A_A */
+  {  7, 14, 0,       0,    127,    0,   -1,  0 }, /* A_B */
+  {  7, 21, 0,       0,    127,    0,   -1,  0 }, /* A_C */
+  {  7,  7, 0,       0,    127,    0,   -1,  0 }, /* A_S */
+  {  7,  7, 0,       0,    127,    0,   -1,  0 }, /* A_H */
+  {  0,  0, 0,       0,     -1,    0,   -1,  0 }, /* A_P */
+  {  7, 14, 0,       0,     -1,    0,   -1,  BFD_RELOC_SPU_IMM7 }, /* A_S3 */
+  {  7, 14, 0,     -32,     31,  -31,    0,  BFD_RELOC_SPU_IMM7 }, /* A_S6 */
+  {  7, 14, 0,       0,     -1,    0,   -1,  BFD_RELOC_SPU_IMM7 }, /* A_S7N */
+  {  7, 14, 0,     -64,     63,  -63,    0,  BFD_RELOC_SPU_IMM7 }, /* A_S7 */
+  {  8, 14, 0,       0,    127,    0,   -1,  BFD_RELOC_SPU_IMM8 }, /* A_U7A */
+  {  8, 14, 0,       0,    127,    0,   -1,  BFD_RELOC_SPU_IMM8 }, /* A_U7B */
+  { 10, 14, 0,    -512,    511, -128,  255,  BFD_RELOC_SPU_IMM10 }, /* A_S10B */
+  { 10, 14, 0,    -512,    511,    0,   -1,  BFD_RELOC_SPU_IMM10 }, /* A_S10 */
+  {  2, 23, 9,   -1024,   1023,    0,   -1,  BFD_RELOC_SPU_PCREL9a }, /* A_S11 */
+  {  2, 14, 9,   -1024,   1023,    0,   -1,  BFD_RELOC_SPU_PCREL9b }, /* A_S11I */
+  { 10, 14, 4,   -8192,   8191,    0,   -1,  BFD_RELOC_SPU_IMM10W }, /* A_S14 */
+  { 16,  7, 0,  -32768,  32767,    0,   -1,  BFD_RELOC_SPU_IMM16 }, /* A_S16 */
+  { 16,  7, 2, -131072, 262143,    0,   -1,  BFD_RELOC_SPU_IMM16W }, /* A_S18 */
+  { 16,  7, 2, -262144, 262143,    0,   -1,  BFD_RELOC_SPU_PCREL16 }, /* A_R18 */
+  {  7, 14, 0,       0,     -1,    0,   -1,  BFD_RELOC_SPU_IMM7 }, /* A_U3 */
+  {  7, 14, 0,       0,    127,    0,   31,  BFD_RELOC_SPU_IMM7 }, /* A_U5 */
+  {  7, 14, 0,       0,    127,    0,   63,  BFD_RELOC_SPU_IMM7 }, /* A_U6 */
+  {  7, 14, 0,       0,     -1,    0,   -1,  BFD_RELOC_SPU_IMM7 }, /* A_U7 */
+  { 14,  0, 0,       0,  16383,    0,   -1,  0 }, /* A_U14 */
+  { 16,  7, 0,  -32768,  65535,    0,   -1,  BFD_RELOC_SPU_IMM16 }, /* A_X16 */
+  { 18,  7, 0,       0, 262143,    0,   -1,  BFD_RELOC_SPU_IMM18 }, /* A_U18 */
+};
+
+/* Some flags for handling errors.  This is very hackish and added after
+ * the fact. */
+static int syntax_error_arg;
+static const char *syntax_error_param;
+static int syntax_reg;
+
+static char *
+insn_fmt_string (struct spu_opcode *format)
+{
+  static char buf[64];
+  int len = 0;
+  int i;
+
+  len += sprintf (&buf[len], "%s\t", format->mnemonic);
+  for (i = 1; i <= format->arg[0]; i++)
+    {
+      int arg = format->arg[i];
+      char *exp;
+      if (i > 1 && arg != A_P && format->arg[i-1] != A_P) 
+	buf[len++] =  ',';
+      if (arg == A_P)
+	exp = "(";
+      else if (arg < A_P)
+	exp = i == syntax_error_arg ? "REG" : "reg";
+      else 
+	exp = i == syntax_error_arg ? "IMM" : "imm";
+      len += sprintf (&buf[len], "%s", exp);
+      if (i > 1 && format->arg[i-1] == A_P) 
+	buf[len++] =  ')';
+    }
+  buf[len] = 0;
+  return buf;
+}
+
+void
+md_assemble (char *op)
+{
+  char *param, *thisfrag;
+  char c;
+  struct spu_opcode *format;
+  struct spu_insn insn;
+  int i;
+
+  assert (op);
+
+  /* skip over instruction to find parameters */
+
+  for (param = op; *param != 0 && !ISSPACE (*param); param++)
+    ;
+  c = *param;
+  *param = 0;
+
+  if (c != 0 && c != '\n')
+    param++;
+
+  /* try to find the instruction in the hash table */
+
+  if ((format = (struct spu_opcode *) hash_find (op_hash, op)) == NULL)
+    {
+      as_bad (_("Invalid mnemonic '%s'"), op);
+      return;
+    }
+
+  if (!use_dd2 && strcmp (format->mnemonic, "orx") == 0)
+    {
+      as_bad (_("'%s' is only available in DD2.0 or higher."), op);
+      return;
+    }
+
+  while (1)
+    {
+      /* try parsing this instruction into insn */
+      for (i = 0; i < MAX_RELOCS; i++)
+	{
+	  insn.exp[i].X_add_symbol = 0;
+	  insn.exp[i].X_op_symbol = 0;
+	  insn.exp[i].X_add_number = 0;
+	  insn.exp[i].X_op = O_illegal;
+	  insn.reloc_arg[i] = -1;
+	  insn.flag[i] = 0;
+	}
+      insn.opcode = format->opcode;
+      insn.tag = (enum spu_insns) (format - spu_opcodes);
+
+      syntax_error_arg = 0;
+      syntax_error_param = 0;
+      syntax_reg = 0;
+      if (calcop (format, param, &insn))
+	break;
+
+      /* if it doesn't parse try the next instruction */
+      if (!strcmp (format[0].mnemonic, format[1].mnemonic))
+	format++;
+      else
+	{
+	  int parg = format[0].arg[syntax_error_arg-1];
+
+	  as_fatal (_("Error in argument %d.  Expecting:  \"%s\""),
+		    syntax_error_arg - (parg == A_P),
+		    insn_fmt_string (format));
+	  return;
+	}
+    }
+
+  if ((syntax_reg & 4)
+      && ! (insn.tag == M_RDCH
+	    || insn.tag == M_RCHCNT
+	    || insn.tag == M_WRCH))
+    as_warn (_("Mixing register syntax, with and without '$'."));
+  if (syntax_error_param)
+    {
+      const char *d = syntax_error_param;
+      while (*d != '$')
+	d--;
+      as_warn (_("Treating '%-*s' as a symbol."), (int)(syntax_error_param - d), d);
+    }
+
+  /* grow the current frag and plop in the opcode */
+
+  thisfrag = frag_more (4);
+  md_number_to_chars (thisfrag, insn.opcode, 4);
+
+  /* if this instruction requires labels mark it for later */
+
+  for (i = 0; i < MAX_RELOCS; i++)
+    if (insn.reloc_arg[i] >= 0) 
+      {
+        fixS *fixP;
+        bfd_reloc_code_real_type reloc = arg_encode[insn.reloc_arg[i]].reloc;
+	int pcrel = 0;
+
+        if (reloc == BFD_RELOC_SPU_PCREL9a
+	    || reloc == BFD_RELOC_SPU_PCREL9b
+            || reloc == BFD_RELOC_SPU_PCREL16)
+	  pcrel = 1;
+	if (insn.flag[i] == 1)
+	  reloc = BFD_RELOC_SPU_HI16;
+	else if (insn.flag[i] == 2)
+	  reloc = BFD_RELOC_SPU_LO16;
+	fixP = fix_new_exp (frag_now,
+			    thisfrag - frag_now->fr_literal,
+			    4,
+			    &insn.exp[i],
+			    pcrel,
+			    reloc);
+	fixP->tc_fix_data.arg_format = insn.reloc_arg[i];
+	fixP->tc_fix_data.insn_tag = insn.tag;
+      }
+  dwarf2_emit_insn (4);
+}
+
+static int
+calcop (struct spu_opcode *format, const char *param, struct spu_insn *insn)
+{
+  int i;
+  int paren = 0;
+  int arg;
+
+  for (i = 1; i <= format->arg[0]; i++)
+    {
+      arg = format->arg[i];
+      syntax_error_arg = i;
+
+      while (ISSPACE (*param))
+        param++;
+      if (*param == 0 || *param == ',')
+	return 0;
+      if (arg < A_P)
+        param = get_reg (param, insn, arg, 1);
+      else if (arg > A_P)
+        param = get_imm (param, insn,  arg);
+      else if (arg == A_P)
+	{
+	  paren++;
+	  if ('(' != *param++)
+	    return 0;
+	}
+
+      if (!param)
+	return 0;
+
+      while (ISSPACE (*param))
+        param++;
+
+      if (arg != A_P && paren)
+	{
+	  paren--;
+	  if (')' != *param++)
+	    return 0;
+	}
+      else if (i < format->arg[0]
+	       && format->arg[i] != A_P
+	       && format->arg[i+1] != A_P)
+	{
+	  if (',' != *param++)
+	    {
+	      syntax_error_arg++;
+	      return 0;
+	    }
+	}
+    }
+  while (ISSPACE (*param))
+    param++;
+  return !paren && (*param == 0 || *param == '\n');
+}
+
+struct reg_name {
+    unsigned int regno;
+    unsigned int length;
+    char name[32];
+};
+
+#define REG_NAME(NO,NM) { NO, sizeof (NM) - 1, NM }
+
+static struct reg_name reg_name[] = {
+  REG_NAME (0, "lr"),  /* link register */
+  REG_NAME (1, "sp"),  /* stack pointer */
+  REG_NAME (0, "rp"),  /* link register */
+  REG_NAME (127, "fp"),  /* frame pointer */
+};
+
+static struct reg_name sp_reg_name[] = {
+};
+
+static struct reg_name ch_reg_name[] = {
+  REG_NAME (  0, "SPU_RdEventStat"),
+  REG_NAME (  1, "SPU_WrEventMask"),
+  REG_NAME (  2, "SPU_WrEventAck"),
+  REG_NAME (  3, "SPU_RdSigNotify1"),
+  REG_NAME (  4, "SPU_RdSigNotify2"),
+  REG_NAME (  7, "SPU_WrDec"),
+  REG_NAME (  8, "SPU_RdDec"),
+  REG_NAME ( 11, "SPU_RdEventMask"), /* DD2.0 only */
+  REG_NAME ( 13, "SPU_RdMachStat"),
+  REG_NAME ( 14, "SPU_WrSRR0"),
+  REG_NAME ( 15, "SPU_RdSRR0"),
+  REG_NAME ( 28, "SPU_WrOutMbox"),
+  REG_NAME ( 29, "SPU_RdInMbox"),
+  REG_NAME ( 30, "SPU_WrOutIntrMbox"),
+  REG_NAME (  9, "MFC_WrMSSyncReq"),
+  REG_NAME ( 12, "MFC_RdTagMask"),   /* DD2.0 only */
+  REG_NAME ( 16, "MFC_LSA"),
+  REG_NAME ( 17, "MFC_EAH"),
+  REG_NAME ( 18, "MFC_EAL"),
+  REG_NAME ( 19, "MFC_Size"),
+  REG_NAME ( 20, "MFC_TagID"),
+  REG_NAME ( 21, "MFC_Cmd"),
+  REG_NAME ( 22, "MFC_WrTagMask"),
+  REG_NAME ( 23, "MFC_WrTagUpdate"),
+  REG_NAME ( 24, "MFC_RdTagStat"),
+  REG_NAME ( 25, "MFC_RdListStallStat"),
+  REG_NAME ( 26, "MFC_WrListStallAck"),
+  REG_NAME ( 27, "MFC_RdAtomicStat"),
+};
+#undef REG_NAME
+
+static const char *
+get_reg (const char *param, struct spu_insn *insn, int arg, int accept_expr)
+{
+  unsigned regno;
+  int saw_prefix = 0;
+
+  if (*param == '$')
+    {
+      saw_prefix = 1;
+      param++;
+    }
+    
+  if (arg == A_H) /* Channel */
+    {
+      if ((param[0] == 'c' || param[0] == 'C')
+	  && (param[1] == 'h' || param[1] == 'H')
+	  && ISDIGIT (param[2]))
+        param += 2;
+    }
+  else if (arg == A_S) /* Special purpose register */
+    {
+      if ((param[0] == 's' || param[0] == 'S')
+	  && (param[1] == 'p' || param[1] == 'P')
+	  && ISDIGIT (param[2]))
+        param += 2;
+    }
+
+  if (ISDIGIT (*param))
+    {
+      regno = 0;
+      while (ISDIGIT (*param))
+	regno = regno * 10 + *param++ - '0';
+    }
+  else
+    {
+      struct reg_name *rn;
+      unsigned int i, n, l = 0;
+
+      if (arg == A_H) /* Channel */
+	{
+	  rn = ch_reg_name;
+	  n = sizeof (ch_reg_name) / sizeof (*ch_reg_name);
+	}
+      else if (arg == A_S) /* Special purpose register */
+	{
+	  rn = sp_reg_name;
+	  n = sizeof (sp_reg_name) / sizeof (*sp_reg_name);
+	}
+      else
+	{
+	  rn = reg_name;
+	  n = sizeof (reg_name) / sizeof (*reg_name);
+	}
+      regno = 128;
+      for (i = 0; i < n; i++)
+	if (rn[i].length > l
+	    && 0 == strncasecmp (param, rn[i].name, rn[i].length))
+          {
+	    l = rn[i].length;
+            regno = rn[i].regno;
+          }
+      param += l;
+    }
+
+  if (!use_dd2
+      && arg == A_H)
+    {
+      if (regno == 11)
+	as_bad (_("'SPU_RdEventMask' (channel 11) is only available in DD2.0 or higher."));
+      else if (regno == 12)
+	as_bad (_("'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher."));
+    }
+
+  if (regno < 128)
+    {
+      insn->opcode |= regno << arg_encode[arg].pos;
+      if ((!saw_prefix && syntax_reg == 1)
+	  || (saw_prefix && syntax_reg == 2))
+	syntax_reg |= 4;
+      syntax_reg |= saw_prefix ? 1 : 2;
+      return param;
+    }
+
+  if (accept_expr)
+    {
+      char *save_ptr;
+      expressionS ex;
+      save_ptr = input_line_pointer;
+      input_line_pointer = (char *)param;
+      expression (&ex);
+      param = input_line_pointer;
+      input_line_pointer = save_ptr;
+      if (ex.X_op == O_register || ex.X_op == O_constant)
+	{
+	  insn->opcode |= ex.X_add_number << arg_encode[arg].pos;
+	  return param;
+	}
+    }
+  return 0;
+}
+
+static const char *
+get_imm (const char *param, struct spu_insn *insn, int arg)
+{
+  int val;
+  char *save_ptr;
+  int low = 0, high = 0;
+  int reloc_i = insn->reloc_arg[0] >= 0 ? 1 : 0;
+
+  if (strncasecmp (param, "%lo(", 4) == 0)
+    {
+      param += 3;
+      low = 1;
+      as_warn (_("Using old style, %%lo(expr), please change to PPC style, expr@l."));
+    }
+  else if (strncasecmp (param, "%hi(", 4) == 0)
+    {
+      param += 3;
+      high = 1;
+      as_warn (_("Using old style, %%hi(expr), please change to PPC style, expr@h."));
+    }
+  else if (strncasecmp (param, "%pic(", 5) == 0)
+    {
+      /* Currently we expect %pic(expr) == expr, so do nothing here.
+	 i.e. for code loaded at address 0 $toc will be 0.  */
+      param += 4;
+    }
+      
+  if (*param == '$')
+    {
+      /* Symbols can start with $, but if this symbol matches a register
+	 name, it's probably a mistake.  The only way to avoid this
+	 warning is to rename the symbol.  */
+      struct spu_insn tmp_insn;
+      const char *np = get_reg (param, &tmp_insn, arg, 0);
+
+      if (np)
+	syntax_error_param = np;
+    }
+      
+  save_ptr = input_line_pointer;
+  input_line_pointer = (char *) param;
+  expression (&insn->exp[reloc_i]);
+  param = input_line_pointer;
+  input_line_pointer = save_ptr;
+
+  /* Similar to ppc_elf_suffix in tc-ppc.c.  We have so few cases to
+     handle we do it inlined here. */
+  if (param[0] == '@' && !ISALNUM (param[2]) && param[2] != '@')
+    {
+      if (param[1] == 'h' || param[1] == 'H')
+	{
+	  high = 1;
+	  param += 2;
+	}
+      else if (param[1] == 'l' || param[1] == 'L')
+	{
+	  low = 1;
+	  param += 2;
+	}
+    }
+
+  if (insn->exp[reloc_i].X_op == O_constant)
+    {
+      val = insn->exp[reloc_i].X_add_number;
+
+      if (emulate_apuasm)
+	{
+	  /* Convert the value to a format we expect. */ 
+          val <<= arg_encode[arg].rshift;
+	  if (arg == A_U7A)
+	    val = 173 - val;
+	  else if (arg == A_U7B)
+	    val = 155 - val; 
+	}
+
+      if (high)
+	val = val >> 16;
+      else if (low)
+	val = val & 0xffff;
+
+      /* Warn about out of range expressions. */
+      {
+	int hi = arg_encode[arg].hi;
+	int lo = arg_encode[arg].lo;
+	int whi = arg_encode[arg].whi;
+	int wlo = arg_encode[arg].wlo;
+
+	if (hi > lo && (val < lo || val > hi))
+	  as_fatal (_("Constant expression %d out of range, [%d, %d]."),
+		    val, lo, hi);
+	else if (whi > wlo && (val < wlo || val > whi))
+	  as_warn (_("Constant expression %d out of range, [%d, %d]."),
+		   val, wlo, whi);
+      }
+
+      if (arg == A_U7A)
+        val = 173 - val;
+      else if (arg == A_U7B)
+        val = 155 - val; 
+
+      /* Branch hints have a split encoding.  Do the bottom part. */
+      if (arg == A_S11 || arg == A_S11I)
+	insn->opcode |= ((val >> 2) & 0x7f);
+
+      insn->opcode |= (((val >> arg_encode[arg].rshift)
+			& ((1 << arg_encode[arg].size) - 1))
+		       << arg_encode[arg].pos);
+      insn->reloc_arg[reloc_i] = -1;
+      insn->flag[reloc_i] = 0;
+    }
+  else
+    {
+      insn->reloc_arg[reloc_i] = arg;
+      if (high)
+	insn->flag[reloc_i] = 1;
+      else if (low)
+	insn->flag[reloc_i] = 2;
+    }
+
+  return param;
+}
+
+#define MAX_LITTLENUMS 6
+
+/* Turn a string in input_line_pointer into a floating point constant of type
+   type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
+   emitted is stored in *sizeP .  An error message is returned, or NULL on OK.
+ */
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  LITTLENUM_TYPE *wordP;
+  char *t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+    case 'x':
+    case 'X':
+      prec = 6;
+      break;
+
+    case 'p':
+    case 'P':
+      prec = 6;
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("Bad call to MD_ATOF()");
+    }
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * sizeof (LITTLENUM_TYPE);
+  for (wordP = words; prec--;)
+    {
+      md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+  return 0;
+}
+
+#ifndef WORKING_DOT_WORD
+int md_short_jump_size = 4;
+
+void
+md_create_short_jump (char *ptr,
+		      addressT from_addr ATTRIBUTE_UNUSED,
+		      addressT to_addr ATTRIBUTE_UNUSED,
+		      fragS *frag,
+		      symbolS *to_symbol)
+{
+  ptr[0] = (char) 0xc0;
+  ptr[1] = 0x00;
+  ptr[2] = 0x00;
+  ptr[3] = 0x00;
+  fix_new (frag,
+	   ptr - frag->fr_literal,
+	   4,
+	   to_symbol,
+	   (offsetT) 0,
+	   0,
+	   BFD_RELOC_SPU_PCREL16);
+}
+
+int md_long_jump_size = 4;
+
+void
+md_create_long_jump (char *ptr,
+		     addressT from_addr ATTRIBUTE_UNUSED,
+		     addressT to_addr ATTRIBUTE_UNUSED,
+		     fragS *frag,
+		     symbolS *to_symbol)
+{
+  ptr[0] = (char) 0xc0;
+  ptr[1] = 0x00;
+  ptr[2] = 0x00;
+  ptr[3] = 0x00;
+  fix_new (frag,
+	   ptr - frag->fr_literal,
+	   4,
+	   to_symbol,
+	   (offsetT) 0,
+	   0,
+	   BFD_RELOC_SPU_PCREL16);
+}
+#endif
+
+/* Support @ppu on symbols referenced in .int/.long/.word/.quad.  */
+static void
+spu_cons (int nbytes)
+{
+  expressionS exp;
+
+  if (is_it_end_of_statement ())
+    {
+      demand_empty_rest_of_line ();
+      return;
+    }
+
+  do
+    {
+      deferred_expression (&exp);
+      if ((exp.X_op == O_symbol
+	   || exp.X_op == O_constant)
+	  && strncasecmp (input_line_pointer, "@ppu", 4) == 0)
+	{
+	  char *p = frag_more (nbytes);
+	  enum bfd_reloc_code_real reloc;
+
+	  /* Check for identifier@suffix+constant.  */
+	  input_line_pointer += 4;
+	  if (*input_line_pointer == '-' || *input_line_pointer == '+')
+	    {
+	      expressionS new_exp;
+
+	      expression (&new_exp);
+	      if (new_exp.X_op == O_constant)
+		exp.X_add_number += new_exp.X_add_number;
+	    }
+
+	  reloc = nbytes == 4 ? BFD_RELOC_SPU_PPU32 : BFD_RELOC_SPU_PPU64;
+	  fix_new_exp (frag_now, p - frag_now->fr_literal, nbytes,
+		       &exp, 0, reloc);
+	}
+      else
+	emit_expr (&exp, nbytes);
+    }
+  while (*input_line_pointer++ == ',');
+
+  /* Put terminator back into stream.  */
+  input_line_pointer--;
+  demand_empty_rest_of_line ();
+}
+
+int
+md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
+			       segT segment_type ATTRIBUTE_UNUSED)
+{
+  as_fatal (_("Relaxation should never occur"));
+  return -1;
+}
+
+/* If while processing a fixup, a reloc really needs to be created,
+   then it is done here.  */
+
+arelent *
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
+{
+  arelent *reloc;
+  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  if (fixp->fx_addsy)
+    *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  else if (fixp->fx_subsy)
+    *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
+  else
+    abort ();
+  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+  if (reloc->howto == (reloc_howto_type *) NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    _("reloc %d not supported by object file format"),
+		    (int) fixp->fx_r_type);
+      return NULL;
+    }
+  reloc->addend = fixp->fx_addnumber;
+  return reloc;
+}
+
+/* Round up a section's size to the appropriate boundary.  */
+
+valueT
+md_section_align (segT seg, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, seg);
+  valueT mask = ((valueT) 1 << align) - 1;
+
+  return (size + mask) & ~mask;
+}
+
+/* Where a PC relative offset is calculated from.  On the spu they
+   are calculated from the beginning of the branch instruction.  */
+
+long
+md_pcrel_from (fixS *fixp)
+{
+  return fixp->fx_frag->fr_address + fixp->fx_where;
+}
+
+/* Fill in rs_align_code fragments.  */
+
+void
+spu_handle_align (fragS *fragp)
+{
+  static const unsigned char nop_pattern[8] = {
+    0x40, 0x20, 0x00, 0x00, /* even nop */
+    0x00, 0x20, 0x00, 0x00, /* odd  nop */
+  };
+
+  int bytes;
+  char *p;
+
+  if (fragp->fr_type != rs_align_code)
+    return;
+
+  bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
+  p = fragp->fr_literal + fragp->fr_fix;
+
+  if (bytes & 3)
+    {
+      int fix = bytes & 3;
+      memset (p, 0, fix);
+      p += fix;
+      bytes -= fix;
+      fragp->fr_fix += fix;
+    }
+  if (bytes & 4)
+    {
+      memcpy (p, &nop_pattern[4], 4);
+      p += 4;
+      bytes -= 4;
+      fragp->fr_fix += 4;
+    }
+
+  memcpy (p, nop_pattern, 8);
+  fragp->fr_var = 8;
+}
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+{
+  unsigned int res;
+  valueT val = *valP;
+  char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
+
+  if (fixP->fx_subsy != (symbolS *) NULL)
+    {
+      /* We can't actually support subtracting a symbol.  */
+      as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
+    }
+
+  if (fixP->fx_addsy != NULL)
+    {
+      if (fixP->fx_pcrel)
+	{
+	  /* Hack around bfd_install_relocation brain damage.  */
+	  val += fixP->fx_frag->fr_address + fixP->fx_where;
+
+	  switch (fixP->fx_r_type)
+	    {
+	    case BFD_RELOC_32:
+	      fixP->fx_r_type = BFD_RELOC_32_PCREL;
+	      break;
+
+	    case BFD_RELOC_SPU_PCREL16:
+	    case BFD_RELOC_SPU_PCREL9a:
+	    case BFD_RELOC_SPU_PCREL9b:
+	    case BFD_RELOC_32_PCREL:
+	      break;
+
+	    default:
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("expression too complex"));
+	      break;
+	    }
+	}
+    }
+
+  fixP->fx_addnumber = val;
+
+  if (fixP->fx_r_type == BFD_RELOC_SPU_PPU32
+      || fixP->fx_r_type == BFD_RELOC_SPU_PPU64)
+    return;
+
+  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
+    {
+      fixP->fx_done = 1;
+      res = 0;
+      if (fixP->tc_fix_data.arg_format > A_P)
+	{
+	  int hi = arg_encode[fixP->tc_fix_data.arg_format].hi;
+	  int lo = arg_encode[fixP->tc_fix_data.arg_format].lo;
+	  if (hi > lo && ((offsetT) val < lo || (offsetT) val > hi))
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  "Relocation doesn't fit. (relocation value = 0x%lx)",
+			  (long) val);
+	}
+
+      switch (fixP->fx_r_type)
+        {
+        case BFD_RELOC_8:
+	  md_number_to_chars (place, val, 1);
+	  return;
+
+        case BFD_RELOC_16:
+	  md_number_to_chars (place, val, 2);
+	  return;
+
+        case BFD_RELOC_32:
+	  md_number_to_chars (place, val, 4);
+	  return;
+
+        case BFD_RELOC_64:
+	  md_number_to_chars (place, val, 8);
+	  return;
+
+        case BFD_RELOC_SPU_IMM7:
+          res = (val & 0x7f) << 14;
+          break;
+
+        case BFD_RELOC_SPU_IMM8:
+          res = (val & 0xff) << 14;
+          break;
+
+        case BFD_RELOC_SPU_IMM10:
+          res = (val & 0x3ff) << 14;
+          break;
+
+        case BFD_RELOC_SPU_IMM10W:
+          res = (val & 0x3ff0) << 10;
+          break;
+
+        case BFD_RELOC_SPU_IMM16:
+          res = (val & 0xffff) << 7;
+          break;
+
+        case BFD_RELOC_SPU_IMM16W:
+          res = (val & 0x3fffc) << 5;
+          break;
+
+        case BFD_RELOC_SPU_IMM18:
+          res = (val & 0x3ffff) << 7;
+          break;
+
+        case BFD_RELOC_SPU_PCREL9a:
+          res = ((val & 0x1fc) >> 2) | ((val & 0x600) << 14);
+          break;
+
+        case BFD_RELOC_SPU_PCREL9b:
+          res = ((val & 0x1fc) >> 2) | ((val & 0x600) << 5);
+          break;
+
+        case BFD_RELOC_SPU_PCREL16:
+          res = (val & 0x3fffc) << 5;
+          break;
+
+        default:
+          as_bad_where (fixP->fx_file, fixP->fx_line,
+                        _("reloc %d not supported by object file format"),
+                        (int) fixP->fx_r_type);
+        }
+
+      if (res != 0)
+        {
+          place[0] |= (res >> 24) & 0xff;
+          place[1] |= (res >> 16) & 0xff;
+          place[2] |= (res >> 8) & 0xff;
+          place[3] |= (res) & 0xff;
+        }
+    }
+}
diff --git a/contrib/binutils/gas/config/tc-spu.h b/contrib/binutils/gas/config/tc-spu.h
new file mode 100644
index 0000000..4c6c2d4
--- /dev/null
+++ b/contrib/binutils/gas/config/tc-spu.h
@@ -0,0 +1,107 @@
+/* spu.h -- Assembler for spu
+
+   Copyright 2006, 2007 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef TC_SPU
+#define TC_SPU 1
+
+#include "opcode/spu.h"
+
+#define TARGET_FORMAT "elf32-spu"
+#define TARGET_ARCH bfd_arch_spu
+#define TARGET_NAME "elf32-spu"
+
+#define TARGET_BYTES_BIG_ENDIAN 1
+
+struct tc_fix_info {
+  unsigned short arg_format;
+  unsigned short insn_tag;
+};
+
+/* fixS will have a member named tc_fix_data of this type.  */
+#define TC_FIX_TYPE struct tc_fix_info
+#define TC_INIT_FIX_DATA(FIXP) \
+  do						\
+    {						\
+      (FIXP)->tc_fix_data.arg_format = 0;	\
+      (FIXP)->tc_fix_data.insn_tag = 0;		\
+    }						\
+  while (0)
+
+/* Don't reduce function symbols to section symbols, and don't adjust
+   references to PPU symbols.  */
+#define tc_fix_adjustable(FIXP) \
+  (!(S_IS_FUNCTION ((FIXP)->fx_addsy)			\
+     || (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU32	\
+     || (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU64))
+
+/* Keep relocs on calls.  Branches to function symbols are tail or
+   sibling calls.  */
+#define TC_FORCE_RELOCATION(FIXP) \
+  ((FIXP)->tc_fix_data.insn_tag == M_BRSL		\
+   || (FIXP)->tc_fix_data.insn_tag == M_BRASL		\
+   || (((FIXP)->tc_fix_data.insn_tag == M_BR		\
+	|| (FIXP)->tc_fix_data.insn_tag == M_BRA)	\
+       && (FIXP)->fx_addsy != NULL			\
+       && S_IS_FUNCTION ((FIXP)->fx_addsy))		\
+   || (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU32		\
+   || (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU64		\
+   || generic_force_reloc (FIXP))
+
+/* Values passed to md_apply_fix don't include symbol values.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+/* The spu uses pseudo-ops with no leading period.  */
+#define NO_PSEUDO_DOT 1
+
+/* Don't warn on word overflow; it happens on %hi relocs.  */
+#undef WARN_SIGNED_OVERFLOW_WORD
+
+#define DIFF_EXPR_OK
+
+#define WORKING_DOT_WORD
+
+#define md_number_to_chars number_to_chars_bigendian
+
+#define md_convert_frag(b,s,f)		{as_fatal (_("spu convert_frag\n"));}
+
+/* We don't need to do anything special for undefined symbols.  */
+#define md_undefined_symbol(s) 0
+
+extern symbolS *section_symbol (asection *);
+#define md_operand(e) \
+  do {								\
+    if (strncasecmp (input_line_pointer, "@ppu", 4) == 0)	\
+      {								\
+	e->X_op = O_symbol;					\
+	if (abs_section_sym == NULL)				\
+	  abs_section_sym = section_symbol (absolute_section);	\
+	e->X_add_symbol = abs_section_sym;			\
+	e->X_add_number = 0;					\
+      }								\
+  } while (0)
+
+/* Fill in rs_align_code fragments.  */
+extern void spu_handle_align PARAMS ((fragS *));
+#define HANDLE_ALIGN(frag)  spu_handle_align (frag)
+
+#define MAX_MEM_FOR_RS_ALIGN_CODE  (7 + 8)
+
+#endif /* TC_SPU */
diff --git a/contrib/binutils/gas/config/te-pep.h b/contrib/binutils/gas/config/te-pep.h
new file mode 100644
index 0000000..164b22d
--- /dev/null
+++ b/contrib/binutils/gas/config/te-pep.h
@@ -0,0 +1,10 @@
+#define TE_PEP
+#define COFF_WITH_pex64
+
+#define TE_PE
+#define LEX_AT (LEX_BEGIN_NAME | LEX_NAME) /* Can have @'s inside labels.  */
+
+/* The PE format supports long section names.  */
+#define COFF_LONG_SECTION_NAMES
+
+#include "obj-format.h"
diff --git a/contrib/binutils/gas/configure b/contrib/binutils/gas/configure
index dca6497..d2cc2e7 100755
--- a/contrib/binutils/gas/configure
+++ b/contrib/binutils/gas/configure
@@ -241,6 +241,155 @@ IFS=" 	$as_nl"
 $as_unset CDPATH
 
 
+
+# Check that we are running under the correct shell.
+SHELL=${CONFIG_SHELL-/bin/sh}
+
+case X$lt_ECHO in
+X*--fallback-echo)
+  # Remove one level of quotation (which was required for Make).
+  ECHO=`echo "$lt_ECHO" | sed 's,\\\\\$\\$0,'$0','`
+  ;;
+esac
+
+ECHO=${lt_ECHO-echo}
+if test "X$1" = X--no-reexec; then
+  # Discard the --no-reexec flag, and continue.
+  shift
+elif test "X$1" = X--fallback-echo; then
+  # Avoid inline document here, it may be left over
+  :
+elif test "X`{ $ECHO '\t'; } 2>/dev/null`" = 'X\t' ; then
+  # Yippee, $ECHO works!
+  :
+else
+  # Restart under the correct shell.
+  exec $SHELL "$0" --no-reexec ${1+"$@"}
+fi
+
+if test "X$1" = X--fallback-echo; then
+  # used as fallback echo
+  shift
+  cat <<_LT_EOF
+$*
+_LT_EOF
+  exit 0
+fi
+
+# The HP-UX ksh and POSIX shell print the target directory to stdout
+# if CDPATH is set.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+if test -z "$lt_ECHO"; then
+  if test "X${echo_test_string+set}" != Xset; then
+    # find a string as large as possible, as long as the shell can cope with it
+    for cmd in 'sed 50q "$0"' 'sed 20q "$0"' 'sed 10q "$0"' 'sed 2q "$0"' 'echo test'; do
+      # expected sizes: less than 2Kb, 1Kb, 512 bytes, 16 bytes, ...
+      if { echo_test_string=`eval $cmd`; } 2>/dev/null &&
+	 { test "X$echo_test_string" = "X$echo_test_string"; } 2>/dev/null
+      then
+        break
+      fi
+    done
+  fi
+
+  if test "X`{ $ECHO '\t'; } 2>/dev/null`" = 'X\t' &&
+     echo_testing_string=`{ $ECHO "$echo_test_string"; } 2>/dev/null` &&
+     test "X$echo_testing_string" = "X$echo_test_string"; then
+    :
+  else
+    # The Solaris, AIX, and Digital Unix default echo programs unquote
+    # backslashes.  This makes it impossible to quote backslashes using
+    #   echo "$something" | sed 's/\\/\\\\/g'
+    #
+    # So, first we look for a working echo in the user's PATH.
+
+    lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+    for dir in $PATH /usr/ucb; do
+      IFS="$lt_save_ifs"
+      if (test -f $dir/echo || test -f $dir/echo$ac_exeext) &&
+         test "X`($dir/echo '\t') 2>/dev/null`" = 'X\t' &&
+         echo_testing_string=`($dir/echo "$echo_test_string") 2>/dev/null` &&
+         test "X$echo_testing_string" = "X$echo_test_string"; then
+        ECHO="$dir/echo"
+        break
+      fi
+    done
+    IFS="$lt_save_ifs"
+
+    if test "X$ECHO" = Xecho; then
+      # We didn't find a better echo, so look for alternatives.
+      if test "X`{ print -r '\t'; } 2>/dev/null`" = 'X\t' &&
+         echo_testing_string=`{ print -r "$echo_test_string"; } 2>/dev/null` &&
+         test "X$echo_testing_string" = "X$echo_test_string"; then
+        # This shell has a builtin print -r that does the trick.
+        ECHO='print -r'
+      elif { test -f /bin/ksh || test -f /bin/ksh$ac_exeext; } &&
+	   test "X$CONFIG_SHELL" != X/bin/ksh; then
+        # If we have ksh, try running configure again with it.
+        ORIGINAL_CONFIG_SHELL=${CONFIG_SHELL-/bin/sh}
+        export ORIGINAL_CONFIG_SHELL
+        CONFIG_SHELL=/bin/ksh
+        export CONFIG_SHELL
+        exec $CONFIG_SHELL "$0" --no-reexec ${1+"$@"}
+      else
+        # Try using printf.
+        ECHO='printf %s\n'
+        if test "X`{ $ECHO '\t'; } 2>/dev/null`" = 'X\t' &&
+	   echo_testing_string=`{ $ECHO "$echo_test_string"; } 2>/dev/null` &&
+	   test "X$echo_testing_string" = "X$echo_test_string"; then
+	  # Cool, printf works
+	  :
+        elif echo_testing_string=`($ORIGINAL_CONFIG_SHELL "$0" --fallback-echo '\t') 2>/dev/null` &&
+	     test "X$echo_testing_string" = 'X\t' &&
+	     echo_testing_string=`($ORIGINAL_CONFIG_SHELL "$0" --fallback-echo "$echo_test_string") 2>/dev/null` &&
+	     test "X$echo_testing_string" = "X$echo_test_string"; then
+	  CONFIG_SHELL=$ORIGINAL_CONFIG_SHELL
+	  export CONFIG_SHELL
+	  SHELL="$CONFIG_SHELL"
+	  export SHELL
+	  ECHO="$CONFIG_SHELL $0 --fallback-echo"
+        elif echo_testing_string=`($CONFIG_SHELL "$0" --fallback-echo '\t') 2>/dev/null` &&
+	     test "X$echo_testing_string" = 'X\t' &&
+	     echo_testing_string=`($CONFIG_SHELL "$0" --fallback-echo "$echo_test_string") 2>/dev/null` &&
+	     test "X$echo_testing_string" = "X$echo_test_string"; then
+	  ECHO="$CONFIG_SHELL $0 --fallback-echo"
+        else
+	  # maybe with a smaller string...
+	  prev=:
+
+	  for cmd in 'echo test' 'sed 2q "$0"' 'sed 10q "$0"' 'sed 20q "$0"' 'sed 50q "$0"'; do
+	    if { test "X$echo_test_string" = "X`eval $cmd`"; } 2>/dev/null
+	    then
+	      break
+	    fi
+	    prev="$cmd"
+	  done
+
+	  if test "$prev" != 'sed 50q "$0"'; then
+	    echo_test_string=`eval $prev`
+	    export echo_test_string
+	    exec ${ORIGINAL_CONFIG_SHELL-${CONFIG_SHELL-/bin/sh}} "$0" ${1+"$@"}
+	  else
+	    # Oops.  We lost completely, so just stick with echo.
+	    ECHO=echo
+	  fi
+        fi
+      fi
+    fi
+  fi
+fi
+
+# Copy echo and quote the copy suitably for passing to libtool from
+# the Makefile, instead of quoting the original, which is used later.
+lt_ECHO=$ECHO
+if test "X$lt_ECHO" = "X$CONFIG_SHELL $0 --fallback-echo"; then
+   lt_ECHO="$CONFIG_SHELL \\\$\$0 --fallback-echo"
+fi
+
+
+
+
 # Name of the host.
 # hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
 # so uname gets run too.
@@ -309,7 +458,7 @@ ac_includes_default="\
 # include <unistd.h>
 #endif"
 
-ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE LN_S RANLIB ac_ct_RANLIB LIBTOOL WARN_CFLAGS NO_WERROR GDBINIT cgen_cpu_prefix extra_objects target_cpu_type obj_format te_file install_tooldir atof BFDLIB OPCODES_LIB BFDVER_H ALL_OBJ_DEPS YACC LEX LEXLIB LEX_OUTPUT_ROOT CPP EGREP ALLOCA USE_NLS MSGFMT GMSGFMT XGETTEXT USE_INCLUDED_LIBINTL CATALOGS CATOBJEXT DATADIRNAME GMOFILES INSTOBJEXT INTLDEPS INTLLIBS INTLOBJS POFILES POSUB INCLUDE_LOCALE_H GT_NO GT_YES MKINSTALLDIRS l MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT LIBM datarootdir docdir htmldir LIBOBJS LTLIBOBJS'
+ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE LIBTOOL SED EGREP FGREP GREP LD DUMPBIN ac_ct_DUMPBIN NM LN_S AR ac_ct_AR RANLIB ac_ct_RANLIB lt_ECHO CPP WARN_CFLAGS NO_WERROR GDBINIT cgen_cpu_prefix extra_objects target_cpu_type obj_format te_file install_tooldir atof OPCODES_LIB YACC LEX LEXLIB LEX_OUTPUT_ROOT USE_NLS LIBINTL LIBINTL_DEP INCINTL XGETTEXT GMSGFMT POSUB CATALOGS DATADIRNAME INSTOBJEXT GENCAT CATOBJEXT MKINSTALLDIRS MSGFMT MSGMERGE MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT GENINSRC_NEVER_TRUE GENINSRC_NEVER_FALSE ALLOCA LIBM datarootdir docdir htmldir LIBOBJS LTLIBOBJS'
 ac_subst_files=''
 
 # Initialize some variables set by options.
@@ -852,14 +1001,18 @@ Optional Features:
   --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
   --disable-dependency-tracking  speeds up one-time build
   --enable-dependency-tracking   do not reject slow dependency extractors
-  --enable-shared=PKGS  build shared libraries default=yes
-  --enable-static=PKGS  build static libraries default=yes
-  --enable-fast-install=PKGS  optimize for fast installation default=yes
+  --enable-shared[=PKGS]
+                          build shared libraries [default=yes]
+  --enable-static[=PKGS]
+                          build static libraries [default=yes]
+  --enable-fast-install[=PKGS]
+                          optimize for fast installation [default=yes]
   --disable-libtool-lock  avoid locking (might break parallel builds)
-   --enable-targets       alternative target configurations besides the primary
+  --enable-targets        alternative target configurations besides the primary
   --enable-commonbfdlib   build shared BFD/opcodes/libiberty library
-  --enable-werror    treat compile warnings as errors
-  --enable-build-warnings Enable build-time compiler warnings
+  --enable-checking       enable run-time checks
+  --enable-werror         treat compile warnings as errors
+  --enable-build-warnings enable build-time compiler warnings
   --disable-nls           do not use Native Language Support
   --enable-maintainer-mode  enable make rules and dependencies not useful
 			  (and sometimes confusing) to the casual installer
@@ -867,9 +1020,9 @@ Optional Features:
 Optional Packages:
   --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
   --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
-  --with-gnu-ld           assume the C compiler uses GNU ld default=no
-  --with-pic              try to use only PIC/non-PIC objects default=use both
-  --with-included-gettext use the GNU gettext library included here
+  --with-pic              try to use only PIC/non-PIC objects [default=use
+                          both]
+  --with-gnu-ld           assume the C compiler uses GNU ld [default=no]
 
 Some influential environment variables:
   CC          C compiler command
@@ -3072,73 +3225,264 @@ fi
 
 
 
+
+
+macro_version='2.1a'
+macro_revision='1.2435'
+
+
+
+
+
+
+
+
+
+
+
+
+ltmain="$ac_aux_dir/ltmain.sh"
+
+# Set options
+
+enable_dlopen=no
+
+
+enable_win32_dll=no
+
+
 # Check whether --enable-shared or --disable-shared was given.
 if test "${enable_shared+set}" = set; then
   enableval="$enable_shared"
   p=${PACKAGE-default}
-case $enableval in
-yes) enable_shared=yes ;;
-no) enable_shared=no ;;
-*)
-  enable_shared=no
-  # Look at the argument we got.  We use all the common list separators.
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
-  for pkg in $enableval; do
-    if test "X$pkg" = "X$p"; then
-      enable_shared=yes
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
+    case $enableval in
+    yes) enable_shared=yes ;;
+    no) enable_shared=no ;;
+    *)
+      enable_shared=no
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for pkg in $enableval; do
+	IFS="$lt_save_ifs"
+	if test "X$pkg" = "X$p"; then
+	  enable_shared=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac
 else
   enable_shared=yes
 fi;
+
+
+
+
+
+
+
+
 # Check whether --enable-static or --disable-static was given.
 if test "${enable_static+set}" = set; then
   enableval="$enable_static"
   p=${PACKAGE-default}
-case $enableval in
-yes) enable_static=yes ;;
-no) enable_static=no ;;
-*)
-  enable_static=no
-  # Look at the argument we got.  We use all the common list separators.
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
-  for pkg in $enableval; do
-    if test "X$pkg" = "X$p"; then
-      enable_static=yes
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
+    case $enableval in
+    yes) enable_static=yes ;;
+    no) enable_static=no ;;
+    *)
+     enable_static=no
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for pkg in $enableval; do
+	IFS="$lt_save_ifs"
+	if test "X$pkg" = "X$p"; then
+	  enable_static=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac
 else
   enable_static=yes
 fi;
+
+
+
+
+
+
+
+
+
+# Check whether --with-pic or --without-pic was given.
+if test "${with_pic+set}" = set; then
+  withval="$with_pic"
+  pic_mode="$withval"
+else
+  pic_mode=default
+fi;
+
+test -z "$pic_mode" && pic_mode=default
+
+
+
+
+
+
+
 # Check whether --enable-fast-install or --disable-fast-install was given.
 if test "${enable_fast_install+set}" = set; then
   enableval="$enable_fast_install"
   p=${PACKAGE-default}
-case $enableval in
-yes) enable_fast_install=yes ;;
-no) enable_fast_install=no ;;
-*)
-  enable_fast_install=no
-  # Look at the argument we got.  We use all the common list separators.
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
-  for pkg in $enableval; do
-    if test "X$pkg" = "X$p"; then
-      enable_fast_install=yes
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
+    case $enableval in
+    yes) enable_fast_install=yes ;;
+    no) enable_fast_install=no ;;
+    *)
+      enable_fast_install=no
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for pkg in $enableval; do
+	IFS="$lt_save_ifs"
+	if test "X$pkg" = "X$p"; then
+	  enable_fast_install=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac
 else
   enable_fast_install=yes
 fi;
 
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking for a sed that does not truncate output" >&5
+echo $ECHO_N "checking for a sed that does not truncate output... $ECHO_C" >&6
+if test "${lt_cv_path_SED+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  # Loop through the user's path and test for sed and gsed.
+# Then use that list of sed's as ones to test for truncation.
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for lt_ac_prog in sed gsed; do
+    for ac_exec_ext in '' $ac_executable_extensions; do
+      if $as_executable_p "$as_dir/$lt_ac_prog$ac_exec_ext"; then
+        lt_ac_sed_list="$lt_ac_sed_list $as_dir/$lt_ac_prog$ac_exec_ext"
+      fi
+    done
+  done
+done
+IFS=$as_save_IFS
+lt_ac_max=0
+lt_ac_count=0
+# Add /usr/xpg4/bin/sed as it is typically found on Solaris
+# along with /bin/sed that truncates output.
+for lt_ac_sed in $lt_ac_sed_list /usr/xpg4/bin/sed; do
+  test ! -f $lt_ac_sed && continue
+  cat /dev/null > conftest.in
+  lt_ac_count=0
+  echo $ECHO_N "0123456789$ECHO_C" >conftest.in
+  # Check for GNU sed and select it if it is found.
+  if "$lt_ac_sed" --version 2>&1 < /dev/null | grep 'GNU' > /dev/null; then
+    lt_cv_path_SED=$lt_ac_sed
+    break
+  fi
+  while true; do
+    cat conftest.in conftest.in >conftest.tmp
+    mv conftest.tmp conftest.in
+    cp conftest.in conftest.nl
+    echo >>conftest.nl
+    $lt_ac_sed -e 's/a$//' < conftest.nl >conftest.out || break
+    cmp -s conftest.out conftest.nl || break
+    # 10000 chars as input seems more than enough
+    test $lt_ac_count -gt 10 && break
+    lt_ac_count=`expr $lt_ac_count + 1`
+    if test $lt_ac_count -gt $lt_ac_max; then
+      lt_ac_max=$lt_ac_count
+      lt_cv_path_SED=$lt_ac_sed
+    fi
+  done
+done
+
+fi
+
+SED=$lt_cv_path_SED
+
+echo "$as_me:$LINENO: result: $SED" >&5
+echo "${ECHO_T}$SED" >&6
+
+test -z "$SED" && SED=sed
+Xsed="$SED -e 1s/^X//"
+
+
+
+
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking for egrep" >&5
+echo $ECHO_N "checking for egrep... $ECHO_C" >&6
+if test "${ac_cv_prog_egrep+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if echo a | (grep -E '(a|b)') >/dev/null 2>&1
+    then ac_cv_prog_egrep='grep -E'
+    else ac_cv_prog_egrep='egrep'
+    fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5
+echo "${ECHO_T}$ac_cv_prog_egrep" >&6
+ EGREP=$ac_cv_prog_egrep
+
+
+echo "$as_me:$LINENO: checking for fgrep" >&5
+echo $ECHO_N "checking for fgrep... $ECHO_C" >&6
+if test "${ac_cv_prog_fgrep+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if echo 'ab*c' | (grep -F 'ab*c') >/dev/null 2>&1
+    then ac_cv_prog_fgrep='grep -F'
+    else ac_cv_prog_fgrep='fgrep'
+    fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_prog_fgrep" >&5
+echo "${ECHO_T}$ac_cv_prog_fgrep" >&6
+ FGREP=$ac_cv_prog_fgrep
+
+
+test -z "$GREP" && GREP=grep
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 # Check whether --with-gnu-ld or --without-gnu-ld was given.
 if test "${with_gnu_ld+set}" = set; then
   withval="$with_gnu_ld"
@@ -3149,8 +3493,8 @@ fi;
 ac_prog=ld
 if test "$GCC" = yes; then
   # Check if gcc -print-prog-name=ld gives a path.
-  echo "$as_me:$LINENO: checking for ld used by GCC" >&5
-echo $ECHO_N "checking for ld used by GCC... $ECHO_C" >&6
+  echo "$as_me:$LINENO: checking for ld used by $CC" >&5
+echo $ECHO_N "checking for ld used by $CC... $ECHO_C" >&6
   case $host in
   *-*-mingw*)
     # gcc leaves a trailing carriage return which upsets mingw
@@ -3160,12 +3504,12 @@ echo $ECHO_N "checking for ld used by GCC... $ECHO_C" >&6
   esac
   case $ac_prog in
     # Accept absolute paths.
-    [\\/]* | [A-Za-z]:[\\/]*)
+    [\\/]* | ?:[\\/]*)
       re_direlt='/[^/][^/]*/\.\./'
-      # Canonicalize the path of ld
-      ac_prog=`echo $ac_prog| sed 's%\\\\%/%g'`
-      while echo $ac_prog | grep "$re_direlt" > /dev/null 2>&1; do
-	ac_prog=`echo $ac_prog| sed "s%$re_direlt%/%"`
+      # Canonicalize the pathname of ld
+      ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'`
+      while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do
+	ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"`
       done
       test -z "$LD" && LD="$ac_prog"
       ;;
@@ -3189,22 +3533,26 @@ if test "${lt_cv_path_LD+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   if test -z "$LD"; then
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}"
+  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
   for ac_dir in $PATH; do
+    IFS="$lt_save_ifs"
     test -z "$ac_dir" && ac_dir=.
     if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then
       lt_cv_path_LD="$ac_dir/$ac_prog"
       # Check to see if the program is GNU ld.  I'd rather use --version,
-      # but apparently some GNU ld's only accept -v.
+      # but apparently some variants of GNU ld only accept -v.
       # Break only if it was the GNU/non-GNU ld that we prefer.
-      if "$lt_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then
+      case `"$lt_cv_path_LD" -v 2>&1 </dev/null` in
+      *GNU* | *'with BFD'*)
 	test "$with_gnu_ld" != no && break
-      else
+	;;
+      *)
 	test "$with_gnu_ld" != yes && break
-      fi
+	;;
+      esac
     fi
   done
-  IFS="$ac_save_ifs"
+  IFS="$lt_save_ifs"
 else
   lt_cv_path_LD="$LD" # Let the user override the test with a path.
 fi
@@ -3226,32 +3574,31 @@ echo $ECHO_N "checking if the linker ($LD) is GNU ld... $ECHO_C" >&6
 if test "${lt_cv_prog_gnu_ld+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  # I'd rather use --version here, but apparently some GNU ld's only accept -v.
-if $LD -v 2>&1 </dev/null | egrep '(GNU|with BFD)' 1>&5; then
+  # I'd rather use --version here, but apparently some GNU lds only accept -v.
+case `$LD -v 2>&1 </dev/null` in
+*GNU* | *'with BFD'*)
   lt_cv_prog_gnu_ld=yes
-else
+  ;;
+*)
   lt_cv_prog_gnu_ld=no
-fi
+  ;;
+esac
 fi
 echo "$as_me:$LINENO: result: $lt_cv_prog_gnu_ld" >&5
 echo "${ECHO_T}$lt_cv_prog_gnu_ld" >&6
 with_gnu_ld=$lt_cv_prog_gnu_ld
 
 
-echo "$as_me:$LINENO: checking for $LD option to reload object files" >&5
-echo $ECHO_N "checking for $LD option to reload object files... $ECHO_C" >&6
-if test "${lt_cv_ld_reload_flag+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  lt_cv_ld_reload_flag='-r'
-fi
-echo "$as_me:$LINENO: result: $lt_cv_ld_reload_flag" >&5
-echo "${ECHO_T}$lt_cv_ld_reload_flag" >&6
-reload_flag=$lt_cv_ld_reload_flag
-test -n "$reload_flag" && reload_flag=" $reload_flag"
 
-echo "$as_me:$LINENO: checking for BSD-compatible nm" >&5
-echo $ECHO_N "checking for BSD-compatible nm... $ECHO_C" >&6
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking for BSD- or MS-compatible name lister (nm)" >&5
+echo $ECHO_N "checking for BSD- or MS-compatible name lister (nm)... $ECHO_C" >&6
 if test "${lt_cv_path_NM+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
@@ -3259,35 +3606,173 @@ else
   # Let the user override the test.
   lt_cv_path_NM="$NM"
 else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}"
-  for ac_dir in $PATH /usr/ccs/bin /usr/ucb /bin; do
-    test -z "$ac_dir" && ac_dir=.
-    tmp_nm=$ac_dir/${ac_tool_prefix}nm
-    if test -f $tmp_nm || test -f $tmp_nm$ac_exeext ; then
-      # Check to see if the nm accepts a BSD-compat flag.
-      # Adding the `sed 1q' prevents false positives on HP-UX, which says:
-      #   nm: unknown option "B" ignored
-      # Tru64's nm complains that /dev/null is an invalid object file
-      if ($tmp_nm -B /dev/null 2>&1 | sed '1q'; exit 0) | egrep '(/dev/null|Invalid file or object type)' >/dev/null; then
-	lt_cv_path_NM="$tmp_nm -B"
-	break
-      elif ($tmp_nm -p /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then
-	lt_cv_path_NM="$tmp_nm -p"
-	break
-      else
-	lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but
-	continue # so that we can try to find one that supports BSD flags
+  lt_nm_to_check="${ac_tool_prefix}nm"
+  if test -n "$ac_tool_prefix" && test "$build" = "$host"; then
+    lt_nm_to_check="$lt_nm_to_check nm"
+  fi
+  for lt_tmp_nm in $lt_nm_to_check; do
+    lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+    for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do
+      IFS="$lt_save_ifs"
+      test -z "$ac_dir" && ac_dir=.
+      tmp_nm="$ac_dir/$lt_tmp_nm"
+      if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then
+	# Check to see if the nm accepts a BSD-compat flag.
+	# Adding the `sed 1q' prevents false positives on HP-UX, which says:
+	#   nm: unknown option "B" ignored
+	# Tru64's nm complains that /dev/null is an invalid object file
+	case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in
+	*/dev/null* | *'Invalid file or object type'*)
+	  lt_cv_path_NM="$tmp_nm -B"
+	  break
+	  ;;
+	*)
+	  case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in
+	  */dev/null*)
+	    lt_cv_path_NM="$tmp_nm -p"
+	    break
+	    ;;
+	  *)
+	    lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but
+	    continue # so that we can try to find one that supports BSD flags
+	    ;;
+	  esac
+	  ;;
+	esac
       fi
-    fi
+    done
+    IFS="$lt_save_ifs"
   done
-  IFS="$ac_save_ifs"
-  test -z "$lt_cv_path_NM" && lt_cv_path_NM=nm
+  : ${lt_cv_path_NM=no}
+fi
+fi
+echo "$as_me:$LINENO: result: $lt_cv_path_NM" >&5
+echo "${ECHO_T}$lt_cv_path_NM" >&6
+if test "$lt_cv_path_NM" != "no"; then
+  NM="$lt_cv_path_NM"
+else
+  # Didn't find any BSD compatible name lister, look for dumpbin.
+  if test -n "$ac_tool_prefix"; then
+  for ac_prog in "dumpbin -symbols" "link -dump -symbols"
+  do
+    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
+set dummy $ac_tool_prefix$ac_prog; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_DUMPBIN+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if test -n "$DUMPBIN"; then
+  ac_cv_prog_DUMPBIN="$DUMPBIN" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_DUMPBIN="$ac_tool_prefix$ac_prog"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+
+fi
 fi
+DUMPBIN=$ac_cv_prog_DUMPBIN
+if test -n "$DUMPBIN"; then
+  echo "$as_me:$LINENO: result: $DUMPBIN" >&5
+echo "${ECHO_T}$DUMPBIN" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
 fi
 
-NM="$lt_cv_path_NM"
-echo "$as_me:$LINENO: result: $NM" >&5
-echo "${ECHO_T}$NM" >&6
+    test -n "$DUMPBIN" && break
+  done
+fi
+if test -z "$DUMPBIN"; then
+  ac_ct_DUMPBIN=$DUMPBIN
+  for ac_prog in "dumpbin -symbols" "link -dump -symbols"
+do
+  # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_DUMPBIN+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if test -n "$ac_ct_DUMPBIN"; then
+  ac_cv_prog_ac_ct_DUMPBIN="$ac_ct_DUMPBIN" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_DUMPBIN="$ac_prog"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+
+fi
+fi
+ac_ct_DUMPBIN=$ac_cv_prog_ac_ct_DUMPBIN
+if test -n "$ac_ct_DUMPBIN"; then
+  echo "$as_me:$LINENO: result: $ac_ct_DUMPBIN" >&5
+echo "${ECHO_T}$ac_ct_DUMPBIN" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+  test -n "$ac_ct_DUMPBIN" && break
+done
+test -n "$ac_ct_DUMPBIN" || ac_ct_DUMPBIN=":"
+
+  DUMPBIN=$ac_ct_DUMPBIN
+fi
+
+
+  if test "$DUMPBIN" != ":"; then
+    NM="$DUMPBIN"
+  fi
+fi
+test -z "$NM" && NM=nm
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking the name lister ($NM) interface" >&5
+echo $ECHO_N "checking the name lister ($NM) interface... $ECHO_C" >&6
+if test "${lt_cv_nm_interface+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_nm_interface="BSD nm"
+  echo "int some_variable = 0;" > conftest.$ac_ext
+  (eval echo "\"\$as_me:3761: $ac_compile\"" >&5)
+  (eval "$ac_compile" 2>conftest.err)
+  cat conftest.err >&5
+  (eval echo "\"\$as_me:3764: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
+  (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out)
+  cat conftest.err >&5
+  (eval echo "\"\$as_me:3767: output\"" >&5)
+  cat conftest.out >&5
+  if $GREP 'External.*some_variable' conftest.out > /dev/null; then
+    lt_cv_nm_interface="MS dumpbin"
+  fi
+  rm -f conftest*
+fi
+echo "$as_me:$LINENO: result: $lt_cv_nm_interface" >&5
+echo "${ECHO_T}$lt_cv_nm_interface" >&6
 
 echo "$as_me:$LINENO: checking whether ln -s works" >&5
 echo $ECHO_N "checking whether ln -s works... $ECHO_C" >&6
@@ -3300,8 +3785,234 @@ else
 echo "${ECHO_T}no, using $LN_S" >&6
 fi
 
-echo "$as_me:$LINENO: checking how to recognise dependant libraries" >&5
-echo $ECHO_N "checking how to recognise dependant libraries... $ECHO_C" >&6
+# find the maximum length of command line arguments
+echo "$as_me:$LINENO: checking the maximum length of command line arguments" >&5
+echo $ECHO_N "checking the maximum length of command line arguments... $ECHO_C" >&6
+if test "${lt_cv_sys_max_cmd_len+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+    i=0
+  teststring="ABCD"
+
+  case $build_os in
+  msdosdjgpp*)
+    # On DJGPP, this test can blow up pretty badly due to problems in libc
+    # (any single argument exceeding 2000 bytes causes a buffer overrun
+    # during glob expansion).  Even if it were fixed, the result of this
+    # check would be larger than it should be.
+    lt_cv_sys_max_cmd_len=12288;    # 12K is about right
+    ;;
+
+  gnu*)
+    # Under GNU Hurd, this test is not required because there is
+    # no limit to the length of command line arguments.
+    # Libtool will interpret -1 as no limit whatsoever
+    lt_cv_sys_max_cmd_len=-1;
+    ;;
+
+  cygwin* | mingw*)
+    # On Win9x/ME, this test blows up -- it succeeds, but takes
+    # about 5 minutes as the teststring grows exponentially.
+    # Worse, since 9x/ME are not pre-emptively multitasking,
+    # you end up with a "frozen" computer, even though with patience
+    # the test eventually succeeds (with a max line length of 256k).
+    # Instead, let's just punt: use the minimum linelength reported by
+    # all of the supported platforms: 8192 (on NT/2K/XP).
+    lt_cv_sys_max_cmd_len=8192;
+    ;;
+
+  amigaos*)
+    # On AmigaOS with pdksh, this test takes hours, literally.
+    # So we just punt and use a minimum line length of 8192.
+    lt_cv_sys_max_cmd_len=8192;
+    ;;
+
+  netbsd* | freebsd* | openbsd* | darwin* | dragonfly*)
+    # This has been around since 386BSD, at least.  Likely further.
+    if test -x /sbin/sysctl; then
+      lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax`
+    elif test -x /usr/sbin/sysctl; then
+      lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax`
+    else
+      lt_cv_sys_max_cmd_len=65536	# usable default for all BSDs
+    fi
+    # And add a safety zone
+    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
+    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
+    ;;
+
+  interix*)
+    # We know the value 262144 and hardcode it with a safety zone (like BSD)
+    lt_cv_sys_max_cmd_len=196608
+    ;;
+
+  osf*)
+    # Dr. Hans Ekkehard Plesser reports seeing a kernel panic running configure
+    # due to this test when exec_disable_arg_limit is 1 on Tru64. It is not
+    # nice to cause kernel panics so lets avoid the loop below.
+    # First set a reasonable default.
+    lt_cv_sys_max_cmd_len=16384
+    #
+    if test -x /sbin/sysconfig; then
+      case `/sbin/sysconfig -q proc exec_disable_arg_limit` in
+        *1*) lt_cv_sys_max_cmd_len=-1 ;;
+      esac
+    fi
+    ;;
+  sco3.2v5*)
+    lt_cv_sys_max_cmd_len=102400
+    ;;
+  sysv5* | sco5v6* | sysv4.2uw2*)
+    kargmax=`grep ARG_MAX /etc/conf/cf.d/stune 2>/dev/null`
+    if test -n "$kargmax"; then
+      lt_cv_sys_max_cmd_len=`echo $kargmax | sed 's/.*[	 ]//'`
+    else
+      lt_cv_sys_max_cmd_len=32768
+    fi
+    ;;
+  *)
+    lt_cv_sys_max_cmd_len=`getconf ARG_MAX 2> /dev/null`
+    if test -n $lt_cv_sys_max_cmd_len; then
+      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
+      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
+    else
+      # Make teststring a little bigger before we do anything with it.
+      # a 1K string should be a reasonable start.
+      for i in 1 2 3 4 5 6 7 8 ; do
+        teststring=$teststring$teststring
+      done
+      SHELL=${SHELL-${CONFIG_SHELL-/bin/sh}}
+      # If test is not a shell built-in, we'll probably end up computing a
+      # maximum length that is only half of the actual maximum length, but
+      # we can't tell.
+      while { test "X"`$SHELL $0 --fallback-echo "X$teststring$teststring" 2>/dev/null` \
+	         = "XX$teststring$teststring"; } >/dev/null 2>&1 &&
+	      test $i != 17 # 1/2 MB should be enough
+      do
+        i=`expr $i + 1`
+        teststring=$teststring$teststring
+      done
+      # Only check the string length outside the loop.
+      lt_cv_sys_max_cmd_len=`expr "X$teststring" : ".*" 2>&1`
+      teststring=
+      # Add a significant safety factor because C++ compilers can tack on
+      # massive amounts of additional arguments before passing them to the
+      # linker.  It appears as though 1/2 is a usable value.
+      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 2`
+    fi
+    ;;
+  esac
+
+fi
+
+if test -n $lt_cv_sys_max_cmd_len ; then
+  echo "$as_me:$LINENO: result: $lt_cv_sys_max_cmd_len" >&5
+echo "${ECHO_T}$lt_cv_sys_max_cmd_len" >&6
+else
+  echo "$as_me:$LINENO: result: none" >&5
+echo "${ECHO_T}none" >&6
+fi
+max_cmd_len=$lt_cv_sys_max_cmd_len
+
+
+
+
+
+
+
+: ${CP="cp -f"}
+: ${MV="mv -f"}
+: ${RM="rm -f"}
+
+echo "$as_me:$LINENO: checking whether the shell understands some XSI constructs" >&5
+echo $ECHO_N "checking whether the shell understands some XSI constructs... $ECHO_C" >&6
+# Try some XSI features
+xsi_shell=no
+( _lt_dummy="a/b/c"
+  test "${_lt_dummy##*/},${_lt_dummy%/*},"${_lt_dummy%"$_lt_dummy"}, \
+      = c,a/b,, ) >/dev/null 2>&1 \
+  && xsi_shell=yes
+echo "$as_me:$LINENO: result: $xsi_shell" >&5
+echo "${ECHO_T}$xsi_shell" >&6
+
+
+echo "$as_me:$LINENO: checking whether the shell understands \"+=\"" >&5
+echo $ECHO_N "checking whether the shell understands \"+=\"... $ECHO_C" >&6
+lt_shell_append=no
+( foo=bar; set foo baz; eval "$1+=\$2" && test "$foo" = barbaz ) \
+    >/dev/null 2>&1 \
+  && lt_shell_append=yes
+echo "$as_me:$LINENO: result: $lt_shell_append" >&5
+echo "${ECHO_T}$lt_shell_append" >&6
+
+
+if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
+  lt_unset=unset
+else
+  lt_unset=false
+fi
+
+
+
+
+
+# test EBCDIC or ASCII
+case `echo X|tr X '\101'` in
+ A) # ASCII based system
+    # \n is not interpreted correctly by Solaris 8 /usr/ucb/tr
+  lt_SP2NL='tr \040 \012'
+  lt_NL2SP='tr \015\012 \040\040'
+  ;;
+ *) # EBCDIC based system
+  lt_SP2NL='tr \100 \n'
+  lt_NL2SP='tr \r\n \100\100'
+  ;;
+esac
+
+
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking for $LD option to reload object files" >&5
+echo $ECHO_N "checking for $LD option to reload object files... $ECHO_C" >&6
+if test "${lt_cv_ld_reload_flag+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_ld_reload_flag='-r'
+fi
+echo "$as_me:$LINENO: result: $lt_cv_ld_reload_flag" >&5
+echo "${ECHO_T}$lt_cv_ld_reload_flag" >&6
+reload_flag=$lt_cv_ld_reload_flag
+case $reload_flag in
+"" | " "*) ;;
+*) reload_flag=" $reload_flag" ;;
+esac
+reload_cmds='$LD$reload_flag -o $output$reload_objs'
+case $host_os in
+  darwin*)
+    if test "$GCC" = yes; then
+      reload_cmds='$LTCC $LTCFLAGS -nostdlib ${wl}-r -o $output$reload_objs'
+    else
+      reload_cmds='$LD$reload_flag -o $output$reload_objs'
+    fi
+    ;;
+esac
+
+
+
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking how to recognize dependent libraries" >&5
+echo $ECHO_N "checking how to recognize dependent libraries... $ECHO_C" >&6
 if test "${lt_cv_deplibs_check_method+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
@@ -3314,13 +4025,13 @@ lt_cv_deplibs_check_method='unknown'
 # `unknown' -- same as none, but documents that we really don't know.
 # 'pass_all' -- all dependencies passed with no checks.
 # 'test_compile' -- check by making test program.
-# 'file_magic [regex]' -- check by looking for files in library path
-# which responds to the $file_magic_cmd with a given egrep regex.
+# 'file_magic [[regex]]' -- check by looking for files in library path
+# which responds to the $file_magic_cmd with a given extended regex.
 # If you have `file' or equivalent on your system and you're not sure
 # whether `pass_all' will *always* work, you probably want this one.
 
 case $host_os in
-aix*)
+aix4* | aix5*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
@@ -3328,39 +4039,42 @@ beos*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-bsdi4*)
+bsdi[45]*)
   lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)'
   lt_cv_file_magic_cmd='/usr/bin/file -L'
   lt_cv_file_magic_test_file=/shlib/libc.so
   ;;
 
-cygwin* | mingw* |pw32*)
-  lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?'
-  lt_cv_file_magic_cmd='$OBJDUMP -f'
+cygwin*)
+  # func_win32_libid is a shell function defined in ltmain.sh
+  lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL'
+  lt_cv_file_magic_cmd='func_win32_libid'
+  ;;
+
+mingw* | pw32*)
+  # Base MSYS/MinGW do not provide the 'file' command needed by
+  # func_win32_libid shell function, so use a weaker test based on 'objdump',
+  # unless we find 'file', for example because we are cross-compiling.
+  if ( file / ) >/dev/null 2>&1; then
+    lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL'
+    lt_cv_file_magic_cmd='func_win32_libid'
+  else
+    lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?'
+    lt_cv_file_magic_cmd='$OBJDUMP -f'
+  fi
   ;;
 
 darwin* | rhapsody*)
-  # this will be overwritten by pass_all, but leave it in just in case
-  lt_cv_deplibs_check_method='file_magic Mach-O dynamically linked shared library'
-  lt_cv_file_magic_cmd='/usr/bin/file -L'
-  case "$host_os" in
-  rhapsody* | darwin1.012)
-    lt_cv_file_magic_test_file='/System/Library/Frameworks/System.framework/System'
-    ;;
-  *) # Darwin 1.3 on
-    lt_cv_file_magic_test_file='/usr/lib/libSystem.dylib'
-    ;;
-  esac
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-freebsd* | kfreebsd*-gnu)
-  if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then
+freebsd* | dragonfly*)
+  if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then
     case $host_cpu in
     i*86 )
       # Not sure whether the presence of OpenBSD here was a mistake.
       # Let's accept both of them until this is cleared up.
-      lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD)/i[3-9]86 (compact )?demand paged shared library'
+      lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[3-9]86 (compact )?demand paged shared library'
       lt_cv_file_magic_cmd=/usr/bin/file
       lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*`
       ;;
@@ -3374,92 +4088,116 @@ gnu*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-hpux10.20*|hpux11*)
+hpux10.20* | hpux11*)
+  lt_cv_file_magic_cmd=/usr/bin/file
   case $host_cpu in
-  hppa*)
-    lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9].[0-9]) shared library'
-    lt_cv_file_magic_cmd=/usr/bin/file
-    lt_cv_file_magic_test_file=/usr/lib/libc.sl
-    ;;
   ia64*)
     lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - IA64'
-    lt_cv_file_magic_cmd=/usr/bin/file
     lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so
     ;;
-  esac
-  ;;
-
-irix5* | irix6*)
-  case $host_os in
-  irix5*)
-    # this will be overridden with pass_all, but let us keep it just in case
-    lt_cv_deplibs_check_method="file_magic ELF 32-bit MSB dynamic lib MIPS - version 1"
+  hppa*64*)
+    lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - PA-RISC [0-9].[0-9]'
+    lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl
     ;;
   *)
-    case $LD in
-    *-32|*"-32 ") libmagic=32-bit;;
-    *-n32|*"-n32 ") libmagic=N32;;
-    *-64|*"-64 ") libmagic=64-bit;;
-    *) libmagic=never-match;;
-    esac
-    # this will be overridden with pass_all, but let us keep it just in case
-    lt_cv_deplibs_check_method="file_magic ELF ${libmagic} MSB mips-[1234] dynamic lib MIPS - version 1"
+    lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9].[0-9]) shared library'
+    lt_cv_file_magic_test_file=/usr/lib/libc.sl
     ;;
   esac
-  lt_cv_file_magic_test_file=`echo /lib${libsuff}/libc.so*`
+  ;;
+
+interix[3-9]*)
+  # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here
+  lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|\.a)$'
+  ;;
+
+irix5* | irix6* | nonstopux*)
+  case $LD in
+  *-32|*"-32 ") libmagic=32-bit;;
+  *-n32|*"-n32 ") libmagic=N32;;
+  *-64|*"-64 ") libmagic=64-bit;;
+  *) libmagic=never-match;;
+  esac
   lt_cv_deplibs_check_method=pass_all
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux* | k*bsd*-gnu)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-netbsd* | knetbsd*-gnu)
-  if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then
-    lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so\.[0-9]+\.[0-9]+$'
+netbsd*)
+  if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then
+    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$'
   else
-    lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so$'
+    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|_pic\.a)$'
   fi
   ;;
 
-newsos6)
+newos6*)
   lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)'
   lt_cv_file_magic_cmd=/usr/bin/file
   lt_cv_file_magic_test_file=/usr/lib/libnls.so
   ;;
 
+*nto* | *qnx*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+openbsd*)
+  if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|\.so|_pic\.a)$'
+  else
+    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$'
+  fi
+  ;;
+
 osf3* | osf4* | osf5*)
-  # this will be overridden with pass_all, but let us keep it just in case
-  lt_cv_deplibs_check_method='file_magic COFF format alpha shared library'
-  lt_cv_file_magic_test_file=/shlib/libc.so
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-sco3.2v5*)
+rdos*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
 solaris*)
   lt_cv_deplibs_check_method=pass_all
-  lt_cv_file_magic_test_file=/lib/libc.so
   ;;
 
-sysv5uw[78]* | sysv4*uw2*)
+sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*)
+sysv4 | sysv4.3*)
   case $host_vendor in
-  ncr)
-    lt_cv_deplibs_check_method=pass_all
-    ;;
   motorola)
     lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]'
     lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*`
     ;;
+  ncr)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
+  sequent)
+    lt_cv_file_magic_cmd='/bin/file'
+    lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )'
+    ;;
+  sni)
+    lt_cv_file_magic_cmd='/bin/file'
+    lt_cv_deplibs_check_method="file_magic ELF [0-9][0-9]*-bit [LM]SB dynamic lib"
+    lt_cv_file_magic_test_file=/lib/libc.so
+    ;;
+  siemens)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
+  pc)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
   esac
   ;;
+
+tpf*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
 esac
 
 fi
@@ -3467,222 +4205,29 @@ echo "$as_me:$LINENO: result: $lt_cv_deplibs_check_method" >&5
 echo "${ECHO_T}$lt_cv_deplibs_check_method" >&6
 file_magic_cmd=$lt_cv_file_magic_cmd
 deplibs_check_method=$lt_cv_deplibs_check_method
+test -z "$deplibs_check_method" && deplibs_check_method=unknown
 
 
 
 
-# Autoconf 2.13's AC_OBJEXT and AC_EXEEXT macros only works for C compilers!
-
-# find the maximum length of command line arguments
-echo "$as_me:$LINENO: checking the maximum length of command line arguments" >&5
-echo $ECHO_N "checking the maximum length of command line arguments... $ECHO_C" >&6
-if test "${lt_cv_sys_max_cmd_len+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-    i=0
-  teststring="ABCD"
-
-  case $build_os in
-  msdosdjgpp*)
-    # On DJGPP, this test can blow up pretty badly due to problems in libc
-    # (any single argument exceeding 2000 bytes causes a buffer overrun
-    # during glob expansion).  Even if it were fixed, the result of this
-    # check would be larger than it should be.
-    lt_cv_sys_max_cmd_len=12288;    # 12K is about right
-    ;;
-
-  cygwin* | mingw*)
-    # On Win9x/ME, this test blows up -- it succeeds, but takes
-    # about 5 minutes as the teststring grows exponentially.
-    # Worse, since 9x/ME are not pre-emptively multitasking,
-    # you end up with a "frozen" computer, even though with patience
-    # the test eventually succeeds (with a max line length of 256k).
-    # Instead, let's just punt: use the minimum linelength reported by
-    # all of the supported platforms: 8192 (on NT/2K/XP).
-    lt_cv_sys_max_cmd_len=8192;
-    ;;
-
-  amigaos*)
-    # On AmigaOS with pdksh, this test takes hours, literally.
-    # So we just punt and use a minimum line length of 8192.
-    lt_cv_sys_max_cmd_len=8192;
-    ;;
-
-  netbsd* | freebsd* | openbsd* | darwin* | dragonfly*)
-    # This has been around since 386BSD, at least.  Likely further.
-    if test -x /sbin/sysctl; then
-      lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax`
-    elif test -x /usr/sbin/sysctl; then
-      lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax`
-    else
-      lt_cv_sys_max_cmd_len=65536 # usable default for *BSD
-    fi
-    # And add a safety zone
-    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
-    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
-    ;;
-  esac
-
-fi
-
-if test -n "$lt_cv_sys_max_cmd_len" ; then
-  echo "$as_me:$LINENO: result: $lt_cv_sys_max_cmd_len" >&5
-echo "${ECHO_T}$lt_cv_sys_max_cmd_len" >&6
-else
-  echo "$as_me:$LINENO: result: none" >&5
-echo "${ECHO_T}none" >&6
-fi
-
-
-# Only perform the check for file, if the check method requires it
-case $deplibs_check_method in
-file_magic*)
-  if test "$file_magic_cmd" = '$MAGIC_CMD'; then
-    echo "$as_me:$LINENO: checking for ${ac_tool_prefix}file" >&5
-echo $ECHO_N "checking for ${ac_tool_prefix}file... $ECHO_C" >&6
-if test "${lt_cv_path_MAGIC_CMD+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case $MAGIC_CMD in
-  /*)
-  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
-  ;;
-  ?:/*)
-  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path.
-  ;;
-  *)
-  ac_save_MAGIC_CMD="$MAGIC_CMD"
-  IFS="${IFS=   }"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="/usr/bin:$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/${ac_tool_prefix}file; then
-      lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file"
-      if test -n "$file_magic_test_file"; then
-	case $deplibs_check_method in
-	"file_magic "*)
-	  file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`"
-	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
-	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
-	    egrep "$file_magic_regex" > /dev/null; then
-	    :
-	  else
-	    cat <<EOF 1>&2
-
-*** Warning: the command libtool uses to detect shared libraries,
-*** $file_magic_cmd, produces output that libtool cannot recognize.
-*** The result is that libtool may fail to recognize shared libraries
-*** as such.  This will affect the creation of libtool libraries that
-*** depend on shared libraries, but programs linked with such libtool
-*** libraries will work regardless of this problem.  Nevertheless, you
-*** may want to report the problem to your system manager and/or to
-*** bug-libtool@gnu.org
-
-EOF
-	  fi ;;
-	esac
-      fi
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  MAGIC_CMD="$ac_save_MAGIC_CMD"
-  ;;
-esac
-fi
 
-MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
-if test -n "$MAGIC_CMD"; then
-  echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5
-echo "${ECHO_T}$MAGIC_CMD" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
 
-if test -z "$lt_cv_path_MAGIC_CMD"; then
-  if test -n "$ac_tool_prefix"; then
-    echo "$as_me:$LINENO: checking for file" >&5
-echo $ECHO_N "checking for file... $ECHO_C" >&6
-if test "${lt_cv_path_MAGIC_CMD+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case $MAGIC_CMD in
-  /*)
-  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
-  ;;
-  ?:/*)
-  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path.
-  ;;
-  *)
-  ac_save_MAGIC_CMD="$MAGIC_CMD"
-  IFS="${IFS=   }"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="/usr/bin:$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/file; then
-      lt_cv_path_MAGIC_CMD="$ac_dir/file"
-      if test -n "$file_magic_test_file"; then
-	case $deplibs_check_method in
-	"file_magic "*)
-	  file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`"
-	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
-	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
-	    egrep "$file_magic_regex" > /dev/null; then
-	    :
-	  else
-	    cat <<EOF 1>&2
 
-*** Warning: the command libtool uses to detect shared libraries,
-*** $file_magic_cmd, produces output that libtool cannot recognize.
-*** The result is that libtool may fail to recognize shared libraries
-*** as such.  This will affect the creation of libtool libraries that
-*** depend on shared libraries, but programs linked with such libtool
-*** libraries will work regardless of this problem.  Nevertheless, you
-*** may want to report the problem to your system manager and/or to
-*** bug-libtool@gnu.org
 
-EOF
-	  fi ;;
-	esac
-      fi
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  MAGIC_CMD="$ac_save_MAGIC_CMD"
-  ;;
-esac
-fi
 
-MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
-if test -n "$MAGIC_CMD"; then
-  echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5
-echo "${ECHO_T}$MAGIC_CMD" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
 
-  else
-    MAGIC_CMD=:
-  fi
-fi
 
-  fi
-  ;;
-esac
 
 if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
-set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+  # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ar; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_RANLIB+set}" = set; then
+if test "${ac_cv_prog_AR+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+  if test -n "$AR"; then
+  ac_cv_prog_AR="$AR" # Let the user override the test.
 else
 as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
 for as_dir in $PATH
@@ -3691,7 +4236,7 @@ do
   test -z "$as_dir" && as_dir=.
   for ac_exec_ext in '' $ac_executable_extensions; do
   if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+    ac_cv_prog_AR="${ac_tool_prefix}ar"
     echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
     break 2
   fi
@@ -3700,27 +4245,27 @@ done
 
 fi
 fi
-RANLIB=$ac_cv_prog_RANLIB
-if test -n "$RANLIB"; then
-  echo "$as_me:$LINENO: result: $RANLIB" >&5
-echo "${ECHO_T}$RANLIB" >&6
+AR=$ac_cv_prog_AR
+if test -n "$AR"; then
+  echo "$as_me:$LINENO: result: $AR" >&5
+echo "${ECHO_T}$AR" >&6
 else
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
 fi
 
 fi
-if test -z "$ac_cv_prog_RANLIB"; then
-  ac_ct_RANLIB=$RANLIB
-  # Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
+if test -z "$ac_cv_prog_AR"; then
+  ac_ct_AR=$AR
+  # Extract the first word of "ar", so it can be a program name with args.
+set dummy ar; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
+if test "${ac_cv_prog_ac_ct_AR+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  if test -n "$ac_ct_RANLIB"; then
-  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
+  if test -n "$ac_ct_AR"; then
+  ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test.
 else
 as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
 for as_dir in $PATH
@@ -3729,30 +4274,43 @@ do
   test -z "$as_dir" && as_dir=.
   for ac_exec_ext in '' $ac_executable_extensions; do
   if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_RANLIB="ranlib"
+    ac_cv_prog_ac_ct_AR="ar"
     echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
     break 2
   fi
 done
 done
 
-  test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
+  test -z "$ac_cv_prog_ac_ct_AR" && ac_cv_prog_ac_ct_AR="false"
 fi
 fi
-ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
-if test -n "$ac_ct_RANLIB"; then
-  echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
-echo "${ECHO_T}$ac_ct_RANLIB" >&6
+ac_ct_AR=$ac_cv_prog_ac_ct_AR
+if test -n "$ac_ct_AR"; then
+  echo "$as_me:$LINENO: result: $ac_ct_AR" >&5
+echo "${ECHO_T}$ac_ct_AR" >&6
 else
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
 fi
 
-  RANLIB=$ac_ct_RANLIB
+  AR=$ac_ct_AR
 else
-  RANLIB="$ac_cv_prog_RANLIB"
+  AR="$ac_cv_prog_AR"
 fi
 
+test -z "$AR" && AR=ar
+test -z "$AR_FLAGS" && AR_FLAGS=cru
+
+
+
+
+
+
+
+
+
+
+
 if test -n "$ac_tool_prefix"; then
   # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args.
 set dummy ${ac_tool_prefix}strip; ac_word=$2
@@ -3833,96 +4391,471 @@ else
   STRIP="$ac_cv_prog_STRIP"
 fi
 
+test -z "$STRIP" && STRIP=:
 
-# Check for any special flags to pass to ltconfig.
-libtool_flags="--cache-file=$cache_file"
-test "$enable_shared" = no && libtool_flags="$libtool_flags --disable-shared"
-test "$enable_static" = no && libtool_flags="$libtool_flags --disable-static"
-test "$enable_fast_install" = no && libtool_flags="$libtool_flags --disable-fast-install"
-test "$GCC" = yes && libtool_flags="$libtool_flags --with-gcc"
-test "$lt_cv_prog_gnu_ld" = yes && libtool_flags="$libtool_flags --with-gnu-ld"
 
 
-# Check whether --enable-libtool-lock or --disable-libtool-lock was given.
-if test "${enable_libtool_lock+set}" = set; then
-  enableval="$enable_libtool_lock"
 
-fi;
-test "x$enable_libtool_lock" = xno && libtool_flags="$libtool_flags --disable-lock"
-test x"$silent" = xyes && libtool_flags="$libtool_flags --silent"
 
 
-# Check whether --with-pic or --without-pic was given.
-if test "${with_pic+set}" = set; then
-  withval="$with_pic"
-  pic_mode="$withval"
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_RANLIB+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  pic_mode=default
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+
+fi
+fi
+RANLIB=$ac_cv_prog_RANLIB
+if test -n "$RANLIB"; then
+  echo "$as_me:$LINENO: result: $RANLIB" >&5
+echo "${ECHO_T}$RANLIB" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$ac_cv_prog_RANLIB"; then
+  ac_ct_RANLIB=$RANLIB
+  # Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if test -n "$ac_ct_RANLIB"; then
+  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_RANLIB="ranlib"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+
+  test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
+fi
+fi
+ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
+if test -n "$ac_ct_RANLIB"; then
+  echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
+echo "${ECHO_T}$ac_ct_RANLIB" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+  RANLIB=$ac_ct_RANLIB
+else
+  RANLIB="$ac_cv_prog_RANLIB"
+fi
+
+test -z "$RANLIB" && RANLIB=:
+
+
+
+
+
+
+# Determine commands to create old-style static archives.
+old_archive_cmds='$AR $AR_FLAGS $oldlib$oldobjs$old_deplibs'
+old_postinstall_cmds='chmod 644 $oldlib'
+old_postuninstall_cmds=
+
+if test -n "$RANLIB"; then
+  case $host_os in
+  openbsd*)
+    old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB -t \$oldlib"
+    ;;
+  *)
+    old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB \$oldlib"
+    ;;
+  esac
+  old_archive_cmds="$old_archive_cmds~\$RANLIB \$oldlib"
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# If no C compiler was specified, use CC.
+LTCC=${LTCC-"$CC"}
+
+# If no C compiler flags were specified, use CFLAGS.
+LTCFLAGS=${LTCFLAGS-"$CFLAGS"}
+
+# Allow CC to be a program name with arguments.
+compiler=$CC
+
+
+# Check for command to grab the raw symbol name followed by C symbol from nm.
+echo "$as_me:$LINENO: checking command to parse $NM output from $compiler object" >&5
+echo $ECHO_N "checking command to parse $NM output from $compiler object... $ECHO_C" >&6
+if test "${lt_cv_sys_global_symbol_pipe+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+
+# These are sane defaults that work on at least a few old systems.
+# [They come from Ultrix.  What could be older than Ultrix?!! ;)]
+
+# Character class describing NM global symbol codes.
+symcode='[BCDEGRST]'
+
+# Regexp to match symbols that can be accessed directly from C.
+sympat='\([_A-Za-z][_A-Za-z0-9]*\)'
+
+# Define system-specific variables.
+case $host_os in
+aix*)
+  symcode='[BCDT]'
+  ;;
+cygwin* | mingw* | pw32*)
+  symcode='[ABCDGISTW]'
+  ;;
+hpux*)
+  if test "$host_cpu" = ia64; then
+    symcode='[ABCDEGRST]'
+  fi
+  ;;
+irix* | nonstopux*)
+  symcode='[BCDEGRST]'
+  ;;
+osf*)
+  symcode='[BCDEGQRST]'
+  ;;
+solaris*)
+  symcode='[BDRT]'
+  ;;
+sco3.2v5*)
+  symcode='[DT]'
+  ;;
+sysv4.2uw2*)
+  symcode='[DT]'
+  ;;
+sysv5* | sco5v6* | unixware* | OpenUNIX*)
+  symcode='[ABDT]'
+  ;;
+sysv4)
+  symcode='[DFNSTU]'
+  ;;
+esac
+
+# If we're using GNU nm, then use its standard symbol codes.
+case `$NM -V 2>&1` in
+*GNU* | *'with BFD'*)
+  symcode='[ABCDGIRSTW]' ;;
+esac
+
+# Transform an extracted symbol line into a proper C declaration.
+# Some systems (esp. on ia64) link data and code symbols differently,
+# so use this general approach.
+lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'"
+
+# Transform an extracted symbol line into symbol name and symbol address
+lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\) $/  {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/  {\"\2\", (void *) \&\2},/p'"
+
+# Handle CRLF in mingw tool chain
+opt_cr=
+case $build_os in
+mingw*)
+  opt_cr=`$ECHO 'x\{0,1\}' | tr x '\015'` # option cr in regexp
+  ;;
+esac
+
+# Try without a prefix underscore, then with it.
+for ac_symprfx in "" "_"; do
+
+  # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol.
+  symxfrm="\\1 $ac_symprfx\\2 \\2"
+
+  # Write the raw and C identifiers.
+  if test "$lt_cv_nm_interface" = "MS dumpbin"; then
+    # Fake it for dumpbin and say T for any non-static function
+    # and D for any global variable.
+    # Also find C++ and __fastcall symbols from MSVC++,
+    # which start with @ or ?.
+    lt_cv_sys_global_symbol_pipe="$AWK '"\
+"     {last_section=section; section=\$ 3};"\
+"     /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\
+"     \$ 0!~/External *\|/{next};"\
+"     / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\
+"     {if(hide[section]) next};"\
+"     {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\
+"     {split(\$ 0, a, /\||\r/); split(a[2], s)};"\
+"     s[1]~/^[@?]/{print s[1], s[1]; next};"\
+"     s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\
+"     ' prfx=^$ac_symprfx"
+  else
+    lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[	 ]\($symcode$symcode*\)[	 ][	 ]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'"
+  fi
+
+  # Check to see that the pipe works correctly.
+  pipe_works=no
+
+  rm -f conftest*
+  cat > conftest.$ac_ext <<_LT_EOF
+#ifdef __cplusplus
+extern "C" {
+#endif
+char nm_test_var;
+void nm_test_func(void);
+void nm_test_func(void){}
+#ifdef __cplusplus
+}
+#endif
+int main(){nm_test_var='a';nm_test_func();return(0);}
+_LT_EOF
+
+  if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; then
+    # Now try to grab the symbols.
+    nlist=conftest.nm
+    if { (eval echo "$as_me:$LINENO: \"$NM conftest.$ac_objext \| $lt_cv_sys_global_symbol_pipe \> $nlist\"") >&5
+  (eval $NM conftest.$ac_objext \| $lt_cv_sys_global_symbol_pipe \> $nlist) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && test -s "$nlist"; then
+      # Try sorting and uniquifying the output.
+      if sort "$nlist" | uniq > "$nlist"T; then
+	mv -f "$nlist"T "$nlist"
+      else
+	rm -f "$nlist"T
+      fi
+
+      # Make sure that we snagged all the symbols we need.
+      if $GREP ' nm_test_var$' "$nlist" >/dev/null; then
+	if $GREP ' nm_test_func$' "$nlist" >/dev/null; then
+	  cat <<_LT_EOF > conftest.$ac_ext
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+_LT_EOF
+	  # Now generate the symbol file.
+	  eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext'
+
+	  cat <<_LT_EOF >> conftest.$ac_ext
+
+/* The mapping between symbol names and symbols.  */
+const struct {
+  const char *name;
+  void       *address;
+}
+lt__PROGRAM__LTX_preloaded_symbols[] =
+{
+  { "@PROGRAM@", (void *) 0 },
+_LT_EOF
+	  $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/  {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext
+	  cat <<\_LT_EOF >> conftest.$ac_ext
+  {0, (void *) 0}
+};
+
+/* This works around a problem in FreeBSD linker */
+#ifdef FREEBSD_WORKAROUND
+static const void *lt_preloaded_setup() {
+  return lt__PROGRAM__LTX_preloaded_symbols;
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+_LT_EOF
+	  # Now try linking the two files.
+	  mv conftest.$ac_objext conftstm.$ac_objext
+	  lt_save_LIBS="$LIBS"
+	  lt_save_CFLAGS="$CFLAGS"
+	  LIBS="conftstm.$ac_objext"
+	  CFLAGS="$CFLAGS$lt_prog_compiler_no_builtin_flag"
+	  if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && test -s conftest${ac_exeext}; then
+	    pipe_works=yes
+	  fi
+	  LIBS="$lt_save_LIBS"
+	  CFLAGS="$lt_save_CFLAGS"
+	else
+	  echo "cannot find nm_test_func in $nlist" >&5
+	fi
+      else
+	echo "cannot find nm_test_var in $nlist" >&5
+      fi
+    else
+      echo "cannot run $lt_cv_sys_global_symbol_pipe" >&5
+    fi
+  else
+    echo "$progname: failed program was:" >&5
+    cat conftest.$ac_ext >&5
+  fi
+  rm -f conftest* conftst*
+
+  # Do not use the global_symbol_pipe unless it works.
+  if test "$pipe_works" = yes; then
+    break
+  else
+    lt_cv_sys_global_symbol_pipe=
+  fi
+done
+
+fi
+
+if test -z "$lt_cv_sys_global_symbol_pipe"; then
+  lt_cv_sys_global_symbol_to_cdecl=
+fi
+if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then
+  echo "$as_me:$LINENO: result: failed" >&5
+echo "${ECHO_T}failed" >&6
+else
+  echo "$as_me:$LINENO: result: ok" >&5
+echo "${ECHO_T}ok" >&6
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# Check whether --enable-libtool-lock or --disable-libtool-lock was given.
+if test "${enable_libtool_lock+set}" = set; then
+  enableval="$enable_libtool_lock"
+
 fi;
-test x"$pic_mode" = xyes && libtool_flags="$libtool_flags --prefer-pic"
-test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic"
+test "x$enable_libtool_lock" != xno && enable_libtool_lock=yes
 
 # Some flags need to be propagated to the compiler or linker for good
 # libtool support.
 case $host in
-*-*-irix6*)
+ia64-*-hpux*)
   # Find out which ABI we are using.
-  echo '#line 3870 "configure"' > conftest.$ac_ext
+  echo 'int i;' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   (eval $ac_compile) 2>&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; then
-   if test "$lt_cv_prog_gnu_ld" = yes; then
-    case `/usr/bin/file conftest.$ac_objext` in
-    *32-bit*)
-      LD="${LD-ld} -melf32bsmip"
-      ;;
-    *N32*)
-      LD="${LD-ld} -melf32bmipn32"
-      ;;
-    *64-bit*)
-      LD="${LD-ld} -melf64bmip"
-      ;;
-    esac
-   else
     case `/usr/bin/file conftest.$ac_objext` in
-    *32-bit*)
-      LD="${LD-ld} -32"
-      ;;
-    *N32*)
-      LD="${LD-ld} -n32"
-      ;;
-    *64-bit*)
-      LD="${LD-ld} -64"
-      ;;
+      *ELF-32*)
+	HPUX_IA64_MODE="32"
+	;;
+      *ELF-64*)
+	HPUX_IA64_MODE="64"
+	;;
     esac
-   fi
   fi
   rm -rf conftest*
   ;;
-
-ia64-*-hpux*)
+*-*-irix6*)
   # Find out which ABI we are using.
-  echo 'int i;' > conftest.$ac_ext
+  echo '#line 4822 "configure"' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   (eval $ac_compile) 2>&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; then
-    case "`/usr/bin/file conftest.o`" in
-    *ELF-32*)
-      HPUX_IA64_MODE="32"
-      ;;
-    *ELF-64*)
-      HPUX_IA64_MODE="64"
-      ;;
-    esac
+    if test "$lt_cv_prog_gnu_ld" = yes; then
+      case `/usr/bin/file conftest.$ac_objext` in
+	*32-bit*)
+	  LD="${LD-ld} -melf32bsmip"
+	  ;;
+	*N32*)
+	  LD="${LD-ld} -melf32bmipn32"
+	  ;;
+	*64-bit*)
+	  LD="${LD-ld} -melf64bmip"
+	;;
+      esac
+    else
+      case `/usr/bin/file conftest.$ac_objext` in
+	*32-bit*)
+	  LD="${LD-ld} -32"
+	  ;;
+	*N32*)
+	  LD="${LD-ld} -n32"
+	  ;;
+	*64-bit*)
+	  LD="${LD-ld} -64"
+	  ;;
+      esac
+    fi
   fi
   rm -rf conftest*
   ;;
 
-x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)
+x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
+s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
   # Find out which ABI we are using.
   echo 'int i;' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
@@ -3930,39 +4863,45 @@ x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; then
-    case "`/usr/bin/file conftest.o`" in
-    *32-bit*)
-      case $host in
-        x86_64-*linux*)
-          LD="${LD-ld} -m elf_i386"
-          ;;
-        ppc64-*linux*|powerpc64-*linux*)
-          LD="${LD-ld} -m elf32ppclinux"
-          ;;
-        s390x-*linux*)
-          LD="${LD-ld} -m elf_s390"
-          ;;
-        sparc64-*linux*)
-          LD="${LD-ld} -m elf32_sparc"
-          ;;
-      esac
-      ;;
-    *64-bit*)
-      case $host in
-        x86_64-*linux*)
-          LD="${LD-ld} -m elf_x86_64"
-          ;;
-        ppc*-*linux*|powerpc*-*linux*)
-          LD="${LD-ld} -m elf64ppc"
-          ;;
-        s390*-*linux*)
-          LD="${LD-ld} -m elf64_s390"
-          ;;
-        sparc*-*linux*)
-          LD="${LD-ld} -m elf64_sparc"
-          ;;
-      esac
-      ;;
+    case `/usr/bin/file conftest.o` in
+      *32-bit*)
+	case $host in
+	  x86_64-*kfreebsd*-gnu)
+	    LD="${LD-ld} -m elf_i386_fbsd"
+	    ;;
+	  x86_64-*linux*)
+	    LD="${LD-ld} -m elf_i386"
+	    ;;
+	  ppc64-*linux*|powerpc64-*linux*)
+	    LD="${LD-ld} -m elf32ppclinux"
+	    ;;
+	  s390x-*linux*)
+	    LD="${LD-ld} -m elf_s390"
+	    ;;
+	  sparc64-*linux*)
+	    LD="${LD-ld} -m elf32_sparc"
+	    ;;
+	esac
+	;;
+      *64-bit*)
+	case $host in
+	  x86_64-*kfreebsd*-gnu)
+	    LD="${LD-ld} -m elf_x86_64_fbsd"
+	    ;;
+	  x86_64-*linux*)
+	    LD="${LD-ld} -m elf_x86_64"
+	    ;;
+	  ppc*-*linux*|powerpc*-*linux*)
+	    LD="${LD-ld} -m elf64ppc"
+	    ;;
+	  s390*-*linux*|s390*-*tpf*)
+	    LD="${LD-ld} -m elf64_s390"
+	    ;;
+	  sparc*-*linux*)
+	    LD="${LD-ld} -m elf64_sparc"
+	    ;;
+	esac
+	;;
     esac
   fi
   rm -rf conftest*
@@ -3977,9 +4916,7 @@ echo $ECHO_N "checking whether the C compiler needs -belf... $ECHO_C" >&6
 if test "${lt_cv_cc_needs_belf+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-
-
-     ac_ext=c
+  ac_ext=c
 ac_cpp='$CPP $CPPFLAGS'
 ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
 ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
@@ -4045,112 +4982,4551 @@ echo "${ECHO_T}$lt_cv_cc_needs_belf" >&6
     CFLAGS="$SAVE_CFLAGS"
   fi
   ;;
+sparc*-*solaris*)
+  # Find out which ABI we are using.
+  echo 'int i;' > conftest.$ac_ext
+  if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; then
+    case `/usr/bin/file conftest.o` in
+    *64-bit*)
+      case $lt_cv_prog_gnu_ld in
+      yes*) LD="${LD-ld} -m elf64_sparc" ;;
+      *)    LD="${LD-ld} -64" ;;
+      esac
+      ;;
+    esac
+  fi
+  rm -rf conftest*
+  ;;
+esac
+
+need_locks="$enable_libtool_lock"
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
+echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+  CPP=
+fi
+if test -z "$CPP"; then
+  if test "${ac_cv_prog_CPP+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+      # Double quotes because CPP needs to be expanded
+    for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
+    do
+      ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+  # Use a header file that comes with gcc, so configuring glibc
+  # with a fresh cross-compiler works.
+  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+  # <limits.h> exists even on freestanding compilers.
+  # On the NeXT, cc -E runs the code through the compiler's parser,
+  # not just through cpp. "Syntax error" is here to catch this case.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+		     Syntax error
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null; then
+  if test -s conftest.err; then
+    ac_cpp_err=$ac_c_preproc_warn_flag
+    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+  else
+    ac_cpp_err=
+  fi
+else
+  ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+  :
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+  # OK, works on sane cases.  Now check whether non-existent headers
+  # can be detected and how.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null; then
+  if test -s conftest.err; then
+    ac_cpp_err=$ac_c_preproc_warn_flag
+    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+  else
+    ac_cpp_err=
+  fi
+else
+  ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+  # Broken: success on invalid input.
+continue
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+  break
+fi
+
+    done
+    ac_cv_prog_CPP=$CPP
+
+fi
+  CPP=$ac_cv_prog_CPP
+else
+  ac_cv_prog_CPP=$CPP
+fi
+echo "$as_me:$LINENO: result: $CPP" >&5
+echo "${ECHO_T}$CPP" >&6
+ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+  # Use a header file that comes with gcc, so configuring glibc
+  # with a fresh cross-compiler works.
+  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+  # <limits.h> exists even on freestanding compilers.
+  # On the NeXT, cc -E runs the code through the compiler's parser,
+  # not just through cpp. "Syntax error" is here to catch this case.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+		     Syntax error
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null; then
+  if test -s conftest.err; then
+    ac_cpp_err=$ac_c_preproc_warn_flag
+    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+  else
+    ac_cpp_err=
+  fi
+else
+  ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+  :
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+  # OK, works on sane cases.  Now check whether non-existent headers
+  # can be detected and how.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null; then
+  if test -s conftest.err; then
+    ac_cpp_err=$ac_c_preproc_warn_flag
+    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+  else
+    ac_cpp_err=
+  fi
+else
+  ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+  # Broken: success on invalid input.
+continue
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+  :
+else
+  { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&5
+echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&2;}
+   { (exit 1); exit 1; }; }
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+echo "$as_me:$LINENO: checking for ANSI C header files" >&5
+echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6
+if test "${ac_cv_header_stdc+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_header_stdc=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_header_stdc=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+
+if test $ac_cv_header_stdc = yes; then
+  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <string.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  $EGREP "memchr" >/dev/null 2>&1; then
+  :
+else
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <stdlib.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  $EGREP "free" >/dev/null 2>&1; then
+  :
+else
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+  if test "$cross_compiling" = yes; then
+  :
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <ctype.h>
+#if ((' ' & 0x0FF) == 0x020)
+# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#else
+# define ISLOWER(c) \
+		   (('a' <= (c) && (c) <= 'i') \
+		     || ('j' <= (c) && (c) <= 'r') \
+		     || ('s' <= (c) && (c) <= 'z'))
+# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
+#endif
+
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int
+main ()
+{
+  int i;
+  for (i = 0; i < 256; i++)
+    if (XOR (islower (i), ISLOWER (i))
+	|| toupper (i) != TOUPPER (i))
+      exit(2);
+  exit (0);
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  :
+else
+  echo "$as_me: program exited with status $ac_status" >&5
+echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_header_stdc=no
+fi
+rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
+echo "${ECHO_T}$ac_cv_header_stdc" >&6
+if test $ac_cv_header_stdc = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define STDC_HEADERS 1
+_ACEOF
+
+fi
+
+# On IRIX 5.3, sys/types and inttypes.h are conflicting.
+
+
+
+
+
+
+
+
+
+for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
+		  inttypes.h stdint.h unistd.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  eval "$as_ac_Header=yes"
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_Header=no"
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+for ac_header in dlfcn.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  eval "$as_ac_Header=yes"
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_Header=no"
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+# This can be used to rebuild libtool when needed
+LIBTOOL_DEPS="$ltmain"
+
+# Always use our own libtool.
+LIBTOOL='$(SHELL) $(top_builddir)/libtool'
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+test -z "$LN_S" && LN_S="ln -s"
+
+
 
 
+
+
+
+
+
+
+
+
+
+
+if test -n "${ZSH_VERSION+set}" ; then
+   setopt NO_GLOB_SUBST
+fi
+
+echo "$as_me:$LINENO: checking for objdir" >&5
+echo $ECHO_N "checking for objdir... $ECHO_C" >&6
+if test "${lt_cv_objdir+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  rm -f .libs 2>/dev/null
+mkdir .libs 2>/dev/null
+if test -d .libs; then
+  lt_cv_objdir=.libs
+else
+  # MS-DOS does not allow filenames that begin with a dot.
+  lt_cv_objdir=_libs
+fi
+rmdir .libs 2>/dev/null
+fi
+echo "$as_me:$LINENO: result: $lt_cv_objdir" >&5
+echo "${ECHO_T}$lt_cv_objdir" >&6
+objdir=$lt_cv_objdir
+
+
+
+
+
+cat >>confdefs.h <<_ACEOF
+#define LT_OBJDIR "$lt_cv_objdir/"
+_ACEOF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+case $host_os in
+aix3*)
+  # AIX sometimes has problems with the GCC collect2 program.  For some
+  # reason, if we set the COLLECT_NAMES environment variable, the problems
+  # vanish in a puff of smoke.
+  if test "X${COLLECT_NAMES+set}" != Xset; then
+    COLLECT_NAMES=
+    export COLLECT_NAMES
+  fi
+  ;;
 esac
 
+# Sed substitution that helps us do robust quoting.  It backslashifies
+# metacharacters that are still active within double-quoted strings.
+sed_quote_subst='s/\(["`$\\]\)/\\\1/g'
+
+# Same as above, but do not quote variable references.
+double_quote_subst='s/\(["`\\]\)/\\\1/g'
+
+# Sed substitution to delay expansion of an escaped shell variable in a
+# double_quote_subst'ed string.
+delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g'
+
+# Sed substitution to delay expansion of an escaped single quote.
+delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g'
+
+# Sed substitution to avoid accidental globbing in evaled expressions
+no_glob_subst='s/\*/\\\*/g'
+
+# Global variables:
+ofile=libtool
+can_build_shared=yes
+
+# All known linkers require a `.a' archive for static linking (except MSVC,
+# which needs '.lib').
+libext=a
+
+with_gnu_ld="$lt_cv_prog_gnu_ld"
+
+old_CC="$CC"
+old_CFLAGS="$CFLAGS"
+
+# Set sane defaults for various variables
+test -z "$CC" && CC=cc
+test -z "$LTCC" && LTCC=$CC
+test -z "$LTCFLAGS" && LTCFLAGS=$CFLAGS
+test -z "$LD" && LD=ld
+test -z "$ac_objext" && ac_objext=o
+
+for cc_temp in $compiler""; do
+  case $cc_temp in
+    compile | *[\\/]compile | ccache | *[\\/]ccache ) ;;
+    distcc | *[\\/]distcc | purify | *[\\/]purify ) ;;
+    \-*) ;;
+    *) break;;
+  esac
+done
+cc_basename=`$ECHO "X$cc_temp" | $Xsed -e 's%.*/%%' -e "s%^$host_alias-%%"`
+
+
+# Only perform the check for file, if the check method requires it
+test -z "$MAGIC_CMD" && MAGIC_CMD=file
+case $deplibs_check_method in
+file_magic*)
+  if test "$file_magic_cmd" = '$MAGIC_CMD'; then
+    echo "$as_me:$LINENO: checking for ${ac_tool_prefix}file" >&5
+echo $ECHO_N "checking for ${ac_tool_prefix}file... $ECHO_C" >&6
+if test "${lt_cv_path_MAGIC_CMD+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  case $MAGIC_CMD in
+[\\/*] |  ?:[\\/]*)
+  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
+  ;;
+*)
+  lt_save_MAGIC_CMD="$MAGIC_CMD"
+  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+  ac_dummy="/usr/bin$PATH_SEPARATOR$PATH"
+  for ac_dir in $ac_dummy; do
+    IFS="$lt_save_ifs"
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/${ac_tool_prefix}file; then
+      lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file"
+      if test -n "$file_magic_test_file"; then
+	case $deplibs_check_method in
+	"file_magic "*)
+	  file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"`
+	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
+	    $EGREP "$file_magic_regex" > /dev/null; then
+	    :
+	  else
+	    cat <<_LT_EOF 1>&2
+
+*** Warning: the command libtool uses to detect shared libraries,
+*** $file_magic_cmd, produces output that libtool cannot recognize.
+*** The result is that libtool may fail to recognize shared libraries
+*** as such.  This will affect the creation of libtool libraries that
+*** depend on shared libraries, but programs linked with such libtool
+*** libraries will work regardless of this problem.  Nevertheless, you
+*** may want to report the problem to your system manager and/or to
+*** bug-libtool@gnu.org
+
+_LT_EOF
+	  fi ;;
+	esac
+      fi
+      break
+    fi
+  done
+  IFS="$lt_save_ifs"
+  MAGIC_CMD="$lt_save_MAGIC_CMD"
+  ;;
+esac
+fi
+
+MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+if test -n "$MAGIC_CMD"; then
+  echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5
+echo "${ECHO_T}$MAGIC_CMD" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+
+
+
+
+if test -z "$lt_cv_path_MAGIC_CMD"; then
+  if test -n "$ac_tool_prefix"; then
+    echo "$as_me:$LINENO: checking for file" >&5
+echo $ECHO_N "checking for file... $ECHO_C" >&6
+if test "${lt_cv_path_MAGIC_CMD+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  case $MAGIC_CMD in
+[\\/*] |  ?:[\\/]*)
+  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
+  ;;
+*)
+  lt_save_MAGIC_CMD="$MAGIC_CMD"
+  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+  ac_dummy="/usr/bin$PATH_SEPARATOR$PATH"
+  for ac_dir in $ac_dummy; do
+    IFS="$lt_save_ifs"
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/file; then
+      lt_cv_path_MAGIC_CMD="$ac_dir/file"
+      if test -n "$file_magic_test_file"; then
+	case $deplibs_check_method in
+	"file_magic "*)
+	  file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"`
+	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
+	    $EGREP "$file_magic_regex" > /dev/null; then
+	    :
+	  else
+	    cat <<_LT_EOF 1>&2
+
+*** Warning: the command libtool uses to detect shared libraries,
+*** $file_magic_cmd, produces output that libtool cannot recognize.
+*** The result is that libtool may fail to recognize shared libraries
+*** as such.  This will affect the creation of libtool libraries that
+*** depend on shared libraries, but programs linked with such libtool
+*** libraries will work regardless of this problem.  Nevertheless, you
+*** may want to report the problem to your system manager and/or to
+*** bug-libtool@gnu.org
+
+_LT_EOF
+	  fi ;;
+	esac
+      fi
+      break
+    fi
+  done
+  IFS="$lt_save_ifs"
+  MAGIC_CMD="$lt_save_MAGIC_CMD"
+  ;;
+esac
+fi
+
+MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+if test -n "$MAGIC_CMD"; then
+  echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5
+echo "${ECHO_T}$MAGIC_CMD" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+
+  else
+    MAGIC_CMD=:
+  fi
+fi
+
+  fi
+  ;;
+esac
+
+# Use C for the default configuration in the libtool script
+
+lt_save_CC="$CC"
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+# Source file extension for C test sources.
+ac_ext=c
+
+# Object file extension for compiled C test sources.
+objext=o
+objext=$objext
+
+# Code to be used in simple compile tests
+lt_simple_compile_test_code="int some_variable = 0;"
+
+# Code to be used in simple link tests
+lt_simple_link_test_code='int main(){return(0);}'
+
+
+
+
+
+
+
+# If no C compiler was specified, use CC.
+LTCC=${LTCC-"$CC"}
+
+# If no C compiler flags were specified, use CFLAGS.
+LTCFLAGS=${LTCFLAGS-"$CFLAGS"}
+
+# Allow CC to be a program name with arguments.
+compiler=$CC
+
+# Save the default compiler, since it gets overwritten when the other
+# tags are being tested, and _LT_TAGVAR(compiler, []) is a NOP.
+compiler_DEFAULT=$CC
+
+# save warnings/boilerplate of simple test code
+ac_outfile=conftest.$ac_objext
+echo "$lt_simple_compile_test_code" >conftest.$ac_ext
+eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err
+_lt_compiler_boilerplate=`cat conftest.err`
+$RM conftest*
+
+ac_outfile=conftest.$ac_objext
+echo "$lt_simple_link_test_code" >conftest.$ac_ext
+eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err
+_lt_linker_boilerplate=`cat conftest.err`
+$RM conftest*
+
+
+## CAVEAT EMPTOR:
+## There is no encapsulation within the following macros, do not change
+## the running order or otherwise move them around unless you know exactly
+## what you are doing...
+if test -n "$compiler"; then
+
+lt_prog_compiler_no_builtin_flag=
+
+if test "$GCC" = yes; then
+  lt_prog_compiler_no_builtin_flag=' -fno-builtin'
+
+  echo "$as_me:$LINENO: checking if $compiler supports -fno-rtti -fno-exceptions" >&5
+echo $ECHO_N "checking if $compiler supports -fno-rtti -fno-exceptions... $ECHO_C" >&6
+if test "${lt_cv_prog_compiler_rtti_exceptions+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_prog_compiler_rtti_exceptions=no
+   ac_outfile=conftest.$ac_objext
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+   lt_compiler_flag="-fno-rtti -fno-exceptions"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   # The option is referenced via a variable to avoid confusing sed.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:5922: $lt_compile\"" >&5)
+   (eval "$lt_compile" 2>conftest.err)
+   ac_status=$?
+   cat conftest.err >&5
+   echo "$as_me:5926: \$? = $ac_status" >&5
+   if (exit $ac_status) && test -s "$ac_outfile"; then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings other than the usual output.
+     $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' >conftest.exp
+     $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
+     if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then
+       lt_cv_prog_compiler_rtti_exceptions=yes
+     fi
+   fi
+   $RM conftest*
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_rtti_exceptions" >&5
+echo "${ECHO_T}$lt_cv_prog_compiler_rtti_exceptions" >&6
+
+if test x"$lt_cv_prog_compiler_rtti_exceptions" = xyes; then
+    lt_prog_compiler_no_builtin_flag="$lt_prog_compiler_no_builtin_flag -fno-rtti -fno-exceptions"
+else
+    :
+fi
+
+fi
+
+
+
+
+
+
+  lt_prog_compiler_wl=
+lt_prog_compiler_pic=
+lt_prog_compiler_static=
+
+echo "$as_me:$LINENO: checking for $compiler option to produce PIC" >&5
+echo $ECHO_N "checking for $compiler option to produce PIC... $ECHO_C" >&6
+
+  if test "$GCC" = yes; then
+    lt_prog_compiler_wl='-Wl,'
+    lt_prog_compiler_static='-static'
+
+    case $host_os in
+      aix*)
+      # All AIX code is PIC.
+      if test "$host_cpu" = ia64; then
+	# AIX 5 now supports IA64 processor
+	lt_prog_compiler_static='-Bstatic'
+      fi
+      ;;
+
+    amigaos*)
+      if test "$host_cpu" = m68k; then
+        # FIXME: we need at least 68020 code to build shared libraries, but
+        # adding the `-m68020' flag to GCC prevents building anything better,
+        # like `-m68040'.
+        lt_prog_compiler_pic='-m68020 -resident32 -malways-restore-a4'
+      fi
+      ;;
+
+    beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*)
+      # PIC is the default for these OSes.
+      ;;
+
+    mingw* | cygwin* | pw32* | os2*)
+      # This hack is so that the source file can tell whether it is being
+      # built for inclusion in a dll (and should export symbols for example).
+      # Although the cygwin gcc ignores -fPIC, still need this for old-style
+      # (--disable-auto-import) libraries
+      lt_prog_compiler_pic='-DDLL_EXPORT'
+      ;;
+
+    darwin* | rhapsody*)
+      # PIC is the default on this platform
+      # Common symbols not allowed in MH_DYLIB files
+      lt_prog_compiler_pic='-fno-common'
+      ;;
+
+    hpux*)
+      # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but
+      # not for PA HP-UX.
+      case $host_cpu in
+      hppa*64*|ia64*)
+	# +Z the default
+	;;
+      *)
+	lt_prog_compiler_pic='-fPIC'
+	;;
+      esac
+      ;;
+
+    interix[3-9]*)
+      # Interix 3.x gcc -fpic/-fPIC options generate broken code.
+      # Instead, we relocate shared libraries at runtime.
+      ;;
+
+    msdosdjgpp*)
+      # Just because we use GCC doesn't mean we suddenly get shared libraries
+      # on systems that don't support them.
+      lt_prog_compiler_can_build_shared=no
+      enable_shared=no
+      ;;
+
+    *nto* | *qnx*)
+      # QNX uses GNU C++, but need to define -shared option too, otherwise
+      # it will coredump.
+      lt_prog_compiler_pic='-fPIC -shared'
+      ;;
+
+    sysv4*MP*)
+      if test -d /usr/nec; then
+	lt_prog_compiler_pic=-Kconform_pic
+      fi
+      ;;
+
+    *)
+      lt_prog_compiler_pic='-fPIC'
+      ;;
+    esac
+  else
+    # PORTME Check for flag to pass linker flags through the system compiler.
+    case $host_os in
+    aix*)
+      lt_prog_compiler_wl='-Wl,'
+      if test "$host_cpu" = ia64; then
+	# AIX 5 now supports IA64 processor
+	lt_prog_compiler_static='-Bstatic'
+      else
+	lt_prog_compiler_static='-bnso -bI:/lib/syscalls.exp'
+      fi
+      ;;
+    darwin*)
+      # PIC is the default on this platform
+      # Common symbols not allowed in MH_DYLIB files
+      case $cc_basename in
+      xlc*)
+        lt_prog_compiler_pic='-qnocommon'
+        lt_prog_compiler_wl='-Wl,'
+        ;;
+      esac
+      ;;
+
+    mingw* | cygwin* | pw32* | os2*)
+      # This hack is so that the source file can tell whether it is being
+      # built for inclusion in a dll (and should export symbols for example).
+      lt_prog_compiler_pic='-DDLL_EXPORT'
+      ;;
+
+    hpux9* | hpux10* | hpux11*)
+      lt_prog_compiler_wl='-Wl,'
+      # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but
+      # not for PA HP-UX.
+      case $host_cpu in
+      hppa*64*|ia64*)
+	# +Z the default
+	;;
+      *)
+	lt_prog_compiler_pic='+Z'
+	;;
+      esac
+      # Is there a better lt_prog_compiler_static that works with the bundled CC?
+      lt_prog_compiler_static='${wl}-a ${wl}archive'
+      ;;
+
+    irix5* | irix6* | nonstopux*)
+      lt_prog_compiler_wl='-Wl,'
+      # PIC (with -KPIC) is the default.
+      lt_prog_compiler_static='-non_shared'
+      ;;
+
+    linux* | k*bsd*-gnu)
+      case $cc_basename in
+      icc* | ecc*)
+	lt_prog_compiler_wl='-Wl,'
+	lt_prog_compiler_pic='-KPIC'
+	lt_prog_compiler_static='-static'
+        ;;
+      pgcc* | pgf77* | pgf90* | pgf95*)
+        # Portland Group compilers (*not* the Pentium gcc compiler,
+	# which looks to be a dead project)
+	lt_prog_compiler_wl='-Wl,'
+	lt_prog_compiler_pic='-fpic'
+	lt_prog_compiler_static='-Bstatic'
+        ;;
+      ccc*)
+        lt_prog_compiler_wl='-Wl,'
+        # All Alpha code is PIC.
+        lt_prog_compiler_static='-non_shared'
+        ;;
+      *)
+	case `$CC -V 2>&1 | sed 5q` in
+	*Sun\ C*)
+	  # Sun C 5.9
+	  lt_prog_compiler_pic='-KPIC'
+	  lt_prog_compiler_static='-Bstatic'
+	  lt_prog_compiler_wl='-Wl,'
+	  ;;
+	*Sun\ F*)
+	  # Sun Fortran 8.3 passes all unrecognized flags to the linker
+	  lt_prog_compiler_pic='-KPIC'
+	  lt_prog_compiler_static='-Bstatic'
+	  lt_prog_compiler_wl=''
+	  ;;
+	esac
+	;;
+      esac
+      ;;
+
+    newsos6)
+      lt_prog_compiler_pic='-KPIC'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    *nto* | *qnx*)
+      # QNX uses GNU C++, but need to define -shared option too, otherwise
+      # it will coredump.
+      lt_prog_compiler_pic='-fPIC -shared'
+      ;;
+
+    osf3* | osf4* | osf5*)
+      lt_prog_compiler_wl='-Wl,'
+      # All OSF/1 code is PIC.
+      lt_prog_compiler_static='-non_shared'
+      ;;
+
+    rdos*)
+      lt_prog_compiler_static='-non_shared'
+      ;;
+
+    solaris*)
+      lt_prog_compiler_pic='-KPIC'
+      lt_prog_compiler_static='-Bstatic'
+      case $cc_basename in
+      f77* | f90* | f95*)
+	lt_prog_compiler_wl='-Qoption ld ';;
+      *)
+	lt_prog_compiler_wl='-Wl,';;
+      esac
+      ;;
+
+    sunos4*)
+      lt_prog_compiler_wl='-Qoption ld '
+      lt_prog_compiler_pic='-PIC'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    sysv4 | sysv4.2uw2* | sysv4.3*)
+      lt_prog_compiler_wl='-Wl,'
+      lt_prog_compiler_pic='-KPIC'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    sysv4*MP*)
+      if test -d /usr/nec ;then
+	lt_prog_compiler_pic='-Kconform_pic'
+	lt_prog_compiler_static='-Bstatic'
+      fi
+      ;;
+
+    sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*)
+      lt_prog_compiler_wl='-Wl,'
+      lt_prog_compiler_pic='-KPIC'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    unicos*)
+      lt_prog_compiler_wl='-Wl,'
+      lt_prog_compiler_can_build_shared=no
+      ;;
+
+    uts4*)
+      lt_prog_compiler_pic='-pic'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    *)
+      lt_prog_compiler_can_build_shared=no
+      ;;
+    esac
+  fi
+
+case $host_os in
+  # For platforms which do not support PIC, -DPIC is meaningless:
+  *djgpp*)
+    lt_prog_compiler_pic=
+    ;;
+  *)
+    lt_prog_compiler_pic="$lt_prog_compiler_pic -DPIC"
+    ;;
+esac
+echo "$as_me:$LINENO: result: $lt_prog_compiler_pic" >&5
+echo "${ECHO_T}$lt_prog_compiler_pic" >&6
+
+
+
+
+
 
-# Save cache, so that ltconfig can load it
-cat >confcache <<\_ACEOF
-# This file is a shell script that caches the results of configure
-# tests run on this system so they can be shared between configure
-# scripts and configure runs, see configure's option --config-cache.
-# It is not useful on other systems.  If it contains results you don't
-# want to keep, you may remove or edit it.
 #
-# config.status only pays attention to the cache file if you give it
-# the --recheck option to rerun configure.
+# Check to make sure the PIC flag actually works.
 #
-# `ac_cv_env_foo' variables (set or unset) will be overridden when
-# loading this file, other *unset* `ac_cv_foo' will be assigned the
-# following values.
+if test -n "$lt_prog_compiler_pic"; then
+  echo "$as_me:$LINENO: checking if $compiler PIC flag $lt_prog_compiler_pic works" >&5
+echo $ECHO_N "checking if $compiler PIC flag $lt_prog_compiler_pic works... $ECHO_C" >&6
+if test "${lt_prog_compiler_pic_works+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_prog_compiler_pic_works=no
+   ac_outfile=conftest.$ac_objext
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+   lt_compiler_flag="$lt_prog_compiler_pic -DPIC"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   # The option is referenced via a variable to avoid confusing sed.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:6244: $lt_compile\"" >&5)
+   (eval "$lt_compile" 2>conftest.err)
+   ac_status=$?
+   cat conftest.err >&5
+   echo "$as_me:6248: \$? = $ac_status" >&5
+   if (exit $ac_status) && test -s "$ac_outfile"; then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings other than the usual output.
+     $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' >conftest.exp
+     $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
+     if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then
+       lt_prog_compiler_pic_works=yes
+     fi
+   fi
+   $RM conftest*
+
+fi
+echo "$as_me:$LINENO: result: $lt_prog_compiler_pic_works" >&5
+echo "${ECHO_T}$lt_prog_compiler_pic_works" >&6
+
+if test x"$lt_prog_compiler_pic_works" = xyes; then
+    case $lt_prog_compiler_pic in
+     "" | " "*) ;;
+     *) lt_prog_compiler_pic=" $lt_prog_compiler_pic" ;;
+     esac
+else
+    lt_prog_compiler_pic=
+     lt_prog_compiler_can_build_shared=no
+fi
+
+fi
+
+
+
+
+
+
+#
+# Check to make sure the static flag actually works.
+#
+wl=$lt_prog_compiler_wl eval lt_tmp_static_flag=\"$lt_prog_compiler_static\"
+echo "$as_me:$LINENO: checking if $compiler static flag $lt_tmp_static_flag works" >&5
+echo $ECHO_N "checking if $compiler static flag $lt_tmp_static_flag works... $ECHO_C" >&6
+if test "${lt_prog_compiler_static_works+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_prog_compiler_static_works=no
+   save_LDFLAGS="$LDFLAGS"
+   LDFLAGS="$LDFLAGS $lt_tmp_static_flag"
+   echo "$lt_simple_link_test_code" > conftest.$ac_ext
+   if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then
+     # The linker can only warn and ignore the option if not recognized
+     # So say no if there are warnings
+     if test -s conftest.err; then
+       # Append any errors to the config.log.
+       cat conftest.err 1>&5
+       $ECHO "X$_lt_linker_boilerplate" | $Xsed -e '/^$/d' > conftest.exp
+       $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
+       if diff conftest.exp conftest.er2 >/dev/null; then
+         lt_prog_compiler_static_works=yes
+       fi
+     else
+       lt_prog_compiler_static_works=yes
+     fi
+   fi
+   $RM conftest*
+   LDFLAGS="$save_LDFLAGS"
+
+fi
+echo "$as_me:$LINENO: result: $lt_prog_compiler_static_works" >&5
+echo "${ECHO_T}$lt_prog_compiler_static_works" >&6
+
+if test x"$lt_prog_compiler_static_works" = xyes; then
+    :
+else
+    lt_prog_compiler_static=
+fi
+
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking if $compiler supports -c -o file.$ac_objext" >&5
+echo $ECHO_N "checking if $compiler supports -c -o file.$ac_objext... $ECHO_C" >&6
+if test "${lt_cv_prog_compiler_c_o+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_prog_compiler_c_o=no
+   $RM -r conftest 2>/dev/null
+   mkdir conftest
+   cd conftest
+   mkdir out
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+
+   lt_compiler_flag="-o out/conftest2.$ac_objext"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:6349: $lt_compile\"" >&5)
+   (eval "$lt_compile" 2>out/conftest.err)
+   ac_status=$?
+   cat out/conftest.err >&5
+   echo "$as_me:6353: \$? = $ac_status" >&5
+   if (exit $ac_status) && test -s out/conftest2.$ac_objext
+   then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings
+     $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' > out/conftest.exp
+     $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2
+     if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then
+       lt_cv_prog_compiler_c_o=yes
+     fi
+   fi
+   chmod u+w . 2>&5
+   $RM conftest*
+   # SGI C++ compiler will create directory out/ii_files/ for
+   # template instantiation
+   test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files
+   $RM out/* && rmdir out
+   cd ..
+   $RM -r conftest
+   $RM conftest*
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_c_o" >&5
+echo "${ECHO_T}$lt_cv_prog_compiler_c_o" >&6
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking if $compiler supports -c -o file.$ac_objext" >&5
+echo $ECHO_N "checking if $compiler supports -c -o file.$ac_objext... $ECHO_C" >&6
+if test "${lt_cv_prog_compiler_c_o+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_prog_compiler_c_o=no
+   $RM -r conftest 2>/dev/null
+   mkdir conftest
+   cd conftest
+   mkdir out
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+
+   lt_compiler_flag="-o out/conftest2.$ac_objext"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:6404: $lt_compile\"" >&5)
+   (eval "$lt_compile" 2>out/conftest.err)
+   ac_status=$?
+   cat out/conftest.err >&5
+   echo "$as_me:6408: \$? = $ac_status" >&5
+   if (exit $ac_status) && test -s out/conftest2.$ac_objext
+   then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings
+     $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' > out/conftest.exp
+     $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2
+     if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then
+       lt_cv_prog_compiler_c_o=yes
+     fi
+   fi
+   chmod u+w . 2>&5
+   $RM conftest*
+   # SGI C++ compiler will create directory out/ii_files/ for
+   # template instantiation
+   test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files
+   $RM out/* && rmdir out
+   cd ..
+   $RM -r conftest
+   $RM conftest*
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_c_o" >&5
+echo "${ECHO_T}$lt_cv_prog_compiler_c_o" >&6
+
+
+
+
+hard_links="nottested"
+if test "$lt_cv_prog_compiler_c_o" = no && test "$need_locks" != no; then
+  # do not overwrite the value of need_locks provided by the user
+  echo "$as_me:$LINENO: checking if we can lock with hard links" >&5
+echo $ECHO_N "checking if we can lock with hard links... $ECHO_C" >&6
+  hard_links=yes
+  $RM conftest*
+  ln conftest.a conftest.b 2>/dev/null && hard_links=no
+  touch conftest.a
+  ln conftest.a conftest.b 2>&5 || hard_links=no
+  ln conftest.a conftest.b 2>/dev/null && hard_links=no
+  echo "$as_me:$LINENO: result: $hard_links" >&5
+echo "${ECHO_T}$hard_links" >&6
+  if test "$hard_links" = no; then
+    { echo "$as_me:$LINENO: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&5
+echo "$as_me: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&2;}
+    need_locks=warn
+  fi
+else
+  need_locks=no
+fi
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking whether the $compiler linker ($LD) supports shared libraries" >&5
+echo $ECHO_N "checking whether the $compiler linker ($LD) supports shared libraries... $ECHO_C" >&6
+
+  runpath_var=
+  allow_undefined_flag=
+  always_export_symbols=no
+  archive_cmds=
+  archive_expsym_cmds=
+  compiler_needs_object=no
+  enable_shared_with_static_runtimes=no
+  export_dynamic_flag_spec=
+  export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols'
+  hardcode_automatic=no
+  hardcode_direct=no
+  hardcode_direct_absolute=no
+  hardcode_libdir_flag_spec=
+  hardcode_libdir_flag_spec_ld=
+  hardcode_libdir_separator=
+  hardcode_minus_L=no
+  hardcode_shlibpath_var=unsupported
+  inherit_rpath=no
+  link_all_deplibs=unknown
+  module_cmds=
+  module_expsym_cmds=
+  old_archive_from_new_cmds=
+  old_archive_from_expsyms_cmds=
+  thread_safe_flag_spec=
+  whole_archive_flag_spec=
+  # include_expsyms should be a list of space-separated symbols to be *always*
+  # included in the symbol list
+  include_expsyms=
+  # exclude_expsyms can be an extended regexp of symbols to exclude
+  # it will be wrapped by ` (' and `)$', so one must not match beginning or
+  # end of line.  Example: `a|bc|.*d.*' will exclude the symbols `a' and `bc',
+  # as well as any symbol that contains `d'.
+  exclude_expsyms="_GLOBAL_OFFSET_TABLE_"
+  # Although _GLOBAL_OFFSET_TABLE_ is a valid symbol C name, most a.out
+  # platforms (ab)use it in PIC code, but their linkers get confused if
+  # the symbol is explicitly referenced.  Since portable code cannot
+  # rely on this symbol name, it's probably fine to never include it in
+  # preloaded symbol tables.
+  extract_expsyms_cmds=
+
+  case $host_os in
+  cygwin* | mingw* | pw32*)
+    # FIXME: the MSVC++ port hasn't been tested in a loooong time
+    # When not using gcc, we currently assume that we are using
+    # Microsoft Visual C++.
+    if test "$GCC" != yes; then
+      with_gnu_ld=no
+    fi
+    ;;
+  interix*)
+    # we just hope/assume this is gcc and not c89 (= MSVC++)
+    with_gnu_ld=yes
+    ;;
+  openbsd*)
+    with_gnu_ld=no
+    ;;
+  esac
+
+  ld_shlibs=yes
+  if test "$with_gnu_ld" = yes; then
+    # If archive_cmds runs LD, not CC, wlarc should be empty
+    wlarc='${wl}'
+
+    # Set some defaults for GNU ld with shared library support. These
+    # are reset later if shared libraries are not supported. Putting them
+    # here allows them to be overridden if necessary.
+    runpath_var=LD_RUN_PATH
+    hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+    export_dynamic_flag_spec='${wl}--export-dynamic'
+    # ancient GNU ld didn't support --whole-archive et. al.
+    if $LD --help 2>&1 | $GREP 'no-whole-archive' > /dev/null; then
+      whole_archive_flag_spec="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive'
+    else
+      whole_archive_flag_spec=
+    fi
+    supports_anon_versioning=no
+    case `$LD -v 2>&1` in
+      *\ [01].* | *\ 2.[0-9].* | *\ 2.10.*) ;; # catch versions < 2.11
+      *\ 2.11.93.0.2\ *) supports_anon_versioning=yes ;; # RH7.3 ...
+      *\ 2.11.92.0.12\ *) supports_anon_versioning=yes ;; # Mandrake 8.2 ...
+      *\ 2.11.*) ;; # other 2.11 versions
+      *) supports_anon_versioning=yes ;;
+    esac
+
+    # See if GNU ld supports shared libraries.
+    case $host_os in
+    aix3* | aix4* | aix5*)
+      # On AIX/PPC, the GNU linker is very broken
+      if test "$host_cpu" != ia64; then
+	ld_shlibs=no
+	cat <<_LT_EOF 1>&2
+
+*** Warning: the GNU linker, at least up to release 2.9.1, is reported
+*** to be unable to reliably create shared libraries on AIX.
+*** Therefore, libtool is disabling shared libraries support.  If you
+*** really care for shared libraries, you may want to modify your PATH
+*** so that a non-GNU linker is found, and then restart.
+
+_LT_EOF
+      fi
+      ;;
+
+    amigaos*)
+      if test "$host_cpu" = m68k; then
+        archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
+        hardcode_libdir_flag_spec='-L$libdir'
+        hardcode_minus_L=yes
+      fi
+
+      # Samuel A. Falvo II <kc5tja@dolphin.openprojects.net> reports
+      # that the semantics of dynamic libraries on AmigaOS, at least up
+      # to version 4, is to share data among multiple programs linked
+      # with the same dynamic library.  Since this doesn't match the
+      # behavior of shared libraries on other platforms, we can't use
+      # them.
+      ld_shlibs=no
+      ;;
+
+    beos*)
+      if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	allow_undefined_flag=unsupported
+	# Joseph Beckenbach <jrb3@best.com> says some releases of gcc
+	# support --undefined.  This deserves some investigation.  FIXME
+	archive_cmds='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+      else
+	ld_shlibs=no
+      fi
+      ;;
+
+    cygwin* | mingw* | pw32*)
+      # _LT_TAGVAR(hardcode_libdir_flag_spec, ) is actually meaningless,
+      # as there is no search path for DLLs.
+      hardcode_libdir_flag_spec='-L$libdir'
+      allow_undefined_flag=unsupported
+      always_export_symbols=no
+      enable_shared_with_static_runtimes=yes
+      export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1 DATA/'\'' | $SED -e '\''/^[AITW][ ]/s/.*[ ]//'\'' | sort | uniq > $export_symbols'
+
+      if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then
+        archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
+	# If the export-symbols file already is a .def file (1st line
+	# is EXPORTS), use it as is; otherwise, prepend...
+	archive_expsym_cmds='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then
+	  cp $export_symbols $output_objdir/$soname.def;
+	else
+	  echo EXPORTS > $output_objdir/$soname.def;
+	  cat $export_symbols >> $output_objdir/$soname.def;
+	fi~
+	$CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
+      else
+	ld_shlibs=no
+      fi
+      ;;
+
+    interix[3-9]*)
+      hardcode_direct=no
+      hardcode_shlibpath_var=no
+      hardcode_libdir_flag_spec='${wl}-rpath,$libdir'
+      export_dynamic_flag_spec='${wl}-E'
+      # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc.
+      # Instead, shared libraries are loaded at an image base (0x10000000 by
+      # default) and relocated if they conflict, which is a slow very memory
+      # consuming and fragmenting process.  To avoid this, we pick a random,
+      # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link
+      # time.  Moving up from 0x10000000 also allows more sbrk(2) space.
+      archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
+      archive_expsym_cmds='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
+      ;;
+
+    gnu* | linux* | tpf* | k*bsd*-gnu)
+      tmp_diet=no
+      if test "$host_os" = linux-dietlibc; then
+	case $cc_basename in
+	  diet\ *) tmp_diet=yes;;	# linux-dietlibc with static linking (!diet-dyn)
+	esac
+      fi
+      if $LD --help 2>&1 | $EGREP ': supported targets:.* elf' > /dev/null \
+	 && test "$tmp_diet" = no
+      then
+	tmp_addflag=
+	case $cc_basename,$host_cpu in
+        pgcc*)				# Portland Group C compiler
+	  whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $ECHO \"$new_convenience\"` ${wl}--no-whole-archive'
+	  tmp_addflag=' $pic_flag'
+	  ;;
+	pgf77* | pgf90* | pgf95*)	# Portland Group f77 and f90 compilers
+	  whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $ECHO \"$new_convenience\"` ${wl}--no-whole-archive'
+	  tmp_addflag=' $pic_flag -Mnomain' ;;
+	ecc*,ia64* | icc*,ia64*)	# Intel C compiler on ia64
+	  tmp_addflag=' -i_dynamic' ;;
+	efc*,ia64* | ifort*,ia64*)	# Intel Fortran compiler on ia64
+	  tmp_addflag=' -i_dynamic -nofor_main' ;;
+	ifc* | ifort*)			# Intel Fortran compiler
+	  tmp_addflag=' -nofor_main' ;;
+	esac
+	case `$CC -V 2>&1 | sed 5q` in
+	*Sun\ C*)			# Sun C 5.9
+	  whole_archive_flag_spec='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; $ECHO \"$new_convenience\"` ${wl}--no-whole-archive'
+	  compiler_needs_object=yes
+	  tmp_sharedflag='-G' ;;
+	*Sun\ F*)			# Sun Fortran 8.3
+	  tmp_sharedflag='-G' ;;
+	*)
+	  tmp_sharedflag='-shared' ;;
+	esac
+	archive_cmds='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+
+        if test "x$supports_anon_versioning" = xyes; then
+          archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~
+	    cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~
+	    echo "local: *; };" >> $output_objdir/$libname.ver~
+	    $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib'
+        fi
+      else
+        ld_shlibs=no
+      fi
+      ;;
+
+    netbsd*)
+      if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+	archive_cmds='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib'
+	wlarc=
+      else
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+      fi
+      ;;
+
+    solaris*)
+      if $LD -v 2>&1 | $GREP 'BFD 2\.8' > /dev/null; then
+	ld_shlibs=no
+	cat <<_LT_EOF 1>&2
+
+*** Warning: The releases 2.8.* of the GNU linker cannot reliably
+*** create shared libraries on Solaris systems.  Therefore, libtool
+*** is disabling shared libraries support.  We urge you to upgrade GNU
+*** binutils to release 2.9.1 or newer.  Another option is to modify
+*** your PATH or compiler configuration so that the native linker is
+*** used, and then restart.
+
+_LT_EOF
+      elif $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+      else
+	ld_shlibs=no
+      fi
+      ;;
+
+    sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*)
+      case `$LD -v 2>&1` in
+        *\ [01].* | *\ 2.[0-9].* | *\ 2.1[0-5].*)
+	ld_shlibs=no
+	cat <<_LT_EOF 1>&2
+
+*** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not
+*** reliably create shared libraries on SCO systems.  Therefore, libtool
+*** is disabling shared libraries support.  We urge you to upgrade GNU
+*** binutils to release 2.16.91.0.3 or newer.  Another option is to modify
+*** your PATH or compiler configuration so that the native linker is
+*** used, and then restart.
+
+_LT_EOF
+	;;
+	*)
+	  # For security reasons, it is highly recommended that you always
+	  # use absolute paths for naming shared libraries, and exclude the
+	  # DT_RUNPATH tag from executables and libraries.  But doing so
+	  # requires that you compile everything twice, which is a pain.
+	  if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	    hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+	    archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	    archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+	  else
+	    ld_shlibs=no
+	  fi
+	;;
+      esac
+      ;;
+
+    sunos4*)
+      archive_cmds='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags'
+      wlarc=
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    *)
+      if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+      else
+	ld_shlibs=no
+      fi
+      ;;
+    esac
+
+    if test "$ld_shlibs" = no; then
+      runpath_var=
+      hardcode_libdir_flag_spec=
+      export_dynamic_flag_spec=
+      whole_archive_flag_spec=
+    fi
+  else
+    # PORTME fill in a description of your system's linker (not GNU ld)
+    case $host_os in
+    aix3*)
+      allow_undefined_flag=unsupported
+      always_export_symbols=yes
+      archive_expsym_cmds='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname'
+      # Note: this linker hardcodes the directories in LIBPATH if there
+      # are no directories specified by -L.
+      hardcode_minus_L=yes
+      if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then
+	# Neither direct hardcoding nor static linking is supported with a
+	# broken collect2.
+	hardcode_direct=unsupported
+      fi
+      ;;
+
+    aix4* | aix5*)
+      if test "$host_cpu" = ia64; then
+	# On IA64, the linker does run time linking by default, so we don't
+	# have to do anything special.
+	aix_use_runtimelinking=no
+	exp_sym_flag='-Bexport'
+	no_entry_flag=""
+      else
+	# If we're using GNU nm, then we don't want the "-C" option.
+	# -C means demangle to AIX nm, but means don't demangle with GNU nm
+	if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then
+	  export_symbols_cmds='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+	else
+	  export_symbols_cmds='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+	fi
+	aix_use_runtimelinking=no
+
+	# Test if we are trying to use run time linking or normal
+	# AIX style linking. If -brtl is somewhere in LDFLAGS, we
+	# need to do runtime linking.
+	case $host_os in aix4.[23]|aix4.[23].*|aix5*)
+	  for ld_flag in $LDFLAGS; do
+	  if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then
+	    aix_use_runtimelinking=yes
+	    break
+	  fi
+	  done
+	  ;;
+	esac
+
+	exp_sym_flag='-bexport'
+	no_entry_flag='-bnoentry'
+      fi
+
+      # When large executables or shared objects are built, AIX ld can
+      # have problems creating the table of contents.  If linking a library
+      # or program results in "error TOC overflow" add -mminimal-toc to
+      # CXXFLAGS/CFLAGS for g++/gcc.  In the cases where that is not
+      # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS.
+
+      archive_cmds=''
+      hardcode_direct=yes
+      hardcode_direct_absolute=yes
+      hardcode_libdir_separator=':'
+      link_all_deplibs=yes
+      file_list_spec='${wl}-f,'
+
+      if test "$GCC" = yes; then
+	case $host_os in aix4.[012]|aix4.[012].*)
+	# We only want to do this on AIX 4.2 and lower, the check
+	# below for broken collect2 doesn't work under 4.3+
+	  collect2name=`${CC} -print-prog-name=collect2`
+	  if test -f "$collect2name" &&
+	   strings "$collect2name" | $GREP resolve_lib_name >/dev/null
+	  then
+	  # We have reworked collect2
+	  :
+	  else
+	  # We have old collect2
+	  hardcode_direct=unsupported
+	  # It fails to find uninstalled libraries when the uninstalled
+	  # path is not listed in the libpath.  Setting hardcode_minus_L
+	  # to unsupported forces relinking
+	  hardcode_minus_L=yes
+	  hardcode_libdir_flag_spec='-L$libdir'
+	  hardcode_libdir_separator=
+	  fi
+	  ;;
+	esac
+	shared_flag='-shared'
+	if test "$aix_use_runtimelinking" = yes; then
+	  shared_flag="$shared_flag "'${wl}-G'
+	fi
+      else
+	# not using gcc
+	if test "$host_cpu" = ia64; then
+	# VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release
+	# chokes on -Wl,-G. The following line is correct:
+	  shared_flag='-G'
+	else
+	  if test "$aix_use_runtimelinking" = yes; then
+	    shared_flag='${wl}-G'
+	  else
+	    shared_flag='${wl}-bM:SRE'
+	  fi
+	fi
+      fi
 
+      # It seems that -bexpall does not export symbols beginning with
+      # underscore (_), so it is better to generate a list of symbols to export.
+      always_export_symbols=yes
+      if test "$aix_use_runtimelinking" = yes; then
+	# Warning - without using the other runtime loading flags (-brtl),
+	# -berok will link without error, but may produce a broken library.
+	allow_undefined_flag='-berok'
+        # Determine the default libpath from the value encoded in an
+        # empty executable.
+        cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
 _ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
 
-# The following way of writing the cache mishandles newlines in values,
-# but we know of no workaround that is simple, portable, and efficient.
-# So, don't put newlines in cache variables' values.
-# Ultrix sh set writes to stderr and can't be redirected directly,
-# and sets the high bit in the cache file unless we assign to the vars.
+int
+main ()
 {
-  (set) 2>&1 |
-    case `(ac_space=' '; set | grep ac_space) 2>&1` in
-    *ac_space=\ *)
-      # `set' does not quote correctly, so add quotes (double-quote
-      # substitution turns \\\\ into \\, and sed turns \\ into \).
-      sed -n \
-	"s/'/'\\\\''/g;
-	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+
+lt_aix_libpath_sed='
+    /Import File Strings/,/^$/ {
+	/^0/ {
+	    s/^0  *\(.*\)$/\1/
+	    p
+	}
+    }'
+aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+# Check for a 64-bit object if we didn't find anything.
+if test -z "$aix_libpath"; then
+  aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+fi
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi
+
+        hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath"
+        archive_expsym_cmds='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then $ECHO "X${wl}${allow_undefined_flag}" | $Xsed; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag"
+      else
+	if test "$host_cpu" = ia64; then
+	  hardcode_libdir_flag_spec='${wl}-R $libdir:/usr/lib:/lib'
+	  allow_undefined_flag="-z nodefs"
+	  archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols"
+	else
+	 # Determine the default libpath from the value encoded in an
+	 # empty executable.
+	 cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+
+lt_aix_libpath_sed='
+    /Import File Strings/,/^$/ {
+	/^0/ {
+	    s/^0  *\(.*\)$/\1/
+	    p
+	}
+    }'
+aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+# Check for a 64-bit object if we didn't find anything.
+if test -z "$aix_libpath"; then
+  aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+fi
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi
+
+	 hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath"
+	  # Warning - without using the other run time loading flags,
+	  # -berok will link without error, but may produce a broken library.
+	  no_undefined_flag=' ${wl}-bernotok'
+	  allow_undefined_flag=' ${wl}-berok'
+	  # Exported symbols can be pulled into shared objects from archives
+	  whole_archive_flag_spec='$convenience'
+	  archive_cmds_need_lc=yes
+	  # This is similar to how AIX traditionally builds its shared libraries.
+	  archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname'
+	fi
+      fi
+      ;;
+
+    amigaos*)
+      if test "$host_cpu" = m68k; then
+        archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
+        hardcode_libdir_flag_spec='-L$libdir'
+        hardcode_minus_L=yes
+      fi
+      # see comment about different semantics on the GNU ld section
+      ld_shlibs=no
+      ;;
+
+    bsdi[45]*)
+      export_dynamic_flag_spec=-rdynamic
+      ;;
+
+    cygwin* | mingw* | pw32*)
+      # When not using gcc, we currently assume that we are using
+      # Microsoft Visual C++.
+      # hardcode_libdir_flag_spec is actually meaningless, as there is
+      # no search path for DLLs.
+      hardcode_libdir_flag_spec=' '
+      allow_undefined_flag=unsupported
+      # Tell ltmain to make .lib files, not .a files.
+      libext=lib
+      # Tell ltmain to make .dll files, not .so files.
+      shrext_cmds=".dll"
+      # FIXME: Setting linknames here is a bad hack.
+      archive_cmds='$CC -o $lib $libobjs $compiler_flags `$ECHO "X$deplibs" | $Xsed -e '\''s/ -lc$//'\''` -link -dll~linknames='
+      # The linker will automatically build a .lib file if we build a DLL.
+      old_archive_from_new_cmds='true'
+      # FIXME: Should let the user specify the lib program.
+      old_archive_cmds='lib -OUT:$oldlib$oldobjs$old_deplibs'
+      fix_srcfile_path='`cygpath -w "$srcfile"`'
+      enable_shared_with_static_runtimes=yes
+      ;;
+
+    darwin* | rhapsody*)
+      case $host_os in
+      rhapsody* | darwin1.[012])
+	allow_undefined_flag='${wl}-undefined ${wl}suppress'
+	;;
+      *) # Darwin 1.3 on
+	case ${MACOSX_DEPLOYMENT_TARGET-10.0} in
+	10.[012])
+	  allow_undefined_flag='${wl}-flat_namespace ${wl}-undefined ${wl}suppress'
+	  ;;
+	10.*)
+	  allow_undefined_flag='${wl}-undefined ${wl}dynamic_lookup'
+	  ;;
+	esac
+	;;
+      esac
+      archive_cmds_need_lc=no
+      hardcode_direct=no
+      hardcode_automatic=yes
+      hardcode_shlibpath_var=unsupported
+      whole_archive_flag_spec=''
+      link_all_deplibs=yes
+      if test "$GCC" = yes ; then
+	if test "${lt_cv_apple_cc_single_mod+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_apple_cc_single_mod=no
+	if test -z "${LT_MULTI_MODULE}"; then
+	  # By default we will add the -single_module flag. You can override
+	  # by either setting the environment variable LT_MULTI_MODULE
+	  # non-empty at configure time, or by adding -multi-module to the
+	  # link flags.
+	  echo "int foo(void){return 1;}" > conftest.c
+	  $LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \
+	      -dynamiclib ${wl}-single_module conftest.c
+	  if test -f libconftest.dylib; then
+	      lt_cv_apple_cc_single_mod=yes
+	      rm libconftest.dylib
+	  fi
+	  rm conftest.$ac_ext
+	fi
+fi
+
+	output_verbose_link_cmd=echo
+	if test "X$lt_cv_apple_cc_single_mod" = Xyes ; then
+	  archive_cmds='$CC -dynamiclib $single_module $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring'
+	  archive_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $single_module -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+	else
+	  archive_cmds='$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring'
+	  archive_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+	fi
+	module_cmds='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags'
+	module_expsym_cmds='sed -e "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag  -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+      else
+	case $cc_basename in
+	xlc*)
+	  output_verbose_link_cmd=echo
+	  archive_cmds='$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}`$ECHO $rpath/$soname` $verstring'
+	  module_cmds='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags'
+	  # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds
+	  archive_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}$rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+	  module_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag  -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+	  ;;
+	*)
+	  ld_shlibs=no
+	  ;;
+	esac
+      fi
+      ;;
+
+    dgux*)
+      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_libdir_flag_spec='-L$libdir'
+      hardcode_shlibpath_var=no
+      ;;
+
+    freebsd1*)
+      ld_shlibs=no
+      ;;
+
+    # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor
+    # support.  Future versions do this automatically, but an explicit c++rt0.o
+    # does not break anything, and helps significantly (at the cost of a little
+    # extra space).
+    freebsd2.2*)
+      archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o'
+      hardcode_libdir_flag_spec='-R$libdir'
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    # Unfortunately, older versions of FreeBSD 2 do not have this feature.
+    freebsd2*)
+      archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_direct=yes
+      hardcode_minus_L=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    # FreeBSD 3 and greater uses gcc -shared to do shared libraries.
+    freebsd* | dragonfly*)
+      archive_cmds='$CC -shared -o $lib $libobjs $deplibs $compiler_flags'
+      hardcode_libdir_flag_spec='-R$libdir'
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    hpux9*)
+      if test "$GCC" = yes; then
+	archive_cmds='$RM $output_objdir/$soname~$CC -shared -fPIC ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
+      else
+	archive_cmds='$RM $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
+      fi
+      hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
+      hardcode_libdir_separator=:
+      hardcode_direct=yes
+
+      # hardcode_minus_L: Not really in the search PATH,
+      # but as the default location of the library.
+      hardcode_minus_L=yes
+      export_dynamic_flag_spec='${wl}-E'
+      ;;
+
+    hpux10*)
+      if test "$GCC" = yes -a "$with_gnu_ld" = no; then
+	archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags'
+      fi
+      if test "$with_gnu_ld" = no; then
+	hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
+	hardcode_libdir_flag_spec_ld='+b $libdir'
+	hardcode_libdir_separator=:
+	hardcode_direct=yes
+	hardcode_direct_absolute=yes
+	export_dynamic_flag_spec='${wl}-E'
+	# hardcode_minus_L: Not really in the search PATH,
+	# but as the default location of the library.
+	hardcode_minus_L=yes
+      fi
+      ;;
+
+    hpux11*)
+      if test "$GCC" = yes -a "$with_gnu_ld" = no; then
+	case $host_cpu in
+	hppa*64*)
+	  archive_cmds='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	ia64*)
+	  archive_cmds='$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	*)
+	  archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	esac
+      else
+	case $host_cpu in
+	hppa*64*)
+	  archive_cmds='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	ia64*)
+	  archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	*)
+	  archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	esac
+      fi
+      if test "$with_gnu_ld" = no; then
+	hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
+	hardcode_libdir_separator=:
+
+	case $host_cpu in
+	hppa*64*|ia64*)
+	  hardcode_direct=no
+	  hardcode_shlibpath_var=no
+	  ;;
+	*)
+	  hardcode_direct=yes
+	  hardcode_direct_absolute=yes
+	  export_dynamic_flag_spec='${wl}-E'
+
+	  # hardcode_minus_L: Not really in the search PATH,
+	  # but as the default location of the library.
+	  hardcode_minus_L=yes
+	  ;;
+	esac
+      fi
+      ;;
+
+    irix5* | irix6* | nonstopux*)
+      if test "$GCC" = yes; then
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+	# Try to use the -exported_symbol ld option, if it does not
+	# work, assume that -exports_file does not work either and
+	# implicitly export all symbols.
+        save_LDFLAGS="$LDFLAGS"
+        LDFLAGS="$LDFLAGS -shared ${wl}-exported_symbol ${wl}foo ${wl}-update_registry ${wl}/dev/null"
+        cat >conftest.$ac_ext <<_ACEOF
+int foo(void) {}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations ${wl}-exports_file ${wl}$export_symbols -o $lib'
+
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+        LDFLAGS="$save_LDFLAGS"
+      else
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib'
+	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -exports_file $export_symbols -o $lib'
+      fi
+      archive_cmds_need_lc='no'
+      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+      hardcode_libdir_separator=:
+      inherit_rpath=yes
+      link_all_deplibs=yes
+      ;;
+
+    netbsd*)
+      if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+	archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'  # a.out
+      else
+	archive_cmds='$LD -shared -o $lib $libobjs $deplibs $linker_flags'      # ELF
+      fi
+      hardcode_libdir_flag_spec='-R$libdir'
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    newsos6)
+      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_direct=yes
+      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+      hardcode_libdir_separator=:
+      hardcode_shlibpath_var=no
+      ;;
+
+    *nto* | *qnx*)
+      ;;
+
+    openbsd*)
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      hardcode_direct_absolute=yes
+      if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+	archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols'
+	hardcode_libdir_flag_spec='${wl}-rpath,$libdir'
+	export_dynamic_flag_spec='${wl}-E'
+      else
+        case $host_os in
+	openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*)
+	  archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
+	  hardcode_libdir_flag_spec='-R$libdir'
+	  ;;
+	*)
+	  archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags'
+	  hardcode_libdir_flag_spec='${wl}-rpath,$libdir'
+	  ;;
+        esac
+      fi
+      ;;
+
+    os2*)
+      hardcode_libdir_flag_spec='-L$libdir'
+      hardcode_minus_L=yes
+      allow_undefined_flag=unsupported
+      archive_cmds='$ECHO "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$ECHO "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~$ECHO DATA >> $output_objdir/$libname.def~$ECHO " SINGLE NONSHARED" >> $output_objdir/$libname.def~$ECHO EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def'
+      old_archive_from_new_cmds='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def'
+      ;;
+
+    osf3*)
+      if test "$GCC" = yes; then
+	allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*'
+	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+      else
+	allow_undefined_flag=' -expect_unresolved \*'
+	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib'
+      fi
+      archive_cmds_need_lc='no'
+      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+      hardcode_libdir_separator=:
       ;;
+
+    osf4* | osf5*)	# as osf3* with the addition of -msym flag
+      if test "$GCC" = yes; then
+	allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*'
+	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+	hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+      else
+	allow_undefined_flag=' -expect_unresolved \*'
+	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -msym -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib'
+	archive_expsym_cmds='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; printf "%s\\n" "-hidden">> $lib.exp~
+	$CC -shared${allow_undefined_flag} ${wl}-input ${wl}$lib.exp $compiler_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib~$RM $lib.exp'
+
+	# Both c and cxx compiler support -rpath directly
+	hardcode_libdir_flag_spec='-rpath $libdir'
+      fi
+      archive_cmds_need_lc='no'
+      hardcode_libdir_separator=:
+      ;;
+
+    solaris*)
+      no_undefined_flag=' -z defs'
+      if test "$GCC" = yes; then
+	wlarc='${wl}'
+	archive_cmds='$CC -shared ${wl}-z ${wl}text ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	  $CC -shared ${wl}-z ${wl}text ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp'
+      else
+	case `$CC -V 2>&1` in
+	*"Compilers 5.0"*)
+	  wlarc=''
+	  archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	  archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	  $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$RM $lib.exp'
+	  ;;
+	*)
+	  wlarc='${wl}'
+	  archive_cmds='$CC -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $compiler_flags'
+	  archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	  $CC -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp'
+	  ;;
+	esac
+      fi
+      hardcode_libdir_flag_spec='-R$libdir'
+      hardcode_shlibpath_var=no
+      case $host_os in
+      solaris2.[0-5] | solaris2.[0-5].*) ;;
+      *)
+	# The compiler driver will combine and reorder linker options,
+	# but understands `-z linker_flag'.  GCC discards it without `$wl',
+	# but is careful enough not to reorder.
+	# Supported since Solaris 2.6 (maybe 2.5.1?)
+	if test "$GCC" = yes; then
+	  whole_archive_flag_spec='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract'
+	else
+	  whole_archive_flag_spec='-z allextract$convenience -z defaultextract'
+	fi
+	;;
+      esac
+      link_all_deplibs=yes
+      ;;
+
+    sunos4*)
+      if test "x$host_vendor" = xsequent; then
+	# Use $CC to link under sequent, because it throws in some extra .o
+	# files that make .init and .fini sections work.
+	archive_cmds='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	archive_cmds='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags'
+      fi
+      hardcode_libdir_flag_spec='-L$libdir'
+      hardcode_direct=yes
+      hardcode_minus_L=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    sysv4)
+      case $host_vendor in
+	sni)
+	  archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	  hardcode_direct=yes # is this really true???
+	;;
+	siemens)
+	  ## LD is ld it makes a PLAMLIB
+	  ## CC just makes a GrossModule.
+	  archive_cmds='$LD -G -o $lib $libobjs $deplibs $linker_flags'
+	  reload_cmds='$CC -r -o $output$reload_objs'
+	  hardcode_direct=no
+        ;;
+	motorola)
+	  archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	  hardcode_direct=no #Motorola manual says yes, but my tests say they lie
+	;;
+      esac
+      runpath_var='LD_RUN_PATH'
+      hardcode_shlibpath_var=no
+      ;;
+
+    sysv4.3*)
+      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_shlibpath_var=no
+      export_dynamic_flag_spec='-Bexport'
+      ;;
+
+    sysv4*MP*)
+      if test -d /usr/nec; then
+	archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	hardcode_shlibpath_var=no
+	runpath_var=LD_RUN_PATH
+	hardcode_runpath_var=yes
+	ld_shlibs=yes
+      fi
+      ;;
+
+    sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*)
+      no_undefined_flag='${wl}-z,text'
+      archive_cmds_need_lc=no
+      hardcode_shlibpath_var=no
+      runpath_var='LD_RUN_PATH'
+
+      if test "$GCC" = yes; then
+	archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      fi
+      ;;
+
+    sysv5* | sco3.2v5* | sco5v6*)
+      # Note: We can NOT use -z defs as we might desire, because we do not
+      # link with -lc, and that would cause any symbols used from libc to
+      # always be unresolved, which means just about no library would
+      # ever link correctly.  If we're not using GNU ld we use -z text
+      # though, which does catch some bad symbols but isn't as heavy-handed
+      # as -z defs.
+      no_undefined_flag='${wl}-z,text'
+      allow_undefined_flag='${wl}-z,nodefs'
+      archive_cmds_need_lc=no
+      hardcode_shlibpath_var=no
+      hardcode_libdir_flag_spec='${wl}-R,$libdir'
+      hardcode_libdir_separator=':'
+      link_all_deplibs=yes
+      export_dynamic_flag_spec='${wl}-Bexport'
+      runpath_var='LD_RUN_PATH'
+
+      if test "$GCC" = yes; then
+	archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      fi
+      ;;
+
+    uts4*)
+      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_libdir_flag_spec='-L$libdir'
+      hardcode_shlibpath_var=no
+      ;;
+
     *)
-      # `set' quotes correctly as required by POSIX, so do not add quotes.
-      sed -n \
-	"s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
+      ld_shlibs=no
       ;;
-    esac;
-} |
-  sed '
-     t clear
-     : clear
-     s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
-     t end
-     /^ac_cv_env/!s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
-     : end' >>confcache
-if diff $cache_file confcache >/dev/null 2>&1; then :; else
-  if test -w $cache_file; then
-    test "x$cache_file" != "x/dev/null" && echo "updating cache $cache_file"
-    cat confcache >$cache_file
+    esac
+
+    if test x$host_vendor = xsni; then
+      case $host in
+      sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*)
+	export_dynamic_flag_spec='${wl}-Blargedynsym'
+	;;
+      esac
+    fi
+  fi
+
+echo "$as_me:$LINENO: result: $ld_shlibs" >&5
+echo "${ECHO_T}$ld_shlibs" >&6
+test "$ld_shlibs" = no && can_build_shared=no
+
+with_gnu_ld=$with_gnu_ld
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#
+# Do we need to explicitly link libc?
+#
+case "x$archive_cmds_need_lc" in
+x|xyes)
+  # Assume -lc should be added
+  archive_cmds_need_lc=yes
+
+  if test "$enable_shared" = yes && test "$GCC" = yes; then
+    case $archive_cmds in
+    *'~'*)
+      # FIXME: we may have to deal with multi-command sequences.
+      ;;
+    '$CC '*)
+      # Test whether the compiler implicitly links with -lc since on some
+      # systems, -lgcc has to come before -lc. If gcc already passes -lc
+      # to ld, don't add -lc before -lgcc.
+      echo "$as_me:$LINENO: checking whether -lc should be explicitly linked in" >&5
+echo $ECHO_N "checking whether -lc should be explicitly linked in... $ECHO_C" >&6
+      $RM conftest*
+      echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+
+      if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } 2>conftest.err; then
+        soname=conftest
+        lib=conftest
+        libobjs=conftest.$ac_objext
+        deplibs=
+        wl=$lt_prog_compiler_wl
+	pic_flag=$lt_prog_compiler_pic
+        compiler_flags=-v
+        linker_flags=-v
+        verstring=
+        output_objdir=.
+        libname=conftest
+        lt_save_allow_undefined_flag=$allow_undefined_flag
+        allow_undefined_flag=
+        if { (eval echo "$as_me:$LINENO: \"$archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1\"") >&5
+  (eval $archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }
+        then
+	  archive_cmds_need_lc=no
+        else
+	  archive_cmds_need_lc=yes
+        fi
+        allow_undefined_flag=$lt_save_allow_undefined_flag
+      else
+        cat conftest.err 1>&5
+      fi
+      $RM conftest*
+      echo "$as_me:$LINENO: result: $archive_cmds_need_lc" >&5
+echo "${ECHO_T}$archive_cmds_need_lc" >&6
+      ;;
+    esac
+  fi
+  ;;
+esac
+
+
+
+
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+
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking dynamic linker characteristics" >&5
+echo $ECHO_N "checking dynamic linker characteristics... $ECHO_C" >&6
+withGCC=$GCC
+if test "$withGCC" = yes; then
+  case $host_os in
+    darwin*) lt_awk_arg="/^libraries:/,/LR/" ;;
+    *) lt_awk_arg="/^libraries:/" ;;
+  esac
+  lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e "s,=/,/,g"`
+  if $ECHO "$lt_search_path_spec" | $GREP ';' >/dev/null ; then
+    # if the path contains ";" then we assume it to be the separator
+    # otherwise default to the standard path separator (i.e. ":") - it is
+    # assumed that no part of a normal pathname contains ";" but that should
+    # okay in the real world where ";" in dirpaths is itself problematic.
+    lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED -e 's/;/ /g'`
   else
-    echo "not updating unwritable cache $cache_file"
+    lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED  -e "s/$PATH_SEPARATOR/ /g"`
+  fi
+  # Ok, now we have the path, separated by spaces, we can step through it
+  # and add multilib dir if necessary.
+  lt_tmp_lt_search_path_spec=
+  lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS -print-multi-os-directory 2>/dev/null`
+  for lt_sys_path in $lt_search_path_spec; do
+    if test -d "$lt_sys_path/$lt_multi_os_dir"; then
+      lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path/$lt_multi_os_dir"
+    else
+      test -d "$lt_sys_path" && \
+	lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path"
+    fi
+  done
+  lt_search_path_spec=`$ECHO $lt_tmp_lt_search_path_spec | awk '
+BEGIN {RS=" "; FS="/|\n";} {
+  lt_foo="";
+  lt_count=0;
+  for (lt_i = NF; lt_i > 0; lt_i--) {
+    if ($lt_i != "" && $lt_i != ".") {
+      if ($lt_i == "..") {
+        lt_count++;
+      } else {
+        if (lt_count == 0) {
+          lt_foo="/" $lt_i lt_foo;
+        } else {
+          lt_count--;
+        }
+      }
+    }
+  }
+  if (lt_foo != "") { lt_freq[lt_foo]++; }
+  if (lt_freq[lt_foo] == 1) { print lt_foo; }
+}'`
+  sys_lib_search_path_spec=`$ECHO $lt_search_path_spec`
+else
+  sys_lib_search_path_spec="/lib /usr/lib /usr/local/lib"
+fi
+library_names_spec=
+libname_spec='lib$name'
+soname_spec=
+shrext_cmds=".so"
+postinstall_cmds=
+postuninstall_cmds=
+finish_cmds=
+finish_eval=
+shlibpath_var=
+shlibpath_overrides_runpath=unknown
+version_type=none
+dynamic_linker="$host_os ld.so"
+sys_lib_dlsearch_path_spec="/lib /usr/lib"
+need_lib_prefix=unknown
+hardcode_into_libs=no
+
+# when you set need_version to no, make sure it does not cause -set_version
+# flags to be left without arguments
+need_version=unknown
+
+case $host_os in
+aix3*)
+  version_type=linux
+  library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a'
+  shlibpath_var=LIBPATH
+
+  # AIX 3 has no versioning support, so we append a major version to the name.
+  soname_spec='${libname}${release}${shared_ext}$major'
+  ;;
+
+aix4* | aix5*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  hardcode_into_libs=yes
+  if test "$host_cpu" = ia64; then
+    # AIX 5 supports IA64
+    library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}'
+    shlibpath_var=LD_LIBRARY_PATH
+  else
+    # With GCC up to 2.95.x, collect2 would create an import file
+    # for dependence libraries.  The import file would start with
+    # the line `#! .'.  This would cause the generated library to
+    # depend on `.', always an invalid library.  This was fixed in
+    # development snapshots of GCC prior to 3.0.
+    case $host_os in
+      aix4 | aix4.[01] | aix4.[01].*)
+      if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)'
+	   echo ' yes '
+	   echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then
+	:
+      else
+	can_build_shared=no
+      fi
+      ;;
+    esac
+    # AIX (on Power*) has no versioning support, so currently we can not hardcode correct
+    # soname into executable. Probably we can add versioning support to
+    # collect2, so additional links can be useful in future.
+    if test "$aix_use_runtimelinking" = yes; then
+      # If using run time linking (on AIX 4.2 or later) use lib<name>.so
+      # instead of lib<name>.a to let people know that these are not
+      # typical AIX shared libraries.
+      library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    else
+      # We preserve .a as extension for shared libraries through AIX4.2
+      # and later when we are not doing run time linking.
+      library_names_spec='${libname}${release}.a $libname.a'
+      soname_spec='${libname}${release}${shared_ext}$major'
+    fi
+    shlibpath_var=LIBPATH
+  fi
+  ;;
+
+amigaos*)
+  if test "$host_cpu" = m68k; then
+    library_names_spec='$libname.ixlibrary $libname.a'
+    # Create ${libname}_ixlibrary.a entries in /sys/libs.
+    finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`$ECHO "X$lib" | $Xsed -e '\''s%^.*/\([^/]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done'
+  else
+    dynamic_linker=no
+  fi
+  ;;
+
+beos*)
+  library_names_spec='${libname}${shared_ext}'
+  dynamic_linker="$host_os ld.so"
+  shlibpath_var=LIBRARY_PATH
+  ;;
+
+bsdi[45]*)
+  version_type=linux
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib"
+  sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib"
+  # the default ld.so.conf also contains /usr/contrib/lib and
+  # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow
+  # libtool to hard-code these into programs
+  ;;
+
+cygwin* | mingw* | pw32*)
+  version_type=windows
+  shrext_cmds=".dll"
+  need_version=no
+  need_lib_prefix=no
+
+  case $withGCC,$host_os in
+  yes,cygwin* | yes,mingw* | yes,pw32*)
+    library_names_spec='$libname.dll.a'
+    # DLL is installed to $(libdir)/../bin by postinstall_cmds
+    postinstall_cmds='base_file=`basename \${file}`~
+      dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~
+      dldir=$destdir/`dirname \$dlpath`~
+      test -d \$dldir || mkdir -p \$dldir~
+      $install_prog $dir/$dlname \$dldir/$dlname~
+      chmod a+x \$dldir/$dlname~
+      if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then
+        eval '\''$striplib \$dldir/$dlname'\'' || exit \$?;
+      fi'
+    postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~
+      dlpath=$dir/\$dldll~
+       $RM \$dlpath'
+    shlibpath_overrides_runpath=yes
+
+    case $host_os in
+    cygwin*)
+      # Cygwin DLLs use 'cyg' prefix rather than 'lib'
+      soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}'
+      sys_lib_search_path_spec="/usr/lib /lib/w32api /lib /usr/local/lib"
+      ;;
+    mingw*)
+      # MinGW DLLs use traditional 'lib' prefix
+      soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}'
+      sys_lib_search_path_spec=`$CC -print-search-dirs | $GREP "^libraries:" | $SED -e "s/^libraries://" -e "s,=/,/,g"`
+      if $ECHO "$sys_lib_search_path_spec" | $GREP ';[c-zC-Z]:/' >/dev/null; then
+        # It is most probably a Windows format PATH printed by
+        # mingw gcc, but we are running on Cygwin. Gcc prints its search
+        # path with ; separators, and with drive letters. We can handle the
+        # drive letters (cygwin fileutils understands them), so leave them,
+        # especially as we might pass files found there to a mingw objdump,
+        # which wouldn't understand a cygwinified path. Ahh.
+        sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e 's/;/ /g'`
+      else
+        sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED  -e "s/$PATH_SEPARATOR/ /g"`
+      fi
+      ;;
+    pw32*)
+      # pw32 DLLs use 'pw' prefix rather than 'lib'
+      library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}'
+      ;;
+    esac
+    ;;
+
+  *)
+    library_names_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext} $libname.lib'
+    ;;
+  esac
+  dynamic_linker='Win32 ld.exe'
+  # FIXME: first we should search . and the directory the executable is in
+  shlibpath_var=PATH
+  ;;
+
+darwin* | rhapsody*)
+  dynamic_linker="$host_os dyld"
+  version_type=darwin
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext'
+  soname_spec='${libname}${release}${major}$shared_ext'
+  shlibpath_overrides_runpath=yes
+  shlibpath_var=DYLD_LIBRARY_PATH
+  shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`'
+
+  sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/local/lib"
+  sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib'
+  ;;
+
+dgux*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  ;;
+
+freebsd1*)
+  dynamic_linker=no
+  ;;
+
+freebsd* | dragonfly*)
+  # DragonFly does not have aout.  When/if they implement a new
+  # versioning mechanism, adjust this.
+  if test -x /usr/bin/objformat; then
+    objformat=`/usr/bin/objformat`
+  else
+    case $host_os in
+    freebsd[123]*) objformat=aout ;;
+    *) objformat=elf ;;
+    esac
   fi
+  version_type=freebsd-$objformat
+  case $version_type in
+    freebsd-elf*)
+      library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}'
+      need_version=no
+      need_lib_prefix=no
+      ;;
+    freebsd-*)
+      library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix'
+      need_version=yes
+      ;;
+  esac
+  shlibpath_var=LD_LIBRARY_PATH
+  case $host_os in
+  freebsd2*)
+    shlibpath_overrides_runpath=yes
+    ;;
+  freebsd3.[01]* | freebsdelf3.[01]*)
+    shlibpath_overrides_runpath=yes
+    hardcode_into_libs=yes
+    ;;
+  freebsd3.[2-9]* | freebsdelf3.[2-9]* | \
+  freebsd4.[0-5] | freebsdelf4.[0-5] | freebsd4.1.1 | freebsdelf4.1.1)
+    shlibpath_overrides_runpath=no
+    hardcode_into_libs=yes
+    ;;
+  *) # from 4.6 on, and DragonFly
+    shlibpath_overrides_runpath=yes
+    hardcode_into_libs=yes
+    ;;
+  esac
+  ;;
+
+gnu*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  hardcode_into_libs=yes
+  ;;
+
+hpux9* | hpux10* | hpux11*)
+  # Give a soname corresponding to the major version so that dld.sl refuses to
+  # link against other versions.
+  version_type=sunos
+  need_lib_prefix=no
+  need_version=no
+  case $host_cpu in
+  ia64*)
+    shrext_cmds='.so'
+    hardcode_into_libs=yes
+    dynamic_linker="$host_os dld.so"
+    shlibpath_var=LD_LIBRARY_PATH
+    shlibpath_overrides_runpath=yes # Unless +noenvvar is specified.
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    if test "X$HPUX_IA64_MODE" = X32; then
+      sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib"
+    else
+      sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64"
+    fi
+    sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec
+    ;;
+  hppa*64*)
+    shrext_cmds='.sl'
+    hardcode_into_libs=yes
+    dynamic_linker="$host_os dld.sl"
+    shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH
+    shlibpath_overrides_runpath=yes # Unless +noenvvar is specified.
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64"
+    sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec
+    ;;
+  *)
+    shrext_cmds='.sl'
+    dynamic_linker="$host_os dld.sl"
+    shlibpath_var=SHLIB_PATH
+    shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    ;;
+  esac
+  # HP-UX runs *really* slowly unless shared libraries are mode 555.
+  postinstall_cmds='chmod 555 $lib'
+  ;;
+
+interix[3-9]*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  ;;
+
+irix5* | irix6* | nonstopux*)
+  case $host_os in
+    nonstopux*) version_type=nonstopux ;;
+    *)
+	if test "$lt_cv_prog_gnu_ld" = yes; then
+		version_type=linux
+	else
+		version_type=irix
+	fi ;;
+  esac
+  need_lib_prefix=no
+  need_version=no
+  soname_spec='${libname}${release}${shared_ext}$major'
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}'
+  case $host_os in
+  irix5* | nonstopux*)
+    libsuff= shlibsuff=
+    ;;
+  *)
+    case $LD in # libtool.m4 will add one of these switches to LD
+    *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ")
+      libsuff= shlibsuff= libmagic=32-bit;;
+    *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ")
+      libsuff=32 shlibsuff=N32 libmagic=N32;;
+    *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ")
+      libsuff=64 shlibsuff=64 libmagic=64-bit;;
+    *) libsuff= shlibsuff= libmagic=never-match;;
+    esac
+    ;;
+  esac
+  shlibpath_var=LD_LIBRARY${shlibsuff}_PATH
+  shlibpath_overrides_runpath=no
+  sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}"
+  sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}"
+  hardcode_into_libs=yes
+  ;;
+
+# No shared lib support for Linux oldld, aout, or coff.
+linux*oldld* | linux*aout* | linux*coff*)
+  dynamic_linker=no
+  ;;
+
+# This must be Linux ELF.
+linux* | k*bsd*-gnu)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  # Some binutils ld are patched to set DT_RUNPATH
+  save_LDFLAGS=$LDFLAGS
+  save_libdir=$libdir
+  eval "libdir=/foo; wl=\"$lt_prog_compiler_wl\"; \
+       LDFLAGS=\"\$LDFLAGS $hardcode_libdir_flag_spec\""
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  if  ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir"; then
+  shlibpath_overrides_runpath=yes
 fi
-rm -f confcache
 
-# Actually configure libtool.  ac_aux_dir is where install-sh is found.
-AR="$AR" LTCC="$CC" CC="$CC" CFLAGS="$CFLAGS" CPPFLAGS="$CPPFLAGS" \
-MAGIC_CMD="$MAGIC_CMD" LD="$LD" LDFLAGS="$LDFLAGS" LIBS="$LIBS" \
-LN_S="$LN_S" NM="$NM" RANLIB="$RANLIB" STRIP="$STRIP" \
-AS="$AS" DLLTOOL="$DLLTOOL" OBJDUMP="$OBJDUMP" \
-objext="$OBJEXT" exeext="$EXEEXT" reload_flag="$reload_flag" \
-deplibs_check_method="$deplibs_check_method" file_magic_cmd="$file_magic_cmd" \
-${CONFIG_SHELL-/bin/sh} $ac_aux_dir/ltconfig --no-reexec \
-$libtool_flags --no-verify --build="$build" $ac_aux_dir/ltmain.sh $host \
-|| { { echo "$as_me:$LINENO: error: libtool configure failed" >&5
-echo "$as_me: error: libtool configure failed" >&2;}
-   { (exit 1); exit 1; }; }
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
 
-# Reload cache, that may have been modified by ltconfig
-if test -r "$cache_file"; then
-  # Some versions of bash will fail to source /dev/null (special
-  # files actually), so we avoid doing that.
-  if test -f "$cache_file"; then
-    { echo "$as_me:$LINENO: loading cache $cache_file" >&5
-echo "$as_me: loading cache $cache_file" >&6;}
-    case $cache_file in
-      [\\/]* | ?:[\\/]* ) . $cache_file;;
-      *)                      . ./$cache_file;;
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+  LDFLAGS=$save_LDFLAGS
+  libdir=$save_libdir
+
+  # This implies no fast_install, which is unacceptable.
+  # Some rework will be needed to allow for fast_install
+  # before this can be enabled.
+  hardcode_into_libs=yes
+
+  # Append ld.so.conf contents to the search path
+  if test -f /etc/ld.so.conf; then
+    lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;s/[:,	]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;/^$/d' | tr '\n' ' '`
+    sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
+  fi
+
+  # We used to test for /lib/ld.so.1 and disable shared libraries on
+  # powerpc, because MkLinux only supported shared libraries with the
+  # GNU dynamic linker.  Since this was broken with cross compilers,
+  # most powerpc-linux boxes support dynamic linking these days and
+  # people can always --disable-shared, the test was removed, and we
+  # assume the GNU/Linux dynamic linker is in use.
+  dynamic_linker='GNU/Linux ld.so'
+  ;;
+
+netbsd*)
+  version_type=sunos
+  need_lib_prefix=no
+  need_version=no
+  if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
+    finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir'
+    dynamic_linker='NetBSD (a.out) ld.so'
+  else
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    dynamic_linker='NetBSD ld.elf_so'
+  fi
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  hardcode_into_libs=yes
+  ;;
+
+newsos6)
+  version_type=linux
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  ;;
+
+*nto* | *qnx*)
+  version_type=qnx
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  dynamic_linker='ldqnx.so'
+  ;;
+
+openbsd*)
+  version_type=sunos
+  sys_lib_dlsearch_path_spec="/usr/lib"
+  need_lib_prefix=no
+  # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs.
+  case $host_os in
+    openbsd3.3 | openbsd3.3.*)	need_version=yes ;;
+    *)				need_version=no  ;;
+  esac
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
+  finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+    case $host_os in
+      openbsd2.[89] | openbsd2.[89].*)
+	shlibpath_overrides_runpath=no
+	;;
+      *)
+	shlibpath_overrides_runpath=yes
+	;;
+      esac
+  else
+    shlibpath_overrides_runpath=yes
+  fi
+  ;;
+
+os2*)
+  libname_spec='$name'
+  shrext_cmds=".dll"
+  need_lib_prefix=no
+  library_names_spec='$libname${shared_ext} $libname.a'
+  dynamic_linker='OS/2 ld.exe'
+  shlibpath_var=LIBPATH
+  ;;
+
+osf3* | osf4* | osf5*)
+  version_type=osf
+  need_lib_prefix=no
+  need_version=no
+  soname_spec='${libname}${release}${shared_ext}$major'
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  shlibpath_var=LD_LIBRARY_PATH
+  sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib"
+  sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec"
+  ;;
+
+rdos*)
+  dynamic_linker=no
+  ;;
+
+solaris*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  hardcode_into_libs=yes
+  # ldd complains unless libraries are executable
+  postinstall_cmds='chmod +x $lib'
+  ;;
+
+sunos4*)
+  version_type=sunos
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
+  finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  if test "$with_gnu_ld" = yes; then
+    need_lib_prefix=no
+  fi
+  need_version=yes
+  ;;
+
+sysv4 | sysv4.3*)
+  version_type=linux
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  case $host_vendor in
+    sni)
+      shlibpath_overrides_runpath=no
+      need_lib_prefix=no
+      runpath_var=LD_RUN_PATH
+      ;;
+    siemens)
+      need_lib_prefix=no
+      ;;
+    motorola)
+      need_lib_prefix=no
+      need_version=no
+      shlibpath_overrides_runpath=no
+      sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib'
+      ;;
+  esac
+  ;;
+
+sysv4*MP*)
+  if test -d /usr/nec ;then
+    version_type=linux
+    library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}'
+    soname_spec='$libname${shared_ext}.$major'
+    shlibpath_var=LD_LIBRARY_PATH
+  fi
+  ;;
+
+sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*)
+  version_type=freebsd-elf
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  hardcode_into_libs=yes
+  if test "$with_gnu_ld" = yes; then
+    sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib'
+  else
+    sys_lib_search_path_spec='/usr/ccs/lib /usr/lib'
+    case $host_os in
+      sco3.2v5*)
+        sys_lib_search_path_spec="$sys_lib_search_path_spec /lib"
+	;;
     esac
   fi
+  sys_lib_dlsearch_path_spec='/usr/lib'
+  ;;
+
+tpf*)
+  # TPF is a cross-target only.  Preferred cross-host = GNU/Linux.
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_name_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  ;;
+
+uts4*)
+  version_type=linux
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  ;;
+
+*)
+  dynamic_linker=no
+  ;;
+esac
+echo "$as_me:$LINENO: result: $dynamic_linker" >&5
+echo "${ECHO_T}$dynamic_linker" >&6
+test "$dynamic_linker" = no && can_build_shared=no
+
+variables_saved_for_relink="PATH $shlibpath_var $runpath_var"
+if test "$GCC" = yes; then
+  variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH"
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking how to hardcode library paths into programs" >&5
+echo $ECHO_N "checking how to hardcode library paths into programs... $ECHO_C" >&6
+hardcode_action=
+if test -n "$hardcode_libdir_flag_spec" ||
+   test -n "$runpath_var" ||
+   test "X$hardcode_automatic" = "Xyes" ; then
+
+  # We can hardcode non-existent directories.
+  if test "$hardcode_direct" != no &&
+     # If the only mechanism to avoid hardcoding is shlibpath_var, we
+     # have to relink, otherwise we might link with an installed library
+     # when we should be linking with a yet-to-be-installed one
+     ## test "$_LT_TAGVAR(hardcode_shlibpath_var, )" != no &&
+     test "$hardcode_minus_L" != no; then
+    # Linking always hardcodes the temporary library directory.
+    hardcode_action=relink
+  else
+    # We can link without hardcoding, and we can hardcode nonexisting dirs.
+    hardcode_action=immediate
+  fi
 else
-  { echo "$as_me:$LINENO: creating cache $cache_file" >&5
-echo "$as_me: creating cache $cache_file" >&6;}
-  >$cache_file
+  # We cannot hardcode anything, or else we can only hardcode existing
+  # directories.
+  hardcode_action=unsupported
 fi
+echo "$as_me:$LINENO: result: $hardcode_action" >&5
+echo "${ECHO_T}$hardcode_action" >&6
 
+if test "$hardcode_action" = relink ||
+   test "$inherit_rpath" = yes; then
+  # Fast installation is not supported
+  enable_fast_install=no
+elif test "$shlibpath_overrides_runpath" = yes ||
+     test "$enable_shared" = no; then
+  # Fast installation is not necessary
+  enable_fast_install=needless
+fi
 
-# This can be used to rebuild libtool when needed
-LIBTOOL_DEPS="$ac_aux_dir/ltconfig $ac_aux_dir/ltmain.sh $ac_aux_dir/ltcf-c.sh"
 
-# Always use our own libtool.
-LIBTOOL='$(SHELL) $(top_builddir)/libtool'
 
-# Redirect the config.log output again, so that the ltconfig log is not
-# clobbered by the next message.
-exec 5>>./config.log
 
 
 
+  if test "x$enable_dlopen" != xyes; then
+  enable_dlopen=unknown
+  enable_dlopen_self=unknown
+  enable_dlopen_self_static=unknown
+else
+  lt_cv_dlopen=no
+  lt_cv_dlopen_libs=
+
+  case $host_os in
+  beos*)
+    lt_cv_dlopen="load_add_on"
+    lt_cv_dlopen_libs=
+    lt_cv_dlopen_self=yes
+    ;;
+
+  mingw* | pw32*)
+    lt_cv_dlopen="LoadLibrary"
+    lt_cv_dlopen_libs=
+    ;;
+
+  cygwin*)
+    lt_cv_dlopen="dlopen"
+    lt_cv_dlopen_libs=
+    ;;
+
+  darwin*)
+  # if libdl is installed we need to link against it
+    echo "$as_me:$LINENO: checking for dlopen in -ldl" >&5
+echo $ECHO_N "checking for dlopen in -ldl... $ECHO_C" >&6
+if test "${ac_cv_lib_dl_dlopen+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-ldl  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dlopen ();
+int
+main ()
+{
+dlopen ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_dl_dlopen=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_dl_dlopen=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_dl_dlopen" >&5
+echo "${ECHO_T}$ac_cv_lib_dl_dlopen" >&6
+if test $ac_cv_lib_dl_dlopen = yes; then
+  lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"
+else
+
+    lt_cv_dlopen="dyld"
+    lt_cv_dlopen_libs=
+    lt_cv_dlopen_self=yes
+
+fi
+
+    ;;
+
+  *)
+    echo "$as_me:$LINENO: checking for shl_load" >&5
+echo $ECHO_N "checking for shl_load... $ECHO_C" >&6
+if test "${ac_cv_func_shl_load+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+/* Define shl_load to an innocuous variant, in case <limits.h> declares shl_load.
+   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
+#define shl_load innocuous_shl_load
+
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char shl_load (); below.
+    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+    <limits.h> exists even on freestanding compilers.  */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef shl_load
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char shl_load ();
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_shl_load) || defined (__stub___shl_load)
+choke me
+#else
+char (*f) () = shl_load;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != shl_load;
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_func_shl_load=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_func_shl_load=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_func_shl_load" >&5
+echo "${ECHO_T}$ac_cv_func_shl_load" >&6
+if test $ac_cv_func_shl_load = yes; then
+  lt_cv_dlopen="shl_load"
+else
+  echo "$as_me:$LINENO: checking for shl_load in -ldld" >&5
+echo $ECHO_N "checking for shl_load in -ldld... $ECHO_C" >&6
+if test "${ac_cv_lib_dld_shl_load+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-ldld  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char shl_load ();
+int
+main ()
+{
+shl_load ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_dld_shl_load=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_dld_shl_load=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_dld_shl_load" >&5
+echo "${ECHO_T}$ac_cv_lib_dld_shl_load" >&6
+if test $ac_cv_lib_dld_shl_load = yes; then
+  lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-dld"
+else
+  echo "$as_me:$LINENO: checking for dlopen" >&5
+echo $ECHO_N "checking for dlopen... $ECHO_C" >&6
+if test "${ac_cv_func_dlopen+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+/* Define dlopen to an innocuous variant, in case <limits.h> declares dlopen.
+   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
+#define dlopen innocuous_dlopen
+
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char dlopen (); below.
+    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+    <limits.h> exists even on freestanding compilers.  */
 
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef dlopen
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dlopen ();
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_dlopen) || defined (__stub___dlopen)
+choke me
+#else
+char (*f) () = dlopen;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != dlopen;
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_func_dlopen=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_func_dlopen=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_func_dlopen" >&5
+echo "${ECHO_T}$ac_cv_func_dlopen" >&6
+if test $ac_cv_func_dlopen = yes; then
+  lt_cv_dlopen="dlopen"
+else
+  echo "$as_me:$LINENO: checking for dlopen in -ldl" >&5
+echo $ECHO_N "checking for dlopen in -ldl... $ECHO_C" >&6
+if test "${ac_cv_lib_dl_dlopen+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-ldl  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dlopen ();
+int
+main ()
+{
+dlopen ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_dl_dlopen=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_dl_dlopen=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_dl_dlopen" >&5
+echo "${ECHO_T}$ac_cv_lib_dl_dlopen" >&6
+if test $ac_cv_lib_dl_dlopen = yes; then
+  lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"
+else
+  echo "$as_me:$LINENO: checking for dlopen in -lsvld" >&5
+echo $ECHO_N "checking for dlopen in -lsvld... $ECHO_C" >&6
+if test "${ac_cv_lib_svld_dlopen+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-lsvld  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dlopen ();
+int
+main ()
+{
+dlopen ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_svld_dlopen=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_svld_dlopen=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_svld_dlopen" >&5
+echo "${ECHO_T}$ac_cv_lib_svld_dlopen" >&6
+if test $ac_cv_lib_svld_dlopen = yes; then
+  lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld"
+else
+  echo "$as_me:$LINENO: checking for dld_link in -ldld" >&5
+echo $ECHO_N "checking for dld_link in -ldld... $ECHO_C" >&6
+if test "${ac_cv_lib_dld_dld_link+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-ldld  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dld_link ();
+int
+main ()
+{
+dld_link ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_dld_dld_link=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_dld_dld_link=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_dld_dld_link" >&5
+echo "${ECHO_T}$ac_cv_lib_dld_dld_link" >&6
+if test $ac_cv_lib_dld_dld_link = yes; then
+  lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-dld"
+fi
+
+
+fi
+
+
+fi
+
+
+fi
+
+
+fi
+
+
+fi
+
+    ;;
+  esac
+
+  if test "x$lt_cv_dlopen" != xno; then
+    enable_dlopen=yes
+  else
+    enable_dlopen=no
+  fi
+
+  case $lt_cv_dlopen in
+  dlopen)
+    save_CPPFLAGS="$CPPFLAGS"
+    test "x$ac_cv_header_dlfcn_h" = xyes && CPPFLAGS="$CPPFLAGS -DHAVE_DLFCN_H"
+
+    save_LDFLAGS="$LDFLAGS"
+    wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $export_dynamic_flag_spec\"
+
+    save_LIBS="$LIBS"
+    LIBS="$lt_cv_dlopen_libs $LIBS"
+
+    echo "$as_me:$LINENO: checking whether a program can dlopen itself" >&5
+echo $ECHO_N "checking whether a program can dlopen itself... $ECHO_C" >&6
+if test "${lt_cv_dlopen_self+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  	  if test "$cross_compiling" = yes; then :
+  lt_cv_dlopen_self=cross
+else
+  lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+  lt_status=$lt_dlunknown
+  cat > conftest.$ac_ext <<_LT_EOF
+#line 9201 "configure"
+#include "confdefs.h"
+
+#if HAVE_DLFCN_H
+#include <dlfcn.h>
+#endif
+
+#include <stdio.h>
+
+#ifdef RTLD_GLOBAL
+#  define LT_DLGLOBAL		RTLD_GLOBAL
+#else
+#  ifdef DL_GLOBAL
+#    define LT_DLGLOBAL		DL_GLOBAL
+#  else
+#    define LT_DLGLOBAL		0
+#  endif
+#endif
+
+/* We may have to define LT_DLLAZY_OR_NOW in the command line if we
+   find out it does not work in some platform. */
+#ifndef LT_DLLAZY_OR_NOW
+#  ifdef RTLD_LAZY
+#    define LT_DLLAZY_OR_NOW		RTLD_LAZY
+#  else
+#    ifdef DL_LAZY
+#      define LT_DLLAZY_OR_NOW		DL_LAZY
+#    else
+#      ifdef RTLD_NOW
+#        define LT_DLLAZY_OR_NOW	RTLD_NOW
+#      else
+#        ifdef DL_NOW
+#          define LT_DLLAZY_OR_NOW	DL_NOW
+#        else
+#          define LT_DLLAZY_OR_NOW	0
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+#ifdef __cplusplus
+extern "C" void exit (int);
+#endif
+
+void fnord() { int i=42;}
+int main ()
+{
+  void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW);
+  int status = $lt_dlunknown;
+
+  if (self)
+    {
+      if (dlsym (self,"fnord"))       status = $lt_dlno_uscore;
+      else if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore;
+      /* dlclose (self); */
+    }
+  else
+    puts (dlerror ());
+
+    exit (status);
+}
+_LT_EOF
+  if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && test -s conftest${ac_exeext} 2>/dev/null; then
+    (./conftest; exit; ) >&5 2>/dev/null
+    lt_status=$?
+    case x$lt_status in
+      x$lt_dlno_uscore) lt_cv_dlopen_self=yes ;;
+      x$lt_dlneed_uscore) lt_cv_dlopen_self=yes ;;
+      x$lt_dlunknown|x*) lt_cv_dlopen_self=no ;;
+    esac
+  else :
+    # compilation failed
+    lt_cv_dlopen_self=no
+  fi
+fi
+rm -fr conftest*
+
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_dlopen_self" >&5
+echo "${ECHO_T}$lt_cv_dlopen_self" >&6
+
+    if test "x$lt_cv_dlopen_self" = xyes; then
+      wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\"
+      echo "$as_me:$LINENO: checking whether a statically linked program can dlopen itself" >&5
+echo $ECHO_N "checking whether a statically linked program can dlopen itself... $ECHO_C" >&6
+if test "${lt_cv_dlopen_self_static+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  	  if test "$cross_compiling" = yes; then :
+  lt_cv_dlopen_self_static=cross
+else
+  lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+  lt_status=$lt_dlunknown
+  cat > conftest.$ac_ext <<_LT_EOF
+#line 9301 "configure"
+#include "confdefs.h"
+
+#if HAVE_DLFCN_H
+#include <dlfcn.h>
+#endif
+
+#include <stdio.h>
+
+#ifdef RTLD_GLOBAL
+#  define LT_DLGLOBAL		RTLD_GLOBAL
+#else
+#  ifdef DL_GLOBAL
+#    define LT_DLGLOBAL		DL_GLOBAL
+#  else
+#    define LT_DLGLOBAL		0
+#  endif
+#endif
+
+/* We may have to define LT_DLLAZY_OR_NOW in the command line if we
+   find out it does not work in some platform. */
+#ifndef LT_DLLAZY_OR_NOW
+#  ifdef RTLD_LAZY
+#    define LT_DLLAZY_OR_NOW		RTLD_LAZY
+#  else
+#    ifdef DL_LAZY
+#      define LT_DLLAZY_OR_NOW		DL_LAZY
+#    else
+#      ifdef RTLD_NOW
+#        define LT_DLLAZY_OR_NOW	RTLD_NOW
+#      else
+#        ifdef DL_NOW
+#          define LT_DLLAZY_OR_NOW	DL_NOW
+#        else
+#          define LT_DLLAZY_OR_NOW	0
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+#ifdef __cplusplus
+extern "C" void exit (int);
+#endif
+
+void fnord() { int i=42;}
+int main ()
+{
+  void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW);
+  int status = $lt_dlunknown;
+
+  if (self)
+    {
+      if (dlsym (self,"fnord"))       status = $lt_dlno_uscore;
+      else if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore;
+      /* dlclose (self); */
+    }
+  else
+    puts (dlerror ());
+
+    exit (status);
+}
+_LT_EOF
+  if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && test -s conftest${ac_exeext} 2>/dev/null; then
+    (./conftest; exit; ) >&5 2>/dev/null
+    lt_status=$?
+    case x$lt_status in
+      x$lt_dlno_uscore) lt_cv_dlopen_self_static=yes ;;
+      x$lt_dlneed_uscore) lt_cv_dlopen_self_static=yes ;;
+      x$lt_dlunknown|x*) lt_cv_dlopen_self_static=no ;;
+    esac
+  else :
+    # compilation failed
+    lt_cv_dlopen_self_static=no
+  fi
+fi
+rm -fr conftest*
+
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_dlopen_self_static" >&5
+echo "${ECHO_T}$lt_cv_dlopen_self_static" >&6
+    fi
+
+    CPPFLAGS="$save_CPPFLAGS"
+    LDFLAGS="$save_LDFLAGS"
+    LIBS="$save_LIBS"
+    ;;
+  esac
+
+  case $lt_cv_dlopen_self in
+  yes|no) enable_dlopen_self=$lt_cv_dlopen_self ;;
+  *) enable_dlopen_self=unknown ;;
+  esac
+
+  case $lt_cv_dlopen_self_static in
+  yes|no) enable_dlopen_self_static=$lt_cv_dlopen_self_static ;;
+  *) enable_dlopen_self_static=unknown ;;
+  esac
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+striplib=
+old_striplib=
+echo "$as_me:$LINENO: checking whether stripping libraries is possible" >&5
+echo $ECHO_N "checking whether stripping libraries is possible... $ECHO_C" >&6
+if test -n "$STRIP" && $STRIP -V 2>&1 | $GREP "GNU strip" >/dev/null; then
+  test -z "$old_striplib" && old_striplib="$STRIP --strip-debug"
+  test -z "$striplib" && striplib="$STRIP --strip-unneeded"
+  echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
+else
+# FIXME - insert some real tests, host_os isn't really good enough
+  case $host_os in
+  darwin*)
+    if test -n "$STRIP" ; then
+      striplib="$STRIP -x"
+      old_striplib="$STRIP -S"
+      echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
+    else
+      echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+    fi
+    ;;
+  *)
+    echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+    ;;
+  esac
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+  # Report which library types will actually be built
+  echo "$as_me:$LINENO: checking if libtool supports shared libraries" >&5
+echo $ECHO_N "checking if libtool supports shared libraries... $ECHO_C" >&6
+  echo "$as_me:$LINENO: result: $can_build_shared" >&5
+echo "${ECHO_T}$can_build_shared" >&6
+
+  echo "$as_me:$LINENO: checking whether to build shared libraries" >&5
+echo $ECHO_N "checking whether to build shared libraries... $ECHO_C" >&6
+  test "$can_build_shared" = "no" && enable_shared=no
+
+  # On AIX, shared libraries and static libraries use the same namespace, and
+  # are all built from PIC.
+  case $host_os in
+  aix3*)
+    test "$enable_shared" = yes && enable_static=no
+    if test -n "$RANLIB"; then
+      archive_cmds="$archive_cmds~\$RANLIB \$lib"
+      postinstall_cmds='$RANLIB $lib'
+    fi
+    ;;
+
+  aix4* | aix5*)
+    if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then
+      test "$enable_shared" = yes && enable_static=no
+    fi
+    ;;
+  esac
+  echo "$as_me:$LINENO: result: $enable_shared" >&5
+echo "${ECHO_T}$enable_shared" >&6
+
+  echo "$as_me:$LINENO: checking whether to build static libraries" >&5
+echo $ECHO_N "checking whether to build static libraries... $ECHO_C" >&6
+  # Make sure either enable_shared or enable_static is yes.
+  test "$enable_shared" = yes || enable_static=yes
+  echo "$as_me:$LINENO: result: $enable_static" >&5
+echo "${ECHO_T}$enable_static" >&6
+
+
+
+
+fi
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+CC="$lt_save_CC"
+
+
+
+
+
+
+
+
+
+
+
+
+
+                  ac_config_commands="$ac_config_commands libtool"
+
+
+
+
+# Only expand once:
 
 
 
@@ -4165,7 +9541,8 @@ echo "$as_me: error: enable-targets option must specify target names or 'all'" >
   no)	    enable_targets= ;;
   *)	    enable_targets=$enableval ;;
 esac
-fi; # Check whether --enable-commonbfdlib or --disable-commonbfdlib was given.
+fi;
+# Check whether --enable-commonbfdlib or --disable-commonbfdlib was given.
 if test "${enable_commonbfdlib+set}" = set; then
   enableval="$enable_commonbfdlib"
   case "${enableval}" in
@@ -4176,6 +9553,25 @@ echo "$as_me: error: bad value ${enableval} for BFD commonbfdlib option" >&2;}
    { (exit 1); exit 1; }; } ;;
 esac
 fi;
+ac_checking=yes
+if grep '^RELEASE=y' ${srcdir}/../bfd/Makefile.am >/dev/null 2>/dev/null ; then
+  ac_checking=
+fi
+# Check whether --enable-checking or --disable-checking was given.
+if test "${enable_checking+set}" = set; then
+  enableval="$enable_checking"
+  case "${enableval}" in
+  no|none)  ac_checking= ;;
+  *)	    ac_checking=yes ;;
+esac
+fi; if test x$ac_checking != x ; then
+
+cat >>confdefs.h <<\_ACEOF
+#define ENABLE_CHECKING 1
+_ACEOF
+
+fi
+
 using_cgen=no
 
 
@@ -4733,7 +10129,7 @@ _ACEOF
 
     # Do we need the opcodes library?
     case ${cpu_type} in
-      vax | i386 | tic30)
+      vax | tic30)
 	;;
 
       *)
@@ -4779,6 +10175,10 @@ _ACEOF
 	esac
 	;;
 
+      mep)
+	using_cgen=yes
+	;;
+
       mips)
 	echo ${extra_objects} | grep -s "itbl-parse.o"
 	if test $? -ne 0 ; then
@@ -4896,6 +10296,19 @@ if test ${all_targets} = "yes"; then
       ;;
     esac
   ;;
+  x86_64)
+    case ${obj_format} in
+    aout)
+      emulations="$emulations i386coff i386elf"
+      ;;
+    coff)
+      emulations="$emulations i386aout i386elf"
+    ;;
+    elf)
+      emulations="$emulations i386aout i386coff"
+      ;;
+    esac
+  ;;
   esac
 fi
 
@@ -4903,8 +10316,7 @@ fi
 # IEEE FP.  On those that don't support FP at all, usually IEEE
 # is emulated.
 case ${target_cpu} in
-  vax | tahoe )	atof=${target_cpu} ;;
-  pdp11)	atof=vax ;;
+  vax | pdp11 )	atof=vax ;;
   *)		atof=ieee ;;
 esac
 
@@ -4960,6 +10372,11 @@ cat >>confdefs.h <<\_ACEOF
 #define M88KCOFF 1
 _ACEOF
  ;;
+      x86_64)
+cat >>confdefs.h <<\_ACEOF
+#define I386COFF 1
+_ACEOF
+ ;;
     esac
     ;;
 esac
@@ -5069,11 +10486,6 @@ cat >>confdefs.h <<\_ACEOF
 #define OBJ_MAYBE_GENERIC 1
 _ACEOF
  ;;
-      ieee)
-cat >>confdefs.h <<\_ACEOF
-#define OBJ_MAYBE_IEEE 1
-_ACEOF
-    ;;
       som)
 cat >>confdefs.h <<\_ACEOF
 #define OBJ_MAYBE_SOM 1
@@ -5134,14 +10546,6 @@ yes)
   ;;
 esac
 
-BFDLIB=../bfd/libbfd.la
-BFDVER_H=../bfd/bfdver.h
-ALL_OBJ_DEPS="$ALL_OBJ_DEPS"' ../bfd/bfd.h $(INCDIR)/symcat.h'
-
-
-
-
-
 
 
 
@@ -6220,2479 +11624,138 @@ if test "$LEX" = :; then
 fi
 
 ALL_LINGUAS="fr tr es rw"
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
-set dummy ${ac_tool_prefix}ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-RANLIB=$ac_cv_prog_RANLIB
-if test -n "$RANLIB"; then
-  echo "$as_me:$LINENO: result: $RANLIB" >&5
-echo "${ECHO_T}$RANLIB" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_RANLIB"; then
-  ac_ct_RANLIB=$RANLIB
-  # Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_RANLIB"; then
-  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_RANLIB="ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-  test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
-fi
-fi
-ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
-if test -n "$ac_ct_RANLIB"; then
-  echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
-echo "${ECHO_T}$ac_ct_RANLIB" >&6
-else
+# If we haven't got the data from the intl directory,
+# assume NLS is disabled.
+USE_NLS=no
+LIBINTL=
+LIBINTL_DEP=
+INCINTL=
+XGETTEXT=
+GMSGFMT=
+POSUB=
+
+if test -f  ../intl/config.intl; then
+  .  ../intl/config.intl
+fi
+echo "$as_me:$LINENO: checking whether NLS is requested" >&5
+echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
+if test x"$USE_NLS" != xyes; then
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
-fi
-
-  RANLIB=$ac_ct_RANLIB
-else
-  RANLIB="$ac_cv_prog_RANLIB"
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
-echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6
-# On Suns, sometimes $CPP names a directory.
-if test -n "$CPP" && test -d "$CPP"; then
-  CPP=
-fi
-if test -z "$CPP"; then
-  if test "${ac_cv_prog_CPP+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-      # Double quotes because CPP needs to be expanded
-    for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
-    do
-      ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  break
-fi
-
-    done
-    ac_cv_prog_CPP=$CPP
-
-fi
-  CPP=$ac_cv_prog_CPP
-else
-  ac_cv_prog_CPP=$CPP
-fi
-echo "$as_me:$LINENO: result: $CPP" >&5
-echo "${ECHO_T}$CPP" >&6
-ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  :
-else
-  { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&5
-echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-
-echo "$as_me:$LINENO: checking for egrep" >&5
-echo $ECHO_N "checking for egrep... $ECHO_C" >&6
-if test "${ac_cv_prog_egrep+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if echo a | (grep -E '(a|b)') >/dev/null 2>&1
-    then ac_cv_prog_egrep='grep -E'
-    else ac_cv_prog_egrep='egrep'
-    fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5
-echo "${ECHO_T}$ac_cv_prog_egrep" >&6
- EGREP=$ac_cv_prog_egrep
-
-
-echo "$as_me:$LINENO: checking for ANSI C header files" >&5
-echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6
-if test "${ac_cv_header_stdc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-#include <float.h>
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_header_stdc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_header_stdc=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-
-if test $ac_cv_header_stdc = yes; then
-  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <string.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "memchr" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "free" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
-  if test "$cross_compiling" = yes; then
-  :
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ctype.h>
-#if ((' ' & 0x0FF) == 0x020)
-# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
-# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
-#else
-# define ISLOWER(c) \
-		   (('a' <= (c) && (c) <= 'i') \
-		     || ('j' <= (c) && (c) <= 'r') \
-		     || ('s' <= (c) && (c) <= 'z'))
-# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
-#endif
-
-#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
-int
-main ()
-{
-  int i;
-  for (i = 0; i < 256; i++)
-    if (XOR (islower (i), ISLOWER (i))
-	|| toupper (i) != TOUPPER (i))
-      exit(2);
-  exit (0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  :
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_header_stdc=no
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
-echo "${ECHO_T}$ac_cv_header_stdc" >&6
-if test $ac_cv_header_stdc = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define STDC_HEADERS 1
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5
-echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6
-if test "${ac_cv_c_const+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-/* FIXME: Include the comments suggested by Paul. */
-#ifndef __cplusplus
-  /* Ultrix mips cc rejects this.  */
-  typedef int charset[2];
-  const charset x;
-  /* SunOS 4.1.1 cc rejects this.  */
-  char const *const *ccp;
-  char **p;
-  /* NEC SVR4.0.2 mips cc rejects this.  */
-  struct point {int x, y;};
-  static struct point const zero = {0,0};
-  /* AIX XL C 1.02.0.0 rejects this.
-     It does not let you subtract one const X* pointer from another in
-     an arm of an if-expression whose if-part is not a constant
-     expression */
-  const char *g = "string";
-  ccp = &g + (g ? g-g : 0);
-  /* HPUX 7.0 cc rejects these. */
-  ++ccp;
-  p = (char**) ccp;
-  ccp = (char const *const *) p;
-  { /* SCO 3.2v4 cc rejects this.  */
-    char *t;
-    char const *s = 0 ? (char *) 0 : (char const *) 0;
-
-    *t++ = 0;
-  }
-  { /* Someone thinks the Sun supposedly-ANSI compiler will reject this.  */
-    int x[] = {25, 17};
-    const int *foo = &x[0];
-    ++foo;
-  }
-  { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
-    typedef const int *iptr;
-    iptr p = 0;
-    ++p;
-  }
-  { /* AIX XL C 1.02.0.0 rejects this saying
-       "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */
-    struct s { int j; const int *ap[3]; };
-    struct s *b; b->j = 5;
-  }
-  { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
-    const int foo = 10;
-  }
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_const=yes
 else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_c_const=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5
-echo "${ECHO_T}$ac_cv_c_const" >&6
-if test $ac_cv_c_const = no; then
+  echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
 
 cat >>confdefs.h <<\_ACEOF
-#define const
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for inline" >&5
-echo $ECHO_N "checking for inline... $ECHO_C" >&6
-if test "${ac_cv_c_inline+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_c_inline=no
-for ac_kw in inline __inline__ __inline; do
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifndef __cplusplus
-typedef int foo_t;
-static $ac_kw foo_t static_foo () {return 0; }
-$ac_kw foo_t foo () {return 0; }
-#endif
-
+#define ENABLE_NLS 1
 _ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_inline=$ac_kw; break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
 
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-done
 
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_inline" >&5
-echo "${ECHO_T}$ac_cv_c_inline" >&6
-
-
-case $ac_cv_c_inline in
-  inline | yes) ;;
-  *)
-    case $ac_cv_c_inline in
-      no) ac_val=;;
-      *) ac_val=$ac_cv_c_inline;;
+  echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
+echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6
+  # Look for .po and .gmo files in the source directory.
+  CATALOGS=
+  XLINGUAS=
+  for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do
+    # If there aren't any .gmo files the shell will give us the
+    # literal string "../path/to/srcdir/po/*.gmo" which has to be
+    # weeded out.
+    case "$cat" in *\**)
+      continue;;
     esac
-    cat >>confdefs.h <<_ACEOF
-#ifndef __cplusplus
-#define inline $ac_val
-#endif
-_ACEOF
-    ;;
-esac
-
-# On IRIX 5.3, sys/types and inttypes.h are conflicting.
-
-
-
-
-
-
-
-
-
-for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
-		  inttypes.h stdint.h unistd.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_Header=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_Header=no"
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-echo "$as_me:$LINENO: checking for off_t" >&5
-echo $ECHO_N "checking for off_t... $ECHO_C" >&6
-if test "${ac_cv_type_off_t+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-int
-main ()
-{
-if ((off_t *) 0)
-  return 0;
-if (sizeof (off_t))
-  return 0;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_type_off_t=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_type_off_t=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_type_off_t" >&5
-echo "${ECHO_T}$ac_cv_type_off_t" >&6
-if test $ac_cv_type_off_t = yes; then
-  :
-else
-
-cat >>confdefs.h <<_ACEOF
-#define off_t long
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for size_t" >&5
-echo $ECHO_N "checking for size_t... $ECHO_C" >&6
-if test "${ac_cv_type_size_t+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-int
-main ()
-{
-if ((size_t *) 0)
-  return 0;
-if (sizeof (size_t))
-  return 0;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_type_size_t=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_type_size_t=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5
-echo "${ECHO_T}$ac_cv_type_size_t" >&6
-if test $ac_cv_type_size_t = yes; then
-  :
-else
-
-cat >>confdefs.h <<_ACEOF
-#define size_t unsigned
-_ACEOF
-
-fi
-
-# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
-# for constant arguments.  Useless!
-echo "$as_me:$LINENO: checking for working alloca.h" >&5
-echo $ECHO_N "checking for working alloca.h... $ECHO_C" >&6
-if test "${ac_cv_working_alloca_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <alloca.h>
-int
-main ()
-{
-char *p = (char *) alloca (2 * sizeof (int));
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_working_alloca_h=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_working_alloca_h=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_working_alloca_h" >&5
-echo "${ECHO_T}$ac_cv_working_alloca_h" >&6
-if test $ac_cv_working_alloca_h = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_ALLOCA_H 1
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for alloca" >&5
-echo $ECHO_N "checking for alloca... $ECHO_C" >&6
-if test "${ac_cv_func_alloca_works+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __GNUC__
-# define alloca __builtin_alloca
-#else
-# ifdef _MSC_VER
-#  include <malloc.h>
-#  define alloca _alloca
-# else
-#  if HAVE_ALLOCA_H
-#   include <alloca.h>
-#  else
-#   ifdef _AIX
- #pragma alloca
-#   else
-#    ifndef alloca /* predefined by HP cc +Olibcalls */
-char *alloca ();
-#    endif
-#   endif
-#  endif
-# endif
-#endif
-
-int
-main ()
-{
-char *p = (char *) alloca (1);
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_func_alloca_works=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_func_alloca_works=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_func_alloca_works" >&5
-echo "${ECHO_T}$ac_cv_func_alloca_works" >&6
-
-if test $ac_cv_func_alloca_works = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_ALLOCA 1
-_ACEOF
-
-else
-  # The SVR3 libPW and SVR4 libucb both contain incompatible functions
-# that cause trouble.  Some versions do not even contain alloca or
-# contain a buggy version.  If you still want to use their alloca,
-# use ar to extract alloca.o from them instead of compiling alloca.c.
-
-ALLOCA=alloca.$ac_objext
-
-cat >>confdefs.h <<\_ACEOF
-#define C_ALLOCA 1
-_ACEOF
-
-
-echo "$as_me:$LINENO: checking whether \`alloca.c' needs Cray hooks" >&5
-echo $ECHO_N "checking whether \`alloca.c' needs Cray hooks... $ECHO_C" >&6
-if test "${ac_cv_os_cray+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#if defined(CRAY) && ! defined(CRAY2)
-webecray
-#else
-wenotbecray
-#endif
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "webecray" >/dev/null 2>&1; then
-  ac_cv_os_cray=yes
-else
-  ac_cv_os_cray=no
-fi
-rm -f conftest*
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_os_cray" >&5
-echo "${ECHO_T}$ac_cv_os_cray" >&6
-if test $ac_cv_os_cray = yes; then
-  for ac_func in _getb67 GETB67 getb67; do
-    as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-
-cat >>confdefs.h <<_ACEOF
-#define CRAY_STACKSEG_END $ac_func
-_ACEOF
-
-    break
-fi
-
+    # The quadruple backslash is collapsed to a double backslash
+    # by the backticks, then collapsed again by the double quotes,
+    # leaving us with one backslash in the sed expression (right
+    # before the dot that mustn't act as a wildcard).
+    cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"`
+    lang=`echo $cat | sed -e "s!\\\\.gmo!!"`
+    # The user is allowed to set LINGUAS to a list of languages to
+    # install catalogs for.  If it's empty that means "all of them."
+    if test "x$LINGUAS" = x; then
+      CATALOGS="$CATALOGS $cat"
+      XLINGUAS="$XLINGUAS $lang"
+    else
+      case "$LINGUAS" in *$lang*)
+        CATALOGS="$CATALOGS $cat"
+        XLINGUAS="$XLINGUAS $lang"
+        ;;
+      esac
+    fi
   done
-fi
-
-echo "$as_me:$LINENO: checking stack direction for C alloca" >&5
-echo $ECHO_N "checking stack direction for C alloca... $ECHO_C" >&6
-if test "${ac_cv_c_stack_direction+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_c_stack_direction=0
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-int
-find_stack_direction ()
-{
-  static char *addr = 0;
-  auto char dummy;
-  if (addr == 0)
-    {
-      addr = &dummy;
-      return find_stack_direction ();
-    }
-  else
-    return (&dummy > addr) ? 1 : -1;
-}
-
-int
-main ()
-{
-  exit (find_stack_direction () < 0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_stack_direction=1
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_c_stack_direction=-1
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_stack_direction" >&5
-echo "${ECHO_T}$ac_cv_c_stack_direction" >&6
-
-cat >>confdefs.h <<_ACEOF
-#define STACK_DIRECTION $ac_cv_c_stack_direction
-_ACEOF
+  LINGUAS="$XLINGUAS"
+  echo "$as_me:$LINENO: result: $LINGUAS" >&5
+echo "${ECHO_T}$LINGUAS" >&6
 
 
-fi
+    DATADIRNAME=share
 
+  INSTOBJEXT=.mo
 
+  GENCAT=gencat
 
-for ac_header in stdlib.h unistd.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
+  CATOBJEXT=.gmo
 
-ac_header_compiler=no
 fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
 
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
+        MKINSTALLDIRS=
+  if test -n "$ac_aux_dir"; then
+    case "$ac_aux_dir" in
+      /*) MKINSTALLDIRS="$ac_aux_dir/mkinstalldirs" ;;
+      *) MKINSTALLDIRS="\$(top_builddir)/$ac_aux_dir/mkinstalldirs" ;;
+    esac
   fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-for ac_func in getpagesize
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-echo "$as_me:$LINENO: checking for working mmap" >&5
-echo $ECHO_N "checking for working mmap... $ECHO_C" >&6
-if test "${ac_cv_func_mmap_fixed_mapped+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_func_mmap_fixed_mapped=no
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-/* malloc might have been renamed as rpl_malloc. */
-#undef malloc
-
-/* Thanks to Mike Haertel and Jim Avera for this test.
-   Here is a matrix of mmap possibilities:
-	mmap private not fixed
-	mmap private fixed at somewhere currently unmapped
-	mmap private fixed at somewhere already mapped
-	mmap shared not fixed
-	mmap shared fixed at somewhere currently unmapped
-	mmap shared fixed at somewhere already mapped
-   For private mappings, we should verify that changes cannot be read()
-   back from the file, nor mmap's back from the file at a different
-   address.  (There have been systems where private was not correctly
-   implemented like the infamous i386 svr4.0, and systems where the
-   VM page cache was not coherent with the file system buffer cache
-   like early versions of FreeBSD and possibly contemporary NetBSD.)
-   For shared mappings, we should conversely verify that changes get
-   propagated back to all the places they're supposed to be.
-
-   Grep wants private fixed already mapped.
-   The main things grep needs to know about mmap are:
-   * does it exist and is it safe to write into the mmap'd area
-   * how to use it (BSD variants)  */
-
-#include <fcntl.h>
-#include <sys/mman.h>
-
-#if !STDC_HEADERS && !HAVE_STDLIB_H
-char *malloc ();
-#endif
-
-/* This mess was copied from the GNU getpagesize.h.  */
-#if !HAVE_GETPAGESIZE
-/* Assume that all systems that can run configure have sys/param.h.  */
-# if !HAVE_SYS_PARAM_H
-#  define HAVE_SYS_PARAM_H 1
-# endif
-
-# ifdef _SC_PAGESIZE
-#  define getpagesize() sysconf(_SC_PAGESIZE)
-# else /* no _SC_PAGESIZE */
-#  if HAVE_SYS_PARAM_H
-#   include <sys/param.h>
-#   ifdef EXEC_PAGESIZE
-#    define getpagesize() EXEC_PAGESIZE
-#   else /* no EXEC_PAGESIZE */
-#    ifdef NBPG
-#     define getpagesize() NBPG * CLSIZE
-#     ifndef CLSIZE
-#      define CLSIZE 1
-#     endif /* no CLSIZE */
-#    else /* no NBPG */
-#     ifdef NBPC
-#      define getpagesize() NBPC
-#     else /* no NBPC */
-#      ifdef PAGESIZE
-#       define getpagesize() PAGESIZE
-#      endif /* PAGESIZE */
-#     endif /* no NBPC */
-#    endif /* no NBPG */
-#   endif /* no EXEC_PAGESIZE */
-#  else /* no HAVE_SYS_PARAM_H */
-#   define getpagesize() 8192	/* punt totally */
-#  endif /* no HAVE_SYS_PARAM_H */
-# endif /* no _SC_PAGESIZE */
-
-#endif /* no HAVE_GETPAGESIZE */
-
-int
-main ()
-{
-  char *data, *data2, *data3;
-  int i, pagesize;
-  int fd;
-
-  pagesize = getpagesize ();
-
-  /* First, make a file with some known garbage in it. */
-  data = (char *) malloc (pagesize);
-  if (!data)
-    exit (1);
-  for (i = 0; i < pagesize; ++i)
-    *(data + i) = rand ();
-  umask (0);
-  fd = creat ("conftest.mmap", 0600);
-  if (fd < 0)
-    exit (1);
-  if (write (fd, data, pagesize) != pagesize)
-    exit (1);
-  close (fd);
-
-  /* Next, try to mmap the file at a fixed address which already has
-     something else allocated at it.  If we can, also make sure that
-     we see the same garbage.  */
-  fd = open ("conftest.mmap", O_RDWR);
-  if (fd < 0)
-    exit (1);
-  data2 = (char *) malloc (2 * pagesize);
-  if (!data2)
-    exit (1);
-  data2 += (pagesize - ((long) data2 & (pagesize - 1))) & (pagesize - 1);
-  if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE,
-		     MAP_PRIVATE | MAP_FIXED, fd, 0L))
-    exit (1);
-  for (i = 0; i < pagesize; ++i)
-    if (*(data + i) != *(data2 + i))
-      exit (1);
-
-  /* Finally, make sure that changes to the mapped area do not
-     percolate back to the file as seen by read().  (This is a bug on
-     some variants of i386 svr4.0.)  */
-  for (i = 0; i < pagesize; ++i)
-    *(data2 + i) = *(data2 + i) + 1;
-  data3 = (char *) malloc (pagesize);
-  if (!data3)
-    exit (1);
-  if (read (fd, data3, pagesize) != pagesize)
-    exit (1);
-  for (i = 0; i < pagesize; ++i)
-    if (*(data + i) != *(data3 + i))
-      exit (1);
-  close (fd);
-  exit (0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_func_mmap_fixed_mapped=yes
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_func_mmap_fixed_mapped=no
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_func_mmap_fixed_mapped" >&5
-echo "${ECHO_T}$ac_cv_func_mmap_fixed_mapped" >&6
-if test $ac_cv_func_mmap_fixed_mapped = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_MMAP 1
-_ACEOF
-
-fi
-rm -f conftest.mmap
-
-
-
-
-
-
-
-
-
-
-
-for ac_header in argz.h limits.h locale.h nl_types.h malloc.h string.h \
-unistd.h values.h sys/param.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
+  if test -z "$MKINSTALLDIRS"; then
+    MKINSTALLDIRS="\$(top_srcdir)/mkinstalldirs"
   fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-
-
-
-
-
-
-
-for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
-__argz_count __argz_stringify __argz_next
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-
-   if test "${ac_cv_func_stpcpy+set}" != "set"; then
-
-for ac_func in stpcpy
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-   fi
-   if test "${ac_cv_func_stpcpy}" = "yes"; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_STPCPY 1
-_ACEOF
-
-   fi
-
-   if test $ac_cv_header_locale_h = yes; then
-    echo "$as_me:$LINENO: checking for LC_MESSAGES" >&5
-echo $ECHO_N "checking for LC_MESSAGES... $ECHO_C" >&6
-if test "${am_cv_val_LC_MESSAGES+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <locale.h>
-int
-main ()
-{
-return LC_MESSAGES
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  am_cv_val_LC_MESSAGES=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
 
-am_cv_val_LC_MESSAGES=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $am_cv_val_LC_MESSAGES" >&5
-echo "${ECHO_T}$am_cv_val_LC_MESSAGES" >&6
-    if test $am_cv_val_LC_MESSAGES = yes; then
 
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_LC_MESSAGES 1
-_ACEOF
 
-    fi
-  fi
-   echo "$as_me:$LINENO: checking whether NLS is requested" >&5
+  echo "$as_me:$LINENO: checking whether NLS is requested" >&5
 echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
-        # Check whether --enable-nls or --disable-nls was given.
+    # Check whether --enable-nls or --disable-nls was given.
 if test "${enable_nls+set}" = set; then
   enableval="$enable_nls"
   USE_NLS=$enableval
 else
   USE_NLS=yes
 fi;
-    echo "$as_me:$LINENO: result: $USE_NLS" >&5
+  echo "$as_me:$LINENO: result: $USE_NLS" >&5
 echo "${ECHO_T}$USE_NLS" >&6
 
 
-    USE_INCLUDED_LIBINTL=no
 
-        if test "$USE_NLS" = "yes"; then
-      echo "$as_me:$LINENO: checking whether included gettext is requested" >&5
-echo $ECHO_N "checking whether included gettext is requested... $ECHO_C" >&6
 
-# Check whether --with-included-gettext or --without-included-gettext was given.
-if test "${with_included_gettext+set}" = set; then
-  withval="$with_included_gettext"
-  nls_cv_force_use_gnu_gettext=$withval
-else
-  nls_cv_force_use_gnu_gettext=no
-fi;
-      echo "$as_me:$LINENO: result: $nls_cv_force_use_gnu_gettext" >&5
-echo "${ECHO_T}$nls_cv_force_use_gnu_gettext" >&6
-
-      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
-      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
-                        		nls_cv_header_intl=
-	nls_cv_header_libgt=
-	CATOBJEXT=
-
-	if test "${ac_cv_header_libintl_h+set}" = set; then
-  echo "$as_me:$LINENO: checking for libintl.h" >&5
-echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6
-if test "${ac_cv_header_libintl_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5
-echo "${ECHO_T}$ac_cv_header_libintl_h" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking libintl.h usability" >&5
-echo $ECHO_N "checking libintl.h usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <libintl.h>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
 
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
 
-# Is the header present?
-echo "$as_me:$LINENO: checking libintl.h presence" >&5
-echo $ECHO_N "checking libintl.h presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <libintl.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+# Prepare PATH_SEPARATOR.
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  echo "#! /bin/sh" >conf$$.sh
+  echo  "exit 0"   >>conf$$.sh
+  chmod +x conf$$.sh
+  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+    PATH_SEPARATOR=';'
   else
-    ac_cpp_err=
+    PATH_SEPARATOR=:
   fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: libintl.h: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: libintl.h: present but cannot be compiled" >&5
-echo "$as_me: WARNING: libintl.h: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: libintl.h:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: libintl.h: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: libintl.h:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: libintl.h: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: libintl.h: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for libintl.h" >&5
-echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6
-if test "${ac_cv_header_libintl_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_header_libintl_h=$ac_header_preproc
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5
-echo "${ECHO_T}$ac_cv_header_libintl_h" >&6
-
-fi
-if test $ac_cv_header_libintl_h = yes; then
-  echo "$as_me:$LINENO: checking for gettext in libc" >&5
-echo $ECHO_N "checking for gettext in libc... $ECHO_C" >&6
-if test "${gt_cv_func_gettext_libc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <libintl.h>
-int
-main ()
-{
-return (int) gettext ("")
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  gt_cv_func_gettext_libc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-gt_cv_func_gettext_libc=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libc" >&5
-echo "${ECHO_T}$gt_cv_func_gettext_libc" >&6
-
-	   if test "$gt_cv_func_gettext_libc" != "yes"; then
-	     echo "$as_me:$LINENO: checking for bindtextdomain in -lintl" >&5
-echo $ECHO_N "checking for bindtextdomain in -lintl... $ECHO_C" >&6
-if test "${ac_cv_lib_intl_bindtextdomain+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lintl  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char bindtextdomain ();
-int
-main ()
-{
-bindtextdomain ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_intl_bindtextdomain=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_intl_bindtextdomain=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
+  rm -f conf$$.sh
 fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_intl_bindtextdomain" >&5
-echo "${ECHO_T}$ac_cv_lib_intl_bindtextdomain" >&6
-if test $ac_cv_lib_intl_bindtextdomain = yes; then
-  echo "$as_me:$LINENO: checking for gettext in libintl" >&5
-echo $ECHO_N "checking for gettext in libintl... $ECHO_C" >&6
-if test "${gt_cv_func_gettext_libintl+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
 
-int
-main ()
-{
-return (int) gettext ("")
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  gt_cv_func_gettext_libintl=yes
+# Find out how to test for executable files. Don't use a zero-byte file,
+# as systems may use methods other than mode bits to determine executability.
+cat >conf$$.file <<_ASEOF
+#! /bin/sh
+exit 0
+_ASEOF
+chmod +x conf$$.file
+if test -x conf$$.file >/dev/null 2>&1; then
+  ac_executable_p="test -x"
 else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-gt_cv_func_gettext_libintl=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libintl" >&5
-echo "${ECHO_T}$gt_cv_func_gettext_libintl" >&6
+  ac_executable_p="test -f"
 fi
+rm -f conf$$.file
 
-	   fi
-
-	   if test "$gt_cv_func_gettext_libc" = "yes" \
-	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_GETTEXT 1
-_ACEOF
-
-	      # Extract the first word of "msgfmt", so it can be a program name with args.
+# Extract the first word of "msgfmt", so it can be a program name with args.
 set dummy msgfmt; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
@@ -8700,137 +11763,39 @@ if test "${ac_cv_path_MSGFMT+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
+  [\\/]* | ?:[\\/]*)
+    ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+    ;;
   *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
-  ;;
+    ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR
+    for ac_dir in $PATH; do
+      IFS="$ac_save_IFS"
+      test -z "$ac_dir" && ac_dir=.
+      for ac_exec_ext in '' $ac_executable_extensions; do
+        if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then
+          if $ac_dir/$ac_word --statistics /dev/null >/dev/null 2>&1 &&
+     (if $ac_dir/$ac_word --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then
+            ac_cv_path_MSGFMT="$ac_dir/$ac_word$ac_exec_ext"
+            break 2
+          fi
+        fi
+      done
+    done
+    IFS="$ac_save_IFS"
+  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT=":"
+    ;;
 esac
 fi
 MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
+if test "$MSGFMT" != ":"; then
   echo "$as_me:$LINENO: result: $MSGFMT" >&5
 echo "${ECHO_T}$MSGFMT" >&6
 else
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
 fi
-	      if test "$MSGFMT" != "no"; then
-
-for ac_func in dcgettext
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
 
-		# Extract the first word of "gmsgfmt", so it can be a program name with args.
+  # Extract the first word of "gmsgfmt", so it can be a program name with args.
 set dummy gmsgfmt; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
@@ -8870,7 +11835,37 @@ else
 echo "${ECHO_T}no" >&6
 fi
 
-		# Extract the first word of "xgettext", so it can be a program name with args.
+
+
+# Prepare PATH_SEPARATOR.
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  echo "#! /bin/sh" >conf$$.sh
+  echo  "exit 0"   >>conf$$.sh
+  chmod +x conf$$.sh
+  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+    PATH_SEPARATOR=';'
+  else
+    PATH_SEPARATOR=:
+  fi
+  rm -f conf$$.sh
+fi
+
+# Find out how to test for executable files. Don't use a zero-byte file,
+# as systems may use methods other than mode bits to determine executability.
+cat >conf$$.file <<_ASEOF
+#! /bin/sh
+exit 0
+_ASEOF
+chmod +x conf$$.file
+if test -x conf$$.file >/dev/null 2>&1; then
+  ac_executable_p="test -x"
+else
+  ac_executable_p="test -f"
+fi
+rm -f conf$$.file
+
+# Extract the first word of "xgettext", so it can be a program name with args.
 set dummy xgettext; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
@@ -8878,27 +11873,31 @@ if test "${ac_cv_path_XGETTEXT+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
+  [\\/]* | ?:[\\/]*)
+    ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+    ;;
   *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
+    ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR
+    for ac_dir in $PATH; do
+      IFS="$ac_save_IFS"
+      test -z "$ac_dir" && ac_dir=.
+      for ac_exec_ext in '' $ac_executable_extensions; do
+        if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then
+          if $ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 &&
+     (if $ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then
+            ac_cv_path_XGETTEXT="$ac_dir/$ac_word$ac_exec_ext"
+            break 2
+          fi
+        fi
+      done
+    done
+    IFS="$ac_save_IFS"
   test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
+    ;;
 esac
 fi
 XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
+if test "$XGETTEXT" != ":"; then
   echo "$as_me:$LINENO: result: $XGETTEXT" >&5
 echo "${ECHO_T}$XGETTEXT" >&6
 else
@@ -8906,461 +11905,103 @@ else
 echo "${ECHO_T}no" >&6
 fi
 
-		cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-extern int _nl_msg_cat_cntr;
-			       return _nl_msg_cat_cntr
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  CATOBJEXT=.gmo
-		   DATADIRNAME=share
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-CATOBJEXT=.mo
-		   DATADIRNAME=lib
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-		INSTOBJEXT=.mo
-	      fi
-	    fi
-
-fi
-
-
+    rm -f messages.po
 
 
-        if test x"$CATOBJEXT" = x && test -d $srcdir/../intl; then
-	  # Neither gettext nor catgets in included in the C library.
-	  # Fall back on GNU gettext library (assuming it is present).
-	  nls_cv_use_gnu_gettext=yes
-        fi
-      fi
-
-      if test "$nls_cv_use_gnu_gettext" = "yes"; then
-                INTLOBJS="\$(GETTOBJS)"
-        # Extract the first word of "msgfmt", so it can be a program name with args.
-set dummy msgfmt; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_MSGFMT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
-  ;;
-esac
-fi
-MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
-  echo "$as_me:$LINENO: result: $MSGFMT" >&5
-echo "${ECHO_T}$MSGFMT" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-        # Extract the first word of "gmsgfmt", so it can be a program name with args.
-set dummy gmsgfmt; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_GMSGFMT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case $GMSGFMT in
-  [\\/]* | ?:[\\/]*)
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_path_GMSGFMT="$as_dir/$ac_word$ac_exec_ext"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
+# Prepare PATH_SEPARATOR.
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  echo "#! /bin/sh" >conf$$.sh
+  echo  "exit 0"   >>conf$$.sh
+  chmod +x conf$$.sh
+  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+    PATH_SEPARATOR=';'
+  else
+    PATH_SEPARATOR=:
   fi
-done
-done
-
-  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
-  ;;
-esac
+  rm -f conf$$.sh
 fi
-GMSGFMT=$ac_cv_path_GMSGFMT
 
-if test -n "$GMSGFMT"; then
-  echo "$as_me:$LINENO: result: $GMSGFMT" >&5
-echo "${ECHO_T}$GMSGFMT" >&6
+# Find out how to test for executable files. Don't use a zero-byte file,
+# as systems may use methods other than mode bits to determine executability.
+cat >conf$$.file <<_ASEOF
+#! /bin/sh
+exit 0
+_ASEOF
+chmod +x conf$$.file
+if test -x conf$$.file >/dev/null 2>&1; then
+  ac_executable_p="test -x"
 else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
+  ac_executable_p="test -f"
 fi
+rm -f conf$$.file
 
-        # Extract the first word of "xgettext", so it can be a program name with args.
-set dummy xgettext; ac_word=$2
+# Extract the first word of "msgmerge", so it can be a program name with args.
+set dummy msgmerge; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_XGETTEXT+set}" = set; then
+if test "${ac_cv_path_MSGMERGE+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
+  case "$MSGMERGE" in
+  [\\/]* | ?:[\\/]*)
+    ac_cv_path_MSGMERGE="$MSGMERGE" # Let the user override the test with a path.
+    ;;
   *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
+    ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR
+    for ac_dir in $PATH; do
+      IFS="$ac_save_IFS"
+      test -z "$ac_dir" && ac_dir=.
+      for ac_exec_ext in '' $ac_executable_extensions; do
+        if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then
+          if $ac_dir/$ac_word --update -q /dev/null /dev/null >/dev/null 2>&1; then
+            ac_cv_path_MSGMERGE="$ac_dir/$ac_word$ac_exec_ext"
+            break 2
+          fi
+        fi
+      done
+    done
+    IFS="$ac_save_IFS"
+  test -z "$ac_cv_path_MSGMERGE" && ac_cv_path_MSGMERGE=":"
+    ;;
 esac
 fi
-XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
-  echo "$as_me:$LINENO: result: $XGETTEXT" >&5
-echo "${ECHO_T}$XGETTEXT" >&6
+MSGMERGE="$ac_cv_path_MSGMERGE"
+if test "$MSGMERGE" != ":"; then
+  echo "$as_me:$LINENO: result: $MSGMERGE" >&5
+echo "${ECHO_T}$MSGMERGE" >&6
 else
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
 fi
 
 
-	USE_INCLUDED_LIBINTL=yes
-        CATOBJEXT=.gmo
-        INSTOBJEXT=.mo
-        DATADIRNAME=share
-	INTLDEPS='$(top_builddir)/../intl/libintl.a'
-	INTLLIBS=$INTLDEPS
-	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
-        nls_cv_header_intl=libintl.h
-        nls_cv_header_libgt=libgettext.h
-      fi
-
-            if test "$XGETTEXT" != ":"; then
-			if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
-	  : ;
-	else
-	  echo "$as_me:$LINENO: result: found xgettext programs is not GNU xgettext; ignore it" >&5
-echo "${ECHO_T}found xgettext programs is not GNU xgettext; ignore it" >&6
-	  XGETTEXT=":"
-	fi
-      fi
-
-      # We need to process the po/ directory.
-      POSUB=po
+      if test "$GMSGFMT" != ":"; then
+            if $GMSGFMT --statistics /dev/null >/dev/null 2>&1 &&
+       (if $GMSGFMT --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then
+      : ;
     else
-      DATADIRNAME=share
-      nls_cv_header_intl=libintl.h
-      nls_cv_header_libgt=libgettext.h
-    fi
-
-    # If this is used in GNU gettext we have to set USE_NLS to `yes'
-    # because some of the sources are only built for this goal.
-    if test "$PACKAGE" = gettext; then
-      USE_NLS=yes
-      USE_INCLUDED_LIBINTL=yes
+      GMSGFMT=`echo "$GMSGFMT" | sed -e 's,^.*/,,'`
+      echo "$as_me:$LINENO: result: found $GMSGFMT program is not GNU msgfmt; ignore it" >&5
+echo "${ECHO_T}found $GMSGFMT program is not GNU msgfmt; ignore it" >&6
+      GMSGFMT=":"
     fi
+  fi
 
-                for lang in $ALL_LINGUAS; do
-      GMOFILES="$GMOFILES $lang.gmo"
-      POFILES="$POFILES $lang.po"
-    done
-
-
-
-
-
-
-
-
-
-
-
-
-    if test "x$CATOBJEXT" != "x"; then
-
-cat >>confdefs.h <<\_ACEOF
-#define ENABLE_NLS 1
-_ACEOF
-
+      if test "$XGETTEXT" != ":"; then
+            if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 &&
+       (if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then
+      : ;
+    else
+      echo "$as_me:$LINENO: result: found xgettext program is not GNU xgettext; ignore it" >&5
+echo "${ECHO_T}found xgettext program is not GNU xgettext; ignore it" >&6
+      XGETTEXT=":"
     fi
-
-
-   if test "x$CATOBJEXT" != "x"; then
-     if test "x$ALL_LINGUAS" = "x"; then
-       LINGUAS=
-     else
-       echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
-echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6
-       NEW_LINGUAS=
-       for lang in ${LINGUAS=$ALL_LINGUAS}; do
-         case "$ALL_LINGUAS" in
-          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
-         esac
-       done
-       LINGUAS=$NEW_LINGUAS
-       echo "$as_me:$LINENO: result: $LINGUAS" >&5
-echo "${ECHO_T}$LINGUAS" >&6
-     fi
-
-          if test -n "$LINGUAS"; then
-       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
-     fi
-   fi
-
-            if test $ac_cv_header_locale_h = yes; then
-     INCLUDE_LOCALE_H="#include <locale.h>"
-   else
-     INCLUDE_LOCALE_H="\
-/* The system does not provide the header <locale.h>.  Take care yourself.  */"
-   fi
-
-
-            if test -f $srcdir/po2tbl.sed.in; then
-      if test "$CATOBJEXT" = ".cat"; then
-	 if test "${ac_cv_header_linux_version_h+set}" = set; then
-  echo "$as_me:$LINENO: checking for linux/version.h" >&5
-echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6
-if test "${ac_cv_header_linux_version_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5
-echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking linux/version.h usability" >&5
-echo $ECHO_N "checking linux/version.h usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <linux/version.h>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking linux/version.h presence" >&5
-echo $ECHO_N "checking linux/version.h presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <linux/version.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
+        rm -f messages.po
   fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
 
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
+            ac_config_commands="$ac_config_commands default-1"
 
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: linux/version.h: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: present but cannot be compiled" >&5
-echo "$as_me: WARNING: linux/version.h: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: linux/version.h:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: linux/version.h: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: linux/version.h:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: linux/version.h: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: linux/version.h: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for linux/version.h" >&5
-echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6
-if test "${ac_cv_header_linux_version_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_header_linux_version_h=$ac_header_preproc
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5
-echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6
-
-fi
-if test $ac_cv_header_linux_version_h = yes; then
-  msgformat=linux
-else
-  msgformat=xopen
-fi
-
-
-
-	          	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
-      fi
-            sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
-	 $srcdir/po2tbl.sed.in > po2tbl.sed
-   fi
-
-            if test "$PACKAGE" = "gettext"; then
-     GT_NO="#NO#"
-     GT_YES=
-   else
-     GT_NO=
-     GT_YES="#YES#"
-   fi
-
-
-
-   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
-
-
-      l=
-
-
-            if test -f $srcdir/po/POTFILES.in; then
-      test -d po || mkdir po
-      if test "x$srcdir" != "x."; then
-	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
-	    posrcprefix="$srcdir/"
-	 else
-	    posrcprefix="../$srcdir/"
-	 fi
-      else
-	 posrcprefix="../"
-      fi
-      rm -f po/POTFILES
-      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
-	 < $srcdir/po/POTFILES.in > po/POTFILES
-   fi
 
 
 echo "$as_me:$LINENO: checking whether to enable maintainer-specific portions of Makefiles" >&5
@@ -9389,6 +12030,16 @@ fi
 
 
 
+if false; then
+  GENINSRC_NEVER_TRUE=
+  GENINSRC_NEVER_FALSE='#'
+else
+  GENINSRC_NEVER_TRUE='#'
+  GENINSRC_NEVER_FALSE=
+fi
+
+
+
 
 
 
@@ -10211,8 +12862,7 @@ yes)
   LIBM=
 case $host in
 *-*-beos* | *-*-cygwin* | *-*-pw32* | *-*-darwin*)
-  # These system don't have libm
-  # on darwin the libm is a symbolic link to libSystem.dylib
+  # These system don't have libm, or don't need it
   ;;
 *-ncr-sysv4.3*)
   echo "$as_me:$LINENO: checking for _mwvalidcheckl in -lmw" >&5
@@ -10283,9 +12933,9 @@ if test $ac_cv_lib_mw__mwvalidcheckl = yes; then
   LIBM="-lmw"
 fi
 
-  echo "$as_me:$LINENO: checking for main in -lm" >&5
-echo $ECHO_N "checking for main in -lm... $ECHO_C" >&6
-if test "${ac_cv_lib_m_main+set}" = set; then
+  echo "$as_me:$LINENO: checking for cos in -lm" >&5
+echo $ECHO_N "checking for cos in -lm... $ECHO_C" >&6
+if test "${ac_cv_lib_m_cos+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   ac_check_lib_save_LIBS=$LIBS
@@ -10297,11 +12947,17 @@ cat confdefs.h >>conftest.$ac_ext
 cat >>conftest.$ac_ext <<_ACEOF
 /* end confdefs.h.  */
 
-
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char cos ();
 int
 main ()
 {
-main ();
+cos ();
   ;
   return 0;
 }
@@ -10328,28 +12984,28 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; }; then
-  ac_cv_lib_m_main=yes
+  ac_cv_lib_m_cos=yes
 else
   echo "$as_me: failed program was:" >&5
 sed 's/^/| /' conftest.$ac_ext >&5
 
-ac_cv_lib_m_main=no
+ac_cv_lib_m_cos=no
 fi
 rm -f conftest.err conftest.$ac_objext \
       conftest$ac_exeext conftest.$ac_ext
 LIBS=$ac_check_lib_save_LIBS
 fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_m_main" >&5
-echo "${ECHO_T}$ac_cv_lib_m_main" >&6
-if test $ac_cv_lib_m_main = yes; then
+echo "$as_me:$LINENO: result: $ac_cv_lib_m_cos" >&5
+echo "${ECHO_T}$ac_cv_lib_m_cos" >&6
+if test $ac_cv_lib_m_cos = yes; then
   LIBM="$LIBM -lm"
 fi
 
   ;;
 *)
-  echo "$as_me:$LINENO: checking for main in -lm" >&5
-echo $ECHO_N "checking for main in -lm... $ECHO_C" >&6
-if test "${ac_cv_lib_m_main+set}" = set; then
+  echo "$as_me:$LINENO: checking for cos in -lm" >&5
+echo $ECHO_N "checking for cos in -lm... $ECHO_C" >&6
+if test "${ac_cv_lib_m_cos+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   ac_check_lib_save_LIBS=$LIBS
@@ -10361,11 +13017,17 @@ cat confdefs.h >>conftest.$ac_ext
 cat >>conftest.$ac_ext <<_ACEOF
 /* end confdefs.h.  */
 
-
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char cos ();
 int
 main ()
 {
-main ();
+cos ();
   ;
   return 0;
 }
@@ -10392,20 +13054,20 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; }; then
-  ac_cv_lib_m_main=yes
+  ac_cv_lib_m_cos=yes
 else
   echo "$as_me: failed program was:" >&5
 sed 's/^/| /' conftest.$ac_ext >&5
 
-ac_cv_lib_m_main=no
+ac_cv_lib_m_cos=no
 fi
 rm -f conftest.err conftest.$ac_objext \
       conftest$ac_exeext conftest.$ac_ext
 LIBS=$ac_check_lib_save_LIBS
 fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_m_main" >&5
-echo "${ECHO_T}$ac_cv_lib_m_main" >&6
-if test $ac_cv_lib_m_main = yes; then
+echo "$as_me:$LINENO: result: $ac_cv_lib_m_cos" >&5
+echo "${ECHO_T}$ac_cv_lib_m_cos" >&6
+if test $ac_cv_lib_m_cos = yes; then
   LIBM="-lm"
 fi
 
@@ -10413,6 +13075,7 @@ fi
 esac
 
 
+
   ;;
 esac
 
@@ -11124,6 +13787,16 @@ fi
 
 
 
+case "${host}" in
+*-*-msdos* | *-*-go32* | *-*-mingw32* | *-*-cygwin* | *-*-windows*)
+
+cat >>confdefs.h <<\_ACEOF
+#define USE_BINARY_FOPEN 1
+_ACEOF
+ ;;
+esac
+
+
 
 
 
@@ -11246,6 +13919,13 @@ echo "$as_me: error: conditional \"MAINTAINER_MODE\" was never defined.
 Usually this means the macro was only invoked conditionally." >&2;}
    { (exit 1); exit 1; }; }
 fi
+if test -z "${GENINSRC_NEVER_TRUE}" && test -z "${GENINSRC_NEVER_FALSE}"; then
+  { { echo "$as_me:$LINENO: error: conditional \"GENINSRC_NEVER\" was never defined.
+Usually this means the macro was only invoked conditionally." >&5
+echo "$as_me: error: conditional \"GENINSRC_NEVER\" was never defined.
+Usually this means the macro was only invoked conditionally." >&2;}
+   { (exit 1); exit 1; }; }
+fi
 
 : ${CONFIG_STATUS=./config.status}
 ac_clean_files_save=$ac_clean_files
@@ -11680,6 +14360,254 @@ cat >>$CONFIG_STATUS <<_ACEOF
 #
 
 AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"
+
+
+# The HP-UX ksh and POSIX shell print the target directory to stdout
+# if CDPATH is set.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+sed_quote_subst='$sed_quote_subst'
+double_quote_subst='$double_quote_subst'
+delay_variable_subst='$delay_variable_subst'
+macro_version='`$ECHO "X$macro_version" | $Xsed -e "$delay_single_quote_subst"`'
+macro_revision='`$ECHO "X$macro_revision" | $Xsed -e "$delay_single_quote_subst"`'
+enable_shared='`$ECHO "X$enable_shared" | $Xsed -e "$delay_single_quote_subst"`'
+enable_static='`$ECHO "X$enable_static" | $Xsed -e "$delay_single_quote_subst"`'
+pic_mode='`$ECHO "X$pic_mode" | $Xsed -e "$delay_single_quote_subst"`'
+enable_fast_install='`$ECHO "X$enable_fast_install" | $Xsed -e "$delay_single_quote_subst"`'
+host_alias='`$ECHO "X$host_alias" | $Xsed -e "$delay_single_quote_subst"`'
+host='`$ECHO "X$host" | $Xsed -e "$delay_single_quote_subst"`'
+host_os='`$ECHO "X$host_os" | $Xsed -e "$delay_single_quote_subst"`'
+build_alias='`$ECHO "X$build_alias" | $Xsed -e "$delay_single_quote_subst"`'
+build='`$ECHO "X$build" | $Xsed -e "$delay_single_quote_subst"`'
+build_os='`$ECHO "X$build_os" | $Xsed -e "$delay_single_quote_subst"`'
+SED='`$ECHO "X$SED" | $Xsed -e "$delay_single_quote_subst"`'
+Xsed='`$ECHO "X$Xsed" | $Xsed -e "$delay_single_quote_subst"`'
+GREP='`$ECHO "X$GREP" | $Xsed -e "$delay_single_quote_subst"`'
+EGREP='`$ECHO "X$EGREP" | $Xsed -e "$delay_single_quote_subst"`'
+FGREP='`$ECHO "X$FGREP" | $Xsed -e "$delay_single_quote_subst"`'
+LD='`$ECHO "X$LD" | $Xsed -e "$delay_single_quote_subst"`'
+NM='`$ECHO "X$NM" | $Xsed -e "$delay_single_quote_subst"`'
+LN_S='`$ECHO "X$LN_S" | $Xsed -e "$delay_single_quote_subst"`'
+max_cmd_len='`$ECHO "X$max_cmd_len" | $Xsed -e "$delay_single_quote_subst"`'
+ac_objext='`$ECHO "X$ac_objext" | $Xsed -e "$delay_single_quote_subst"`'
+exeext='`$ECHO "X$exeext" | $Xsed -e "$delay_single_quote_subst"`'
+lt_unset='`$ECHO "X$lt_unset" | $Xsed -e "$delay_single_quote_subst"`'
+lt_SP2NL='`$ECHO "X$lt_SP2NL" | $Xsed -e "$delay_single_quote_subst"`'
+lt_NL2SP='`$ECHO "X$lt_NL2SP" | $Xsed -e "$delay_single_quote_subst"`'
+reload_flag='`$ECHO "X$reload_flag" | $Xsed -e "$delay_single_quote_subst"`'
+reload_cmds='`$ECHO "X$reload_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+deplibs_check_method='`$ECHO "X$deplibs_check_method" | $Xsed -e "$delay_single_quote_subst"`'
+file_magic_cmd='`$ECHO "X$file_magic_cmd" | $Xsed -e "$delay_single_quote_subst"`'
+AR='`$ECHO "X$AR" | $Xsed -e "$delay_single_quote_subst"`'
+AR_FLAGS='`$ECHO "X$AR_FLAGS" | $Xsed -e "$delay_single_quote_subst"`'
+STRIP='`$ECHO "X$STRIP" | $Xsed -e "$delay_single_quote_subst"`'
+RANLIB='`$ECHO "X$RANLIB" | $Xsed -e "$delay_single_quote_subst"`'
+old_postinstall_cmds='`$ECHO "X$old_postinstall_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+old_postuninstall_cmds='`$ECHO "X$old_postuninstall_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+old_archive_cmds='`$ECHO "X$old_archive_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+CC='`$ECHO "X$CC" | $Xsed -e "$delay_single_quote_subst"`'
+CFLAGS='`$ECHO "X$CFLAGS" | $Xsed -e "$delay_single_quote_subst"`'
+compiler='`$ECHO "X$compiler" | $Xsed -e "$delay_single_quote_subst"`'
+GCC='`$ECHO "X$GCC" | $Xsed -e "$delay_single_quote_subst"`'
+lt_cv_sys_global_symbol_pipe='`$ECHO "X$lt_cv_sys_global_symbol_pipe" | $Xsed -e "$delay_single_quote_subst"`'
+lt_cv_sys_global_symbol_to_cdecl='`$ECHO "X$lt_cv_sys_global_symbol_to_cdecl" | $Xsed -e "$delay_single_quote_subst"`'
+lt_cv_sys_global_symbol_to_c_name_address='`$ECHO "X$lt_cv_sys_global_symbol_to_c_name_address" | $Xsed -e "$delay_single_quote_subst"`'
+objdir='`$ECHO "X$objdir" | $Xsed -e "$delay_single_quote_subst"`'
+SHELL='`$ECHO "X$SHELL" | $Xsed -e "$delay_single_quote_subst"`'
+ECHO='`$ECHO "X$ECHO" | $Xsed -e "$delay_single_quote_subst"`'
+MAGIC_CMD='`$ECHO "X$MAGIC_CMD" | $Xsed -e "$delay_single_quote_subst"`'
+lt_prog_compiler_no_builtin_flag='`$ECHO "X$lt_prog_compiler_no_builtin_flag" | $Xsed -e "$delay_single_quote_subst"`'
+lt_prog_compiler_wl='`$ECHO "X$lt_prog_compiler_wl" | $Xsed -e "$delay_single_quote_subst"`'
+lt_prog_compiler_pic='`$ECHO "X$lt_prog_compiler_pic" | $Xsed -e "$delay_single_quote_subst"`'
+lt_prog_compiler_static='`$ECHO "X$lt_prog_compiler_static" | $Xsed -e "$delay_single_quote_subst"`'
+lt_cv_prog_compiler_c_o='`$ECHO "X$lt_cv_prog_compiler_c_o" | $Xsed -e "$delay_single_quote_subst"`'
+need_locks='`$ECHO "X$need_locks" | $Xsed -e "$delay_single_quote_subst"`'
+libext='`$ECHO "X$libext" | $Xsed -e "$delay_single_quote_subst"`'
+shrext_cmds='`$ECHO "X$shrext_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+extract_expsyms_cmds='`$ECHO "X$extract_expsyms_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+archive_cmds_need_lc='`$ECHO "X$archive_cmds_need_lc" | $Xsed -e "$delay_single_quote_subst"`'
+enable_shared_with_static_runtimes='`$ECHO "X$enable_shared_with_static_runtimes" | $Xsed -e "$delay_single_quote_subst"`'
+export_dynamic_flag_spec='`$ECHO "X$export_dynamic_flag_spec" | $Xsed -e "$delay_single_quote_subst"`'
+whole_archive_flag_spec='`$ECHO "X$whole_archive_flag_spec" | $Xsed -e "$delay_single_quote_subst"`'
+compiler_needs_object='`$ECHO "X$compiler_needs_object" | $Xsed -e "$delay_single_quote_subst"`'
+old_archive_from_new_cmds='`$ECHO "X$old_archive_from_new_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+old_archive_from_expsyms_cmds='`$ECHO "X$old_archive_from_expsyms_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+archive_cmds='`$ECHO "X$archive_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+archive_expsym_cmds='`$ECHO "X$archive_expsym_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+module_cmds='`$ECHO "X$module_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+module_expsym_cmds='`$ECHO "X$module_expsym_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+with_gnu_ld='`$ECHO "X$with_gnu_ld" | $Xsed -e "$delay_single_quote_subst"`'
+allow_undefined_flag='`$ECHO "X$allow_undefined_flag" | $Xsed -e "$delay_single_quote_subst"`'
+no_undefined_flag='`$ECHO "X$no_undefined_flag" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_libdir_flag_spec='`$ECHO "X$hardcode_libdir_flag_spec" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_libdir_flag_spec_ld='`$ECHO "X$hardcode_libdir_flag_spec_ld" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_libdir_separator='`$ECHO "X$hardcode_libdir_separator" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_direct='`$ECHO "X$hardcode_direct" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_direct_absolute='`$ECHO "X$hardcode_direct_absolute" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_minus_L='`$ECHO "X$hardcode_minus_L" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_shlibpath_var='`$ECHO "X$hardcode_shlibpath_var" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_automatic='`$ECHO "X$hardcode_automatic" | $Xsed -e "$delay_single_quote_subst"`'
+inherit_rpath='`$ECHO "X$inherit_rpath" | $Xsed -e "$delay_single_quote_subst"`'
+link_all_deplibs='`$ECHO "X$link_all_deplibs" | $Xsed -e "$delay_single_quote_subst"`'
+fix_srcfile_path='`$ECHO "X$fix_srcfile_path" | $Xsed -e "$delay_single_quote_subst"`'
+always_export_symbols='`$ECHO "X$always_export_symbols" | $Xsed -e "$delay_single_quote_subst"`'
+export_symbols_cmds='`$ECHO "X$export_symbols_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+exclude_expsyms='`$ECHO "X$exclude_expsyms" | $Xsed -e "$delay_single_quote_subst"`'
+include_expsyms='`$ECHO "X$include_expsyms" | $Xsed -e "$delay_single_quote_subst"`'
+prelink_cmds='`$ECHO "X$prelink_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+file_list_spec='`$ECHO "X$file_list_spec" | $Xsed -e "$delay_single_quote_subst"`'
+variables_saved_for_relink='`$ECHO "X$variables_saved_for_relink" | $Xsed -e "$delay_single_quote_subst"`'
+need_lib_prefix='`$ECHO "X$need_lib_prefix" | $Xsed -e "$delay_single_quote_subst"`'
+need_version='`$ECHO "X$need_version" | $Xsed -e "$delay_single_quote_subst"`'
+version_type='`$ECHO "X$version_type" | $Xsed -e "$delay_single_quote_subst"`'
+runpath_var='`$ECHO "X$runpath_var" | $Xsed -e "$delay_single_quote_subst"`'
+shlibpath_var='`$ECHO "X$shlibpath_var" | $Xsed -e "$delay_single_quote_subst"`'
+shlibpath_overrides_runpath='`$ECHO "X$shlibpath_overrides_runpath" | $Xsed -e "$delay_single_quote_subst"`'
+libname_spec='`$ECHO "X$libname_spec" | $Xsed -e "$delay_single_quote_subst"`'
+library_names_spec='`$ECHO "X$library_names_spec" | $Xsed -e "$delay_single_quote_subst"`'
+soname_spec='`$ECHO "X$soname_spec" | $Xsed -e "$delay_single_quote_subst"`'
+postinstall_cmds='`$ECHO "X$postinstall_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+postuninstall_cmds='`$ECHO "X$postuninstall_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+finish_cmds='`$ECHO "X$finish_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+finish_eval='`$ECHO "X$finish_eval" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_into_libs='`$ECHO "X$hardcode_into_libs" | $Xsed -e "$delay_single_quote_subst"`'
+sys_lib_search_path_spec='`$ECHO "X$sys_lib_search_path_spec" | $Xsed -e "$delay_single_quote_subst"`'
+sys_lib_dlsearch_path_spec='`$ECHO "X$sys_lib_dlsearch_path_spec" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_action='`$ECHO "X$hardcode_action" | $Xsed -e "$delay_single_quote_subst"`'
+enable_dlopen='`$ECHO "X$enable_dlopen" | $Xsed -e "$delay_single_quote_subst"`'
+enable_dlopen_self='`$ECHO "X$enable_dlopen_self" | $Xsed -e "$delay_single_quote_subst"`'
+enable_dlopen_self_static='`$ECHO "X$enable_dlopen_self_static" | $Xsed -e "$delay_single_quote_subst"`'
+old_striplib='`$ECHO "X$old_striplib" | $Xsed -e "$delay_single_quote_subst"`'
+striplib='`$ECHO "X$striplib" | $Xsed -e "$delay_single_quote_subst"`'
+
+LTCC='$LTCC'
+LTCFLAGS='$LTCFLAGS'
+compiler='$compiler_DEFAULT'
+
+# Quote evaled strings.
+for var in SED \
+GREP \
+EGREP \
+FGREP \
+LD \
+NM \
+LN_S \
+lt_SP2NL \
+lt_NL2SP \
+reload_flag \
+deplibs_check_method \
+file_magic_cmd \
+AR \
+AR_FLAGS \
+STRIP \
+RANLIB \
+CC \
+CFLAGS \
+compiler \
+lt_cv_sys_global_symbol_pipe \
+lt_cv_sys_global_symbol_to_cdecl \
+lt_cv_sys_global_symbol_to_c_name_address \
+SHELL \
+ECHO \
+lt_prog_compiler_no_builtin_flag \
+lt_prog_compiler_wl \
+lt_prog_compiler_pic \
+lt_prog_compiler_static \
+lt_cv_prog_compiler_c_o \
+need_locks \
+shrext_cmds \
+export_dynamic_flag_spec \
+whole_archive_flag_spec \
+compiler_needs_object \
+with_gnu_ld \
+allow_undefined_flag \
+no_undefined_flag \
+hardcode_libdir_flag_spec \
+hardcode_libdir_flag_spec_ld \
+hardcode_libdir_separator \
+fix_srcfile_path \
+exclude_expsyms \
+include_expsyms \
+file_list_spec \
+variables_saved_for_relink \
+libname_spec \
+library_names_spec \
+soname_spec \
+finish_eval \
+old_striplib \
+striplib; do
+    case \`eval \\\\\$ECHO "X\\\\\$\$var"\` in
+    *[\\\\\\\`\\"\\\$]*)
+      eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"X\\\$\$var\\" | \\\$Xsed -e \\"\\\$sed_quote_subst\\"\\\`\\\\\\""
+      ;;
+    *)
+      eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\""
+      ;;
+    esac
+done
+
+# Double-quote double-evaled strings.
+for var in reload_cmds \
+old_postinstall_cmds \
+old_postuninstall_cmds \
+old_archive_cmds \
+extract_expsyms_cmds \
+old_archive_from_new_cmds \
+old_archive_from_expsyms_cmds \
+archive_cmds \
+archive_expsym_cmds \
+module_cmds \
+module_expsym_cmds \
+export_symbols_cmds \
+prelink_cmds \
+postinstall_cmds \
+postuninstall_cmds \
+finish_cmds \
+sys_lib_search_path_spec \
+sys_lib_dlsearch_path_spec; do
+    case \`eval \\\\\$ECHO "X\\\\\$\$var"\` in
+    *[\\\\\\\`\\"\\\$]*)
+      eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"X\\\$\$var\\" | \\\$Xsed -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\""
+      ;;
+    *)
+      eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\""
+      ;;
+    esac
+done
+
+# Fix-up fallback echo if it was mangled by the above quoting rules.
+case \$lt_ECHO in
+*'\\\$0 --fallback-echo"')  lt_ECHO=\`\$ECHO "X\$lt_ECHO" | \$Xsed -e 's/\\\\\\\\\\\\\\\$0 --fallback-echo"\$/\$0 --fallback-echo"/'\`
+  ;;
+esac
+
+ac_aux_dir='$ac_aux_dir'
+xsi_shell='$xsi_shell'
+lt_shell_append='$lt_shell_append'
+
+# See if we are running on zsh, and set the options which allow our
+# commands through without removal of \ escapes INIT.
+if test -n "\${ZSH_VERSION+set}" ; then
+   setopt NO_GLOB_SUBST
+fi
+
+
+    PACKAGE='$PACKAGE'
+    VERSION='$VERSION'
+    TIMESTAMP='$TIMESTAMP'
+    RM='$RM'
+    ofile='$ofile'
+
+
+
+# Capture the value of obsolete ALL_LINGUAS because we need it to compute
+    # POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES, CATALOGS. But hide it
+    # from automake.
+    eval 'OBSOLETE_ALL_LINGUAS''="$ALL_LINGUAS"'
+    # Capture the value of LINGUAS because we need it to compute CATALOGS.
+    LINGUAS="${LINGUAS-%UNSET%}"
+
 target_cpu_type=${target_cpu_type}
  cgen_cpu_prefix=${cgen_cpu_prefix}
  obj_format=${obj_format}
@@ -11700,6 +14628,8 @@ do
   "doc/Makefile" ) CONFIG_FILES="$CONFIG_FILES doc/Makefile" ;;
   "po/Makefile.in" ) CONFIG_FILES="$CONFIG_FILES po/Makefile.in:po/Make-in" ;;
   "depfiles" ) CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;;
+  "libtool" ) CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;;
+  "default-1" ) CONFIG_COMMANDS="$CONFIG_COMMANDS default-1" ;;
   "default" ) CONFIG_COMMANDS="$CONFIG_COMMANDS default" ;;
   "config.h" ) CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
   *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5
@@ -11837,10 +14767,22 @@ s,@AMDEPBACKSLASH@,$AMDEPBACKSLASH,;t t
 s,@CCDEPMODE@,$CCDEPMODE,;t t
 s,@am__fastdepCC_TRUE@,$am__fastdepCC_TRUE,;t t
 s,@am__fastdepCC_FALSE@,$am__fastdepCC_FALSE,;t t
+s,@LIBTOOL@,$LIBTOOL,;t t
+s,@SED@,$SED,;t t
+s,@EGREP@,$EGREP,;t t
+s,@FGREP@,$FGREP,;t t
+s,@GREP@,$GREP,;t t
+s,@LD@,$LD,;t t
+s,@DUMPBIN@,$DUMPBIN,;t t
+s,@ac_ct_DUMPBIN@,$ac_ct_DUMPBIN,;t t
+s,@NM@,$NM,;t t
 s,@LN_S@,$LN_S,;t t
+s,@AR@,$AR,;t t
+s,@ac_ct_AR@,$ac_ct_AR,;t t
 s,@RANLIB@,$RANLIB,;t t
 s,@ac_ct_RANLIB@,$ac_ct_RANLIB,;t t
-s,@LIBTOOL@,$LIBTOOL,;t t
+s,@lt_ECHO@,$lt_ECHO,;t t
+s,@CPP@,$CPP,;t t
 s,@WARN_CFLAGS@,$WARN_CFLAGS,;t t
 s,@NO_WERROR@,$NO_WERROR,;t t
 s,@GDBINIT@,$GDBINIT,;t t
@@ -11851,40 +14793,32 @@ s,@obj_format@,$obj_format,;t t
 s,@te_file@,$te_file,;t t
 s,@install_tooldir@,$install_tooldir,;t t
 s,@atof@,$atof,;t t
-s,@BFDLIB@,$BFDLIB,;t t
 s,@OPCODES_LIB@,$OPCODES_LIB,;t t
-s,@BFDVER_H@,$BFDVER_H,;t t
-s,@ALL_OBJ_DEPS@,$ALL_OBJ_DEPS,;t t
 s,@YACC@,$YACC,;t t
 s,@LEX@,$LEX,;t t
 s,@LEXLIB@,$LEXLIB,;t t
 s,@LEX_OUTPUT_ROOT@,$LEX_OUTPUT_ROOT,;t t
-s,@CPP@,$CPP,;t t
-s,@EGREP@,$EGREP,;t t
-s,@ALLOCA@,$ALLOCA,;t t
 s,@USE_NLS@,$USE_NLS,;t t
-s,@MSGFMT@,$MSGFMT,;t t
-s,@GMSGFMT@,$GMSGFMT,;t t
+s,@LIBINTL@,$LIBINTL,;t t
+s,@LIBINTL_DEP@,$LIBINTL_DEP,;t t
+s,@INCINTL@,$INCINTL,;t t
 s,@XGETTEXT@,$XGETTEXT,;t t
-s,@USE_INCLUDED_LIBINTL@,$USE_INCLUDED_LIBINTL,;t t
+s,@GMSGFMT@,$GMSGFMT,;t t
+s,@POSUB@,$POSUB,;t t
 s,@CATALOGS@,$CATALOGS,;t t
-s,@CATOBJEXT@,$CATOBJEXT,;t t
 s,@DATADIRNAME@,$DATADIRNAME,;t t
-s,@GMOFILES@,$GMOFILES,;t t
 s,@INSTOBJEXT@,$INSTOBJEXT,;t t
-s,@INTLDEPS@,$INTLDEPS,;t t
-s,@INTLLIBS@,$INTLLIBS,;t t
-s,@INTLOBJS@,$INTLOBJS,;t t
-s,@POFILES@,$POFILES,;t t
-s,@POSUB@,$POSUB,;t t
-s,@INCLUDE_LOCALE_H@,$INCLUDE_LOCALE_H,;t t
-s,@GT_NO@,$GT_NO,;t t
-s,@GT_YES@,$GT_YES,;t t
+s,@GENCAT@,$GENCAT,;t t
+s,@CATOBJEXT@,$CATOBJEXT,;t t
 s,@MKINSTALLDIRS@,$MKINSTALLDIRS,;t t
-s,@l@,$l,;t t
+s,@MSGFMT@,$MSGFMT,;t t
+s,@MSGMERGE@,$MSGMERGE,;t t
 s,@MAINTAINER_MODE_TRUE@,$MAINTAINER_MODE_TRUE,;t t
 s,@MAINTAINER_MODE_FALSE@,$MAINTAINER_MODE_FALSE,;t t
 s,@MAINT@,$MAINT,;t t
+s,@GENINSRC_NEVER_TRUE@,$GENINSRC_NEVER_TRUE,;t t
+s,@GENINSRC_NEVER_FALSE@,$GENINSRC_NEVER_FALSE,;t t
+s,@ALLOCA@,$ALLOCA,;t t
 s,@LIBM@,$LIBM,;t t
 s,@datarootdir@,$datarootdir,;t t
 s,@docdir@,$docdir,;t t
@@ -12573,6 +15507,656 @@ echo "$as_me: error: cannot create directory $dirpart/$fdir" >&2;}
   done
 done
  ;;
+    libtool )
+
+    # See if we are running on zsh, and set the options which allow our
+    # commands through without removal of \ escapes.
+    if test -n "${ZSH_VERSION+set}" ; then
+      setopt NO_GLOB_SUBST
+    fi
+
+    cfgfile="${ofile}T"
+    trap "$RM \"$cfgfile\"; exit 1" 1 2 15
+    $RM "$cfgfile"
+
+    cat <<_LT_EOF >> "$cfgfile"
+#! $SHELL
+
+# `$ECHO "$ofile" | sed 's%^.*/%%'` - Provide generalized library-building support services.
+# Generated automatically by $as_me (GNU $PACKAGE$TIMESTAMP) $VERSION
+# Libtool was configured on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
+# NOTE: Changes made to this file will be lost: look at ltmain.sh.
+#
+# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005,
+# 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of GNU Libtool:
+# Originally by Gordon Matzigkeit <gord@gnu.ai.mit.edu>, 1996
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, a copy can be downloaded from
+# http://www.gnu.org/copyleft/gpl.html, or by writing to the Free
+# Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that program.
+
+
+# The names of the tagged configurations supported by this script.
+available_tags=""
+
+# ### BEGIN LIBTOOL CONFIG
+
+# Which release of libtool.m4 was used?
+macro_version=$macro_version
+macro_revision=$macro_revision
+
+# Whether or not to build shared libraries.
+build_libtool_libs=$enable_shared
+
+# Whether or not to build static libraries.
+build_old_libs=$enable_static
+
+# What type of objects to build.
+pic_mode=$pic_mode
+
+# Whether or not to optimize for fast installation.
+fast_install=$enable_fast_install
+
+# The host system.
+host_alias=$host_alias
+host=$host
+host_os=$host_os
+
+# The build system.
+build_alias=$build_alias
+build=$build
+build_os=$build_os
+
+# A sed program that does not truncate output.
+SED=$lt_SED
+
+# Sed that helps us avoid accidentally triggering echo(1) options like -n.
+Xsed="\$SED -e 1s/^X//"
+
+# A grep program that handles long lines.
+GREP=$lt_GREP
+
+# An ERE matcher.
+EGREP=$lt_EGREP
+
+# A literal string matcher.
+FGREP=$lt_FGREP
+
+# A BSD- or MS-compatible name lister.
+NM=$lt_NM
+
+# Whether we need soft or hard links.
+LN_S=$lt_LN_S
+
+# What is the maximum length of a command?
+max_cmd_len=$max_cmd_len
+
+# Object file suffix (normally "o").
+objext=$ac_objext
+
+# Executable file suffix (normally "").
+exeext=$exeext
+
+# whether the shell understands "unset".
+lt_unset=$lt_unset
+
+# turn spaces into newlines.
+SP2NL=$lt_lt_SP2NL
+
+# turn newlines into spaces.
+NL2SP=$lt_lt_NL2SP
+
+# How to create reloadable object files.
+reload_flag=$lt_reload_flag
+reload_cmds=$lt_reload_cmds
+
+# Method to check whether dependent libraries are shared objects.
+deplibs_check_method=$lt_deplibs_check_method
+
+# Command to use when deplibs_check_method == "file_magic".
+file_magic_cmd=$lt_file_magic_cmd
+
+# The archiver.
+AR=$lt_AR
+AR_FLAGS=$lt_AR_FLAGS
+
+# A symbol stripping program.
+STRIP=$lt_STRIP
+
+# Commands used to install an old-style archive.
+RANLIB=$lt_RANLIB
+old_postinstall_cmds=$lt_old_postinstall_cmds
+old_postuninstall_cmds=$lt_old_postuninstall_cmds
+
+# A C compiler.
+LTCC=$lt_CC
+
+# LTCC compiler flags.
+LTCFLAGS=$lt_CFLAGS
+
+# Take the output of nm and produce a listing of raw symbols and C names.
+global_symbol_pipe=$lt_lt_cv_sys_global_symbol_pipe
+
+# Transform the output of nm in a proper C declaration.
+global_symbol_to_cdecl=$lt_lt_cv_sys_global_symbol_to_cdecl
+
+# Transform the output of nm in a C name address pair.
+global_symbol_to_c_name_address=$lt_lt_cv_sys_global_symbol_to_c_name_address
+
+# The name of the directory that contains temporary libtool files.
+objdir=$objdir
+
+# Shell to use when invoking shell scripts.
+SHELL=$lt_SHELL
+
+# An echo program that does not interpret backslashes.
+ECHO=$lt_ECHO
+
+# Used to examine libraries when file_magic_cmd begins with "file".
+MAGIC_CMD=$MAGIC_CMD
+
+# Must we lock files when doing compilation?
+need_locks=$lt_need_locks
+
+# Old archive suffix (normally "a").
+libext=$libext
+
+# Shared library suffix (normally ".so").
+shrext_cmds=$lt_shrext_cmds
+
+# The commands to extract the exported symbol list from a shared archive.
+extract_expsyms_cmds=$lt_extract_expsyms_cmds
+
+# Variables whose values should be saved in libtool wrapper scripts and
+# restored at link time.
+variables_saved_for_relink=$lt_variables_saved_for_relink
+
+# Do we need the "lib" prefix for modules?
+need_lib_prefix=$need_lib_prefix
+
+# Do we need a version for libraries?
+need_version=$need_version
+
+# Library versioning type.
+version_type=$version_type
+
+# Shared library runtime path variable.
+runpath_var=$runpath_var
+
+# Shared library path variable.
+shlibpath_var=$shlibpath_var
+
+# Is shlibpath searched before the hard-coded library search path?
+shlibpath_overrides_runpath=$shlibpath_overrides_runpath
+
+# Format of library name prefix.
+libname_spec=$lt_libname_spec
+
+# List of archive names.  First name is the real one, the rest are links.
+# The last name is the one that the linker finds with -lNAME
+library_names_spec=$lt_library_names_spec
+
+# The coded name of the library, if different from the real name.
+soname_spec=$lt_soname_spec
+
+# Command to use after installation of a shared archive.
+postinstall_cmds=$lt_postinstall_cmds
+
+# Command to use after uninstallation of a shared archive.
+postuninstall_cmds=$lt_postuninstall_cmds
+
+# Commands used to finish a libtool library installation in a directory.
+finish_cmds=$lt_finish_cmds
+
+# As "finish_cmds", except a single script fragment to be evaled but
+# not shown.
+finish_eval=$lt_finish_eval
+
+# Whether we should hardcode library paths into libraries.
+hardcode_into_libs=$hardcode_into_libs
+
+# Compile-time system search path for libraries.
+sys_lib_search_path_spec=$lt_sys_lib_search_path_spec
+
+# Run-time system search path for libraries.
+sys_lib_dlsearch_path_spec=$lt_sys_lib_dlsearch_path_spec
+
+# Whether dlopen is supported.
+dlopen_support=$enable_dlopen
+
+# Whether dlopen of programs is supported.
+dlopen_self=$enable_dlopen_self
+
+# Whether dlopen of statically linked programs is supported.
+dlopen_self_static=$enable_dlopen_self_static
+
+# Commands to strip libraries.
+old_striplib=$lt_old_striplib
+striplib=$lt_striplib
+
+
+# The linker used to build libraries.
+LD=$lt_LD
+
+# Commands used to build an old-style archive.
+old_archive_cmds=$lt_old_archive_cmds
+
+# A language specific compiler.
+CC=$lt_compiler
+
+# Is the compiler the GNU compiler?
+with_gcc=$GCC
+
+# Compiler flag to turn off builtin functions.
+no_builtin_flag=$lt_lt_prog_compiler_no_builtin_flag
+
+# How to pass a linker flag through the compiler.
+wl=$lt_lt_prog_compiler_wl
+
+# Additional compiler flags for building library objects.
+pic_flag=$lt_lt_prog_compiler_pic
+
+# Compiler flag to prevent dynamic linking.
+link_static_flag=$lt_lt_prog_compiler_static
+
+# Does compiler simultaneously support -c and -o options?
+compiler_c_o=$lt_lt_cv_prog_compiler_c_o
+
+# Whether or not to add -lc for building shared libraries.
+build_libtool_need_lc=$archive_cmds_need_lc
+
+# Whether or not to disallow shared libs when runtime libs are static.
+allow_libtool_libs_with_static_runtimes=$enable_shared_with_static_runtimes
+
+# Compiler flag to allow reflexive dlopens.
+export_dynamic_flag_spec=$lt_export_dynamic_flag_spec
+
+# Compiler flag to generate shared objects directly from archives.
+whole_archive_flag_spec=$lt_whole_archive_flag_spec
+
+# Whether the compiler copes with passing no objects directly.
+compiler_needs_object=$lt_compiler_needs_object
+
+# Create an old-style archive from a shared archive.
+old_archive_from_new_cmds=$lt_old_archive_from_new_cmds
+
+# Create a temporary old-style archive to link instead of a shared archive.
+old_archive_from_expsyms_cmds=$lt_old_archive_from_expsyms_cmds
+
+# Commands used to build a shared archive.
+archive_cmds=$lt_archive_cmds
+archive_expsym_cmds=$lt_archive_expsym_cmds
+
+# Commands used to build a loadable module if different from building
+# a shared archive.
+module_cmds=$lt_module_cmds
+module_expsym_cmds=$lt_module_expsym_cmds
+
+# Whether we are building with GNU ld or not.
+with_gnu_ld=$lt_with_gnu_ld
+
+# Flag that allows shared libraries with undefined symbols to be built.
+allow_undefined_flag=$lt_allow_undefined_flag
+
+# Flag that enforces no undefined symbols.
+no_undefined_flag=$lt_no_undefined_flag
+
+# Flag to hardcode \$libdir into a binary during linking.
+# This must work even if \$libdir does not exist
+hardcode_libdir_flag_spec=$lt_hardcode_libdir_flag_spec
+
+# If ld is used when linking, flag to hardcode \$libdir into a binary
+# during linking.  This must work even if \$libdir does not exist.
+hardcode_libdir_flag_spec_ld=$lt_hardcode_libdir_flag_spec_ld
+
+# Whether we need a single "-rpath" flag with a separated argument.
+hardcode_libdir_separator=$lt_hardcode_libdir_separator
+
+# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes
+# DIR into the resulting binary.
+hardcode_direct=$hardcode_direct
+
+# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes
+# DIR into the resulting binary and the resulting library dependency is
+# "absolute",i.e impossible to change by setting \${shlibpath_var} if the
+# library is relocated.
+hardcode_direct_absolute=$hardcode_direct_absolute
+
+# Set to "yes" if using the -LDIR flag during linking hardcodes DIR
+# into the resulting binary.
+hardcode_minus_L=$hardcode_minus_L
+
+# Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR
+# into the resulting binary.
+hardcode_shlibpath_var=$hardcode_shlibpath_var
+
+# Set to "yes" if building a shared library automatically hardcodes DIR
+# into the library and all subsequent libraries and executables linked
+# against it.
+hardcode_automatic=$hardcode_automatic
+
+# Set to yes if linker adds runtime paths of dependent libraries
+# to runtime path list.
+inherit_rpath=$inherit_rpath
+
+# Whether libtool must link a program against all its dependency libraries.
+link_all_deplibs=$link_all_deplibs
+
+# Fix the shell variable \$srcfile for the compiler.
+fix_srcfile_path=$lt_fix_srcfile_path
+
+# Set to "yes" if exported symbols are required.
+always_export_symbols=$always_export_symbols
+
+# The commands to list exported symbols.
+export_symbols_cmds=$lt_export_symbols_cmds
+
+# Symbols that should not be listed in the preloaded symbols.
+exclude_expsyms=$lt_exclude_expsyms
+
+# Symbols that must always be exported.
+include_expsyms=$lt_include_expsyms
+
+# Commands necessary for linking programs (against libraries) with templates.
+prelink_cmds=$lt_prelink_cmds
+
+# Specify filename containing input files.
+file_list_spec=$lt_file_list_spec
+
+# How to hardcode a shared library path into an executable.
+hardcode_action=$hardcode_action
+
+# ### END LIBTOOL CONFIG
+
+_LT_EOF
+
+  case $host_os in
+  aix3*)
+    cat <<\_LT_EOF >> "$cfgfile"
+# AIX sometimes has problems with the GCC collect2 program.  For some
+# reason, if we set the COLLECT_NAMES environment variable, the problems
+# vanish in a puff of smoke.
+if test "X${COLLECT_NAMES+set}" != Xset; then
+  COLLECT_NAMES=
+  export COLLECT_NAMES
+fi
+_LT_EOF
+    ;;
+  esac
+
+
+ltmain="$ac_aux_dir/ltmain.sh"
+
+
+  # We use sed instead of cat because bash on DJGPP gets confused if
+  # if finds mixed CR/LF and LF-only lines.  Since sed operates in
+  # text mode, it properly converts lines to CR/LF.  This bash problem
+  # is reportedly fixed, but why not run on old versions too?
+  sed '/^# Generated shell functions inserted here/q' "$ltmain" >> "$cfgfile" \
+    || (rm -f "$cfgfile"; exit 1)
+
+  case $xsi_shell in
+  yes)
+    cat << \_LT_EOF >> "$cfgfile"
+# func_dirname file append nondir_replacement
+# Compute the dirname of FILE.  If nonempty, add APPEND to the result,
+# otherwise set result to NONDIR_REPLACEMENT.
+func_dirname ()
+{
+  case ${1} in
+    */*) func_dirname_result="${1%/*}${2}" ;;
+    *  ) func_dirname_result="${3}" ;;
+  esac
+}
+
+# func_basename file
+func_basename ()
+{
+  func_basename_result="${1##*/}"
+}
+
+# func_stripname prefix suffix name
+# strip PREFIX and SUFFIX off of NAME.
+# PREFIX and SUFFIX must not contain globbing or regex special
+# characters, hashes, percent signs, but SUFFIX may contain a leading
+# dot (in which case that matches only a dot).
+func_stripname ()
+{
+  # pdksh 5.2.14 does not do ${X%$Y} correctly if both X and Y are
+  # positional parameters, so assign one to ordinary parameter first.
+  func_stripname_result=${3}
+  func_stripname_result=${func_stripname_result#"${1}"}
+  func_stripname_result=${func_stripname_result%"${2}"}
+}
+
+# func_opt_split
+func_opt_split ()
+{
+  func_opt_split_opt=${1%%=*}
+  func_opt_split_arg=${1#*=}
+}
+
+# func_lo2o object
+func_lo2o ()
+{
+  case ${1} in
+    *.lo) func_lo2o_result=${1%.lo}.${objext} ;;
+    *)    func_lo2o_result=${1} ;;
+  esac
+}
+_LT_EOF
+    ;;
+  *) # Bourne compatible functions.
+    cat << \_LT_EOF >> "$cfgfile"
+# func_dirname file append nondir_replacement
+# Compute the dirname of FILE.  If nonempty, add APPEND to the result,
+# otherwise set result to NONDIR_REPLACEMENT.
+func_dirname ()
+{
+  # Extract subdirectory from the argument.
+  func_dirname_result=`$ECHO "X${1}" | $Xsed -e "$dirname"`
+  if test "X$func_dirname_result" = "X${1}"; then
+    func_dirname_result="${3}"
+  else
+    func_dirname_result="$func_dirname_result${2}"
+  fi
+}
+
+# func_basename file
+func_basename ()
+{
+  func_basename_result=`$ECHO "X${1}" | $Xsed -e "$basename"`
+}
+
+# func_stripname prefix suffix name
+# strip PREFIX and SUFFIX off of NAME.
+# PREFIX and SUFFIX must not contain globbing or regex special
+# characters, hashes, percent signs, but SUFFIX may contain a leading
+# dot (in which case that matches only a dot).
+# func_strip_suffix prefix name
+func_stripname ()
+{
+  case ${2} in
+    .*) func_stripname_result=`$ECHO "X${3}" \
+           | $Xsed -e "s%^${1}%%" -e "s%\\\\${2}\$%%"`;;
+    *)  func_stripname_result=`$ECHO "X${3}" \
+           | $Xsed -e "s%^${1}%%" -e "s%${2}\$%%"`;;
+  esac
+}
+
+# sed scripts:
+my_sed_long_opt='1s/^\(-[^=]*\)=.*/\1/;q'
+my_sed_long_arg='1s/^-[^=]*=//'
+
+# func_opt_split
+func_opt_split ()
+{
+  func_opt_split_opt=`$ECHO "X${1}" | $Xsed -e "$my_sed_long_opt"`
+  func_opt_split_arg=`$ECHO "X${1}" | $Xsed -e "$my_sed_long_arg"`
+}
+
+# func_lo2o object
+func_lo2o ()
+{
+  func_lo2o_result=`$ECHO "X${1}" | $Xsed -e "$lo2o"`
+}
+_LT_EOF
+esac
+
+case $lt_shell_append in
+  yes)
+    cat << \_LT_EOF >> "$cfgfile"
+
+# func_append var value
+# Append VALUE to the end of shell variable VAR.
+func_append ()
+{
+  eval "$1+=\$2"
+}
+_LT_EOF
+    ;;
+  *)
+    cat << \_LT_EOF >> "$cfgfile"
+
+# func_append var value
+# Append VALUE to the end of shell variable VAR.
+func_append ()
+{
+  eval "$1=\$$1\$2"
+}
+_LT_EOF
+    ;;
+  esac
+
+
+  sed -n '/^# Generated shell functions inserted here/,$p' "$ltmain" >> "$cfgfile" \
+    || (rm -f "$cfgfile"; exit 1)
+
+  mv -f "$cfgfile" "$ofile" ||
+    (rm -f "$ofile" && cp "$cfgfile" "$ofile" && rm -f "$cfgfile")
+  chmod +x "$ofile"
+
+ ;;
+    default-1 )
+    for ac_file in $CONFIG_FILES; do
+      # Support "outfile[:infile[:infile...]]"
+      case "$ac_file" in
+        *:*) ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+      esac
+      # PO directories have a Makefile.in generated from Makefile.in.in.
+      case "$ac_file" in */Makefile.in)
+        # Adjust a relative srcdir.
+        ac_dir=`echo "$ac_file"|sed 's%/[^/][^/]*$%%'`
+        ac_dir_suffix="/`echo "$ac_dir"|sed 's%^\./%%'`"
+        ac_dots=`echo "$ac_dir_suffix"|sed 's%/[^/]*%../%g'`
+        # In autoconf-2.13 it is called $ac_given_srcdir.
+        # In autoconf-2.50 it is called $srcdir.
+        test -n "$ac_given_srcdir" || ac_given_srcdir="$srcdir"
+        case "$ac_given_srcdir" in
+          .)  top_srcdir=`echo $ac_dots|sed 's%/$%%'` ;;
+          /*) top_srcdir="$ac_given_srcdir" ;;
+          *)  top_srcdir="$ac_dots$ac_given_srcdir" ;;
+        esac
+        if test -f "$ac_given_srcdir/$ac_dir/POTFILES.in"; then
+          rm -f "$ac_dir/POTFILES"
+          test -n "$as_me" && echo "$as_me: creating $ac_dir/POTFILES" || echo "creating $ac_dir/POTFILES"
+          cat "$ac_given_srcdir/$ac_dir/POTFILES.in" | sed -e "/^#/d" -e "/^[ 	]*\$/d" -e "s,.*,     $top_srcdir/& \\\\," | sed -e "\$s/\(.*\) \\\\/\1/" > "$ac_dir/POTFILES"
+          POMAKEFILEDEPS="POTFILES.in"
+          # ALL_LINGUAS, POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES depend
+          # on $ac_dir but don't depend on user-specified configuration
+          # parameters.
+          if test -f "$ac_given_srcdir/$ac_dir/LINGUAS"; then
+            # The LINGUAS file contains the set of available languages.
+            if test -n "$OBSOLETE_ALL_LINGUAS"; then
+              test -n "$as_me" && echo "$as_me: setting ALL_LINGUAS in configure.in is obsolete" || echo "setting ALL_LINGUAS in configure.in is obsolete"
+            fi
+            ALL_LINGUAS_=`sed -e "/^#/d" "$ac_given_srcdir/$ac_dir/LINGUAS"`
+            # Hide the ALL_LINGUAS assigment from automake.
+            eval 'ALL_LINGUAS''=$ALL_LINGUAS_'
+            POMAKEFILEDEPS="$POMAKEFILEDEPS LINGUAS"
+          else
+            # The set of available languages was given in configure.in.
+            eval 'ALL_LINGUAS''=$OBSOLETE_ALL_LINGUAS'
+          fi
+          case "$ac_given_srcdir" in
+            .) srcdirpre= ;;
+            *) srcdirpre='$(srcdir)/' ;;
+          esac
+          POFILES=
+          GMOFILES=
+          UPDATEPOFILES=
+          DUMMYPOFILES=
+          for lang in $ALL_LINGUAS; do
+            POFILES="$POFILES $srcdirpre$lang.po"
+            GMOFILES="$GMOFILES $srcdirpre$lang.gmo"
+            UPDATEPOFILES="$UPDATEPOFILES $lang.po-update"
+            DUMMYPOFILES="$DUMMYPOFILES $lang.nop"
+          done
+          # CATALOGS depends on both $ac_dir and the user's LINGUAS
+          # environment variable.
+          INST_LINGUAS=
+          if test -n "$ALL_LINGUAS"; then
+            for presentlang in $ALL_LINGUAS; do
+              useit=no
+              if test "%UNSET%" != "$LINGUAS"; then
+                desiredlanguages="$LINGUAS"
+              else
+                desiredlanguages="$ALL_LINGUAS"
+              fi
+              for desiredlang in $desiredlanguages; do
+                # Use the presentlang catalog if desiredlang is
+                #   a. equal to presentlang, or
+                #   b. a variant of presentlang (because in this case,
+                #      presentlang can be used as a fallback for messages
+                #      which are not translated in the desiredlang catalog).
+                case "$desiredlang" in
+                  "$presentlang"*) useit=yes;;
+                esac
+              done
+              if test $useit = yes; then
+                INST_LINGUAS="$INST_LINGUAS $presentlang"
+              fi
+            done
+          fi
+          CATALOGS=
+          if test -n "$INST_LINGUAS"; then
+            for lang in $INST_LINGUAS; do
+              CATALOGS="$CATALOGS $lang.gmo"
+            done
+          fi
+          test -n "$as_me" && echo "$as_me: creating $ac_dir/Makefile" || echo "creating $ac_dir/Makefile"
+          sed -e "/^POTFILES =/r $ac_dir/POTFILES" -e "/^# Makevars/r $ac_given_srcdir/$ac_dir/Makevars" -e "s|@POFILES@|$POFILES|g" -e "s|@GMOFILES@|$GMOFILES|g" -e "s|@UPDATEPOFILES@|$UPDATEPOFILES|g" -e "s|@DUMMYPOFILES@|$DUMMYPOFILES|g" -e "s|@CATALOGS@|$CATALOGS|g" -e "s|@POMAKEFILEDEPS@|$POMAKEFILEDEPS|g" "$ac_dir/Makefile.in" > "$ac_dir/Makefile"
+          for f in "$ac_given_srcdir/$ac_dir"/Rules-*; do
+            if test -f "$f"; then
+              case "$f" in
+                *.orig | *.bak | *~) ;;
+                *) cat "$f" >> "$ac_dir/Makefile" ;;
+              esac
+            fi
+          done
+        fi
+        ;;
+      esac
+    done ;;
     default ) rm -f targ-cpu.c targ-cpu.h obj-format.h obj-format.c targ-env.h atof-targ.c itbl-cpu.h
  echo '#include "tc-'"${target_cpu_type}"'.h"' > targ-cpu.h
  echo '#include "obj-'"${obj_format}"'.h"' > obj-format.h
@@ -12580,9 +16164,7 @@ done
  echo '#include "itbl-'"${target_cpu_type}"'.h"' > itbl-cpu.h
  if test "x$cgen_cpu_prefix" != x ; then
    echo '#include "opcodes/'"${cgen_cpu_prefix}"'-desc.h"' > cgen-desc.h
- fi
-
- sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile ;;
+ fi ;;
   esac
 done
 _ACEOF
diff --git a/contrib/binutils/gas/configure.in b/contrib/binutils/gas/configure.in
index fe69a51..02e8e53 100644
--- a/contrib/binutils/gas/configure.in
+++ b/contrib/binutils/gas/configure.in
@@ -23,13 +23,14 @@ AM_INIT_AUTOMAKE(gas, ${BFD_VERSION})
 AM_PROG_LIBTOOL
 
 AC_ARG_ENABLE(targets,
-[   --enable-targets       alternative target configurations besides the primary],
+[  --enable-targets        alternative target configurations besides the primary],
 [case "${enableval}" in
   yes | "") AC_ERROR(enable-targets option must specify target names or 'all')
 	    ;;
   no)	    enable_targets= ;;
   *)	    enable_targets=$enableval ;;
 esac])dnl
+
 AC_ARG_ENABLE(commonbfdlib,
 [  --enable-commonbfdlib   build shared BFD/opcodes/libiberty library],
 [case "${enableval}" in
@@ -38,6 +39,20 @@ AC_ARG_ENABLE(commonbfdlib,
   *)   AC_MSG_ERROR([bad value ${enableval} for BFD commonbfdlib option]) ;;
 esac])dnl
 
+ac_checking=yes
+if grep '^RELEASE=y' ${srcdir}/../bfd/Makefile.am >/dev/null 2>/dev/null ; then
+  ac_checking=
+fi
+AC_ARG_ENABLE(checking,
+[  --enable-checking       enable run-time checks],
+[case "${enableval}" in
+  no|none)  ac_checking= ;;
+  *)	    ac_checking=yes ;;
+esac])dnl
+if test x$ac_checking != x ; then
+  AC_DEFINE(ENABLE_CHECKING, 1, [Define if you want run-time sanity checks.])
+fi
+
 using_cgen=no
 
 AM_BINUTILS_WARNINGS
@@ -258,7 +273,7 @@ changequote([,])dnl
 
     # Do we need the opcodes library?
     case ${cpu_type} in
-      vax | i386 | tic30)
+      vax | tic30)
 	;;
 
       *)
@@ -304,18 +319,22 @@ changequote([,])dnl
 	esac
 	;;
 
+      mep)
+	using_cgen=yes
+	;;
+
       mips)
-	echo ${extra_objects} | grep -s "itbl-parse.o" 
+	echo ${extra_objects} | grep -s "itbl-parse.o"
 	if test $? -ne 0 ; then
 	  extra_objects="$extra_objects itbl-parse.o"
 	fi
 
-	echo ${extra_objects} | grep -s "itbl-lex.o" 
+	echo ${extra_objects} | grep -s "itbl-lex.o"
 	if test $? -ne 0 ; then
 	  extra_objects="$extra_objects itbl-lex.o"
 	fi
 
-	echo ${extra_objects} | grep -s "itbl-ops.o" 
+	echo ${extra_objects} | grep -s "itbl-ops.o"
 	if test $? -ne 0 ; then
 	  extra_objects="$extra_objects itbl-ops.o"
 	fi
@@ -417,6 +436,19 @@ if test ${all_targets} = "yes"; then
       ;;
     esac
   ;;
+  x86_64)
+    case ${obj_format} in
+    aout)
+      emulations="$emulations i386coff i386elf"
+      ;;
+    coff)
+      emulations="$emulations i386aout i386elf"
+    ;;
+    elf)
+      emulations="$emulations i386aout i386coff"
+      ;;
+    esac
+  ;;
   esac
 fi
 
@@ -424,8 +456,7 @@ fi
 # IEEE FP.  On those that don't support FP at all, usually IEEE
 # is emulated.
 case ${target_cpu} in
-  vax | tahoe )	atof=${target_cpu} ;;
-  pdp11)	atof=vax ;;
+  vax | pdp11 )	atof=vax ;;
   *)		atof=ieee ;;
 esac
 
@@ -462,6 +493,7 @@ case ${obj_format} in
       i386) AC_DEFINE(I386COFF, 1, [Using i386 COFF?]) ;;
       m68k) AC_DEFINE(M68KCOFF, 1, [Using m68k COFF?]) ;;
       m88k) AC_DEFINE(M88KCOFF, 1, [Using m88k COFF?]) ;;
+      x86_64) AC_DEFINE(I386COFF, 1, [Using i386 COFF?]) ;;
     esac
     ;;
 esac
@@ -511,7 +543,6 @@ if test `set . $formats ; shift ; echo $#` -gt 1 ; then
       ecoff)	AC_DEFINE(OBJ_MAYBE_ECOFF, 1,   [ECOFF support?])   ;;
       elf)	AC_DEFINE(OBJ_MAYBE_ELF, 1,     [ELF support?])     ;;
       generic)	AC_DEFINE(OBJ_MAYBE_GENERIC, 1, [generic support?]) ;;
-      ieee)	AC_DEFINE(OBJ_MAYBE_IEEE, 1,    [IEEE support?])    ;;
       som)	AC_DEFINE(OBJ_MAYBE_SOM, 1,     [SOM support?])     ;;
     esac
     extra_objects="$extra_objects obj-$fmt.o"
@@ -556,16 +587,8 @@ yes)
   ;;
 esac
 
-BFDLIB=../bfd/libbfd.la
-BFDVER_H=../bfd/bfdver.h
-ALL_OBJ_DEPS="$ALL_OBJ_DEPS"' ../bfd/bfd.h $(INCDIR)/symcat.h'
-
-AC_SUBST(BFDLIB)
 AC_SUBST(OPCODES_LIB)
 
-AC_SUBST(BFDVER_H)
-AC_SUBST(ALL_OBJ_DEPS)
-
 AC_DEFINE_UNQUOTED(TARGET_ALIAS,	"${target_alias}", [Target alias.])
 AC_DEFINE_UNQUOTED(TARGET_CANONICAL,	"${target}",       [Canonical target.])
 AC_DEFINE_UNQUOTED(TARGET_CPU,		"${target_cpu}",   [Target CPU.])
@@ -578,9 +601,11 @@ AC_PROG_YACC
 AM_PROG_LEX
 
 ALL_LINGUAS="fr tr es rw"
-CY_GNU_GETTEXT
+ZW_GNU_GETTEXT_SISTER_DIR
+AM_PO_SUBDIRS
 
 AM_MAINTAINER_MODE
+AM_CONDITIONAL(GENINSRC_NEVER, false)
 AC_EXEEXT
 
 AC_CHECK_HEADERS(string.h stdlib.h memory.h strings.h unistd.h stdarg.h varargs.h errno.h sys/types.h)
@@ -609,7 +634,7 @@ AC_CHECK_FUNCS(sbrk)
 
 # do we need the math library?
 case "${need_libm}" in
-yes) 
+yes)
   AC_CHECK_LIBM
   AC_SUBST(LIBM)
   ;;
@@ -669,6 +694,8 @@ GAS_CHECK_DECL_NEEDED(strstr, f, char *(*f)(), $gas_test_headers)
 
 AC_CHECK_DECLS([vsnprintf])
 
+BFD_BINARY_FOPEN
+
 dnl Required for html and install-html targets.
 AC_SUBST(datarootdir)
 AC_SUBST(docdir)
@@ -691,9 +718,7 @@ AC_CONFIG_COMMANDS([default],
  echo '#include "itbl-'"${target_cpu_type}"'.h"' > itbl-cpu.h
  if test "x$cgen_cpu_prefix" != x ; then
    echo '#include "opcodes/'"${cgen_cpu_prefix}"'-desc.h"' > cgen-desc.h
- fi
-
- sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile],
+ fi],
 [target_cpu_type=${target_cpu_type}
  cgen_cpu_prefix=${cgen_cpu_prefix}
  obj_format=${obj_format}
diff --git a/contrib/binutils/gas/debug.c b/contrib/binutils/gas/debug.c
index fe2ed8c..3218fff 100644
--- a/contrib/binutils/gas/debug.c
+++ b/contrib/binutils/gas/debug.c
@@ -1,5 +1,5 @@
 /* This file is debug.c
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2000
+   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2000, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -25,26 +25,28 @@
 
 dmp_frags ()
 {
+  asection *s;
   frchainS *chp;
   char *p;
 
-  for (chp = frchain_root; chp; chp = chp->frch_next)
-    {
-      switch (chp->frch_seg)
-	{
-	case SEG_DATA:
-	  p = "Data";
-	  break;
-	case SEG_TEXT:
-	  p = "Text";
-	  break;
-	default:
-	  p = "???";
-	  break;
-	}
-      printf ("\nSEGMENT %s %d\n", p, chp->frch_subseg);
-      dmp_frag (chp->frch_root, "\t");
-    }
+  for (s = stdoutput->sections; s; s = s->next)
+    for (chp = seg_info (s)->frchainP; chp; chp = chp->frch_next)
+      {
+	switch (s)
+	  {
+	  case SEG_DATA:
+	    p = "Data";
+	    break;
+	  case SEG_TEXT:
+	    p = "Text";
+	    break;
+	  default:
+	    p = "???";
+	    break;
+	  }
+	printf ("\nSEGMENT %s %d\n", p, chp->frch_subseg);
+	dmp_frag (chp->frch_root, "\t");
+      }
 }
 
 dmp_frag (fp, indent)
diff --git a/contrib/binutils/gas/dep-in.sed b/contrib/binutils/gas/dep-in.sed
index f23c201..d81c460 100644
--- a/contrib/binutils/gas/dep-in.sed
+++ b/contrib/binutils/gas/dep-in.sed
@@ -12,14 +12,13 @@ s!@SRCDIR@/config!$(srcdir)/config!g
 s!@SRCDIR@/\.\./opcodes!$(srcdir)/../opcodes!g
 s!@TOPDIR@/opcodes!$(srcdir)/../opcodes!g
 s!@SRCDIR@/!!g
-s!\.\./bfd/bfdver\.h!$(BFDVER_H)!g
 s! \$(srcdir)/config/te-generic\.h!!g
-s! \.\./bfd/bfd\.h!!g
 s! itbl-cpu\.h!!g
 s! itbl-parse\.h!!g
 s! \.\./intl/libintl\.h!!g
 
-s! \$(INCDIR)/bin-bugs\.h!!g
+s! \.\./bfd/bfd\.h!!g
+s! \$(INCDIR)/symcat\.h!!g
 s! \$(INCDIR)/ansidecl\.h!!g
 s! \$(INCDIR)/libiberty\.h!!g
 s! \$(INCDIR)/progress\.h!!g
diff --git a/contrib/binutils/gas/doc/Makefile.am b/contrib/binutils/gas/doc/Makefile.am
index d48a9cc..4f6ff92 100644
--- a/contrib/binutils/gas/doc/Makefile.am
+++ b/contrib/binutils/gas/doc/Makefile.am
@@ -16,9 +16,12 @@ POD2MAN = pod2man --center="GNU Development Tools" \
 man_MANS = as.1
 
 info_TEXINFOS = as.texinfo 
+as_TEXINFOS = asconfig.texi $(CPU_DOCS)
 
-AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
-TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
+AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
+		   -I ../../bfd/doc
+TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
+		   -I ../../bfd/doc
 
 asconfig.texi: $(CONFIG).texi
 	rm -f asconfig.texi
@@ -29,7 +32,9 @@ CPU_DOCS = \
 	c-alpha.texi \
 	c-arc.texi \
 	c-arm.texi \
+	c-avr.texi \
 	c-bfin.texi \
+	c-cr16.texi \
 	c-d10v.texi \
 	c-cris.texi \
 	c-h8300.texi \
@@ -61,13 +66,6 @@ CPU_DOCS = \
 	c-z80.texi \
 	c-z8k.texi
 
-gasver.texi: $(srcdir)/../../bfd/configure
-	rm -f $@
-	eval `grep '^ *VERSION=' $(srcdir)/../../bfd/configure`; \
-	  echo "@set VERSION $$VERSION" > $@
-
-$(srcdir)/as.info as.dvi as.html: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
-
 # We want install to imply install-info as per GNU standards, despite the
 # cygnus option.
 install-data-local: install-info
@@ -97,7 +95,7 @@ install-html-am: $(HTMLS)
 
 noinst_TEXINFOS = internals.texi
 
-MAINTAINERCLEANFILES = asconfig.texi gasver.texi
+MAINTAINERCLEANFILES = asconfig.texi
 
 BASEDIR = $(srcdir)/../..
 BFDDIR = $(BASEDIR)/bfd
@@ -112,7 +110,7 @@ info-local: $(MANS)
 # Build the man page from the texinfo file
 # The sed command removes the no-adjust Nroff command so that
 # the man output looks standard.
-as.1: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
+as.1: $(srcdir)/as.texinfo asconfig.texi $(CPU_DOCS)
 	touch $@
 	-$(TEXI2POD) $(MANCONF) < $(srcdir)/as.texinfo > as.pod
 	-($(POD2MAN) as.pod | \
@@ -120,3 +118,12 @@ as.1: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
 	        mv -f $@.T$$$$ $@) || \
 	        (rm -f $@.T$$$$ && exit 1)
 	rm -f as.pod
+
+MAINTAINERCLEANFILES += as.info
+
+# Automake 1.9 will only build info files in the objdir if they are
+# mentioned in DISTCLEANFILES.  It doesn't have to be unconditional,
+# though, so we use a bogus condition.
+if GENINSRC_NEVER
+DISTCLEANFILES = as.info
+endif
diff --git a/contrib/binutils/gas/doc/Makefile.in b/contrib/binutils/gas/doc/Makefile.in
index cd9dad2..86f3d7a 100644
--- a/contrib/binutils/gas/doc/Makefile.in
+++ b/contrib/binutils/gas/doc/Makefile.in
@@ -37,11 +37,19 @@ build_triplet = @build@
 host_triplet = @host@
 target_triplet = @target@
 subdir = doc
-DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am
+DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
+	$(as_TEXINFOS)
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/acinclude.m4 \
-	$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../libtool.m4 \
-	$(top_srcdir)/../gettext.m4 $(top_srcdir)/configure.in
+am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
+	$(top_srcdir)/../bfd/warning.m4 \
+	$(top_srcdir)/../config/depstand.m4 \
+	$(top_srcdir)/../config/gettext-sister.m4 \
+	$(top_srcdir)/../config/lead-dot.m4 \
+	$(top_srcdir)/../config/nls.m4 $(top_srcdir)/../config/po.m4 \
+	$(top_srcdir)/../config/progtest.m4 \
+	$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
+	$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
+	$(top_srcdir)/acinclude.m4 $(top_srcdir)/configure.in
 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
 	$(ACLOCAL_M4)
 mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs
@@ -50,7 +58,7 @@ CONFIG_CLEAN_FILES =
 depcomp =
 am__depfiles_maybe =
 SOURCES =
-INFO_DEPS = $(srcdir)/as.info
+INFO_DEPS = as.info
 TEXINFO_TEX = $(top_srcdir)/../texinfo/texinfo.tex
 am__TEXINFO_TEX_DIR = $(top_srcdir)/../texinfo
 DVIS = as.dvi
@@ -68,16 +76,14 @@ NROFF = nroff
 MANS = $(man_MANS)
 ACLOCAL = @ACLOCAL@
 ALLOCA = @ALLOCA@
-ALL_OBJ_DEPS = @ALL_OBJ_DEPS@
 AMDEP_FALSE = @AMDEP_FALSE@
 AMDEP_TRUE = @AMDEP_TRUE@
 AMTAR = @AMTAR@
+AR = @AR@
 AUTOCONF = @AUTOCONF@
 AUTOHEADER = @AUTOHEADER@
 AUTOMAKE = @AUTOMAKE@
 AWK = @AWK@
-BFDLIB = @BFDLIB@
-BFDVER_H = @BFDVER_H@
 CATALOGS = @CATALOGS@
 CATOBJEXT = @CATOBJEXT@
 CC = @CC@
@@ -89,29 +95,32 @@ CYGPATH_W = @CYGPATH_W@
 DATADIRNAME = @DATADIRNAME@
 DEFS = @DEFS@
 DEPDIR = @DEPDIR@
+DUMPBIN = @DUMPBIN@
 ECHO_C = @ECHO_C@
 ECHO_N = @ECHO_N@
 ECHO_T = @ECHO_T@
 EGREP = @EGREP@
 EXEEXT = @EXEEXT@
+FGREP = @FGREP@
 GDBINIT = @GDBINIT@
-GMOFILES = @GMOFILES@
+GENCAT = @GENCAT@
+GENINSRC_NEVER_FALSE = @GENINSRC_NEVER_FALSE@
+GENINSRC_NEVER_TRUE = @GENINSRC_NEVER_TRUE@
 GMSGFMT = @GMSGFMT@
-GT_NO = @GT_NO@
-GT_YES = @GT_YES@
-INCLUDE_LOCALE_H = @INCLUDE_LOCALE_H@
+GREP = @GREP@
+INCINTL = @INCINTL@
 INSTALL_DATA = @INSTALL_DATA@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_SCRIPT = @INSTALL_SCRIPT@
 INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
 INSTOBJEXT = @INSTOBJEXT@
-INTLDEPS = @INTLDEPS@
-INTLLIBS = @INTLLIBS@
-INTLOBJS = @INTLOBJS@
+LD = @LD@
 LDFLAGS = @LDFLAGS@
 LEX = @LEX@
 LEXLIB = @LEXLIB@
 LEX_OUTPUT_ROOT = @LEX_OUTPUT_ROOT@
+LIBINTL = @LIBINTL@
+LIBINTL_DEP = @LIBINTL_DEP@
 LIBM = @LIBM@
 LIBOBJS = @LIBOBJS@
 LIBS = @LIBS@
@@ -124,6 +133,8 @@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@
 MAKEINFO = @MAKEINFO@
 MKINSTALLDIRS = @MKINSTALLDIRS@
 MSGFMT = @MSGFMT@
+MSGMERGE = @MSGMERGE@
+NM = @NM@
 NO_WERROR = @NO_WERROR@
 OBJEXT = @OBJEXT@
 OPCODES_LIB = @OPCODES_LIB@
@@ -134,19 +145,20 @@ PACKAGE_STRING = @PACKAGE_STRING@
 PACKAGE_TARNAME = @PACKAGE_TARNAME@
 PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
-POFILES = @POFILES@
 POSUB = @POSUB@
 RANLIB = @RANLIB@
+SED = @SED@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
-USE_INCLUDED_LIBINTL = @USE_INCLUDED_LIBINTL@
 USE_NLS = @USE_NLS@
 VERSION = @VERSION@
 WARN_CFLAGS = @WARN_CFLAGS@
 XGETTEXT = @XGETTEXT@
 YACC = @YACC@
+ac_ct_AR = @ac_ct_AR@
 ac_ct_CC = @ac_ct_CC@
+ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
 ac_ct_RANLIB = @ac_ct_RANLIB@
 ac_ct_STRIP = @ac_ct_STRIP@
 am__fastdepCC_FALSE = @am__fastdepCC_FALSE@
@@ -179,10 +191,10 @@ includedir = @includedir@
 infodir = @infodir@
 install_sh = @install_sh@
 install_tooldir = @install_tooldir@
-l = @l@
 libdir = @libdir@
 libexecdir = @libexecdir@
 localstatedir = @localstatedir@
+lt_ECHO = @lt_ECHO@
 mandir = @mandir@
 mkdir_p = @mkdir_p@
 obj_format = @obj_format@
@@ -212,13 +224,20 @@ POD2MAN = pod2man --center="GNU Development Tools" \
 
 man_MANS = as.1
 info_TEXINFOS = as.texinfo 
-AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
-TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
+as_TEXINFOS = asconfig.texi $(CPU_DOCS)
+AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
+		   -I ../../bfd/doc
+
+TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
+		   -I ../../bfd/doc
+
 CPU_DOCS = \
 	c-alpha.texi \
 	c-arc.texi \
 	c-arm.texi \
+	c-avr.texi \
 	c-bfin.texi \
+	c-cr16.texi \
 	c-d10v.texi \
 	c-cris.texi \
 	c-h8300.texi \
@@ -254,14 +273,19 @@ html__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
 
 # This one isn't ready for prime time yet.  Not even a little bit.
 noinst_TEXINFOS = internals.texi
-MAINTAINERCLEANFILES = asconfig.texi gasver.texi
+MAINTAINERCLEANFILES = asconfig.texi as.info
 BASEDIR = $(srcdir)/../..
 BFDDIR = $(BASEDIR)/bfd
 CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in
+
+# Automake 1.9 will only build info files in the objdir if they are
+# mentioned in DISTCLEANFILES.  It doesn't have to be unconditional,
+# though, so we use a bogus condition.
+@GENINSRC_NEVER_TRUE@DISTCLEANFILES = as.info
 all: all-am
 
 .SUFFIXES:
-.SUFFIXES: .dvi .html .info .pdf .ps .texinfo
+.SUFFIXES: .dvi .ps
 $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__configure_deps)
 	@for dep in $?; do \
 	  case '$(am__configure_deps)' in \
@@ -271,9 +295,9 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__confi
 	      exit 1;; \
 	  esac; \
 	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  doc/Makefile'; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus  doc/Makefile'; \
 	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --foreign  doc/Makefile
+	  $(AUTOMAKE) --cygnus  doc/Makefile
 .PRECIOUS: Makefile
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	@case '$?' in \
@@ -301,42 +325,38 @@ clean-libtool:
 distclean-libtool:
 	-rm -f libtool
 
-.texinfo.info:
+as.info: as.texinfo $(as_TEXINFOS)
 	restore=: && backupdir="$(am__leading_dot)am$$$$" && \
-	am__cwd=`pwd` && cd $(srcdir) && \
 	rm -rf $$backupdir && mkdir $$backupdir && \
 	if ($(MAKEINFO) --version) >/dev/null 2>&1; then \
 	  for f in $@ $@-[0-9] $@-[0-9][0-9] $(@:.info=).i[0-9] $(@:.info=).i[0-9][0-9]; do \
 	    if test -f $$f; then mv $$f $$backupdir; restore=mv; else :; fi; \
 	  done; \
 	else :; fi && \
-	cd "$$am__cwd"; \
 	if $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
-	 -o $@ $<; \
+	 -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo; \
 	then \
 	  rc=0; \
-	  cd $(srcdir); \
 	else \
 	  rc=$$?; \
-	  cd $(srcdir) && \
 	  $$restore $$backupdir/* `echo "./$@" | sed 's|[^/]*$$||'`; \
 	fi; \
 	rm -rf $$backupdir; exit $$rc
 
-.texinfo.dvi:
+as.dvi: as.texinfo $(as_TEXINFOS) 
 	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
 	MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
-	$(TEXI2DVI) $<
+	$(TEXI2DVI) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo
 
-.texinfo.pdf:
+as.pdf: as.texinfo $(as_TEXINFOS) 
 	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
 	MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
-	$(TEXI2PDF) $<
+	$(TEXI2PDF) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo
 
-.texinfo.html:
+as.html: as.texinfo $(as_TEXINFOS) 
 	rm -rf $(@:.html=.htp)
 	if $(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
-	 -o $(@:.html=.htp) $<; \
+	 -o $(@:.html=.htp) `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo; \
 	then \
 	  rm -rf $@; \
 	  if test ! -d $(@:.html=.htp) && test -d $(@:.html=); then \
@@ -346,10 +366,6 @@ distclean-libtool:
 	    rm -rf $(@:.html=); else rm -Rf $(@:.html=.htp) $@; fi; \
 	  exit 1; \
 	fi
-$(srcdir)/as.info: as.texinfo 
-as.dvi: as.texinfo 
-as.pdf: as.texinfo 
-as.html: as.texinfo 
 .dvi.ps:
 	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
 	$(DVIPS) -o $@ $<
@@ -481,6 +497,7 @@ clean-generic:
 
 distclean-generic:
 	-test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+	-test -z "$(DISTCLEANFILES)" || rm -f $(DISTCLEANFILES)
 
 maintainer-clean-generic:
 	@echo "This command is intended for maintainers to use"
@@ -586,13 +603,6 @@ asconfig.texi: $(CONFIG).texi
 	cp $(srcdir)/$(CONFIG).texi ./asconfig.texi
 	chmod u+w ./asconfig.texi
 
-gasver.texi: $(srcdir)/../../bfd/configure
-	rm -f $@
-	eval `grep '^ *VERSION=' $(srcdir)/../../bfd/configure`; \
-	  echo "@set VERSION $$VERSION" > $@
-
-$(srcdir)/as.info as.dvi as.html: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
-
 # We want install to imply install-info as per GNU standards, despite the
 # cygnus option.
 install-data-local: install-info
@@ -624,7 +634,7 @@ info-local: $(MANS)
 # Build the man page from the texinfo file
 # The sed command removes the no-adjust Nroff command so that
 # the man output looks standard.
-as.1: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
+as.1: $(srcdir)/as.texinfo asconfig.texi $(CPU_DOCS)
 	touch $@
 	-$(TEXI2POD) $(MANCONF) < $(srcdir)/as.texinfo > as.pod
 	-($(POD2MAN) as.pod | \
diff --git a/contrib/binutils/gas/doc/all.texi b/contrib/binutils/gas/doc/all.texi
index 5192f54..b4778bf 100644
--- a/contrib/binutils/gas/doc/all.texi
+++ b/contrib/binutils/gas/doc/all.texi
@@ -29,7 +29,9 @@
 @set ALPHA
 @set ARC
 @set ARM
+@set AVR
 @set BFIN
+@set CR16
 @set CRIS
 @set D10V
 @set D30V
@@ -63,7 +65,7 @@
 @set Z80
 @set Z8000
 
-@c Does this version of the assembler use the difference-table kluge?
+@c Does this version of the assembler use the difference-table kludge?
 @set DIFF-TBL-KLUGE
 
 @c Do all machines described use IEEE floating point?
diff --git a/contrib/binutils/gas/doc/as.1 b/contrib/binutils/gas/doc/as.1
deleted file mode 100644
index 89e3b4c..0000000
--- a/contrib/binutils/gas/doc/as.1
+++ /dev/null
@@ -1,1109 +0,0 @@
-.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.32
-.\"
-.\" Standard preamble:
-.\" ========================================================================
-.de Sh \" Subsection heading
-.br
-.if t .Sp
-.ne 5
-.PP
-\fB\\$1\fR
-.PP
-..
-.de Sp \" Vertical space (when we can't use .PP)
-.if t .sp .5v
-.if n .sp
-..
-.de Vb \" Begin verbatim text
-.ft CW
-.nf
-.ne \\$1
-..
-.de Ve \" End verbatim text
-.ft R
-.fi
-..
-.\" Set up some character translations and predefined strings.  \*(-- will
-.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
-.\" double quote, and \*(R" will give a right double quote.  \*(C+ will
-.\" give a nicer C++.  Capital omega is used to do unbreakable dashes and
-.\" therefore won't be available.  \*(C` and \*(C' expand to `' in nroff,
-.\" nothing in troff, for use with C<>.
-.tr \(*W-
-.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
-.ie n \{\
-.    ds -- \(*W-
-.    ds PI pi
-.    if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
-.    if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\"  diablo 12 pitch
-.    ds L" ""
-.    ds R" ""
-.    ds C` ""
-.    ds C' ""
-'br\}
-.el\{\
-.    ds -- \|\(em\|
-.    ds PI \(*p
-.    ds L" ``
-.    ds R" ''
-'br\}
-.\"
-.\" If the F register is turned on, we'll generate index entries on stderr for
-.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
-.\" entries marked with X<> in POD.  Of course, you'll have to process the
-.\" output yourself in some meaningful fashion.
-.if \nF \{\
-.    de IX
-.    tm Index:\\$1\t\\n%\t"\\$2"
-..
-.    nr % 0
-.    rr F
-.\}
-.\"
-.\" For nroff, turn off justification.  Always turn off hyphenation; it makes
-.\" way too many mistakes in technical documents.
-.hy 0
-.\"
-.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
-.\" Fear.  Run.  Save yourself.  No user-serviceable parts.
-.    \" fudge factors for nroff and troff
-.if n \{\
-.    ds #H 0
-.    ds #V .8m
-.    ds #F .3m
-.    ds #[ \f1
-.    ds #] \fP
-.\}
-.if t \{\
-.    ds #H ((1u-(\\\\n(.fu%2u))*.13m)
-.    ds #V .6m
-.    ds #F 0
-.    ds #[ \&
-.    ds #] \&
-.\}
-.    \" simple accents for nroff and troff
-.if n \{\
-.    ds ' \&
-.    ds ` \&
-.    ds ^ \&
-.    ds , \&
-.    ds ~ ~
-.    ds /
-.\}
-.if t \{\
-.    ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
-.    ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
-.    ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
-.    ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
-.    ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
-.    ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
-.\}
-.    \" troff and (daisy-wheel) nroff accents
-.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
-.ds 8 \h'\*(#H'\(*b\h'-\*(#H'
-.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#]
-.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H'
-.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u'
-.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#]
-.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#]
-.ds ae a\h'-(\w'a'u*4/10)'e
-.ds Ae A\h'-(\w'A'u*4/10)'E
-.    \" corrections for vroff
-.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u'
-.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u'
-.    \" for low resolution devices (crt and lpr)
-.if \n(.H>23 .if \n(.V>19 \
-\{\
-.    ds : e
-.    ds 8 ss
-.    ds o a
-.    ds d- d\h'-1'\(ga
-.    ds D- D\h'-1'\(hy
-.    ds th \o'bp'
-.    ds Th \o'LP'
-.    ds ae ae
-.    ds Ae AE
-.\}
-.rm #[ #] #H #V #F C
-.\" ========================================================================
-.\"
-.IX Title "AS 1"
-.TH AS 1 "2006-06-23" "binutils-2.17" "GNU Development Tools"
-.SH "NAME"
-AS \- the portable GNU assembler.
-.SH "SYNOPSIS"
-.IX Header "SYNOPSIS"
-as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]
- [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]
- [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]
- [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR]
- [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR]
- [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR
- \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-reduce\-memory\-overheads\fR] [\fB\-\-statistics\fR]
- [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR]
- [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR]
- [\fB\-\-target\-help\fR] [\fItarget-options\fR]
- [\fB\-\-\fR|\fIfiles\fR ...]
-.PP
-\&\fITarget Alpha options:\fR
-   [\fB\-m\fR\fIcpu\fR]
-   [\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
-   [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
-   [\fB\-F\fR] [\fB\-32addr\fR]
-.PP
-\&\fITarget \s-1ARC\s0 options:\fR
-   [\fB\-marc[5|6|7|8]\fR]
-   [\fB\-EB\fR|\fB\-EL\fR]
-.PP
-\&\fITarget \s-1ARM\s0 options:\fR
-   [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
-   [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
-   [\fB\-mfpu\fR=\fIfloating-point-format\fR]
-   [\fB\-mfloat\-abi\fR=\fIabi\fR]
-   [\fB\-meabi\fR=\fIver\fR]
-   [\fB\-mthumb\fR]
-   [\fB\-EB\fR|\fB\-EL\fR]
-   [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
-    \fB\-mapcs\-reentrant\fR]
-   [\fB\-mthumb\-interwork\fR] [\fB\-k\fR]
-.PP
-\&\fITarget \s-1CRIS\s0 options:\fR
-   [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
-   [\fB\-\-pic\fR] [\fB\-N\fR]
-   [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
-   [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR]
-.PP
-\&\fITarget D10V options:\fR
-   [\fB\-O\fR]
-.PP
-\&\fITarget D30V options:\fR
-   [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
-.PP
-\&\fITarget i386 options:\fR
-   [\fB\-\-32\fR|\fB\-\-64\fR] [\fB\-n\fR]
-.PP
-\&\fITarget i960 options:\fR
-   [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|
-    \fB\-AKC\fR|\fB\-AMC\fR]
-   [\fB\-b\fR] [\fB\-no\-relax\fR]
-.PP
-\&\fITarget \s-1IA\-64\s0 options:\fR
-   [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR]
-   [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR]
-   [\fB\-mle\fR|\fBmbe\fR]
-   [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR]
-   [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]
-   [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]
-   [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR]
-.PP
-\&\fITarget \s-1IP2K\s0 options:\fR
-   [\fB\-mip2022\fR|\fB\-mip2022ext\fR]
-.PP
-\&\fITarget M32C options:\fR
-   [\fB\-m32c\fR|\fB\-m16c\fR]
-.PP
-\&\fITarget M32R options:\fR
-   [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
-   \fB\-\-W[n]p\fR]
-.PP
-\&\fITarget M680X0 options:\fR
-   [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
-.PP
-\&\fITarget M68HC11 options:\fR
-   [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR]
-   [\fB\-mshort\fR|\fB\-mlong\fR]
-   [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR]
-   [\fB\-\-force\-long\-branchs\fR] [\fB\-\-short\-branchs\fR]
-   [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
-   [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
-.PP
-\&\fITarget \s-1MCORE\s0 options:\fR
-   [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
-   [\fB\-mcpu=[210|340]\fR]
-.PP
-\&\fITarget \s-1MIPS\s0 options:\fR
-   [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]
-   [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]
-   [\fB\-non_shared\fR] [\fB\-xgot\fR]
-   [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]
-   [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]
-   [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]
-   [\fB\-mips64\fR] [\fB\-mips64r2\fR]
-   [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]
-   [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]
-   [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]
-   [\fB\-mips16\fR] [\fB\-no\-mips16\fR]
-   [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]
-   [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]
-   [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR]
-   [\fB\-mmt\fR] [\fB\-mno\-mt\fR]
-   [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]
-   [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR]
-.PP
-\&\fITarget \s-1MMIX\s0 options:\fR
-   [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
-   [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
-   [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
-   [\fB\-\-linker\-allocated\-gregs\fR]
-.PP
-\&\fITarget \s-1PDP11\s0 options:\fR
-   [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
-   [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
-   [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]  
-.PP
-\&\fITarget picoJava options:\fR
-   [\fB\-mb\fR|\fB\-me\fR]
-.PP
-\&\fITarget PowerPC options:\fR
-   [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|
-    \fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|
-    \fB\-mbooke32\fR|\fB\-mbooke64\fR]
-   [\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR]
-   [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
-   [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR]
-   [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR]
-   [\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
-.PP
-\&\fITarget \s-1SPARC\s0 options:\fR
-   [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
-    \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]
-   [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR]
-   [\fB\-32\fR|\fB\-64\fR]
-.PP
-\&\fITarget \s-1TIC54X\s0 options:\fR
- [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR] 
- [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR]
-.PP
-\&\fITarget Z80 options:\fR
-  [\fB\-z80\fR] [\fB\-r800\fR]
-  [ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR]
-  [ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR]
-  [ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR]
-  [ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR]
-  [ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR]
-  [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR]
-.PP
-\&\fITarget Xtensa options:\fR
- [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]absolute\-literals\fR]
- [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]
- [\fB\-\-[no\-]transform\fR]
- [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR]
-.SH "DESCRIPTION"
-.IX Header "DESCRIPTION"
-\&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
-If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
-should find a fairly similar environment when you use it on another
-architecture.  Each version has much in common with the others,
-including object file formats, most assembler directives (often called
-\&\fIpseudo-ops\fR) and assembler syntax.
-.PP
-\&\fBas\fR is primarily intended to assemble the output of the
-\&\s-1GNU\s0 C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker
-\&\f(CW\*(C`ld\*(C'\fR.  Nevertheless, we've tried to make \fBas\fR
-assemble correctly everything that other assemblers for the same
-machine would assemble.
-Any exceptions are documented explicitly.
-This doesn't mean \fBas\fR always uses the same syntax as another
-assembler for the same architecture; for example, we know of several
-incompatible versions of 680x0 assembly language syntax.
-.PP
-Each time you run \fBas\fR it assembles exactly one source
-program.  The source program is made up of one or more files.
-(The standard input is also a file.)
-.PP
-You give \fBas\fR a command line that has zero or more input file
-names.  The input files are read (from left file name to right).  A
-command line argument (in any position) that has no special meaning
-is taken to be an input file name.
-.PP
-If you give \fBas\fR no file names it attempts to read one input file
-from the \fBas\fR standard input, which is normally your terminal.  You
-may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
-to assemble.
-.PP
-Use \fB\-\-\fR if you need to explicitly name the standard input file
-in your command line.
-.PP
-If the source is empty, \fBas\fR produces a small, empty object
-file.
-.PP
-\&\fBas\fR may write warnings and error messages to the standard error
-file (usually your terminal).  This should not happen when  a compiler
-runs \fBas\fR automatically.  Warnings report an assumption made so
-that \fBas\fR could keep assembling a flawed program; errors report a
-grave problem that stops the assembly.
-.PP
-If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler,
-you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
-The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
-by commas.  For example:
-.PP
-.Vb 1
-\&        gcc \-c \-g \-O \-Wa,\-alh,\-L file.c
-.Ve
-.PP
-This passes two options to the assembler: \fB\-alh\fR (emit a listing to
-standard output with high-level and assembly source) and \fB\-L\fR (retain
-local symbols in the symbol table).
-.PP
-Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
-command-line options are automatically passed to the assembler by the compiler.
-(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
-precisely what options it passes to each compilation pass, including the
-assembler.)
-.SH "OPTIONS"
-.IX Header "OPTIONS"
-.IP "\fB@\fR\fIfile\fR" 4
-.IX Item "@file"
-Read command-line options from \fIfile\fR.  The options read are
-inserted in place of the original @\fIfile\fR option.  If \fIfile\fR
-does not exist, or cannot be read, then the option will be treated
-literally, and not removed.  
-.Sp
-Options in \fIfile\fR are separated by whitespace.  A whitespace
-character may be included in an option by surrounding the entire
-option in either single or double quotes.  Any character (including a
-backslash) may be included by prefixing the character to be included
-with a backslash.  The \fIfile\fR may itself contain additional
-@\fIfile\fR options; any such options will be processed recursively.
-.IP "\fB\-a[cdhlmns]\fR" 4
-.IX Item "-a[cdhlmns]"
-Turn on listings, in any of a variety of ways:
-.RS 4
-.IP "\fB\-ac\fR" 4
-.IX Item "-ac"
-omit false conditionals
-.IP "\fB\-ad\fR" 4
-.IX Item "-ad"
-omit debugging directives
-.IP "\fB\-ah\fR" 4
-.IX Item "-ah"
-include high-level source
-.IP "\fB\-al\fR" 4
-.IX Item "-al"
-include assembly
-.IP "\fB\-am\fR" 4
-.IX Item "-am"
-include macro expansions
-.IP "\fB\-an\fR" 4
-.IX Item "-an"
-omit forms processing
-.IP "\fB\-as\fR" 4
-.IX Item "-as"
-include symbols
-.IP "\fB=file\fR" 4
-.IX Item "=file"
-set the name of the listing file
-.RE
-.RS 4
-.Sp
-You may combine these options; for example, use \fB\-aln\fR for assembly
-listing without forms processing.  The \fB=file\fR option, if used, must be
-the last one.  By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
-.RE
-.IP "\fB\-\-alternate\fR" 4
-.IX Item "--alternate"
-Begin in alternate macro mode, see \fBAltmacro,,\f(CB\*(C`.altmacro\*(C'\fB\fR.
-.IP "\fB\-D\fR" 4
-.IX Item "-D"
-Ignored.  This option is accepted for script compatibility with calls to
-other assemblers.
-.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
-.IX Item "--defsym sym=value"
-Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
-\&\fIvalue\fR must be an integer constant.  As in C, a leading \fB0x\fR
-indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value.
-.IP "\fB\-f\fR" 4
-.IX Item "-f"
-\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is
-compiler output).
-.IP "\fB\-g\fR" 4
-.IX Item "-g"
-.PD 0
-.IP "\fB\-\-gen\-debug\fR" 4
-.IX Item "--gen-debug"
-.PD
-Generate debugging information for each assembler source line using whichever
-debug format is preferred by the target.  This currently means either \s-1STABS\s0,
-\&\s-1ECOFF\s0 or \s-1DWARF2\s0.
-.IP "\fB\-\-gstabs\fR" 4
-.IX Item "--gstabs"
-Generate stabs debugging information for each assembler line.  This
-may help debugging assembler code, if the debugger can handle it.
-.IP "\fB\-\-gstabs+\fR" 4
-.IX Item "--gstabs+"
-Generate stabs debugging information for each assembler line, with \s-1GNU\s0
-extensions that probably only gdb can handle, and that could make other
-debuggers crash or refuse to read your program.  This
-may help debugging assembler code.  Currently the only \s-1GNU\s0 extension is
-the location of the current working directory at assembling time.
-.IP "\fB\-\-gdwarf\-2\fR" 4
-.IX Item "--gdwarf-2"
-Generate \s-1DWARF2\s0 debugging information for each assembler line.  This
-may help debugging assembler code, if the debugger can handle it.  Note\-\-\-this
-option is only supported by some targets, not all of them.
-.IP "\fB\-\-help\fR" 4
-.IX Item "--help"
-Print a summary of the command line options and exit.
-.IP "\fB\-\-target\-help\fR" 4
-.IX Item "--target-help"
-Print a summary of all target specific options and exit.
-.IP "\fB\-I\fR \fIdir\fR" 4
-.IX Item "-I dir"
-Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
-.IP "\fB\-J\fR" 4
-.IX Item "-J"
-Don't warn about signed overflow.
-.IP "\fB\-K\fR" 4
-.IX Item "-K"
-Issue warnings when difference tables altered for long displacements.
-.IP "\fB\-L\fR" 4
-.IX Item "-L"
-.PD 0
-.IP "\fB\-\-keep\-locals\fR" 4
-.IX Item "--keep-locals"
-.PD
-Keep (in the symbol table) local symbols.  On traditional a.out systems
-these start with \fBL\fR, but different systems have different local
-label prefixes.
-.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
-.IX Item "--listing-lhs-width=number"
-Set the maximum width, in words, of the output data column for an assembler
-listing to \fInumber\fR.
-.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
-.IX Item "--listing-lhs-width2=number"
-Set the maximum width, in words, of the output data column for continuation
-lines in an assembler listing to \fInumber\fR.
-.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
-.IX Item "--listing-rhs-width=number"
-Set the maximum width of an input source line, as displayed in a listing, to
-\&\fInumber\fR bytes.
-.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
-.IX Item "--listing-cont-lines=number"
-Set the maximum number of lines printed in a listing for a single line of input
-to \fInumber\fR + 1.
-.IP "\fB\-o\fR \fIobjfile\fR" 4
-.IX Item "-o objfile"
-Name the object-file output from \fBas\fR \fIobjfile\fR.
-.IP "\fB\-R\fR" 4
-.IX Item "-R"
-Fold the data section into the text section.
-.Sp
-Set the default size of \s-1GAS\s0's hash tables to a prime number close to
-\&\fInumber\fR.  Increasing this value can reduce the length of time it takes the
-assembler to perform its tasks, at the expense of increasing the assembler's
-memory requirements.  Similarly reducing this value can reduce the memory
-requirements at the expense of speed.
-.IP "\fB\-\-reduce\-memory\-overheads\fR" 4
-.IX Item "--reduce-memory-overheads"
-This option reduces \s-1GAS\s0's memory requirements, at the expense of making the
-assembly processes slower.  Currently this switch is a synonym for
-\&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well.
-.IP "\fB\-\-statistics\fR" 4
-.IX Item "--statistics"
-Print the maximum space (in bytes) and total time (in seconds) used by
-assembly.
-.IP "\fB\-\-strip\-local\-absolute\fR" 4
-.IX Item "--strip-local-absolute"
-Remove local absolute symbols from the outgoing symbol table.
-.IP "\fB\-v\fR" 4
-.IX Item "-v"
-.PD 0
-.IP "\fB\-version\fR" 4
-.IX Item "-version"
-.PD
-Print the \fBas\fR version.
-.IP "\fB\-\-version\fR" 4
-.IX Item "--version"
-Print the \fBas\fR version and exit.
-.IP "\fB\-W\fR" 4
-.IX Item "-W"
-.PD 0
-.IP "\fB\-\-no\-warn\fR" 4
-.IX Item "--no-warn"
-.PD
-Suppress warning messages.
-.IP "\fB\-\-fatal\-warnings\fR" 4
-.IX Item "--fatal-warnings"
-Treat warnings as errors.
-.IP "\fB\-\-warn\fR" 4
-.IX Item "--warn"
-Don't suppress warning messages or treat them as errors.
-.IP "\fB\-w\fR" 4
-.IX Item "-w"
-Ignored.
-.IP "\fB\-x\fR" 4
-.IX Item "-x"
-Ignored.
-.IP "\fB\-Z\fR" 4
-.IX Item "-Z"
-Generate an object file even after errors.
-.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
-.IX Item "-- | files ..."
-Standard input, or source files to assemble.
-.PP
-The following options are available when as is configured for
-an \s-1ARC\s0 processor.
-.IP "\fB\-marc[5|6|7|8]\fR" 4
-.IX Item "-marc[5|6|7|8]"
-This option selects the core processor variant.
-.IP "\fB\-EB | \-EL\fR" 4
-.IX Item "-EB | -EL"
-Select either big-endian (\-EB) or little-endian (\-EL) output.
-.PP
-The following options are available when as is configured for the \s-1ARM\s0
-processor family.
-.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
-.IX Item "-mcpu=processor[+extension...]"
-Specify which \s-1ARM\s0 processor variant is the target.
-.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
-.IX Item "-march=architecture[+extension...]"
-Specify which \s-1ARM\s0 architecture variant is used by the target.
-.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
-.IX Item "-mfpu=floating-point-format"
-Select which Floating Point architecture is the target.
-.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4
-.IX Item "-mfloat-abi=abi"
-Select which floating point \s-1ABI\s0 is in use.
-.IP "\fB\-mthumb\fR" 4
-.IX Item "-mthumb"
-Enable Thumb only instruction decoding.
-.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4
-.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant"
-Select which procedure calling convention is in use.
-.IP "\fB\-EB | \-EL\fR" 4
-.IX Item "-EB | -EL"
-Select either big-endian (\-EB) or little-endian (\-EL) output.
-.IP "\fB\-mthumb\-interwork\fR" 4
-.IX Item "-mthumb-interwork"
-Specify that the code has been generated with interworking between Thumb and
-\&\s-1ARM\s0 code in mind.
-.IP "\fB\-k\fR" 4
-.IX Item "-k"
-Specify that \s-1PIC\s0 code has been generated.
-.PP
-See the info pages for documentation of the CRIS-specific options.
-.PP
-The following options are available when as is configured for
-a D10V processor.
-.IP "\fB\-O\fR" 4
-.IX Item "-O"
-Optimize output by parallelizing instructions.
-.PP
-The following options are available when as is configured for a D30V
-processor.
-.IP "\fB\-O\fR" 4
-.IX Item "-O"
-Optimize output by parallelizing instructions.
-.IP "\fB\-n\fR" 4
-.IX Item "-n"
-Warn when nops are generated.
-.IP "\fB\-N\fR" 4
-.IX Item "-N"
-Warn when a nop after a 32\-bit multiply instruction is generated.
-.PP
-The following options are available when as is configured for the
-Intel 80960 processor.
-.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4
-.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
-Specify which variant of the 960 architecture is the target.
-.IP "\fB\-b\fR" 4
-.IX Item "-b"
-Add code to collect statistics about branches taken.
-.IP "\fB\-no\-relax\fR" 4
-.IX Item "-no-relax"
-Do not alter compare-and-branch instructions for long displacements;
-error if necessary.
-.PP
-The following options are available when as is configured for the
-Ubicom \s-1IP2K\s0 series.
-.IP "\fB\-mip2022ext\fR" 4
-.IX Item "-mip2022ext"
-Specifies that the extended \s-1IP2022\s0 instructions are allowed.
-.IP "\fB\-mip2022\fR" 4
-.IX Item "-mip2022"
-Restores the default behaviour, which restricts the permitted instructions to
-just the basic \s-1IP2022\s0 ones.
-.PP
-The following options are available when as is configured for the
-Renesas M32C and M16C processors.
-.IP "\fB\-m32c\fR" 4
-.IX Item "-m32c"
-Assemble M32C instructions.
-.IP "\fB\-m16c\fR" 4
-.IX Item "-m16c"
-Assemble M16C instructions (the default).
-.PP
-The following options are available when as is configured for the
-Renesas M32R (formerly Mitsubishi M32R) series.
-.IP "\fB\-\-m32rx\fR" 4
-.IX Item "--m32rx"
-Specify which processor in the M32R family is the target.  The default
-is normally the M32R, but this option changes it to the M32RX.
-.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
-.IX Item "--warn-explicit-parallel-conflicts or --Wp"
-Produce warning messages when questionable parallel constructs are
-encountered. 
-.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
-.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
-Do not produce warning messages when questionable parallel constructs are 
-encountered. 
-.PP
-The following options are available when as is configured for the
-Motorola 68000 series.
-.IP "\fB\-l\fR" 4
-.IX Item "-l"
-Shorten references to undefined symbols, to one word instead of two.
-.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
-.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
-.PD 0
-.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
-.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
-.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
-.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
-.PD
-Specify what processor in the 68000 family is the target.  The default
-is normally the 68020, but this can be changed at configuration time.
-.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
-.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
-The target machine does (or does not) have a floating-point coprocessor.
-The default is to assume a coprocessor for 68020, 68030, and cpu32.  Although
-the basic 68000 is not compatible with the 68881, a combination of the
-two can be specified, since it's possible to do emulation of the
-coprocessor instructions with the main processor.
-.IP "\fB\-m68851 | \-mno\-68851\fR" 4
-.IX Item "-m68851 | -mno-68851"
-The target machine does (or does not) have a memory-management
-unit coprocessor.  The default is to assume an \s-1MMU\s0 for 68020 and up.
-.PP
-For details about the \s-1PDP\-11\s0 machine dependent features options,
-see \fBPDP\-11\-Options\fR.
-.IP "\fB\-mpic | \-mno\-pic\fR" 4
-.IX Item "-mpic | -mno-pic"
-Generate position-independent (or position\-dependent) code.  The
-default is \fB\-mpic\fR.
-.IP "\fB\-mall\fR" 4
-.IX Item "-mall"
-.PD 0
-.IP "\fB\-mall\-extensions\fR" 4
-.IX Item "-mall-extensions"
-.PD
-Enable all instruction set extensions.  This is the default.
-.IP "\fB\-mno\-extensions\fR" 4
-.IX Item "-mno-extensions"
-Disable all instruction set extensions.
-.IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4
-.IX Item "-mextension | -mno-extension"
-Enable (or disable) a particular instruction set extension.
-.IP "\fB\-m\fR\fIcpu\fR" 4
-.IX Item "-mcpu"
-Enable the instruction set extensions supported by a particular \s-1CPU\s0, and
-disable all other extensions.
-.IP "\fB\-m\fR\fImachine\fR" 4
-.IX Item "-mmachine"
-Enable the instruction set extensions supported by a particular machine
-model, and disable all other extensions.
-.PP
-The following options are available when as is configured for
-a picoJava processor.
-.IP "\fB\-mb\fR" 4
-.IX Item "-mb"
-Generate \*(L"big endian\*(R" format output.
-.IP "\fB\-ml\fR" 4
-.IX Item "-ml"
-Generate \*(L"little endian\*(R" format output.
-.PP
-The following options are available when as is configured for the
-Motorola 68HC11 or 68HC12 series.
-.IP "\fB\-m68hc11 | \-m68hc12 | \-m68hcs12\fR" 4
-.IX Item "-m68hc11 | -m68hc12 | -m68hcs12"
-Specify what processor is the target.  The default is
-defined by the configuration option when building the assembler.
-.IP "\fB\-mshort\fR" 4
-.IX Item "-mshort"
-Specify to use the 16\-bit integer \s-1ABI\s0.
-.IP "\fB\-mlong\fR" 4
-.IX Item "-mlong"
-Specify to use the 32\-bit integer \s-1ABI\s0.  
-.IP "\fB\-mshort\-double\fR" 4
-.IX Item "-mshort-double"
-Specify to use the 32\-bit double \s-1ABI\s0.  
-.IP "\fB\-mlong\-double\fR" 4
-.IX Item "-mlong-double"
-Specify to use the 64\-bit double \s-1ABI\s0.  
-.IP "\fB\-\-force\-long\-branchs\fR" 4
-.IX Item "--force-long-branchs"
-Relative branches are turned into absolute ones. This concerns
-conditional branches, unconditional branches and branches to a
-sub routine.
-.IP "\fB\-S | \-\-short\-branchs\fR" 4
-.IX Item "-S | --short-branchs"
-Do not turn relative branchs into absolute ones
-when the offset is out of range.
-.IP "\fB\-\-strict\-direct\-mode\fR" 4
-.IX Item "--strict-direct-mode"
-Do not turn the direct addressing mode into extended addressing mode
-when the instruction does not support direct addressing mode.
-.IP "\fB\-\-print\-insn\-syntax\fR" 4
-.IX Item "--print-insn-syntax"
-Print the syntax of instruction in case of error.
-.IP "\fB\-\-print\-opcodes\fR" 4
-.IX Item "--print-opcodes"
-print the list of instructions with syntax and then exit.
-.IP "\fB\-\-generate\-example\fR" 4
-.IX Item "--generate-example"
-print an example of instruction for each possible instruction and then exit.
-This option is only useful for testing \fBas\fR.
-.PP
-The following options are available when \fBas\fR is configured
-for the \s-1SPARC\s0 architecture:
-.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4
-.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
-.PD 0
-.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4
-.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
-.PD
-Explicitly select a variant of the \s-1SPARC\s0 architecture.
-.Sp
-\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
-\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
-.Sp
-\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
-UltraSPARC extensions.
-.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4
-.IX Item "-xarch=v8plus | -xarch=v8plusa"
-For compatibility with the Solaris v9 assembler.  These options are
-equivalent to \-Av8plus and \-Av8plusa, respectively.
-.IP "\fB\-bump\fR" 4
-.IX Item "-bump"
-Warn when the assembler switches to another architecture.
-.PP
-The following options are available when as is configured for the 'c54x
-architecture. 
-.IP "\fB\-mfar\-mode\fR" 4
-.IX Item "-mfar-mode"
-Enable extended addressing mode.  All addresses and relocations will assume
-extended addressing (usually 23 bits).
-.IP "\fB\-mcpu=\fR\fI\s-1CPU_VERSION\s0\fR" 4
-.IX Item "-mcpu=CPU_VERSION"
-Sets the \s-1CPU\s0 version being compiled for.
-.IP "\fB\-merrors\-to\-file\fR \fI\s-1FILENAME\s0\fR" 4
-.IX Item "-merrors-to-file FILENAME"
-Redirect error output to a file, for broken systems which don't support such
-behaviour in the shell.
-.PP
-The following options are available when as is configured for
-a \s-1MIPS\s0 processor.
-.IP "\fB\-G\fR \fInum\fR" 4
-.IX Item "-G num"
-This option sets the largest size of an object that can be referenced
-implicitly with the \f(CW\*(C`gp\*(C'\fR register.  It is only accepted for targets that
-use \s-1ECOFF\s0 format, such as a DECstation running Ultrix.  The default value is 8.
-.IP "\fB\-EB\fR" 4
-.IX Item "-EB"
-Generate \*(L"big endian\*(R" format output.
-.IP "\fB\-EL\fR" 4
-.IX Item "-EL"
-Generate \*(L"little endian\*(R" format output.
-.IP "\fB\-mips1\fR" 4
-.IX Item "-mips1"
-.PD 0
-.IP "\fB\-mips2\fR" 4
-.IX Item "-mips2"
-.IP "\fB\-mips3\fR" 4
-.IX Item "-mips3"
-.IP "\fB\-mips4\fR" 4
-.IX Item "-mips4"
-.IP "\fB\-mips5\fR" 4
-.IX Item "-mips5"
-.IP "\fB\-mips32\fR" 4
-.IX Item "-mips32"
-.IP "\fB\-mips32r2\fR" 4
-.IX Item "-mips32r2"
-.IP "\fB\-mips64\fR" 4
-.IX Item "-mips64"
-.IP "\fB\-mips64r2\fR" 4
-.IX Item "-mips64r2"
-.PD
-Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
-\&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an
-alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for
-\&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR.
-\&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips64\fR, and
-\&\fB\-mips64r2\fR
-correspond to generic
-\&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, \fB\s-1MIPS64\s0\fR,
-and \fB\s-1MIPS64\s0 Release 2\fR
-\&\s-1ISA\s0 processors, respectively.
-.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4
-.IX Item "-march=CPU"
-Generate code for a particular \s-1MIPS\s0 cpu.
-.IP "\fB\-mtune=\fR\fIcpu\fR" 4
-.IX Item "-mtune=cpu"
-Schedule and tune for a particular \s-1MIPS\s0 cpu.
-.IP "\fB\-mfix7000\fR" 4
-.IX Item "-mfix7000"
-.PD 0
-.IP "\fB\-mno\-fix7000\fR" 4
-.IX Item "-mno-fix7000"
-.PD
-Cause nops to be inserted if the read of the destination register
-of an mfhi or mflo instruction occurs in the following two instructions.
-.IP "\fB\-mdebug\fR" 4
-.IX Item "-mdebug"
-.PD 0
-.IP "\fB\-no\-mdebug\fR" 4
-.IX Item "-no-mdebug"
-.PD
-Cause stabs-style debugging output to go into an ECOFF-style .mdebug
-section instead of the standard \s-1ELF\s0 .stabs sections.
-.IP "\fB\-mpdr\fR" 4
-.IX Item "-mpdr"
-.PD 0
-.IP "\fB\-mno\-pdr\fR" 4
-.IX Item "-mno-pdr"
-.PD
-Control generation of \f(CW\*(C`.pdr\*(C'\fR sections.
-.IP "\fB\-mgp32\fR" 4
-.IX Item "-mgp32"
-.PD 0
-.IP "\fB\-mfp32\fR" 4
-.IX Item "-mfp32"
-.PD
-The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these
-flags force a certain group of registers to be treated as 32 bits wide at
-all times.  \fB\-mgp32\fR controls the size of general-purpose registers
-and \fB\-mfp32\fR controls the size of floating-point registers.
-.IP "\fB\-mips16\fR" 4
-.IX Item "-mips16"
-.PD 0
-.IP "\fB\-no\-mips16\fR" 4
-.IX Item "-no-mips16"
-.PD
-Generate code for the \s-1MIPS\s0 16 processor.  This is equivalent to putting
-\&\f(CW\*(C`.set mips16\*(C'\fR at the start of the assembly file.  \fB\-no\-mips16\fR
-turns off this option.
-.IP "\fB\-mips3d\fR" 4
-.IX Item "-mips3d"
-.PD 0
-.IP "\fB\-no\-mips3d\fR" 4
-.IX Item "-no-mips3d"
-.PD
-Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.
-This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
-\&\fB\-no\-mips3d\fR turns off this option.
-.IP "\fB\-mdmx\fR" 4
-.IX Item "-mdmx"
-.PD 0
-.IP "\fB\-no\-mdmx\fR" 4
-.IX Item "-no-mdmx"
-.PD
-Generate code for the \s-1MDMX\s0 Application Specific Extension.
-This tells the assembler to accept \s-1MDMX\s0 instructions.
-\&\fB\-no\-mdmx\fR turns off this option.
-.IP "\fB\-mdsp\fR" 4
-.IX Item "-mdsp"
-.PD 0
-.IP "\fB\-mno\-dsp\fR" 4
-.IX Item "-mno-dsp"
-.PD
-Generate code for the \s-1DSP\s0 Application Specific Extension.
-This tells the assembler to accept \s-1DSP\s0 instructions.
-\&\fB\-mno\-dsp\fR turns off this option.
-.IP "\fB\-mmt\fR" 4
-.IX Item "-mmt"
-.PD 0
-.IP "\fB\-mno\-mt\fR" 4
-.IX Item "-mno-mt"
-.PD
-Generate code for the \s-1MT\s0 Application Specific Extension.
-This tells the assembler to accept \s-1MT\s0 instructions.
-\&\fB\-mno\-mt\fR turns off this option.
-.IP "\fB\-\-construct\-floats\fR" 4
-.IX Item "--construct-floats"
-.PD 0
-.IP "\fB\-\-no\-construct\-floats\fR" 4
-.IX Item "--no-construct-floats"
-.PD
-The \fB\-\-no\-construct\-floats\fR option disables the construction of
-double width floating point constants by loading the two halves of the
-value into the two single width floating point registers that make up
-the double width register.  By default \fB\-\-construct\-floats\fR is
-selected, allowing construction of these floating point constants.
-.IP "\fB\-\-emulation=\fR\fIname\fR" 4
-.IX Item "--emulation=name"
-This option causes \fBas\fR to emulate \fBas\fR configured
-for some other target, in all respects, including output format (choosing
-between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
-debugging information or store symbol table information, and default
-endianness.  The available configuration names are: \fBmipsecoff\fR,
-\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
-\&\fBmipsbelf\fR.  The first two do not alter the default endianness from that
-of the primary target for which the assembler was configured; the others change
-the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR
-in the name.  Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
-selection in any case.
-.Sp
-This option is currently supported only when the primary target
-\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
-Furthermore, the primary target or others specified with
-\&\fB\-\-enable\-targets=...\fR at configuration time must include support for
-the other format, if both are to be available.  For example, the Irix 5
-configuration includes support for both.
-.Sp
-Eventually, this option will support more configurations, with more
-fine-grained control over the assembler's behavior, and will be supported for
-more processors.
-.IP "\fB\-nocpp\fR" 4
-.IX Item "-nocpp"
-\&\fBas\fR ignores this option.  It is accepted for compatibility with
-the native tools.
-.IP "\fB\-\-trap\fR" 4
-.IX Item "--trap"
-.PD 0
-.IP "\fB\-\-no\-trap\fR" 4
-.IX Item "--no-trap"
-.IP "\fB\-\-break\fR" 4
-.IX Item "--break"
-.IP "\fB\-\-no\-break\fR" 4
-.IX Item "--no-break"
-.PD
-Control how to deal with multiplication overflow and division by zero.
-\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
-(and only work for Instruction Set Architecture level 2 and higher);
-\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
-break exception.
-.IP "\fB\-n\fR" 4
-.IX Item "-n"
-When this option is used, \fBas\fR will issue a warning every
-time it generates a nop instruction from a macro.
-.PP
-The following options are available when as is configured for
-an MCore processor.
-.IP "\fB\-jsri2bsr\fR" 4
-.IX Item "-jsri2bsr"
-.PD 0
-.IP "\fB\-nojsri2bsr\fR" 4
-.IX Item "-nojsri2bsr"
-.PD
-Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation.  By default this is enabled.
-The command line option \fB\-nojsri2bsr\fR can be used to disable it.
-.IP "\fB\-sifilter\fR" 4
-.IX Item "-sifilter"
-.PD 0
-.IP "\fB\-nosifilter\fR" 4
-.IX Item "-nosifilter"
-.PD
-Enable or disable the silicon filter behaviour.  By default this is disabled.
-The default can be overridden by the \fB\-sifilter\fR command line option.
-.IP "\fB\-relax\fR" 4
-.IX Item "-relax"
-Alter jump instructions for long displacements.
-.IP "\fB\-mcpu=[210|340]\fR" 4
-.IX Item "-mcpu=[210|340]"
-Select the cpu type on the target hardware.  This controls which instructions
-can be assembled.
-.IP "\fB\-EB\fR" 4
-.IX Item "-EB"
-Assemble for a big endian target.
-.IP "\fB\-EL\fR" 4
-.IX Item "-EL"
-Assemble for a little endian target.
-.PP
-See the info pages for documentation of the MMIX-specific options.
-.PP
-The following options are available when as is configured for
-an Xtensa processor.
-.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
-.IX Item "--text-section-literals | --no-text-section-literals"
-With \fB\-\-text\-section\-literals\fR, literal pools are interspersed
-in the text section.  The default is
-\&\fB\-\-no\-text\-section\-literals\fR, which places literals in a
-separate section in the output file.  These options only affect literals
-referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for
-absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
-.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4
-.IX Item "--absolute-literals | --no-absolute-literals"
-Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute
-or PC-relative addressing.  The default is to assume absolute addressing
-if the Xtensa processor includes the absolute \f(CW\*(C`L32R\*(C'\fR addressing
-option.  Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR mode can be used.
-.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
-.IX Item "--target-align | --no-target-align"
-Enable or disable automatic alignment to reduce branch penalties at the
-expense of some code density.  The default is \fB\-\-target\-align\fR.
-.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4
-.IX Item "--longcalls | --no-longcalls"
-Enable or disable transformation of call instructions to allow calls
-across a greater range of addresses.  The default is
-\&\fB\-\-no\-longcalls\fR.
-.IP "\fB\-\-transform | \-\-no\-transform\fR" 4
-.IX Item "--transform | --no-transform"
-Enable or disable all assembler transformations of Xtensa instructions.
-The default is \fB\-\-transform\fR;
-\&\fB\-\-no\-transform\fR should be used only in the rare cases when the
-instructions must be exactly as specified in the assembly source.
-.PP
-The following options are available when as is configured for
-a Z80 family processor.
-.IP "\fB\-z80\fR" 4
-.IX Item "-z80"
-Assemble for Z80 processor.
-.IP "\fB\-r800\fR" 4
-.IX Item "-r800"
-Assemble for R800 processor.
-.IP "\fB\-ignore\-undocumented\-instructions\fR" 4
-.IX Item "-ignore-undocumented-instructions"
-.PD 0
-.IP "\fB\-Wnud\fR" 4
-.IX Item "-Wnud"
-.PD
-Assemble undocumented Z80 instructions that also work on R800 without warning.
-.IP "\fB\-ignore\-unportable\-instructions\fR" 4
-.IX Item "-ignore-unportable-instructions"
-.PD 0
-.IP "\fB\-Wnup\fR" 4
-.IX Item "-Wnup"
-.PD
-Assemble all undocumented Z80 instructions without warning.
-.IP "\fB\-warn\-undocumented\-instructions\fR" 4
-.IX Item "-warn-undocumented-instructions"
-.PD 0
-.IP "\fB\-Wud\fR" 4
-.IX Item "-Wud"
-.PD
-Issue a warning for undocumented Z80 instructions that also work on R800.
-.IP "\fB\-warn\-unportable\-instructions\fR" 4
-.IX Item "-warn-unportable-instructions"
-.PD 0
-.IP "\fB\-Wup\fR" 4
-.IX Item "-Wup"
-.PD
-Issue a warning for undocumented Z80 instructions that do notwork on R800.  
-.IP "\fB\-forbid\-undocumented\-instructions\fR" 4
-.IX Item "-forbid-undocumented-instructions"
-.PD 0
-.IP "\fB\-Fud\fR" 4
-.IX Item "-Fud"
-.PD
-Treat all undocumented instructions as errors.
-.IP "\fB\-forbid\-unportable\-instructions\fR" 4
-.IX Item "-forbid-unportable-instructions"
-.PD 0
-.IP "\fB\-Fup\fR" 4
-.IX Item "-Fup"
-.PD
-Treat undocumented Z80 intructions that do notwork on R800 as errors.
-.SH "SEE ALSO"
-.IX Header "SEE ALSO"
-\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
-.SH "COPYRIGHT"
-.IX Header "COPYRIGHT"
-Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
-.PP
-Permission is granted to copy, distribute and/or modify this document
-under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
-or any later version published by the Free Software Foundation;
-with no Invariant Sections, with no Front-Cover Texts, and with no
-Back-Cover Texts.  A copy of the license is included in the
-section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
diff --git a/contrib/binutils/gas/doc/as.texinfo b/contrib/binutils/gas/doc/as.texinfo
index 6daaed0..b6f7f32 100644
--- a/contrib/binutils/gas/doc/as.texinfo
+++ b/contrib/binutils/gas/doc/as.texinfo
@@ -1,6 +1,6 @@
 \input texinfo @c                               -*-Texinfo-*-
 @c  Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-@c  2001, 2002, 2003, 2004, 2005
+@c  2001, 2002, 2003, 2004, 2005, 2006, 2007
 @c  Free Software Foundation, Inc.
 @c UPDATE!!  On future updates--
 @c   (1)   check for new machine-dep cmdline options in
@@ -22,7 +22,7 @@
 @c man begin NAME
 @c ---
 @include asconfig.texi
-@include gasver.texi
+@include bfdver.texi
 @c ---
 @c man end
 @c ---
@@ -96,11 +96,12 @@ END-INFO-DIR-ENTRY
 @finalout
 @syncodeindex ky cp
 
-@ifinfo
+@copying
 This file documents the GNU Assembler "@value{AS}".
 
 @c man begin COPYRIGHT
-Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
+2006, 2007 Free Software Foundation, Inc.
 
 Permission is granted to copy, distribute and/or modify this document
 under the terms of the GNU Free Documentation License, Version 1.1
@@ -110,15 +111,7 @@ Back-Cover Texts.  A copy of the license is included in the
 section entitled ``GNU Free Documentation License''.
 
 @c man end
-
-@ignore
-Permission is granted to process this file through Tex and print the
-results, provided the printed document carries copying permission
-notice identical to this one except for the removal of this paragraph
-(this paragraph not being relevant to the printed manual).
-
-@end ignore
-@end ifinfo
+@end copying
 
 @titlepage
 @title Using @value{AS}
@@ -126,11 +119,15 @@ notice identical to this one except for the removal of this paragraph
 @ifclear GENERIC
 @subtitle for the @value{TARGET} family
 @end ifclear
+@ifset VERSION_PACKAGE
+@sp 1
+@subtitle @value{VERSION_PACKAGE}
+@end ifset
 @sp 1
 @subtitle Version @value{VERSION}
 @sp 1
 @sp 13
-The Free Software Foundation Inc.  thanks The Nice Computer
+The Free Software Foundation Inc.@: thanks The Nice Computer
 Company of Australia for loaning Dean Elsner to write the
 first (Vax) version of @command{as} for Project @sc{gnu}.
 The proprietors, management and staff of TNCCA thank FSF for
@@ -153,7 +150,8 @@ done.
 @end tex
 
 @vskip 0pt plus 1filll
-Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
+2006, 2007 Free Software Foundation, Inc.
 
       Permission is granted to copy, distribute and/or modify this document
       under the terms of the GNU Free Documentation License, Version 1.1
@@ -163,13 +161,17 @@ Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Fr
       section entitled ``GNU Free Documentation License''.
 
 @end titlepage
+@contents
 
 @ifnottex
 @node Top
 @top Using @value{AS}
 
-This file is a user guide to the @sc{gnu} assembler @command{@value{AS}} version
-@value{VERSION}.
+This file is a user guide to the @sc{gnu} assembler @command{@value{AS}}
+@ifset VERSION_PACKAGE
+@value{VERSION_PACKAGE}
+@end ifset
+version @value{VERSION}.
 @ifclear GENERIC
 This version of the file describes @command{@value{AS}} configured to generate
 code for @value{TARGET} architectures.
@@ -191,7 +193,7 @@ section entitled ``GNU Free Documentation License''.
 * Reporting Bugs::              Reporting Bugs
 * Acknowledgements::            Who Did What
 * GNU Free Documentation License::  GNU Free Documentation License
-* Index::                       Index
+* AS Index::                    AS Index
 @end menu
 @end ifnottex
 
@@ -209,7 +211,7 @@ code for @value{TARGET} architectures.
 @cindex option summary
 @cindex summary of options
 Here is a brief summary of how to invoke @command{@value{AS}}.  For details,
-@pxref{Invoking,,Command-Line Options}.
+see @ref{Invoking,,Command-Line Options}.
 
 @c man title AS the portable GNU assembler.
 
@@ -296,6 +298,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 
 @emph{Target i386 options:}
    [@b{--32}|@b{--64}] [@b{-n}]
+   [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] 
 @end ifset
 @ifset I960
 
@@ -343,7 +346,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-m68hc11}|@b{-m68hc12}|@b{-m68hcs12}]
    [@b{-mshort}|@b{-mlong}]
    [@b{-mshort-double}|@b{-mlong-double}]
-   [@b{--force-long-branchs}] [@b{--short-branchs}]
+   [@b{--force-long-branches}] [@b{--short-branches}]
    [@b{--strict-direct-mode}] [@b{--print-insn-syntax}]
    [@b{--print-opcodes}] [@b{--generate-example}]
 @end ifset
@@ -358,7 +361,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @emph{Target MIPS options:}
    [@b{-nocpp}] [@b{-EL}] [@b{-EB}] [@b{-O}[@var{optimization level}]]
    [@b{-g}[@var{debug level}]] [@b{-G} @var{num}] [@b{-KPIC}] [@b{-call_shared}]
-   [@b{-non_shared}] [@b{-xgot}]
+   [@b{-non_shared}] [@b{-xgot} [@b{-mvxworks-pic}]
    [@b{-mabi}=@var{ABI}] [@b{-32}] [@b{-n32}] [@b{-64}] [@b{-mfp32}] [@b{-mgp32}]
    [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}]
    [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}]
@@ -367,9 +370,11 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}]
    [@b{-mfix7000}] [@b{-mno-fix7000}]
    [@b{-mips16}] [@b{-no-mips16}]
+   [@b{-msmartmips}] [@b{-mno-smartmips}]
    [@b{-mips3d}] [@b{-no-mips3d}]
    [@b{-mdmx}] [@b{-no-mdmx}]
    [@b{-mdsp}] [@b{-mno-dsp}]
+   [@b{-mdspr2}] [@b{-mno-dspr2}]
    [@b{-mmt}] [@b{-mno-mt}]
    [@b{-mdebug}] [@b{-no-mdebug}]
    [@b{-mpdr}] [@b{-mno-pdr}]
@@ -487,7 +492,10 @@ listing without forms processing.  The @samp{=file} option, if used, must be
 the last one.  By itself, @samp{-a} defaults to @samp{-ahls}.
 
 @item --alternate
-Begin in alternate macro mode, see @ref{Altmacro,,@code{.altmacro}}.
+Begin in alternate macro mode.
+@ifclear man
+@xref{Altmacro,,@code{.altmacro}}.
+@end ifclear
 
 @item -D
 Ignored.  This option is accepted for script compatibility with calls to
@@ -496,7 +504,9 @@ other assemblers.
 @item --defsym @var{sym}=@var{value}
 Define the symbol @var{sym} to be @var{value} before assembling the input file.
 @var{value} must be an integer constant.  As in C, a leading @samp{0x}
-indicates a hexadecimal value, and a leading @samp{0} indicates an octal value.
+indicates a hexadecimal value, and a leading @samp{0} indicates an octal
+value.  The value of the symbol can be overridden inside a source file via the
+use of a @code{.set} pseudo-op.
 
 @item -f
 ``fast''---skip whitespace and comment preprocessing (assume source is
@@ -546,9 +556,12 @@ Issue warnings when difference tables altered for long displacements.
 
 @item -L
 @itemx --keep-locals
-Keep (in the symbol table) local symbols.  On traditional a.out systems
-these start with @samp{L}, but different systems have different local
-label prefixes.
+Keep (in the symbol table) local symbols.  These symbols start with
+system-specific local label prefixes, typically @samp{.L} for ELF systems
+or @samp{L} for traditional a.out systems.
+@ifclear man
+@xref{Symbol Names}.
+@end ifclear
 
 @item --listing-lhs-width=@var{number}
 Set the maximum width, in words, of the output data column for an assembler
@@ -866,13 +879,13 @@ Specify to use the 32-bit double ABI.
 @item -mlong-double
 Specify to use the 64-bit double ABI.  
 
-@item --force-long-branchs
+@item --force-long-branches
 Relative branches are turned into absolute ones. This concerns
 conditional branches, unconditional branches and branches to a
 sub routine.
 
-@item -S | --short-branchs
-Do not turn relative branchs into absolute ones
+@item -S | --short-branches
+Do not turn relative branches into absolute ones
 when the offset is out of range.
 
 @item --strict-direct-mode
@@ -1006,6 +1019,12 @@ Generate code for the MIPS 16 processor.  This is equivalent to putting
 @code{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
 turns off this option.
 
+@item -msmartmips
+@itemx -mno-smartmips
+Enables the SmartMIPS extension to the MIPS32 instruction set. This is
+equivalent to putting @code{.set smartmips} at the start of the assembly file.
+@samp{-mno-smartmips} turns off this option.
+
 @item -mips3d
 @itemx -no-mips3d
 Generate code for the MIPS-3D Application Specific Extension.
@@ -1020,10 +1039,17 @@ This tells the assembler to accept MDMX instructions.
 
 @item -mdsp
 @itemx -mno-dsp
-Generate code for the DSP Application Specific Extension.
-This tells the assembler to accept DSP instructions.
+Generate code for the DSP Release 1 Application Specific Extension.
+This tells the assembler to accept DSP Release 1 instructions.
 @samp{-mno-dsp} turns off this option.
 
+@item -mdspr2
+@itemx -mno-dspr2
+Generate code for the DSP Release 2 Application Specific Extension.
+This option implies -mdsp.
+This tells the assembler to accept DSP Release 2 instructions.
+@samp{-mno-dspr2} turns off this option.
+
 @item -mmt
 @itemx -mno-mt
 Generate code for the MT Application Specific Extension.
@@ -1173,13 +1199,13 @@ Assemble all undocumented Z80 instructions without warning.
 Issue a warning for undocumented Z80 instructions that also work on R800.
 @item  -warn-unportable-instructions 
 @itemx -Wup
-Issue a warning for undocumented Z80 instructions that do notwork on R800.  
+Issue a warning for undocumented Z80 instructions that do not work on R800.  
 @item  -forbid-undocumented-instructions 
 @itemx -Fud
 Treat all undocumented instructions as errors.
 @item  -forbid-unportable-instructions 
 @itemx -Fup
-Treat undocumented Z80 intructions that do notwork on R800 as errors.
+Treat undocumented Z80 instructions that do not work on R800 as errors.
 @end table
 @end ifset
 
@@ -1504,7 +1530,8 @@ because many of them aren't supposed to happen.
 
 @cindex options, all versions of assembler
 This chapter describes command-line options available in @emph{all}
-versions of the @sc{gnu} assembler; @pxref{Machine Dependencies}, for options specific
+versions of the @sc{gnu} assembler; see @ref{Machine Dependencies},
+for options specific
 @ifclear GENERIC
 to the @value{TARGET} target.
 @end ifclear
@@ -1549,7 +1576,7 @@ assembler.)
 * K::             -K for difference tables
 @end ifset
 
-* L::             -L to retain local labels
+* L::             -L to retain local symbols
 * listing::       --listing-XXX to configure listing output
 * M::		  -M or --mri to assemble in MRI compatibility mode
 * MD::            --MD for dependency tracking
@@ -1604,7 +1631,8 @@ listing-control directives have no effect.
 The letters after @samp{-a} may be combined into one option,
 @emph{e.g.}, @samp{-aln}.
 
-Note if the assembler source is coming from the standard input (eg because it
+Note if the assembler source is coming from the standard input (e.g.,
+because it
 is being created by @code{@value{GCC}} and the @samp{-pipe} command line switch
 is being used) then the listing will not contain any comments or preprocessor
 directives.  This is because the listing code buffers input source lines from
@@ -1674,33 +1702,28 @@ alteration on other platforms.
 @ifset DIFF-TBL-KLUGE
 @cindex difference tables, warning
 @cindex warning for altered difference tables
-@command{@value{AS}} sometimes alters the code emitted for directives of the form
-@samp{.word @var{sym1}-@var{sym2}}; @pxref{Word,,@code{.word}}.
+@command{@value{AS}} sometimes alters the code emitted for directives of the
+form @samp{.word @var{sym1}-@var{sym2}}.  @xref{Word,,@code{.word}}.
 You can use the @samp{-K} option if you want a warning issued when this
 is done.
 @end ifset
 
 @node L
-@section Include Local Labels: @option{-L}
+@section Include Local Symbols: @option{-L}
 
 @kindex -L
-@cindex local labels, retaining in output
-Labels beginning with @samp{L} (upper case only) are called @dfn{local
-labels}. @xref{Symbol Names}.  Normally you do not see such labels when
-debugging, because they are intended for the use of programs (like
-compilers) that compose assembler programs, not for your notice.
-Normally both @command{@value{AS}} and @code{@value{LD}} discard such labels, so you do not
-normally debug with them.
-
-This option tells @command{@value{AS}} to retain those @samp{L@dots{}} symbols
+@cindex local symbols, retaining in output
+Symbols beginning with system-specific local label prefixes, typically
+@samp{.L} for ELF systems or @samp{L} for traditional a.out systems, are
+called @dfn{local symbols}.  @xref{Symbol Names}.  Normally you do not see
+such symbols when debugging, because they are intended for the use of
+programs (like compilers) that compose assembler programs, not for your
+notice.  Normally both @command{@value{AS}} and @code{@value{LD}} discard
+such symbols, so you do not normally debug with them.
+
+This option tells @command{@value{AS}} to retain those local symbols
 in the object file.  Usually if you do this you also tell the linker
-@code{@value{LD}} to preserve symbols whose names begin with @samp{L}.
-
-By default, a local label is any label beginning with @samp{L}, but each
-target is allowed to redefine the local label prefix.
-@ifset HPPA
-On the HPPA local labels begin with @samp{L$}.
-@end ifset
+@code{@value{LD}} to preserve those symbols.
 
 @node listing
 @section Configuring listing output: @option{--listing}
@@ -1708,9 +1731,11 @@ On the HPPA local labels begin with @samp{L$}.
 The listing feature of the assembler can be enabled via the command line switch
 @samp{-a} (@pxref{a}).  This feature combines the input source file(s) with a
 hex dump of the corresponding locations in the output object file, and displays
-them as a listing file.  The format of this listing can be controlled by pseudo
-ops inside the assembler source (@pxref{List} @pxref{Title} @pxref{Sbttl}
-@pxref{Psize} @pxref{Eject}) and also by the following switches:
+them as a listing file.  The format of this listing can be controlled by
+directives inside the assembler source (i.e., @code{.list} (@pxref{List}),
+@code{.title} (@pxref{Title}), @code{.sbttl} (@pxref{Sbttl}),
+@code{.psize} (@pxref{Psize}), and
+@code{.eject} (@pxref{Eject}) and also by the following switches:
 
 @table @gcctabopt
 @item --listing-lhs-width=@samp{number}
@@ -2072,7 +2097,7 @@ anything else you may get from your C compiler's preprocessor.  You can
 do include file processing with the @code{.include} directive
 (@pxref{Include,,@code{.include}}).  You can use the @sc{gnu} C compiler driver
 to get other ``CPP'' style preprocessing by giving the input file a
-@samp{.S} suffix.  @xref{Overall Options,, Options Controlling the Kind of
+@samp{.S} suffix.  @xref{Overall Options, ,Options Controlling the Kind of
 Output, gcc.info, Using GNU CC}.
 
 Excess whitespace, comments, and character constants
@@ -2209,7 +2234,7 @@ extends to the end of the line.
 To be compatible with past assemblers, lines that begin with @samp{#} have a
 special interpretation.  Following the @samp{#} should be an absolute
 expression (@pxref{Expressions}): the logical line number of the @emph{next}
-line.  Then a string (@pxref{Strings,, Strings}) is allowed: if present it is a
+line.  Then a string (@pxref{Strings, ,Strings}) is allowed: if present it is a
 new logical file name.  The rest of the line, if any, should be whitespace.
 
 If the first non-whitespace characters on the line are not numeric,
@@ -2284,8 +2309,8 @@ constants are an exception: they do not end statements.
 @end ifclear
 @ifset GENERIC
 A @dfn{statement} ends at a newline character (@samp{\n}) or line
-separator character.  (The line separator is usually @samp{;}, unless
-this conflicts with the comment character; @pxref{Machine Dependencies}.)  The
+separator character.  (The line separator is usually @samp{;}, unless this
+conflicts with the comment character; see @ref{Machine Dependencies}.)  The
 newline or separator character is considered part of the preceding
 statement.  Newlines and separators within character constants are an
 exception: they do not end statements.
@@ -2670,7 +2695,7 @@ independently of any floating point hardware in the computer running
 @cindex bit fields
 @cindex constants, bit field
 You can also define numeric constants as @dfn{bit fields}.
-specify two numbers separated by a colon---
+Specify two numbers separated by a colon---
 @example
 @var{mask}:@var{value}
 @end example
@@ -3069,8 +3094,8 @@ You
 can also use the @code{.subsection} directive (@pxref{SubSection})
 to specify a subsection: @samp{.subsection @var{expression}}.
 @end ifset
-@var{Expression} should be an absolute expression.
-(@xref{Expressions}.)  If you just say @samp{.text} then @samp{.text 0}
+@var{Expression} should be an absolute expression
+(@pxref{Expressions}).  If you just say @samp{.text} then @samp{.text 0}
 is assumed.  Likewise @samp{.data} means @samp{.data 0}.  Assembly
 begins in @code{text 0}.  For instance:
 @smallexample
@@ -3109,7 +3134,7 @@ The @code{.lcomm} pseudo-op defines a symbol in the bss section; see
 @ref{Lcomm,,@code{.lcomm}}.
 
 The @code{.comm} pseudo-op may be used to declare a common symbol, which is
-another form of uninitialized symbol; see @xref{Comm,,@code{.comm}}.
+another form of uninitialized symbol; see @ref{Comm,,@code{.comm}}.
 
 @ifset GENERIC
 When assembling for a target which supports multiple sections, such as ELF or
@@ -3180,8 +3205,8 @@ equals sign @samp{=}@samp{=} here represents an equivalent of the
 Symbol names begin with a letter or with one of @samp{._}.  On most
 machines, you can also use @code{$} in symbol names; exceptions are
 noted in @ref{Machine Dependencies}.  That character may be followed by any
-string of digits, letters, dollar signs (unless otherwise noted in
-@ref{Machine Dependencies}), and underscores.
+string of digits, letters, dollar signs (unless otherwise noted for a
+particular target machine), and underscores.
 @end ifclear
 @ifset SPECIAL-SYMS
 @ifset H8
@@ -3203,16 +3228,32 @@ in a program.
 
 @cindex local symbol names
 @cindex symbol names, local
+A local symbol is any symbol beginning with certain local label prefixes.
+By default, the local label prefix is @samp{.L} for ELF systems or
+@samp{L} for traditional a.out systems, but each target may have its own
+set of local label prefixes.
+@ifset HPPA
+On the HPPA local symbols begin with @samp{L$}.
+@end ifset
+
+Local symbols are defined and used within the assembler, but they are
+normally not saved in object files.  Thus, they are not visible when debugging.
+You may use the @samp{-L} option (@pxref{L, ,Include Local Symbols:
+@option{-L}}) to retain the local symbols in the object files.
+
+@subheading Local Labels
+
+@cindex local labels
 @cindex temporary symbol names
 @cindex symbol names, temporary
-Local symbols help compilers and programmers use names temporarily.
+Local labels help compilers and programmers use names temporarily.
 They create symbols which are guaranteed to be unique over the entire scope of
 the input source code and which can be referred to by a simple notation.
-To define a local symbol, write a label of the form @samp{@b{N}:} (where @b{N}
+To define a local label, write a label of the form @samp{@b{N}:} (where @b{N}
 represents any positive integer).  To refer to the most recent previous
-definition of that symbol write @samp{@b{N}b}, using the same number as when
+definition of that label write @samp{@b{N}b}, using the same number as when
 you defined the label.  To refer to the next definition of a local label, write
-@samp{@b{N}f}--- The @samp{b} stands for``backwards'' and the @samp{f} stands
+@samp{@b{N}f}---the @samp{b} stands for ``backwards'' and the @samp{f} stands
 for ``forwards''.
 
 There is no restriction on how you can use these labels, and you can reuse them
@@ -3241,16 +3282,17 @@ label_3:  branch label_4
 label_4:  branch label_3
 @end smallexample
 
-Local symbol names are only a notational device.  They are immediately
+Local label names are only a notational device.  They are immediately
 transformed into more conventional symbol names before the assembler uses them.
-The symbol names stored in the symbol table, appearing in error messages and
-optionally emitted to the object file.  The names are constructed using these
-parts:
+The symbol names are stored in the symbol table, appear in error messages, and
+are optionally emitted to the object file.  The names are constructed using
+these parts:
 
 @table @code
-@item L
-All local labels begin with @samp{L}. Normally both @command{@value{AS}} and
-@code{@value{LD}} forget symbols that start with @samp{L}. These labels are
+@item @emph{local label prefix}
+All local symbols begin with the system-specific local label prefix.
+Normally both @command{@value{AS}} and @code{@value{LD}} forget symbols
+that start with the local label prefix.  These labels are
 used for symbols you are never intended to see.  If you use the
 @samp{-L} option then @command{@value{AS}} retains these symbols in the
 object file. If you also instruct @code{@value{LD}} to retain these symbols,
@@ -3268,30 +3310,30 @@ of the same name.  The character has ASCII value of @samp{\002} (control-B).
 This is a serial number to keep the labels distinct.  The first definition of
 @samp{0:} gets the number @samp{1}.  The 15th definition of @samp{0:} gets the 
 number @samp{15}, and so on.  Likewise the first definition of @samp{1:} gets
-the number @samp{1} and its 15th defintion gets @samp{15} as well.
+the number @samp{1} and its 15th definition gets @samp{15} as well.
 @end table
 
-So for example, the first @code{1:} is named @code{L1@kbd{C-B}1}, the 44th
-@code{3:} is named @code{L3@kbd{C-B}44}.
+So for example, the first @code{1:} may be named @code{.L1@kbd{C-B}1}, and
+the 44th @code{3:} may be named @code{.L3@kbd{C-B}44}.
 
 @subheading Dollar Local Labels
 @cindex dollar local symbols
 
 @code{@value{AS}} also supports an even more local form of local labels called
-dollar labels.  These labels go out of scope (ie they become undefined) as soon
-as a non-local label is defined.  Thus they remain valid for only a small
+dollar labels.  These labels go out of scope (i.e., they become undefined) as
+soon as a non-local label is defined.  Thus they remain valid for only a small
 region of the input source code.  Normal local labels, by contrast, remain in
 scope for the entire file, or until they are redefined by another occurrence of
 the same local label.
 
 Dollar labels are defined in exactly the same way as ordinary local labels,
 except that instead of being terminated by a colon, they are terminated by a
-dollar sign.  eg @samp{@b{55$}}.
+dollar sign, e.g., @samp{@b{55$}}.
 
 They can also be distinguished from ordinary local labels by their transformed
-name which uses ASCII character @samp{\001} (control-A) as the magic character
-to distinguish them from ordinary labels.  Thus the 5th defintion of @samp{6$}
-is named @samp{L6@kbd{C-A}5}.
+names which use ASCII character @samp{\001} (control-A) as the magic character
+to distinguish them from ordinary labels.  For example, the fifth definition of
+@samp{6$} may be named @samp{.L6@kbd{C-A}5}.
 
 @node Dot
 @section The Special Dot Symbol
@@ -3722,14 +3764,14 @@ Some machine configurations provide additional directives.
 @end ifset
 @ifclear GENERIC
 @ifset machine-directives
-@xref{Machine Dependencies} for additional directives.
+@xref{Machine Dependencies}, for additional directives.
 @end ifset
 @end ifclear
 
 @menu
 * Abort::                       @code{.abort}
 @ifset COFF
-* ABORT::                       @code{.ABORT}
+* ABORT (COFF)::                       @code{.ABORT}
 @end ifset
 
 * Align::                       @code{.align @var{abs-expr} , @var{abs-expr}}
@@ -3740,7 +3782,7 @@ Some machine configurations provide additional directives.
 * Byte::                        @code{.byte @var{expressions}}
 * Comm::                        @code{.comm @var{symbol} , @var{length} }
 
-* CFI directives::		@code{.cfi_startproc}, @code{.cfi_endproc}, etc.
+* CFI directives::		@code{.cfi_startproc [simple]}, @code{.cfi_endproc}, etc.
 
 * Data::                        @code{.data @var{subsection}}
 @ifset COFF
@@ -3818,8 +3860,8 @@ Some machine configurations provide additional directives.
 * Noaltmacro::                  @code{.noaltmacro}
 * Nolist::                      @code{.nolist}
 * Octa::                        @code{.octa @var{bignums}}
-* Org::                         @code{.org @var{new-lc} , @var{fill}}
-* P2align::                     @code{.p2align @var{abs-expr} , @var{abs-expr}}
+* Org::                         @code{.org @var{new-lc}, @var{fill}}
+* P2align::                     @code{.p2align @var{abs-expr}, @var{abs-expr}, @var{abs-expr}}
 @ifset ELF
 * PopSection::                  @code{.popsection}
 * Previous::                    @code{.previous}
@@ -3837,6 +3879,7 @@ Some machine configurations provide additional directives.
 @end ifset
 
 * Quad::                        @code{.quad @var{bignums}}
+* Reloc::			@code{.reloc @var{offset}, @var{reloc_name}[, @var{expression}]}
 * Rept::			@code{.rept @var{count}}
 * Sbttl::                       @code{.sbttl "@var{subheading}"}
 @ifset COFF
@@ -3907,8 +3950,8 @@ of the source quit, it could use this directive tells @command{@value{AS}} to
 quit also.  One day @code{.abort} will not be supported.
 
 @ifset COFF
-@node ABORT
-@section @code{.ABORT}
+@node ABORT (COFF)
+@section @code{.ABORT} (COFF)
 
 @cindex @code{ABORT} directive
 When producing COFF output, @command{@value{AS}} accepts this directive as a
@@ -4058,19 +4101,40 @@ The syntax for @code{.comm} differs slightly on the HPPA.  The syntax is
 @end ifset
 
 @node CFI directives
-@section @code{.cfi_startproc}
+@section @code{.cfi_startproc [simple]}
 @cindex @code{cfi_startproc} directive
 @code{.cfi_startproc} is used at the beginning of each function that
 should have an entry in @code{.eh_frame}. It initializes some internal
-data structures and emits architecture dependent initial CFI instructions.
-Don't forget to close the function by 
+data structures. Don't forget to close the function by
 @code{.cfi_endproc}.
 
+Unless @code{.cfi_startproc} is used along with parameter @code{simple} 
+it also emits some architecture dependent initial CFI instructions.
+ 
 @section @code{.cfi_endproc}
 @cindex @code{cfi_endproc} directive
 @code{.cfi_endproc} is used at the end of a function where it closes its
 unwind entry previously opened by
-@code{.cfi_startproc}. and emits it to @code{.eh_frame}.
+@code{.cfi_startproc}, and emits it to @code{.eh_frame}.
+
+@section @code{.cfi_personality @var{encoding} [, @var{exp}]}
+@code{.cfi_personality} defines personality routine and its encoding.
+@var{encoding} must be a constant determining how the personality
+should be encoded.  If it is 255 (@code{DW_EH_PE_omit}), second
+argument is not present, otherwise second argument should be
+a constant or a symbol name.  When using indirect encodings,
+the symbol provided should be the location where personality
+can be loaded from, not the personality routine itself.
+The default after @code{.cfi_startproc} is @code{.cfi_personality 0xff},
+no personality routine.
+
+@section @code{.cfi_lsda @var{encoding} [, @var{exp}]}
+@code{.cfi_lsda} defines LSDA and its encoding.
+@var{encoding} must be a constant determining how the LSDA
+should be encoded.  If it is 255 (@code{DW_EH_PE_omit}), second
+argument is not present, otherwise second argument should be a constant
+or a symbol name.  The default after @code{.cfi_startproc} is @code{.cfi_lsda 0xff},
+no LSDA.
 
 @section @code{.cfi_def_cfa @var{register}, @var{offset}}
 @code{.cfi_def_cfa} defines a rule for computing CFA as: @i{take 
@@ -4102,6 +4166,31 @@ using the known displacement of the CFA register from the CFA.
 This is often easier to use, because the number will match the
 code it's annotating.
 
+@section @code{.cfi_register @var{register1}, @var{register2}}
+Previous value of @var{register1} is saved in register @var{register2}.
+
+@section @code{.cfi_restore @var{register}}
+@code{.cfi_restore} says that the rule for @var{register} is now the 
+same as it was at the beginning of the function, after all initial 
+instruction added by @code{.cfi_startproc} were executed.
+
+@section @code{.cfi_undefined @var{register}}
+From now on the previous value of @var{register} can't be restored anymore.
+
+@section @code{.cfi_same_value @var{register}}
+Current value of @var{register} is the same like in the previous frame, 
+i.e. no restoration needed.
+
+@section @code{.cfi_remember_state}, 
+First save all current rules for all registers by @code{.cfi_remember_state}, 
+then totally screw them up by subsequent @code{.cfi_*} directives and when 
+everything is hopelessly bad, use @code{.cfi_restore_state} to restore 
+the previous saved state.
+
+@section @code{.cfi_return_column @var{register}}
+Change return column @var{register}, i.e. the return address is either 
+directly in @var{register} or can be accessed by rules for @var{register}.
+
 @section @code{.cfi_signal_frame}
 Mark current function as signal trampoline.
 
@@ -4121,9 +4210,9 @@ to the @code{.debug_line} file name table.  The @var{fileno} operand should
 be a unique positive integer to use as the index of the entry in the table.
 The @var{filename} operand is a C string literal.
 
-The detail of filename indicies is exposed to the user because the filename
+The detail of filename indices is exposed to the user because the filename
 table is shared with the @code{.debug_info} section of the dwarf2 debugging
-information, and thus the user must know the exact indicies that table
+information, and thus the user must know the exact indices that table
 entries will have.
 
 @section @code{.loc @var{fileno} @var{lineno} [@var{column}] [@var{options}]}
@@ -4262,7 +4351,7 @@ Force a page break at this point, when generating assembly listings.
 
 @cindex @code{else} directive
 @code{.else} is part of the @command{@value{AS}} support for conditional
-assembly; @pxref{If,,@code{.if}}.  It marks the beginning of a section
+assembly; see @ref{If,,@code{.if}}.  It marks the beginning of a section
 of code to be assembled if the condition for the preceding @code{.if}
 was false.
 
@@ -4271,7 +4360,7 @@ was false.
 
 @cindex @code{elseif} directive
 @code{.elseif} is part of the @command{@value{AS}} support for conditional
-assembly; @pxref{If,,@code{.if}}.  It is shorthand for beginning a new
+assembly; see @ref{If,,@code{.if}}.  It is shorthand for beginning a new
 @code{.if} block that would otherwise fill the entire @code{.else} section.
 
 @node End
@@ -4316,7 +4405,7 @@ conditionally.  @xref{If,,@code{.if}}.
 @cindex assigning values to symbols
 @cindex symbols, assigning values to
 This directive sets the value of @var{symbol} to @var{expression}.
-It is synonymous with @samp{.set}; @pxref{Set,,@code{.set}}.
+It is synonymous with @samp{.set}; see @ref{Set,,@code{.set}}.
 
 @ifset HPPA
 The syntax for @code{equ} on the HPPA is 
@@ -4327,8 +4416,8 @@ The syntax for @code{equ} on the HPPA is
 The syntax for @code{equ} on the Z80 is 
 @samp{@var{symbol} equ @var{expression}}. 
 On the Z80 it is an eror if @var{symbol} is already defined,
-but the symbol is not protected from later redefinition, 
-compare @xref{Equiv}.
+but the symbol is not protected from later redefinition. 
+Compare @ref{Equiv}.
 @end ifset
 
 @node Equiv
@@ -4484,7 +4573,7 @@ compatibility with other assemblers.
 @ifset HPPA
 On the HPPA, @code{.global} is not always enough to make it accessible to other
 partial programs.  You may need the HPPA-only @code{.EXPORT} directive as well.
-@xref{HPPA Directives,, HPPA Assembler Directives}.
+@xref{HPPA Directives, ,HPPA Assembler Directives}.
 @end ifset
 
 @ifset ELF
@@ -4721,8 +4810,7 @@ is equivalent to assembling
         move    d3,sp@@-
 @end example
 
-For some caveats with the spelling of @var{symbol}, see also the discussion
-at @xref{Macro}.
+For some caveats with the spelling of @var{symbol}, see also @ref{Macro}.
 
 @node Irpc
 @section @code{.irpc @var{symbol},@var{values}}@dots{}
@@ -4907,7 +4995,7 @@ the initial value of the listing counter is one.
 @section @code{.long @var{expressions}}
 
 @cindex @code{long} directive
-@code{.long} is the same as @samp{.int}, @pxref{Int,,@code{.int}}.
+@code{.long} is the same as @samp{.int}.  @xref{Int,,@code{.int}}.
 
 @ignore
 @c no one seems to know what this is for or whether this description is
@@ -4971,7 +5059,7 @@ indicate whether all invocations must specify a non-blank value (through
 (through @samp{:@code{vararg}}).  You can supply a default value for any
 macro argument by following the name with @samp{=@var{deflt}}.  You
 cannot define two macros with the same @var{macname} unless it has been
-subject to the @code{.purgem} directive (@xref{Purgem}.) between the two
+subject to the @code{.purgem} directive (@pxref{Purgem}) between the two
 definitions.  For example, these are all valid @code{.macro} statements:
 
 @table @code
@@ -4979,7 +5067,7 @@ definitions.  For example, these are all valid @code{.macro} statements:
 Begin the definition of a macro called @code{comm}, which takes no
 arguments.
 
-@item .macro plus1 p, p1
+@item  .macro plus1 p, p1
 @itemx .macro plus1 p p1
 Either statement begins the definition of a macro called @code{plus1},
 which takes two arguments; within the macro definition, write
@@ -4993,7 +5081,6 @@ After the definition is complete, you can call the macro either as
 @var{a} and @samp{\p2} evaluating to @var{b}), or as @samp{reserve_str
 ,@var{b}} (with @samp{\p1} evaluating as the default, in this case
 @samp{0}, and @samp{\p2} evaluating to @var{b}).
-@end table
 
 @item .macro m p1:req, p2=0, p3:vararg
 Begin the definition of a macro called @code{m}, with at least three
@@ -5005,21 +5092,72 @@ When you call a macro, you can specify the argument values either by
 position, or by keyword.  For example, @samp{sum 9,17} is equivalent to
 @samp{sum to=17, from=9}.
 
+@end table
+
 Note that since each of the @var{macargs} can be an identifier exactly
 as any other one permitted by the target architecture, there may be
 occasional problems if the target hand-crafts special meanings to certain
-characters when they occur in a special position.  For example, if colon
+characters when they occur in a special position.  For example, if the colon
 (@code{:}) is generally permitted to be part of a symbol name, but the
-architecture specific code special-cases it when occuring as the final
+architecture specific code special-cases it when occurring as the final
 character of a symbol (to denote a label), then the macro parameter
 replacement code will have no way of knowing that and consider the whole
 construct (including the colon) an identifier, and check only this
-identifier for being the subject to parameter substitution.  In this
-example, besides the potential of just separating identifier and colon
-by white space, using alternate macro syntax (@xref{Altmacro}.) and
-ampersand (@code{&}) as the character to separate literal text from macro
-parameters (or macro parameters from one another) would provide a way to
-achieve the same effect:
+identifier for being the subject to parameter substitution.  So for example
+this macro definition:
+
+@example
+	.macro label l
+\l:
+	.endm
+@end example
+
+might not work as expected.  Invoking @samp{label foo} might not create a label
+called @samp{foo} but instead just insert the text @samp{\l:} into the
+assembler source, probably generating an error about an unrecognised
+identifier.
+
+Similarly problems might occur with the period character (@samp{.})
+which is often allowed inside opcode names (and hence identifier names).  So
+for example constructing a macro to build an opcode from a base name and a
+length specifier like this:
+
+@example
+	.macro opcode base length
+        \base.\length
+	.endm
+@end example
+
+and invoking it as @samp{opcode store l} will not create a @samp{store.l}
+instruction but instead generate some kind of error as the assembler tries to
+interpret the text @samp{\base.\length}.
+
+There are several possible ways around this problem:
+
+@table @code
+@item Insert white space
+If it is possible to use white space characters then this is the simplest
+solution.  eg:
+
+@example
+	.macro label l
+\l :
+	.endm
+@end example
+
+@item Use @samp{\()}
+The string @samp{\()} can be used to separate the end of a macro argument from
+the following text.  eg:
+
+@example
+	.macro opcode base length
+        \base\().\length
+	.endm
+@end example
+
+@item Use the alternate macro syntax mode
+In the alternative macro syntax mode the ampersand character (@samp{&}) can be
+used as a separator.  eg:
 
 @example
 	.altmacro
@@ -5027,9 +5165,11 @@ achieve the same effect:
 l&:
 	.endm
 @end example
+@end table
 
-This applies identically to the identifiers used in @code{.irp} (@xref{Irp}.)
-and @code{.irpc} (@xref{Irpc}.).
+Note: this problem of correctly identifying string parameters to pseudo ops
+also applies to the identifiers used in @code{.irp} (@pxref{Irp}) 
+and @code{.irpc} (@pxref{Irpc}) as well.
 
 @item .endm
 @cindex @code{endm} directive
@@ -5071,7 +5211,7 @@ You can write strings delimited in these other ways besides
 
 @table @code
 @item '@var{string}'
-You can delimit strings with single-quote charaters.
+You can delimit strings with single-quote characters.
 
 @item <@var{string}>
 You can delimit strings with matching angle brackets.
@@ -5090,7 +5230,7 @@ and use the result as a string.
 
 @node Noaltmacro
 @section @code{.noaltmacro}
-Disable alternate macro mode.  @ref{Altmacro}
+Disable alternate macro mode.  @xref{Altmacro}.
 
 @node Nolist
 @section @code{.nolist}
@@ -5314,6 +5454,20 @@ warning message; and just takes the lowest order 16 bytes of the bignum.
 @cindex integer, 16-byte
 @end ifset
 
+@node Reloc
+@section @code{.reloc @var{offset}, @var{reloc_name}[, @var{expression}]}
+
+@cindex @code{reloc} directive
+Generate a relocation at @var{offset} of type @var{reloc_name} with value
+@var{expression}.  If @var{offset} is a number, the relocation is generated in
+the current section.  If @var{offset} is an expression that resolves to a
+symbol plus offset, the relocation is generated in the given symbol's section.
+@var{expression}, if present, must resolve to a symbol plus addend or to an
+absolute value, but note that not all targets support an addend.  e.g. ELF REL
+targets such as i386 store an addend in the section contents rather than in the
+relocation.  This low level interface does not support addends stored in the
+section.
+
 @node Rept
 @section @code{.rept @var{count}}
 
@@ -5487,7 +5641,7 @@ ARM) then another character is used instead.  For example the ARM port uses the
 @code{%} character.
 
 If @var{flags} contains the @code{M} symbol then the @var{type} argument must
-be specified as well as an extra argument - @var{entsize} - like this:
+be specified as well as an extra argument---@var{entsize}---like this:
 
 @smallexample
 .section @var{name} , "@var{flags}"M, @@@var{type}, @var{entsize}
@@ -5516,7 +5670,7 @@ indicates that only one copy of this section should be retained
 an alias for comdat
 @end table
 
-Note - if both the @var{M} and @var{G} flags are present then the fields for
+Note: if both the @var{M} and @var{G} flags are present then the fields for
 the Merge flag should come first, like this:
 
 @smallexample
@@ -5589,7 +5743,7 @@ On Z80 @code{set} is a real instruction, use
 @xref{Word,,@code{.word}}.
 
 In some configurations, however, @code{.short} and @code{.word} generate
-numbers of different lengths; @pxref{Machine Dependencies}.
+numbers of different lengths.  @xref{Machine Dependencies}.
 @end ifset
 @ifclear GENERIC
 @ifset W16
@@ -5672,7 +5826,7 @@ symbols.
 @cindex @code{sleb128} directive
 @var{sleb128} stands for ``signed little endian base 128.''  This is a 
 compact, variable length representation of numbers used by the DWARF
-symbolic debugging format.  @xref{Uleb128,@code{.uleb128}}.
+symbolic debugging format.  @xref{Uleb128, ,@code{.uleb128}}.
 
 @ifclear no-space-dir
 @node Skip
@@ -5964,9 +6118,21 @@ For ELF targets, the @code{.type} directive is used like this:
 This sets the type of symbol @var{name} to be either a
 function symbol or an object symbol.  There are five different syntaxes
 supported for the @var{type description} field, in order to provide
-compatibility with various other assemblers.  The syntaxes supported are:
+compatibility with various other assemblers.
+
+Because some of the characters used in these syntaxes (such as @samp{@@} and
+@samp{#}) are comment characters for some architectures, some of the syntaxes
+below do not work on all architectures.  The first variant will be accepted by
+the GNU assembler on all architectures so that variant should be used for
+maximum portability, if you do not need to assemble your code with other
+assemblers.
+
+The syntaxes supported are:
 
 @smallexample
+  .type <name> STT_FUNCTION
+  .type <name> STT_OBJECT
+
   .type <name>,#function
   .type <name>,#object
 
@@ -5978,9 +6144,6 @@ compatibility with various other assemblers.  The syntaxes supported are:
   
   .type <name>,"function"
   .type <name>,"object"
-  
-  .type <name> STT_FUNCTION
-  .type <name> STT_OBJECT
 @end smallexample
 @end ifset
 @end ifset
@@ -5991,7 +6154,7 @@ compatibility with various other assemblers.  The syntaxes supported are:
 @cindex @code{uleb128} directive
 @var{uleb128} stands for ``unsigned little endian base 128.''  This is a 
 compact, variable length representation of numbers used by the DWARF
-symbolic debugging format.  @xref{Sleb128,@code{.sleb128}}.
+symbolic debugging format.  @xref{Sleb128, ,@code{.sleb128}}.
 
 @ifset COFF
 @node Val
@@ -6034,7 +6197,7 @@ This directive finds or creates a symbol @code{table} and creates a
 This directive finds the symbol @code{child} and finds or creates the symbol
 @code{parent} and then creates a @code{VTABLE_INHERIT} relocation for the
 parent whose addend is the value of the child symbol.  As a special case the
-parent name of @code{0} is treated as refering the @code{*ABS*} section.
+parent name of @code{0} is treated as referring to the @code{*ABS*} section.
 @end ifset
 
 @node Warning
@@ -6182,9 +6345,15 @@ subject, see the hardware manufacturer's manual.
 @ifset ARM
 * ARM-Dependent::               ARM Dependent Features
 @end ifset
+@ifset AVR
+* AVR-Dependent::               AVR Dependent Features
+@end ifset
 @ifset BFIN
 * BFIN-Dependent::		BFIN Dependent Features
 @end ifset
+@ifset CR16
+* CR16-Dependent::              CR16 Dependent Features
+@end ifset
 @ifset CRIS
 * CRIS-Dependent::              CRIS Dependent Features
 @end ifset
@@ -6298,10 +6467,18 @@ subject, see the hardware manufacturer's manual.
 @include c-arm.texi
 @end ifset
 
+@ifset AVR
+@include c-avr.texi
+@end ifset
+
 @ifset BFIN
 @include c-bfin.texi
 @end ifset
 
+@ifset CR16
+@include c-cr16.texi
+@end ifset
+
 @ifset CRIS
 @include c-cris.texi
 @end ifset
@@ -6508,8 +6685,10 @@ You can find contact information for many support companies and
 individuals in the file @file{etc/SERVICE} in the @sc{gnu} Emacs
 distribution.
 
+@ifset BUGURL
 In any event, we also recommend that you send bug reports for @command{@value{AS}}
-to @samp{bug-binutils@@gnu.org}.
+to @value{BUGURL}.
+@end ifset
 
 The fundamental principle of reporting bugs usefully is this:
 @strong{report all the facts}.  If you are not sure whether to state a
@@ -6583,7 +6762,7 @@ make a mistake.
 
 Even if the problem you experience is a fatal signal, you should still say so
 explicitly.  Suppose something strange is going on, such as, your copy of
-@command{@value{AS}} is out of synch, or you have encountered a bug in the C
+@command{@value{AS}} is out of sync, or you have encountered a bug in the C
 library on your system.  (This has happened!)  Your copy might crash and ours
 would not.  If you told us to expect a crash, then when ours fails to crash, we
 would know that the bug was not happening for us.  If you had not told us to
@@ -6736,7 +6915,7 @@ Timothy Wall, Michael Hayes, and Greg Smart contributed to the various tic*
 flavors.
 
 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from Tensilica,
-Inc. added support for Xtensa processors.
+Inc.@: added support for Xtensa processors.
 
 Several engineers at Cygnus Support have also provided many small bug fixes and
 configuration enhancements.
@@ -6748,12 +6927,11 @@ intentionally leaving anyone out.
 
 @include fdl.texi
 
-@node Index
-@unnumbered Index
+@node AS Index
+@unnumbered AS Index
 
 @printindex cp
 
-@contents
 @bye
 @c Local Variables:
 @c fill-column: 79
diff --git a/contrib/binutils/gas/doc/c-arc.texi b/contrib/binutils/gas/doc/c-arc.texi
index 04544d1..7f8ed6e 100644
--- a/contrib/binutils/gas/doc/c-arc.texi
+++ b/contrib/binutils/gas/doc/c-arc.texi
@@ -230,7 +230,7 @@ Determines the kinds of suffixes to be allowed.  Valid values are
 @code{SUFFIX_FLAG} which indicates the absence or presence of
 conditional suffixes and flag setting by the extension instruction.
 It is also possible to specify that an instruction sets the flags and
-is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
+is condtional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
 
 @item @var{syntaxclass}
 Determines the syntax class for the instruction.  It can have the
@@ -251,7 +251,7 @@ Syntax Class Modifiers are:
 
 @item @code{OP1_MUST_BE_IMM}:
 Modifies syntax class SYNTAX_3OP,  specifying that the first operand
-of a three-operand instruction must be an immediate (i.e. the result
+of a three-operand instruction must be an immediate (i.e., the result
 is discarded).  OP1_MUST_BE_IMM is used by bitwise ORing it with
 SYNTAX_3OP as given in the example below.  This could usually be used
 to set the flags using specific instructions and not retain results. 
diff --git a/contrib/binutils/gas/doc/c-arm.texi b/contrib/binutils/gas/doc/c-arm.texi
index ca0998b..8fc2972 100644
--- a/contrib/binutils/gas/doc/c-arm.texi
+++ b/contrib/binutils/gas/doc/c-arm.texi
@@ -155,9 +155,9 @@ names are recognized:
 @code{armv6z},
 @code{armv6zk},
 @code{armv7},
-@code{armv7a},
-@code{armv7r},
-@code{armv7m},
+@code{armv7-a},
+@code{armv7-r},
+@code{armv7-m},
 @code{iwmmxt}
 and
 @code{xscale}.
@@ -254,7 +254,7 @@ and
 @item -meabi=@var{ver}
 This option specifies which EABI version the produced object files should
 conform to.
-The following values are recognised:
+The following values are recognized:
 @code{gnu},
 @code{4}
 and
@@ -284,6 +284,7 @@ as position-independent code (PIC).
 @menu
 * ARM-Chars::                Special Characters
 * ARM-Regs::                 Register Names
+* ARM-Relocations::	     Relocations
 @end menu
 
 @node ARM-Chars
@@ -323,7 +324,46 @@ Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 @cindex ARM floating point (@sc{ieee})
 The ARM family uses @sc{ieee} floating-point numbers.
 
+@node ARM-Relocations
+@subsection ARM relocation generation
+
+@cindex data relocations, ARM
+@cindex ARM data relocations
+Specific data relocations can be generated by putting the relocation name
+in parentheses after the symbol name.  For example:
+
+@smallexample
+        .word foo(TARGET1)
+@end smallexample
+
+This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
+@var{foo}.
+The following relocations are supported:
+@code{GOT},
+@code{GOTOFF},
+@code{TARGET1},
+@code{TARGET2},
+@code{SBREL},
+@code{TLSGD},
+@code{TLSLDM},
+@code{TLSLDO},
+@code{GOTTPOFF}
+and
+@code{TPOFF}.
+
+For compatibility with older toolchains the assembler also accepts
+@code{(PLT)} after branch targets.  This will generate the deprecated
+@samp{R_ARM_PLT32} relocation.
 
+@cindex MOVW and MOVT relocations, ARM
+Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
+by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
+respectively.  For example to load the 32-bit address of foo into r0:
+
+@smallexample
+        MOVW r0, #:lower16:foo
+        MOVT r0, #:upper16:foo
+@end smallexample
 
 @node ARM Directives
 @section ARM Machine Directives
@@ -351,7 +391,7 @@ example:
 @cindex @code{unreq} directive, ARM
 @item .unreq @var{alias-name}
 This undefines a register alias which was previously defined using the
-@code{req} directive.  For example:
+@code{req}, @code{dn} or @code{qn} directives.  For example:
 
 @smallexample
         foo .req r0
@@ -362,6 +402,36 @@ An error occurs if the name is undefined.  Note - this pseudo op can
 be used to delete builtin in register name aliases (eg 'r0').  This
 should only be done if it is really necessary.
 
+@cindex @code{dn} and @code{qn} directives, ARM
+@item @var{name} .dn @var{register name} [@var{.type}] [@var{[index]}]
+@item @var{name} .qn @var{register name} [@var{.type}] [@var{[index]}]
+
+The @code{dn} and @code{qn} directives are used to create typed
+and/or indexed register aliases for use in Advanced SIMD Extension
+(Neon) instructions.  The former should be used to create aliases
+of double-precision registers, and the latter to create aliases of
+quad-precision registers.
+
+If these directives are used to create typed aliases, those aliases can
+be used in Neon instructions instead of writing types after the mnemonic
+or after each operand.  For example:
+
+@smallexample
+        x .dn d2.f32
+        y .dn d3.f32
+        z .dn d4.f32[1]
+        vmul x,y,z
+@end smallexample
+
+This is equivalent to writing the following:
+
+@smallexample
+        vmul.f32 d2,d3,d4[1]
+@end smallexample
+
+Aliases created using @code{dn} or @code{qn} can be destroyed using
+@code{unreq}.
+
 @cindex @code{code} directive, ARM
 @item .code @code{[16|32]}
 This directive selects the instruction set being generated. The value 16
@@ -389,6 +459,9 @@ between Arm and Thumb instructions and should be used even if
 interworking is not going to be performed.  The presence of this
 directive also implies @code{.thumb}
 
+This directive is not neccessary when generating EABI objects.  On these
+targets the encoding is implicit when generating Thumb code.
+
 @cindex @code{thumb_set} directive, ARM
 @item .thumb_set
 This performs the equivalent of a @code{.set} directive in that it
@@ -466,7 +539,7 @@ instruction.
   sfmfd f4, 2, [sp]!
 @exdent @emph{VFP registers}
   .save @{d8, d9, d10@}
-  fstmdf sp!, @{d8, d9, d10@}
+  fstmdx sp!, @{d8, d9, d10@}
 @exdent @emph{iWMMXt registers}
   .save @{wr10, wr11@}
   wstrd wr11, [sp, #-8]!
@@ -478,6 +551,26 @@ or
   wstrd wr10, [sp, #-8]!
 @end smallexample
 
+@cindex @code{.vsave} directive, ARM
+@item .vsave @var{vfp-reglist}
+Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
+using FLDMD.  Also works for VFPv3 registers
+that are to be restored using VLDM.
+The format of @var{vfp-reglist} is the same as the corresponding store-multiple
+instruction.
+
+@smallexample
+@exdent @emph{VFP registers}
+  .vsave @{d8, d9, d10@}
+  fstmdd sp!, @{d8, d9, d10@}
+@exdent @emph{VFPv3 registers}
+  .vsave @{d15, d16, d17@}
+  vstm sp!, @{d15, d16, d17@}
+@end smallexample
+
+Since FLDMX and FSTMX are now deprecated, this directive should be
+used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
+
 @cindex @code{.pad} directive, ARM
 @item .pad #@var{count}
 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
@@ -485,8 +578,10 @@ A positive value indicates the function prologue allocated stack space by
 decrementing the stack pointer.
 
 @cindex @code{.movsp} directive, ARM
-@item .movsp @var{reg}
-Tell the unwinder that @var{reg} contains the current stack pointer.
+@item .movsp @var{reg} [, #@var{offset}]
+Tell the unwinder that @var{reg} contains an offset from the current
+stack pointer.  If @var{offset} is not specified then it is assumed to be
+zero.
 
 @cindex @code{.setfp} directive, ARM
 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
@@ -523,6 +618,12 @@ for the @option{-mcpu} commandline option.
 Select the target architecture.  Valid values for @var{name} are the same as
 for the @option{-march} commandline option.
 
+@cindex @code{.object_arch} directive, ARM
+@item .object_arch @var{name}
+Override the architecture recorded in the EABI object attribute section.
+Valid values for @var{name} are the same as for the @code{.arch} directive.
+Typically this is useful when code uses runtime detection of CPU features.
+
 @cindex @code{.fpu} directive, ARM
 @item .fpu @var{name}
 Select the floating point unit to assemble for.  Valid values for @var{name}
diff --git a/contrib/binutils/gas/doc/c-avr.texi b/contrib/binutils/gas/doc/c-avr.texi
new file mode 100644
index 0000000..9bf743d
--- /dev/null
+++ b/contrib/binutils/gas/doc/c-avr.texi
@@ -0,0 +1,364 @@
+@c Copyright 2006
+@c Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node AVR-Dependent
+@chapter AVR Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter AVR Dependent Features
+@end ifclear
+
+@cindex AVR support
+@menu
+* AVR Options::              Options
+* AVR Syntax::               Syntax
+* AVR Opcodes::              Opcodes
+@end menu
+
+@node AVR Options
+@section Options
+@cindex AVR options (none)
+@cindex options for AVR (none)
+
+@table @code
+
+@cindex @code{-mmcu=} command line option, AVR
+@item -mmcu=@var{mcu}
+Specify ATMEL AVR instruction set or MCU type.
+
+Instruction set avr1 is for the minimal AVR core, not supported by the C
+compiler, only for assembler programs (MCU types: at90s1200, attiny10,
+attiny11, attiny12, attiny15, attiny28).
+
+Instruction set avr2 (default) is for the classic AVR core with up to
+8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
+attiny26, at90s2333, at90s2343, at90s4414, at90s4433, at90s4434,
+at90s8515, at90c8534, at90s8535, at86rf401, attiny13, attiny2313,
+attiny261, attiny461, attiny861, attiny24, attiny44, attiny84, attiny25,
+attiny45, attiny85).
+
+Instruction set avr3 is for the classic AVR core with up to 128K program
+memory space (MCU types: atmega103, atmega603, at43usb320, at43usb355,
+at76c711).
+
+Instruction set avr4 is for the enhanced AVR core with up to 8K program
+memory space (MCU types: atmega48, atmega8, atmega83, atmega85, atmega88,
+atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm3).
+
+Instruction set avr5 is for the enhanced AVR core with up to 128K program
+memory space (MCU types: atmega16, atmega161, atmega162, atmega163,
+atmega164p, atmega165, atmega165p, atmega168, atmega169, atmega169p, 
+atmega32, atmega323, atmega324p, atmega325, atmega325p, atmega329, 
+atmega329p, atmega3250, atmega3250p, atmega3290, atmega3290p, atmega406, 
+atmega64, atmega640, atmega644, atmega644p, atmega128, atmega1280, 
+atmega1281, atmega645, atmega649, atmega6450, atmega6490, atmega16hva, 
+at90can32, at90can64, at90can128, at90usb82, at90usb162, at90usb646, 
+at90usb647, at90usb1286, at90usb1287, at94k).
+
+Instruction set avr6 is for the enhanced AVR core with 256K program
+memory space (MCU types: atmega2560, atmega2561).
+
+@cindex @code{-mall-opcodes} command line option, AVR
+@item -mall-opcodes
+Accept all AVR opcodes, even if not supported by @code{-mmcu}.
+
+@cindex @code{-mno-skip-bug} command line option, AVR
+@item -mno-skip-bug
+This option disable warnings for skipping two-word instructions.
+
+@cindex @code{-mno-wrap} command line option, AVR
+@item -mno-wrap
+This option reject @code{rjmp/rcall} instructions with 8K wrap-around.
+
+@end table
+
+
+@node AVR Syntax
+@section Syntax
+@menu
+* AVR-Chars::                Special Characters
+* AVR-Regs::                 Register Names
+* AVR-Modifiers::            Relocatable Expression Modifiers
+@end menu
+
+@node AVR-Chars
+@subsection Special Characters
+
+@cindex line comment character, AVR
+@cindex AVR line comment character
+
+The presence of a @samp{;} on a line indicates the start of a comment
+that extends to the end of the current line.  If a @samp{#} appears as
+the first character of a line, the whole line is treated as a comment.
+
+@cindex line separator, AVR
+@cindex statement separator, AVR
+@cindex AVR line separator
+
+The @samp{$} character can be used instead of a newline to separate
+statements.
+
+@node AVR-Regs
+@subsection Register Names
+
+@cindex AVR register names
+@cindex register names, AVR
+
+The AVR has 32 x 8-bit general purpose working registers @samp{r0},
+@samp{r1}, ... @samp{r31}.
+Six of the 32 registers can be used as three 16-bit indirect address
+register pointers for Data Space addressing. One of the these address
+pointers can also be used as an address pointer for look up tables in
+Flash program memory. These added function registers are the 16-bit
+@samp{X}, @samp{Y} and @samp{Z} - registers.
+
+@smallexample
+X = @r{r26:r27}
+Y = @r{r28:r29}
+Z = @r{r30:r31}
+@end smallexample
+
+@node AVR-Modifiers
+@subsection Relocatable Expression Modifiers
+
+@cindex AVR modifiers
+@cindex syntax, AVR
+
+The assembler supports several modifiers when using relocatable addresses
+in AVR instruction operands.  The general syntax is the following:
+
+@smallexample
+modifier(relocatable-expression)
+@end smallexample
+
+@table @code
+@cindex symbol modifiers
+
+@item lo8
+
+This modifier allows you to use bits 0 through 7 of
+an address expression as 8 bit relocatable expression.
+
+@item hi8
+
+This modifier allows you to use bits 7 through 15 of an address expression
+as 8 bit relocatable expression.  This is useful with, for example, the
+AVR @samp{ldi} instruction and @samp{lo8} modifier.
+
+For example
+
+@smallexample
+ldi r26, lo8(sym+10)
+ldi r27, hi8(sym+10)
+@end smallexample
+
+@item hh8
+
+This modifier allows you to use bits 16 through 23 of
+an address expression as 8 bit relocatable expression.
+Also, can be useful for loading 32 bit constants.
+
+@item hlo8
+
+Synonym of @samp{hh8}.
+
+@item hhi8
+
+This modifier allows you to use bits 24 through 31 of
+an expression as 8 bit expression. This is useful with, for example, the
+AVR @samp{ldi} instruction and @samp{lo8}, @samp{hi8}, @samp{hlo8},
+@samp{hhi8}, modifier.
+
+For example
+
+@smallexample
+ldi r26, lo8(285774925)
+ldi r27, hi8(285774925)
+ldi r28, hlo8(285774925)
+ldi r29, hhi8(285774925)
+; r29,r28,r27,r26 = 285774925
+@end smallexample
+
+@item pm_lo8
+
+This modifier allows you to use bits 0 through 7 of
+an address expression as 8 bit relocatable expression.
+This modifier useful for addressing data or code from
+Flash/Program memory. The using of @samp{pm_lo8} similar
+to @samp{lo8}.
+
+@item pm_hi8
+
+This modifier allows you to use bits 8 through 15 of
+an address expression as 8 bit relocatable expression.
+This modifier useful for addressing data or code from
+Flash/Program memory.
+
+@item pm_hh8
+
+This modifier allows you to use bits 15 through 23 of
+an address expression as 8 bit relocatable expression.
+This modifier useful for addressing data or code from
+Flash/Program memory.
+
+@end table
+
+@node AVR Opcodes
+@section Opcodes
+
+@cindex AVR opcode summary
+@cindex opcode summary, AVR
+@cindex mnemonics, AVR
+@cindex instruction summary, AVR
+For detailed information on the AVR machine instruction set, see
+@url{www.atmel.com/products/AVR}.
+
+@code{@value{AS}} implements all the standard AVR opcodes.
+The following table summarizes the AVR opcodes, and their arguments.
+
+@smallexample
+@i{Legend:}
+   r   @r{any register}
+   d   @r{`ldi' register (r16-r31)}
+   v   @r{`movw' even register (r0, r2, ..., r28, r30)}
+   a   @r{`fmul' register (r16-r23)}
+   w   @r{`adiw' register (r24,r26,r28,r30)}
+   e   @r{pointer registers (X,Y,Z)}
+   b   @r{base pointer register and displacement ([YZ]+disp)}
+   z   @r{Z pointer register (for [e]lpm Rd,Z[+])}
+   M   @r{immediate value from 0 to 255}
+   n   @r{immediate value from 0 to 255 ( n = ~M ). Relocation impossible}
+   s   @r{immediate value from 0 to 7}
+   P   @r{Port address value from 0 to 63. (in, out)}
+   p   @r{Port address value from 0 to 31. (cbi, sbi, sbic, sbis)}
+   K   @r{immediate value from 0 to 63 (used in `adiw', `sbiw')}
+   i   @r{immediate value}
+   l   @r{signed pc relative offset from -64 to 63}
+   L   @r{signed pc relative offset from -2048 to 2047}
+   h   @r{absolute code address (call, jmp)}
+   S   @r{immediate value from 0 to 7 (S = s << 4)}
+   ?   @r{use this opcode entry if no parameters, else use next opcode entry}
+
+1001010010001000   clc  
+1001010011011000   clh  
+1001010011111000   cli  
+1001010010101000   cln  
+1001010011001000   cls  
+1001010011101000   clt  
+1001010010111000   clv  
+1001010010011000   clz  
+1001010000001000   sec  
+1001010001011000   seh  
+1001010001111000   sei  
+1001010000101000   sen  
+1001010001001000   ses  
+1001010001101000   set  
+1001010000111000   sev  
+1001010000011000   sez  
+100101001SSS1000   bclr    S
+100101000SSS1000   bset    S
+1001010100001001   icall
+1001010000001001   ijmp 
+1001010111001000   lpm     ?
+1001000ddddd010+   lpm     r,z
+1001010111011000   elpm    ?
+1001000ddddd011+   elpm    r,z
+0000000000000000   nop  
+1001010100001000   ret  
+1001010100011000   reti 
+1001010110001000   sleep
+1001010110011000   break
+1001010110101000   wdr  
+1001010111101000   spm  
+000111rdddddrrrr   adc     r,r
+000011rdddddrrrr   add     r,r
+001000rdddddrrrr   and     r,r
+000101rdddddrrrr   cp      r,r
+000001rdddddrrrr   cpc     r,r
+000100rdddddrrrr   cpse    r,r
+001001rdddddrrrr   eor     r,r
+001011rdddddrrrr   mov     r,r
+100111rdddddrrrr   mul     r,r
+001010rdddddrrrr   or      r,r
+000010rdddddrrrr   sbc     r,r
+000110rdddddrrrr   sub     r,r
+001001rdddddrrrr   clr     r
+000011rdddddrrrr   lsl     r
+000111rdddddrrrr   rol     r
+001000rdddddrrrr   tst     r
+0111KKKKddddKKKK   andi    d,M
+0111KKKKddddKKKK   cbr     d,n
+1110KKKKddddKKKK   ldi     d,M
+11101111dddd1111   ser     d
+0110KKKKddddKKKK   ori     d,M
+0110KKKKddddKKKK   sbr     d,M
+0011KKKKddddKKKK   cpi     d,M
+0100KKKKddddKKKK   sbci    d,M
+0101KKKKddddKKKK   subi    d,M
+1111110rrrrr0sss   sbrc    r,s
+1111111rrrrr0sss   sbrs    r,s
+1111100ddddd0sss   bld     r,s
+1111101ddddd0sss   bst     r,s
+10110PPdddddPPPP   in      r,P
+10111PPrrrrrPPPP   out     P,r
+10010110KKddKKKK   adiw    w,K
+10010111KKddKKKK   sbiw    w,K
+10011000pppppsss   cbi     p,s
+10011010pppppsss   sbi     p,s
+10011001pppppsss   sbic    p,s
+10011011pppppsss   sbis    p,s
+111101lllllll000   brcc    l
+111100lllllll000   brcs    l
+111100lllllll001   breq    l
+111101lllllll100   brge    l
+111101lllllll101   brhc    l
+111100lllllll101   brhs    l
+111101lllllll111   brid    l
+111100lllllll111   brie    l
+111100lllllll000   brlo    l
+111100lllllll100   brlt    l
+111100lllllll010   brmi    l
+111101lllllll001   brne    l
+111101lllllll010   brpl    l
+111101lllllll000   brsh    l
+111101lllllll110   brtc    l
+111100lllllll110   brts    l
+111101lllllll011   brvc    l
+111100lllllll011   brvs    l
+111101lllllllsss   brbc    s,l
+111100lllllllsss   brbs    s,l
+1101LLLLLLLLLLLL   rcall   L
+1100LLLLLLLLLLLL   rjmp    L
+1001010hhhhh111h   call    h
+1001010hhhhh110h   jmp     h
+1001010rrrrr0101   asr     r
+1001010rrrrr0000   com     r
+1001010rrrrr1010   dec     r
+1001010rrrrr0011   inc     r
+1001010rrrrr0110   lsr     r
+1001010rrrrr0001   neg     r
+1001000rrrrr1111   pop     r
+1001001rrrrr1111   push    r
+1001010rrrrr0111   ror     r
+1001010rrrrr0010   swap    r
+00000001ddddrrrr   movw    v,v
+00000010ddddrrrr   muls    d,d
+000000110ddd0rrr   mulsu   a,a
+000000110ddd1rrr   fmul    a,a
+000000111ddd0rrr   fmuls   a,a
+000000111ddd1rrr   fmulsu  a,a
+1001001ddddd0000   sts     i,r
+1001000ddddd0000   lds     r,i
+10o0oo0dddddbooo   ldd     r,b
+100!000dddddee-+   ld      r,e
+10o0oo1rrrrrbooo   std     b,r
+100!001rrrrree-+   st      e,r
+1001010100011001   eicall  
+1001010000011001   eijmp   
+@end smallexample
diff --git a/contrib/binutils/gas/doc/c-cr16.texi b/contrib/binutils/gas/doc/c-cr16.texi
new file mode 100644
index 0000000..4748d56
--- /dev/null
+++ b/contrib/binutils/gas/doc/c-cr16.texi
@@ -0,0 +1,80 @@
+@c Copyright 2007 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node CR16-Dependent
+@chapter CR16 Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter CR16 Dependent Features
+@end ifclear
+
+@cindex CR16 support
+@menu
+* CR16 Operand Qualifiers::     CR16 Machine Operand Qualifiers
+@end menu
+
+@node CR16 Operand Qualifiers
+@section CR16 Operand Qualifiers
+@cindex CR16 Operand Qualifiers
+
+The National Semiconductor CR16 target of @code{@value{AS}} has a few machine dependent operand qualifiers.  
+
+Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The @code{@@} is required. CR16 architecture uses one of the following expression qualifiers:
+
+@table @code
+@item  s 
+- @code{Specifies expression operand type as small}
+@item  m 
+- @code{Specifies expression operand type as medium}
+@item  l 
+- @code{Specifies expression operand type as large}
+@item  c 
+- @code{Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.}
+@end table
+
+CR16 target operand qualifiers and its size (in bits):
+
+@table @samp
+@item Immediate Operand
+- s ---- 4 bits
+@item 
+- m ---- 16 bits, for movb and movw instructions.
+@item 
+- m ---- 20 bits, movd instructions.
+@item 
+- l ---- 32 bits
+
+@item Absolute Operand
+- s ---- Illegal specifier for this operand.
+@item  
+- m ---- 20 bits, movd instructions.
+
+@item Displacement Operand
+- s ---- 8 bits
+@item
+- m ---- 16 bits
+@item 
+- l ---- 24 bits
+@end table
+
+For example:
+@example
+1   @code{movw $_myfun@@c,r1}
+
+    This loads the address of _myfun, shifted right by 1, into r1.
+
+2   @code{movd $_myfun@@c,(r2,r1)}
+
+    This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
+                
+3   @code{_myfun_ptr:}
+    @code{.long _myfun@@c}
+    @code{loadd _myfun_ptr, (r1,r0)}
+    @code{jal (r1,r0)}
+
+    This .long directive, the address of _myfunc, shifted right by 1 at link time.
+@end example
diff --git a/contrib/binutils/gas/doc/c-i386.texi b/contrib/binutils/gas/doc/c-i386.texi
index 81039c4..48b251a 100644
--- a/contrib/binutils/gas/doc/c-i386.texi
+++ b/contrib/binutils/gas/doc/c-i386.texi
@@ -76,6 +76,49 @@ character, which means that it cannot be used in expressions.  The
 not disable @samp{/} at the beginning of a line starting a comment, or
 affect using @samp{#} for starting a comment.
 
+@cindex @samp{-march=} option, i386
+@cindex @samp{-march=} option, x86-64
+@item -march=@var{CPU}
+This option specifies an instruction set architecture for generating
+instructions.  The following architectures are recognized:
+@code{i8086},
+@code{i186},
+@code{i286},
+@code{i386},
+@code{i486},
+@code{i586},
+@code{i686},
+@code{pentium},
+@code{pentiumpro},
+@code{pentiumii},
+@code{pentiumiii},
+@code{pentium4},
+@code{prescott},
+@code{nocona},
+@code{core},
+@code{core2},
+@code{k6},
+@code{k6_2},
+@code{athlon},
+@code{sledgehammer},
+@code{opteron},
+@code{k8},
+@code{generic32} and
+@code{generic64}.
+
+This option only affects instructions generated by the assembler. The
+@code{.arch} directive will take precedent.
+
+@cindex @samp{-mtune=} option, i386
+@cindex @samp{-mtune=} option, x86-64
+@item -mtune=@var{CPU}
+This option specifies a processor to optimize for. When used in
+conjunction with the @option{-march} option, only instructions
+of the processor specified by the @option{-march} option will be
+generated.
+
+Valid @var{CPU} values are identical to @option{-march=@var{CPU}}.
+
 @end table
 
 @node i386-Syntax
@@ -604,7 +647,7 @@ then stores the result in the 4 byte location @samp{mem})
 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
 instructions for integer data), available on Intel's Pentium MMX
 processors and Pentium II processors, AMD's K6 and K6-2 processors,
-Cyrix' M2 processor, and probably others.  It also supports AMD's 3DNow!
+Cyrix' M2 processor, and probably others.  It also supports AMD's 3DNow!@:
 instruction set (SIMD instructions for 32-bit floating point data)
 available on AMD's K6-2 processor and possibly others in the future.
 
@@ -667,7 +710,7 @@ value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
 @end smallexample
 
 The same code in a 16-bit code section would generate the machine
-opcode bytes @samp{6a 04} (ie. without the operand size prefix), which
+opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
 is correct since the processor default operand size is assumed to be 16
 bits in a 16-bit code section.
 
@@ -709,8 +752,13 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
-@item @samp{k6} @tab @samp{athlon} @samp{sledgehammer}
-@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.sse3} @samp{.3dnow}
+@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
+@item @samp{amdfam10}
+@item @samp{k6} @tab @samp{athlon} @tab @samp{sledgehammer} @tab @samp{k8} 
+@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
+@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
+@item @samp{.sse4a} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.padlock}
+@item @samp{.pacifica} @tab @samp{.svme} @tab @samp{.abm}
 @end multitable
 
 Apart from the warning, there are only two other effects on
diff --git a/contrib/binutils/gas/doc/c-mips.texi b/contrib/binutils/gas/doc/c-mips.texi
index 3c70ff2..f92cb00 100644
--- a/contrib/binutils/gas/doc/c-mips.texi
+++ b/contrib/binutils/gas/doc/c-mips.texi
@@ -60,6 +60,18 @@ little-endian output at run time (unlike the other @sc{gnu} development
 tools, which must be configured for one or the other).  Use @samp{-EB}
 to select big-endian output, and @samp{-EL} for little-endian.
 
+@item -KPIC
+@cindex PIC selection, MIPS
+@cindex @option{-KPIC} option, MIPS
+Generate SVR4-style PIC.  This option tells the assembler to generate
+SVR4-style position-independent macro expansions.  It also tells the
+assembler to mark the output file as PIC.
+
+@item -mvxworks-pic
+@cindex @option{-mvxworks-pic} option, MIPS
+Generate VxWorks PIC.  This option tells the assembler to generate
+VxWorks-style position-independent macro expansions.
+
 @cindex MIPS architecture options
 @item -mips1
 @itemx -mips2
@@ -91,21 +103,38 @@ flags force a certain group of registers to be treated as 32 bits wide at
 all times.  @samp{-mgp32} controls the size of general-purpose registers
 and @samp{-mfp32} controls the size of floating-point registers.
 
+The @code{.set gp=32} and @code{.set fp=32} directives allow the size
+of registers to be changed for parts of an object. The default value is
+restored by @code{.set gp=default} and @code{.set fp=default}.
+
 On some MIPS variants there is a 32-bit mode flag; when this flag is
 set, 64-bit instructions generate a trap.  Also, some 32-bit OSes only
 save the 32-bit registers on a context switch, so it is essential never
 to use the 64-bit registers.
 
 @item -mgp64
-Assume that 64-bit general purpose registers are available.  This is
-provided in the interests of symmetry with -gp32.
+@itemx -mfp64
+Assume that 64-bit registers are available.  This is provided in the
+interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
+
+The @code{.set gp=64} and @code{.set fp=64} directives allow the size
+of registers to be changed for parts of an object. The default value is
+restored by @code{.set gp=default} and @code{.set fp=default}.
 
 @item -mips16
 @itemx -no-mips16
 Generate code for the MIPS 16 processor.  This is equivalent to putting
-@samp{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
+@code{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
 turns off this option.
 
+@item -msmartmips
+@itemx -mno-smartmips
+Enables the SmartMIPS extensions to the MIPS32 instruction set, which
+provides a number of new instructions which target smartcard and
+cryptographic applications.  This is equivalent to putting
+@code{.set smartmips} at the start of the assembly file.
+@samp{-mno-smartmips} turns off this option.
+
 @item -mips3d
 @itemx -no-mips3d
 Generate code for the MIPS-3D Application Specific Extension.
@@ -120,10 +149,17 @@ This tells the assembler to accept MDMX instructions.
 
 @item -mdsp
 @itemx -mno-dsp
-Generate code for the DSP Application Specific Extension.
-This tells the assembler to accept DSP instructions.
+Generate code for the DSP Release 1 Application Specific Extension.
+This tells the assembler to accept DSP Release 1 instructions.
 @samp{-mno-dsp} turns off this option.
 
+@item -mdspr2
+@itemx -mno-dspr2
+Generate code for the DSP Release 2 Application Specific Extension.
+This option implies -mdsp.
+This tells the assembler to accept DSP Release 2 instructions.
+@samp{-mno-dspr2} turns off this option.
+
 @item -mmt
 @itemx -mno-mt
 Generate code for the MT Application Specific Extension.
@@ -202,8 +238,34 @@ rm7000,
 rm9000,
 10000,
 12000,
-mips32-4k,
-sb1
+4kc,
+4km,
+4kp,
+4ksc,
+4kec,
+4kem,
+4kep,
+4ksd,
+m4k,
+m4kp,
+24kc,
+24kf,
+24kx,
+24kec,
+24kef,
+24kex,
+34kc,
+34kf,
+34kx,
+74kc,
+74kf,
+74kx,
+5kc,
+5kf,
+20kc,
+25kf,
+sb1,
+sb1a
 @end quotation
 
 @item -mtune=@var{cpu}
@@ -391,13 +453,21 @@ assembly.  @code{.set mips@var{n}} affects not only which instructions
 are permitted, but also how certain macros are expanded.  @code{.set
 mips0} restores the @sc{isa} level to its original level: either the
 level you selected with command line options, or the default for your
-configuration.  You can use this feature to permit specific @sc{r4000}
+configuration.  You can use this feature to permit specific @sc{mips3}
 instructions while assembling in 32 bit mode.  Use this directive with
 care!
 
-The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
+@cindex MIPS CPU override
+@kindex @code{.set arch=@var{cpu}}
+The @code{.set arch=@var{cpu}} directive provides even finer control.
+It changes the effective CPU target and allows the assembler to use
+instructions specific to a particular CPU.  All CPUs supported by the
+@samp{-march} command line option are also selectable by this directive.
+The original value is restored by @code{.set arch=default}.
+
+The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
 in which it will assemble instructions for the MIPS 16 processor.  Use
-@samp{.set nomips16} to return to normal 32 bit mode.
+@code{.set nomips16} to return to normal 32 bit mode.
 
 Traditional @sc{mips} assemblers do not support this directive.
 
@@ -407,10 +477,10 @@ Traditional @sc{mips} assemblers do not support this directive.
 @kindex @code{.set autoextend}
 @kindex @code{.set noautoextend}
 By default, MIPS 16 instructions are automatically extended to 32 bits
-when necessary.  The directive @samp{.set noautoextend} will turn this
-off.  When @samp{.set noautoextend} is in effect, any 32 bit instruction
-must be explicitly extended with the @samp{.e} modifier (e.g.,
-@samp{li.e $4,1000}).  The directive @samp{.set autoextend} may be used
+when necessary.  The directive @code{.set noautoextend} will turn this
+off.  When @code{.set noautoextend} is in effect, any 32 bit instruction
+must be explicitly extended with the @code{.e} modifier (e.g.,
+@code{li.e $4,1000}).  The directive @code{.set autoextend} may be used
 to once again automatically extend instructions when necessary.
 
 This directive is only meaningful when in MIPS 16 mode.  Traditional
@@ -455,6 +525,15 @@ from the MIPS-3D Application Specific Extension from that point on
 in the assembly.  The @code{.set nomips3d} directive prevents MIPS-3D
 instructions from being accepted.
 
+@cindex SmartMIPS instruction generation override
+@kindex @code{.set smartmips}
+@kindex @code{.set nosmartmips}
+The directive @code{.set smartmips} makes the assembler accept
+instructions from the SmartMIPS Application Specific Extension to the
+MIPS32 @sc{isa} from that point on in the assembly.  The
+@code{.set nosmartmips} directive prevents SmartMIPS instructions from
+being accepted.
+
 @cindex MIPS MDMX instruction generation override
 @kindex @code{.set mdmx}
 @kindex @code{.set nomdmx}
@@ -463,13 +542,22 @@ from the MDMX Application Specific Extension from that point on
 in the assembly.  The @code{.set nomdmx} directive prevents MDMX
 instructions from being accepted.
 
-@cindex MIPS DSP instruction generation override
+@cindex MIPS DSP Release 1 instruction generation override
 @kindex @code{.set dsp}
 @kindex @code{.set nodsp}
 The directive @code{.set dsp} makes the assembler accept instructions
-from the DSP Application Specific Extension from that point on
-in the assembly.  The @code{.set nodsp} directive prevents DSP
-instructions from being accepted.
+from the DSP Release 1 Application Specific Extension from that point
+on in the assembly.  The @code{.set nodsp} directive prevents DSP
+Release 1 instructions from being accepted.
+
+@cindex MIPS DSP Release 2 instruction generation override
+@kindex @code{.set dspr2}
+@kindex @code{.set nodspr2}
+The directive @code{.set dspr2} makes the assembler accept instructions
+from the DSP Release 2 Application Specific Extension from that point
+on in the assembly.  This dirctive implies @code{.set dsp}.  The
+@code{.set nodspr2} directive prevents DSP Release 2 instructions from
+being accepted.
 
 @cindex MIPS MT instruction generation override
 @kindex @code{.set mt}
diff --git a/contrib/binutils/gas/doc/c-ppc.texi b/contrib/binutils/gas/doc/c-ppc.texi
index 4c9c096..a41e1dd 100644
--- a/contrib/binutils/gas/doc/c-ppc.texi
+++ b/contrib/binutils/gas/doc/c-ppc.texi
@@ -1,4 +1,4 @@
-@c Copyright 2001, 2002, 2003, 2005
+@c Copyright 2001, 2002, 2003, 2005, 2006
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -58,6 +58,12 @@ Generate code for PowerPC 7400/7410/7450/7455.
 @item -mppc64, -m620
 Generate code for PowerPC 620/625/630.
 
+@item -me500, -me500x2
+Generate code for Motorola e500 core complex.
+
+@item -mspe
+Generate code for Motorola SPE instructions.
+
 @item -mppc64bridge
 Generate code for PowerPC 64, including bridge insns.
 
@@ -79,6 +85,12 @@ Generate code for Power4 architecture.
 @item -mpower5
 Generate code for Power5 architecture.
 
+@item -mpower6
+Generate code for Power6 architecture.
+
+@item -mcell
+Generate code for Cell Broadband Engine architecture.
+
 @item -mcom
 Generate code Power/PowerPC common instructions.
 
@@ -92,10 +104,10 @@ Allow symbolic names for registers.
 Do not allow symbolic names for registers.
 
 @item -mrelocatable
-Support for GCC's -mrelocatble option.
+Support for GCC's -mrelocatable option.
 
 @item -mrelocatable-lib
-Support for GCC's -mrelocatble-lib option.
+Support for GCC's -mrelocatable-lib option.
 
 @item -memb
 Set PPC_EMB bit in ELF flags.
diff --git a/contrib/binutils/gas/doc/gasver.texi b/contrib/binutils/gas/doc/gasver.texi
deleted file mode 100644
index 11d1801..0000000
--- a/contrib/binutils/gas/doc/gasver.texi
+++ /dev/null
@@ -1 +0,0 @@
-@set VERSION 2.17
diff --git a/contrib/binutils/gas/doc/internals.texi b/contrib/binutils/gas/doc/internals.texi
index dffdb1e..c63a2db 100644
--- a/contrib/binutils/gas/doc/internals.texi
+++ b/contrib/binutils/gas/doc/internals.texi
@@ -1,6 +1,6 @@
 \input texinfo
 @c  Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-@c  2001, 2002, 2003, 2004, 2005
+@c  2001, 2002, 2003, 2004, 2005, 2006
 @c  Free Software Foundation, Inc.
 @setfilename internals.info
 @node Top
@@ -838,7 +838,7 @@ GAS will call @code{md_parse_option} whenever @code{getopt} returns an
 unrecognized code, presumably indicating a special code value which appears in
 @code{md_longopts}.  This function should return non-zero if it handled the
 option and zero otherwise.  There is no need to print a message about an option
-not being recognised.  This will be handled by the generic code.
+not being recognized.  This will be handled by the generic code.
 
 GAS will call @code{md_show_usage} when a usage message is printed; it should
 print a description of the machine specific options. @code{md_after_pase_args},
@@ -891,7 +891,7 @@ If this macro is defined, GAS will use it instead of @code{comment_chars}.
 @cindex tc_symbol_chars
 If this macro is defined, it is a pointer to a null terminated list of
 characters which may appear in an operand.  GAS already assumes that all
-alphanumberic characters, and @samp{$}, @samp{.}, and @samp{_} may appear in an
+alphanumeric characters, and @samp{$}, @samp{.}, and @samp{_} may appear in an
 operand (see @samp{symbol_chars} in @file{app.c}).  This macro may be defined
 to treat additional characters as appearing in an operand.  This affects the
 way in which GAS removes whitespace before passing the string to
@@ -1279,7 +1279,7 @@ absolute symbol.  If undefined, @code{TC_FORCE_RELOCATION} will be used.
 @cindex TC_FORCE_RELOCATION_LOCAL
 Like @code{TC_FORCE_RELOCATION}, but used only for fixup expressions against a
 symbol in the current section.  If undefined, fixups that are not
-@code{fx_pcrel} or @code{fx_plt} or for which @code{TC_FORCE_RELOCATION}
+@code{fx_pcrel} or for which @code{TC_FORCE_RELOCATION}
 returns non-zero, will emit relocs.
 
 @item TC_FORCE_RELOCATION_SUB_SAME (@var{fix}, @var{seg})
@@ -1609,7 +1609,7 @@ symbol's flags.
 
 @item obj_clear_weak_hook
 @cindex obj_clear_weak_hook
-If you define this macro, @code{S_CLEAR_WEAKREFD} will call it after clearning
+If you define this macro, @code{S_CLEAR_WEAKREFD} will call it after cleaning
 the @code{weakrefd} flag, but before modifying any other flags.
 
 @item obj_frob_file
@@ -1844,10 +1844,6 @@ Returns non-zero if any warnings or errors, respectively, have been printed
 during this invocation.
 @end deftypefun
 
-@deftypefun @{@} void as_perror (const char *@var{gripe}, const char *@var{filename})
-Displays a BFD or system error, then clears the error status.
-@end deftypefun
-
 @deftypefun  @{@} void as_tsktsk (const char *@var{format}, ...)
 @deftypefunx @{@} void as_warn (const char *@var{format}, ...)
 @deftypefunx @{@} void as_bad (const char *@var{format}, ...)
diff --git a/contrib/binutils/gas/dw2gencfi.c b/contrib/binutils/gas/dw2gencfi.c
index bfa5d5c..97e1237 100644
--- a/contrib/binutils/gas/dw2gencfi.c
+++ b/contrib/binutils/gas/dw2gencfi.c
@@ -21,6 +21,7 @@
 
 #include "as.h"
 #include "dw2gencfi.h"
+#include "subsegs.h"
 
 
 /* We re-use DWARF2_LINE_MIN_INSN_LENGTH for the code alignment field
@@ -87,6 +88,10 @@ struct fde_entry
   symbolS *end_address;
   struct cfi_insn_data *data;
   struct cfi_insn_data **last;
+  unsigned char per_encoding;
+  unsigned char lsda_encoding;
+  expressionS personality;
+  expressionS lsda;
   unsigned int return_column;
   unsigned int signal_frame;
 };
@@ -97,15 +102,13 @@ struct cie_entry
   symbolS *start_address;
   unsigned int return_column;
   unsigned int signal_frame;
+  unsigned char per_encoding;
+  unsigned char lsda_encoding;
+  expressionS personality;
   struct cfi_insn_data *first, *last;
 };
 
 
-/* Current open FDE entry.  */
-static struct fde_entry *cur_fde_data;
-static symbolS *last_address;
-static offsetT cur_cfa_offset;
-
 /* List of FDE entries.  */
 static struct fde_entry *all_fde_data;
 static struct fde_entry **last_fde_data = &all_fde_data;
@@ -120,7 +123,14 @@ struct cfa_save_data
   offsetT cfa_offset;
 };
 
-static struct cfa_save_data *cfa_save_stack;
+/* Current open FDE entry.  */
+struct frch_cfi_data
+{
+  struct fde_entry *cur_fde_data;
+  symbolS *last_address;
+  offsetT cur_cfa_offset;
+  struct cfa_save_data *cfa_save_stack;
+};
 
 /* Construct a new FDE structure and add it to the end of the fde list.  */
 
@@ -129,12 +139,15 @@ alloc_fde_entry (void)
 {
   struct fde_entry *fde = xcalloc (1, sizeof (struct fde_entry));
 
-  cur_fde_data = fde;
+  frchain_now->frch_cfi_data = xcalloc (1, sizeof (struct frch_cfi_data));
+  frchain_now->frch_cfi_data->cur_fde_data = fde;
   *last_fde_data = fde;
   last_fde_data = &fde->next;
 
   fde->last = &fde->data;
   fde->return_column = DWARF2_DEFAULT_RETURN_COLUMN;
+  fde->per_encoding = DW_EH_PE_omit;
+  fde->lsda_encoding = DW_EH_PE_omit;
 
   return fde;
 }
@@ -149,6 +162,7 @@ static struct cfi_insn_data *
 alloc_cfi_insn_data (void)
 {
   struct cfi_insn_data *insn = xcalloc (1, sizeof (struct cfi_insn_data));
+  struct fde_entry *cur_fde_data = frchain_now->frch_cfi_data->cur_fde_data;
 
   *cur_fde_data->last = insn;
   cur_fde_data->last = &insn->next;
@@ -163,7 +177,7 @@ cfi_new_fde (symbolS *label)
 {
   struct fde_entry *fde = alloc_fde_entry ();
   fde->start_address = label;
-  last_address = label;
+  frchain_now->frch_cfi_data->last_address = label;
 }
 
 /* End the currently open FDE.  */
@@ -171,8 +185,9 @@ cfi_new_fde (symbolS *label)
 void 
 cfi_end_fde (symbolS *label)
 {
-  cur_fde_data->end_address = label;
-  cur_fde_data = NULL;
+  frchain_now->frch_cfi_data->cur_fde_data->end_address = label;
+  free (frchain_now->frch_cfi_data);
+  frchain_now->frch_cfi_data = NULL;
 }
 
 /* Set the return column for the current FDE.  */
@@ -180,7 +195,7 @@ cfi_end_fde (symbolS *label)
 void
 cfi_set_return_column (unsigned regno)
 {
-  cur_fde_data->return_column = regno;
+  frchain_now->frch_cfi_data->cur_fde_data->return_column = regno;
 }
 
 /* Universal functions to store new instructions.  */
@@ -239,10 +254,10 @@ cfi_add_advance_loc (symbolS *label)
   struct cfi_insn_data *insn = alloc_cfi_insn_data ();
 
   insn->insn = DW_CFA_advance_loc;
-  insn->u.ll.lab1 = last_address;
+  insn->u.ll.lab1 = frchain_now->frch_cfi_data->last_address;
   insn->u.ll.lab2 = label;
 
-  last_address = label;
+  frchain_now->frch_cfi_data->last_address = label;
 }
 
 /* Add a DW_CFA_offset record to the CFI data.  */
@@ -252,6 +267,7 @@ cfi_add_CFA_offset (unsigned regno, offsetT offset)
 {
   unsigned int abs_data_align;
 
+  assert (DWARF2_CIE_DATA_ALIGNMENT != 0);
   cfi_add_CFA_insn_reg_offset (DW_CFA_offset, regno, offset);
 
   abs_data_align = (DWARF2_CIE_DATA_ALIGNMENT < 0
@@ -266,7 +282,7 @@ void
 cfi_add_CFA_def_cfa (unsigned regno, offsetT offset)
 {
   cfi_add_CFA_insn_reg_offset (DW_CFA_def_cfa, regno, offset);
-  cur_cfa_offset = offset;
+  frchain_now->frch_cfi_data->cur_cfa_offset = offset;
 }
 
 /* Add a DW_CFA_register record to the CFI data.  */
@@ -291,7 +307,7 @@ void
 cfi_add_CFA_def_cfa_offset (offsetT offset)
 {
   cfi_add_CFA_insn_offset (DW_CFA_def_cfa_offset, offset);
-  cur_cfa_offset = offset;
+  frchain_now->frch_cfi_data->cur_cfa_offset = offset;
 }
 
 void
@@ -320,9 +336,9 @@ cfi_add_CFA_remember_state (void)
   cfi_add_CFA_insn (DW_CFA_remember_state);
 
   p = xmalloc (sizeof (*p));
-  p->cfa_offset = cur_cfa_offset;
-  p->next = cfa_save_stack;
-  cfa_save_stack = p;
+  p->cfa_offset = frchain_now->frch_cfi_data->cur_cfa_offset;
+  p->next = frchain_now->frch_cfi_data->cfa_save_stack;
+  frchain_now->frch_cfi_data->cfa_save_stack = p;
 }
 
 void
@@ -332,11 +348,11 @@ cfi_add_CFA_restore_state (void)
 
   cfi_add_CFA_insn (DW_CFA_restore_state);
 
-  p = cfa_save_stack;
+  p = frchain_now->frch_cfi_data->cfa_save_stack;
   if (p)
     {
-      cur_cfa_offset = p->cfa_offset;
-      cfa_save_stack = p->next;
+      frchain_now->frch_cfi_data->cur_cfa_offset = p->cfa_offset;
+      frchain_now->frch_cfi_data->cfa_save_stack = p->next;
       free (p);
     }
   else
@@ -350,6 +366,8 @@ static void dot_cfi (int);
 static void dot_cfi_escape (int);
 static void dot_cfi_startproc (int);
 static void dot_cfi_endproc (int);
+static void dot_cfi_personality (int);
+static void dot_cfi_lsda (int);
 
 /* Fake CFI type; outside the byte range of any real CFI insn.  */
 #define CFI_adjust_cfa_offset	0x100
@@ -378,6 +396,8 @@ const pseudo_typeS cfi_pseudo_table[] =
     { "cfi_window_save", dot_cfi, DW_CFA_GNU_window_save },
     { "cfi_escape", dot_cfi_escape, 0 },
     { "cfi_signal_frame", dot_cfi, CFI_signal_frame },
+    { "cfi_personality", dot_cfi_personality, 0 },
+    { "cfi_lsda", dot_cfi_lsda, 0 },
     { NULL, NULL, 0 }
   };
 
@@ -448,7 +468,7 @@ dot_cfi (int arg)
   offsetT offset;
   unsigned reg1, reg2;
 
-  if (!cur_fde_data)
+  if (frchain_now->frch_cfi_data == NULL)
     {
       as_bad (_("CFI instruction used without previous .cfi_startproc"));
       ignore_rest_of_line ();
@@ -456,8 +476,9 @@ dot_cfi (int arg)
     }
 
   /* If the last address was not at the current PC, advance to current.  */
-  if (symbol_get_frag (last_address) != frag_now
-      || S_GET_VALUE (last_address) != frag_now_fix ())
+  if (symbol_get_frag (frchain_now->frch_cfi_data->last_address) != frag_now
+      || S_GET_VALUE (frchain_now->frch_cfi_data->last_address)
+	 != frag_now_fix ())
     cfi_add_advance_loc (symbol_temp_new_now ());
 
   switch (arg)
@@ -473,7 +494,8 @@ dot_cfi (int arg)
       reg1 = cfi_parse_reg ();
       cfi_parse_separator ();
       offset = cfi_parse_const ();
-      cfi_add_CFA_offset (reg1, offset - cur_cfa_offset);
+      cfi_add_CFA_offset (reg1,
+			  offset - frchain_now->frch_cfi_data->cur_cfa_offset);
       break;
 
     case DW_CFA_def_cfa:
@@ -502,7 +524,8 @@ dot_cfi (int arg)
 
     case CFI_adjust_cfa_offset:
       offset = cfi_parse_const ();
-      cfi_add_CFA_def_cfa_offset (cur_cfa_offset + offset);
+      cfi_add_CFA_def_cfa_offset (frchain_now->frch_cfi_data->cur_cfa_offset
+				  + offset);
       break;
 
     case DW_CFA_restore:
@@ -552,7 +575,7 @@ dot_cfi (int arg)
       break;
 
     case CFI_signal_frame:
-      cur_fde_data->signal_frame = 1;
+      frchain_now->frch_cfi_data->cur_fde_data->signal_frame = 1;
       break;
 
     default:
@@ -568,7 +591,7 @@ dot_cfi_escape (int ignored ATTRIBUTE_UNUSED)
   struct cfi_escape_data *head, **tail, *e;
   struct cfi_insn_data *insn;
 
-  if (!cur_fde_data)
+  if (frchain_now->frch_cfi_data == NULL)
     {
       as_bad (_("CFI instruction used without previous .cfi_startproc"));
       ignore_rest_of_line ();
@@ -576,8 +599,9 @@ dot_cfi_escape (int ignored ATTRIBUTE_UNUSED)
     }
 
   /* If the last address was not at the current PC, advance to current.  */
-  if (symbol_get_frag (last_address) != frag_now
-      || S_GET_VALUE (last_address) != frag_now_fix ())
+  if (symbol_get_frag (frchain_now->frch_cfi_data->last_address) != frag_now
+      || S_GET_VALUE (frchain_now->frch_cfi_data->last_address)
+	 != frag_now_fix ())
     cfi_add_advance_loc (symbol_temp_new_now ());
 
   tail = &head;
@@ -600,11 +624,153 @@ dot_cfi_escape (int ignored ATTRIBUTE_UNUSED)
 }
 
 static void
+dot_cfi_personality (int ignored ATTRIBUTE_UNUSED)
+{
+  struct fde_entry *fde;
+  offsetT encoding;
+
+  if (frchain_now->frch_cfi_data == NULL)
+    {
+      as_bad (_("CFI instruction used without previous .cfi_startproc"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  fde = frchain_now->frch_cfi_data->cur_fde_data;
+  encoding = get_absolute_expression ();
+  if (encoding == DW_EH_PE_omit)
+    {
+      demand_empty_rest_of_line ();
+      fde->per_encoding = encoding;
+      return;
+    }
+
+  if ((encoding & 0xff) != encoding
+      || ((encoding & 0x70) != 0
+#if defined DIFF_EXPR_OK || defined tc_cfi_emit_pcrel_expr
+	  && (encoding & 0x70) != DW_EH_PE_pcrel
+#endif
+	  )
+	 /* leb128 can be handled, but does something actually need it?  */
+      || (encoding & 7) == DW_EH_PE_uleb128
+      || (encoding & 7) > DW_EH_PE_udata8)
+    {
+      as_bad (_("invalid or unsupported encoding in .cfi_personality"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  if (*input_line_pointer++ != ',')
+    {
+      as_bad (_(".cfi_personality requires encoding and symbol arguments"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  expression_and_evaluate (&fde->personality);
+  switch (fde->personality.X_op)
+    {
+    case O_symbol:
+      break;
+    case O_constant:
+      if ((encoding & 0x70) == DW_EH_PE_pcrel)
+	encoding = DW_EH_PE_omit;
+      break;
+    default:
+      encoding = DW_EH_PE_omit;
+      break;
+    }
+
+  fde->per_encoding = encoding;
+
+  if (encoding == DW_EH_PE_omit)
+    {
+      as_bad (_("wrong second argument to .cfi_personality"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  demand_empty_rest_of_line ();
+}
+
+static void
+dot_cfi_lsda (int ignored ATTRIBUTE_UNUSED)
+{
+  struct fde_entry *fde;
+  offsetT encoding;
+
+  if (frchain_now->frch_cfi_data == NULL)
+    {
+      as_bad (_("CFI instruction used without previous .cfi_startproc"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  fde = frchain_now->frch_cfi_data->cur_fde_data;
+  encoding = get_absolute_expression ();
+  if (encoding == DW_EH_PE_omit)
+    {
+      demand_empty_rest_of_line ();
+      fde->lsda_encoding = encoding;
+      return;
+    }
+
+  if ((encoding & 0xff) != encoding
+      || ((encoding & 0x70) != 0
+#if defined DIFF_EXPR_OK || defined tc_cfi_emit_pcrel_expr
+	  && (encoding & 0x70) != DW_EH_PE_pcrel
+#endif
+	  )
+	 /* leb128 can be handled, but does something actually need it?  */
+      || (encoding & 7) == DW_EH_PE_uleb128
+      || (encoding & 7) > DW_EH_PE_udata8)
+    {
+      as_bad (_("invalid or unsupported encoding in .cfi_lsda"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  if (*input_line_pointer++ != ',')
+    {
+      as_bad (_(".cfi_lsda requires encoding and symbol arguments"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  fde->lsda_encoding = encoding;
+
+  expression_and_evaluate (&fde->lsda);
+  switch (fde->lsda.X_op)
+    {
+    case O_symbol:
+      break;
+    case O_constant:
+      if ((encoding & 0x70) == DW_EH_PE_pcrel)
+	encoding = DW_EH_PE_omit;
+      break;
+    default:
+      encoding = DW_EH_PE_omit;
+      break;
+    }
+
+  fde->lsda_encoding = encoding;
+
+  if (encoding == DW_EH_PE_omit)
+    {
+      as_bad (_("wrong second argument to .cfi_lsda"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  demand_empty_rest_of_line ();
+}
+
+static void
 dot_cfi_startproc (int ignored ATTRIBUTE_UNUSED)
 {
   int simple = 0;
 
-  if (cur_fde_data)
+  if (frchain_now->frch_cfi_data != NULL)
     {
       as_bad (_("previous CFI entry not closed (missing .cfi_endproc)"));
       ignore_rest_of_line ();
@@ -631,7 +797,7 @@ dot_cfi_startproc (int ignored ATTRIBUTE_UNUSED)
     }
   demand_empty_rest_of_line ();
 
-  cur_cfa_offset = 0;
+  frchain_now->frch_cfi_data->cur_cfa_offset = 0;
   if (!simple)
     tc_cfi_frame_initial_instructions ();
 }
@@ -639,7 +805,7 @@ dot_cfi_startproc (int ignored ATTRIBUTE_UNUSED)
 static void
 dot_cfi_endproc (int ignored ATTRIBUTE_UNUSED)
 {
-  if (! cur_fde_data)
+  if (frchain_now->frch_cfi_data == NULL)
     {
       as_bad (_(".cfi_endproc without corresponding .cfi_startproc"));
       ignore_rest_of_line ();
@@ -714,18 +880,18 @@ output_cfi_insn (struct cfi_insn_data *insn)
 	      out_one (DW_CFA_advance_loc + scaled);
 	    else if (delta <= 0xFF)
 	      {
-	        out_one (DW_CFA_advance_loc1);
-	        out_one (delta);
+		out_one (DW_CFA_advance_loc1);
+		out_one (delta);
 	      }
 	    else if (delta <= 0xFFFF)
 	      {
-	        out_one (DW_CFA_advance_loc2);
-	        out_two (delta);
+		out_one (DW_CFA_advance_loc2);
+		out_two (delta);
 	      }
 	    else
 	      {
-	        out_one (DW_CFA_advance_loc4);
-	        out_four (delta);
+		out_one (DW_CFA_advance_loc4);
+		out_four (delta);
 	      }
 	  }
 	else
@@ -850,12 +1016,33 @@ output_cfi_insn (struct cfi_insn_data *insn)
     }
 }
 
+static offsetT
+encoding_size (unsigned char encoding)
+{
+  if (encoding == DW_EH_PE_omit)
+    return 0;
+  switch (encoding & 0x7)
+    {
+    case 0:
+      return bfd_get_arch_size (stdoutput) == 64 ? 8 : 4;
+    case DW_EH_PE_udata2:
+      return 2;
+    case DW_EH_PE_udata4:
+      return 4;
+    case DW_EH_PE_udata8:
+      return 8;
+    default:
+      abort ();
+    }
+}
+
 static void
 output_cie (struct cie_entry *cie)
 {
   symbolS *after_size_address, *end_address;
   expressionS exp;
   struct cfi_insn_data *i;
+  offsetT augmentation_size;
 
   cie->start_address = symbol_temp_new_now ();
   after_size_address = symbol_temp_make ();
@@ -871,6 +1058,10 @@ output_cie (struct cie_entry *cie)
   out_four (0);					/* CIE id.  */
   out_one (DW_CIE_VERSION);			/* Version.  */
   out_one ('z');				/* Augmentation.  */
+  if (cie->per_encoding != DW_EH_PE_omit)
+    out_one ('P');
+  if (cie->lsda_encoding != DW_EH_PE_omit)
+    out_one ('L');
   out_one ('R');
   if (cie->signal_frame)
     out_one ('S');
@@ -881,7 +1072,32 @@ output_cie (struct cie_entry *cie)
     out_one (cie->return_column);
   else
     out_uleb128 (cie->return_column);
-  out_uleb128 (1);				/* Augmentation size.  */
+  augmentation_size = 1 + (cie->lsda_encoding != DW_EH_PE_omit);
+  if (cie->per_encoding != DW_EH_PE_omit)
+    augmentation_size += 1 + encoding_size (cie->per_encoding);
+  out_uleb128 (augmentation_size);		/* Augmentation size.  */
+  if (cie->per_encoding != DW_EH_PE_omit)
+    {
+      offsetT size = encoding_size (cie->per_encoding);
+      out_one (cie->per_encoding);
+      exp = cie->personality;
+      if ((cie->per_encoding & 0x70) == DW_EH_PE_pcrel)
+	{
+#ifdef DIFF_EXPR_OK
+	  exp.X_op = O_subtract;
+	  exp.X_op_symbol = symbol_temp_new_now ();
+	  emit_expr (&exp, size);
+#elif defined (tc_cfi_emit_pcrel_expr)
+	  tc_cfi_emit_pcrel_expr (&exp, size);
+#else
+	  abort ();
+#endif
+	}
+      else
+	emit_expr (&exp, size);
+    }
+  if (cie->lsda_encoding != DW_EH_PE_omit)
+    out_one (cie->lsda_encoding);
 #if defined DIFF_EXPR_OK || defined tc_cfi_emit_pcrel_expr
   out_one (DW_EH_PE_pcrel | DW_EH_PE_sdata4);
 #else
@@ -902,6 +1118,7 @@ output_fde (struct fde_entry *fde, struct cie_entry *cie,
 {
   symbolS *after_size_address, *end_address;
   expressionS exp;
+  offsetT augmentation_size;
 
   after_size_address = symbol_temp_make ();
   end_address = symbol_temp_make ();
@@ -917,7 +1134,7 @@ output_fde (struct fde_entry *fde, struct cie_entry *cie,
   exp.X_op_symbol = cie->start_address;
   emit_expr (&exp, 4);				/* CIE offset.  */
 
-#ifdef DIFF_EXPR_OK  
+#ifdef DIFF_EXPR_OK
   exp.X_add_symbol = fde->start_address;
   exp.X_op_symbol = symbol_temp_new_now ();
   emit_expr (&exp, 4);				/* Code offset.  */
@@ -937,7 +1154,27 @@ output_fde (struct fde_entry *fde, struct cie_entry *cie,
   exp.X_op_symbol = fde->start_address;		/* Code length.  */
   emit_expr (&exp, 4);
 
-  out_uleb128 (0);				/* Augmentation size.  */
+  augmentation_size = encoding_size (fde->lsda_encoding);
+  out_uleb128 (augmentation_size);		/* Augmentation size.  */
+
+  if (fde->lsda_encoding != DW_EH_PE_omit)
+    {
+      exp = fde->lsda;
+      if ((fde->lsda_encoding & 0x70) == DW_EH_PE_pcrel)
+	{
+#ifdef DIFF_EXPR_OK
+	  exp.X_op = O_subtract;
+	  exp.X_op_symbol = symbol_temp_new_now ();
+	  emit_expr (&exp, augmentation_size);
+#elif defined (tc_cfi_emit_pcrel_expr)
+	  tc_cfi_emit_pcrel_expr (&exp, augmentation_size);
+#else
+	  abort ();
+#endif
+	}
+      else
+	emit_expr (&exp, augmentation_size);
+    }
 
   for (; first; first = first->next)
     output_cfi_insn (first);
@@ -955,8 +1192,31 @@ select_cie_for_fde (struct fde_entry *fde, struct cfi_insn_data **pfirst)
   for (cie = cie_root; cie; cie = cie->next)
     {
       if (cie->return_column != fde->return_column
-	  || cie->signal_frame != fde->signal_frame)
+	  || cie->signal_frame != fde->signal_frame
+	  || cie->per_encoding != fde->per_encoding
+	  || cie->lsda_encoding != fde->lsda_encoding)
 	continue;
+      if (cie->per_encoding != DW_EH_PE_omit)
+	{
+	  if (cie->personality.X_op != fde->personality.X_op
+	      || cie->personality.X_add_number
+		 != fde->personality.X_add_number)
+	    continue;
+	  switch (cie->personality.X_op)
+	    {
+	    case O_constant:
+	      if (cie->personality.X_unsigned != fde->personality.X_unsigned)
+		continue;
+	      break;
+	    case O_symbol:
+	      if (cie->personality.X_add_symbol
+		  != fde->personality.X_add_symbol)
+		continue;
+	      break;
+	    default:
+	      abort ();
+	    }
+	}
       for (i = cie->first, j = fde->data;
 	   i != cie->last && j != NULL;
 	   i = i->next, j = j->next)
@@ -1029,6 +1289,9 @@ select_cie_for_fde (struct fde_entry *fde, struct cfi_insn_data **pfirst)
   cie_root = cie;
   cie->return_column = fde->return_column;
   cie->signal_frame = fde->signal_frame;
+  cie->per_encoding = fde->per_encoding;
+  cie->lsda_encoding = fde->lsda_encoding;
+  cie->personality = fde->personality;
   cie->first = fde->data;
 
   for (i = cie->first; i ; i = i->next)
@@ -1052,12 +1315,6 @@ cfi_finish (void)
   struct fde_entry *fde;
   int save_flag_traditional_format;
 
-  if (cur_fde_data)
-    {
-      as_bad (_("open CFI at the end of file; missing .cfi_endproc directive"));
-      cur_fde_data->end_address = cur_fde_data->start_address;
-    }
-
   if (all_fde_data == 0)
     return;
 
@@ -1077,6 +1334,12 @@ cfi_finish (void)
       struct cfi_insn_data *first;
       struct cie_entry *cie;
 
+      if (fde->end_address == NULL)
+	{
+	  as_bad (_("open CFI at the end of file; missing .cfi_endproc directive"));
+	  fde->end_address = fde->start_address;
+	}
+
       cie = select_cie_for_fde (fde, &first);
       output_fde (fde, cie, first, fde->next == NULL ? EH_FRAME_ALIGNMENT : 2);
     }
diff --git a/contrib/binutils/gas/dwarf2dbg.c b/contrib/binutils/gas/dwarf2dbg.c
index 16666fa..671a9b0 100644
--- a/contrib/binutils/gas/dwarf2dbg.c
+++ b/contrib/binutils/gas/dwarf2dbg.c
@@ -28,7 +28,6 @@
 	      [epilogue_begin] [is_stmt VALUE] [isa VALUE]
 */
 
-#include "ansidecl.h"
 #include "as.h"
 #include "safe-ctype.h"
 
@@ -46,6 +45,29 @@
 #include "dwarf2dbg.h"
 #include <filenames.h>
 
+#ifdef HAVE_DOS_BASED_FILE_SYSTEM
+/* We need to decide which character to use as a directory separator.
+   Just because HAVE_DOS_BASED_FILE_SYSTEM is defined, it does not
+   necessarily mean that the backslash character is the one to use.
+   Some environments, eg Cygwin, can support both naming conventions.
+   So we use the heuristic that we only need to use the backslash if
+   the path is an absolute path starting with a DOS style drive
+   selector.  eg C: or D:  */
+# define INSERT_DIR_SEPARATOR(string, offset) \
+  do \
+    { \
+      if (offset > 1 \
+          && string[0] != 0 \
+          && string[1] == ':') \
+       string [offset] = '\\'; \
+      else \
+       string [offset] = '/'; \
+    } \
+  while (0)
+#else
+# define INSERT_DIR_SEPARATOR(string, offset) string[offset] = '/'
+#endif
+
 #ifndef DWARF2_FORMAT
 # define DWARF2_FORMAT() dwarf2_format_32bit
 #endif
@@ -66,6 +88,13 @@
 #define DL_FILES	1
 #define DL_BODY		2
 
+/* If linker relaxation might change offsets in the code, the DWARF special
+   opcodes and variable-length operands cannot be used.  If this macro is
+   nonzero, use the DW_LNS_fixed_advance_pc opcode instead.  */
+#ifndef DWARF2_USE_FIXED_ADVANCE_PC
+# define DWARF2_USE_FIXED_ADVANCE_PC	0
+#endif
+
 /* First special line opcde - leave room for the standard opcodes.
    Note: If you want to change this, you'll have to update the
    "standard_opcode_lengths" table that is emitted below in
@@ -169,22 +198,22 @@ static void out_two (int);
 static void out_four (int);
 static void out_abbrev (int, int);
 static void out_uleb128 (addressT);
-static offsetT get_frag_fix (fragS *);
+static void out_sleb128 (addressT);
+static offsetT get_frag_fix (fragS *, segT);
 static void out_set_addr (symbolS *);
 static int size_inc_line_addr (int, addressT);
 static void emit_inc_line_addr (int, addressT, char *, int);
 static void out_inc_line_addr (int, addressT);
+static void out_fixed_inc_line_addr (int, symbolS *, symbolS *);
 static void relax_inc_line_addr (int, symbolS *, symbolS *);
 static void process_entries (segT, struct line_entry *);
 static void out_file_list (void);
 static void out_debug_line (segT);
 static void out_debug_aranges (segT, segT);
 static void out_debug_abbrev (segT);
-static void out_debug_info (segT, segT, segT);
 
 #ifndef TC_DWARF2_EMIT_OFFSET
-# define TC_DWARF2_EMIT_OFFSET  generic_dwarf2_emit_offset
-static void generic_dwarf2_emit_offset (symbolS *, unsigned int);
+#define TC_DWARF2_EMIT_OFFSET  generic_dwarf2_emit_offset
 
 /* Create an offset to .dwarf2_*.  */
 
@@ -569,7 +598,7 @@ dwarf2_directive_loc (int dummy ATTRIBUTE_UNUSED)
 	  char *cp = (char *) alloca (dir_len + 1 + file_len + 1);
 
 	  memcpy (cp, dirs[files[filenum].dir], dir_len);
-	  cp[dir_len] = '/';
+	  INSERT_DIR_SEPARATOR (cp, dir_len);
 	  memcpy (cp + dir_len + 1, files[filenum].filename, file_len);
 	  cp[dir_len + file_len + 1] = '\0';
 	  listing_source_file (cp);
@@ -670,27 +699,18 @@ dwarf2_directive_loc_mark_labels (int dummy ATTRIBUTE_UNUSED)
 static struct frag *
 first_frag_for_seg (segT seg)
 {
-  frchainS *f, *first = NULL;
-
-  for (f = frchain_root; f; f = f->frch_next)
-    if (f->frch_seg == seg
-	&& (! first || first->frch_subseg > f->frch_subseg))
-      first = f;
-
-  return first ? first->frch_root : NULL;
+  return seg_info (seg)->frchainP->frch_root;
 }
 
 static struct frag *
 last_frag_for_seg (segT seg)
 {
-  frchainS *f, *last = NULL;
+  frchainS *f = seg_info (seg)->frchainP;
 
-  for (f = frchain_root; f; f = f->frch_next)
-    if (f->frch_seg == seg
-	&& (! last || last->frch_subseg < f->frch_subseg))
-      last= f;
+  while (f->frch_next != NULL)
+    f = f->frch_next;
 
-  return last ? last->frch_last : NULL;
+  return f->frch_last;
 }
 
 /* Emit a single byte into the current segment.  */
@@ -733,6 +753,14 @@ out_uleb128 (addressT value)
   output_leb128 (frag_more (sizeof_leb128 (value, 0)), value, 0);
 }
 
+/* Emit a signed "little-endian base 128" number.  */
+
+static void
+out_sleb128 (addressT value)
+{
+  output_leb128 (frag_more (sizeof_leb128 (value, 1)), value, 1);
+}
+
 /* Emit a tuple for .debug_abbrev.  */
 
 static inline void
@@ -745,7 +773,7 @@ out_abbrev (int name, int form)
 /* Get the size of a fragment.  */
 
 static offsetT
-get_frag_fix (fragS *frag)
+get_frag_fix (fragS *frag, segT seg)
 {
   frchainS *fr;
 
@@ -755,7 +783,7 @@ get_frag_fix (fragS *frag)
   /* If a fragment is the last in the chain, special measures must be
      taken to find its size before relaxation, since it may be pending
      on some subsegment chain.  */
-  for (fr = frchain_root; fr; fr = fr->frch_next)
+  for (fr = seg_info (seg)->frchainP; fr; fr = fr->frch_next)
     if (fr->frch_last == frag)
       return (char *) obstack_next_free (&fr->frch_obstack) - frag->fr_literal;
 
@@ -966,6 +994,45 @@ out_inc_line_addr (int line_delta, addressT addr_delta)
   emit_inc_line_addr (line_delta, addr_delta, frag_more (len), len);
 }
 
+/* Write out an alternative form of line and address skips using
+   DW_LNS_fixed_advance_pc opcodes.  This uses more space than the default
+   line and address information, but it helps support linker relaxation that
+   changes the code offsets.  */
+
+static void
+out_fixed_inc_line_addr (int line_delta, symbolS *to_sym, symbolS *from_sym)
+{
+  expressionS expr;
+
+  /* INT_MAX is a signal that this is actually a DW_LNE_end_sequence.  */
+  if (line_delta == INT_MAX)
+    {
+      out_opcode (DW_LNS_fixed_advance_pc);
+      expr.X_op = O_subtract;
+      expr.X_add_symbol = to_sym;
+      expr.X_op_symbol = from_sym;
+      expr.X_add_number = 0;
+      emit_expr (&expr, 2);
+
+      out_opcode (DW_LNS_extended_op);
+      out_byte (1);
+      out_opcode (DW_LNE_end_sequence);
+      return;
+    }
+
+  out_opcode (DW_LNS_advance_line);
+  out_sleb128 (line_delta);
+
+  out_opcode (DW_LNS_fixed_advance_pc);
+  expr.X_op = O_subtract;
+  expr.X_add_symbol = to_sym;
+  expr.X_op_symbol = from_sym;
+  expr.X_add_number = 0;
+  emit_expr (&expr, 2);
+
+  out_opcode (DW_LNS_copy);
+}
+
 /* Generate a variant frag that we can use to relax address/line
    increments between fragments of the target segment.  */
 
@@ -1116,6 +1183,8 @@ process_entries (segT seg, struct line_entry *e)
 	  out_set_addr (lab);
 	  out_inc_line_addr (line_delta, 0);
 	}
+      else if (DWARF2_USE_FIXED_ADVANCE_PC)
+	out_fixed_inc_line_addr (line_delta, lab, last_lab);
       else if (frag == last_frag)
 	out_inc_line_addr (line_delta, frag_ofs - last_frag_ofs);
       else
@@ -1134,8 +1203,13 @@ process_entries (segT seg, struct line_entry *e)
 
   /* Emit a DW_LNE_end_sequence for the end of the section.  */
   frag = last_frag_for_seg (seg);
-  frag_ofs = get_frag_fix (frag);
-  if (frag == last_frag)
+  frag_ofs = get_frag_fix (frag, seg);
+  if (DWARF2_USE_FIXED_ADVANCE_PC)
+    {
+      lab = symbol_temp_new (seg, frag_ofs, frag);
+      out_fixed_inc_line_addr (INT_MAX, lab, last_lab);
+    }
+  else if (frag == last_frag)
     out_inc_line_addr (INT_MAX, frag_ofs - last_frag_ofs);
   else
     {
@@ -1277,6 +1351,54 @@ out_debug_line (segT line_seg)
   symbol_set_value_now (line_end);
 }
 
+static void
+out_debug_ranges (segT ranges_seg)
+{
+  unsigned int addr_size = sizeof_address;
+  struct line_seg *s;
+  expressionS expr;
+  unsigned int i;
+
+  subseg_set (ranges_seg, 0);
+
+  /* Base Address Entry.  */
+  for (i = 0; i < addr_size; i++) 
+    out_byte (0xff);
+  for (i = 0; i < addr_size; i++) 
+    out_byte (0);
+
+  /* Range List Entry.  */
+  for (s = all_segs; s; s = s->next)
+    {
+      fragS *frag;
+      symbolS *beg, *end;
+
+      frag = first_frag_for_seg (s->seg);
+      beg = symbol_temp_new (s->seg, 0, frag);
+      s->text_start = beg;
+
+      frag = last_frag_for_seg (s->seg);
+      end = symbol_temp_new (s->seg, get_frag_fix (frag, s->seg), frag);
+      s->text_end = end;
+
+      expr.X_op = O_symbol;
+      expr.X_add_symbol = beg;
+      expr.X_add_number = 0;
+      emit_expr (&expr, addr_size);
+
+      expr.X_op = O_symbol;
+      expr.X_add_symbol = end;
+      expr.X_add_number = 0;
+      emit_expr (&expr, addr_size);
+    }
+
+  /* End of Range Entry.   */
+  for (i = 0; i < addr_size; i++) 
+    out_byte (0);
+  for (i = 0; i < addr_size; i++) 
+    out_byte (0);
+}
+
 /* Emit data for .debug_aranges.  */
 
 static void
@@ -1332,7 +1454,7 @@ out_debug_aranges (segT aranges_seg, segT info_seg)
       s->text_start = beg;
 
       frag = last_frag_for_seg (s->seg);
-      end = symbol_temp_new (s->seg, get_frag_fix (frag), frag);
+      end = symbol_temp_new (s->seg, get_frag_fix (frag, s->seg), frag);
       s->text_end = end;
 
       expr.X_op = O_symbol;
@@ -1369,6 +1491,13 @@ out_debug_abbrev (segT abbrev_seg)
       out_abbrev (DW_AT_low_pc, DW_FORM_addr);
       out_abbrev (DW_AT_high_pc, DW_FORM_addr);
     }
+  else
+    {
+      if (DWARF2_FORMAT () == dwarf2_format_32bit)
+	out_abbrev (DW_AT_ranges, DW_FORM_data4);
+      else
+	out_abbrev (DW_AT_ranges, DW_FORM_data8);
+    }
   out_abbrev (DW_AT_name, DW_FORM_string);
   out_abbrev (DW_AT_comp_dir, DW_FORM_string);
   out_abbrev (DW_AT_producer, DW_FORM_string);
@@ -1382,7 +1511,7 @@ out_debug_abbrev (segT abbrev_seg)
 /* Emit a description of this compilation unit for .debug_info.  */
 
 static void
-out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg)
+out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg, segT ranges_seg)
 {
   char producer[128];
   char *comp_dir;
@@ -1445,8 +1574,7 @@ out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg)
   /* ??? sizeof_offset */
   TC_DWARF2_EMIT_OFFSET (section_symbol (line_seg), 4);
 
-  /* These two attributes may only be emitted if all of the code is
-     contiguous.  Multiple sections are not that.  */
+  /* These two attributes are emitted if all of the code is contiguous.  */
   if (all_segs->next == NULL)
     {
       /* DW_AT_low_pc */
@@ -1461,6 +1589,12 @@ out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg)
       expr.X_add_number = 0;
       emit_expr (&expr, sizeof_address);
     }
+  else
+    {
+      /* This attribute is emitted if the code is disjoint.  */
+      /* DW_AT_ranges.  */
+      TC_DWARF2_EMIT_OFFSET (section_symbol (ranges_seg), sizeof_offset);
+    }
 
   /* DW_AT_name.  We don't have the actual file name that was present
      on the command line, so assume files[1] is the main input file.
@@ -1473,7 +1607,7 @@ out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg)
       len = strlen (dirs[files[1].dir]);
       p = frag_more (len + 1);
       memcpy (p, dirs[files[1].dir], len);
-      p[len] = '/';
+      INSERT_DIR_SEPARATOR (p, len);
     }
   len = strlen (files[1].filename) + 1;
   p = frag_more (len);
@@ -1551,6 +1685,7 @@ dwarf2_finish (void)
     {
       segT abbrev_seg;
       segT aranges_seg;
+      segT ranges_seg;
 
       assert (all_segs);
       
@@ -1567,8 +1702,19 @@ dwarf2_finish (void)
 
       record_alignment (aranges_seg, ffs (2 * sizeof_address) - 1);
 
+      if (all_segs->next == NULL)
+	ranges_seg = NULL;
+      else
+	{
+	  ranges_seg = subseg_new (".debug_ranges", 0);
+	  bfd_set_section_flags (stdoutput, ranges_seg, 
+				 SEC_READONLY | SEC_DEBUGGING);
+	  record_alignment (ranges_seg, ffs (2 * sizeof_address) - 1);
+	  out_debug_ranges (ranges_seg);
+	}
+
       out_debug_aranges (aranges_seg, info_seg);
       out_debug_abbrev (abbrev_seg);
-      out_debug_info (info_seg, abbrev_seg, line_seg);
+      out_debug_info (info_seg, abbrev_seg, line_seg, ranges_seg);
     }
 }
diff --git a/contrib/binutils/gas/ecoff.c b/contrib/binutils/gas/ecoff.c
index 45116e8..2f9f71f 100644
--- a/contrib/binutils/gas/ecoff.c
+++ b/contrib/binutils/gas/ecoff.c
@@ -1,6 +1,6 @@
 /* ECOFF debugging support.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005
+   2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
    Contributed by Cygnus Support.
    This file was put together by Ian Lance Taylor <ian@cygnus.com>.  A
@@ -2778,7 +2778,7 @@ ecoff_directive_val (int ignore ATTRIBUTE_UNUSED)
   expression (&exp);
   if (exp.X_op != O_constant && exp.X_op != O_symbol)
     {
-      as_bad (_(".val expression is too copmlex"));
+      as_bad (_(".val expression is too complex"));
       demand_empty_rest_of_line ();
       return;
     }
diff --git a/contrib/binutils/gas/expr.c b/contrib/binutils/gas/expr.c
index 69f0aac..11f2942 100644
--- a/contrib/binutils/gas/expr.c
+++ b/contrib/binutils/gas/expr.c
@@ -1,6 +1,6 @@
 /* expr.c -operands, expressions-
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -25,7 +25,6 @@
    (It also gives smaller files to re-compile.)
    Here, "operand"s are of expressions, not instructions.  */
 
-#include <string.h>
 #define min(a, b)       ((a) < (b) ? (a) : (b))
 
 #include "as.h"
@@ -1003,11 +1002,6 @@ operand (expressionS *expressionP, enum expr_mode mode)
     case '-':
     case '+':
       {
-	/* Do not accept ++e or --e as +(+e) or -(-e)
-	   Disabled, since the preprocessor removes whitespace.  */
-	if (0 && (c == '-' || c == '+') && *input_line_pointer == c)
-	  goto target_op;
-	
 	operand (expressionP, mode);
 	if (expressionP->X_op == O_constant)
 	  {
@@ -1291,7 +1285,6 @@ operand (expressionS *expressionP, enum expr_mode mode)
 	}
       else
 	{
-	target_op:
 	  /* Let the target try to parse it.  Success is indicated by changing
 	     the X_op field to something other than O_absent and pointing
 	     input_line_pointer past the expression.  If it can't parse the
@@ -1552,11 +1545,7 @@ operator (int *num_chars)
 
     case '+':
     case '-':
-      /* Do not allow a++b and a--b to be a + (+b) and a - (-b)
-	 Disabled, since the preprocessor removes whitespace.  */
-      if (1 || input_line_pointer[1] != c)
-	return op_encoding[c];
-      return O_illegal;
+      return op_encoding[c];
 
     case '<':
       switch (input_line_pointer[1])
@@ -1647,7 +1636,7 @@ expr (int rankarg,		/* Larger # is higher rank.  */
   operatorT op_right;
   int op_chars;
 
-  know (rank >= 0);
+  know (rankarg >= 0);
 
   /* Save the value of dot for the fixup code.  */
   if (rank == 0)
@@ -1796,7 +1785,9 @@ expr (int rankarg,		/* Larger # is higher rank.  */
 	    case O_bit_or_not:		resultP->X_add_number |= ~v; break;
 	    case O_bit_exclusive_or:	resultP->X_add_number ^= v; break;
 	    case O_bit_and:		resultP->X_add_number &= v; break;
-	    case O_add:			resultP->X_add_number += v; break;
+	      /* Constant + constant (O_add) is handled by the
+		 previous if statement for constant + X, so is omitted
+		 here.  */
 	    case O_subtract:		resultP->X_add_number -= v; break;
 	    case O_eq:
 	      resultP->X_add_number =
diff --git a/contrib/binutils/gas/frags.c b/contrib/binutils/gas/frags.c
index b08ef50..adb9b19 100644
--- a/contrib/binutils/gas/frags.c
+++ b/contrib/binutils/gas/frags.c
@@ -389,9 +389,9 @@ frag_append_1_char (int datum)
    not already accounted for in the frag FR_ADDRESS.  */
 
 bfd_boolean
-frag_offset_fixed_p (fragS *frag1, fragS *frag2, bfd_vma *offset)
+frag_offset_fixed_p (const fragS *frag1, const fragS *frag2, bfd_vma *offset)
 {
-  fragS *frag;
+  const fragS *frag;
   bfd_vma off;
 
   /* Start with offset initialised to difference between the two frags.
diff --git a/contrib/binutils/gas/frags.h b/contrib/binutils/gas/frags.h
index 8804467..66630db 100644
--- a/contrib/binutils/gas/frags.h
+++ b/contrib/binutils/gas/frags.h
@@ -148,6 +148,6 @@ char *frag_var (relax_stateT type,
 		offsetT offset,
 		char *opcode);
 
-bfd_boolean frag_offset_fixed_p (fragS *, fragS *, bfd_vma *);
+bfd_boolean frag_offset_fixed_p (const fragS *, const fragS *, bfd_vma *);
 
 #endif /* FRAGS_H */
diff --git a/contrib/binutils/gas/gdbinit.in b/contrib/binutils/gas/gdbinit.in
index e946726..fb1046d 100644
--- a/contrib/binutils/gas/gdbinit.in
+++ b/contrib/binutils/gas/gdbinit.in
@@ -6,7 +6,6 @@ break as_warn_where
 break as_bad
 break as_bad_where
 break as_fatal
-break as_perror
 break as_assert
 break as_abort
 
diff --git a/contrib/binutils/gas/input-file.c b/contrib/binutils/gas/input-file.c
index 343f049..0907bad 100644
--- a/contrib/binutils/gas/input-file.c
+++ b/contrib/binutils/gas/input-file.c
@@ -1,6 +1,6 @@
 /* input_file.c - Deal with Input Files -
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1999, 2000, 2001,
-   2002, 2003, 2005
+   2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -25,9 +25,6 @@
    What we lose in "efficiency" we gain in modularity.
    Note we don't need to #include the "as.h" file. No common coupling!  */
 
-#include <stdio.h>
-#include <string.h>
-#include <errno.h>
 #include "as.h"
 #include "input-file.h"
 #include "safe-ctype.h"
@@ -143,8 +140,8 @@ input_file_open (char *filename, /* "" means use stdin. Must not be 0.  */
 
   if (f_in == NULL)
     {
-      bfd_set_error (bfd_error_system_call);
-      as_perror (_("Can't open %s for reading"), file_name);
+      as_bad (_("can't open %s for reading: %s"),
+	      file_name, xstrerror (errno));
       return;
     }
 
@@ -152,8 +149,8 @@ input_file_open (char *filename, /* "" means use stdin. Must not be 0.  */
 
   if (ferror (f_in))
     {
-      bfd_set_error (bfd_error_system_call);
-      as_perror (_("Can't open %s for reading"), file_name);
+      as_bad (_("can't read from %s: %s"),
+	      file_name, xstrerror (errno));
 
       fclose (f_in);
       f_in = NULL;
@@ -166,8 +163,8 @@ input_file_open (char *filename, /* "" means use stdin. Must not be 0.  */
       c = getc (f_in);
       if (c == 'N')
 	{
-	  fgets (buf, 80, f_in);
-	  if (!strncmp (buf, "O_APP", 5) && ISSPACE (buf[5]))
+	  if (fgets (buf, sizeof (buf), f_in)
+	      && !strncmp (buf, "O_APP", 5) && ISSPACE (buf[5]))
 	    preprocess = 0;
 	  if (!strchr (buf, '\n'))
 	    ungetc ('#', f_in);	/* It was longer.  */
@@ -176,8 +173,8 @@ input_file_open (char *filename, /* "" means use stdin. Must not be 0.  */
 	}
       else if (c == 'A')
 	{
-	  fgets (buf, 80, f_in);
-	  if (!strncmp (buf, "PP", 2) && ISSPACE (buf[2]))
+	  if (fgets (buf, sizeof (buf), f_in)
+	      && !strncmp (buf, "PP", 2) && ISSPACE (buf[2]))
 	    preprocess = 1;
 	  if (!strchr (buf, '\n'))
 	    ungetc ('#', f_in);
@@ -215,8 +212,7 @@ input_file_get (char *buf, int buflen)
   size = fread (buf, sizeof (char), buflen, f_in);
   if (size < 0)
     {
-      bfd_set_error (bfd_error_system_call);
-      as_perror (_("Can't read from %s"), file_name);
+      as_bad (_("can't read from %s: %s"), file_name, xstrerror (errno));
       size = 0;
     }
   return size;
@@ -242,8 +238,7 @@ input_file_give_next_buffer (char *where /* Where to place 1st character of new
     size = fread (where, sizeof (char), BUFFER_SIZE, f_in);
   if (size < 0)
     {
-      bfd_set_error (bfd_error_system_call);
-      as_perror (_("Can't read from %s"), file_name);
+      as_bad (_("can't read from %s: %s"), file_name, xstrerror (errno));
       size = 0;
     }
   if (size)
@@ -251,10 +246,8 @@ input_file_give_next_buffer (char *where /* Where to place 1st character of new
   else
     {
       if (fclose (f_in))
-	{
-	  bfd_set_error (bfd_error_system_call);
-	  as_perror (_("Can't close %s"), file_name);
-	}
+	as_warn (_("can't close %s: %s"), file_name, xstrerror (errno));
+
       f_in = (FILE *) 0;
       return_value = 0;
     }
diff --git a/contrib/binutils/gas/input-file.h b/contrib/binutils/gas/input-file.h
index bc8289e..0628716 100644
--- a/contrib/binutils/gas/input-file.h
+++ b/contrib/binutils/gas/input-file.h
@@ -1,5 +1,6 @@
 /* input_file.h header for input-file.c
-   Copyright 1987, 1992, 1993, 2000, 2003 Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1993, 2000, 2003, 2005, 2006
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -51,8 +52,8 @@
  *
  * input_file_close ()			Closes opened file.
  *
- * All errors are reported (using as_perror) so caller doesn't have to think
- * about I/O errors. No I/O errors are fatal: an end-of-file may be faked.
+ * All errors are reported so caller doesn't have to think
+ * about I/O errors.
  */
 
 char *input_file_give_next_buffer (char *where);
diff --git a/contrib/binutils/gas/input-scrub.c b/contrib/binutils/gas/input-scrub.c
index 8562ee2..5698a6d 100644
--- a/contrib/binutils/gas/input-scrub.c
+++ b/contrib/binutils/gas/input-scrub.c
@@ -1,6 +1,6 @@
 /* input_scrub.c - Break up input buffers into whole numbers of lines.
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   2000, 2001, 2003
+   2000, 2001, 2003, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -20,7 +20,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <errno.h>		/* Need this to make errno declaration right */
 #include "as.h"
 #include "input-file.h"
 #include "sb.h"
@@ -57,6 +56,10 @@
 #define BEFORE_SIZE (1)
 #define AFTER_SIZE  (1)
 
+#ifndef TC_EOL_IN_INSN
+#define TC_EOL_IN_INSN(P) 0
+#endif
+
 static char *buffer_start;	/*->1st char of full buffer area.  */
 static char *partial_where;	/*->after last full line in buffer.  */
 static int partial_size;	/* >=0. Number of chars in partial line in buffer.  */
@@ -342,8 +345,9 @@ input_scrub_next_buffer (char **bufp)
   if (limit)
     {
       register char *p;		/* Find last newline.  */
-
-      for (p = limit - 1; *p != '\n'; --p)
+      /* Terminate the buffer to avoid confusing TC_EOL_IN_INSN.  */
+      *limit = '\0';
+      for (p = limit - 1; *p != '\n' || TC_EOL_IN_INSN (p); --p)
 	;
       ++p;
 
@@ -369,7 +373,9 @@ input_scrub_next_buffer (char **bufp)
 	      return NULL;
 	    }
 
-	  for (p = limit - 1; *p != '\n'; --p)
+	  /* Terminate the buffer to avoid confusing TC_EOL_IN_INSN.  */
+	  *limit = '\0';
+	  for (p = limit - 1; *p != '\n' || TC_EOL_IN_INSN (p); --p)
 	    ;
 	  ++p;
 	}
@@ -429,13 +435,34 @@ bump_line_counters (void)
    Returns nonzero if the filename actually changes.  */
 
 int
-new_logical_line (char *fname, /* DON'T destroy it!  We point to it!  */
-		  int line_number)
+new_logical_line_flags (char *fname, /* DON'T destroy it!  We point to it!  */
+			int line_number,
+			int flags)
 {
+  switch (flags)
+    {
+    case 0:
+      break;
+    case 1:
+      if (line_number != -1)
+	abort ();
+      break;
+    case 1 << 1:
+    case 1 << 2:
+      /* FIXME: we could check that include nesting is correct.  */
+      break;
+    default:
+      abort ();
+    }
+
   if (line_number >= 0)
     logical_input_line = line_number;
-  else if (line_number == -2 && logical_input_line > 0)
-    --logical_input_line;
+  else if (line_number == -1 && fname && !*fname && (flags & (1 << 2)))
+    {
+      logical_input_file = physical_input_file;
+      logical_input_line = physical_input_line;
+      fname = NULL;
+    }
 
   if (fname
       && (logical_input_file == NULL
@@ -447,6 +474,13 @@ new_logical_line (char *fname, /* DON'T destroy it!  We point to it!  */
   else
     return 0;
 }
+
+int
+new_logical_line (char *fname, int line_number)
+{
+  return new_logical_line_flags (fname, line_number, 0);
+}
+
 
 /* Return the current file name and line number.
    namep should be char * const *, but there are compilers which screw
diff --git a/contrib/binutils/gas/itbl-lex.l b/contrib/binutils/gas/itbl-lex.l
index aceeac4..185f956 100644
--- a/contrib/binutils/gas/itbl-lex.l
+++ b/contrib/binutils/gas/itbl-lex.l
@@ -1,5 +1,6 @@
 /* itbl-lex.l
-   Copyright 1997, 1998, 2001, 2002, 2005 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 2001, 2002, 2005, 2006
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,10 +20,7 @@
    02110-1301, USA.  */
 
 %{
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-
+#include "as.h"
 #include "itbl-lex.h"
 #include <itbl-parse.h>
 
diff --git a/contrib/binutils/gas/itbl-ops.c b/contrib/binutils/gas/itbl-ops.c
index bd1f647..41fa033 100644
--- a/contrib/binutils/gas/itbl-ops.c
+++ b/contrib/binutils/gas/itbl-ops.c
@@ -1,5 +1,5 @@
 /* itbl-ops.c
-   Copyright 1997, 1999, 2000, 2001, 2002, 2003, 2005
+   Copyright 1997, 1999, 2000, 2001, 2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -89,9 +89,7 @@
  *
  */
 
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
+#include "as.h"
 #include "itbl-ops.h"
 #include <itbl-parse.h>
 
@@ -147,12 +145,7 @@ struct itbl_entry {
 
 static int itbl_num_opcodes = 0;
 /* Array of entries for each processor and entry type */
-static struct itbl_entry *entries[e_nprocs][e_ntypes] = {
-  {0, 0, 0, 0, 0, 0},
-  {0, 0, 0, 0, 0, 0},
-  {0, 0, 0, 0, 0, 0},
-  {0, 0, 0, 0, 0, 0}
-};
+static struct itbl_entry *entries[e_nprocs][e_ntypes];
 
 /* local prototypes */
 static unsigned long build_opcode (struct itbl_entry *e);
@@ -253,8 +246,6 @@ itbl_add_operand (struct itbl_entry *e, int yytype, int sbit,
 /* Interfaces for assembler and disassembler */
 
 #ifndef STAND_ALONE
-#include "as.h"
-#include "symbols.h"
 static void append_insns_as_macros (void);
 
 /* Initialize for gas.  */
diff --git a/contrib/binutils/gas/itbl-ops.h b/contrib/binutils/gas/itbl-ops.h
index 47dc8b2..d9dbf7c 100644
--- a/contrib/binutils/gas/itbl-ops.h
+++ b/contrib/binutils/gas/itbl-ops.h
@@ -1,5 +1,5 @@
 /* itbl-ops.h
-   Copyright 1997, 1999, 2000, 2003 Free Software Foundation, Inc.
+   Copyright 1997, 1999, 2000, 2003, 2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -20,14 +20,6 @@
 
 /* External functions, constants and defines for itbl support */
 
-#include "ansidecl.h"
-
-/* Include file notes: "expr.h" needed before targ-*.h,
- * "targ-env.h" includes the chain of target dependant headers,
- * "targ-cpu.h" has the HAVE_ITBL_CPU define, and
- * as.h includes them all */
-#include "as.h"
-
 #ifdef HAVE_ITBL_CPU
 #include "itbl-cpu.h"
 #endif
@@ -77,7 +69,7 @@ typedef enum
 typedef enum
   {
     e_p0,
-    e_nprocs = NUMBER_OF_PROCESSORS,
+    e_nprocs = ITBL_NUMBER_OF_PROCESSORS,
     e_invproc			/* invalid processor */
   } e_processor;
 
diff --git a/contrib/binutils/gas/itbl-parse.y b/contrib/binutils/gas/itbl-parse.y
index a7a52df..ff48657 100644
--- a/contrib/binutils/gas/itbl-parse.y
+++ b/contrib/binutils/gas/itbl-parse.y
@@ -1,5 +1,5 @@
 /* itbl-parse.y
-   Copyright 1997, 2002, 2003, 2005 Free Software Foundation, Inc.
+   Copyright 1997, 2002, 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -246,7 +246,7 @@ FIXME! hex is ambiguous with any digit
 
 */
 
-#include <stdio.h>
+#include "as.h"
 #include "itbl-lex.h"
 #include "itbl-ops.h"
 
@@ -274,7 +274,7 @@ FIXME! hex is ambiguous with any digit
 
 static int sbit, ebit;
 static struct itbl_entry *insn=0;
-static int yyerror PARAMS ((const char *));
+static int yyerror (const char *);
 
 %}
 
diff --git a/contrib/binutils/gas/listing.c b/contrib/binutils/gas/listing.c
index 61ef6f5..1b55cbf 100644
--- a/contrib/binutils/gas/listing.c
+++ b/contrib/binutils/gas/listing.c
@@ -1,6 +1,6 @@
 /* listing.c - maintain assembly listings
    Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2005
+   2001, 2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -946,15 +946,6 @@ listing_listing (char *name ATTRIBUTE_UNUSED)
   buffer = xmalloc (listing_rhs_width);
   data_buffer = xmalloc (MAX_BYTES);
   eject = 1;
-  list = head;
-
-  while (list != (list_info_type *) NULL && 0)
-    {
-      if (list->next)
-	list->frag = list->next->frag;
-      list = list->next;
-    }
-
   list = head->next;
 
   while (list)
@@ -1085,8 +1076,7 @@ listing_print (char *name)
 	using_stdout = 0;
       else
 	{
-	  bfd_set_error (bfd_error_system_call);
-	  as_perror (_("can't open list file: %s"), name);
+	  as_warn (_("can't open %s: %s"), name, xstrerror (errno));
 	  list_file = stdout;
 	  using_stdout = 1;
 	}
@@ -1104,10 +1094,7 @@ listing_print (char *name)
   if (! using_stdout)
     {
       if (fclose (list_file) == EOF)
-	{
-	  bfd_set_error (bfd_error_system_call);
-	  as_perror (_("error closing list file: %s"), name);
-	}
+	as_warn (_("can't close %s: %s"), name, xstrerror (errno));
     }
 
   if (last_open_file)
diff --git a/contrib/binutils/gas/macro.c b/contrib/binutils/gas/macro.c
index af98bad..d7d470b 100644
--- a/contrib/binutils/gas/macro.c
+++ b/contrib/binutils/gas/macro.c
@@ -1,6 +1,6 @@
 /* macro.c - macro support for gas
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005 Free Software Foundation, Inc.
+   2004, 2005, 2006 Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
       sac@cygnus.com
@@ -22,47 +22,11 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include "config.h"
-
-#ifndef __GNUC__
-# if HAVE_ALLOCA_H
-#  include <alloca.h>
-# else
-#  ifdef _AIX
-/* Indented so that pre-ansi C compilers will ignore it, rather than
-   choke on it.  Some versions of AIX require this to be the first
-   thing in the file.  */
- #pragma alloca
-#  else
-#   ifndef alloca /* predefined by HP cc +Olibcalls */
-#    if !defined (__STDC__) && !defined (__hpux)
-extern char *alloca ();
-#    else
-extern void *alloca ();
-#    endif /* __STDC__, __hpux */
-#   endif /* alloca */
-#  endif /* _AIX */
-# endif /* HAVE_ALLOCA_H */
-#endif /* __GNUC__ */
-
-#include <stdio.h>
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#include <strings.h>
-#endif
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
 #include "as.h"
-#include "libiberty.h"
 #include "safe-ctype.h"
 #include "sb.h"
-#include "hash.h"
 #include "macro.h"
 
-#include "asintl.h"
-
 /* The routines in this file handle macro definition and expansion.
    They are called by gas.  */
 
@@ -1025,7 +989,6 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
   sb t;
   formal_entry *ptr;
   formal_entry *f;
-  int is_positional = 0;
   int is_keyword = 0;
   int narg = 0;
   const char *err = NULL;
@@ -1116,8 +1079,6 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
 	}
       else
 	{
-	  /* This is a positional arg.  */
-	  is_positional = 1;
 	  if (is_keyword)
 	    {
 	      err = _("can't mix positional and keyword arguments");
@@ -1364,8 +1325,14 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
     }
   else
     {
+      bfd_boolean in_quotes = FALSE;
+
       if (irpc && in->ptr[idx] == '"')
-	++idx;
+	{
+	  in_quotes = TRUE;
+	  ++idx;
+	}
+
       while (idx < in->len)
 	{
 	  if (!irpc)
@@ -1376,6 +1343,9 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
 		{
 		  int nxt;
 
+		  if (irpc)
+		    in_quotes = ! in_quotes;
+	  
 		  nxt = sb_skip_white (idx + 1, in);
 		  if (nxt >= in->len)
 		    {
@@ -1387,12 +1357,13 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
 	      sb_add_char (&f.actual, in->ptr[idx]);
 	      ++idx;
 	    }
+
 	  err = macro_expand_body (&sub, out, &f, h, 0);
 	  if (err != NULL)
 	    break;
 	  if (!irpc)
 	    idx = sb_skip_comma (idx, in);
-	  else
+	  else if (! in_quotes)
 	    idx = sb_skip_white (idx, in);
 	}
     }
diff --git a/contrib/binutils/gas/macro.h b/contrib/binutils/gas/macro.h
index 4fdaa52..104aeae 100644
--- a/contrib/binutils/gas/macro.h
+++ b/contrib/binutils/gas/macro.h
@@ -1,5 +1,5 @@
 /* macro.h - header file for macro support for gas
-   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2002, 2003, 2004
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2002, 2003, 2004, 2006
    Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
@@ -26,9 +26,6 @@
 
 #define MACRO_H
 
-#include "ansidecl.h"
-#include "sb.h"
-
 /* Structures used to store macros.
 
    Each macro knows its name and included text.  It gets built with a
diff --git a/contrib/binutils/gas/messages.c b/contrib/binutils/gas/messages.c
index b1b94cd..c8788dc 100644
--- a/contrib/binutils/gas/messages.c
+++ b/contrib/binutils/gas/messages.c
@@ -1,6 +1,6 @@
 /* messages.c - error reporter -
    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2001,
-   2003, 2004, 2005
+   2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
    This file is part of GAS, the GNU Assembler.
 
@@ -116,24 +116,6 @@ as_show_where (void)
     fprintf (stderr, "%s:%u: ", file, line);
 }
 
-/* Like perror(3), but with more info.  */
-
-void
-as_perror (const char *gripe,		/* Unpunctuated error theme.  */
-	   const char *filename)
-{
-  const char *errtxt;
-  int saved_errno = errno;
-
-  as_show_where ();
-  fprintf (stderr, gripe, filename);
-  errno = saved_errno;
-  errtxt = bfd_errmsg (bfd_get_error ());
-  fprintf (stderr, ": %s\n", errtxt);
-  errno = 0;
-  bfd_set_error (bfd_error_no_error);
-}
-
 /* Send to stderr a string as a warning, and locate warning
    in input file(s).
    Please only use this for when we have some recovery action.
@@ -474,6 +456,24 @@ as_internal_value_out_of_range (char *    prefix,
   if (prefix == NULL)
     prefix = "";
 
+  if (val >= min && val <= max)
+    {
+      addressT right = max & -max;
+
+      if (max <= 1)
+	abort ();
+
+      /* xgettext:c-format  */
+      err = _("%s out of domain (%d is not a multiple of %d)");
+      if (bad)
+	as_bad_where (file, line, err,
+		      prefix, (int) val, (int) right);
+      else
+	as_warn_where (file, line, err,
+		       prefix, (int) val, (int) right);
+      return;
+    }
+
   if (   val < HEX_MAX_THRESHOLD
       && min < HEX_MAX_THRESHOLD
       && max < HEX_MAX_THRESHOLD
diff --git a/contrib/binutils/gas/output-file.c b/contrib/binutils/gas/output-file.c
index f94359a..9603dc4 100644
--- a/contrib/binutils/gas/output-file.c
+++ b/contrib/binutils/gas/output-file.c
@@ -1,6 +1,6 @@
 /* output-file.c -  Deal with the output file
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1996, 1998, 1999, 2001,
-   2003, 2004, 2005 Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,17 +19,13 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <stdio.h>
-
 #include "as.h"
-
 #include "output-file.h"
 
 #ifndef TARGET_MACH
 #define TARGET_MACH 0
 #endif
 
-#include "bfd.h"
 bfd *stdoutput;
 
 void
@@ -40,11 +36,12 @@ output_file_create (char *name)
 
   else if (!(stdoutput = bfd_openw (name, TARGET_FORMAT)))
     {
-      if (bfd_get_error () == bfd_error_invalid_target)
-	as_perror (_("Selected target format '%s' unknown"), TARGET_FORMAT);
+      bfd_error_type err = bfd_get_error ();
+
+      if (err == bfd_error_invalid_target)
+	as_fatal (_("selected target format '%s' unknown"), TARGET_FORMAT);
       else
-	as_perror (_("FATAL: can't create %s"), name);
-      exit (EXIT_FAILURE);
+	as_fatal (_("can't create %s: %s"), name, bfd_errmsg (err));
     }
 
   bfd_set_format (stdoutput, bfd_object);
@@ -56,12 +53,19 @@ output_file_create (char *name)
 void
 output_file_close (char *filename)
 {
+  bfd_boolean res;
+
+  if (stdoutput == NULL)
+    return;
+    
   /* Close the bfd.  */
-  if (bfd_close (stdoutput) == 0)
-    {
-      bfd_perror (filename);
-      as_perror (_("FATAL: can't close %s\n"), filename);
-      exit (EXIT_FAILURE);
-    }
-  stdoutput = NULL;		/* Trust nobody!  */
+  res = bfd_close (stdoutput);
+
+  /* Prevent an infinite loop - if the close failed we will call as_fatal
+     which will call xexit() which may call this function again...  */
+  stdoutput = NULL;
+
+  if (! res)
+    as_fatal (_("can't close %s: %s"), filename,
+	      bfd_errmsg (bfd_get_error ()));
 }
diff --git a/contrib/binutils/gas/po/Make-in b/contrib/binutils/gas/po/Make-in
index be09b4c..86ff314 100644
--- a/contrib/binutils/gas/po/Make-in
+++ b/contrib/binutils/gas/po/Make-in
@@ -16,6 +16,7 @@ SHELL = /bin/sh
 srcdir = @srcdir@
 top_srcdir = @top_srcdir@
 VPATH = @srcdir@
+top_builddir = @top_builddir@
 
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -72,7 +73,7 @@ INSTOBJEXT = @INSTOBJEXT@
 	$(MSGFMT) -o $@ $<
 
 .po.gmo:
-	file=$(srcdir)/`echo $* | sed 's,.*/,,'`.gmo \
+	file=`echo $* | sed 's,.*/,,'`.gmo \
 	  && rm -f $$file && $(GMSGFMT) -o $$file $<
 
 .po.cat:
diff --git a/contrib/binutils/gas/po/POTFILES.in b/contrib/binutils/gas/po/POTFILES.in
index 3a173a5..4215a09 100644
--- a/contrib/binutils/gas/po/POTFILES.in
+++ b/contrib/binutils/gas/po/POTFILES.in
@@ -24,8 +24,6 @@ config/obj-elf.c
 config/obj-elf.h
 config/obj-evax.c
 config/obj-evax.h
-config/obj-ieee.c
-config/obj-ieee.h
 config/obj-som.c
 config/obj-som.h
 config/tc-alpha.c
@@ -38,6 +36,8 @@ config/tc-avr.c
 config/tc-avr.h
 config/tc-bfin.c
 config/tc-bfin.h
+config/tc-cr16.c
+config/tc-cr16.h
 config/tc-cris.c
 config/tc-cris.h
 config/tc-crx.c
@@ -78,6 +78,8 @@ config/tc-m68k.c
 config/tc-m68k.h
 config/tc-mcore.c
 config/tc-mcore.h
+config/tc-mep.c
+config/tc-mep.h
 config/tc-mips.c
 config/tc-mips.h
 config/tc-mmix.c
@@ -102,12 +104,16 @@ config/tc-ppc.c
 config/tc-ppc.h
 config/tc-s390.c
 config/tc-s390.h
+config/tc-score.c
+config/tc-score.h
 config/tc-sh64.c
 config/tc-sh64.h
 config/tc-sh.c
 config/tc-sh.h
 config/tc-sparc.c
 config/tc-sparc.h
+config/tc-spu.c
+config/tc-spu.h
 config/tc-tic30.c
 config/tc-tic30.h
 config/tc-tic54x.c
diff --git a/contrib/binutils/gas/po/gas.pot b/contrib/binutils/gas/po/gas.pot
index 122a678..575f36e 100644
--- a/contrib/binutils/gas/po/gas.pot
+++ b/contrib/binutils/gas/po/gas.pot
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2005-10-25 08:41+0930\n"
+"POT-Creation-Date: 2007-07-02 15:56+0930\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -16,64 +16,64 @@ msgstr ""
 "Content-Type: text/plain; charset=CHARSET\n"
 "Content-Transfer-Encoding: 8bit\n"
 
-#: app.c:470 app.c:484
+#: app.c:473 app.c:487
 msgid "end of file in comment"
 msgstr ""
 
-#: app.c:560 app.c:605
+#: app.c:559 app.c:604
 #, c-format
 msgid "end of file in string; '%c' inserted"
 msgstr ""
 
-#: app.c:631
+#: app.c:630
 #, c-format
 msgid "unknown escape '\\%c' in string; ignored"
 msgstr ""
 
-#: app.c:786
+#: app.c:793
 msgid "end of file not at end of a line; newline inserted"
 msgstr ""
 
-#: app.c:945
+#: app.c:949
 msgid "end of file in multiline comment"
 msgstr ""
 
-#: app.c:1010
+#: app.c:1014
 msgid "end of file after a one-character quote; \\0 inserted"
 msgstr ""
 
-#: app.c:1018
+#: app.c:1022
 msgid "end of file in escape character"
 msgstr ""
 
-#: app.c:1030
+#: app.c:1034
 msgid "missing close quote; (assumed)"
 msgstr ""
 
-#: app.c:1098 app.c:1152 app.c:1163 app.c:1228
+#: app.c:1102 app.c:1156 app.c:1167 app.c:1241
 msgid "end of file in comment; newline inserted"
 msgstr ""
 
-#: as.c:161
+#: as.c:158
 msgid "missing emulation mode name"
 msgstr ""
 
-#: as.c:176
+#: as.c:173
 #, c-format
 msgid "unrecognized emulation name `%s'"
 msgstr ""
 
-#: as.c:223
+#: as.c:220
 #, c-format
 msgid "GNU assembler version %s (%s) using BFD version %s\n"
 msgstr ""
 
-#: as.c:230
+#: as.c:227
 #, c-format
 msgid "Usage: %s [option...] [asmfile...]\n"
 msgstr ""
 
-#: as.c:232
+#: as.c:229
 #, c-format
 msgid ""
 "Options:\n"
@@ -89,131 +89,131 @@ msgid ""
 "                      \t  =FILE  list to FILE (must be last sub-option)\n"
 msgstr ""
 
-#: as.c:245
+#: as.c:242
 #, c-format
 msgid "  --alternate             initially turn on alternate macro syntax\n"
 msgstr ""
 
-#: as.c:247
+#: as.c:244
 #, c-format
 msgid "  -D                      produce assembler debugging messages\n"
 msgstr ""
 
-#: as.c:249
+#: as.c:246
 #, c-format
 msgid "  --defsym SYM=VAL        define symbol SYM to given value\n"
 msgstr ""
 
-#: as.c:265
+#: as.c:262
 #, c-format
 msgid "                          emulate output (default %s)\n"
 msgstr ""
 
-#: as.c:270
+#: as.c:267
 #, c-format
 msgid "  --execstack             require executable stack for this object\n"
 msgstr ""
 
-#: as.c:272
+#: as.c:269
 #, c-format
 msgid ""
 "  --noexecstack           don't require executable stack for this object\n"
 msgstr ""
 
-#: as.c:275
+#: as.c:272
 #, c-format
 msgid "  -f                      skip whitespace and comment preprocessing\n"
 msgstr ""
 
-#: as.c:277
+#: as.c:274
 #, c-format
 msgid "  -g --gen-debug          generate debugging information\n"
 msgstr ""
 
-#: as.c:279
+#: as.c:276
 #, c-format
 msgid "  --gstabs                generate STABS debugging information\n"
 msgstr ""
 
-#: as.c:281
+#: as.c:278
 #, c-format
 msgid ""
 "  --gstabs+               generate STABS debug info with GNU extensions\n"
 msgstr ""
 
-#: as.c:283
+#: as.c:280
 #, c-format
 msgid "  --gdwarf-2              generate DWARF2 debugging information\n"
 msgstr ""
 
-#: as.c:285
+#: as.c:282
 #, c-format
 msgid "  --hash-size=<value>     set the hash table size close to <value>\n"
 msgstr ""
 
-#: as.c:287
+#: as.c:284
 #, c-format
 msgid "  --help                  show this message and exit\n"
 msgstr ""
 
-#: as.c:289
+#: as.c:286
 #, c-format
 msgid "  --target-help           show target specific options\n"
 msgstr ""
 
-#: as.c:291
+#: as.c:288
 #, c-format
 msgid ""
 "  -I DIR                  add DIR to search list for .include directives\n"
 msgstr ""
 
-#: as.c:293
+#: as.c:290
 #, c-format
 msgid "  -J                      don't warn about signed overflow\n"
 msgstr ""
 
-#: as.c:295
+#: as.c:292
 #, c-format
 msgid ""
 "  -K                      warn when differences altered for long "
 "displacements\n"
 msgstr ""
 
-#: as.c:297
+#: as.c:294
 #, c-format
 msgid "  -L,--keep-locals        keep local symbols (e.g. starting with `L')\n"
 msgstr ""
 
-#: as.c:299
+#: as.c:296
 #, c-format
 msgid "  -M,--mri                assemble in MRI compatibility mode\n"
 msgstr ""
 
-#: as.c:301
+#: as.c:298
 #, c-format
 msgid ""
 "  --MD FILE               write dependency information in FILE (default "
 "none)\n"
 msgstr ""
 
-#: as.c:303
+#: as.c:300
 #, c-format
 msgid "  -nocpp                  ignored\n"
 msgstr ""
 
-#: as.c:305
+#: as.c:302
 #, c-format
 msgid ""
 "  -o OBJFILE              name the object-file output OBJFILE (default a."
 "out)\n"
 msgstr ""
 
-#: as.c:307
+#: as.c:304
 #, c-format
 msgid "  -R                      fold data section into text section\n"
 msgstr ""
 
-#: as.c:309
+#: as.c:306
 #, c-format
 msgid ""
 "  --reduce-memory-overheads \n"
@@ -221,44 +221,44 @@ msgid ""
 "                          assembly times\n"
 msgstr ""
 
-#: as.c:313
+#: as.c:310
 #, c-format
 msgid ""
 "  --statistics            print various measured statistics from execution\n"
 msgstr ""
 
-#: as.c:315
+#: as.c:312
 #, c-format
 msgid "  --strip-local-absolute  strip local absolute symbols\n"
 msgstr ""
 
-#: as.c:317
+#: as.c:314
 #, c-format
 msgid ""
 "  --traditional-format    Use same format as native assembler when possible\n"
 msgstr ""
 
-#: as.c:319
+#: as.c:316
 #, c-format
 msgid "  --version               print assembler version number and exit\n"
 msgstr ""
 
-#: as.c:321
+#: as.c:318
 #, c-format
 msgid "  -W  --no-warn           suppress warnings\n"
 msgstr ""
 
-#: as.c:323
+#: as.c:320
 #, c-format
 msgid "  --warn                  don't suppress warnings\n"
 msgstr ""
 
-#: as.c:325
+#: as.c:322
 #, c-format
 msgid "  --fatal-warnings        treat warnings as errors\n"
 msgstr ""
 
-#: as.c:327
+#: as.c:324
 #, c-format
 msgid ""
 "  --itbl INSTTBL          extend instruction set to include instructions\n"
@@ -266,22 +266,22 @@ msgid ""
 "INSTTBL\n"
 msgstr ""
 
-#: as.c:330
+#: as.c:327
 #, c-format
 msgid "  -w                      ignored\n"
 msgstr ""
 
-#: as.c:332
+#: as.c:329
 #, c-format
 msgid "  -X                      ignored\n"
 msgstr ""
 
-#: as.c:334
+#: as.c:331
 #, c-format
 msgid "  -Z                      generate object file even after errors\n"
 msgstr ""
 
-#: as.c:336
+#: as.c:333
 #, c-format
 msgid ""
 "  --listing-lhs-width     set the width in words of the output data column "
@@ -289,7 +289,7 @@ msgid ""
 "                          the listing\n"
 msgstr ""
 
-#: as.c:339
+#: as.c:336
 #, c-format
 msgid ""
 "  --listing-lhs-width2    set the width in words of the continuation lines\n"
@@ -298,124 +298,129 @@ msgid ""
 "                          the width of the first line\n"
 msgstr ""
 
-#: as.c:343
+#: as.c:340
 #, c-format
 msgid ""
 "  --listing-rhs-width     set the max width in characters of the lines from\n"
 "                          the source file\n"
 msgstr ""
 
-#: as.c:346
+#: as.c:343
 #, c-format
 msgid ""
 "  --listing-cont-lines    set the maximum number of continuation lines used\n"
 "                          for the output data column of the listing\n"
 msgstr ""
 
-#: as.c:353
+#: as.c:346
+#, c-format
+msgid "  @FILE                   read options from FILE\n"
+msgstr ""
+
+#: as.c:354
 #, c-format
 msgid "Report bugs to %s\n"
 msgstr ""
 
-#: as.c:553
+#: as.c:554
 #, c-format
 msgid "unrecognized option -%c%s"
 msgstr ""
 
 #. This output is intended to follow the GNU standards document.
-#: as.c:591
+#: as.c:592
 #, c-format
 msgid "GNU assembler %s\n"
 msgstr ""
 
-#: as.c:592
+#: as.c:593
 #, c-format
-msgid "Copyright 2005 Free Software Foundation, Inc.\n"
+msgid "Copyright 2007 Free Software Foundation, Inc.\n"
 msgstr ""
 
-#: as.c:593
+#: as.c:594
 #, c-format
 msgid ""
 "This program is free software; you may redistribute it under the terms of\n"
 "the GNU General Public License.  This program has absolutely no warranty.\n"
 msgstr ""
 
-#: as.c:596
+#: as.c:597
 #, c-format
 msgid "This assembler was configured for a target of `%s'.\n"
 msgstr ""
 
-#: as.c:603
+#: as.c:604
 msgid "multiple emulation names specified"
 msgstr ""
 
-#: as.c:605
+#: as.c:606
 msgid "emulations not handled in this configuration"
 msgstr ""
 
-#: as.c:610
+#: as.c:611
 #, c-format
 msgid "alias = %s\n"
 msgstr ""
 
-#: as.c:611
+#: as.c:612
 #, c-format
 msgid "canonical = %s\n"
 msgstr ""
 
-#: as.c:612
+#: as.c:613
 #, c-format
 msgid "cpu-type = %s\n"
 msgstr ""
 
-#: as.c:614
+#: as.c:615
 #, c-format
 msgid "format = %s\n"
 msgstr ""
 
-#: as.c:617
+#: as.c:618
 #, c-format
 msgid "bfd-target = %s\n"
 msgstr ""
 
-#: as.c:630
+#: as.c:631
 msgid "bad defsym; format is --defsym name=value"
 msgstr ""
 
-#: as.c:650
+#: as.c:651
 msgid "no file name following -t option"
 msgstr ""
 
-#: as.c:665
+#: as.c:666
 #, c-format
 msgid "failed to read instruction table %s\n"
 msgstr ""
 
-#: as.c:832
+#: as.c:833
 #, c-format
 msgid "invalid listing option `%c'"
 msgstr ""
 
-#: as.c:885
+#: as.c:886
 msgid "--hash-size needs a numeric argument"
 msgstr ""
 
-#: as.c:910
+#: as.c:911
 #, c-format
 msgid "%s: total time in assembly: %ld.%06ld\n"
 msgstr ""
 
-#: as.c:913
+#: as.c:914
 #, c-format
 msgid "%s: data size %ld\n"
 msgstr ""
 
-#: as.c:1175
+#: as.c:1222
 #, c-format
 msgid "%d warnings, treating warnings as errors"
 msgstr ""
 
-#: as.h:200
+#: as.h:237
 #, c-format
 msgid "Case value %ld unexpected at line %d of file \"%s\"\n"
 msgstr ""
@@ -424,71 +429,71 @@ msgstr ""
 #. * We have a GROSS internal error.
 #. * This should never happen.
 #.
-#: atof-generic.c:419 config/tc-m68k.c:3118
+#: atof-generic.c:417 config/tc-m68k.c:3342
 msgid "failed sanity check"
 msgstr ""
 
-#: cond.c:82
+#: cond.c:83
 msgid "invalid identifier for \".ifdef\""
 msgstr ""
 
-#: cond.c:149
+#: cond.c:150
 msgid "non-constant expression in \".if\" statement"
 msgstr ""
 
-#: cond.c:276
+#: cond.c:277
 msgid "bad format for ifc or ifnc"
 msgstr ""
 
-#: cond.c:306
+#: cond.c:307
 msgid "\".elseif\" without matching \".if\""
 msgstr ""
 
-#: cond.c:310
+#: cond.c:311
 msgid "\".elseif\" after \".else\""
 msgstr ""
 
-#: cond.c:313 cond.c:419
+#: cond.c:314 cond.c:420
 msgid "here is the previous \"else\""
 msgstr ""
 
-#: cond.c:316 cond.c:422
+#: cond.c:317 cond.c:423
 msgid "here is the previous \"if\""
 msgstr ""
 
-#: cond.c:345
+#: cond.c:346
 msgid "non-constant expression in \".elseif\" statement"
 msgstr ""
 
-#: cond.c:383
+#: cond.c:384
 msgid "\".endif\" without \".if\""
 msgstr ""
 
-#: cond.c:412
+#: cond.c:413
 msgid "\".else\" without matching \".if\""
 msgstr ""
 
-#: cond.c:416
+#: cond.c:417
 msgid "duplicate \"else\""
 msgstr ""
 
-#: cond.c:467
+#: cond.c:468
 msgid ".ifeqs syntax error"
 msgstr ""
 
-#: cond.c:548
+#: cond.c:549
 msgid "end of macro inside conditional"
 msgstr ""
 
-#: cond.c:550
+#: cond.c:551
 msgid "end of file inside conditional"
 msgstr ""
 
-#: cond.c:553
+#: cond.c:554
 msgid "here is the start of the unterminated conditional"
 msgstr ""
 
-#: cond.c:557
+#: cond.c:558
 msgid "here is the \"else\" of the unterminated conditional"
 msgstr ""
 
@@ -502,7 +507,7 @@ msgstr ""
 msgid "Attempt to put an undefined symbol into set %s"
 msgstr ""
 
-#: config/obj-aout.c:116 config/obj-coff.c:1328
+#: config/obj-aout.c:116 config/obj-coff.c:1340
 #, c-format
 msgid "Symbol `%s' can not be both weak and common"
 msgstr ""
@@ -513,82 +518,82 @@ msgid "Inserting \"%s\" into structure table failed: %s"
 msgstr ""
 
 #. Zero is used as an end marker in the file.
-#: config/obj-coff.c:354
+#: config/obj-coff.c:366
 msgid "Line numbers must be positive integers\n"
 msgstr ""
 
-#: config/obj-coff.c:386
+#: config/obj-coff.c:398
 msgid ".ln pseudo-op inside .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:428 ecoff.c:3240
+#: config/obj-coff.c:440 ecoff.c:3240
 msgid ".loc outside of .text"
 msgstr ""
 
-#: config/obj-coff.c:435
+#: config/obj-coff.c:447
 msgid ".loc pseudo-op inside .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:516
+#: config/obj-coff.c:528
 msgid ".def pseudo-op used inside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:555
+#: config/obj-coff.c:567
 msgid ".endef pseudo-op used outside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:594
+#: config/obj-coff.c:606
 #, c-format
 msgid "`%s' symbol without preceding function"
 msgstr ""
 
-#: config/obj-coff.c:681
+#: config/obj-coff.c:693
 #, c-format
 msgid "unexpected storage class %d"
 msgstr ""
 
-#: config/obj-coff.c:790
+#: config/obj-coff.c:802
 msgid ".dim pseudo-op used outside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:810
+#: config/obj-coff.c:822
 msgid "badly formed .dim directive ignored"
 msgstr ""
 
-#: config/obj-coff.c:859
+#: config/obj-coff.c:871
 msgid ".size pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:874
+#: config/obj-coff.c:886
 msgid ".scl pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:891
+#: config/obj-coff.c:903
 msgid ".tag pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:909
+#: config/obj-coff.c:921
 #, c-format
 msgid "tag not found for .tag %s"
 msgstr ""
 
-#: config/obj-coff.c:922
+#: config/obj-coff.c:934
 msgid ".type pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:941
+#: config/obj-coff.c:953
 msgid ".val pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1108
+#: config/obj-coff.c:1120
 msgid "badly formed .weak directive ignored"
 msgstr ""
 
-#: config/obj-coff.c:1286
+#: config/obj-coff.c:1298
 msgid "mismatched .eb"
 msgstr ""
 
-#: config/obj-coff.c:1307
+#: config/obj-coff.c:1319
 #, c-format
 msgid "C_EFCN symbol for %s out of scope"
 msgstr ""
@@ -596,28 +601,28 @@ msgstr ""
 #. STYP_INFO
 #. STYP_LIB
 #. STYP_OVER
-#: config/obj-coff.c:1533
+#: config/obj-coff.c:1591
 #, c-format
 msgid "unsupported section attribute '%c'"
 msgstr ""
 
-#: config/obj-coff.c:1538 config/tc-ppc.c:4610
+#: config/obj-coff.c:1595 config/tc-ppc.c:4617
 #, c-format
 msgid "unknown section attribute '%c'"
 msgstr ""
 
-#: config/obj-coff.c:1568 config/tc-ppc.c:4628 config/tc-tic54x.c:4287
-#: read.c:2551
+#: config/obj-coff.c:1623 config/tc-ppc.c:4635 config/tc-tic54x.c:4285
+#: read.c:2750
 #, c-format
 msgid "error setting flags for \"%s\": %s"
 msgstr ""
 
-#: config/obj-coff.c:1579
+#: config/obj-coff.c:1634
 #, c-format
 msgid "Ignoring changed section attributes for %s"
 msgstr ""
 
-#: config/obj-coff.c:1710
+#: config/obj-coff.c:1765
 #, c-format
 msgid "0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n"
 msgstr ""
@@ -630,192 +635,173 @@ msgstr ""
 msgid "Can't set register masks"
 msgstr ""
 
-#: config/obj-elf.c:318 config/tc-sparc.c:3973 config/tc-v850.c:451
+#: config/obj-elf.c:322 config/tc-sparc.c:4053 config/tc-v850.c:450
 #, c-format
 msgid "bad .common segment %s"
 msgstr ""
 
-#: config/obj-elf.c:596
+#: config/obj-elf.c:600
 #, c-format
 msgid "setting incorrect section type for %s"
 msgstr ""
 
-#: config/obj-elf.c:601
+#: config/obj-elf.c:605
 #, c-format
 msgid "ignoring incorrect section type for %s"
 msgstr ""
 
-#: config/obj-elf.c:638
+#: config/obj-elf.c:647
 #, c-format
 msgid "setting incorrect section attributes for %s"
 msgstr ""
 
-#: config/obj-elf.c:690
+#: config/obj-elf.c:699
 #, c-format
 msgid "ignoring changed section type for %s"
 msgstr ""
 
-#: config/obj-elf.c:702
+#: config/obj-elf.c:711
 #, c-format
 msgid "ignoring changed section attributes for %s"
 msgstr ""
 
-#: config/obj-elf.c:704
+#: config/obj-elf.c:713
 #, c-format
 msgid "ignoring changed section entity size for %s"
 msgstr ""
 
-#: config/obj-elf.c:757
+#: config/obj-elf.c:766
 msgid "unrecognized .section attribute: want a,w,x,M,S,G,T"
 msgstr ""
 
-#: config/obj-elf.c:794
+#: config/obj-elf.c:803
 msgid "unrecognized section attribute"
 msgstr ""
 
-#: config/obj-elf.c:822 read.c:2535
+#: config/obj-elf.c:831 read.c:2734
 msgid "unrecognized section type"
 msgstr ""
 
-#: config/obj-elf.c:852
+#: config/obj-elf.c:861
 msgid "missing name"
 msgstr ""
 
-#: config/obj-elf.c:963
+#: config/obj-elf.c:972
 msgid "invalid merge entity size"
 msgstr ""
 
-#: config/obj-elf.c:970
+#: config/obj-elf.c:979
 msgid "entity size for SHF_MERGE not specified"
 msgstr ""
 
-#: config/obj-elf.c:990
+#: config/obj-elf.c:999
 msgid "group name for SHF_GROUP not specified"
 msgstr ""
 
-#: config/obj-elf.c:1003
+#: config/obj-elf.c:1012
 msgid "character following name is not '#'"
 msgstr ""
 
-#: config/obj-elf.c:1118
+#: config/obj-elf.c:1127
 msgid ".previous without corresponding .section; ignored"
 msgstr ""
 
-#: config/obj-elf.c:1144
+#: config/obj-elf.c:1153
 msgid ".popsection without corresponding .pushsection; ignored"
 msgstr ""
 
-#: config/obj-elf.c:1196
+#: config/obj-elf.c:1205
 msgid "expected comma after name in .symver"
 msgstr ""
 
-#: config/obj-elf.c:1220
+#: config/obj-elf.c:1229
 #, c-format
 msgid "missing version name in `%s' for symbol `%s'"
 msgstr ""
 
-#: config/obj-elf.c:1231
+#: config/obj-elf.c:1240
 #, c-format
 msgid "multiple versions [`%s'|`%s'] for symbol `%s'"
 msgstr ""
 
-#: config/obj-elf.c:1461
+#: config/obj-elf.c:1470
 msgid "expected quoted string"
 msgstr ""
 
-#: config/obj-elf.c:1481
+#: config/obj-elf.c:1490
 #, c-format
 msgid "expected comma after name `%s' in .size directive"
 msgstr ""
 
-#: config/obj-elf.c:1490
+#: config/obj-elf.c:1499
 msgid "missing expression in .size directive"
 msgstr ""
 
-#: config/obj-elf.c:1577
+#: config/obj-elf.c:1586
 #, c-format
 msgid "unrecognized symbol type \"%s\""
 msgstr ""
 
-#: config/obj-elf.c:1745
+#: config/obj-elf.c:1754
 msgid ".size expression too complicated to fix up"
 msgstr ""
 
-#: config/obj-elf.c:1777
+#: config/obj-elf.c:1786
 #, c-format
 msgid ""
 "invalid attempt to declare external version name as default in symbol `%s'"
 msgstr ""
 
-#: config/obj-elf.c:1838 ecoff.c:3598
+#: config/obj-elf.c:1847 ecoff.c:3598
 #, c-format
 msgid "symbol `%s' can not be both weak and common"
 msgstr ""
 
-#: config/obj-elf.c:1945
+#: config/obj-elf.c:1954
 #, c-format
 msgid "assuming all members of group `%s' are COMDAT"
 msgstr ""
 
-#: config/obj-elf.c:1967
+#: config/obj-elf.c:1976
 #, c-format
 msgid "can't create group: %s"
 msgstr ""
 
-#: config/obj-elf.c:2076
+#: config/obj-elf.c:2086
 #, c-format
 msgid "failed to set up debugging information: %s"
 msgstr ""
 
-#: config/obj-elf.c:2096
+#: config/obj-elf.c:2106
 #, c-format
 msgid "can't start writing .mdebug section: %s"
 msgstr ""
 
-#: config/obj-elf.c:2104
+#: config/obj-elf.c:2114
 #, c-format
 msgid "could not write .mdebug section: %s"
 msgstr ""
 
-#: config/obj-elf.h:140
-#, c-format
-msgid "can't allocate ELF private section data: %s"
-msgstr ""
-
-#: config/obj-ieee.c:69
-#, c-format
-msgid "Out of step\n"
-msgstr ""
-
-#: config/obj-ieee.c:449
-msgid "too many sections"
-msgstr ""
-
-#: config/obj-ieee.c:511
-#, c-format
-msgid "FATAL: Can't create %s"
-msgstr ""
-
 #: config/obj-som.c:129
 msgid "Only one .version pseudo-op per file!"
 msgstr ""
 
-#: config/obj-som.c:146 config/obj-som.c:191
+#: config/obj-som.c:146 config/obj-som.c:188
 msgid "Expected quoted string"
 msgstr ""
 
-#: config/obj-som.c:155
+#: config/obj-som.c:153
 #, c-format
-msgid "FATAL: Attaching version header %s"
+msgid "attaching version header %s: %s"
 msgstr ""
 
-#: config/obj-som.c:174
+#: config/obj-som.c:171
 msgid "Only one .copyright pseudo-op per file!"
 msgstr ""
 
-#: config/obj-som.c:200
+#: config/obj-som.c:195
 #, c-format
-msgid "FATAL: Attaching copyright header %s"
+msgid "attaching copyright header %s: %s"
 msgstr ""
 
 #: config/tc-alpha.c:592
@@ -887,8 +873,8 @@ msgstr ""
 msgid "opcode `%s' not supported for target %s"
 msgstr ""
 
-#: config/tc-alpha.c:1129 config/tc-alpha.c:3145 config/tc-avr.c:1221
-#: config/tc-msp430.c:1870
+#: config/tc-alpha.c:1129 config/tc-alpha.c:3145 config/tc-avr.c:1321
+#: config/tc-msp430.c:1868
 #, c-format
 msgid "unknown opcode `%s'"
 msgstr ""
@@ -968,17 +954,17 @@ msgstr ""
 msgid "sequence number in use for !tlsgd!%ld"
 msgstr ""
 
-#: config/tc-alpha.c:1823 config/tc-arc.c:294 config/tc-mn10200.c:889
-#: config/tc-mn10300.c:2600 config/tc-ppc.c:1476 config/tc-s390.c:614
-#: config/tc-v850.c:1573
+#: config/tc-alpha.c:1823 config/tc-arc.c:292 config/tc-mn10200.c:888
+#: config/tc-mn10300.c:2604 config/tc-ppc.c:1541 config/tc-s390.c:615
+#: config/tc-v850.c:1588
 msgid "operand"
 msgstr ""
 
-#: config/tc-alpha.c:1926 config/tc-alpha.c:1950 config/tc-d10v.c:585
-#: config/tc-d30v.c:573 config/tc-mn10200.c:1133 config/tc-mn10300.c:1893
-#: config/tc-ppc.c:2348 config/tc-ppc.c:2565 config/tc-ppc.c:2577
-#: config/tc-s390.c:1230 config/tc-s390.c:1330 config/tc-s390.c:1459
-#: config/tc-v850.c:1747 config/tc-v850.c:1770 config/tc-v850.c:1973
+#: config/tc-alpha.c:1926 config/tc-alpha.c:1950 config/tc-d10v.c:584
+#: config/tc-d30v.c:572 config/tc-mn10200.c:1132 config/tc-mn10300.c:1892
+#: config/tc-ppc.c:2402 config/tc-ppc.c:2619 config/tc-ppc.c:2631
+#: config/tc-s390.c:1231 config/tc-s390.c:1331 config/tc-s390.c:1460
+#: config/tc-v850.c:1762 config/tc-v850.c:1785 config/tc-v850.c:1988
 msgid "too many fixups"
 msgstr ""
 
@@ -994,17 +980,17 @@ msgstr ""
 msgid "can not resolve expression"
 msgstr ""
 
-#: config/tc-alpha.c:3275 config/tc-ppc.c:1781 config/tc-ppc.c:4373
+#: config/tc-alpha.c:3275 config/tc-ppc.c:1840 config/tc-ppc.c:4380
 #, c-format
 msgid ".COMMon length (%ld.) <0! Ignored."
 msgstr ""
 
-#: config/tc-alpha.c:3304 config/tc-sparc.c:3843 config/tc-v850.c:246
+#: config/tc-alpha.c:3304 config/tc-sparc.c:3923 config/tc-v850.c:245
 msgid "Ignoring attempt to re-define symbol"
 msgstr ""
 
-#: config/tc-alpha.c:3313 config/tc-alpha.c:3322 config/tc-ppc.c:4410
-#: config/tc-sparc.c:3851
+#: config/tc-alpha.c:3313 config/tc-alpha.c:3322 config/tc-ppc.c:4417
+#: config/tc-sparc.c:3931
 #, c-format
 msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
@@ -1033,7 +1019,7 @@ msgstr ""
 msgid ".fmask outside of .ent"
 msgstr ""
 
-#: config/tc-alpha.c:3547 ecoff.c:3204
+#: config/tc-alpha.c:3547 config/tc-score.c:5886 ecoff.c:3204
 msgid ".mask outside of .ent"
 msgstr ""
 
@@ -1045,7 +1031,8 @@ msgstr ""
 msgid "bad .mask directive"
 msgstr ""
 
-#: config/tc-alpha.c:3590 config/tc-mips.c:14022 ecoff.c:3168
+#: config/tc-alpha.c:3590 config/tc-mips.c:14589 config/tc-score.c:6029
+#: ecoff.c:3168
 msgid ".frame outside of .ent"
 msgstr ""
 
@@ -1134,7 +1121,7 @@ msgstr ""
 msgid "No symbol after .code_address"
 msgstr ""
 
-#: config/tc-alpha.c:4226
+#: config/tc-alpha.c:4226 config/tc-score.c:5892
 msgid "Bad .mask directive"
 msgstr ""
 
@@ -1168,7 +1155,7 @@ msgstr ""
 msgid "Alignment too large: %d. assumed"
 msgstr ""
 
-#: config/tc-alpha.c:4497 config/tc-d30v.c:2083
+#: config/tc-alpha.c:4497 config/tc-d30v.c:2082
 msgid "Alignment negative: 0 assumed"
 msgstr ""
 
@@ -1191,15 +1178,16 @@ msgstr ""
 msgid "internal error: can't hash macro `%s': %s"
 msgstr ""
 
-#: config/tc-alpha.c:4998 config/tc-i960.c:710 config/tc-xtensa.c:5112
-#: config/tc-xtensa.c:5181 config/tc-xtensa.c:5227
+#: config/tc-alpha.c:4998 config/tc-arm.c:6012 config/tc-arm.c:6024
+#: config/tc-i960.c:708 config/tc-xtensa.c:5161 config/tc-xtensa.c:5239
+#: config/tc-xtensa.c:5285 config/tc-z80.c:1893
 msgid "syntax error"
 msgstr ""
 
-#: config/tc-alpha.c:5067 config/tc-h8300.c:2055 config/tc-hppa.c:4041
-#: config/tc-i860.c:1059 config/tc-m68hc11.c:558 config/tc-m68k.c:4524
-#: config/tc-ns32k.c:1945 config/tc-or32.c:579 config/tc-sparc.c:2944
-#: config/tc-z8k.c:1310
+#: config/tc-alpha.c:5067 config/tc-h8300.c:2053 config/tc-hppa.c:1381
+#: config/tc-i860.c:1057 config/tc-m68hc11.c:560 config/tc-m68k.c:4654
+#: config/tc-ns32k.c:1943 config/tc-or32.c:580 config/tc-sparc.c:2998
+#: config/tc-spu.c:748 config/tc-z8k.c:1332
 msgid "Bad call to MD_ATOF()"
 msgstr ""
 
@@ -1241,7 +1229,7 @@ msgstr ""
 msgid "type %d reloc done?\n"
 msgstr ""
 
-#: config/tc-alpha.c:5420 config/tc-alpha.c:5427 config/tc-mips.c:8657
+#: config/tc-alpha.c:5420 config/tc-alpha.c:5427
 msgid "Used $at without \".set noat\""
 msgstr ""
 
@@ -1250,12 +1238,12 @@ msgstr ""
 msgid "!samegp reloc against symbol without .prologue: %s"
 msgstr ""
 
-#: config/tc-alpha.c:5626 config/tc-xtensa.c:5739
+#: config/tc-alpha.c:5626 config/tc-xtensa.c:5795
 #, c-format
 msgid "cannot represent `%s' relocation in object file"
 msgstr ""
 
-#: config/tc-alpha.c:5632 config/tc-xtensa.c:5747
+#: config/tc-alpha.c:5632 config/tc-xtensa.c:5803
 #, c-format
 msgid "internal error? cannot generate `%s' relocation"
 msgstr ""
@@ -1265,555 +1253,722 @@ msgstr ""
 msgid "frame reg expected, using $%d."
 msgstr ""
 
-#: config/tc-arc.c:1077 config/tc-ip2k.c:249
+#: config/tc-arc.c:1076 config/tc-ip2k.c:248
 msgid "md_estimate_size_before_relax\n"
 msgstr ""
 
-#: config/tc-arc.c:1088
+#: config/tc-arc.c:1087
 msgid "md_convert_frag\n"
 msgstr ""
 
 #. We can't actually support subtracting a symbol.
-#: config/tc-arc.c:1288 config/tc-arm.c:1021 config/tc-arm.c:5764
-#: config/tc-arm.c:5815 config/tc-arm.c:6614 config/tc-arm.c:7256
-#: config/tc-arm.c:7284 config/tc-arm.c:7536 config/tc-arm.c:7553
-#: config/tc-arm.c:7674 config/tc-avr.c:970 config/tc-cris.c:3928
-#: config/tc-d10v.c:1539 config/tc-d30v.c:1938 config/tc-mips.c:3794
-#: config/tc-mips.c:4902 config/tc-mips.c:5834 config/tc-mips.c:6428
-#: config/tc-msp430.c:1979 config/tc-ppc.c:5562 config/tc-v850.c:2274
-#: config/tc-xstormy16.c:484
+#: config/tc-arc.c:1287 config/tc-arm.c:1522 config/tc-arm.c:8104
+#: config/tc-arm.c:8155 config/tc-arm.c:8388 config/tc-arm.c:9111
+#: config/tc-arm.c:9915 config/tc-arm.c:9943 config/tc-arm.c:10200
+#: config/tc-arm.c:10217 config/tc-arm.c:10339 config/tc-avr.c:1052
+#: config/tc-cris.c:3984 config/tc-d10v.c:1536 config/tc-d30v.c:1937
+#: config/tc-mips.c:4176 config/tc-mips.c:5300 config/tc-mips.c:6239
+#: config/tc-mips.c:6831 config/tc-msp430.c:1976 config/tc-ppc.c:5585
+#: config/tc-spu.c:961 config/tc-spu.c:985 config/tc-v850.c:2303
+#: config/tc-xstormy16.c:484 config/tc-xtensa.c:5597 config/tc-xtensa.c:11559
 msgid "expression too complex"
 msgstr ""
 
-#: config/tc-arm.c:352
+#: config/tc-arm.c:483
 msgid "ARM register expected"
 msgstr ""
 
-#: config/tc-arm.c:353
+#: config/tc-arm.c:484
 msgid "bad or missing co-processor number"
 msgstr ""
 
-#: config/tc-arm.c:354
+#: config/tc-arm.c:485
 msgid "co-processor register expected"
 msgstr ""
 
-#: config/tc-arm.c:355
+#: config/tc-arm.c:486
 msgid "FPA register expected"
 msgstr ""
 
-#: config/tc-arm.c:356
+#: config/tc-arm.c:487
 msgid "VFP single precision register expected"
 msgstr ""
 
-#: config/tc-arm.c:357
-msgid "VFP double precision register expected"
+#: config/tc-arm.c:488
+msgid "VFP/Neon double precision register expected"
+msgstr ""
+
+#: config/tc-arm.c:489
+msgid "Neon quad precision register expected"
+msgstr ""
+
+#: config/tc-arm.c:490
+msgid "VFP single or double precision register expected"
+msgstr ""
+
+#: config/tc-arm.c:491
+msgid "Neon double or quad precision register expected"
 msgstr ""
 
-#: config/tc-arm.c:358
+#: config/tc-arm.c:492
+msgid "VFP single, double or Neon quad precision register expected"
+msgstr ""
+
+#: config/tc-arm.c:493
 msgid "VFP system register expected"
 msgstr ""
 
-#: config/tc-arm.c:359
+#: config/tc-arm.c:494
 msgid "Maverick MVF register expected"
 msgstr ""
 
-#: config/tc-arm.c:360
+#: config/tc-arm.c:495
 msgid "Maverick MVD register expected"
 msgstr ""
 
-#: config/tc-arm.c:361
+#: config/tc-arm.c:496
 msgid "Maverick MVFX register expected"
 msgstr ""
 
-#: config/tc-arm.c:362
+#: config/tc-arm.c:497
 msgid "Maverick MVDX register expected"
 msgstr ""
 
-#: config/tc-arm.c:363
+#: config/tc-arm.c:498
 msgid "Maverick MVAX register expected"
 msgstr ""
 
-#: config/tc-arm.c:364
+#: config/tc-arm.c:499
 msgid "Maverick DSPSC register expected"
 msgstr ""
 
-#: config/tc-arm.c:365
+#: config/tc-arm.c:500
 msgid "iWMMXt data register expected"
 msgstr ""
 
-#: config/tc-arm.c:366
+#: config/tc-arm.c:501 config/tc-arm.c:5821
 msgid "iWMMXt control register expected"
 msgstr ""
 
-#: config/tc-arm.c:367
+#: config/tc-arm.c:502
 msgid "iWMMXt scalar register expected"
 msgstr ""
 
-#: config/tc-arm.c:368
+#: config/tc-arm.c:503
 msgid "XScale accumulator register expected"
 msgstr ""
 
-#: config/tc-arm.c:499
+#. For score5u : div/mul will pop warning message, mmu/alw/asw will pop error message.
+#: config/tc-arm.c:652 config/tc-score.c:47
 msgid "bad arguments to instruction"
 msgstr ""
 
-#: config/tc-arm.c:500
+#: config/tc-arm.c:653 config/tc-score.c:48
 msgid "r15 not allowed here"
 msgstr ""
 
-#: config/tc-arm.c:501
+#: config/tc-arm.c:654
 msgid "instruction cannot be conditional"
 msgstr ""
 
-#: config/tc-arm.c:502
+#: config/tc-arm.c:655
 msgid "registers may not be the same"
 msgstr ""
 
-#: config/tc-arm.c:503
+#: config/tc-arm.c:656
 msgid "lo register required"
 msgstr ""
 
-#: config/tc-arm.c:504
+#: config/tc-arm.c:657
 msgid "instruction not supported in Thumb16 mode"
 msgstr ""
 
-#: config/tc-arm.c:640
+#: config/tc-arm.c:658
+msgid "instruction does not accept this addressing mode"
+msgstr ""
+
+#: config/tc-arm.c:659
+msgid "branch must be last instruction in IT block"
+msgstr ""
+
+#: config/tc-arm.c:660
+msgid "instruction not allowed in IT block"
+msgstr ""
+
+#: config/tc-arm.c:661
+msgid "selected FPU does not support instruction"
+msgstr ""
+
+#: config/tc-arm.c:803
 msgid "immediate expression requires a # prefix"
 msgstr ""
 
-#: config/tc-arm.c:666 expr.c:1302 read.c:2228
+#: config/tc-arm.c:830 config/tc-score.c:5675 expr.c:1298 read.c:2435
 msgid "bad expression"
 msgstr ""
 
-#: config/tc-arm.c:677 config/tc-i860.c:1005 config/tc-sparc.c:2844
+#: config/tc-arm.c:841 config/tc-i860.c:1003 config/tc-sparc.c:2898
 msgid "bad segment"
 msgstr ""
 
-#: config/tc-arm.c:693 config/tc-arm.c:3230 config/tc-i960.c:1302
+#: config/tc-arm.c:858 config/tc-arm.c:4346 config/tc-i960.c:1300
+#: config/tc-score.c:985
 msgid "invalid constant"
 msgstr ""
 
-#: config/tc-arm.c:754
+#: config/tc-arm.c:919 config/tc-score.c:4749
 msgid "bad call to MD_ATOF()"
 msgstr ""
 
-#: config/tc-arm.c:821
+#: config/tc-arm.c:986
 msgid "expected #constant"
 msgstr ""
 
-#: config/tc-arm.c:953
+#: config/tc-arm.c:1147
+#, c-format
+msgid "unexpected character `%c' in type specifier"
+msgstr ""
+
+#: config/tc-arm.c:1164
+#, c-format
+msgid "bad size %d in type specifier"
+msgstr ""
+
+#: config/tc-arm.c:1214
+msgid "only one type should be specified for operand"
+msgstr ""
+
+#: config/tc-arm.c:1220
+msgid "vector type expected"
+msgstr ""
+
+#: config/tc-arm.c:1292
+msgid "can't redefine type for operand"
+msgstr ""
+
+#: config/tc-arm.c:1303
+msgid "only D registers may be indexed"
+msgstr ""
+
+#: config/tc-arm.c:1309
+msgid "can't change index for operand"
+msgstr ""
+
+#: config/tc-arm.c:1325 config/tc-arm.c:3947
+msgid "constant expression required"
+msgstr ""
+
+#: config/tc-arm.c:1369
+msgid "register operand expected, but got scalar"
+msgstr ""
+
+#: config/tc-arm.c:1402
+msgid "scalar must have an index"
+msgstr ""
+
+#: config/tc-arm.c:1407 config/tc-arm.c:13097 config/tc-arm.c:13145
+#: config/tc-arm.c:13547
+msgid "scalar index out of range"
+msgstr ""
+
+#: config/tc-arm.c:1454
 msgid "bad range in register list"
 msgstr ""
 
-#: config/tc-arm.c:961 config/tc-arm.c:970 config/tc-arm.c:1011
+#: config/tc-arm.c:1462 config/tc-arm.c:1471 config/tc-arm.c:1512
 #, c-format
 msgid "Warning: duplicated register (r%d) in register list"
 msgstr ""
 
-#: config/tc-arm.c:973
+#: config/tc-arm.c:1474
 msgid "Warning: register range not in ascending order"
 msgstr ""
 
-#: config/tc-arm.c:984
+#: config/tc-arm.c:1485
 msgid "missing `}'"
 msgstr ""
 
-#: config/tc-arm.c:1000
+#: config/tc-arm.c:1501
 msgid "invalid register mask"
 msgstr ""
 
-#: config/tc-arm.c:1091 config/tc-arm.c:1126 config/tc-h8300.c:991
-#: config/tc-mips.c:9797 config/tc-mips.c:9827
+#: config/tc-arm.c:1583
+msgid "expecting {"
+msgstr ""
+
+#: config/tc-arm.c:1638 config/tc-arm.c:1682
+msgid "register out of range in list"
+msgstr ""
+
+#: config/tc-arm.c:1654 config/tc-arm.c:1699 config/tc-h8300.c:989
+#: config/tc-mips.c:10168 config/tc-mips.c:10190
 msgid "invalid register list"
 msgstr ""
 
-#: config/tc-arm.c:1097 config/tc-arm.c:2402 config/tc-arm.c:2535
+#: config/tc-arm.c:1660 config/tc-arm.c:3412 config/tc-arm.c:3545
 msgid "register list not in ascending order"
 msgstr ""
 
-#: config/tc-arm.c:1118
+#: config/tc-arm.c:1691
 msgid "register range not in ascending order"
 msgstr ""
 
-#: config/tc-arm.c:1151
+#: config/tc-arm.c:1724
 msgid "non-contiguous register range"
 msgstr ""
 
-#: config/tc-arm.c:1199
+#: config/tc-arm.c:1850
+msgid "don't use Rn-Rm syntax with non-unit stride"
+msgstr ""
+
+#: config/tc-arm.c:1905
+msgid "error parsing element/structure list"
+msgstr ""
+
+#: config/tc-arm.c:1911
+msgid "expected }"
+msgstr ""
+
+#: config/tc-arm.c:1967
 #, c-format
 msgid "ignoring attempt to redefine built-in register '%s'"
 msgstr ""
 
-#: config/tc-arm.c:1204
+#: config/tc-arm.c:1972
 #, c-format
 msgid "ignoring redefinition of register alias '%s'"
 msgstr ""
 
-#: config/tc-arm.c:1248
+#: config/tc-arm.c:2000
+msgid "attempt to redefine typed alias"
+msgstr ""
+
+#: config/tc-arm.c:2038
 #, c-format
 msgid "unknown register '%s' -- .req ignored"
 msgstr ""
 
-#: config/tc-arm.c:1291
+#: config/tc-arm.c:2121
+msgid "bad type for register"
+msgstr ""
+
+#: config/tc-arm.c:2132
+msgid "expression must be constant"
+msgstr ""
+
+#: config/tc-arm.c:2149
+msgid "can't redefine the type of a register alias"
+msgstr ""
+
+#: config/tc-arm.c:2156
+msgid "you must specify a single type only"
+msgstr ""
+
+#: config/tc-arm.c:2169
+msgid "can't redefine the index of a scalar alias"
+msgstr ""
+
+#: config/tc-arm.c:2177
+msgid "scalar index must be constant"
+msgstr ""
+
+#: config/tc-arm.c:2186
+msgid "expecting ]"
+msgstr ""
+
+#: config/tc-arm.c:2223
 msgid "invalid syntax for .req directive"
 msgstr ""
 
-#: config/tc-arm.c:1317
+#: config/tc-arm.c:2229
+msgid "invalid syntax for .dn directive"
+msgstr ""
+
+#: config/tc-arm.c:2235
+msgid "invalid syntax for .qn directive"
+msgstr ""
+
+#: config/tc-arm.c:2261
 msgid "invalid syntax for .unreq directive"
 msgstr ""
 
-#: config/tc-arm.c:1323
+#: config/tc-arm.c:2267
 #, c-format
 msgid "unknown register alias '%s'"
 msgstr ""
 
-#: config/tc-arm.c:1325
+#: config/tc-arm.c:2269
 #, c-format
 msgid "ignoring attempt to undefine built-in register '%s'"
 msgstr ""
 
-#: config/tc-arm.c:1456
+#: config/tc-arm.c:2402
 msgid "selected processor does not support THUMB opcodes"
 msgstr ""
 
-#: config/tc-arm.c:1470
+#: config/tc-arm.c:2416
 msgid "selected processor does not support ARM opcodes"
 msgstr ""
 
-#: config/tc-arm.c:1483
+#: config/tc-arm.c:2429
 #, c-format
 msgid "invalid instruction size selected (%d)"
 msgstr ""
 
-#: config/tc-arm.c:1515
+#: config/tc-arm.c:2461
 #, c-format
 msgid "invalid operand to .code directive (%d) (expecting 16 or 32)"
 msgstr ""
 
-#: config/tc-arm.c:1571
+#: config/tc-arm.c:2517
 #, c-format
 msgid "expected comma after name \"%s\""
 msgstr ""
 
-#: config/tc-arm.c:1621 config/tc-m32r.c:589
+#: config/tc-arm.c:2567 config/tc-m32r.c:588
 #, c-format
 msgid "symbol `%s' already defined"
 msgstr ""
 
-#: config/tc-arm.c:1655
+#: config/tc-arm.c:2601
 #, c-format
 msgid "unrecognized syntax mode \"%s\""
 msgstr ""
 
-#: config/tc-arm.c:1675
+#: config/tc-arm.c:2622
 #, c-format
 msgid "alignment too large: %d assumed"
 msgstr ""
 
-#: config/tc-arm.c:1678
+#: config/tc-arm.c:2625
 msgid "alignment negative. 0 assumed."
 msgstr ""
 
-#: config/tc-arm.c:1816
+#: config/tc-arm.c:2772
 msgid "literal pool overflow"
 msgstr ""
 
-#: config/tc-arm.c:1972 config/tc-arm.c:3888
+#: config/tc-arm.c:2928 config/tc-arm.c:5756
 msgid "unrecognized relocation suffix"
 msgstr ""
 
-#: config/tc-arm.c:1985
+#: config/tc-arm.c:2941
 msgid "(plt) is only valid on branch targets"
 msgstr ""
 
-#: config/tc-arm.c:1991 config/tc-s390.c:1128 config/tc-s390.c:1742
-#: config/tc-xtensa.c:1601
+#: config/tc-arm.c:2947 config/tc-s390.c:1129 config/tc-s390.c:1743
+#: config/tc-xtensa.c:1545
 #, c-format
 msgid "%s relocations do not fit in %d bytes"
 msgstr ""
 
-#: config/tc-arm.c:2039 dwarf2dbg.c:659
+#: config/tc-arm.c:2995 dwarf2dbg.c:689
 msgid "expected 0 or 1"
 msgstr ""
 
-#: config/tc-arm.c:2043
+#: config/tc-arm.c:2999
 msgid "missing comma"
 msgstr ""
 
-#: config/tc-arm.c:2098
+#: config/tc-arm.c:3054
 msgid "dupicate .handlerdata directive"
 msgstr ""
 
-#: config/tc-arm.c:2169
+#: config/tc-arm.c:3125
 msgid "personality routine specified for cantunwind frame"
 msgstr ""
 
-#: config/tc-arm.c:2183
+#: config/tc-arm.c:3139
 msgid "duplicate .personalityindex directive"
 msgstr ""
 
-#: config/tc-arm.c:2190
+#: config/tc-arm.c:3146
 msgid "bad personality routine number"
 msgstr ""
 
-#: config/tc-arm.c:2209
+#: config/tc-arm.c:3165
 msgid "duplicate .personality directive"
 msgstr ""
 
-#: config/tc-arm.c:2232 config/tc-arm.c:2354
+#: config/tc-arm.c:3188 config/tc-arm.c:3316 config/tc-arm.c:3364
 msgid "expected register list"
 msgstr ""
 
-#: config/tc-arm.c:2310
+#: config/tc-arm.c:3270
 msgid "expected , <constant>"
 msgstr ""
 
-#: config/tc-arm.c:2319
+#: config/tc-arm.c:3279
 msgid "number of registers must be in the range [1:4]"
 msgstr ""
 
-#: config/tc-arm.c:2416 config/tc-arm.c:2549
+#: config/tc-arm.c:3426 config/tc-arm.c:3559
 msgid "bad register range"
 msgstr ""
 
-#: config/tc-arm.c:2602
+#: config/tc-arm.c:3613
 msgid "register expected"
 msgstr ""
 
-#: config/tc-arm.c:2612
+#: config/tc-arm.c:3623
 msgid "FPA .unwind_save does not take a register list"
 msgstr ""
 
-#: config/tc-arm.c:2625
+#: config/tc-arm.c:3641
 msgid ".unwind_save does not support this kind of register"
 msgstr ""
 
-#: config/tc-arm.c:2650
+#: config/tc-arm.c:3677
 msgid "SP and PC not permitted in .unwind_movsp directive"
 msgstr ""
 
-#: config/tc-arm.c:2655
+#: config/tc-arm.c:3682
 msgid "unexpected .unwind_movsp directive"
 msgstr ""
 
-#: config/tc-arm.c:2679
+#: config/tc-arm.c:3706
 msgid "stack increment must be multiple of 4"
 msgstr ""
 
-#: config/tc-arm.c:2708
+#: config/tc-arm.c:3735
 msgid "expected <reg>, <reg>"
 msgstr ""
 
-#: config/tc-arm.c:2726
+#: config/tc-arm.c:3753
 msgid "register must be either sp or set by a previousunwind_movsp directive"
 msgstr ""
 
-#: config/tc-arm.c:2762
+#: config/tc-arm.c:3789
 msgid "expected <offset>, <opcode>"
 msgstr ""
 
-#: config/tc-arm.c:2774
+#: config/tc-arm.c:3801
 msgid "unwind opcode too long"
 msgstr ""
 
-#: config/tc-arm.c:2779
+#: config/tc-arm.c:3806
 msgid "invalid unwind opcode"
 msgstr ""
 
-#: config/tc-arm.c:2829
-msgid "expected numeric constant"
-msgstr ""
-
-#: config/tc-arm.c:2838
-msgid "expected comma"
-msgstr ""
-
-#: config/tc-arm.c:2877
-msgid "bad string constant"
-msgstr ""
-
-#: config/tc-arm.c:2881
-msgid "expected <tag> , <value>"
-msgstr ""
-
-#: config/tc-arm.c:2957
-msgid "constant expression required"
-msgstr ""
-
-#: config/tc-arm.c:2963 config/tc-arm.c:6472 config/tc-arm.c:11799
-#: config/tc-arm.c:11824 config/tc-arm.c:11832 config/tc-z8k.c:1122
-#: config/tc-z8k.c:1132
+#: config/tc-arm.c:3953 config/tc-arm.c:4816 config/tc-arm.c:8391
+#: config/tc-arm.c:8873 config/tc-arm.c:11671 config/tc-arm.c:18619
+#: config/tc-arm.c:18644 config/tc-arm.c:18652 config/tc-z8k.c:1144
+#: config/tc-z8k.c:1154
 msgid "immediate value out of range"
 msgstr ""
 
-#: config/tc-arm.c:3058
+#: config/tc-arm.c:4100
 msgid "invalid FPA immediate expression"
 msgstr ""
 
-#: config/tc-arm.c:3108 config/tc-arm.c:3116
+#: config/tc-arm.c:4224 config/tc-arm.c:4232
 msgid "shift expression expected"
 msgstr ""
 
-#: config/tc-arm.c:3130
+#: config/tc-arm.c:4246
 msgid "'LSL' or 'ASR' required"
 msgstr ""
 
-#: config/tc-arm.c:3138
+#: config/tc-arm.c:4254
 msgid "'LSL' required"
 msgstr ""
 
-#: config/tc-arm.c:3146
+#: config/tc-arm.c:4262
 msgid "'ASR' required"
 msgstr ""
 
-#: config/tc-arm.c:3218 config/tc-arm.c:4349 config/tc-v850.c:1844
-#: config/tc-v850.c:1865
+#: config/tc-arm.c:4334 config/tc-arm.c:4810 config/tc-arm.c:6382
+#: config/tc-v850.c:1859 config/tc-v850.c:1880
 msgid "constant expression expected"
 msgstr ""
 
-#: config/tc-arm.c:3225
+#: config/tc-arm.c:4341
 msgid "invalid rotation"
 msgstr ""
 
-#: config/tc-arm.c:3340 config/tc-arm.c:3640
+#: config/tc-arm.c:4501 config/tc-arm.c:4646
+msgid "unknown group relocation"
+msgstr ""
+
+#: config/tc-arm.c:4614
+msgid "alignment must be constant"
+msgstr ""
+
+#: config/tc-arm.c:4677
+msgid "this group relocation is not allowed on this instruction"
+msgstr ""
+
+#: config/tc-arm.c:4689 config/tc-arm.c:5080
 msgid "']' expected"
 msgstr ""
 
-#: config/tc-arm.c:3358
+#: config/tc-arm.c:4707
 msgid "'}' expected at end of 'option' field"
 msgstr ""
 
-#: config/tc-arm.c:3363
+#: config/tc-arm.c:4712
 msgid "cannot combine index with option"
 msgstr ""
 
-#: config/tc-arm.c:3376
+#: config/tc-arm.c:4725
 msgid "cannot combine pre- and post-indexing"
 msgstr ""
 
-#: config/tc-arm.c:3472
+#: config/tc-arm.c:4886
 msgid "flag for {c}psr instruction expected"
 msgstr ""
 
-#: config/tc-arm.c:3497
+#: config/tc-arm.c:4911
 msgid "unrecognized CPS flag"
 msgstr ""
 
-#: config/tc-arm.c:3504
+#: config/tc-arm.c:4918
 msgid "missing CPS flags"
 msgstr ""
 
-#: config/tc-arm.c:3527 config/tc-arm.c:3533
+#: config/tc-arm.c:4941 config/tc-arm.c:4947
 msgid "valid endian specifiers are be or le"
 msgstr ""
 
-#: config/tc-arm.c:3555
+#: config/tc-arm.c:4969
 msgid "missing rotation field after comma"
 msgstr ""
 
-#: config/tc-arm.c:3570
+#: config/tc-arm.c:4984
 msgid "rotation can only be 0, 8, 16, or 24"
 msgstr ""
 
-#: config/tc-arm.c:3590
+#: config/tc-arm.c:5004
 msgid "condition required"
 msgstr ""
 
-#: config/tc-arm.c:3632
+#: config/tc-arm.c:5042 config/tc-arm.c:6877
+msgid "'[' expected"
+msgstr ""
+
+#: config/tc-arm.c:5055
+msgid "',' expected"
+msgstr ""
+
+#: config/tc-arm.c:5072
 msgid "invalid shift"
 msgstr ""
 
-#: config/tc-arm.c:3929
+#: config/tc-arm.c:5145
+msgid "can't use Neon quad register here"
+msgstr ""
+
+#: config/tc-arm.c:5211
+msgid "expected <Rm> or <Dm> or <Qm> operand"
+msgstr ""
+
+#: config/tc-arm.c:5291
+msgid "parse error"
+msgstr ""
+
+#: config/tc-arm.c:5301 read.c:2092
+msgid "expected comma"
+msgstr ""
+
+#: config/tc-arm.c:5591 config/tc-arm.c:5661
+msgid "immediate value is out of range"
+msgstr ""
+
+#: config/tc-arm.c:5806
 msgid "iWMMXt data or control register expected"
 msgstr ""
 
-#: config/tc-arm.c:4051
+#: config/tc-arm.c:6038 config/tc-score.c:56
 msgid "garbage following instruction"
 msgstr ""
 
-#: config/tc-arm.c:4185
+#: config/tc-arm.c:6125
+msgid "D register out of range for selected VFP version"
+msgstr ""
+
+#: config/tc-arm.c:6204
 msgid "instruction does not accept preindexed addressing"
 msgstr ""
 
 #. unindexed - only for coprocessor
-#: config/tc-arm.c:4201 config/tc-arm.c:5857
+#: config/tc-arm.c:6220 config/tc-arm.c:8197
 msgid "instruction does not accept unindexed addressing"
 msgstr ""
 
-#: config/tc-arm.c:4209
+#: config/tc-arm.c:6228
 msgid "destination register same as write-back base"
 msgstr ""
 
-#: config/tc-arm.c:4210
+#: config/tc-arm.c:6229
 msgid "source register same as write-back base"
 msgstr ""
 
-#: config/tc-arm.c:4256
+#: config/tc-arm.c:6275
 msgid "instruction does not accept scaled register index"
 msgstr ""
 
-#: config/tc-arm.c:4295
+#: config/tc-arm.c:6315
 msgid "instruction does not support unindexed addressing"
 msgstr ""
 
-#: config/tc-arm.c:4310
+#: config/tc-arm.c:6330
 msgid "pc may not be used with write-back"
 msgstr ""
 
-#: config/tc-arm.c:4315
+#: config/tc-arm.c:6335
 msgid "instruction does not support writeback"
 msgstr ""
 
-#: config/tc-arm.c:4344
+#: config/tc-arm.c:6377
 msgid "invalid pseudo operation"
 msgstr ""
 
-#: config/tc-arm.c:4390
+#: config/tc-arm.c:6423
 msgid "literal pool insertion failed"
 msgstr ""
 
-#: config/tc-arm.c:4448
+#: config/tc-arm.c:6481
 msgid "Rn must not overlap other operands"
 msgstr ""
 
-#: config/tc-arm.c:4534 config/tc-arm.c:4553 config/tc-arm.c:4566
-#: config/tc-arm.c:6360 config/tc-arm.c:6380 config/tc-arm.c:6394
+#: config/tc-arm.c:6581 config/tc-arm.c:6600 config/tc-arm.c:6613
+#: config/tc-arm.c:8740 config/tc-arm.c:8760 config/tc-arm.c:8774
 msgid "bit-field extends past end of register"
 msgstr ""
 
-#: config/tc-arm.c:4595
+#: config/tc-arm.c:6642
 msgid "the only suffix valid here is '(plt)'"
 msgstr ""
 
-#: config/tc-arm.c:4627
+#: config/tc-arm.c:6695
 msgid "use of r15 in blx in ARM mode is not really useful"
 msgstr ""
 
-#: config/tc-arm.c:4645
+#: config/tc-arm.c:6718
 msgid "use of r15 in bx in ARM mode is not really useful"
 msgstr ""
 
-#: config/tc-arm.c:4657 config/tc-arm.c:6508
+#: config/tc-arm.c:6730 config/tc-arm.c:8912
 msgid "use of r15 in bxj is not really useful"
 msgstr ""
 
-#: config/tc-arm.c:4761 config/tc-arm.c:4770
+#: config/tc-arm.c:6844 config/tc-arm.c:6853
 msgid "writeback of base register is UNPREDICTABLE"
 msgstr ""
 
-#: config/tc-arm.c:4764
+#: config/tc-arm.c:6847
 msgid "writeback of base register when in register list is UNPREDICTABLE"
 msgstr ""
 
-#: config/tc-arm.c:4774
+#: config/tc-arm.c:6857
 msgid "if writeback register is in list, it must be the lowest reg in the list"
 msgstr ""
 
-#: config/tc-arm.c:4789
+#: config/tc-arm.c:6872
 msgid "first destination register must be even"
 msgstr ""
 
-#: config/tc-arm.c:4792 config/tc-arm.c:4849
+#: config/tc-arm.c:6875 config/tc-arm.c:6942
 msgid "can only load two consecutive registers"
 msgstr ""
 
@@ -1821,863 +1976,1052 @@ msgstr ""
 #. have been called in the first place.
 #. If op 2 were present and equal to PC, this function wouldn't
 #. have been called in the first place.
-#: config/tc-arm.c:4793 config/tc-arm.c:4852 config/tc-arm.c:5299
-#: config/tc-arm.c:6886
+#: config/tc-arm.c:6876 config/tc-arm.c:6945 config/tc-arm.c:7467
+#: config/tc-arm.c:9390
 msgid "r14 not allowed here"
 msgstr ""
 
-#: config/tc-arm.c:4794
-msgid "'[' expected"
-msgstr ""
-
-#: config/tc-arm.c:4807
+#: config/tc-arm.c:6890
 msgid "base register written back, and overlaps second destination register"
 msgstr ""
 
-#: config/tc-arm.c:4815
+#: config/tc-arm.c:6898
 msgid "index register overlaps destination register"
 msgstr ""
 
-#: config/tc-arm.c:4829 config/tc-arm.c:5272 config/tc-arm.c:6706
-#: config/tc-arm.c:7581
-msgid "instruction does not accept this addressing mode"
-msgstr ""
-
-#: config/tc-arm.c:4835 config/tc-arm.c:5281
+#: config/tc-arm.c:6928 config/tc-arm.c:7449
 msgid "offset must be zero in ARM encoding"
 msgstr ""
 
-#: config/tc-arm.c:4846 config/tc-arm.c:5293
+#: config/tc-arm.c:6939 config/tc-arm.c:7461
 msgid "even register required"
 msgstr ""
 
-#: config/tc-arm.c:4877 config/tc-arm.c:4908
+#: config/tc-arm.c:6970 config/tc-arm.c:7001
 msgid "this instruction requires a post-indexed address"
 msgstr ""
 
-#: config/tc-arm.c:4935
-msgid "rd and rm should be different in mla"
+#: config/tc-arm.c:7028
+msgid "Rd and Rm should be different in mla"
+msgstr ""
+
+#: config/tc-arm.c:7052 config/tc-arm.c:9648
+msgid ":lower16: not allowed this instruction"
+msgstr ""
+
+#: config/tc-arm.c:7054
+msgid ":upper16: not allowed instruction"
+msgstr ""
+
+#: config/tc-arm.c:7073
+msgid "operand 1 must be FPSCR"
 msgstr ""
 
-#: config/tc-arm.c:4967 config/tc-arm.c:7121
+#: config/tc-arm.c:7106 config/tc-arm.c:9757
 msgid "'CPSR' or 'SPSR' expected"
 msgstr ""
 
-#: config/tc-arm.c:5000
-msgid "rd and rm should be different in mul"
+#: config/tc-arm.c:7143
+msgid "Rd and Rm should be different in mul"
 msgstr ""
 
-#: config/tc-arm.c:5021
+#: config/tc-arm.c:7164
 msgid "rdhi, rdlo and rm must all be different"
 msgstr ""
 
-#: config/tc-arm.c:5083
+#: config/tc-arm.c:7226
 msgid "'[' expected after PLD mnemonic"
 msgstr ""
 
-#: config/tc-arm.c:5085
+#: config/tc-arm.c:7228 config/tc-arm.c:7243
 msgid "post-indexed expression used in preload instruction"
 msgstr ""
 
-#: config/tc-arm.c:5087
+#: config/tc-arm.c:7230 config/tc-arm.c:7245
 msgid "writeback used in preload instruction"
 msgstr ""
 
-#: config/tc-arm.c:5089
+#: config/tc-arm.c:7232 config/tc-arm.c:7247
 msgid "unindexed addressing used in preload instruction"
 msgstr ""
 
-#: config/tc-arm.c:5188 config/tc-arm.c:7492
-msgid "source1 and dest must be same register"
+#: config/tc-arm.c:7241
+msgid "'[' expected after PLI mnemonic"
 msgstr ""
 
-#: config/tc-arm.c:5238 config/tc-arm.c:7178
+#: config/tc-arm.c:7394 config/tc-arm.c:9837
 msgid "rdhi and rdlo must be different"
 msgstr ""
 
-#: config/tc-arm.c:5296
+#: config/tc-arm.c:7420
+msgid "SRS base register must be r13"
+msgstr ""
+
+#: config/tc-arm.c:7464
 msgid "can only store two consecutive registers"
 msgstr ""
 
-#: config/tc-arm.c:5391 config/tc-arm.c:5408
+#: config/tc-arm.c:7559 config/tc-arm.c:7576
 msgid "only two consecutive VFP SP registers allowed here"
 msgstr ""
 
-#: config/tc-arm.c:5436 config/tc-arm.c:5451
+#: config/tc-arm.c:7604 config/tc-arm.c:7619
 msgid "this addressing mode requires base-register writeback"
 msgstr ""
 
-#: config/tc-arm.c:5529
+#: config/tc-arm.c:7794
 msgid "this instruction does not support indexing"
 msgstr ""
 
-#: config/tc-arm.c:5552
+#: config/tc-arm.c:7818
 msgid "only r15 allowed here"
 msgstr ""
 
-#: config/tc-arm.c:5757
+#: config/tc-arm.c:7953
+msgid "immediate operand requires iWMMXt2"
+msgstr ""
+
+#: config/tc-arm.c:8097
 msgid "shift by register not allowed in thumb mode"
 msgstr ""
 
-#: config/tc-arm.c:5769 config/tc-arm.c:11339
+#: config/tc-arm.c:8109 config/tc-arm.c:18126
 msgid "shift expression is too large"
 msgstr ""
 
-#: config/tc-arm.c:5795
-msgid "Thumb does not support the ldr =N pseudo-operation"
+#: config/tc-arm.c:8135
+msgid "Instruction does not support =N addresses"
 msgstr ""
 
-#: config/tc-arm.c:5800
+#: config/tc-arm.c:8140
 msgid "cannot use register index with PC-relative addressing"
 msgstr ""
 
-#: config/tc-arm.c:5801
+#: config/tc-arm.c:8141
 msgid "cannot use register index with this instruction"
 msgstr ""
 
-#: config/tc-arm.c:5803
+#: config/tc-arm.c:8143
 msgid "Thumb does not support negative register indexing"
 msgstr ""
 
-#: config/tc-arm.c:5805
+#: config/tc-arm.c:8145
 msgid "Thumb does not support register post-indexing"
 msgstr ""
 
-#: config/tc-arm.c:5807
+#: config/tc-arm.c:8147
 msgid "Thumb does not support register indexing with writeback"
 msgstr ""
 
-#: config/tc-arm.c:5809
+#: config/tc-arm.c:8149
 msgid "Thumb supports only LSL in shifted register indexing"
 msgstr ""
 
-#: config/tc-arm.c:5818
+#: config/tc-arm.c:8158 config/tc-arm.c:12899
 msgid "shift out of range"
 msgstr ""
 
-#: config/tc-arm.c:5826
+#: config/tc-arm.c:8166
 msgid "cannot use writeback with PC-relative addressing"
 msgstr ""
 
-#: config/tc-arm.c:5828
+#: config/tc-arm.c:8168
 msgid "cannot use writeback with this instruction"
 msgstr ""
 
-#: config/tc-arm.c:5847
+#: config/tc-arm.c:8187
 msgid "cannot use post-indexing with PC-relative addressing"
 msgstr ""
 
-#: config/tc-arm.c:5848
+#: config/tc-arm.c:8188
 msgid "cannot use post-indexing with this instruction"
 msgstr ""
 
-#: config/tc-arm.c:5975
+#: config/tc-arm.c:8315
 msgid "PC not allowed as destination"
 msgstr ""
 
-#: config/tc-arm.c:6093 config/tc-arm.c:6234 config/tc-arm.c:6326
-#: config/tc-arm.c:7092
+#: config/tc-arm.c:8386
+msgid "only SUBS PC, LR, #const allowed"
+msgstr ""
+
+#: config/tc-arm.c:8459 config/tc-arm.c:8600 config/tc-arm.c:8692
+#: config/tc-arm.c:9712
 msgid "shift must be constant"
 msgstr ""
 
-#: config/tc-arm.c:6120 config/tc-arm.c:6249 config/tc-arm.c:6341
-#: config/tc-arm.c:7105
+#: config/tc-arm.c:8486 config/tc-arm.c:8615 config/tc-arm.c:8707
+#: config/tc-arm.c:9725
 msgid "unshifted register required"
 msgstr ""
 
-#: config/tc-arm.c:6135 config/tc-arm.c:6352 config/tc-arm.c:7165
+#: config/tc-arm.c:8501 config/tc-arm.c:8718 config/tc-arm.c:9824
 msgid "dest must overlap one source register"
 msgstr ""
 
-#: config/tc-arm.c:6252
+#: config/tc-arm.c:8618
 msgid "dest and source1 must be the same register"
 msgstr ""
 
-#: config/tc-arm.c:6537
+#: config/tc-arm.c:8869
+msgid "instruction is always unconditional"
+msgstr ""
+
+#: config/tc-arm.c:8951
+msgid "selected processor does not support 'A' form of this instruction"
+msgstr ""
+
+#: config/tc-arm.c:8954
 msgid "Thumb does not support the 2-argument form of this instruction"
 msgstr ""
 
-#: config/tc-arm.c:6616
-msgid "Thumb load/store multiple does not support {reglist}^"
+#: config/tc-arm.c:9053
+msgid "SP not allowed in register list"
 msgstr ""
 
-#: config/tc-arm.c:6633 config/tc-arm.c:6649 config/tc-arm.c:6680
-#, c-format
-msgid "value stored for r%d is UNPREDICTABLE"
+#: config/tc-arm.c:9058
+msgid "LR and PC should not both be in register list"
 msgstr ""
 
-#: config/tc-arm.c:6643
-msgid "SP should not be in register list"
+#: config/tc-arm.c:9062
+msgid "base register should not be in register list when written back"
 msgstr ""
 
-#: config/tc-arm.c:6647
-msgid "PC should not be in register list"
+#: config/tc-arm.c:9068
+msgid "PC not allowed in register list"
 msgstr ""
 
-#: config/tc-arm.c:6656 config/tc-arm.c:7311
-msgid "LR and PC should not both be in register list"
+#: config/tc-arm.c:9071 config/tc-arm.c:9137 config/tc-arm.c:9177
+#, c-format
+msgid "value stored for r%d is UNPREDICTABLE"
 msgstr ""
 
-#: config/tc-arm.c:6659
-msgid "base register should not be in register list when written back"
+#: config/tc-arm.c:9113
+msgid "Thumb load/store multiple does not support {reglist}^"
+msgstr ""
+
+#: config/tc-arm.c:9170
+msgid "Thumb-2 instruction only valid in unified syntax"
 msgstr ""
 
-#: config/tc-arm.c:6677 config/tc-arm.c:6687
+#: config/tc-arm.c:9174 config/tc-arm.c:9184
 msgid "this instruction will write back the base register"
 msgstr ""
 
-#: config/tc-arm.c:6690
+#: config/tc-arm.c:9187
 msgid "this instruction will not write back the base register"
 msgstr ""
 
-#: config/tc-arm.c:6719
+#: config/tc-arm.c:9216
 msgid "r14 not allowed as first register when second register is omitted"
 msgstr ""
 
-#: config/tc-arm.c:6809 config/tc-arm.c:6822 config/tc-arm.c:6858
+#: config/tc-arm.c:9313 config/tc-arm.c:9326 config/tc-arm.c:9362
 msgid "Thumb does not support this addressing mode"
 msgstr ""
 
-#: config/tc-arm.c:6826
+#: config/tc-arm.c:9330
 msgid "byte or halfword not valid for base register"
 msgstr ""
 
-#: config/tc-arm.c:6829
+#: config/tc-arm.c:9333
 msgid "r15 based store not allowed"
 msgstr ""
 
-#: config/tc-arm.c:6831
+#: config/tc-arm.c:9335
 msgid "invalid base register for register offset"
 msgstr ""
 
-#: config/tc-arm.c:7032
+#: config/tc-arm.c:9633
 msgid "only lo regs allowed with immediate"
 msgstr ""
 
-#: config/tc-arm.c:7130
-msgid "Thumb encoding does not support an immediate here"
+#: config/tc-arm.c:9653
+msgid ":upper16: not allowed this instruction"
 msgstr ""
 
-#: config/tc-arm.c:7200
-msgid "Thumb does not support NOP with hints"
+#: config/tc-arm.c:9747 config/tc-arm.c:9779 config/tc-arm.c:9785
+msgid "selected processor does not support requested special purpose register"
 msgstr ""
 
-#: config/tc-arm.c:7282
-msgid "push/pop do not support {reglist}^"
+#: config/tc-arm.c:9753
+#, c-format
+msgid ""
+"selected processor does not support requested special purpose register %x"
 msgstr ""
 
-#: config/tc-arm.c:7301
-msgid "SP not allowed in register list"
+#: config/tc-arm.c:9774
+msgid "Thumb encoding does not support an immediate here"
 msgstr ""
 
-#: config/tc-arm.c:7305
-msgid "PC not allowed in register list"
+#: config/tc-arm.c:9859
+msgid "Thumb does not support NOP with hints"
+msgstr ""
+
+#: config/tc-arm.c:9941
+msgid "push/pop do not support {reglist}^"
 msgstr ""
 
-#: config/tc-arm.c:7328
+#: config/tc-arm.c:9964
 msgid "invalid register list to push/pop instruction"
 msgstr ""
 
-#: config/tc-arm.c:7513
+#: config/tc-arm.c:10156
+msgid "source1 and dest must be same register"
+msgstr ""
+
+#: config/tc-arm.c:10177
 msgid "ror #imm not supported"
 msgstr ""
 
-#: config/tc-arm.c:7638
+#: config/tc-arm.c:10302
 msgid "Thumb encoding does not support rotation"
 msgstr ""
 
-#: config/tc-arm.c:7656
+#: config/tc-arm.c:10321
+msgid "instruction requires register index"
+msgstr ""
+
+#: config/tc-arm.c:10323
 msgid "PC is not a valid index register"
 msgstr ""
 
-#: config/tc-arm.c:7658
+#: config/tc-arm.c:10325
 msgid "instruction does not allow shifted index"
 msgstr ""
 
-#: config/tc-arm.c:7660
-msgid "instruction requires shifted index"
+#: config/tc-arm.c:10744
+msgid "invalid instruction shape"
+msgstr ""
+
+#: config/tc-arm.c:10986
+msgid "types specified in both the mnemonic and operands"
+msgstr ""
+
+#: config/tc-arm.c:11023
+msgid "operand types can't be inferred"
+msgstr ""
+
+#: config/tc-arm.c:11029
+msgid "type specifier has the wrong number of parts"
+msgstr ""
+
+#: config/tc-arm.c:11084
+msgid "operand size must match register width"
+msgstr ""
+
+#: config/tc-arm.c:11095
+msgid "bad type in Neon instruction"
+msgstr ""
+
+#: config/tc-arm.c:11106
+msgid "inconsistent types in Neon instruction"
+msgstr ""
+
+#: config/tc-arm.c:12155
+msgid "scalar out of range for multiply instruction"
+msgstr ""
+
+#: config/tc-arm.c:12319 config/tc-arm.c:12331
+msgid "immediate out of range for insert"
+msgstr ""
+
+#: config/tc-arm.c:12343 config/tc-arm.c:13245
+msgid "immediate out of range for shift"
+msgstr ""
+
+#: config/tc-arm.c:12400 config/tc-arm.c:12427 config/tc-arm.c:12745
+#: config/tc-arm.c:13191
+msgid "immediate out of range"
+msgstr ""
+
+#: config/tc-arm.c:12464
+msgid "immediate out of range for narrowing operation"
+msgstr ""
+
+#: config/tc-arm.c:12584
+msgid "operands 0 and 1 must be the same register"
+msgstr ""
+
+#: config/tc-arm.c:12719
+msgid "operand size must be specified for immediate VMOV"
+msgstr ""
+
+#: config/tc-arm.c:12729
+msgid "immediate has bits set outside the operand size"
+msgstr ""
+
+#: config/tc-arm.c:12925
+msgid "elements must be smaller than reversal region"
 msgstr ""
 
-#: config/tc-arm.c:7943 config/tc-arm.c:8015
+#: config/tc-arm.c:13096 config/tc-arm.c:13144
+msgid "bad type for scalar"
+msgstr ""
+
+#: config/tc-arm.c:13208 config/tc-arm.c:13216
+msgid "VFP registers must be adjacent"
+msgstr ""
+
+#: config/tc-arm.c:13357
+msgid "bad list length for table lookup"
+msgstr ""
+
+#: config/tc-arm.c:13387
+msgid "writeback (!) must be used for VLDMDB and VSTMDB"
+msgstr ""
+
+#: config/tc-arm.c:13390
+msgid "register list must contain at least 1 and at most 16 registers"
+msgstr ""
+
+#: config/tc-arm.c:13467
+msgid "bad alignment"
+msgstr ""
+
+#: config/tc-arm.c:13484
+msgid "bad list type for instruction"
+msgstr ""
+
+#: config/tc-arm.c:13526
+msgid "unsupported alignment for instruction"
+msgstr ""
+
+#: config/tc-arm.c:13545 config/tc-arm.c:13639 config/tc-arm.c:13650
+#: config/tc-arm.c:13660 config/tc-arm.c:13674
+msgid "bad list length"
+msgstr ""
+
+#: config/tc-arm.c:13550
+msgid "stride of 2 unavailable when element size is 8"
+msgstr ""
+
+#: config/tc-arm.c:13583 config/tc-arm.c:13658
+msgid "can't use alignment with this instruction"
+msgstr ""
+
+#: config/tc-arm.c:13722
+msgid "post-index must be a register"
+msgstr ""
+
+#: config/tc-arm.c:13724
+msgid "bad register for post-index"
+msgstr ""
+
+#: config/tc-arm.c:14011 config/tc-arm.c:14097
 msgid "conditional infixes are deprecated in unified syntax"
 msgstr ""
 
-#: config/tc-arm.c:8047
+#: config/tc-arm.c:14130
 #, c-format
 msgid "bad instruction `%s'"
 msgstr ""
 
-#: config/tc-arm.c:8063 config/tc-arm.c:8126
+#: config/tc-arm.c:14136
+msgid "s suffix on comparison instruction is deprecated"
+msgstr ""
+
+#: config/tc-arm.c:14155 config/tc-arm.c:14236
 #, c-format
 msgid "selected processor does not support `%s'"
 msgstr ""
 
-#: config/tc-arm.c:8069
+#: config/tc-arm.c:14161
 msgid "Thumb does not support conditional execution"
 msgstr ""
 
-#: config/tc-arm.c:8080
+#: config/tc-arm.c:14184
 msgid "incorrect condition in IT block"
 msgstr ""
 
-#: config/tc-arm.c:8088
+#: config/tc-arm.c:14190
 msgid "thumb conditional instrunction not in IT block"
 msgstr ""
 
-#: config/tc-arm.c:8108
+#: config/tc-arm.c:14210
 #, c-format
 msgid "cannot honor width suffix -- `%s'"
 msgstr ""
 
-#: config/tc-arm.c:8131
+#: config/tc-arm.c:14241
 #, c-format
 msgid "width suffixes are invalid in ARM mode -- `%s'"
 msgstr ""
 
-#: config/tc-arm.c:10340
+#: config/tc-arm.c:14265
+#, c-format
+msgid "attempt to use an ARM instruction on a Thumb-only processor -- `%s'"
+msgstr ""
+
+#: config/tc-arm.c:16992
 msgid "alignments greater than 32 bytes not supported in .text sections."
 msgstr ""
 
-#: config/tc-arm.c:10634
+#: config/tc-arm.c:17286
 msgid "handerdata in cantunwind frame"
 msgstr ""
 
-#: config/tc-arm.c:10651
+#: config/tc-arm.c:17303
 msgid "too many unwind opcodes for personality routine 0"
 msgstr ""
 
-#: config/tc-arm.c:10683
+#: config/tc-arm.c:17335
 msgid "too many unwind opcodes"
 msgstr ""
 
-#: config/tc-arm.c:11085 config/tc-arm.c:11365
+#: config/tc-arm.c:17869 config/tc-arm.c:18153
 #, c-format
 msgid "undefined symbol %s used as an immediate value"
 msgstr ""
 
-#: config/tc-arm.c:11099 config/tc-arm.c:11394
+#: config/tc-arm.c:17883 config/tc-arm.c:18192
 #, c-format
 msgid "invalid constant (%lx) after fixup"
 msgstr ""
 
-#: config/tc-arm.c:11136
+#: config/tc-arm.c:17920
 #, c-format
 msgid "unable to compute ADRL instructions for PC offset of 0x%lx"
 msgstr ""
 
-#: config/tc-arm.c:11168 config/tc-arm.c:11193
+#: config/tc-arm.c:17955 config/tc-arm.c:17980
 msgid "invalid literal constant: pool needs to be closer"
 msgstr ""
 
-#: config/tc-arm.c:11171 config/tc-arm.c:11209
+#: config/tc-arm.c:17958 config/tc-arm.c:17996
 #, c-format
 msgid "bad immediate value for offset (%ld)"
 msgstr ""
 
-#: config/tc-arm.c:11195
+#: config/tc-arm.c:17982
 #, c-format
-msgid "bad immediate value for half-word offset (%ld)"
+msgid "bad immediate value for 8-bit offset (%ld)"
 msgstr ""
 
-#: config/tc-arm.c:11250
+#: config/tc-arm.c:18037
 msgid "offset not a multiple of 4"
 msgstr ""
 
-#: config/tc-arm.c:11257 config/tc-arm.c:11272 config/tc-arm.c:11287
-#: config/tc-arm.c:11298 config/tc-arm.c:11321 config/tc-pj.c:499
-#: config/tc-sh.c:4084
+#: config/tc-arm.c:18044 config/tc-arm.c:18059 config/tc-arm.c:18074
+#: config/tc-arm.c:18085 config/tc-arm.c:18108 config/tc-pj.c:499
+#: config/tc-sh.c:4214
 msgid "offset out of range"
 msgstr ""
 
-#: config/tc-arm.c:11410
+#: config/tc-arm.c:18208
 msgid "invalid smc expression"
 msgstr ""
 
-#: config/tc-arm.c:11421 config/tc-arm.c:11430
+#: config/tc-arm.c:18219 config/tc-arm.c:18228
 msgid "invalid swi expression"
 msgstr ""
 
-#: config/tc-arm.c:11440
+#: config/tc-arm.c:18238
 msgid "invalid expression in load/store multiple"
 msgstr ""
 
-#: config/tc-arm.c:11455
+#: config/tc-arm.c:18268
 msgid "misaligned branch destination"
 msgstr ""
 
-#: config/tc-arm.c:11459 config/tc-arm.c:11479 config/tc-arm.c:11497
-#: config/tc-arm.c:11510 config/tc-arm.c:11523 config/tc-arm.c:11562
-#: config/tc-arm.c:11587
+#: config/tc-arm.c:18272 config/tc-arm.c:18309 config/tc-arm.c:18323
+#: config/tc-arm.c:18336 config/tc-arm.c:18375 config/tc-arm.c:18400
 msgid "branch out of range"
 msgstr ""
 
-#: config/tc-arm.c:11475
-msgid "misaligned BLX destination"
-msgstr ""
-
-#: config/tc-arm.c:11536
+#: config/tc-arm.c:18349
 msgid "conditional branch out of range"
 msgstr ""
 
-#: config/tc-arm.c:11657
+#: config/tc-arm.c:18477
 msgid "rel31 relocation overflow"
 msgstr ""
 
-#: config/tc-arm.c:11669 config/tc-arm.c:11694
+#: config/tc-arm.c:18489 config/tc-arm.c:18512
 msgid "co-processor offset out of range"
 msgstr ""
 
-#: config/tc-arm.c:11710
+#: config/tc-arm.c:18529
 #, c-format
 msgid "invalid offset, target not word aligned (0x%08lX)"
 msgstr ""
 
-#: config/tc-arm.c:11716 config/tc-arm.c:11725 config/tc-arm.c:11733
-#: config/tc-arm.c:11741 config/tc-arm.c:11749
+#: config/tc-arm.c:18536 config/tc-arm.c:18545 config/tc-arm.c:18553
+#: config/tc-arm.c:18561 config/tc-arm.c:18569
 #, c-format
 msgid "invalid offset, value too big (0x%08lX)"
 msgstr ""
 
-#: config/tc-arm.c:11790
+#: config/tc-arm.c:18610
 msgid "invalid Hi register with immediate"
 msgstr ""
 
-#: config/tc-arm.c:11806
+#: config/tc-arm.c:18626
 msgid "invalid immediate for stack address calculation"
 msgstr ""
 
-#: config/tc-arm.c:11814
+#: config/tc-arm.c:18634
 #, c-format
 msgid "invalid immediate for address calculation (value = 0x%08lX)"
 msgstr ""
 
-#: config/tc-arm.c:11844
+#: config/tc-arm.c:18664
 #, c-format
 msgid "invalid immediate: %ld is too large"
 msgstr ""
 
-#: config/tc-arm.c:11856
+#: config/tc-arm.c:18676
 #, c-format
 msgid "invalid shift value: %ld"
 msgstr ""
 
-#: config/tc-arm.c:11875
+#: config/tc-arm.c:18703
+msgid "offset too big"
+msgstr ""
+
+#: config/tc-arm.c:18755
+#, c-format
+msgid "the offset 0x%08lX is not representable"
+msgstr ""
+
+#: config/tc-arm.c:18795
+#, c-format
+msgid "bad offset 0x%08lX (only 12 bits available for the magnitude)"
+msgstr ""
+
+#: config/tc-arm.c:18834
+#, c-format
+msgid "bad offset 0x%08lX (only 8 bits available for the magnitude)"
+msgstr ""
+
+#: config/tc-arm.c:18874
+#, c-format
+msgid "bad offset 0x%08lX (must be word-aligned)"
+msgstr ""
+
+#: config/tc-arm.c:18879
+#, c-format
+msgid "bad offset 0x%08lX (must be an 8-bit number of words)"
+msgstr ""
+
+#: config/tc-arm.c:18905 config/tc-score.c:5480
 #, c-format
 msgid "bad relocation fixup type (%d)"
 msgstr ""
 
-#: config/tc-arm.c:11943
+#: config/tc-arm.c:19008
 msgid "literal referenced across section boundary"
 msgstr ""
 
-#: config/tc-arm.c:11973
+#: config/tc-arm.c:19068
 msgid "internal relocation (type: IMMEDIATE) not fixed up"
 msgstr ""
 
-#: config/tc-arm.c:11978
+#: config/tc-arm.c:19073
 msgid "ADRL used for a symbol not defined in the same file"
 msgstr ""
 
-#: config/tc-arm.c:11987
+#: config/tc-arm.c:19088
 #, c-format
 msgid "undefined local label `%s'"
 msgstr ""
 
-#: config/tc-arm.c:11993
+#: config/tc-arm.c:19094
 msgid "internal_relocation (type: OFFSET_IMM) not fixed up"
 msgstr ""
 
-#: config/tc-arm.c:12014 config/tc-cris.c:3869 config/tc-mcore.c:1995
-#: config/tc-mmix.c:2888 config/tc-ns32k.c:2284
+#: config/tc-arm.c:19115 config/tc-cris.c:3925 config/tc-mcore.c:1992
+#: config/tc-mmix.c:2887 config/tc-ns32k.c:2282 config/tc-score.c:5571
 msgid "<unknown>"
 msgstr ""
 
-#: config/tc-arm.c:12017 config/tc-arm.c:12038
+#: config/tc-arm.c:19118 config/tc-arm.c:19139 config/tc-score.c:5573
 #, c-format
 msgid "cannot represent %s relocation in this object file format"
 msgstr ""
 
-#: config/tc-arm.c:12254
+#: config/tc-arm.c:19373
 #, c-format
 msgid "%s: unexpected function type: %d"
 msgstr ""
 
-#: config/tc-arm.c:12331
+#: config/tc-arm.c:19463 config/tc-score.c:6592 config/tc-score.c:6608
+#: config/tc-score.c:6613
 msgid "virtual memory exhausted"
 msgstr ""
 
-#: config/tc-arm.c:12357
+#: config/tc-arm.c:19496
 msgid "use of old and new-style options to set CPU type"
 msgstr ""
 
-#: config/tc-arm.c:12367
+#: config/tc-arm.c:19506
 msgid "use of old and new-style options to set FPU type"
 msgstr ""
 
-#: config/tc-arm.c:12441
+#: config/tc-arm.c:19581
 msgid "hard-float conflicts with specified fpu"
 msgstr ""
 
-#: config/tc-arm.c:12633
+#: config/tc-arm.c:19764
 msgid "generate PIC code"
 msgstr ""
 
-#: config/tc-arm.c:12634
+#: config/tc-arm.c:19765
 msgid "assemble Thumb code"
 msgstr ""
 
-#: config/tc-arm.c:12635
+#: config/tc-arm.c:19766
 msgid "support ARM/Thumb interworking"
 msgstr ""
 
-#: config/tc-arm.c:12637
+#: config/tc-arm.c:19768
 msgid "code uses 32-bit program counter"
 msgstr ""
 
-#: config/tc-arm.c:12638
+#: config/tc-arm.c:19769
 msgid "code uses 26-bit program counter"
 msgstr ""
 
-#: config/tc-arm.c:12639
+#: config/tc-arm.c:19770
 msgid "floating point args are in fp regs"
 msgstr ""
 
-#: config/tc-arm.c:12641
+#: config/tc-arm.c:19772
 msgid "re-entrant code"
 msgstr ""
 
-#: config/tc-arm.c:12642
+#: config/tc-arm.c:19773
 msgid "code is ATPCS conformant"
 msgstr ""
 
-#: config/tc-arm.c:12643
+#: config/tc-arm.c:19774
 msgid "assemble for big-endian"
 msgstr ""
 
-#: config/tc-arm.c:12644
+#: config/tc-arm.c:19775
 msgid "assemble for little-endian"
 msgstr ""
 
 #. These are recognized by the assembler, but have no affect on code.
-#: config/tc-arm.c:12648
+#: config/tc-arm.c:19779
 msgid "use frame pointer"
 msgstr ""
 
-#: config/tc-arm.c:12649
+#: config/tc-arm.c:19780
 msgid "use stack size checking"
 msgstr ""
 
 #. DON'T add any new processors to this list -- we want the whole list
 #. to go away...  Add them to the processors table instead.
-#: config/tc-arm.c:12653 config/tc-arm.c:12654
+#: config/tc-arm.c:19796 config/tc-arm.c:19797
 msgid "use -mcpu=arm1"
 msgstr ""
 
-#: config/tc-arm.c:12655 config/tc-arm.c:12656
+#: config/tc-arm.c:19798 config/tc-arm.c:19799
 msgid "use -mcpu=arm2"
 msgstr ""
 
-#: config/tc-arm.c:12657 config/tc-arm.c:12658
+#: config/tc-arm.c:19800 config/tc-arm.c:19801
 msgid "use -mcpu=arm250"
 msgstr ""
 
-#: config/tc-arm.c:12659 config/tc-arm.c:12660
+#: config/tc-arm.c:19802 config/tc-arm.c:19803
 msgid "use -mcpu=arm3"
 msgstr ""
 
-#: config/tc-arm.c:12661 config/tc-arm.c:12662
+#: config/tc-arm.c:19804 config/tc-arm.c:19805
 msgid "use -mcpu=arm6"
 msgstr ""
 
-#: config/tc-arm.c:12663 config/tc-arm.c:12664
+#: config/tc-arm.c:19806 config/tc-arm.c:19807
 msgid "use -mcpu=arm600"
 msgstr ""
 
-#: config/tc-arm.c:12665 config/tc-arm.c:12666
+#: config/tc-arm.c:19808 config/tc-arm.c:19809
 msgid "use -mcpu=arm610"
 msgstr ""
 
-#: config/tc-arm.c:12667 config/tc-arm.c:12668
+#: config/tc-arm.c:19810 config/tc-arm.c:19811
 msgid "use -mcpu=arm620"
 msgstr ""
 
-#: config/tc-arm.c:12669 config/tc-arm.c:12670
+#: config/tc-arm.c:19812 config/tc-arm.c:19813
 msgid "use -mcpu=arm7"
 msgstr ""
 
-#: config/tc-arm.c:12671 config/tc-arm.c:12672
+#: config/tc-arm.c:19814 config/tc-arm.c:19815
 msgid "use -mcpu=arm70"
 msgstr ""
 
-#: config/tc-arm.c:12673 config/tc-arm.c:12674
+#: config/tc-arm.c:19816 config/tc-arm.c:19817
 msgid "use -mcpu=arm700"
 msgstr ""
 
-#: config/tc-arm.c:12675 config/tc-arm.c:12676
+#: config/tc-arm.c:19818 config/tc-arm.c:19819
 msgid "use -mcpu=arm700i"
 msgstr ""
 
-#: config/tc-arm.c:12677 config/tc-arm.c:12678
+#: config/tc-arm.c:19820 config/tc-arm.c:19821
 msgid "use -mcpu=arm710"
 msgstr ""
 
-#: config/tc-arm.c:12679 config/tc-arm.c:12680
+#: config/tc-arm.c:19822 config/tc-arm.c:19823
 msgid "use -mcpu=arm710c"
 msgstr ""
 
-#: config/tc-arm.c:12681 config/tc-arm.c:12682
+#: config/tc-arm.c:19824 config/tc-arm.c:19825
 msgid "use -mcpu=arm720"
 msgstr ""
 
-#: config/tc-arm.c:12683 config/tc-arm.c:12684
+#: config/tc-arm.c:19826 config/tc-arm.c:19827
 msgid "use -mcpu=arm7d"
 msgstr ""
 
-#: config/tc-arm.c:12685 config/tc-arm.c:12686
+#: config/tc-arm.c:19828 config/tc-arm.c:19829
 msgid "use -mcpu=arm7di"
 msgstr ""
 
-#: config/tc-arm.c:12687 config/tc-arm.c:12688
+#: config/tc-arm.c:19830 config/tc-arm.c:19831
 msgid "use -mcpu=arm7m"
 msgstr ""
 
-#: config/tc-arm.c:12689 config/tc-arm.c:12690
+#: config/tc-arm.c:19832 config/tc-arm.c:19833
 msgid "use -mcpu=arm7dm"
 msgstr ""
 
-#: config/tc-arm.c:12691 config/tc-arm.c:12692
+#: config/tc-arm.c:19834 config/tc-arm.c:19835
 msgid "use -mcpu=arm7dmi"
 msgstr ""
 
-#: config/tc-arm.c:12693 config/tc-arm.c:12694
+#: config/tc-arm.c:19836 config/tc-arm.c:19837
 msgid "use -mcpu=arm7100"
 msgstr ""
 
-#: config/tc-arm.c:12695 config/tc-arm.c:12696
+#: config/tc-arm.c:19838 config/tc-arm.c:19839
 msgid "use -mcpu=arm7500"
 msgstr ""
 
-#: config/tc-arm.c:12697 config/tc-arm.c:12698
+#: config/tc-arm.c:19840 config/tc-arm.c:19841
 msgid "use -mcpu=arm7500fe"
 msgstr ""
 
-#: config/tc-arm.c:12699 config/tc-arm.c:12700 config/tc-arm.c:12701
-#: config/tc-arm.c:12702
+#: config/tc-arm.c:19842 config/tc-arm.c:19843 config/tc-arm.c:19844
+#: config/tc-arm.c:19845
 msgid "use -mcpu=arm7tdmi"
 msgstr ""
 
-#: config/tc-arm.c:12703 config/tc-arm.c:12704
+#: config/tc-arm.c:19846 config/tc-arm.c:19847
 msgid "use -mcpu=arm710t"
 msgstr ""
 
-#: config/tc-arm.c:12705 config/tc-arm.c:12706
+#: config/tc-arm.c:19848 config/tc-arm.c:19849
 msgid "use -mcpu=arm720t"
 msgstr ""
 
-#: config/tc-arm.c:12707 config/tc-arm.c:12708
+#: config/tc-arm.c:19850 config/tc-arm.c:19851
 msgid "use -mcpu=arm740t"
 msgstr ""
 
-#: config/tc-arm.c:12709 config/tc-arm.c:12710
+#: config/tc-arm.c:19852 config/tc-arm.c:19853
 msgid "use -mcpu=arm8"
 msgstr ""
 
-#: config/tc-arm.c:12711 config/tc-arm.c:12712
+#: config/tc-arm.c:19854 config/tc-arm.c:19855
 msgid "use -mcpu=arm810"
 msgstr ""
 
-#: config/tc-arm.c:12713 config/tc-arm.c:12714
+#: config/tc-arm.c:19856 config/tc-arm.c:19857
 msgid "use -mcpu=arm9"
 msgstr ""
 
-#: config/tc-arm.c:12715 config/tc-arm.c:12716
+#: config/tc-arm.c:19858 config/tc-arm.c:19859
 msgid "use -mcpu=arm9tdmi"
 msgstr ""
 
-#: config/tc-arm.c:12717 config/tc-arm.c:12718
+#: config/tc-arm.c:19860 config/tc-arm.c:19861
 msgid "use -mcpu=arm920"
 msgstr ""
 
-#: config/tc-arm.c:12719 config/tc-arm.c:12720
+#: config/tc-arm.c:19862 config/tc-arm.c:19863
 msgid "use -mcpu=arm940"
 msgstr ""
 
-#: config/tc-arm.c:12721
+#: config/tc-arm.c:19864
 msgid "use -mcpu=strongarm"
 msgstr ""
 
-#: config/tc-arm.c:12723
+#: config/tc-arm.c:19866
 msgid "use -mcpu=strongarm110"
 msgstr ""
 
-#: config/tc-arm.c:12725
+#: config/tc-arm.c:19868
 msgid "use -mcpu=strongarm1100"
 msgstr ""
 
-#: config/tc-arm.c:12727
+#: config/tc-arm.c:19870
 msgid "use -mcpu=strongarm1110"
 msgstr ""
 
-#: config/tc-arm.c:12728
+#: config/tc-arm.c:19871
 msgid "use -mcpu=xscale"
 msgstr ""
 
-#: config/tc-arm.c:12729
+#: config/tc-arm.c:19872
 msgid "use -mcpu=iwmmxt"
 msgstr ""
 
-#: config/tc-arm.c:12730
+#: config/tc-arm.c:19873
 msgid "use -mcpu=all"
 msgstr ""
 
 #. Architecture variants -- don't add any more to this list either.
-#: config/tc-arm.c:12733 config/tc-arm.c:12734
+#: config/tc-arm.c:19876 config/tc-arm.c:19877
 msgid "use -march=armv2"
 msgstr ""
 
-#: config/tc-arm.c:12735 config/tc-arm.c:12736
+#: config/tc-arm.c:19878 config/tc-arm.c:19879
 msgid "use -march=armv2a"
 msgstr ""
 
-#: config/tc-arm.c:12737 config/tc-arm.c:12738
+#: config/tc-arm.c:19880 config/tc-arm.c:19881
 msgid "use -march=armv3"
 msgstr ""
 
-#: config/tc-arm.c:12739 config/tc-arm.c:12740
+#: config/tc-arm.c:19882 config/tc-arm.c:19883
 msgid "use -march=armv3m"
 msgstr ""
 
-#: config/tc-arm.c:12741 config/tc-arm.c:12742
+#: config/tc-arm.c:19884 config/tc-arm.c:19885
 msgid "use -march=armv4"
 msgstr ""
 
-#: config/tc-arm.c:12743 config/tc-arm.c:12744
+#: config/tc-arm.c:19886 config/tc-arm.c:19887
 msgid "use -march=armv4t"
 msgstr ""
 
-#: config/tc-arm.c:12745 config/tc-arm.c:12746
+#: config/tc-arm.c:19888 config/tc-arm.c:19889
 msgid "use -march=armv5"
 msgstr ""
 
-#: config/tc-arm.c:12747 config/tc-arm.c:12748
+#: config/tc-arm.c:19890 config/tc-arm.c:19891
 msgid "use -march=armv5t"
 msgstr ""
 
-#: config/tc-arm.c:12749 config/tc-arm.c:12750
+#: config/tc-arm.c:19892 config/tc-arm.c:19893
 msgid "use -march=armv5te"
 msgstr ""
 
 #. Floating point variants -- don't add any more to this list either.
-#: config/tc-arm.c:12753
+#: config/tc-arm.c:19896
 msgid "use -mfpu=fpe"
 msgstr ""
 
-#: config/tc-arm.c:12754
+#: config/tc-arm.c:19897
 msgid "use -mfpu=fpa10"
 msgstr ""
 
-#: config/tc-arm.c:12755
+#: config/tc-arm.c:19898
 msgid "use -mfpu=fpa11"
 msgstr ""
 
-#: config/tc-arm.c:12757
+#: config/tc-arm.c:19900
 msgid "use either -mfpu=softfpa or -mfpu=softvfp"
 msgstr ""
 
-#: config/tc-arm.c:12986
+#: config/tc-arm.c:20161
 msgid "invalid architectural extension"
 msgstr ""
 
-#: config/tc-arm.c:13000
+#: config/tc-arm.c:20175
 msgid "missing architectural extension"
 msgstr ""
 
-#: config/tc-arm.c:13013
+#: config/tc-arm.c:20188
 #, c-format
 msgid "unknown architectural extnsion `%s'"
 msgstr ""
 
-#: config/tc-arm.c:13037
+#: config/tc-arm.c:20212
 #, c-format
 msgid "missing cpu name `%s'"
 msgstr ""
 
-#: config/tc-arm.c:13062 config/tc-arm.c:13389
+#: config/tc-arm.c:20237 config/tc-arm.c:20622
 #, c-format
 msgid "unknown cpu `%s'"
 msgstr ""
 
-#: config/tc-arm.c:13080
+#: config/tc-arm.c:20255
 #, c-format
 msgid "missing architecture name `%s'"
 msgstr ""
 
-#: config/tc-arm.c:13097 config/tc-arm.c:13423
+#: config/tc-arm.c:20272 config/tc-arm.c:20656 config/tc-arm.c:20687
 #, c-format
 msgid "unknown architecture `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:13113 config/tc-arm.c:13454
+#: config/tc-arm.c:20288 config/tc-arm.c:20718
 #, c-format
 msgid "unknown floating point format `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:13129
+#: config/tc-arm.c:20304
 #, c-format
 msgid "unknown floating point abi `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:13145
+#: config/tc-arm.c:20320
 #, c-format
 msgid "unknown EABI `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:13152
+#: config/tc-arm.c:20327
 msgid "<cpu name>\t  assemble for CPU <cpu name>"
 msgstr ""
 
-#: config/tc-arm.c:13154
+#: config/tc-arm.c:20329
 msgid "<arch name>\t  assemble for architecture <arch name>"
 msgstr ""
 
-#: config/tc-arm.c:13156
+#: config/tc-arm.c:20331
 msgid "<fpu name>\t  assemble for FPU architecture <fpu name>"
 msgstr ""
 
-#: config/tc-arm.c:13158
+#: config/tc-arm.c:20333
 msgid "<abi>\t  assemble for floating point ABI <abi>"
 msgstr ""
 
-#: config/tc-arm.c:13161
+#: config/tc-arm.c:20336
 msgid "<ver>\t  assemble for eabi version <ver>"
 msgstr ""
 
-#: config/tc-arm.c:13202 config/tc-arm.c:13224
+#: config/tc-arm.c:20378 config/tc-arm.c:20398 config/tc-arm.c:20420
 #, c-format
 msgid "option `-%c%s' is deprecated: %s"
 msgstr ""
 
-#: config/tc-arm.c:13245
+#: config/tc-arm.c:20441
 #, c-format
 msgid " ARM-specific assembler options:\n"
 msgstr ""
 
-#: config/tc-arm.c:13256
+#: config/tc-arm.c:20452
 #, c-format
 msgid "  -EB                     assemble code for a big-endian cpu\n"
 msgstr ""
 
-#: config/tc-arm.c:13261
+#: config/tc-arm.c:20457
 #, c-format
 msgid "  -EL                     assemble code for a little-endian cpu\n"
 msgstr ""
 
-#: config/tc-avr.c:209
+#: config/tc-avr.c:258
 #, c-format
 msgid "Known MCU names:"
 msgstr ""
 
-#: config/tc-avr.c:275
+#: config/tc-avr.c:324
 #, c-format
 msgid ""
 "AVR options:\n"
@@ -2691,7 +3035,7 @@ msgid ""
 "                   or immediate microcontroller name.\n"
 msgstr ""
 
-#: config/tc-avr.c:285
+#: config/tc-avr.c:334
 #, c-format
 msgid ""
 "  -mall-opcodes    accept all AVR opcodes, even if not supported by MCU\n"
@@ -2701,562 +3045,719 @@ msgid ""
 "                   (default for avr3, avr5)\n"
 msgstr ""
 
-#: config/tc-avr.c:329 config/tc-msp430.c:749
+#: config/tc-avr.c:378 config/tc-msp430.c:747
 #, c-format
 msgid "unknown MCU: %s\n"
 msgstr ""
 
-#: config/tc-avr.c:338
+#: config/tc-avr.c:387
 #, c-format
 msgid "redefinition of mcu type `%s' to `%s'"
 msgstr ""
 
-#: config/tc-avr.c:385 config/tc-crx.c:491 config/tc-d10v.c:278
-#: config/tc-d30v.c:312 config/tc-mips.c:10241 config/tc-mmix.c:2264
-#: config/tc-mn10200.c:342 config/tc-msp430.c:873 config/tc-pj.c:342
-#: config/tc-ppc.c:5211 config/tc-sh.c:2986 config/tc-v850.c:1199
+#: config/tc-avr.c:434 config/tc-cr16.c:670 config/tc-crx.c:491
+#: config/tc-d10v.c:277 config/tc-d30v.c:311 config/tc-mips.c:10769
+#: config/tc-mmix.c:2263 config/tc-mn10200.c:341 config/tc-msp430.c:871
+#: config/tc-pj.c:342 config/tc-ppc.c:5206 config/tc-sh.c:3076
+#: config/tc-v850.c:1198
 msgid "bad call to md_atof"
 msgstr ""
 
-#: config/tc-avr.c:447
+#: config/tc-avr.c:501
 msgid "constant value required"
 msgstr ""
 
-#: config/tc-avr.c:450
+#: config/tc-avr.c:504
 #, c-format
 msgid "number must be less than %d"
 msgstr ""
 
-#: config/tc-avr.c:476 config/tc-avr.c:583
+#: config/tc-avr.c:530 config/tc-avr.c:665
 #, c-format
 msgid "constant out of 8-bit range: %d"
 msgstr ""
 
-#: config/tc-avr.c:488 config/tc-d10v.c:498 config/tc-d30v.c:490
-#: config/tc-h8300.c:451 config/tc-mcore.c:665 config/tc-mmix.c:489
-#: config/tc-mn10200.c:1078 config/tc-mn10300.c:1820 config/tc-msp430.c:457
-#: config/tc-or32.c:306 config/tc-ppc.c:2382 config/tc-s390.c:1220
-#: config/tc-sh64.c:2213 config/tc-sh.c:1272 config/tc-v850.c:1952
-#: config/tc-z8k.c:328
+#: config/tc-avr.c:542 config/tc-d10v.c:497 config/tc-d30v.c:489
+#: config/tc-h8300.c:449 config/tc-mcore.c:662 config/tc-mmix.c:488
+#: config/tc-mn10200.c:1077 config/tc-mn10300.c:1819 config/tc-msp430.c:455
+#: config/tc-or32.c:307 config/tc-ppc.c:2436 config/tc-s390.c:1221
+#: config/tc-sh64.c:2213 config/tc-sh.c:1359 config/tc-v850.c:1967
+#: config/tc-z80.c:575 config/tc-z8k.c:350
 msgid "missing operand"
 msgstr ""
 
-#: config/tc-avr.c:536 read.c:3345
+#: config/tc-avr.c:598 config/tc-score.c:974 read.c:3560
 msgid "illegal expression"
 msgstr ""
 
-#: config/tc-avr.c:562 config/tc-avr.c:1282
+#: config/tc-avr.c:627 config/tc-avr.c:1386
 msgid "`)' required"
 msgstr ""
 
-#: config/tc-avr.c:638
+#: config/tc-avr.c:648
+msgid "expression dangerous with linker stubs"
+msgstr ""
+
+#: config/tc-avr.c:720
 msgid "register r16-r23 required"
 msgstr ""
 
-#: config/tc-avr.c:644
+#: config/tc-avr.c:726
 msgid "register number above 15 required"
 msgstr ""
 
-#: config/tc-avr.c:650
+#: config/tc-avr.c:732
 msgid "even register number required"
 msgstr ""
 
-#: config/tc-avr.c:656
+#: config/tc-avr.c:738
 msgid "register r24, r26, r28 or r30 required"
 msgstr ""
 
-#: config/tc-avr.c:662
+#: config/tc-avr.c:744
 msgid "register name or number from 0 to 31 required"
 msgstr ""
 
-#: config/tc-avr.c:680
+#: config/tc-avr.c:762
 msgid "pointer register (X, Y or Z) required"
 msgstr ""
 
-#: config/tc-avr.c:687
+#: config/tc-avr.c:769
 msgid "cannot both predecrement and postincrement"
 msgstr ""
 
-#: config/tc-avr.c:695
+#: config/tc-avr.c:777
 msgid "addressing mode not supported"
 msgstr ""
 
-#: config/tc-avr.c:701
+#: config/tc-avr.c:783
 msgid "can't predecrement"
 msgstr ""
 
-#: config/tc-avr.c:704
+#: config/tc-avr.c:786
 msgid "pointer register Z required"
 msgstr ""
 
-#: config/tc-avr.c:722
+#: config/tc-avr.c:804
 msgid "pointer register (Y or Z) required"
 msgstr ""
 
-#: config/tc-avr.c:826
+#: config/tc-avr.c:908
 #, c-format
 msgid "unknown constraint `%c'"
 msgstr ""
 
-#: config/tc-avr.c:878
+#: config/tc-avr.c:960
 msgid "`,' required"
 msgstr ""
 
-#: config/tc-avr.c:896
+#: config/tc-avr.c:978
 msgid "undefined combination of operands"
 msgstr ""
 
-#: config/tc-avr.c:905
+#: config/tc-avr.c:987
 msgid "skipping two-word instruction"
 msgstr ""
 
-#: config/tc-avr.c:997 config/tc-avr.c:1013 config/tc-avr.c:1135
-#: config/tc-msp430.c:2012 config/tc-msp430.c:2030
+#: config/tc-avr.c:1079 config/tc-avr.c:1095 config/tc-avr.c:1209
+#: config/tc-msp430.c:2009 config/tc-msp430.c:2027
 #, c-format
 msgid "odd address operand: %ld"
 msgstr ""
 
-#: config/tc-avr.c:1005 config/tc-avr.c:1024 config/tc-avr.c:1046
-#: config/tc-avr.c:1053 config/tc-avr.c:1060 config/tc-d10v.c:538
-#: config/tc-d30v.c:589 config/tc-msp430.c:2020 config/tc-msp430.c:2035
-#: config/tc-msp430.c:2045
+#: config/tc-avr.c:1087 config/tc-avr.c:1106 config/tc-avr.c:1128
+#: config/tc-avr.c:1135 config/tc-avr.c:1142 config/tc-d10v.c:537
+#: config/tc-d30v.c:588 config/tc-msp430.c:2017 config/tc-msp430.c:2032
+#: config/tc-msp430.c:2042
 #, c-format
 msgid "operand out of range: %ld"
 msgstr ""
 
-#: config/tc-avr.c:1144 config/tc-d10v.c:1622 config/tc-d30v.c:2060
-#: config/tc-msp430.c:2063
+#: config/tc-avr.c:1218 config/tc-d10v.c:1619 config/tc-d30v.c:2059
+#: config/tc-msp430.c:2060
 #, c-format
 msgid "line %d: unknown relocation type: 0x%x"
 msgstr ""
 
-#: config/tc-avr.c:1158
+#: config/tc-avr.c:1232
 msgid "only constant expression allowed"
 msgstr ""
 
 #. xgettext:c-format.
-#: config/tc-avr.c:1192 config/tc-bfin.c:689 config/tc-d10v.c:1494
-#: config/tc-d30v.c:1804 config/tc-mn10200.c:814 config/tc-mn10300.c:2308
-#: config/tc-msp430.c:2098 config/tc-or32.c:1019 config/tc-ppc.c:6064
-#: config/tc-v850.c:2190
+#: config/tc-avr.c:1292 config/tc-bfin.c:771 config/tc-d10v.c:1491
+#: config/tc-d30v.c:1803 config/tc-mn10200.c:813 config/tc-mn10300.c:2311
+#: config/tc-msp430.c:2095 config/tc-or32.c:1017 config/tc-ppc.c:6085
+#: config/tc-spu.c:884 config/tc-spu.c:1071 config/tc-v850.c:2219
+#: config/tc-z80.c:2017
 #, c-format
 msgid "reloc %d not supported by object file format"
 msgstr ""
 
-#: config/tc-avr.c:1215 config/tc-d10v.c:1782 config/tc-d10v.c:1796
-#: config/tc-h8300.c:1868 config/tc-mcore.c:884 config/tc-msp430.c:1862
-#: config/tc-pj.c:254 config/tc-sh.c:2457 config/tc-z8k.c:1194
+#: config/tc-avr.c:1315 config/tc-h8300.c:1866 config/tc-mcore.c:881
+#: config/tc-msp430.c:1860 config/tc-pj.c:254 config/tc-sh.c:2544
+#: config/tc-z8k.c:1216
 msgid "can't find opcode "
 msgstr ""
 
-#: config/tc-avr.c:1232
+#: config/tc-avr.c:1332
 #, c-format
 msgid "illegal opcode %s for mcu %s"
 msgstr ""
 
-#: config/tc-avr.c:1241
+#: config/tc-avr.c:1341
 msgid "garbage at end of line"
 msgstr ""
 
-#: config/tc-avr.c:1309 config/tc-avr.c:1316
+#: config/tc-avr.c:1413 config/tc-avr.c:1420
 #, c-format
 msgid "illegal %srelocation size: %d"
 msgstr ""
 
-#: config/tc-bfin.c:263
+#: config/tc-bfin.c:338
 #, c-format
 msgid " BFIN specific command line options:\n"
 msgstr ""
 
-#: config/tc-bfin.c:646 config/tc-fr30.c:358 config/tc-frv.c:1600
-#: config/tc-i960.c:1756 config/tc-ip2k.c:371 config/tc-m32c.c:912
-#: config/tc-m32r.c:2143 config/tc-openrisc.c:376 config/tc-xstormy16.c:631
+#: config/tc-bfin.c:728 config/tc-fr30.c:357 config/tc-frv.c:1599
+#: config/tc-i960.c:1754 config/tc-ip2k.c:370 config/tc-m32c.c:1236
+#: config/tc-m32r.c:2142 config/tc-mep.c:1713 config/tc-openrisc.c:375
+#: config/tc-xc16x.c:258 config/tc-xstormy16.c:631
 msgid "Bad call to md_atof()"
 msgstr ""
 
-#: config/tc-cris.c:532 config/tc-m68hc11.c:2794
+#: config/tc-cr16.c:159 read.c:4266
+msgid "using a bit field width of zero"
+msgstr ""
+
+#: config/tc-cr16.c:167 read.c:4274
+#, c-format
+msgid "field width \"%s\" too complex for a bitfield"
+msgstr ""
+
+#: config/tc-cr16.c:176 read.c:4282
+#, c-format
+msgid "field width %lu too big to fit in %d bytes: truncated to %d bits"
+msgstr ""
+
+#: config/tc-cr16.c:198 read.c:4304
+#, c-format
+msgid "field value \"%s\" too complex for a bitfield"
+msgstr ""
+
+#: config/tc-cr16.c:379
+#, c-format
+msgid "Unknown register pair - index relative mode: `%d'"
+msgstr ""
+
+#: config/tc-cr16.c:558 config/tc-crx.c:344 config/tc-mn10200.c:800
+#: write.c:959
+#, c-format
+msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
+msgstr ""
+
+#: config/tc-cr16.c:574 config/tc-crx.c:360
+#, c-format
+msgid "internal error: reloc %d (`%s') not supported by object file format"
+msgstr ""
+
+#: config/tc-cr16.c:762 config/tc-cr16.c:785 config/tc-cris.c:1181
+#: config/tc-crx.c:582 config/tc-crx.c:609 config/tc-crx.c:627
+msgid "Virtual memory exhausted"
+msgstr ""
+
+#: config/tc-cr16.c:770 config/tc-crx.c:619 config/tc-crx.c:637
+#: config/tc-i386.c:1230 config/tc-i386.c:1252 config/tc-m68k.c:4387
+#, c-format
+msgid "Internal Error:  Can't hash %s: %s"
+msgstr ""
+
+#: config/tc-cr16.c:796 config/tc-cris.c:1215 config/tc-crx.c:592
+#, c-format
+msgid "Can't hash `%s': %s\n"
+msgstr ""
+
+#: config/tc-cr16.c:797 config/tc-cris.c:1216 config/tc-crx.c:593
+msgid "(unknown reason)"
+msgstr ""
+
+#. Missing or bad expr becomes absolute 0.
+#: config/tc-cr16.c:847 config/tc-crx.c:665 config/tc-i386.c:4865
+#, c-format
+msgid "missing or invalid displacement expression `%s' taken as 0"
+msgstr ""
+
+#: config/tc-cr16.c:959
+#, c-format
+msgid "operand %d: illegal use expression: `%s`"
+msgstr ""
+
+#: config/tc-cr16.c:1016 config/tc-crx.c:1173
+#, c-format
+msgid "Unknown register: `%d'"
+msgstr ""
+
+#. Issue a error message when register is illegal.
+#: config/tc-cr16.c:1024 config/tc-crx.c:1181
+#, c-format
+msgid "Illegal register (`%s') in Instruction: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1095 config/tc-cr16.c:1170 config/tc-crx.c:803
+#: config/tc-crx.c:823 config/tc-crx.c:838
+#, c-format
+msgid "Illegal register `%s' in Instruction `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1123 config/tc-cr16.c:1134
+#, c-format
+msgid "Illegal register pair `%s' in Instruction `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1159 config/tc-i960.c:835
+msgid "unmatched '['"
+msgstr ""
+
+#: config/tc-cr16.c:1165 config/tc-i960.c:842
+msgid "garbage after index spec ignored"
+msgstr ""
+
+#: config/tc-cr16.c:1313 config/tc-crx.c:982
+#, c-format
+msgid "Illegal operands (whitespace): `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1325 config/tc-cr16.c:1332 config/tc-cr16.c:1349
+#: config/tc-crx.c:994 config/tc-crx.c:1001 config/tc-crx.c:1018
+#: config/tc-crx.c:1810
+#, c-format
+msgid "Missing matching brackets : `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1381 config/tc-crx.c:1044
+#, c-format
+msgid "Unknown exception: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1468 config/tc-crx.c:1140
+#, c-format
+msgid "Illegal `cinv' parameter: `%c'"
+msgstr ""
+
+#: config/tc-cr16.c:1490 config/tc-cr16.c:1529
+#, c-format
+msgid "Unknown register pair: `%d'"
+msgstr ""
+
+#. Issue a error message when register  pair is illegal.
+#: config/tc-cr16.c:1498
+#, c-format
+msgid "Illegal register pair (`%s') in Instruction: `%s'"
+msgstr ""
+
+#. Issue a error message when register  pair is illegal.
+#: config/tc-cr16.c:1537
+#, c-format
+msgid "Illegal index register pair (`%s') in Instruction: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1576
+#, c-format
+msgid "Unknown processor register : `%d'"
+msgstr ""
+
+#. Issue a error message when register  pair is illegal.
+#: config/tc-cr16.c:1584
+#, c-format
+msgid "Illegal processor register (`%s') in Instruction: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1632
+#, c-format
+msgid "Unknown processor register (32 bit) : `%d'"
+msgstr ""
+
+#. Issue a error message when register  pair is illegal.
+#: config/tc-cr16.c:1640
+#, c-format
+msgid "Illegal 32 bit - processor register (`%s') in Instruction: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:2004 config/tc-crx.c:1708 config/tc-crx.c:1725
+#, c-format
+msgid "Same src/dest register is used (`r%d'), result is undefined"
+msgstr ""
+
+#: config/tc-cr16.c:2025
+msgid "RA register is saved twice."
+msgstr ""
+
+#: config/tc-cr16.c:2029
+#, c-format
+msgid "`%s' Illegal use of registers."
+msgstr ""
+
+#: config/tc-cr16.c:2043
+#, c-format
+msgid "`%s' Illegal count-register combination."
+msgstr ""
+
+#: config/tc-cr16.c:2049
+#, c-format
+msgid "`%s' Illegal use of register."
+msgstr ""
+
+#: config/tc-cr16.c:2058 config/tc-crx.c:1717
+#, c-format
+msgid "`%s' has undefined result"
+msgstr ""
+
+#: config/tc-cr16.c:2066
+#, c-format
+msgid "Same src/dest register is used (`r%d'),result is undefined"
+msgstr ""
+
+#: config/tc-cr16.c:2237 config/tc-crx.c:1622
+msgid "Incorrect number of operands"
+msgstr ""
+
+#: config/tc-cr16.c:2239 config/tc-crx.c:1624
+#, c-format
+msgid "Illegal type of operand (arg %d)"
+msgstr ""
+
+#: config/tc-cr16.c:2245 config/tc-crx.c:1630
+#, c-format
+msgid "Operand out of range (arg %d)"
+msgstr ""
+
+#: config/tc-cr16.c:2248 config/tc-crx.c:1633
+#, c-format
+msgid "Operand has odd displacement (arg %d)"
+msgstr ""
+
+#: config/tc-cr16.c:2251 config/tc-cr16.c:2282 config/tc-crx.c:1646
+#: config/tc-crx.c:1677
+#, c-format
+msgid "Illegal operand (arg %d)"
+msgstr ""
+
+#. Give an error if a frag containing code is not aligned to a 2-byte
+#. boundary.
+#: config/tc-cr16.c:2351 config/tc-cr16.h:71 config/tc-crx.c:1999
+#: config/tc-crx.h:76
+msgid "instruction address is not a multiple of 2"
+msgstr ""
+
+#: config/tc-cr16.c:2428 config/tc-cris.c:1529 config/tc-cris.c:1537
+#: config/tc-crx.c:2035 config/tc-dlx.c:685 config/tc-hppa.c:3261
+#: config/tc-i860.c:490 config/tc-i860.c:507 config/tc-i860.c:987
+#: config/tc-sparc.c:1431 config/tc-sparc.c:1439
+#, c-format
+msgid "Unknown opcode: `%s'"
+msgstr ""
+
+#: config/tc-cris.c:547 config/tc-m68hc11.c:2796
 #, c-format
 msgid "internal inconsistency problem in %s: fr_symbol %lx"
 msgstr ""
 
-#: config/tc-cris.c:536 config/tc-m68hc11.c:2798 config/tc-msp430.c:2289
+#: config/tc-cris.c:551 config/tc-m68hc11.c:2800 config/tc-msp430.c:2286
 #, c-format
 msgid "internal inconsistency problem in %s: resolved symbol"
 msgstr ""
 
-#: config/tc-cris.c:546 config/tc-m68hc11.c:2804
+#: config/tc-cris.c:561 config/tc-m68hc11.c:2806
 #, c-format
 msgid "internal inconsistency problem in %s: fr_subtype %d"
 msgstr ""
 
-#: config/tc-cris.c:872
+#: config/tc-cris.c:901
 msgid "Relaxation to long branches for .arch common_v10_v32 not implemented"
 msgstr ""
 
-#: config/tc-cris.c:902
+#: config/tc-cris.c:931
 msgid "Complicated LAPC target operand is not a multiple of two.  Use LAPC.D"
 msgstr ""
 
-#: config/tc-cris.c:907
+#: config/tc-cris.c:936
 #, c-format
 msgid ""
 "Internal error found in md_convert_frag: offset %ld.  Please report this."
 msgstr ""
 
-#: config/tc-cris.c:932
+#: config/tc-cris.c:961
 #, c-format
 msgid "internal inconsistency in %s: bdapq no symbol"
 msgstr ""
 
-#: config/tc-cris.c:945
+#: config/tc-cris.c:974
 #, c-format
 msgid "internal inconsistency in %s: bdap.w with no symbol"
 msgstr ""
 
-#: config/tc-cris.c:969
+#: config/tc-cris.c:998
 msgid "section alignment must be >= 4 bytes to check MULS/MULU safeness"
 msgstr ""
 
-#: config/tc-cris.c:978
+#: config/tc-cris.c:1007
 msgid "dangerous MULS/MULU location; give it higher alignment"
 msgstr ""
 
-#: config/tc-cris.c:1083
+#: config/tc-cris.c:1112
 msgid ""
 "Out-of-range .word offset handling is not implemented for .arch "
 "common_v10_v32"
 msgstr ""
 
-#: config/tc-cris.c:1148 config/tc-crx.c:582 config/tc-crx.c:609
-#: config/tc-crx.c:627
-msgid "Virtual memory exhausted"
-msgstr ""
-
-#: config/tc-cris.c:1182 config/tc-crx.c:592
-#, c-format
-msgid "Can't hash `%s': %s\n"
-msgstr ""
-
-#: config/tc-cris.c:1183 config/tc-crx.c:593
-msgid "(unknown reason)"
-msgstr ""
-
-#: config/tc-cris.c:1187
+#: config/tc-cris.c:1220
 #, c-format
 msgid "Buggy opcode: `%s' \"%s\"\n"
 msgstr ""
 
-#: config/tc-cris.c:1493 config/tc-cris.c:1501 config/tc-crx.c:2029
-#: config/tc-dlx.c:685 config/tc-hppa.c:1625 config/tc-i860.c:492
-#: config/tc-i860.c:509 config/tc-i860.c:989 config/tc-sparc.c:1417
-#: config/tc-sparc.c:1425
-#, c-format
-msgid "Unknown opcode: `%s'"
-msgstr ""
-
-#: config/tc-cris.c:1599
+#: config/tc-cris.c:1635
 #, c-format
 msgid "Immediate value not in 5 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1615
+#: config/tc-cris.c:1651
 #, c-format
 msgid "Immediate value not in 4 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1667
+#: config/tc-cris.c:1703
 #, c-format
 msgid "Immediate value not in 6 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1682
+#: config/tc-cris.c:1718
 #, c-format
 msgid "Immediate value not in 6 bit unsigned range: %ld"
 msgstr ""
 
 #. Others have a generic warning.
-#: config/tc-cris.c:1790
+#: config/tc-cris.c:1826
 #, c-format
 msgid "Unimplemented register `%s' specified"
 msgstr ""
 
 #. We've come to the end of instructions with this
 #. opcode, so it must be an error.
-#: config/tc-cris.c:2033
+#: config/tc-cris.c:2069
 msgid "Illegal operands"
 msgstr ""
 
-#: config/tc-cris.c:2074 config/tc-cris.c:2114
+#: config/tc-cris.c:2110 config/tc-cris.c:2150
 #, c-format
 msgid "Immediate value not in 8 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2084 config/tc-cris.c:2135
+#: config/tc-cris.c:2120 config/tc-cris.c:2171
 #, c-format
 msgid "Immediate value not in 16 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2119
+#: config/tc-cris.c:2155
 #, c-format
 msgid "Immediate value not in 8 bit signed range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2124
+#: config/tc-cris.c:2160
 #, c-format
 msgid "Immediate value not in 8 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2140
+#: config/tc-cris.c:2176
 #, c-format
 msgid "Immediate value not in 16 bit signed range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2145
+#: config/tc-cris.c:2181
 #, c-format
 msgid "Immediate value not in 16 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2167
+#: config/tc-cris.c:2203
 msgid "PIC relocation size does not match operand size"
 msgstr ""
 
-#: config/tc-cris.c:3304
+#: config/tc-cris.c:3346
 msgid "Calling gen_cond_branch_32 for .arch common_v10_v32\n"
 msgstr ""
 
-#: config/tc-cris.c:3308
+#: config/tc-cris.c:3350
 msgid "32-bit conditional branch generated"
 msgstr ""
 
-#: config/tc-cris.c:3367
+#: config/tc-cris.c:3411
 msgid "Complex expression not supported"
 msgstr ""
 
 #. FIXME:  Is this function mentioned in the internals.texi manual?  If
 #. not, add it.
-#: config/tc-cris.c:3490
+#: config/tc-cris.c:3537
 msgid "Bad call to md_atof () - floating point formats are not supported"
 msgstr ""
 
-#: config/tc-cris.c:3531
+#: config/tc-cris.c:3578
 msgid "PC-relative relocation must be trivially resolved"
 msgstr ""
 
-#: config/tc-cris.c:3584
+#: config/tc-cris.c:3631
 #, c-format
 msgid "Value not in 16 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3595
+#: config/tc-cris.c:3642
 #, c-format
 msgid "Value not in 16 bit signed range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3606
+#: config/tc-cris.c:3653
 #, c-format
 msgid "Value not in 8 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3614
+#: config/tc-cris.c:3661
 #, c-format
 msgid "Value not in 8 bit signed range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3625
+#: config/tc-cris.c:3672
 #, c-format
 msgid "Value not in 4 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3633
+#: config/tc-cris.c:3680
 #, c-format
 msgid "Value not in 5 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3641
+#: config/tc-cris.c:3688
 #, c-format
 msgid "Value not in 6 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3649
+#: config/tc-cris.c:3696
 #, c-format
 msgid "Value not in 6 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3695
+#: config/tc-cris.c:3742
 #, c-format
 msgid "Please use --help to see usage and options for this assembler.\n"
 msgstr ""
 
-#: config/tc-cris.c:3707
+#: config/tc-cris.c:3754
 msgid "--no-underscore is invalid with a.out format"
 msgstr ""
 
-#: config/tc-cris.c:3727
+#: config/tc-cris.c:3778
 #, c-format
 msgid "invalid <arch> in --march=<arch>: %s"
 msgstr ""
 
-#: config/tc-cris.c:3821
+#: config/tc-cris.c:3877
 msgid ""
 "Semantics error.  This type of operand can not be relocated, it must be an "
 "assembly-time constant"
 msgstr ""
 
-#: config/tc-cris.c:3870
+#: config/tc-cris.c:3926
 #, c-format
 msgid "Cannot generate relocation type for symbol %s, code %s"
 msgstr ""
 
 #. The messages are formatted to line up with the generic options.
-#: config/tc-cris.c:3883
+#: config/tc-cris.c:3939
 #, c-format
 msgid "CRIS-specific options:\n"
 msgstr ""
 
-#: config/tc-cris.c:3885
+#: config/tc-cris.c:3941
 msgid ""
 "  -h, -H                  Don't execute, print this help text.  Deprecated.\n"
 msgstr ""
 
-#: config/tc-cris.c:3887
+#: config/tc-cris.c:3943
 msgid "  -N                      Warn when branches are expanded to jumps.\n"
 msgstr ""
 
-#: config/tc-cris.c:3889
+#: config/tc-cris.c:3945
 msgid ""
 "  --underscore            User symbols are normally prepended with "
 "underscore.\n"
 msgstr ""
 
-#: config/tc-cris.c:3891
+#: config/tc-cris.c:3947
 msgid "                          Registers will not need any prefix.\n"
 msgstr ""
 
-#: config/tc-cris.c:3893
+#: config/tc-cris.c:3949
 msgid "  --no-underscore         User symbols do not have any prefix.\n"
 msgstr ""
 
-#: config/tc-cris.c:3895
+#: config/tc-cris.c:3951
 msgid "                          Registers will require a `$'-prefix.\n"
 msgstr ""
 
-#: config/tc-cris.c:3897
+#: config/tc-cris.c:3953
 msgid "  --pic\t\t\tEnable generation of position-independent code.\n"
 msgstr ""
 
-#: config/tc-cris.c:3899
+#: config/tc-cris.c:3955
 msgid ""
 "  --march=<arch>\t\tGenerate code for <arch>.  Valid choices for <arch>\n"
 "\t\t\t\tare v0_v10, v10, v32 and common_v10_v32.\n"
 msgstr ""
 
-#: config/tc-cris.c:3920
+#: config/tc-cris.c:3976
 msgid "Invalid relocation"
 msgstr ""
 
-#: config/tc-cris.c:3957
+#: config/tc-cris.c:4013
 msgid "Invalid pc-relative relocation"
 msgstr ""
 
-#: config/tc-cris.c:4002
+#: config/tc-cris.c:4058
 #, c-format
 msgid "Adjusted signed .word (%ld) overflows: `switch'-statement too large."
 msgstr ""
 
-#: config/tc-cris.c:4032
+#: config/tc-cris.c:4088
 #, c-format
 msgid ".syntax %s requires command-line option `--underscore'"
 msgstr ""
 
-#: config/tc-cris.c:4041
+#: config/tc-cris.c:4097
 #, c-format
 msgid ".syntax %s requires command-line option `--no-underscore'"
 msgstr ""
 
-#: config/tc-cris.c:4078
+#: config/tc-cris.c:4134
 msgid "Unknown .syntax operand"
 msgstr ""
 
-#: config/tc-cris.c:4088
+#: config/tc-cris.c:4144
 msgid "Pseudodirective .file is only valid when generating ELF"
 msgstr ""
 
-#: config/tc-cris.c:4100
+#: config/tc-cris.c:4156
 msgid "Pseudodirective .loc is only valid when generating ELF"
 msgstr ""
 
-#: config/tc-cris.c:4243
+#: config/tc-cris.c:4299
 msgid "unknown operand to .arch"
 msgstr ""
 
-#: config/tc-cris.c:4252
+#: config/tc-cris.c:4308
 msgid ".arch <arch> requires a matching --march=... option"
 msgstr ""
 
-#: config/tc-crx.c:344 config/tc-mn10200.c:801 write.c:2209
-#, c-format
-msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
-msgstr ""
-
-#: config/tc-crx.c:360
-#, c-format
-msgid "internal error: reloc %d (`%s') not supported by object file format"
-msgstr ""
-
-#: config/tc-crx.c:619 config/tc-crx.c:637 config/tc-i386.c:953
-#: config/tc-i386.c:976 config/tc-m68k.c:4149
-#, c-format
-msgid "Internal Error:  Can't hash %s: %s"
-msgstr ""
-
-#. Missing or bad expr becomes absolute 0.
-#: config/tc-crx.c:665 config/tc-i386.c:4259
-#, c-format
-msgid "missing or invalid displacement expression `%s' taken as 0"
-msgstr ""
-
-#: config/tc-crx.c:803 config/tc-crx.c:823 config/tc-crx.c:838
-#, c-format
-msgid "Illegal register `%s' in Instruction `%s'"
-msgstr ""
-
 #: config/tc-crx.c:866
 #, c-format
 msgid "Illegal Scale - `%d'"
 msgstr ""
 
-#: config/tc-crx.c:982
-#, c-format
-msgid "Illegal operands (whitespace): `%s'"
-msgstr ""
-
-#: config/tc-crx.c:994 config/tc-crx.c:1001 config/tc-crx.c:1018
-#: config/tc-crx.c:1804
-#, c-format
-msgid "Missing matching brackets : `%s'"
-msgstr ""
-
-#: config/tc-crx.c:1044
-#, c-format
-msgid "Unknown exception: `%s'"
-msgstr ""
-
-#: config/tc-crx.c:1140
-#, c-format
-msgid "Illegal `cinv' parameter: `%c'"
-msgstr ""
-
-#: config/tc-crx.c:1173
-#, c-format
-msgid "Unknown register: `%d'"
-msgstr ""
-
-#. Issue a error message when register is illegal.
-#: config/tc-crx.c:1181
-#, c-format
-msgid "Illegal register (`%s') in Instruction: `%s'"
-msgstr ""
-
 #: config/tc-crx.c:1310
 #, c-format
 msgid "Illegal Co-processor register in Instruction `%s' "
@@ -3267,110 +3768,70 @@ msgstr ""
 msgid "Illegal Co-processor special register in Instruction `%s' "
 msgstr ""
 
-#: config/tc-crx.c:1616
-msgid "Incorrect number of operands"
-msgstr ""
-
-#: config/tc-crx.c:1618
-#, c-format
-msgid "Illegal type of operand (arg %d)"
-msgstr ""
-
-#: config/tc-crx.c:1624
-#, c-format
-msgid "Operand out of range (arg %d)"
-msgstr ""
-
-#: config/tc-crx.c:1627
-#, c-format
-msgid "Operand has odd displacement (arg %d)"
-msgstr ""
-
-#: config/tc-crx.c:1630
+#: config/tc-crx.c:1636
 #, c-format
 msgid "Invalid DISPU4 operand value (arg %d)"
 msgstr ""
 
-#: config/tc-crx.c:1633
+#: config/tc-crx.c:1639
 #, c-format
 msgid "Invalid CST4 operand value (arg %d)"
 msgstr ""
 
-#: config/tc-crx.c:1636
+#: config/tc-crx.c:1642
 #, c-format
 msgid "Operand value is not within upper 64 KB (arg %d)"
 msgstr ""
 
-#: config/tc-crx.c:1640 config/tc-crx.c:1671
-#, c-format
-msgid "Illegal operand (arg %d)"
-msgstr ""
-
-#: config/tc-crx.c:1702 config/tc-crx.c:1719
-#, c-format
-msgid "Same src/dest register is used (`r%d'), result is undefined"
-msgstr ""
-
-#: config/tc-crx.c:1711
-#, c-format
-msgid "`%s' has undefined result"
-msgstr ""
-
-#: config/tc-crx.c:1773
+#: config/tc-crx.c:1779
 msgid "Invalid Register in Register List"
 msgstr ""
 
-#: config/tc-crx.c:1827
+#: config/tc-crx.c:1833
 #, c-format
 msgid "Illegal register `%s' in cop-register list"
 msgstr ""
 
-#: config/tc-crx.c:1835
+#: config/tc-crx.c:1841
 #, c-format
 msgid "Illegal register `%s' in cop-special-register list"
 msgstr ""
 
-#: config/tc-crx.c:1854
+#: config/tc-crx.c:1860
 #, c-format
 msgid "Illegal register `%s' in user register list"
 msgstr ""
 
-#: config/tc-crx.c:1873
+#: config/tc-crx.c:1879
 #, c-format
 msgid "Illegal register `%s' in register list"
 msgstr ""
 
-#: config/tc-crx.c:1879
+#: config/tc-crx.c:1885
 #, c-format
 msgid "Maximum %d bits may be set in `mask16' operand"
 msgstr ""
 
-#: config/tc-crx.c:1888
+#: config/tc-crx.c:1894
 #, c-format
 msgid "rest of line ignored; first ignored character is `%c'"
 msgstr ""
 
-#: config/tc-crx.c:1896
+#: config/tc-crx.c:1902
 #, c-format
 msgid "Illegal `mask16' operand, operation is undefined - `%s'"
 msgstr ""
 
 #. HI can't be specified without LO (and vise-versa).
-#: config/tc-crx.c:1902
+#: config/tc-crx.c:1908
 msgid "HI/LO registers should be specified together"
 msgstr ""
 
-#: config/tc-crx.c:1908
+#: config/tc-crx.c:1914
 msgid "HI/LO registers should be specified without additional registers"
 msgstr ""
 
-#. Give an error if a frag containing code is not aligned to a 2-byte
-#. boundary.
-#: config/tc-crx.c:1993 config/tc-crx.h:76
-msgid "instruction address is not a multiple of 2"
-msgstr ""
-
-#: config/tc-d10v.c:217
+#: config/tc-d10v.c:216
 #, c-format
 msgid ""
 "D10V options:\n"
@@ -3381,140 +3842,144 @@ msgid ""
 "                        instructions together.\n"
 msgstr ""
 
-#: config/tc-d10v.c:496 config/tc-d30v.c:488 config/tc-mn10200.c:1075
-#: config/tc-mn10300.c:1817 config/tc-ppc.c:2380 config/tc-s390.c:1218
-#: config/tc-v850.c:1949
+#: config/tc-d10v.c:495 config/tc-d30v.c:487 config/tc-mn10200.c:1074
+#: config/tc-mn10300.c:1816 config/tc-ppc.c:2434 config/tc-s390.c:1219
+#: config/tc-v850.c:1964 config/tc-z80.c:422
 msgid "illegal operand"
 msgstr ""
 
-#: config/tc-d10v.c:608
+#: config/tc-d10v.c:607
 msgid "operand is not an immediate"
 msgstr ""
 
-#: config/tc-d10v.c:626
+#: config/tc-d10v.c:625
 #, c-format
 msgid "operand out of range: %lu"
 msgstr ""
 
-#: config/tc-d10v.c:684
+#: config/tc-d10v.c:683
 msgid "Instruction must be executed in parallel with another instruction."
 msgstr ""
 
-#: config/tc-d10v.c:738 config/tc-d10v.c:746
+#: config/tc-d10v.c:737 config/tc-d10v.c:745
 #, c-format
 msgid "packing conflict: %s must dispatch sequentially"
 msgstr ""
 
-#: config/tc-d10v.c:845
+#: config/tc-d10v.c:844
 #, c-format
 msgid "resource conflict (R%d)"
 msgstr ""
 
-#: config/tc-d10v.c:848
+#: config/tc-d10v.c:847
 #, c-format
 msgid "resource conflict (A%d)"
 msgstr ""
 
-#: config/tc-d10v.c:850
+#: config/tc-d10v.c:849
 msgid "resource conflict (PSW)"
 msgstr ""
 
-#: config/tc-d10v.c:852
+#: config/tc-d10v.c:851
 msgid "resource conflict (C flag)"
 msgstr ""
 
-#: config/tc-d10v.c:854
+#: config/tc-d10v.c:853
 msgid "resource conflict (F flag)"
 msgstr ""
 
-#: config/tc-d10v.c:1004
+#: config/tc-d10v.c:1003
 msgid "Instruction must be executed in parallel"
 msgstr ""
 
-#: config/tc-d10v.c:1007
+#: config/tc-d10v.c:1006
 msgid "Long instructions may not be combined."
 msgstr ""
 
-#: config/tc-d10v.c:1040
+#: config/tc-d10v.c:1039
 msgid "One of these instructions may not be executed in parallel."
 msgstr ""
 
-#: config/tc-d10v.c:1044 config/tc-d30v.c:1071
+#: config/tc-d10v.c:1043 config/tc-d30v.c:1070
 msgid "Two IU instructions may not be executed in parallel"
 msgstr ""
 
-#: config/tc-d10v.c:1046 config/tc-d10v.c:1054 config/tc-d10v.c:1068
-#: config/tc-d10v.c:1083 config/tc-d30v.c:1072 config/tc-d30v.c:1081
+#: config/tc-d10v.c:1045 config/tc-d10v.c:1053 config/tc-d10v.c:1067
+#: config/tc-d10v.c:1082 config/tc-d30v.c:1071 config/tc-d30v.c:1080
 msgid "Swapping instruction order"
 msgstr ""
 
-#: config/tc-d10v.c:1052 config/tc-d30v.c:1078
+#: config/tc-d10v.c:1051 config/tc-d30v.c:1077
 msgid "Two MU instructions may not be executed in parallel"
 msgstr ""
 
-#: config/tc-d10v.c:1072 config/tc-d30v.c:1098
+#: config/tc-d10v.c:1071 config/tc-d30v.c:1097
 msgid "IU instruction may not be in the left container"
 msgstr ""
 
-#: config/tc-d10v.c:1074 config/tc-d10v.c:1089
+#: config/tc-d10v.c:1073 config/tc-d10v.c:1088
 msgid ""
 "Instruction in R container is squashed by flow control instruction in L "
 "container."
 msgstr ""
 
-#: config/tc-d10v.c:1087 config/tc-d30v.c:1109
+#: config/tc-d10v.c:1086 config/tc-d30v.c:1108
 msgid "MU instruction may not be in the right container"
 msgstr ""
 
-#: config/tc-d10v.c:1093 config/tc-d30v.c:1121
+#: config/tc-d10v.c:1092 config/tc-d30v.c:1120
 msgid "unknown execution type passed to write_2_short()"
 msgstr ""
 
-#: config/tc-d10v.c:1221 config/tc-d10v.c:1394
+#: config/tc-d10v.c:1220 config/tc-d10v.c:1393
 msgid "bad opcode or operands"
 msgstr ""
 
-#: config/tc-d10v.c:1296 config/tc-m68k.c:4625
+#: config/tc-d10v.c:1295
 msgid "value out of range"
 msgstr ""
 
-#: config/tc-d10v.c:1370
+#: config/tc-d10v.c:1369
 msgid "illegal operand - register name found where none expected"
 msgstr ""
 
-#: config/tc-d10v.c:1405
+#: config/tc-d10v.c:1404
 msgid "Register number must be EVEN"
 msgstr ""
 
-#: config/tc-d10v.c:1408
+#: config/tc-d10v.c:1407
 msgid "Unsupported use of sp"
 msgstr ""
 
-#: config/tc-d10v.c:1427
+#: config/tc-d10v.c:1426
 #, c-format
 msgid "cr%ld is a reserved control register"
 msgstr ""
 
-#: config/tc-d10v.c:1466 config/tc-d30v.c:1430
+#: config/tc-d10v.c:1599
 #, c-format
-msgid "unknown opcode: %s"
+msgid "line %d: rep or repi must include at least 4 instructions"
+msgstr ""
+
+#: config/tc-d10v.c:1779
+msgid "can't find previous opcode "
 msgstr ""
 
-#: config/tc-d10v.c:1602
+#: config/tc-d10v.c:1791
 #, c-format
-msgid "line %d: rep or repi must include at least 4 instructions"
+msgid "could not assemble: %s"
 msgstr ""
 
-#: config/tc-d10v.c:1810 config/tc-d10v.c:1832 config/tc-d30v.c:1777
+#: config/tc-d10v.c:1806 config/tc-d10v.c:1828 config/tc-d30v.c:1776
 msgid "Unable to mix instructions as specified"
 msgstr ""
 
-#: config/tc-d30v.c:150
+#: config/tc-d30v.c:149
 #, c-format
 msgid "Register name %s conflicts with symbol of the same name"
 msgstr ""
 
-#: config/tc-d30v.c:240
+#: config/tc-d30v.c:239
 #, c-format
 msgid ""
 "\n"
@@ -3528,126 +3993,131 @@ msgid ""
 "-C                      Opposite of -C.  -c is the default.\n"
 msgstr ""
 
-#: config/tc-d30v.c:402
+#: config/tc-d30v.c:401
 msgid "unexpected 12-bit reloc type"
 msgstr ""
 
-#: config/tc-d30v.c:409
+#: config/tc-d30v.c:408
 msgid "unexpected 18-bit reloc type"
 msgstr ""
 
-#: config/tc-d30v.c:659
+#: config/tc-d30v.c:658
 #, c-format
 msgid "%s NOP inserted"
 msgstr ""
 
-#: config/tc-d30v.c:660
+#: config/tc-d30v.c:659
 msgid "sequential"
 msgstr ""
 
-#: config/tc-d30v.c:660
+#: config/tc-d30v.c:659
 msgid "parallel"
 msgstr ""
 
-#: config/tc-d30v.c:1067
+#: config/tc-d30v.c:1066
 msgid "Instructions may not be executed in parallel"
 msgstr ""
 
-#: config/tc-d30v.c:1080
+#: config/tc-d30v.c:1079
 #, c-format
 msgid "Executing %s in IU may not work"
 msgstr ""
 
-#: config/tc-d30v.c:1087
+#: config/tc-d30v.c:1086
 #, c-format
 msgid "Executing %s in IU may not work in parallel execution"
 msgstr ""
 
-#: config/tc-d30v.c:1100
+#: config/tc-d30v.c:1099
 #, c-format
 msgid "special left instruction `%s' kills instruction `%s' in right container"
 msgstr ""
 
-#: config/tc-d30v.c:1111
+#: config/tc-d30v.c:1110
 #, c-format
 msgid "Executing %s in reverse serial with %s may not work"
 msgstr ""
 
-#: config/tc-d30v.c:1114
+#: config/tc-d30v.c:1113
 #, c-format
 msgid "Executing %s in IU in reverse serial may not work"
 msgstr ""
 
-#: config/tc-d30v.c:1303
+#: config/tc-d30v.c:1302
 msgid "Odd numbered register used as target of multi-register instruction"
 msgstr ""
 
-#: config/tc-d30v.c:1367 config/tc-d30v.c:1402
+#: config/tc-d30v.c:1366 config/tc-d30v.c:1401
 #, c-format
 msgid "unknown condition code: %s"
 msgstr ""
 
-#: config/tc-d30v.c:1395
+#: config/tc-d30v.c:1394
 #, c-format
 msgid "cmpu doesn't support condition code %s"
 msgstr ""
 
-#: config/tc-d30v.c:1441
+#: config/tc-d30v.c:1429
+#, c-format
+msgid "unknown opcode: %s"
+msgstr ""
+
+#: config/tc-d30v.c:1440
 #, c-format
 msgid "operands for opcode `%s' do not match any valid format"
 msgstr ""
 
-#: config/tc-d30v.c:1656 config/tc-d30v.c:1673
+#: config/tc-d30v.c:1655 config/tc-d30v.c:1672
 msgid "Cannot assemble instruction"
 msgstr ""
 
-#: config/tc-d30v.c:1658
+#: config/tc-d30v.c:1657
 msgid "First opcode is long.  Unable to mix instructions as specified."
 msgstr ""
 
-#: config/tc-d30v.c:1727
+#: config/tc-d30v.c:1726
 msgid "word of NOPs added between word multiply and load"
 msgstr ""
 
-#: config/tc-d30v.c:1729
+#: config/tc-d30v.c:1728
 msgid "word of NOPs added between word multiply and 16-bit multiply"
 msgstr ""
 
-#: config/tc-d30v.c:1761
+#: config/tc-d30v.c:1760
 msgid "Instruction uses long version, so it cannot be mixed as specified"
 msgstr ""
 
-#: config/tc-d30v.c:1888
+#: config/tc-d30v.c:1887
 #, c-format
 msgid "value too large to fit in %d bits"
 msgstr ""
 
-#: config/tc-d30v.c:1949
+#: config/tc-d30v.c:1948
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a byte"
 msgstr ""
 
-#: config/tc-d30v.c:1952
+#: config/tc-d30v.c:1951
 #, c-format
 msgid "line %d: unable to place value %lx into a byte"
 msgstr ""
 
-#: config/tc-d30v.c:1960
+#: config/tc-d30v.c:1959
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a short"
 msgstr ""
 
-#: config/tc-d30v.c:1963
+#: config/tc-d30v.c:1962
 #, c-format
 msgid "line %d: unable to place value %lx into a short"
 msgstr ""
 
-#: config/tc-d30v.c:1971
+#: config/tc-d30v.c:1970
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a quad"
 msgstr ""
 
-#: config/tc-d30v.c:2079
+#: config/tc-d30v.c:2078
 #, c-format
 msgid "Alignment too large: %d assumed"
 msgstr ""
@@ -3661,8 +4131,8 @@ msgid ".endfunc missing for previous .proc"
 msgstr ""
 
 #. Probably a memory allocation problem?  Give up now.
-#: config/tc-dlx.c:297 config/tc-hppa.c:1489 config/tc-mips.c:1415
-#: config/tc-mips.c:1467 config/tc-or32.c:210 config/tc-sparc.c:855
+#: config/tc-dlx.c:297 config/tc-hppa.c:8306 config/tc-mips.c:1764
+#: config/tc-mips.c:1816 config/tc-or32.c:211 config/tc-sparc.c:869
 msgid "Broken assembler.  No assembly attempted."
 msgstr ""
 
@@ -3681,7 +4151,7 @@ msgstr ""
 msgid "Expression Error for operand modifier %%hi/%%lo\n"
 msgstr ""
 
-#: config/tc-dlx.c:634 config/tc-or32.c:873
+#: config/tc-dlx.c:634 config/tc-or32.c:871
 #, c-format
 msgid "Invalid expression after %%%%\n"
 msgstr ""
@@ -3718,7 +4188,7 @@ msgstr ""
 msgid "failed general register sanity check."
 msgstr ""
 
-#: config/tc-dlx.c:1175 config/tc-or32.c:835
+#: config/tc-dlx.c:1175 config/tc-or32.c:833
 #, c-format
 msgid "label \"$%d\" redefined"
 msgstr ""
@@ -3727,314 +4197,315 @@ msgstr ""
 msgid "Invalid expression after # number\n"
 msgstr ""
 
-#: config/tc-fr30.c:83
+#: config/tc-fr30.c:82
 #, c-format
 msgid " FR30 specific command line options:\n"
 msgstr ""
 
-#: config/tc-fr30.c:136
+#: config/tc-fr30.c:135
 #, c-format
 msgid "Instruction %s not allowed in a delay slot."
 msgstr ""
 
-#: config/tc-frv.c:461
+#: config/tc-frv.c:460
 #, c-format
 msgid "FRV specific command line options:\n"
 msgstr ""
 
-#: config/tc-frv.c:462
+#: config/tc-frv.c:461
 #, c-format
 msgid "-G n         Data >= n bytes is in small data area\n"
 msgstr ""
 
-#: config/tc-frv.c:463
+#: config/tc-frv.c:462
 #, c-format
 msgid "-mgpr-32     Note 32 gprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:464
+#: config/tc-frv.c:463
 #, c-format
 msgid "-mgpr-64     Note 64 gprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:465
+#: config/tc-frv.c:464
 #, c-format
 msgid "-mfpr-32     Note 32 fprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:466
+#: config/tc-frv.c:465
 #, c-format
 msgid "-mfpr-64     Note 64 fprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:467
+#: config/tc-frv.c:466
 #, c-format
 msgid "-msoft-float Note software fp is used\n"
 msgstr ""
 
-#: config/tc-frv.c:468
+#: config/tc-frv.c:467
 #, c-format
 msgid "-mdword      Note stack is aligned to a 8 byte boundary\n"
 msgstr ""
 
-#: config/tc-frv.c:469
+#: config/tc-frv.c:468
 #, c-format
 msgid "-mno-dword   Note stack is aligned to a 4 byte boundary\n"
 msgstr ""
 
-#: config/tc-frv.c:470
+#: config/tc-frv.c:469
 #, c-format
 msgid "-mdouble     Note fp double insns are used\n"
 msgstr ""
 
-#: config/tc-frv.c:471
+#: config/tc-frv.c:470
 #, c-format
 msgid "-mmedia      Note media insns are used\n"
 msgstr ""
 
-#: config/tc-frv.c:472
+#: config/tc-frv.c:471
 #, c-format
 msgid "-mmuladd     Note multiply add/subtract insns are used\n"
 msgstr ""
 
-#: config/tc-frv.c:473
+#: config/tc-frv.c:472
 #, c-format
 msgid "-mpack       Note instructions are packed\n"
 msgstr ""
 
-#: config/tc-frv.c:474
+#: config/tc-frv.c:473
 #, c-format
 msgid "-mno-pack    Do not allow instructions to be packed\n"
 msgstr ""
 
-#: config/tc-frv.c:475
+#: config/tc-frv.c:474
 #, c-format
 msgid "-mpic        Note small position independent code\n"
 msgstr ""
 
-#: config/tc-frv.c:476
+#: config/tc-frv.c:475
 #, c-format
 msgid "-mPIC        Note large position independent code\n"
 msgstr ""
 
-#: config/tc-frv.c:477
+#: config/tc-frv.c:476
 #, c-format
 msgid "-mlibrary-pic Compile library for large position indepedent code\n"
 msgstr ""
 
-#: config/tc-frv.c:478
+#: config/tc-frv.c:477
 #, c-format
 msgid "-mfdpic      Assemble for the FDPIC ABI\n"
 msgstr ""
 
-#: config/tc-frv.c:479
+#: config/tc-frv.c:478
 #, c-format
 msgid "-mnopic      Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic\n"
 msgstr ""
 
-#: config/tc-frv.c:480
+#: config/tc-frv.c:479
 #, c-format
 msgid "-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"
 msgstr ""
 
-#: config/tc-frv.c:481
+#: config/tc-frv.c:480
 #, c-format
 msgid "             Record the cpu type\n"
 msgstr ""
 
-#: config/tc-frv.c:482
+#: config/tc-frv.c:481
 #, c-format
 msgid "-mtomcat-stats Print out stats for tomcat workarounds\n"
 msgstr ""
 
-#: config/tc-frv.c:483
+#: config/tc-frv.c:482
 #, c-format
 msgid "-mtomcat-debug Debug tomcat workarounds\n"
 msgstr ""
 
-#: config/tc-frv.c:1187
+#: config/tc-frv.c:1186
 msgid "VLIW packing used for -mno-pack"
 msgstr ""
 
-#: config/tc-frv.c:1197
+#: config/tc-frv.c:1196
 msgid "Instruction not supported by this architecture"
 msgstr ""
 
-#: config/tc-frv.c:1207
+#: config/tc-frv.c:1206
 msgid "VLIW packing constraint violation"
 msgstr ""
 
-#: config/tc-frv.c:1874
+#: config/tc-frv.c:1873
 #, c-format
 msgid "Relocation %s is not safe for %s"
 msgstr ""
 
-#: config/tc-h8300.c:78 config/tc-h8300.c:87 config/tc-h8300.c:97
-#: config/tc-h8300.c:107 config/tc-h8300.c:117 config/tc-h8300.c:128
-#: config/tc-h8300.c:195 config/tc-hppa.c:1449 config/tc-hppa.c:6926
-#: config/tc-hppa.c:6932 config/tc-hppa.c:6938 config/tc-hppa.c:6944
-#: config/tc-mn10300.c:1223 config/tc-mn10300.c:1228 config/tc-mn10300.c:2725
+#: config/tc-h8300.c:76 config/tc-h8300.c:85 config/tc-h8300.c:95
+#: config/tc-h8300.c:105 config/tc-h8300.c:115 config/tc-h8300.c:126
+#: config/tc-h8300.c:193 config/tc-hppa.c:6839 config/tc-hppa.c:6845
+#: config/tc-hppa.c:6851 config/tc-hppa.c:6857 config/tc-hppa.c:8264
+#: config/tc-mn10300.c:1222 config/tc-mn10300.c:1227 config/tc-mn10300.c:2729
+#: config/tc-xc16x.c:79 config/tc-xc16x.c:86 config/tc-xc16x.c:93
 msgid "could not set architecture and machine"
 msgstr ""
 
-#: config/tc-h8300.c:397 config/tc-h8300.c:405
+#: config/tc-h8300.c:395 config/tc-h8300.c:403
 msgid "Reg not valid for H8/300"
 msgstr ""
 
-#: config/tc-h8300.c:486
+#: config/tc-h8300.c:484
 msgid "invalid operand size requested"
 msgstr ""
 
-#: config/tc-h8300.c:585
+#: config/tc-h8300.c:583
 msgid "Invalid register list for ldm/stm\n"
 msgstr ""
 
-#: config/tc-h8300.c:611 config/tc-h8300.c:616 config/tc-h8300.c:623
+#: config/tc-h8300.c:609 config/tc-h8300.c:614 config/tc-h8300.c:621
 msgid "mismatch between register and suffix"
 msgstr ""
 
-#: config/tc-h8300.c:650
+#: config/tc-h8300.c:648
 msgid "address too high for vector table jmp/jsr"
 msgstr ""
 
-#: config/tc-h8300.c:677 config/tc-h8300.c:789 config/tc-h8300.c:799
+#: config/tc-h8300.c:675 config/tc-h8300.c:787 config/tc-h8300.c:797
 msgid "Wrong size pointer register for architecture."
 msgstr ""
 
-#: config/tc-h8300.c:736 config/tc-h8300.c:744 config/tc-h8300.c:773
+#: config/tc-h8300.c:734 config/tc-h8300.c:742 config/tc-h8300.c:771
 msgid "expected @(exp, reg16)"
 msgstr ""
 
-#: config/tc-h8300.c:762
+#: config/tc-h8300.c:760
 msgid "expected .L, .W or .B for register in indexed addressing mode"
 msgstr ""
 
-#: config/tc-h8300.c:956
+#: config/tc-h8300.c:954
 msgid "expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""
 msgstr ""
 
-#: config/tc-h8300.c:974 config/tc-h8300.c:983
+#: config/tc-h8300.c:972 config/tc-h8300.c:981
 msgid "expected register"
 msgstr ""
 
-#: config/tc-h8300.c:999
+#: config/tc-h8300.c:997
 msgid "expected closing paren"
 msgstr ""
 
-#: config/tc-h8300.c:1058
+#: config/tc-h8300.c:1056
 #, c-format
 msgid "can't use high part of register in operand %d"
 msgstr ""
 
-#: config/tc-h8300.c:1215
+#: config/tc-h8300.c:1213
 #, c-format
 msgid "Opcode `%s' with these operand types not available in %s mode"
 msgstr ""
 
-#: config/tc-h8300.c:1224
+#: config/tc-h8300.c:1222
 msgid "mismatch between opcode size and operand size"
 msgstr ""
 
-#: config/tc-h8300.c:1260
+#: config/tc-h8300.c:1258
 #, c-format
 msgid "operand %s0x%lx out of range."
 msgstr ""
 
-#: config/tc-h8300.c:1356
+#: config/tc-h8300.c:1354
 msgid "Can't work out size of operand.\n"
 msgstr ""
 
-#: config/tc-h8300.c:1405
+#: config/tc-h8300.c:1403
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300 mode"
 msgstr ""
 
-#: config/tc-h8300.c:1410
+#: config/tc-h8300.c:1408
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300H mode"
 msgstr ""
 
-#: config/tc-h8300.c:1416
+#: config/tc-h8300.c:1414
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300S mode"
 msgstr ""
 
-#: config/tc-h8300.c:1477 config/tc-h8300.c:1497
+#: config/tc-h8300.c:1475 config/tc-h8300.c:1495
 msgid "Need #1 or #2 here"
 msgstr ""
 
-#: config/tc-h8300.c:1492
+#: config/tc-h8300.c:1490
 msgid "#4 not valid on H8/300."
 msgstr ""
 
-#: config/tc-h8300.c:1598 config/tc-h8300.c:1680
+#: config/tc-h8300.c:1596 config/tc-h8300.c:1678
 #, c-format
 msgid "branch operand has odd offset (%lx)\n"
 msgstr ""
 
-#: config/tc-h8300.c:1718
+#: config/tc-h8300.c:1716
 msgid "destination operand must be 16 bit register"
 msgstr ""
 
-#: config/tc-h8300.c:1727
+#: config/tc-h8300.c:1725
 msgid "source operand must be 8 bit register"
 msgstr ""
 
-#: config/tc-h8300.c:1735
+#: config/tc-h8300.c:1733
 msgid "destination operand must be 16bit absolute address"
 msgstr ""
 
-#: config/tc-h8300.c:1742
+#: config/tc-h8300.c:1740
 msgid "destination operand must be 8 bit register"
 msgstr ""
 
-#: config/tc-h8300.c:1750
+#: config/tc-h8300.c:1748
 msgid "source operand must be 16bit absolute address"
 msgstr ""
 
 #. This seems more sane than saying "too many operands".  We'll
 #. get here only if the trailing trash starts with a comma.
 #. Types or values of args don't match.
-#: config/tc-h8300.c:1758 config/tc-mmix.c:473 config/tc-mmix.c:485
-#: config/tc-mmix.c:2526 config/tc-mmix.c:2550 config/tc-mmix.c:2823
-#: config/tc-or32.c:527
+#: config/tc-h8300.c:1756 config/tc-mmix.c:472 config/tc-mmix.c:484
+#: config/tc-mmix.c:2525 config/tc-mmix.c:2549 config/tc-mmix.c:2822
+#: config/tc-or32.c:528
 msgid "invalid operands"
 msgstr ""
 
-#: config/tc-h8300.c:1789
+#: config/tc-h8300.c:1787
 msgid "operand/size mis-match"
 msgstr ""
 
-#: config/tc-h8300.c:1885 config/tc-mips.c:9358 config/tc-sh64.c:2795
-#: config/tc-sh.c:2838 config/tc-z8k.c:1204
+#: config/tc-h8300.c:1883 config/tc-mips.c:9767 config/tc-sh64.c:2795
+#: config/tc-sh.c:2925 config/tc-z8k.c:1226
 msgid "unknown opcode"
 msgstr ""
 
-#: config/tc-h8300.c:1918
+#: config/tc-h8300.c:1916
 msgid "invalid operand in ldm"
 msgstr ""
 
-#: config/tc-h8300.c:1927
+#: config/tc-h8300.c:1925
 msgid "invalid operand in stm"
 msgstr ""
 
-#: config/tc-h8300.c:2093
+#: config/tc-h8300.c:2091
 #, c-format
 msgid "call to tc_aout_fix_to_chars \n"
 msgstr ""
 
-#: config/tc-h8300.c:2102
+#: config/tc-h8300.c:2100 config/tc-xc16x.c:389
 #, c-format
 msgid "call to md_convert_frag \n"
 msgstr ""
 
-#: config/tc-h8300.c:2146
+#: config/tc-h8300.c:2144 config/tc-xc16x.c:293
 #, c-format
 msgid "call tomd_estimate_size_before_relax \n"
 msgstr ""
 
-#: config/tc-h8300.c:2197 config/tc-mcore.c:2282 config/tc-pj.c:538
-#: config/tc-sh.c:4270
+#: config/tc-h8300.c:2195 config/tc-mcore.c:2265 config/tc-pj.c:538
+#: config/tc-sh.c:4401 config/tc-xc16x.c:357
 #, c-format
 msgid "Cannot represent relocation type %s"
 msgstr ""
@@ -4043,619 +4514,625 @@ msgstr ""
 #. IGNORE is used to suppress the error message.
 #. Variant of CHECK_FIELD for use in md_apply_fix and other places where
 #. the current file and line number are not valid.
-#: config/tc-hppa.c:1176 config/tc-hppa.c:1190
+#: config/tc-hppa.c:1015 config/tc-hppa.c:1029
 #, c-format
 msgid "Field out of range [%d..%d] (%d)."
 msgstr ""
 
 #. Simple alignment checking for FIELD against ALIGN (a power of two).
 #. IGNORE is used to suppress the error message.
-#: config/tc-hppa.c:1204
+#: config/tc-hppa.c:1043
 #, c-format
 msgid "Field not properly aligned [%d] (%d)."
 msgstr ""
 
-#: config/tc-hppa.c:1233
+#: config/tc-hppa.c:1092
 msgid "Missing .exit\n"
 msgstr ""
 
-#: config/tc-hppa.c:1236
+#: config/tc-hppa.c:1095
 msgid "Missing .procend\n"
 msgstr ""
 
-#: config/tc-hppa.c:1422
+#: config/tc-hppa.c:1277
 #, c-format
 msgid "Invalid field selector.  Assuming F%%."
 msgstr ""
 
-#: config/tc-hppa.c:1455
-msgid "-R option not supported on this target."
-msgstr ""
-
-#: config/tc-hppa.c:1471 config/tc-sparc.c:811 config/tc-sparc.c:847
-#, c-format
-msgid "Internal error: can't hash `%s': %s\n"
+#: config/tc-hppa.c:1304
+msgid "Bad segment in expression."
 msgstr ""
 
-#: config/tc-hppa.c:1479 config/tc-i860.c:238
+#: config/tc-hppa.c:1329
 #, c-format
-msgid "internal error: losing opcode: `%s' \"%s\"\n"
-msgstr ""
-
-#: config/tc-hppa.c:1550 config/tc-hppa.c:7065 config/tc-hppa.c:7122
-msgid "Missing function name for .PROC (corrupted label chain)"
-msgstr ""
-
-#: config/tc-hppa.c:1553 config/tc-hppa.c:7125
-msgid "Missing function name for .PROC"
+msgid "Invalid Nullification: (%c)"
 msgstr ""
 
-#: config/tc-hppa.c:1857
-msgid "Invalid Indexed Load Completer."
+#: config/tc-hppa.c:1438
+msgid "Cannot handle fixup"
 msgstr ""
 
-#: config/tc-hppa.c:1862
-msgid "Invalid Indexed Load Completer Syntax."
+#: config/tc-hppa.c:1736
+#, c-format
+msgid "  -Q                      ignored\n"
 msgstr ""
 
-#: config/tc-hppa.c:1896
-msgid "Invalid Short Load/Store Completer."
+#: config/tc-hppa.c:1740
+#, c-format
+msgid "  -c                      print a warning if a comment is found\n"
 msgstr ""
 
-#: config/tc-hppa.c:1956 config/tc-hppa.c:1961
-msgid "Invalid Store Bytes Short Completer"
+#: config/tc-hppa.c:1806
+#, c-format
+msgid "no hppa_fixup entry for fixup type 0x%x"
 msgstr ""
 
-#: config/tc-hppa.c:2272 config/tc-hppa.c:2278
-msgid "Invalid left/right combination completer"
+#: config/tc-hppa.c:1985
+msgid "Unknown relocation encountered in md_apply_fix."
 msgstr ""
 
-#: config/tc-hppa.c:2327 config/tc-hppa.c:2334
-msgid "Invalid permutation completer"
+#: config/tc-hppa.c:2173 config/tc-hppa.c:2198
+#, c-format
+msgid "Undefined register: '%s'."
 msgstr ""
 
-#: config/tc-hppa.c:2434
+#: config/tc-hppa.c:2232
 #, c-format
-msgid "Invalid Add Condition: %s"
+msgid "Non-absolute symbol: '%s'."
 msgstr ""
 
-#: config/tc-hppa.c:2445 config/tc-hppa.c:2455
-msgid "Invalid Add and Branch Condition"
+#: config/tc-hppa.c:2247
+#, c-format
+msgid "Undefined absolute constant: '%s'."
 msgstr ""
 
-#: config/tc-hppa.c:2476 config/tc-hppa.c:2613
-msgid "Invalid Compare/Subtract Condition"
+#: config/tc-hppa.c:2278 config/tc-hppa.c:5697
+msgid "could not update architecture and machine"
 msgstr ""
 
-#: config/tc-hppa.c:2516
+#: config/tc-hppa.c:2316
 #, c-format
-msgid "Invalid Bit Branch Condition: %c"
+msgid "Invalid FP Compare Condition: %s"
 msgstr ""
 
-#: config/tc-hppa.c:2601
+#: config/tc-hppa.c:2371
 #, c-format
-msgid "Invalid Compare/Subtract Condition: %s"
+msgid "Invalid FTEST completer: %s"
 msgstr ""
 
-#: config/tc-hppa.c:2628
-msgid "Invalid Compare and Branch Condition"
+#: config/tc-hppa.c:2437 config/tc-hppa.c:2474
+#, c-format
+msgid "Invalid FP Operand Format: %3s"
 msgstr ""
 
-#: config/tc-hppa.c:2724
-msgid "Invalid Logical Instruction Condition."
+#: config/tc-hppa.c:2609
+msgid "Bad segment (should be absolute)."
 msgstr ""
 
-#: config/tc-hppa.c:2779
-msgid "Invalid Shift/Extract/Deposit Condition."
+#: config/tc-hppa.c:2635
+#, c-format
+msgid "Invalid argument location: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:2891
-msgid "Invalid Unit Instruction Condition."
+#: config/tc-hppa.c:2664
+#, c-format
+msgid "Invalid argument description: %d"
 msgstr ""
 
-#: config/tc-hppa.c:3270 config/tc-hppa.c:3302 config/tc-hppa.c:3333
-#: config/tc-hppa.c:3363
-msgid "Branch to unaligned address"
+#: config/tc-hppa.c:3490
+msgid "Invalid Indexed Load Completer."
 msgstr ""
 
-#: config/tc-hppa.c:3541
-msgid "Invalid SFU identifier"
+#: config/tc-hppa.c:3495
+msgid "Invalid Indexed Load Completer Syntax."
 msgstr ""
 
-#: config/tc-hppa.c:3591
-msgid "Invalid COPR identifier"
+#: config/tc-hppa.c:3529
+msgid "Invalid Short Load/Store Completer."
 msgstr ""
 
-#: config/tc-hppa.c:3720
-msgid "Invalid Floating Point Operand Format."
+#: config/tc-hppa.c:3589 config/tc-hppa.c:3594
+msgid "Invalid Store Bytes Short Completer"
 msgstr ""
 
-#: config/tc-hppa.c:3837 config/tc-hppa.c:3857 config/tc-hppa.c:3877
-#: config/tc-hppa.c:3897 config/tc-hppa.c:3917
-msgid "Invalid register for single precision fmpyadd or fmpysub"
+#: config/tc-hppa.c:3905 config/tc-hppa.c:3911
+msgid "Invalid left/right combination completer"
 msgstr ""
 
-#: config/tc-hppa.c:3968 config/tc-hppa.c:4928
-msgid "could not update architecture and machine"
+#: config/tc-hppa.c:3960 config/tc-hppa.c:3967
+msgid "Invalid permutation completer"
 msgstr ""
 
-#: config/tc-hppa.c:3985
+#: config/tc-hppa.c:4067
 #, c-format
-msgid "Invalid operands %s"
+msgid "Invalid Add Condition: %s"
 msgstr ""
 
-#: config/tc-hppa.c:4103
-msgid "Cannot handle fixup"
+#: config/tc-hppa.c:4078 config/tc-hppa.c:4088
+msgid "Invalid Add and Branch Condition"
 msgstr ""
 
-#: config/tc-hppa.c:4404
-#, c-format
-msgid "  -Q                      ignored\n"
+#: config/tc-hppa.c:4109 config/tc-hppa.c:4246
+msgid "Invalid Compare/Subtract Condition"
 msgstr ""
 
-#: config/tc-hppa.c:4408
+#: config/tc-hppa.c:4149
 #, c-format
-msgid "  -c                      print a warning if a comment is found\n"
+msgid "Invalid Bit Branch Condition: %c"
 msgstr ""
 
-#: config/tc-hppa.c:4479
+#: config/tc-hppa.c:4234
 #, c-format
-msgid "no hppa_fixup entry for fixup type 0x%x"
+msgid "Invalid Compare/Subtract Condition: %s"
 msgstr ""
 
-#: config/tc-hppa.c:4650
-msgid "Unknown relocation encountered in md_apply_fix."
+#: config/tc-hppa.c:4261
+msgid "Invalid Compare and Branch Condition"
 msgstr ""
 
-#: config/tc-hppa.c:4792 config/tc-hppa.c:4817
-#, c-format
-msgid "Undefined register: '%s'."
+#: config/tc-hppa.c:4357
+msgid "Invalid Logical Instruction Condition."
 msgstr ""
 
-#: config/tc-hppa.c:4851
-#, c-format
-msgid "Non-absolute symbol: '%s'."
+#: config/tc-hppa.c:4412
+msgid "Invalid Shift/Extract/Deposit Condition."
 msgstr ""
 
-#: config/tc-hppa.c:4866
-#, c-format
-msgid "Undefined absolute constant: '%s'."
+#: config/tc-hppa.c:4524
+msgid "Invalid Unit Instruction Condition."
 msgstr ""
 
-#: config/tc-hppa.c:4967
-#, c-format
-msgid "Invalid FP Compare Condition: %s"
+#: config/tc-hppa.c:4999 config/tc-hppa.c:5031 config/tc-hppa.c:5062
+#: config/tc-hppa.c:5092
+msgid "Branch to unaligned address"
 msgstr ""
 
-#: config/tc-hppa.c:5023
-#, c-format
-msgid "Invalid FTEST completer: %s"
+#: config/tc-hppa.c:5270
+msgid "Invalid SFU identifier"
 msgstr ""
 
-#: config/tc-hppa.c:5090 config/tc-hppa.c:5128
-#, c-format
-msgid "Invalid FP Operand Format: %3s"
+#: config/tc-hppa.c:5320
+msgid "Invalid COPR identifier"
 msgstr ""
 
-#: config/tc-hppa.c:5207
-msgid "Bad segment in expression."
+#: config/tc-hppa.c:5449
+msgid "Invalid Floating Point Operand Format."
 msgstr ""
 
-#: config/tc-hppa.c:5266
-msgid "Bad segment (should be absolute)."
+#: config/tc-hppa.c:5566 config/tc-hppa.c:5586 config/tc-hppa.c:5606
+#: config/tc-hppa.c:5626 config/tc-hppa.c:5646
+msgid "Invalid register for single precision fmpyadd or fmpysub"
 msgstr ""
 
-#: config/tc-hppa.c:5309
+#: config/tc-hppa.c:5714
 #, c-format
-msgid "Invalid argument location: %s\n"
+msgid "Invalid operands %s"
 msgstr ""
 
-#: config/tc-hppa.c:5340
-#, c-format
-msgid "Invalid argument description: %d"
+#: config/tc-hppa.c:5769 config/tc-hppa.c:6975 config/tc-hppa.c:7030
+msgid "Missing function name for .PROC (corrupted label chain)"
 msgstr ""
 
-#: config/tc-hppa.c:5363
-#, c-format
-msgid "Invalid Nullification: (%c)"
+#: config/tc-hppa.c:5772 config/tc-hppa.c:7033
+msgid "Missing function name for .PROC"
 msgstr ""
 
-#: config/tc-hppa.c:5960
+#: config/tc-hppa.c:5831
 msgid "Argument to .BLOCK/.BLOCKZ must be between 0 and 0x3fffffff"
 msgstr ""
 
-#: config/tc-hppa.c:6076
+#: config/tc-hppa.c:5927
 #, c-format
 msgid "Invalid .CALL argument: %s"
 msgstr ""
 
-#: config/tc-hppa.c:6198
+#: config/tc-hppa.c:6061
 msgid ".callinfo is not within a procedure definition"
 msgstr ""
 
-#: config/tc-hppa.c:6218
+#: config/tc-hppa.c:6081
 #, c-format
 msgid "FRAME parameter must be a multiple of 8: %d\n"
 msgstr ""
 
-#: config/tc-hppa.c:6237
+#: config/tc-hppa.c:6100
 msgid "Value for ENTRY_GR must be in the range 3..18\n"
 msgstr ""
 
-#: config/tc-hppa.c:6249
+#: config/tc-hppa.c:6112
 msgid "Value for ENTRY_FR must be in the range 12..21\n"
 msgstr ""
 
-#: config/tc-hppa.c:6259
+#: config/tc-hppa.c:6122
 msgid "Value for ENTRY_SR must be 3\n"
 msgstr ""
 
-#: config/tc-hppa.c:6315
+#: config/tc-hppa.c:6178
 #, c-format
 msgid "Invalid .CALLINFO argument: %s"
 msgstr ""
 
-#: config/tc-hppa.c:6427
+#: config/tc-hppa.c:6288
 msgid "The .ENTER pseudo-op is not supported"
 msgstr ""
 
-#: config/tc-hppa.c:6443
+#: config/tc-hppa.c:6304
 msgid "Misplaced .entry. Ignored."
 msgstr ""
 
-#: config/tc-hppa.c:6447
+#: config/tc-hppa.c:6308
 msgid "Missing .callinfo."
 msgstr ""
 
-#: config/tc-hppa.c:6513
+#: config/tc-hppa.c:6372
 msgid ".REG expression must be a register"
 msgstr ""
 
-#: config/tc-hppa.c:6529
+#: config/tc-hppa.c:6388
 msgid "bad or irreducible absolute expression; zero assumed"
 msgstr ""
 
-#: config/tc-hppa.c:6540
+#: config/tc-hppa.c:6399
 msgid ".REG must use a label"
 msgstr ""
 
-#: config/tc-hppa.c:6542
+#: config/tc-hppa.c:6401
 msgid ".EQU must use a label"
 msgstr ""
 
-#: config/tc-hppa.c:6595
+#: config/tc-hppa.c:6463
+#, c-format
+msgid "Symbol '%s' could not be created."
+msgstr ""
+
+#: config/tc-hppa.c:6467
+msgid "No memory for symbol name."
+msgstr ""
+
+#: config/tc-hppa.c:6516
 msgid ".EXIT must appear within a procedure"
 msgstr ""
 
-#: config/tc-hppa.c:6599
+#: config/tc-hppa.c:6520
 msgid "Missing .callinfo"
 msgstr ""
 
-#: config/tc-hppa.c:6603
+#: config/tc-hppa.c:6524
 msgid "No .ENTRY for this .EXIT"
 msgstr ""
 
-#: config/tc-hppa.c:6630
+#: config/tc-hppa.c:6564
 #, c-format
-msgid "Cannot define export symbol: %s\n"
+msgid "Using ENTRY rather than CODE in export directive for %s"
 msgstr ""
 
-#: config/tc-hppa.c:6688
+#: config/tc-hppa.c:6681
 #, c-format
-msgid "Using ENTRY rather than CODE in export directive for %s"
+msgid "Undefined .EXPORT/.IMPORT argument (ignored): %s"
 msgstr ""
 
-#: config/tc-hppa.c:6805
+#: config/tc-hppa.c:6705
 #, c-format
-msgid "Undefined .EXPORT/.IMPORT argument (ignored): %s"
+msgid "Cannot define export symbol: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:6887
+#: config/tc-hppa.c:6802
 msgid "Missing label name on .LABEL"
 msgstr ""
 
-#: config/tc-hppa.c:6892
+#: config/tc-hppa.c:6807
 msgid "extra .LABEL arguments ignored."
 msgstr ""
 
-#: config/tc-hppa.c:6909
+#: config/tc-hppa.c:6823
 msgid "The .LEAVE pseudo-op is not supported"
 msgstr ""
 
-#: config/tc-hppa.c:6948
+#: config/tc-hppa.c:6861
 msgid "Unrecognized .LEVEL argument\n"
 msgstr ""
 
-#: config/tc-hppa.c:6984
+#: config/tc-hppa.c:6895
 #, c-format
 msgid "Cannot define static symbol: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:7019
+#: config/tc-hppa.c:6929
 msgid "Nested procedures"
 msgstr ""
 
-#: config/tc-hppa.c:7029
+#: config/tc-hppa.c:6939
 msgid "Cannot allocate unwind descriptor\n"
 msgstr ""
 
-#: config/tc-hppa.c:7129
+#: config/tc-hppa.c:7037
 msgid "misplaced .procend"
 msgstr ""
 
-#: config/tc-hppa.c:7132
+#: config/tc-hppa.c:7040
 msgid "Missing .callinfo for this procedure"
 msgstr ""
 
-#: config/tc-hppa.c:7135
+#: config/tc-hppa.c:7043
 msgid "Missing .EXIT for a .ENTRY"
 msgstr ""
 
-#: config/tc-hppa.c:7173
+#: config/tc-hppa.c:7080
 msgid "Not in a space.\n"
 msgstr ""
 
-#: config/tc-hppa.c:7176
+#: config/tc-hppa.c:7083
 msgid "Not in a subspace.\n"
 msgstr ""
 
-#: config/tc-hppa.c:7267
+#: config/tc-hppa.c:7172
 msgid "Invalid .SPACE argument"
 msgstr ""
 
-#: config/tc-hppa.c:7314
+#: config/tc-hppa.c:7218
 msgid "Can't change spaces within a procedure definition. Ignored"
 msgstr ""
 
-#: config/tc-hppa.c:7443
+#: config/tc-hppa.c:7346
 #, c-format
 msgid "Undefined space: '%s' Assuming space number = 0."
 msgstr ""
 
-#: config/tc-hppa.c:7467
+#: config/tc-hppa.c:7369
 msgid "Must be in a space before changing or declaring subspaces.\n"
 msgstr ""
 
-#: config/tc-hppa.c:7471
+#: config/tc-hppa.c:7373
 msgid "Can't change subspaces within a procedure definition. Ignored"
 msgstr ""
 
-#: config/tc-hppa.c:7507
+#: config/tc-hppa.c:7409
 msgid "Parameters of an existing subspace can't be modified"
 msgstr ""
 
-#: config/tc-hppa.c:7559
+#: config/tc-hppa.c:7461
 msgid "Alignment must be a power of 2"
 msgstr ""
 
-#: config/tc-hppa.c:7606
+#: config/tc-hppa.c:7508
 msgid "FIRST not supported as a .SUBSPACE argument"
 msgstr ""
 
-#: config/tc-hppa.c:7608
+#: config/tc-hppa.c:7510
 msgid "Invalid .SUBSPACE argument"
 msgstr ""
 
-#: config/tc-hppa.c:7797
+#: config/tc-hppa.c:7699
 #, c-format
 msgid "Internal error: Unable to find containing space for %s."
 msgstr ""
 
-#: config/tc-hppa.c:7837
+#: config/tc-hppa.c:7737
 #, c-format
 msgid "Out of memory: could not allocate new space chain entry: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:7926
+#: config/tc-hppa.c:7825
 #, c-format
 msgid "Out of memory: could not allocate new subspace chain entry: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:8662
+#: config/tc-hppa.c:8270
+msgid "-R option not supported on this target."
+msgstr ""
+
+#: config/tc-hppa.c:8287 config/tc-sparc.c:825 config/tc-sparc.c:861
 #, c-format
-msgid "Symbol '%s' could not be created."
+msgid "Internal error: can't hash `%s': %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:8666
-msgid "No memory for symbol name."
+#: config/tc-hppa.c:8296 config/tc-i860.c:236
+#, c-format
+msgid "internal error: losing opcode: `%s' \"%s\"\n"
 msgstr ""
 
-#: config/tc-i386.c:721
+#: config/tc-i386.c:983
 #, c-format
 msgid "%s shortened to %s"
 msgstr ""
 
-#: config/tc-i386.c:777
+#: config/tc-i386.c:1053
 msgid "same type of prefix used twice"
 msgstr ""
 
-#: config/tc-i386.c:795
+#: config/tc-i386.c:1066
 msgid "64bit mode not supported on this CPU."
 msgstr ""
 
-#: config/tc-i386.c:799
+#: config/tc-i386.c:1070
 msgid "32bit mode not supported on this CPU."
 msgstr ""
 
-#: config/tc-i386.c:832
+#: config/tc-i386.c:1101
 msgid "bad argument to syntax directive."
 msgstr ""
 
-#: config/tc-i386.c:884
+#: config/tc-i386.c:1161
 #, c-format
 msgid "no such architecture: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:889
+#: config/tc-i386.c:1166
 msgid "missing cpu architecture"
 msgstr ""
 
-#: config/tc-i386.c:903
+#: config/tc-i386.c:1180
 #, c-format
 msgid "no such architecture modifier: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:919 config/tc-i386.c:5342
+#: config/tc-i386.c:1196 config/tc-i386.c:6133 config/tc-i386.c:6167
 msgid "Unknown architecture"
 msgstr ""
 
-#: config/tc-i386.c:1247
+#: config/tc-i386.c:1528
 #, c-format
 msgid "unknown relocation (%u)"
 msgstr ""
 
-#: config/tc-i386.c:1249
+#: config/tc-i386.c:1530
 #, c-format
 msgid "%u-byte relocation cannot be applied to %u-byte field"
 msgstr ""
 
-#: config/tc-i386.c:1253
+#: config/tc-i386.c:1534
 msgid "non-pc-relative relocation for pc-relative field"
 msgstr ""
 
-#: config/tc-i386.c:1258
+#: config/tc-i386.c:1539
 msgid "relocated field and relocation type differ in signedness"
 msgstr ""
 
-#: config/tc-i386.c:1267
+#: config/tc-i386.c:1548
 msgid "there are no unsigned pc-relative relocations"
 msgstr ""
 
-#: config/tc-i386.c:1275
+#: config/tc-i386.c:1556
 #, c-format
 msgid "cannot do %u byte pc-relative relocation"
 msgstr ""
 
-#: config/tc-i386.c:1292
+#: config/tc-i386.c:1573
 #, c-format
 msgid "cannot do %s %u byte relocation"
 msgstr ""
 
-#: config/tc-i386.c:1496 config/tc-i386.c:2527
+#: config/tc-i386.c:1790 config/tc-i386.c:2963
 #, c-format
 msgid "ambiguous operand size for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1544
+#: config/tc-i386.c:1838
 #, c-format
-msgid "can't use register '%%%s' as operand %d in '%s'."
+msgid "can't use register '%s%s' as operand %d in '%s'."
 msgstr ""
 
 #. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.
-#: config/tc-i386.c:1573
+#: config/tc-i386.c:1870
 #, c-format
 msgid "translating to `%sp'"
 msgstr ""
 
-#: config/tc-i386.c:1618
+#: config/tc-i386.c:1915
 #, c-format
-msgid "can't encode register '%%%s' in an instruction requiring REX prefix."
+msgid "can't encode register '%s%s' in an instruction requiring REX prefix."
 msgstr ""
 
-#: config/tc-i386.c:1659 config/tc-i386.c:1767
+#: config/tc-i386.c:1955 config/tc-i386.c:2063
 #, c-format
 msgid "no such instruction: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1670 config/tc-i386.c:1799
+#: config/tc-i386.c:1966 config/tc-i386.c:2095
 #, c-format
 msgid "invalid character %s in mnemonic"
 msgstr ""
 
-#: config/tc-i386.c:1677
+#: config/tc-i386.c:1973
 msgid "expecting prefix; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1679
+#: config/tc-i386.c:1975
 msgid "expecting mnemonic; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1695 config/tc-i386.c:1818
+#: config/tc-i386.c:1991 config/tc-i386.c:2114
 #, c-format
 msgid "`%s' is only supported in 64-bit mode"
 msgstr ""
 
-#: config/tc-i386.c:1696 config/tc-i386.c:1817
+#: config/tc-i386.c:1992 config/tc-i386.c:2113
 #, c-format
 msgid "`%s' is not supported in 64-bit mode"
 msgstr ""
 
-#: config/tc-i386.c:1707
+#: config/tc-i386.c:2003
 #, c-format
 msgid "redundant %s prefix"
 msgstr ""
 
-#: config/tc-i386.c:1824
+#: config/tc-i386.c:2120
 #, c-format
 msgid "`%s' is not supported on `%s%s'"
 msgstr ""
 
-#: config/tc-i386.c:1831
+#: config/tc-i386.c:2127
 msgid "use .code16 to ensure correct addressing mode"
 msgstr ""
 
-#: config/tc-i386.c:1844
+#: config/tc-i386.c:2140
 #, c-format
 msgid "expecting string instruction after `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1878
+#: config/tc-i386.c:2172
 #, c-format
 msgid "invalid character %s before operand %d"
 msgstr ""
 
-#: config/tc-i386.c:1892
+#: config/tc-i386.c:2186
 #, c-format
 msgid "unbalanced parenthesis in operand %d."
 msgstr ""
 
-#: config/tc-i386.c:1895
+#: config/tc-i386.c:2189
 #, c-format
 msgid "unbalanced brackets in operand %d."
 msgstr ""
 
-#: config/tc-i386.c:1904
+#: config/tc-i386.c:2198
 #, c-format
 msgid "invalid character %s in operand %d"
 msgstr ""
 
-#: config/tc-i386.c:1931
+#: config/tc-i386.c:2225
 #, c-format
 msgid "spurious operands; (%d operands/instruction max)"
 msgstr ""
 
-#: config/tc-i386.c:1954
+#: config/tc-i386.c:2248
 msgid "expecting operand after ','; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1959
+#: config/tc-i386.c:2253
 msgid "expecting operand before ','; got nothing"
 msgstr ""
 
 #. We found no match.
-#: config/tc-i386.c:2336
+#: config/tc-i386.c:2741
 #, c-format
 msgid "suffix or operands invalid for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:2347
+#: config/tc-i386.c:2752
 #, c-format
 msgid "indirect %s without `*'"
 msgstr ""
 
 #. Warn them that a data or address size prefix doesn't
 #. affect assembly of the next line of code.
-#: config/tc-i386.c:2355
+#: config/tc-i386.c:2760
 #, c-format
 msgid "stand-alone `%s' prefix"
 msgstr ""
 
-#: config/tc-i386.c:2384 config/tc-i386.c:2399
+#: config/tc-i386.c:2794 config/tc-i386.c:2809
 #, c-format
 msgid "`%s' operand %d must use `%%es' segment"
 msgstr ""
 
-#: config/tc-i386.c:2509
+#. We have to know the operand size for crc32.
+#: config/tc-i386.c:2862
+#, c-format
+msgid "ambiguous memory operand size for `%s`"
+msgstr ""
+
+#: config/tc-i386.c:2944
 msgid ""
 "no instruction mnemonic suffix given and no register operands; can't size "
 "instruction"
@@ -4663,385 +5140,444 @@ msgstr ""
 
 #. Prohibit these changes in the 64bit mode, since the
 #. lowering is more complicated.
-#: config/tc-i386.c:2610 config/tc-i386.c:2669 config/tc-i386.c:2686
-#: config/tc-i386.c:2718 config/tc-i386.c:2751
+#: config/tc-i386.c:3068 config/tc-i386.c:3131 config/tc-i386.c:3150
+#: config/tc-i386.c:3183 config/tc-i386.c:3217
 #, c-format
-msgid "Incorrect register `%%%s' used with `%c' suffix"
+msgid "Incorrect register `%s%s' used with `%c' suffix"
 msgstr ""
 
-#: config/tc-i386.c:2618 config/tc-i386.c:2676 config/tc-i386.c:2758
+#: config/tc-i386.c:3076 config/tc-i386.c:3138 config/tc-i386.c:3224
 #, c-format
-msgid "using `%%%s' instead of `%%%s' due to `%c' suffix"
+msgid "using `%s%s' instead of `%s%s' due to `%c' suffix"
 msgstr ""
 
-#: config/tc-i386.c:2633 config/tc-i386.c:2654 config/tc-i386.c:2705
-#: config/tc-i386.c:2736
+#: config/tc-i386.c:3093 config/tc-i386.c:3115 config/tc-i386.c:3169
+#: config/tc-i386.c:3201
 #, c-format
-msgid "`%%%s' not allowed with `%s%c'"
+msgid "`%s%s' not allowed with `%s%c'"
 msgstr ""
 
-#: config/tc-i386.c:2799
+#: config/tc-i386.c:3267
 msgid "no instruction mnemonic suffix given; can't determine immediate size"
 msgstr ""
 
-#: config/tc-i386.c:2832
+#: config/tc-i386.c:3301
 #, c-format
 msgid ""
 "no instruction mnemonic suffix given; can't determine immediate size %x %c"
 msgstr ""
 
-#. Reversed arguments on faddp, fsubp, etc.
-#: config/tc-i386.c:2881
+#: config/tc-i386.c:3339
 #, c-format
-msgid "translating to `%s %%%s,%%%s'"
+msgid "the last operand of `%s' must be `%sxmm0'"
 msgstr ""
 
-#. Extraneous `l' suffix on fp insn.
-#: config/tc-i386.c:2888
+#: config/tc-i386.c:3342
 #, c-format
-msgid "translating to `%s %%%s'"
+msgid "the first operand of `%s' must be `%sxmm0'"
 msgstr ""
 
-#: config/tc-i386.c:2906
+#: config/tc-i386.c:3379
 #, c-format
 msgid "you can't `pop %%cs'"
 msgstr ""
 
-#: config/tc-i386.c:2927
+#. Reversed arguments on faddp, fsubp, etc.
+#: config/tc-i386.c:3401
+#, c-format
+msgid "translating to `%s %s%s,%s%s'"
+msgstr ""
+
+#. Extraneous `l' suffix on fp insn.
+#: config/tc-i386.c:3408
+#, c-format
+msgid "translating to `%s %s%s'"
+msgstr ""
+
+#: config/tc-i386.c:3436
 #, c-format
 msgid "segment override on `%s' is ineffectual"
 msgstr ""
 
-#: config/tc-i386.c:3236 config/tc-i386.c:3330 config/tc-i386.c:3375
+#: config/tc-i386.c:3777 config/tc-i386.c:3871 config/tc-i386.c:3916
 msgid "skipping prefixes on this instruction"
 msgstr ""
 
-#: config/tc-i386.c:3395
+#: config/tc-i386.c:3936
 msgid "16-bit jump out of range"
 msgstr ""
 
-#: config/tc-i386.c:3404
+#: config/tc-i386.c:3945
 #, c-format
 msgid "can't handle non absolute segment in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3897
+#: config/tc-i386.c:4501
 #, c-format
 msgid "@%s reloc is not supported with %d-bit output format"
 msgstr ""
 
-#: config/tc-i386.c:3986
-msgid "only 1 or 2 immediate operands are allowed"
+#: config/tc-i386.c:4585
+#, c-format
+msgid "at most %d immediate operands are allowed"
 msgstr ""
 
-#: config/tc-i386.c:4007 config/tc-i386.c:4218
+#: config/tc-i386.c:4607 config/tc-i386.c:4824
 #, c-format
 msgid "junk `%s' after expression"
 msgstr ""
 
 #. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:4016
+#: config/tc-i386.c:4616
 #, c-format
 msgid "missing or invalid immediate expression `%s' taken as 0"
 msgstr ""
 
-#: config/tc-i386.c:4041 config/tc-i386.c:4277
+#: config/tc-i386.c:4642 config/tc-i386.c:4883
 #, c-format
 msgid "unimplemented segment %s in operand"
 msgstr ""
 
-#: config/tc-i386.c:4088
+#: config/tc-i386.c:4648
+#, c-format
+msgid "illegal immediate register operand %s"
+msgstr ""
+
+#: config/tc-i386.c:4691
 #, c-format
 msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4097
+#: config/tc-i386.c:4700
 #, c-format
 msgid "scale factor of %d without an index register"
 msgstr ""
 
-#: config/tc-i386.c:4236
+#: config/tc-i386.c:4723
+#, c-format
+msgid "at most %d displacement operands are allowed"
+msgstr ""
+
+#: config/tc-i386.c:4842
 #, c-format
 msgid "bad expression used with @%s"
 msgstr ""
 
-#: config/tc-i386.c:4386
+#: config/tc-i386.c:4990
 #, c-format
 msgid "`%s' is not a valid base/index expression"
 msgstr ""
 
-#: config/tc-i386.c:4390
+#: config/tc-i386.c:4994
 #, c-format
 msgid "`%s' is not a valid %s bit base/index expression"
 msgstr ""
 
-#: config/tc-i386.c:4464
+#: config/tc-i386.c:5066
 #, c-format
 msgid "bad memory operand `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4479
+#: config/tc-i386.c:5081
 #, c-format
 msgid "junk `%s' after register"
 msgstr ""
 
-#: config/tc-i386.c:4488 config/tc-i386.c:4603 config/tc-i386.c:4641
+#: config/tc-i386.c:5090 config/tc-i386.c:5206 config/tc-i386.c:5247
 #, c-format
 msgid "bad register name `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4496
+#: config/tc-i386.c:5098
 msgid "immediate operand illegal with absolute jump"
 msgstr ""
 
-#: config/tc-i386.c:4518
+#: config/tc-i386.c:5120
 #, c-format
 msgid "too many memory references for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4596
+#: config/tc-i386.c:5198
 #, c-format
 msgid "expecting `,' or `)' after index register in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4620
+#: config/tc-i386.c:5223
 #, c-format
 msgid "expecting `)' after scale factor in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4627
+#: config/tc-i386.c:5231
 #, c-format
 msgid "expecting index register or scale factor after `,'; got '%c'"
 msgstr ""
 
-#: config/tc-i386.c:4634
+#: config/tc-i386.c:5239
 #, c-format
 msgid "expecting `,' or `)' after base register in `%s'"
 msgstr ""
 
 #. It's not a memory operand; argh!
-#: config/tc-i386.c:4675
+#: config/tc-i386.c:5281
 #, c-format
 msgid "invalid char %s beginning operand %d `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4850
+#: config/tc-i386.c:5457
 msgid "long jump required"
 msgstr ""
 
-#: config/tc-i386.c:5127
+#: config/tc-i386.c:5512
+msgid "jump target out of range"
+msgstr ""
+
+#: config/tc-i386.c:5757
 msgid "Bad call to md_atof ()"
 msgstr ""
 
-#: config/tc-i386.c:5294
+#: config/tc-i386.c:6012
 msgid "No compiled in support for x86_64"
 msgstr ""
 
-#: config/tc-i386.c:5315
+#: config/tc-i386.c:6041 config/tc-i386.c:6057
+#, c-format
+msgid "Invalid -march= option: `%s'"
+msgstr ""
+
+#: config/tc-i386.c:6062 config/tc-i386.c:6074
+#, c-format
+msgid "Invalid -mtune= option: `%s'"
+msgstr ""
+
+#: config/tc-i386.c:6088
 #, c-format
 msgid ""
 "  -Q                      ignored\n"
 "  -V                      print assembler version number\n"
 "  -k                      ignored\n"
-"  -n                      Do not optimize code alignment\n"
-"  -q                      quieten some warnings\n"
-"  -s                      ignored\n"
 msgstr ""
 
-#: config/tc-i386.c:5323
+#: config/tc-i386.c:6093
 #, c-format
 msgid ""
 "  -n                      Do not optimize code alignment\n"
 "  -q                      quieten some warnings\n"
 msgstr ""
 
-#: config/tc-i386.c:5425 config/tc-s390.c:1861
+#: config/tc-i386.c:6097
+#, c-format
+msgid "  -s                      ignored\n"
+msgstr ""
+
+#: config/tc-i386.c:6101
+#, c-format
+msgid "  --32/--64               generate 32bit/64bit code\n"
+msgstr ""
+
+#: config/tc-i386.c:6105
+#, c-format
+msgid "  --divide                do not treat `/' as a comment character\n"
+msgstr ""
+
+#: config/tc-i386.c:6108
+#, c-format
+msgid "  --divide                ignored\n"
+msgstr ""
+
+#: config/tc-i386.c:6111
+#, c-format
+msgid ""
+"  -march=CPU/-mtune=CPU   generate code/optimize for CPU, where CPU is one "
+"of:\n"
+"                           i386, i486, pentium, pentiumpro, pentium4, "
+"nocona,\n"
+"                           core, core2, k6, athlon, k8, generic32, "
+"generic64\n"
+msgstr ""
+
+#: config/tc-i386.c:6251 config/tc-s390.c:1862
 msgid "GOT already in symbol table"
 msgstr ""
 
-#: config/tc-i386.c:5568
+#: config/tc-i386.c:6400
 #, c-format
 msgid "can not do %d byte pc-relative relocation"
 msgstr ""
 
-#: config/tc-i386.c:5586
+#: config/tc-i386.c:6418
 #, c-format
 msgid "can not do %d byte relocation"
 msgstr ""
 
-#: config/tc-i386.c:5657 config/tc-s390.c:2307
+#: config/tc-i386.c:6497 config/tc-s390.c:2308
 #, c-format
 msgid "cannot represent relocation type %s"
 msgstr ""
 
-#: config/tc-i386.c:5912
+#: config/tc-i386.c:6749
 #, c-format
 msgid "invalid operand for '%s' ('%s' unexpected)"
 msgstr ""
 
-#: config/tc-i386.c:5924
+#: config/tc-i386.c:6761
 #, c-format
 msgid "too many memory references for '%s'"
 msgstr ""
 
 #. See the comments in intel_bracket_expr.
-#: config/tc-i386.c:5935
+#: config/tc-i386.c:6772
 #, c-format
 msgid "Treating `%s' as memory reference"
 msgstr ""
 
-#: config/tc-i386.c:6247
+#: config/tc-i386.c:7088
 #, c-format
 msgid "Unknown operand modifier `%s'"
 msgstr ""
 
-#: config/tc-i386.c:6262
+#: config/tc-i386.c:7103
 msgid "Conflicting operand modifiers"
 msgstr ""
 
-#: config/tc-i386.c:6311
+#: config/tc-i386.c:7152
 msgid "Invalid operand to `OFFSET'"
 msgstr ""
 
-#: config/tc-i386.c:6384
+#: config/tc-i386.c:7225
 #, c-format
 msgid "`[%.*s]' taken to mean just `%.*s'"
 msgstr ""
 
-#: config/tc-i386.c:6474
+#: config/tc-i386.c:7316
 #, c-format
 msgid "`%s' is not a valid segment register"
 msgstr ""
 
-#: config/tc-i386.c:6478
+#: config/tc-i386.c:7321
 msgid "Extra segment override ignored"
 msgstr ""
 
-#: config/tc-i386.c:6512 config/tc-i386.c:6681
+#: config/tc-i386.c:7355 config/tc-i386.c:7517
 msgid "Register scaling only allowed in memory operands"
 msgstr ""
 
-#: config/tc-i386.c:6534 config/tc-i386.c:6658
+#: config/tc-i386.c:7377 config/tc-i386.c:7493
 #, c-format
 msgid "Syntax error: Expecting a constant, got `%s'"
 msgstr ""
 
-#: config/tc-i386.c:6562
+#: config/tc-i386.c:7405
 msgid "Too many register references in memory operand"
 msgstr ""
 
-#: config/tc-i386.c:6573
-msgid "Using register names in OFFSET expressions is deprecated"
-msgstr ""
-
-#: config/tc-i386.c:6586
+#: config/tc-i386.c:7421
 msgid "Invalid use of register"
 msgstr ""
 
-#: config/tc-i386.c:6731
+#: config/tc-i386.c:7570
 #, c-format
 msgid "Unrecognized token '%s'"
 msgstr ""
 
-#: config/tc-i386.c:6748
+#: config/tc-i386.c:7586
 #, c-format
 msgid "Unexpected token `%s'"
 msgstr ""
 
-#: config/tc-i386.c:6910
+#: config/tc-i386.c:7744
 msgid "`:' expected"
 msgstr ""
 
-#: config/tc-i386.c:6935
+#: config/tc-i386.c:7769
 #, c-format
 msgid "Unrecognized token `%s'"
 msgstr ""
 
-#: config/tc-i386.c:7070
+#: config/tc-i386.c:7904
 msgid "Bad .section directive: want a,l,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-i386.c:7073
+#: config/tc-i386.c:7907
 msgid "Bad .section directive: want a,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-i386.c:7092
+#: config/tc-i386.c:7926
 msgid ".largecomm supported only in 64bit mode, producing .comm"
 msgstr ""
 
-#: config/tc-i860.c:124
+#: config/tc-i860.c:122
 msgid "Directive .dual available only with -mintel-syntax option"
 msgstr ""
 
-#: config/tc-i860.c:134
+#: config/tc-i860.c:132
 msgid "Directive .enddual available only with -mintel-syntax option"
 msgstr ""
 
-#: config/tc-i860.c:147
+#: config/tc-i860.c:145
 msgid "Directive .atmp available only with -mintel-syntax option"
 msgstr ""
 
-#: config/tc-i860.c:169 config/tc-i860.c:173
+#: config/tc-i860.c:167 config/tc-i860.c:171
 msgid "Unknown temporary pseudo register"
 msgstr ""
 
-#: config/tc-i860.c:229 config/tc-mips.c:1412
+#: config/tc-i860.c:227 config/tc-mips.c:1761
 #, c-format
 msgid "internal error: can't hash `%s': %s\n"
 msgstr ""
 
-#: config/tc-i860.c:249
+#: config/tc-i860.c:247
 msgid "Defective assembler.  No assembly attempted."
 msgstr ""
 
-#: config/tc-i860.c:395 config/tc-i860.c:940 config/tc-m68k.c:3443
-#: config/tc-m68k.c:3475 config/tc-sparc.c:2657
+#: config/tc-i860.c:393 config/tc-i860.c:938 config/tc-m68k.c:3667
+#: config/tc-m68k.c:3699 config/tc-sparc.c:2711
 msgid "failed sanity check."
 msgstr ""
 
-#: config/tc-i860.c:402
+#: config/tc-i860.c:400
 #, c-format
 msgid "Expanded opcode after delayed branch: `%s'"
 msgstr ""
 
-#: config/tc-i860.c:406
+#: config/tc-i860.c:404
 #, c-format
 msgid "Expanded opcode in dual mode: `%s'"
 msgstr ""
 
-#: config/tc-i860.c:410
+#: config/tc-i860.c:408
 #, c-format
 msgid "An instruction was expanded (%s)"
 msgstr ""
 
-#: config/tc-i860.c:676
+#: config/tc-i860.c:674
 msgid "Pipelined instruction: fsrc1 = fdest"
 msgstr ""
 
-#: config/tc-i860.c:879 config/tc-i860.c:886 config/tc-i860.c:893
+#: config/tc-i860.c:877 config/tc-i860.c:884 config/tc-i860.c:891
 msgid "Assembler does not yet support PIC"
 msgstr ""
 
-#: config/tc-i860.c:957
+#: config/tc-i860.c:955
 #, c-format
 msgid "Illegal operands for %s"
 msgstr ""
 
-#: config/tc-i860.c:974
+#: config/tc-i860.c:972
 #, c-format
 msgid "'d.%s' must be 8-byte aligned"
 msgstr ""
 
-#: config/tc-i860.c:982
+#: config/tc-i860.c:980
 #, c-format
 msgid "Prefix 'd.' invalid for instruction `%s'"
 msgstr ""
 
-#: config/tc-i860.c:1088
+#: config/tc-i860.c:1086
 msgid "i860_estimate_size_before_relax\n"
 msgstr ""
 
-#: config/tc-i860.c:1187
+#: config/tc-i860.c:1185
 #, c-format
 msgid ""
 "  -EL\t\t\t  generate code for little endian mode (default)\n"
@@ -5052,42 +5588,42 @@ msgid ""
 msgstr ""
 
 #. SVR4 compatibility flags.
-#: config/tc-i860.c:1195
+#: config/tc-i860.c:1193
 #, c-format
 msgid ""
 "  -V\t\t\t  print assembler version number\n"
 "  -Qy, -Qn\t\t  ignored\n"
 msgstr ""
 
-#: config/tc-i860.c:1258
+#: config/tc-i860.c:1256
 msgid "This immediate requires 0 MOD 2 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1261
+#: config/tc-i860.c:1259
 msgid "This immediate requires 0 MOD 4 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1264
+#: config/tc-i860.c:1262
 msgid "This immediate requires 0 MOD 8 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1267
+#: config/tc-i860.c:1265
 msgid "This immediate requires 0 MOD 16 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1362
+#: config/tc-i860.c:1360
 msgid "5-bit immediate too large"
 msgstr ""
 
-#: config/tc-i860.c:1365
+#: config/tc-i860.c:1363
 msgid "5-bit field must be absolute"
 msgstr ""
 
-#: config/tc-i860.c:1410 config/tc-i860.c:1433
+#: config/tc-i860.c:1408 config/tc-i860.c:1431
 msgid "A branch offset requires 0 MOD 4 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1454
+#: config/tc-i860.c:1452
 #, c-format
 msgid "Unrecognized fix-up (0x%08lx)"
 msgstr ""
@@ -5096,95 +5632,87 @@ msgstr ""
 msgid "i860_convert_frag\n"
 msgstr ""
 
-#: config/tc-i960.c:488
+#: config/tc-i960.c:486
 #, c-format
 msgid "Hashing returned \"%s\"."
 msgstr ""
 
-#: config/tc-i960.c:584 config/tc-i960.c:1114
+#: config/tc-i960.c:582 config/tc-i960.c:1112
 msgid "expression syntax error"
 msgstr ""
 
-#: config/tc-i960.c:620
+#: config/tc-i960.c:618
 msgid "attempt to branch into different segment"
 msgstr ""
 
-#: config/tc-i960.c:624
+#: config/tc-i960.c:622
 #, c-format
 msgid "target of %s instruction must be a label"
 msgstr ""
 
-#: config/tc-i960.c:734
+#: config/tc-i960.c:732
 msgid "unaligned register"
 msgstr ""
 
-#: config/tc-i960.c:756
+#: config/tc-i960.c:754
 msgid "no such sfr in this architecture"
 msgstr ""
 
-#: config/tc-i960.c:794
+#: config/tc-i960.c:792
 msgid "illegal literal"
 msgstr ""
 
-#: config/tc-i960.c:837
-msgid "unmatched '['"
-msgstr ""
-
-#: config/tc-i960.c:844
-msgid "garbage after index spec ignored"
-msgstr ""
-
-#: config/tc-i960.c:944
+#: config/tc-i960.c:942
 msgid "invalid index register"
 msgstr ""
 
-#: config/tc-i960.c:967
+#: config/tc-i960.c:965
 msgid "invalid scale factor"
 msgstr ""
 
-#: config/tc-i960.c:1191
+#: config/tc-i960.c:1189
 msgid "architecture of opcode conflicts with that of earlier instruction(s)"
 msgstr ""
 
-#: config/tc-i960.c:1425 config/tc-xtensa.c:11295
+#: config/tc-i960.c:1423 config/tc-xtensa.c:11325
 msgid "too many operands"
 msgstr ""
 
 #. We never moved: there was no opcode either!
-#: config/tc-i960.c:1473
+#: config/tc-i960.c:1471
 msgid "missing opcode"
 msgstr ""
 
-#: config/tc-i960.c:1613
+#: config/tc-i960.c:1611
 msgid "branch prediction invalid on this opcode"
 msgstr ""
 
-#: config/tc-i960.c:1651
+#: config/tc-i960.c:1649
 #, c-format
 msgid "invalid opcode, \"%s\"."
 msgstr ""
 
-#: config/tc-i960.c:1653
+#: config/tc-i960.c:1651
 #, c-format
 msgid "improper number of operands.  expecting %d, got %d"
 msgstr ""
 
-#: config/tc-i960.c:1810
+#: config/tc-i960.c:1808
 #, c-format
 msgid "Fixup of %ld too large for field width of %d"
 msgstr ""
 
-#: config/tc-i960.c:1920
+#: config/tc-i960.c:1918
 #, c-format
 msgid "invalid architecture %s"
 msgstr ""
 
-#: config/tc-i960.c:1940
+#: config/tc-i960.c:1938
 #, c-format
 msgid "I960 options:\n"
 msgstr ""
 
-#: config/tc-i960.c:1943
+#: config/tc-i960.c:1941
 #, c-format
 msgid ""
 "\n"
@@ -5196,153 +5724,153 @@ msgid ""
 "\t\t\tlong displacements\n"
 msgstr ""
 
-#: config/tc-i960.c:2207
+#: config/tc-i960.c:2205
 msgid "should have 1 or 2 operands"
 msgstr ""
 
-#: config/tc-i960.c:2215 config/tc-i960.c:2230
+#: config/tc-i960.c:2213 config/tc-i960.c:2228
 #, c-format
 msgid "Redefining leafproc %s"
 msgstr ""
 
-#: config/tc-i960.c:2260
+#: config/tc-i960.c:2258
 msgid "should have two operands"
 msgstr ""
 
-#: config/tc-i960.c:2270
+#: config/tc-i960.c:2268
 msgid "'entry_num' must be absolute number in [0,31]"
 msgstr ""
 
-#: config/tc-i960.c:2278
+#: config/tc-i960.c:2276
 #, c-format
 msgid "Redefining entrynum for sysproc %s"
 msgstr ""
 
 #. Should not happen: see block comment above.
-#: config/tc-i960.c:2378
+#: config/tc-i960.c:2376
 #, c-format
 msgid "Trying to 'bal' to %s"
 msgstr ""
 
-#: config/tc-i960.c:2388
+#: config/tc-i960.c:2386
 msgid "Looks like a proc, but can't tell what kind.\n"
 msgstr ""
 
-#: config/tc-i960.c:2407
+#: config/tc-i960.c:2405
 msgid "big endian mode is not supported"
 msgstr ""
 
-#: config/tc-i960.c:2409
+#: config/tc-i960.c:2407
 #, c-format
 msgid "ignoring unrecognized .endian type `%s'"
 msgstr ""
 
-#: config/tc-i960.c:2454
+#: config/tc-i960.c:2452
 msgid "can't use COBR format with external label"
 msgstr ""
 
-#: config/tc-i960.c:2629
+#: config/tc-i960.c:2627
 msgid "option --link-relax is only supported in b.out format"
 msgstr ""
 
-#: config/tc-i960.c:2656
+#: config/tc-i960.c:2654
 #, c-format
 msgid "No 'bal' entry point for leafproc %s"
 msgstr ""
 
-#: config/tc-ia64.c:1008
+#: config/tc-ia64.c:1030
 msgid "Bad .section directive: want a,o,s,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-ia64.c:1151
+#: config/tc-ia64.c:1173
 msgid "Unwind directive not followed by an instruction."
 msgstr ""
 
-#: config/tc-ia64.c:5114
+#: config/tc-ia64.c:5123
 msgid "Register name expected"
 msgstr ""
 
-#: config/tc-ia64.c:5119 config/tc-ia64.c:5435
+#: config/tc-ia64.c:5128 config/tc-ia64.c:5444
 msgid "Comma expected"
 msgstr ""
 
-#: config/tc-ia64.c:5127
+#: config/tc-ia64.c:5136
 msgid "Register value annotation ignored"
 msgstr ""
 
-#: config/tc-ia64.c:5168
+#: config/tc-ia64.c:5177
 msgid "Directive invalid within a bundle"
 msgstr ""
 
-#: config/tc-ia64.c:5261
+#: config/tc-ia64.c:5270
 msgid "Missing predicate relation type"
 msgstr ""
 
-#: config/tc-ia64.c:5267
+#: config/tc-ia64.c:5276
 msgid "Unrecognized predicate relation type"
 msgstr ""
 
-#: config/tc-ia64.c:5314
+#: config/tc-ia64.c:5323
 msgid "Bad register range"
 msgstr ""
 
-#: config/tc-ia64.c:5323
+#: config/tc-ia64.c:5332
 msgid "Predicate register expected"
 msgstr ""
 
-#: config/tc-ia64.c:5328
+#: config/tc-ia64.c:5337
 msgid "Duplicate predicate register ignored"
 msgstr ""
 
-#: config/tc-ia64.c:5346
+#: config/tc-ia64.c:5355
 msgid "Predicate source and target required"
 msgstr ""
 
-#: config/tc-ia64.c:5348 config/tc-ia64.c:5360
+#: config/tc-ia64.c:5357 config/tc-ia64.c:5369
 msgid "Use of p0 is not valid in this context"
 msgstr ""
 
-#: config/tc-ia64.c:5355
+#: config/tc-ia64.c:5364
 msgid "At least two PR arguments expected"
 msgstr ""
 
-#: config/tc-ia64.c:5369
+#: config/tc-ia64.c:5378
 msgid "At least one PR argument expected"
 msgstr ""
 
-#: config/tc-ia64.c:5405
+#: config/tc-ia64.c:5414
 #, c-format
 msgid "Inserting \"%s\" into entry hint table failed: %s"
 msgstr ""
 
 #. FIXME -- need 62-bit relocation type
-#: config/tc-ia64.c:5881
+#: config/tc-ia64.c:5890
 msgid "62-bit relocation not yet implemented"
 msgstr ""
 
 #. XXX technically, this is wrong: we should not be issuing warning
 #. messages until we're sure this instruction pattern is going to
 #. be used!
-#: config/tc-ia64.c:5954
+#: config/tc-ia64.c:5974
 msgid "lower 16 bits of mask ignored"
 msgstr ""
 
-#: config/tc-ia64.c:6569
+#: config/tc-ia64.c:6589
 msgid "Value truncated to 62 bits"
 msgstr ""
 
 #. Give an error if a frag containing code is not aligned to a 16 byte
 #. boundary.
-#: config/tc-ia64.c:6707 config/tc-ia64.h:171
+#: config/tc-ia64.c:6727 config/tc-ia64.h:171
 msgid "instruction address is not a multiple of 16"
 msgstr ""
 
-#: config/tc-ia64.c:7249
+#: config/tc-ia64.c:7277
 #, c-format
 msgid "Unrecognized option '-x%s'"
 msgstr ""
 
-#: config/tc-ia64.c:7277
+#: config/tc-ia64.c:7305
 msgid ""
 "IA-64 options:\n"
 "  --mconstant-gp\t  mark output file as using the constant-GP model\n"
@@ -5368,370 +5896,370 @@ msgid ""
 "\t\t\t  dependency violation checking\n"
 msgstr ""
 
-#: config/tc-ia64.c:7307
+#: config/tc-ia64.c:7335
 msgid "--gstabs is not supported for ia64"
 msgstr ""
 
-#: config/tc-ia64.c:7641 config/tc-mips.c:1401
+#: config/tc-ia64.c:7640 config/tc-mips.c:1750
 msgid "Could not set architecture and machine"
 msgstr ""
 
-#: config/tc-ia64.c:7767
+#: config/tc-ia64.c:7766
 msgid "Explicit stops are ignored in auto mode"
 msgstr ""
 
-#: config/tc-ia64.c:7789
+#: config/tc-ia64.c:7788
 msgid "Found '{' after explicit switch to automatic mode"
 msgstr ""
 
-#: config/tc-ia64.c:8392
+#: config/tc-ia64.c:8393
 #, c-format
 msgid "Unhandled dependency %s for %s (%s), note %d"
 msgstr ""
 
-#: config/tc-ia64.c:9667
+#: config/tc-ia64.c:9669
 #, c-format
 msgid "Unrecognized dependency specifier %d\n"
 msgstr ""
 
-#: config/tc-ia64.c:10561
+#: config/tc-ia64.c:10566
 msgid "Only the first path encountering the conflict is reported"
 msgstr ""
 
-#: config/tc-ia64.c:10564
+#: config/tc-ia64.c:10569
 msgid "This is the location of the conflicting usage"
 msgstr ""
 
-#: config/tc-ia64.c:11788
+#: config/tc-ia64.c:11793
 msgid "Can't add stop bit to mark end of instruction group"
 msgstr ""
 
-#: config/tc-ia64.c:11888 read.c:1440 read.c:2206 read.c:2846 read.c:3173
-#: read.c:3204
+#: config/tc-ia64.c:11893 config/tc-score.c:6398 read.c:1442 read.c:2413
+#: read.c:3042 read.c:3375 read.c:3419
 msgid "expected symbol name"
 msgstr ""
 
-#: config/tc-ia64.c:11898 read.c:2216 read.c:2856 read.c:3188 stabs.c:466
+#: config/tc-ia64.c:11903 read.c:2423 read.c:3052 read.c:3403 stabs.c:466
 #, c-format
 msgid "expected comma after \"%s\""
 msgstr ""
 
-#: config/tc-ia64.c:11940
+#: config/tc-ia64.c:11945
 #, c-format
 msgid "`%s' is already the alias of %s `%s'"
 msgstr ""
 
-#: config/tc-ia64.c:11950
+#: config/tc-ia64.c:11955
 #, c-format
 msgid "%s `%s' already has an alias `%s'"
 msgstr ""
 
-#: config/tc-ia64.c:11961
+#: config/tc-ia64.c:11966
 #, c-format
 msgid "inserting \"%s\" into %s alias hash table failed: %s"
 msgstr ""
 
-#: config/tc-ia64.c:11969
+#: config/tc-ia64.c:11974
 #, c-format
 msgid "inserting \"%s\" into %s name hash table failed: %s"
 msgstr ""
 
-#: config/tc-ia64.c:11988
+#: config/tc-ia64.c:11993
 #, c-format
 msgid "symbol `%s' aliased to `%s' is not used"
 msgstr ""
 
-#: config/tc-ia64.c:12010
+#: config/tc-ia64.c:12015
 #, c-format
 msgid "section `%s' aliased to `%s' is not used"
 msgstr ""
 
-#: config/tc-ip2k.c:158
+#: config/tc-ip2k.c:157
 #, c-format
 msgid "IP2K specific command line options:\n"
 msgstr ""
 
-#: config/tc-ip2k.c:159
+#: config/tc-ip2k.c:158
 #, c-format
 msgid "  -mip2022               restrict to IP2022 insns \n"
 msgstr ""
 
-#: config/tc-ip2k.c:160
+#: config/tc-ip2k.c:159
 #, c-format
 msgid "  -mip2022ext            permit extended IP2022 insn\n"
 msgstr ""
 
-#: config/tc-ip2k.c:274
+#: config/tc-ip2k.c:273
 msgid "md_pcrel_from\n"
 msgstr ""
 
-#: config/tc-m32c.c:128
+#: config/tc-m32c.c:137
 #, c-format
 msgid " M32C specific command line options:\n"
 msgstr ""
 
 #. Pretend that we do not recognise this option.
-#: config/tc-m32r.c:332
+#: config/tc-m32r.c:331
 msgid "Unrecognised option: -hidden"
 msgstr ""
 
-#: config/tc-m32r.c:359 config/tc-sparc.c:593
+#: config/tc-m32r.c:358 config/tc-sparc.c:595
 msgid "Unrecognized option following -K"
 msgstr ""
 
-#: config/tc-m32r.c:374
+#: config/tc-m32r.c:373
 #, c-format
 msgid " M32R specific command line options:\n"
 msgstr ""
 
-#: config/tc-m32r.c:376
+#: config/tc-m32r.c:375
 #, c-format
 msgid ""
 "  -m32r                   disable support for the m32rx instruction set\n"
 msgstr ""
 
-#: config/tc-m32r.c:378
+#: config/tc-m32r.c:377
 #, c-format
 msgid "  -m32rx                  support the extended m32rx instruction set\n"
 msgstr ""
 
-#: config/tc-m32r.c:380
+#: config/tc-m32r.c:379
 #, c-format
 msgid "  -m32r2                  support the extended m32r2 instruction set\n"
 msgstr ""
 
-#: config/tc-m32r.c:382
+#: config/tc-m32r.c:381
 #, c-format
 msgid "  -EL,-little             produce little endian code and data\n"
 msgstr ""
 
-#: config/tc-m32r.c:384
+#: config/tc-m32r.c:383
 #, c-format
 msgid "  -EB,-big                produce big endian code and data\n"
 msgstr ""
 
-#: config/tc-m32r.c:386
+#: config/tc-m32r.c:385
 #, c-format
 msgid "  -parallel               try to combine instructions in parallel\n"
 msgstr ""
 
-#: config/tc-m32r.c:388
+#: config/tc-m32r.c:387
 #, c-format
 msgid "  -no-parallel            disable -parallel\n"
 msgstr ""
 
-#: config/tc-m32r.c:390
+#: config/tc-m32r.c:389
 #, c-format
 msgid ""
 "  -no-bitinst             disallow the M32R2's extended bit-field "
 "instructions\n"
 msgstr ""
 
-#: config/tc-m32r.c:392
+#: config/tc-m32r.c:391
 #, c-format
 msgid "  -O                      try to optimize code.  Implies -parallel\n"
 msgstr ""
 
-#: config/tc-m32r.c:395
+#: config/tc-m32r.c:394
 #, c-format
 msgid ""
 "  -warn-explicit-parallel-conflicts     warn when parallel instructions\n"
 msgstr ""
 
-#: config/tc-m32r.c:397
+#: config/tc-m32r.c:396
 #, c-format
 msgid "                                         might violate contraints\n"
 msgstr ""
 
-#: config/tc-m32r.c:399
+#: config/tc-m32r.c:398
 #, c-format
 msgid "  -no-warn-explicit-parallel-conflicts  do not warn when parallel\n"
 msgstr ""
 
-#: config/tc-m32r.c:401
+#: config/tc-m32r.c:400
 #, c-format
 msgid ""
 "                                         instructions might violate "
 "contraints\n"
 msgstr ""
 
-#: config/tc-m32r.c:403
+#: config/tc-m32r.c:402
 #, c-format
 msgid ""
 "  -Wp                     synonym for -warn-explicit-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:405
+#: config/tc-m32r.c:404
 #, c-format
 msgid ""
 "  -Wnp                    synonym for -no-warn-explicit-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:407
+#: config/tc-m32r.c:406
 #, c-format
 msgid ""
 "  -ignore-parallel-conflicts            do not check parallel instructions\n"
 msgstr ""
 
-#: config/tc-m32r.c:409
+#: config/tc-m32r.c:408
 #, c-format
 msgid "                                         fo contraint violations\n"
 msgstr ""
 
-#: config/tc-m32r.c:411
+#: config/tc-m32r.c:410
 #, c-format
 msgid ""
 "  -no-ignore-parallel-conflicts         check parallel instructions for\n"
 msgstr ""
 
-#: config/tc-m32r.c:413
+#: config/tc-m32r.c:412
 #, c-format
 msgid "                                         contraint violations\n"
 msgstr ""
 
-#: config/tc-m32r.c:415
+#: config/tc-m32r.c:414
 #, c-format
 msgid "  -Ip                     synonym for -ignore-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:417
+#: config/tc-m32r.c:416
 #, c-format
 msgid "  -nIp                    synonym for -no-ignore-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:420
+#: config/tc-m32r.c:419
 #, c-format
 msgid ""
 "  -warn-unmatched-high    warn when an (s)high reloc has no matching low "
 "reloc\n"
 msgstr ""
 
-#: config/tc-m32r.c:422
+#: config/tc-m32r.c:421
 #, c-format
 msgid "  -no-warn-unmatched-high do not warn about missing low relocs\n"
 msgstr ""
 
-#: config/tc-m32r.c:424
+#: config/tc-m32r.c:423
 #, c-format
 msgid "  -Wuh                    synonym for -warn-unmatched-high\n"
 msgstr ""
 
-#: config/tc-m32r.c:426
+#: config/tc-m32r.c:425
 #, c-format
 msgid "  -Wnuh                   synonym for -no-warn-unmatched-high\n"
 msgstr ""
 
-#: config/tc-m32r.c:429
+#: config/tc-m32r.c:428
 #, c-format
 msgid "  -KPIC                   generate PIC\n"
 msgstr ""
 
-#: config/tc-m32r.c:850
+#: config/tc-m32r.c:849
 msgid "instructions write to the same destination register."
 msgstr ""
 
-#: config/tc-m32r.c:858
+#: config/tc-m32r.c:857
 msgid "Instructions do not use parallel execution pipelines."
 msgstr ""
 
-#: config/tc-m32r.c:866
+#: config/tc-m32r.c:865
 msgid "Instructions share the same execution pipeline"
 msgstr ""
 
-#: config/tc-m32r.c:931 config/tc-m32r.c:1045
+#: config/tc-m32r.c:930 config/tc-m32r.c:1044
 #, c-format
 msgid "not a 16 bit instruction '%s'"
 msgstr ""
 
-#: config/tc-m32r.c:943 config/tc-m32r.c:1057 config/tc-m32r.c:1241
+#: config/tc-m32r.c:942 config/tc-m32r.c:1056 config/tc-m32r.c:1240
 #, c-format
 msgid "instruction '%s' is for the M32R2 only"
 msgstr ""
 
-#: config/tc-m32r.c:956 config/tc-m32r.c:1070 config/tc-m32r.c:1254
+#: config/tc-m32r.c:955 config/tc-m32r.c:1069 config/tc-m32r.c:1253
 #, c-format
 msgid "unknown instruction '%s'"
 msgstr ""
 
-#: config/tc-m32r.c:965 config/tc-m32r.c:1077 config/tc-m32r.c:1261
+#: config/tc-m32r.c:964 config/tc-m32r.c:1076 config/tc-m32r.c:1260
 #, c-format
 msgid "instruction '%s' is for the M32RX only"
 msgstr ""
 
-#: config/tc-m32r.c:974 config/tc-m32r.c:1086
+#: config/tc-m32r.c:973 config/tc-m32r.c:1085
 #, c-format
 msgid "instruction '%s' cannot be executed in parallel."
 msgstr ""
 
-#: config/tc-m32r.c:1029 config/tc-m32r.c:1111 config/tc-m32r.c:1318
+#: config/tc-m32r.c:1028 config/tc-m32r.c:1110 config/tc-m32r.c:1317
 msgid "internal error: lookup/get operands failed"
 msgstr ""
 
-#: config/tc-m32r.c:1096
+#: config/tc-m32r.c:1095
 #, c-format
 msgid "'%s': only the NOP instruction can be issued in parallel on the m32r"
 msgstr ""
 
-#: config/tc-m32r.c:1125
+#: config/tc-m32r.c:1124
 #, c-format
 msgid ""
 "%s: output of 1st instruction is the same as an input to 2nd instruction - "
 "is this intentional ?"
 msgstr ""
 
-#: config/tc-m32r.c:1129
+#: config/tc-m32r.c:1128
 #, c-format
 msgid ""
 "%s: output of 2nd instruction is the same as an input to 1st instruction - "
 "is this intentional ?"
 msgstr ""
 
-#: config/tc-m32r.c:1493 config/tc-ppc.c:1773 config/tc-ppc.c:4365
+#: config/tc-m32r.c:1492 config/tc-ppc.c:1832 config/tc-ppc.c:4372
 msgid "Expected comma after symbol-name: rest of line ignored."
 msgstr ""
 
-#: config/tc-m32r.c:1503
+#: config/tc-m32r.c:1502
 #, c-format
 msgid ".SCOMMon length (%ld.) <0! Ignored."
 msgstr ""
 
-#: config/tc-m32r.c:1517 config/tc-ppc.c:1795 config/tc-ppc.c:2952
-#: config/tc-ppc.c:4389
+#: config/tc-m32r.c:1516 config/tc-ppc.c:1854 config/tc-ppc.c:2993
+#: config/tc-ppc.c:4396
 msgid "ignoring bad alignment"
 msgstr ""
 
-#: config/tc-m32r.c:1529 config/tc-ppc.c:1832 config/tc-v850.c:323
+#: config/tc-m32r.c:1528 config/tc-ppc.c:1891 config/tc-v850.c:322
 msgid "Common alignment not a power of 2"
 msgstr ""
 
-#: config/tc-m32r.c:1544 config/tc-ppc.c:1806 config/tc-ppc.c:4401
+#: config/tc-m32r.c:1543 config/tc-ppc.c:1865 config/tc-ppc.c:4408
 #, c-format
 msgid "Ignoring attempt to re-define symbol `%s'."
 msgstr ""
 
-#: config/tc-m32r.c:1553
+#: config/tc-m32r.c:1552
 #, c-format
 msgid "Length of .scomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/tc-m32r.c:1789
+#: config/tc-m32r.c:1788
 msgid "Addend to unresolved symbol not on word boundary."
 msgstr ""
 
-#: config/tc-m32r.c:1930 config/tc-m32r.c:1983 config/tc-sh.c:749
+#: config/tc-m32r.c:1929 config/tc-m32r.c:1982 config/tc-sh.c:747
 msgid "Invalid PIC expression."
 msgstr ""
 
-#: config/tc-m32r.c:2074
+#: config/tc-m32r.c:2073
 msgid "Unmatched high/shigh reloc"
 msgstr ""
 
-#: config/tc-m32r.c:2334 config/tc-sparc.c:3524
+#: config/tc-m32r.c:2333 config/tc-sparc.c:3604
 #, c-format
 msgid "internal error: can't export reloc type %d (`%s')"
 msgstr ""
 
-#: config/tc-m68hc11.c:369
+#: config/tc-m68hc11.c:371
 #, c-format
 msgid ""
 "Motorola 68HC11/68HC12/68HCS12 options:\n"
@@ -5741,8 +6269,8 @@ msgid ""
 "  -mlong                  use 32-bit int ABI\n"
 "  -mshort-double          use 32-bit double ABI\n"
 "  -mlong-double           use 64-bit double ABI (default)\n"
-"  --force-long-branchs    always turn relative branchs into absolute ones\n"
-"  -S,--short-branchs      do not turn relative branchs into absolute ones\n"
+"  --force-long-branches   always turn relative branches into absolute ones\n"
+"  -S,--short-branches     do not turn relative branches into absolute ones\n"
 "                          when the offset is out of range\n"
 "  --strict-direct-mode    do not turn the direct mode into extended mode\n"
 "                          when the instruction does not support direct mode\n"
@@ -5752,56 +6280,56 @@ msgid ""
 "                          (used for testing)\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:415
+#: config/tc-m68hc11.c:417
 #, c-format
 msgid "Default target `%s' is not supported."
 msgstr ""
 
 #. Dump the opcode statistics table.
-#: config/tc-m68hc11.c:433
+#: config/tc-m68hc11.c:435
 #, c-format
 msgid "Name   # Modes  Min ops  Max ops  Modes mask  # Used\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:499
+#: config/tc-m68hc11.c:501
 #, c-format
 msgid "Option `%s' is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:721
+#: config/tc-m68hc11.c:723
 msgid "#<imm8>"
 msgstr ""
 
-#: config/tc-m68hc11.c:730
+#: config/tc-m68hc11.c:732
 msgid "#<imm16>"
 msgstr ""
 
-#: config/tc-m68hc11.c:739 config/tc-m68hc11.c:748
+#: config/tc-m68hc11.c:741 config/tc-m68hc11.c:750
 msgid "<imm8>,X"
 msgstr ""
 
-#: config/tc-m68hc11.c:775
+#: config/tc-m68hc11.c:777
 msgid "*<abs8>"
 msgstr ""
 
-#: config/tc-m68hc11.c:787
+#: config/tc-m68hc11.c:789
 msgid "#<mask>"
 msgstr ""
 
-#: config/tc-m68hc11.c:797
+#: config/tc-m68hc11.c:799
 #, c-format
 msgid "symbol%d"
 msgstr ""
 
-#: config/tc-m68hc11.c:799
+#: config/tc-m68hc11.c:801
 msgid "<abs>"
 msgstr ""
 
-#: config/tc-m68hc11.c:818
+#: config/tc-m68hc11.c:820
 msgid "<label>"
 msgstr ""
 
-#: config/tc-m68hc11.c:834
+#: config/tc-m68hc11.c:836
 #, c-format
 msgid ""
 "# Example of `%s' instructions\n"
@@ -5809,862 +6337,902 @@ msgid ""
 "_start:\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:881
+#: config/tc-m68hc11.c:883
 #, c-format
 msgid "Instruction `%s' is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:886
+#: config/tc-m68hc11.c:888
 #, c-format
 msgid "Instruction formats for `%s':"
 msgstr ""
 
-#: config/tc-m68hc11.c:1016
+#: config/tc-m68hc11.c:1018
 #, c-format
 msgid "Immediate operand is not allowed for operand %d."
 msgstr ""
 
-#: config/tc-m68hc11.c:1060
+#: config/tc-m68hc11.c:1062
 msgid "Indirect indexed addressing is not valid for 68HC11."
 msgstr ""
 
-#: config/tc-m68hc11.c:1080
+#: config/tc-m68hc11.c:1082
 msgid "Spurious `,' or bad indirect register addressing mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1102
+#: config/tc-m68hc11.c:1104
 msgid "Missing second register or offset for indexed-indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1112
+#: config/tc-m68hc11.c:1114
 msgid "Missing second register for indexed-indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1128
+#: config/tc-m68hc11.c:1130
 msgid "Missing `]' to close indexed-indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1173
+#: config/tc-m68hc11.c:1175
 msgid "Illegal operand."
 msgstr ""
 
-#: config/tc-m68hc11.c:1178
+#: config/tc-m68hc11.c:1180
 msgid "Missing operand."
 msgstr ""
 
-#: config/tc-m68hc11.c:1231
+#: config/tc-m68hc11.c:1233
 msgid "Pre-increment mode is not valid for 68HC11"
 msgstr ""
 
-#: config/tc-m68hc11.c:1244
+#: config/tc-m68hc11.c:1246
 msgid "Wrong register in register indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1252
+#: config/tc-m68hc11.c:1254
 msgid "Missing `]' to close register indirect operand."
 msgstr ""
 
-#: config/tc-m68hc11.c:1272
+#: config/tc-m68hc11.c:1274
 msgid "Post-decrement mode is not valid for 68HC11."
 msgstr ""
 
-#: config/tc-m68hc11.c:1280
+#: config/tc-m68hc11.c:1282
 msgid "Post-increment mode is not valid for 68HC11."
 msgstr ""
 
-#: config/tc-m68hc11.c:1298
+#: config/tc-m68hc11.c:1300
 msgid "Invalid indexed indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1390
+#: config/tc-m68hc11.c:1392
 #, c-format
 msgid "Trap id `%ld' is out of range."
 msgstr ""
 
-#: config/tc-m68hc11.c:1394
+#: config/tc-m68hc11.c:1396
 msgid "Trap id must be within [0x30..0x39] or [0x40..0xff]."
 msgstr ""
 
-#: config/tc-m68hc11.c:1401
+#: config/tc-m68hc11.c:1403
 #, c-format
 msgid "Operand out of 8-bit range: `%ld'."
 msgstr ""
 
-#: config/tc-m68hc11.c:1408
+#: config/tc-m68hc11.c:1410
 msgid "The trap id must be a constant."
 msgstr ""
 
-#: config/tc-m68hc11.c:1443
+#: config/tc-m68hc11.c:1445
 #, c-format
 msgid "Operand `%x' not recognized in fixup8."
 msgstr ""
 
-#: config/tc-m68hc11.c:1460 config/tc-m68hc11.c:1509
+#: config/tc-m68hc11.c:1462 config/tc-m68hc11.c:1511
 #, c-format
 msgid "Operand out of 16-bit range: `%ld'."
 msgstr ""
 
-#: config/tc-m68hc11.c:1492 config/tc-m68hc11.c:1525
+#: config/tc-m68hc11.c:1494 config/tc-m68hc11.c:1527
 #, c-format
 msgid "Operand `%x' not recognized in fixup16."
 msgstr ""
 
-#: config/tc-m68hc11.c:1542
+#: config/tc-m68hc11.c:1544
 #, c-format
 msgid "Unexpected branch conversion with `%x'"
 msgstr ""
 
-#: config/tc-m68hc11.c:1633 config/tc-m68hc11.c:1771
+#: config/tc-m68hc11.c:1635 config/tc-m68hc11.c:1773
 #, c-format
 msgid "Operand out of range for a relative branch: `%ld'"
 msgstr ""
 
-#: config/tc-m68hc11.c:1739
+#: config/tc-m68hc11.c:1741
 msgid "Invalid register for dbcc/tbcc instruction."
 msgstr ""
 
-#: config/tc-m68hc11.c:1827
+#: config/tc-m68hc11.c:1829
 #, c-format
 msgid "Increment/decrement value is out of range: `%ld'."
 msgstr ""
 
-#: config/tc-m68hc11.c:1838
+#: config/tc-m68hc11.c:1840
 msgid "Expecting a register."
 msgstr ""
 
-#: config/tc-m68hc11.c:1853
+#: config/tc-m68hc11.c:1855
 msgid "Invalid register for post/pre increment."
 msgstr ""
 
-#: config/tc-m68hc11.c:1883
+#: config/tc-m68hc11.c:1885
 msgid "Invalid register."
 msgstr ""
 
-#: config/tc-m68hc11.c:1890
+#: config/tc-m68hc11.c:1892
 #, c-format
 msgid "Offset out of 16-bit range: %ld."
 msgstr ""
 
-#: config/tc-m68hc11.c:1895
+#: config/tc-m68hc11.c:1897
 #, c-format
 msgid "Offset out of 5-bit range for movw/movb insn: %ld."
 msgstr ""
 
-#: config/tc-m68hc11.c:2001
+#: config/tc-m68hc11.c:2003
 msgid "Expecting register D for indexed indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:2003
+#: config/tc-m68hc11.c:2005
 msgid "Indexed indirect mode is not allowed for movb/movw."
 msgstr ""
 
-#: config/tc-m68hc11.c:2020
+#: config/tc-m68hc11.c:2022
 msgid "Invalid accumulator register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2045
+#: config/tc-m68hc11.c:2047
 msgid "Invalid indexed register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2053
+#: config/tc-m68hc11.c:2055
 msgid "Addressing mode not implemented yet."
 msgstr ""
 
-#: config/tc-m68hc11.c:2066
+#: config/tc-m68hc11.c:2068
 msgid "Invalid source register for this instruction, use 'tfr'."
 msgstr ""
 
-#: config/tc-m68hc11.c:2068
+#: config/tc-m68hc11.c:2070
 msgid "Invalid source register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2073
+#: config/tc-m68hc11.c:2075
 msgid "Invalid destination register for this instruction, use 'tfr'."
 msgstr ""
 
-#: config/tc-m68hc11.c:2075
+#: config/tc-m68hc11.c:2077
 msgid "Invalid destination register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2171
+#: config/tc-m68hc11.c:2173
 msgid "Invalid indexed register, expecting register X."
 msgstr ""
 
-#: config/tc-m68hc11.c:2173
+#: config/tc-m68hc11.c:2175
 msgid "Invalid indexed register, expecting register Y."
 msgstr ""
 
-#: config/tc-m68hc11.c:2479
+#: config/tc-m68hc11.c:2481
 msgid "No instruction or missing opcode."
 msgstr ""
 
-#: config/tc-m68hc11.c:2544
+#: config/tc-m68hc11.c:2546
 #, c-format
 msgid "Opcode `%s' is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:2566
+#: config/tc-m68hc11.c:2568
 #, c-format
 msgid "Garbage at end of instruction: `%s'."
 msgstr ""
 
-#: config/tc-m68hc11.c:2589
+#: config/tc-m68hc11.c:2591
 #, c-format
 msgid "Invalid operand for `%s'"
 msgstr ""
 
-#: config/tc-m68hc11.c:2640
+#: config/tc-m68hc11.c:2642
 #, c-format
 msgid "Invalid mode: %s\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:2700
+#: config/tc-m68hc11.c:2702
 msgid "bad .relax format"
 msgstr ""
 
-#: config/tc-m68hc11.c:2744
+#: config/tc-m68hc11.c:2746
 #, c-format
 msgid "Relocation %d is not supported by object file format."
 msgstr ""
 
-#: config/tc-m68hc11.c:3023
+#: config/tc-m68hc11.c:3025
 msgid "bra or bsr with undefined symbol."
 msgstr ""
 
-#: config/tc-m68hc11.c:3126 config/tc-m68hc11.c:3183
+#: config/tc-m68hc11.c:3128 config/tc-m68hc11.c:3185
 #, c-format
 msgid "Subtype %d is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:3242
+#: config/tc-m68hc11.c:3244
 msgid "Expression too complex."
 msgstr ""
 
-#: config/tc-m68hc11.c:3275
+#: config/tc-m68hc11.c:3277
 msgid "Value out of 16-bit range."
 msgstr ""
 
-#: config/tc-m68hc11.c:3293
+#: config/tc-m68hc11.c:3295
 #, c-format
 msgid "Value %ld too large for 8-bit PC-relative branch."
 msgstr ""
 
-#: config/tc-m68hc11.c:3300
+#: config/tc-m68hc11.c:3302
 #, c-format
 msgid "Auto increment/decrement offset '%ld' is out of range."
 msgstr ""
 
-#: config/tc-m68hc11.c:3313
+#: config/tc-m68hc11.c:3315
 #, c-format
 msgid "Offset out of 5-bit range for movw/movb insn: %ld"
 msgstr ""
 
-#: config/tc-m68hc11.c:3329
+#: config/tc-m68hc11.c:3331
 #, c-format
 msgid "Line %d: unknown relocation type: 0x%x."
 msgstr ""
 
-#: config/tc-m68k.c:696
-msgid "no matching ColdFire architectures found"
-msgstr ""
-
-#: config/tc-m68k.c:710
-msgid " or "
-msgstr ""
-
-#: config/tc-m68k.c:715
-msgid ", or "
-msgstr ""
-
-#: config/tc-m68k.c:732
-msgid ", or aliases"
-msgstr ""
-
-#: config/tc-m68k.c:843
+#: config/tc-m68k.c:1009
 #, c-format
 msgid "Can not do %d byte pc-relative relocation"
 msgstr ""
 
-#: config/tc-m68k.c:845
+#: config/tc-m68k.c:1011
 #, c-format
 msgid "Can not do %d byte pc-relative pic relocation"
 msgstr ""
 
-#: config/tc-m68k.c:850
+#: config/tc-m68k.c:1016
 #, c-format
 msgid "Can not do %d byte relocation"
 msgstr ""
 
-#: config/tc-m68k.c:852
+#: config/tc-m68k.c:1018
 #, c-format
 msgid "Can not do %d byte pic relocation"
 msgstr ""
 
-#: config/tc-m68k.c:915
+#: config/tc-m68k.c:1083
 #, c-format
 msgid "Unable to produce reloc against symbol '%s'"
 msgstr ""
 
-#: config/tc-m68k.c:959 config/tc-vax.c:3435
+#: config/tc-m68k.c:1127 config/tc-vax.c:2366
 #, c-format
 msgid "Cannot make %s relocation PC relative"
 msgstr ""
 
-#: config/tc-m68k.c:1050 config/tc-vax.c:1890
+#: config/tc-m68k.c:1226 config/tc-vax.c:1876
 msgid "No operator"
 msgstr ""
 
-#: config/tc-m68k.c:1080 config/tc-vax.c:1907
+#: config/tc-m68k.c:1256 config/tc-vax.c:1892
 msgid "Unknown operator"
 msgstr ""
 
-#: config/tc-m68k.c:1944
+#: config/tc-m68k.c:2143
 msgid "invalid instruction for this architecture; needs "
 msgstr ""
 
-#: config/tc-m68k.c:1950
+#: config/tc-m68k.c:2147
 msgid "ColdFire ISA_A"
 msgstr ""
 
-#: config/tc-m68k.c:1958
+#: config/tc-m68k.c:2150
 msgid "ColdFire hardware divide"
 msgstr ""
 
-#: config/tc-m68k.c:1966
+#: config/tc-m68k.c:2153
 msgid "ColdFire ISA_A+"
 msgstr ""
 
-#: config/tc-m68k.c:1974
+#: config/tc-m68k.c:2156
 msgid "ColdFire ISA_B"
 msgstr ""
 
-#: config/tc-m68k.c:1982
+#: config/tc-m68k.c:2159
 msgid "ColdFire fpu"
 msgstr ""
 
-#: config/tc-m68k.c:1989
-msgid "fpu (68040, 68060 or 68881/68882)"
+#: config/tc-m68k.c:2162
+msgid "M68K fpu"
 msgstr ""
 
-#: config/tc-m68k.c:1992
-msgid "mmu (68030 or 68851)"
+#: config/tc-m68k.c:2165
+msgid "M68K mmu"
 msgstr ""
 
-#: config/tc-m68k.c:1995
+#: config/tc-m68k.c:2168
 msgid "68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:1998
+#: config/tc-m68k.c:2171
 msgid "68000 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2001
+#: config/tc-m68k.c:2174
 msgid "68010 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2029
+#: config/tc-m68k.c:2227
 msgid "operands mismatch"
 msgstr ""
 
-#: config/tc-m68k.c:2090 config/tc-m68k.c:2096 config/tc-m68k.c:2102
-#: config/tc-mmix.c:2488 config/tc-mmix.c:2512
+#: config/tc-m68k.c:2290 config/tc-m68k.c:2296 config/tc-m68k.c:2302
+#: config/tc-mmix.c:2487 config/tc-mmix.c:2511
 msgid "operand out of range"
 msgstr ""
 
-#: config/tc-m68k.c:2159
+#: config/tc-m68k.c:2359
 #, c-format
 msgid "Bignum too big for %c format; truncated"
 msgstr ""
 
-#: config/tc-m68k.c:2236
+#: config/tc-m68k.c:2436
 msgid "displacement too large for this architecture; needs 68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2347
+#: config/tc-m68k.c:2547
 msgid ""
 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2352
+#: config/tc-m68k.c:2552
 msgid "invalid index size for coldfire"
 msgstr ""
 
-#: config/tc-m68k.c:2405
+#: config/tc-m68k.c:2605
 msgid "Forcing byte displacement"
 msgstr ""
 
-#: config/tc-m68k.c:2407
+#: config/tc-m68k.c:2607
 msgid "byte displacement out of range"
 msgstr ""
 
-#: config/tc-m68k.c:2455 config/tc-m68k.c:2493
+#: config/tc-m68k.c:2655 config/tc-m68k.c:2693
 msgid "invalid operand mode for this architecture; needs 68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2479 config/tc-m68k.c:2513
+#: config/tc-m68k.c:2679 config/tc-m68k.c:2713
 msgid ":b not permitted; defaulting to :w"
 msgstr ""
 
-#: config/tc-m68k.c:2590
+#: config/tc-m68k.c:2790
 msgid "unsupported byte value; use a different suffix"
 msgstr ""
 
-#: config/tc-m68k.c:2605
+#: config/tc-m68k.c:2805
 msgid "unknown/incorrect operand"
 msgstr ""
 
-#: config/tc-m68k.c:2648 config/tc-m68k.c:2656 config/tc-m68k.c:2663
-#: config/tc-m68k.c:2670
+#: config/tc-m68k.c:2848 config/tc-m68k.c:2856 config/tc-m68k.c:2863
+#: config/tc-m68k.c:2870
 msgid "out of range"
 msgstr ""
 
-#: config/tc-m68k.c:2716
-msgid "Can't use long branches on 68000/68010/5200"
+#: config/tc-m68k.c:2942
+msgid "Can't use long branches on this architecture"
 msgstr ""
 
-#: config/tc-m68k.c:2833
+#: config/tc-m68k.c:3047
 msgid "Expression out of range, using 0"
 msgstr ""
 
-#: config/tc-m68k.c:3014 config/tc-m68k.c:3030
+#: config/tc-m68k.c:3238 config/tc-m68k.c:3254
 msgid "Floating point register in register list"
 msgstr ""
 
-#: config/tc-m68k.c:3020
+#: config/tc-m68k.c:3244
 msgid "Wrong register in floating-point reglist"
 msgstr ""
 
-#: config/tc-m68k.c:3036
+#: config/tc-m68k.c:3260
 msgid "incorrect register in reglist"
 msgstr ""
 
-#: config/tc-m68k.c:3042
+#: config/tc-m68k.c:3266
 msgid "wrong register in floating-point reglist"
 msgstr ""
 
 #. ERROR.
-#: config/tc-m68k.c:3505
+#: config/tc-m68k.c:3729
 msgid "Extra )"
 msgstr ""
 
 #. ERROR.
-#: config/tc-m68k.c:3516
+#: config/tc-m68k.c:3740
 msgid "Missing )"
 msgstr ""
 
-#: config/tc-m68k.c:3533
+#: config/tc-m68k.c:3757
 msgid "Missing operand"
 msgstr ""
 
-#: config/tc-m68k.c:3890
+#: config/tc-m68k.c:4074
+#, c-format
+msgid "unrecognized default cpu `%s'"
+msgstr ""
+
+#: config/tc-m68k.c:4128
 #, c-format
 msgid "%s -- statement `%s' ignored"
 msgstr ""
 
-#: config/tc-m68k.c:3939
+#: config/tc-m68k.c:4177
 #, c-format
 msgid "Don't know how to figure width of %c in md_assemble()"
 msgstr ""
 
-#: config/tc-m68k.c:4108
+#: config/tc-m68k.c:4346
 #, c-format
 msgid "Internal Error:  Can't allocate m68k_sorted_opcodes of size %d"
 msgstr ""
 
-#: config/tc-m68k.c:4159 config/tc-m68k.c:4198
+#: config/tc-m68k.c:4397 config/tc-m68k.c:4436
 #, c-format
 msgid "Internal Error: Can't find %s in hash table"
 msgstr ""
 
-#: config/tc-m68k.c:4162 config/tc-m68k.c:4201
+#: config/tc-m68k.c:4400 config/tc-m68k.c:4439
 #, c-format
 msgid "Internal Error: Can't hash %s: %s"
 msgstr ""
 
-#: config/tc-m68k.c:4282
-msgid "architecture not yet selected: defaulting to 68020"
+#: config/tc-m68k.c:4564
+#, c-format
+msgid "text label `%s' aligned to odd boundary"
 msgstr ""
 
-#: config/tc-m68k.c:4342
+#: config/tc-m68k.c:4764
 #, c-format
-msgid "unrecognized default cpu `%s' ???"
+msgid "value %ld out of range"
 msgstr ""
 
-#: config/tc-m68k.c:4353
-msgid "68040 and 68851 specified; mmu instructions may assemble incorrectly"
+#: config/tc-m68k.c:4778
+msgid "invalid byte branch offset"
 msgstr ""
 
-#: config/tc-m68k.c:4370
-msgid "options for 68881 and no-68881 both given"
+#: config/tc-m68k.c:4814
+msgid "short branch with zero offset: use :w"
 msgstr ""
 
-#: config/tc-m68k.c:4373
-msgid "options for 68851 and no-68851 both given"
+#: config/tc-m68k.c:4839
+msgid "Conversion of PC relative BSR to absolute JSR"
 msgstr ""
 
-#: config/tc-m68k.c:4434
-#, c-format
-msgid "text label `%s' aligned to odd boundary"
+#: config/tc-m68k.c:4850
+msgid "Conversion of PC relative branch to absolute jump"
 msgstr ""
 
-#: config/tc-m68k.c:4638
-msgid "invalid byte branch offset"
+#: config/tc-m68k.c:4867 config/tc-m68k.c:4928
+msgid "Conversion of PC relative conditional branch to absolute jump"
 msgstr ""
 
-#: config/tc-m68k.c:4674
-msgid "short branch with zero offset: use :w"
+#: config/tc-m68k.c:4908
+msgid "Conversion of DBcc to absolute jump"
 msgstr ""
 
-#: config/tc-m68k.c:4698
-msgid "Tried to convert PC relative BSR to absolute JSR"
+#: config/tc-m68k.c:4992
+msgid "Conversion of PC relative displacement to absolute"
 msgstr ""
 
-#: config/tc-m68k.c:4708 config/tc-m68k.c:5054
+#: config/tc-m68k.c:5204
 msgid "Tried to convert PC relative branch to absolute jump"
 msgstr ""
 
-#: config/tc-m68k.c:4724 config/tc-m68k.c:4783 config/tc-m68k.c:4847
-msgid "Tried to convert PC relative conditional branch to absolute jump"
-msgstr ""
-
-#: config/tc-m68k.c:4764
-msgid "Tried to convert DBcc to absolute jump"
-msgstr ""
-
-#: config/tc-m68k.c:5098 config/tc-m68k.c:5109 config/tc-m68k.c:5149
+#: config/tc-m68k.c:5248 config/tc-m68k.c:5259 config/tc-m68k.c:5299
 msgid "expression out of range: defaulting to 1"
 msgstr ""
 
-#: config/tc-m68k.c:5141
+#: config/tc-m68k.c:5291
 msgid "expression out of range: defaulting to 0"
 msgstr ""
 
-#: config/tc-m68k.c:5182 config/tc-m68k.c:5194
+#: config/tc-m68k.c:5332 config/tc-m68k.c:5344
 #, c-format
 msgid "Can't deal with expression; defaulting to %ld"
 msgstr ""
 
-#: config/tc-m68k.c:5208
+#: config/tc-m68k.c:5358
 msgid "expression doesn't fit in BYTE"
 msgstr ""
 
-#: config/tc-m68k.c:5212
+#: config/tc-m68k.c:5362
 msgid "expression doesn't fit in WORD"
 msgstr ""
 
-#: config/tc-m68k.c:5299
+#: config/tc-m68k.c:5449
 #, c-format
 msgid "%s: unrecognized processor name"
 msgstr ""
 
-#: config/tc-m68k.c:5363
+#: config/tc-m68k.c:5510
 msgid "bad coprocessor id"
 msgstr ""
 
-#: config/tc-m68k.c:5369
+#: config/tc-m68k.c:5516
 msgid "unrecognized fopt option"
 msgstr ""
 
-#: config/tc-m68k.c:5502
+#: config/tc-m68k.c:5649
 #, c-format
 msgid "option `%s' may not be negated"
 msgstr ""
 
-#: config/tc-m68k.c:5513
+#: config/tc-m68k.c:5660
 #, c-format
 msgid "option `%s' not recognized"
 msgstr ""
 
-#: config/tc-m68k.c:5542
+#: config/tc-m68k.c:5689
 msgid "bad format of OPT NEST=depth"
 msgstr ""
 
-#: config/tc-m68k.c:5598
+#: config/tc-m68k.c:5745
 msgid "missing label"
 msgstr ""
 
-#: config/tc-m68k.c:5622 config/tc-m68k.c:5651
+#: config/tc-m68k.c:5769 config/tc-m68k.c:5798
 msgid "bad register list"
 msgstr ""
 
-#: config/tc-m68k.c:5624
+#: config/tc-m68k.c:5771
 #, c-format
 msgid "bad register list: %s"
 msgstr ""
 
-#: config/tc-m68k.c:5722
+#: config/tc-m68k.c:5869
 msgid "restore without save"
 msgstr ""
 
-#: config/tc-m68k.c:5876 config/tc-m68k.c:6246
+#: config/tc-m68k.c:6023 config/tc-m68k.c:6393
 msgid "syntax error in structured control directive"
 msgstr ""
 
-#: config/tc-m68k.c:5921
+#: config/tc-m68k.c:6068
 msgid "missing condition code in structured control directive"
 msgstr ""
 
-#: config/tc-m68k.c:5992
+#: config/tc-m68k.c:6139
 #, c-format
 msgid ""
 "Condition <%c%c> in structured control directive can not be encoded correctly"
 msgstr ""
 
-#: config/tc-m68k.c:6288
+#: config/tc-m68k.c:6435
 msgid "missing then"
 msgstr ""
 
-#: config/tc-m68k.c:6369
+#: config/tc-m68k.c:6516
 msgid "else without matching if"
 msgstr ""
 
-#: config/tc-m68k.c:6402
+#: config/tc-m68k.c:6549
 msgid "endi without matching if"
 msgstr ""
 
-#: config/tc-m68k.c:6442
+#: config/tc-m68k.c:6589
 msgid "break outside of structured loop"
 msgstr ""
 
-#: config/tc-m68k.c:6480
+#: config/tc-m68k.c:6627
 msgid "next outside of structured loop"
 msgstr ""
 
-#: config/tc-m68k.c:6531
+#: config/tc-m68k.c:6678
 msgid "missing ="
 msgstr ""
 
-#: config/tc-m68k.c:6569
+#: config/tc-m68k.c:6716
 msgid "missing to or downto"
 msgstr ""
 
-#: config/tc-m68k.c:6605 config/tc-m68k.c:6639 config/tc-m68k.c:6853
+#: config/tc-m68k.c:6752 config/tc-m68k.c:6786 config/tc-m68k.c:7000
 msgid "missing do"
 msgstr ""
 
-#: config/tc-m68k.c:6740
+#: config/tc-m68k.c:6887
 msgid "endf without for"
 msgstr ""
 
-#: config/tc-m68k.c:6794
+#: config/tc-m68k.c:6941
 msgid "until without repeat"
 msgstr ""
 
-#: config/tc-m68k.c:6888
+#: config/tc-m68k.c:7035
 msgid "endw without while"
 msgstr ""
 
-#: config/tc-m68k.c:7050
+#: config/tc-m68k.c:7068 config/tc-m68k.c:7096
+msgid "already assembled instructions"
+msgstr ""
+
+#: config/tc-m68k.c:7173
+#, c-format
+msgid "`%s' is deprecated, use `%s'"
+msgstr ""
+
+#: config/tc-m68k.c:7192
+#, c-format
+msgid "cpu `%s' unrecognized"
+msgstr ""
+
+#: config/tc-m68k.c:7198
+#, c-format
+msgid "already selected `%s' processor"
+msgstr ""
+
+#: config/tc-m68k.c:7218
+#, c-format
+msgid "architecture `%s' unrecognized"
+msgstr ""
+
+#: config/tc-m68k.c:7224
+#, c-format
+msgid "already selected `%s' architecture"
+msgstr ""
+
+#: config/tc-m68k.c:7247
 #, c-format
-msgid "unrecognized architecture specification `%s'"
+msgid "extension `%s' unrecognized"
 msgstr ""
 
-#: config/tc-m68k.c:7143
+#: config/tc-m68k.c:7365
+#, c-format
+msgid "option `-A%s' is deprecated: use `-%s'"
+msgstr ""
+
+#: config/tc-m68k.c:7398
+msgid "architecture features both enabled and disabled"
+msgstr ""
+
+#: config/tc-m68k.c:7425
+msgid "selected processor does not have all features of selected architecture"
+msgstr ""
+
+#: config/tc-m68k.c:7434
+msgid "m68k and cf features both selected"
+msgstr ""
+
+#: config/tc-m68k.c:7446
+msgid "68040 and 68851 specified; mmu instructions may assemble incorrectly"
+msgstr ""
+
+#: config/tc-m68k.c:7480
 #, c-format
 msgid ""
-"680X0 options:\n"
-"-l\t\t\tuse 1 word for refs to undefined symbols [default 2]\n"
-"-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n"
-"-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n"
-"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m521x  | -m5249  |\n"
-"-m528x  | -m5307  | -m5407  | -m547x  | -m548x  | -mcfv4  | -mcfv4e\n"
-"\t\t\tspecify variant of 680X0 architecture [default %s]\n"
-"-m68881 | -m68882 | -mno-68881 | -mno-68882\n"
-"\t\t\ttarget has/lacks floating-point coprocessor\n"
-"\t\t\t[default yes for 68020, 68030, and cpu32]\n"
+"-march=<arch>\t\tset architecture\n"
+"-mcpu=<cpu>\t\tset cpu [default %s]\n"
 msgstr ""
 
-#: config/tc-m68k.c:7155
+#: config/tc-m68k.c:7485
+#, c-format
+msgid "-m[no-]%-16s enable/disable%s architecture extension\n"
+msgstr ""
+
+#: config/tc-m68k.c:7491
 #, c-format
 msgid ""
-"-m68851 | -mno-68851\n"
-"\t\t\ttarget has/lacks memory-management unit coprocessor\n"
-"\t\t\t[default yes for 68020 and up]\n"
+"-l\t\t\tuse 1 word for refs to undefined symbols [default 2]\n"
 "-pic, -k\t\tgenerate position independent code\n"
 "-S\t\t\tturn jbsr into jsr\n"
 "--pcrel                 never turn PC-relative branches into absolute jumps\n"
 "--register-prefix-optional\n"
 "\t\t\trecognize register names without prefix character\n"
 "--bitwise-or\t\tdo not treat `|' as a comment character\n"
-msgstr ""
-
-#: config/tc-m68k.c:7165
-#, c-format
-msgid ""
 "--base-size-default-16\tbase reg without size is 16 bits\n"
 "--base-size-default-32\tbase reg without size is 32 bits (default)\n"
 "--disp-size-default-16\tdisplacement with unknown size is 16 bits\n"
 "--disp-size-default-32\tdisplacement with unknown size is 32 bits (default)\n"
 msgstr ""
 
-#: config/tc-m68k.c:7200
+#: config/tc-m68k.c:7505
+#, c-format
+msgid "Architecture variants are: "
+msgstr ""
+
+#: config/tc-m68k.c:7514
+#, c-format
+msgid "Processor variants are: "
+msgstr ""
+
+#: config/tc-m68k.c:7521 config/tc-xtensa.c:6029
+#, c-format
+msgid "\n"
+msgstr ""
+
+#: config/tc-m68k.c:7552
 #, c-format
 msgid "Error %s in %s\n"
 msgstr ""
 
-#: config/tc-m68k.c:7204
+#: config/tc-m68k.c:7556
 #, c-format
 msgid "Opcode(%d.%s): "
 msgstr ""
 
-#: config/tc-mcore.c:524
+#: config/tc-m68k.c:7715
+msgid "Not a defined coldfire architecture"
+msgstr ""
+
+#: config/tc-mcore.c:521
 #, c-format
 msgid "register expected, but saw '%.6s'"
 msgstr ""
 
-#: config/tc-mcore.c:606
+#: config/tc-mcore.c:603
 #, c-format
 msgid "control register expected, but saw '%.6s'"
 msgstr ""
 
-#: config/tc-mcore.c:642
+#: config/tc-mcore.c:639
 msgid "bad/missing psr specifier"
 msgstr ""
 
-#: config/tc-mcore.c:692
+#: config/tc-mcore.c:689
 msgid "more than 65K literal pools"
 msgstr ""
 
-#: config/tc-mcore.c:746
+#: config/tc-mcore.c:743
 msgid "missing ']'"
 msgstr ""
 
-#: config/tc-mcore.c:785
+#: config/tc-mcore.c:782
 msgid "operand must be a constant"
 msgstr ""
 
-#: config/tc-mcore.c:787
+#: config/tc-mcore.c:784
 #, c-format
 msgid "operand must be absolute in range %u..%u, not %ld"
 msgstr ""
 
-#: config/tc-mcore.c:822
+#: config/tc-mcore.c:819
 msgid "operand must be a multiple of 4"
 msgstr ""
 
-#: config/tc-mcore.c:829
+#: config/tc-mcore.c:826
 msgid "operand must be a multiple of 2"
 msgstr ""
 
-#: config/tc-mcore.c:843 config/tc-mcore.c:1359 config/tc-mcore.c:1413
+#: config/tc-mcore.c:840 config/tc-mcore.c:1356 config/tc-mcore.c:1410
 msgid "base register expected"
 msgstr ""
 
-#: config/tc-mcore.c:891
+#: config/tc-mcore.c:888
 #, c-format
 msgid "unknown opcode \"%s\""
 msgstr ""
 
-#: config/tc-mcore.c:934
+#: config/tc-mcore.c:931
 msgid "invalid register: r15 illegal"
 msgstr ""
 
-#: config/tc-mcore.c:983 config/tc-mcore.c:1564
+#: config/tc-mcore.c:980 config/tc-mcore.c:1561
 msgid "M340 specific opcode used when assembling for M210"
 msgstr ""
 
-#: config/tc-mcore.c:1001 config/tc-mcore.c:1041 config/tc-mcore.c:1060
-#: config/tc-mcore.c:1079 config/tc-mcore.c:1107 config/tc-mcore.c:1136
-#: config/tc-mcore.c:1173 config/tc-mcore.c:1208 config/tc-mcore.c:1227
-#: config/tc-mcore.c:1246 config/tc-mcore.c:1280 config/tc-mcore.c:1305
-#: config/tc-mcore.c:1362 config/tc-mcore.c:1416 config/tc-mcore.c:1452
-#: config/tc-mcore.c:1511 config/tc-mcore.c:1533 config/tc-mcore.c:1556
+#: config/tc-mcore.c:998 config/tc-mcore.c:1038 config/tc-mcore.c:1057
+#: config/tc-mcore.c:1076 config/tc-mcore.c:1104 config/tc-mcore.c:1133
+#: config/tc-mcore.c:1170 config/tc-mcore.c:1205 config/tc-mcore.c:1224
+#: config/tc-mcore.c:1243 config/tc-mcore.c:1277 config/tc-mcore.c:1302
+#: config/tc-mcore.c:1359 config/tc-mcore.c:1413 config/tc-mcore.c:1449
+#: config/tc-mcore.c:1508 config/tc-mcore.c:1530 config/tc-mcore.c:1553
 msgid "second operand missing"
 msgstr ""
 
-#: config/tc-mcore.c:1017
+#: config/tc-mcore.c:1014
 msgid "destination register must be r1"
 msgstr ""
 
-#: config/tc-mcore.c:1038
+#: config/tc-mcore.c:1035
 msgid "source register must be r1"
 msgstr ""
 
-#: config/tc-mcore.c:1102 config/tc-mcore.c:1159
+#: config/tc-mcore.c:1099 config/tc-mcore.c:1156
 msgid "immediate is not a power of two"
 msgstr ""
 
-#: config/tc-mcore.c:1130
+#: config/tc-mcore.c:1127
 msgid "translating bgeni to movi"
 msgstr ""
 
-#: config/tc-mcore.c:1167
+#: config/tc-mcore.c:1164
 msgid "translating mgeni to movi"
 msgstr ""
 
-#: config/tc-mcore.c:1199
+#: config/tc-mcore.c:1196
 msgid "translating bmaski to movi"
 msgstr ""
 
-#: config/tc-mcore.c:1275
+#: config/tc-mcore.c:1272
 #, c-format
 msgid "displacement too large (%d)"
 msgstr ""
 
-#: config/tc-mcore.c:1289
+#: config/tc-mcore.c:1286
 msgid "Invalid register: r0 and r15 illegal"
 msgstr ""
 
-#: config/tc-mcore.c:1320
+#: config/tc-mcore.c:1317
 msgid "bad starting register: r0 and r15 invalid"
 msgstr ""
 
-#: config/tc-mcore.c:1333
+#: config/tc-mcore.c:1330
 msgid "ending register must be r15"
 msgstr ""
 
-#: config/tc-mcore.c:1353
+#: config/tc-mcore.c:1350
 msgid "bad base register: must be r0"
 msgstr ""
 
-#: config/tc-mcore.c:1371
+#: config/tc-mcore.c:1368
 msgid "first register must be r4"
 msgstr ""
 
-#: config/tc-mcore.c:1382
+#: config/tc-mcore.c:1379
 msgid "last register must be r7"
 msgstr ""
 
-#: config/tc-mcore.c:1419
+#: config/tc-mcore.c:1416
 msgid "reg-reg expected"
 msgstr ""
 
-#: config/tc-mcore.c:1530
+#: config/tc-mcore.c:1527
 msgid "second operand must be 1"
 msgstr ""
 
-#: config/tc-mcore.c:1551
+#: config/tc-mcore.c:1548
 msgid "zero used as immediate value"
 msgstr ""
 
-#: config/tc-mcore.c:1578
+#: config/tc-mcore.c:1575
 msgid "duplicated psr bit specifier"
 msgstr ""
 
-#: config/tc-mcore.c:1584
+#: config/tc-mcore.c:1581
 msgid "`af' must appear alone"
 msgstr ""
 
-#: config/tc-mcore.c:1591
+#: config/tc-mcore.c:1588
 #, c-format
 msgid "unimplemented opcode \"%s\""
 msgstr ""
 
-#: config/tc-mcore.c:1600
+#: config/tc-mcore.c:1597
 #, c-format
 msgid "ignoring operands: %s "
 msgstr ""
 
-#: config/tc-mcore.c:1665
+#: config/tc-mcore.c:1662
 msgid "Bad call to MD_NTOF()"
 msgstr ""
 
-#: config/tc-mcore.c:1736
+#: config/tc-mcore.c:1733
 #, c-format
 msgid "unrecognised cpu type '%s'"
 msgstr ""
 
-#: config/tc-mcore.c:1754
+#: config/tc-mcore.c:1751
 #, c-format
 msgid ""
 "MCORE specific options:\n"
@@ -6675,671 +7243,763 @@ msgid ""
 "  -EL                     assemble for a little endian system\n"
 msgstr ""
 
-#: config/tc-mcore.c:1772
+#: config/tc-mcore.c:1769
 msgid "failed sanity check: short_jump"
 msgstr ""
 
-#: config/tc-mcore.c:1782
+#: config/tc-mcore.c:1779
 msgid "failed sanity check: long_jump"
 msgstr ""
 
-#: config/tc-mcore.c:1808
+#: config/tc-mcore.c:1805
 #, c-format
 msgid "odd displacement at %x"
 msgstr ""
 
-#: config/tc-mcore.c:1990
+#: config/tc-mcore.c:1987
 msgid "unknown"
 msgstr ""
 
-#: config/tc-mcore.c:2017
+#: config/tc-mcore.c:2014
 #, c-format
 msgid "odd distance branch (0x%lx bytes)"
 msgstr ""
 
-#: config/tc-mcore.c:2021
+#: config/tc-mcore.c:2018
 #, c-format
 msgid "pcrel for branch to %s too far (0x%lx)"
 msgstr ""
 
-#: config/tc-mcore.c:2041
+#: config/tc-mcore.c:2038
 #, c-format
 msgid "pcrel for lrw/jmpi/jsri to %s too far (0x%lx)"
 msgstr ""
 
-#: config/tc-mcore.c:2053
+#: config/tc-mcore.c:2050
 #, c-format
 msgid "pcrel for loopt too far (0x%lx)"
 msgstr ""
 
-#: config/tc-mcore.c:2263
+#: config/tc-mcore.c:2246
 #, c-format
 msgid "Can not do %d byte %srelocation"
 msgstr ""
 
-#: config/tc-mcore.c:2265
+#: config/tc-mcore.c:2248
 msgid "pc-relative"
 msgstr ""
 
+#: config/tc-mep.c:300
+#, c-format
+msgid ""
+"MeP specific command line options:\n"
+"  -EB                     assemble for a big endian system (default)\n"
+"  -EL                     assemble for a little endian system\n"
+"  -mconfig=<name>         specify a chip configuration to use\n"
+"  -maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n"
+"  -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n"
+"  -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n"
+"                          enable/disable the given opcodes\n"
+"\n"
+"  If -mconfig is given, the other -m options modify it.  Otherwise,\n"
+"  if no -m options are given, all core opcodes are enabled;\n"
+"  if any enabling -m options are given, only those are enabled;\n"
+"  if only disabling -m options are given, only those are disabled.\n"
+msgstr ""
+
+#. There are no insns in the queue and a plus is present.
+#. This is a syntax error.  Let's not tolerate this.
+#. We can relax this later if necessary.
+#: config/tc-mep.c:1007
+msgid "Invalid use of parallelization operator."
+msgstr ""
+
+#: config/tc-mep.c:1049
+msgid "Leading plus sign not allowed in core mode"
+msgstr ""
+
+#: config/tc-mep.c:1530
+#, c-format
+msgid "Don't know how to relocate plain operands of type %s"
+msgstr ""
+
+#: config/tc-mep.c:1540
+#, c-format
+msgid "Perhaps you are missing %%tpoff()?"
+msgstr ""
+
+#: config/tc-mep.c:1646
+msgid "Unmatched high relocation"
+msgstr ""
+
+#: config/tc-mep.c:1772
+msgid "Bad .section directive: want a,v,w,x,M,S in string"
+msgstr ""
+
+#: config/tc-mep.c:1830
+msgid ".vliw unavailable when VLIW is disabled."
+msgstr ""
+
 #. Prototypes for static functions.
-#: config/tc-mips.c:957
+#: config/tc-mips.c:988
 #, c-format
 msgid "internal Error, line %d, %s"
 msgstr ""
 
-#: config/tc-mips.c:1443
+#: config/tc-mips.c:1745
+msgid "-G may not be used in position-independent code"
+msgstr ""
+
+#: config/tc-mips.c:1792
 #, c-format
 msgid "internal: can't hash `%s': %s"
 msgstr ""
 
-#: config/tc-mips.c:1451
+#: config/tc-mips.c:1800
 #, c-format
 msgid "internal error: bad mips16 opcode: %s %s\n"
 msgstr ""
 
-#: config/tc-mips.c:1652
+#: config/tc-mips.c:1972
 #, c-format
 msgid "returned from mips_ip(%s) insn_opcode = 0x%x\n"
 msgstr ""
 
-#: config/tc-mips.c:2327 config/tc-mips.c:13480
+#: config/tc-mips.c:2681 config/tc-mips.c:14040
 msgid "extended instruction in delay slot"
 msgstr ""
 
-#: config/tc-mips.c:2391 config/tc-mips.c:2401
+#: config/tc-mips.c:2745 config/tc-mips.c:2752
 #, c-format
 msgid "jump to misaligned address (0x%lx)"
 msgstr ""
 
-#: config/tc-mips.c:2394 config/tc-mips.c:2404
+#: config/tc-mips.c:2762 config/tc-mips.c:3524
+#, c-format
+msgid "branch to misaligned address (0x%lx)"
+msgstr ""
+
+#: config/tc-mips.c:2767 config/tc-mips.c:3527
 #, c-format
-msgid "jump address range overflow (0x%lx)"
+msgid "branch address range overflow (0x%lx)"
 msgstr ""
 
-#: config/tc-mips.c:2893
+#: config/tc-mips.c:3252
 msgid ""
 "Macro instruction expanded into multiple instructions in a branch delay slot"
 msgstr ""
 
-#: config/tc-mips.c:2896
+#: config/tc-mips.c:3255
 msgid "Macro instruction expanded into multiple instructions"
 msgstr ""
 
-#: config/tc-mips.c:3414 config/tc-mips.c:7338 config/tc-mips.c:7362
-#: config/tc-mips.c:7435 config/tc-mips.c:7458
+#: config/tc-mips.c:3796 config/tc-mips.c:7741 config/tc-mips.c:7765
+#: config/tc-mips.c:7838 config/tc-mips.c:7861
 msgid "operand overflow"
 msgstr ""
 
-#: config/tc-mips.c:3433 config/tc-mips.c:4033 config/tc-mips.c:6734
-#: config/tc-mips.c:7525
+#: config/tc-mips.c:3815 config/tc-mips.c:4415 config/tc-mips.c:7137
+#: config/tc-mips.c:7928
 msgid "Macro used $at after \".set noat\""
 msgstr ""
 
-#: config/tc-mips.c:3462
+#: config/tc-mips.c:3844
 msgid "unsupported large constant"
 msgstr ""
 
-#: config/tc-mips.c:3464
+#: config/tc-mips.c:3846
 #, c-format
 msgid "Instruction %s requires absolute expression"
 msgstr ""
 
-#: config/tc-mips.c:3597 config/tc-mips.c:5844 config/tc-mips.c:6438
+#: config/tc-mips.c:3979 config/tc-mips.c:6249 config/tc-mips.c:6841
 #, c-format
 msgid "Number (0x%s) larger than 32 bits"
 msgstr ""
 
-#: config/tc-mips.c:3617
+#: config/tc-mips.c:3999
 msgid "Number larger than 64 bits"
 msgstr ""
 
-#: config/tc-mips.c:3911 config/tc-mips.c:3939 config/tc-mips.c:3977
-#: config/tc-mips.c:4022 config/tc-mips.c:6053 config/tc-mips.c:6092
-#: config/tc-mips.c:6131 config/tc-mips.c:6553 config/tc-mips.c:6605
+#: config/tc-mips.c:4293 config/tc-mips.c:4321 config/tc-mips.c:4359
+#: config/tc-mips.c:4404 config/tc-mips.c:6458 config/tc-mips.c:6497
+#: config/tc-mips.c:6536 config/tc-mips.c:6956 config/tc-mips.c:7008
+#: config/tc-score.c:4239
 msgid "PIC code offset overflow (max 16 signed bits)"
 msgstr ""
 
-#: config/tc-mips.c:4328 config/tc-mips.c:4394 config/tc-mips.c:4482
-#: config/tc-mips.c:4529 config/tc-mips.c:4590 config/tc-mips.c:4638
-#: config/tc-mips.c:7619 config/tc-mips.c:7626 config/tc-mips.c:7633
-#: config/tc-mips.c:7740
+#: config/tc-mips.c:4726 config/tc-mips.c:4792 config/tc-mips.c:4880
+#: config/tc-mips.c:4927 config/tc-mips.c:4988 config/tc-mips.c:5036
+#: config/tc-mips.c:8022 config/tc-mips.c:8029 config/tc-mips.c:8036
+#: config/tc-mips.c:8143
 msgid "Unsupported large constant"
 msgstr ""
 
 #. result is always true
-#: config/tc-mips.c:4360
+#: config/tc-mips.c:4758
 #, c-format
 msgid "Branch %s is always true"
 msgstr ""
 
-#: config/tc-mips.c:4601 config/tc-mips.c:4649 config/tc-mips.c:8309
+#: config/tc-mips.c:4999 config/tc-mips.c:5047 config/tc-mips.c:8808
 #, c-format
 msgid "Improper position (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:4607 config/tc-mips.c:8376
+#: config/tc-mips.c:5005 config/tc-mips.c:8875
 #, c-format
 msgid "Improper extract size (%lu, position %lu)"
 msgstr ""
 
-#: config/tc-mips.c:4655 config/tc-mips.c:8340
+#: config/tc-mips.c:5053 config/tc-mips.c:8839
 #, c-format
 msgid "Improper insert size (%lu, position %lu)"
 msgstr ""
 
-#: config/tc-mips.c:4692 config/tc-mips.c:4789
+#: config/tc-mips.c:5090 config/tc-mips.c:5187
 msgid "Divide by zero."
 msgstr ""
 
-#: config/tc-mips.c:4875
+#: config/tc-mips.c:5273
 msgid "dla used to load 32-bit register"
 msgstr ""
 
-#: config/tc-mips.c:4878
+#: config/tc-mips.c:5276
 msgid "la used to load 64-bit address"
 msgstr ""
 
-#: config/tc-mips.c:4990
+#: config/tc-mips.c:5388 config/tc-z80.c:700
 msgid "offset too large"
 msgstr ""
 
-#: config/tc-mips.c:5162 config/tc-mips.c:5441
+#: config/tc-mips.c:5562 config/tc-mips.c:5841
 msgid "PIC code offset overflow (max 32 signed bits)"
 msgstr ""
 
-#: config/tc-mips.c:5487
+#: config/tc-mips.c:5887
 msgid "MIPS PIC call to register other than $25"
 msgstr ""
 
-#: config/tc-mips.c:5493 config/tc-mips.c:5504 config/tc-mips.c:5628
-#: config/tc-mips.c:5639
+#: config/tc-mips.c:5893 config/tc-mips.c:5904 config/tc-mips.c:6026
+#: config/tc-mips.c:6037
 msgid "No .cprestore pseudo-op used in PIC code"
 msgstr ""
 
-#: config/tc-mips.c:5498 config/tc-mips.c:5633
+#: config/tc-mips.c:5898 config/tc-mips.c:6031
 msgid "No .frame pseudo-op used in PIC code"
 msgstr ""
 
-#: config/tc-mips.c:5704 config/tc-mips.c:5792 config/tc-mips.c:6338
-#: config/tc-mips.c:6369 config/tc-mips.c:6387 config/tc-mips.c:7037
+#: config/tc-mips.c:6052
+msgid "Non-PIC jump used in PIC library"
+msgstr ""
+
+#: config/tc-mips.c:6104 config/tc-mips.c:6195 config/tc-mips.c:6741
+#: config/tc-mips.c:6772 config/tc-mips.c:6790 config/tc-mips.c:7440
 msgid "opcode not supported on this processor"
 msgstr ""
 
-#: config/tc-mips.c:6903 config/tc-mips.c:6934 config/tc-mips.c:6985
-#: config/tc-mips.c:7015
+#: config/tc-mips.c:7306 config/tc-mips.c:7337 config/tc-mips.c:7388
+#: config/tc-mips.c:7418
 msgid "Improper rotate count"
 msgstr ""
 
-#: config/tc-mips.c:7070
+#: config/tc-mips.c:7473
 #, c-format
 msgid "Instruction %s: result is always false"
 msgstr ""
 
-#: config/tc-mips.c:7216
+#: config/tc-mips.c:7619
 #, c-format
 msgid "Instruction %s: result is always true"
 msgstr ""
 
 #. FIXME: Check if this is one of the itbl macros, since they
 #. are added dynamically.
-#: config/tc-mips.c:7521
+#: config/tc-mips.c:7924
 #, c-format
 msgid "Macro %s not implemented yet"
 msgstr ""
 
-#: config/tc-mips.c:7771
+#: config/tc-mips.c:8174
 #, c-format
 msgid "internal: bad mips opcode (mask error): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:7799 config/tc-mips.c:8430
+#: config/tc-mips.c:8206 config/tc-mips.c:8929
 #, c-format
 msgid "internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:7876
+#: config/tc-mips.c:8284
 #, c-format
 msgid "internal: bad mips opcode (unknown operand type `%c'): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:7883
+#: config/tc-mips.c:8291
 #, c-format
 msgid "internal: bad mips opcode (bits 0x%lx undefined): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:8000
+#: config/tc-mips.c:8473 config/tc-mips.c:9806
 #, c-format
 msgid "opcode not supported on this processor: %s (%s)"
 msgstr ""
 
-#: config/tc-mips.c:8031 config/tc-mips.c:8045 config/tc-mips.c:8059
-#: config/tc-mips.c:8073 config/tc-mips.c:8100 config/tc-mips.c:8147
+#: config/tc-mips.c:8506
+#, c-format
+msgid "BALIGN immediate not 1 or 3 (%lu)"
+msgstr ""
+
+#: config/tc-mips.c:8519 config/tc-mips.c:8532 config/tc-mips.c:8545
+#: config/tc-mips.c:8558 config/tc-mips.c:8584 config/tc-mips.c:8628
 #, c-format
 msgid "DSP immediate not in range 0..%d (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8092 config/tc-mips.c:8120
+#: config/tc-mips.c:8576 config/tc-mips.c:8603
 msgid "Invalid dsp acc register"
 msgstr ""
 
-#: config/tc-mips.c:8131 config/tc-mips.c:8165 config/tc-mips.c:8184
+#: config/tc-mips.c:8614 config/tc-mips.c:8645 config/tc-mips.c:8662
 #, c-format
 msgid "DSP immediate not in range %ld..%ld (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:8200 config/tc-mips.c:8214
+#: config/tc-mips.c:8675
+#, c-format
+msgid "MT usermode bit not 0 or 1 (%lu)"
+msgstr ""
+
+#: config/tc-mips.c:8686
 #, c-format
-msgid "MT immediate not in range 0..%d (%lu)"
+msgid "MT load high bit not 0 or 1 (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8233 config/tc-mips.c:8246
+#: config/tc-mips.c:8703 config/tc-mips.c:8716
 msgid "Invalid dsp/smartmips acc register"
 msgstr ""
 
-#: config/tc-mips.c:8395 config/tc-mips.c:8899
+#: config/tc-mips.c:8781
+#, c-format
+msgid "Illegal %s number (%lu, 0x%lx)"
+msgstr ""
+
+#: config/tc-mips.c:8894 config/tc-mips.c:9315
 msgid "absolute expression required"
 msgstr ""
 
-#: config/tc-mips.c:8418 config/tc-mips.c:8579
+#: config/tc-mips.c:8917
 #, c-format
 msgid "Invalid register number (%d)"
 msgstr ""
 
-#: config/tc-mips.c:8426
+#: config/tc-mips.c:8925
 msgid "Invalid coprocessor 0 register number"
 msgstr ""
 
-#: config/tc-mips.c:8447
+#: config/tc-mips.c:8946
 #, c-format
 msgid "Improper shift amount (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8470 config/tc-mips.c:9731 config/tc-mips.c:9844
+#: config/tc-mips.c:8969 config/tc-mips.c:10119 config/tc-mips.c:10372
 #, c-format
 msgid "Invalid value for `%s' (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8485
+#: config/tc-mips.c:8984
 #, c-format
-msgid "Illegal break code (%lu)"
+msgid "Code for %s not in range 0..1023 (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8496
+#: config/tc-mips.c:8996
 #, c-format
-msgid "Illegal lower break code (%lu)"
+msgid "Lower code for %s not in range 0..1023 (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8507
+#: config/tc-mips.c:9008
 #, c-format
-msgid "Illegal 20-bit code (%lu)"
+msgid "Code for %s not in range 0..1048575 (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8519
+#: config/tc-mips.c:9021
 #, c-format
 msgid "Coproccesor code > 25 bits (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8532
+#: config/tc-mips.c:9035
 #, c-format
 msgid "Illegal 19-bit code (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8543
+#: config/tc-mips.c:9048
 #, c-format
 msgid "Invalid performance register (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8754
+#: config/tc-mips.c:9188
 #, c-format
 msgid "Invalid MDMX Immediate (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:8794
-#, c-format
-msgid "Invalid float register number (%d)"
-msgstr ""
-
-#: config/tc-mips.c:8810
+#: config/tc-mips.c:9226
 #, c-format
 msgid "Float register should be even, was %d"
 msgstr ""
 
-#: config/tc-mips.c:8849
+#: config/tc-mips.c:9265
 #, c-format
 msgid "Bad element selector %ld"
 msgstr ""
 
-#: config/tc-mips.c:8857
+#: config/tc-mips.c:9273
 #, c-format
 msgid "Expecting ']' found '%s'"
 msgstr ""
 
-#: config/tc-mips.c:8963
+#: config/tc-mips.c:9379
 #, c-format
 msgid "Bad floating point constant: %s"
 msgstr ""
 
-#: config/tc-mips.c:9084
+#: config/tc-mips.c:9499
 msgid "Can't use floating point insn in this section"
 msgstr ""
 
-#: config/tc-mips.c:9145
+#: config/tc-mips.c:9560
 msgid "expression out of range"
 msgstr ""
 
-#: config/tc-mips.c:9185
+#: config/tc-mips.c:9600
 msgid "lui expression not in range 0..65535"
 msgstr ""
 
-#: config/tc-mips.c:9209
-#, c-format
-msgid "Invalid condition code register $fcc%d"
-msgstr ""
-
-#: config/tc-mips.c:9214
+#: config/tc-mips.c:9621
 #, c-format
 msgid "Condition code register should be even for %s, was %d"
 msgstr ""
 
-#: config/tc-mips.c:9219
+#: config/tc-mips.c:9626
 #, c-format
 msgid "Condition code register should be 0 or 4 for %s, was %d"
 msgstr ""
 
-#: config/tc-mips.c:9245
+#: config/tc-mips.c:9652
 msgid "invalid coprocessor sub-selection value (0-7)"
 msgstr ""
 
-#: config/tc-mips.c:9257 config/tc-mips.c:9274
+#: config/tc-mips.c:9664 config/tc-mips.c:9681
 #, c-format
 msgid "bad byte vector index (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:9285
+#: config/tc-mips.c:9692
 #, c-format
 msgid "bad char = '%c'\n"
 msgstr ""
 
-#: config/tc-mips.c:9296 config/tc-mips.c:9301 config/tc-mips.c:9869
+#: config/tc-mips.c:9703 config/tc-mips.c:9708 config/tc-mips.c:10397
 msgid "illegal operands"
 msgstr ""
 
-#: config/tc-mips.c:9367
+#: config/tc-mips.c:9776 config/tc-score.c:2418
 msgid "unrecognized opcode"
 msgstr ""
 
-#: config/tc-mips.c:9504
-#, c-format
-msgid "invalid register number (%d)"
-msgstr ""
-
-#: config/tc-mips.c:9595
+#: config/tc-mips.c:9983
 msgid "used $at without \".set noat\""
 msgstr ""
 
-#: config/tc-mips.c:9763
+#: config/tc-mips.c:10155 config/tc-mips.c:10236 config/tc-mips.c:10251
 msgid "can't parse register list"
 msgstr ""
 
-#: config/tc-mips.c:9987
+#: config/tc-mips.c:10224
+msgid "more than one frame size in list"
+msgstr ""
+
+#: config/tc-mips.c:10279
+msgid "unexpected register in list"
+msgstr ""
+
+#: config/tc-mips.c:10289
+msgid "arg/static registers overlap"
+msgstr ""
+
+#: config/tc-mips.c:10307
+msgid "invalid arg register list"
+msgstr ""
+
+#: config/tc-mips.c:10316 config/tc-mips.c:10339
+msgid "invalid static register list"
+msgstr ""
+
+#: config/tc-mips.c:10346
+msgid "missing frame size"
+msgstr ""
+
+#: config/tc-mips.c:10349
+msgid "invalid frame size"
+msgstr ""
+
+#: config/tc-mips.c:10515
 msgid "extended operand requested but not required"
 msgstr ""
 
-#: config/tc-mips.c:9989
+#: config/tc-mips.c:10517
 msgid "invalid unextended operand value"
 msgstr ""
 
-#: config/tc-mips.c:10017
+#: config/tc-mips.c:10545
 msgid "operand value out of range for instruction"
 msgstr ""
 
-#: config/tc-mips.c:10469
+#: config/tc-mips.c:11007
 #, c-format
 msgid "A different %s was already specified, is now %s"
 msgstr ""
 
-#: config/tc-mips.c:10689
+#: config/tc-mips.c:11242
 msgid "-call_shared is supported only for ELF format"
 msgstr ""
 
-#: config/tc-mips.c:10696 config/tc-mips.c:10725 config/tc-mips.c:11834
-#: config/tc-mips.c:12060
-msgid "-G may not be used with SVR4 PIC code"
-msgstr ""
-
-#: config/tc-mips.c:10705
+#: config/tc-mips.c:11252
 msgid "-non_shared is supported only for ELF format"
 msgstr ""
 
-#: config/tc-mips.c:10736
+#: config/tc-mips.c:11278
 msgid "-32 is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10745
+#: config/tc-mips.c:11287
 msgid "-n32 is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10754
+#: config/tc-mips.c:11296
 msgid "-64 is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10759 config/tc-mips.c:10796
+#: config/tc-mips.c:11301 config/tc-mips.c:11338
 msgid "No compiled in support for 64 bit object file format"
 msgstr ""
 
-#: config/tc-mips.c:10783
+#: config/tc-mips.c:11325
 msgid "-mabi is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10803
+#: config/tc-mips.c:11345
 #, c-format
 msgid "invalid abi -mabi=%s"
 msgstr ""
 
-#: config/tc-mips.c:10877
+#: config/tc-mips.c:11423
 msgid "-G not supported in this configuration."
 msgstr ""
 
-#: config/tc-mips.c:10903
+#: config/tc-mips.c:11449
 #, c-format
 msgid "-%s conflicts with the other architecture options, which imply -%s"
 msgstr ""
 
-#: config/tc-mips.c:10934
+#: config/tc-mips.c:11480
 msgid "-mgp64 used with a 32-bit processor"
 msgstr ""
 
-#: config/tc-mips.c:10936
+#: config/tc-mips.c:11482
 msgid "-mgp32 used with a 64-bit ABI"
 msgstr ""
 
-#: config/tc-mips.c:10938
+#: config/tc-mips.c:11484
 msgid "-mgp64 used with a 32-bit ABI"
 msgstr ""
 
-#: config/tc-mips.c:10968
+#: config/tc-mips.c:11522
+msgid "-mfp64 used with a 32-bit fpu"
+msgstr ""
+
+#: config/tc-mips.c:11525
+msgid "-mfp64 used with a 32-bit ABI"
+msgstr ""
+
+#: config/tc-mips.c:11529
+msgid "-mfp32 used with a 64-bit ABI"
+msgstr ""
+
+#: config/tc-mips.c:11543
 msgid "trap exception not supported at ISA 1"
 msgstr ""
 
-#: config/tc-mips.c:11229
-msgid "Cannot branch to undefined symbol."
+#: config/tc-mips.c:11553
+msgid "-mfp32 used with -mips3d"
 msgstr ""
 
-#: config/tc-mips.c:11236
-msgid "Cannot branch to symbol in another section."
+#: config/tc-mips.c:11559
+msgid "-mfp32 used with -mdmx"
 msgstr ""
 
-#: config/tc-mips.c:11245
-msgid "Pretending global symbol used as branch target is local."
+#: config/tc-mips.c:11632
+msgid "PC relative MIPS16 instruction references a different section"
 msgstr ""
 
-#: config/tc-mips.c:11402 config/tc-sparc.c:3229 config/tc-sparc.c:3236
-#: config/tc-sparc.c:3243 config/tc-sparc.c:3250 config/tc-sparc.c:3257
-#: config/tc-sparc.c:3266 config/tc-sparc.c:3277 config/tc-sparc.c:3299
-#: config/tc-sparc.c:3323 write.c:861 write.c:933
+#: config/tc-mips.c:11923 config/tc-sparc.c:3283 config/tc-sparc.c:3290
+#: config/tc-sparc.c:3297 config/tc-sparc.c:3304 config/tc-sparc.c:3311
+#: config/tc-sparc.c:3320 config/tc-sparc.c:3331 config/tc-sparc.c:3353
+#: config/tc-sparc.c:3377 write.c:1096
 msgid "relocation overflow"
 msgstr ""
 
-#: config/tc-mips.c:11412
+#: config/tc-mips.c:11933
 #, c-format
-msgid "Branch to odd address (%lx)"
+msgid "Branch to misaligned address (%lx)"
 msgstr ""
 
-#: config/tc-mips.c:11461
+#: config/tc-mips.c:11980
 msgid "Branch out of range"
 msgstr ""
 
-#: config/tc-mips.c:11540
+#: config/tc-mips.c:12055
 #, c-format
 msgid "Alignment too large: %d. assumed."
 msgstr ""
 
-#: config/tc-mips.c:11543
+#: config/tc-mips.c:12058
 msgid "Alignment negative: 0 assumed."
 msgstr ""
 
-#: config/tc-mips.c:11780
+#: config/tc-mips.c:12302
 #, c-format
 msgid "%s: no such section"
 msgstr ""
 
-#: config/tc-mips.c:11829
+#: config/tc-mips.c:12351
 #, c-format
 msgid ".option pic%d not supported"
 msgstr ""
 
-#: config/tc-mips.c:11840
+#: config/tc-mips.c:12356 config/tc-mips.c:12648
+msgid "-G may not be used with SVR4 PIC code"
+msgstr ""
+
+#: config/tc-mips.c:12362
 #, c-format
 msgid "Unrecognized option \"%s\""
 msgstr ""
 
-#: config/tc-mips.c:11893
+#: config/tc-mips.c:12415
 msgid "`noreorder' must be set before `nomacro'"
 msgstr ""
 
-#: config/tc-mips.c:11952
+#: config/tc-mips.c:12532
 #, c-format
 msgid "unknown architecture %s"
 msgstr ""
 
-#: config/tc-mips.c:11965 config/tc-mips.c:11995
+#: config/tc-mips.c:12545 config/tc-mips.c:12575
 #, c-format
 msgid "unknown ISA level %s"
 msgstr ""
 
-#: config/tc-mips.c:11973
+#: config/tc-mips.c:12553
 #, c-format
 msgid "unknown ISA or architecture %s"
 msgstr ""
 
-#: config/tc-mips.c:12023
+#: config/tc-mips.c:12603
 msgid ".set pop with no .set push"
 msgstr ""
 
-#: config/tc-mips.c:12044
+#: config/tc-mips.c:12632
 #, c-format
 msgid "Tried to set unrecognized symbol: %s\n"
 msgstr ""
 
-#: config/tc-mips.c:12102
+#: config/tc-mips.c:12690
 msgid ".cpload not in noreorder section"
 msgstr ""
 
-#: config/tc-mips.c:12171 config/tc-mips.c:12190
+#: config/tc-mips.c:12758 config/tc-mips.c:12777
 msgid "missing argument separator ',' for .cpsetup"
 msgstr ""
 
-#: config/tc-mips.c:12380
+#: config/tc-mips.c:12971 config/tc-score.c:6323
 msgid "Unsupported use of .gpword"
 msgstr ""
 
-#: config/tc-mips.c:12416
+#: config/tc-mips.c:13011
 msgid "Unsupported use of .gpdword"
 msgstr ""
 
-#: config/tc-mips.c:12548
-msgid "expected `$'"
-msgstr ""
-
-#: config/tc-mips.c:12556
-msgid "Bad register number"
-msgstr ""
-
-#: config/tc-mips.c:12604
-msgid "Unrecognized register name"
-msgstr ""
-
-#: config/tc-mips.c:12837
+#: config/tc-mips.c:13356
 msgid "unsupported PC relative reference to different section"
 msgstr ""
 
-#: config/tc-mips.c:12950 config/tc-xtensa.c:1593 config/tc-xtensa.c:1804
+#: config/tc-mips.c:13469 config/tc-xtensa.c:1537 config/tc-xtensa.c:1772
 msgid "unsupported relocation"
 msgstr ""
 
-#: config/tc-mips.c:13158
+#: config/tc-mips.c:13719
 #, c-format
 msgid "Can not represent %s relocation in this object file format"
 msgstr ""
 
-#: config/tc-mips.c:13244
+#: config/tc-mips.c:13804
 msgid "relaxed out-of-range branch into a jump"
 msgstr ""
 
-#: config/tc-mips.c:13766
+#: config/tc-mips.c:14334
 msgid "missing .end at end of assembly"
 msgstr ""
 
-#: config/tc-mips.c:13781
+#: config/tc-mips.c:14349 config/tc-score.c:5929
 msgid "expected simple number"
 msgstr ""
 
-#: config/tc-mips.c:13807
+#: config/tc-mips.c:14375 config/tc-score.c:5955
 #, c-format
 msgid " *input_line_pointer == '%c' 0x%02x\n"
 msgstr ""
 
-#: config/tc-mips.c:13809
+#: config/tc-mips.c:14377 config/tc-score.c:5956
 msgid "invalid number"
 msgstr ""
 
-#: config/tc-mips.c:13882
+#: config/tc-mips.c:14450 config/tc-score.c:6105
 msgid ".end not in text section"
 msgstr ""
 
-#: config/tc-mips.c:13886
+#: config/tc-mips.c:14454 config/tc-score.c:6108
 msgid ".end directive without a preceding .ent directive."
 msgstr ""
 
-#: config/tc-mips.c:13895
+#: config/tc-mips.c:14463 config/tc-score.c:6116
 msgid ".end symbol does not match .ent symbol."
 msgstr ""
 
-#: config/tc-mips.c:13902
+#: config/tc-mips.c:14470 config/tc-score.c:6121
 msgid ".end directive missing or unknown symbol"
 msgstr ""
 
-#: config/tc-mips.c:13978
+#: config/tc-mips.c:14545 config/tc-score.c:5994
 msgid ".ent or .aent not in text section."
 msgstr ""
 
-#: config/tc-mips.c:13981
+#: config/tc-mips.c:14548 config/tc-score.c:5996
 msgid "missing .end"
 msgstr ""
 
-#: config/tc-mips.c:14033
+#: config/tc-mips.c:14600
 msgid "Bad .frame directive"
 msgstr ""
 
-#: config/tc-mips.c:14065
+#: config/tc-mips.c:14632
 msgid ".mask/.fmask outside of .ent"
 msgstr ""
 
-#: config/tc-mips.c:14072
+#: config/tc-mips.c:14639
 msgid "Bad .mask/.fmask directive"
 msgstr ""
 
-#: config/tc-mips.c:14337
+#: config/tc-mips.c:14934
 #, c-format
 msgid ""
 "MIPS options:\n"
@@ -7350,7 +8010,7 @@ msgid ""
 "\t\t\timplicitly with the gp register [default 8]\n"
 msgstr ""
 
-#: config/tc-mips.c:14344
+#: config/tc-mips.c:14941
 #, c-format
 msgid ""
 "-mips1\t\t\tgenerate MIPS ISA I instructions\n"
@@ -7365,7 +8025,7 @@ msgid ""
 "-march=CPU/-mtune=CPU\tgenerate code/schedule for CPU, where CPU is one of:\n"
 msgstr ""
 
-#: config/tc-mips.c:14363
+#: config/tc-mips.c:14960
 #, c-format
 msgid ""
 "-mCPU\t\t\tequivalent to -march=CPU -mtune=CPU. Deprecated.\n"
@@ -7373,35 +8033,48 @@ msgid ""
 "\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n"
 msgstr ""
 
-#: config/tc-mips.c:14376
+#: config/tc-mips.c:14973
 #, c-format
 msgid ""
 "-mips16\t\t\tgenerate mips16 instructions\n"
 "-no-mips16\t\tdo not generate mips16 instructions\n"
 msgstr ""
 
-#: config/tc-mips.c:14379
+#: config/tc-mips.c:14976
+#, c-format
+msgid ""
+"-msmartmips\t\tgenerate smartmips instructions\n"
+"-mno-smartmips\t\tdo not generate smartmips instructions\n"
+msgstr ""
+
+#: config/tc-mips.c:14979
 #, c-format
 msgid ""
 "-mdsp\t\t\tgenerate DSP instructions\n"
 "-mno-dsp\t\tdo not generate DSP instructions\n"
 msgstr ""
 
-#: config/tc-mips.c:14382
+#: config/tc-mips.c:14982
+#, c-format
+msgid ""
+"-mdspr2\t\t\tgenerate DSP R2 instructions\n"
+"-mno-dspr2\t\tdo not generate DSP R2 instructions\n"
+msgstr ""
+
+#: config/tc-mips.c:14985
 #, c-format
 msgid ""
 "-mmt\t\t\tgenerate MT instructions\n"
 "-mno-mt\t\t\tdo not generate MT instructions\n"
 msgstr ""
 
-#: config/tc-mips.c:14385
+#: config/tc-mips.c:14988
 #, c-format
 msgid ""
 "-mfix-vr4120\t\twork around certain VR4120 errata\n"
 "-mfix-vr4130\t\twork around VR4130 mflo/mfhi errata\n"
 "-mgp32\t\t\tuse 32-bit GPRs, regardless of the chosen ISA\n"
 "-mfp32\t\t\tuse 32-bit FPRs, regardless of the chosen ISA\n"
-"-mno-shared\t\toptimize output for executables\n"
 "-msym32\t\t\tassume all symbols have 32-bit values\n"
 "-O0\t\t\tremove unneeded NOPs, do not swap branches\n"
 "-O\t\t\tremove unneeded NOPs and swap branches\n"
@@ -7410,19 +8083,20 @@ msgid ""
 "--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"
 msgstr ""
 
-#: config/tc-mips.c:14398
+#: config/tc-mips.c:15000
 #, c-format
 msgid ""
 "-KPIC, -call_shared\tgenerate SVR4 position independent code\n"
+"-mvxworks-pic\t\tgenerate VxWorks position independent code\n"
 "-non_shared\t\tdo not generate position independent code\n"
 "-xgot\t\t\tassume a 32 bit GOT\n"
 "-mpdr, -mno-pdr\t\tenable/disable creation of .pdr sections\n"
 "-mshared, -mno-shared   disable/enable .cpload optimization for\n"
-"                        non-shared code\n"
+"                        position dependent (non shared) code\n"
 "-mabi=ABI\t\tcreate ABI conformant object file for:\n"
 msgstr ""
 
-#: config/tc-mips.c:14417
+#: config/tc-mips.c:15020
 #, c-format
 msgid ""
 "-32\t\t\tcreate o32 ABI object file (default)\n"
@@ -7430,54 +8104,54 @@ msgid ""
 "-64\t\t\tcreate 64 ABI object file\n"
 msgstr ""
 
-#: config/tc-mmix.c:694
+#: config/tc-mmix.c:693
 #, c-format
 msgid " MMIX-specific command line options:\n"
 msgstr ""
 
-#: config/tc-mmix.c:695
+#: config/tc-mmix.c:694
 #, c-format
 msgid ""
 "  -fixed-special-register-names\n"
 "                          Allow only the original special register names.\n"
 msgstr ""
 
-#: config/tc-mmix.c:698
+#: config/tc-mmix.c:697
 #, c-format
 msgid "  -globalize-symbols      Make all symbols global.\n"
 msgstr ""
 
-#: config/tc-mmix.c:700
+#: config/tc-mmix.c:699
 #, c-format
 msgid "  -gnu-syntax             Turn off mmixal syntax compatibility.\n"
 msgstr ""
 
-#: config/tc-mmix.c:702
+#: config/tc-mmix.c:701
 #, c-format
 msgid "  -relax                  Create linker relaxable code.\n"
 msgstr ""
 
-#: config/tc-mmix.c:704
+#: config/tc-mmix.c:703
 #, c-format
 msgid ""
 "  -no-predefined-syms     Do not provide mmixal built-in constants.\n"
 "                          Implies -fixed-special-register-names.\n"
 msgstr ""
 
-#: config/tc-mmix.c:707
+#: config/tc-mmix.c:706
 #, c-format
 msgid ""
 "  -no-expand              Do not expand GETA, branches, PUSHJ or JUMP\n"
 "                          into multiple instructions.\n"
 msgstr ""
 
-#: config/tc-mmix.c:710
+#: config/tc-mmix.c:709
 #, c-format
 msgid ""
 "  -no-merge-gregs         Do not merge GREG definitions with nearby values.\n"
 msgstr ""
 
-#: config/tc-mmix.c:712
+#: config/tc-mmix.c:711
 #, c-format
 msgid ""
 "  -linker-allocated-gregs If there's no suitable GREG definition for "
@@ -7485,7 +8159,7 @@ msgid ""
 "resolve.\n"
 msgstr ""
 
-#: config/tc-mmix.c:715
+#: config/tc-mmix.c:714
 #, c-format
 msgid ""
 "  -x                      Do not warn when an operand to GETA, a branch,\n"
@@ -7494,185 +8168,185 @@ msgid ""
 "                          -linker-allocated-gregs."
 msgstr ""
 
-#: config/tc-mmix.c:841
+#: config/tc-mmix.c:840
 #, c-format
 msgid "unknown opcode: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:963 config/tc-mmix.c:978
+#: config/tc-mmix.c:962 config/tc-mmix.c:977
 msgid "specified location wasn't TETRA-aligned"
 msgstr ""
 
-#: config/tc-mmix.c:965 config/tc-mmix.c:980 config/tc-mmix.c:4124
-#: config/tc-mmix.c:4140
+#: config/tc-mmix.c:964 config/tc-mmix.c:979 config/tc-mmix.c:4125
+#: config/tc-mmix.c:4141
 msgid "unaligned data at an absolute location is not supported"
 msgstr ""
 
-#: config/tc-mmix.c:1090
+#: config/tc-mmix.c:1089
 #, c-format
 msgid "invalid operand to opcode %s: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:1112 config/tc-mmix.c:1139 config/tc-mmix.c:1172
-#: config/tc-mmix.c:1180 config/tc-mmix.c:1197 config/tc-mmix.c:1225
-#: config/tc-mmix.c:1246 config/tc-mmix.c:1271 config/tc-mmix.c:1319
-#: config/tc-mmix.c:1417 config/tc-mmix.c:1442 config/tc-mmix.c:1474
-#: config/tc-mmix.c:1506 config/tc-mmix.c:1536 config/tc-mmix.c:1589
-#: config/tc-mmix.c:1606 config/tc-mmix.c:1633 config/tc-mmix.c:1661
-#: config/tc-mmix.c:1688 config/tc-mmix.c:1714 config/tc-mmix.c:1730
-#: config/tc-mmix.c:1756 config/tc-mmix.c:1772 config/tc-mmix.c:1788
-#: config/tc-mmix.c:1851 config/tc-mmix.c:1867
+#: config/tc-mmix.c:1111 config/tc-mmix.c:1138 config/tc-mmix.c:1171
+#: config/tc-mmix.c:1179 config/tc-mmix.c:1196 config/tc-mmix.c:1224
+#: config/tc-mmix.c:1245 config/tc-mmix.c:1270 config/tc-mmix.c:1318
+#: config/tc-mmix.c:1416 config/tc-mmix.c:1441 config/tc-mmix.c:1473
+#: config/tc-mmix.c:1505 config/tc-mmix.c:1535 config/tc-mmix.c:1588
+#: config/tc-mmix.c:1605 config/tc-mmix.c:1632 config/tc-mmix.c:1660
+#: config/tc-mmix.c:1687 config/tc-mmix.c:1713 config/tc-mmix.c:1729
+#: config/tc-mmix.c:1755 config/tc-mmix.c:1771 config/tc-mmix.c:1787
+#: config/tc-mmix.c:1850 config/tc-mmix.c:1866
 #, c-format
 msgid "invalid operands to opcode %s: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:1844
+#: config/tc-mmix.c:1843
 #, c-format
 msgid "unsupported operands to %s: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:1969
+#: config/tc-mmix.c:1968
 msgid "internal: mmix_prefix_name but empty prefix"
 msgstr ""
 
-#: config/tc-mmix.c:2013
+#: config/tc-mmix.c:2012
 #, c-format
 msgid "too many GREG registers allocated (max %d)"
 msgstr ""
 
-#: config/tc-mmix.c:2071
+#: config/tc-mmix.c:2070
 msgid "BSPEC already active.  Nesting is not supported."
 msgstr ""
 
-#: config/tc-mmix.c:2080
+#: config/tc-mmix.c:2079
 msgid "invalid BSPEC expression"
 msgstr ""
 
-#: config/tc-mmix.c:2096
+#: config/tc-mmix.c:2095
 #, c-format
 msgid "can't create section %s"
 msgstr ""
 
-#: config/tc-mmix.c:2101
+#: config/tc-mmix.c:2100
 #, c-format
 msgid "can't set section flags for section %s"
 msgstr ""
 
-#: config/tc-mmix.c:2122
+#: config/tc-mmix.c:2121
 msgid "ESPEC without preceding BSPEC"
 msgstr ""
 
-#: config/tc-mmix.c:2151
+#: config/tc-mmix.c:2150
 msgid "missing local expression"
 msgstr ""
 
-#: config/tc-mmix.c:2389
+#: config/tc-mmix.c:2388
 msgid "operand out of range, instruction expanded"
 msgstr ""
 
 #. The BFD_RELOC_MMIX_LOCAL-specific message is supposed to be
 #. user-friendly, though a little bit non-substantial.
-#: config/tc-mmix.c:2640
+#: config/tc-mmix.c:2639
 msgid "directive LOCAL must be placed in code or data"
 msgstr ""
 
-#: config/tc-mmix.c:2641
+#: config/tc-mmix.c:2640
 msgid "internal confusion: relocation in a section without contents"
 msgstr ""
 
-#: config/tc-mmix.c:2755
+#: config/tc-mmix.c:2754
 msgid "internal: BFD_RELOC_MMIX_BASE_PLUS_OFFSET not resolved to section"
 msgstr ""
 
-#: config/tc-mmix.c:2803
+#: config/tc-mmix.c:2802
 msgid "no suitable GREG definition for operands"
 msgstr ""
 
-#: config/tc-mmix.c:2862
+#: config/tc-mmix.c:2861
 msgid "operands were not reducible at assembly-time"
 msgstr ""
 
-#: config/tc-mmix.c:2889
+#: config/tc-mmix.c:2888
 #, c-format
 msgid "cannot generate relocation type for symbol %s, code %s"
 msgstr ""
 
-#: config/tc-mmix.c:2909
+#: config/tc-mmix.c:2908
 #, c-format
 msgid "internal: unhandled label %s"
 msgstr ""
 
-#: config/tc-mmix.c:2939
+#: config/tc-mmix.c:2938
 msgid "[0-9]H labels may not appear alone on a line"
 msgstr ""
 
-#: config/tc-mmix.c:2948
+#: config/tc-mmix.c:2947
 msgid "[0-9]H labels do not mix with dot-pseudos"
 msgstr ""
 
-#: config/tc-mmix.c:3036
+#: config/tc-mmix.c:3035
 msgid "invalid characters in input"
 msgstr ""
 
-#: config/tc-mmix.c:3140
+#: config/tc-mmix.c:3141
 msgid "empty label field for IS"
 msgstr ""
 
-#: config/tc-mmix.c:3466
+#: config/tc-mmix.c:3467
 #, c-format
 msgid "internal: unexpected relax type %d:%d"
 msgstr ""
 
-#: config/tc-mmix.c:3488
+#: config/tc-mmix.c:3489
 msgid "BSPEC without ESPEC."
 msgstr ""
 
-#: config/tc-mmix.c:3688
+#: config/tc-mmix.c:3689
 msgid "GREG expression too complicated"
 msgstr ""
 
-#: config/tc-mmix.c:3703
+#: config/tc-mmix.c:3704
 msgid "internal: GREG expression not resolved to section"
 msgstr ""
 
-#: config/tc-mmix.c:3752
+#: config/tc-mmix.c:3753
 msgid "register section has contents\n"
 msgstr ""
 
-#: config/tc-mmix.c:3879
+#: config/tc-mmix.c:3880
 msgid "section change from within a BSPEC/ESPEC pair is not supported"
 msgstr ""
 
-#: config/tc-mmix.c:3900
+#: config/tc-mmix.c:3901
 msgid "directive LOC from within a BSPEC/ESPEC pair is not supported"
 msgstr ""
 
-#: config/tc-mmix.c:3911
+#: config/tc-mmix.c:3912
 msgid "invalid LOC expression"
 msgstr ""
 
-#: config/tc-mmix.c:3936 config/tc-mmix.c:3962
+#: config/tc-mmix.c:3937 config/tc-mmix.c:3963
 msgid "LOC expression stepping backwards is not supported"
 msgstr ""
 
 #. We will only get here in rare cases involving #NO_APP,
 #. where the unterminated string is not recognized by the
 #. preformatting pass.
-#: config/tc-mmix.c:4046 config/tc-mmix.c:4206
+#: config/tc-mmix.c:4047 config/tc-mmix.c:4207 config/tc-z80.c:1691
 msgid "unterminated string"
 msgstr ""
 
-#: config/tc-mmix.c:4063
+#: config/tc-mmix.c:4064
 msgid "BYTE expression not a pure number"
 msgstr ""
 
 #. Note that mmixal does not allow negative numbers in
 #. BYTE sequences, so neither should we.
-#: config/tc-mmix.c:4072
+#: config/tc-mmix.c:4073
 msgid "BYTE expression not in the range 0..255"
 msgstr ""
 
-#: config/tc-mmix.c:4122 config/tc-mmix.c:4138
+#: config/tc-mmix.c:4123 config/tc-mmix.c:4139
 msgid "data item with alignment larger than location"
 msgstr ""
 
@@ -7682,82 +8356,82 @@ msgstr ""
 msgid "`&' serial number operator is not supported"
 msgstr ""
 
-#: config/tc-mn10200.c:305
+#: config/tc-mn10200.c:304
 #, c-format
 msgid ""
 "MN10200 options:\n"
 "none yet\n"
 msgstr ""
 
-#: config/tc-mn10200.c:931 config/tc-mn10300.c:1392 config/tc-ppc.c:2135
-#: config/tc-s390.c:1557 config/tc-v850.c:1621
+#: config/tc-mn10200.c:930 config/tc-mn10300.c:1391 config/tc-ppc.c:2189
+#: config/tc-s390.c:1558 config/tc-v850.c:1636
 #, c-format
 msgid "Unrecognized opcode: `%s'"
 msgstr ""
 
-#: config/tc-mn10200.c:1174 config/tc-mn10300.c:1965 config/tc-ppc.c:2614
-#: config/tc-s390.c:1472 config/tc-v850.c:2026
+#: config/tc-mn10200.c:1173 config/tc-mn10300.c:1964 config/tc-ppc.c:2668
+#: config/tc-s390.c:1473 config/tc-v850.c:2041
 #, c-format
 msgid "junk at end of line: `%s'"
 msgstr ""
 
-#: config/tc-mn10300.c:695
+#: config/tc-mn10300.c:694
 #, c-format
 msgid ""
-"MN10300 options:\n"
+"MN10300 assembler options:\n"
 "none yet\n"
 msgstr ""
 
-#: config/tc-mn10300.c:1361 config/tc-sh.c:778 read.c:3871
+#: config/tc-mn10300.c:1360 config/tc-sh.c:776 config/tc-z80.c:671 read.c:4194
 #, c-format
 msgid "unsupported BFD relocation size %u"
 msgstr ""
 
-#: config/tc-mn10300.c:1409
+#: config/tc-mn10300.c:1408
 msgid "Invalid opcode/operands"
 msgstr ""
 
-#: config/tc-mn10300.c:1936
+#: config/tc-mn10300.c:1935
 msgid "Invalid register specification."
 msgstr ""
 
-#: config/tc-mn10300.c:2518
+#: config/tc-mn10300.c:2522
 #, c-format
 msgid "Bad relocation fixup type (%d)"
 msgstr ""
 
-#: config/tc-msp430.c:552
+#: config/tc-msp430.c:550
 msgid ".profiler pseudo requires at least two operands."
 msgstr ""
 
-#: config/tc-msp430.c:611
+#: config/tc-msp430.c:609
 msgid "unknown profiling flag - ignored."
 msgstr ""
 
-#: config/tc-msp430.c:627
+#: config/tc-msp430.c:625
 msgid "ambigious flags combination - '.profiler' directive ignored."
 msgstr ""
 
-#: config/tc-msp430.c:637
+#: config/tc-msp430.c:635
 msgid "profiling in absolute section? Hm..."
 msgstr ""
 
-#: config/tc-msp430.c:726
+#: config/tc-msp430.c:724
 #, c-format
 msgid "Known MCU names:\n"
 msgstr ""
 
-#: config/tc-msp430.c:729
+#: config/tc-msp430.c:727
 #, c-format
 msgid "\t %s\n"
 msgstr ""
 
-#: config/tc-msp430.c:755
+#: config/tc-msp430.c:753
 #, c-format
 msgid "redefinition of mcu type %s' to %s'"
 msgstr ""
 
-#: config/tc-msp430.c:798
+#: config/tc-msp430.c:796
 #, c-format
 msgid ""
 "MSP430 options:\n"
@@ -7785,322 +8459,322 @@ msgid ""
 "                  msp430x447  msp430x448  msp430x449\n"
 msgstr ""
 
-#: config/tc-msp430.c:821
+#: config/tc-msp430.c:819
 #, c-format
 msgid ""
 "  -mQ - enable relaxation at assembly time. DANGEROUS!\n"
 "  -mP - enable polymorph instructions\n"
 msgstr ""
 
-#: config/tc-msp430.c:1011
+#: config/tc-msp430.c:1009
 #, c-format
 msgid "value %d out of range. Use #lo() or #hi()"
 msgstr ""
 
-#: config/tc-msp430.c:1099
+#: config/tc-msp430.c:1097
 #, c-format
 msgid "unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "
 msgstr ""
 
-#: config/tc-msp430.c:1150
+#: config/tc-msp430.c:1148
 #, c-format
 msgid "Registers cannot be used within immediate expression [%s]"
 msgstr ""
 
-#: config/tc-msp430.c:1152
+#: config/tc-msp430.c:1150
 #, c-format
 msgid "unknown operand %s"
 msgstr ""
 
-#: config/tc-msp430.c:1174 config/tc-msp430.c:1309
+#: config/tc-msp430.c:1172 config/tc-msp430.c:1307
 #, c-format
 msgid "value out of range: %d"
 msgstr ""
 
-#: config/tc-msp430.c:1185
+#: config/tc-msp430.c:1183
 #, c-format
 msgid "Registers cannot be used within absolute expression [%s]"
 msgstr ""
 
-#: config/tc-msp430.c:1187 config/tc-msp430.c:1330
+#: config/tc-msp430.c:1185 config/tc-msp430.c:1328
 #, c-format
 msgid "unknown expression in operand %s"
 msgstr ""
 
-#: config/tc-msp430.c:1201 config/tc-msp430.c:1208
+#: config/tc-msp430.c:1199 config/tc-msp430.c:1206
 #, c-format
 msgid "unknown addressing mode %s"
 msgstr ""
 
-#: config/tc-msp430.c:1216
+#: config/tc-msp430.c:1214
 #, c-format
 msgid "Bad register name r%s"
 msgstr ""
 
-#: config/tc-msp430.c:1228
+#: config/tc-msp430.c:1226
 #, c-format
 msgid "MSP430 does not have %d registers"
 msgstr ""
 
-#: config/tc-msp430.c:1248
+#: config/tc-msp430.c:1246
 msgid "')' required"
 msgstr ""
 
-#: config/tc-msp430.c:1261
+#: config/tc-msp430.c:1259
 #, c-format
 msgid "unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"
 msgstr ""
 
-#: config/tc-msp430.c:1270
+#: config/tc-msp430.c:1268
 #, c-format
 msgid "unknown operator (r%s substituded as a register name"
 msgstr ""
 
-#: config/tc-msp430.c:1282 config/tc-msp430.c:1293
+#: config/tc-msp430.c:1280 config/tc-msp430.c:1291
 #, c-format
 msgid "unknown operator %s"
 msgstr ""
 
-#: config/tc-msp430.c:1287
+#: config/tc-msp430.c:1285
 msgid "r2 should not be used in indexed addressing mode"
 msgstr ""
 
-#: config/tc-msp430.c:1328
+#: config/tc-msp430.c:1326
 #, c-format
 msgid "Registers cannot be used as a prefix of indexed expression [%s]"
 msgstr ""
 
 #. Unreachable.
-#: config/tc-msp430.c:1377
+#: config/tc-msp430.c:1375
 #, c-format
 msgid "unknown addressing mode for operand %s"
 msgstr ""
 
-#: config/tc-msp430.c:1402
+#: config/tc-msp430.c:1400
 #, c-format
 msgid "Internal bug. Try to use 0(r%d) instead of @r%d"
 msgstr ""
 
-#: config/tc-msp430.c:1412
+#: config/tc-msp430.c:1410
 msgid "this addressing mode is not applicable for destination operand"
 msgstr ""
 
-#: config/tc-msp430.c:1456
+#: config/tc-msp430.c:1454
 #, c-format
 msgid "instruction %s requires %d operand(s)"
 msgstr ""
 
-#: config/tc-msp430.c:1709
+#: config/tc-msp430.c:1707
 #, c-format
 msgid "Even number required. Rounded to %d"
 msgstr ""
 
-#: config/tc-msp430.c:1720
+#: config/tc-msp430.c:1718
 #, c-format
 msgid "Wrong displacement  %d"
 msgstr ""
 
-#: config/tc-msp430.c:1737
+#: config/tc-msp430.c:1735
 msgid "instruction requires label sans '$'"
 msgstr ""
 
-#: config/tc-msp430.c:1742
+#: config/tc-msp430.c:1740
 msgid "instruction requires label or value in range -511:512"
 msgstr ""
 
-#: config/tc-msp430.c:1749 config/tc-msp430.c:1793 config/tc-msp430.c:1832
+#: config/tc-msp430.c:1747 config/tc-msp430.c:1791 config/tc-msp430.c:1830
 msgid "instruction requires label"
 msgstr ""
 
-#: config/tc-msp430.c:1757 config/tc-msp430.c:1799
+#: config/tc-msp430.c:1755 config/tc-msp430.c:1797
 msgid "polymorphs are not enabled. Use -mP option to enable."
 msgstr ""
 
-#: config/tc-msp430.c:1836
+#: config/tc-msp430.c:1834
 msgid "Ilegal instruction or not implmented opcode."
 msgstr ""
 
-#: config/tc-msp430.c:2187
+#: config/tc-msp430.c:2184
 #, c-format
 msgid "internal inconsistency problem in %s: insn %04lx"
 msgstr ""
 
-#: config/tc-msp430.c:2217 config/tc-msp430.c:2240
+#: config/tc-msp430.c:2214 config/tc-msp430.c:2237
 #, c-format
 msgid "internal inconsistency problem in %s: ext. insn %04lx"
 msgstr ""
 
-#: config/tc-msp430.c:2252
+#: config/tc-msp430.c:2249
 #, c-format
 msgid "internal inconsistency problem in %s:  %lx"
 msgstr ""
 
-#: config/tc-ns32k.c:441
+#: config/tc-ns32k.c:439
 msgid "Invalid syntax in PC-relative addressing mode"
 msgstr ""
 
-#: config/tc-ns32k.c:465
+#: config/tc-ns32k.c:463
 msgid "Invalid syntax in External addressing mode"
 msgstr ""
 
-#: config/tc-ns32k.c:546
+#: config/tc-ns32k.c:544
 msgid "Invalid syntax in Memory Relative addressing mode"
 msgstr ""
 
-#: config/tc-ns32k.c:613
+#: config/tc-ns32k.c:611
 msgid "Invalid scaled-indexed mode, use (b,w,d,q)"
 msgstr ""
 
-#: config/tc-ns32k.c:618
+#: config/tc-ns32k.c:616
 msgid "Syntax in scaled-indexed mode, use [Rn:m] where n=[0..7] m={b,w,d,q}"
 msgstr ""
 
-#: config/tc-ns32k.c:623
+#: config/tc-ns32k.c:621
 msgid "Scaled-indexed addressing mode combined with scaled-index"
 msgstr ""
 
-#: config/tc-ns32k.c:634
+#: config/tc-ns32k.c:632
 msgid "Invalid or illegal addressing mode combined with scaled-index"
 msgstr ""
 
-#: config/tc-ns32k.c:757
+#: config/tc-ns32k.c:755
 msgid "Premature end of suffix -- Defaulting to d"
 msgstr ""
 
-#: config/tc-ns32k.c:770
+#: config/tc-ns32k.c:768
 msgid "Bad suffix after ':' use {b|w|d} Defaulting to d"
 msgstr ""
 
-#: config/tc-ns32k.c:815
+#: config/tc-ns32k.c:813
 msgid "Very short instr to option, ie you can't do it on a NULLstr"
 msgstr ""
 
-#: config/tc-ns32k.c:865
+#: config/tc-ns32k.c:863
 msgid "No such entry in list. (cpu/mmu register)"
 msgstr ""
 
-#: config/tc-ns32k.c:922
+#: config/tc-ns32k.c:920
 msgid "Internal consistency error.  check ns32k-opcode.h"
 msgstr ""
 
-#: config/tc-ns32k.c:946
+#: config/tc-ns32k.c:944
 msgid "Address of immediate operand"
 msgstr ""
 
-#: config/tc-ns32k.c:947
+#: config/tc-ns32k.c:945
 msgid "Invalid immediate write operand."
 msgstr ""
 
-#: config/tc-ns32k.c:1077
+#: config/tc-ns32k.c:1075
 msgid "Bad opcode-table-option, check in file ns32k-opcode.h"
 msgstr ""
 
-#: config/tc-ns32k.c:1110
+#: config/tc-ns32k.c:1108
 msgid "No such opcode"
 msgstr ""
 
-#: config/tc-ns32k.c:1185
+#: config/tc-ns32k.c:1183
 msgid "Bad suffix, defaulting to d"
 msgstr ""
 
-#: config/tc-ns32k.c:1212
+#: config/tc-ns32k.c:1210
 msgid "Too many operands passed to instruction"
 msgstr ""
 
 #. Check error in default.
-#: config/tc-ns32k.c:1224
+#: config/tc-ns32k.c:1222
 msgid "Wrong numbers of operands in default, check ns32k-opcodes.h"
 msgstr ""
 
-#: config/tc-ns32k.c:1227
+#: config/tc-ns32k.c:1225
 msgid "Wrong number of operands"
 msgstr ""
 
-#: config/tc-ns32k.c:1300
+#: config/tc-ns32k.c:1298
 #, c-format
 msgid "Can not do %d byte pc-relative relocation for storage type %d"
 msgstr ""
 
-#: config/tc-ns32k.c:1303
+#: config/tc-ns32k.c:1301
 #, c-format
 msgid "Can not do %d byte relocation for storage type %d"
 msgstr ""
 
-#: config/tc-ns32k.c:1395
+#: config/tc-ns32k.c:1393
 #, c-format
 msgid "value of %ld out of byte displacement range."
 msgstr ""
 
-#: config/tc-ns32k.c:1405
+#: config/tc-ns32k.c:1403
 #, c-format
 msgid "value of %ld out of word displacement range."
 msgstr ""
 
-#: config/tc-ns32k.c:1420
+#: config/tc-ns32k.c:1418
 #, c-format
 msgid "value of %ld out of double word displacement range."
 msgstr ""
 
-#: config/tc-ns32k.c:1441
+#: config/tc-ns32k.c:1439
 #, c-format
 msgid "Internal logic error.  line %d, file \"%s\""
 msgstr ""
 
-#: config/tc-ns32k.c:1489
+#: config/tc-ns32k.c:1487
 #, c-format
 msgid "Internal logic error. line %d, file \"%s\""
 msgstr ""
 
-#: config/tc-ns32k.c:1590
+#: config/tc-ns32k.c:1588
 msgid "Bit field out of range"
 msgstr ""
 
-#: config/tc-ns32k.c:1690
+#: config/tc-ns32k.c:1688
 msgid "iif convert internal pcrel/binary"
 msgstr ""
 
-#: config/tc-ns32k.c:1707
+#: config/tc-ns32k.c:1705
 msgid "Bignum too big for long"
 msgstr ""
 
-#: config/tc-ns32k.c:1784
+#: config/tc-ns32k.c:1782
 msgid "iif convert internal pcrel/pointer"
 msgstr ""
 
-#: config/tc-ns32k.c:1789
+#: config/tc-ns32k.c:1787
 msgid "Internal logic error in iif.iifP[n].type"
 msgstr ""
 
 #. We cant relax this case.
-#: config/tc-ns32k.c:1825
+#: config/tc-ns32k.c:1823
 msgid "Can't relax difference"
 msgstr ""
 
-#: config/tc-ns32k.c:1866
-msgid "Displacement to large for :d"
+#: config/tc-ns32k.c:1864
+msgid "Displacement too large for :d"
 msgstr ""
 
-#: config/tc-ns32k.c:1879
+#: config/tc-ns32k.c:1877
 msgid "Internal logic error in iif.iifP[].type"
 msgstr ""
 
 #. Fatal.
-#: config/tc-ns32k.c:1911
+#: config/tc-ns32k.c:1909
 #, c-format
 msgid "Can't hash %s: %s"
 msgstr ""
 
-#: config/tc-ns32k.c:2181
+#: config/tc-ns32k.c:2179
 #, c-format
 msgid "invalid architecture option -m%s, ignored"
 msgstr ""
 
-#: config/tc-ns32k.c:2194
+#: config/tc-ns32k.c:2192
 #, c-format
 msgid "invalid default displacement size \"%s\". Defaulting to %d."
 msgstr ""
 
-#: config/tc-ns32k.c:2210
+#: config/tc-ns32k.c:2208
 #, c-format
 msgid ""
 "NS32K options:\n"
@@ -8108,45 +8782,45 @@ msgid ""
 "--disp-size-default=<1|2|4>\n"
 msgstr ""
 
-#: config/tc-ns32k.c:2285
+#: config/tc-ns32k.c:2283
 #, c-format
 msgid "Cannot find relocation type for symbol %s, code %d"
 msgstr ""
 
-#: config/tc-or32.c:360
+#: config/tc-or32.c:361
 #, c-format
 msgid "unknown opcode1: `%s'"
 msgstr ""
 
-#: config/tc-or32.c:366
+#: config/tc-or32.c:367
 #, c-format
 msgid "unknown opcode2 `%s'."
 msgstr ""
 
-#: config/tc-or32.c:403
+#: config/tc-or32.c:404
 #, c-format
 msgid "instruction not allowed: %s"
 msgstr ""
 
-#: config/tc-or32.c:406
+#: config/tc-or32.c:407
 #, c-format
 msgid "too many operands: %s"
 msgstr ""
 
-#: config/tc-or32.c:490
+#: config/tc-or32.c:491
 msgid "call/jmp target out of range (1)"
 msgstr ""
 
-#: config/tc-or32.c:674
+#: config/tc-or32.c:672
 msgid "call/jmp target out of range (2)"
 msgstr ""
 
-#: config/tc-or32.c:693
+#: config/tc-or32.c:691
 #, c-format
 msgid "bad relocation type: 0x%02x"
 msgstr ""
 
-#: config/tc-or32.c:885
+#: config/tc-or32.c:883
 msgid "invalid register in & expression"
 msgstr ""
 
@@ -8154,7 +8828,7 @@ msgstr ""
 msgid "Low order bits truncated in immediate float operand"
 msgstr ""
 
-#: config/tc-pdp11.c:679
+#: config/tc-pdp11.c:679 config/tc-z80.c:1890 config/tc-z80.c:1903
 #, c-format
 msgid "Unknown instruction '%s'"
 msgstr ""
@@ -8180,8 +8854,8 @@ msgid ""
 "-big\t\t\tgenerate big endian code\n"
 msgstr ""
 
-#: config/tc-pj.c:431 config/tc-sh.c:3955 config/tc-sh.c:3962
-#: config/tc-sh.c:3969 config/tc-sh.c:3976
+#: config/tc-pj.c:431 config/tc-sh.c:4086 config/tc-sh.c:4093
+#: config/tc-sh.c:4100 config/tc-sh.c:4107
 msgid "pcrel too far"
 msgstr ""
 
@@ -8193,17 +8867,17 @@ msgstr ""
 msgid "estimate size\n"
 msgstr ""
 
-#: config/tc-ppc.c:991
+#: config/tc-ppc.c:979
 #, c-format
 msgid "%s unsupported"
 msgstr ""
 
-#: config/tc-ppc.c:1057 config/tc-s390.c:417 config/tc-s390.c:424
+#: config/tc-ppc.c:1045 config/tc-s390.c:418 config/tc-s390.c:425
 #, c-format
 msgid "invalid switch -m%s"
 msgstr ""
 
-#: config/tc-ppc.c:1094
+#: config/tc-ppc.c:1081
 #, c-format
 msgid ""
 "PowerPC options:\n"
@@ -8221,7 +8895,7 @@ msgid ""
 "\t\t\tgenerate code For PowerPC 7400/7410/7450/7455\n"
 msgstr ""
 
-#: config/tc-ppc.c:1108
+#: config/tc-ppc.c:1095
 #, c-format
 msgid ""
 "-mppc64, -m620\t\tgenerate code for PowerPC 620/625/630\n"
@@ -8230,11 +8904,13 @@ msgid ""
 "-mbooke, mbooke32\tgenerate code for 32-bit PowerPC BookE\n"
 "-mpower4\t\tgenerate code for Power4 architecture\n"
 "-mpower5\t\tgenerate code for Power5 architecture\n"
+"-mpower6\t\tgenerate code for Power6 architecture\n"
+"-mcell\t\t\tgenerate code for Cell Broadband Engine architecture\n"
 "-mcom\t\t\tgenerate code Power/PowerPC common instructions\n"
 "-many\t\t\tgenerate code for any architecture (PWR/PWRX/PPC)\n"
 msgstr ""
 
-#: config/tc-ppc.c:1117
+#: config/tc-ppc.c:1106
 #, c-format
 msgid ""
 "-maltivec\t\tgenerate code for AltiVec\n"
@@ -8245,7 +8921,7 @@ msgid ""
 "-mno-regnames\t\tDo not allow symbolic names for registers\n"
 msgstr ""
 
-#: config/tc-ppc.c:1125
+#: config/tc-ppc.c:1114
 #, c-format
 msgid ""
 "-mrelocatable\t\tsupport for GCC's -mrelocatble option\n"
@@ -8261,251 +8937,276 @@ msgid ""
 "-Qy, -Qn\t\tignored\n"
 msgstr ""
 
-#: config/tc-ppc.c:1162
+#: config/tc-ppc.c:1151
 #, c-format
 msgid "Unknown default cpu = %s, os = %s"
 msgstr ""
 
-#: config/tc-ppc.c:1188
+#: config/tc-ppc.c:1177
 msgid "Neither Power nor PowerPC opcodes were selected."
 msgstr ""
 
-#: config/tc-ppc.c:1285 config/tc-s390.c:519
+#: config/tc-ppc.c:1256
 #, c-format
-msgid "Internal assembler error for instruction %s"
+msgid "powerpc_operands[%d].bitm invalid"
+msgstr ""
+
+#: config/tc-ppc.c:1263
+#, c-format
+msgid "powerpc_operands[%d] duplicates powerpc_operands[%d]"
+msgstr ""
+
+#: config/tc-ppc.c:1281
+#, c-format
+msgid "mask trims opcode bits for %s"
+msgstr ""
+
+#: config/tc-ppc.c:1290
+#, c-format
+msgid "operand index error for %s"
+msgstr ""
+
+#: config/tc-ppc.c:1302
+#, c-format
+msgid "operand %d overlap in %s"
+msgstr ""
+
+#: config/tc-ppc.c:1344
+#, c-format
+msgid "duplicate instruction %s"
 msgstr ""
 
-#: config/tc-ppc.c:1309
+#: config/tc-ppc.c:1368
 #, c-format
-msgid "Internal assembler error for macro %s"
+msgid "duplicate macro %s"
 msgstr ""
 
-#: config/tc-ppc.c:1640
+#: config/tc-ppc.c:1702
 msgid "identifier+constant@got means identifier@got+constant"
 msgstr ""
 
-#: config/tc-ppc.c:1707
+#: config/tc-ppc.c:1768
 #, c-format
 msgid "%s relocations do not fit in %d bytes\n"
 msgstr ""
 
-#: config/tc-ppc.c:1814
+#: config/tc-ppc.c:1873
 #, c-format
 msgid "Length of .lcomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/tc-ppc.c:1896
+#: config/tc-ppc.c:1953
 msgid "Relocation cannot be done when using -mrelocatable"
 msgstr ""
 
-#: config/tc-ppc.c:1945
+#: config/tc-ppc.c:2002
 msgid "TOC section size exceeds 64k"
 msgstr ""
 
-#: config/tc-ppc.c:2027
+#: config/tc-ppc.c:2083
 #, c-format
 msgid "syntax error: invalid toc specifier `%s'"
 msgstr ""
 
-#: config/tc-ppc.c:2041
+#: config/tc-ppc.c:2097
 #, c-format
 msgid "syntax error: expected `]', found  `%c'"
 msgstr ""
 
-#: config/tc-ppc.c:2320
+#: config/tc-ppc.c:2374
 msgid "[tocv] symbol is not a toc symbol"
 msgstr ""
 
-#: config/tc-ppc.c:2331
+#: config/tc-ppc.c:2385
 msgid "Unimplemented toc32 expression modifier"
 msgstr ""
 
-#: config/tc-ppc.c:2336
+#: config/tc-ppc.c:2390
 msgid "Unimplemented toc64 expression modifier"
 msgstr ""
 
-#: config/tc-ppc.c:2340
+#: config/tc-ppc.c:2394
 #, c-format
 msgid "Unexpected return value [%d] from parse_toc_entry!\n"
 msgstr ""
 
-#: config/tc-ppc.c:2558
+#: config/tc-ppc.c:2612
 msgid "unsupported relocation for DS offset field"
 msgstr ""
 
-#: config/tc-ppc.c:2602
+#: config/tc-ppc.c:2656
 #, c-format
 msgid "syntax error; found `%c' but expected `%c'"
 msgstr ""
 
-#: config/tc-ppc.c:2645 config/tc-ppc.h:111
+#: config/tc-ppc.c:2699 config/tc-ppc.h:92
 msgid "instruction address is not a multiple of 4"
 msgstr ""
 
-#: config/tc-ppc.c:2756
+#: config/tc-ppc.c:2808
 msgid "wrong number of operands"
 msgstr ""
 
-#: config/tc-ppc.c:2812
+#: config/tc-ppc.c:2862
 msgid "Bad .section directive: want a,e,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-ppc.c:2927
+#: config/tc-ppc.c:2968
 msgid "missing size"
 msgstr ""
 
-#: config/tc-ppc.c:2936
+#: config/tc-ppc.c:2977
 msgid "negative size"
 msgstr ""
 
-#: config/tc-ppc.c:2973
+#: config/tc-ppc.c:3014
 msgid "missing real symbol name"
 msgstr ""
 
-#: config/tc-ppc.c:2994
+#: config/tc-ppc.c:3035
 msgid "attempt to redefine symbol"
 msgstr ""
 
-#: config/tc-ppc.c:3241
+#: config/tc-ppc.c:3277
 msgid "The XCOFF file format does not support arbitrary sections"
 msgstr ""
 
-#: config/tc-ppc.c:3318
+#: config/tc-ppc.c:3351
 msgid "missing rename string"
 msgstr ""
 
-#: config/tc-ppc.c:3349 config/tc-ppc.c:3904 read.c:3064
+#: config/tc-ppc.c:3381 config/tc-ppc.c:3923 read.c:3260
 msgid "missing value"
 msgstr ""
 
-#: config/tc-ppc.c:3367
+#: config/tc-ppc.c:3399
 msgid "illegal .stabx expression; zero assumed"
 msgstr ""
 
-#: config/tc-ppc.c:3399
+#: config/tc-ppc.c:3431
 msgid "missing class"
 msgstr ""
 
-#: config/tc-ppc.c:3408
+#: config/tc-ppc.c:3440
 msgid "missing type"
 msgstr ""
 
-#: config/tc-ppc.c:3489
+#: config/tc-ppc.c:3520
 msgid "missing symbol name"
 msgstr ""
 
-#: config/tc-ppc.c:3683
+#: config/tc-ppc.c:3710
 msgid "nested .bs blocks"
 msgstr ""
 
-#: config/tc-ppc.c:3716
+#: config/tc-ppc.c:3742
 msgid ".es without preceding .bs"
 msgstr ""
 
-#: config/tc-ppc.c:3896
+#: config/tc-ppc.c:3915
 msgid "non-constant byte count"
 msgstr ""
 
-#: config/tc-ppc.c:3944
+#: config/tc-ppc.c:3962
 msgid ".tc not in .toc section"
 msgstr ""
 
-#: config/tc-ppc.c:3963
+#: config/tc-ppc.c:3981
 msgid ".tc with no label"
 msgstr ""
 
-#: config/tc-ppc.c:4055
+#: config/tc-ppc.c:4072
 msgid ".machine stack overflow"
 msgstr ""
 
-#: config/tc-ppc.c:4062
+#: config/tc-ppc.c:4079
 msgid ".machine stack underflow"
 msgstr ""
 
-#: config/tc-ppc.c:4069
+#: config/tc-ppc.c:4086
 #, c-format
 msgid "invalid machine `%s'"
 msgstr ""
 
-#: config/tc-ppc.c:4123
+#: config/tc-ppc.c:4137
 msgid "No previous section to return to. Directive ignored."
 msgstr ""
 
 #. Section Contents
 #. unknown
-#: config/tc-ppc.c:4540
+#: config/tc-ppc.c:4547
 msgid "Unsupported section attribute -- 'a'"
 msgstr ""
 
-#: config/tc-ppc.c:4729
+#: config/tc-ppc.c:4731
 msgid "bad symbol suffix"
 msgstr ""
 
-#: config/tc-ppc.c:4822
+#: config/tc-ppc.c:4823
 msgid "Unrecognized symbol suffix"
 msgstr ""
 
-#: config/tc-ppc.c:4912
+#: config/tc-ppc.c:4911
 msgid "two .function pseudo-ops with no intervening .ef"
 msgstr ""
 
-#: config/tc-ppc.c:4925
+#: config/tc-ppc.c:4924
 msgid ".ef with no preceding .function"
 msgstr ""
 
-#: config/tc-ppc.c:5053
+#: config/tc-ppc.c:5052
 #, c-format
 msgid "warning: symbol %s has no csect"
 msgstr ""
 
-#: config/tc-ppc.c:5357
+#: config/tc-ppc.c:5345
 msgid "symbol in .toc does not match any .tc"
 msgstr ""
 
-#: config/tc-ppc.c:5686 config/tc-s390.c:2092 config/tc-v850.c:2314
+#: config/tc-ppc.c:5709 config/tc-s390.c:2093 config/tc-v850.c:2343
 #: config/tc-xstormy16.c:538
 msgid "unresolved expression that must be resolved"
 msgstr ""
 
-#: config/tc-ppc.c:5689
+#: config/tc-ppc.c:5712
 #, c-format
 msgid "unsupported relocation against %s"
 msgstr ""
 
-#: config/tc-ppc.c:5762
+#: config/tc-ppc.c:5785
 #, c-format
 msgid "cannot emit PC relative %s relocation against %s"
 msgstr ""
 
-#: config/tc-ppc.c:5767
+#: config/tc-ppc.c:5790
 #, c-format
 msgid "cannot emit PC relative %s relocation"
 msgstr ""
 
-#: config/tc-ppc.c:5949
+#: config/tc-ppc.c:5972
 #, c-format
 msgid "Unable to handle reference to symbol %s"
 msgstr ""
 
-#: config/tc-ppc.c:5952
+#: config/tc-ppc.c:5975
 msgid "Unable to resolve expression"
 msgstr ""
 
-#: config/tc-ppc.c:5979
+#: config/tc-ppc.c:6002
 msgid "must branch to an address a multiple of 4"
 msgstr ""
 
-#: config/tc-ppc.c:5983
+#: config/tc-ppc.c:6006
 #, c-format
 msgid "@local or @plt branch destination is too far away, %ld bytes"
 msgstr ""
 
-#: config/tc-ppc.c:6014
+#: config/tc-ppc.c:6037
 #, c-format
 msgid "Gas failure, reloc value %d\n"
 msgstr ""
 
-#: config/tc-s390.c:460
+#: config/tc-s390.c:461
 #, c-format
 msgid ""
 "        S390 options:\n"
@@ -8516,80 +9217,375 @@ msgid ""
 "        -m64              Set file format to 64 bit format\n"
 msgstr ""
 
-#: config/tc-s390.c:467
+#: config/tc-s390.c:468
 #, c-format
 msgid ""
 "        -V                print assembler version number\n"
 "        -Qy, -Qn          ignored\n"
 msgstr ""
 
-#: config/tc-s390.c:503
+#: config/tc-s390.c:504
 #, c-format
 msgid "Internal assembler error for instruction format %s"
 msgstr ""
 
-#: config/tc-s390.c:766
+#: config/tc-s390.c:520
+#, c-format
+msgid "Internal assembler error for instruction %s"
+msgstr ""
+
+#: config/tc-s390.c:767
 #, c-format
 msgid "identifier+constant@%s means identifier@%s+constant"
 msgstr ""
 
-#: config/tc-s390.c:849
+#: config/tc-s390.c:850
 msgid "Can't handle O_big in s390_exp_compare"
 msgstr ""
 
-#: config/tc-s390.c:933
+#: config/tc-s390.c:934
 msgid "Invalid suffix for literal pool entry"
 msgstr ""
 
-#: config/tc-s390.c:990
+#: config/tc-s390.c:991
 msgid "Big number is too big"
 msgstr ""
 
-#: config/tc-s390.c:1138
+#: config/tc-s390.c:1139
 msgid "relocation not applicable"
 msgstr ""
 
-#: config/tc-s390.c:1326
+#: config/tc-s390.c:1327
 msgid "invalid operand suffix"
 msgstr ""
 
-#: config/tc-s390.c:1349
+#: config/tc-s390.c:1350
 msgid "syntax error; missing '(' after displacement"
 msgstr ""
 
-#: config/tc-s390.c:1365 config/tc-s390.c:1409 config/tc-s390.c:1439
+#: config/tc-s390.c:1366 config/tc-s390.c:1410 config/tc-s390.c:1440
 msgid "syntax error; expected ,"
 msgstr ""
 
-#: config/tc-s390.c:1397
+#: config/tc-s390.c:1398
 msgid "syntax error; missing ')' after base register"
 msgstr ""
 
-#: config/tc-s390.c:1426
+#: config/tc-s390.c:1427
 msgid "syntax error; ')' not allowed here"
 msgstr ""
 
-#: config/tc-s390.c:1619 config/tc-s390.c:1642 config/tc-s390.c:1655
+#: config/tc-s390.c:1620 config/tc-s390.c:1643 config/tc-s390.c:1656
 msgid "Invalid .insn format\n"
 msgstr ""
 
-#: config/tc-s390.c:1627
+#: config/tc-s390.c:1628
 #, c-format
 msgid "Unrecognized opcode format: `%s'"
 msgstr ""
 
-#: config/tc-s390.c:1658
+#: config/tc-s390.c:1659
 msgid "second operand of .insn not a constant\n"
 msgstr ""
 
-#: config/tc-s390.c:1661
+#: config/tc-s390.c:1662
 msgid "missing comma after insn constant\n"
 msgstr ""
 
-#: config/tc-s390.c:2095
+#: config/tc-s390.c:2096
 msgid "unsupported relocation type"
 msgstr ""
 
+#: config/tc-score.c:49
+msgid "instruction is not conditional"
+msgstr ""
+
+#: config/tc-score.c:50
+msgid "acc0 expected"
+msgstr ""
+
+#: config/tc-score.c:51
+msgid "div / mul are reserved instructions"
+msgstr ""
+
+#: config/tc-score.c:52
+msgid "This architecture doesn't support mmu"
+msgstr ""
+
+#: config/tc-score.c:53
+msgid "This architecture doesn't support atomic instruction"
+msgstr ""
+
+#: config/tc-score.c:54
+msgid "the label length is longer than 1024"
+msgstr ""
+
+#: config/tc-score.c:238
+msgid "S+core register expected"
+msgstr ""
+
+#: config/tc-score.c:239
+msgid "S+core special-register expected"
+msgstr ""
+
+#: config/tc-score.c:240
+msgid "S+core co-processor register expected"
+msgstr ""
+
+#: config/tc-score.c:858 config/tc-score.c:1758
+msgid "Using temp register(r1)"
+msgstr ""
+
+#: config/tc-score.c:877
+#, c-format
+msgid "register expected, not '%.100s'"
+msgstr ""
+
+#: config/tc-score.c:1263 config/tc-score.c:1270 config/tc-score.c:2645
+#: config/tc-score.c:2650 config/tc-score.c:2928 config/tc-score.c:2933
+#, c-format
+msgid "invalid constant: %d bit expression not in range %d..%d"
+msgstr ""
+
+#: config/tc-score.c:1310
+msgid "invalid constant: bit expression not defined"
+msgstr ""
+
+#: config/tc-score.c:1772
+#, c-format
+msgid "low register(r0-r15)expected, not '%.100s'"
+msgstr ""
+
+#: config/tc-score.c:1867
+#, c-format
+msgid "high register(r16-r31)expected, not '%.100s'"
+msgstr ""
+
+#: config/tc-score.c:2099
+#, c-format
+msgid "Fix data dependency: %s %s -- %s %s  (insert %d nop!/%d)"
+msgstr ""
+
+#: config/tc-score.c:2118
+#, c-format
+msgid "Fix data dependency: %s %s -- %s %s  (insert 1 pflush/%d)"
+msgstr ""
+
+#: config/tc-score.c:2134 config/tc-score.c:2141
+#, c-format
+msgid "data dependency: %s %s -- %s %s  (%d/%d bubble)"
+msgstr ""
+
+#: config/tc-score.c:2431 config/tc-score.c:5662
+#, c-format
+msgid "%s -- `%s'"
+msgstr ""
+
+#: config/tc-score.c:2588
+msgid "address offset must be half word alignment"
+msgstr ""
+
+#: config/tc-score.c:2596
+msgid "address offset must be word alignment"
+msgstr ""
+
+#: config/tc-score.c:2738 config/tc-score.c:2885
+msgid "register same as write-back base"
+msgstr ""
+
+#: config/tc-score.c:2855
+msgid "pre-indexed expression expected"
+msgstr ""
+
+#: config/tc-score.c:2865 config/tc-score.c:3223 config/tc-score.c:3239
+#: config/tc-score.c:3310 config/tc-score.c:3353 config/tc-score.c:3475
+#: config/tc-score.c:3549 config/tc-score.c:3603 config/tc-score.c:3649
+msgid "missing ]"
+msgstr ""
+
+#: config/tc-score.c:3466
+msgid "base register nums are over 3 bit"
+msgstr ""
+
+#: config/tc-score.c:3543 config/tc-score.c:3594
+msgid "missing +"
+msgstr ""
+
+#: config/tc-score.c:3587
+#, c-format
+msgid "%s register same as write-back base"
+msgstr ""
+
+#: config/tc-score.c:3589
+msgid "destination"
+msgstr ""
+
+#: config/tc-score.c:3589
+msgid "source"
+msgstr ""
+
+#: config/tc-score.c:3993
+msgid "li rd label isn't correct instruction form"
+msgstr ""
+
+#: config/tc-score.c:4506 config/tc-score.c:4535 config/tc-score.c:4561
+msgid "lacking label  "
+msgstr ""
+
+#: config/tc-score.c:4513
+msgid "invalid constant: 25 bit expression not in range -2^24..2^24"
+msgstr ""
+
+#: config/tc-score.c:4541
+msgid "invalid constant: 12 bit expression not in range -2^11..2^11"
+msgstr ""
+
+#: config/tc-score.c:4567
+msgid "invalid constant: 20 bit expression not in range -2^19..2^19"
+msgstr ""
+
+#: config/tc-score.c:4600
+msgid "lacking label"
+msgstr ""
+
+#: config/tc-score.c:4605
+msgid "invalid constant: 9 bit expression not in range -2^8..2^8"
+msgstr ""
+
+#: config/tc-score.c:5344
+#, c-format
+msgid " branch relocation truncate (0x%x) [-2^8 ~ 2^8]"
+msgstr ""
+
+#: config/tc-score.c:5361 config/tc-score.c:5391
+#, c-format
+msgid " branch relocation truncate (0x%x) [-2^19 ~ 2^19]"
+msgstr ""
+
+#: config/tc-score.c:5415
+#, c-format
+msgid " branch relocation truncate (0x%x)  [-2^8 ~ 2^8]"
+msgstr ""
+
+#: config/tc-score.c:5581
+#, c-format
+msgid "cannot represent %s relocation in this object file format1"
+msgstr ""
+
+#: config/tc-score.c:5640
+msgid "pce instruction error (16 bit || 16 bit)'"
+msgstr ""
+
+#: config/tc-score.c:5770
+#, c-format
+msgid "Sunplus-v2-0-0-20060510\n"
+msgstr ""
+
+#: config/tc-score.c:5786
+#, c-format
+msgid " Score-specific assembler options:\n"
+msgstr ""
+
+#: config/tc-score.c:5788
+#, c-format
+msgid "        -EB\t\tassemble code for a big-endian cpu\n"
+msgstr ""
+
+#: config/tc-score.c:5793
+#, c-format
+msgid "        -EL\t\tassemble code for a little-endian cpu\n"
+msgstr ""
+
+#: config/tc-score.c:5797
+#, c-format
+msgid "        -FIXDD\t\tassemble code for fix data dependency\n"
+msgstr ""
+
+#: config/tc-score.c:5799
+#, c-format
+msgid ""
+"        -NWARN\t\tassemble code for no warning message for fix data "
+"dependency\n"
+msgstr ""
+
+#: config/tc-score.c:5801
+#, c-format
+msgid "        -SCORE5\t\tassemble code for target is SCORE5\n"
+msgstr ""
+
+#: config/tc-score.c:5803
+#, c-format
+msgid "        -SCORE5U\tassemble code for target is SCORE5U\n"
+msgstr ""
+
+#: config/tc-score.c:5805
+#, c-format
+msgid ""
+"        -SCORE7\t\tassemble code for target is SCORE7, this is default "
+"setting\n"
+msgstr ""
+
+#: config/tc-score.c:5807
+#, c-format
+msgid ""
+"        -USE_R1\t\tassemble code for no warning message when using temp "
+"register r1\n"
+msgstr ""
+
+#: config/tc-score.c:5809
+#, c-format
+msgid "        -KPIC\t\tassemble code for PIC\n"
+msgstr ""
+
+#: config/tc-score.c:5811
+#, c-format
+msgid "        -O0\t\tassembler will not perform any optimizations\n"
+msgstr ""
+
+#: config/tc-score.c:5813
+#, c-format
+msgid ""
+"        -G gpnum\tassemble code for setting gpsize and default is 8 byte\n"
+msgstr ""
+
+#: config/tc-score.c:5815
+#, c-format
+msgid "        -V \t\tSunplus release version \n"
+msgstr ""
+
+#: config/tc-score.c:6415 read.c:1459
+msgid "missing size expression"
+msgstr ""
+
+#: config/tc-score.c:6421
+#, c-format
+msgid "BSS length (%d) < 0 ignored"
+msgstr ""
+
+#: config/tc-score.c:6436 read.c:2277
+#, c-format
+msgid "error setting flags for \".sbss\": %s"
+msgstr ""
+
+#: config/tc-score.c:6450 config/tc-sparc.c:3797
+msgid "missing alignment"
+msgstr ""
+
+#: config/tc-score.c:6487
+#, c-format
+msgid "alignment too large; %d assumed"
+msgstr ""
+
+#: config/tc-score.c:6492 read.c:2338
+msgid "alignment negative; 0 assumed"
+msgstr ""
+
+#: config/tc-score.c:6559 config/tc-z80.c:289 ecoff.c:3355 read.c:1478
+#: read.c:1591 read.c:2455 read.c:3002 read.c:3387 symbols.c:326 symbols.c:432
+#, c-format
+msgid "symbol `%s' is already defined"
+msgstr ""
+
 #: config/tc-sh64.c:568
 msgid "This operand must be constant at assembly time"
 msgstr ""
@@ -8672,7 +9668,7 @@ msgstr ""
 
 #: config/tc-sh64.c:1536
 #, c-format
-msgid "invalid operand, not an 16-bit unsigned value: %d"
+msgid "invalid operand, not a 16-bit unsigned value: %d"
 msgstr ""
 
 #: config/tc-sh64.c:1542
@@ -8759,212 +9755,212 @@ msgstr ""
 msgid "-expand-pt32 invalid together with -no-expand"
 msgstr ""
 
-#: config/tc-sh64.c:3201
+#: config/tc-sh64.c:3199
 msgid ""
 "SHmedia code not allowed in same section as constants and SHcompact code"
 msgstr ""
 
-#: config/tc-sh64.c:3219
+#: config/tc-sh64.c:3217
 msgid "No segment info for current section"
 msgstr ""
 
-#: config/tc-sh64.c:3258
+#: config/tc-sh64.c:3256
 msgid "duplicate datalabel operator ignored"
 msgstr ""
 
-#: config/tc-sh64.c:3328
+#: config/tc-sh64.c:3326
 msgid "Invalid DataLabel expression"
 msgstr ""
 
-#: config/tc-sh.c:65
+#: config/tc-sh.c:63
 msgid "directive .big encountered when option -big required"
 msgstr ""
 
-#: config/tc-sh.c:75
+#: config/tc-sh.c:73
 msgid "directive .little encountered when option -little required"
 msgstr ""
 
-#: config/tc-sh.c:1277
+#: config/tc-sh.c:1364
 msgid "misplaced PIC operand"
 msgstr ""
 
-#: config/tc-sh.c:1315
+#: config/tc-sh.c:1402
 msgid "illegal double indirection"
 msgstr ""
 
-#: config/tc-sh.c:1324
+#: config/tc-sh.c:1411
 msgid "illegal register after @-"
 msgstr ""
 
-#: config/tc-sh.c:1340
+#: config/tc-sh.c:1427
 msgid "must be @(r0,...)"
 msgstr ""
 
-#: config/tc-sh.c:1364
+#: config/tc-sh.c:1451
 msgid "syntax error in @(r0,...)"
 msgstr ""
 
-#: config/tc-sh.c:1369
+#: config/tc-sh.c:1456
 msgid "syntax error in @(r0...)"
 msgstr ""
 
-#: config/tc-sh.c:1414
+#: config/tc-sh.c:1501
 msgid "Deprecated syntax."
 msgstr ""
 
-#: config/tc-sh.c:1426 config/tc-sh.c:1431
+#: config/tc-sh.c:1513 config/tc-sh.c:1518
 msgid "syntax error in @(disp,[Rn, gbr, pc])"
 msgstr ""
 
-#: config/tc-sh.c:1436
+#: config/tc-sh.c:1523
 msgid "expecting )"
 msgstr ""
 
-#: config/tc-sh.c:1444
+#: config/tc-sh.c:1531
 msgid "illegal register after @"
 msgstr ""
 
-#: config/tc-sh.c:2115
+#: config/tc-sh.c:2202
 #, c-format
 msgid "unhandled %d\n"
 msgstr ""
 
-#: config/tc-sh.c:2281
+#: config/tc-sh.c:2368
 #, c-format
 msgid "Invalid register: 'r%d'"
 msgstr ""
 
-#: config/tc-sh.c:2385
+#: config/tc-sh.c:2472
 #, c-format
 msgid "failed for %d\n"
 msgstr ""
 
-#: config/tc-sh.c:2498 config/tc-sh.c:2894
+#: config/tc-sh.c:2585 config/tc-sh.c:2984
 msgid "invalid operands for opcode"
 msgstr ""
 
-#: config/tc-sh.c:2503
+#: config/tc-sh.c:2590
 msgid "insn can't be combined with parallel processing insn"
 msgstr ""
 
-#: config/tc-sh.c:2510 config/tc-sh.c:2521 config/tc-sh.c:2553
+#: config/tc-sh.c:2597 config/tc-sh.c:2608 config/tc-sh.c:2640
 msgid "multiple movx specifications"
 msgstr ""
 
-#: config/tc-sh.c:2515 config/tc-sh.c:2537 config/tc-sh.c:2576
+#: config/tc-sh.c:2602 config/tc-sh.c:2624 config/tc-sh.c:2663
 msgid "multiple movy specifications"
 msgstr ""
 
-#: config/tc-sh.c:2524 config/tc-sh.c:2557
+#: config/tc-sh.c:2611 config/tc-sh.c:2644
 msgid "invalid movx address register"
 msgstr ""
 
-#: config/tc-sh.c:2526
+#: config/tc-sh.c:2613
 msgid "insn cannot be combined with non-nopy"
 msgstr ""
 
-#: config/tc-sh.c:2540 config/tc-sh.c:2596
+#: config/tc-sh.c:2627 config/tc-sh.c:2683
 msgid "invalid movy address register"
 msgstr ""
 
-#: config/tc-sh.c:2542
+#: config/tc-sh.c:2629
 msgid "insn cannot be combined with non-nopx"
 msgstr ""
 
-#: config/tc-sh.c:2555
+#: config/tc-sh.c:2642
 msgid "previous movy requires nopx"
 msgstr ""
 
-#: config/tc-sh.c:2563 config/tc-sh.c:2568
+#: config/tc-sh.c:2650 config/tc-sh.c:2655
 msgid "invalid movx dsp register"
 msgstr ""
 
-#: config/tc-sh.c:2578
+#: config/tc-sh.c:2665
 msgid "previous movx requires nopy"
 msgstr ""
 
-#: config/tc-sh.c:2587 config/tc-sh.c:2592
+#: config/tc-sh.c:2674 config/tc-sh.c:2679
 msgid "invalid movy dsp register"
 msgstr ""
 
-#: config/tc-sh.c:2602
+#: config/tc-sh.c:2689
 msgid "dsp immediate shift value not constant"
 msgstr ""
 
-#: config/tc-sh.c:2616 config/tc-sh.c:2642
+#: config/tc-sh.c:2703 config/tc-sh.c:2729
 msgid "multiple parallel processing specifications"
 msgstr ""
 
-#: config/tc-sh.c:2635
+#: config/tc-sh.c:2722
 msgid "multiple condition specifications"
 msgstr ""
 
-#: config/tc-sh.c:2673
+#: config/tc-sh.c:2760
 msgid "insn cannot be combined with pmuls"
 msgstr ""
 
-#: config/tc-sh.c:2689
+#: config/tc-sh.c:2776
 msgid "bad combined pmuls output operand"
 msgstr ""
 
-#: config/tc-sh.c:2699
+#: config/tc-sh.c:2786
 msgid "destination register is same for parallel insns"
 msgstr ""
 
-#: config/tc-sh.c:2708
+#: config/tc-sh.c:2795
 msgid "condition not followed by conditionalizable insn"
 msgstr ""
 
-#: config/tc-sh.c:2718
+#: config/tc-sh.c:2805
 msgid "unrecognized characters at end of parallel processing insn"
 msgstr ""
 
-#: config/tc-sh.c:2834
+#: config/tc-sh.c:2921
 msgid "opcode not valid for this cpu variant"
 msgstr ""
 
-#: config/tc-sh.c:2867
+#: config/tc-sh.c:2954
 msgid "Delayed branches not available on SH1"
 msgstr ""
 
-#: config/tc-sh.c:2899
+#: config/tc-sh.c:2989
 #, c-format
 msgid "excess operands: '%s'"
 msgstr ""
 
-#: config/tc-sh.c:3026
+#: config/tc-sh.c:3116
 msgid ".uses pseudo-op seen when not relaxing"
 msgstr ""
 
-#: config/tc-sh.c:3032
+#: config/tc-sh.c:3122
 msgid "bad .uses format"
 msgstr ""
 
-#: config/tc-sh.c:3130
+#: config/tc-sh.c:3224
 msgid "Invalid combination: --isa=SHcompact with --isa=SHmedia"
 msgstr ""
 
-#: config/tc-sh.c:3136
+#: config/tc-sh.c:3230
 msgid "Invalid combination: --isa=SHmedia with --isa=SHcompact"
 msgstr ""
 
-#: config/tc-sh.c:3138
+#: config/tc-sh.c:3232
 msgid "Invalid combination: --abi=64 with --isa=SHcompact"
 msgstr ""
 
-#: config/tc-sh.c:3179
+#: config/tc-sh.c:3273
 msgid "Invalid combination: --abi=32 with --abi=64"
 msgstr ""
 
-#: config/tc-sh.c:3185
+#: config/tc-sh.c:3279
 msgid "Invalid combination: --abi=64 with --abi=32"
 msgstr ""
 
-#: config/tc-sh.c:3187
+#: config/tc-sh.c:3281
 msgid "Invalid combination: --isa=SHcompact with --abi=64"
 msgstr ""
 
-#: config/tc-sh.c:3221
+#: config/tc-sh.c:3315
 #, c-format
 msgid ""
 "SH options:\n"
@@ -8981,7 +9977,7 @@ msgid ""
 "    | fp"
 msgstr ""
 
-#: config/tc-sh.c:3247
+#: config/tc-sh.c:3341
 #, c-format
 msgid ""
 "--isa=[shmedia\t\tset as the default instruction set for SH64\n"
@@ -8990,7 +9986,7 @@ msgid ""
 "    | SHcompact]\n"
 msgstr ""
 
-#: config/tc-sh.c:3252
+#: config/tc-sh.c:3346
 #, c-format
 msgid ""
 "--abi=[32|64]\t\tset size of expanded SHmedia operands and object\n"
@@ -9004,89 +10000,89 @@ msgid ""
 "\t\t\tto 32 bits only\n"
 msgstr ""
 
-#: config/tc-sh.c:3336
+#: config/tc-sh.c:3445
 msgid ".uses does not refer to a local symbol in the same section"
 msgstr ""
 
-#: config/tc-sh.c:3355
+#: config/tc-sh.c:3464
 msgid "can't find fixup pointed to by .uses"
 msgstr ""
 
-#: config/tc-sh.c:3375
+#: config/tc-sh.c:3484
 msgid ".uses target does not refer to a local symbol in the same section"
 msgstr ""
 
-#: config/tc-sh.c:3452
+#: config/tc-sh.c:3561
 msgid "displacement overflows 12-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3455
+#: config/tc-sh.c:3564
 #, c-format
 msgid "displacement to defined symbol %s overflows 12-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3459
+#: config/tc-sh.c:3568
 #, c-format
 msgid "displacement to undefined symbol %s overflows 12-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3532
+#: config/tc-sh.c:3641
 msgid "displacement overflows 8-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3535
+#: config/tc-sh.c:3644
 #, c-format
 msgid "displacement to defined symbol %s overflows 8-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3539
+#: config/tc-sh.c:3648
 #, c-format
 msgid "displacement to undefined symbol %s overflows 8-bit field "
 msgstr ""
 
-#: config/tc-sh.c:3556
+#: config/tc-sh.c:3665
 #, c-format
 msgid "overflow in branch to %s; converted into longer instruction sequence"
 msgstr ""
 
-#: config/tc-sh.c:3622 config/tc-sh.c:3669 config/tc-sparc.c:4234
-#: config/tc-sparc.c:4259
+#: config/tc-sh.c:3731 config/tc-sh.c:3778 config/tc-sparc.c:4314
+#: config/tc-sparc.c:4339
 msgid "misaligned data"
 msgstr ""
 
-#: config/tc-sh.c:4076
+#: config/tc-sh.c:4206
 msgid "misaligned offset"
 msgstr ""
 
-#: config/tc-sparc.c:288
+#: config/tc-sparc.c:286
 msgid "Invalid default architecture, broken assembler."
 msgstr ""
 
-#: config/tc-sparc.c:292 config/tc-sparc.c:495
+#: config/tc-sparc.c:290 config/tc-sparc.c:497
 msgid "Bad opcode table, broken assembler."
 msgstr ""
 
-#: config/tc-sparc.c:487
+#: config/tc-sparc.c:489
 #, c-format
 msgid "invalid architecture -xarch=%s"
 msgstr ""
 
-#: config/tc-sparc.c:489
+#: config/tc-sparc.c:491
 #, c-format
 msgid "invalid architecture -A%s"
 msgstr ""
 
-#: config/tc-sparc.c:556
+#: config/tc-sparc.c:558
 #, c-format
 msgid "No compiled in support for %d bit object file format"
 msgstr ""
 
-#: config/tc-sparc.c:634
+#: config/tc-sparc.c:636
 #, c-format
 msgid "SPARC options:\n"
 msgstr ""
 
-#: config/tc-sparc.c:663
+#: config/tc-sparc.c:665
 #, c-format
 msgid ""
 "\n"
@@ -9098,24 +10094,24 @@ msgid ""
 "-no-relax\t\tavoid changing any jumps and branches\n"
 msgstr ""
 
-#: config/tc-sparc.c:671
+#: config/tc-sparc.c:673
 #, c-format
 msgid "-k\t\t\tgenerate PIC\n"
 msgstr ""
 
-#: config/tc-sparc.c:675
+#: config/tc-sparc.c:677
 #, c-format
 msgid ""
 "-32\t\t\tcreate 32 bit object file\n"
 "-64\t\t\tcreate 64 bit object file\n"
 msgstr ""
 
-#: config/tc-sparc.c:678
+#: config/tc-sparc.c:680
 #, c-format
 msgid "\t\t\t[default is %d]\n"
 msgstr ""
 
-#: config/tc-sparc.c:680
+#: config/tc-sparc.c:682
 #, c-format
 msgid ""
 "-TSO\t\t\tuse Total Store Ordering\n"
@@ -9123,12 +10119,12 @@ msgid ""
 "-RMO\t\t\tuse Relaxed Memory Ordering\n"
 msgstr ""
 
-#: config/tc-sparc.c:684
+#: config/tc-sparc.c:686
 #, c-format
 msgid "\t\t\t[default is %s]\n"
 msgstr ""
 
-#: config/tc-sparc.c:686
+#: config/tc-sparc.c:688
 #, c-format
 msgid ""
 "-KPIC\t\t\tgenerate PIC\n"
@@ -9142,7 +10138,7 @@ msgid ""
 "-s\t\t\tignored\n"
 msgstr ""
 
-#: config/tc-sparc.c:698
+#: config/tc-sparc.c:700
 #, c-format
 msgid ""
 "-EL\t\t\tgenerate code for a little endian machine\n"
@@ -9151,1172 +10147,1181 @@ msgid ""
 "                        instructions and little endian data.\n"
 msgstr ""
 
-#: config/tc-sparc.c:819
+#: config/tc-sparc.c:833
 #, c-format
 msgid "Internal error: losing opcode: `%s' \"%s\"\n"
 msgstr ""
 
-#: config/tc-sparc.c:838
+#: config/tc-sparc.c:852
 #, c-format
 msgid "Internal error: can't find opcode `%s' for `%s'\n"
 msgstr ""
 
-#: config/tc-sparc.c:984
+#: config/tc-sparc.c:998
 msgid "Support for 64-bit arithmetic not compiled in."
 msgstr ""
 
-#: config/tc-sparc.c:1031
+#: config/tc-sparc.c:1045
 msgid "set: number not in 0..4294967295 range"
 msgstr ""
 
-#: config/tc-sparc.c:1038
+#: config/tc-sparc.c:1052
 msgid "set: number not in -2147483648..4294967295 range"
 msgstr ""
 
-#: config/tc-sparc.c:1098
+#: config/tc-sparc.c:1112
 msgid "setsw: number not in -2147483648..4294967295 range"
 msgstr ""
 
-#: config/tc-sparc.c:1147
+#: config/tc-sparc.c:1161
 msgid "setx: temporary register same as destination register"
 msgstr ""
 
-#: config/tc-sparc.c:1218
+#: config/tc-sparc.c:1232
 msgid "setx: illegal temporary register g0"
 msgstr ""
 
-#: config/tc-sparc.c:1316
+#: config/tc-sparc.c:1330
 msgid "FP branch in delay slot"
 msgstr ""
 
-#: config/tc-sparc.c:1331
+#: config/tc-sparc.c:1345
 msgid "FP branch preceded by FP instruction; NOP inserted"
 msgstr ""
 
-#: config/tc-sparc.c:1371
+#: config/tc-sparc.c:1385
 msgid "failed special case insn sanity check"
 msgstr ""
 
-#: config/tc-sparc.c:1461
+#: config/tc-sparc.c:1475
 msgid ": invalid membar mask name"
 msgstr ""
 
-#: config/tc-sparc.c:1477
+#: config/tc-sparc.c:1491
 msgid ": invalid membar mask expression"
 msgstr ""
 
-#: config/tc-sparc.c:1482
+#: config/tc-sparc.c:1496
 msgid ": invalid membar mask number"
 msgstr ""
 
-#: config/tc-sparc.c:1497
+#: config/tc-sparc.c:1511
 msgid ": invalid siam mode expression"
 msgstr ""
 
-#: config/tc-sparc.c:1502
+#: config/tc-sparc.c:1516
 msgid ": invalid siam mode number"
 msgstr ""
 
-#: config/tc-sparc.c:1518
+#: config/tc-sparc.c:1532
 msgid ": invalid prefetch function name"
 msgstr ""
 
-#: config/tc-sparc.c:1526
+#: config/tc-sparc.c:1540
 msgid ": invalid prefetch function expression"
 msgstr ""
 
-#: config/tc-sparc.c:1531
+#: config/tc-sparc.c:1545
 msgid ": invalid prefetch function number"
 msgstr ""
 
-#: config/tc-sparc.c:1559 config/tc-sparc.c:1571
+#: config/tc-sparc.c:1573 config/tc-sparc.c:1585
 msgid ": unrecognizable privileged register"
 msgstr ""
 
-#: config/tc-sparc.c:1595 config/tc-sparc.c:1620
+#: config/tc-sparc.c:1609 config/tc-sparc.c:1621
+msgid ": unrecognizable hyperprivileged register"
+msgstr ""
+
+#: config/tc-sparc.c:1645 config/tc-sparc.c:1670
 msgid ": unrecognizable v9a or v9b ancillary state register"
 msgstr ""
 
-#: config/tc-sparc.c:1600
+#: config/tc-sparc.c:1650
 msgid ": rd on write only ancillary state register"
 msgstr ""
 
 #. %sys_tick and %sys_tick_cmpr are v9bnotv9a
-#: config/tc-sparc.c:1608
+#: config/tc-sparc.c:1658
 msgid ": unrecognizable v9a ancillary state register"
 msgstr ""
 
-#: config/tc-sparc.c:1644
+#: config/tc-sparc.c:1694
 msgid ": asr number must be between 16 and 31"
 msgstr ""
 
-#: config/tc-sparc.c:1652
+#: config/tc-sparc.c:1702
 msgid ": asr number must be between 0 and 31"
 msgstr ""
 
-#: config/tc-sparc.c:1662
+#: config/tc-sparc.c:1712
 #, c-format
 msgid ": expecting %asrN"
 msgstr ""
 
-#: config/tc-sparc.c:1844 config/tc-sparc.c:1882 config/tc-sparc.c:2289
-#: config/tc-sparc.c:2325
+#: config/tc-sparc.c:1898 config/tc-sparc.c:1936 config/tc-sparc.c:2343
+#: config/tc-sparc.c:2379
 #, c-format
 msgid "Illegal operands: %%%s requires arguments in ()"
 msgstr ""
 
-#: config/tc-sparc.c:1850
+#: config/tc-sparc.c:1904
 #, c-format
 msgid ""
 "Illegal operands: %%%s cannot be used together with other relocs in the insn "
 "()"
 msgstr ""
 
-#: config/tc-sparc.c:1861
+#: config/tc-sparc.c:1915
 #, c-format
 msgid "Illegal operands: %%%s can be only used with call __tls_get_addr"
 msgstr ""
 
-#: config/tc-sparc.c:2068
+#: config/tc-sparc.c:2122
 msgid "detected global register use not covered by .register pseudo-op"
 msgstr ""
 
-#: config/tc-sparc.c:2139
+#: config/tc-sparc.c:2193
 msgid ": There are only 64 f registers; [0-63]"
 msgstr ""
 
-#: config/tc-sparc.c:2141 config/tc-sparc.c:2159
+#: config/tc-sparc.c:2195 config/tc-sparc.c:2213
 msgid ": There are only 32 f registers; [0-31]"
 msgstr ""
 
-#: config/tc-sparc.c:2151
+#: config/tc-sparc.c:2205
 msgid ": There are only 32 single precision f registers; [0-31]"
 msgstr ""
 
-#: config/tc-sparc.c:2337
+#: config/tc-sparc.c:2391
 #, c-format
 msgid ""
 "Illegal operands: Can't do arithmetics other than + and - involving %%%s()"
 msgstr ""
 
-#: config/tc-sparc.c:2447
+#: config/tc-sparc.c:2501
 #, c-format
 msgid "Illegal operands: Can't add non-constant expression to %%%s()"
 msgstr ""
 
-#: config/tc-sparc.c:2457
+#: config/tc-sparc.c:2511
 #, c-format
 msgid ""
 "Illegal operands: Can't do arithmetics involving %%%s() of a relocatable "
 "symbol"
 msgstr ""
 
-#: config/tc-sparc.c:2475
+#: config/tc-sparc.c:2529
 msgid ": PC-relative operand can't be a constant"
 msgstr ""
 
-#: config/tc-sparc.c:2482
+#: config/tc-sparc.c:2536
 msgid ": TLS operand can't be a constant"
 msgstr ""
 
-#: config/tc-sparc.c:2515
+#: config/tc-sparc.c:2569
 msgid ": invalid ASI name"
 msgstr ""
 
-#: config/tc-sparc.c:2523
+#: config/tc-sparc.c:2577
 msgid ": invalid ASI expression"
 msgstr ""
 
-#: config/tc-sparc.c:2528
+#: config/tc-sparc.c:2582
 msgid ": invalid ASI number"
 msgstr ""
 
-#: config/tc-sparc.c:2625
+#: config/tc-sparc.c:2679
 msgid "OPF immediate operand out of range (0-0x1ff)"
 msgstr ""
 
-#: config/tc-sparc.c:2630
+#: config/tc-sparc.c:2684
 msgid "non-immediate OPF operand, ignored"
 msgstr ""
 
-#: config/tc-sparc.c:2649
+#: config/tc-sparc.c:2703
 msgid ": invalid cpreg name"
 msgstr ""
 
-#: config/tc-sparc.c:2678
+#: config/tc-sparc.c:2732
 #, c-format
 msgid "Illegal operands%s"
 msgstr ""
 
-#: config/tc-sparc.c:2712
+#: config/tc-sparc.c:2766
 #, c-format
 msgid "architecture bumped from \"%s\" to \"%s\" on \"%s\""
 msgstr ""
 
-#: config/tc-sparc.c:2748
+#: config/tc-sparc.c:2802
 #, c-format
 msgid "Architecture mismatch on \"%s\"."
 msgstr ""
 
-#: config/tc-sparc.c:2749
+#: config/tc-sparc.c:2803
 #, c-format
 msgid " (Requires %s; requested architecture is %s.)"
 msgstr ""
 
-#: config/tc-sparc.c:3369
+#: config/tc-sparc.c:3423
 #, c-format
 msgid "bad or unhandled relocation type: 0x%02x"
 msgstr ""
 
-#: config/tc-sparc.c:3679
+#: config/tc-sparc.c:3759
 msgid "Expected comma after name"
 msgstr ""
 
-#: config/tc-sparc.c:3688
+#: config/tc-sparc.c:3768
 #, c-format
 msgid "BSS length (%d.) <0! Ignored."
 msgstr ""
 
-#: config/tc-sparc.c:3700
+#: config/tc-sparc.c:3780
 msgid "bad .reserve segment -- expected BSS segment"
 msgstr ""
 
-#: config/tc-sparc.c:3717
-msgid "missing alignment"
-msgstr ""
-
-#: config/tc-sparc.c:3728
+#: config/tc-sparc.c:3808
 #, c-format
 msgid "alignment too large; assuming %d"
 msgstr ""
 
-#: config/tc-sparc.c:3734 config/tc-sparc.c:3885
+#: config/tc-sparc.c:3814 config/tc-sparc.c:3965
 msgid "negative alignment"
 msgstr ""
 
-#: config/tc-sparc.c:3744 config/tc-sparc.c:3908 read.c:1313 read.c:2143
+#: config/tc-sparc.c:3824 config/tc-sparc.c:3988 read.c:1315 read.c:2350
 msgid "alignment not a power of 2"
 msgstr ""
 
-#: config/tc-sparc.c:3822 config/tc-v850.c:223
+#: config/tc-sparc.c:3902 config/tc-v850.c:222
 msgid "Expected comma after symbol-name"
 msgstr ""
 
-#: config/tc-sparc.c:3832
+#: config/tc-sparc.c:3912
 #, c-format
 msgid ".COMMon length (%lu) out of range ignored"
 msgstr ""
 
-#: config/tc-sparc.c:3865
+#: config/tc-sparc.c:3945
 msgid "Expected comma after common length"
 msgstr ""
 
-#: config/tc-sparc.c:3879
+#: config/tc-sparc.c:3959
 #, c-format
 msgid "alignment too large; assuming %ld"
 msgstr ""
 
-#: config/tc-sparc.c:4025
+#: config/tc-sparc.c:4105
 msgid "Unknown segment type"
 msgstr ""
 
-#: config/tc-sparc.c:4104 config/tc-sparc.c:4114
+#: config/tc-sparc.c:4184 config/tc-sparc.c:4194
 #, c-format
 msgid "register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"
 msgstr ""
 
-#: config/tc-sparc.c:4132
+#: config/tc-sparc.c:4212
 msgid "redefinition of global register"
 msgstr ""
 
-#: config/tc-sparc.c:4143
+#: config/tc-sparc.c:4223
 #, c-format
 msgid "Register symbol %s already defined."
 msgstr ""
 
-#: config/tc-sparc.c:4352
+#: config/tc-sparc.c:4432
 #, c-format
 msgid "Illegal operands: %%r_plt in %d-byte data field"
 msgstr ""
 
-#: config/tc-sparc.c:4362
+#: config/tc-sparc.c:4442
 #, c-format
 msgid "Illegal operands: %%r_tls_dtpoff in %d-byte data field"
 msgstr ""
 
-#: config/tc-sparc.c:4399
+#: config/tc-sparc.c:4479 config/tc-vax.c:3312
 #, c-format
 msgid "Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"
 msgstr ""
 
-#: config/tc-sparc.c:4407 config/tc-sparc.c:4438 config/tc-sparc.c:4447
+#: config/tc-sparc.c:4487 config/tc-sparc.c:4518 config/tc-sparc.c:4527
+#: config/tc-vax.c:3320 config/tc-vax.c:3351 config/tc-vax.c:3360
 #, c-format
 msgid "Illegal operands: %%r_%s%d requires arguments in ()"
 msgstr ""
 
-#: config/tc-sparc.c:4456
+#: config/tc-sparc.c:4536 config/tc-vax.c:3369
 #, c-format
 msgid "Illegal operands: garbage after %%r_%s%d()"
 msgstr ""
 
-#: config/tc-sparc.h:46
+#: config/tc-sparc.h:60
 msgid "sparc convert_frag\n"
 msgstr ""
 
-#: config/tc-sparc.h:48
+#: config/tc-sparc.h:62 config/tc-z80.h:53
 msgid "estimate_size_before_relax called"
 msgstr ""
 
+#: config/tc-spu.c:126
+#, c-format
+msgid "Can't hash instruction '%s':%s"
+msgstr ""
+
+#: config/tc-spu.c:180
+msgid ""
+"SPU options:\n"
+"  --apuasm\t\t  emulate behaviour of apuasm\n"
+msgstr ""
+
+#: config/tc-spu.c:286
+#, c-format
+msgid "Invalid mnemonic '%s'"
+msgstr ""
+
+#: config/tc-spu.c:292
+#, c-format
+msgid "'%s' is only available in DD2.0 or higher."
+msgstr ""
+
+#: config/tc-spu.c:324
+#, c-format
+msgid "Error in argument %d.  Expecting:  \"%s\""
+msgstr ""
+
+#: config/tc-spu.c:335
+msgid "Mixing register syntax, with and without '$'."
+msgstr ""
+
+#: config/tc-spu.c:341
+#, c-format
+msgid "Treating '%-*s' as a symbol."
+msgstr ""
+
+#: config/tc-spu.c:551
+msgid "'SPU_RdEventMask' (channel 11) is only available in DD2.0 or higher."
+msgstr ""
+
+#: config/tc-spu.c:553
+msgid "'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher."
+msgstr ""
+
+#: config/tc-spu.c:596
+#, c-format
+msgid "Using old style, %%lo(expr), please change to PPC style, expr@l."
+msgstr ""
+
+#: config/tc-spu.c:602
+#, c-format
+msgid "Using old style, %%hi(expr), please change to PPC style, expr@h."
+msgstr ""
+
+#: config/tc-spu.c:672 config/tc-spu.c:675
+#, c-format
+msgid "Constant expression %d out of range, [%d, %d]."
+msgstr ""
+
+#: config/tc-spu.c:860
+msgid "Relaxation should never occur"
+msgstr ""
+
+#: config/tc-spu.h:83
+msgid "spu convert_frag\n"
+msgstr ""
+
 #. Only word (et al.), align, or conditionals are allowed within
 #. .struct/.union.
-#: config/tc-tic54x.c:222
+#: config/tc-tic54x.c:220
 msgid "pseudo-op illegal within .struct/.union"
 msgstr ""
 
-#: config/tc-tic54x.c:347
+#: config/tc-tic54x.c:345
 #, c-format
 msgid "C54x-specific command line  options:\n"
 msgstr ""
 
-#: config/tc-tic54x.c:348
+#: config/tc-tic54x.c:346
 #, c-format
 msgid "-mfar-mode | -mf          Use extended addressing\n"
 msgstr ""
 
-#: config/tc-tic54x.c:349
+#: config/tc-tic54x.c:347
 #, c-format
 msgid "-mcpu=<CPU version>       Specify the CPU version\n"
 msgstr ""
 
-#: config/tc-tic54x.c:350
+#: config/tc-tic54x.c:348
 #, c-format
 msgid "-merrors-to-file <filename>\n"
 msgstr ""
 
-#: config/tc-tic54x.c:351
+#: config/tc-tic54x.c:349
 #, c-format
 msgid "-me <filename>            Redirect errors to a file\n"
 msgstr ""
 
-#: config/tc-tic54x.c:473
+#: config/tc-tic54x.c:471
 msgid "Comma and symbol expected for '.asg STRING, SYMBOL'"
 msgstr ""
 
-#: config/tc-tic54x.c:527
+#: config/tc-tic54x.c:525
 msgid "Unterminated string after absolute expression"
 msgstr ""
 
-#: config/tc-tic54x.c:535
+#: config/tc-tic54x.c:533
 msgid "Comma and symbol expected for '.eval EXPR, SYMBOL'"
 msgstr ""
 
-#: config/tc-tic54x.c:547
+#: config/tc-tic54x.c:545
 msgid "symbols assigned with .eval must begin with a letter"
 msgstr ""
 
-#: config/tc-tic54x.c:805
+#: config/tc-tic54x.c:803
 msgid "Offset on nested structures is ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:856
+#: config/tc-tic54x.c:854
 #, c-format
 msgid ".end%s without preceding .%s"
 msgstr ""
 
-#: config/tc-tic54x.c:923
+#: config/tc-tic54x.c:921
 #, c-format
 msgid "Unrecognized struct/union tag '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:925
+#: config/tc-tic54x.c:923
 msgid ".tag requires a structure tag"
 msgstr ""
 
-#: config/tc-tic54x.c:931
+#: config/tc-tic54x.c:929
 msgid "Label required for .tag"
 msgstr ""
 
-#: config/tc-tic54x.c:950
+#: config/tc-tic54x.c:948
 #, c-format
 msgid ".tag target '%s' undefined"
 msgstr ""
 
-#: config/tc-tic54x.c:1013
+#: config/tc-tic54x.c:1011
 #, c-format
 msgid ".field count '%d' out of range (1 <= X <= 32)"
 msgstr ""
 
-#: config/tc-tic54x.c:1041
+#: config/tc-tic54x.c:1039
 #, c-format
 msgid "Unrecognized field type '%c'"
 msgstr ""
 
 #. Disallow .byte with a non constant expression that will
 #. require relocation.
-#: config/tc-tic54x.c:1178
+#: config/tc-tic54x.c:1176
 msgid "Relocatable values require at least WORD storage"
 msgstr ""
 
-#: config/tc-tic54x.c:1240
+#: config/tc-tic54x.c:1238
 msgid "Use of .def/.ref is deprecated.  Use .global instead"
 msgstr ""
 
-#: config/tc-tic54x.c:1439
+#: config/tc-tic54x.c:1437
 msgid ".space/.bes repeat count is negative, ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:1444
+#: config/tc-tic54x.c:1442
 msgid ".space/.bes repeat count is zero, ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:1522
+#: config/tc-tic54x.c:1520
 msgid "Missing size argument"
 msgstr ""
 
-#: config/tc-tic54x.c:1659
+#: config/tc-tic54x.c:1657
 msgid "CPU version has already been set"
 msgstr ""
 
-#: config/tc-tic54x.c:1663
+#: config/tc-tic54x.c:1661
 #, c-format
 msgid "Unrecognized version '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:1669
+#: config/tc-tic54x.c:1667
 msgid "Changing of CPU version on the fly not supported"
 msgstr ""
 
-#: config/tc-tic54x.c:1805
+#: config/tc-tic54x.c:1803
 msgid "p2align not supported on this target"
 msgstr ""
 
-#: config/tc-tic54x.c:1818
+#: config/tc-tic54x.c:1816
 msgid "Argument to .even ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:1865
+#: config/tc-tic54x.c:1863
 msgid "Invalid field size, must be from 1 to 32"
 msgstr ""
 
-#: config/tc-tic54x.c:1878
+#: config/tc-tic54x.c:1876
 msgid "field size must be 16 when value is relocatable"
 msgstr ""
 
-#: config/tc-tic54x.c:1893
+#: config/tc-tic54x.c:1891
 msgid "field value truncated"
 msgstr ""
 
-#: config/tc-tic54x.c:2002 config/tc-tic54x.c:2319
+#: config/tc-tic54x.c:2000 config/tc-tic54x.c:2317
 #, c-format
 msgid "Unrecognized section '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2011
+#: config/tc-tic54x.c:2009
 msgid "Current section is unitialized, section name required for .clink"
 msgstr ""
 
-#: config/tc-tic54x.c:2225
+#: config/tc-tic54x.c:2223
 msgid "ENDLOOP without corresponding LOOP"
 msgstr ""
 
-#: config/tc-tic54x.c:2269
+#: config/tc-tic54x.c:2267
 msgid "Mixing of normal and extended addressing not supported"
 msgstr ""
 
-#: config/tc-tic54x.c:2275
+#: config/tc-tic54x.c:2273
 msgid "Extended addressing not supported on the specified CPU"
 msgstr ""
 
-#: config/tc-tic54x.c:2325
+#: config/tc-tic54x.c:2323
 msgid ".sblock may be used for initialized sections only"
 msgstr ""
 
-#: config/tc-tic54x.c:2356
+#: config/tc-tic54x.c:2354
 msgid "Symbol missing for .set/.equ"
 msgstr ""
 
-#: config/tc-tic54x.c:2415
+#: config/tc-tic54x.c:2413
 msgid ".var may only be used within a macro definition"
 msgstr ""
 
-#: config/tc-tic54x.c:2423
+#: config/tc-tic54x.c:2421
 msgid "Substitution symbols must begin with a letter"
 msgstr ""
 
-#: config/tc-tic54x.c:2517
+#: config/tc-tic54x.c:2515
 #, c-format
-msgid "Can't open macro library file '%s' for reading."
+msgid "can't open macro library file '%s' for reading: %s"
 msgstr ""
 
-#: config/tc-tic54x.c:2524
+#: config/tc-tic54x.c:2522
 #, c-format
 msgid "File '%s' not in macro archive format"
 msgstr ""
 
-#: config/tc-tic54x.c:2656
+#: config/tc-tic54x.c:2654
 #, c-format
 msgid "Bad COFF version '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2665
+#: config/tc-tic54x.c:2663
 #, c-format
 msgid "Bad CPU version '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2678 config/tc-tic54x.c:2681
+#: config/tc-tic54x.c:2676 config/tc-tic54x.c:2679
 #, c-format
 msgid "Can't redirect stderr to the file '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2809
+#: config/tc-tic54x.c:2807
 #, c-format
 msgid "Undefined substitution symbol '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:3466
+#: config/tc-tic54x.c:3464
 msgid "Badly formed address expression"
 msgstr ""
 
-#: config/tc-tic54x.c:3730
+#: config/tc-tic54x.c:3728
 #, c-format
 msgid "Invalid dmad syntax '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:3796
+#: config/tc-tic54x.c:3794
 #, c-format
 msgid ""
 "Use the .mmregs directive to use memory-mapped register names such as '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:3849
+#: config/tc-tic54x.c:3847
 msgid "Address mode *+ARx is write-only. Results of reading are undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:3869
+#: config/tc-tic54x.c:3867
 #, c-format
 msgid "Unrecognized indirect address format \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:3908
+#: config/tc-tic54x.c:3906
 #, c-format
 msgid "Operand '%s' out of range (%d <= x <= %d)"
 msgstr ""
 
-#: config/tc-tic54x.c:3928
+#: config/tc-tic54x.c:3926
 msgid "Error in relocation handling"
 msgstr ""
 
-#: config/tc-tic54x.c:3949 config/tc-tic54x.c:4013 config/tc-tic54x.c:4045
+#: config/tc-tic54x.c:3947 config/tc-tic54x.c:4011 config/tc-tic54x.c:4043
 #, c-format
 msgid "Unrecognized condition code \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:3966
+#: config/tc-tic54x.c:3964
 #, c-format
 msgid "Condition \"%s\" does not match preceding group"
 msgstr ""
 
-#: config/tc-tic54x.c:3974
+#: config/tc-tic54x.c:3972
 #, c-format
 msgid ""
 "Condition \"%s\" uses a different accumulator from a preceding condition"
 msgstr ""
 
-#: config/tc-tic54x.c:3981
+#: config/tc-tic54x.c:3979
 msgid "Only one comparison conditional allowed"
 msgstr ""
 
-#: config/tc-tic54x.c:3986
+#: config/tc-tic54x.c:3984
 msgid "Only one overflow conditional allowed"
 msgstr ""
 
-#: config/tc-tic54x.c:3994
+#: config/tc-tic54x.c:3992
 #, c-format
 msgid "Duplicate %s conditional"
 msgstr ""
 
-#: config/tc-tic54x.c:4029
+#: config/tc-tic54x.c:4027
 msgid "Invalid auxiliary register (use AR0-AR7)"
 msgstr ""
 
-#: config/tc-tic54x.c:4065
+#: config/tc-tic54x.c:4063
 msgid "lk addressing modes are invalid for memory-mapped register addressing"
 msgstr ""
 
-#: config/tc-tic54x.c:4073
+#: config/tc-tic54x.c:4071
 msgid ""
 "Address mode *+ARx is not allowed in memory-mapped register addressing.  "
 "Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:4099
+#: config/tc-tic54x.c:4097
 msgid ""
 "Destination accumulator for each part of this parallel instruction must be "
 "different"
 msgstr ""
 
-#: config/tc-tic54x.c:4148
+#: config/tc-tic54x.c:4146
 #, c-format
 msgid "Memory mapped register \"%s\" out of range"
 msgstr ""
 
-#: config/tc-tic54x.c:4187
+#: config/tc-tic54x.c:4185
 msgid "Invalid operand (use 1, 2, or 3)"
 msgstr ""
 
-#: config/tc-tic54x.c:4212
+#: config/tc-tic54x.c:4210
 msgid "A status register or status bit name is required"
 msgstr ""
 
-#: config/tc-tic54x.c:4222
+#: config/tc-tic54x.c:4220
 #, c-format
 msgid "Unrecognized status bit \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4245
+#: config/tc-tic54x.c:4243
 #, c-format
 msgid "Invalid status register \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4257
+#: config/tc-tic54x.c:4255
 #, c-format
 msgid "Operand \"%s\" out of range (use 1 or 2)"
 msgstr ""
 
-#: config/tc-tic54x.c:4465
+#: config/tc-tic54x.c:4463
 #, c-format
 msgid "Unrecognized instruction \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4494
+#: config/tc-tic54x.c:4492
 #, c-format
 msgid "Unrecognized operand list '%s' for instruction '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:4526
+#: config/tc-tic54x.c:4524
 #, c-format
 msgid "Unrecognized parallel instruction \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4577
+#: config/tc-tic54x.c:4575
 #, c-format
 msgid "Invalid operand (s) for parallel instruction \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4580
+#: config/tc-tic54x.c:4578
 #, c-format
 msgid "Unrecognized parallel instruction combination \"%s || %s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4817
+#: config/tc-tic54x.c:4815
 #, c-format
 msgid "%s symbol recursion stopped at second appearance of '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:4857
+#: config/tc-tic54x.c:4855
 msgid "Unrecognized substitution symbol function"
 msgstr ""
 
-#: config/tc-tic54x.c:4862
+#: config/tc-tic54x.c:4860
 msgid "Missing '(' after substitution symbol function"
 msgstr ""
 
-#: config/tc-tic54x.c:4876
+#: config/tc-tic54x.c:4874
 msgid "Expecting second argument"
 msgstr ""
 
-#: config/tc-tic54x.c:4889 config/tc-tic54x.c:4939
+#: config/tc-tic54x.c:4887 config/tc-tic54x.c:4937
 msgid "Extra junk in function call, expecting ')'"
 msgstr ""
 
-#: config/tc-tic54x.c:4915
+#: config/tc-tic54x.c:4913
 msgid "Function expects two arguments"
 msgstr ""
 
-#: config/tc-tic54x.c:4928
+#: config/tc-tic54x.c:4926
 msgid "Expecting character constant argument"
 msgstr ""
 
-#: config/tc-tic54x.c:4934
+#: config/tc-tic54x.c:4932
 msgid "Both arguments must be substitution symbols"
 msgstr ""
 
-#: config/tc-tic54x.c:4987
+#: config/tc-tic54x.c:4985
 #, c-format
 msgid "Invalid subscript (use 1 to %d)"
 msgstr ""
 
-#: config/tc-tic54x.c:4997
+#: config/tc-tic54x.c:4995
 #, c-format
 msgid "Invalid length (use 0 to %d"
 msgstr ""
 
-#: config/tc-tic54x.c:5007
+#: config/tc-tic54x.c:5005
 msgid "Missing ')' in subscripted substitution symbol expression"
 msgstr ""
 
-#: config/tc-tic54x.c:5027
+#: config/tc-tic54x.c:5025
 msgid "Missing forced substitution terminator ':'"
 msgstr ""
 
-#: config/tc-tic54x.c:5182
+#: config/tc-tic54x.c:5180
 #, c-format
 msgid ""
 "Instruction does not fit in available delay slots (%d-word insn, %d slots "
 "left)"
 msgstr ""
 
-#: config/tc-tic54x.c:5223
+#: config/tc-tic54x.c:5221
 #, c-format
 msgid "Unrecognized parallel instruction '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:5235
+#: config/tc-tic54x.c:5233
 #, c-format
 msgid "Instruction '%s' requires an LP cpu version"
 msgstr ""
 
-#: config/tc-tic54x.c:5242
+#: config/tc-tic54x.c:5240
 #, c-format
 msgid "Instruction '%s' requires far mode addressing"
 msgstr ""
 
-#: config/tc-tic54x.c:5254
+#: config/tc-tic54x.c:5252
 #, c-format
 msgid ""
 "Instruction does not fit in available delay slots (%d-word insn, %d slots "
 "left). Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5264
+#: config/tc-tic54x.c:5262
 msgid ""
 "Instructions which cause PC discontinuity are not allowed in a delay slot. "
 "Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5275
+#: config/tc-tic54x.c:5273
 #, c-format
 msgid "'%s' is not repeatable. Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5279
+#: config/tc-tic54x.c:5277
 msgid ""
 "Instructions using long offset modifiers or absolute addresses are not "
 "repeatable. Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5459
+#: config/tc-tic54x.c:5457
 #, c-format
 msgid "Unsupported relocation size %d"
 msgstr ""
 
-#: config/tc-tic54x.c:5602
+#: config/tc-tic54x.c:5600
 msgid "non-absolute value used with .space/.bes"
 msgstr ""
 
-#: config/tc-tic54x.c:5606
+#: config/tc-tic54x.c:5604
 #, c-format
 msgid "negative value ignored in %s"
 msgstr ""
 
-#: config/tc-tic54x.c:5695
+#: config/tc-tic54x.c:5693
 #, c-format
 msgid "attempt to .space/.bes backwards? (%ld)"
 msgstr ""
 
-#: config/tc-tic54x.c:5729
+#: config/tc-tic54x.c:5727
 #, c-format
 msgid "Invalid label '%s'"
 msgstr ""
 
-#: config/tc-v850.c:234
+#: config/tc-v850.c:233
 #, c-format
 msgid ".COMMon length (%d.) < 0! Ignored."
 msgstr ""
 
-#: config/tc-v850.c:255
+#: config/tc-v850.c:254
 #, c-format
 msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
 msgstr ""
 
-#: config/tc-v850.c:281
+#: config/tc-v850.c:280
 msgid "Common alignment negative; 0 assumed"
 msgstr ""
 
-#: config/tc-v850.c:939
+#: config/tc-v850.c:938
 #, c-format
 msgid "unknown operand shift: %x\n"
 msgstr ""
 
-#: config/tc-v850.c:940
+#: config/tc-v850.c:939
 msgid "internal failure in parse_register_list"
 msgstr ""
 
-#: config/tc-v850.c:956
+#: config/tc-v850.c:955
 msgid "constant expression or register list expected"
 msgstr ""
 
-#: config/tc-v850.c:961 config/tc-v850.c:974 config/tc-v850.c:993
+#: config/tc-v850.c:960 config/tc-v850.c:973 config/tc-v850.c:992
 msgid "high bits set in register list expression"
 msgstr ""
 
-#: config/tc-v850.c:1032 config/tc-v850.c:1095
+#: config/tc-v850.c:1031 config/tc-v850.c:1094
 msgid "illegal register included in list"
 msgstr ""
 
-#: config/tc-v850.c:1038
+#: config/tc-v850.c:1037
 msgid "system registers cannot be included in list"
 msgstr ""
 
-#: config/tc-v850.c:1043
+#: config/tc-v850.c:1042
 msgid "PSW cannot be included in list"
 msgstr ""
 
-#: config/tc-v850.c:1050
+#: config/tc-v850.c:1049
 msgid "High value system registers cannot be included in list"
 msgstr ""
 
-#: config/tc-v850.c:1074
+#: config/tc-v850.c:1073
 msgid "second register should follow dash in register list"
 msgstr ""
 
-#: config/tc-v850.c:1119
+#: config/tc-v850.c:1118
 #, c-format
 msgid " V850 options:\n"
 msgstr ""
 
-#: config/tc-v850.c:1120
+#: config/tc-v850.c:1119
 #, c-format
 msgid "  -mwarn-signed-overflow    Warn if signed immediate values overflow\n"
 msgstr ""
 
-#: config/tc-v850.c:1121
+#: config/tc-v850.c:1120
 #, c-format
 msgid ""
 "  -mwarn-unsigned-overflow  Warn if unsigned immediate values overflow\n"
 msgstr ""
 
-#: config/tc-v850.c:1122
+#: config/tc-v850.c:1121
 #, c-format
 msgid "  -mv850                    The code is targeted at the v850\n"
 msgstr ""
 
-#: config/tc-v850.c:1123
+#: config/tc-v850.c:1122
 #, c-format
 msgid "  -mv850e                   The code is targeted at the v850e\n"
 msgstr ""
 
-#: config/tc-v850.c:1124
+#: config/tc-v850.c:1123
 #, c-format
 msgid "  -mv850e1                  The code is targeted at the v850e1\n"
 msgstr ""
 
-#: config/tc-v850.c:1125
+#: config/tc-v850.c:1124
 #, c-format
 msgid ""
 "  -mv850any                 The code is generic, despite any processor "
 "specific instructions\n"
 msgstr ""
 
-#: config/tc-v850.c:1126
+#: config/tc-v850.c:1125
 #, c-format
 msgid "  -mrelax                   Enable relaxation\n"
 msgstr ""
 
-#: config/tc-v850.c:1308
+#: config/tc-v850.c:1323
 #, c-format
 msgid "Unable to determine default target processor from string: %s"
 msgstr ""
 
-#: config/tc-v850.c:1343
+#: config/tc-v850.c:1358
 msgid "lo() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1360
+#: config/tc-v850.c:1375
 msgid "ctoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1382
+#: config/tc-v850.c:1397
 msgid "sdaoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1404
+#: config/tc-v850.c:1419
 msgid "zdaoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1437
+#: config/tc-v850.c:1452
 msgid "tdaoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1642
+#: config/tc-v850.c:1657
 msgid "Target processor does not support this instruction."
 msgstr ""
 
-#: config/tc-v850.c:1731 config/tc-v850.c:1760 config/tc-v850.c:1940
+#: config/tc-v850.c:1746 config/tc-v850.c:1775 config/tc-v850.c:1955
 msgid "immediate operand is too large"
 msgstr ""
 
-#: config/tc-v850.c:1742
+#: config/tc-v850.c:1757
 msgid "AAARG -> unhandled constant reloc"
 msgstr ""
 
-#: config/tc-v850.c:1785
+#: config/tc-v850.c:1800
 msgid "invalid register name"
 msgstr ""
 
-#: config/tc-v850.c:1789
+#: config/tc-v850.c:1804
 msgid "register r0 cannot be used here"
 msgstr ""
 
-#: config/tc-v850.c:1800
+#: config/tc-v850.c:1815
 msgid "invalid system register name"
 msgstr ""
 
-#: config/tc-v850.c:1812
+#: config/tc-v850.c:1827
 msgid "expected EP register"
 msgstr ""
 
-#: config/tc-v850.c:1828
+#: config/tc-v850.c:1843
 msgid "invalid condition code name"
 msgstr ""
 
-#: config/tc-v850.c:1848 config/tc-v850.c:1852
+#: config/tc-v850.c:1863 config/tc-v850.c:1867
 msgid "constant too big to fit into instruction"
 msgstr ""
 
-#: config/tc-v850.c:1905
+#: config/tc-v850.c:1920
 msgid "syntax error: value is missing before the register name"
 msgstr ""
 
-#: config/tc-v850.c:1907
+#: config/tc-v850.c:1922
 msgid "syntax error: register not expected"
 msgstr ""
 
-#: config/tc-v850.c:1920
+#: config/tc-v850.c:1935
 msgid "syntax error: system register not expected"
 msgstr ""
 
-#: config/tc-v850.c:1924
+#: config/tc-v850.c:1939
 msgid "syntax error: condition code not expected"
 msgstr ""
 
-#: config/tc-v850.c:1958
+#: config/tc-v850.c:1973 config/tc-xtensa.c:11545
 msgid "invalid operand"
 msgstr ""
 
-#: config/tc-vax.c:290
-#, c-format
-msgid "VIP_BEGIN error:%s"
-msgstr ""
-
-#: config/tc-vax.c:461
-#, c-format
-msgid "Ignoring statement due to \"%s\""
-msgstr ""
-
-#: config/tc-vax.c:480
-#, c-format
-msgid "Aborting because statement has \"%s\""
-msgstr ""
-
-#: config/tc-vax.c:527
-msgid "Can't relocate expression"
-msgstr ""
-
-#: config/tc-vax.c:630
-msgid "Bignum not permitted in short literal. Immediate mode assumed."
-msgstr ""
-
-#: config/tc-vax.c:639
-msgid "Can't do flonum short literal: immediate mode used."
-msgstr ""
-
-#: config/tc-vax.c:684
-#, c-format
-msgid "A bignum/flonum may not be a displacement: 0x%lx used"
-msgstr ""
-
-#: config/tc-vax.c:1007
-#, c-format
-msgid "Short literal overflow(%ld.), immediate mode assumed."
-msgstr ""
-
-#: config/tc-vax.c:1016
-#, c-format
-msgid "Forced short literal to immediate mode. now_seg=%s to_seg=%s"
-msgstr ""
-
-#: config/tc-vax.c:1081
-msgid "Length specification ignored. Address mode 9F used"
-msgstr ""
-
-#: config/tc-vax.c:1142
-msgid "Invalid operand:  immediate value used as base address."
-msgstr ""
-
-#: config/tc-vax.c:1144
-msgid "Invalid operand:  immediate value used as address."
-msgstr ""
-
-#: config/tc-vax.c:1169
-msgid "Symbol used as immediate operand in PIC mode."
-msgstr ""
-
-#: config/tc-vax.c:1942
-msgid "odd number of bytes in operand description"
-msgstr ""
-
-#: config/tc-vax.c:1958
-msgid "Bad operand"
-msgstr ""
-
-#: config/tc-vax.c:1963
-msgid "Not enough operands"
-msgstr ""
-
-#: config/tc-vax.c:1970
-msgid "Too many operands"
-msgstr ""
-
-#: config/tc-vax.c:2533
+#: config/tc-vax.c:1343
 msgid "no '[' to match ']'"
 msgstr ""
 
-#: config/tc-vax.c:2553
+#: config/tc-vax.c:1359
 msgid "bad register in []"
 msgstr ""
 
-#: config/tc-vax.c:2555
+#: config/tc-vax.c:1361
 msgid "[PC] index banned"
 msgstr ""
 
-#: config/tc-vax.c:2590
+#: config/tc-vax.c:1397
 msgid "no '(' to match ')'"
 msgstr ""
 
-#: config/tc-vax.c:2730
+#: config/tc-vax.c:1513
 msgid "invalid branch operand"
 msgstr ""
 
-#: config/tc-vax.c:2759
+#: config/tc-vax.c:1540
 msgid "address prohibits @"
 msgstr ""
 
-#: config/tc-vax.c:2761
+#: config/tc-vax.c:1542
 msgid "address prohibits #"
 msgstr ""
 
-#: config/tc-vax.c:2765
+#: config/tc-vax.c:1546
 msgid "address prohibits -()"
 msgstr ""
 
-#: config/tc-vax.c:2767
+#: config/tc-vax.c:1548
 msgid "address prohibits ()+"
 msgstr ""
 
-#: config/tc-vax.c:2770
+#: config/tc-vax.c:1551
 msgid "address prohibits ()"
 msgstr ""
 
-#: config/tc-vax.c:2772
+#: config/tc-vax.c:1553
 msgid "address prohibits []"
 msgstr ""
 
-#: config/tc-vax.c:2774
+#: config/tc-vax.c:1555
 msgid "address prohibits register"
 msgstr ""
 
-#: config/tc-vax.c:2776
+#: config/tc-vax.c:1557
 msgid "address prohibits displacement length specifier"
 msgstr ""
 
-#: config/tc-vax.c:2806
+#: config/tc-vax.c:1585
 msgid "invalid operand of S^#"
 msgstr ""
 
-#: config/tc-vax.c:2823
+#: config/tc-vax.c:1598
 msgid "S^# needs expression"
 msgstr ""
 
-#: config/tc-vax.c:2830
+#: config/tc-vax.c:1605
 msgid "S^# may only read-access"
 msgstr ""
 
-#: config/tc-vax.c:2855
+#: config/tc-vax.c:1628
 msgid "invalid operand of -()"
 msgstr ""
 
-#: config/tc-vax.c:2861
+#: config/tc-vax.c:1634
 msgid "-(PC) unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2863
+#: config/tc-vax.c:1636
 msgid "[]index same as -()register: unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2899
+#: config/tc-vax.c:1668
 msgid "invalid operand of ()+"
 msgstr ""
 
-#: config/tc-vax.c:2905
+#: config/tc-vax.c:1674
 msgid "(PC)+ unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2907
+#: config/tc-vax.c:1676
 msgid "[]index same as ()+register: unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2932
+#: config/tc-vax.c:1699
 msgid "# conflicts length"
 msgstr ""
 
-#: config/tc-vax.c:2934
+#: config/tc-vax.c:1701
 msgid "# bars register"
 msgstr ""
 
-#: config/tc-vax.c:2956
+#: config/tc-vax.c:1721
 msgid "writing or modifying # is unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2986
+#: config/tc-vax.c:1747
 msgid "length not needed"
 msgstr ""
 
-#: config/tc-vax.c:2993
+#: config/tc-vax.c:1754
 msgid "can't []index a register, because it has no address"
 msgstr ""
 
-#: config/tc-vax.c:2995
+#: config/tc-vax.c:1756
 msgid "a register has no address"
 msgstr ""
 
-#: config/tc-vax.c:3006
+#: config/tc-vax.c:1765
 msgid "PC part of operand unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:3281
+#: config/tc-vax.c:1921
+msgid "odd number of bytes in operand description"
+msgstr ""
+
+#: config/tc-vax.c:1935
+msgid "Bad operand"
+msgstr ""
+
+#: config/tc-vax.c:1940
+msgid "Not enough operands"
+msgstr ""
+
+#: config/tc-vax.c:1947
+msgid "Too many operands"
+msgstr ""
+
+#: config/tc-vax.c:2217
 msgid "SYMBOL TABLE not implemented"
 msgstr ""
 
-#: config/tc-vax.c:3285
+#: config/tc-vax.c:2221
 msgid "TOKEN TRACE not implemented"
 msgstr ""
 
-#: config/tc-vax.c:3289
+#: config/tc-vax.c:2225
 #, c-format
 msgid "Displacement length %s ignored!"
 msgstr ""
 
-#: config/tc-vax.c:3293
+#: config/tc-vax.c:2229
 #, c-format
 msgid "I don't need or use temp. file \"%s\"."
 msgstr ""
 
-#: config/tc-vax.c:3297
+#: config/tc-vax.c:2233
 msgid "I don't use an interpass file! -V ignored"
 msgstr ""
 
-#: config/tc-vax.c:3354
+#: config/tc-vax.c:2290
 #, c-format
 msgid ""
 "VAX options:\n"
@@ -10328,7 +11333,7 @@ msgid ""
 "-V\t\t\tignored\n"
 msgstr ""
 
-#: config/tc-vax.c:3363
+#: config/tc-vax.c:2299
 #, c-format
 msgid ""
 "VMS options:\n"
@@ -10340,6 +11345,69 @@ msgid ""
 "-v\"VERSION\"\t\tcode being assembled was produced by compiler \"VERSION\"\n"
 msgstr ""
 
+#: config/tc-vax.c:2464
+#, c-format
+msgid "Ignoring statement due to \"%s\""
+msgstr ""
+
+#: config/tc-vax.c:2481
+#, c-format
+msgid "Aborting because statement has \"%s\""
+msgstr ""
+
+#: config/tc-vax.c:2526
+msgid "Can't relocate expression"
+msgstr ""
+
+#: config/tc-vax.c:2629
+msgid "Bignum not permitted in short literal. Immediate mode assumed."
+msgstr ""
+
+#: config/tc-vax.c:2638
+msgid "Can't do flonum short literal: immediate mode used."
+msgstr ""
+
+#: config/tc-vax.c:2685
+#, c-format
+msgid "A bignum/flonum may not be a displacement: 0x%lx used"
+msgstr ""
+
+#: config/tc-vax.c:2996
+#, c-format
+msgid "Short literal overflow(%ld.), immediate mode assumed."
+msgstr ""
+
+#: config/tc-vax.c:3005
+#, c-format
+msgid "Forced short literal to immediate mode. now_seg=%s to_seg=%s"
+msgstr ""
+
+#: config/tc-vax.c:3070
+msgid "Length specification ignored. Address mode 9F used"
+msgstr ""
+
+#: config/tc-vax.c:3128
+msgid "Invalid operand:  immediate value used as base address."
+msgstr ""
+
+#: config/tc-vax.c:3130
+msgid "Invalid operand:  immediate value used as address."
+msgstr ""
+
+#: config/tc-vax.c:3155
+msgid "Symbol used as immediate operand in PIC mode."
+msgstr ""
+
+#: config/tc-vax.c:3258
+#, c-format
+msgid "VIP_BEGIN error:%s"
+msgstr ""
+
+#: config/tc-xc16x.c:211
+#, c-format
+msgid " XC16X specific command line options:\n"
+msgstr ""
+
 #: config/tc-xstormy16.c:78
 #, c-format
 msgid " XSTORMY16 specific command line options:\n"
@@ -10350,715 +11418,740 @@ msgstr ""
 msgid "internal error: can't install fix for reloc type %d (`%s')"
 msgstr ""
 
-#: config/tc-xtensa.c:590
+#: config/tc-xtensa.c:602
 msgid "illegal range of target hardware versions"
 msgstr ""
 
-#: config/tc-xtensa.c:738
+#: config/tc-xtensa.c:751
 msgid "--density option is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:741
+#: config/tc-xtensa.c:754
 msgid "--no-density option is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:750
+#: config/tc-xtensa.c:763
 msgid "--generics is deprecated; use --transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:753
+#: config/tc-xtensa.c:766
 msgid "--no-generics is deprecated; use --no-transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:756
+#: config/tc-xtensa.c:769
 msgid "--relax is deprecated; use --transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:759
+#: config/tc-xtensa.c:772
 msgid "--no-relax is deprecated; use --no-transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:776
+#: config/tc-xtensa.c:789
 msgid "--absolute-literals option not supported in this Xtensa configuration"
 msgstr ""
 
-#: config/tc-xtensa.c:849
+#: config/tc-xtensa.c:862
 msgid "prefer-l32r conflicts with prefer-const16"
 msgstr ""
 
-#: config/tc-xtensa.c:855
+#: config/tc-xtensa.c:868
 msgid "prefer-const16 conflicts with prefer-l32r"
 msgstr ""
 
-#: config/tc-xtensa.c:863 config/tc-xtensa.c:872 config/tc-xtensa.c:876
+#: config/tc-xtensa.c:876 config/tc-xtensa.c:885 config/tc-xtensa.c:889
 msgid "invalid target hardware version"
 msgstr ""
 
-#: config/tc-xtensa.c:1078
+#: config/tc-xtensa.c:1064
 msgid "unmatched end directive"
 msgstr ""
 
-#: config/tc-xtensa.c:1107
+#: config/tc-xtensa.c:1093
 msgid ".begin directive with no matching .end directive"
 msgstr ""
 
-#: config/tc-xtensa.c:1148
+#: config/tc-xtensa.c:1134
 msgid "[no-]generics is deprecated; use [no-]transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1153
+#: config/tc-xtensa.c:1139
 msgid "[no-]relax is deprecated; use [no-]transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1166
+#: config/tc-xtensa.c:1152
 #, c-format
 msgid "directive %s cannot be negated"
 msgstr ""
 
-#: config/tc-xtensa.c:1172
+#: config/tc-xtensa.c:1158
 msgid "unknown directive"
 msgstr ""
 
-#: config/tc-xtensa.c:1194 config/tc-xtensa.c:1300 config/tc-xtensa.c:1573
-#: config/tc-xtensa.c:5496
+#: config/tc-xtensa.c:1179 config/tc-xtensa.c:1275 config/tc-xtensa.c:1517
+#: config/tc-xtensa.c:5545
 msgid "directives are not valid inside bundles"
 msgstr ""
 
-#: config/tc-xtensa.c:1206
+#: config/tc-xtensa.c:1191
 msgid ".begin literal is deprecated; use .literal instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1220
+#: config/tc-xtensa.c:1205
 msgid "cannot set literal_prefix inside literal fragment"
 msgstr ""
 
-#: config/tc-xtensa.c:1263
+#: config/tc-xtensa.c:1238
 msgid ".begin [no-]density is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1270 config/tc-xtensa.c:1320
+#: config/tc-xtensa.c:1245 config/tc-xtensa.c:1295
 msgid "Xtensa absolute literals option not supported; ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1313
+#: config/tc-xtensa.c:1288
 msgid ".end [no-]density is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1338
+#: config/tc-xtensa.c:1313
 #, c-format
 msgid "does not match begin %s%s at %s:%d"
 msgstr ""
 
-#: config/tc-xtensa.c:1393
+#: config/tc-xtensa.c:1368
 msgid ".literal_position inside literal directive; ignoring"
 msgstr ""
 
-#: config/tc-xtensa.c:1413
+#: config/tc-xtensa.c:1388
 msgid ".literal not allowed inside .begin literal region"
 msgstr ""
 
-#: config/tc-xtensa.c:1449
+#: config/tc-xtensa.c:1424
 msgid "expected comma or colon after symbol name; rest of line ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1542
+#: config/tc-xtensa.c:1486
 msgid "fall through frequency must be greater than 0"
 msgstr ""
 
-#: config/tc-xtensa.c:1550
+#: config/tc-xtensa.c:1494
 msgid "branch target frequency must be greater than 0"
 msgstr ""
 
-#: config/tc-xtensa.c:1598
+#: config/tc-xtensa.c:1542
 #, c-format
 msgid "opcode-specific %s relocation used outside an instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:1751 config/tc-xtensa.c:1768
+#: config/tc-xtensa.c:1721 config/tc-xtensa.c:1738
 #, c-format
 msgid "bad register name: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:1757
+#: config/tc-xtensa.c:1727
 #, c-format
 msgid "bad register number: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:1836
+#: config/tc-xtensa.c:1804
 msgid "register number out of range"
 msgstr ""
 
-#: config/tc-xtensa.c:1920
+#: config/tc-xtensa.c:1888
 msgid "extra comma"
 msgstr ""
 
-#: config/tc-xtensa.c:1922
+#: config/tc-xtensa.c:1890
 msgid "extra colon"
 msgstr ""
 
-#: config/tc-xtensa.c:1924
+#: config/tc-xtensa.c:1892
 msgid "missing argument"
 msgstr ""
 
-#: config/tc-xtensa.c:1926
+#: config/tc-xtensa.c:1894
 msgid "missing comma or colon"
 msgstr ""
 
-#: config/tc-xtensa.c:1983
+#: config/tc-xtensa.c:1951
 msgid "incorrect register number, ignoring"
 msgstr ""
 
-#: config/tc-xtensa.c:1990
+#: config/tc-xtensa.c:1958
 msgid "too many arguments"
 msgstr ""
 
-#: config/tc-xtensa.c:2063
+#: config/tc-xtensa.c:2031
 #, c-format
 msgid "cannot encode opcode \"%s\""
 msgstr ""
 
-#: config/tc-xtensa.c:2157
+#: config/tc-xtensa.c:2125
 #, c-format
 msgid "not enough operands (%d) for '%s'; expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:2164
+#: config/tc-xtensa.c:2132
 #, c-format
 msgid "too many operands (%d) for '%s'; expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:2219
+#: config/tc-xtensa.c:2183
 #, c-format
 msgid "invalid register '%s' for '%s' instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:2226
+#: config/tc-xtensa.c:2190
 #, c-format
 msgid "invalid register number (%ld) for '%s' instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:2295
+#: config/tc-xtensa.c:2258
 #, c-format
 msgid "invalid register number (%ld) for '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:2685
+#: config/tc-xtensa.c:2649
 #, c-format
 msgid "operand %d of '%s' has out of range value '%u'"
 msgstr ""
 
-#: config/tc-xtensa.c:2691
+#: config/tc-xtensa.c:2655
 #, c-format
 msgid "operand %d of '%s' has invalid value '%u'"
 msgstr ""
 
-#: config/tc-xtensa.c:2739
+#: config/tc-xtensa.c:2703
 #, c-format
 msgid "internal error: unknown option name '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:3791
+#: config/tc-xtensa.c:3778
 msgid "INSTR_LABEL_DEF not supported yet"
 msgstr ""
 
-#: config/tc-xtensa.c:3820
+#: config/tc-xtensa.c:3807
 msgid "can't handle generation of literal/labels yet"
 msgstr ""
 
-#: config/tc-xtensa.c:3824
+#: config/tc-xtensa.c:3811
 msgid "can't handle undefined OP TYPE"
 msgstr ""
 
-#: config/tc-xtensa.c:3885
+#: config/tc-xtensa.c:3872
 #, c-format
 msgid "found %d operands for '%s':  Expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:3892
+#: config/tc-xtensa.c:3879
 #, c-format
 msgid "found too many (%d) operands for '%s':  Expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:4029
+#: config/tc-xtensa.c:4016
 msgid "invalid immediate"
 msgstr ""
 
-#: config/tc-xtensa.c:4140
+#: config/tc-xtensa.c:4130
 #, c-format
 msgid "invalid relocation for operand %i of '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:4150
+#: config/tc-xtensa.c:4140
 #, c-format
 msgid "invalid expression for operand %i of '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:4160
+#: config/tc-xtensa.c:4150
 #, c-format
 msgid "invalid relocation in instruction slot %i"
 msgstr ""
 
-#: config/tc-xtensa.c:4167
+#: config/tc-xtensa.c:4157
 #, c-format
 msgid "undefined symbol for opcode \"%s\""
 msgstr ""
 
-#: config/tc-xtensa.c:4608
+#: config/tc-xtensa.c:4612
 msgid "opcode 'NOP.N' unavailable in this configuration"
 msgstr ""
 
-#: config/tc-xtensa.c:4668
+#: config/tc-xtensa.c:4672
 msgid "get_expanded_loop_offset: invalid opcode"
 msgstr ""
 
-#: config/tc-xtensa.c:4751
+#: config/tc-xtensa.c:4804
 #, c-format
 msgid "assembly state not set for first frag in section %s"
 msgstr ""
 
-#: config/tc-xtensa.c:4804
+#: config/tc-xtensa.c:4857
 #, c-format
 msgid "unaligned branch target: %d bytes at 0x%lx"
 msgstr ""
 
-#: config/tc-xtensa.c:4843
+#: config/tc-xtensa.c:4896
 #, c-format
 msgid "unaligned loop: %d bytes at 0x%lx"
 msgstr ""
 
-#: config/tc-xtensa.c:4867
+#: config/tc-xtensa.c:4920
 msgid "unexpected fix"
 msgstr ""
 
-#: config/tc-xtensa.c:4878 config/tc-xtensa.c:4882
+#: config/tc-xtensa.c:4931 config/tc-xtensa.c:4935
 msgid "undecodable fix"
 msgstr ""
 
-#: config/tc-xtensa.c:5012
+#: config/tc-xtensa.c:5061
 msgid "labels are not valid inside bundles"
 msgstr ""
 
-#: config/tc-xtensa.c:5032
+#: config/tc-xtensa.c:5081
 msgid "invalid last instruction for a zero-overhead loop"
 msgstr ""
 
-#: config/tc-xtensa.c:5097
+#: config/tc-xtensa.c:5146
 msgid "extra opening brace"
 msgstr ""
 
-#: config/tc-xtensa.c:5107
+#: config/tc-xtensa.c:5156
 msgid "extra closing brace"
 msgstr ""
 
-#: config/tc-xtensa.c:5125
+#: config/tc-xtensa.c:5183
 msgid "missing closing brace"
 msgstr ""
 
-#: config/tc-xtensa.c:5205
+#: config/tc-xtensa.c:5263
 #, c-format
 msgid "unknown opcode or format name '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:5211
+#: config/tc-xtensa.c:5269
 msgid "format names only valid inside bundles"
 msgstr ""
 
-#: config/tc-xtensa.c:5216
+#: config/tc-xtensa.c:5274
 #, c-format
 msgid "multiple formats specified for one bundle; using '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:5271
+#: config/tc-xtensa.c:5323
 msgid "entry instruction with stack decrement < 16"
 msgstr ""
 
-#: config/tc-xtensa.c:5275
-msgid "entry instruction with non-constant decrement"
-msgstr ""
-
-#: config/tc-xtensa.c:5330
+#: config/tc-xtensa.c:5376
 msgid "unaligned entry instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:5389
+#: config/tc-xtensa.c:5438
 msgid "bad instruction format"
 msgstr ""
 
-#: config/tc-xtensa.c:5392
+#: config/tc-xtensa.c:5441
 msgid "invalid relocation"
 msgstr ""
 
-#: config/tc-xtensa.c:5403
+#: config/tc-xtensa.c:5452
 #, c-format
 msgid "invalid relocation for '%s' instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:5415
+#: config/tc-xtensa.c:5464
 #, c-format
 msgid "invalid relocation for operand %d of '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:5572
+#: config/tc-xtensa.c:5628
 msgid "cannot represent subtraction with an offset"
 msgstr ""
 
-#: config/tc-xtensa.c:5660
+#: config/tc-xtensa.c:5716
 #, c-format
 msgid "unhandled local relocation fix %s"
 msgstr ""
 
-#: config/tc-xtensa.c:5968
+#: config/tc-xtensa.c:6023
 msgid "couldn't find a valid instruction format"
 msgstr ""
 
-#: config/tc-xtensa.c:5969
+#: config/tc-xtensa.c:6024
 #, c-format
 msgid "    ops were: "
 msgstr ""
 
-#: config/tc-xtensa.c:5971
+#: config/tc-xtensa.c:6026
 #, c-format
 msgid " %s;"
 msgstr ""
 
-#: config/tc-xtensa.c:5974
-#, c-format
-msgid "\n"
-msgstr ""
-
-#: config/tc-xtensa.c:5982
+#: config/tc-xtensa.c:6037
 #, c-format
 msgid "format '%s' allows %d slots, but there are %d opcodes"
 msgstr ""
 
-#: config/tc-xtensa.c:5993 config/tc-xtensa.c:6091
+#: config/tc-xtensa.c:6048 config/tc-xtensa.c:6146
 msgid "illegal resource usage in bundle"
 msgstr ""
 
-#: config/tc-xtensa.c:6178
+#: config/tc-xtensa.c:6233
 #, c-format
 msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"
 msgstr ""
 
-#: config/tc-xtensa.c:6183
+#: config/tc-xtensa.c:6238
 #, c-format
 msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"
 msgstr ""
 
-#: config/tc-xtensa.c:6188
+#: config/tc-xtensa.c:6243
 #, c-format
-msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"
 msgstr ""
 
-#: config/tc-xtensa.c:6193
+#: config/tc-xtensa.c:6248
 #, c-format
 msgid ""
-"opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"
+"opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"
 msgstr ""
 
-#: config/tc-xtensa.c:6209
+#: config/tc-xtensa.c:6264
 msgid "multiple branches or jumps in the same bundle"
 msgstr ""
 
-#: config/tc-xtensa.c:6664
+#: config/tc-xtensa.c:6712
 msgid "cannot assemble into a literal fragment"
 msgstr ""
 
-#: config/tc-xtensa.c:6666
+#: config/tc-xtensa.c:6714
 msgid "..."
 msgstr ""
 
-#: config/tc-xtensa.c:7175
+#: config/tc-xtensa.c:7258
 msgid ""
 "instruction sequence (write a0, branch, retw) may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:7285
+#: config/tc-xtensa.c:7370
 msgid "branching or jumping to a loop end may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:7384
+#: config/tc-xtensa.c:7452
 msgid "loop end too close to another loop end may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:7393
+#: config/tc-xtensa.c:7461
 #, c-format
 msgid "fr_var %lu < length %d"
 msgstr ""
 
-#: config/tc-xtensa.c:7564
+#: config/tc-xtensa.c:7620
 msgid ""
 "loop containing less than three instructions may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:7636
+#: config/tc-xtensa.c:7692
 msgid "undecodable instruction in instruction frag"
 msgstr ""
 
-#: config/tc-xtensa.c:7745
+#: config/tc-xtensa.c:7802
 msgid "invalid empty loop"
 msgstr ""
 
-#: config/tc-xtensa.c:7750
+#: config/tc-xtensa.c:7807
 msgid "loop target does not follow loop instruction in section"
 msgstr ""
 
-#: config/tc-xtensa.c:8287
+#: config/tc-xtensa.c:8380
 msgid "bad relaxation state"
 msgstr ""
 
-#: config/tc-xtensa.c:8345
+#: config/tc-xtensa.c:8438
 #, c-format
 msgid "fr_var (%ld) < length (%d)"
 msgstr ""
 
-#: config/tc-xtensa.c:8846
+#: config/tc-xtensa.c:8945
 msgid "internal error: relaxation failed"
 msgstr ""
 
-#: config/tc-xtensa.c:8852
+#: config/tc-xtensa.c:8951
 msgid "internal error: relaxation requires too many steps"
 msgstr ""
 
-#: config/tc-xtensa.c:9027
+#: config/tc-xtensa.c:9127
 msgid "invalid relaxation fragment result"
 msgstr ""
 
-#: config/tc-xtensa.c:9107
+#: config/tc-xtensa.c:9206
 msgid "unable to widen instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:9250
+#: config/tc-xtensa.c:9346
 msgid "multiple literals in expansion"
 msgstr ""
 
-#: config/tc-xtensa.c:9254
+#: config/tc-xtensa.c:9350
 msgid "no registered fragment for literal"
 msgstr ""
 
-#: config/tc-xtensa.c:9256
+#: config/tc-xtensa.c:9352
 msgid "number of literal tokens != 1"
 msgstr ""
 
-#: config/tc-xtensa.c:9400 config/tc-xtensa.c:9406
+#: config/tc-xtensa.c:9482 config/tc-xtensa.c:9488
 #, c-format
 msgid "unresolved loop target symbol: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:9512
+#: config/tc-xtensa.c:9594
 #, c-format
 msgid "invalid expression evaluation type %d"
 msgstr ""
 
-#: config/tc-xtensa.c:9534
+#: config/tc-xtensa.c:9611
 msgid "loop too long for LOOP instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:9805
+#: config/tc-xtensa.c:9881
 #, c-format
 msgid "fixes not all moved from %s"
 msgstr ""
 
-#: config/tc-xtensa.c:9947
+#: config/tc-xtensa.c:10012
 msgid ""
 "literal pool location required for text-section-literals; specify with ."
 "literal_position"
 msgstr ""
 
-#: config/tc-xtensa.c:10456
-#, c-format
-msgid "could not create section %s"
-msgstr ""
-
-#: config/tc-xtensa.c:10458
-#, c-format
-msgid "invalid flag combination on section %s"
-msgstr ""
-
-#: config/tc-xtensa.c:10844
+#: config/tc-xtensa.c:10941
 msgid "too many operands in instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:11078
-#, c-format
-msgid "invalid symbolic operand %d on '%s'"
+#: config/tc-xtensa.c:11152
+msgid "invalid symbolic operand"
 msgstr ""
 
-#: config/tc-xtensa.c:11147 config/tc-xtensa.c:11221
+#: config/tc-xtensa.c:11213
 msgid "operand number mismatch"
 msgstr ""
 
-#: config/tc-xtensa.c:11150
-msgid "cannot encode opcode"
-msgstr ""
-
-#: config/tc-xtensa.c:11225
+#: config/tc-xtensa.c:11217
 #, c-format
 msgid "cannot encode opcode \"%s\" in the given format \"%s\""
 msgstr ""
 
-#: config/tc-xtensa.c:11250
+#: config/tc-xtensa.c:11242
 #, c-format
 msgid "xtensa-isa failure: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:11283
+#: config/tc-xtensa.c:11313
 msgid "invalid opcode"
 msgstr ""
 
-#: config/tc-xtensa.c:11289
+#: config/tc-xtensa.c:11319
 msgid "too few operands"
 msgstr ""
 
-#: config/tc-xtensa.c:11416 config/tc-xtensa.c:11424
+#: config/tc-xtensa.c:11434 config/tc-xtensa.c:11440
 msgid "out of memory"
 msgstr ""
 
-#: config/tc-xtensa.c:11536
-msgid "instruction with constant operands does not fit"
+#: config/tc-xtensa.c:11551
+msgid "symbolic operand not allowed"
+msgstr ""
+
+#: config/tc-xtensa.c:11588
+msgid "cannot decode instruction format"
+msgstr ""
+
+#: config/tc-xtensa.c:11732
+msgid "ignoring extra '-rename-section' delimiter ':'"
 msgstr ""
 
-#: config/tc-xtensa.c:11545 config/tc-xtensa.c:11566
+#: config/tc-xtensa.c:11737
 #, c-format
-msgid "invalid operand %d on '%s'"
+msgid "ignoring invalid '-rename-section' specification: '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:11557
-msgid "invalid subtract operand"
+#: config/tc-xtensa.c:11748
+#, c-format
+msgid "section %s renamed multiple times"
 msgstr ""
 
-#: config/tc-xtensa.c:11571
+#: config/tc-xtensa.c:11750
 #, c-format
-msgid "invalid expression for operand %d on '%s'"
+msgid "multiple sections remapped to output section %s"
 msgstr ""
 
-#: config/tc-xtensa.c:11601
-msgid "cannot decode instruction format"
+#: config/tc-z80.c:244
+msgid "-- unterminated string"
 msgstr ""
 
-#: config/tc-xtensa.c:11760
-msgid "ignoring extra '-rename-section' delimiter ':'"
+#: config/tc-z80.c:314
+msgid "floating point numbers are not implemented"
 msgstr ""
 
-#: config/tc-xtensa.c:11765
-#, c-format
-msgid "ignoring invalid '-rename-section' specification: '%s'"
+#: config/tc-z80.c:493 config/tc-z80.c:499
+msgid "mismatched parentheses"
+msgstr ""
+
+#: config/tc-z80.c:553
+msgid "bad offset expression syntax"
+msgstr ""
+
+#: config/tc-z80.c:577
+msgid "bad expression syntax"
+msgstr ""
+
+#: config/tc-z80.c:690
+msgid "cannot make a relative jump to an absolute location"
+msgstr ""
+
+#: config/tc-z80.c:702 config/tc-z80.c:1960
+msgid "overflow"
+msgstr ""
+
+#: config/tc-z80.c:1070 config/tc-z80.c:1113 config/tc-z80.c:1157
+#: config/tc-z80.c:1277 config/tc-z80.c:1331 config/tc-z80.c:1600
+msgid "bad intruction syntax"
+msgstr ""
+
+#: config/tc-z80.c:1203
+msgid "condition code invalid for jr"
+msgstr ""
+
+#: config/tc-z80.c:1225
+msgid "bad instruction syntax"
+msgstr ""
+
+#: config/tc-z80.c:1704
+msgid "parentheses ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:11776
+#: config/tc-z80.c:1909 read.c:3501
 #, c-format
-msgid "section %s renamed multiple times"
+msgid "junk at end of line, first unrecognized character is `%c'"
+msgstr ""
+
+#: config/tc-z80.c:1935 config/tc-z8k.c:1513 config/tc-z8k.c:1576
+msgid "relative jump out of range"
+msgstr ""
+
+#: config/tc-z80.c:1952
+msgid "index offset  out of range"
 msgstr ""
 
-#: config/tc-xtensa.c:11778
+#: config/tc-z80.c:1994 config/tc-z8k.c:1584
 #, c-format
-msgid "multiple sections remapped to output section %s"
+msgid "md_apply_fix: unknown r_type 0x%x\n"
 msgstr ""
 
-#: config/tc-z8k.c:268
+#: config/tc-z8k.c:282
 #, c-format
 msgid "register rr%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:270
+#: config/tc-z8k.c:284
 #, c-format
 msgid "register rr%d does not exist"
 msgstr ""
 
-#: config/tc-z8k.c:280
+#: config/tc-z8k.c:296
 #, c-format
 msgid "register rh%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:290
+#: config/tc-z8k.c:308
 #, c-format
 msgid "register rl%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:301
+#: config/tc-z8k.c:321
 #, c-format
 msgid "register rq%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:303
+#: config/tc-z8k.c:323
 #, c-format
 msgid "register rq%d does not exist"
 msgstr ""
 
-#: config/tc-z8k.c:313
+#: config/tc-z8k.c:335
 #, c-format
 msgid "register r%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:354
+#: config/tc-z8k.c:376
 #, c-format
 msgid "expected %c"
 msgstr ""
 
-#: config/tc-z8k.c:369
+#: config/tc-z8k.c:391
 #, c-format
 msgid "register is wrong size for a word %s"
 msgstr ""
 
-#: config/tc-z8k.c:383
+#: config/tc-z8k.c:405
 #, c-format
 msgid "register is wrong size for address %s"
 msgstr ""
 
-#: config/tc-z8k.c:517
+#: config/tc-z8k.c:539
 #, c-format
 msgid "unknown interrupt %s"
 msgstr ""
 
 #. No interrupt type specified, opcode won't do anything.
-#: config/tc-z8k.c:540
+#: config/tc-z8k.c:562
 msgid "opcode has no effect"
 msgstr ""
 
-#: config/tc-z8k.c:651
+#: config/tc-z8k.c:673
 msgid "Missing ) in ra(rb)"
 msgstr ""
 
-#: config/tc-z8k.c:731 config/tc-z8k.c:770
+#: config/tc-z8k.c:753 config/tc-z8k.c:792
 #, c-format
 msgid "invalid condition code '%s'"
 msgstr ""
 
-#: config/tc-z8k.c:743
+#: config/tc-z8k.c:765
 #, c-format
 msgid "invalid flag '%s'"
 msgstr ""
 
-#: config/tc-z8k.c:897 config/tc-z8k.c:903
+#: config/tc-z8k.c:919 config/tc-z8k.c:925
 msgid "invalid indirect register size"
 msgstr ""
 
-#: config/tc-z8k.c:920 config/tc-z8k.c:1068 config/tc-z8k.c:1073
+#: config/tc-z8k.c:942 config/tc-z8k.c:1090 config/tc-z8k.c:1095
 msgid "invalid control register name"
 msgstr ""
 
-#: config/tc-z8k.c:1057
+#: config/tc-z8k.c:1079
 msgid "immediate must be 1 or 2"
 msgstr ""
 
-#: config/tc-z8k.c:1060
+#: config/tc-z8k.c:1082
 msgid "immediate 1 or 2 expected"
 msgstr ""
 
-#: config/tc-z8k.c:1091
+#: config/tc-z8k.c:1113
 msgid "can't use R0 here"
 msgstr ""
 
-#: config/tc-z8k.c:1249
+#: config/tc-z8k.c:1271
 msgid "Can't find opcode to match operands"
 msgstr ""
 
-#: config/tc-z8k.c:1348
+#: config/tc-z8k.c:1370
 #, c-format
 msgid "invalid architecture -z%s"
 msgstr ""
 
-#: config/tc-z8k.c:1368
+#: config/tc-z8k.c:1390
 #, c-format
 msgid ""
 " Z8K options:\n"
@@ -11067,33 +12160,24 @@ msgid ""
 "  -linkrelax              create linker relaxable code\n"
 msgstr ""
 
-#: config/tc-z8k.c:1380
+#: config/tc-z8k.c:1402
 #, c-format
 msgid "call to md_convert_frag\n"
 msgstr ""
 
-#: config/tc-z8k.c:1487 config/tc-z8k.c:1527 config/tc-z8k.c:1550
+#: config/tc-z8k.c:1509 config/tc-z8k.c:1549 config/tc-z8k.c:1572
 msgid "cannot branch to odd address"
 msgstr ""
 
-#: config/tc-z8k.c:1491 config/tc-z8k.c:1554
-msgid "relative jump out of range"
-msgstr ""
-
-#: config/tc-z8k.c:1509
+#: config/tc-z8k.c:1531
 msgid "relative address out of range"
 msgstr ""
 
-#: config/tc-z8k.c:1530
+#: config/tc-z8k.c:1552
 msgid "relative call out of range"
 msgstr ""
 
-#: config/tc-z8k.c:1562
-#, c-format
-msgid "md_apply_fix: unknown r_type 0x%x\n"
-msgstr ""
-
-#: config/tc-z8k.c:1574
+#: config/tc-z8k.c:1596
 #, c-format
 msgid "call to md_estimate_size_before_relax\n"
 msgstr ""
@@ -11108,67 +12192,91 @@ msgstr ""
 msgid "can't close `%s'"
 msgstr ""
 
-#: dw2gencfi.c:258
+#: dw2gencfi.c:276
 #, c-format
 msgid "register save offset not a multiple of %u"
 msgstr ""
 
-#: dw2gencfi.c:341
+#: dw2gencfi.c:359
 msgid "CFI state restore without previous remember"
 msgstr ""
 
-#: dw2gencfi.c:387
+#: dw2gencfi.c:411
 msgid "missing separator"
 msgstr ""
 
-#: dw2gencfi.c:409 dw2gencfi.c:427
+#: dw2gencfi.c:433 dw2gencfi.c:451
 msgid "bad register expression"
 msgstr ""
 
-#: dw2gencfi.c:449 dw2gencfi.c:551
+#: dw2gencfi.c:473 dw2gencfi.c:596 dw2gencfi.c:634 dw2gencfi.c:704
 msgid "CFI instruction used without previous .cfi_startproc"
 msgstr ""
 
-#: dw2gencfi.c:587
+#: dw2gencfi.c:658
+msgid "invalid or unsupported encoding in .cfi_personality"
+msgstr ""
+
+#: dw2gencfi.c:665
+msgid ".cfi_personality requires encoding and symbol arguments"
+msgstr ""
+
+#: dw2gencfi.c:688
+msgid "wrong second argument to .cfi_personality"
+msgstr ""
+
+#: dw2gencfi.c:728
+msgid "invalid or unsupported encoding in .cfi_lsda"
+msgstr ""
+
+#: dw2gencfi.c:735
+msgid ".cfi_lsda requires encoding and symbol arguments"
+msgstr ""
+
+#: dw2gencfi.c:760
+msgid "wrong second argument to .cfi_lsda"
+msgstr ""
+
+#: dw2gencfi.c:775
 msgid "previous CFI entry not closed (missing .cfi_endproc)"
 msgstr ""
 
-#: dw2gencfi.c:622
+#: dw2gencfi.c:810
 msgid ".cfi_endproc without corresponding .cfi_startproc"
 msgstr ""
 
-#: dw2gencfi.c:1031
+#: dw2gencfi.c:1339
 msgid "open CFI at the end of file; missing .cfi_endproc directive"
 msgstr ""
 
-#: dwarf2dbg.c:523 dwarf2dbg.c:549
+#: dwarf2dbg.c:553 dwarf2dbg.c:579
 msgid "file number less than one"
 msgstr ""
 
-#: dwarf2dbg.c:529
+#: dwarf2dbg.c:559
 #, c-format
 msgid "file number %ld already allocated"
 msgstr ""
 
-#: dwarf2dbg.c:554 dwarf2dbg.c:1169
+#: dwarf2dbg.c:584 dwarf2dbg.c:1244
 #, c-format
 msgid "unassigned file number %ld"
 msgstr ""
 
-#: dwarf2dbg.c:622
+#: dwarf2dbg.c:652
 msgid "is_stmt value not 0 or 1"
 msgstr ""
 
-#: dwarf2dbg.c:634
+#: dwarf2dbg.c:664
 msgid "isa number less than zero"
 msgstr ""
 
-#: dwarf2dbg.c:640
+#: dwarf2dbg.c:670
 #, c-format
 msgid "unknown .loc sub-directive `%s'"
 msgstr ""
 
-#: dwarf2dbg.c:1234 dwarf2dbg.c:1428
+#: dwarf2dbg.c:1309 dwarf2dbg.c:1558
 msgid "internal error: unknown dwarf2 format"
 msgstr ""
 
@@ -11285,7 +12393,7 @@ msgid ".val pseudo-op used outside of .def/.endef; ignored"
 msgstr ""
 
 #: ecoff.c:2781
-msgid ".val expression is too copmlex"
+msgid ".val expression is too complex"
 msgstr ""
 
 #: ecoff.c:2811
@@ -11325,12 +12433,6 @@ msgstr ""
 msgid ".loc before .file"
 msgstr ""
 
-#: ecoff.c:3355 read.c:1473 read.c:1579 read.c:2256 read.c:2803 symbols.c:327
-#: symbols.c:423
-#, c-format
-msgid "symbol `%s' is already defined"
-msgstr ""
-
 #: ecoff.c:3368
 msgid "bad .weakext directive"
 msgstr ""
@@ -11368,92 +12470,92 @@ msgstr ""
 msgid "GP prologue size exceeds field size, using 0 instead"
 msgstr ""
 
-#: expr.c:82 read.c:3351
+#: expr.c:81 read.c:3566
 msgid "bignum invalid"
 msgstr ""
 
-#: expr.c:84 read.c:3353 read.c:3702 read.c:4550
+#: expr.c:83 read.c:3568 read.c:4025 read.c:4873
 msgid "floating point number invalid"
 msgstr ""
 
-#: expr.c:203
+#: expr.c:202
 msgid "bad floating-point constant: exponent overflow"
 msgstr ""
 
-#: expr.c:207
+#: expr.c:206
 #, c-format
 msgid "bad floating-point constant: unknown error code=%d"
 msgstr ""
 
-#: expr.c:383
+#: expr.c:385
 msgid ""
 "a bignum with underscores may not have more than 8 hex digits in any word"
 msgstr ""
 
-#: expr.c:406
+#: expr.c:408
 msgid "a bignum with underscores must have exactly 4 words"
 msgstr ""
 
 #. Either not seen or not defined.
 #. @@ Should print out the original string instead of
 #. the parsed number.
-#: expr.c:529
+#: expr.c:531
 #, c-format
 msgid "backward ref to unknown label \"%d:\""
 msgstr ""
 
-#: expr.c:647
+#: expr.c:649
 msgid "character constant too large"
 msgstr ""
 
-#: expr.c:893
+#: expr.c:895
 #, c-format
 msgid "expr.c(operand): bad atof_generic return val %d"
 msgstr ""
 
-#: expr.c:954
+#: expr.c:956
 #, c-format
 msgid "missing '%c'"
 msgstr ""
 
-#: expr.c:965 read.c:4034
+#: expr.c:967 read.c:4357
 msgid "EBCDIC constants are not supported"
 msgstr ""
 
-#: expr.c:1082
+#: expr.c:1079
 #, c-format
 msgid "Unary operator %c ignored because bad operand follows"
 msgstr ""
 
-#: expr.c:1128 expr.c:1153
+#: expr.c:1125 expr.c:1150
 msgid "syntax error in .startof. or .sizeof."
 msgstr ""
 
-#: expr.c:1665
+#: expr.c:1661
 msgid "missing operand; zero assumed"
 msgstr ""
 
-#: expr.c:1700
+#: expr.c:1696
 msgid "left operand is a bignum; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1702
+#: expr.c:1698
 msgid "left operand is a float; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1711
+#: expr.c:1707
 msgid "right operand is a bignum; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1713
+#: expr.c:1709
 msgid "right operand is a float; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1769 symbols.c:1207
+#: expr.c:1768 symbols.c:1349
 msgid "division by zero"
 msgstr ""
 
-#: expr.c:1867
+#: expr.c:1868
 msgid "operation combines symbols in different segments"
 msgstr ""
 
@@ -11482,34 +12584,34 @@ msgstr ""
 #. line here (assuming of course that we actually have a line of
 #. input to read), so that it can be displayed in the listing
 #. that is produced at the end of the assembly.
-#: input-file.c:141 input-scrub.c:238 listing.c:332
+#: input-file.c:138 input-scrub.c:241 listing.c:332
 msgid "{standard input}"
 msgstr ""
 
-#: input-file.c:147 input-file.c:156
+#: input-file.c:143
 #, c-format
-msgid "Can't open %s for reading"
+msgid "can't open %s for reading: %s"
 msgstr ""
 
-#: input-file.c:219 input-file.c:246
+#: input-file.c:152 input-file.c:215 input-file.c:241
 #, c-format
-msgid "Can't read from %s"
+msgid "can't read from %s: %s"
 msgstr ""
 
-#: input-file.c:256
+#: input-file.c:249 listing.c:1097 output-file.c:69
 #, c-format
-msgid "Can't close %s"
+msgid "can't close %s: %s"
 msgstr ""
 
-#: input-scrub.c:263
+#: input-scrub.c:266
 msgid "macros nested too deeply"
 msgstr ""
 
-#: input-scrub.c:365 input-scrub.c:387
+#: input-scrub.c:369 input-scrub.c:393
 msgid "partial line at end of file ignored"
 msgstr ""
 
-#: itbl-ops.c:338
+#: itbl-ops.c:329
 #, c-format
 msgid "Unable to allocate memory for new instructions\n"
 msgstr ""
@@ -11522,255 +12624,246 @@ msgstr ""
 msgid "Error:"
 msgstr ""
 
-#: listing.c:1089
-#, c-format
-msgid "can't open list file: %s"
-msgstr ""
-
-#: listing.c:1109
+#: listing.c:1079
 #, c-format
-msgid "error closing list file: %s"
+msgid "can't open %s: %s"
 msgstr ""
 
-#: listing.c:1182
+#: listing.c:1169
 msgid "strange paper height, set to no form"
 msgstr ""
 
-#: listing.c:1246
+#: listing.c:1233
 msgid "new line in title"
 msgstr ""
 
 #. Turns the next expression into a string.
-#: macro.c:436
+#: macro.c:371
 #, no-c-format
 msgid "% operator needs absolute expression"
 msgstr ""
 
-#: macro.c:558
+#: macro.c:521
 #, c-format
 msgid "Missing parameter qualifier for `%s' in macro `%s'"
 msgstr ""
 
-#: macro.c:568
+#: macro.c:531
 #, c-format
 msgid "`%s' is not a valid parameter qualifier for `%s' in macro `%s'"
 msgstr ""
 
-#: macro.c:585
+#: macro.c:548
 #, c-format
 msgid "Pointless default value for required parameter `%s' in macro `%s'"
 msgstr ""
 
-#: macro.c:597
+#: macro.c:560
 #, c-format
 msgid "A parameter named `%s' already exists for macro `%s'"
 msgstr ""
 
-#: macro.c:634
+#: macro.c:597
 #, c-format
 msgid "Reserved word `%s' used as parameter in macro `%s'"
 msgstr ""
 
-#: macro.c:672
+#: macro.c:635
 #, c-format
 msgid "unexpected end of file in macro `%s' definition"
 msgstr ""
 
-#: macro.c:684
+#: macro.c:647
 #, c-format
 msgid "missing `)' after formals in macro definition `%s'"
 msgstr ""
 
-#: macro.c:699
+#: macro.c:662
 msgid "Missing macro name"
 msgstr ""
 
-#: macro.c:708
+#: macro.c:671
 #, c-format
 msgid "Bad parameter list for macro `%s'"
 msgstr ""
 
-#: macro.c:714
+#: macro.c:677
 #, c-format
 msgid "Macro `%s' was already defined"
 msgstr ""
 
-#: macro.c:837 macro.c:839
+#: macro.c:800 macro.c:802
 msgid "missing `)'"
 msgstr ""
 
-#: macro.c:934
+#: macro.c:897
 #, c-format
 msgid "`%s' was already used as parameter (or another local) name"
 msgstr ""
 
-#: macro.c:1093
+#: macro.c:1055
 msgid "confusion in formal parameters"
 msgstr ""
 
-#: macro.c:1100
+#: macro.c:1062
 #, c-format
 msgid "Parameter named `%s' does not exist for macro `%s'"
 msgstr ""
 
-#: macro.c:1108
+#: macro.c:1070
 #, c-format
 msgid "Value for parameter `%s' of macro `%s' was already specified"
 msgstr ""
 
-#: macro.c:1124
+#: macro.c:1084
 msgid "can't mix positional and keyword arguments"
 msgstr ""
 
-#: macro.c:1135
+#: macro.c:1095
 msgid "too many positional arguments"
 msgstr ""
 
-#: macro.c:1183
+#: macro.c:1143
 #, c-format
 msgid "Missing value for required parameter `%s' of macro `%s'"
 msgstr ""
 
-#: macro.c:1320
+#: macro.c:1280
 #, c-format
 msgid "Attempt to purge non-existant macro `%s'"
 msgstr ""
 
-#: macro.c:1339
+#: macro.c:1299
 msgid "unexpected end of file in irp or irpc"
 msgstr ""
 
-#: macro.c:1347
+#: macro.c:1307
 msgid "missing model parameter"
 msgstr ""
 
-#: messages.c:104
+#: messages.c:82
 #, c-format
 msgid "Assembler messages:\n"
 msgstr ""
 
-#: messages.c:206
+#: messages.c:166
 #, c-format
 msgid "Warning: "
 msgstr ""
 
-#: messages.c:307
+#: messages.c:267
 #, c-format
 msgid "Error: "
 msgstr ""
 
-#: messages.c:402 messages.c:422
+#: messages.c:362 messages.c:382
 #, c-format
 msgid "Fatal error: "
 msgstr ""
 
-#: messages.c:437
+#: messages.c:397
 #, c-format
 msgid "Internal error!\n"
 msgstr ""
 
-#: messages.c:439
+#: messages.c:399
 #, c-format
 msgid "Assertion failure in %s at %s line %d.\n"
 msgstr ""
 
-#: messages.c:442
+#: messages.c:402
 #, c-format
 msgid "Assertion failure at %s line %d.\n"
 msgstr ""
 
-#: messages.c:443 messages.c:460
+#: messages.c:403 messages.c:420
 #, c-format
 msgid "Please report this bug.\n"
 msgstr ""
 
-#: messages.c:455
+#: messages.c:415
 #, c-format
 msgid "Internal error, aborting at %s line %d in %s\n"
 msgstr ""
 
-#: messages.c:458
+#: messages.c:418
 #, c-format
 msgid "Internal error, aborting at %s line %d\n"
 msgstr ""
 
-#: messages.c:507
+#: messages.c:467
+#, c-format
+msgid "%s out of domain (%d is not a multiple of %d)"
+msgstr ""
+
+#: messages.c:485
 #, c-format
 msgid "%s out of range (%d is not between %d and %d)"
 msgstr ""
 
 #. xgettext:c-format.
-#: messages.c:530
+#: messages.c:508
 #, c-format
 msgid "%s out of range (0x%s is not between 0x%s and 0x%s)"
 msgstr ""
 
-#: output-file.c:39
+#: output-file.c:35
 #, c-format
 msgid "can't open a bfd on stdout %s"
 msgstr ""
 
-#: output-file.c:44
-#, c-format
-msgid "Selected target format '%s' unknown"
-msgstr ""
-
-#: output-file.c:46
+#: output-file.c:42
 #, c-format
-msgid "FATAL: can't create %s"
+msgid "selected target format '%s' unknown"
 msgstr ""
 
-#: output-file.c:63
+#: output-file.c:44
 #, c-format
-msgid "FATAL: can't close %s\n"
+msgid "can't create %s: %s"
 msgstr ""
 
-#: read.c:450
+#: read.c:458
 msgid "bad or irreducible absolute expression"
 msgstr ""
 
-#: read.c:476
+#: read.c:484
 #, c-format
 msgid "error constructing %s pseudo-op table: %s"
 msgstr ""
 
-#: read.c:896
+#: read.c:894
 #, c-format
 msgid "unknown pseudo-op: `%s'"
 msgstr ""
 
-#: read.c:983
+#: read.c:981
 #, c-format
 msgid "label \"%d$\" redefined"
 msgstr ""
 
-#: read.c:1214
+#: read.c:1216
 msgid ".abort detected.  Abandoning ship."
 msgstr ""
 
-#: read.c:1232 read.c:2406
+#: read.c:1234 read.c:2605
 msgid "ignoring fill value in absolute section"
 msgstr ""
 
-#: read.c:1322
+#: read.c:1324
 #, c-format
 msgid "alignment too large: %u assumed"
 msgstr ""
 
-#: read.c:1354
+#: read.c:1356
 msgid "expected fill pattern missing"
 msgstr ""
 
-#: read.c:1457
-msgid "missing size expression"
-msgstr ""
-
-#: read.c:1463
+#: read.c:1465
 #, c-format
 msgid "size (%ld) out of range, ignored"
 msgstr ""
 
-#: read.c:1483
+#: read.c:1494
 #, c-format
 msgid "size of \"%s\" is already %ld; not changing to %ld"
 msgstr ""
@@ -11784,309 +12877,314 @@ msgstr ""
 #. We do not want to barf on this, especially since such files are used
 #. in the GCC and GDB testsuites.  So we check for negative line numbers
 #. rather than non-positive line numbers.
-#: read.c:1712
+#: read.c:1744
 #, c-format
 msgid "line numbers must be positive; line number %d rejected"
 msgstr ""
 
-#: read.c:1739
+#: read.c:1781
+#, c-format
+msgid "incompatible flag %i in line directive"
+msgstr ""
+
+#: read.c:1793
+#, c-format
+msgid "unsupported flag %i in line directive"
+msgstr ""
+
+#: read.c:1832
 msgid "start address not supported"
 msgstr ""
 
-#: read.c:1748
+#: read.c:1841
 msgid ".err encountered"
 msgstr ""
 
-#: read.c:1764
+#: read.c:1857
 msgid ".error directive invoked in source file"
 msgstr ""
 
-#: read.c:1765
+#: read.c:1858
 msgid ".warning directive invoked in source file"
 msgstr ""
 
-#: read.c:1771
+#: read.c:1864
 #, c-format
 msgid "%s argument must be a string"
 msgstr ""
 
-#: read.c:1803 read.c:1805
+#: read.c:1896 read.c:1898
 #, c-format
 msgid ".fail %ld encountered"
 msgstr ""
 
-#: read.c:1841
+#: read.c:1934
 #, c-format
 msgid ".fill size clamped to %d"
 msgstr ""
 
-#: read.c:1846
+#: read.c:1939
 msgid "size negative; .fill ignored"
 msgstr ""
 
-#: read.c:1852
+#: read.c:1945
 msgid "repeat < 0; .fill ignored"
 msgstr ""
 
-#: read.c:2010
+#: read.c:2083
+msgid "expected numeric constant"
+msgstr ""
+
+#: read.c:2139
+msgid "bad string constant"
+msgstr ""
+
+#: read.c:2143
+msgid "expected <tag> , <value>"
+msgstr ""
+
+#: read.c:2217
 #, c-format
 msgid "unrecognized .linkonce type `%s'"
 msgstr ""
 
-#: read.c:2022
+#: read.c:2229
 msgid ".linkonce is not supported for this object file format"
 msgstr ""
 
-#: read.c:2044
+#: read.c:2251
 #, c-format
 msgid "bfd_set_section_flags: %s"
 msgstr ""
 
-#: read.c:2070
-#, c-format
-msgid "error setting flags for \".sbss\": %s"
-msgstr ""
-
-#: read.c:2117
+#: read.c:2324
 msgid "expected alignment after size"
 msgstr ""
 
-#: read.c:2131
-msgid "alignment negative; 0 assumed"
-msgstr ""
-
-#: read.c:2340
+#: read.c:2539
 #, c-format
 msgid "attempt to redefine pseudo-op `%s' ignored"
 msgstr ""
 
-#: read.c:2401
+#: read.c:2600
 #, c-format
 msgid "invalid segment \"%s\""
 msgstr ""
 
-#: read.c:2409
+#: read.c:2608
 msgid "only constant offsets supported in absolute section"
 msgstr ""
 
-#: read.c:2448
+#: read.c:2647
 msgid "MRI style ORG pseudo-op not supported"
 msgstr ""
 
-#: read.c:2601
+#: read.c:2800
 #, c-format
 msgid "unrecognized section type `%s'"
 msgstr ""
 
-#: read.c:2615
+#: read.c:2814
 msgid "absolute sections are not supported"
 msgstr ""
 
-#: read.c:2630
+#: read.c:2829
 #, c-format
 msgid "unrecognized section command `%s'"
 msgstr ""
 
-#: read.c:2694
+#: read.c:2893
 #, c-format
 msgid ".end%c encountered without preceeding %s"
 msgstr ""
 
-#: read.c:2724
+#: read.c:2923
 #, c-format
 msgid "%s without %s"
 msgstr ""
 
-#: read.c:2951
+#: read.c:3147
 msgid "unsupported variable size or fill value"
 msgstr ""
 
-#: read.c:2979
+#: read.c:3175
 msgid ".space repeat count is zero, ignored"
 msgstr ""
 
-#: read.c:2981
+#: read.c:3177
 msgid ".space repeat count is negative, ignored"
 msgstr ""
 
-#: read.c:3010
+#: read.c:3206
 msgid "space allocation too complex in absolute section"
 msgstr ""
 
-#: read.c:3016
+#: read.c:3212
 msgid "space allocation too complex in common section"
 msgstr ""
 
-#: read.c:3103 read.c:4276
+#: read.c:3299 read.c:4599
 #, c-format
 msgid "bad floating literal: %s"
 msgstr ""
 
-#: read.c:3243
+#: read.c:3458
 #, c-format
 msgid "%s: would close weakref loop: %s"
 msgstr ""
 
-#: read.c:3286
-#, c-format
-msgid "junk at end of line, first unrecognized character is `%c'"
-msgstr ""
-
-#: read.c:3289
+#: read.c:3504
 #, c-format
 msgid "junk at end of line, first unrecognized character valued 0x%x"
 msgstr ""
 
-#: read.c:3347
+#: read.c:3562
 msgid "missing expression"
 msgstr ""
 
-#: read.c:3408
+#: read.c:3624
 #, c-format
 msgid "`%s' can't be equated to common symbol '%s'"
 msgstr ""
 
-#: read.c:3536
+#: read.c:3752
 msgid "rva without symbol"
 msgstr ""
 
-#: read.c:3658
-msgid "attempt to store value in absolute section"
+#: read.c:3809
+msgid "missing or bad offset expression"
 msgstr ""
 
-#: read.c:3696 read.c:4544
-msgid "zero assumed for missing expression"
+#: read.c:3830
+msgid "missing reloc type"
 msgstr ""
 
-#: read.c:3708 read.c:4556 write.c:265
-msgid "register value used as expression"
+#: read.c:3842
+msgid "unrecognized reloc type"
 msgstr ""
 
-#. Leading bits contain both 0s & 1s.
-#: read.c:3786
-#, c-format
-msgid "value 0x%lx truncated to 0x%lx"
+#: read.c:3858
+msgid "bad reloc expression"
 msgstr ""
 
-#: read.c:3802
-#, c-format
-msgid "bignum truncated to %d bytes"
+#: read.c:3981
+msgid "attempt to store value in absolute section"
 msgstr ""
 
-#: read.c:3943
-msgid "using a bit field width of zero"
+#: read.c:4019 read.c:4867
+msgid "zero assumed for missing expression"
 msgstr ""
 
-#: read.c:3951
-#, c-format
-msgid "field width \"%s\" too complex for a bitfield"
+#: read.c:4031 read.c:4879 write.c:260
+msgid "register value used as expression"
 msgstr ""
 
-#: read.c:3959
+#. Leading bits contain both 0s & 1s.
+#: read.c:4109
 #, c-format
-msgid "field width %lu too big to fit in %d bytes: truncated to %d bits"
+msgid "value 0x%lx truncated to 0x%lx"
 msgstr ""
 
-#: read.c:3981
+#: read.c:4125
 #, c-format
-msgid "field value \"%s\" too complex for a bitfield"
+msgid "bignum truncated to %d bytes"
 msgstr ""
 
-#: read.c:4107 read.c:4298
+#: read.c:4430 read.c:4621
 msgid "unresolvable or nonpositive repeat count; using 1"
 msgstr ""
 
-#: read.c:4156
+#: read.c:4479
 #, c-format
 msgid "unknown floating type type '%c'"
 msgstr ""
 
-#: read.c:4178
+#: read.c:4501
 msgid "floating point constant too large"
 msgstr ""
 
-#: read.c:4670
+#: read.c:4993
 msgid "strings must be placed into a section"
 msgstr ""
 
-#: read.c:4720
+#: read.c:5043
 msgid "expected <nn>"
 msgstr ""
 
 #. To be compatible with BSD 4.2 as: give the luser a linefeed!!
-#: read.c:4753 read.c:4839
+#: read.c:5076 read.c:5162
 msgid "unterminated string; newline inserted"
 msgstr ""
 
-#: read.c:4847
+#: read.c:5170
 msgid "bad escaped character in string"
 msgstr ""
 
-#: read.c:4872
+#: read.c:5195
 msgid "expected address expression"
 msgstr ""
 
-#: read.c:4891
+#: read.c:5214
 #, c-format
 msgid "symbol \"%s\" undefined; zero assumed"
 msgstr ""
 
-#: read.c:4894
+#: read.c:5217
 msgid "some symbol undefined; zero assumed"
 msgstr ""
 
-#: read.c:4930
+#: read.c:5253
 msgid "this string may not contain '\\0'"
 msgstr ""
 
-#: read.c:4966
+#: read.c:5289
 msgid "missing string"
 msgstr ""
 
-#: read.c:5053
+#: read.c:5376
 #, c-format
 msgid ".incbin count zero, ignoring `%s'"
 msgstr ""
 
-#: read.c:5079
+#: read.c:5402
 #, c-format
 msgid "file not found: %s"
 msgstr ""
 
-#: read.c:5093
+#: read.c:5416
 #, c-format
 msgid "seek to end of .incbin file failed `%s'"
 msgstr ""
 
-#: read.c:5104
+#: read.c:5427
 #, c-format
 msgid "skip (%ld) or count (%ld) invalid for file size (%ld)"
 msgstr ""
 
-#: read.c:5111
+#: read.c:5434
 #, c-format
 msgid "could not skip to %ld in file `%s'"
 msgstr ""
 
-#: read.c:5120
+#: read.c:5443
 #, c-format
 msgid "truncated file `%s', %ld of %ld bytes read"
 msgstr ""
 
-#: read.c:5278
+#: read.c:5601
 msgid "missing .func"
 msgstr ""
 
-#: read.c:5295
+#: read.c:5618
 msgid ".endfunc missing for previous .func"
 msgstr ""
 
-#: read.c:5418
+#: read.c:5741
 #, c-format
 msgid "missing closing `%c'"
 msgstr ""
 
-#: read.c:5420
+#: read.c:5743
 msgid "stray `\\'"
 msgstr ""
 
@@ -12107,187 +13205,203 @@ msgstr ""
 msgid "comma missing in .xstabs"
 msgstr ""
 
-#: symbols.c:278
+#: symbols.c:277
 #, c-format
 msgid "cannot define symbol `%s' in absolute section"
 msgstr ""
 
-#: symbols.c:409
+#: symbols.c:417
 #, c-format
 msgid "symbol `%s' is already defined as \"%s\"/%s%ld"
 msgstr ""
 
-#: symbols.c:483 symbols.c:490
+#: symbols.c:494 symbols.c:501
 #, c-format
 msgid "inserting \"%s\" into symbol table failed: %s"
 msgstr ""
 
-#: symbols.c:864 symbols.c:868
+#: symbols.c:957 symbols.c:961
 #, c-format
 msgid "undefined symbol `%s' in operation"
 msgstr ""
 
-#: symbols.c:875
+#: symbols.c:968
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s'"
 msgstr ""
 
-#: symbols.c:879
+#: symbols.c:972
 #, c-format
 msgid "invalid section for operation on `%s'"
 msgstr ""
 
-#: symbols.c:887 symbols.c:890
+#: symbols.c:980 symbols.c:983
 #, c-format
 msgid "undefined symbol `%s' in operation setting `%s'"
 msgstr ""
 
-#: symbols.c:897
+#: symbols.c:989
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s' setting `%s'"
 msgstr ""
 
-#: symbols.c:901
+#: symbols.c:992
 #, c-format
 msgid "invalid section for operation on `%s' setting `%s'"
 msgstr ""
 
-#: symbols.c:951
+#: symbols.c:1042
 #, c-format
 msgid "symbol definition loop encountered at `%s'"
 msgstr ""
 
-#: symbols.c:1209
+#: symbols.c:1069
+#, c-format
+msgid "cannot convert expression symbol %s to complex relocation"
+msgstr ""
+
+#: symbols.c:1351
 #, c-format
 msgid "division by zero when setting `%s'"
 msgstr ""
 
-#: symbols.c:1291 write.c:1545
+#: symbols.c:1432 write.c:1805
 #, c-format
 msgid "can't resolve value for symbol `%s'"
 msgstr ""
 
-#: symbols.c:1738
+#: symbols.c:1882
 #, c-format
 msgid "\"%d\" (instance number %d of a %s label)"
 msgstr ""
 
-#: symbols.c:1775
+#: symbols.c:1911
 #, c-format
 msgid "attempt to get value of unresolved symbol `%s'"
 msgstr ""
 
-#: symbols.c:2045
+#: symbols.c:2184
 msgid "section symbols are already global"
 msgstr ""
 
-#: symbols.c:2150
+#: symbols.c:2289
 #, c-format
 msgid "Accessing function `%s' as thread-local object"
 msgstr ""
 
-#: symbols.c:2154
+#: symbols.c:2293
 #, c-format
 msgid "Accessing `%s' as thread-local object"
 msgstr ""
 
-#: write.c:164
+#: write.c:159
 #, c-format
 msgid "field fx_size too small to hold %d"
 msgstr ""
 
-#: write.c:440
+#: write.c:436
 #, c-format
 msgid "attempt to .org/.space backwards? (%ld)"
 msgstr ""
 
-#: write.c:691
+#: write.c:664
+msgid "invalid offset expression"
+msgstr ""
+
+#: write.c:686
+msgid "invalid reloc expression"
+msgstr ""
+
+#: write.c:1039
+#, c-format
+msgid "value of %s too large for field of %d bytes at %s"
+msgstr ""
+
+#: write.c:1051
 #, c-format
-msgid "Local symbol `%s' can't be equated to undefined symbol `%s'"
+msgid "signed .word overflow; switch may be too large; %ld at 0x%lx"
 msgstr ""
 
-#: write.c:865 write.c:937
+#: write.c:1099
 msgid "relocation out of range"
 msgstr ""
 
-#: write.c:868 write.c:940
+#: write.c:1102
 #, c-format
 msgid "%s:%u: bad return from bfd_install_relocation: %x"
 msgstr ""
 
-#: write.c:920
+#: write.c:1166
 msgid "internal error: fixup not contained within frag"
 msgstr ""
 
-#: write.c:1026 write.c:1050
+#: write.c:1219
+msgid "reloc not within (fixed part of) section"
+msgstr ""
+
+#: write.c:1286 write.c:1307
 #, c-format
-msgid "FATAL: Can't write %s"
+msgid "can't write %s: %s"
 msgstr ""
 
-#: write.c:1082
+#: write.c:1337
 msgid "cannot write to output file"
 msgstr ""
 
-#: write.c:1223
+#: write.c:1487
 #, c-format
 msgid "%d error%s, %d warning%s, generating bad object file"
 msgstr ""
 
-#: write.c:1230
+#: write.c:1494
 #, c-format
 msgid "%d error%s, %d warning%s, no object file generated"
 msgstr ""
 
-#: write.c:1464
+#: write.c:1729
 #, c-format
 msgid "%s: global symbols not supported in common sections"
 msgstr ""
 
-#: write.c:1478
+#: write.c:1743
 #, c-format
 msgid "local label `%s' is not defined"
 msgstr ""
 
-#: write.c:1498
+#: write.c:1763
 #, c-format
 msgid "Local symbol `%s' can't be equated to common symbol `%s'"
 msgstr ""
 
-#: write.c:1768
+#: write.c:2028
 #, c-format
 msgid "alignment padding (%lu bytes) not a multiple of %ld"
 msgstr ""
 
-#: write.c:1900
+#: write.c:2186
 #, c-format
 msgid ".word %s-%s+%s didn't fit"
 msgstr ""
 
-#: write.c:1976
+#: write.c:2275
+msgid "padding added"
+msgstr ""
+
+#: write.c:2325
 msgid "attempt to move .org backwards"
 msgstr ""
 
-#: write.c:2004
+#: write.c:2353
 msgid ".space specifies non-absolute value"
 msgstr ""
 
-#: write.c:2011
+#: write.c:2368
 msgid ".space or .fill with negative value, ignored"
 msgstr ""
 
-#: write.c:2067
+#: write.c:2439
 #, c-format
 msgid ""
 "Infinite loop encountered whilst attempting to compute the addresses of "
 "symbols in section %s"
 msgstr ""
-
-#: write.c:2289
-#, c-format
-msgid "value of %s too large for field of %d bytes at %s"
-msgstr ""
-
-#: write.c:2301
-#, c-format
-msgid "signed .word overflow; switch may be too large; %ld at 0x%lx"
-msgstr ""
diff --git a/contrib/binutils/gas/read.c b/contrib/binutils/gas/read.c
index 0485d72..0098d76 100644
--- a/contrib/binutils/gas/read.c
+++ b/contrib/binutils/gas/read.c
@@ -1,6 +1,6 @@
 /* read.c - read a source file -
    Copyright 1986, 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
-   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
 This file is part of GAS, the GNU Assembler.
@@ -38,7 +38,6 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
 #include "sb.h"
 #include "macro.h"
 #include "obstack.h"
-#include "listing.h"
 #include "ecoff.h"
 #include "dw2gencfi.h"
 
@@ -214,6 +213,10 @@ static void do_align (int, char *, int, int);
 static void s_align (int, int);
 static void s_altmacro (int);
 static void s_bad_end (int);
+#ifdef OBJ_ELF
+static void s_gnu_attribute (int);
+#endif
+static void s_reloc (int);
 static int hex_float (int, char *);
 static segT get_known_segmented_expression (expressionS * expP);
 static void pobegin (void);
@@ -330,7 +333,7 @@ static const pseudo_typeS potable[] = {
 /* extend  */
   {"extern", s_ignore, 0},	/* We treat all undef as ext.  */
   {"appfile", s_app_file, 1},
-  {"appline", s_app_line, 0},
+  {"appline", s_app_line, 1},
   {"fail", s_fail, 0},
   {"file", s_app_file, 0},
   {"fill", s_fill, 0},
@@ -339,6 +342,9 @@ static const pseudo_typeS potable[] = {
   {"func", s_func, 0},
   {"global", s_globl, 0},
   {"globl", s_globl, 0},
+#ifdef OBJ_ELF
+  {"gnu_attribute", s_gnu_attribute, 0},
+#endif
   {"hword", cons, 2},
   {"if", s_if, (int) O_ne},
   {"ifb", s_ifb, 1},
@@ -365,6 +371,7 @@ static const pseudo_typeS potable[] = {
   {"irepc", s_irp, 1},
   {"lcomm", s_lcomm, 0},
   {"lflags", listing_flags, 0},	/* Listing flags.  */
+  {"linefile", s_app_line, 0},
   {"linkonce", s_linkonce, 0},
   {"list", listing_list, 1},	/* Turn listing on.  */
   {"llen", listing_psize, 1},
@@ -391,6 +398,7 @@ static const pseudo_typeS potable[] = {
   {"psize", listing_psize, 0},	/* Set paper size.  */
   {"purgem", s_purgem, 0},
   {"quad", cons, 8},
+  {"reloc", s_reloc, 0},
   {"rep", s_rept, 0},
   {"rept", s_rept, 0},
   {"rva", s_rva, 4},
@@ -605,8 +613,6 @@ read_a_source_file (char *name)
 
       last_eol = NULL;
 #endif
-      know (buffer_limit[-1] == '\n');	/* Must have a sentinel.  */
-
       while (input_line_pointer < buffer_limit)
 	{
 	  /* We have more of this buffer to parse.  */
@@ -695,19 +701,11 @@ read_a_source_file (char *name)
 
 	     Depending on what compiler is used, the order of these tests
 	     may vary to catch most common case 1st.
-	     Each test is independent of all other tests at the (top) level.
-	     PLEASE make a compiler that doesn't use this assembler.
-	     It is crufty to waste a compiler's time encoding things for this
-	     assembler, which then wastes more time decoding it.
-	     (And communicating via (linear) files is silly!
-	     If you must pass stuff, please pass a tree!)  */
-	  if ((c = *input_line_pointer++) == '\t'
-	      || c == ' '
-	      || c == '\f'
-	      || c == 0)
+	     Each test is independent of all other tests at the (top)
+	     level.  */
+	  do
 	    c = *input_line_pointer++;
-
-	  know (c != ' ');	/* No further leading whitespace.  */
+	  while (c == '\t' || c == ' ' || c == '\f');
 
 #ifndef NO_LISTING
 	  /* If listing is on, and we are expanding a macro, then give
@@ -1008,10 +1006,14 @@ read_a_source_file (char *name)
 	      unsigned int new_length;
 	      char *tmp_buf = 0;
 
-	      bump_line_counters ();
 	      s = input_line_pointer;
 	      if (strncmp (s, "APP\n", 4))
-		continue;	/* We ignore it */
+		{
+		  /* We ignore it.  */
+		  ignore_rest_of_line ();
+		  continue;
+		}
+	      bump_line_counters ();
 	      s += 4;
 
 	      sb_new (&sbuf);
@@ -1110,7 +1112,7 @@ read_a_source_file (char *name)
 	    continue;
 #endif
 	  input_line_pointer--;
-	  /* Report unknown char as ignored.  */
+	  /* Report unknown char as error.  */
 	  demand_empty_rest_of_line ();
 	}
 
@@ -1279,7 +1281,7 @@ s_align (int arg, int bytes_p)
   unsigned int align_limit = ALIGN_LIMIT;
   unsigned int align;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
   offsetT fill = 0;
   int max;
   int fill_p;
@@ -1423,7 +1425,7 @@ s_comm_internal (int param,
   offsetT temp, size;
   symbolS *symbolP = NULL;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
   expressionS exp;
 
   if (flag_mri)
@@ -1478,10 +1480,7 @@ s_comm_internal (int param,
 	  ignore_rest_of_line ();
 	  goto out;
 	}
-      /* This could be avoided when the symbol wasn't used so far, but
-	 the comment in struc-symbol.h says this flag isn't reliable.  */
-      if (1 || !symbol_used_p (symbolP))
-	symbolP = symbol_clone (symbolP, 1);
+      symbolP = symbol_clone (symbolP, 1);
       S_SET_SEGMENT (symbolP, undefined_section);
       S_SET_VALUE (symbolP, 0);
       symbol_set_frag (symbolP, &zero_address_frag);
@@ -1538,7 +1537,7 @@ s_mri_common (int small ATTRIBUTE_UNUSED)
   symbolS *sym;
   offsetT align;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (!flag_mri)
     {
@@ -1681,11 +1680,8 @@ s_app_file (int appfile)
   /* Some assemblers tolerate immediately following '"'.  */
   if ((s = demand_copy_string (&length)) != 0)
     {
-      /* If this is a fake .appfile, a fake newline was inserted into
-	 the buffer.  Passing -2 to new_logical_line tells it to
-	 account for it.  */
       int may_omit
-	= (!new_logical_line (s, appfile ? -2 : -1) && appfile);
+	= (!new_logical_line_flags (s, -1, 1) && appfile);
 
       /* In MRI mode, the preprocessor may have inserted an extraneous
 	 backquote.  */
@@ -1700,18 +1696,40 @@ s_app_file (int appfile)
     }
 }
 
+static int
+get_linefile_number (int *flag)
+{
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer < '0' || *input_line_pointer > '9')
+    return 0;
+
+  *flag = get_absolute_expression ();
+
+  return 1;
+}
+
 /* Handle the .appline pseudo-op.  This is automatically generated by
    do_scrub_chars when a preprocessor # line comment is seen.  This
    default definition may be overridden by the object or CPU specific
    pseudo-ops.  */
 
 void
-s_app_line (int ignore ATTRIBUTE_UNUSED)
+s_app_line (int appline)
 {
+  char *file = NULL;
   int l;
 
   /* The given number is that of the next line.  */
-  l = get_absolute_expression () - 1;
+  if (appline)
+    l = get_absolute_expression ();
+  else if (!get_linefile_number (&l))
+    {
+      ignore_rest_of_line ();
+      return;
+    }
+
+  l--;
 
   if (l < -1)
     /* Some of the back ends can't deal with non-positive line numbers.
@@ -1727,13 +1745,74 @@ s_app_line (int ignore ATTRIBUTE_UNUSED)
 	     l + 1);
   else
     {
-      new_logical_line ((char *) NULL, l);
+      int flags = 0;
+      int length = 0;
+
+      if (!appline)
+	{
+	  SKIP_WHITESPACE ();
+
+	  if (*input_line_pointer == '"')
+	    file = demand_copy_string (&length);
+
+	  if (file)
+	    {
+	      int this_flag;
+
+	      while (get_linefile_number (&this_flag))
+		switch (this_flag)
+		  {
+		    /* From GCC's cpp documentation:
+		       1: start of a new file.
+		       2: returning to a file after having included
+		          another file.
+		       3: following text comes from a system header file.
+		       4: following text should be treated as extern "C".
+
+		       4 is nonsensical for the assembler; 3, we don't
+		       care about, so we ignore it just in case a
+		       system header file is included while
+		       preprocessing assembly.  So 1 and 2 are all we
+		       care about, and they are mutually incompatible.
+		       new_logical_line_flags() demands this.  */
+		  case 1:
+		  case 2:
+		    if (flags && flags != (1 << this_flag))
+		      as_warn (_("incompatible flag %i in line directive"),
+			       this_flag);
+		    else
+		      flags |= 1 << this_flag;
+		    break;
+
+		  case 3:
+		  case 4:
+		    /* We ignore these.  */
+		    break;
+
+		  default:
+		    as_warn (_("unsupported flag %i in line directive"),
+			     this_flag);
+		    break;
+		  }
+
+	      if (!is_end_of_line[(unsigned char)*input_line_pointer])
+		file = 0;
+	    }
+	}
+
+      if (appline || file)
+	{
+	  new_logical_line_flags (file, l, flags);
 #ifdef LISTING
-      if (listing)
-	listing_source_line (l);
+	  if (listing)
+	    listing_source_line (l);
 #endif
+	}
     }
-  demand_empty_rest_of_line ();
+  if (appline || file)
+    demand_empty_rest_of_line ();
+  else
+    ignore_rest_of_line ();
 }
 
 /* Handle the .end pseudo-op.  Actually, the real work is done in
@@ -1807,7 +1886,7 @@ s_fail (int ignore ATTRIBUTE_UNUSED)
 {
   offsetT temp;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (flag_mri)
     stop = mri_comment_field (&stopc);
@@ -1929,7 +2008,7 @@ s_globl (int ignore ATTRIBUTE_UNUSED)
   int c;
   symbolS *symbolP;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (flag_mri)
     stop = mri_comment_field (&stopc);
@@ -1960,6 +2039,120 @@ s_globl (int ignore ATTRIBUTE_UNUSED)
     mri_comment_end (stop, stopc);
 }
 
+#ifdef OBJ_ELF
+#define skip_whitespace(str)  do { if (*(str) == ' ') ++(str); } while (0)
+
+static inline int
+skip_past_char (char ** str, char c)
+{
+  if (**str == c)
+    {
+      (*str)++;
+      return 0;
+    }
+  else
+    return -1;
+}
+#define skip_past_comma(str) skip_past_char (str, ',')
+
+/* Parse an attribute directive for VENDOR.  */
+void
+s_vendor_attribute (int vendor)
+{
+  expressionS exp;
+  int type;
+  int tag;
+  unsigned int i = 0;
+  char *s = NULL;
+  char saved_char;
+
+  expression (& exp);
+  if (exp.X_op != O_constant)
+    goto bad;
+
+  tag = exp.X_add_number;
+  type = _bfd_elf_obj_attrs_arg_type (stdoutput, vendor, tag);
+
+  if (skip_past_comma (&input_line_pointer) == -1)
+    goto bad;
+  if (type & 1)
+    {
+      expression (& exp);
+      if (exp.X_op != O_constant)
+	{
+	  as_bad (_("expected numeric constant"));
+	  ignore_rest_of_line ();
+	  return;
+	}
+      i = exp.X_add_number;
+    }
+  if (type == 3
+      && skip_past_comma (&input_line_pointer) == -1)
+    {
+      as_bad (_("expected comma"));
+      ignore_rest_of_line ();
+      return;
+    }
+  if (type & 2)
+    {
+      skip_whitespace(input_line_pointer);
+      if (*input_line_pointer != '"')
+	goto bad_string;
+      input_line_pointer++;
+      s = input_line_pointer;
+      while (*input_line_pointer && *input_line_pointer != '"')
+	input_line_pointer++;
+      if (*input_line_pointer != '"')
+	goto bad_string;
+      saved_char = *input_line_pointer;
+      *input_line_pointer = 0;
+    }
+  else
+    {
+      s = NULL;
+      saved_char = 0;
+    }
+
+  switch (type)
+    {
+    case 3:
+      bfd_elf_add_obj_attr_compat (stdoutput, vendor, i, s);
+      break;
+    case 2:
+      bfd_elf_add_obj_attr_string (stdoutput, vendor, tag, s);
+      break;
+    case 1:
+      bfd_elf_add_obj_attr_int (stdoutput, vendor, tag, i);
+      break;
+    default:
+      abort ();
+    }
+
+  if (s)
+    {
+      *input_line_pointer = saved_char;
+      input_line_pointer++;
+    }
+  demand_empty_rest_of_line ();
+  return;
+bad_string:
+  as_bad (_("bad string constant"));
+  ignore_rest_of_line ();
+  return;
+bad:
+  as_bad (_("expected <tag> , <value>"));
+  ignore_rest_of_line ();
+}
+
+/* Parse a .gnu_attribute directive.  */
+
+static void
+s_gnu_attribute (int ignored ATTRIBUTE_UNUSED)
+{
+  s_vendor_attribute (OBJ_ATTR_GNU);
+}
+#endif /* OBJ_ELF */
+
 /* Handle the MRI IRP and IRPC pseudo-ops.  */
 
 void
@@ -2812,10 +3005,7 @@ assign_symbol (char *name, int mode)
       /* If the symbol is volatile, copy the symbol and replace the
 	 original with the copy, so that previous uses of the symbol will
 	 retain the value of the symbol at the point of use.  */
-      else if (S_IS_VOLATILE (symbolP)
-	  /* This could be avoided when the symbol wasn't used so far, but
-	     the comment in struc-symbol.h says this flag isn't reliable.  */
-	  && (1 || symbol_used_p (symbolP)))
+      else if (S_IS_VOLATILE (symbolP))
 	symbolP = symbol_clone (symbolP, 1);
     }
 
@@ -2881,7 +3071,7 @@ s_space (int mult)
   expressionS val;
   char *p = 0;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
   int bytes;
 
 #ifdef md_flush_pending_output
@@ -3057,7 +3247,7 @@ s_float_space (int float_type)
   int flen;
   char temp[MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT];
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (flag_mri)
     stop = mri_comment_field (&stopc);
@@ -3134,11 +3324,17 @@ void
 s_struct (int ignore ATTRIBUTE_UNUSED)
 {
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (flag_mri)
     stop = mri_comment_field (&stopc);
   abs_section_offset = get_absolute_expression ();
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+  /* The ELF backend needs to know that we are changing sections, so
+     that .previous works correctly. */
+  if (IS_ELF)
+    obj_elf_section_change_hook ();
+#endif
   subseg_set (absolute_section, 0);
   demand_empty_rest_of_line ();
   if (flag_mri)
@@ -3186,17 +3382,14 @@ s_weakref (int ignore ATTRIBUTE_UNUSED)
 
   if (S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP))
     {
-      if(!S_IS_VOLATILE (symbolP))
+      if (!S_IS_VOLATILE (symbolP))
 	{
 	  as_bad (_("symbol `%s' is already defined"), name);
 	  *end_name = delim;
 	  ignore_rest_of_line ();
 	  return;
 	}
-      /* This could be avoided when the symbol wasn't used so far, but
-	 the comment in struc-symbol.h says this flag isn't reliable.  */
-      if (1 || !symbol_used_p (symbolP))
-	symbolP = symbol_clone (symbolP, 1);
+      symbolP = symbol_clone (symbolP, 1);
       S_CLEAR_VOLATILE (symbolP);
     }
 
@@ -3408,6 +3601,7 @@ pseudo_set (symbolS *symbolP)
       S_SET_SEGMENT (symbolP, reg_section);
       S_SET_VALUE (symbolP, (valueT) exp.X_add_number);
       set_zero_frag (symbolP);
+      symbol_get_value_expression (symbolP)->X_op = O_register;
       break;
 
     case O_symbol:
@@ -3514,7 +3708,7 @@ cons_worker (register int nbytes,	/* 1=.byte, 2=.word, 4=.long.  */
   int c;
   expressionS exp;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
 #ifdef md_flush_pending_output
   md_flush_pending_output ();
@@ -3588,6 +3782,113 @@ s_rva (int size)
   cons_worker (size, 1);
 }
 
+/* .reloc offset, reloc_name, symbol+addend.  */
+
+void
+s_reloc (int ignore ATTRIBUTE_UNUSED)
+{
+  char *stop = NULL;
+  char stopc = 0;
+  expressionS exp;
+  char *r_name;
+  int c;
+  struct reloc_list *reloc;
+
+  reloc = xmalloc (sizeof (*reloc));
+
+  if (flag_mri)
+    stop = mri_comment_field (&stopc);
+
+  expression (&exp);
+  switch (exp.X_op)
+    {
+    case O_illegal:
+    case O_absent:
+    case O_big:
+    case O_register:
+      as_bad (_("missing or bad offset expression"));
+      goto err_out;
+    case O_constant:
+      exp.X_add_symbol = section_symbol (now_seg);
+      exp.X_op = O_symbol;
+      /* Fall thru */
+    case O_symbol:
+      if (exp.X_add_number == 0)
+	{
+	  reloc->u.a.offset_sym = exp.X_add_symbol;
+	  break;
+	}
+      /* Fall thru */
+    default:
+      reloc->u.a.offset_sym = make_expr_symbol (&exp);
+      break;
+    }
+
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer != ',')
+    {
+      as_bad (_("missing reloc type"));
+      goto err_out;
+    }
+
+  ++input_line_pointer;
+  SKIP_WHITESPACE ();
+  r_name = input_line_pointer;
+  c = get_symbol_end ();
+  reloc->u.a.howto = bfd_reloc_name_lookup (stdoutput, r_name);
+  *input_line_pointer = c;
+  if (reloc->u.a.howto == NULL)
+    {
+      as_bad (_("unrecognized reloc type"));
+      goto err_out;
+    }
+
+  exp.X_op = O_absent;
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer == ',')
+    {
+      ++input_line_pointer;
+      expression_and_evaluate (&exp);
+    }
+  switch (exp.X_op)
+    {
+    case O_illegal:
+    case O_big:
+    case O_register:
+      as_bad (_("bad reloc expression"));
+    err_out:
+      ignore_rest_of_line ();
+      free (reloc);
+      if (flag_mri)
+	mri_comment_end (stop, stopc);
+      return;
+    case O_absent:
+      reloc->u.a.sym = NULL;
+      reloc->u.a.addend = 0;
+      break;
+    case O_constant:
+      reloc->u.a.sym = NULL;
+      reloc->u.a.addend = exp.X_add_number;
+      break;
+    case O_symbol:
+      reloc->u.a.sym = exp.X_add_symbol;
+      reloc->u.a.addend = exp.X_add_number;
+      break;
+    default:
+      reloc->u.a.sym = make_expr_symbol (&exp);
+      reloc->u.a.addend = 0;
+      break;
+    }
+
+  as_where (&reloc->file, &reloc->line);
+  reloc->next = reloc_list;
+  reloc_list = reloc;
+
+  demand_empty_rest_of_line ();
+  if (flag_mri)
+    mri_comment_end (stop, stopc);
+}
+
 /* Put the contents of expression EXP into the object file using
    NBYTES bytes.  If need_pass_2 is 1, this does nothing.  */
 
@@ -5010,7 +5311,7 @@ void
 equals (char *sym_name, int reassign)
 {
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   input_line_pointer++;
   if (*input_line_pointer == '=')
diff --git a/contrib/binutils/gas/read.h b/contrib/binutils/gas/read.h
index a18272d..6ac153b 100644
--- a/contrib/binutils/gas/read.h
+++ b/contrib/binutils/gas/read.h
@@ -185,4 +185,5 @@ extern void stringer (int append_zero);
 extern void s_xstab (int what);
 extern void s_rva (int);
 extern void s_incbin (int);
+extern void s_vendor_attribute (int);
 extern void s_weakref (int);
diff --git a/contrib/binutils/gas/sb.c b/contrib/binutils/gas/sb.c
index ecd772c..5fa0bc6 100644
--- a/contrib/binutils/gas/sb.c
+++ b/contrib/binutils/gas/sb.c
@@ -1,5 +1,5 @@
 /* sb.c - string buffer manipulation routines
-   Copyright 1994, 1995, 2000, 2003 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 2000, 2003, 2006 Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
       sac@cygnus.com
@@ -21,19 +21,8 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include "config.h"
-#include <stdio.h>
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#include <strings.h>
-#endif
-#include "libiberty.h"
-#include "sb.h"
 #include "as.h"
+#include "sb.h"
 
 /* These routines are about manipulating strings.
 
@@ -56,7 +45,10 @@ static void sb_check (sb *, int);
 static int string_count[sb_max_power_two];
 
 /* Free list of sb structures.  */
-static sb_list_vector free_list;
+static struct
+{
+  sb_element *size[sb_max_power_two];
+} free_list;
 
 /* Initializes an sb.  */
 
@@ -66,8 +58,7 @@ sb_build (sb *ptr, int size)
   /* See if we can find one to allocate.  */
   sb_element *e;
 
-  if (size > sb_max_power_two)
-    abort ();
+  assert (size < sb_max_power_two);
 
   e = free_list.size[size];
   if (!e)
diff --git a/contrib/binutils/gas/sb.h b/contrib/binutils/gas/sb.h
index 5732688..5a886f9 100644
--- a/contrib/binutils/gas/sb.h
+++ b/contrib/binutils/gas/sb.h
@@ -1,5 +1,5 @@
 /* sb.h - header file for string buffer manipulation routines
-   Copyright 1994, 1995, 2000, 2003 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 2000, 2003, 2006 Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
       sac@cygnus.com
@@ -25,9 +25,6 @@
 
 #define SB_H
 
-#include <stdio.h>
-#include "ansidecl.h"
-
 /* String blocks
 
    I had a couple of choices when deciding upon this data structure.
@@ -70,14 +67,6 @@ typedef struct le
 }
 sb_element;
 
-/* The free list.  */
-
-typedef struct
-{
-  sb_element *size[sb_max_power_two];
-}
-sb_list_vector;
-
 extern void sb_new (sb *);
 extern void sb_kill (sb *);
 extern void sb_add_sb (sb *, sb *);
diff --git a/contrib/binutils/gas/subsegs.c b/contrib/binutils/gas/subsegs.c
index 9401d61..0094764 100644
--- a/contrib/binutils/gas/subsegs.c
+++ b/contrib/binutils/gas/subsegs.c
@@ -1,6 +1,6 @@
 /* subsegs.c - subsegments -
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -27,20 +27,12 @@
 #include "subsegs.h"
 #include "obstack.h"
 
-frchainS *frchain_root, *frchain_now;
+frchainS *frchain_now;
 
 static struct obstack frchains;
 
-/* Gas segment information for bfd_abs_section_ptr and
-   bfd_und_section_ptr.  */
-static segment_info_type *abs_seg_info;
-static segment_info_type *und_seg_info;
-
-static void subseg_set_rest (segT, subsegT);
-
 static fragS dummy_frag;
 
-static frchainS absolute_frchain;
 
 void
 subsegs_begin (void)
@@ -50,16 +42,8 @@ subsegs_begin (void)
   obstack_alignment_mask (&frchains) = __alignof__ (frchainS) - 1;
 #endif
 
-  frchain_root = NULL;
   frchain_now = NULL;		/* Warn new_subseg() that we are booting.  */
-
   frag_now = &dummy_frag;
-
-  absolute_frchain.frch_seg = absolute_section;
-  absolute_frchain.frch_subseg = 0;
-  absolute_frchain.fix_root = absolute_frchain.fix_tail = 0;
-  absolute_frchain.frch_frag_now = &zero_address_frag;
-  absolute_frchain.frch_root = absolute_frchain.frch_last = &zero_address_frag;
 }
 
 /*
@@ -75,37 +59,25 @@ subsegs_begin (void)
 void
 subseg_change (register segT seg, register int subseg)
 {
-  segment_info_type *seginfo;
+  segment_info_type *seginfo = seg_info (seg);
   now_seg = seg;
   now_subseg = subseg;
 
-  if (now_seg == absolute_section)
-    return;
-
-  seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
   if (! seginfo)
     {
-      seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
-      memset ((PTR) seginfo, 0, sizeof (*seginfo));
-      seginfo->fix_root = NULL;
-      seginfo->fix_tail = NULL;
+      seginfo = xcalloc (1, sizeof (*seginfo));
       seginfo->bfd_section = seg;
-      seginfo->sym = 0;
-      if (seg == bfd_abs_section_ptr)
-	abs_seg_info = seginfo;
-      else if (seg == bfd_und_section_ptr)
-	und_seg_info = seginfo;
-      else
-	bfd_set_section_userdata (stdoutput, seg, (PTR) seginfo);
+      bfd_set_section_userdata (stdoutput, seg, seginfo);
     }
 }
 
 static void
 subseg_set_rest (segT seg, subsegT subseg)
 {
-  register frchainS *frcP;	/* crawl frchain chain */
-  register frchainS **lastPP;	/* address of last pointer */
+  frchainS *frcP;		/* crawl frchain chain */
+  frchainS **lastPP;		/* address of last pointer */
   frchainS *newP;		/* address of new frchain */
+  segment_info_type *seginfo;
 
   mri_common_symbol = NULL;
 
@@ -113,72 +85,26 @@ subseg_set_rest (segT seg, subsegT subseg)
     frchain_now->frch_frag_now = frag_now;
 
   assert (frchain_now == 0
-	  || now_seg == undefined_section
-	  || now_seg == absolute_section
 	  || frchain_now->frch_last == frag_now);
 
   subseg_change (seg, (int) subseg);
 
-  if (seg == absolute_section)
-    {
-      frchain_now = &absolute_frchain;
-      frag_now = &zero_address_frag;
-      return;
-    }
+  seginfo = seg_info (seg);
 
-  assert (frchain_now == 0
-	  || now_seg == undefined_section
-	  || frchain_now->frch_last == frag_now);
-
-  /*
-   * Attempt to find or make a frchain for that sub seg.
-   * Crawl along chain of frchainSs, begins @ frchain_root.
-   * If we need to make a frchainS, link it into correct
-   * position of chain rooted in frchain_root.
-   */
-  for (frcP = *(lastPP = &frchain_root);
-       frcP && frcP->frch_seg <= seg;
+  /* Attempt to find or make a frchain for that subsection.
+     We keep the list sorted by subsection number.  */
+  for (frcP = *(lastPP = &seginfo->frchainP);
+       frcP != NULL;
        frcP = *(lastPP = &frcP->frch_next))
+    if (frcP->frch_subseg >= subseg)
+      break;
+
+  if (frcP == NULL || frcP->frch_subseg != subseg)
     {
-      if (frcP->frch_seg == seg
-	  && frcP->frch_subseg >= subseg)
-	{
-	  break;
-	}
-    }
-  /*
-   * frcP:		Address of the 1st frchainS in correct segment with
-   *		frch_subseg >= subseg.
-   *		We want to either use this frchainS, or we want
-   *		to insert a new frchainS just before it.
-   *
-   *		If frcP==NULL, then we are at the end of the chain
-   *		of frchainS-s. A NULL frcP means we fell off the end
-   *		of the chain looking for a
-   *		frch_subseg >= subseg, so we
-   *		must make a new frchainS.
-   *
-   *		If we ever maintain a pointer to
-   *		the last frchainS in the chain, we change that pointer
-   *		ONLY when frcP==NULL.
-   *
-   * lastPP:	Address of the pointer with value frcP;
-   *		Never NULL.
-   *		May point to frchain_root.
-   *
-   */
-  if (!frcP
-      || (frcP->frch_seg > seg
-	  || frcP->frch_subseg > subseg))	/* Kinky logic only works with 2 segments.  */
-    {
-      /*
-       * This should be the only code that creates a frchainS.
-       */
-      segment_info_type *seginfo;
+      /* This should be the only code that creates a frchainS.  */
 
-      newP = (frchainS *) obstack_alloc (&frchains, sizeof (frchainS));
+      newP = obstack_alloc (&frchains, sizeof (frchainS));
       newP->frch_subseg = subseg;
-      newP->frch_seg = seg;
       newP->fix_root = NULL;
       newP->fix_tail = NULL;
       obstack_begin (&newP->frch_obstack, chunksize);
@@ -187,21 +113,15 @@ subseg_set_rest (segT seg, subsegT subseg)
 #endif
       newP->frch_frag_now = frag_alloc (&newP->frch_obstack);
       newP->frch_frag_now->fr_type = rs_fill;
+      newP->frch_cfi_data = NULL;
 
       newP->frch_root = newP->frch_last = newP->frch_frag_now;
 
       *lastPP = newP;
-      newP->frch_next = frcP;	/* perhaps NULL */
-
-      seginfo = seg_info (seg);
-      if (seginfo && (!seginfo->frchainP || seginfo->frchainP == frcP))
-	seginfo->frchainP = newP;
-
+      newP->frch_next = frcP;
       frcP = newP;
     }
-  /*
-   * Here with frcP pointing to the frchainS for subseg.
-   */
+
   frchain_now = frcP;
   frag_now = frcP->frch_frag_now;
 
@@ -221,7 +141,6 @@ subseg_set_rest (segT seg, subsegT subseg)
  * Out:	now_subseg, now_seg updated.
  *	Frchain_now points to the (possibly new) struct frchain for this
  *	sub-segment.
- *	Frchain_root updated if needed.
  */
 
 segT
@@ -244,32 +163,13 @@ subseg_get (const char *segname, int force_new)
   else
     secptr = bfd_make_section_anyway (stdoutput, segname);
 
-#ifdef obj_sec_set_private_data
-  obj_sec_set_private_data (stdoutput, secptr);
-#endif
-
   seginfo = seg_info (secptr);
   if (! seginfo)
     {
-      /* Check whether output_section is set first because secptr may
-	 be bfd_abs_section_ptr.  */
-      if (secptr->output_section != secptr)
-	secptr->output_section = secptr;
-      seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
-      memset ((PTR) seginfo, 0, sizeof (*seginfo));
-      seginfo->fix_root = NULL;
-      seginfo->fix_tail = NULL;
+      secptr->output_section = secptr;
+      seginfo = xcalloc (1, sizeof (*seginfo));
       seginfo->bfd_section = secptr;
-      if (secptr == bfd_abs_section_ptr)
-	abs_seg_info = seginfo;
-      else if (secptr == bfd_und_section_ptr)
-	und_seg_info = seginfo;
-      else
-	bfd_set_section_userdata (stdoutput, secptr, (PTR) seginfo);
-      seginfo->frchainP = NULL;
-      seginfo->lineno_list_head = seginfo->lineno_list_tail = NULL;
-      seginfo->sym = NULL;
-      seginfo->dot = NULL;
+      bfd_set_section_userdata (stdoutput, secptr, seginfo);
     }
   return secptr;
 }
@@ -278,13 +178,9 @@ segT
 subseg_new (const char *segname, subsegT subseg)
 {
   segT secptr;
-  segment_info_type *seginfo;
 
   secptr = subseg_get (segname, 0);
   subseg_set_rest (secptr, subseg);
-  seginfo = seg_info (secptr);
-  if (! seginfo->frchainP)
-    seginfo->frchainP = frchain_now;
   return secptr;
 }
 
@@ -294,13 +190,9 @@ segT
 subseg_force_new (const char *segname, subsegT subseg)
 {
   segT secptr;
-  segment_info_type *seginfo;
 
   secptr = subseg_get (segname, 1);
   subseg_set_rest (secptr, subseg);
-  seginfo = seg_info (secptr);
-  if (! seginfo->frchainP)
-    seginfo->frchainP = frchain_now;
   return secptr;
 }
 
@@ -316,19 +208,6 @@ subseg_set (segT secptr, subsegT subseg)
 #define obj_sec_sym_ok_for_reloc(SEC)	0
 #endif
 
-/* Get the gas information we are storing for a section.  */
-
-segment_info_type *
-seg_info (segT sec)
-{
-  if (sec == bfd_abs_section_ptr)
-    return abs_seg_info;
-  else if (sec == bfd_und_section_ptr)
-    return und_seg_info;
-  else
-    return (segment_info_type *) bfd_get_section_userdata (stdoutput, sec);
-}
-
 symbolS *
 section_symbol (segT sec)
 {
@@ -418,28 +297,33 @@ void
 subsegs_print_statistics (FILE *file)
 {
   frchainS *frchp;
+  asection *s;
+
   fprintf (file, "frag chains:\n");
-  for (frchp = frchain_root; frchp; frchp = frchp->frch_next)
+  for (s = stdoutput->sections; s; s = s->next)
     {
-      int count = 0;
-      fragS *fragp;
+      segment_info_type *seginfo;
 
-      /* If frch_subseg is non-zero, it's probably been chained onto
-	 the end of a previous subsection.  Don't count it again.  */
-      if (frchp->frch_subseg != 0)
+      /* Skip gas-internal sections.  */
+      if (segment_name (s)[0] == '*')
 	continue;
 
-      /* Skip gas-internal sections.  */
-      if (segment_name (frchp->frch_seg)[0] == '*')
+      seginfo = seg_info (s);
+      if (!seginfo)
 	continue;
 
-      for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
+      for (frchp = seginfo->frchainP; frchp; frchp = frchp->frch_next)
 	{
-	  count++;
+	  int count = 0;
+	  fragS *fragp;
+
+	  for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
+	    count++;
+
+	  fprintf (file, "\n");
+	  fprintf (file, "\t%p %-10s\t%10d frags\n", (void *) frchp,
+		   segment_name (s), count);
 	}
-      fprintf (file, "\n");
-      fprintf (file, "\t%p %-10s\t%10d frags\n", (void *) frchp,
-	       segment_name (frchp->frch_seg), count);
     }
 }
 
diff --git a/contrib/binutils/gas/subsegs.h b/contrib/binutils/gas/subsegs.h
index 23ab4f9..54a5a6a 100644
--- a/contrib/binutils/gas/subsegs.h
+++ b/contrib/binutils/gas/subsegs.h
@@ -1,6 +1,6 @@
 /* subsegs.h -> subsegs.c
-   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2003, 2005
-   Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2003, 2005,
+   2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -40,24 +40,23 @@
 
 #include "obstack.h"
 
+struct frch_cfi_data;
+
 struct frchain			/* control building of a frag chain */
 {				/* FRCH = FRagment CHain control */
   struct frag *frch_root;	/* 1st struct frag in chain, or NULL */
   struct frag *frch_last;	/* last struct frag in chain, or NULL */
   struct frchain *frch_next;	/* next in chain of struct frchain-s */
-  segT frch_seg;		/* SEG_TEXT or SEG_DATA.  */
   subsegT frch_subseg;		/* subsegment number of this chain */
   fixS *fix_root;		/* Root of fixups for this subsegment.  */
   fixS *fix_tail;		/* Last fixup for this subsegment.  */
   struct obstack frch_obstack;	/* for objects in this frag chain */
   fragS *frch_frag_now;		/* frag_now for this subsegment */
+  struct frch_cfi_data *frch_cfi_data;
 };
 
 typedef struct frchain frchainS;
 
-/* All subsegments' chains hang off here.  NULL means no frchains yet.  */
-extern frchainS *frchain_root;
-
 /* Frchain we are assembling into now.  That is, the current segment's
    frag chain, even if it contains no (complete) frags.  */
 extern frchainS *frchain_now;
@@ -109,7 +108,10 @@ typedef struct segment_info_struct {
 #endif
 } segment_info_type;
 
-extern segment_info_type *seg_info (segT);
+
+#define seg_info(sec) \
+  ((segment_info_type *) bfd_get_section_userdata (stdoutput, sec))
+
 extern symbolS *section_symbol (segT);
 
 extern void subsegs_print_statistics (FILE *);
diff --git a/contrib/binutils/gas/symbols.c b/contrib/binutils/gas/symbols.c
index 5935a74..816395f 100644
--- a/contrib/binutils/gas/symbols.c
+++ b/contrib/binutils/gas/symbols.c
@@ -1,6 +1,6 @@
 /* symbols.c -symbol table-
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -144,8 +144,7 @@ symbol_create (const char *name, /* It is copied, the caller can destroy/modify.
 
   symbolP->bsym = bfd_make_empty_symbol (stdoutput);
   if (symbolP->bsym == NULL)
-    as_perror ("%s", "bfd_make_empty_symbol");
-  symbolP->bsym->udata.p = (PTR) symbolP;
+    as_fatal ("bfd_make_empty_symbol: %s", bfd_errmsg (bfd_get_error ()));
   S_SET_NAME (symbolP, preserved_copy_of_name);
 
   S_SET_SEGMENT (symbolP, segment);
@@ -336,10 +335,7 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
 	       || S_IS_COMMON (symbolP)
 	       || S_IS_VOLATILE (symbolP))
 	{
-	  if (S_IS_VOLATILE (symbolP)
-	      /* This could be avoided when the symbol wasn't used so far, but
-		 the comment in struc-symbol.h says this flag isn't reliable.  */
-	      && (1 || !symbol_used_p (symbolP)))
+	  if (S_IS_VOLATILE (symbolP))
 	    {
 	      symbolP = symbol_clone (symbolP, 1);
 	      S_SET_VALUE (symbolP, 0);
@@ -567,18 +563,15 @@ symbol_clone (symbolS *orgsymP, int replace)
     orgsymP = local_symbol_convert ((struct local_symbol *) orgsymP);
   bsymorg = orgsymP->bsym;
 
-  know (S_IS_DEFINED (orgsymP));
-
   newsymP = obstack_alloc (&notes, sizeof (*newsymP));
   *newsymP = *orgsymP;
   bsymnew = bfd_make_empty_symbol (bfd_asymbol_bfd (bsymorg));
   if (bsymnew == NULL)
-    as_perror ("%s", "bfd_make_empty_symbol");
+    as_fatal ("bfd_make_empty_symbol: %s", bfd_errmsg (bfd_get_error ()));
   newsymP->bsym = bsymnew;
   bsymnew->name = bsymorg->name;
   bsymnew->flags =  bsymorg->flags;
   bsymnew->section =  bsymorg->section;
-  bsymnew->udata.p = (PTR) newsymP;
   bfd_copy_private_symbol_data (bfd_asymbol_bfd (bsymorg), bsymorg,
 				bfd_asymbol_bfd (bsymnew), bsymnew);
 
@@ -603,11 +596,13 @@ symbol_clone (symbolS *orgsymP, int replace)
 	symbol_lastP = newsymP;
       else if (orgsymP->sy_next)
 	orgsymP->sy_next->sy_previous = newsymP;
-      orgsymP->sy_next = NULL;
+      orgsymP->sy_previous = orgsymP->sy_next = orgsymP;
       debug_verify_symchain (symbol_rootP, symbol_lastP);
 
       symbol_table_insert (newsymP);
     }
+  else
+    newsymP->sy_previous = newsymP->sy_next = newsymP;
 
   return newsymP;
 }
@@ -884,6 +879,69 @@ verify_symbol_chain (symbolS *rootP, symbolS *lastP)
   assert (lastP == symbolP);
 }
 
+#ifdef OBJ_COMPLEX_RELC
+
+static int
+use_complex_relocs_for (symbolS * symp)
+{
+  switch (symp->sy_value.X_op)
+    {
+    case O_constant:
+      return 0;
+
+    case O_symbol:
+    case O_symbol_rva:
+    case O_uminus:
+    case O_bit_not:
+    case O_logical_not:
+      if (  (S_IS_COMMON (symp->sy_value.X_add_symbol)
+	   || S_IS_LOCAL (symp->sy_value.X_add_symbol))
+	  &&
+	      (S_IS_DEFINED (symp->sy_value.X_add_symbol)
+	   && S_GET_SEGMENT (symp->sy_value.X_add_symbol) != expr_section))
+	return 0;
+      break;
+
+    case O_multiply:
+    case O_divide:
+    case O_modulus:
+    case O_left_shift:
+    case O_right_shift:
+    case O_bit_inclusive_or:
+    case O_bit_or_not:
+    case O_bit_exclusive_or:
+    case O_bit_and:
+    case O_add:
+    case O_subtract:
+    case O_eq:
+    case O_ne:
+    case O_lt:
+    case O_le:
+    case O_ge:
+    case O_gt:
+    case O_logical_and:
+    case O_logical_or:
+
+      if (  (S_IS_COMMON (symp->sy_value.X_add_symbol)
+	   || S_IS_LOCAL (symp->sy_value.X_add_symbol))
+	  && 
+	    (S_IS_COMMON (symp->sy_value.X_op_symbol)
+	   || S_IS_LOCAL (symp->sy_value.X_op_symbol))
+
+	  && S_IS_DEFINED (symp->sy_value.X_add_symbol)
+	  && S_IS_DEFINED (symp->sy_value.X_op_symbol)
+	  && S_GET_SEGMENT (symp->sy_value.X_add_symbol) != expr_section
+	  && S_GET_SEGMENT (symp->sy_value.X_op_symbol) != expr_section)
+	return 0;
+      break;
+      
+    default:
+      break;
+    }
+  return 1;
+}
+#endif
+
 static void
 report_op_error (symbolS *symp, symbolS *left, symbolS *right)
 {
@@ -986,6 +1044,53 @@ resolve_symbol_value (symbolS *symp)
       final_val = 0;
       resolved = 1;
     }
+#ifdef OBJ_COMPLEX_RELC
+  else if (final_seg == expr_section
+	   && use_complex_relocs_for (symp))
+    {
+      symbolS * relc_symbol = NULL;
+      char * relc_symbol_name = NULL;
+
+      relc_symbol_name = symbol_relc_make_expr (& symp->sy_value);
+
+      /* For debugging, print out conversion input & output.  */
+#ifdef DEBUG_SYMS
+      print_expr (& symp->sy_value);
+      if (relc_symbol_name)
+	fprintf (stderr, "-> relc symbol: %s\n", relc_symbol_name);
+#endif
+
+      if (relc_symbol_name != NULL)
+	relc_symbol = symbol_new (relc_symbol_name, undefined_section,
+				  0, & zero_address_frag);
+
+      if (relc_symbol == NULL)
+	{
+	  as_bad (_("cannot convert expression symbol %s to complex relocation"),
+		  S_GET_NAME (symp));
+	  resolved = 0;
+	}
+      else
+	{
+	  symbol_table_insert (relc_symbol);
+
+ 	  /* S_CLEAR_EXTERNAL (relc_symbol); */
+	  if (symp->bsym->flags & BSF_SRELC)
+	    relc_symbol->bsym->flags |= BSF_SRELC;
+	  else
+	    relc_symbol->bsym->flags |= BSF_RELC;	  
+	  /* symp->bsym->flags |= BSF_RELC; */
+	  copy_symbol_attributes (symp, relc_symbol);
+	  symp->sy_value.X_op = O_symbol;
+	  symp->sy_value.X_add_symbol = relc_symbol;
+	  symp->sy_value.X_add_number = 0;
+	  resolved = 1;
+	}
+
+      final_seg = undefined_section;
+      goto exit_dont_set_value;
+    }
+#endif
   else
     {
       symbolS *add_symbol, *op_symbol;
@@ -1016,6 +1121,9 @@ resolve_symbol_value (symbolS *symp)
 	  final_val += symp->sy_frag->fr_address / OCTETS_PER_BYTE;
 	  if (final_seg == expr_section)
 	    final_seg = absolute_section;
+	  /* Fall through.  */
+
+	case O_register:
 	  resolved = 1;
 	  break;
 
@@ -1083,8 +1191,9 @@ resolve_symbol_value (symbolS *symp)
 	      symp->sy_resolving = 0;
 	      goto exit_dont_set_value;
 	    }
-	  else if (finalize_syms && final_seg == expr_section
-		   && seg_left != expr_section)
+	  else if (finalize_syms
+		   && ((final_seg == expr_section && seg_left != expr_section)
+		       || symbol_shadow_p (symp)))
 	    {
 	      /* If the symbol is an expression symbol, do similarly
 		 as for undefined and common syms above.  Handles
@@ -1292,7 +1401,6 @@ resolve_symbol_value (symbolS *symp)
 		      && symbol_resolved_p (op_symbol));
 	  break;
 
-	case O_register:
 	case O_big:
 	case O_illegal:
 	  /* Give an error (below) if not in expr_section.  We don't
@@ -1839,6 +1947,10 @@ copy_symbol_attributes (symbolS *dest, symbolS *src)
 #ifdef OBJ_COPY_SYMBOL_ATTRIBUTES
   OBJ_COPY_SYMBOL_ATTRIBUTES (dest, src);
 #endif
+
+#ifdef TC_COPY_SYMBOL_ATTRIBUTES
+  TC_COPY_SYMBOL_ATTRIBUTES (dest, src);
+#endif
 }
 
 int
@@ -2497,6 +2609,17 @@ symbol_constant_p (symbolS *s)
   return s->sy_value.X_op == O_constant;
 }
 
+/* Return whether a symbol was cloned and thus removed from the global
+   symbol list.  */
+
+int
+symbol_shadow_p (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    return 0;
+  return s->sy_next == s;
+}
+
 /* Return the BFD symbol for a symbol.  */
 
 asymbol *
@@ -2818,3 +2941,219 @@ symbol_print_statistics (FILE *file)
   fprintf (file, "%lu mini local symbols created, %lu converted\n",
 	   local_symbol_count, local_symbol_conversion_count);
 }
+
+#ifdef OBJ_COMPLEX_RELC
+
+/* Convert given symbol to a new complex-relocation symbol name.  This
+   may be a recursive function, since it might be called for non-leaf
+   nodes (plain symbols) in the expression tree.  The caller owns the
+   returning string, so should free it eventually.  Errors are
+   indicated via as_bad and a NULL return value.  The given symbol
+   is marked with sy_used_in_reloc.  */
+
+char *
+symbol_relc_make_sym (symbolS * sym)
+{
+  char * terminal = NULL;
+  const char * sname;
+  char typetag;
+  int sname_len;
+
+  assert (sym != NULL);
+
+  /* Recurse to symbol_relc_make_expr if this symbol
+     is defined as an expression or a plain value.  */
+  if (   S_GET_SEGMENT (sym) == expr_section
+      || S_GET_SEGMENT (sym) == absolute_section)
+    return symbol_relc_make_expr (& sym->sy_value);
+
+  /* This may be a "fake symbol" L0\001, referring to ".".
+     Write out a special null symbol to refer to this position.  */
+  if (! strcmp (S_GET_NAME (sym), FAKE_LABEL_NAME))
+    return xstrdup (".");
+
+  /* We hope this is a plain leaf symbol.  Construct the encoding
+     as {S,s}II...:CCCCCCC....
+     where 'S'/'s' means section symbol / plain symbol
+     III is decimal for the symbol name length
+     CCC is the symbol name itself.  */
+  symbol_mark_used_in_reloc (sym);
+
+  sname = S_GET_NAME (sym);
+  sname_len = strlen (sname);
+  typetag = symbol_section_p (sym) ? 'S' : 's';
+
+  terminal = xmalloc (1 /* S or s */
+		      + 8 /* sname_len in decimal */
+		      + 1 /* _ spacer */
+		      + sname_len /* name itself */
+		      + 1 /* \0 */ );
+
+  sprintf (terminal, "%c%d:%s", typetag, sname_len, sname);
+  return terminal;
+}
+
+/* Convert given value to a new complex-relocation symbol name.  This
+   is a non-recursive function, since it is be called for leaf nodes
+   (plain values) in the expression tree.  The caller owns the
+   returning string, so should free() it eventually.  No errors.  */
+
+char *
+symbol_relc_make_value (offsetT val)
+{
+  char * terminal = xmalloc (28);  /* Enough for long long.  */
+
+  terminal[0] = '#';
+  sprintf_vma (& terminal[1], val);
+  return terminal;
+}
+
+/* Convert given expression to a new complex-relocation symbol name.
+   This is a recursive function, since it traverses the entire given
+   expression tree.  The caller owns the returning string, so should
+   free() it eventually.  Errors are indicated via as_bad() and a NULL
+   return value.  */
+
+char *
+symbol_relc_make_expr (expressionS * exp)
+{
+  char * opstr = NULL; /* Operator prefix string.  */
+  int    arity = 0;    /* Arity of this operator.  */
+  char * operands[3];  /* Up to three operands.  */
+  char * concat_string = NULL;
+
+  operands[0] = operands[1] = operands[2] = NULL;
+
+  assert (exp != NULL);
+
+  /* Match known operators -> fill in opstr, arity, operands[] and fall
+     through to construct subexpression fragments; may instead return 
+     string directly for leaf nodes.  */
+
+  /* See expr.h for the meaning of all these enums.  Many operators 
+     have an unnatural arity (X_add_number implicitly added).  The
+     conversion logic expands them to explicit "+" subexpressions.   */
+
+  switch (exp->X_op)
+    {
+    default:
+      as_bad ("Unknown expression operator (enum %d)", exp->X_op);
+      break;
+
+      /* Leaf nodes.  */
+    case O_constant:
+      return symbol_relc_make_value (exp->X_add_number);
+
+    case O_symbol:
+      if (exp->X_add_number) 
+	{ 
+	  arity = 2; 
+	  opstr = "+"; 
+	  operands[0] = symbol_relc_make_sym (exp->X_add_symbol);
+	  operands[1] = symbol_relc_make_value (exp->X_add_number);
+	  break;
+	}
+      else
+	return symbol_relc_make_sym (exp->X_add_symbol);
+
+      /* Helper macros for nesting nodes.  */
+
+#define HANDLE_XADD_OPT1(str_) 						\
+      if (exp->X_add_number)						\
+        {								\
+          arity = 2;							\
+          opstr = "+:" str_;						\
+          operands[0] = symbol_relc_make_sym (exp->X_add_symbol);	\
+          operands[1] = symbol_relc_make_value (exp->X_add_number);	\
+          break;							\
+        }								\
+      else								\
+        {								\
+          arity = 1;							\
+          opstr = str_;							\
+          operands[0] = symbol_relc_make_sym (exp->X_add_symbol);	\
+        }								\
+      break
+      
+#define HANDLE_XADD_OPT2(str_) 						\
+      if (exp->X_add_number)						\
+        {								\
+          arity = 3;							\
+          opstr = "+:" str_;						\
+          operands[0] = symbol_relc_make_sym (exp->X_add_symbol);	\
+          operands[1] = symbol_relc_make_sym (exp->X_op_symbol);	\
+          operands[2] = symbol_relc_make_value (exp->X_add_number);	\
+        }								\
+      else								\
+        {								\
+          arity = 2;							\
+          opstr = str_;							\
+          operands[0] = symbol_relc_make_sym (exp->X_add_symbol);	\
+          operands[1] = symbol_relc_make_sym (exp->X_op_symbol);	\
+        } 								\
+      break
+
+      /* Nesting nodes.  */
+
+    case O_uminus:       	HANDLE_XADD_OPT1 ("0-");
+    case O_bit_not:      	HANDLE_XADD_OPT1 ("~");
+    case O_logical_not:  	HANDLE_XADD_OPT1 ("!");
+    case O_multiply:     	HANDLE_XADD_OPT2 ("*");
+    case O_divide:       	HANDLE_XADD_OPT2 ("/");
+    case O_modulus:      	HANDLE_XADD_OPT2 ("%");
+    case O_left_shift:   	HANDLE_XADD_OPT2 ("<<");
+    case O_right_shift:  	HANDLE_XADD_OPT2 (">>");
+    case O_bit_inclusive_or:	HANDLE_XADD_OPT2 ("|");
+    case O_bit_exclusive_or:	HANDLE_XADD_OPT2 ("^");
+    case O_bit_and:      	HANDLE_XADD_OPT2 ("&");
+    case O_add:          	HANDLE_XADD_OPT2 ("+");
+    case O_subtract:     	HANDLE_XADD_OPT2 ("-");
+    case O_eq:           	HANDLE_XADD_OPT2 ("==");
+    case O_ne:           	HANDLE_XADD_OPT2 ("!=");
+    case O_lt:           	HANDLE_XADD_OPT2 ("<");
+    case O_le:           	HANDLE_XADD_OPT2 ("<=");
+    case O_ge:           	HANDLE_XADD_OPT2 (">=");
+    case O_gt:           	HANDLE_XADD_OPT2 (">");
+    case O_logical_and:  	HANDLE_XADD_OPT2 ("&&");
+    case O_logical_or:   	HANDLE_XADD_OPT2 ("||");
+    }
+
+  /* Validate & reject early.  */
+  if (arity >= 1 && ((operands[0] == NULL) || (strlen (operands[0]) == 0)))
+    opstr = NULL;
+  if (arity >= 2 && ((operands[1] == NULL) || (strlen (operands[1]) == 0)))
+    opstr = NULL;
+  if (arity >= 3 && ((operands[2] == NULL) || (strlen (operands[2]) == 0)))
+    opstr = NULL;
+
+  if (opstr == NULL)
+    concat_string = NULL;
+  else
+    {
+      /* Allocate new string; include inter-operand padding gaps etc.  */
+      concat_string = xmalloc (strlen (opstr) 
+			       + 1
+			       + (arity >= 1 ? (strlen (operands[0]) + 1 ) : 0)
+			       + (arity >= 2 ? (strlen (operands[1]) + 1 ) : 0)
+			       + (arity >= 3 ? (strlen (operands[2]) + 0 ) : 0)
+			       + 1);
+      assert (concat_string != NULL);
+      
+      /* Format the thing.  */
+      sprintf (concat_string, 
+	       (arity == 0 ? "%s" :
+		arity == 1 ? "%s:%s" :
+		arity == 2 ? "%s:%s:%s" :
+		/* arity == 3 */ "%s:%s:%s:%s"),
+	       opstr, operands[0], operands[1], operands[2]);
+    }
+
+  /* Free operand strings (not opstr).  */
+  if (arity >= 1) xfree (operands[0]);
+  if (arity >= 2) xfree (operands[1]);
+  if (arity >= 3) xfree (operands[2]);
+
+  return concat_string;
+}
+
+#endif
diff --git a/contrib/binutils/gas/symbols.h b/contrib/binutils/gas/symbols.h
index 7a4b8f7..483f8ee 100644
--- a/contrib/binutils/gas/symbols.h
+++ b/contrib/binutils/gas/symbols.h
@@ -35,6 +35,9 @@ extern int symbol_table_frozen;
    default.  */
 extern int symbols_case_sensitive;
 
+char * symbol_relc_make_expr  (expressionS *);
+char * symbol_relc_make_sym   (symbolS *);
+char * symbol_relc_make_value (offsetT);
 char *decode_local_label_name (char *s);
 symbolS *symbol_find (const char *name);
 symbolS *symbol_find_noref (const char *name, int noref);
@@ -192,6 +195,7 @@ extern int symbol_section_p (symbolS *);
 extern int symbol_equated_p (symbolS *);
 extern int symbol_equated_reloc_p (symbolS *);
 extern int symbol_constant_p (symbolS *);
+extern int symbol_shadow_p (symbolS *);
 extern asymbol *symbol_get_bfdsym (symbolS *);
 extern void symbol_set_bfdsym (symbolS *, asymbol *);
 
diff --git a/contrib/binutils/gas/write.c b/contrib/binutils/gas/write.c
index 9186717..29ea284 100644
--- a/contrib/binutils/gas/write.c
+++ b/contrib/binutils/gas/write.c
@@ -1,6 +1,6 @@
 /* write.c - emit .o file
    Copyright 1986, 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
-   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -27,6 +27,7 @@
 #include "obstack.h"
 #include "output-file.h"
 #include "dwarf2dbg.h"
+#include "libbfd.h"
 
 #ifndef TC_ADJUST_RELOC_COUNT
 #define TC_ADJUST_RELOC_COUNT(FIX, COUNT)
@@ -45,7 +46,6 @@
 #ifndef TC_FORCE_RELOCATION_LOCAL
 #define TC_FORCE_RELOCATION_LOCAL(FIX)		\
   (!(FIX)->fx_pcrel				\
-   || (FIX)->fx_plt				\
    || TC_FORCE_RELOCATION (FIX))
 #endif
 
@@ -97,6 +97,16 @@
 #define TC_FAKE_LABEL(NAME) (strcmp ((NAME), FAKE_LABEL_NAME) == 0)
 #endif
 
+/* Positive values of TC_FX_SIZE_SLACK allow a target to define
+   fixups that far past the end of a frag.  Having such fixups
+   is of course most most likely a bug in setting fx_size correctly.
+   A negative value disables the fixup check entirely, which is
+   appropriate for something like the Renesas / SuperH SH_COUNT
+   reloc.  */
+#ifndef TC_FX_SIZE_SLACK
+#define TC_FX_SIZE_SLACK(FIX) 0
+#endif
+
 /* Used to control final evaluation of expressions.  */
 int finalize_syms = 0;
 
@@ -107,9 +117,10 @@ symbolS *abs_section_sym;
 /* Remember the value of dot when parsing expressions.  */
 addressT dot_value;
 
-void print_fixup (fixS *);
+/* Relocs generated by ".reloc" pseudo.  */
+struct reloc_list* reloc_list;
 
-static void renumber_sections (bfd *, asection *, PTR);
+void print_fixup (fixS *);
 
 /* We generally attach relocs to frag chains.  However, after we have
    chained these all together into a segment, any relocs we add after
@@ -121,22 +132,6 @@ static int n_fixups;
 
 #define RELOC_ENUM enum bfd_reloc_code_real
 
-static fixS *fix_new_internal (fragS *, int where, int size,
-			       symbolS *add, symbolS *sub,
-			       offsetT offset, int pcrel,
-			       RELOC_ENUM r_type);
-static long fixup_segment (fixS *, segT);
-static relax_addressT relax_align (relax_addressT addr, int align);
-static fragS *chain_frchains_together_1 (segT, struct frchain *);
-static void chain_frchains_together (bfd *, segT, PTR);
-static void cvt_frag_to_fill (segT, fragS *);
-static void adjust_reloc_syms (bfd *, asection *, PTR);
-static void fix_segment (bfd *, asection *, PTR);
-static void write_relocs (bfd *, asection *, PTR);
-static void write_contents (bfd *, asection *, PTR);
-static void set_symtab (void);
-static void merge_data_into_text (void);
-
 /* Create a fixS in obstack 'notes'.  */
 
 static fixS *
@@ -153,7 +148,7 @@ fix_new_internal (fragS *frag,		/* Which frag?  */
 
   n_fixups++;
 
-  fixP = (fixS *) obstack_alloc (&notes, sizeof (fixS));
+  fixP = obstack_alloc (&notes, sizeof (fixS));
 
   fixP->fx_frag = frag;
   fixP->fx_where = where;
@@ -169,13 +164,13 @@ fix_new_internal (fragS *frag,		/* Which frag?  */
   fixP->fx_offset = offset;
   fixP->fx_dot_value = dot_value;
   fixP->fx_pcrel = pcrel;
-  fixP->fx_plt = 0;
   fixP->fx_r_type = r_type;
   fixP->fx_im_disp = 0;
   fixP->fx_pcrel_adjust = 0;
   fixP->fx_bit_fixP = 0;
   fixP->fx_addnumber = 0;
   fixP->fx_tcbit = 0;
+  fixP->fx_tcbit2 = 0;
   fixP->fx_done = 0;
   fixP->fx_no_overflow = 0;
   fixP->fx_signed = 0;
@@ -365,7 +360,7 @@ get_recorded_alignment (segT seg)
 /* Reset the section indices after removing the gas created sections.  */
 
 static void
-renumber_sections (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, PTR countparg)
+renumber_sections (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *countparg)
 {
   int *countp = (int *) countparg;
 
@@ -379,7 +374,7 @@ chain_frchains_together_1 (segT section, struct frchain *frchp)
   fragS dummy, *prev_frag = &dummy;
   fixS fix_dummy, *prev_fix = &fix_dummy;
 
-  for (; frchp && frchp->frch_seg == section; frchp = frchp->frch_next)
+  for (; frchp; frchp = frchp->frch_next)
     {
       prev_frag->fr_next = frchp->frch_root;
       prev_frag = frchp->frch_last;
@@ -394,6 +389,7 @@ chain_frchains_together_1 (segT section, struct frchain *frchp)
 	}
     }
   assert (prev_frag->fr_type != 0);
+  assert (prev_frag != &dummy);
   prev_frag->fr_next = 0;
   return prev_frag;
 }
@@ -401,7 +397,7 @@ chain_frchains_together_1 (segT section, struct frchain *frchp)
 static void
 chain_frchains_together (bfd *abfd ATTRIBUTE_UNUSED,
 			 segT section,
-			 PTR xxx ATTRIBUTE_UNUSED)
+			 void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *info;
 
@@ -529,10 +525,8 @@ relax_seg (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *xxx)
     info->changed = 1;
 }
 
-static void size_seg (bfd *, asection *, PTR);
-
 static void
-size_seg (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
+size_seg (bfd *abfd, asection *sec, void *xxx ATTRIBUTE_UNUSED)
 {
   flagword flags;
   fragS *fragp;
@@ -562,11 +556,7 @@ size_seg (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
   if (size > 0 && ! seginfo->bss)
     flags |= SEC_HAS_CONTENTS;
 
-  /* @@ This is just an approximation.  */
-  if (seginfo && seginfo->fix_root)
-    flags |= SEC_RELOC;
-  else
-    flags &= ~SEC_RELOC;
+  flags &= ~SEC_RELOC;
   x = bfd_set_section_flags (abfd, sec, flags);
   assert (x);
 
@@ -637,13 +627,93 @@ dump_section_relocs (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, FILE *stream)
 #define EMIT_SECTION_SYMBOLS 1
 #endif
 
+/* Resolve U.A.OFFSET_SYM and U.A.SYM fields of RELOC_LIST entries,
+   and check for validity.  Convert RELOC_LIST from using U.A fields
+   to U.B fields.  */
+static void
+resolve_reloc_expr_symbols (void)
+{
+  struct reloc_list *r;
+
+  for (r = reloc_list; r; r = r->next)
+    {
+      expressionS *symval;
+      symbolS *sym;
+      bfd_vma offset, addend;
+      asection *sec;
+      reloc_howto_type *howto;
+
+      resolve_symbol_value (r->u.a.offset_sym);
+      symval = symbol_get_value_expression (r->u.a.offset_sym);
+
+      offset = 0;
+      sym = NULL;
+      if (symval->X_op == O_constant)
+	sym = r->u.a.offset_sym;
+      else if (symval->X_op == O_symbol)
+	{
+	  sym = symval->X_add_symbol;
+	  offset = symval->X_add_number;
+	  symval = symbol_get_value_expression (symval->X_add_symbol);
+	}
+      if (sym == NULL
+	  || symval->X_op != O_constant
+	  || (sec = S_GET_SEGMENT (sym)) == NULL
+	  || !SEG_NORMAL (sec))
+	{
+	  as_bad_where (r->file, r->line, _("invalid offset expression"));
+	  sec = NULL;
+	}
+      else
+	offset += S_GET_VALUE (sym);
+
+      sym = NULL;
+      addend = r->u.a.addend;
+      if (r->u.a.sym != NULL)
+	{
+	  resolve_symbol_value (r->u.a.sym);
+	  symval = symbol_get_value_expression (r->u.a.sym);
+	  if (symval->X_op == O_constant)
+	    sym = r->u.a.sym;
+	  else if (symval->X_op == O_symbol)
+	    {
+	      sym = symval->X_add_symbol;
+	      addend += symval->X_add_number;
+	      symval = symbol_get_value_expression (symval->X_add_symbol);
+	    }
+	  if (symval->X_op != O_constant)
+	    {
+	      as_bad_where (r->file, r->line, _("invalid reloc expression"));
+	      sec = NULL;
+	    }
+	  else if (sym != NULL)
+	    symbol_mark_used_in_reloc (sym);
+	}
+      if (sym == NULL)
+	{
+	  if (abs_section_sym == NULL)
+	    abs_section_sym = section_symbol (absolute_section);
+	  sym = abs_section_sym;
+	}
+
+      howto = r->u.a.howto;
+
+      r->u.b.sec = sec;
+      r->u.b.s = symbol_get_bfdsym (sym);
+      r->u.b.r.sym_ptr_ptr = &r->u.b.s;
+      r->u.b.r.address = offset;
+      r->u.b.r.addend = addend;
+      r->u.b.r.howto = howto;
+    }
+}
+
 /* This pass over fixups decides whether symbols can be replaced with
    section symbols.  */
 
 static void
 adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
 		   asection *sec,
-		   PTR xxx ATTRIBUTE_UNUSED)
+		   void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *seginfo = seg_info (sec);
   fixS *fixp;
@@ -680,17 +750,21 @@ adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
 
 	/* If this symbol is equated to an undefined or common symbol,
 	   convert the fixup to being against that symbol.  */
-	if (symbol_equated_reloc_p (sym)
-	    || S_IS_WEAKREFR (sym))
+	while (symbol_equated_reloc_p (sym)
+	       || S_IS_WEAKREFR (sym))
 	  {
+	    symbolS *newsym = symbol_get_value_expression (sym)->X_add_symbol;
+	    if (sym == newsym)
+	      break;
 	    fixp->fx_offset += symbol_get_value_expression (sym)->X_add_number;
-	    sym = symbol_get_value_expression (sym)->X_add_symbol;
-	    fixp->fx_addsy = sym;
+	    fixp->fx_addsy = newsym;
+	    sym = newsym;
 	  }
 
 	if (symbol_mri_common_p (sym))
 	  {
-	    /* These symbols are handled specially in fixup_segment.  */
+	    fixp->fx_offset += S_GET_VALUE (sym);
+	    fixp->fx_addsy = symbol_get_value_expression (sym)->X_add_symbol;
 	    continue;
 	  }
 
@@ -719,14 +793,14 @@ adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
 	if (bfd_is_abs_section (symsec))
 	  {
 	    /* The fixup_segment routine normally will not use this
-               symbol in a relocation.  */
+	       symbol in a relocation.  */
 	    continue;
 	  }
 
 	/* Don't try to reduce relocs which refer to non-local symbols
-           in .linkonce sections.  It can lead to confusion when a
-           debugging section refers to a .linkonce section.  I hope
-           this will always be correct.  */
+	   in .linkonce sections.  It can lead to confusion when a
+	   debugging section refers to a .linkonce section.  I hope
+	   this will always be correct.  */
 	if (symsec != sec && ! S_IS_LOCAL (sym))
 	  {
 	    if ((symsec->flags & SEC_LINK_ONCE) != 0
@@ -763,10 +837,241 @@ adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
   dump_section_relocs (abfd, sec, stderr);
 }
 
+/* fixup_segment()
+
+   Go through all the fixS's in a segment and see which ones can be
+   handled now.  (These consist of fixS where we have since discovered
+   the value of a symbol, or the address of the frag involved.)
+   For each one, call md_apply_fix to put the fix into the frag data.
+
+   Result is a count of how many relocation structs will be needed to
+   handle the remaining fixS's that we couldn't completely handle here.
+   These will be output later by emit_relocations().  */
+
+static long
+fixup_segment (fixS *fixP, segT this_segment)
+{
+  long seg_reloc_count = 0;
+  valueT add_number;
+  fragS *fragP;
+  segT add_symbol_segment = absolute_section;
+
+  if (fixP != NULL && abs_section_sym == NULL)
+    abs_section_sym = section_symbol (absolute_section);
+
+  /* If the linker is doing the relaxing, we must not do any fixups.
+
+     Well, strictly speaking that's not true -- we could do any that
+     are PC-relative and don't cross regions that could change size.
+     And for the i960 we might be able to turn callx/callj into bal
+     anyways in cases where we know the maximum displacement.  */
+  if (linkrelax && TC_LINKRELAX_FIXUP (this_segment))
+    {
+      for (; fixP; fixP = fixP->fx_next)
+	if (!fixP->fx_done)
+	  {
+	    if (fixP->fx_addsy == NULL)
+	      {
+		/* There was no symbol required by this relocation.
+		   However, BFD doesn't really handle relocations
+		   without symbols well. So fake up a local symbol in
+		   the absolute section.  */
+		fixP->fx_addsy = abs_section_sym;
+	      }
+	    symbol_mark_used_in_reloc (fixP->fx_addsy);
+	    if (fixP->fx_subsy != NULL)
+	      symbol_mark_used_in_reloc (fixP->fx_subsy);
+	    seg_reloc_count++;
+	  }
+      TC_ADJUST_RELOC_COUNT (fixP, seg_reloc_count);
+      return seg_reloc_count;
+    }
+
+  for (; fixP; fixP = fixP->fx_next)
+    {
+#ifdef DEBUG5
+      fprintf (stderr, "\nprocessing fixup:\n");
+      print_fixup (fixP);
+#endif
+
+      fragP = fixP->fx_frag;
+      know (fragP);
+#ifdef TC_VALIDATE_FIX
+      TC_VALIDATE_FIX (fixP, this_segment, skip);
+#endif
+      add_number = fixP->fx_offset;
+
+      if (fixP->fx_addsy != NULL)
+	add_symbol_segment = S_GET_SEGMENT (fixP->fx_addsy);
+
+      if (fixP->fx_subsy != NULL)
+	{
+	  segT sub_symbol_segment;
+	  resolve_symbol_value (fixP->fx_subsy);
+	  sub_symbol_segment = S_GET_SEGMENT (fixP->fx_subsy);
+	  if (fixP->fx_addsy != NULL
+	      && sub_symbol_segment == add_symbol_segment
+	      && !TC_FORCE_RELOCATION_SUB_SAME (fixP, add_symbol_segment))
+	    {
+	      add_number += S_GET_VALUE (fixP->fx_addsy);
+	      add_number -= S_GET_VALUE (fixP->fx_subsy);
+	      fixP->fx_offset = add_number;
+	      fixP->fx_addsy = NULL;
+	      fixP->fx_subsy = NULL;
+#ifdef TC_M68K
+	      /* See the comment below about 68k weirdness.  */
+	      fixP->fx_pcrel = 0;
+#endif
+	    }
+	  else if (sub_symbol_segment == absolute_section
+		   && !TC_FORCE_RELOCATION_SUB_ABS (fixP))
+	    {
+	      add_number -= S_GET_VALUE (fixP->fx_subsy);
+	      fixP->fx_offset = add_number;
+	      fixP->fx_subsy = NULL;
+	    }
+	  else if (sub_symbol_segment == this_segment
+		   && !TC_FORCE_RELOCATION_SUB_LOCAL (fixP))
+	    {
+	      add_number -= S_GET_VALUE (fixP->fx_subsy);
+	      fixP->fx_offset = (add_number + fixP->fx_dot_value
+				 + fixP->fx_frag->fr_address);
+
+	      /* Make it pc-relative.  If the back-end code has not
+		 selected a pc-relative reloc, cancel the adjustment
+		 we do later on all pc-relative relocs.  */
+	      if (0
+#ifdef TC_M68K
+		  /* Do this for m68k even if it's already described
+		     as pc-relative.  On the m68k, an operand of
+		     "pc@(foo-.-2)" should address "foo" in a
+		     pc-relative mode.  */
+		  || 1
+#endif
+		  || !fixP->fx_pcrel)
+		add_number += MD_PCREL_FROM_SECTION (fixP, this_segment);
+	      fixP->fx_subsy = NULL;
+	      fixP->fx_pcrel = 1;
+	    }
+	  else if (!TC_VALIDATE_FIX_SUB (fixP))
+	    {
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("can't resolve `%s' {%s section} - `%s' {%s section}"),
+			    fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
+			    segment_name (add_symbol_segment),
+			    S_GET_NAME (fixP->fx_subsy),
+			    segment_name (sub_symbol_segment));
+	    }
+	}
+
+      if (fixP->fx_addsy)
+	{
+	  if (add_symbol_segment == this_segment
+	      && !TC_FORCE_RELOCATION_LOCAL (fixP))
+	    {
+	      /* This fixup was made when the symbol's segment was
+		 SEG_UNKNOWN, but it is now in the local segment.
+		 So we know how to do the address without relocation.  */
+	      add_number += S_GET_VALUE (fixP->fx_addsy);
+	      fixP->fx_offset = add_number;
+	      if (fixP->fx_pcrel)
+		add_number -= MD_PCREL_FROM_SECTION (fixP, this_segment);
+	      fixP->fx_addsy = NULL;
+	      fixP->fx_pcrel = 0;
+	    }
+	  else if (add_symbol_segment == absolute_section
+		   && !TC_FORCE_RELOCATION_ABS (fixP))
+	    {
+	      add_number += S_GET_VALUE (fixP->fx_addsy);
+	      fixP->fx_offset = add_number;
+	      fixP->fx_addsy = NULL;
+	    }
+	  else if (add_symbol_segment != undefined_section
+		   && ! bfd_is_com_section (add_symbol_segment)
+		   && MD_APPLY_SYM_VALUE (fixP))
+	    add_number += S_GET_VALUE (fixP->fx_addsy);
+	}
+
+      if (fixP->fx_pcrel)
+	{
+	  add_number -= MD_PCREL_FROM_SECTION (fixP, this_segment);
+	  if (!fixP->fx_done && fixP->fx_addsy == NULL)
+	    {
+	      /* There was no symbol required by this relocation.
+		 However, BFD doesn't really handle relocations
+		 without symbols well. So fake up a local symbol in
+		 the absolute section.  */
+	      fixP->fx_addsy = abs_section_sym;
+	    }
+	}
+
+      if (!fixP->fx_done)
+	md_apply_fix (fixP, &add_number, this_segment);
+
+      if (!fixP->fx_done)
+	{
+	  ++seg_reloc_count;
+	  if (fixP->fx_addsy == NULL)
+	    fixP->fx_addsy = abs_section_sym;
+	  symbol_mark_used_in_reloc (fixP->fx_addsy);
+	  if (fixP->fx_subsy != NULL)
+	    symbol_mark_used_in_reloc (fixP->fx_subsy);
+	}
+
+      if (!fixP->fx_bit_fixP && !fixP->fx_no_overflow && fixP->fx_size != 0)
+	{
+	  if (fixP->fx_size < sizeof (valueT))
+	    {
+	      valueT mask;
+
+	      mask = 0;
+	      mask--;		/* Set all bits to one.  */
+	      mask <<= fixP->fx_size * 8 - (fixP->fx_signed ? 1 : 0);
+	      if ((add_number & mask) != 0 && (add_number & mask) != mask)
+		{
+		  char buf[50], buf2[50];
+		  sprint_value (buf, fragP->fr_address + fixP->fx_where);
+		  if (add_number > 1000)
+		    sprint_value (buf2, add_number);
+		  else
+		    sprintf (buf2, "%ld", (long) add_number);
+		  as_bad_where (fixP->fx_file, fixP->fx_line,
+				_("value of %s too large for field of %d bytes at %s"),
+				buf2, fixP->fx_size, buf);
+		} /* Generic error checking.  */
+	    }
+#ifdef WARN_SIGNED_OVERFLOW_WORD
+	  /* Warn if a .word value is too large when treated as a signed
+	     number.  We already know it is not too negative.  This is to
+	     catch over-large switches generated by gcc on the 68k.  */
+	  if (!flag_signed_overflow_ok
+	      && fixP->fx_size == 2
+	      && add_number > 0x7fff)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("signed .word overflow; switch may be too large; %ld at 0x%lx"),
+			  (long) add_number,
+			  (long) (fragP->fr_address + fixP->fx_where));
+#endif
+	}			/* Not a bit fix.  */
+
+#ifdef TC_VALIDATE_FIX
+    skip:  ATTRIBUTE_UNUSED_LABEL
+      ;
+#endif
+#ifdef DEBUG5
+      fprintf (stderr, "result:\n");
+      print_fixup (fixP);
+#endif
+    }				/* For each fixS in this segment.  */
+
+  TC_ADJUST_RELOC_COUNT (fixP, seg_reloc_count);
+  return seg_reloc_count;
+}
+
 static void
 fix_segment (bfd *abfd ATTRIBUTE_UNUSED,
 	     asection *sec,
-	     PTR xxx ATTRIBUTE_UNUSED)
+	     void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *seginfo = seg_info (sec);
 
@@ -774,14 +1079,40 @@ fix_segment (bfd *abfd ATTRIBUTE_UNUSED,
 }
 
 static void
-write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
+install_reloc (asection *sec, arelent *reloc, fragS *fragp,
+	       char *file, unsigned int line)
+{
+  char *err;
+  bfd_reloc_status_type s;
+
+  s = bfd_install_relocation (stdoutput, reloc,
+			      fragp->fr_literal, fragp->fr_address,
+			      sec, &err);
+  switch (s)
+    {
+    case bfd_reloc_ok:
+      break;
+    case bfd_reloc_overflow:
+      as_bad_where (file, line, _("relocation overflow"));
+      break;
+    case bfd_reloc_outofrange:
+      as_bad_where (file, line, _("relocation out of range"));
+      break;
+    default:
+      as_fatal (_("%s:%u: bad return from bfd_install_relocation: %x"),
+		file, line, s);
+    }
+}
+
+static void
+write_relocs (bfd *abfd, asection *sec, void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *seginfo = seg_info (sec);
   unsigned int i;
   unsigned int n;
+  struct reloc_list *my_reloc_list, **rp, *r;
   arelent **relocs;
   fixS *fixp;
-  char *err;
 
   /* If seginfo is NULL, we did not create this section; don't do
      anything with it.  */
@@ -790,153 +1121,73 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
 
   n = 0;
   for (fixp = seginfo->fix_root; fixp; fixp = fixp->fx_next)
-    n++;
+    if (!fixp->fx_done)
+      n++;
 
-#ifndef RELOC_EXPANSION_POSSIBLE
-  /* Set up reloc information as well.  */
-  relocs = (arelent **) xcalloc (n, sizeof (arelent *));
+#ifdef RELOC_EXPANSION_POSSIBLE
+  n *= MAX_RELOC_EXPANSION;
+#endif
 
-  i = 0;
-  for (fixp = seginfo->fix_root; fixp != (fixS *) NULL; fixp = fixp->fx_next)
+  /* Extract relocs for this section from reloc_list.  */
+  rp = &reloc_list;
+  my_reloc_list = NULL;
+  while ((r = *rp) != NULL)
     {
-      arelent *reloc;
-      bfd_reloc_status_type s;
-      symbolS *sym;
-
-      if (fixp->fx_done)
-	{
-	  n--;
-	  continue;
-	}
-
-      /* If this is an undefined symbol which was equated to another
-         symbol, then generate the reloc against the latter symbol
-         rather than the former.  */
-      sym = fixp->fx_addsy;
-      while (symbol_equated_reloc_p (sym))
-	{
-	  symbolS *n;
-
-	  /* We must avoid looping, as that can occur with a badly
-	     written program.  */
-	  n = symbol_get_value_expression (sym)->X_add_symbol;
-	  if (n == sym)
-	    break;
-	  fixp->fx_offset += symbol_get_value_expression (sym)->X_add_number;
-	  sym = n;
-	}
-      fixp->fx_addsy = sym;
-
-      reloc = tc_gen_reloc (sec, fixp);
-      if (!reloc)
+      if (r->u.b.sec == sec)
 	{
-	  n--;
-	  continue;
+	  *rp = r->next;
+	  r->next = my_reloc_list;
+	  my_reloc_list = r;
+	  n++;
 	}
-
-      /*
-	This test is triggered inappropriately for the SH:
-         if (fixp->fx_where + fixp->fx_size
-	     > fixp->fx_frag->fr_fix + fixp->fx_frag->fr_offset)
-	     abort ();
-      */
-
-      s = bfd_install_relocation (stdoutput, reloc,
-				  fixp->fx_frag->fr_literal,
-				  fixp->fx_frag->fr_address,
-				  sec, &err);
-      switch (s)
-	{
-	case bfd_reloc_ok:
-	  break;
-	case bfd_reloc_overflow:
-	  as_bad_where (fixp->fx_file, fixp->fx_line,
-			_("relocation overflow"));
-	  break;
-	case bfd_reloc_outofrange:
-	  as_bad_where (fixp->fx_file, fixp->fx_line,
-			_("relocation out of range"));
-	  break;
-	default:
-	  as_fatal (_("%s:%u: bad return from bfd_install_relocation: %x"),
-		    fixp->fx_file, fixp->fx_line, s);
-	}
-      relocs[i++] = reloc;
+      else
+	rp = &r->next;
     }
-#else
-  n = n * MAX_RELOC_EXPANSION;
-  /* Set up reloc information as well.  */
-  relocs = (arelent **) xcalloc (n, sizeof (arelent *));
+
+  relocs = xcalloc (n, sizeof (arelent *));
 
   i = 0;
   for (fixp = seginfo->fix_root; fixp != (fixS *) NULL; fixp = fixp->fx_next)
     {
-      arelent **reloc;
-      bfd_reloc_status_type s;
-      symbolS *sym;
       int j;
+      int fx_size, slack;
+      offsetT loc;
 
       if (fixp->fx_done)
-	{
-	  n--;
-	  continue;
-	}
+	continue;
+
+      fx_size = fixp->fx_size;
+      slack = TC_FX_SIZE_SLACK (fixp);
+      if (slack > 0)
+	fx_size = fx_size > slack ? fx_size - slack : 0;
+      loc = fixp->fx_where + fx_size;
+      if (slack >= 0 && loc > fixp->fx_frag->fr_fix)
+	as_bad_where (fixp->fx_file, fixp->fx_line,
+		      _("internal error: fixup not contained within frag"));
 
-      /* If this is an undefined symbol which was equated to another
-         symbol, then generate the reloc against the latter symbol
-         rather than the former.  */
-      sym = fixp->fx_addsy;
-      while (symbol_equated_reloc_p (sym))
-	{
-	  symbolS *n;
-
-	  /* We must avoid looping, as that can occur with a badly
-	     written program.  */
-	  n = symbol_get_value_expression (sym)->X_add_symbol;
-	  if (n == sym)
-	    break;
-	  fixp->fx_offset += symbol_get_value_expression (sym)->X_add_number;
-	  sym = n;
-	}
-      fixp->fx_addsy = sym;
+#ifndef RELOC_EXPANSION_POSSIBLE
+      {
+	arelent *reloc = tc_gen_reloc (sec, fixp);
 
-      reloc = tc_gen_reloc (sec, fixp);
+	if (!reloc)
+	  continue;
+	relocs[i++] = reloc;
+	j = 1;
+      }
+#else
+      {
+	arelent **reloc = tc_gen_reloc (sec, fixp);
 
-      for (j = 0; reloc[j]; j++)
-	{
+	for (j = 0; reloc[j]; j++)
 	  relocs[i++] = reloc[j];
-	  assert (i <= n);
-	}
-      if (fixp->fx_where + fixp->fx_size
-	  > fixp->fx_frag->fr_fix + fixp->fx_frag->fr_offset)
-	as_bad_where (fixp->fx_file, fixp->fx_line,
-		      _("internal error: fixup not contained within frag"));
-      for (j = 0; reloc[j]; j++)
-	{
-	  s = bfd_install_relocation (stdoutput, reloc[j],
-				      fixp->fx_frag->fr_literal,
-				      fixp->fx_frag->fr_address,
-				      sec, &err);
-	  switch (s)
-	    {
-	    case bfd_reloc_ok:
-	      break;
-	    case bfd_reloc_overflow:
-	      as_bad_where (fixp->fx_file, fixp->fx_line,
-			    _("relocation overflow"));
-	      break;
-	    case bfd_reloc_outofrange:
-	      as_bad_where (fixp->fx_file, fixp->fx_line,
-			    _("relocation out of range"));
-	      break;
-	    default:
-	      as_fatal (_("%s:%u: bad return from bfd_install_relocation: %x"),
-			fixp->fx_file, fixp->fx_line, s);
-	    }
-	}
+      }
+#endif
+
+      for ( ; j != 0; --j)
+	install_reloc (sec, relocs[i - j], fixp->fx_frag,
+		       fixp->fx_file, fixp->fx_line);
     }
   n = i;
-#endif
 
 #ifdef DEBUG4
   {
@@ -956,12 +1207,30 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
   }
 #endif
 
+  for (r = my_reloc_list; r != NULL; r = r->next)
+    {
+      fragS *f;
+      for (f = seginfo->frchainP->frch_root; f; f = f->fr_next)
+	if (f->fr_address <= r->u.b.r.address
+	    && r->u.b.r.address < f->fr_address + f->fr_fix)
+	  break;
+      if (f == NULL)
+	as_bad_where (r->file, r->line,
+		      _("reloc not within (fixed part of) section"));
+      else
+	{
+	  relocs[n++] = &r->u.b.r;
+	  install_reloc (sec, &r->u.b.r, f, r->file, r->line);
+	}
+    }
+
   if (n)
-    bfd_set_reloc (stdoutput, sec, relocs, n);
-  else
-    bfd_set_section_flags (abfd, sec,
-			   (bfd_get_section_flags (abfd, sec)
-			    & (flagword) ~SEC_RELOC));
+    {
+      flagword flags = bfd_get_section_flags (abfd, sec);
+      flags |= SEC_RELOC;
+      bfd_set_section_flags (abfd, sec, flags);
+      bfd_set_reloc (stdoutput, sec, relocs, n);
+    }
 
 #ifdef SET_SECTION_RELOCS
   SET_SECTION_RELOCS (sec, relocs, n);
@@ -987,7 +1256,7 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
 static void
 write_contents (bfd *abfd ATTRIBUTE_UNUSED,
 		asection *sec,
-		PTR xxx ATTRIBUTE_UNUSED)
+		void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *seginfo = seg_info (sec);
   addressT offset = 0;
@@ -1014,11 +1283,8 @@ write_contents (bfd *abfd ATTRIBUTE_UNUSED,
 					f->fr_literal, (file_ptr) offset,
 					(bfd_size_type) f->fr_fix);
 	  if (!x)
-	    {
-	      bfd_perror (stdoutput->filename);
-	      as_perror (_("FATAL: Can't write %s"), stdoutput->filename);
-	      exit (EXIT_FAILURE);
-	    }
+	    as_fatal (_("can't write %s: %s"), stdoutput->filename,
+		      bfd_errmsg (bfd_get_error ()));
 	  offset += f->fr_fix;
 	}
       fill_literal = f->fr_literal + f->fr_fix;
@@ -1038,12 +1304,8 @@ write_contents (bfd *abfd ATTRIBUTE_UNUSED,
 						(file_ptr) offset,
 						(bfd_size_type) fill_size);
 		  if (!x)
-		    {
-		      bfd_perror (stdoutput->filename);
-		      as_perror (_("FATAL: Can't write %s"),
-				 stdoutput->filename);
-		      exit (EXIT_FAILURE);
-		    }
+		    as_fatal (_("can't write %s: %s"), stdoutput->filename,
+			      bfd_errmsg (bfd_get_error ()));
 		  offset += fill_size;
 		}
 	    }
@@ -1097,7 +1359,6 @@ set_symtab (void)
   asymbol **asympp;
   symbolS *symp;
   bfd_boolean result;
-  extern PTR bfd_alloc (bfd *, bfd_size_type);
 
   /* Count symbols.  We can't rely on a count made by the loop in
      write_object_file, because *_frob_file may add a new symbol or
@@ -1111,7 +1372,7 @@ set_symtab (void)
       int i;
       bfd_size_type amt = (bfd_size_type) nsyms * sizeof (asymbol *);
 
-      asympp = (asymbol **) bfd_alloc (stdoutput, amt);
+      asympp = bfd_alloc (stdoutput, amt);
       symp = symbol_rootP;
       for (i = 0; i < nsyms; i++, symp = symbol_next (symp))
 	{
@@ -1138,8 +1399,7 @@ set_symtab (void)
    of the section.  This allows proper nop-filling at the end of
    code-bearing sections.  */
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN)					\
-  (!(FRCHAIN)->frch_next || (FRCHAIN)->frch_next->frch_seg != (SEG)	\
-   ? get_recorded_alignment (SEG) : 0)
+  (!(FRCHAIN)->frch_next ? get_recorded_alignment (SEG) : 0)
 #else
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
 #endif
@@ -1149,48 +1409,58 @@ void
 subsegs_finish (void)
 {
   struct frchain *frchainP;
+  asection *s;
 
-  for (frchainP = frchain_root; frchainP; frchainP = frchainP->frch_next)
+  for (s = stdoutput->sections; s; s = s->next)
     {
-      int alignment = 0;
-
-      subseg_set (frchainP->frch_seg, frchainP->frch_subseg);
+      segment_info_type *seginfo = seg_info (s);
+      if (!seginfo)
+	continue;
 
-      /* This now gets called even if we had errors.  In that case,
-         any alignment is meaningless, and, moreover, will look weird
-         if we are generating a listing.  */
-      if (!had_errors ())
+      for (frchainP = seginfo->frchainP;
+	   frchainP != NULL;
+	   frchainP = frchainP->frch_next)
 	{
-	  alignment = SUB_SEGMENT_ALIGN (now_seg, frchainP);
-	  if ((bfd_get_section_flags (now_seg->owner, now_seg) & SEC_MERGE)
-	      && now_seg->entsize)
-	    {
-	      unsigned int entsize = now_seg->entsize;
-	      int entalign = 0;
+	  int alignment = 0;
+
+	  subseg_set (s, frchainP->frch_subseg);
 
-	      while ((entsize & 1) == 0)
+	  /* This now gets called even if we had errors.  In that case,
+	     any alignment is meaningless, and, moreover, will look weird
+	     if we are generating a listing.  */
+	  if (!had_errors ())
+	    {
+	      alignment = SUB_SEGMENT_ALIGN (now_seg, frchainP);
+	      if ((bfd_get_section_flags (now_seg->owner, now_seg) & SEC_MERGE)
+		  && now_seg->entsize)
 		{
-		  ++entalign;
-		  entsize >>= 1;
+		  unsigned int entsize = now_seg->entsize;
+		  int entalign = 0;
+
+		  while ((entsize & 1) == 0)
+		    {
+		      ++entalign;
+		      entsize >>= 1;
+		    }
+		  if (entalign > alignment)
+		    alignment = entalign;
 		}
-	      if (entalign > alignment)
-		alignment = entalign;
 	    }
-	}
 
-      if (subseg_text_p (now_seg))
-	frag_align_code (alignment, 0);
-      else
-	frag_align (alignment, 0, 0);
+	  if (subseg_text_p (now_seg))
+	    frag_align_code (alignment, 0);
+	  else
+	    frag_align (alignment, 0, 0);
 
-      /* frag_align will have left a new frag.
-	 Use this last frag for an empty ".fill".
+	  /* frag_align will have left a new frag.
+	     Use this last frag for an empty ".fill".
 
-	 For this segment ...
-	 Create a last frag. Do not leave a "being filled in frag".  */
-      frag_wane (frag_now);
-      frag_now->fr_fix = 0;
-      know (frag_now->fr_next == NULL);
+	     For this segment ...
+	     Create a last frag. Do not leave a "being filled in frag".  */
+	  frag_wane (frag_now);
+	  frag_now->fr_fix = 0;
+	  know (frag_now->fr_next == NULL);
+	}
     }
 }
 
@@ -1411,6 +1681,7 @@ write_object_file (void)
 	resolve_symbol_value (symp);
     }
   resolve_local_symbol_values ();
+  resolve_reloc_expr_symbols ();
 
   PROGRESS (1);
 
@@ -1478,7 +1749,7 @@ write_object_file (void)
 	  resolve_symbol_value (symp);
 
 	  /* Skip symbols which were equated to undefined or common
-             symbols.  */
+	     symbols.  */
 	  if (symbol_equated_reloc_p (symp)
 	      || S_IS_WEAKREFR (symp))
 	    {
@@ -1807,23 +2078,48 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
   /* Do relax().  */
   {
     unsigned long max_iterations;
-    offsetT stretch;	/* May be any size, 0 or negative.  */
-    /* Cumulative number of addresses we have relaxed this pass.
-       We may have relaxed more than one address.  */
-    int stretched;	/* Have we stretched on this pass?  */
-    /* This is 'cuz stretch may be zero, when, in fact some piece of code
-       grew, and another shrank.  If a branch instruction doesn't fit anymore,
-       we could be scrod.  */
+
+    /* Cumulative address adjustment.  */
+    offsetT stretch;
+
+    /* Have we made any adjustment this pass?  We can't just test
+       stretch because one piece of code may have grown and another
+       shrank.  */
+    int stretched;
+
+    /* Most horrible, but gcc may give us some exception data that
+       is impossible to assemble, of the form
+
+       .align 4
+       .byte 0, 0
+       .uleb128 end - start
+       start:
+       .space 128*128 - 1
+       .align 4
+       end:
+
+       If the leb128 is two bytes in size, then end-start is 128*128,
+       which requires a three byte leb128.  If the leb128 is three
+       bytes in size, then end-start is 128*128-1, which requires a
+       two byte leb128.  We work around this dilemma by inserting
+       an extra 4 bytes of alignment just after the .align.  This
+       works because the data after the align is accessed relative to
+       the end label.
+
+       This counter is used in a tiny state machine to detect
+       whether a leb128 followed by an align is impossible to
+       relax.  */
+    int rs_leb128_fudge = 0;
 
     /* We want to prevent going into an infinite loop where one frag grows
        depending upon the location of a symbol which is in turn moved by
        the growing frag.  eg:
 
-         foo = .
-         .org foo+16
-         foo = .
+	 foo = .
+	 .org foo+16
+	 foo = .
 
-	So we dictate that this algorithm can be at most O2.  */
+       So we dictate that this algorithm can be at most O2.  */
     max_iterations = frag_count * frag_count;
     /* Check for overflow.  */
     if (max_iterations < frag_count)
@@ -1936,6 +2232,49 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
 		    }
 
 		  growth = newoff - oldoff;
+
+		  /* If this align happens to follow a leb128 and
+		     we have determined that the leb128 is bouncing
+		     in size, then break the cycle by inserting an
+		     extra alignment.  */
+		  if (growth < 0
+		      && (rs_leb128_fudge & 16) != 0
+		      && (rs_leb128_fudge & 15) >= 2)
+		    {
+		      segment_info_type *seginfo = seg_info (segment);
+		      struct obstack *ob = &seginfo->frchainP->frch_obstack;
+		      struct frag *newf;
+
+		      newf = frag_alloc (ob);
+		      obstack_blank_fast (ob, fragP->fr_var);
+		      obstack_finish (ob);
+		      memcpy (newf, fragP, SIZEOF_STRUCT_FRAG);
+		      memcpy (newf->fr_literal,
+			      fragP->fr_literal + fragP->fr_fix,
+			      fragP->fr_var);
+		      newf->fr_type = rs_fill;
+		      newf->fr_fix = 0;
+		      newf->fr_offset = (((offsetT) 1 << fragP->fr_offset)
+					 / fragP->fr_var);
+		      if (newf->fr_offset * newf->fr_var
+			  != (offsetT) 1 << fragP->fr_offset)
+			{
+			  newf->fr_offset = (offsetT) 1 << fragP->fr_offset;
+			  newf->fr_var = 1;
+			}
+		      /* Include growth of new frag, because rs_fill
+			 frags don't normally grow.  */
+		      growth += newf->fr_offset * newf->fr_var;
+		      /* The new frag address is newoff.  Adjust this
+			 for the amount we'll add when we process the
+			 new frag.  */
+		      newf->fr_address = newoff - stretch - growth;
+		      newf->relax_marker ^= 1;
+		      fragP->fr_next = newf;
+#ifdef DEBUG
+		      as_warn (_("padding added"));
+#endif
+		    }
 		}
 		break;
 
@@ -1946,11 +2285,11 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
 
 		  if (symbolP)
 		    {
-                      /* Convert from an actual address to an octet offset
-                         into the section.  Here it is assumed that the
-                         section's VMA is zero, and can omit subtracting it
-                         from the symbol's value to get the address offset.  */
-                      know (S_GET_SEGMENT (symbolP)->vma == 0);
+		      /* Convert from an actual address to an octet offset
+			 into the section.  Here it is assumed that the
+			 section's VMA is zero, and can omit subtracting it
+			 from the symbol's value to get the address offset.  */
+		      know (S_GET_SEGMENT (symbolP)->vma == 0);
 		      target += S_GET_VALUE (symbolP) * OCTETS_PER_BYTE;
 		    }
 
@@ -1986,7 +2325,7 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
 				    _("attempt to move .org backwards"));
 
 		      /* We've issued an error message.  Change the
-                         frag to avoid cascading errors.  */
+			 frag to avoid cascading errors.  */
 		      fragP->fr_type = rs_align;
 		      fragP->fr_subtype = 0;
 		      fragP->fr_offset = 0;
@@ -2075,8 +2414,23 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
 	      {
 		stretch += growth;
 		stretched = 1;
+		if (fragP->fr_type == rs_leb128)
+		  rs_leb128_fudge += 16;
+		else if (fragP->fr_type == rs_align
+			 && (rs_leb128_fudge & 16) != 0
+			 && stretch == 0)
+		  rs_leb128_fudge += 16;
+		else
+		  rs_leb128_fudge = 0;
 	      }
 	  }
+
+	if (stretch == 0
+	    && (rs_leb128_fudge & 16) == 0
+	    && (rs_leb128_fudge & -16) != 0)
+	  rs_leb128_fudge += 1;
+	else
+	  rs_leb128_fudge = 0;
       }
     /* Until nothing further to relax.  */
     while (stretched && -- max_iterations);
@@ -2095,246 +2449,6 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
   return ret;
 }
 
-/* fixup_segment()
-
-   Go through all the fixS's in a segment and see which ones can be
-   handled now.  (These consist of fixS where we have since discovered
-   the value of a symbol, or the address of the frag involved.)
-   For each one, call md_apply_fix to put the fix into the frag data.
-
-   Result is a count of how many relocation structs will be needed to
-   handle the remaining fixS's that we couldn't completely handle here.
-   These will be output later by emit_relocations().  */
-
-static long
-fixup_segment (fixS *fixP, segT this_segment)
-{
-  long seg_reloc_count = 0;
-  valueT add_number;
-  fragS *fragP;
-  segT add_symbol_segment = absolute_section;
-
-  if (fixP != NULL && abs_section_sym == NULL)
-    abs_section_sym = section_symbol (absolute_section);
-
-  /* If the linker is doing the relaxing, we must not do any fixups.
-
-     Well, strictly speaking that's not true -- we could do any that
-     are PC-relative and don't cross regions that could change size.
-     And for the i960 we might be able to turn callx/callj into bal
-     anyways in cases where we know the maximum displacement.  */
-  if (linkrelax && TC_LINKRELAX_FIXUP (this_segment))
-    {
-      for (; fixP; fixP = fixP->fx_next)
-	if (!fixP->fx_done)
-	  {
-	    if (fixP->fx_addsy == NULL)
-	      {
-		/* There was no symbol required by this relocation.
-		   However, BFD doesn't really handle relocations
-		   without symbols well. So fake up a local symbol in
-		   the absolute section.  */
-		fixP->fx_addsy = abs_section_sym;
-	      }
-	    symbol_mark_used_in_reloc (fixP->fx_addsy);
-	    if (fixP->fx_subsy != NULL)
-	      symbol_mark_used_in_reloc (fixP->fx_subsy);
-	    seg_reloc_count++;
-	  }
-      TC_ADJUST_RELOC_COUNT (fixP, seg_reloc_count);
-      return seg_reloc_count;
-    }
-
-  for (; fixP; fixP = fixP->fx_next)
-    {
-#ifdef DEBUG5
-      fprintf (stderr, "\nprocessing fixup:\n");
-      print_fixup (fixP);
-#endif
-
-      fragP = fixP->fx_frag;
-      know (fragP);
-#ifdef TC_VALIDATE_FIX
-      TC_VALIDATE_FIX (fixP, this_segment, skip);
-#endif
-      add_number = fixP->fx_offset;
-
-      if (fixP->fx_addsy != NULL
-	  && symbol_mri_common_p (fixP->fx_addsy))
-	{
-	  add_number += S_GET_VALUE (fixP->fx_addsy);
-	  fixP->fx_offset = add_number;
-	  fixP->fx_addsy
-	    = symbol_get_value_expression (fixP->fx_addsy)->X_add_symbol;
-	}
-
-      if (fixP->fx_addsy != NULL)
-	add_symbol_segment = S_GET_SEGMENT (fixP->fx_addsy);
-
-      if (fixP->fx_subsy != NULL)
-	{
-	  segT sub_symbol_segment;
-	  resolve_symbol_value (fixP->fx_subsy);
-	  sub_symbol_segment = S_GET_SEGMENT (fixP->fx_subsy);
-	  if (fixP->fx_addsy != NULL
-	      && sub_symbol_segment == add_symbol_segment
-	      && !TC_FORCE_RELOCATION_SUB_SAME (fixP, add_symbol_segment))
-	    {
-	      add_number += S_GET_VALUE (fixP->fx_addsy);
-	      add_number -= S_GET_VALUE (fixP->fx_subsy);
-	      fixP->fx_offset = add_number;
-	      fixP->fx_addsy = NULL;
-	      fixP->fx_subsy = NULL;
-#ifdef TC_M68K
-	      /* See the comment below about 68k weirdness.  */
-	      fixP->fx_pcrel = 0;
-#endif
-	    }
-	  else if (sub_symbol_segment == absolute_section
-		   && !TC_FORCE_RELOCATION_SUB_ABS (fixP))
-	    {
-	      add_number -= S_GET_VALUE (fixP->fx_subsy);
-	      fixP->fx_offset = add_number;
-	      fixP->fx_subsy = NULL;
-	    }
-	  else if (sub_symbol_segment == this_segment
-		   && !TC_FORCE_RELOCATION_SUB_LOCAL (fixP))
-	    {
-	      add_number -= S_GET_VALUE (fixP->fx_subsy);
-	      fixP->fx_offset = (add_number + fixP->fx_dot_value
-				 + fixP->fx_frag->fr_address);
-
-	      /* Make it pc-relative.  If the back-end code has not
-		 selected a pc-relative reloc, cancel the adjustment
-		 we do later on all pc-relative relocs.  */
-	      if (0
-#ifdef TC_M68K
-		  /* Do this for m68k even if it's already described
-		     as pc-relative.  On the m68k, an operand of
-		     "pc@(foo-.-2)" should address "foo" in a
-		     pc-relative mode.  */
-		  || 1
-#endif
-		  || !fixP->fx_pcrel)
-		add_number += MD_PCREL_FROM_SECTION (fixP, this_segment);
-	      fixP->fx_subsy = NULL;
-	      fixP->fx_pcrel = 1;
-	    }
-	  else if (!TC_VALIDATE_FIX_SUB (fixP))
-	    {
-	      as_bad_where (fixP->fx_file, fixP->fx_line,
-			    _("can't resolve `%s' {%s section} - `%s' {%s section}"),
-			    fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
-			    segment_name (add_symbol_segment),
-			    S_GET_NAME (fixP->fx_subsy),
-			    segment_name (sub_symbol_segment));
-	    }
-	}
-
-      if (fixP->fx_addsy)
-	{
-	  if (add_symbol_segment == this_segment
-	      && !TC_FORCE_RELOCATION_LOCAL (fixP))
-	    {
-	      /* This fixup was made when the symbol's segment was
-		 SEG_UNKNOWN, but it is now in the local segment.
-		 So we know how to do the address without relocation.  */
-	      add_number += S_GET_VALUE (fixP->fx_addsy);
-	      fixP->fx_offset = add_number;
-	      if (fixP->fx_pcrel)
-		add_number -= MD_PCREL_FROM_SECTION (fixP, this_segment);
-	      fixP->fx_addsy = NULL;
-	      fixP->fx_pcrel = 0;
-	    }
-	  else if (add_symbol_segment == absolute_section
-		   && !TC_FORCE_RELOCATION_ABS (fixP))
-	    {
-	      add_number += S_GET_VALUE (fixP->fx_addsy);
-	      fixP->fx_offset = add_number;
-	      fixP->fx_addsy = NULL;
-	    }
-	  else if (add_symbol_segment != undefined_section
-		   && ! bfd_is_com_section (add_symbol_segment)
-		   && MD_APPLY_SYM_VALUE (fixP))
-	    add_number += S_GET_VALUE (fixP->fx_addsy);
-	}
-
-      if (fixP->fx_pcrel)
-	{
-	  add_number -= MD_PCREL_FROM_SECTION (fixP, this_segment);
-	  if (!fixP->fx_done && fixP->fx_addsy == NULL)
-	    {
-	      /* There was no symbol required by this relocation.
-		 However, BFD doesn't really handle relocations
-		 without symbols well. So fake up a local symbol in
-		 the absolute section.  */
-	      fixP->fx_addsy = abs_section_sym;
-	    }
-	}
-
-      if (!fixP->fx_done)
-	md_apply_fix (fixP, &add_number, this_segment);
-
-      if (!fixP->fx_done)
-	{
-	  ++seg_reloc_count;
-	  if (fixP->fx_addsy == NULL)
-	    fixP->fx_addsy = abs_section_sym;
-	  symbol_mark_used_in_reloc (fixP->fx_addsy);
-	  if (fixP->fx_subsy != NULL)
-	    symbol_mark_used_in_reloc (fixP->fx_subsy);
-	}
-
-      if (!fixP->fx_bit_fixP && !fixP->fx_no_overflow && fixP->fx_size != 0)
-	{
-	  if (fixP->fx_size < sizeof (valueT))
-	    {
-	      valueT mask;
-
-	      mask = 0;
-	      mask--;		/* Set all bits to one.  */
-	      mask <<= fixP->fx_size * 8 - (fixP->fx_signed ? 1 : 0);
-	      if ((add_number & mask) != 0 && (add_number & mask) != mask)
-		{
-		  char buf[50], buf2[50];
-		  sprint_value (buf, fragP->fr_address + fixP->fx_where);
-		  if (add_number > 1000)
-		    sprint_value (buf2, add_number);
-		  else
-		    sprintf (buf2, "%ld", (long) add_number);
-		  as_bad_where (fixP->fx_file, fixP->fx_line,
-				_("value of %s too large for field of %d bytes at %s"),
-				buf2, fixP->fx_size, buf);
-		} /* Generic error checking.  */
-	    }
-#ifdef WARN_SIGNED_OVERFLOW_WORD
-	  /* Warn if a .word value is too large when treated as a signed
-	     number.  We already know it is not too negative.  This is to
-	     catch over-large switches generated by gcc on the 68k.  */
-	  if (!flag_signed_overflow_ok
-	      && fixP->fx_size == 2
-	      && add_number > 0x7fff)
-	    as_bad_where (fixP->fx_file, fixP->fx_line,
-			  _("signed .word overflow; switch may be too large; %ld at 0x%lx"),
-			  (long) add_number,
-			  (long) (fragP->fr_address + fixP->fx_where));
-#endif
-	}			/* Not a bit fix.  */
-
-#ifdef TC_VALIDATE_FIX
-    skip:  ATTRIBUTE_UNUSED_LABEL
-      ;
-#endif
-#ifdef DEBUG5
-      fprintf (stderr, "result:\n");
-      print_fixup (fixP);
-#endif
-    }				/* For each fixS in this segment.  */
-
-  TC_ADJUST_RELOC_COUNT (fixP, seg_reloc_count);
-  return seg_reloc_count;
-}
-
 void
 number_to_chars_bigendian (char *buf, valueT val, int n)
 {
diff --git a/contrib/binutils/gas/write.h b/contrib/binutils/gas/write.h
index 1f9b72d..4f75eb6 100644
--- a/contrib/binutils/gas/write.h
+++ b/contrib/binutils/gas/write.h
@@ -1,6 +1,7 @@
 /* write.h
    Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2001,
-   2002, 2003, 2005, 2006 Free Software Foundation, Inc.
+   2002, 2003, 2005, 2006, 2007
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -22,12 +23,6 @@
 #ifndef __write_h__
 #define __write_h__
 
-#ifndef TC_I960
-#ifdef hpux
-#define EXEC_MACHINE_TYPE HP9000S200_ID
-#endif
-#endif /* TC_I960 */
-
 /* This is the name of a fake symbol which will never appear in the
    assembler output.  S_IS_LOCAL detects it because of the \001.  */
 #ifndef FAKE_LABEL_NAME
@@ -45,29 +40,16 @@ struct fix
   /* These small fields are grouped together for compactness of
      this structure, and efficiency of access on some architectures.  */
 
-  /* pc-relative offset adjust (only used by m68k) */
-  char fx_pcrel_adjust;
-
-  /* How many bytes are involved? */
-  unsigned char fx_size;
-
   /* Is this a pc-relative relocation?  */
   unsigned fx_pcrel : 1;
 
-  /* Is this a relocation to a procedure linkage table entry?  If so,
-     some of the reductions we try to apply are invalid.  A better way
-     might be to represent PLT entries with different kinds of
-     symbols, and use normal relocations (with undefined symbols);
-     look into it for version 2.6.  */
-  unsigned fx_plt : 1;
-
   /* Is this value an immediate displacement?  */
-  /* Only used on i960 and ns32k; merge it into TC_FIX_TYPE sometime.  */
+  /* Only used on ns32k; merge it into TC_FIX_TYPE sometime.  */
   unsigned fx_im_disp : 2;
 
-  /* A bit for the CPU specific code.
-     This probably can be folded into tc_fix_data, below.  */
+  /* Some bits for the CPU specific code.  */
   unsigned fx_tcbit : 1;
+  unsigned fx_tcbit2 : 1;
 
   /* Has this relocation already been applied?  */
   unsigned fx_done : 1;
@@ -82,6 +64,12 @@ struct fix
   /* The value is signed when checking for overflow.  */
   unsigned fx_signed : 1;
 
+  /* pc-relative offset adjust (only used by m68k and m68hc11) */
+  char fx_pcrel_adjust;
+
+  /* How many bytes are involved? */
+  unsigned char fx_size;
+
   /* Which frag does this fix apply to?  */
   fragS *fx_frag;
 
@@ -132,6 +120,10 @@ struct fix
     const struct cgen_insn *insn;
     /* Target specific data, usually reloc number.  */
     int opinfo;
+    /* Which ifield this fixup applies to. */
+    struct cgen_maybe_multi_ifield * field;
+    /* is this field is the MSB field in a set? */
+    int msb_field_p;
   } fx_cgen;
 #endif
 
@@ -144,11 +136,33 @@ struct fix
 
 typedef struct fix fixS;
 
+struct reloc_list
+{
+  struct reloc_list *next;
+  union
+  {
+    struct
+    {
+      symbolS *offset_sym;
+      reloc_howto_type *howto;
+      symbolS *sym;
+      bfd_vma addend;
+    } a;
+    struct
+    {
+      asection *sec;
+      asymbol *s;
+      arelent r;
+    } b;
+  } u;
+  char *file;
+  unsigned int line;
+};
+
 extern int finalize_syms;
 extern symbolS *abs_section_sym;
 extern addressT dot_value;
-extern long string_byte_count;
-extern int section_alignment[];
+extern struct reloc_list* reloc_list;
 
 extern void append (char **charPP, char *fromP, unsigned long length);
 extern void record_alignment (segT seg, int align);