diff options
Diffstat (limited to 'contrib/binutils/gas/doc/c-i386.texi')
| -rw-r--r-- | contrib/binutils/gas/doc/c-i386.texi | 56 |
1 files changed, 52 insertions, 4 deletions
diff --git a/contrib/binutils/gas/doc/c-i386.texi b/contrib/binutils/gas/doc/c-i386.texi index 81039c4..48b251a 100644 --- a/contrib/binutils/gas/doc/c-i386.texi +++ b/contrib/binutils/gas/doc/c-i386.texi @@ -76,6 +76,49 @@ character, which means that it cannot be used in expressions. The not disable @samp{/} at the beginning of a line starting a comment, or affect using @samp{#} for starting a comment. +@cindex @samp{-march=} option, i386 +@cindex @samp{-march=} option, x86-64 +@item -march=@var{CPU} +This option specifies an instruction set architecture for generating +instructions. The following architectures are recognized: +@code{i8086}, +@code{i186}, +@code{i286}, +@code{i386}, +@code{i486}, +@code{i586}, +@code{i686}, +@code{pentium}, +@code{pentiumpro}, +@code{pentiumii}, +@code{pentiumiii}, +@code{pentium4}, +@code{prescott}, +@code{nocona}, +@code{core}, +@code{core2}, +@code{k6}, +@code{k6_2}, +@code{athlon}, +@code{sledgehammer}, +@code{opteron}, +@code{k8}, +@code{generic32} and +@code{generic64}. + +This option only affects instructions generated by the assembler. The +@code{.arch} directive will take precedent. + +@cindex @samp{-mtune=} option, i386 +@cindex @samp{-mtune=} option, x86-64 +@item -mtune=@var{CPU} +This option specifies a processor to optimize for. When used in +conjunction with the @option{-march} option, only instructions +of the processor specified by the @option{-march} option will be +generated. + +Valid @var{CPU} values are identical to @option{-march=@var{CPU}}. + @end table @node i386-Syntax @@ -604,7 +647,7 @@ then stores the result in the 4 byte location @samp{mem}) @code{@value{AS}} supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, -Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! +Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future. @@ -667,7 +710,7 @@ value @samp{4} onto the stack, decrementing @samp{%esp} by 2. @end smallexample The same code in a 16-bit code section would generate the machine -opcode bytes @samp{6a 04} (ie. without the operand size prefix), which +opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section. @@ -709,8 +752,13 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} -@item @samp{k6} @tab @samp{athlon} @samp{sledgehammer} -@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.sse3} @samp{.3dnow} +@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} +@item @samp{amdfam10} +@item @samp{k6} @tab @samp{athlon} @tab @samp{sledgehammer} @tab @samp{k8} +@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} +@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} +@item @samp{.sse4a} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.padlock} +@item @samp{.pacifica} @tab @samp{.svme} @tab @samp{.abm} @end multitable Apart from the warning, there are only two other effects on |
