diff options
Diffstat (limited to 'contrib/binutils/gas/doc/c-arm.texi')
| -rw-r--r-- | contrib/binutils/gas/doc/c-arm.texi | 117 |
1 files changed, 109 insertions, 8 deletions
diff --git a/contrib/binutils/gas/doc/c-arm.texi b/contrib/binutils/gas/doc/c-arm.texi index ca0998b..8fc2972 100644 --- a/contrib/binutils/gas/doc/c-arm.texi +++ b/contrib/binutils/gas/doc/c-arm.texi @@ -155,9 +155,9 @@ names are recognized: @code{armv6z}, @code{armv6zk}, @code{armv7}, -@code{armv7a}, -@code{armv7r}, -@code{armv7m}, +@code{armv7-a}, +@code{armv7-r}, +@code{armv7-m}, @code{iwmmxt} and @code{xscale}. @@ -254,7 +254,7 @@ and @item -meabi=@var{ver} This option specifies which EABI version the produced object files should conform to. -The following values are recognised: +The following values are recognized: @code{gnu}, @code{4} and @@ -284,6 +284,7 @@ as position-independent code (PIC). @menu * ARM-Chars:: Special Characters * ARM-Regs:: Register Names +* ARM-Relocations:: Relocations @end menu @node ARM-Chars @@ -323,7 +324,46 @@ Either @samp{#} or @samp{$} can be used to indicate immediate operands. @cindex ARM floating point (@sc{ieee}) The ARM family uses @sc{ieee} floating-point numbers. +@node ARM-Relocations +@subsection ARM relocation generation + +@cindex data relocations, ARM +@cindex ARM data relocations +Specific data relocations can be generated by putting the relocation name +in parentheses after the symbol name. For example: + +@smallexample + .word foo(TARGET1) +@end smallexample + +This will generate an @samp{R_ARM_TARGET1} relocation against the symbol +@var{foo}. +The following relocations are supported: +@code{GOT}, +@code{GOTOFF}, +@code{TARGET1}, +@code{TARGET2}, +@code{SBREL}, +@code{TLSGD}, +@code{TLSLDM}, +@code{TLSLDO}, +@code{GOTTPOFF} +and +@code{TPOFF}. + +For compatibility with older toolchains the assembler also accepts +@code{(PLT)} after branch targets. This will generate the deprecated +@samp{R_ARM_PLT32} relocation. +@cindex MOVW and MOVT relocations, ARM +Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated +by prefixing the value with @samp{#:lower16:} and @samp{#:upper16} +respectively. For example to load the 32-bit address of foo into r0: + +@smallexample + MOVW r0, #:lower16:foo + MOVT r0, #:upper16:foo +@end smallexample @node ARM Directives @section ARM Machine Directives @@ -351,7 +391,7 @@ example: @cindex @code{unreq} directive, ARM @item .unreq @var{alias-name} This undefines a register alias which was previously defined using the -@code{req} directive. For example: +@code{req}, @code{dn} or @code{qn} directives. For example: @smallexample foo .req r0 @@ -362,6 +402,36 @@ An error occurs if the name is undefined. Note - this pseudo op can be used to delete builtin in register name aliases (eg 'r0'). This should only be done if it is really necessary. +@cindex @code{dn} and @code{qn} directives, ARM +@item @var{name} .dn @var{register name} [@var{.type}] [@var{[index]}] +@item @var{name} .qn @var{register name} [@var{.type}] [@var{[index]}] + +The @code{dn} and @code{qn} directives are used to create typed +and/or indexed register aliases for use in Advanced SIMD Extension +(Neon) instructions. The former should be used to create aliases +of double-precision registers, and the latter to create aliases of +quad-precision registers. + +If these directives are used to create typed aliases, those aliases can +be used in Neon instructions instead of writing types after the mnemonic +or after each operand. For example: + +@smallexample + x .dn d2.f32 + y .dn d3.f32 + z .dn d4.f32[1] + vmul x,y,z +@end smallexample + +This is equivalent to writing the following: + +@smallexample + vmul.f32 d2,d3,d4[1] +@end smallexample + +Aliases created using @code{dn} or @code{qn} can be destroyed using +@code{unreq}. + @cindex @code{code} directive, ARM @item .code @code{[16|32]} This directive selects the instruction set being generated. The value 16 @@ -389,6 +459,9 @@ between Arm and Thumb instructions and should be used even if interworking is not going to be performed. The presence of this directive also implies @code{.thumb} +This directive is not neccessary when generating EABI objects. On these +targets the encoding is implicit when generating Thumb code. + @cindex @code{thumb_set} directive, ARM @item .thumb_set This performs the equivalent of a @code{.set} directive in that it @@ -466,7 +539,7 @@ instruction. sfmfd f4, 2, [sp]! @exdent @emph{VFP registers} .save @{d8, d9, d10@} - fstmdf sp!, @{d8, d9, d10@} + fstmdx sp!, @{d8, d9, d10@} @exdent @emph{iWMMXt registers} .save @{wr10, wr11@} wstrd wr11, [sp, #-8]! @@ -478,6 +551,26 @@ or wstrd wr10, [sp, #-8]! @end smallexample +@cindex @code{.vsave} directive, ARM +@item .vsave @var{vfp-reglist} +Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist} +using FLDMD. Also works for VFPv3 registers +that are to be restored using VLDM. +The format of @var{vfp-reglist} is the same as the corresponding store-multiple +instruction. + +@smallexample +@exdent @emph{VFP registers} + .vsave @{d8, d9, d10@} + fstmdd sp!, @{d8, d9, d10@} +@exdent @emph{VFPv3 registers} + .vsave @{d15, d16, d17@} + vstm sp!, @{d15, d16, d17@} +@end smallexample + +Since FLDMX and FSTMX are now deprecated, this directive should be +used in favour of @code{.save} for saving VFP registers for ARMv6 and above. + @cindex @code{.pad} directive, ARM @item .pad #@var{count} Generate unwinder annotations for a stack adjustment of @var{count} bytes. @@ -485,8 +578,10 @@ A positive value indicates the function prologue allocated stack space by decrementing the stack pointer. @cindex @code{.movsp} directive, ARM -@item .movsp @var{reg} -Tell the unwinder that @var{reg} contains the current stack pointer. +@item .movsp @var{reg} [, #@var{offset}] +Tell the unwinder that @var{reg} contains an offset from the current +stack pointer. If @var{offset} is not specified then it is assumed to be +zero. @cindex @code{.setfp} directive, ARM @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}] @@ -523,6 +618,12 @@ for the @option{-mcpu} commandline option. Select the target architecture. Valid values for @var{name} are the same as for the @option{-march} commandline option. +@cindex @code{.object_arch} directive, ARM +@item .object_arch @var{name} +Override the architecture recorded in the EABI object attribute section. +Valid values for @var{name} are the same as for the @code{.arch} directive. +Typically this is useful when code uses runtime detection of CPU features. + @cindex @code{.fpu} directive, ARM @item .fpu @var{name} Select the floating point unit to assemble for. Valid values for @var{name} |
