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Diffstat (limited to 'contrib/binutils/gas/doc/as.1')
| -rw-r--r-- | contrib/binutils/gas/doc/as.1 | 161 |
1 files changed, 136 insertions, 25 deletions
diff --git a/contrib/binutils/gas/doc/as.1 b/contrib/binutils/gas/doc/as.1 index b0de343..e16cbe9 100644 --- a/contrib/binutils/gas/doc/as.1 +++ b/contrib/binutils/gas/doc/as.1 @@ -1,4 +1,4 @@ -.\" Automatically generated by Pod::Man v1.3, Pod::Parser v1.13 +.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.14 .\" .\" Standard preamble: .\" ======================================================================== @@ -21,7 +21,6 @@ .. .de Ve \" End verbatim text .ft R - .fi .. .\" Set up some character translations and predefined strings. \*(-- will @@ -129,15 +128,14 @@ .\" ======================================================================== .\" .IX Title "AS 1" -.TH AS 1 "2002-08-05" "binutils-2.12.91" "GNU Development Tools" -.UC +.TH AS 1 "2004-05-17" "binutils-2.15" "GNU Development Tools" .SH "NAME" -\&\s-1AS\s0 \- the portable \s-1GNU\s0 assembler. +AS \- the portable GNU assembler. .SH "SYNOPSIS" .IX Header "SYNOPSIS" as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] - [\fB\-f\fR] [\fB\-\-gstabs\fR] [\fB\-\-gdwarf2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] - [\fB\-J\fR] [\fB\-K\fR] [\fB\-L\fR] + [\fB\-f\fR] [\fB\-\-gstabs\fR] [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf2\fR] [\fB\-\-help\fR] + [\fB\-I\fR \fIdir\fR] [\fB\-J\fR] [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-statistics\fR] [\fB\-v\fR] @@ -158,7 +156,8 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f \&\fITarget \s-1ARM\s0 options:\fR [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]] [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]] - [\fB\-mfpu\fR=\fIfloating-point-fromat\fR] + [\fB\-mfpu\fR=\fIfloating-point-format\fR] + [\fB\-mfloat\-abi\fR=\fIabi\fR] [\fB\-mthumb\fR] [\fB\-EB\fR|\fB\-EL\fR] [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR| @@ -177,13 +176,16 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR] .PP \&\fITarget i386 options:\fR - [\fB\-\-32\fR|\fB\-\-64\fR] + [\fB\-\-32\fR|\fB\-\-64\fR] [\fB\-n\fR] .PP \&\fITarget i960 options:\fR [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR| \fB\-AKC\fR|\fB\-AMC\fR] [\fB\-b\fR] [\fB\-no\-relax\fR] .PP +\&\fITarget \s-1IP2K\s0 options:\fR + [\fB\-mip2022\fR|\fB\-mip2022ext\fR] +.PP \&\fITarget M32R options:\fR [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR| \fB\-\-W[n]p\fR] @@ -192,7 +194,9 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...] .PP \&\fITarget M68HC11 options:\fR - [\fB\-m68hc11\fR|\fB\-m68hc12\fR] + [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR] + [\fB\-mshort\fR|\fB\-mlong\fR] + [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR] [\fB\-\-force\-long\-branchs\fR] [\fB\-\-short\-branchs\fR] [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR] [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR] @@ -202,12 +206,13 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f [\fB\-mcpu=[210|340]\fR] .PP \&\fITarget \s-1MIPS\s0 options:\fR - [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-n\fR] [\fB\-O\fR[\fIoptimization level\fR]] + [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]] [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR] [\fB\-non_shared\fR] [\fB\-xgot\fR] [\fB\-\-membedded\-pic\fR] [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR] [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR] - [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips64\fR] + [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR] + [\fB\-mips64\fR] [\fB\-mips64r2\fR] [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR] [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR] [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR] @@ -215,6 +220,7 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR] [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR] [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR] + [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR] .PP \&\fITarget \s-1MMIX\s0 options:\fR [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR] @@ -245,6 +251,15 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR] [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR] [\fB\-32\fR|\fB\-64\fR] +.PP +\&\fITarget \s-1TIC54X\s0 options:\fR + [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR] + [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR] +.PP +\&\fITarget Xtensa options:\fR + [\fB\-\-[no\-]density\fR] [\fB\-\-[no\-]relax\fR] [\fB\-\-[no\-]generics\fR] + [\fB\-\-[no\-]text\-section\-literals\fR] + [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR] .SH "DESCRIPTION" .IX Header "DESCRIPTION" \&\s-1GNU\s0 \fBas\fR is really a family of assemblers. @@ -255,8 +270,8 @@ including object file formats, most assembler directives (often called \&\fIpseudo-ops\fR) and assembler syntax. .PP \&\fBas\fR is primarily intended to assemble the output of the -\&\s-1GNU\s0 C compiler for use by the linker -\&. Nevertheless, we've tried to make \fBas\fR +\&\s-1GNU\s0 C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker +\&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly. @@ -290,7 +305,7 @@ runs \fBas\fR automatically. Warnings report an assumption made so that \fBas\fR could keep assembling a flawed program; errors report a grave problem that stops the assembly. .PP -If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler (version 2), +If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler, you can use the \fB\-Wa\fR option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the \fB\-Wa\fR) by commas. For example: @@ -298,8 +313,9 @@ by commas. For example: .Vb 1 \& gcc -c -g -O -Wa,-alh,-L file.c .Ve +.PP This passes two options to the assembler: \fB\-alh\fR (emit a listing to -standard output with with high-level and assembly source) and \fB\-L\fR (retain +standard output with high-level and assembly source) and \fB\-L\fR (retain local symbols in the symbol table). .PP Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler @@ -361,10 +377,17 @@ compiler output). .IX Item "--gstabs" Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. +.IP "\fB\-\-gstabs+\fR" 4 +.IX Item "--gstabs+" +Generate stabs debugging information for each assembler line, with \s-1GNU\s0 +extensions that probably only gdb can handle, and that could make other +debuggers crash or refuse to read your program. This +may help debugging assembler code. Currently the only \s-1GNU\s0 extension is +the location of the current working directory at assembling time. .IP "\fB\-\-gdwarf2\fR" 4 .IX Item "--gdwarf2" Generate \s-1DWARF2\s0 debugging information for each assembler line. This -may help debugging assembler code, if the debugger can handle it. Note \- this +may help debugging assembler code, if the debugger can handle it. Note\-\-\-this option is only supported by some targets, not all of them. .IP "\fB\-\-help\fR" 4 .IX Item "--help" @@ -380,7 +403,7 @@ Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR direct Don't warn about signed overflow. .IP "\fB\-K\fR" 4 .IX Item "-K" -This option is accepted but has no effect on the \s-1TARGET\s0 family. +Issue warnings when difference tables altered for long displacements. .IP "\fB\-L\fR" 4 .IX Item "-L" .PD 0 @@ -475,6 +498,9 @@ Specify which \s-1ARM\s0 architecture variant is used by the target. .IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4 .IX Item "-mfpu=floating-point-format" Select which Floating Point architecture is the target. +.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4 +.IX Item "-mfloat-abi=abi" +Select which floating point \s-1ABI\s0 is in use. .IP "\fB\-mthumb\fR" 4 .IX Item "-mthumb" Enable Thumb only instruction decoding. @@ -526,7 +552,17 @@ Do not alter compare-and-branch instructions for long displacements; error if necessary. .PP The following options are available when as is configured for the -Mitsubishi M32R series. +Ubicom \s-1IP2K\s0 series. +.IP "\fB\-mip2022ext\fR" 4 +.IX Item "-mip2022ext" +Specifies that the extended \s-1IP2022\s0 instructions are allowed. +.IP "\fB\-mip2022\fR" 4 +.IX Item "-mip2022" +Restores the default behaviour, which restricts the permitted instructions to +just the basic \s-1IP2022\s0 ones. +.PP +The following options are available when as is configured for the +Renesas M32R (formerly Mitsubishi M32R) series. .IP "\fB\-\-m32rx\fR" 4 .IX Item "--m32rx" Specify which processor in the M32R family is the target. The default @@ -606,10 +642,22 @@ Generate ``little endian'' format output. .PP The following options are available when as is configured for the Motorola 68HC11 or 68HC12 series. -.IP "\fB\-m68hc11 | \-m68hc12\fR" 4 -.IX Item "-m68hc11 | -m68hc12" +.IP "\fB\-m68hc11 | \-m68hc12 | \-m68hcs12\fR" 4 +.IX Item "-m68hc11 | -m68hc12 | -m68hcs12" Specify what processor is the target. The default is defined by the configuration option when building the assembler. +.IP "\fB\-mshort\fR" 4 +.IX Item "-mshort" +Specify to use the 16\-bit integer \s-1ABI\s0. +.IP "\fB\-mlong\fR" 4 +.IX Item "-mlong" +Specify to use the 32\-bit integer \s-1ABI\s0. +.IP "\fB\-mshort\-double\fR" 4 +.IX Item "-mshort-double" +Specify to use the 32\-bit double \s-1ABI\s0. +.IP "\fB\-mlong\-double\fR" 4 +.IX Item "-mlong-double" +Specify to use the 64\-bit double \s-1ABI\s0. .IP "\fB\-\-force\-long\-branchs\fR" 4 .IX Item "--force-long-branchs" Relative branches are turned into absolute ones. This concerns @@ -657,6 +705,20 @@ equivalent to \-Av8plus and \-Av8plusa, respectively. .IX Item "-bump" Warn when the assembler switches to another architecture. .PP +The following options are available when as is configured for the 'c54x +architecture. +.IP "\fB\-mfar\-mode\fR" 4 +.IX Item "-mfar-mode" +Enable extended addressing mode. All addresses and relocations will assume +extended addressing (usually 23 bits). +.IP "\fB\-mcpu=\fR\fI\s-1CPU_VERSION\s0\fR" 4 +.IX Item "-mcpu=CPU_VERSION" +Sets the \s-1CPU\s0 version being compiled for. +.IP "\fB\-merrors\-to\-file\fR \fI\s-1FILENAME\s0\fR" 4 +.IX Item "-merrors-to-file FILENAME" +Redirect error output to a file, for broken systems which don't support such +behaviour in the shell. +.PP The following options are available when as is configured for a \s-1MIPS\s0 processor. .IP "\fB\-G\fR \fInum\fR" 4 @@ -683,16 +745,23 @@ Generate ``little endian'' format output. .IX Item "-mips5" .IP "\fB\-mips32\fR" 4 .IX Item "-mips32" +.IP "\fB\-mips32r2\fR" 4 +.IX Item "-mips32r2" .IP "\fB\-mips64\fR" 4 .IX Item "-mips64" +.IP "\fB\-mips64r2\fR" 4 +.IX Item "-mips64r2" .PD Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level. \&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for \&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR. -\&\fB\-mips5\fR, \fB\-mips32\fR, and \fB\-mips64\fR correspond to generic -\&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, and \fB\s-1MIPS64\s0\fR \s-1ISA\s0 processors, -respectively. +\&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips64\fR, and +\&\fB\-mips64r2\fR +correspond to generic +\&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, \fB\s-1MIPS64\s0\fR, +and \fB\s-1MIPS64\s0 Release 2\fR +\&\s-1ISA\s0 processors, respectively. .IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4 .IX Item "-march=CPU" Generate code for a particular \s-1MIPS\s0 cpu. @@ -715,6 +784,13 @@ of an mfhi or mflo instruction occurs in the following two instructions. .PD Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard \s-1ELF\s0 .stabs sections. +.IP "\fB\-mpdr\fR" 4 +.IX Item "-mpdr" +.PD 0 +.IP "\fB\-mno\-pdr\fR" 4 +.IX Item "-mno-pdr" +.PD +Control generation of \f(CW\*(C`.pdr\*(C'\fR sections. .IP "\fB\-mgp32\fR" 4 .IX Item "-mgp32" .PD 0 @@ -844,6 +920,41 @@ Assemble for a big endian target. Assemble for a little endian target. .PP See the info pages for documentation of the MMIX-specific options. +.PP +The following options are available when as is configured for +an Xtensa processor. +.IP "\fB\-\-density | \-\-no\-density\fR" 4 +.IX Item "--density | --no-density" +Enable or disable use of instructions from the Xtensa code density +option. This is enabled by default when the Xtensa processor supports +the code density option. +.IP "\fB\-\-relax | \-\-no\-relax\fR" 4 +.IX Item "--relax | --no-relax" +Enable or disable instruction relaxation. This is enabled by default. +Note: In the current implementation, these options also control whether +assembler optimizations are performed, making these options equivalent +to \fB\-\-generics\fR and \fB\-\-no\-generics\fR. +.IP "\fB\-\-generics | \-\-no\-generics\fR" 4 +.IX Item "--generics | --no-generics" +Enable or disable all assembler transformations of Xtensa instructions. +The default is \fB\-\-generics\fR; +\&\fB\-\-no\-generics\fR should be used only in the rare cases when the +instructions must be exactly as specified in the assembly source. +.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4 +.IX Item "--text-section-literals | --no-text-section-literals" +With \fB\-\-text\-section\-literals\fR, literal pools are interspersed +in the text section. The default is +\&\fB\-\-no\-text\-section\-literals\fR, which places literals in a +separate section in the output file. +.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4 +.IX Item "--target-align | --no-target-align" +Enable or disable automatic alignment to reduce branch penalties at the +expense of some code density. The default is \fB\-\-target\-align\fR. +.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4 +.IX Item "--longcalls | --no-longcalls" +Enable or disable transformation of call instructions to allow calls +across a greater range of addresses. The default is +\&\fB\-\-no\-longcalls\fR. .SH "SEE ALSO" .IX Header "SEE ALSO" \&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR. @@ -856,4 +967,4 @@ under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the -section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". +section entitled ``\s-1GNU\s0 Free Documentation License''. |
