diff options
Diffstat (limited to 'contrib/binutils/bfd/doc/reloc.texi')
| -rw-r--r-- | contrib/binutils/bfd/doc/reloc.texi | 443 |
1 files changed, 381 insertions, 62 deletions
diff --git a/contrib/binutils/bfd/doc/reloc.texi b/contrib/binutils/bfd/doc/reloc.texi index 1ebd430..9253a33 100644 --- a/contrib/binutils/bfd/doc/reloc.texi +++ b/contrib/binutils/bfd/doc/reloc.texi @@ -60,7 +60,7 @@ typedef enum bfd_reloc_status typedef struct reloc_cache_entry @{ /* A pointer into the canonical table of pointers. */ - struct symbol_cache_entry **sym_ptr_ptr; + struct bfd_symbol **sym_ptr_ptr; /* offset in section. */ bfd_size_type address; @@ -84,15 +84,16 @@ Here is a description of each of the fields within an @code{arelent}: @code{sym_ptr_ptr} @end itemize The symbol table pointer points to a pointer to the symbol -associated with the relocation request. It is -the pointer into the table returned by the back end's -@code{get_symtab} action. @xref{Symbols}. The symbol is referenced -through a pointer to a pointer so that tools like the linker -can fix up all the symbols of the same name by modifying only -one pointer. The relocation routine looks in the symbol and -uses the base of the section the symbol is attached to and the -value of the symbol as the initial relocation offset. If the -symbol pointer is zero, then the section provided is looked up. +associated with the relocation request. It is the pointer +into the table returned by the back end's +@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is +referenced through a pointer to a pointer so that tools like +the linker can fix up all the symbols of the same name by +modifying only one pointer. The relocation routine looks in +the symbol and uses the base of the section the symbol is +attached to and the value of the symbol as the initial +relocation offset. If the symbol pointer is zero, then the +section provided is looked up. @itemize @bullet @@ -254,7 +255,7 @@ information that libbfd needs to know to tie up a back end's data. @example -struct symbol_cache_entry; /* Forward declaration. */ +struct bfd_symbol; /* Forward declaration. */ struct reloc_howto_struct @{ @@ -283,7 +284,7 @@ struct reloc_howto_struct data section of the addend. The relocation function will subtract from the relocation value the address of the location being relocated. */ - boolean pc_relative; + bfd_boolean pc_relative; /* The bit position of the reloc value in the destination. The relocated value is left shifted by this amount. */ @@ -295,11 +296,11 @@ struct reloc_howto_struct /* If this field is non null, then the supplied function is called rather than the normal function. This allows really - strange relocation methods to be accomodated (e.g., i960 callj + strange relocation methods to be accommodated (e.g., i960 callj instructions). */ bfd_reloc_status_type (*special_function) - PARAMS ((bfd *, arelent *, struct symbol_cache_entry *, PTR, asection *, - bfd *, char **)); + (bfd *, arelent *, struct bfd_symbol *, void *, asection *, + bfd *, char **); /* The textual name of the relocation type. */ char *name; @@ -319,21 +320,20 @@ struct reloc_howto_struct USE_REL targets set this field to TRUE. Why this is so is peculiar to each particular target. For relocs that aren't used in partial links (e.g. GOT stuff) it doesn't matter what this is set to. */ - boolean partial_inplace; - - /* The src_mask selects which parts of the read in data - are to be used in the relocation sum. E.g., if this was an 8 bit - byte of data which we read and relocated, this would be - 0x000000ff. When we have relocs which have an addend, such as - sun4 extended relocs, the value in the offset part of a - relocating field is garbage so we never use it. In this case - the mask would be 0x00000000. */ + bfd_boolean partial_inplace; + + /* src_mask selects the part of the instruction (or data) to be used + in the relocation sum. If the target relocations don't have an + addend in the reloc, eg. ELF USE_REL, src_mask will normally equal + dst_mask to extract the addend from the section contents. If + relocations do have an addend in the reloc, eg. ELF USE_RELA, this + field should be zero. Non-zero values for ELF USE_RELA targets are + bogus as in those cases the value in the dst_mask part of the + section contents should be treated as garbage. */ bfd_vma src_mask; - /* The dst_mask selects which parts of the instruction are replaced - into the instruction. In most cases src_mask == dst_mask, - except in the above special case, where dst_mask would be - 0x000000ff, and src_mask would be 0x00000000. */ + /* dst_mask selects which parts of the instruction (or data) are + replaced with a relocated value. */ bfd_vma dst_mask; /* When some formats create PC relative instructions, they leave @@ -342,7 +342,7 @@ struct reloc_howto_struct be made just by adding in an ordinary offset (e.g., sun3 a.out). Some formats leave the displacement part of an instruction empty (e.g., m88k bcs); this flag signals the fact. */ - boolean pcrel_offset; + bfd_boolean pcrel_offset; @}; @end example @@ -361,7 +361,7 @@ moment, we are compatible, so do it this way. @example #define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \ HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \ - NAME, false, 0, 0, IN) + NAME, FALSE, 0, 0, IN) @end example @@ -369,8 +369,8 @@ moment, we are compatible, so do it this way. This is used to fill in an empty howto entry in an array. @example #define EMPTY_HOWTO(C) \ - HOWTO ((C), 0, 0, 0, false, 0, complain_overflow_dont, NULL, \ - NULL, false, 0, 0, false) + HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \ + NULL, FALSE, 0, 0, FALSE) @end example @@ -379,7 +379,7 @@ Helper routine to turn a symbol into a relocation value. @example #define HOWTO_PREPARE(relocation, symbol) \ @{ \ - if (symbol != (asymbol *) NULL) \ + if (symbol != NULL) \ @{ \ if (bfd_is_com_section (symbol->section)) \ @{ \ @@ -422,8 +422,7 @@ arelent_chain; @subsubsection @code{bfd_check_overflow} @strong{Synopsis} @example -bfd_reloc_status_type -bfd_check_overflow +bfd_reloc_status_type bfd_check_overflow (enum complain_overflow how, unsigned int bitsize, unsigned int rightshift, @@ -441,11 +440,10 @@ Perform overflow checking on @var{relocation} which has @subsubsection @code{bfd_perform_relocation} @strong{Synopsis} @example -bfd_reloc_status_type -bfd_perform_relocation +bfd_reloc_status_type bfd_perform_relocation (bfd *abfd, arelent *reloc_entry, - PTR data, + void *data, asection *input_section, bfd *output_bfd, char **error_message); @@ -470,11 +468,10 @@ this return @code{bfd_reloc_dangerous}. @subsubsection @code{bfd_install_relocation} @strong{Synopsis} @example -bfd_reloc_status_type -bfd_install_relocation +bfd_reloc_status_type bfd_install_relocation (bfd *abfd, arelent *reloc_entry, - PTR data, bfd_vma data_start, + void *data, bfd_vma data_start, asection *input_section, char **error_message); @end example @@ -647,6 +644,32 @@ SPARC64 relocations @deffn {} BFD_RELOC_SPARC_REV32 SPARC little endian relocation @end deffn +@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 +@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 +@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD +@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL +@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 +@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 +@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD +@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL +@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 +@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 +@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD +@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 +@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 +@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD +@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX +@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD +@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 +@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 +@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 +@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 +@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 +@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 +@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 +@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 +SPARC TLS relocations +@end deffn @deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 Alpha ECOFF and ELF relocations. Some of these treat the symbol or "addend" in some special way. @@ -713,7 +736,7 @@ GP register. @end deffn @deffn {} BFD_RELOC_ALPHA_BRSGP Like BFD_RELOC_23_PCREL_S2, except that the source and target must -share a common GP, and the target address is adjusted for +share a common GP, and the target address is adjusted for STO_ALPHA_STD_GPLOAD. @end deffn @deffn {} BFD_RELOC_ALPHA_TLSGD @@ -783,6 +806,8 @@ Relocation against a MIPS literal section. @deffnx {} BFD_RELOC_MIPS_REL16 @deffnx {} BFD_RELOC_MIPS_RELGOT @deffnx {} BFD_RELOC_MIPS_JALR +MIPS ELF relocations. +@end deffn @deffn {} BFD_RELOC_FRV_LABEL16 @deffnx {} BFD_RELOC_FRV_LABEL24 @deffnx {} BFD_RELOC_FRV_LO16 @@ -792,9 +817,48 @@ Relocation against a MIPS literal section. @deffnx {} BFD_RELOC_FRV_GPREL32 @deffnx {} BFD_RELOC_FRV_GPRELHI @deffnx {} BFD_RELOC_FRV_GPRELLO +@deffnx {} BFD_RELOC_FRV_GOT12 +@deffnx {} BFD_RELOC_FRV_GOTHI +@deffnx {} BFD_RELOC_FRV_GOTLO +@deffnx {} BFD_RELOC_FRV_FUNCDESC +@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 +@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI +@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO +@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE +@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 +@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI +@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO +@deffnx {} BFD_RELOC_FRV_GOTOFF12 +@deffnx {} BFD_RELOC_FRV_GOTOFFHI +@deffnx {} BFD_RELOC_FRV_GOTOFFLO Fujitsu Frv Relocations. @end deffn -MIPS ELF relocations. +@deffn {} BFD_RELOC_MN10300_GOTOFF24 +This is a 24bit GOT-relative reloc for the mn10300. +@end deffn +@deffn {} BFD_RELOC_MN10300_GOT32 +This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes +in the instruction. +@end deffn +@deffn {} BFD_RELOC_MN10300_GOT24 +This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes +in the instruction. +@end deffn +@deffn {} BFD_RELOC_MN10300_GOT16 +This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes +in the instruction. +@end deffn +@deffn {} BFD_RELOC_MN10300_COPY +Copy symbol at runtime. +@end deffn +@deffn {} BFD_RELOC_MN10300_GLOB_DAT +Create GOT entry. +@end deffn +@deffn {} BFD_RELOC_MN10300_JMP_SLOT +Create PLT entry. +@end deffn +@deffn {} BFD_RELOC_MN10300_RELATIVE +Adjust by program base. @end deffn @deffn {} BFD_RELOC_386_GOT32 @deffnx {} BFD_RELOC_386_PLT32 @@ -826,6 +890,14 @@ i386/elf relocations @deffnx {} BFD_RELOC_X86_64_RELATIVE @deffnx {} BFD_RELOC_X86_64_GOTPCREL @deffnx {} BFD_RELOC_X86_64_32S +@deffnx {} BFD_RELOC_X86_64_DTPMOD64 +@deffnx {} BFD_RELOC_X86_64_DTPOFF64 +@deffnx {} BFD_RELOC_X86_64_TPOFF64 +@deffnx {} BFD_RELOC_X86_64_TLSGD +@deffnx {} BFD_RELOC_X86_64_TLSLD +@deffnx {} BFD_RELOC_X86_64_DTPOFF32 +@deffnx {} BFD_RELOC_X86_64_GOTTPOFF +@deffnx {} BFD_RELOC_X86_64_TPOFF32 x86-64/elf relocations @end deffn @deffn {} BFD_RELOC_NS32K_IMM_8 @@ -909,11 +981,53 @@ Picojava relocs. Not all of these appear in object files. @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS Power(rs6000) and PowerPC relocations. @end deffn +@deffn {} BFD_RELOC_PPC_TLS +@deffnx {} BFD_RELOC_PPC_DTPMOD +@deffnx {} BFD_RELOC_PPC_TPREL16 +@deffnx {} BFD_RELOC_PPC_TPREL16_LO +@deffnx {} BFD_RELOC_PPC_TPREL16_HI +@deffnx {} BFD_RELOC_PPC_TPREL16_HA +@deffnx {} BFD_RELOC_PPC_TPREL +@deffnx {} BFD_RELOC_PPC_DTPREL16 +@deffnx {} BFD_RELOC_PPC_DTPREL16_LO +@deffnx {} BFD_RELOC_PPC_DTPREL16_HI +@deffnx {} BFD_RELOC_PPC_DTPREL16_HA +@deffnx {} BFD_RELOC_PPC_DTPREL +@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 +@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO +@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI +@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA +@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 +@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO +@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI +@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA +@deffnx {} BFD_RELOC_PPC_GOT_TPREL16 +@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO +@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI +@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA +@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 +@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO +@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI +@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA +@deffnx {} BFD_RELOC_PPC64_TPREL16_DS +@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS +@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER +@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA +@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST +@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA +@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS +@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS +@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER +@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA +@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST +@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA +PowerPC and PowerPC64 thread-local storage relocations. +@end deffn @deffn {} BFD_RELOC_I370_D12 IBM 370/390 relocations @end deffn @deffn {} BFD_RELOC_CTOR -The type of reloc used to build a contructor table - at the moment +The type of reloc used to build a constructor table - at the moment probably a 32 bit wide absolute relocation, but the target can choose. It generally does map to one of the other relocation types. @end deffn @@ -938,6 +1052,7 @@ field in the instruction. @deffnx {} BFD_RELOC_ARM_SWI @deffnx {} BFD_RELOC_ARM_MULTI @deffnx {} BFD_RELOC_ARM_CP_OFF_IMM +@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 @deffnx {} BFD_RELOC_ARM_ADR_IMM @deffnx {} BFD_RELOC_ARM_LDR_IMM @deffnx {} BFD_RELOC_ARM_LITERAL @@ -1034,7 +1149,15 @@ These relocs are only used within the ARM assembler. They are not @deffnx {} BFD_RELOC_SH_IMM_HI16 @deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL @deffnx {} BFD_RELOC_SH_PT_16 -Hitachi SH relocs. Not all of these appear in object files. +@deffnx {} BFD_RELOC_SH_TLS_GD_32 +@deffnx {} BFD_RELOC_SH_TLS_LD_32 +@deffnx {} BFD_RELOC_SH_TLS_LDO_32 +@deffnx {} BFD_RELOC_SH_TLS_IE_32 +@deffnx {} BFD_RELOC_SH_TLS_LE_32 +@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 +@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 +@deffnx {} BFD_RELOC_SH_TLS_TPOFF32 +Renesas / SuperH SH relocs. Not all of these appear in object files. @end deffn @deffn {} BFD_RELOC_THUMB_PCREL_BRANCH9 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 @@ -1131,7 +1254,7 @@ DLX relocs DLX relocs @end deffn @deffn {} BFD_RELOC_M32R_24 -Mitsubishi M32R relocs. +Renesas M32R (formerly Mitsubishi M32R) relocs. This is a 24 bit absolute address. @end deffn @deffn {} BFD_RELOC_M32R_10_PCREL @@ -1158,6 +1281,22 @@ This is a 16-bit reloc containing the lower 16 bits of an address. This is a 16-bit reloc containing the small data area offset for use in add3, load, and store instructions. @end deffn +@deffn {} BFD_RELOC_M32R_GOT24 +@deffnx {} BFD_RELOC_M32R_26_PLTREL +@deffnx {} BFD_RELOC_M32R_COPY +@deffnx {} BFD_RELOC_M32R_GLOB_DAT +@deffnx {} BFD_RELOC_M32R_JMP_SLOT +@deffnx {} BFD_RELOC_M32R_RELATIVE +@deffnx {} BFD_RELOC_M32R_GOTOFF +@deffnx {} BFD_RELOC_M32R_GOTPC24 +@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO +@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO +@deffnx {} BFD_RELOC_M32R_GOT16_LO +@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO +@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO +@deffnx {} BFD_RELOC_M32R_GOTPC_LO +For PIC. +@end deffn @deffn {} BFD_RELOC_V850_9_PCREL This is a 9-bit reloc @end deffn @@ -1201,11 +1340,11 @@ This is a 4 bit offset from the tiny data area pointer. @end deffn @deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET This is a 16 bit offset from the short data area pointer, with the -bits placed non-contigously in the instruction. +bits placed non-contiguously in the instruction. @end deffn @deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET This is a 16 bit offset from the zero data area pointer, with the -bits placed non-contigously in the instruction. +bits placed non-contiguously in the instruction. @end deffn @deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET This is a 6 bit offset from the call table base pointer. @@ -1213,6 +1352,15 @@ This is a 6 bit offset from the call table base pointer. @deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET This is a 16 bit offset from the call table base pointer. @end deffn +@deffn {} BFD_RELOC_V850_LONGCALL +Used for relaxing indirect function calls. +@end deffn +@deffn {} BFD_RELOC_V850_LONGJUMP +Used for relaxing indirect jumps. +@end deffn +@deffn {} BFD_RELOC_V850_ALIGN +Used to maintain alignment whilst relaxing. +@end deffn @deffn {} BFD_RELOC_MN10300_32_PCREL This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the instruction. @@ -1305,6 +1453,7 @@ These are relocations for a conditional branch instruction. @deffnx {} BFD_RELOC_MMIX_PUSHJ_1 @deffnx {} BFD_RELOC_MMIX_PUSHJ_2 @deffnx {} BFD_RELOC_MMIX_PUSHJ_3 +@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE These are relocations for the PUSHJ instruction. @end deffn @deffn {} BFD_RELOC_MMIX_JMP @@ -1455,6 +1604,95 @@ PC relative 32 bit shifted by 1. @deffn {} BFD_RELOC_390_GOTENT 32 bit rel. offset to GOT entry. @end deffn +@deffn {} BFD_RELOC_390_GOTOFF64 +64 bit offset to GOT. +@end deffn +@deffn {} BFD_RELOC_390_GOTPLT12 +12-bit offset to symbol-entry within GOT, with PLT handling. +@end deffn +@deffn {} BFD_RELOC_390_GOTPLT16 +16-bit offset to symbol-entry within GOT, with PLT handling. +@end deffn +@deffn {} BFD_RELOC_390_GOTPLT32 +32-bit offset to symbol-entry within GOT, with PLT handling. +@end deffn +@deffn {} BFD_RELOC_390_GOTPLT64 +64-bit offset to symbol-entry within GOT, with PLT handling. +@end deffn +@deffn {} BFD_RELOC_390_GOTPLTENT +32-bit rel. offset to symbol-entry within GOT, with PLT handling. +@end deffn +@deffn {} BFD_RELOC_390_PLTOFF16 +16-bit rel. offset from the GOT to a PLT entry. +@end deffn +@deffn {} BFD_RELOC_390_PLTOFF32 +32-bit rel. offset from the GOT to a PLT entry. +@end deffn +@deffn {} BFD_RELOC_390_PLTOFF64 +64-bit rel. offset from the GOT to a PLT entry. +@end deffn +@deffn {} BFD_RELOC_390_TLS_LOAD +@deffnx {} BFD_RELOC_390_TLS_GDCALL +@deffnx {} BFD_RELOC_390_TLS_LDCALL +@deffnx {} BFD_RELOC_390_TLS_GD32 +@deffnx {} BFD_RELOC_390_TLS_GD64 +@deffnx {} BFD_RELOC_390_TLS_GOTIE12 +@deffnx {} BFD_RELOC_390_TLS_GOTIE32 +@deffnx {} BFD_RELOC_390_TLS_GOTIE64 +@deffnx {} BFD_RELOC_390_TLS_LDM32 +@deffnx {} BFD_RELOC_390_TLS_LDM64 +@deffnx {} BFD_RELOC_390_TLS_IE32 +@deffnx {} BFD_RELOC_390_TLS_IE64 +@deffnx {} BFD_RELOC_390_TLS_IEENT +@deffnx {} BFD_RELOC_390_TLS_LE32 +@deffnx {} BFD_RELOC_390_TLS_LE64 +@deffnx {} BFD_RELOC_390_TLS_LDO32 +@deffnx {} BFD_RELOC_390_TLS_LDO64 +@deffnx {} BFD_RELOC_390_TLS_DTPMOD +@deffnx {} BFD_RELOC_390_TLS_DTPOFF +@deffnx {} BFD_RELOC_390_TLS_TPOFF +s390 tls relocations. +@end deffn +@deffn {} BFD_RELOC_390_20 +@deffnx {} BFD_RELOC_390_GOT20 +@deffnx {} BFD_RELOC_390_GOTPLT20 +@deffnx {} BFD_RELOC_390_TLS_GOTIE20 +Long displacement extension. +@end deffn +@deffn {} BFD_RELOC_IP2K_FR9 +Scenix IP2K - 9-bit register number / data address +@end deffn +@deffn {} BFD_RELOC_IP2K_BANK +Scenix IP2K - 4-bit register/data bank number +@end deffn +@deffn {} BFD_RELOC_IP2K_ADDR16CJP +Scenix IP2K - low 13 bits of instruction word address +@end deffn +@deffn {} BFD_RELOC_IP2K_PAGE3 +Scenix IP2K - high 3 bits of instruction word address +@end deffn +@deffn {} BFD_RELOC_IP2K_LO8DATA +@deffnx {} BFD_RELOC_IP2K_HI8DATA +@deffnx {} BFD_RELOC_IP2K_EX8DATA +Scenix IP2K - ext/low/high 8 bits of data address +@end deffn +@deffn {} BFD_RELOC_IP2K_LO8INSN +@deffnx {} BFD_RELOC_IP2K_HI8INSN +Scenix IP2K - low/high 8 bits of instruction word address +@end deffn +@deffn {} BFD_RELOC_IP2K_PC_SKIP +Scenix IP2K - even/odd PC modifier to modify snb pcl.0 +@end deffn +@deffn {} BFD_RELOC_IP2K_TEXT +Scenix IP2K - 16 bit word address in text section. +@end deffn +@deffn {} BFD_RELOC_IP2K_FR_OFFSET +Scenix IP2K - 7-bit sp or dp offset +@end deffn +@deffn {} BFD_RELOC_VPE4KMATH_DATA +@deffnx {} BFD_RELOC_VPE4KMATH_INSN +Scenix VPE4K coprocessor - data/insn-space addressing +@end deffn @deffn {} BFD_RELOC_VTABLE_INHERIT @deffnx {} BFD_RELOC_VTABLE_ENTRY These two relocations are used by the linker to determine which of @@ -1464,7 +1702,7 @@ that are not used, so that the code for those functions need not be included in the output. VTABLE_INHERIT is a zero-space relocation used to describe to the -linker the inheritence tree of a C++ virtual function table. The +linker the inheritance tree of a C++ virtual function table. The relocation's symbol should be the parent class' vtable, and the relocation should be located at the child vtable. @@ -1558,15 +1796,50 @@ Intel IA64 Relocations. @end deffn @deffn {} BFD_RELOC_M68HC11_HI8 Motorola 68HC11 reloc. -This is the 8 bits high part of an absolute address. +This is the 8 bit high part of an absolute address. @end deffn @deffn {} BFD_RELOC_M68HC11_LO8 Motorola 68HC11 reloc. -This is the 8 bits low part of an absolute address. +This is the 8 bit low part of an absolute address. @end deffn @deffn {} BFD_RELOC_M68HC11_3B Motorola 68HC11 reloc. -This is the 3 bits of a value. +This is the 3 bit of a value. +@end deffn +@deffn {} BFD_RELOC_M68HC11_RL_JUMP +Motorola 68HC11 reloc. +This reloc marks the beginning of a jump/call instruction. +It is used for linker relaxation to correctly identify beginning +of instruction and change some branches to use PC-relative +addressing mode. +@end deffn +@deffn {} BFD_RELOC_M68HC11_RL_GROUP +Motorola 68HC11 reloc. +This reloc marks a group of several instructions that gcc generates +and for which the linker relaxation pass can modify and/or remove +some of them. +@end deffn +@deffn {} BFD_RELOC_M68HC11_LO16 +Motorola 68HC11 reloc. +This is the 16-bit lower part of an address. It is used for 'call' +instruction to specify the symbol address without any special +transformation (due to memory bank window). +@end deffn +@deffn {} BFD_RELOC_M68HC11_PAGE +Motorola 68HC11 reloc. +This is a 8-bit reloc that specifies the page number of an address. +It is used by 'call' instruction to specify the page number of +the symbol. +@end deffn +@deffn {} BFD_RELOC_M68HC11_24 +Motorola 68HC11 reloc. +This is a 24-bit reloc that represents the address with a 16-bit +value and a 8-bit page number. The symbol address is transformed +to follow the 16K memory bank of 68HC12 (seen as mapped in the window). +@end deffn +@deffn {} BFD_RELOC_M68HC12_5B +Motorola 68HC12 reloc. +This is the 5 bits of a value. @end deffn @deffn {} BFD_RELOC_CRIS_BDISP8 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 @@ -1649,6 +1922,7 @@ OpenRISC Relocations. H8 elf Relocations. @end deffn @deffn {} BFD_RELOC_XSTORMY16_REL_12 +@deffnx {} BFD_RELOC_XSTORMY16_12 @deffnx {} BFD_RELOC_XSTORMY16_24 @deffnx {} BFD_RELOC_XSTORMY16_FPTR16 Sony Xstormy16 Relocations. @@ -1658,6 +1932,50 @@ Sony Xstormy16 Relocations. @deffnx {} BFD_RELOC_VAX_RELATIVE Relocations used by VAX ELF. @end deffn +@deffn {} BFD_RELOC_MSP430_10_PCREL +@deffnx {} BFD_RELOC_MSP430_16_PCREL +@deffnx {} BFD_RELOC_MSP430_16 +@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE +@deffnx {} BFD_RELOC_MSP430_16_BYTE +msp430 specific relocation codes +@end deffn +@deffn {} BFD_RELOC_IQ2000_OFFSET_16 +@deffnx {} BFD_RELOC_IQ2000_OFFSET_21 +@deffnx {} BFD_RELOC_IQ2000_UHI16 +IQ2000 Relocations. +@end deffn +@deffn {} BFD_RELOC_XTENSA_RTLD +Special Xtensa relocation used only by PLT entries in ELF shared +objects to indicate that the runtime linker should set the value +to one of its own internal functions or data structures. +@end deffn +@deffn {} BFD_RELOC_XTENSA_GLOB_DAT +@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT +@deffnx {} BFD_RELOC_XTENSA_RELATIVE +Xtensa relocations for ELF shared objects. +@end deffn +@deffn {} BFD_RELOC_XTENSA_PLT +Xtensa relocation used in ELF object files for symbols that may require +PLT entries. Otherwise, this is just a generic 32-bit relocation. +@end deffn +@deffn {} BFD_RELOC_XTENSA_OP0 +@deffnx {} BFD_RELOC_XTENSA_OP1 +@deffnx {} BFD_RELOC_XTENSA_OP2 +Generic Xtensa relocations. Only the operand number is encoded +in the relocation. The details are determined by extracting the +instruction opcode. +@end deffn +@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND +Xtensa relocation to mark that the assembler expanded the +instructions from an original target. The expansion size is +encoded in the reloc size. +@end deffn +@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY +Xtensa relocation to mark that the linker should simplify +assembler-expanded instructions. This is commonly used +internally by the linker after analysis of a +BFD_RELOC_XTENSA_ASM_EXPAND. +@end deffn @example @@ -1667,8 +1985,8 @@ typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; @subsubsection @code{bfd_reloc_type_lookup} @strong{Synopsis} @example -reloc_howto_type * -bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code); +reloc_howto_type *bfd_reloc_type_lookup + (bfd *abfd, bfd_reloc_code_real_type code); @end example @strong{Description}@* Return a pointer to a howto structure which, when @@ -1699,21 +2017,22 @@ Useful mainly for printing error messages. @subsubsection @code{bfd_generic_relax_section} @strong{Synopsis} @example -boolean bfd_generic_relax_section +bfd_boolean bfd_generic_relax_section (bfd *abfd, asection *section, struct bfd_link_info *, - boolean *); + bfd_boolean *); @end example @strong{Description}@* Provides default handling for relaxing for back ends which -don't do relaxing -- i.e., does nothing. +don't do relaxing -- i.e., does nothing except make sure that the +final size of the section is set. @findex bfd_generic_gc_sections @subsubsection @code{bfd_generic_gc_sections} @strong{Synopsis} @example -boolean bfd_generic_gc_sections +bfd_boolean bfd_generic_gc_sections (bfd *, struct bfd_link_info *); @end example @strong{Description}@* @@ -1724,7 +2043,7 @@ don't do section gc -- i.e., does nothing. @subsubsection @code{bfd_generic_merge_sections} @strong{Synopsis} @example -boolean bfd_generic_merge_sections +bfd_boolean bfd_generic_merge_sections (bfd *, struct bfd_link_info *); @end example @strong{Description}@* @@ -1735,12 +2054,12 @@ which don't have SEC_MERGE support -- i.e., does nothing. @subsubsection @code{bfd_generic_get_relocated_section_contents} @strong{Synopsis} @example -bfd_byte * -bfd_generic_get_relocated_section_contents (bfd *abfd, +bfd_byte *bfd_generic_get_relocated_section_contents + (bfd *abfd, struct bfd_link_info *link_info, struct bfd_link_order *link_order, bfd_byte *data, - boolean relocateable, + bfd_boolean relocatable, asymbol **symbols); @end example @strong{Description}@* |
