diff options
630 files changed, 54647 insertions, 18925 deletions
@@ -197,7 +197,7 @@ _MAKE+= MK_META_MODE=no _TARGET_ARCH= ${TARGET:S/pc98/i386/:S/arm64/aarch64/} .elif !defined(TARGET) && defined(TARGET_ARCH) && \ ${TARGET_ARCH} != ${MACHINE_ARCH} -_TARGET= ${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb|hf)?/arm/:C/aarch64/arm64/:C/powerpc64/powerpc/:C/riscv64/riscv/} +_TARGET= ${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb)?/arm/:C/aarch64/arm64/:C/powerpc64/powerpc/:C/riscv64/riscv/} .endif .if defined(TARGET) && !defined(_TARGET) _TARGET=${TARGET} @@ -374,7 +374,7 @@ worlds: .if make(universe) || make(universe_kernels) || make(tinderbox) || make(targets) TARGETS?=amd64 arm arm64 i386 mips pc98 powerpc sparc64 _UNIVERSE_TARGETS= ${TARGETS} -TARGET_ARCHES_arm?= arm armeb armv6 armv6hf +TARGET_ARCHES_arm?= arm armeb armv6 TARGET_ARCHES_arm64?= aarch64 TARGET_ARCHES_mips?= mipsel mips mips64el mips64 mipsn32 TARGET_ARCHES_powerpc?= powerpc powerpc64 diff --git a/Makefile.inc1 b/Makefile.inc1 index 3fa5537..36134f5 100644 --- a/Makefile.inc1 +++ b/Makefile.inc1 @@ -219,14 +219,13 @@ KNOWN_ARCHES?= aarch64/arm64 \ arm \ armeb/arm \ armv6/arm \ - armv6hf/arm \ i386 \ i386/pc98 \ mips \ mipsel/mips \ mips64el/mips \ - mips64/mips \ mipsn32el/mips \ + mips64/mips \ mipsn32/mips \ powerpc \ powerpc64/powerpc \ @@ -461,7 +460,7 @@ BFLAGS+= -B${CROSS_BINUTILS_PREFIX} BFLAGS+= -B${WORLDTMP}/usr/bin .endif .if ${TARGET} == "arm" -.if ${TARGET_ARCH:M*hf*} != "" +.if ${TARGET_ARCH:Marmv6*} != "" && ${TARGET_CPUTYPE:M*soft*} == "" TARGET_ABI= gnueabihf .else TARGET_ABI= gnueabi @@ -976,27 +975,19 @@ packageworld: .PHONY # and do a 'make reinstall' on the *client* to install new binaries from the # most recent server build. # -reinstall: .MAKE .PHONY +restage reinstall: .MAKE .PHONY @echo "--------------------------------------------------------------" @echo ">>> Making hierarchy" @echo "--------------------------------------------------------------" ${_+_}cd ${.CURDIR}; ${MAKE} -f Makefile.inc1 \ LOCAL_MTREE=${LOCAL_MTREE:Q} hierarchy - @echo +.if make(restage) @echo "--------------------------------------------------------------" - @echo ">>> Installing everything" - @echo "--------------------------------------------------------------" - ${_+_}cd ${.CURDIR}; ${MAKE} -f Makefile.inc1 install -.if defined(LIBCOMPAT) - ${_+_}cd ${.CURDIR}; ${MAKE} -f Makefile.inc1 install${libcompat} -.endif - -restage: .MAKE .PHONY - @echo "--------------------------------------------------------------" - @echo ">>> Making hierarchy" + @echo ">>> Making distribution" @echo "--------------------------------------------------------------" ${_+_}cd ${.CURDIR}; ${MAKE} -f Makefile.inc1 \ - LOCAL_MTREE=${LOCAL_MTREE:Q} hierarchy distribution + LOCAL_MTREE=${LOCAL_MTREE:Q} distribution +.endif @echo @echo "--------------------------------------------------------------" @echo ">>> Installing everything" diff --git a/ObsoleteFiles.inc b/ObsoleteFiles.inc index 84cd328..3a70a50 100644 --- a/ObsoleteFiles.inc +++ b/ObsoleteFiles.inc @@ -38,6 +38,8 @@ # xargs -n1 | sort | uniq -d; # done +# 20160517: ReiserFS removed +OLD_FILES+=usr/share/man/man5/reiserfs.5.gz # 20160430: kvm_getfiles(3) removed from kvm(3) OLD_LIBS+=usr/lib/libkvm.so.6 OLD_FILES+=usr/share/man/man3/kvm_getfiles.3.gz @@ -45,8 +45,6 @@ crypto Cryptography stuff (see crypto/README). etc Template files for /etc. -games Amusements. - gnu Various commands and libraries under the GNU Public License. Please see gnu/COPYING* for more information. @@ -31,6 +31,14 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW: disable the most expensive debugging functionality run "ln -s 'abort:false,junk:false' /etc/malloc.conf".) +20160517: + The armv6 port now defaults to hard float ABI. Limited support + for running both hardfloat and soft float on the same system + is available using the libraries installed with -DWITH_LIBSOFT. + This has only been tested as an upgrade path for installworld + and packages may fail or need manual intervention to run. New + packages will be needed. + 20160510: Kernel modules compiled outside of a kernel build now default to installing to /boot/modules instead of /boot/kernel. Many kernel diff --git a/contrib/bsnmp/snmpd/main.c b/contrib/bsnmp/snmpd/main.c index 06df31d..ea87127 100644 --- a/contrib/bsnmp/snmpd/main.c +++ b/contrib/bsnmp/snmpd/main.c @@ -1169,7 +1169,7 @@ recv_dgram(struct port_input *pi, struct in_addr *laddr) memcpy(laddr, CMSG_DATA(cmsg), sizeof(struct in_addr)); if (cmsg->cmsg_level == SOL_SOCKET && cmsg->cmsg_type == SCM_CREDS) - memcpy(cred, CMSG_DATA(cmsg), sizeof(struct sockcred)); + cred = (struct sockcred *)CMSG_DATA(cmsg); } if (pi->cred) @@ -1207,7 +1207,7 @@ snmpd_input(struct port_input *pi, struct tport *tport) ret = recv_stream(pi); } else { - struct in_addr laddr; + struct in_addr *laddr; memset(cbuf, 0, CMSG_SPACE(sizeof(struct in_addr))); msg.msg_control = cbuf; @@ -1216,11 +1216,11 @@ snmpd_input(struct port_input *pi, struct tport *tport) cmsgp->cmsg_len = CMSG_LEN(sizeof(struct in_addr)); cmsgp->cmsg_level = IPPROTO_IP; cmsgp->cmsg_type = IP_SENDSRCADDR; - memcpy(&laddr, CMSG_DATA(cmsgp), sizeof(struct in_addr)); + laddr = (struct in_addr *)CMSG_DATA(cmsgp); - ret = recv_dgram(pi, &laddr); + ret = recv_dgram(pi, laddr); - if (laddr.s_addr == 0) { + if (laddr->s_addr == 0) { msg.msg_control = NULL; msg.msg_controllen = 0; } diff --git a/contrib/groff/tmac/doc-syms b/contrib/groff/tmac/doc-syms index e89b658..84f2a4f 100644 --- a/contrib/groff/tmac/doc-syms +++ b/contrib/groff/tmac/doc-syms @@ -659,6 +659,8 @@ .as doc-str-St--susv2 " (\*[Lq]\*[doc-Tn-font-size]SUSv2\*[doc-str-St]\*[Rq]) .ds doc-str-St--susv3 Version\~3 of the Single \*[doc-Tn-font-size]UNIX\*[doc-str-St] Specification .as doc-str-St--susv3 " (\*[Lq]\*[doc-Tn-font-size]SUSv3\*[doc-str-St]\*[Rq]) +.ds doc-str-St--susv4 Version\~4 of the Single \*[doc-Tn-font-size]UNIX\*[doc-str-St] Specification +.as doc-str-St--susv4 " (\*[Lq]\*[doc-Tn-font-size]SUSv4\*[doc-str-St]\*[Rq]) .ds doc-str-St--svid4 System\~V Interface Definition, Fourth Edition .as doc-str-St--svid4 " (\*[Lq]\*[doc-Tn-font-size]SVID\*[doc-str-St]\^4\*[Rq]) .ds doc-str-St--xbd5 \*[doc-Tn-font-size]X/Open\*[doc-str-St] Base Definitions Issue\~5 diff --git a/contrib/groff/tmac/groff_mdoc.man b/contrib/groff/tmac/groff_mdoc.man index b9d0c36..98943a6 100644 --- a/contrib/groff/tmac/groff_mdoc.man +++ b/contrib/groff/tmac/groff_mdoc.man @@ -2097,6 +2097,8 @@ X/Open .St -susv2 .It Li \-susv3 .St -susv3 +.It Li \-susv4 +.St -susv4 .It Li \-svid4 .St -svid4 .It Li \-xbd5 diff --git a/contrib/ipfilter/man/ipf.5 b/contrib/ipfilter/man/ipf.5 index 3e5e9b2..e6b470f 100644 --- a/contrib/ipfilter/man/ipf.5 +++ b/contrib/ipfilter/man/ipf.5 @@ -881,7 +881,7 @@ through without needing to explicitly allow all fragment body packets. An example of how this is done is as follows: .PP .nf -pass in proto udp from any prot = 2049 to any with frags keep fags +pass in proto udp from any port = 2049 to any with frags keep frags .fi .SH Building a tree of rules .PP diff --git a/etc/ntp/leap-seconds b/etc/ntp/leap-seconds index 79d8e15..4fab58f 100644 --- a/etc/ntp/leap-seconds +++ b/etc/ntp/leap-seconds @@ -130,7 +130,7 @@ # Washington, DC # jeffrey.prillaman@usno.navy.mil # -# Last Update of leap second values: 31 Dec 2015 +# Last Update of leap second values: 11 Jan 2016 # # The following line shows this last update date in NTP timestamp # format. This is the date on which the most recent change to @@ -138,7 +138,7 @@ # be identified by the unique pair of characters in the first two # columns as shown below. # -#$ 3660508800 +#$ 3661459200 # # The data in this file will be updated periodically as new leap # seconds are announced. In addition to being entered on the line @@ -170,10 +170,10 @@ # current -- the update time stamp, the data and the name of the file # will not change. # -# Updated through IERS Bulletin C 50 -# File expires on: 1 Jun 2016 +# Updated through IERS Bulletin C 51 +# File expires on: 1 Dec 2016 # -#@ 3673728000 +#@ 3689539200 # 2272060800 10 # 1 Jan 1972 2287785600 11 # 1 Jul 1972 @@ -217,5 +217,5 @@ # the hash line is also ignored in the # computation. # -#h 44a44c49 35b22601 a9c7054c 8c56cf57 9b6f6ed5 +#h 63b4df04 0907d94f 2dadb7a1 684f7767 2a372421 # diff --git a/gnu/usr.bin/binutils/Makefile.inc0 b/gnu/usr.bin/binutils/Makefile.inc0 index a053f5f..28062d5 100644 --- a/gnu/usr.bin/binutils/Makefile.inc0 +++ b/gnu/usr.bin/binutils/Makefile.inc0 @@ -7,7 +7,7 @@ VERSION= "2.17.50 [FreeBSD] 2007-07-03" .if defined(TARGET_ARCH) -TARGET_CPUARCH=${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb|hf)?/arm/:C/powerpc64/powerpc/} +TARGET_CPUARCH=${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb)?/arm/:C/powerpc64/powerpc/} .else TARGET_CPUARCH=${MACHINE_CPUARCH} .endif diff --git a/gnu/usr.bin/cc/Makefile.tgt b/gnu/usr.bin/cc/Makefile.tgt index ee5a794..63be261 100644 --- a/gnu/usr.bin/cc/Makefile.tgt +++ b/gnu/usr.bin/cc/Makefile.tgt @@ -4,7 +4,7 @@ # MACHINE_CPUARCH, but there's no easy way to export make functions... .if defined(TARGET_ARCH) -TARGET_CPUARCH=${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb|hf)?/arm/:C/powerpc64/powerpc/} +TARGET_CPUARCH=${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb)?/arm/:C/powerpc64/powerpc/} .else TARGET_CPUARCH=${MACHINE_CPUARCH} .endif diff --git a/gnu/usr.bin/gdb/Makefile.inc b/gnu/usr.bin/gdb/Makefile.inc index a27051c..34dc907 100644 --- a/gnu/usr.bin/gdb/Makefile.inc +++ b/gnu/usr.bin/gdb/Makefile.inc @@ -23,7 +23,7 @@ OBJ_RL= ${OBJ_ROOT}/../lib/libreadline/readline # MACHINE_CPUARCH, but there's no easy way to export make functions... .if defined(TARGET_ARCH) -TARGET_CPUARCH=${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb|hf)?/arm/:C/powerpc64/powerpc/} +TARGET_CPUARCH=${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb)?/arm/:C/powerpc64/powerpc/} .else TARGET_CPUARCH=${MACHINE_CPUARCH} .endif diff --git a/gnu/usr.bin/gdb/libgdb/Makefile b/gnu/usr.bin/gdb/libgdb/Makefile index 0e28bda..ed00525 100644 --- a/gnu/usr.bin/gdb/libgdb/Makefile +++ b/gnu/usr.bin/gdb/libgdb/Makefile @@ -4,7 +4,7 @@ # MACHINE_CPUARCH, but there's no easy way to export make functions... .if defined(TARGET_ARCH) -TARGET_CPUARCH=${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb|hf)?/arm/:C/powerpc64/powerpc/} +TARGET_CPUARCH=${TARGET_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb)?/arm/:C/powerpc64/powerpc/} .else TARGET_CPUARCH=${MACHINE_CPUARCH} .endif diff --git a/include/pthread.h b/include/pthread.h index 8078bcb..40dca7a 100644 --- a/include/pthread.h +++ b/include/pthread.h @@ -135,6 +135,9 @@ enum pthread_mutextype { #define PTHREAD_MUTEX_DEFAULT PTHREAD_MUTEX_ERRORCHECK +#define PTHREAD_MUTEX_STALLED 0 +#define PTHREAD_MUTEX_ROBUST 1 + struct _pthread_cleanup_info { __uintptr_t pthread_cleanup_pad[8]; }; @@ -229,6 +232,8 @@ int pthread_mutexattr_settype(pthread_mutexattr_t *, int) __nonnull(1); int pthread_mutexattr_setpshared(pthread_mutexattr_t *, int) __nonnull(1); +int pthread_mutex_consistent(pthread_mutex_t *__mutex) + __nonnull(1) __requires_exclusive(*__mutex); int pthread_mutex_destroy(pthread_mutex_t *__mutex) __nonnull(1) __requires_unlocked(*__mutex); int pthread_mutex_init(pthread_mutex_t *__mutex, @@ -310,6 +315,11 @@ int pthread_mutex_setprioceiling(pthread_mutex_t *, int, int *); int pthread_mutexattr_getprotocol(pthread_mutexattr_t *, int *); int pthread_mutexattr_setprotocol(pthread_mutexattr_t *, int); +int pthread_mutexattr_getrobust(pthread_mutexattr_t *__restrict, + int *__restrict) __nonnull_all; +int pthread_mutexattr_setrobust(pthread_mutexattr_t *, int) + __nonnull(1); + int pthread_attr_getinheritsched(const pthread_attr_t *, int *); int pthread_attr_getschedparam(const pthread_attr_t *, struct sched_param *) __nonnull_all; diff --git a/lib/clang/clang.build.mk b/lib/clang/clang.build.mk index 6bc4cdf..a2ee0a5 100644 --- a/lib/clang/clang.build.mk +++ b/lib/clang/clang.build.mk @@ -21,16 +21,19 @@ CFLAGS+= -fno-strict-aliasing TARGET_ARCH?= ${MACHINE_ARCH} BUILD_ARCH?= ${MACHINE_ARCH} -.if ${TARGET_ARCH:Marm*hf*} != "" +# Armv6 uses hard float abi, unless the CPUTYPE has soft in it. +# arm (for armv4 and armv5 CPUs) always uses the soft float ABI. +# For all other targets, we stick with 'unknown'. +.if ${TARGET_ARCH:Marmv6*} && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") TARGET_ABI= gnueabihf -.elif ${TARGET_ARCH:Marm*} != "" +.elif ${TARGET_ARCH:Marm*} TARGET_ABI= gnueabi .else TARGET_ABI= unknown .endif -TARGET_TRIPLE?= ${TARGET_ARCH:C/amd64/x86_64/:C/armv6hf/armv6/:C/arm64/aarch64/}-${TARGET_ABI}-freebsd11.0 -BUILD_TRIPLE?= ${BUILD_ARCH:C/amd64/x86_64/:C/armv6hf/armv6/:C/arm64/aarch64/}-unknown-freebsd11.0 +TARGET_TRIPLE?= ${TARGET_ARCH:C/amd64/x86_64/:C/arm64/aarch64/}-${TARGET_ABI}-freebsd11.0 +BUILD_TRIPLE?= ${BUILD_ARCH:C/amd64/x86_64/:C/arm64/aarch64/}-unknown-freebsd11.0 CFLAGS+= -DLLVM_DEFAULT_TARGET_TRIPLE=\"${TARGET_TRIPLE}\" \ -DLLVM_HOST_TRIPLE=\"${BUILD_TRIPLE}\" \ -DDEFAULT_SYSROOT=\"${TOOLS_PREFIX}\" diff --git a/lib/libbsdstat/bsdstat.c b/lib/libbsdstat/bsdstat.c index 96fba00..564020e 100644 --- a/lib/libbsdstat/bsdstat.c +++ b/lib/libbsdstat/bsdstat.c @@ -53,7 +53,7 @@ bsdstat_setfmt(struct bsdstat *sf, const char *fmt0) "skipped\n", sf->name, tok); continue; } - if (j+3 > (int) sizeof(sf->fmts)) { + if (j+4 > (int) sizeof(sf->fmts)) { fprintf(stderr, "%s: not enough room for all stats; " "stopped at %s\n", sf->name, tok); break; diff --git a/lib/libc/Makefile b/lib/libc/Makefile index 3b72a1b..e511c9b 100644 --- a/lib/libc/Makefile +++ b/lib/libc/Makefile @@ -105,7 +105,8 @@ NOASM= .include "${LIBC_SRCTOP}/rpc/Makefile.inc" .include "${LIBC_SRCTOP}/uuid/Makefile.inc" .include "${LIBC_SRCTOP}/xdr/Makefile.inc" -.if (${LIBC_ARCH} == "arm" && ${MACHINE_ARCH} != "armv6hf") ||\ +.if (${LIBC_ARCH} == "arm" && \ + (${MACHINE_ARCH:Marmv6*} == "" || (defined(CPUTYPE) && ${CPUTYPE:M*soft*}))) || \ ${LIBC_ARCH} == "mips" .include "${LIBC_SRCTOP}/softfloat/Makefile.inc" .endif diff --git a/lib/libc/arm/Makefile.inc b/lib/libc/arm/Makefile.inc index 418f54d..c263ae7 100644 --- a/lib/libc/arm/Makefile.inc +++ b/lib/libc/arm/Makefile.inc @@ -11,7 +11,7 @@ SYM_MAPS+=${LIBC_SRCTOP}/arm/Symbol.map .include "${LIBC_SRCTOP}/arm/aeabi/Makefile.inc" -.if ${MACHINE_ARCH:Marm*hf*} != "" +.if ${MACHINE_ARCH:Marmv6*} && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") SYM_MAPS+=${LIBC_SRCTOP}/arm/Symbol_vfp.map .endif diff --git a/lib/libc/arm/aeabi/Makefile.inc b/lib/libc/arm/aeabi/Makefile.inc index 612e47f..b036db8 100644 --- a/lib/libc/arm/aeabi/Makefile.inc +++ b/lib/libc/arm/aeabi/Makefile.inc @@ -5,13 +5,14 @@ SRCS+= aeabi_atexit.c \ aeabi_unwind_cpp.c \ aeabi_unwind_exidx.c -.if ${MACHINE_ARCH:Marm*hf*} == "" +.if (${MACHINE_ARCH:Marmv6*} && defined(CPUTYPE) && ${CPUTYPE:M*soft*} != "") || \ + ${MACHINE_ARCH:Marmv6*} == "" SRCS+= aeabi_asm_double.S \ aeabi_asm_float.S \ aeabi_double.c \ aeabi_float.c .endif -.if ${MACHINE_ARCH:Marmv6*} +.if ${MACHINE_ARCH:Marmv6*} && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") SRCS+= aeabi_vfp_double.S \ aeabi_vfp_float.S .endif diff --git a/lib/libc/arm/gen/Makefile.inc b/lib/libc/arm/gen/Makefile.inc index c0f5392..615ee17 100644 --- a/lib/libc/arm/gen/Makefile.inc +++ b/lib/libc/arm/gen/Makefile.inc @@ -7,7 +7,7 @@ SRCS+= _ctx_start.S _setjmp.S _set_tp.c alloca.S fabs.c \ arm_initfini.c \ trivial-getcontextx.c -.if ${MACHINE_ARCH} == "armv6hf" +.if ${MACHINE_ARCH:Marmv6*} && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") SRCS+= fpgetmask_vfp.c fpgetround_vfp.c fpgetsticky_vfp.c fpsetmask_vfp.c \ fpsetround_vfp.c fpsetsticky_vfp.c .endif diff --git a/lib/libc/gen/Symbol.map b/lib/libc/gen/Symbol.map index ee4d619..d28991d 100644 --- a/lib/libc/gen/Symbol.map +++ b/lib/libc/gen/Symbol.map @@ -410,6 +410,9 @@ FBSD_1.3 { }; FBSD_1.4 { + pthread_mutex_consistent; + pthread_mutexattr_getrobust; + pthread_mutexattr_setrobust; scandir_b; }; diff --git a/lib/libc/gen/_pthread_stubs.c b/lib/libc/gen/_pthread_stubs.c index bd35bd2..18a2321 100644 --- a/lib/libc/gen/_pthread_stubs.c +++ b/lib/libc/gen/_pthread_stubs.c @@ -125,6 +125,9 @@ pthread_func_entry_t __thr_jtable[PJT_MAX] = { {PJT_DUAL_ENTRY(stub_zero)}, /* PJT_CLEANUP_PUSH_IMP */ {PJT_DUAL_ENTRY(stub_zero)}, /* PJT_CANCEL_ENTER */ {PJT_DUAL_ENTRY(stub_zero)}, /* PJT_CANCEL_LEAVE */ + {PJT_DUAL_ENTRY(stub_zero)}, /* PJT_MUTEX_CONSISTENT */ + {PJT_DUAL_ENTRY(stub_zero)}, /* PJT_MUTEXATTR_GETROBUST */ + {PJT_DUAL_ENTRY(stub_zero)}, /* PJT_MUTEXATTR_SETROBUST */ }; /* @@ -226,9 +229,14 @@ STUB_FUNC2(pthread_mutex_init, PJT_MUTEX_INIT, int, void *, void *) STUB_FUNC1(pthread_mutex_lock, PJT_MUTEX_LOCK, int, void *) STUB_FUNC1(pthread_mutex_trylock, PJT_MUTEX_TRYLOCK, int, void *) STUB_FUNC1(pthread_mutex_unlock, PJT_MUTEX_UNLOCK, int, void *) +STUB_FUNC1(pthread_mutex_consistent, PJT_MUTEX_CONSISTENT, int, void *) STUB_FUNC1(pthread_mutexattr_destroy, PJT_MUTEXATTR_DESTROY, int, void *) STUB_FUNC1(pthread_mutexattr_init, PJT_MUTEXATTR_INIT, int, void *) STUB_FUNC2(pthread_mutexattr_settype, PJT_MUTEXATTR_SETTYPE, int, void *, int) +STUB_FUNC2(pthread_mutexattr_getrobust, PJT_MUTEXATTR_GETROBUST, int, void *, + int *) +STUB_FUNC2(pthread_mutexattr_setrobust, PJT_MUTEXATTR_SETROBUST, int, void *, + int) STUB_FUNC2(pthread_once, PJT_ONCE, int, void *, void *) STUB_FUNC1(pthread_rwlock_destroy, PJT_RWLOCK_DESTROY, int, void *) STUB_FUNC2(pthread_rwlock_init, PJT_RWLOCK_INIT, int, void *, void *) diff --git a/lib/libc/include/libc_private.h b/lib/libc/include/libc_private.h index 8ee77d9..8fdf4a9 100644 --- a/lib/libc/include/libc_private.h +++ b/lib/libc/include/libc_private.h @@ -168,6 +168,9 @@ typedef enum { PJT_CLEANUP_PUSH_IMP, PJT_CANCEL_ENTER, PJT_CANCEL_LEAVE, + PJT_MUTEX_CONSISTENT, + PJT_MUTEXATTR_GETROBUST, + PJT_MUTEXATTR_SETROBUST, PJT_MAX } pjt_index_t; diff --git a/lib/libcompiler_rt/Makefile b/lib/libcompiler_rt/Makefile index 8959225..011bead 100644 --- a/lib/libcompiler_rt/Makefile +++ b/lib/libcompiler_rt/Makefile @@ -199,9 +199,10 @@ SRCF+= stdatomic .endif .for file in ${SRCF} -. if ${MACHINE_ARCH:Marm*hf*} != "" && exists(${CRTSRC}/${CRTARCH}/${file}vfp.S) +.if ${MACHINE_ARCH:Marmv6*} && (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "") && \ + exists(${CRTSRC}/${CRTARCH}/${file}vfp.S) SRCS+= ${file}vfp.S -. elif !(${MACHINE_CPUARCH} == "arm" && ${MACHINE_ARCH:Marm*hf*} == "") && exists(${CRTSRC}/${CRTARCH}/${file}.S) +. elif exists(${CRTSRC}/${CRTARCH}/${file}.S) SRCS+= ${file}.S . else SRCS+= ${file}.c diff --git a/lib/libpam/modules/pam_unix/pam_unix.c b/lib/libpam/modules/pam_unix/pam_unix.c index 8c6b822..5403d5d 100644 --- a/lib/libpam/modules/pam_unix/pam_unix.c +++ b/lib/libpam/modules/pam_unix/pam_unix.c @@ -332,6 +332,7 @@ pam_sm_chauthtok(pam_handle_t *pamh, int flags, * XXX check PAM_DISALLOW_NULL_AUTHTOK */ old_pass = ""; + retval = PAM_SUCCESS; } else { retval = pam_get_authtok(pamh, PAM_OLDAUTHTOK, &old_pass, NULL); diff --git a/lib/libstand/printf.c b/lib/libstand/printf.c index fef5341..71e313c 100644 --- a/lib/libstand/printf.c +++ b/lib/libstand/printf.c @@ -204,6 +204,7 @@ kvprintf(char const *fmt, kvprintf_fn_t *func, void *arg, int radix, va_list ap) char nbuf[MAXNBUF]; char *d; const char *p, *percent, *q; + uint16_t *S; u_char *up; int ch, n; uintmax_t num; @@ -398,6 +399,10 @@ reswitch: switch (ch = (u_char)*fmt++) { while (width--) PCHAR(padc); break; + case 'S': /* Assume console can cope with wide chars */ + for (S = va_arg(ap, uint16_t *); *S != 0; S++) + PCHAR(*S); + break; case 't': tflag = 1; goto reswitch; diff --git a/lib/libthr/libthr.3 b/lib/libthr/libthr.3 index fdd8ef1..fd90cdd 100644 --- a/lib/libthr/libthr.3 +++ b/lib/libthr/libthr.3 @@ -118,7 +118,7 @@ environment variable. If both the spin and yield loops failed to acquire the lock, the thread is taken off the CPU and put to sleep in the kernel with the -.Xr umtx 2 +.Xr _umtx_op 2 syscall. The kernel wakes up a thread and hands the ownership of the lock to the woken thread when the lock becomes available. @@ -236,7 +236,7 @@ logs. .Xr ld-elf.so.1 1 , .Xr getrlimit 2 , .Xr errno 2 , -.Xr umtx 2 , +.Xr _umtx_op 2 , .Xr dlclose 3 , .Xr dlopen 3 , .Xr getenv 3 , diff --git a/lib/libthr/pthread.map b/lib/libthr/pthread.map index 9fb72eb..e568393 100644 --- a/lib/libthr/pthread.map +++ b/lib/libthr/pthread.map @@ -315,3 +315,9 @@ FBSD_1.1 { FBSD_1.2 { pthread_getthreadid_np; }; + +FBSD_1.4 { + pthread_mutex_consistent; + pthread_mutexattr_getrobust; + pthread_mutexattr_setrobust; +}; diff --git a/lib/libthr/thread/thr_cond.c b/lib/libthr/thread/thr_cond.c index 0e37b70..4d9356a 100644 --- a/lib/libthr/thread/thr_cond.c +++ b/lib/libthr/thread/thr_cond.c @@ -188,46 +188,57 @@ _pthread_cond_destroy(pthread_cond_t *cond) */ static int cond_wait_kernel(struct pthread_cond *cvp, struct pthread_mutex *mp, - const struct timespec *abstime, int cancel) + const struct timespec *abstime, int cancel) { - struct pthread *curthread = _get_curthread(); - int recurse; - int error, error2 = 0; + struct pthread *curthread; + int error, error2, recurse, robust; + + curthread = _get_curthread(); + robust = _mutex_enter_robust(curthread, mp); error = _mutex_cv_detach(mp, &recurse); - if (error != 0) + if (error != 0) { + if (robust) + _mutex_leave_robust(curthread, mp); return (error); + } - if (cancel) { + if (cancel) _thr_cancel_enter2(curthread, 0); - error = _thr_ucond_wait((struct ucond *)&cvp->__has_kern_waiters, - (struct umutex *)&mp->m_lock, abstime, - CVWAIT_ABSTIME|CVWAIT_CLOCKID); + error = _thr_ucond_wait((struct ucond *)&cvp->__has_kern_waiters, + (struct umutex *)&mp->m_lock, abstime, CVWAIT_ABSTIME | + CVWAIT_CLOCKID); + if (cancel) _thr_cancel_leave(curthread, 0); - } else { - error = _thr_ucond_wait((struct ucond *)&cvp->__has_kern_waiters, - (struct umutex *)&mp->m_lock, abstime, - CVWAIT_ABSTIME|CVWAIT_CLOCKID); - } /* * Note that PP mutex and ROBUST mutex may return * interesting error codes. */ if (error == 0) { - error2 = _mutex_cv_lock(mp, recurse); + error2 = _mutex_cv_lock(mp, recurse, true); } else if (error == EINTR || error == ETIMEDOUT) { - error2 = _mutex_cv_lock(mp, recurse); + error2 = _mutex_cv_lock(mp, recurse, true); + /* + * Do not do cancellation on EOWNERDEAD there. The + * cancellation cleanup handler will use the protected + * state and unlock the mutex without making the state + * consistent and the state will be unrecoverable. + */ if (error2 == 0 && cancel) _thr_testcancel(curthread); + if (error == EINTR) error = 0; } else { /* We know that it didn't unlock the mutex. */ - error2 = _mutex_cv_attach(mp, recurse); - if (error2 == 0 && cancel) + _mutex_cv_attach(mp, recurse); + if (cancel) _thr_testcancel(curthread); + error2 = 0; } + if (robust) + _mutex_leave_robust(curthread, mp); return (error2 != 0 ? error2 : error); } @@ -240,14 +251,13 @@ cond_wait_kernel(struct pthread_cond *cvp, struct pthread_mutex *mp, static int cond_wait_user(struct pthread_cond *cvp, struct pthread_mutex *mp, - const struct timespec *abstime, int cancel) + const struct timespec *abstime, int cancel) { - struct pthread *curthread = _get_curthread(); + struct pthread *curthread; struct sleepqueue *sq; - int recurse; - int error; - int defered; + int deferred, error, error2, recurse; + curthread = _get_curthread(); if (curthread->wchan != NULL) PANIC("thread was already on queue."); @@ -260,32 +270,31 @@ cond_wait_user(struct pthread_cond *cvp, struct pthread_mutex *mp, * us to check it without locking in pthread_cond_signal(). */ cvp->__has_user_waiters = 1; - defered = 0; - (void)_mutex_cv_unlock(mp, &recurse, &defered); + deferred = 0; + (void)_mutex_cv_unlock(mp, &recurse, &deferred); curthread->mutex_obj = mp; _sleepq_add(cvp, curthread); for(;;) { _thr_clear_wake(curthread); _sleepq_unlock(cvp); - if (defered) { - defered = 0; + if (deferred) { + deferred = 0; if ((mp->m_lock.m_owner & UMUTEX_CONTESTED) == 0) - (void)_umtx_op_err(&mp->m_lock, UMTX_OP_MUTEX_WAKE2, - mp->m_lock.m_flags, 0, 0); + (void)_umtx_op_err(&mp->m_lock, + UMTX_OP_MUTEX_WAKE2, mp->m_lock.m_flags, + 0, 0); } if (curthread->nwaiter_defer > 0) { _thr_wake_all(curthread->defer_waiters, - curthread->nwaiter_defer); + curthread->nwaiter_defer); curthread->nwaiter_defer = 0; } - if (cancel) { + if (cancel) _thr_cancel_enter2(curthread, 0); - error = _thr_sleep(curthread, cvp->__clock_id, abstime); + error = _thr_sleep(curthread, cvp->__clock_id, abstime); + if (cancel) _thr_cancel_leave(curthread, 0); - } else { - error = _thr_sleep(curthread, cvp->__clock_id, abstime); - } _sleepq_lock(cvp); if (curthread->wchan == NULL) { @@ -293,25 +302,26 @@ cond_wait_user(struct pthread_cond *cvp, struct pthread_mutex *mp, break; } else if (cancel && SHOULD_CANCEL(curthread)) { sq = _sleepq_lookup(cvp); - cvp->__has_user_waiters = - _sleepq_remove(sq, curthread); + cvp->__has_user_waiters = _sleepq_remove(sq, curthread); _sleepq_unlock(cvp); curthread->mutex_obj = NULL; - _mutex_cv_lock(mp, recurse); + error2 = _mutex_cv_lock(mp, recurse, false); if (!THR_IN_CRITICAL(curthread)) _pthread_exit(PTHREAD_CANCELED); else /* this should not happen */ - return (0); + return (error2); } else if (error == ETIMEDOUT) { sq = _sleepq_lookup(cvp); cvp->__has_user_waiters = - _sleepq_remove(sq, curthread); + _sleepq_remove(sq, curthread); break; } } _sleepq_unlock(cvp); curthread->mutex_obj = NULL; - _mutex_cv_lock(mp, recurse); + error2 = _mutex_cv_lock(mp, recurse, false); + if (error == 0) + error = error2; return (error); } @@ -338,12 +348,12 @@ cond_wait_common(pthread_cond_t *cond, pthread_mutex_t *mutex, return (error); if (curthread->attr.sched_policy != SCHED_OTHER || - (mp->m_lock.m_flags & (UMUTEX_PRIO_PROTECT|UMUTEX_PRIO_INHERIT| - USYNC_PROCESS_SHARED)) != 0 || + (mp->m_lock.m_flags & (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT | + USYNC_PROCESS_SHARED)) != 0 || (cvp->__flags & USYNC_PROCESS_SHARED) != 0) - return cond_wait_kernel(cvp, mp, abstime, cancel); + return (cond_wait_kernel(cvp, mp, abstime, cancel)); else - return cond_wait_user(cvp, mp, abstime, cancel); + return (cond_wait_user(cvp, mp, abstime, cancel)); } int @@ -420,15 +430,15 @@ cond_signal_common(pthread_cond_t *cond) td = _sleepq_first(sq); mp = td->mutex_obj; cvp->__has_user_waiters = _sleepq_remove(sq, td); - if (mp->m_owner == TID(curthread)) { + if (PMUTEX_OWNER_ID(mp) == TID(curthread)) { if (curthread->nwaiter_defer >= MAX_DEFER_WAITERS) { _thr_wake_all(curthread->defer_waiters, - curthread->nwaiter_defer); + curthread->nwaiter_defer); curthread->nwaiter_defer = 0; } curthread->defer_waiters[curthread->nwaiter_defer++] = - &td->wake_addr->value; - mp->m_flags |= PMUTEX_FLAG_DEFERED; + &td->wake_addr->value; + mp->m_flags |= PMUTEX_FLAG_DEFERRED; } else { waddr = &td->wake_addr->value; } @@ -452,15 +462,15 @@ drop_cb(struct pthread *td, void *arg) struct pthread *curthread = ba->curthread; mp = td->mutex_obj; - if (mp->m_owner == TID(curthread)) { + if (PMUTEX_OWNER_ID(mp) == TID(curthread)) { if (curthread->nwaiter_defer >= MAX_DEFER_WAITERS) { _thr_wake_all(curthread->defer_waiters, - curthread->nwaiter_defer); + curthread->nwaiter_defer); curthread->nwaiter_defer = 0; } curthread->defer_waiters[curthread->nwaiter_defer++] = - &td->wake_addr->value; - mp->m_flags |= PMUTEX_FLAG_DEFERED; + &td->wake_addr->value; + mp->m_flags |= PMUTEX_FLAG_DEFERRED; } else { if (ba->count >= MAX_DEFER_WAITERS) { _thr_wake_all(ba->waddrs, ba->count); diff --git a/lib/libthr/thread/thr_init.c b/lib/libthr/thread/thr_init.c index c852406..0927e15 100644 --- a/lib/libthr/thread/thr_init.c +++ b/lib/libthr/thread/thr_init.c @@ -94,6 +94,7 @@ struct pthread_mutex_attr _pthread_mutexattr_default = { .m_protocol = PTHREAD_PRIO_NONE, .m_ceiling = 0, .m_pshared = PTHREAD_PROCESS_PRIVATE, + .m_robust = PTHREAD_MUTEX_STALLED, }; struct pthread_mutex_attr _pthread_mutexattr_adaptive_default = { @@ -101,6 +102,7 @@ struct pthread_mutex_attr _pthread_mutexattr_adaptive_default = { .m_protocol = PTHREAD_PRIO_NONE, .m_ceiling = 0, .m_pshared = PTHREAD_PROCESS_PRIVATE, + .m_robust = PTHREAD_MUTEX_STALLED, }; /* Default condition variable attributes: */ @@ -265,7 +267,10 @@ static pthread_func_t jmp_table[][2] = { {DUAL_ENTRY(__pthread_cleanup_pop_imp)},/* PJT_CLEANUP_POP_IMP */ {DUAL_ENTRY(__pthread_cleanup_push_imp)},/* PJT_CLEANUP_PUSH_IMP */ {DUAL_ENTRY(_pthread_cancel_enter)}, /* PJT_CANCEL_ENTER */ - {DUAL_ENTRY(_pthread_cancel_leave)} /* PJT_CANCEL_LEAVE */ + {DUAL_ENTRY(_pthread_cancel_leave)}, /* PJT_CANCEL_LEAVE */ + {DUAL_ENTRY(_pthread_mutex_consistent)},/* PJT_MUTEX_CONSISTENT */ + {DUAL_ENTRY(_pthread_mutexattr_getrobust)},/* PJT_MUTEXATTR_GETROBUST */ + {DUAL_ENTRY(_pthread_mutexattr_setrobust)},/* PJT_MUTEXATTR_SETROBUST */ }; static int init_once = 0; @@ -308,7 +313,7 @@ _libpthread_init(struct pthread *curthread) int first, dlopened; /* Check if this function has already been called: */ - if ((_thr_initial != NULL) && (curthread == NULL)) + if (_thr_initial != NULL && curthread == NULL) /* Only initialize the threaded application once. */ return; @@ -316,7 +321,7 @@ _libpthread_init(struct pthread *curthread) * Check the size of the jump table to make sure it is preset * with the correct number of entries. */ - if (sizeof(jmp_table) != (sizeof(pthread_func_t) * PJT_MAX * 2)) + if (sizeof(jmp_table) != sizeof(pthread_func_t) * PJT_MAX * 2) PANIC("Thread jump table not properly initialized"); memcpy(__thr_jtable, jmp_table, sizeof(jmp_table)); __thr_interpose_libc(); diff --git a/lib/libthr/thread/thr_mutex.c b/lib/libthr/thread/thr_mutex.c index f75ea6f..2d507e7 100644 --- a/lib/libthr/thread/thr_mutex.c +++ b/lib/libthr/thread/thr_mutex.c @@ -1,7 +1,7 @@ /* * Copyright (c) 1995 John Birrell <jb@cimlogic.com.au>. * Copyright (c) 2006 David Xu <davidxu@freebsd.org>. - * Copyright (c) 2015 The FreeBSD Foundation + * Copyright (c) 2015, 2016 The FreeBSD Foundation * * All rights reserved. * @@ -39,7 +39,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include <stdbool.h> #include "namespace.h" #include <stdlib.h> #include <errno.h> @@ -64,6 +63,7 @@ _Static_assert(sizeof(struct pthread_mutex) <= PAGE_SIZE, /* * Prototypes */ +int __pthread_mutex_consistent(pthread_mutex_t *mutex); int __pthread_mutex_init(pthread_mutex_t *mutex, const pthread_mutexattr_t *mutex_attr); int __pthread_mutex_trylock(pthread_mutex_t *mutex); @@ -82,9 +82,13 @@ int __pthread_mutex_setyieldloops_np(pthread_mutex_t *mutex, int count); static int mutex_self_trylock(pthread_mutex_t); static int mutex_self_lock(pthread_mutex_t, const struct timespec *abstime); -static int mutex_unlock_common(struct pthread_mutex *, int, int *); +static int mutex_unlock_common(struct pthread_mutex *, bool, int *); static int mutex_lock_sleep(struct pthread *, pthread_mutex_t, const struct timespec *); +static void mutex_init_robust(struct pthread *curthread); +static int mutex_qidx(struct pthread_mutex *m); +static bool is_robust_mutex(struct pthread_mutex *m); +static bool is_pshared_mutex(struct pthread_mutex *m); __weak_reference(__pthread_mutex_init, pthread_mutex_init); __strong_reference(__pthread_mutex_init, _pthread_mutex_init); @@ -94,6 +98,8 @@ __weak_reference(__pthread_mutex_timedlock, pthread_mutex_timedlock); __strong_reference(__pthread_mutex_timedlock, _pthread_mutex_timedlock); __weak_reference(__pthread_mutex_trylock, pthread_mutex_trylock); __strong_reference(__pthread_mutex_trylock, _pthread_mutex_trylock); +__weak_reference(_pthread_mutex_consistent, pthread_mutex_consistent); +__strong_reference(_pthread_mutex_consistent, __pthread_mutex_consistent); /* Single underscore versions provided for libc internal usage: */ /* No difference between libc and application usage of these: */ @@ -125,23 +131,23 @@ mutex_init_link(struct pthread_mutex *m) } static void -mutex_assert_is_owned(struct pthread_mutex *m) +mutex_assert_is_owned(struct pthread_mutex *m __unused) { #if defined(_PTHREADS_INVARIANTS) if (__predict_false(m->m_qe.tqe_prev == NULL)) { char msg[128]; snprintf(msg, sizeof(msg), - "mutex %p own %#x %#x is not on list %p %p", - m, m->m_lock.m_owner, m->m_owner, m->m_qe.tqe_prev, - m->m_qe.tqe_next); + "mutex %p own %#x is not on list %p %p", + m, m->m_lock.m_owner, m->m_qe.tqe_prev, m->m_qe.tqe_next); PANIC(msg); } #endif } static void -mutex_assert_not_owned(struct pthread_mutex *m) +mutex_assert_not_owned(struct pthread *curthread __unused, + struct pthread_mutex *m __unused) { #if defined(_PTHREADS_INVARIANTS) @@ -149,21 +155,68 @@ mutex_assert_not_owned(struct pthread_mutex *m) m->m_qe.tqe_next != NULL)) { char msg[128]; snprintf(msg, sizeof(msg), - "mutex %p own %#x %#x is on list %p %p", - m, m->m_lock.m_owner, m->m_owner, m->m_qe.tqe_prev, - m->m_qe.tqe_next); + "mutex %p own %#x is on list %p %p", + m, m->m_lock.m_owner, m->m_qe.tqe_prev, m->m_qe.tqe_next); + PANIC(msg); + } + if (__predict_false(is_robust_mutex(m) && + (m->m_lock.m_rb_lnk != 0 || m->m_rb_prev != NULL || + (is_pshared_mutex(m) && curthread->robust_list == + (uintptr_t)&m->m_lock) || + (!is_pshared_mutex(m) && curthread->priv_robust_list == + (uintptr_t)&m->m_lock)))) { + char msg[128]; + snprintf(msg, sizeof(msg), + "mutex %p own %#x is on robust linkage %p %p head %p phead %p", + m, m->m_lock.m_owner, (void *)m->m_lock.m_rb_lnk, + m->m_rb_prev, (void *)curthread->robust_list, + (void *)curthread->priv_robust_list); PANIC(msg); } #endif } -static int +static bool is_pshared_mutex(struct pthread_mutex *m) { return ((m->m_lock.m_flags & USYNC_PROCESS_SHARED) != 0); } +static bool +is_robust_mutex(struct pthread_mutex *m) +{ + + return ((m->m_lock.m_flags & UMUTEX_ROBUST) != 0); +} + +int +_mutex_enter_robust(struct pthread *curthread, struct pthread_mutex *m) +{ + +#if defined(_PTHREADS_INVARIANTS) + if (__predict_false(curthread->inact_mtx != 0)) + PANIC("inact_mtx enter"); +#endif + if (!is_robust_mutex(m)) + return (0); + + mutex_init_robust(curthread); + curthread->inact_mtx = (uintptr_t)&m->m_lock; + return (1); +} + +void +_mutex_leave_robust(struct pthread *curthread, struct pthread_mutex *m __unused) +{ + +#if defined(_PTHREADS_INVARIANTS) + if (__predict_false(curthread->inact_mtx != (uintptr_t)&m->m_lock)) + PANIC("inact_mtx leave"); +#endif + curthread->inact_mtx = 0; +} + static int mutex_check_attr(const struct pthread_mutex_attr *attr) { @@ -178,12 +231,27 @@ mutex_check_attr(const struct pthread_mutex_attr *attr) } static void +mutex_init_robust(struct pthread *curthread) +{ + struct umtx_robust_lists_params rb; + + if (curthread == NULL) + curthread = _get_curthread(); + if (curthread->robust_inited) + return; + rb.robust_list_offset = (uintptr_t)&curthread->robust_list; + rb.robust_priv_list_offset = (uintptr_t)&curthread->priv_robust_list; + rb.robust_inact_offset = (uintptr_t)&curthread->inact_mtx; + _umtx_op(NULL, UMTX_OP_ROBUST_LISTS, sizeof(rb), &rb, NULL); + curthread->robust_inited = 1; +} + +static void mutex_init_body(struct pthread_mutex *pmutex, const struct pthread_mutex_attr *attr) { pmutex->m_flags = attr->m_type; - pmutex->m_owner = 0; pmutex->m_count = 0; pmutex->m_spinloops = 0; pmutex->m_yieldloops = 0; @@ -205,7 +273,10 @@ mutex_init_body(struct pthread_mutex *pmutex, } if (attr->m_pshared == PTHREAD_PROCESS_SHARED) pmutex->m_lock.m_flags |= USYNC_PROCESS_SHARED; - + if (attr->m_robust == PTHREAD_MUTEX_ROBUST) { + mutex_init_robust(NULL); + pmutex->m_lock.m_flags |= UMUTEX_ROBUST; + } if (PMUTEX_TYPE(pmutex->m_flags) == PTHREAD_MUTEX_ADAPTIVE_NP) { pmutex->m_spinloops = _thr_spinloops ? _thr_spinloops: MUTEX_ADAPTIVE_SPINS; @@ -262,7 +333,7 @@ set_inherited_priority(struct pthread *curthread, struct pthread_mutex *m) { struct pthread_mutex *m2; - m2 = TAILQ_LAST(&curthread->mq[TMQ_NORM_PP], mutex_queue); + m2 = TAILQ_LAST(&curthread->mq[mutex_qidx(m)], mutex_queue); if (m2 != NULL) m->m_lock.m_ceilings[1] = m2->m_lock.m_ceilings[0]; else @@ -277,7 +348,8 @@ shared_mutex_init(struct pthread_mutex *pmtx, const struct .m_type = PTHREAD_MUTEX_DEFAULT, .m_protocol = PTHREAD_PRIO_NONE, .m_ceiling = 0, - .m_pshared = PTHREAD_PROCESS_SHARED + .m_pshared = PTHREAD_PROCESS_SHARED, + .m_robust = PTHREAD_MUTEX_STALLED, }; bool done; @@ -329,7 +401,7 @@ __pthread_mutex_init(pthread_mutex_t *mutex, if (mutex_attr == NULL || (*mutex_attr)->m_pshared == PTHREAD_PROCESS_PRIVATE) { return (mutex_init(mutex, mutex_attr ? *mutex_attr : NULL, - calloc)); + calloc)); } pmtx = __thr_pshared_offpage(mutex, 1); if (pmtx == NULL) @@ -349,6 +421,7 @@ _pthread_mutex_init_calloc_cb(pthread_mutex_t *mutex, .m_protocol = PTHREAD_PRIO_NONE, .m_ceiling = 0, .m_pshared = PTHREAD_PROCESS_PRIVATE, + .m_robust = PTHREAD_MUTEX_STALLED, }; int ret; @@ -378,7 +451,6 @@ queue_fork(struct pthread *curthread, struct mutex_queue *q, TAILQ_FOREACH(m, qp, m_pqe) { TAILQ_INSERT_TAIL(q, m, m_qe); m->m_lock.m_owner = TID(curthread) | bit; - m->m_owner = TID(curthread); } } @@ -390,6 +462,9 @@ _mutex_fork(struct pthread *curthread) &curthread->mq[TMQ_NORM_PRIV], 0); queue_fork(curthread, &curthread->mq[TMQ_NORM_PP], &curthread->mq[TMQ_NORM_PP_PRIV], UMUTEX_CONTESTED); + queue_fork(curthread, &curthread->mq[TMQ_ROBUST_PP], + &curthread->mq[TMQ_ROBUST_PP_PRIV], UMUTEX_CONTESTED); + curthread->robust_list = 0; } int @@ -407,17 +482,18 @@ _pthread_mutex_destroy(pthread_mutex_t *mutex) if (m == THR_PSHARED_PTR) { m1 = __thr_pshared_offpage(mutex, 0); if (m1 != NULL) { - mutex_assert_not_owned(m1); + mutex_assert_not_owned(_get_curthread(), m1); __thr_pshared_destroy(mutex); } *mutex = THR_MUTEX_DESTROYED; return (0); } - if (m->m_owner != 0) { + if (PMUTEX_OWNER_ID(m) != 0 && + (uint32_t)m->m_lock.m_owner != UMUTEX_RB_NOTRECOV) { ret = EBUSY; } else { *mutex = THR_MUTEX_DESTROYED; - mutex_assert_not_owned(m); + mutex_assert_not_owned(_get_curthread(), m); free(m); ret = 0; } @@ -432,31 +508,81 @@ mutex_qidx(struct pthread_mutex *m) if ((m->m_lock.m_flags & UMUTEX_PRIO_PROTECT) == 0) return (TMQ_NORM); - return (TMQ_NORM_PP); + return (is_robust_mutex(m) ? TMQ_ROBUST_PP : TMQ_NORM_PP); } +/* + * Both enqueue_mutex() and dequeue_mutex() operate on the + * thread-private linkage of the locked mutexes and on the robust + * linkage. + * + * Robust list, as seen by kernel, must be consistent even in the case + * of thread termination at arbitrary moment. Since either enqueue or + * dequeue for list walked by kernel consists of rewriting a single + * forward pointer, it is safe. On the other hand, rewrite of the + * back pointer is not atomic WRT the forward one, but kernel does not + * care. + */ static void -enqueue_mutex(struct pthread *curthread, struct pthread_mutex *m) +enqueue_mutex(struct pthread *curthread, struct pthread_mutex *m, + int error) { + struct pthread_mutex *m1; + uintptr_t *rl; int qidx; - m->m_owner = TID(curthread); /* Add to the list of owned mutexes: */ - mutex_assert_not_owned(m); + if (error != EOWNERDEAD) + mutex_assert_not_owned(curthread, m); qidx = mutex_qidx(m); TAILQ_INSERT_TAIL(&curthread->mq[qidx], m, m_qe); if (!is_pshared_mutex(m)) TAILQ_INSERT_TAIL(&curthread->mq[qidx + 1], m, m_pqe); + if (is_robust_mutex(m)) { + rl = is_pshared_mutex(m) ? &curthread->robust_list : + &curthread->priv_robust_list; + m->m_rb_prev = NULL; + if (*rl != 0) { + m1 = __containerof((void *)*rl, + struct pthread_mutex, m_lock); + m->m_lock.m_rb_lnk = (uintptr_t)&m1->m_lock; + m1->m_rb_prev = m; + } else { + m1 = NULL; + m->m_lock.m_rb_lnk = 0; + } + *rl = (uintptr_t)&m->m_lock; + } } static void dequeue_mutex(struct pthread *curthread, struct pthread_mutex *m) { + struct pthread_mutex *mp, *mn; int qidx; - m->m_owner = 0; mutex_assert_is_owned(m); qidx = mutex_qidx(m); + if (is_robust_mutex(m)) { + mp = m->m_rb_prev; + if (mp == NULL) { + if (is_pshared_mutex(m)) { + curthread->robust_list = m->m_lock.m_rb_lnk; + } else { + curthread->priv_robust_list = + m->m_lock.m_rb_lnk; + } + } else { + mp->m_lock.m_rb_lnk = m->m_lock.m_rb_lnk; + } + if (m->m_lock.m_rb_lnk != 0) { + mn = __containerof((void *)m->m_lock.m_rb_lnk, + struct pthread_mutex, m_lock); + mn->m_rb_prev = m->m_rb_prev; + } + m->m_lock.m_rb_lnk = 0; + m->m_rb_prev = NULL; + } TAILQ_REMOVE(&curthread->mq[qidx], m, m_qe); if (!is_pshared_mutex(m)) TAILQ_REMOVE(&curthread->mq[qidx + 1], m, m_pqe); @@ -496,7 +622,7 @@ __pthread_mutex_trylock(pthread_mutex_t *mutex) struct pthread *curthread; struct pthread_mutex *m; uint32_t id; - int ret; + int ret, robust; ret = check_and_init_mutex(mutex, &m); if (ret != 0) @@ -505,27 +631,32 @@ __pthread_mutex_trylock(pthread_mutex_t *mutex) id = TID(curthread); if (m->m_flags & PMUTEX_FLAG_PRIVATE) THR_CRITICAL_ENTER(curthread); + robust = _mutex_enter_robust(curthread, m); ret = _thr_umutex_trylock(&m->m_lock, id); - if (__predict_true(ret == 0)) { - enqueue_mutex(curthread, m); - } else if (m->m_owner == id) { + if (__predict_true(ret == 0) || ret == EOWNERDEAD) { + enqueue_mutex(curthread, m, ret); + if (ret == EOWNERDEAD) + m->m_lock.m_flags |= UMUTEX_NONCONSISTENT; + } else if (PMUTEX_OWNER_ID(m) == id) { ret = mutex_self_trylock(m); } /* else {} */ - if (ret && (m->m_flags & PMUTEX_FLAG_PRIVATE)) + if (robust) + _mutex_leave_robust(curthread, m); + if ((ret == 0 || ret == EOWNERDEAD) && + (m->m_flags & PMUTEX_FLAG_PRIVATE) != 0) THR_CRITICAL_LEAVE(curthread); return (ret); } static int mutex_lock_sleep(struct pthread *curthread, struct pthread_mutex *m, - const struct timespec *abstime) + const struct timespec *abstime) { - uint32_t id, owner; - int count; - int ret; + uint32_t id, owner; + int count, ret; id = TID(curthread); - if (m->m_owner == id) + if (PMUTEX_OWNER_ID(m) == id) return (mutex_self_lock(m, abstime)); /* @@ -534,10 +665,9 @@ mutex_lock_sleep(struct pthread *curthread, struct pthread_mutex *m, * the lock is likely to be released quickly and it is * faster than entering the kernel */ - if (__predict_false( - (m->m_lock.m_flags & - (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT)) != 0)) - goto sleep_in_kernel; + if (__predict_false((m->m_lock.m_flags & (UMUTEX_PRIO_PROTECT | + UMUTEX_PRIO_INHERIT | UMUTEX_ROBUST | UMUTEX_NONCONSISTENT)) != 0)) + goto sleep_in_kernel; if (!_thr_is_smp) goto yield_loop; @@ -546,7 +676,8 @@ mutex_lock_sleep(struct pthread *curthread, struct pthread_mutex *m, while (count--) { owner = m->m_lock.m_owner; if ((owner & ~UMUTEX_CONTESTED) == 0) { - if (atomic_cmpset_acq_32(&m->m_lock.m_owner, owner, id|owner)) { + if (atomic_cmpset_acq_32(&m->m_lock.m_owner, owner, + id | owner)) { ret = 0; goto done; } @@ -560,7 +691,8 @@ yield_loop: _sched_yield(); owner = m->m_lock.m_owner; if ((owner & ~UMUTEX_CONTESTED) == 0) { - if (atomic_cmpset_acq_32(&m->m_lock.m_owner, owner, id|owner)) { + if (atomic_cmpset_acq_32(&m->m_lock.m_owner, owner, + id | owner)) { ret = 0; goto done; } @@ -568,38 +700,46 @@ yield_loop: } sleep_in_kernel: - if (abstime == NULL) { + if (abstime == NULL) ret = __thr_umutex_lock(&m->m_lock, id); - } else if (__predict_false( - abstime->tv_nsec < 0 || - abstime->tv_nsec >= 1000000000)) { + else if (__predict_false(abstime->tv_nsec < 0 || + abstime->tv_nsec >= 1000000000)) ret = EINVAL; - } else { + else ret = __thr_umutex_timedlock(&m->m_lock, id, abstime); - } done: - if (ret == 0) - enqueue_mutex(curthread, m); - + if (ret == 0 || ret == EOWNERDEAD) { + enqueue_mutex(curthread, m, ret); + if (ret == EOWNERDEAD) + m->m_lock.m_flags |= UMUTEX_NONCONSISTENT; + } return (ret); } static inline int -mutex_lock_common(struct pthread_mutex *m, - const struct timespec *abstime, int cvattach) +mutex_lock_common(struct pthread_mutex *m, const struct timespec *abstime, + bool cvattach, bool rb_onlist) { - struct pthread *curthread = _get_curthread(); - int ret; + struct pthread *curthread; + int ret, robust; + curthread = _get_curthread(); if (!cvattach && m->m_flags & PMUTEX_FLAG_PRIVATE) THR_CRITICAL_ENTER(curthread); - if (_thr_umutex_trylock2(&m->m_lock, TID(curthread)) == 0) { - enqueue_mutex(curthread, m); - ret = 0; + if (!rb_onlist) + robust = _mutex_enter_robust(curthread, m); + ret = _thr_umutex_trylock2(&m->m_lock, TID(curthread)); + if (ret == 0 || ret == EOWNERDEAD) { + enqueue_mutex(curthread, m, ret); + if (ret == EOWNERDEAD) + m->m_lock.m_flags |= UMUTEX_NONCONSISTENT; } else { ret = mutex_lock_sleep(curthread, m, abstime); } - if (ret && (m->m_flags & PMUTEX_FLAG_PRIVATE) && !cvattach) + if (!rb_onlist && robust) + _mutex_leave_robust(curthread, m); + if (ret != 0 && ret != EOWNERDEAD && + (m->m_flags & PMUTEX_FLAG_PRIVATE) != 0 && !cvattach) THR_CRITICAL_LEAVE(curthread); return (ret); } @@ -613,7 +753,7 @@ __pthread_mutex_lock(pthread_mutex_t *mutex) _thr_check_init(); ret = check_and_init_mutex(mutex, &m); if (ret == 0) - ret = mutex_lock_common(m, NULL, 0); + ret = mutex_lock_common(m, NULL, false, false); return (ret); } @@ -627,7 +767,7 @@ __pthread_mutex_timedlock(pthread_mutex_t *mutex, _thr_check_init(); ret = check_and_init_mutex(mutex, &m); if (ret == 0) - ret = mutex_lock_common(m, abstime, 0); + ret = mutex_lock_common(m, abstime, false, false); return (ret); } @@ -644,16 +784,16 @@ _pthread_mutex_unlock(pthread_mutex_t *mutex) } else { mp = *mutex; } - return (mutex_unlock_common(mp, 0, NULL)); + return (mutex_unlock_common(mp, false, NULL)); } int -_mutex_cv_lock(struct pthread_mutex *m, int count) +_mutex_cv_lock(struct pthread_mutex *m, int count, bool rb_onlist) { - int error; + int error; - error = mutex_lock_common(m, NULL, 1); - if (error == 0) + error = mutex_lock_common(m, NULL, true, rb_onlist); + if (error == 0 || error == EOWNERDEAD) m->m_count = count; return (error); } @@ -667,16 +807,17 @@ _mutex_cv_unlock(struct pthread_mutex *m, int *count, int *defer) */ *count = m->m_count; m->m_count = 0; - (void)mutex_unlock_common(m, 1, defer); + (void)mutex_unlock_common(m, true, defer); return (0); } int _mutex_cv_attach(struct pthread_mutex *m, int count) { - struct pthread *curthread = _get_curthread(); + struct pthread *curthread; - enqueue_mutex(curthread, m); + curthread = _get_curthread(); + enqueue_mutex(curthread, m, 0); m->m_count = count; return (0); } @@ -684,12 +825,12 @@ _mutex_cv_attach(struct pthread_mutex *m, int count) int _mutex_cv_detach(struct pthread_mutex *mp, int *recurse) { - struct pthread *curthread = _get_curthread(); - int defered; - int error; + struct pthread *curthread; + int deferred, error; + curthread = _get_curthread(); if ((error = _mutex_owned(curthread, mp)) != 0) - return (error); + return (error); /* * Clear the count in case this is a recursive mutex. @@ -699,15 +840,15 @@ _mutex_cv_detach(struct pthread_mutex *mp, int *recurse) dequeue_mutex(curthread, mp); /* Will this happen in real-world ? */ - if ((mp->m_flags & PMUTEX_FLAG_DEFERED) != 0) { - defered = 1; - mp->m_flags &= ~PMUTEX_FLAG_DEFERED; + if ((mp->m_flags & PMUTEX_FLAG_DEFERRED) != 0) { + deferred = 1; + mp->m_flags &= ~PMUTEX_FLAG_DEFERRED; } else - defered = 0; + deferred = 0; - if (defered) { + if (deferred) { _thr_wake_all(curthread->defer_waiters, - curthread->nwaiter_defer); + curthread->nwaiter_defer); curthread->nwaiter_defer = 0; } return (0); @@ -716,7 +857,7 @@ _mutex_cv_detach(struct pthread_mutex *mp, int *recurse) static int mutex_self_trylock(struct pthread_mutex *m) { - int ret; + int ret; switch (PMUTEX_TYPE(m->m_flags)) { case PTHREAD_MUTEX_ERRORCHECK: @@ -746,7 +887,7 @@ static int mutex_self_lock(struct pthread_mutex *m, const struct timespec *abstime) { struct timespec ts1, ts2; - int ret; + int ret; switch (PMUTEX_TYPE(m->m_flags)) { case PTHREAD_MUTEX_ERRORCHECK: @@ -812,11 +953,11 @@ mutex_self_lock(struct pthread_mutex *m, const struct timespec *abstime) } static int -mutex_unlock_common(struct pthread_mutex *m, int cv, int *mtx_defer) +mutex_unlock_common(struct pthread_mutex *m, bool cv, int *mtx_defer) { - struct pthread *curthread = _get_curthread(); + struct pthread *curthread; uint32_t id; - int defered, error; + int deferred, error, robust; if (__predict_false(m <= THR_MUTEX_DESTROYED)) { if (m == THR_MUTEX_DESTROYED) @@ -824,34 +965,39 @@ mutex_unlock_common(struct pthread_mutex *m, int cv, int *mtx_defer) return (EPERM); } + curthread = _get_curthread(); id = TID(curthread); /* * Check if the running thread is not the owner of the mutex. */ - if (__predict_false(m->m_owner != id)) + if (__predict_false(PMUTEX_OWNER_ID(m) != id)) return (EPERM); error = 0; - if (__predict_false( - PMUTEX_TYPE(m->m_flags) == PTHREAD_MUTEX_RECURSIVE && - m->m_count > 0)) { + if (__predict_false(PMUTEX_TYPE(m->m_flags) == + PTHREAD_MUTEX_RECURSIVE && m->m_count > 0)) { m->m_count--; } else { - if ((m->m_flags & PMUTEX_FLAG_DEFERED) != 0) { - defered = 1; - m->m_flags &= ~PMUTEX_FLAG_DEFERED; + if ((m->m_flags & PMUTEX_FLAG_DEFERRED) != 0) { + deferred = 1; + m->m_flags &= ~PMUTEX_FLAG_DEFERRED; } else - defered = 0; + deferred = 0; + robust = _mutex_enter_robust(curthread, m); dequeue_mutex(curthread, m); error = _thr_umutex_unlock2(&m->m_lock, id, mtx_defer); - - if (mtx_defer == NULL && defered) { - _thr_wake_all(curthread->defer_waiters, - curthread->nwaiter_defer); - curthread->nwaiter_defer = 0; + if (deferred) { + if (mtx_defer == NULL) { + _thr_wake_all(curthread->defer_waiters, + curthread->nwaiter_defer); + curthread->nwaiter_defer = 0; + } else + *mtx_defer = 1; } + if (robust) + _mutex_leave_robust(curthread, m); } if (!cv && m->m_flags & PMUTEX_FLAG_PRIVATE) THR_CRITICAL_LEAVE(curthread); @@ -887,7 +1033,7 @@ _pthread_mutex_setprioceiling(pthread_mutex_t *mutex, struct pthread *curthread; struct pthread_mutex *m, *m1, *m2; struct mutex_queue *q, *qp; - int ret; + int qidx, ret; if (*mutex == THR_PSHARED_PTR) { m = __thr_pshared_offpage(mutex, 0); @@ -907,14 +1053,15 @@ _pthread_mutex_setprioceiling(pthread_mutex_t *mutex, return (ret); curthread = _get_curthread(); - if (m->m_owner == TID(curthread)) { + if (PMUTEX_OWNER_ID(m) == TID(curthread)) { mutex_assert_is_owned(m); m1 = TAILQ_PREV(m, mutex_queue, m_qe); m2 = TAILQ_NEXT(m, m_qe); if ((m1 != NULL && m1->m_lock.m_ceilings[0] > (u_int)ceiling) || (m2 != NULL && m2->m_lock.m_ceilings[0] < (u_int)ceiling)) { - q = &curthread->mq[TMQ_NORM_PP]; - qp = &curthread->mq[TMQ_NORM_PP_PRIV]; + qidx = mutex_qidx(m); + q = &curthread->mq[qidx]; + qp = &curthread->mq[qidx + 1]; TAILQ_REMOVE(q, m, m_qe); if (!is_pshared_mutex(m)) TAILQ_REMOVE(qp, m, m_pqe); @@ -1009,18 +1156,45 @@ _pthread_mutex_isowned_np(pthread_mutex_t *mutex) if (m <= THR_MUTEX_DESTROYED) return (0); } - return (m->m_owner == TID(_get_curthread())); + return (PMUTEX_OWNER_ID(m) == TID(_get_curthread())); } int _mutex_owned(struct pthread *curthread, const struct pthread_mutex *mp) { + if (__predict_false(mp <= THR_MUTEX_DESTROYED)) { if (mp == THR_MUTEX_DESTROYED) return (EINVAL); return (EPERM); } - if (mp->m_owner != TID(curthread)) + if (PMUTEX_OWNER_ID(mp) != TID(curthread)) return (EPERM); return (0); } + +int +_pthread_mutex_consistent(pthread_mutex_t *mutex) +{ + struct pthread_mutex *m; + struct pthread *curthread; + + if (*mutex == THR_PSHARED_PTR) { + m = __thr_pshared_offpage(mutex, 0); + if (m == NULL) + return (EINVAL); + shared_mutex_init(m, NULL); + } else { + m = *mutex; + if (m <= THR_MUTEX_DESTROYED) + return (EINVAL); + } + curthread = _get_curthread(); + if ((m->m_lock.m_flags & (UMUTEX_ROBUST | UMUTEX_NONCONSISTENT)) != + (UMUTEX_ROBUST | UMUTEX_NONCONSISTENT)) + return (EINVAL); + if (PMUTEX_OWNER_ID(m) != TID(curthread)) + return (EPERM); + m->m_lock.m_flags &= ~UMUTEX_NONCONSISTENT; + return (0); +} diff --git a/lib/libthr/thread/thr_mutexattr.c b/lib/libthr/thread/thr_mutexattr.c index a9e07c2..d8a8671 100644 --- a/lib/libthr/thread/thr_mutexattr.c +++ b/lib/libthr/thread/thr_mutexattr.c @@ -80,8 +80,12 @@ __weak_reference(_pthread_mutexattr_getpshared, pthread_mutexattr_getpshared); __weak_reference(_pthread_mutexattr_setpshared, pthread_mutexattr_setpshared); __weak_reference(_pthread_mutexattr_getprotocol, pthread_mutexattr_getprotocol); __weak_reference(_pthread_mutexattr_setprotocol, pthread_mutexattr_setprotocol); -__weak_reference(_pthread_mutexattr_getprioceiling, pthread_mutexattr_getprioceiling); -__weak_reference(_pthread_mutexattr_setprioceiling, pthread_mutexattr_setprioceiling); +__weak_reference(_pthread_mutexattr_getprioceiling, + pthread_mutexattr_getprioceiling); +__weak_reference(_pthread_mutexattr_setprioceiling, + pthread_mutexattr_setprioceiling); +__weak_reference(_pthread_mutexattr_getrobust, pthread_mutexattr_getrobust); +__weak_reference(_pthread_mutexattr_setrobust, pthread_mutexattr_setrobust); int _pthread_mutexattr_init(pthread_mutexattr_t *attr) @@ -119,26 +123,28 @@ int _pthread_mutexattr_getkind_np(pthread_mutexattr_t attr) { int ret; + if (attr == NULL) { errno = EINVAL; ret = -1; } else { ret = attr->m_type; } - return(ret); + return (ret); } int _pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type) { int ret; + if (attr == NULL || *attr == NULL || type >= PTHREAD_MUTEX_TYPE_MAX) { ret = EINVAL; } else { (*attr)->m_type = type; ret = 0; } - return(ret); + return (ret); } int @@ -153,7 +159,7 @@ _pthread_mutexattr_gettype(pthread_mutexattr_t *attr, int *type) *type = (*attr)->m_type; ret = 0; } - return ret; + return (ret); } int @@ -167,7 +173,7 @@ _pthread_mutexattr_destroy(pthread_mutexattr_t *attr) *attr = NULL; ret = 0; } - return(ret); + return (ret); } int @@ -198,12 +204,12 @@ _pthread_mutexattr_getprotocol(pthread_mutexattr_t *mattr, int *protocol) { int ret = 0; - if ((mattr == NULL) || (*mattr == NULL)) + if (mattr == NULL || *mattr == NULL) ret = EINVAL; else *protocol = (*mattr)->m_protocol; - return(ret); + return (ret); } int @@ -211,14 +217,14 @@ _pthread_mutexattr_setprotocol(pthread_mutexattr_t *mattr, int protocol) { int ret = 0; - if ((mattr == NULL) || (*mattr == NULL) || - (protocol < PTHREAD_PRIO_NONE) || (protocol > PTHREAD_PRIO_PROTECT)) + if (mattr == NULL || *mattr == NULL || + protocol < PTHREAD_PRIO_NONE || protocol > PTHREAD_PRIO_PROTECT) ret = EINVAL; else { (*mattr)->m_protocol = protocol; (*mattr)->m_ceiling = THR_MAX_RR_PRIORITY; } - return(ret); + return (ret); } int @@ -226,14 +232,14 @@ _pthread_mutexattr_getprioceiling(pthread_mutexattr_t *mattr, int *prioceiling) { int ret = 0; - if ((mattr == NULL) || (*mattr == NULL)) + if (mattr == NULL || *mattr == NULL) ret = EINVAL; else if ((*mattr)->m_protocol != PTHREAD_PRIO_PROTECT) ret = EINVAL; else *prioceiling = (*mattr)->m_ceiling; - return(ret); + return (ret); } int @@ -241,13 +247,44 @@ _pthread_mutexattr_setprioceiling(pthread_mutexattr_t *mattr, int prioceiling) { int ret = 0; - if ((mattr == NULL) || (*mattr == NULL)) + if (mattr == NULL || *mattr == NULL) ret = EINVAL; else if ((*mattr)->m_protocol != PTHREAD_PRIO_PROTECT) ret = EINVAL; else (*mattr)->m_ceiling = prioceiling; - return(ret); + return (ret); +} + +int +_pthread_mutexattr_getrobust(pthread_mutexattr_t *mattr, int *robust) +{ + int ret; + + if (mattr == NULL || *mattr == NULL) { + ret = EINVAL; + } else { + ret = 0; + *robust = (*mattr)->m_robust; + } + return (ret); +} + +int +_pthread_mutexattr_setrobust(pthread_mutexattr_t *mattr, int robust) +{ + int ret; + + if (mattr == NULL || *mattr == NULL) { + ret = EINVAL; + } else if (robust != PTHREAD_MUTEX_STALLED && + robust != PTHREAD_MUTEX_ROBUST) { + ret = EINVAL; + } else { + ret = 0; + (*mattr)->m_robust = robust; + } + return (ret); } diff --git a/lib/libthr/thread/thr_private.h b/lib/libthr/thread/thr_private.h index f35d3cd..21399f3 100644 --- a/lib/libthr/thread/thr_private.h +++ b/lib/libthr/thread/thr_private.h @@ -45,6 +45,7 @@ #include <errno.h> #include <limits.h> #include <signal.h> +#include <stdbool.h> #include <stddef.h> #include <stdio.h> #include <unistd.h> @@ -141,9 +142,11 @@ TAILQ_HEAD(mutex_queue, pthread_mutex); #define PMUTEX_FLAG_TYPE_MASK 0x0ff #define PMUTEX_FLAG_PRIVATE 0x100 -#define PMUTEX_FLAG_DEFERED 0x200 +#define PMUTEX_FLAG_DEFERRED 0x200 #define PMUTEX_TYPE(mtxflags) ((mtxflags) & PMUTEX_FLAG_TYPE_MASK) +#define PMUTEX_OWNER_ID(m) ((m)->m_lock.m_owner & ~UMUTEX_CONTESTED) + #define MAX_DEFER_WAITERS 50 /* @@ -159,7 +162,6 @@ struct pthread_mutex { */ struct umutex m_lock; int m_flags; - uint32_t m_owner; int m_count; int m_spinloops; int m_yieldloops; @@ -171,6 +173,7 @@ struct pthread_mutex { TAILQ_ENTRY(pthread_mutex) m_qe; /* Link for all private mutexes a thread currently owns. */ TAILQ_ENTRY(pthread_mutex) m_pqe; + struct pthread_mutex *m_rb_prev; }; struct pthread_mutex_attr { @@ -178,10 +181,12 @@ struct pthread_mutex_attr { int m_protocol; int m_ceiling; int m_pshared; + int m_robust; }; #define PTHREAD_MUTEXATTR_STATIC_INITIALIZER \ - { PTHREAD_MUTEX_DEFAULT, PTHREAD_PRIO_NONE, 0, MUTEX_FLAGS_PRIVATE } + { PTHREAD_MUTEX_DEFAULT, PTHREAD_PRIO_NONE, 0, MUTEX_FLAGS_PRIVATE, \ + PTHREAD_MUTEX_STALLED } struct pthread_cond { __uint32_t __has_user_waiters; @@ -491,7 +496,9 @@ struct pthread { #define TMQ_NORM_PRIV 1 /* NORMAL or PRIO_INHERIT normal priv */ #define TMQ_NORM_PP 2 /* PRIO_PROTECT normal mutexes */ #define TMQ_NORM_PP_PRIV 3 /* PRIO_PROTECT normal priv */ -#define TMQ_NITEMS 4 +#define TMQ_ROBUST_PP 4 /* PRIO_PROTECT robust mutexes */ +#define TMQ_ROBUST_PP_PRIV 5 /* PRIO_PROTECT robust priv */ +#define TMQ_NITEMS 6 struct mutex_queue mq[TMQ_NITEMS]; void *ret; @@ -545,6 +552,11 @@ struct pthread { /* Number of threads deferred. */ int nwaiter_defer; + int robust_inited; + uintptr_t robust_list; + uintptr_t priv_robust_list; + uintptr_t inact_mtx; + /* Deferred threads from pthread_cond_signal. */ unsigned int *defer_waiters[MAX_DEFER_WAITERS]; #define _pthread_endzero wake_addr @@ -754,13 +766,17 @@ extern struct pthread *_single_thread __hidden; */ __BEGIN_DECLS int _thr_setthreaded(int) __hidden; -int _mutex_cv_lock(struct pthread_mutex *, int) __hidden; +int _mutex_cv_lock(struct pthread_mutex *, int, bool) __hidden; int _mutex_cv_unlock(struct pthread_mutex *, int *, int *) __hidden; int _mutex_cv_attach(struct pthread_mutex *, int) __hidden; int _mutex_cv_detach(struct pthread_mutex *, int *) __hidden; int _mutex_owned(struct pthread *, const struct pthread_mutex *) __hidden; int _mutex_reinit(pthread_mutex_t *) __hidden; void _mutex_fork(struct pthread *curthread) __hidden; +int _mutex_enter_robust(struct pthread *curthread, struct pthread_mutex *m) + __hidden; +void _mutex_leave_robust(struct pthread *curthread, struct pthread_mutex *m) + __hidden; void _libpthread_init(struct pthread *) __hidden; struct pthread *_thr_alloc(struct pthread *) __hidden; void _thread_exit(const char *, int, const char *) __hidden __dead2; @@ -819,6 +835,11 @@ void _pthread_cleanup_pop(int); void _pthread_exit_mask(void *status, sigset_t *mask) __dead2 __hidden; void _pthread_cancel_enter(int maycancel); void _pthread_cancel_leave(int maycancel); +int _pthread_mutex_consistent(pthread_mutex_t *) __nonnull(1); +int _pthread_mutexattr_getrobust(pthread_mutexattr_t *__restrict, + int *__restrict) __nonnull_all; +int _pthread_mutexattr_setrobust(pthread_mutexattr_t *, int) + __nonnull(1); /* #include <fcntl.h> */ #ifdef _SYS_FCNTL_H_ diff --git a/lib/libthr/thread/thr_umtx.c b/lib/libthr/thread/thr_umtx.c index ebf344b..cd2b101 100644 --- a/lib/libthr/thread/thr_umtx.c +++ b/lib/libthr/thread/thr_umtx.c @@ -33,6 +33,7 @@ __FBSDID("$FreeBSD$"); #ifndef HAS__UMTX_OP_ERR int _umtx_op_err(void *obj, int op, u_long val, void *uaddr, void *uaddr2) { + if (_umtx_op(obj, op, val, uaddr, uaddr2) == -1) return (errno); return (0); @@ -60,19 +61,24 @@ __thr_umutex_lock(struct umutex *mtx, uint32_t id) { uint32_t owner; - if ((mtx->m_flags & (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT)) == 0) { - for (;;) { - /* wait in kernel */ - _umtx_op_err(mtx, UMTX_OP_MUTEX_WAIT, 0, 0, 0); + if ((mtx->m_flags & (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT)) != 0) + return (_umtx_op_err(mtx, UMTX_OP_MUTEX_LOCK, 0, 0, 0)); - owner = mtx->m_owner; - if ((owner & ~UMUTEX_CONTESTED) == 0 && - atomic_cmpset_acq_32(&mtx->m_owner, owner, id|owner)) - return (0); - } + for (;;) { + owner = mtx->m_owner; + if ((owner & ~UMUTEX_CONTESTED) == 0 && + atomic_cmpset_acq_32(&mtx->m_owner, owner, id | owner)) + return (0); + if (owner == UMUTEX_RB_OWNERDEAD && + atomic_cmpset_acq_32(&mtx->m_owner, owner, + id | UMUTEX_CONTESTED)) + return (EOWNERDEAD); + if (owner == UMUTEX_RB_NOTRECOV) + return (ENOTRECOVERABLE); + + /* wait in kernel */ + _umtx_op_err(mtx, UMTX_OP_MUTEX_WAIT, 0, 0, 0); } - - return _umtx_op_err(mtx, UMTX_OP_MUTEX_LOCK, 0, 0, 0); } #define SPINLOOPS 1000 @@ -81,31 +87,33 @@ int __thr_umutex_lock_spin(struct umutex *mtx, uint32_t id) { uint32_t owner; + int count; if (!_thr_is_smp) - return __thr_umutex_lock(mtx, id); - - if ((mtx->m_flags & (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT)) == 0) { - for (;;) { - int count = SPINLOOPS; - while (count--) { - owner = mtx->m_owner; - if ((owner & ~UMUTEX_CONTESTED) == 0) { - if (atomic_cmpset_acq_32( - &mtx->m_owner, - owner, id|owner)) { - return (0); - } - } - CPU_SPINWAIT; - } + return (__thr_umutex_lock(mtx, id)); + if ((mtx->m_flags & (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT)) != 0) + return (_umtx_op_err(mtx, UMTX_OP_MUTEX_LOCK, 0, 0, 0)); - /* wait in kernel */ - _umtx_op_err(mtx, UMTX_OP_MUTEX_WAIT, 0, 0, 0); + for (;;) { + count = SPINLOOPS; + while (count--) { + owner = mtx->m_owner; + if ((owner & ~UMUTEX_CONTESTED) == 0 && + atomic_cmpset_acq_32(&mtx->m_owner, owner, + id | owner)) + return (0); + if (__predict_false(owner == UMUTEX_RB_OWNERDEAD) && + atomic_cmpset_acq_32(&mtx->m_owner, owner, + id | UMUTEX_CONTESTED)) + return (EOWNERDEAD); + if (__predict_false(owner == UMUTEX_RB_NOTRECOV)) + return (ENOTRECOVERABLE); + CPU_SPINWAIT; } - } - return _umtx_op_err(mtx, UMTX_OP_MUTEX_LOCK, 0, 0, 0); + /* wait in kernel */ + _umtx_op_err(mtx, UMTX_OP_MUTEX_WAIT, 0, 0, 0); + } } int @@ -129,21 +137,28 @@ __thr_umutex_timedlock(struct umutex *mtx, uint32_t id, } for (;;) { - if ((mtx->m_flags & (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT)) == 0) { - - /* wait in kernel */ - ret = _umtx_op_err(mtx, UMTX_OP_MUTEX_WAIT, 0, - (void *)tm_size, __DECONST(void *, tm_p)); - - /* now try to lock it */ + if ((mtx->m_flags & (UMUTEX_PRIO_PROTECT | + UMUTEX_PRIO_INHERIT)) == 0) { + /* try to lock it */ owner = mtx->m_owner; if ((owner & ~UMUTEX_CONTESTED) == 0 && - atomic_cmpset_acq_32(&mtx->m_owner, owner, id|owner)) + atomic_cmpset_acq_32(&mtx->m_owner, owner, + id | owner)) return (0); + if (__predict_false(owner == UMUTEX_RB_OWNERDEAD) && + atomic_cmpset_acq_32(&mtx->m_owner, owner, + id | UMUTEX_CONTESTED)) + return (EOWNERDEAD); + if (__predict_false(owner == UMUTEX_RB_NOTRECOV)) + return (ENOTRECOVERABLE); + /* wait in kernel */ + ret = _umtx_op_err(mtx, UMTX_OP_MUTEX_WAIT, 0, + (void *)tm_size, __DECONST(void *, tm_p)); } else { ret = _umtx_op_err(mtx, UMTX_OP_MUTEX_LOCK, 0, - (void *)tm_size, __DECONST(void *, tm_p)); - if (ret == 0) + (void *)tm_size, __DECONST(void *, tm_p)); + if (ret == 0 || ret == EOWNERDEAD || + ret == ENOTRECOVERABLE) break; } if (ret == ETIMEDOUT) @@ -155,46 +170,52 @@ __thr_umutex_timedlock(struct umutex *mtx, uint32_t id, int __thr_umutex_unlock(struct umutex *mtx, uint32_t id) { - return _umtx_op_err(mtx, UMTX_OP_MUTEX_UNLOCK, 0, 0, 0); + + return (_umtx_op_err(mtx, UMTX_OP_MUTEX_UNLOCK, 0, 0, 0)); } int __thr_umutex_trylock(struct umutex *mtx) { - return _umtx_op_err(mtx, UMTX_OP_MUTEX_TRYLOCK, 0, 0, 0); + + return (_umtx_op_err(mtx, UMTX_OP_MUTEX_TRYLOCK, 0, 0, 0)); } int __thr_umutex_set_ceiling(struct umutex *mtx, uint32_t ceiling, - uint32_t *oldceiling) + uint32_t *oldceiling) { - return _umtx_op_err(mtx, UMTX_OP_SET_CEILING, ceiling, oldceiling, 0); + + return (_umtx_op_err(mtx, UMTX_OP_SET_CEILING, ceiling, oldceiling, 0)); } int _thr_umtx_wait(volatile long *mtx, long id, const struct timespec *timeout) { + if (timeout && (timeout->tv_sec < 0 || (timeout->tv_sec == 0 && - timeout->tv_nsec <= 0))) + timeout->tv_nsec <= 0))) return (ETIMEDOUT); - return _umtx_op_err(__DEVOLATILE(void *, mtx), UMTX_OP_WAIT, id, 0, - __DECONST(void*, timeout)); + return (_umtx_op_err(__DEVOLATILE(void *, mtx), UMTX_OP_WAIT, id, 0, + __DECONST(void*, timeout))); } int -_thr_umtx_wait_uint(volatile u_int *mtx, u_int id, const struct timespec *timeout, int shared) +_thr_umtx_wait_uint(volatile u_int *mtx, u_int id, + const struct timespec *timeout, int shared) { + if (timeout && (timeout->tv_sec < 0 || (timeout->tv_sec == 0 && - timeout->tv_nsec <= 0))) + timeout->tv_nsec <= 0))) return (ETIMEDOUT); - return _umtx_op_err(__DEVOLATILE(void *, mtx), - shared ? UMTX_OP_WAIT_UINT : UMTX_OP_WAIT_UINT_PRIVATE, id, 0, - __DECONST(void*, timeout)); + return (_umtx_op_err(__DEVOLATILE(void *, mtx), shared ? + UMTX_OP_WAIT_UINT : UMTX_OP_WAIT_UINT_PRIVATE, id, 0, + __DECONST(void*, timeout))); } int _thr_umtx_timedwait_uint(volatile u_int *mtx, u_int id, int clockid, - const struct timespec *abstime, int shared) + const struct timespec *abstime, int shared) { struct _umtx_time *tm_p, timeout; size_t tm_size; @@ -210,21 +231,23 @@ _thr_umtx_timedwait_uint(volatile u_int *mtx, u_int id, int clockid, tm_size = sizeof(timeout); } - return _umtx_op_err(__DEVOLATILE(void *, mtx), - shared ? UMTX_OP_WAIT_UINT : UMTX_OP_WAIT_UINT_PRIVATE, id, - (void *)tm_size, __DECONST(void *, tm_p)); + return (_umtx_op_err(__DEVOLATILE(void *, mtx), shared ? + UMTX_OP_WAIT_UINT : UMTX_OP_WAIT_UINT_PRIVATE, id, + (void *)tm_size, __DECONST(void *, tm_p))); } int _thr_umtx_wake(volatile void *mtx, int nr_wakeup, int shared) { - return _umtx_op_err(__DEVOLATILE(void *, mtx), shared ? UMTX_OP_WAKE : UMTX_OP_WAKE_PRIVATE, - nr_wakeup, 0, 0); + + return (_umtx_op_err(__DEVOLATILE(void *, mtx), shared ? + UMTX_OP_WAKE : UMTX_OP_WAKE_PRIVATE, nr_wakeup, 0, 0)); } void _thr_ucond_init(struct ucond *cv) { + bzero(cv, sizeof(struct ucond)); } @@ -232,30 +255,34 @@ int _thr_ucond_wait(struct ucond *cv, struct umutex *m, const struct timespec *timeout, int flags) { + struct pthread *curthread; + if (timeout && (timeout->tv_sec < 0 || (timeout->tv_sec == 0 && timeout->tv_nsec <= 0))) { - struct pthread *curthread = _get_curthread(); + curthread = _get_curthread(); _thr_umutex_unlock(m, TID(curthread)); return (ETIMEDOUT); } - return _umtx_op_err(cv, UMTX_OP_CV_WAIT, flags, - m, __DECONST(void*, timeout)); + return (_umtx_op_err(cv, UMTX_OP_CV_WAIT, flags, m, + __DECONST(void*, timeout))); } int _thr_ucond_signal(struct ucond *cv) { + if (!cv->c_has_waiters) return (0); - return _umtx_op_err(cv, UMTX_OP_CV_SIGNAL, 0, NULL, NULL); + return (_umtx_op_err(cv, UMTX_OP_CV_SIGNAL, 0, NULL, NULL)); } int _thr_ucond_broadcast(struct ucond *cv) { + if (!cv->c_has_waiters) return (0); - return _umtx_op_err(cv, UMTX_OP_CV_BROADCAST, 0, NULL, NULL); + return (_umtx_op_err(cv, UMTX_OP_CV_BROADCAST, 0, NULL, NULL)); } int @@ -275,7 +302,8 @@ __thr_rwlock_rdlock(struct urwlock *rwlock, int flags, tm_p = &timeout; tm_size = sizeof(timeout); } - return _umtx_op_err(rwlock, UMTX_OP_RW_RDLOCK, flags, (void *)tm_size, tm_p); + return (_umtx_op_err(rwlock, UMTX_OP_RW_RDLOCK, flags, + (void *)tm_size, tm_p)); } int @@ -294,13 +322,15 @@ __thr_rwlock_wrlock(struct urwlock *rwlock, const struct timespec *tsp) tm_p = &timeout; tm_size = sizeof(timeout); } - return _umtx_op_err(rwlock, UMTX_OP_RW_WRLOCK, 0, (void *)tm_size, tm_p); + return (_umtx_op_err(rwlock, UMTX_OP_RW_WRLOCK, 0, (void *)tm_size, + tm_p)); } int __thr_rwlock_unlock(struct urwlock *rwlock) { - return _umtx_op_err(rwlock, UMTX_OP_RW_UNLOCK, 0, NULL, NULL); + + return (_umtx_op_err(rwlock, UMTX_OP_RW_UNLOCK, 0, NULL, NULL)); } void @@ -338,6 +368,7 @@ _thr_rwl_wrlock(struct urwlock *rwlock) void _thr_rwl_unlock(struct urwlock *rwlock) { + if (_thr_rwlock_unlock(rwlock)) PANIC("unlock error"); } diff --git a/lib/libthr/thread/thr_umtx.h b/lib/libthr/thread/thr_umtx.h index 2c289a7..fff8729 100644 --- a/lib/libthr/thread/thr_umtx.h +++ b/lib/libthr/thread/thr_umtx.h @@ -32,7 +32,11 @@ #include <strings.h> #include <sys/umtx.h> -#define DEFAULT_UMUTEX {0,0,{0,0},{0,0,0,0}} +#ifdef __LP64__ +#define DEFAULT_UMUTEX {0,0,{0,0},0,{0,0}} +#else +#define DEFAULT_UMUTEX {0,0,{0,0},0,0,{0,0}} +#endif #define DEFAULT_URWLOCK {0,0,0,0,{0,0,0,0}} int _umtx_op_err(void *, int op, u_long, void *, void *) __hidden; @@ -75,95 +79,122 @@ void _thr_rwl_unlock(struct urwlock *rwlock) __hidden; static inline int _thr_umutex_trylock(struct umutex *mtx, uint32_t id) { - if (atomic_cmpset_acq_32(&mtx->m_owner, UMUTEX_UNOWNED, id)) - return (0); - if ((mtx->m_flags & UMUTEX_PRIO_PROTECT) == 0) - return (EBUSY); - return (__thr_umutex_trylock(mtx)); + + if (atomic_cmpset_acq_32(&mtx->m_owner, UMUTEX_UNOWNED, id)) + return (0); + if (__predict_false((uint32_t)mtx->m_owner == UMUTEX_RB_OWNERDEAD) && + atomic_cmpset_acq_32(&mtx->m_owner, UMUTEX_RB_OWNERDEAD, + id | UMUTEX_CONTESTED)) + return (EOWNERDEAD); + if (__predict_false((uint32_t)mtx->m_owner == UMUTEX_RB_NOTRECOV)) + return (ENOTRECOVERABLE); + if ((mtx->m_flags & UMUTEX_PRIO_PROTECT) == 0) + return (EBUSY); + return (__thr_umutex_trylock(mtx)); } static inline int _thr_umutex_trylock2(struct umutex *mtx, uint32_t id) { - if (atomic_cmpset_acq_32(&mtx->m_owner, UMUTEX_UNOWNED, id) != 0) - return (0); - if ((uint32_t)mtx->m_owner == UMUTEX_CONTESTED && - __predict_true((mtx->m_flags & (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT)) == 0)) - if (atomic_cmpset_acq_32(&mtx->m_owner, UMUTEX_CONTESTED, id | UMUTEX_CONTESTED)) + + if (atomic_cmpset_acq_32(&mtx->m_owner, UMUTEX_UNOWNED, id) != 0) return (0); - return (EBUSY); + if ((uint32_t)mtx->m_owner == UMUTEX_CONTESTED && + __predict_true((mtx->m_flags & (UMUTEX_PRIO_PROTECT | + UMUTEX_PRIO_INHERIT)) == 0) && + atomic_cmpset_acq_32(&mtx->m_owner, UMUTEX_CONTESTED, + id | UMUTEX_CONTESTED)) + return (0); + if (__predict_false((uint32_t)mtx->m_owner == UMUTEX_RB_OWNERDEAD) && + atomic_cmpset_acq_32(&mtx->m_owner, UMUTEX_RB_OWNERDEAD, + id | UMUTEX_CONTESTED)) + return (EOWNERDEAD); + if (__predict_false((uint32_t)mtx->m_owner == UMUTEX_RB_NOTRECOV)) + return (ENOTRECOVERABLE); + return (EBUSY); } static inline int _thr_umutex_lock(struct umutex *mtx, uint32_t id) { - if (_thr_umutex_trylock2(mtx, id) == 0) - return (0); - return (__thr_umutex_lock(mtx, id)); + + if (_thr_umutex_trylock2(mtx, id) == 0) + return (0); + return (__thr_umutex_lock(mtx, id)); } static inline int _thr_umutex_lock_spin(struct umutex *mtx, uint32_t id) { - if (_thr_umutex_trylock2(mtx, id) == 0) - return (0); - return (__thr_umutex_lock_spin(mtx, id)); + + if (_thr_umutex_trylock2(mtx, id) == 0) + return (0); + return (__thr_umutex_lock_spin(mtx, id)); } static inline int _thr_umutex_timedlock(struct umutex *mtx, uint32_t id, - const struct timespec *timeout) + const struct timespec *timeout) { - if (_thr_umutex_trylock2(mtx, id) == 0) - return (0); - return (__thr_umutex_timedlock(mtx, id, timeout)); + + if (_thr_umutex_trylock2(mtx, id) == 0) + return (0); + return (__thr_umutex_timedlock(mtx, id, timeout)); } static inline int _thr_umutex_unlock2(struct umutex *mtx, uint32_t id, int *defer) { - uint32_t flags = mtx->m_flags; + uint32_t flags, owner; + bool noncst; - if ((flags & (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT)) == 0) { - uint32_t owner; - do { - owner = mtx->m_owner; - if (__predict_false((owner & ~UMUTEX_CONTESTED) != id)) - return (EPERM); - } while (__predict_false(!atomic_cmpset_rel_32(&mtx->m_owner, - owner, UMUTEX_UNOWNED))); - if ((owner & UMUTEX_CONTESTED)) { - if (defer == NULL) - (void)_umtx_op_err(mtx, UMTX_OP_MUTEX_WAKE2, flags, 0, 0); - else - *defer = 1; - } - return (0); + flags = mtx->m_flags; + noncst = (flags & UMUTEX_NONCONSISTENT) != 0; + + if ((flags & (UMUTEX_PRIO_PROTECT | UMUTEX_PRIO_INHERIT)) != 0) { + if (atomic_cmpset_rel_32(&mtx->m_owner, id, noncst ? + UMUTEX_RB_NOTRECOV : UMUTEX_UNOWNED)) + return (0); + return (__thr_umutex_unlock(mtx, id)); } - if (atomic_cmpset_rel_32(&mtx->m_owner, id, UMUTEX_UNOWNED)) - return (0); - return (__thr_umutex_unlock(mtx, id)); + + do { + owner = mtx->m_owner; + if (__predict_false((owner & ~UMUTEX_CONTESTED) != id)) + return (EPERM); + } while (__predict_false(!atomic_cmpset_rel_32(&mtx->m_owner, owner, + noncst ? UMUTEX_RB_NOTRECOV : UMUTEX_UNOWNED))); + if ((owner & UMUTEX_CONTESTED) != 0) { + if (defer == NULL || noncst) + (void)_umtx_op_err(mtx, UMTX_OP_MUTEX_WAKE2, + flags, 0, 0); + else + *defer = 1; + } + return (0); } static inline int _thr_umutex_unlock(struct umutex *mtx, uint32_t id) { - return _thr_umutex_unlock2(mtx, id, NULL); + + return (_thr_umutex_unlock2(mtx, id, NULL)); } static inline int _thr_rwlock_tryrdlock(struct urwlock *rwlock, int flags) { - int32_t state; - int32_t wrflags; + int32_t state, wrflags; - if (flags & URWLOCK_PREFER_READER || rwlock->rw_flags & URWLOCK_PREFER_READER) + if ((flags & URWLOCK_PREFER_READER) != 0 || + (rwlock->rw_flags & URWLOCK_PREFER_READER) != 0) wrflags = URWLOCK_WRITE_OWNER; else wrflags = URWLOCK_WRITE_OWNER | URWLOCK_WRITE_WAITERS; state = rwlock->rw_state; while (!(state & wrflags)) { - if (__predict_false(URWLOCK_READER_COUNT(state) == URWLOCK_MAX_READERS)) + if (__predict_false(URWLOCK_READER_COUNT(state) == + URWLOCK_MAX_READERS)) return (EAGAIN); if (atomic_cmpset_acq_32(&rwlock->rw_state, state, state + 1)) return (0); @@ -179,8 +210,10 @@ _thr_rwlock_trywrlock(struct urwlock *rwlock) int32_t state; state = rwlock->rw_state; - while (!(state & URWLOCK_WRITE_OWNER) && URWLOCK_READER_COUNT(state) == 0) { - if (atomic_cmpset_acq_32(&rwlock->rw_state, state, state | URWLOCK_WRITE_OWNER)) + while ((state & URWLOCK_WRITE_OWNER) == 0 && + URWLOCK_READER_COUNT(state) == 0) { + if (atomic_cmpset_acq_32(&rwlock->rw_state, state, + state | URWLOCK_WRITE_OWNER)) return (0); state = rwlock->rw_state; } @@ -191,6 +224,7 @@ _thr_rwlock_trywrlock(struct urwlock *rwlock) static inline int _thr_rwlock_rdlock(struct urwlock *rwlock, int flags, struct timespec *tsp) { + if (_thr_rwlock_tryrdlock(rwlock, flags) == 0) return (0); return (__thr_rwlock_rdlock(rwlock, flags, tsp)); @@ -199,6 +233,7 @@ _thr_rwlock_rdlock(struct urwlock *rwlock, int flags, struct timespec *tsp) static inline int _thr_rwlock_wrlock(struct urwlock *rwlock, struct timespec *tsp) { + if (_thr_rwlock_trywrlock(rwlock) == 0) return (0); return (__thr_rwlock_wrlock(rwlock, tsp)); @@ -210,18 +245,19 @@ _thr_rwlock_unlock(struct urwlock *rwlock) int32_t state; state = rwlock->rw_state; - if (state & URWLOCK_WRITE_OWNER) { - if (atomic_cmpset_rel_32(&rwlock->rw_state, URWLOCK_WRITE_OWNER, 0)) + if ((state & URWLOCK_WRITE_OWNER) != 0) { + if (atomic_cmpset_rel_32(&rwlock->rw_state, + URWLOCK_WRITE_OWNER, 0)) return (0); } else { for (;;) { if (__predict_false(URWLOCK_READER_COUNT(state) == 0)) return (EPERM); if (!((state & (URWLOCK_WRITE_WAITERS | - URWLOCK_READ_WAITERS)) && + URWLOCK_READ_WAITERS)) != 0 && URWLOCK_READER_COUNT(state) == 1)) { if (atomic_cmpset_rel_32(&rwlock->rw_state, - state, state-1)) + state, state - 1)) return (0); state = rwlock->rw_state; } else { diff --git a/lib/libufs/cgroup.c b/lib/libufs/cgroup.c index 8ab33f7..dfb10d3 100644 --- a/lib/libufs/cgroup.c +++ b/lib/libufs/cgroup.c @@ -157,7 +157,7 @@ gotit: bzero(block, (int)fs->fs_bsize); dp2 = (struct ufs2_dinode *)█ for (i = 0; i < INOPB(fs); i++) { - dp2->di_gen = arc4random() / 2 + 1; + dp2->di_gen = arc4random(); dp2++; } if (bwrite(disk, ino_to_fsba(fs, diff --git a/lib/libutil/login_auth.c b/lib/libutil/login_auth.c index 1fc7e73..647db1e 100644 --- a/lib/libutil/login_auth.c +++ b/lib/libutil/login_auth.c @@ -55,7 +55,7 @@ __FBSDID("$FreeBSD$"); /* * auth_checknologin() - * Checks for the existance of a nologin file in the login_cap + * Checks for the existence of a nologin file in the login_cap * capability <lc>. If there isn't one specified, then it checks * to see if this class should just ignore nologin files. Lastly, * it tries to print out the default nologin file, and, if such diff --git a/lib/libutil/login_cap.c b/lib/libutil/login_cap.c index 8915d0a..9c8d4a6 100644 --- a/lib/libutil/login_cap.c +++ b/lib/libutil/login_cap.c @@ -742,7 +742,7 @@ login_getcapsize(login_cap_t *lc, const char *cap, rlim_t def, rlim_t error) /* * login_getcapbool() - * From the login_cap_t <lc>, check for the existance of the capability + * From the login_cap_t <lc>, check for the existence of the capability * of <cap>. Return <def> if <lc>->lc_cap is NULL, otherwise return * the whether or not <cap> exists there. */ diff --git a/lib/libutil/pidfile.3 b/lib/libutil/pidfile.3 index d5e2470..845b11a 100644 --- a/lib/libutil/pidfile.3 +++ b/lib/libutil/pidfile.3 @@ -151,7 +151,7 @@ if (pfh == NULL) { /* If we cannot create pidfile from other reasons, only warn. */ warn("Cannot open or create pidfile"); /* - * Eventhough pfh is NULL we can continue, as the other pidfile_* + * Even though pfh is NULL we can continue, as the other pidfile_* * function can handle such situation by doing nothing except setting * errno to EDOOFUS. */ diff --git a/lib/libutil/pidfile.c b/lib/libutil/pidfile.c index 3a5e512..157a53c 100644 --- a/lib/libutil/pidfile.c +++ b/lib/libutil/pidfile.c @@ -119,7 +119,7 @@ pidfile_open(const char *path, mode_t mode, pid_t *pidptr) /* * Open the PID file and obtain exclusive lock. - * We truncate PID file here only to remove old PID immediatelly, + * We truncate PID file here only to remove old PID immediately, * PID file will be truncated again in pidfile_write(), so * pidfile_write() can be called multiple times. */ diff --git a/lib/msun/arm/Makefile.inc b/lib/msun/arm/Makefile.inc index 535d5ea..eb73e63 100644 --- a/lib/msun/arm/Makefile.inc +++ b/lib/msun/arm/Makefile.inc @@ -3,7 +3,7 @@ LDBL_PREC = 53 SYM_MAPS += ${.CURDIR}/arm/Symbol.map -.if ${TARGET_ARCH} == "armv6" +.if ${MACHINE_ARCH:Marmv6*} && defined(CPUTYPE) && ${CPUTYPE:M*soft*} != "" ARCH_SRCS = fenv-softfp.c fenv-vfp.c .endif diff --git a/lib/msun/arm/fenv-vfp.c b/lib/msun/arm/fenv-vfp.c index fd615f3..ee02ae8 100644 --- a/lib/msun/arm/fenv-vfp.c +++ b/lib/msun/arm/fenv-vfp.c @@ -28,6 +28,8 @@ #define FENV_MANGLE(x) __vfp_ ##x #include "fenv-mangle.h" -#define __ARM_PCS_VFP +#ifndef __ARM_PCS_VFP +#define __ARM_PCS_VFP 1 +#endif #include "fenv.c" diff --git a/sbin/dhclient/dhclient.c b/sbin/dhclient/dhclient.c index 7da12aa..65f0eb5 100644 --- a/sbin/dhclient/dhclient.c +++ b/sbin/dhclient/dhclient.c @@ -56,8 +56,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include <stddef.h> - #include "dhcpd.h" #include "privsep.h" @@ -1572,18 +1570,16 @@ make_discover(struct interface_info *ip, struct client_lease *lease) } /* set unique client identifier */ - struct hardware client_ident; + char client_ident[sizeof(ip->hw_address.haddr) + 1]; if (!options[DHO_DHCP_CLIENT_IDENTIFIER]) { - size_t hwlen = MIN(ip->hw_address.hlen, - sizeof(client_ident.haddr)); - client_ident.htype = ip->hw_address.htype; - client_ident.hlen = hwlen; - memcpy(client_ident.haddr, ip->hw_address.haddr, hwlen); + int hwlen = (ip->hw_address.hlen < sizeof(client_ident)-1) ? + ip->hw_address.hlen : sizeof(client_ident)-1; + client_ident[0] = ip->hw_address.htype; + memcpy(&client_ident[1], ip->hw_address.haddr, hwlen); options[DHO_DHCP_CLIENT_IDENTIFIER] = &option_elements[DHO_DHCP_CLIENT_IDENTIFIER]; - options[DHO_DHCP_CLIENT_IDENTIFIER]->value = (void *)&client_ident; - hwlen += offsetof(struct hardware, haddr); - options[DHO_DHCP_CLIENT_IDENTIFIER]->len = hwlen; - options[DHO_DHCP_CLIENT_IDENTIFIER]->buf_size = hwlen; + options[DHO_DHCP_CLIENT_IDENTIFIER]->value = client_ident; + options[DHO_DHCP_CLIENT_IDENTIFIER]->len = hwlen+1; + options[DHO_DHCP_CLIENT_IDENTIFIER]->buf_size = hwlen+1; options[DHO_DHCP_CLIENT_IDENTIFIER]->timeout = 0xFFFFFFFF; } @@ -1609,8 +1605,8 @@ make_discover(struct interface_info *ip, struct client_lease *lease) 0, sizeof(ip->client->packet.siaddr)); memset(&(ip->client->packet.giaddr), 0, sizeof(ip->client->packet.giaddr)); - memcpy(ip->client->packet.chaddr, ip->hw_address.haddr, - MIN(ip->hw_address.hlen, sizeof(ip->client->packet.chaddr))); + memcpy(ip->client->packet.chaddr, + ip->hw_address.haddr, ip->hw_address.hlen); } diff --git a/sbin/ipfw/ipfw2.c b/sbin/ipfw/ipfw2.c index 5389268..b2fbf35 100644 --- a/sbin/ipfw/ipfw2.c +++ b/sbin/ipfw/ipfw2.c @@ -2280,6 +2280,9 @@ ipfw_sets_handler(char *av[]) if (!isdigit(*(av[2])) || rt.new_set > RESVD_SET) errx(EX_DATAERR, "invalid dest. set %s\n", av[1]); i = do_range_cmd(cmd, &rt); + if (i < 0) + err(EX_OSERR, "failed to move %s", + cmd == IP_FW_SET_MOVE ? "set": "rule"); } else if (_substrcmp(*av, "disable") == 0 || _substrcmp(*av, "enable") == 0 ) { int which = _substrcmp(*av, "enable") == 0 ? 1 : 0; @@ -5128,11 +5131,35 @@ static struct _s_x intcmds[] = { { NULL, 0 } }; +static struct _s_x otypes[] = { + { "EACTION", IPFW_TLV_EACTION }, + { NULL, 0 } +}; + +static const char* +lookup_eaction_name(ipfw_obj_ntlv *ntlv, int cnt, uint16_t type) +{ + const char *name; + int i; + + name = NULL; + for (i = 0; i < cnt; i++) { + if (ntlv[i].head.type != IPFW_TLV_EACTION) + continue; + if (IPFW_TLV_EACTION_NAME(ntlv[i].idx) != type) + continue; + name = ntlv[i].name; + break; + } + return (name); +} + static void ipfw_list_objects(int ac, char *av[]) { ipfw_obj_lheader req, *olh; ipfw_obj_ntlv *ntlv; + const char *name; size_t sz; int i; @@ -5158,8 +5185,17 @@ ipfw_list_objects(int ac, char *av[]) printf("There are no objects\n"); ntlv = (ipfw_obj_ntlv *)(olh + 1); for (i = 0; i < olh->count; i++) { - printf(" kidx: %4d\ttype: %6d\tname: %s\n", ntlv->idx, - ntlv->head.type, ntlv->name); + name = match_value(otypes, ntlv->head.type); + if (name == NULL) + name = lookup_eaction_name( + (ipfw_obj_ntlv *)(olh + 1), olh->count, + ntlv->head.type); + if (name == NULL) + printf(" kidx: %4d\ttype: %10d\tname: %s\n", + ntlv->idx, ntlv->head.type, ntlv->name); + else + printf(" kidx: %4d\ttype: %10s\tname: %s\n", + ntlv->idx, name, ntlv->name); ntlv++; } free(olh); diff --git a/share/doc/usd/07.mail/mail6.nr b/share/doc/usd/07.mail/mail6.nr index 5af9f86..b8084cf 100644 --- a/share/doc/usd/07.mail/mail6.nr +++ b/share/doc/usd/07.mail/mail6.nr @@ -75,7 +75,7 @@ is a shorthand way of doing Use the .b \-v flag when invoking sendmail. This feature may also be enabled -by setting the the option "verbose". +by setting the option "verbose". .pp The following command line flags are also recognized, but are intended for use by programs invoking diff --git a/share/man/man3/Makefile b/share/man/man3/Makefile index 2a3c12a..72e4c54 100644 --- a/share/man/man3/Makefile +++ b/share/man/man3/Makefile @@ -238,6 +238,7 @@ PTHREAD_MAN= pthread.3 \ pthread_multi_np.3 \ pthread_mutexattr.3 \ pthread_mutexattr_getkind_np.3 \ + pthread_mutex_consistent.3 \ pthread_mutex_destroy.3 \ pthread_mutex_init.3 \ pthread_mutex_lock.3 \ @@ -312,10 +313,12 @@ PTHREAD_MLINKS+=pthread_multi_np.3 pthread_single_np.3 PTHREAD_MLINKS+=pthread_mutexattr.3 pthread_mutexattr_destroy.3 \ pthread_mutexattr.3 pthread_mutexattr_getprioceiling.3 \ pthread_mutexattr.3 pthread_mutexattr_getprotocol.3 \ + pthread_mutexattr.3 pthread_mutexattr_getrobust.3 \ pthread_mutexattr.3 pthread_mutexattr_gettype.3 \ pthread_mutexattr.3 pthread_mutexattr_init.3 \ pthread_mutexattr.3 pthread_mutexattr_setprioceiling.3 \ pthread_mutexattr.3 pthread_mutexattr_setprotocol.3 \ + pthread_mutexattr.3 pthread_mutexattr_setrobust.3 \ pthread_mutexattr.3 pthread_mutexattr_settype.3 PTHREAD_MLINKS+=pthread_mutexattr_getkind_np.3 pthread_mutexattr_setkind_np.3 PTHREAD_MLINKS+=pthread_rwlock_rdlock.3 pthread_rwlock_tryrdlock.3 diff --git a/share/man/man3/pthread_cond_wait.3 b/share/man/man3/pthread_cond_wait.3 index c057098..427c347 100644 --- a/share/man/man3/pthread_cond_wait.3 +++ b/share/man/man3/pthread_cond_wait.3 @@ -27,7 +27,7 @@ .\" .\" $FreeBSD$ .\" -.Dd February 16, 2006 +.Dd April 29, 2016 .Dt PTHREAD_COND_WAIT 3 .Os .Sh NAME @@ -75,13 +75,25 @@ is invalid. The specified .Fa mutex was not locked by the calling thread. +.It Bq Er EOWNERDEAD +The argument +.Fa mutex +points to a robust mutex and the previous owning thread terminated +while holding the mutex lock. +The lock was granted to the caller and it is up to the new owner +to make the state consistent. +.It Bq Er ENOTRECOVERABLE +The state protected by the +.Fa mutex +is not recoverable. .El .Sh SEE ALSO .Xr pthread_cond_broadcast 3 , .Xr pthread_cond_destroy 3 , .Xr pthread_cond_init 3 , .Xr pthread_cond_signal 3 , -.Xr pthread_cond_timedwait 3 +.Xr pthread_cond_timedwait 3 , +.Xr pthread_mutex_consistent 3 .Sh STANDARDS The .Fn pthread_cond_wait diff --git a/share/man/man3/pthread_mutex_consistent.3 b/share/man/man3/pthread_mutex_consistent.3 new file mode 100644 index 0000000..67bfbcb --- /dev/null +++ b/share/man/man3/pthread_mutex_consistent.3 @@ -0,0 +1,94 @@ +.\" Copyright (c) 2016 The FreeBSD Foundation, Inc. +.\" All rights reserved. +.\" +.\" This documentation was written by +.\" Konstantin Belousov <kib@FreeBSD.org> under sponsorship +.\" from the FreeBSD Foundation. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd May 8, 2016 +.Dt PTHREAD_MUTEX_CONSISTENT 3 +.Os +.Sh NAME +.Nm pthread_mutex_consistent +.Nd mark state protected by robust mutex as consistent +.Sh LIBRARY +.Lb libpthread +.Sh SYNOPSIS +.In pthread.h +.Ft int +.Fn pthread_mutex_consistent "pthread_mutex_t *mutex" +.Sh DESCRIPTION +If the thread owning a robust mutex terminates while holding the +mutex, the mutex becomes inconsistent and the next thread that +acquires the mutex lock is notified of the state by the return value +.Er EOWNERDEAD . +In this case, the mutex does not become normally usable again until +the state is marked consistent. +.Pp +The +.Fn pthread_mutex_consistent , +when called with the +.Fa mutex +argument, which points to the initialized robust mutex in an +inconsistent state, marks the by mutex as consistent again. +The consequent unlock of the mutex, by either +.Fn pthread_mutex_unlock +or other methods, allows other contenders to lock the mutex. +.Pp +If the mutex in the inconsistent state is not marked consistent +by the call to +.Fn pthread_mutex_consistent +before unlock, +further attempts to lock the +.Fa mutex +result in the +.Er ENOTRECOVERABLE +condition reported by the locking functions. +.Sh RETURN VALUES +If successful, +.Fn pthread_mutex_consistent +will return zero, otherwise an error number will be returned to +indicate the error. +.Sh ERRORS +The +.Fn pthread_mutex_lock +function will fail if: +.Bl -tag -width Er +.It Bq Er EINVAL +The mutex pointed to by the +.Fa mutex +argument is not robust, or is not in the inconsistent state. +.El +.Sh SEE ALSO +.Xr pthread_mutexattr_setrobust 3 , +.Xr pthread_mutex_init 3 , +.Xr pthread_mutex_lock 3 , +.Xr pthread_mutex_unlock 3 +.Sh STANDARDS +The +.Fn pthread_mutex_lock +function conforms to +.St -susv4 . diff --git a/share/man/man3/pthread_mutex_lock.3 b/share/man/man3/pthread_mutex_lock.3 index 8479a69..bd94380 100644 --- a/share/man/man3/pthread_mutex_lock.3 +++ b/share/man/man3/pthread_mutex_lock.3 @@ -27,7 +27,7 @@ .\" .\" $FreeBSD$ .\" -.Dd January 31, 2006 +.Dd April 29, 2016 .Dt PTHREAD_MUTEX_LOCK 3 .Os .Sh NAME @@ -55,7 +55,7 @@ indicate the error. The .Fn pthread_mutex_lock function will fail if: -.Bl -tag -width Er +.Bl -tag -width "Er ENOTRECOVERABLE" .It Bq Er EINVAL The value specified by .Fa mutex @@ -63,8 +63,20 @@ is invalid. .It Bq Er EDEADLK A deadlock would occur if the thread blocked waiting for .Fa mutex . +.It Bq Er EOWNERDEAD +The argument +.Fa mutex +points to a robust mutex and the previous owning thread terminated +while holding the mutex lock. +The lock was granted to the caller and it is up to the new owner +to make the state consistent. +.It Bq Er ENOTRECOVERABLE +The state protected by the +.Fa mutex +is not recoverable. .El .Sh SEE ALSO +.Xr pthread_mutex_consistent 3 , .Xr pthread_mutex_destroy 3 , .Xr pthread_mutex_init 3 , .Xr pthread_mutex_trylock 3 , diff --git a/share/man/man3/pthread_mutex_timedlock.3 b/share/man/man3/pthread_mutex_timedlock.3 index abc7e2a..384ee9d 100644 --- a/share/man/man3/pthread_mutex_timedlock.3 +++ b/share/man/man3/pthread_mutex_timedlock.3 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd December 30, 2003 +.Dd April 29, 2016 .Dt PTHREAD_MUTEX_TIMEDLOCK 3 .Os .Sh NAME @@ -59,7 +59,7 @@ The .Fn pthread_mutex_timedlock function will fail if: .Bl -tag -width Er -.It Bq Er EINVAL +.It Bq "Er ENOTRECOVERABLE" The .Fa mutex was created with the protocol attribute having the @@ -89,8 +89,20 @@ has been exceeded. .It Bq Er EDEADLK The current thread already owns the .Fa mutex . +.It Bq Er EOWNERDEAD +The argument +.Fa mutex +points to a robust mutex and the previous owning thread terminated +while holding the mutex lock. +The lock was granted to the caller and it is up to the new owner +to make the state consistent. +.It Bq Er ENOTRECOVERABLE +The state protected by the +.Fa mutex +is not recoverable. .El .Sh SEE ALSO +.Xr pthread_mutex_consistent 3 , .Xr pthread_mutex_destroy 3 , .Xr pthread_mutex_init 3 , .Xr pthread_mutex_lock 3 , diff --git a/share/man/man3/pthread_mutex_trylock.3 b/share/man/man3/pthread_mutex_trylock.3 index 049006f..2837704 100644 --- a/share/man/man3/pthread_mutex_trylock.3 +++ b/share/man/man3/pthread_mutex_trylock.3 @@ -27,7 +27,7 @@ .\" .\" $FreeBSD$ .\" -.Dd July 30, 1998 +.Dd April 29, 2016 .Dt PTHREAD_MUTEX_TRYLOCK 3 .Os .Sh NAME @@ -56,7 +56,7 @@ indicate the error. The .Fn pthread_mutex_trylock function will fail if: -.Bl -tag -width Er +.Bl -tag -width "Er ENOTRECOVERABLE" .It Bq Er EINVAL The value specified by .Fa mutex @@ -64,8 +64,20 @@ is invalid. .It Bq Er EBUSY .Fa Mutex is already locked. +.It Bq Er EOWNERDEAD +The argument +.Fa mutex +points to a robust mutex and the previous owning thread terminated +while holding the mutex lock. +The lock was granted to the caller and it is up to the new owner +to make the state consistent. +.It Bq Er ENOTRECOVERABLE +The state protected by the +.Fa mutex +is not recoverable. .El .Sh SEE ALSO +.Xr pthread_mutex_consistent 3 , .Xr pthread_mutex_destroy 3 , .Xr pthread_mutex_init 3 , .Xr pthread_mutex_lock 3 , diff --git a/share/man/man3/pthread_mutex_unlock.3 b/share/man/man3/pthread_mutex_unlock.3 index 77784e1..4d3badd 100644 --- a/share/man/man3/pthread_mutex_unlock.3 +++ b/share/man/man3/pthread_mutex_unlock.3 @@ -27,7 +27,7 @@ .\" .\" $FreeBSD$ .\" -.Dd July 30, 1998 +.Dd April 29, 2016 .Dt PTHREAD_MUTEX_UNLOCK 3 .Os .Sh NAME @@ -46,6 +46,17 @@ then the .Fn pthread_mutex_unlock function unlocks .Fa mutex . +.Pp +If the argument pointed by the +.Fa mutex +is a robust mutex in the inconsistent state, and the call to +.Fn pthread_mutex_consistent +function was not done prior to unlocking, further locking attempts on +the mutex +.Fa mutex +are denied and locking functions return +.Er ENOTRECOVERABLE +error. .Sh RETURN VALUES If successful, .Fn pthread_mutex_unlock diff --git a/share/man/man3/pthread_mutexattr.3 b/share/man/man3/pthread_mutexattr.3 index f976026..e7042d5 100644 --- a/share/man/man3/pthread_mutexattr.3 +++ b/share/man/man3/pthread_mutexattr.3 @@ -26,7 +26,7 @@ .\" EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. .\" .\" $FreeBSD$ -.Dd May 1, 2000 +.Dd April 29, 2016 .Dt PTHREAD_MUTEXATTR 3 .Os .Sh NAME @@ -36,6 +36,8 @@ .Nm pthread_mutexattr_getprioceiling , .Nm pthread_mutexattr_setprotocol , .Nm pthread_mutexattr_getprotocol , +.Nm pthread_mutexattr_setrobust , +.Nm pthread_mutexattr_getrobust , .Nm pthread_mutexattr_settype , .Nm pthread_mutexattr_gettype .Nd mutex attribute operations @@ -56,6 +58,10 @@ .Ft int .Fn pthread_mutexattr_getprotocol "pthread_mutexattr_t *attr" "int *protocol" .Ft int +.Fn pthread_mutexattr_setrobust "pthread_mutexattr_t *attr" "int robust" +.Ft int +.Fn pthread_mutexattr_getrobust "pthread_mutexattr_t *attr" "int *robust" +.Ft int .Fn pthread_mutexattr_settype "pthread_mutexattr_t *attr" "int type" .Ft int .Fn pthread_mutexattr_gettype "pthread_mutexattr_t *attr" "int *type" @@ -165,6 +171,26 @@ function will fail if: Invalid value for .Fa attr . .El +.Pp +The +.Fn pthread_mutexattr_setrobust +function will fail if: +.Bl -tag -width Er +.It Bq Er EINVAL +Invalid value for +.Fa attr , +or invalid value for +.Fa robust . +.El +.Pp +The +.Fn pthread_mutexattr_getrobust +function will fail if: +.Bl -tag -width Er +.It Bq Er EINVAL +Invalid value for +.Fa attr . +.El .Sh SEE ALSO .Xr pthread_mutex_init 3 .Sh STANDARDS @@ -184,4 +210,10 @@ The and .Fn pthread_mutexattr_gettype functions conform to -.St -susv2 +.St -susv2 . +The +.Fn pthread_mutexattr_setrobust +and +.Fn pthread_mutexattr_getrobust +functions conform to +.St -susv4 . diff --git a/share/man/man4/ddb.4 b/share/man/man4/ddb.4 index 087b916..b6ef6ae 100644 --- a/share/man/man4/ddb.4 +++ b/share/man/man4/ddb.4 @@ -60,7 +60,7 @@ .\" .\" $FreeBSD$ .\" -.Dd January 15, 2016 +.Dd May 18, 2016 .Dt DDB 4 .Os .Sh NAME @@ -542,6 +542,11 @@ Output is similar to but also includes the address of the TTY structure. .\" .Pp +.It Ic show Cm all vnets +Show the same output as "show vnet" does, but lists all +virtualized network stacks within the system. +.\" +.Pp .It Ic show Cm allchains Show the same information like "show lockchain" does, but for every thread in the system. @@ -1060,6 +1065,13 @@ Currently, it is not possible to use this command when is compiled in the kernel. .\" .Pp +.It Ic show Cm vnet Ar addr +Prints virtualized network stack +.Vt struct vnet +structure present at the address +.Ar addr . +.\" +.Pp .It Ic show Cm vnode Op Ar addr Prints vnode .Vt struct vnode diff --git a/share/man/man4/gdb.4 b/share/man/man4/gdb.4 index dc73382..de2f4d1 100644 --- a/share/man/man4/gdb.4 +++ b/share/man/man4/gdb.4 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd February 8, 2005 +.Dd May 17, 2016 .Dt GDB 4 .Os .Sh NAME @@ -595,7 +595,7 @@ run the link at more than 9600 bps. Firewire connections do not have this problem. .Pp The debugging macros -.Dq "just grown" . +.Dq just grew. In general, the person who wrote them did so while looking for a specific problem, so they may not be general enough, and they may behave badly when used in ways for which they were not intended, even if those ways make sense. diff --git a/share/man/man5/Makefile b/share/man/man5/Makefile index 108397d..1b04034 100644 --- a/share/man/man5/Makefile +++ b/share/man/man5/Makefile @@ -57,7 +57,6 @@ MAN= acct.5 \ rc.conf.5 \ rctl.conf.5 \ regdomain.5 \ - reiserfs.5 \ remote.5 \ resolver.5 \ services.5 \ diff --git a/share/man/man5/reiserfs.5 b/share/man/man5/reiserfs.5 deleted file mode 100644 index 254afb7..0000000 --- a/share/man/man5/reiserfs.5 +++ /dev/null @@ -1,83 +0,0 @@ -.\" -.\" Copyright (c) 2005 Jean-Sébastien Pédron -.\" All rights reserved. -.\" -.\" Redistribution and use in source and binary forms, with or without -.\" modification, are permitted provided that the following conditions -.\" are met: -.\" 1. Redistributions of source code must retain the above copyright -.\" notice, this list of conditions and the following disclaimer. -.\" 2. Redistributions in binary form must reproduce the above copyright -.\" notice, this list of conditions and the following disclaimer in the -.\" documentation and/or other materials provided with the distribution. -.\" 3. The name of the author may not be used to endorse or promote products -.\" derived from this software without specific prior written permission -.\" -.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -.\" -.\" $FreeBSD$ -.\" -.Dd October 1, 2013 -.Dt REISERFS 5 -.Os -.Sh NAME -.Nm reiserfs -.Nd "Reiser file system" -.Sh SYNOPSIS -To link into the kernel: -.Bd -ragged -offset indent -.Cd "options REISERFS" -.Ed -.Pp -To load as a kernel loadable module: -.Pp -.Dl "kldload reiserfs" -.Sh DESCRIPTION -The -.Nm -driver will permit the -.Fx -kernel to access -.Tn ReiserFS -file systems. -.Sh EXAMPLES -To mount a -.Nm -volume located on -.Pa /dev/ada1s1 : -.Pp -.Dl "mount -t reiserfs /dev/ada1s1 /mnt" -.Sh SEE ALSO -.Xr nmount 2 , -.Xr unmount 2 , -.Xr fstab 5 , -.Xr mount 8 -.Sh HISTORY -The -.Nm -file system support -first appeared in -.Fx 6.0 . -.Sh AUTHORS -.An -nosplit -The ReiserFS kernel implementation was written by -.An Hans Reiser -and ported to -.Fx -by -.An Jean-S\['e]bastien P\['e]dron Aq Mt dumbbell@FreeBSD.org . -.Pp -This manual page was written by -.An Craig Rodrigues Aq Mt rodrigc@FreeBSD.org . -.Sh CAVEATS -Currently, only read-only access is supported for ReiserFS volumes, -writing to a volume is not supported. diff --git a/share/man/man8/nanobsd.8 b/share/man/man8/nanobsd.8 index aae6fff..f12434f 100644 --- a/share/man/man8/nanobsd.8 +++ b/share/man/man8/nanobsd.8 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 20, 2010 +.Dd May 19, 2016 .Dt NANOBSD 8 .Os .Sh NAME @@ -33,7 +33,7 @@ applications .Sh SYNOPSIS .Nm -.Op Fl bhknw +.Op Fl bfhiKknqvwX .Op Fl c Ar config-file .Sh DESCRIPTION The @@ -53,8 +53,16 @@ The following options are available: Skip the build stages (both for kernel and world). .It Fl c Ar config-file Specify the configuration file to use. +.It Fl f +Skip the code slice extraction. .It Fl h Display usage information. +.It Fl i +Skip the disk image build stage. +.It Fl K +Skip the +.Cm installkernel +stage of the build. .It Fl k Skip the .Cm buildkernel @@ -65,10 +73,17 @@ This suppresses the normal cleanup work done before the .Cm buildworld stage and adds -DNO_CLEAN to the make command line used for each build stage (world and kernel). +.It Fl q +Make output more quiet. +.It Fl v +Make output more verbose. .It Fl w Skip the .Cm buildworld stage of the build. +.It Fl X +Make +.Cm native-xtools. .El .Pp The features of diff --git a/share/man/man9/BUS_GET_CPUS.9 b/share/man/man9/BUS_GET_CPUS.9 index 6f0a5ac..7d7c1ad 100644 --- a/share/man/man9/BUS_GET_CPUS.9 +++ b/share/man/man9/BUS_GET_CPUS.9 @@ -62,7 +62,7 @@ argument specifies the size in bytes of the set passed in .Fa cpuset . .Pp .Fn BUS_GET_CPUS -supports querying different types of CPU sets via the the +supports querying different types of CPU sets via the .Fa op argument. Not all set types are supported for every device. If a set type is not supported, diff --git a/share/man/man9/Makefile b/share/man/man9/Makefile index 2731608..5288f03 100644 --- a/share/man/man9/Makefile +++ b/share/man/man9/Makefile @@ -787,7 +787,8 @@ MLINKS+=g_bio.9 g_alloc_bio.9 \ g_bio.9 g_destroy_bio.9 \ g_bio.9 g_duplicate_bio.9 \ g_bio.9 g_new_bio.9 \ - g_bio.9 g_print_bio.9 + g_bio.9 g_print_bio.9 \ + g_bio.9 g_reset_bio.9 MLINKS+=g_consumer.9 g_destroy_consumer.9 \ g_consumer.9 g_new_consumer.9 MLINKS+=g_data.9 g_read_data.9 \ diff --git a/share/man/man9/g_bio.9 b/share/man/man9/g_bio.9 index 34f8f94..5bfbd01 100644 --- a/share/man/man9/g_bio.9 +++ b/share/man/man9/g_bio.9 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 9, 2016 +.Dd May 17, 2016 .Dt G_BIO 9 .Os .Sh NAME @@ -213,27 +213,27 @@ The .Fn g_reset_bio function resets the given .Vt bio -for reuse. -Prior to -.Fx 11 -a -.Vt bio -was reset for reuse with -.Xr bzero 3 . +structure back to its initial state. .Fn g_reset_bio -preserves internal data structures, while resetting all -user visible values. -Its use is required for any +preserves internal data structures, while setting all +user visible fields to their initial values. +When reusing a .Vt bio -that has been returned by +obtained from .Fn g_new_bio , .Fn g_alloc_bio , .Fn g_clone_bio , or -.Fn g_duplicate_bio . -It may be used for a +.Fn g_duplicate_bio +for multiple transactions, +.Fn g_reset_bio +must be called between the transactions in lieu of +.Fn bzero . +While not strictly required for a .Vt bio -created in another way, but that is not required. +structure created by other means, +.Fn g_reset_bio +should be used to initialize it and between transactions. .Sh RETURN VALUES The .Fn g_new_bio diff --git a/share/mk/bsd.cpu.mk b/share/mk/bsd.cpu.mk index 7081c9e..ff64d7d 100644 --- a/share/mk/bsd.cpu.mk +++ b/share/mk/bsd.cpu.mk @@ -309,14 +309,18 @@ MACHINE_CPU += arm . if ${MACHINE_ARCH:Marmv6*} != "" MACHINE_CPU += armv6 . endif -# armv6 is a hybrid. It uses the softfp ABI, but doesn't emulate +# armv6 is a hybrid. It can use the softfp ABI, but doesn't emulate # floating point in the general case, so don't define softfp for # it at this time. arm and armeb are pure softfp, so define it # for them. . if ${MACHINE_ARCH:Marmv6*} == "" MACHINE_CPU += softfp . endif -.if ${MACHINE_ARCH} == "armv6" +# Normally armv6 is hard float ABI from FreeBSD 11 onwards. However +# when CPUTYPE has 'soft' in it, we use the soft-float ABI to allow +# building of soft-float ABI libraries. In this case, we have to +# add the -mfloat-abi=softfp to force that. +.if ${MACHINE_ARCH:Marmv6*} && defined(CPUTYPE) && ${CPUTYPE:M*soft*} != "" # Needs to be CFLAGS not _CPUCFLAGS because it's needed for the ABI # not a nice optimization. CFLAGS += -mfloat-abi=softfp diff --git a/share/mk/local.meta.sys.mk b/share/mk/local.meta.sys.mk index 6088c75..55febe0 100644 --- a/share/mk/local.meta.sys.mk +++ b/share/mk/local.meta.sys.mk @@ -43,7 +43,7 @@ OBJROOT:= ${OBJROOT:H:tA}/${OBJROOT:T} .endif # from src/Makefile (for universe) -TARGET_ARCHES_arm?= arm armeb armv6 armv6hf +TARGET_ARCHES_arm?= arm armeb armv6 TARGET_ARCHES_arm64?= aarch64 TARGET_ARCHES_mips?= mipsel mips mips64el mips64 mipsn32 mipsn32el TARGET_ARCHES_powerpc?= powerpc powerpc64 diff --git a/share/mk/sys.mk b/share/mk/sys.mk index 3b2d472a..7aea72f 100644 --- a/share/mk/sys.mk +++ b/share/mk/sys.mk @@ -13,7 +13,7 @@ unix ?= We run FreeBSD, not UNIX. # and/or endian. This is called MACHINE_CPU in NetBSD, but that's used # for something different in FreeBSD. # -MACHINE_CPUARCH=${MACHINE_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb|hf)?/arm/:C/powerpc64/powerpc/:C/riscv64/riscv/} +MACHINE_CPUARCH=${MACHINE_ARCH:C/mips(n32|64)?(el)?/mips/:C/arm(v6)?(eb)?/arm/:C/powerpc64/powerpc/:C/riscv64/riscv/} .endif diff --git a/sys/amd64/vmm/io/vhpet.c b/sys/amd64/vmm/io/vhpet.c index 1db1c51..f57f407 100644 --- a/sys/amd64/vmm/io/vhpet.c +++ b/sys/amd64/vmm/io/vhpet.c @@ -163,7 +163,7 @@ vhpet_counter(struct vhpet *vhpet, sbintime_t *nowptr) /* * The sbinuptime corresponding to the 'countbase' is * meaningless when the counter is disabled. Make sure - * that the the caller doesn't want to use it. + * that the caller doesn't want to use it. */ KASSERT(nowptr == NULL, ("vhpet_counter: nowptr must be NULL")); } diff --git a/sys/arm/allwinner/a10/a10_intc.c b/sys/arm/allwinner/a10/a10_intc.c index 31e6ef4..41f1f30 100644 --- a/sys/arm/allwinner/a10/a10_intc.c +++ b/sys/arm/allwinner/a10/a10_intc.c @@ -250,6 +250,7 @@ a10_intr(void *arg) static int a10_intr_pic_attach(struct a10_aintc_softc *sc) { + struct intr_pic *pic; int error; uint32_t irq; const char *name; @@ -266,9 +267,9 @@ a10_intr_pic_attach(struct a10_aintc_softc *sc) } xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)); - error = intr_pic_register(sc->sc_dev, xref); - if (error != 0) - return (error); + pic = intr_pic_register(sc->sc_dev, xref); + if (pic == NULL) + return (ENXIO); return (intr_pic_claim_root(sc->sc_dev, xref, a10_intr, sc, 0)); } diff --git a/sys/arm/allwinner/a10_ahci.c b/sys/arm/allwinner/a10_ahci.c index 009ef5f..1b87ed4 100644 --- a/sys/arm/allwinner/a10_ahci.c +++ b/sys/arm/allwinner/a10_ahci.c @@ -158,7 +158,7 @@ ahci_a10_phy_reset(device_t dev) struct ahci_controller *ctlr = device_get_softc(dev); /* - * Here start the the magic -- most of the comments are based + * Here starts the magic -- most of the comments are based * on guesswork, names of routines and printf error * messages. The code works, but it will do that even if the * comments are 100% BS. diff --git a/sys/arm/allwinner/aw_nmi.c b/sys/arm/allwinner/aw_nmi.c index 2b23a4b..a8b4598 100644 --- a/sys/arm/allwinner/aw_nmi.c +++ b/sys/arm/allwinner/aw_nmi.c @@ -362,7 +362,7 @@ aw_nmi_attach(device_t dev) device_get_nameunit(sc->dev), sc->intr.irq) != 0) goto error; - if (intr_pic_register(dev, (intptr_t)xref) != 0) { + if (intr_pic_register(dev, (intptr_t)xref) == NULL) { device_printf(dev, "could not register pic\n"); goto error; } diff --git a/sys/arm/allwinner/files.allwinner b/sys/arm/allwinner/files.allwinner index b2f2723..4d8e071 100644 --- a/sys/arm/allwinner/files.allwinner +++ b/sys/arm/allwinner/files.allwinner @@ -24,6 +24,8 @@ arm/allwinner/if_awg.c optional awg arm/allwinner/if_emac.c optional emac arm/allwinner/sunxi_dma_if.m standard dev/iicbus/twsi/a10_twsi.c optional twsi +dev/usb/controller/generic_ohci.c optional ohci +dev/usb/controller/generic_usb_if.m optional ohci arm/allwinner/aw_sid.c standard arm/allwinner/aw_thermal.c standard #arm/allwinner/console.c standard diff --git a/sys/arm/amlogic/aml8726/aml8726_ccm.c b/sys/arm/amlogic/aml8726/aml8726_ccm.c index 186a3ca..fb2c9a5 100644 --- a/sys/arm/amlogic/aml8726/aml8726_ccm.c +++ b/sys/arm/amlogic/aml8726/aml8726_ccm.c @@ -141,7 +141,7 @@ aml8726_ccm_configure_gates(struct aml8726_ccm_softc *sc) AML_CCM_UNLOCK(sc); } - free(functions, M_OFWPROP); + OF_prop_free(functions); return (0); } diff --git a/sys/arm/amlogic/aml8726/aml8726_mmc.c b/sys/arm/amlogic/aml8726/aml8726_mmc.c index 5205507..3cc0744 100644 --- a/sys/arm/amlogic/aml8726/aml8726_mmc.c +++ b/sys/arm/amlogic/aml8726/aml8726_mmc.c @@ -605,11 +605,11 @@ aml8726_mmc_attach(device_t dev) else { device_printf(dev, "unknown function attribute %.*s in FDT\n", len, function_name); - free(function_name, M_OFWPROP); + OF_prop_free(function_name); return (ENXIO); } - free(function_name, M_OFWPROP); + OF_prop_free(function_name); sc->pwr_en.dev = NULL; @@ -661,7 +661,7 @@ aml8726_mmc_attach(device_t dev) device_printf(dev, "unknown voltage attribute %.*s in FDT\n", len, voltage); - free(voltages, M_OFWPROP); + OF_prop_free(voltages); return (ENXIO); } @@ -678,7 +678,7 @@ aml8726_mmc_attach(device_t dev) } } - free(voltages, M_OFWPROP); + OF_prop_free(voltages); sc->vselect.dev = NULL; diff --git a/sys/arm/amlogic/aml8726/aml8726_pinctrl.c b/sys/arm/amlogic/aml8726/aml8726_pinctrl.c index 63af2f1..a71c25a 100644 --- a/sys/arm/amlogic/aml8726/aml8726_pinctrl.c +++ b/sys/arm/amlogic/aml8726/aml8726_pinctrl.c @@ -210,11 +210,11 @@ aml8726_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) if (f->name == NULL) { device_printf(dev, "unknown function attribute %.*s in FDT\n", len, function_name); - free(function_name, M_OFWPROP); + OF_prop_free(function_name); return (ENXIO); } - free(function_name, M_OFWPROP); + OF_prop_free(function_name); len = OF_getprop_alloc(node, "amlogic,pull", sizeof(char), (void **)&pull); @@ -234,12 +234,12 @@ aml8726_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) device_printf(dev, "unknown pull attribute %.*s in FDT\n", len, pull); - free(pull, M_OFWPROP); + OF_prop_free(pull); return (ENXIO); } } - free(pull, M_OFWPROP); + OF_prop_free(pull); /* * Setting the pull direction isn't supported on all SoC. @@ -403,7 +403,7 @@ aml8726_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) AML_PINCTRL_UNLOCK(sc); } - free(pins, M_OFWPROP); + OF_prop_free(pins); return (0); } diff --git a/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c b/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c index a5be5e4..fc22535 100644 --- a/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c +++ b/sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c @@ -821,7 +821,7 @@ aml8726_sdxc_attach(device_t dev) device_printf(dev, "unknown voltage attribute %.*s in FDT\n", len, voltage); - free(voltages, M_OFWPROP); + OF_prop_free(voltages); return (ENXIO); } @@ -838,7 +838,7 @@ aml8726_sdxc_attach(device_t dev) } } - free(voltages, M_OFWPROP); + OF_prop_free(voltages); sc->vselect.dev = NULL; diff --git a/sys/arm/amlogic/aml8726/aml8726_usb_phy-m3.c b/sys/arm/amlogic/aml8726/aml8726_usb_phy-m3.c index c428943..c24cd23 100644 --- a/sys/arm/amlogic/aml8726/aml8726_usb_phy-m3.c +++ b/sys/arm/amlogic/aml8726/aml8726_usb_phy-m3.c @@ -139,7 +139,7 @@ aml8726_usb_phy_mode(const char *dwcotg_path, uint32_t *mode) AML_USB_PHY_MISC_ID_OVERIDE_DEVICE; } - free(usb_mode, M_OFWPROP); + OF_prop_free(usb_mode); return (0); } @@ -214,7 +214,7 @@ aml8726_usb_phy_attach(device_t dev) } } - free(prop, M_OFWPROP); + OF_prop_free(prop); if (err) { device_printf(dev, "unable to parse gpio\n"); diff --git a/sys/arm/amlogic/aml8726/aml8726_usb_phy-m6.c b/sys/arm/amlogic/aml8726/aml8726_usb_phy-m6.c index 7de23c4..3a108e4 100644 --- a/sys/arm/amlogic/aml8726/aml8726_usb_phy-m6.c +++ b/sys/arm/amlogic/aml8726/aml8726_usb_phy-m6.c @@ -164,7 +164,7 @@ aml8726_usb_phy_attach(device_t dev) sc->force_aca = TRUE; } - free(force_aca, M_OFWPROP); + OF_prop_free(force_aca); err = 0; @@ -187,7 +187,7 @@ aml8726_usb_phy_attach(device_t dev) } } - free(prop, M_OFWPROP); + OF_prop_free(prop); len = OF_getencprop_alloc(node, "usb-hub-rst", 3 * sizeof(pcell_t), (void **)&prop); @@ -200,7 +200,7 @@ aml8726_usb_phy_attach(device_t dev) err = 1; } - free(prop, M_OFWPROP); + OF_prop_free(prop); if (err) { device_printf(dev, "unable to parse gpio\n"); diff --git a/sys/arm/arm/gic.c b/sys/arm/arm/gic.c index c55337e..cd5e6d7 100644 --- a/sys/arm/arm/gic.c +++ b/sys/arm/arm/gic.c @@ -108,6 +108,11 @@ __FBSDID("$FreeBSD$"); #define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ #define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ +/* TYPER Registers */ +#define GICD_TYPER_SECURITYEXT 0x400 +#define GIC_SUPPORT_SECEXT(_sc) \ + ((_sc->typer & GICD_TYPER_SECURITYEXT) == GICD_TYPER_SECURITYEXT) + /* First bit is a polarity bit (0 - low, 1 - high) */ #define GICD_ICFGR_POL_LOW (0 << 0) #define GICD_ICFGR_POL_HIGH (1 << 0) @@ -172,6 +177,7 @@ struct arm_gic_softc { uint8_t ver; struct mtx mutex; uint32_t nirqs; + uint32_t typer; #ifdef GIC_DEBUG_SPURIOUS uint32_t last_irq[MAXCPU]; #endif @@ -299,7 +305,7 @@ arm_gic_init_secondary(device_t dev) gic_d_write_4(sc, GICD_IPRIORITYR(irq >> 2), 0); /* Set all the interrupts to be in Group 0 (secure) */ - for (irq = 0; irq < sc->nirqs; irq += 32) { + for (irq = 0; GIC_SUPPORT_SECEXT(sc) && irq < sc->nirqs; irq += 32) { gic_d_write_4(sc, GICD_IGROUPR(irq >> 5), 0); } @@ -336,7 +342,7 @@ arm_gic_init_secondary(device_t dev) gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); /* Set all the interrupts to be in Group 0 (secure) */ - for (i = 0; i < sc->nirqs; i += 32) { + for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) { gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); } @@ -639,8 +645,8 @@ arm_gic_attach(device_t dev) gic_d_write_4(sc, GICD_CTLR, 0x00); /* Get the number of interrupts */ - nirqs = gic_d_read_4(sc, GICD_TYPER); - nirqs = 32 * ((nirqs & 0x1f) + 1); + sc->typer = gic_d_read_4(sc, GICD_TYPER); + nirqs = 32 * ((sc->typer & 0x1f) + 1); #ifdef INTRNG if (arm_gic_register_isrcs(sc, nirqs)) { @@ -686,7 +692,7 @@ arm_gic_attach(device_t dev) } /* Set all the interrupts to be in Group 0 (secure) */ - for (i = 0; i < sc->nirqs; i += 32) { + for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) { gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); } @@ -705,7 +711,7 @@ arm_gic_attach(device_t dev) * Now, when everything is initialized, it's right time to * register interrupt controller to interrupt framefork. */ - if (intr_pic_register(dev, xref) != 0) { + if (intr_pic_register(dev, xref) == NULL) { device_printf(dev, "could not register PIC\n"); goto cleanup; } diff --git a/sys/arm/broadcom/bcm2835/bcm2835_gpio.c b/sys/arm/broadcom/bcm2835/bcm2835_gpio.c index cab3116..0b59d52 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_gpio.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_gpio.c @@ -1045,8 +1045,11 @@ bcm_gpio_pic_attach(struct bcm_gpio_softc *sc) if (error != 0) return (error); /* XXX deregister ISRCs */ } - return (intr_pic_register(sc->sc_dev, - OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)))); + if (intr_pic_register(sc->sc_dev, + OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) + return (ENXIO); + + return (0); } static int diff --git a/sys/arm/broadcom/bcm2835/bcm2835_intr.c b/sys/arm/broadcom/bcm2835/bcm2835_intr.c index 39ad5f7..b6a7454 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_intr.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_intr.c @@ -341,7 +341,10 @@ bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref) if (error != 0) return (error); } - return (intr_pic_register(sc->sc_dev, xref)); + if (intr_pic_register(sc->sc_dev, xref) == NULL) + return (ENXIO); + + return (0); } #endif diff --git a/sys/arm/broadcom/bcm2835/bcm2836.c b/sys/arm/broadcom/bcm2835/bcm2836.c index 3991609..d90e584 100644 --- a/sys/arm/broadcom/bcm2835/bcm2836.c +++ b/sys/arm/broadcom/bcm2835/bcm2836.c @@ -598,6 +598,7 @@ static int bcm_lintc_pic_attach(struct bcm_lintc_softc *sc) { struct bcm_lintc_irqsrc *bisrcs; + struct intr_pic *pic; int error; u_int flags; uint32_t irq; @@ -653,9 +654,9 @@ bcm_lintc_pic_attach(struct bcm_lintc_softc *sc) } xref = OF_xref_from_node(ofw_bus_get_node(sc->bls_dev)); - error = intr_pic_register(sc->bls_dev, xref); - if (error != 0) - return (error); + pic = intr_pic_register(sc->bls_dev, xref); + if (pic == NULL) + return (ENXIO); return (intr_pic_claim_root(sc->bls_dev, xref, bcm_lintc_intr, sc, 0)); } diff --git a/sys/arm/conf/A10 b/sys/arm/conf/A10 index a648f37..6adad1d 100644 --- a/sys/arm/conf/A10 +++ b/sys/arm/conf/A10 @@ -98,7 +98,7 @@ options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device uhci -#device ohci +device ohci device ehci device umass diff --git a/sys/arm/conf/ALLWINNER b/sys/arm/conf/ALLWINNER index 9b88459..e68ebd9 100644 --- a/sys/arm/conf/ALLWINNER +++ b/sys/arm/conf/ALLWINNER @@ -113,7 +113,7 @@ options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device uhci -#device ohci +device ohci device ehci device umass diff --git a/sys/arm/conf/TEGRA124 b/sys/arm/conf/TEGRA124 index 1b3ec3f..3d55c4b 100644 --- a/sys/arm/conf/TEGRA124 +++ b/sys/arm/conf/TEGRA124 @@ -154,4 +154,3 @@ device fdt_pinctrl # SoC-specific devices #device hwpmc -#options HWPMC_HOOKS diff --git a/sys/arm/conf/std.armv6 b/sys/arm/conf/std.armv6 index 4dc4906..e414bbf 100644 --- a/sys/arm/conf/std.armv6 +++ b/sys/arm/conf/std.armv6 @@ -36,6 +36,7 @@ options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev +options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) options FREEBSD_BOOT_LOADER # Process metadata passed from loader(8) options VFP # Enable floating point hardware support diff --git a/sys/arm/freescale/imx/imx_sdhci.c b/sys/arm/freescale/imx/imx_sdhci.c index 2dc41db..e928ba4 100644 --- a/sys/arm/freescale/imx/imx_sdhci.c +++ b/sys/arm/freescale/imx/imx_sdhci.c @@ -625,7 +625,7 @@ imx_sdhci_intr(void *arg) * out of the hardware now so that we can present it later when the DAT0 * line is released. * - * If we need to wait for the the DAT0 line to be released, we set up a + * If we need to wait for the DAT0 line to be released, we set up a * timeout point 250ms in the future. This number comes from the SD * spec, which allows a command to take that long. In the real world, * cards tend to take 10-20ms for a long-running command such as a write diff --git a/sys/arm/include/asm.h b/sys/arm/include/asm.h index c63b7d1..44b9d2b 100644 --- a/sys/arm/include/asm.h +++ b/sys/arm/include/asm.h @@ -79,7 +79,7 @@ /* * EENTRY()/EEND() mark "extra" entry/exit points from a function. - * LEENTRY()/LEEND() are the the same for local symbols. + * LEENTRY()/LEEND() are the same for local symbols. * The unwind info cannot handle the concept of a nested function, or a function * with multiple .fnstart directives, but some of our assembler code is written * with multiple labels to allow entry at several points. The EENTRY() macro diff --git a/sys/arm/include/atomic-v4.h b/sys/arm/include/atomic-v4.h index 0c0b377..b4ff5bf 100644 --- a/sys/arm/include/atomic-v4.h +++ b/sys/arm/include/atomic-v4.h @@ -372,6 +372,8 @@ atomic_swap_32(volatile u_int32_t *p, u_int32_t v) #define atomic_cmpset_rel_32 atomic_cmpset_32 #define atomic_cmpset_acq_32 atomic_cmpset_32 +#define atomic_cmpset_rel_64 atomic_cmpset_64 +#define atomic_cmpset_acq_64 atomic_cmpset_64 #define atomic_set_rel_32 atomic_set_32 #define atomic_set_acq_32 atomic_set_32 #define atomic_clear_rel_32 atomic_clear_32 diff --git a/sys/arm/mv/mpic.c b/sys/arm/mv/mpic.c index 7e07d66..1dbcb34 100644 --- a/sys/arm/mv/mpic.c +++ b/sys/arm/mv/mpic.c @@ -274,7 +274,7 @@ mv_mpic_attach(device_t dev) bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); return (ENXIO); } - if (intr_pic_register(dev, OF_xref_from_device(dev)) != 0) { + if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) { device_printf(dev, "could not register PIC\n"); bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); return (ENXIO); diff --git a/sys/arm/nvidia/tegra_gpio.c b/sys/arm/nvidia/tegra_gpio.c index bfe093c..0f88e64 100644 --- a/sys/arm/nvidia/tegra_gpio.c +++ b/sys/arm/nvidia/tegra_gpio.c @@ -452,8 +452,11 @@ tegra_gpio_pic_attach(struct tegra_gpio_softc *sc) if (error != 0) return (error); /* XXX deregister ISRCs */ } - return (intr_pic_register(sc->dev, - OF_xref_from_node(ofw_bus_get_node(sc->dev)))); + if (intr_pic_register(sc->dev, + OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL) + return (ENXIO); + + return (0); } static int diff --git a/sys/arm/nvidia/tegra_lic.c b/sys/arm/nvidia/tegra_lic.c index 6228c01..5a27a65 100644 --- a/sys/arm/nvidia/tegra_lic.c +++ b/sys/arm/nvidia/tegra_lic.c @@ -233,7 +233,7 @@ tegra_lic_attach(device_t dev) } - if (intr_pic_register(dev, OF_xref_from_node(node)) != 0) { + if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { device_printf(dev, "Cannot register PIC\n"); goto fail; } diff --git a/sys/arm/ti/aintc.c b/sys/arm/ti/aintc.c index 5fb4695..ae5bad6 100644 --- a/sys/arm/ti/aintc.c +++ b/sys/arm/ti/aintc.c @@ -220,6 +220,7 @@ ti_aintc_post_filter(device_t dev, struct intr_irqsrc *isrc) static int ti_aintc_pic_attach(struct ti_aintc_softc *sc) { + struct intr_pic *pic; int error; uint32_t irq; const char *name; @@ -236,9 +237,9 @@ ti_aintc_pic_attach(struct ti_aintc_softc *sc) } xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)); - error = intr_pic_register(sc->sc_dev, xref); - if (error != 0) - return (error); + pic = intr_pic_register(sc->sc_dev, xref); + if (pic == NULL) + return (ENXIO); return (intr_pic_claim_root(sc->sc_dev, xref, ti_aintc_intr, sc, 0)); } diff --git a/sys/arm/ti/omap4/omap4_wugen.c b/sys/arm/ti/omap4/omap4_wugen.c index f2bed61..8909126 100644 --- a/sys/arm/ti/omap4/omap4_wugen.c +++ b/sys/arm/ti/omap4/omap4_wugen.c @@ -210,7 +210,7 @@ omap4_wugen_attach(device_t dev) return (ENXIO); } - if (intr_pic_register(dev, OF_xref_from_node(node)) != 0) { + if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { device_printf(dev, "can't register PIC\n"); goto fail; } diff --git a/sys/arm/ti/ti_gpio.c b/sys/arm/ti/ti_gpio.c index a67884e..583a65a 100644 --- a/sys/arm/ti/ti_gpio.c +++ b/sys/arm/ti/ti_gpio.c @@ -904,8 +904,11 @@ ti_gpio_pic_attach(struct ti_gpio_softc *sc) if (error != 0) return (error); /* XXX deregister ISRCs */ } - return (intr_pic_register(sc->sc_dev, - OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)))); + if (intr_pic_register(sc->sc_dev, + OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) + return (ENXIO); + + return (0); } static int diff --git a/sys/arm64/arm64/autoconf.c b/sys/arm64/arm64/autoconf.c index c29b335..3f233d7 100644 --- a/sys/arm64/arm64/autoconf.c +++ b/sys/arm64/arm64/autoconf.c @@ -80,7 +80,13 @@ configure(void *dummy) static void configure_final(void *dummy) { + +#ifdef INTRNG + /* Enable interrupt reception on this CPU */ + intr_enable(); +#else arm_enable_intr(); +#endif cninit_finish(); if (bootverbose) diff --git a/sys/arm64/arm64/gic.c b/sys/arm64/arm64/gic.c index 2140086..68b7cab 100644 --- a/sys/arm64/arm64/gic.c +++ b/sys/arm64/arm64/gic.c @@ -94,6 +94,11 @@ __FBSDID("$FreeBSD$"); #define GIC_LAST_PPI 31 /* core) peripheral interrupts. */ #define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */ +/* TYPER Registers */ +#define GICD_TYPER_SECURITYEXT 0x400 +#define GIC_SUPPORT_SECEXT(_sc) \ + ((_sc->typer & GICD_TYPER_SECURITYEXT) == GICD_TYPER_SECURITYEXT) + /* First bit is a polarity bit (0 - low, 1 - high) */ #define GICD_ICFGR_POL_LOW (0 << 0) #define GICD_ICFGR_POL_HIGH (1 << 0) @@ -164,7 +169,7 @@ gic_init_secondary(device_t dev) gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0); /* Set all the interrupts to be in Group 0 (secure) */ - for (i = 0; i < sc->nirqs; i += 32) { + for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) { gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); } @@ -221,8 +226,8 @@ arm_gic_attach(device_t dev) gic_d_write_4(sc, GICD_CTLR, 0x00); /* Get the number of interrupts */ - sc->nirqs = gic_d_read_4(sc, GICD_TYPER); - sc->nirqs = 32 * ((sc->nirqs & 0x1f) + 1); + sc->typer = gic_d_read_4(sc, GICD_TYPER); + sc->nirqs = 32 * ((sc->typer & 0x1f) + 1); arm_register_root_pic(dev, sc->nirqs); @@ -257,7 +262,7 @@ arm_gic_attach(device_t dev) } /* Set all the interrupts to be in Group 0 (secure) */ - for (i = 0; i < sc->nirqs; i += 32) { + for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) { gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0); } diff --git a/sys/arm64/arm64/gic.h b/sys/arm64/arm64/gic.h index d22d43b..a8ba6a8 100644 --- a/sys/arm64/arm64/gic.h +++ b/sys/arm64/arm64/gic.h @@ -49,6 +49,7 @@ struct arm_gic_softc { uint8_t ver; struct mtx mutex; uint32_t nirqs; + uint32_t typer; }; DECLARE_CLASS(arm_gicv2m_driver); diff --git a/sys/arm64/arm64/gic_v3.c b/sys/arm64/arm64/gic_v3.c index 15a51a3..79df02c 100644 --- a/sys/arm64/arm64/gic_v3.c +++ b/sys/arm64/arm64/gic_v3.c @@ -1,7 +1,10 @@ /*- - * Copyright (c) 2015 The FreeBSD Foundation + * Copyright (c) 2015-2016 The FreeBSD Foundation * All rights reserved. * + * This software was developed by Andrew Turner under + * the sponsorship of the FreeBSD Foundation. + * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * @@ -27,6 +30,8 @@ * SUCH DAMAGE. */ +#include "opt_platform.h" + #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); @@ -58,6 +63,28 @@ __FBSDID("$FreeBSD$"); #include "gic_v3_reg.h" #include "gic_v3_var.h" +#ifdef INTRNG +static pic_disable_intr_t gic_v3_disable_intr; +static pic_enable_intr_t gic_v3_enable_intr; +static pic_map_intr_t gic_v3_map_intr; +static pic_setup_intr_t gic_v3_setup_intr; +static pic_teardown_intr_t gic_v3_teardown_intr; +static pic_post_filter_t gic_v3_post_filter; +static pic_post_ithread_t gic_v3_post_ithread; +static pic_pre_ithread_t gic_v3_pre_ithread; +static pic_bind_intr_t gic_v3_bind_intr; +#ifdef SMP +static pic_init_secondary_t gic_v3_init_secondary; +static pic_ipi_send_t gic_v3_ipi_send; +static pic_ipi_setup_t gic_v3_ipi_setup; +#endif + +static u_int gic_irq_cpu; +#ifdef SMP +static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1]; +static u_int sgi_first_unused = GIC_FIRST_SGI; +#endif +#else /* Device and PIC methods */ static int gic_v3_bind(device_t, u_int, u_int); static void gic_v3_dispatch(device_t, struct trapframe *); @@ -68,11 +95,29 @@ static void gic_v3_unmask_irq(device_t, u_int); static void gic_v3_init_secondary(device_t); static void gic_v3_ipi_send(device_t, cpuset_t, u_int); #endif +#endif static device_method_t gic_v3_methods[] = { /* Device interface */ DEVMETHOD(device_detach, gic_v3_detach), +#ifdef INTRNG + /* Interrupt controller interface */ + DEVMETHOD(pic_disable_intr, gic_v3_disable_intr), + DEVMETHOD(pic_enable_intr, gic_v3_enable_intr), + DEVMETHOD(pic_map_intr, gic_v3_map_intr), + DEVMETHOD(pic_setup_intr, gic_v3_setup_intr), + DEVMETHOD(pic_teardown_intr, gic_v3_teardown_intr), + DEVMETHOD(pic_post_filter, gic_v3_post_filter), + DEVMETHOD(pic_post_ithread, gic_v3_post_ithread), + DEVMETHOD(pic_pre_ithread, gic_v3_pre_ithread), +#ifdef SMP + DEVMETHOD(pic_bind_intr, gic_v3_bind_intr), + DEVMETHOD(pic_init_secondary, gic_v3_init_secondary), + DEVMETHOD(pic_ipi_send, gic_v3_ipi_send), + DEVMETHOD(pic_ipi_setup, gic_v3_ipi_setup), +#endif +#else /* PIC interface */ DEVMETHOD(pic_bind, gic_v3_bind), DEVMETHOD(pic_dispatch, gic_v3_dispatch), @@ -83,6 +128,8 @@ static device_method_t gic_v3_methods[] = { DEVMETHOD(pic_init_secondary, gic_v3_init_secondary), DEVMETHOD(pic_ipi_send, gic_v3_ipi_send), #endif +#endif + /* End */ DEVMETHOD_END }; @@ -144,6 +191,10 @@ gic_v3_attach(device_t dev) int rid; int err; size_t i; +#ifdef INTRNG + u_int irq; + const char *name; +#endif sc = device_get_softc(dev); sc->gic_registered = FALSE; @@ -192,6 +243,36 @@ gic_v3_attach(device_t dev) if (sc->gic_nirqs > GIC_I_NUM_MAX) sc->gic_nirqs = GIC_I_NUM_MAX; +#ifdef INTRNG + sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs, + M_GIC_V3, M_WAITOK | M_ZERO); + name = device_get_nameunit(dev); + for (irq = 0; irq < sc->gic_nirqs; irq++) { + struct intr_irqsrc *isrc; + + sc->gic_irqs[irq].gi_irq = irq; + sc->gic_irqs[irq].gi_pol = INTR_POLARITY_CONFORM; + sc->gic_irqs[irq].gi_trig = INTR_TRIGGER_CONFORM; + + isrc = &sc->gic_irqs[irq].gi_isrc; + if (irq <= GIC_LAST_SGI) { + err = intr_isrc_register(isrc, sc->dev, + INTR_ISRCF_IPI, "%s,i%u", name, irq - GIC_FIRST_SGI); + } else if (irq <= GIC_LAST_PPI) { + err = intr_isrc_register(isrc, sc->dev, + INTR_ISRCF_PPI, "%s,p%u", name, irq - GIC_FIRST_PPI); + } else { + err = intr_isrc_register(isrc, sc->dev, 0, + "%s,s%u", name, irq - GIC_FIRST_SPI); + } + if (err != 0) { + /* XXX call intr_isrc_deregister() */ + free(sc->gic_irqs, M_DEVBUF); + return (err); + } + } +#endif + /* Get the number of supported interrupt identifier bits */ sc->gic_idbits = GICD_TYPER_IDBITS(typer); @@ -210,8 +291,10 @@ gic_v3_attach(device_t dev) * Full success. * Now register PIC to the interrupts handling layer. */ +#ifndef INTRNG arm_register_root_pic(dev, sc->gic_nirqs); sc->gic_registered = TRUE; +#endif return (0); } @@ -244,6 +327,514 @@ gic_v3_detach(device_t dev) return (0); } +#ifdef INTRNG +int +arm_gic_v3_intr(void *arg) +{ + struct gic_v3_softc *sc = arg; + struct gic_v3_irqsrc *gi; + uint64_t active_irq; + struct trapframe *tf; + bool first; + + first = true; + + while (1) { + if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) { + /* + * Hardware: Cavium ThunderX + * Chip revision: Pass 1.0 (early version) + * Pass 1.1 (production) + * ERRATUM: 22978, 23154 + */ + __asm __volatile( + "nop;nop;nop;nop;nop;nop;nop;nop; \n" + "mrs %0, ICC_IAR1_EL1 \n" + "nop;nop;nop;nop; \n" + "dsb sy \n" + : "=&r" (active_irq)); + } else { + active_irq = gic_icc_read(IAR1); + } + + if (__predict_false(active_irq >= sc->gic_nirqs)) + return (FILTER_HANDLED); + + tf = curthread->td_intr_frame; + gi = &sc->gic_irqs[active_irq]; + if (active_irq <= GIC_LAST_SGI) { + /* Call EOI for all IPI before dispatch. */ + gic_icc_write(EOIR1, (uint64_t)active_irq); +#ifdef SMP + intr_ipi_dispatch(sgi_to_ipi[gi->gi_irq], tf); +#else + device_printf(sc->dev, "SGI %u on UP system detected\n", + active_irq - GIC_FIRST_SGI); +#endif + } else if (active_irq >= GIC_FIRST_PPI && + active_irq <= GIC_LAST_SPI) { + if (gi->gi_pol == INTR_TRIGGER_EDGE) + gic_icc_write(EOIR1, gi->gi_irq); + + if (intr_isrc_dispatch(&gi->gi_isrc, tf) != 0) { + if (gi->gi_pol != INTR_TRIGGER_EDGE) + gic_icc_write(EOIR1, gi->gi_irq); + gic_v3_disable_intr(sc->dev, &gi->gi_isrc); + device_printf(sc->dev, + "Stray irq %lu disabled\n", active_irq); + } + } + } +} + +#ifdef FDT +static int +gic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp, + enum intr_polarity *polp, enum intr_trigger *trigp) +{ + u_int irq; + + if (ncells < 3) + return (EINVAL); + + /* + * The 1st cell is the interrupt type: + * 0 = SPI + * 1 = PPI + * The 2nd cell contains the interrupt number: + * [0 - 987] for SPI + * [0 - 15] for PPI + * The 3rd cell is the flags, encoded as follows: + * bits[3:0] trigger type and level flags + * 1 = edge triggered + * 2 = edge triggered (PPI only) + * 4 = level-sensitive + * 8 = level-sensitive (PPI only) + */ + switch (cells[0]) { + case 0: + irq = GIC_FIRST_SPI + cells[1]; + /* SPI irq is checked later. */ + break; + case 1: + irq = GIC_FIRST_PPI + cells[1]; + if (irq > GIC_LAST_PPI) { + device_printf(dev, "unsupported PPI interrupt " + "number %u\n", cells[1]); + return (EINVAL); + } + break; + default: + device_printf(dev, "unsupported interrupt type " + "configuration %u\n", cells[0]); + return (EINVAL); + } + + switch (cells[2] & 0xf) { + case 1: + *trigp = INTR_TRIGGER_EDGE; + *polp = INTR_POLARITY_HIGH; + break; + case 2: + *trigp = INTR_TRIGGER_EDGE; + *polp = INTR_POLARITY_LOW; + break; + case 4: + *trigp = INTR_TRIGGER_LEVEL; + *polp = INTR_POLARITY_HIGH; + break; + case 8: + *trigp = INTR_TRIGGER_LEVEL; + *polp = INTR_POLARITY_LOW; + break; + default: + device_printf(dev, "unsupported trigger/polarity " + "configuration 0x%02x\n", cells[2]); + return (EINVAL); + } + + /* Check the interrupt is valid */ + if (irq >= GIC_FIRST_SPI && *polp != INTR_POLARITY_HIGH) + return (EINVAL); + + *irqp = irq; + return (0); +} +#endif + +static int +do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp, + enum intr_polarity *polp, enum intr_trigger *trigp) +{ + struct gic_v3_softc *sc; + enum intr_polarity pol; + enum intr_trigger trig; +#ifdef FDT + struct intr_map_data_fdt *daf; +#endif + u_int irq; + + sc = device_get_softc(dev); + + switch (data->type) { +#ifdef FDT + case INTR_MAP_DATA_FDT: + daf = (struct intr_map_data_fdt *)data; + if (gic_map_fdt(dev, daf->ncells, daf->cells, &irq, &pol, + &trig) != 0) + return (EINVAL); + break; +#endif + default: + return (EINVAL); + } + + if (irq >= sc->gic_nirqs) + return (EINVAL); + switch (pol) { + case INTR_POLARITY_CONFORM: + case INTR_POLARITY_LOW: + case INTR_POLARITY_HIGH: + break; + default: + return (EINVAL); + } + switch (trig) { + case INTR_TRIGGER_CONFORM: + case INTR_TRIGGER_EDGE: + case INTR_TRIGGER_LEVEL: + break; + default: + return (EINVAL); + } + + *irqp = irq; + if (polp != NULL) + *polp = pol; + if (trigp != NULL) + *trigp = trig; + return (0); +} + +static int +gic_v3_map_intr(device_t dev, struct intr_map_data *data, + struct intr_irqsrc **isrcp) +{ + struct gic_v3_softc *sc; + int error; + u_int irq; + + error = do_gic_v3_map_intr(dev, data, &irq, NULL, NULL); + if (error == 0) { + sc = device_get_softc(dev); + *isrcp = GIC_INTR_ISRC(sc, irq); + } + return (error); +} + +static int +gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc, + struct resource *res, struct intr_map_data *data) +{ + struct gic_v3_softc *sc = device_get_softc(dev); + struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; + enum intr_trigger trig; + enum intr_polarity pol; + uint32_t reg; + u_int irq; + int error; + + if (data == NULL) + return (ENOTSUP); + + error = do_gic_v3_map_intr(dev, data, &irq, &pol, &trig); + if (error != 0) + return (error); + + if (gi->gi_irq != irq || pol == INTR_POLARITY_CONFORM || + trig == INTR_TRIGGER_CONFORM) + return (EINVAL); + + /* Compare config if this is not first setup. */ + if (isrc->isrc_handlers != 0) { + if (pol != gi->gi_pol || trig != gi->gi_trig) + return (EINVAL); + else + return (0); + } + + gi->gi_pol = pol; + gi->gi_trig = trig; + + /* + * XXX - In case that per CPU interrupt is going to be enabled in time + * when SMP is already started, we need some IPI call which + * enables it on others CPUs. Further, it's more complicated as + * pic_enable_source() and pic_disable_source() should act on + * per CPU basis only. Thus, it should be solved here somehow. + */ + if (isrc->isrc_flags & INTR_ISRCF_PPI) + CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu); + + if (irq >= GIC_FIRST_PPI && irq <= GIC_LAST_SPI) { + mtx_lock_spin(&sc->gic_mtx); + + /* Set the trigger and polarity */ + if (irq <= GIC_LAST_PPI) + reg = gic_r_read(sc, 4, + GICR_SGI_BASE_SIZE + GICD_ICFGR(irq)); + else + reg = gic_d_read(sc, 4, GICD_ICFGR(irq)); + if (trig == INTR_TRIGGER_LEVEL) + reg &= ~(2 << ((irq % 16) * 2)); + else + reg |= 2 << ((irq % 16) * 2); + + if (irq <= GIC_LAST_PPI) { + gic_r_write(sc, 4, + GICR_SGI_BASE_SIZE + GICD_ICFGR(irq), reg); + gic_v3_wait_for_rwp(sc, REDIST); + } else { + gic_d_write(sc, 4, GICD_ICFGR(irq), reg); + gic_v3_wait_for_rwp(sc, DIST); + } + + mtx_unlock_spin(&sc->gic_mtx); + + gic_v3_bind_intr(dev, isrc); + } + + return (0); +} + +static int +gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc, + struct resource *res, struct intr_map_data *data) +{ + struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; + + if (isrc->isrc_handlers == 0) { + gi->gi_pol = INTR_POLARITY_CONFORM; + gi->gi_trig = INTR_TRIGGER_CONFORM; + } + + return (0); +} + +static void +gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc) +{ + struct gic_v3_softc *sc; + struct gic_v3_irqsrc *gi; + u_int irq; + + sc = device_get_softc(dev); + gi = (struct gic_v3_irqsrc *)isrc; + irq = gi->gi_irq; + + if (irq <= GIC_LAST_PPI) { + /* SGIs and PPIs in corresponding Re-Distributor */ + gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq), + GICD_I_MASK(irq)); + gic_v3_wait_for_rwp(sc, REDIST); + } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) { + /* SPIs in distributor */ + gic_d_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq)); + gic_v3_wait_for_rwp(sc, DIST); + } else + panic("%s: Unsupported IRQ %u", __func__, irq); +} + +static void +gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc) +{ + struct gic_v3_softc *sc; + struct gic_v3_irqsrc *gi; + u_int irq; + + sc = device_get_softc(dev); + gi = (struct gic_v3_irqsrc *)isrc; + irq = gi->gi_irq; + + if (irq <= GIC_LAST_PPI) { + /* SGIs and PPIs in corresponding Re-Distributor */ + gic_r_write(sc, 4, GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq), + GICD_I_MASK(irq)); + gic_v3_wait_for_rwp(sc, REDIST); + } else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) { + /* SPIs in distributor */ + gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq)); + gic_v3_wait_for_rwp(sc, DIST); + } else + panic("%s: Unsupported IRQ %u", __func__, irq); +} + +static void +gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc) +{ + struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; + + gic_v3_disable_intr(dev, isrc); + gic_icc_write(EOIR1, gi->gi_irq); +} + +static void +gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc) +{ + + gic_v3_enable_intr(dev, isrc); +} + +static void +gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc) +{ + struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; + + if (gi->gi_pol == INTR_TRIGGER_EDGE) + return; + + gic_icc_write(EOIR1, gi->gi_irq); +} + +static int +gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc) +{ + struct gic_v3_softc *sc; + struct gic_v3_irqsrc *gi; + int cpu; + + gi = (struct gic_v3_irqsrc *)isrc; + if (gi->gi_irq <= GIC_LAST_PPI) + return (EINVAL); + + KASSERT(gi->gi_irq >= GIC_FIRST_SPI && gi->gi_irq <= GIC_LAST_SPI, + ("%s: Attempting to bind an invalid IRQ", __func__)); + + sc = device_get_softc(dev); + + if (CPU_EMPTY(&isrc->isrc_cpu)) { + gic_irq_cpu = intr_irq_next_cpu(gic_irq_cpu, &all_cpus); + CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu); + gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq), + CPU_AFFINITY(gic_irq_cpu)); + } else { + /* + * We can only bind to a single CPU so select + * the first CPU found. + */ + cpu = CPU_FFS(&isrc->isrc_cpu) - 1; + gic_d_write(sc, 4, GICD_IROUTER(gi->gi_irq), CPU_AFFINITY(cpu)); + } + + return (0); +} + +#ifdef SMP +static void +gic_v3_init_secondary(device_t dev) +{ + struct gic_v3_softc *sc; + gic_v3_initseq_t *init_func; + struct intr_irqsrc *isrc; + u_int cpu, irq; + int err; + + sc = device_get_softc(dev); + cpu = PCPU_GET(cpuid); + + /* Train init sequence for boot CPU */ + for (init_func = gic_v3_secondary_init; *init_func != NULL; + init_func++) { + err = (*init_func)(sc); + if (err != 0) { + device_printf(dev, + "Could not initialize GIC for CPU%u\n", cpu); + return; + } + } + + /* Unmask attached SGI interrupts. */ + for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) { + isrc = GIC_INTR_ISRC(sc, irq); + if (intr_isrc_init_on_cpu(isrc, cpu)) + gic_v3_enable_intr(dev, isrc); + } + + /* Unmask attached PPI interrupts. */ + for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) { + isrc = GIC_INTR_ISRC(sc, irq); + if (intr_isrc_init_on_cpu(isrc, cpu)) + gic_v3_enable_intr(dev, isrc); + } +} + +static void +gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, + u_int ipi) +{ + struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc; + uint64_t aff, val, irq; + int i; + +#define GIC_AFF_MASK (CPU_AFF3_MASK | CPU_AFF2_MASK | CPU_AFF1_MASK) +#define GIC_AFFINITY(i) (CPU_AFFINITY(i) & GIC_AFF_MASK) + aff = GIC_AFFINITY(0); + irq = gi->gi_irq; + val = 0; + + /* Iterate through all CPUs in set */ + for (i = 0; i < mp_ncpus; i++) { + /* Move to the next affinity group */ + if (aff != GIC_AFFINITY(i)) { + /* Send the IPI */ + if (val != 0) { + gic_icc_write(SGI1R, val); + val = 0; + } + aff = GIC_AFFINITY(i); + } + + /* Send the IPI to this cpu */ + if (CPU_ISSET(i, &cpus)) { +#define ICC_SGI1R_AFFINITY(aff) \ + (((uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT) | \ + ((uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT) | \ + ((uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT)) + /* Set the affinity when the first at this level */ + if (val == 0) + val = ICC_SGI1R_AFFINITY(aff) | + irq << ICC_SGI1R_EL1_SGIID_SHIFT; + /* Set the bit to send the IPI to te CPU */ + val |= 1 << CPU_AFF0(CPU_AFFINITY(i)); + } + } + + /* Send the IPI to the last cpu affinity group */ + if (val != 0) + gic_icc_write(SGI1R, val); +#undef GIC_AFF_MASK +#undef GIC_AFFINITY +} + +static int +gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp) +{ + struct intr_irqsrc *isrc; + struct gic_v3_softc *sc = device_get_softc(dev); + + if (sgi_first_unused > GIC_LAST_SGI) + return (ENOSPC); + + isrc = GIC_INTR_ISRC(sc, sgi_first_unused); + sgi_to_ipi[sgi_first_unused++] = ipi; + + CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu); + + *isrcp = isrc; + return (0); +} +#endif /* SMP */ +#else /* INTRNG */ /* * PIC interface. */ @@ -451,6 +1042,7 @@ gic_v3_ipi_send(device_t dev, cpuset_t cpuset, u_int ipi) } } #endif +#endif /* !INTRNG */ /* * Helper routines diff --git a/sys/arm64/arm64/gic_v3_fdt.c b/sys/arm64/arm64/gic_v3_fdt.c index 3f21fee..5466900 100644 --- a/sys/arm64/arm64/gic_v3_fdt.c +++ b/sys/arm64/arm64/gic_v3_fdt.c @@ -38,14 +38,13 @@ __FBSDID("$FreeBSD$"); #include <sys/module.h> #include <sys/rman.h> +#include <machine/intr.h> #include <machine/resource.h> #include <dev/ofw/openfirm.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> -#include "pic_if.h" - #include "gic_v3_reg.h" #include "gic_v3_var.h" @@ -117,6 +116,9 @@ gic_v3_fdt_attach(device_t dev) { struct gic_v3_softc *sc; pcell_t redist_regions; +#ifdef INTRNG + intptr_t xref; +#endif int err; sc = device_get_softc(dev); @@ -132,8 +134,22 @@ gic_v3_fdt_attach(device_t dev) sc->gic_redists.nregions = redist_regions; err = gic_v3_attach(dev); - if (err) + if (err != 0) + goto error; + +#ifdef INTRNG + xref = OF_xref_from_node(ofw_bus_get_node(dev)); + if (intr_pic_register(dev, xref) == NULL) { + device_printf(dev, "could not register PIC\n"); goto error; + } + + if (intr_pic_claim_root(dev, xref, arm_gic_v3_intr, sc, + GIC_LAST_SGI - GIC_FIRST_SGI + 1) != 0) { + goto error; + } +#endif + /* * Try to register ITS to this GIC. * GIC will act as a bus in that case. @@ -156,7 +172,7 @@ error: /* Failure so free resources */ gic_v3_detach(dev); - return (err); + return (ENXIO); } /* OFW bus interface */ @@ -279,6 +295,7 @@ gic_v3_ofw_bus_attach(device_t dev) return (bus_generic_attach(dev)); } +#ifndef INTRNG static int gic_v3_its_fdt_probe(device_t dev); static device_method_t gic_v3_its_fdt_methods[] = { @@ -310,3 +327,4 @@ gic_v3_its_fdt_probe(device_t dev) device_set_desc(dev, GIC_V3_ITS_DEVSTR); return (BUS_PROBE_DEFAULT); } +#endif diff --git a/sys/arm64/arm64/gic_v3_its.c b/sys/arm64/arm64/gic_v3_its.c index a2cfa55..c16cf0a 100644 --- a/sys/arm64/arm64/gic_v3_its.c +++ b/sys/arm64/arm64/gic_v3_its.c @@ -75,8 +75,10 @@ static device_method_t gic_v3_its_methods[] = { */ /* MSI-X */ DEVMETHOD(pic_alloc_msix, gic_v3_its_alloc_msix), + DEVMETHOD(pic_release_msix, gic_v3_its_release_msix), /* MSI */ DEVMETHOD(pic_alloc_msi, gic_v3_its_alloc_msi), + DEVMETHOD(pic_release_msi, gic_v3_its_release_msi), DEVMETHOD(pic_map_msi, gic_v3_its_map_msi), /* End */ @@ -882,6 +884,7 @@ retry: bit_nset(bitmap, fclr, fclr + nvecs - 1); lpic->lpi_base = fclr + GIC_FIRST_LPI; lpic->lpi_num = nvecs; + lpic->lpi_busy = 0; lpic->lpi_free = lpic->lpi_num; lpic->lpi_col_ids = col_ids; for (i = 0; i < lpic->lpi_num; i++) { @@ -901,10 +904,9 @@ lpi_free_chunk(struct gic_v3_its_softc *sc, struct lpi_chunk *lpic) { int start, end; - KASSERT((lpic->lpi_free == lpic->lpi_num), - ("Trying to free LPI chunk that is still in use.\n")); - mtx_lock_spin(&sc->its_dev_lock); + KASSERT((lpic->lpi_busy == 0), + ("Trying to free LPI chunk that is still in use.\n")); /* First bit of this chunk in a global bitmap */ start = lpic->lpi_base - GIC_FIRST_LPI; /* and last bit of this chunk... */ @@ -1493,6 +1495,7 @@ its_device_alloc(struct gic_v3_its_softc *sc, device_t pci_dev, u_int nvecs) { struct its_dev *newdev; + vm_offset_t itt_addr; uint64_t typer; uint32_t devid; size_t esize; @@ -1528,16 +1531,18 @@ its_device_alloc(struct gic_v3_its_softc *sc, device_t pci_dev, * Allocate ITT for this device. * PA has to be 256 B aligned. At least two entries for device. */ - newdev->itt = (vm_offset_t)contigmalloc( - roundup2(roundup2(nvecs, 2) * esize, 0x100), M_GIC_V3_ITS, - (M_NOWAIT | M_ZERO), 0, ~0UL, 0x100, 0); - if (newdev->itt == 0) { + newdev->itt_size = roundup2(roundup2(nvecs, 2) * esize, 0x100); + itt_addr = (vm_offset_t)contigmalloc( + newdev->itt_size, M_GIC_V3_ITS, (M_NOWAIT | M_ZERO), + 0, ~0UL, 0x100, 0); + if (itt_addr == 0) { lpi_free_chunk(sc, &newdev->lpis); free(newdev, M_GIC_V3_ITS); return (NULL); } mtx_lock_spin(&sc->its_dev_lock); + newdev->itt = itt_addr; TAILQ_INSERT_TAIL(&sc->its_dev_list, newdev, entry); mtx_unlock_spin(&sc->its_dev_lock); @@ -1547,6 +1552,50 @@ its_device_alloc(struct gic_v3_its_softc *sc, device_t pci_dev, return (newdev); } +static void +its_device_free(struct gic_v3_its_softc *sc, device_t pci_dev, + u_int nvecs) +{ + struct its_dev *odev; + + mtx_lock_spin(&sc->its_dev_lock); + /* Find existing device if any */ + odev = its_device_find_locked(sc, pci_dev, 0); + if (odev == NULL) { + mtx_unlock_spin(&sc->its_dev_lock); + return; + } + + KASSERT((nvecs <= odev->lpis.lpi_num) && (nvecs <= odev->lpis.lpi_busy), + ("Invalid number of LPI vectors to free %d (total %d) (busy %d)", + nvecs, odev->lpis.lpi_num, odev->lpis.lpi_busy)); + /* Just decrement number of busy LPIs in chunk */ + odev->lpis.lpi_busy -= nvecs; + if (odev->lpis.lpi_busy != 0) { + mtx_unlock_spin(&sc->its_dev_lock); + return; + } + + /* + * At that point we know that there are no busy LPIs for this device. + * Entire ITS device can now be removed. + */ + mtx_unlock_spin(&sc->its_dev_lock); + /* Unmap device in ITS */ + its_cmd_mapd(sc, odev, 0); + /* Free ITT */ + KASSERT(odev->itt != 0, ("Invalid ITT in valid ITS device")); + contigfree((void *)odev->itt, odev->itt_size, M_GIC_V3_ITS); + /* Free chunk */ + lpi_free_chunk(sc, &odev->lpis); + /* Free device */ + mtx_lock_spin(&sc->its_dev_lock); + TAILQ_REMOVE(&sc->its_dev_list, odev, entry); + mtx_unlock_spin(&sc->its_dev_lock); + free((void *)odev, M_GIC_V3_ITS); + +} + static __inline void its_device_asign_lpi_locked(struct gic_v3_its_softc *sc, struct its_dev *its_dev, u_int *irq) @@ -1561,6 +1610,7 @@ its_device_asign_lpi_locked(struct gic_v3_its_softc *sc, *irq = its_dev->lpis.lpi_base + (its_dev->lpis.lpi_num - its_dev->lpis.lpi_free); its_dev->lpis.lpi_free--; + its_dev->lpis.lpi_busy++; } /* @@ -1678,6 +1728,18 @@ gic_v3_its_alloc_msix(device_t dev, device_t pci_dev, int *irq) } int +gic_v3_its_release_msix(device_t dev, device_t pci_dev, int irq __unused) +{ + + struct gic_v3_its_softc *sc; + + sc = device_get_softc(dev); + its_device_free(sc, pci_dev, 1); + + return (0); +} + +int gic_v3_its_alloc_msi(device_t dev, device_t pci_dev, int count, int *irqs) { struct gic_v3_its_softc *sc; @@ -1701,6 +1763,18 @@ gic_v3_its_alloc_msi(device_t dev, device_t pci_dev, int count, int *irqs) } int +gic_v3_its_release_msi(device_t dev, device_t pci_dev, int count, + int *irqs __unused) +{ + struct gic_v3_its_softc *sc; + + sc = device_get_softc(dev); + its_device_free(sc, pci_dev, count); + + return (0); +} + +int gic_v3_its_map_msi(device_t dev, device_t pci_dev, int irq, uint64_t *addr, uint32_t *data) { diff --git a/sys/arm64/arm64/gic_v3_var.h b/sys/arm64/arm64/gic_v3_var.h index d95586c..5d026b9 100644 --- a/sys/arm64/arm64/gic_v3_var.h +++ b/sys/arm64/arm64/gic_v3_var.h @@ -41,6 +41,15 @@ DECLARE_CLASS(gic_v3_driver); /* 1 bit per LPI + 1 KB more for the obligatory PPI, SGI, SPI stuff */ #define LPI_PENDTAB_SIZE ((LPI_CONFTAB_SIZE / 8) + 0x400) +#ifdef INTRNG +struct gic_v3_irqsrc { + struct intr_irqsrc gi_isrc; + uint32_t gi_irq; + enum intr_polarity gi_pol; + enum intr_trigger gi_trig; +}; +#endif + struct redist_lpis { vm_offset_t conf_base; vm_offset_t pend_base[MAXCPU]; @@ -75,13 +84,22 @@ struct gic_v3_softc { u_int gic_idbits; boolean_t gic_registered; + +#ifdef INTRNG + struct gic_v3_irqsrc *gic_irqs; +#endif }; +#ifdef INTRNG +#define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc) +#endif + MALLOC_DECLARE(M_GIC_V3); /* Device methods */ int gic_v3_attach(device_t dev); int gic_v3_detach(device_t dev); +int arm_gic_v3_intr(void *); /* * ITS @@ -94,9 +112,11 @@ DECLARE_CLASS(gic_v3_its_driver); /* LPI chunk owned by ITS device */ struct lpi_chunk { u_int lpi_base; - u_int lpi_num; u_int lpi_free; /* First free LPI in set */ u_int *lpi_col_ids; + + u_int lpi_num; /* Total number of LPIs in chunk */ + u_int lpi_busy; /* Number of busy LPIs in chink */ }; /* ITS device */ @@ -110,6 +130,7 @@ struct its_dev { struct lpi_chunk lpis; /* Virtual address of ITT */ vm_offset_t itt; + size_t itt_size; }; TAILQ_HEAD(its_dev_list, its_dev); @@ -259,7 +280,9 @@ extern devclass_t gic_v3_its_devclass; int gic_v3_its_detach(device_t); int gic_v3_its_alloc_msix(device_t, device_t, int *); +int gic_v3_its_release_msix(device_t, device_t, int); int gic_v3_its_alloc_msi(device_t, device_t, int, int *); +int gic_v3_its_release_msi(device_t, device_t, int, int *); int gic_v3_its_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); int its_init_cpu(struct gic_v3_its_softc *); diff --git a/sys/arm64/arm64/mp_machdep.c b/sys/arm64/arm64/mp_machdep.c index 22c99ba..c90d59a 100644 --- a/sys/arm64/arm64/mp_machdep.c +++ b/sys/arm64/arm64/mp_machdep.c @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2015 The FreeBSD Foundation + * Copyright (c) 2015-2016 The FreeBSD Foundation * All rights reserved. * * This software was developed by Andrew Turner under @@ -65,6 +65,29 @@ __FBSDID("$FreeBSD$"); #include <dev/psci/psci.h> +#ifdef INTRNG +#include "pic_if.h" + +typedef void intr_ipi_send_t(void *, cpuset_t, u_int); +typedef void intr_ipi_handler_t(void *); + +#define INTR_IPI_NAMELEN (MAXCOMLEN + 1) +struct intr_ipi { + intr_ipi_handler_t * ii_handler; + void * ii_handler_arg; + intr_ipi_send_t * ii_send; + void * ii_send_arg; + char ii_name[INTR_IPI_NAMELEN]; + u_long * ii_count; +}; + +static struct intr_ipi ipi_sources[INTR_IPI_COUNT]; + +static struct intr_ipi *intr_ipi_lookup(u_int); +static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *, + void *); +#endif /* INTRNG */ + boolean_t ofw_cpu_reg(phandle_t node, u_int, cell_t *); extern struct pcpu __pcpu[]; @@ -184,9 +207,18 @@ release_aps(void *dummy __unused) { int cpu, i; +#ifdef INTRNG + intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL); + intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL); + intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL); + intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL); + intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL); + intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL); +#else /* Setup the IPI handler */ for (i = 0; i < INTR_IPI_COUNT; i++) arm_setup_ipihandler(ipi_handler, i); +#endif atomic_store_rel_int(&aps_ready, 1); /* Wake up the other CPUs */ @@ -214,7 +246,9 @@ void init_secondary(uint64_t cpu) { struct pcpu *pcpup; +#ifndef INTRNG int i; +#endif pcpup = &__pcpu[cpu]; /* @@ -241,11 +275,15 @@ init_secondary(uint64_t cpu) */ identify_cpu(); +#ifdef INTRNG + intr_pic_init_secondary(); +#else /* Configure the interrupt controller */ arm_init_secondary(); for (i = 0; i < INTR_IPI_COUNT; i++) arm_unmask_ipi(i); +#endif /* Start per-CPU event timers. */ cpu_initclocks_ap(); @@ -277,6 +315,64 @@ init_secondary(uint64_t cpu) /* NOTREACHED */ } +#ifdef INTRNG +/* + * Send IPI thru interrupt controller. + */ +static void +pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi) +{ + + KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__)); + PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi); +} + +/* + * Setup IPI handler on interrupt controller. + * + * Not SMP coherent. + */ +static void +intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand, + void *arg) +{ + struct intr_irqsrc *isrc; + struct intr_ipi *ii; + int error; + + KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__)); + KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi)); + + error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc); + if (error != 0) + return; + + isrc->isrc_handlers++; + + ii = intr_ipi_lookup(ipi); + KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi)); + + ii->ii_handler = hand; + ii->ii_handler_arg = arg; + ii->ii_send = pic_ipi_send; + ii->ii_send_arg = isrc; + strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN); + ii->ii_count = intr_ipi_setup_counters(name); +} + +static void +intr_ipi_send(cpuset_t cpus, u_int ipi) +{ + struct intr_ipi *ii; + + ii = intr_ipi_lookup(ipi); + if (ii->ii_count == NULL) + panic("%s: not setup IPI %u", __func__, ipi); + + ii->ii_send(ii->ii_send_arg, cpus, ipi); +} +#endif + static void ipi_ast(void *dummy __unused) { @@ -329,6 +425,7 @@ ipi_stop(void *dummy __unused) CTR0(KTR_SMP, "IPI_STOP (restart)"); } +#ifndef INTRNG static int ipi_handler(void *arg) { @@ -364,6 +461,7 @@ ipi_handler(void *arg) return (FILTER_HANDLED); } +#endif struct cpu_group * cpu_topo(void) @@ -490,3 +588,149 @@ cpu_mp_setmaxid(void) mp_ncpus = 1; mp_maxid = 0; } + +#ifdef INTRNG +/* + * Lookup IPI source. + */ +static struct intr_ipi * +intr_ipi_lookup(u_int ipi) +{ + + if (ipi >= INTR_IPI_COUNT) + panic("%s: no such IPI %u", __func__, ipi); + + return (&ipi_sources[ipi]); +} + +/* + * interrupt controller dispatch function for IPIs. It should + * be called straight from the interrupt controller, when associated + * interrupt source is learned. Or from anybody who has an interrupt + * source mapped. + */ +void +intr_ipi_dispatch(u_int ipi, struct trapframe *tf) +{ + void *arg; + struct intr_ipi *ii; + + ii = intr_ipi_lookup(ipi); + if (ii->ii_count == NULL) + panic("%s: not setup IPI %u", __func__, ipi); + + intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid)); + + /* + * Supply ipi filter with trapframe argument + * if none is registered. + */ + arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf; + ii->ii_handler(arg); +} + +#ifdef notyet +/* + * Map IPI into interrupt controller. + * + * Not SMP coherent. + */ +static int +ipi_map(struct intr_irqsrc *isrc, u_int ipi) +{ + boolean_t is_percpu; + int error; + + if (ipi >= INTR_IPI_COUNT) + panic("%s: no such IPI %u", __func__, ipi); + + KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__)); + + isrc->isrc_type = INTR_ISRCT_NAMESPACE; + isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI; + isrc->isrc_nspc_num = ipi_next_num; + + error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu); + if (error == 0) { + isrc->isrc_dev = intr_irq_root_dev; + ipi_next_num++; + } + return (error); +} + +/* + * Setup IPI handler to interrupt source. + * + * Note that there could be more ways how to send and receive IPIs + * on a platform like fast interrupts for example. In that case, + * one can call this function with ASIF_NOALLOC flag set and then + * call intr_ipi_dispatch() when appropriate. + * + * Not SMP coherent. + */ +int +intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter, + void *arg, u_int flags) +{ + struct intr_irqsrc *isrc; + int error; + + if (filter == NULL) + return(EINVAL); + + isrc = intr_ipi_lookup(ipi); + if (isrc->isrc_ipifilter != NULL) + return (EEXIST); + + if ((flags & AISHF_NOALLOC) == 0) { + error = ipi_map(isrc, ipi); + if (error != 0) + return (error); + } + + isrc->isrc_ipifilter = filter; + isrc->isrc_arg = arg; + isrc->isrc_handlers = 1; + isrc->isrc_count = intr_ipi_setup_counters(name); + isrc->isrc_index = 0; /* it should not be used in IPI case */ + + if (isrc->isrc_dev != NULL) { + PIC_ENABLE_INTR(isrc->isrc_dev, isrc); + PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc); + } + return (0); +} +#endif + +/* Sending IPI */ +void +ipi_all_but_self(u_int ipi) +{ + cpuset_t cpus; + + cpus = all_cpus; + CPU_CLR(PCPU_GET(cpuid), &cpus); + CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); + intr_ipi_send(cpus, ipi); +} + +void +ipi_cpu(int cpu, u_int ipi) +{ + cpuset_t cpus; + + CPU_ZERO(&cpus); + CPU_SET(cpu, &cpus); + + CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi); + intr_ipi_send(cpus, ipi); +} + +void +ipi_selected(cpuset_t cpus, u_int ipi) +{ + + CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); + intr_ipi_send(cpus, ipi); +} +#endif /* INTRNG */ diff --git a/sys/arm64/arm64/nexus.c b/sys/arm64/arm64/nexus.c index ec71409..93f55ae 100644 --- a/sys/arm64/arm64/nexus.c +++ b/sys/arm64/arm64/nexus.c @@ -271,7 +271,13 @@ nexus_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol) { +#ifdef INTRNG + /* TODO: This is wrong, it's needed for ACPI */ + device_printf(dev, "bus_config_intr is obsolete and not supported!\n"); + return (EOPNOTSUPP); +#else return (intr_irq_config(irq, trig, pol)); +#endif } static int @@ -288,8 +294,12 @@ nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags, if (error) return (error); +#ifdef INTRNG + error = intr_setup_irq(child, res, filt, intr, arg, flags, cookiep); +#else error = arm_setup_intr(device_get_nameunit(child), filt, intr, arg, rman_get_start(res), flags, cookiep); +#endif return (error); } @@ -298,7 +308,11 @@ static int nexus_teardown_intr(device_t dev, device_t child, struct resource *r, void *ih) { +#ifdef INTRNG + return (intr_teardown_irq(child, r, ih)); +#else return (intr_irq_remove_handler(child, rman_get_start(r), ih)); +#endif } #ifdef SMP @@ -306,7 +320,11 @@ static int nexus_bind_intr(device_t dev, device_t child, struct resource *irq, int cpu) { +#ifdef INTRNG + return (intr_bind_irq(child, irq, cpu)); +#else return (intr_irq_bind(rman_get_start(irq), cpu)); +#endif } #endif @@ -429,6 +447,9 @@ static int nexus_ofw_map_intr(device_t dev, device_t child, phandle_t iparent, int icells, pcell_t *intr) { +#ifdef INTRNG + return (intr_fdt_map_irq(iparent, intr, icells)); +#else int irq; if (icells == 3) { @@ -441,6 +462,7 @@ nexus_ofw_map_intr(device_t dev, device_t child, phandle_t iparent, int icells, irq = intr[0]; return (irq); +#endif } #endif diff --git a/sys/arm64/conf/GENERIC-INTRNG b/sys/arm64/conf/GENERIC-INTRNG new file mode 100644 index 0000000..9cab02b --- /dev/null +++ b/sys/arm64/conf/GENERIC-INTRNG @@ -0,0 +1,15 @@ +# +# GENERIC-INTRNG -- intrng testing kernel for FreeBSD/arm64 +# +# This config adds intrng support for testing, and to ensure intrng is not +# broken before switching to it. The config is expected to be removed soon +# when intrng becomes the default on arm64. +# +# $FreeBSD$ +# + +include GENERIC + +ident GENERIC-INTRNG + +options INTRNG diff --git a/sys/arm64/include/intr.h b/sys/arm64/include/intr.h index 327b249..cf3e0c5 100644 --- a/sys/arm64/include/intr.h +++ b/sys/arm64/include/intr.h @@ -29,6 +29,28 @@ #ifndef _MACHINE_INTR_H_ #define _MACHINE_INTR_H_ +#ifdef INTRNG + +#ifdef FDT +#include <dev/ofw/openfirm.h> +#endif + +#include <sys/intr.h> + +#ifndef NIRQ +#define NIRQ 1024 /* XXX - It should be an option. */ +#endif + +static inline void +arm_irq_memory_barrier(uintptr_t irq) +{ +} + +#ifdef SMP +void intr_ipi_dispatch(u_int, struct trapframe *); +#endif + +#else int intr_irq_config(u_int, enum intr_trigger, enum intr_polarity); void intr_irq_handler(struct trapframe *); int intr_irq_remove_handler(device_t, u_int, void *); @@ -55,5 +77,6 @@ void arm_init_secondary(void); void arm_setup_ipihandler(driver_filter_t *, u_int); void arm_unmask_ipi(u_int); #endif +#endif #endif /* _MACHINE_INTR_H */ diff --git a/sys/boot/common/bootstrap.h b/sys/boot/common/bootstrap.h index cbfc6f0..e15fc6a 100644 --- a/sys/boot/common/bootstrap.h +++ b/sys/boot/common/bootstrap.h @@ -102,6 +102,7 @@ struct console #define C_PRESENTOUT (1<<1) /* console can provide output */ #define C_ACTIVEIN (1<<2) /* user wants input from console */ #define C_ACTIVEOUT (1<<3) /* user wants output to console */ +#define C_WIDEOUT (1<<4) /* c_out routine groks wide chars */ void (* c_probe)(struct console *cp); /* set c_flags to match hardware */ int (* c_init)(int arg); /* reinit XXX may need more args */ void (* c_out)(int c); /* emit c */ diff --git a/sys/boot/common/commands.c b/sys/boot/common/commands.c index 7fba019..c60c612 100644 --- a/sys/boot/common/commands.c +++ b/sys/boot/common/commands.c @@ -211,6 +211,14 @@ command_help(int argc, char *argv[]) COMMAND_SET(commandlist, "?", "list commands", command_commandlist); +/* + * Please note: although we use the pager for the list of commands, + * this routine is called from the ? FORTH function which then + * unconditionally prints some commands. This will lead to anomalous + * behavior. There's no 'pager_output' binding to FORTH to allow + * things to work right, so I'm documenting the bug rather than + * fixing it. + */ static int command_commandlist(int argc, char *argv[]) { diff --git a/sys/boot/common/disk.c b/sys/boot/common/disk.c index 804fb6b..54626f7 100644 --- a/sys/boot/common/disk.c +++ b/sys/boot/common/disk.c @@ -183,13 +183,14 @@ ptblread(void *d, void *buf, size_t blocks, off_t offset) } #define PWIDTH 35 -static void +static int ptable_print(void *arg, const char *pname, const struct ptable_entry *part) { struct print_args *pa, bsd; struct open_disk *od; struct ptable *table; char line[80]; + int res; pa = (struct print_args *)arg; od = (struct open_disk *)pa->dev->d_opendata; @@ -200,25 +201,29 @@ ptable_print(void *arg, const char *pname, const struct ptable_entry *part) display_size(part->end - part->start + 1, od->sectorsize)); strcat(line, "\n"); - pager_output(line); + if (pager_output(line)) + return 1; + res = 0; if (part->type == PART_FREEBSD) { /* Open slice with BSD label */ pa->dev->d_offset = part->start; table = ptable_open(pa->dev, part->end - part->start + 1, od->sectorsize, ptblread); if (table == NULL) - return; + return 0; sprintf(line, " %s%s", pa->prefix, pname); bsd.dev = pa->dev; bsd.prefix = line; bsd.verbose = pa->verbose; - ptable_iterate(table, &bsd, ptable_print); + res = ptable_iterate(table, &bsd, ptable_print); ptable_close(table); } + + return (res); } #undef PWIDTH -void +int disk_print(struct disk_devdesc *dev, char *prefix, int verbose) { struct open_disk *od; @@ -229,7 +234,7 @@ disk_print(struct disk_devdesc *dev, char *prefix, int verbose) pa.dev = dev; pa.prefix = prefix; pa.verbose = verbose; - ptable_iterate(od->table, &pa, ptable_print); + return (ptable_iterate(od->table, &pa, ptable_print)); } int diff --git a/sys/boot/common/disk.h b/sys/boot/common/disk.h index d24fb1a..d17ace9 100644 --- a/sys/boot/common/disk.h +++ b/sys/boot/common/disk.h @@ -112,7 +112,7 @@ extern int ptblread(void *d, void *buf, size_t blocks, off_t offset); /* * Print information about slices on a disk. */ -extern void disk_print(struct disk_devdesc *dev, char *prefix, int verbose); +extern int disk_print(struct disk_devdesc *dev, char *prefix, int verbose); extern char* disk_fmtdev(struct disk_devdesc *dev); extern int disk_parsedev(struct disk_devdesc *dev, const char *devspec, const char **path); diff --git a/sys/boot/common/module.c b/sys/boot/common/module.c index f8baf98..15c4807 100644 --- a/sys/boot/common/module.c +++ b/sys/boot/common/module.c @@ -277,7 +277,8 @@ command_lsmod(int argc, char *argv[]) if (fp->f_args != NULL) { pager_output(" args: "); pager_output(fp->f_args); - pager_output("\n"); + if (pager_output("\n")) + break; } if (fp->f_modules) { pager_output(" modules: "); @@ -285,13 +286,15 @@ command_lsmod(int argc, char *argv[]) sprintf(lbuf, "%s.%d ", mp->m_name, mp->m_version); pager_output(lbuf); } - pager_output("\n"); - } + if (pager_output("\n")) + break; + } if (verbose) { /* XXX could add some formatting smarts here to display some better */ for (md = fp->f_metadata; md != NULL; md = md->md_next) { sprintf(lbuf, " 0x%04x, 0x%lx\n", md->md_type, (long) md->md_size); - pager_output(lbuf); + if (pager_output(lbuf)) + break; } } } diff --git a/sys/boot/common/part.c b/sys/boot/common/part.c index 33da7bc..51cceca5b 100644 --- a/sys/boot/common/part.c +++ b/sys/boot/common/part.c @@ -829,7 +829,7 @@ ptable_getbestpart(const struct ptable *table, struct ptable_entry *part) return (ENOENT); } -void +int ptable_iterate(const struct ptable *table, void *arg, ptable_iterate_t *iter) { struct pentry *entry; @@ -856,7 +856,9 @@ ptable_iterate(const struct ptable *table, void *arg, ptable_iterate_t *iter) if (table->type == PTABLE_BSD) sprintf(name, "%c", (u_char) 'a' + entry->part.index); - iter(arg, name, &entry->part); + if (iter(arg, name, &entry->part)) + return 1; } + return 0; } diff --git a/sys/boot/common/part.h b/sys/boot/common/part.h index 9f80267..217bf3b 100644 --- a/sys/boot/common/part.h +++ b/sys/boot/common/part.h @@ -63,7 +63,7 @@ struct ptable_entry { /* The offset and size are in sectors */ typedef int (diskread_t)(void *arg, void *buf, size_t blocks, off_t offset); -typedef void (ptable_iterate_t)(void *arg, const char *partname, +typedef int (ptable_iterate_t)(void *arg, const char *partname, const struct ptable_entry *part); struct ptable *ptable_open(void *dev, off_t sectors, uint16_t sectorsize, @@ -75,7 +75,7 @@ int ptable_getpart(const struct ptable *table, struct ptable_entry *part, int index); int ptable_getbestpart(const struct ptable *table, struct ptable_entry *part); -void ptable_iterate(const struct ptable *table, void *arg, +int ptable_iterate(const struct ptable *table, void *arg, ptable_iterate_t *iter); const char *parttype2str(enum partition_type type); diff --git a/sys/boot/common/pnp.c b/sys/boot/common/pnp.c index 589926b..80485f0 100644 --- a/sys/boot/common/pnp.c +++ b/sys/boot/common/pnp.c @@ -68,15 +68,18 @@ pnp_scan(int argc, char *argv[]) } if (verbose) { pager_open(); - pager_output("PNP scan summary:\n"); + if (pager_output("PNP scan summary:\n")) + goto out; STAILQ_FOREACH(pi, &pnp_devices, pi_link) { pager_output(STAILQ_FIRST(&pi->pi_ident)->id_ident); /* first ident should be canonical */ if (pi->pi_desc != NULL) { pager_output(" : "); pager_output(pi->pi_desc); } - pager_output("\n"); + if (pager_output("\n")) + break; } +out: pager_close(); } return(CMD_OK); diff --git a/sys/boot/common/util.c b/sys/boot/common/util.c index 21834be..5869f97 100644 --- a/sys/boot/common/util.c +++ b/sys/boot/common/util.c @@ -120,6 +120,7 @@ printf(const char *fmt, ...) va_list ap; const char *hex = "0123456789abcdef"; char buf[32], *s; + uint16_t *S; unsigned long long u; int c, l; @@ -143,6 +144,10 @@ nextfmt: for (s = va_arg(ap, char *); *s != '\0'; s++) putchar(*s); break; + case 'S': /* Assume console can cope with wide chars */ + for (S = va_arg(ap, uint16_t *); *S != 0; S++) + putchar(*S); + break; case 'd': /* A lie, always prints unsigned */ case 'u': case 'x': diff --git a/sys/boot/efi/libefi/Makefile b/sys/boot/efi/libefi/Makefile index bb2f9ea..82119a5 100644 --- a/sys/boot/efi/libefi/Makefile +++ b/sys/boot/efi/libefi/Makefile @@ -4,7 +4,7 @@ LIB= efi INTERNALLIB= WARNS?= 2 -SRCS= delay.c efi_console.c efinet.c efipart.c errno.c handles.c \ +SRCS= delay.c efi_console.c efinet.c efipart.c env.c errno.c handles.c \ libefi.c time.c .if ${MACHINE_CPUARCH} == "aarch64" diff --git a/sys/boot/efi/libefi/efi_console.c b/sys/boot/efi/libefi/efi_console.c index daf1338..68c9a6b 100644 --- a/sys/boot/efi/libefi/efi_console.c +++ b/sys/boot/efi/libefi/efi_console.c @@ -61,7 +61,7 @@ int efi_cons_poll(void); struct console efi_console = { "efi", "EFI console", - 0, + C_WIDEOUT, efi_cons_probe, efi_cons_init, efi_cons_putchar, @@ -266,6 +266,8 @@ CL(int direction) case 2: /* entire line */ len = x; break; + default: /* NOTREACHED */ + __unreachable(); } if (cury == y - 1) diff --git a/sys/boot/efi/libefi/efinet.c b/sys/boot/efi/libefi/efinet.c index b7888aa..4d367b5 100644 --- a/sys/boot/efi/libefi/efinet.c +++ b/sys/boot/efi/libefi/efinet.c @@ -329,9 +329,12 @@ efinet_dev_print(int verbose) EFI_HANDLE h; int unit; + pager_open(); for (unit = 0, h = efi_find_handle(&efinet_dev, 0); h != NULL; h = efi_find_handle(&efinet_dev, ++unit)) { sprintf(line, " %s%d:\n", efinet_dev.dv_name, unit); - pager_output(line); + if (pager_output(line)) + break; } + pager_close(); } diff --git a/sys/boot/efi/libefi/efipart.c b/sys/boot/efi/libefi/efipart.c index 410057c..e8691c5 100644 --- a/sys/boot/efi/libefi/efipart.c +++ b/sys/boot/efi/libefi/efipart.c @@ -180,21 +180,27 @@ efipart_print(int verbose) EFI_STATUS status; u_int unit; + pager_open(); for (unit = 0, h = efi_find_handle(&efipart_dev, 0); h != NULL; h = efi_find_handle(&efipart_dev, ++unit)) { sprintf(line, " %s%d:", efipart_dev.dv_name, unit); - pager_output(line); + if (pager_output(line)) + break; status = BS->HandleProtocol(h, &blkio_guid, (void **)&blkio); if (!EFI_ERROR(status)) { sprintf(line, " %llu blocks", (unsigned long long)(blkio->Media->LastBlock + 1)); - pager_output(line); + if (pager_output(line)) + break; if (blkio->Media->RemovableMedia) - pager_output(" (removable)"); + if (pager_output(" (removable)")) + break; } - pager_output("\n"); + if (pager_output("\n")) + break; } + pager_close(); } static int diff --git a/sys/boot/efi/libefi/env.c b/sys/boot/efi/libefi/env.c new file mode 100644 index 0000000..6cfe491 --- /dev/null +++ b/sys/boot/efi/libefi/env.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015 Netflix, Inc. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <efi.h> +#include <efilib.h> + +/* + * Simple wrappers to the underlying UEFI functions. + * See http://wiki.phoenix.com/wiki/index.php/EFI_RUNTIME_SERVICES + * for details. + */ +EFI_STATUS +efi_get_next_variable_name(UINTN *variable_name_size, CHAR16 *variable_name, EFI_GUID *vendor_guid) +{ + return RS->GetNextVariableName(variable_name_size, variable_name, vendor_guid); +} + +EFI_STATUS +efi_get_variable(CHAR16 *variable_name, EFI_GUID *vendor_guid, UINT32 *attributes, UINTN *data_size, + void *data) +{ + return RS->GetVariable(variable_name, vendor_guid, attributes, data_size, data); +} + +EFI_STATUS +efi_set_variable(CHAR16 *variable_name, EFI_GUID *vendor_guid, UINT32 attributes, UINTN data_size, + void *data) +{ + return RS->SetVariable(variable_name, vendor_guid, attributes, data_size, data); +} diff --git a/sys/boot/efi/loader/Makefile b/sys/boot/efi/loader/Makefile index f4f6cbf..43b72b0 100644 --- a/sys/boot/efi/loader/Makefile +++ b/sys/boot/efi/loader/Makefile @@ -30,6 +30,17 @@ CWARNFLAGS.zfs.c+= -Wno-sign-compare CWARNFLAGS.zfs.c+= -Wno-array-bounds CWARNFLAGS.zfs.c+= -Wno-missing-prototypes .endif +# In the loader, %S is for CHAR16 strings, not wchar_t strings. This +# mismatch causes issues on some archs, so just ignore it for now. +# The printf in libstand implements CHAR16 strings always. +CWARNFLAGS.main.c+= -Wno-format + +# We implement a slightly non-standard %S in that it always takes a +# CHAR16 that's common in UEFI-land instead of a wchar_t. This only +# seems to matter on arm64 where wchar_t defaults to an int instead +# of a short. There's no good cast to use here so just ignore the +# warnings for now. +CWARNFLAGS.main.c+= -Wno-format .PATH: ${.CURDIR}/arch/${MACHINE} # For smbios.c diff --git a/sys/boot/efi/loader/bootinfo.c b/sys/boot/efi/loader/bootinfo.c index 1f45ea3..34892c6 100644 --- a/sys/boot/efi/loader/bootinfo.c +++ b/sys/boot/efi/loader/bootinfo.c @@ -422,7 +422,7 @@ bi_load(char *args, vm_offset_t *modulep, vm_offset_t *kernendp) if (dtb_size) file_addmetadata(kfp, MODINFOMD_DTBP, sizeof dtbp, &dtbp); else - pager_output("WARNING! Trying to fire up the kernel, but no " + printf("WARNING! Trying to fire up the kernel, but no " "device tree blob found!\n"); #endif file_addmetadata(kfp, MODINFOMD_KERNEND, sizeof kernend, &kernend); diff --git a/sys/boot/efi/loader/main.c b/sys/boot/efi/loader/main.c index 2efffce..5efe631 100644 --- a/sys/boot/efi/loader/main.c +++ b/sys/boot/efi/loader/main.c @@ -31,6 +31,7 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> #include <sys/reboot.h> #include <sys/boot.h> +#include <inttypes.h> #include <stand.h> #include <string.h> #include <setjmp.h> @@ -38,6 +39,8 @@ __FBSDID("$FreeBSD$"); #include <efi.h> #include <efilib.h> +#include <uuid.h> + #include <bootstrap.h> #include <smbios.h> @@ -336,11 +339,8 @@ main(int argc, CHAR16 *argv[]) printf("Image base: 0x%lx\n", (u_long)img->ImageBase); printf("EFI version: %d.%02d\n", ST->Hdr.Revision >> 16, ST->Hdr.Revision & 0xffff); - printf("EFI Firmware: "); - /* printf doesn't understand EFI Unicode */ - ST->ConOut->OutputString(ST->ConOut, ST->FirmwareVendor); - printf(" (rev %d.%02d)\n", ST->FirmwareRevision >> 16, - ST->FirmwareRevision & 0xffff); + printf("EFI Firmware: %S (rev %d.%02d)\n", ST->FirmwareVendor, + ST->FirmwareRevision >> 16, ST->FirmwareRevision & 0xffff); printf("\n"); printf("%s, Revision %s\n", bootprog_name, bootprog_rev); @@ -394,6 +394,9 @@ main(int argc, CHAR16 *argv[]) } } + snprintf(var, sizeof(var), "%d.%02d", ST->Hdr.Revision >> 16, + ST->Hdr.Revision & 0xffff); + env_setenv("efi-version", EV_VOLATILE, var, env_noset, env_nounset); setenv("LINES", "24", 1); /* optional */ for (k = 0; k < ST->NumberOfTableEntries; k++) { @@ -409,6 +412,19 @@ main(int argc, CHAR16 *argv[]) return (EFI_SUCCESS); /* keep compiler happy */ } +/* XXX move to lib stand ? */ +static int +wcscmp(CHAR16 *a, CHAR16 *b) +{ + + while (*a && *b && *a == *b) { + a++; + b++; + } + return *a - *b; +} + + COMMAND_SET(reboot, "reboot", "reboot the system", command_reboot); static int @@ -616,6 +632,7 @@ command_mode(int argc, char *argv[]) } +/* deprecated */ COMMAND_SET(nvram, "nvram", "get or set NVRAM variables", command_nvram); static int @@ -633,6 +650,7 @@ command_nvram(int argc, char *argv[]) /* Initiate the search */ status = RS->GetNextVariableName(&varsz, NULL, NULL); + pager_open(); for (; status != EFI_NOT_FOUND; ) { status = RS->GetNextVariableName(&varsz, var, &varguid); //if (EFI_ERROR(status)) @@ -655,10 +673,11 @@ command_nvram(int argc, char *argv[]) printf("\\x%02x", data[i]); } } - /* XXX */ - pager_output("\n"); free(data); + if (pager_output("\n")) + break; } + pager_close(); return (CMD_OK); } @@ -718,6 +737,201 @@ command_reloadbe(int argc, char *argv[]) } #endif +COMMAND_SET(efishow, "efi-show", "print some or all EFI variables", command_efi_printenv); + +static int +efi_print_var(CHAR16 *varnamearg, EFI_GUID *matchguid, int lflag) +{ + UINTN datasz; + EFI_STATUS status; + UINT32 attr; + CHAR16 *data; + char *str; + uint32_t uuid_status; + + datasz = 0; + status = RS->GetVariable(varnamearg, matchguid, &attr, + &datasz, NULL); + if (status != EFI_BUFFER_TOO_SMALL) { + printf("Can't get the variable: error %#lx\n", status); + return (CMD_ERROR); + } + data = malloc(datasz); + status = RS->GetVariable(varnamearg, matchguid, &attr, + &datasz, data); + if (status != EFI_SUCCESS) { + printf("Can't get the variable: error %#lx\n", status); + return (CMD_ERROR); + } + uuid_to_string((uuid_t *)matchguid, &str, &uuid_status); + printf("%s %S=%S", str, varnamearg, data); + free(str); + free(data); + if (pager_output("\n")) + return (CMD_WARN); + return (CMD_OK); +} + +static int +command_efi_printenv(int argc, char *argv[]) +{ + /* + * efi-printenv [-a] + * print all the env + * efi-printenv -u UUID + * print all the env vars tagged with UUID + * efi-printenv -v var + * search all the env vars and print the ones matching var + * eif-printenv -u UUID -v var + * eif-printenv UUID var + * print all the env vars that match UUID and var + */ + /* XXX We assume EFI_GUID is the same as uuid_t */ + int aflag = 0, gflag = 0, lflag = 0, vflag = 0; + int ch, rv; + unsigned i; + EFI_STATUS status; + EFI_GUID varguid = { 0,0,0,{0,0,0,0,0,0,0,0} }; + EFI_GUID matchguid = { 0,0,0,{0,0,0,0,0,0,0,0} }; + uint32_t uuid_status; + CHAR16 varname[128]; + CHAR16 varnamearg[128]; + UINTN varsz; + + while ((ch = getopt(argc, argv, "ag:lv:")) != -1) { + switch (ch) { + case 'a': + aflag = 1; + break; + case 'g': + gflag = 1; + uuid_from_string(optarg, (uuid_t *)&matchguid, + &uuid_status); + if (uuid_status != uuid_s_ok) { + printf("uid %s could not be parsed\n", optarg); + return (CMD_ERROR); + } + break; + case 'l': + lflag = 1; + break; + case 'v': + vflag = 1; + if (strlen(optarg) >= nitems(varnamearg)) { + printf("Variable %s is longer than %zd characters\n", + optarg, nitems(varnamearg)); + return (CMD_ERROR); + } + for (i = 0; i < strlen(optarg); i++) + varnamearg[i] = optarg[i]; + varnamearg[i] = 0; + default: + printf("Invalid argument %c\n", ch); + return (CMD_ERROR); + } + } + + if (aflag && (gflag || vflag)) { + printf("-a isn't compatible with -v or -u\n"); + return (CMD_ERROR); + } + + if (aflag && optind < argc) { + printf("-a doesn't take any args"); + return (CMD_ERROR); + } + + if (optind == argc) + aflag = 1; + + argc -= optind; + argv += optind; + + pager_open(); + if (vflag && gflag) { + rv = efi_print_var(varnamearg, &matchguid, lflag); + pager_close(); + return (rv); + } + + if (argc == 2) { + optarg = argv[0]; + if (strlen(optarg) >= nitems(varnamearg)) { + printf("Variable %s is longer than %zd characters\n", + optarg, nitems(varnamearg)); + pager_close(); + return (CMD_ERROR); + } + for (i = 0; i < strlen(optarg); i++) + varnamearg[i] = optarg[i]; + varnamearg[i] = 0; + optarg = argv[1]; + uuid_from_string(optarg, (uuid_t *)&matchguid, + &uuid_status); + if (uuid_status != uuid_s_ok) { + printf("uid %s could not be parsed\n", optarg); + pager_close(); + return (CMD_ERROR); + } + rv = efi_print_var(varnamearg, &matchguid, lflag); + pager_close(); + return (rv); + } + + if (argc != 0) { + printf("Too many args\n"); + pager_close(); + return (CMD_ERROR); + } + + /* + * Initiate the search -- note the standard takes pain + * to specify the initial call must be a poiner to a NULL + * character. + */ + varsz = nitems(varname); + varname[0] = 0; + status = RS->GetNextVariableName(&varsz, varname, &varguid); + while (status != EFI_NOT_FOUND) { + status = RS->GetNextVariableName(&varsz, varname, + &varguid); + if (aflag) { + if (efi_print_var(varname, &varguid, lflag) != CMD_OK) + break; + continue; + } + if (vflag) { + if (wcscmp(varnamearg, varname) == 0) + if (efi_print_var(varname, &varguid, lflag) != CMD_OK) + break; + } + if (gflag) { + if (memcmp(&varguid, &matchguid, sizeof(varguid)) == 0) + if (efi_print_var(varname, &varguid, lflag) != CMD_OK) + break; + } + } + pager_close(); + + return (CMD_OK); +} + +COMMAND_SET(efiset, "efi-set", "set EFI variables", command_efi_set); + +static int +command_efi_set(int argc, char *argv[]) +{ + return (CMD_OK); +} + +COMMAND_SET(efiunset, "efi-unset", "delete / unset EFI variables", command_efi_unset); + +static int +command_efi_unset(int argc, char *argv[]) +{ + return (CMD_OK); +} + #ifdef LOADER_FDT_SUPPORT extern int command_fdt_internal(int argc, char *argv[]); diff --git a/sys/boot/fdt/dts/mips/fbsd-mt7620a.dtsi b/sys/boot/fdt/dts/mips/fbsd-mt7620a.dtsi index 36b0132..e88117b 100644 --- a/sys/boot/fdt/dts/mips/fbsd-mt7620a.dtsi +++ b/sys/boot/fdt/dts/mips/fbsd-mt7620a.dtsi @@ -1,35 +1,9 @@ /* $FreeBSD$ */ -/ { - /* Specify alias for serial0 so we have a working console */ - aliases { - serial0 = "/palmbus@10000000/uartlite@c00"; - }; - +&pcie { /* - * OpenWRT doesn't define a clock controller, but we currently need one + * Our driver is different that OpenWRT's, so we need slightly + * different values for the reg property */ - clkctrl: cltctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - /* Specify the clocks node for the usbphy */ - usbphy: usbphy { - clocks = <&clkctrl 22 &clkctrl 25>; - }; - - pcie@10140000 { - /* - * Our driver is different that OpenWRT's, so we need slightly - * different values for the reg property - */ - reg = <0x10140000 0x10000>; - - /* - * Also, we need resets and clocks defined, so we can properly - * initialize the PCIe - */ - clocks = <&clkctrl 26>; - }; + reg = <0x10140000 0x10000>; }; diff --git a/sys/boot/fdt/dts/mips/fbsd-mt7620n.dtsi b/sys/boot/fdt/dts/mips/fbsd-mt7620n.dtsi deleted file mode 100644 index 5a213db..0000000 --- a/sys/boot/fdt/dts/mips/fbsd-mt7620n.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -/* $FreeBSD$ */ - -/ { - /* Specify alias for serial0 so we have a working console */ - aliases { - serial0 = "/palmbus@10000000/uartlite@c00"; - }; - - /* - * OpenWRT doesn't define a clock controller, but we currently need one - */ - clkctrl: cltctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - /* Specify the clocks node for the usbphy */ - usbphy: usbphy { - clocks = <&clkctrl 22 &clkctrl 25>; - }; -}; diff --git a/sys/boot/fdt/dts/mips/fbsd-mt7621.dtsi b/sys/boot/fdt/dts/mips/fbsd-mt7621.dtsi index dc67925..eee36b2 100644 --- a/sys/boot/fdt/dts/mips/fbsd-mt7621.dtsi +++ b/sys/boot/fdt/dts/mips/fbsd-mt7621.dtsi @@ -1,73 +1,49 @@ /* $FreeBSD$ */ -/ { - /* Specify alias for serial0 so we have a working console */ - aliases { - serial0 = "/palmbus@1E000000/uartlite@c00"; - }; - - /* - * OpenWRT doesn't define a clock controller, but we currently need one - */ - clkctrl: cltctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - palmbus@1E000000 { - uartlite@c00 { clock-frequency = <50000000>; }; - - gpio@600 { - /* - * Mark gpio as compatible to simple-bus and override - * its #size-cells and provide a default ranges property - * so we can attach instances of our mtk_gpio_v2 driver - * to it for now. Provide exactly the same resources to - * the instances of mtk_gpio_v2. - */ - compatible = "simple-bus"; - ranges = <0x0 0x600 0x100>; - #size-cells = <1>; - - interrupt-parent = <&gic>; +&palmbus { + gpio@600 { + /* + * Mark gpio as compatible to simple-bus and override + * its #size-cells and provide a default ranges property + * so we can attach instances of our mtk_gpio_v2 driver + * to it for now. Provide exactly the same resources to + * the instances of mtk_gpio_v2. + */ + compatible = "simple-bus"; + ranges = <0x0 0x600 0x100>; + #size-cells = <1>; - gpio0: bank@0 { - reg = <0x0 0x100>; - interrupts = <0 6 4>; - }; + interrupt-parent = <&gic>; - gpio1: bank@1 { - reg = <0x0 0x100>; - interrupts = <0 6 4>; - }; + gpio0: bank@0 { + reg = <0x0 0x100>; + interrupts = <0 6 4>; + }; - gpio2: bank@2 { - reg = <0x0 0x100>; - interrupts = <0 6 4>; - }; + gpio1: bank@1 { + reg = <0x0 0x100>; + interrupts = <0 6 4>; }; - }; - xhci@1E1C0000 { - /* - * A slightly different value for reg size is needed by our - * driver for the moment - */ - reg = <0x1e1c0000 0x20000>; + gpio2: bank@2 { + reg = <0x0 0x100>; + interrupts = <0 6 4>; + }; }; +}; - pcie@1e140000 { - /* - * Our driver is different that OpenWRT's, so we need slightly - * different values for the reg property - */ - reg = <0x1e140000 0x10000>; +&xhci { + /* + * A slightly different value for reg size is needed by our + * driver for the moment + */ + reg = <0x1e1c0000 0x20000>; +}; - /* - * Also, we need resets and clocks defined, so we can properly - * initialize the PCIe - */ - resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>; - clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>; - }; +&pcie { + /* + * Our driver is different that OpenWRT's, so we need slightly + * different values for the reg property + */ + reg = <0x1e140000 0x10000>; }; diff --git a/sys/boot/fdt/dts/mips/fbsd-mt7628an.dtsi b/sys/boot/fdt/dts/mips/fbsd-mt7628an.dtsi index 9595b73..e648879 100644 --- a/sys/boot/fdt/dts/mips/fbsd-mt7628an.dtsi +++ b/sys/boot/fdt/dts/mips/fbsd-mt7628an.dtsi @@ -1,70 +1,40 @@ /* $FreeBSD$ */ -/ { - /* Specify alias for serial0 so we have a working console */ - aliases { - serial0 = "/palmbus@10000000/uart2@e00"; - }; - - /* - * OpenWRT doesn't define a clock controller, but we currently need one - */ - clkctrl: cltctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - palmbus@10000000 { - uartlite@c00 { clock-frequency = <40000000>; }; - uart1@d00 { clock-frequency = <40000000>; }; - uart2@e00 { clock-frequency = <40000000>; }; - - gpio@600 { - /* - * Mark gpio as compatible to simple-bus and override - * its #size-cells and provide a default ranges property - * so we can attach instances of our mtk_gpio_v2 driver - * to it for now. Provide exactly the same resources to - * the instances of mtk_gpio_v2. - */ - compatible = "simple-bus"; - ranges = <0x0 0x600 0x100>; - #size-cells = <1>; - - gpio0: bank@0 { - reg = <0x0 0x100>; - interrupts = <6>; - }; +&palmbus { + gpio@600 { + /* + * Mark gpio as compatible to simple-bus and override + * its #size-cells and provide a default ranges property + * so we can attach instances of our mtk_gpio_v2 driver + * to it for now. Provide exactly the same resources to + * the instances of mtk_gpio_v2. + */ + compatible = "simple-bus"; + ranges = <0x0 0x600 0x100>; + #size-cells = <1>; - gpio1: bank@1 { - reg = <0x0 0x100>; - interrupts = <6>; - }; + gpio0: bank@0 { + reg = <0x0 0x100>; + interrupts = <6>; + }; - gpio2: bank@2 { - reg = <0x0 0x100>; - interrupts = <6>; - }; + gpio1: bank@1 { + reg = <0x0 0x100>; + interrupts = <6>; }; - }; - /* Specify the clocks node for the usbphy */ - usbphy: usbphy@10120000 { - clocks = <&clkctrl 22 &clkctrl 25>; + gpio2: bank@2 { + reg = <0x0 0x100>; + interrupts = <6>; + }; }; +}; - pcie@10140000 { +&pcie { /* * Our driver is different that OpenWRT's, so we need slightly * different values for the reg property */ reg = <0x10140000 0x10000>; - - /* - * Also, we need resets and clocks defined, so we can properly - * initialize the PCIe - */ - resets = <&rstctrl 26>, <&rstctrl 27>; - clocks = <&clkctrl 26>, <&clkctrl 27>; - }; + compatible = "mediatek,mt7628-pci"; }; diff --git a/sys/boot/fdt/dts/mips/fbsd-rt2880.dtsi b/sys/boot/fdt/dts/mips/fbsd-rt2880.dtsi deleted file mode 100644 index 264f504..0000000 --- a/sys/boot/fdt/dts/mips/fbsd-rt2880.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -/* $FreeBSD$ */ - -/ { - /* Specify alias for serial0 so we have a working console */ - aliases { - serial0 = "/palmbus@300000/uartlite@c00"; - }; - - /* - * OpenWRT doesn't define a clock controller, but we currently need one - */ - clkctrl: cltctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; -}; diff --git a/sys/boot/fdt/dts/mips/fbsd-rt3050.dtsi b/sys/boot/fdt/dts/mips/fbsd-rt3050.dtsi deleted file mode 100644 index 52e1921..0000000 --- a/sys/boot/fdt/dts/mips/fbsd-rt3050.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -/* $FreeBSD$ */ - -/ { - /* Specify alias for serial0 so we have a working console */ - aliases { - serial0 = "/palmbus@10000000/uartlite@c00"; - }; - - /* - * OpenWRT doesn't define a clock controller, but we currently need one - */ - clkctrl: cltctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - /* Specify the USB PHY */ - usbphy: usbphy { - compatible = "ralink,rt3050-usbphy"; - resets = <&rstctrl 22>; - clocks = <&clkctrl 18>; - }; -}; diff --git a/sys/boot/fdt/dts/mips/fbsd-rt3352.dtsi b/sys/boot/fdt/dts/mips/fbsd-rt3352.dtsi deleted file mode 100644 index 380ec6d..0000000 --- a/sys/boot/fdt/dts/mips/fbsd-rt3352.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -/* $FreeBSD$ */ - -/ { - /* Specify alias for serial0 so we have a working console */ - aliases { - serial0 = "/palmbus@10000000/uartlite@c00"; - }; - - /* - * OpenWRT doesn't define a clock controller, but we currently need one - */ - clkctrl: cltctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - /* Specify the clocks node for the usbphy */ - usbphy { - clocks = <&clkctrl 18 &clkctrl 20>; - }; -}; diff --git a/sys/boot/fdt/dts/mips/fbsd-rt3883.dtsi b/sys/boot/fdt/dts/mips/fbsd-rt3883.dtsi index d2447b9..f71c29e 100644 --- a/sys/boot/fdt/dts/mips/fbsd-rt3883.dtsi +++ b/sys/boot/fdt/dts/mips/fbsd-rt3883.dtsi @@ -1,37 +1,16 @@ /* $FreeBSD$ */ -/ { - /* Specify alias for serial0 so we have a working console */ - aliases { - serial0 = "/palmbus@10000000/uartlite@c00"; - }; +&pci { + #address-cells = <3>; + #size-cells = <2>; + ranges = < + 0x02000000 0 0x00000000 0x20000000 0 0x10000000 + 0x01000000 0 0x00000000 0x10160000 0 0x00010000 + >; - /* - * OpenWRT doesn't define a clock controller, but we currently need one - */ - clkctrl: cltctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; + interrupt-parent = <&cpuintc>; + interrupts = <4>; - /* Specify the clocks node for the usbphy */ - usbphy: usbphy { - clocks = <&clkctrl 22 &clkctrl 25>; - clock-names = "host", "device"; - }; - - pci@10140000 { - #address-cells = <3>; - #size-cells = <2>; - ranges = < - 0x02000000 0 0x00000000 0x20000000 0 0x10000000 - 0x01000000 0 0x00000000 0x10160000 0 0x00010000 - >; - - interrupt-parent = <&cpuintc>; - interrupts = <4>; - - resets = <&rstctrl 23>; - clocks = <&clkctrl 21>; - }; + resets = <&rstctrl 23>; + clocks = <&clkctrl 21>; }; diff --git a/sys/boot/fdt/dts/mips/fbsd-rt5350.dtsi b/sys/boot/fdt/dts/mips/fbsd-rt5350.dtsi deleted file mode 100644 index 4b6290e..0000000 --- a/sys/boot/fdt/dts/mips/fbsd-rt5350.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -/* $FreeBSD$ */ - -/ { - /* Specify alias for serial0 so we have a working console */ - aliases { - serial0 = "/palmbus@10000000/uartlite@c00"; - }; - - /* - * OpenWRT doesn't define a clock controller, but we currently need one - */ - clkctrl: cltctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - /* Specify the clocks node for the USB PHY */ - usbphy { - clocks = <&clkctrl 18>; - }; -}; diff --git a/sys/boot/fdt/fdt_loader_cmd.c b/sys/boot/fdt/fdt_loader_cmd.c index 1ad9a23..5755851 100644 --- a/sys/boot/fdt/fdt_loader_cmd.c +++ b/sys/boot/fdt/fdt_loader_cmd.c @@ -970,40 +970,52 @@ fdt_cmd_hdr(int argc __unused, char *argv[] __unused) ver = fdt_version(fdtp); pager_open(); sprintf(line, "\nFlattened device tree header (%p):\n", fdtp); - pager_output(line); + if (pager_output(line)) + goto out; sprintf(line, " magic = 0x%08x\n", fdt_magic(fdtp)); - pager_output(line); + if (pager_output(line)) + goto out; sprintf(line, " size = %d\n", fdt_totalsize(fdtp)); - pager_output(line); + if (pager_output(line)) + goto out; sprintf(line, " off_dt_struct = 0x%08x\n", fdt_off_dt_struct(fdtp)); - pager_output(line); + if (pager_output(line)) + goto out; sprintf(line, " off_dt_strings = 0x%08x\n", fdt_off_dt_strings(fdtp)); - pager_output(line); + if (pager_output(line)) + goto out; sprintf(line, " off_mem_rsvmap = 0x%08x\n", fdt_off_mem_rsvmap(fdtp)); - pager_output(line); + if (pager_output(line)) + goto out; sprintf(line, " version = %d\n", ver); - pager_output(line); + if (pager_output(line)) + goto out; sprintf(line, " last compatible version = %d\n", fdt_last_comp_version(fdtp)); - pager_output(line); + if (pager_output(line)) + goto out; if (ver >= 2) { sprintf(line, " boot_cpuid = %d\n", fdt_boot_cpuid_phys(fdtp)); - pager_output(line); + if (pager_output(line)) + goto out; } if (ver >= 3) { sprintf(line, " size_dt_strings = %d\n", fdt_size_dt_strings(fdtp)); - pager_output(line); + if (pager_output(line)) + goto out; } if (ver >= 17) { sprintf(line, " size_dt_struct = %d\n", fdt_size_dt_struct(fdtp)); - pager_output(line); + if (pager_output(line)) + goto out; } +out: pager_close(); return (CMD_OK); @@ -1678,15 +1690,18 @@ fdt_cmd_mres(int argc, char *argv[]) pager_open(); total = fdt_num_mem_rsv(fdtp); if (total > 0) { - pager_output("Reserved memory regions:\n"); + if (pager_output("Reserved memory regions:\n")) + goto out; for (i = 0; i < total; i++) { fdt_get_mem_rsv(fdtp, i, &start, &size); sprintf(line, "reg#%d: (start: 0x%jx, size: 0x%jx)\n", i, start, size); - pager_output(line); + if (pager_output(line)) + goto out; } } else pager_output("No reserved memory regions\n"); +out: pager_close(); return (CMD_OK); diff --git a/sys/boot/ficl/efi.c b/sys/boot/ficl/efi.c new file mode 100644 index 0000000..8a08f70 --- /dev/null +++ b/sys/boot/ficl/efi.c @@ -0,0 +1,207 @@ +/*- + * Copyright (c) 2014 Netflix, Inc + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/******************************************************************* +** e f i . c +** Additional words for EFI +** +*******************************************************************/ + +#ifdef TESTMAIN +#include <sys/types.h> +#include <sys/stat.h> +#include <dirent.h> +#include <fcntl.h> +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#else +#include <stand.h> +#endif +#include "bootstrap.h" +#include <string.h> +#include "ficl.h" + +/* + * FreeBSD's loader interaction words and extras + * + * efi-setenv ( value n name n guid n attr -- 0 | -1) + * efi-getenv ( guid n addr n -- addr' n' | -1 ) + * efi-unsetenv ( name n guid n'' -- ) + */ + +/* + * efi-setenv + * efi-setenv ( value n name n guid n attr -- 0 | -1) + * + * Set environment variables using the SetVariable EFI runtime service. + * + * Value and guid are passed through in binary form (so guid needs to be + * converted to binary form from its string form). Name is converted from + * ASCII to CHAR16. Since ficl doesn't have support for internationalization, + * there's no native CHAR16 interface provided. + * + * attr is an int in the bitmask of the following attributes for this variable. + * + * 1 Non volatile + * 2 Boot service access + * 4 Run time access + * (corresponding to the same bits in the UEFI spec). + */ +void +ficlEfiSetenv(FICL_VM *pVM) +{ +#ifndef TESTMAIN + char *value, *guid; + CHAR16 *name + int i; +#endif + char *namep, *valuep, *guidp; + int names, values, guids, attr; + +#if FICL_ROBUST > 1 + vmCheckStack(pVM, 6, 0); +#endif + attr = stackPopINT(pVM->pStack); + guids = stackPopINT(pVM->pStack); + guidp = (char*)stackPopPtr(pVM->pStack); + names = stackPopINT(pVM->pStack); + namep = (char*)stackPopPtr(pVM->pStack); + values = stackPopINT(pVM->pStack); + valuep = (char*)stackPopPtr(pVM->pStack); + +#ifndef TESTMAIN + guid = (char*)ficlMalloc(guids); + if (guid != NULL) + vmThrowErr(pVM, "Error: out of memory"); + memcpy(guid, guidp, guids); + + name = (char*)ficlMalloc((names + 1) * sizeof(CHAR16)); + if (name == NULL) + vmThrowErr(pVM, "Error: out of memory"); + for (i = 0; i < names; i++) + name[i] = namep[i]; + name[names] = (CHAR16)0; + + value = (char*)ficlMalloc(values + 1); + if (value != NULL) + vmThrowErr(pVM, "Error: out of memory"); + memcpy(value, valuep, values); + + status = efi_set_variable(name, guid, attr, value); + if (status == EFI_SUCCESS) + stackPushINT(pVM->pStack, 0); + else + stackPushINT(pVM->pStack, -1); + + ficlFree(name); + ficlFree(value); + ficlFree(guid); +#endif + + return; +} + +void +ficlEfiGetenv(FICL_VM *pVM) +{ +#ifndef TESTMAIN + char *name, *value; +#endif + char *namep; + int names; + +#if FICL_ROBUST > 1 + vmCheckStack(pVM, 2, 2); +#endif + names = stackPopINT(pVM->pStack); + namep = (char*) stackPopPtr(pVM->pStack); + +#ifndef TESTMAIN + name = (char*) ficlMalloc(names+1); + if (!name) + vmThrowErr(pVM, "Error: out of memory"); + strncpy(name, namep, names); + name[names] = '\0'; + + value = getenv(name); + ficlFree(name); + + if(value != NULL) { + stackPushPtr(pVM->pStack, value); + stackPushINT(pVM->pStack, strlen(value)); + } else +#endif + stackPushINT(pVM->pStack, -1); + + return; +} + +void +ficlEfiUnsetenv(FICL_VM *pVM) +{ +#ifndef TESTMAIN + char *name; +#endif + char *namep; + int names; + +#if FICL_ROBUST > 1 + vmCheckStack(pVM, 2, 0); +#endif + names = stackPopINT(pVM->pStack); + namep = (char*) stackPopPtr(pVM->pStack); + +#ifndef TESTMAIN + name = (char*) ficlMalloc(names+1); + if (!name) + vmThrowErr(pVM, "Error: out of memory"); + strncpy(name, namep, names); + name[names] = '\0'; + + unsetenv(name); + ficlFree(name); +#endif + + return; +} +/************************************************************************** + +** Build FreeBSD platform extensions into the system dictionary +**************************************************************************/ +void ficlEfiCompilePlatform(FICL_SYSTEM *pSys) +{ + FICL_DICT *dp = pSys->dp; + assert (dp); + + dictAppendWord(dp, "efi-setenv", ficlEfiSetenv, FW_DEFAULT); + dictAppendWord(dp, "efi-getenv", ficlEfiGetenv, FW_DEFAULT); + dictAppendWord(dp, "efi-unsetenv", ficlEfiUnsetenv, FW_DEFAULT); + + return; +} diff --git a/sys/boot/ficl/loader.c b/sys/boot/ficl/loader.c index 6641438..04e555c 100644 --- a/sys/boot/ficl/loader.c +++ b/sys/boot/ficl/loader.c @@ -45,6 +45,7 @@ #endif #include "bootstrap.h" #include <string.h> +#include <uuid.h> #include "ficl.h" /* FreeBSD's loader interaction words and extras @@ -59,6 +60,8 @@ * pnpdevices ( -- addr ) * pnphandlers ( -- addr ) * ccall ( [[...[p10] p9] ... p1] n addr -- result ) + * uuid-from-string ( addr n -- addr' ) + * uuid-to-string ( addr' -- addr n ) * .# ( value -- ) */ @@ -350,6 +353,75 @@ ficlCcall(FICL_VM *pVM) return; } +void +ficlUuidFromString(FICL_VM *pVM) +{ +#ifndef TESTMAIN + char *uuid; + uint32_t status; +#endif + char *uuidp; + int uuids; + uuid_t *u; + +#if FICL_ROBUST > 1 + vmCheckStack(pVM, 2, 0); +#endif + + uuids = stackPopINT(pVM->pStack); + uuidp = (char *) stackPopPtr(pVM->pStack); + +#ifndef TESTMAIN + uuid = (char *)ficlMalloc(uuids + 1); + if (!uuid) + vmThrowErr(pVM, "Error: out of memory"); + strncpy(uuid, uuidp, uuids); + uuid[uuids] = '\0'; + + u = (uuid_t *)ficlMalloc(sizeof (*u)); + + uuid_from_string(uuid, u, &status); + ficlFree(uuid); + if (status != uuid_s_ok) { + ficlFree(u); + u = NULL; + } +#else + u = NULL; +#endif + stackPushPtr(pVM->pStack, u); + + + return; +} + +void +ficlUuidToString(FICL_VM *pVM) +{ +#ifndef TESTMAIN + char *uuid; + uint32_t status; +#endif + uuid_t *u; + +#if FICL_ROBUST > 1 + vmCheckStack(pVM, 1, 0); +#endif + + u = (uuid_t *)stackPopPtr(pVM->pStack); + +#ifndef TESTMAIN + uuid_to_string(u, &uuid, &status); + if (status != uuid_s_ok) { + stackPushPtr(pVM->pStack, uuid); + stackPushINT(pVM->pStack, strlen(uuid)); + } else +#endif + stackPushINT(pVM->pStack, -1); + + return; +} + /************************************************************************** f i c l E x e c F D ** reads in text from file fd and passes it to ficlExec() @@ -920,6 +992,8 @@ void ficlCompilePlatform(FICL_SYSTEM *pSys) dictAppendWord(dp, "copyout", ficlCopyout, FW_DEFAULT); dictAppendWord(dp, "findfile", ficlFindfile, FW_DEFAULT); dictAppendWord(dp, "ccall", ficlCcall, FW_DEFAULT); + dictAppendWord(dp, "uuid-from-string", ficlUuidFromString, FW_DEFAULT); + dictAppendWord(dp, "uuid-to-string", ficlUuidToString, FW_DEFAULT); #ifndef TESTMAIN #ifdef __i386__ dictAppendWord(dp, "outb", ficlOutb, FW_DEFAULT); diff --git a/sys/boot/ficl/words.c b/sys/boot/ficl/words.c index 0e8f2c4..eee6fe9 100644 --- a/sys/boot/ficl/words.c +++ b/sys/boot/ficl/words.c @@ -5198,12 +5198,11 @@ void ficlCompileCore(FICL_SYSTEM *pSys) /* ** Set up system's outer interpreter loop - maybe this should be in initSystem? */ - pSys->pInterp[0] = pSys->pInterpret; - pSys->pInterp[1] = pSys->pBranchParen; - pSys->pInterp[2] = (FICL_WORD *)(void *)(-2); + pSys->pInterp[0] = pSys->pInterpret; + pSys->pInterp[1] = pSys->pBranchParen; + pSys->pInterp[2] = (FICL_WORD *)(void *)(-2); assert(dictCellsAvail(dp) > 0); return; } - diff --git a/sys/boot/forth/loader.4th b/sys/boot/forth/loader.4th index 8df8cbb..a18fa1e 100644 --- a/sys/boot/forth/loader.4th +++ b/sys/boot/forth/loader.4th @@ -230,6 +230,13 @@ only forth definitions also support-functions : .? 2 spaces 2swap 15 #type 2 spaces type cr ; +\ Execute the ? command to print all the commands defined in +\ C, then list the ones we support here. Please note that this +\ doesn't use pager_* routines that the C implementation of ? +\ does, so these will always appear, even if you stop early +\ there. And they may cause the commands to scroll off the +\ screen if the number of commands modulus LINES is close +\ to LINEs.... : ? ['] ? execute s" boot-conf" s" load kernel and modules, then autoboot" .? diff --git a/sys/boot/forth/loader.conf b/sys/boot/forth/loader.conf index a56666c..69a4fcd 100644 --- a/sys/boot/forth/loader.conf +++ b/sys/boot/forth/loader.conf @@ -215,7 +215,6 @@ nfsclient_load="NO" # NFS client nfsserver_load="NO" # NFS server nullfs_load="NO" # Null filesystem procfs_load="NO" # Process filesystem -reiserfs_load="NO" # ReiserFS unionfs_load="NO" # Union filesystem zfs_load="NO" # ZFS diff --git a/sys/boot/i386/libi386/bioscd.c b/sys/boot/i386/libi386/bioscd.c index 6d1d1e1..1ea6906 100644 --- a/sys/boot/i386/libi386/bioscd.c +++ b/sys/boot/i386/libi386/bioscd.c @@ -183,11 +183,14 @@ bc_print(int verbose) char line[80]; int i; + pager_open(); for (i = 0; i < nbcinfo; i++) { sprintf(line, " cd%d: Device 0x%x\n", i, bcinfo[i].bc_sp.sp_devicespec); - pager_output(line); + if (pager_output(line)) + break; } + pager_close(); } /* diff --git a/sys/boot/i386/libi386/biosdisk.c b/sys/boot/i386/libi386/biosdisk.c index e5b7835..9032fe1 100644 --- a/sys/boot/i386/libi386/biosdisk.c +++ b/sys/boot/i386/libi386/biosdisk.c @@ -313,11 +313,13 @@ bd_print(int verbose) struct disk_devdesc dev; int i; + pager_open(); for (i = 0; i < nbdinfo; i++) { sprintf(line, " disk%d: BIOS drive %c:\n", i, (bdinfo[i].bd_unit < 0x80) ? ('A' + bdinfo[i].bd_unit): ('C' + bdinfo[i].bd_unit - 0x80)); - pager_output(line); + if (pager_output(line)) + break; dev.d_dev = &biosdisk; dev.d_unit = i; dev.d_slice = -1; @@ -332,6 +334,7 @@ bd_print(int verbose) disk_close(&dev); } } + pager_close(); } /* diff --git a/sys/boot/i386/zfsboot/zfsboot.c b/sys/boot/i386/zfsboot/zfsboot.c index e190b49..e0cc740 100644 --- a/sys/boot/i386/zfsboot/zfsboot.c +++ b/sys/boot/i386/zfsboot/zfsboot.c @@ -397,10 +397,12 @@ probe_drive(struct dsk *dsk) struct gpt_hdr hdr; struct gpt_ent *ent; unsigned part, entries_per_sec; + daddr_t slba; #endif -#ifdef LOADER_GELI_SUPPORT - daddr_t slba, elba; +#if defined(GPT) || defined(LOADER_GELI_SUPPORT) + daddr_t elba; #endif + struct dos_partition *dp; char *sec; unsigned i; diff --git a/sys/boot/pc98/libpc98/bioscd.c b/sys/boot/pc98/libpc98/bioscd.c index d1d1ca1..15758cc 100644 --- a/sys/boot/pc98/libpc98/bioscd.c +++ b/sys/boot/pc98/libpc98/bioscd.c @@ -179,11 +179,14 @@ bc_print(int verbose) char line[80]; int i; + pager_open(); for (i = 0; i < nbcinfo; i++) { sprintf(line, " cd%d: Device 0x%x\n", i, bcinfo[i].bc_sp.sp_devicespec); - pager_output(line); + if (pager_output(line)) + break; } + pager_close(); } /* diff --git a/sys/boot/pc98/libpc98/biosdisk.c b/sys/boot/pc98/libpc98/biosdisk.c index be364c6..0ceeb7b 100644 --- a/sys/boot/pc98/libpc98/biosdisk.c +++ b/sys/boot/pc98/libpc98/biosdisk.c @@ -111,9 +111,9 @@ static int bd_write(struct open_disk *od, daddr_t dblk, int blks, static int bd_int13probe(struct bdinfo *bd); -static void bd_printslice(struct open_disk *od, struct pc98_partition *dp, +static int bd_printslice(struct open_disk *od, struct pc98_partition *dp, char *prefix, int verbose); -static void bd_printbsdslice(struct open_disk *od, daddr_t offset, +static int bd_printbsdslice(struct open_disk *od, daddr_t offset, char *prefix, int verbose); static int bd_init(void); @@ -252,15 +252,18 @@ bd_int13probe(struct bdinfo *bd) static void bd_print(int verbose) { - int i, j; + int i, j, done; char line[80]; struct i386_devdesc dev; struct open_disk *od; struct pc98_partition *dptr; - for (i = 0; i < nbdinfo; i++) { + pager_open(); + done = 0; + for (i = 0; i < nbdinfo && !done; i++) { sprintf(line, " disk%d: BIOS drive %c:\n", i, 'A' + i); - pager_output(line); + if (pager_output(line)) + break; /* try to open the whole disk */ dev.d_unit = i; @@ -276,12 +279,16 @@ bd_print(int verbose) /* Check for a "dedicated" disk */ for (j = 0; j < od->od_nslices; j++) { sprintf(line, " disk%ds%d", i, j + 1); - bd_printslice(od, &dptr[j], line, verbose); + if (bd_printslice(od, &dptr[j], line, verbose)) { + done = 1; + break; + } } } bd_closedisk(od); } } + pager_close(); } /* Given a size in 512 byte sectors, convert it to a human-readable number. */ @@ -311,7 +318,7 @@ display_size(uint64_t size) * Print information about slices on a disk. For the size calculations we * assume a 512 byte sector. */ -static void +static int bd_printslice(struct open_disk *od, struct pc98_partition *dp, char *prefix, int verbose) { @@ -331,10 +338,9 @@ bd_printslice(struct open_disk *od, struct pc98_partition *dp, char *prefix, switch(dp->dp_mid & PC98_MID_MASK) { case PC98_MID_386BSD: - bd_printbsdslice(od, start, prefix, verbose); - return; + return (bd_printbsdslice(od, start, prefix, verbose)); case 0x00: /* unused partition */ - return; + return (0); case 0x01: sprintf(line, "%s: FAT-12%s\n", prefix, stats); break; @@ -350,14 +356,14 @@ bd_printslice(struct open_disk *od, struct pc98_partition *dp, char *prefix, sprintf(line, "%s: Unknown fs: 0x%x %s\n", prefix, dp->dp_mid, stats); } - pager_output(line); + return (pager_output(line)); } /* * Print out each valid partition in the disklabel of a FreeBSD slice. * For size calculations, we assume a 512 byte sector size. */ -static void +static int bd_printbsdslice(struct open_disk *od, daddr_t offset, char *prefix, int verbose) { @@ -368,12 +374,11 @@ bd_printbsdslice(struct open_disk *od, daddr_t offset, char *prefix, /* read disklabel */ if (bd_read(od, offset + LABELSECTOR, 1, buf)) - return; + return (0); lp =(struct disklabel *)(&buf[0]); if (lp->d_magic != DISKMAGIC) { sprintf(line, "%s: FFS bad disklabel\n", prefix); - pager_output(line); - return; + return (pager_output(line)); } /* Print partitions */ @@ -404,9 +409,11 @@ bd_printbsdslice(struct open_disk *od, daddr_t offset, char *prefix, (lp->d_partitions[i].p_fstype == FS_SWAP) ? "swap" : (lp->d_partitions[i].p_fstype == FS_VINUM) ? "vinum" : "FFS"); - pager_output(line); + if (pager_output(line)) + return (1); } } + return (0); } diff --git a/sys/boot/uboot/lib/disk.c b/sys/boot/uboot/lib/disk.c index 018dfed..741b1f8 100644 --- a/sys/boot/uboot/lib/disk.c +++ b/sys/boot/uboot/lib/disk.c @@ -245,6 +245,7 @@ stor_print(int verbose) static char line[80]; int i; + pager_open(); for (i = 0; i < stor_info_no; i++) { dev.d_dev = &uboot_storage; dev.d_unit = i; @@ -252,13 +253,15 @@ stor_print(int verbose) dev.d_partition = -1; sprintf(line, "\tdisk%d (%s)\n", i, ub_stor_type(SI(&dev).type)); - pager_output(line); + if (pager_output(line)) + break; if (stor_opendev(&dev) == 0) { sprintf(line, "\tdisk%d", i); disk_print(&dev, line, verbose); disk_close(&dev); } } + pager_close(); } static int diff --git a/sys/boot/zfs/zfs.c b/sys/boot/zfs/zfs.c index f5aee2e..700da78 100644 --- a/sys/boot/zfs/zfs.c +++ b/sys/boot/zfs/zfs.c @@ -438,7 +438,7 @@ zfs_probe(int fd, uint64_t *pool_guid) return (ret); } -static void +static int zfs_probe_partition(void *arg, const char *partname, const struct ptable_entry *part) { @@ -450,7 +450,7 @@ zfs_probe_partition(void *arg, const char *partname, /* Probe only freebsd-zfs and freebsd partitions */ if (part->type != PART_FREEBSD && part->type != PART_FREEBSD_ZFS) - return; + return 0; ppa = (struct zfs_probe_args *)arg; strncpy(devname, ppa->devname, strlen(ppa->devname) - 1); @@ -458,10 +458,10 @@ zfs_probe_partition(void *arg, const char *partname, sprintf(devname, "%s%s:", devname, partname); pa.fd = open(devname, O_RDONLY); if (pa.fd == -1) - return; + return 0; ret = zfs_probe(pa.fd, ppa->pool_guid); if (ret == 0) - return; + return 0; /* Do we have BSD label here? */ if (part->type == PART_FREEBSD) { pa.devname = devname; @@ -470,11 +470,12 @@ zfs_probe_partition(void *arg, const char *partname, table = ptable_open(&pa, part->end - part->start + 1, ppa->secsz, zfs_diskread); if (table != NULL) { - ptable_iterate(table, &pa, zfs_probe_partition); + ret = ptable_iterate(table, &pa, zfs_probe_partition); ptable_close(table); } } close(pa.fd); + return (ret); } int @@ -893,4 +894,4 @@ zfs_set_env(void) } return (rv); -}
\ No newline at end of file +} diff --git a/sys/cam/cam_periph.c b/sys/cam/cam_periph.c index 8f780fd..0415643 100644 --- a/sys/cam/cam_periph.c +++ b/sys/cam/cam_periph.c @@ -844,7 +844,7 @@ cam_periph_mapmem(union ccb *ccb, struct cam_periph_map_info *mapinfo, } /* - * This keeps the the kernel stack of current thread from getting + * This keeps the kernel stack of current thread from getting * swapped. In low-memory situations where the kernel stack might * otherwise get swapped out, this holds it and allows the thread * to make progress and release the kernel mapped pages sooner. diff --git a/sys/cam/ctl/ctl_frontend_iscsi.c b/sys/cam/ctl/ctl_frontend_iscsi.c index abf8441..d627eea 100644 --- a/sys/cam/ctl/ctl_frontend_iscsi.c +++ b/sys/cam/ctl/ctl_frontend_iscsi.c @@ -49,6 +49,7 @@ __FBSDID("$FreeBSD$"); #include <sys/mutex.h> #include <sys/queue.h> #include <sys/sbuf.h> +#include <sys/socket.h> #include <sys/sysctl.h> #include <sys/systm.h> #include <sys/uio.h> diff --git a/sys/cddl/compat/opensolaris/kern/opensolaris_lookup.c b/sys/cddl/compat/opensolaris/kern/opensolaris_lookup.c index 848007e..4214ca8 100644 --- a/sys/cddl/compat/opensolaris/kern/opensolaris_lookup.c +++ b/sys/cddl/compat/opensolaris/kern/opensolaris_lookup.c @@ -89,13 +89,14 @@ traverse(vnode_t **cvpp, int lktype) if (vfsp == NULL) break; error = vfs_busy(vfsp, 0); + /* * tvp is NULL for *cvpp vnode, which we can't unlock. - * At least some callers expect the reference to be - * maintained to the original *cvpp */ if (tvp != NULL) vput(cvp); + else + vrele(cvp); if (error) return (error); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/gfs.c b/sys/cddl/contrib/opensolaris/uts/common/fs/gfs.c index c5c5c00..27d259d 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/gfs.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/gfs.c @@ -442,19 +442,9 @@ gfs_lookup_dot(vnode_t **vpp, vnode_t *dvp, vnode_t *pvp, const char *nm) *vpp = dvp; return (0); } else if (strcmp(nm, "..") == 0) { - if (pvp == NULL) { - ASSERT(dvp->v_flag & VROOT); - VN_HOLD(dvp); - *vpp = dvp; - ASSERT_VOP_ELOCKED(dvp, "gfs_lookup_dot: non-locked dvp"); - } else { - ltype = VOP_ISLOCKED(dvp); - VOP_UNLOCK(dvp, 0); - VN_HOLD(pvp); - *vpp = pvp; - vn_lock(*vpp, LK_EXCLUSIVE | LK_RETRY); - vn_lock(dvp, ltype | LK_RETRY); - } + ASSERT(pvp != NULL); + VN_HOLD(pvp); + *vpp = pvp; return (0); } diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ctldir.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ctldir.h index 1945686..8849003 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ctldir.h +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ctldir.h @@ -61,7 +61,6 @@ int zfsctl_lookup_objset(vfs_t *vfsp, uint64_t objsetid, zfsvfs_t **zfsvfsp); #define ZFSCTL_INO_ROOT 0x1 #define ZFSCTL_INO_SNAPDIR 0x2 -#define ZFSCTL_INO_SHARES 0x3 #ifdef __cplusplus } diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_geom.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_geom.c index 4f5b2a8..4ab5896 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_geom.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_geom.c @@ -325,52 +325,82 @@ nvlist_get_guids(nvlist_t *list, uint64_t *pguid, uint64_t *vguid) (void) nvlist_lookup_uint64(list, ZPOOL_CONFIG_POOL_GUID, pguid); } -static int -vdev_geom_io(struct g_consumer *cp, int cmd, void *data, off_t offset, off_t size) +/* + * Issue one or more bios to the vdev in parallel + * cmds, datas, offsets, errors, and sizes are arrays of length ncmds. Each IO + * operation is described by parallel entries from each array. There may be + * more bios actually issued than entries in the array + */ +static void +vdev_geom_io(struct g_consumer *cp, int *cmds, void **datas, off_t *offsets, + off_t *sizes, int *errors, int ncmds) { - struct bio *bp; + struct bio **bios; u_char *p; - off_t off, maxio; - int error; + off_t off, maxio, s, end; + int i, n_bios, j; + size_t bios_size; - ASSERT((offset % cp->provider->sectorsize) == 0); - ASSERT((size % cp->provider->sectorsize) == 0); - - bp = g_alloc_bio(); - off = offset; - offset += size; - p = data; maxio = MAXPHYS - (MAXPHYS % cp->provider->sectorsize); - error = 0; - - for (; off < offset; off += maxio, p += maxio, size -= maxio) { - g_reset_bio(bp); - bp->bio_cmd = cmd; - bp->bio_done = NULL; - bp->bio_offset = off; - bp->bio_length = MIN(size, maxio); - bp->bio_data = p; - g_io_request(bp, cp); - error = biowait(bp, "vdev_geom_io"); - if (error != 0) - break; + n_bios = 0; + + /* How many bios are required for all commands ? */ + for (i = 0; i < ncmds; i++) + n_bios += (sizes[i] + maxio - 1) / maxio; + + /* Allocate memory for the bios */ + bios_size = n_bios * sizeof(struct bio*); + bios = kmem_zalloc(bios_size, KM_SLEEP); + + /* Prepare and issue all of the bios */ + for (i = j = 0; i < ncmds; i++) { + off = offsets[i]; + p = datas[i]; + s = sizes[i]; + end = off + s; + ASSERT((off % cp->provider->sectorsize) == 0); + ASSERT((s % cp->provider->sectorsize) == 0); + + for (; off < end; off += maxio, p += maxio, s -= maxio, j++) { + bios[j] = g_alloc_bio(); + bios[j]->bio_cmd = cmds[i]; + bios[j]->bio_done = NULL; + bios[j]->bio_offset = off; + bios[j]->bio_length = MIN(s, maxio); + bios[j]->bio_data = p; + g_io_request(bios[j], cp); + } } + ASSERT(j == n_bios); - g_destroy_bio(bp); - return (error); + /* Wait for all of the bios to complete, and clean them up */ + for (i = j = 0; i < ncmds; i++) { + off = offsets[i]; + s = sizes[i]; + end = off + s; + + for (; off < end; off += maxio, s -= maxio, j++) { + errors[i] = biowait(bios[j], "vdev_geom_io") || errors[i]; + g_destroy_bio(bios[j]); + } + } + kmem_free(bios, bios_size); } static int vdev_geom_read_config(struct g_consumer *cp, nvlist_t **config) { struct g_provider *pp; - vdev_label_t *label; + vdev_phys_t *vdev_lists[VDEV_LABELS]; char *p, *buf; size_t buflen; - uint64_t psize; - off_t offset, size; - uint64_t state, txg; - int error, l, len; + uint64_t psize, state, txg; + off_t offsets[VDEV_LABELS]; + off_t size; + off_t sizes[VDEV_LABELS]; + int cmds[VDEV_LABELS]; + int errors[VDEV_LABELS]; + int l, len; g_topology_assert_not(); @@ -380,22 +410,32 @@ vdev_geom_read_config(struct g_consumer *cp, nvlist_t **config) psize = pp->mediasize; psize = P2ALIGN(psize, (uint64_t)sizeof(vdev_label_t)); - size = sizeof(*label) + pp->sectorsize - - ((sizeof(*label) - 1) % pp->sectorsize) - 1; + size = sizeof(*vdev_lists[0]) + pp->sectorsize - + ((sizeof(*vdev_lists[0]) - 1) % pp->sectorsize) - 1; - label = kmem_alloc(size, KM_SLEEP); - buflen = sizeof(label->vl_vdev_phys.vp_nvlist); + buflen = sizeof(vdev_lists[0]->vp_nvlist); *config = NULL; + /* Create all of the IO requests */ for (l = 0; l < VDEV_LABELS; l++) { + cmds[l] = BIO_READ; + vdev_lists[l] = kmem_alloc(size, KM_SLEEP); + offsets[l] = vdev_label_offset(psize, l, 0) + VDEV_SKIP_SIZE; + sizes[l] = size; + errors[l] = 0; + ASSERT(offsets[l] % pp->sectorsize == 0); + } - offset = vdev_label_offset(psize, l, 0); - if ((offset % pp->sectorsize) != 0) - continue; + /* Issue the IO requests */ + vdev_geom_io(cp, cmds, (void**)vdev_lists, offsets, sizes, errors, + VDEV_LABELS); - if (vdev_geom_io(cp, BIO_READ, label, offset, size) != 0) + /* Parse the labels */ + for (l = 0; l < VDEV_LABELS; l++) { + if (errors[l] != 0) continue; - buf = label->vl_vdev_phys.vp_nvlist; + + buf = vdev_lists[l]->vp_nvlist; if (nvlist_unpack(buf, buflen, config, 0) != 0) continue; @@ -407,7 +447,8 @@ vdev_geom_read_config(struct g_consumer *cp, nvlist_t **config) continue; } - if (state != POOL_STATE_SPARE && state != POOL_STATE_L2CACHE && + if (state != POOL_STATE_SPARE && + state != POOL_STATE_L2CACHE && (nvlist_lookup_uint64(*config, ZPOOL_CONFIG_POOL_TXG, &txg) != 0 || txg == 0)) { nvlist_free(*config); @@ -418,7 +459,10 @@ vdev_geom_read_config(struct g_consumer *cp, nvlist_t **config) break; } - kmem_free(label, size); + /* Free the label storage */ + for (l = 0; l < VDEV_LABELS; l++) + kmem_free(vdev_lists[l], size); + return (*config == NULL ? ENOENT : 0); } diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c index 88c2e27..2052c76 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c @@ -223,7 +223,7 @@ zfsctl_root_inode_cb(vnode_t *vp, int index) { zfsvfs_t *zfsvfs = vp->v_vfsp->vfs_data; - ASSERT(index <= 2); + ASSERT(index < 2); if (index == 0) return (ZFSCTL_INO_SNAPDIR); @@ -294,6 +294,22 @@ zfsctl_root(znode_t *zp) return (zp->z_zfsvfs->z_ctldir); } +static int +zfsctl_common_print(ap) + struct vop_print_args /* { + struct vnode *a_vp; + } */ *ap; +{ + vnode_t *vp = ap->a_vp; + gfs_file_t *fp = vp->v_data; + + printf(" parent = %p\n", fp->gfs_parent); + printf(" type = %d\n", fp->gfs_type); + printf(" index = %d\n", fp->gfs_index); + printf(" ino = %ju\n", (uintmax_t)fp->gfs_ino); + return (0); +} + /* * Common open routine. Disallow any write access. */ @@ -404,8 +420,6 @@ zfsctl_common_fid(ap) ZFS_EXIT(zfsvfs); return (SET_ERROR(ENOSPC)); } -#else - fidp->fid_len = SHORT_FID_LEN; #endif zfid = (zfid_short_t *)fidp; @@ -454,25 +468,6 @@ zfsctl_shares_fid(ap) return (error); } -static int -zfsctl_common_reclaim(ap) - struct vop_reclaim_args /* { - struct vnode *a_vp; - struct thread *a_td; - } */ *ap; -{ - vnode_t *vp = ap->a_vp; - - /* - * Destroy the vm object and flush associated pages. - */ - vnode_destroy_vobject(vp); - VI_LOCK(vp); - vp->v_data = NULL; - VI_UNLOCK(vp); - return (0); -} - /* * .zfs inode namespace * @@ -537,9 +532,20 @@ zfsctl_root_lookup(vnode_t *dvp, char *nm, vnode_t **vpp, pathname_t *pnp, ZFS_ENTER(zfsvfs); if (strcmp(nm, "..") == 0) { +#ifdef illumos err = VFS_ROOT(dvp->v_vfsp, LK_EXCLUSIVE, vpp); +#else + /* + * NB: can not use VFS_ROOT here as it would acquire + * the vnode lock of the parent (root) vnode while + * holding the child's (.zfs) lock. + */ + znode_t *rootzp; + + err = zfs_zget(zfsvfs, zfsvfs->z_root, &rootzp); if (err == 0) - VOP_UNLOCK(*vpp, 0); + *vpp = ZTOV(rootzp); +#endif } else { err = gfs_vop_lookup(dvp, nm, vpp, pnp, flags, rdir, cr, ct, direntflags, realpnp); @@ -550,6 +556,61 @@ zfsctl_root_lookup(vnode_t *dvp, char *nm, vnode_t **vpp, pathname_t *pnp, return (err); } +static int +zfsctl_freebsd_root_lookup(ap) + struct vop_lookup_args /* { + struct vnode *a_dvp; + struct vnode **a_vpp; + struct componentname *a_cnp; + } */ *ap; +{ + vnode_t *dvp = ap->a_dvp; + vnode_t **vpp = ap->a_vpp; + cred_t *cr = ap->a_cnp->cn_cred; + int flags = ap->a_cnp->cn_flags; + int lkflags = ap->a_cnp->cn_lkflags; + int nameiop = ap->a_cnp->cn_nameiop; + char nm[NAME_MAX + 1]; + int err; + + if ((flags & ISLASTCN) && (nameiop == RENAME || nameiop == CREATE)) + return (EOPNOTSUPP); + + ASSERT(ap->a_cnp->cn_namelen < sizeof(nm)); + strlcpy(nm, ap->a_cnp->cn_nameptr, ap->a_cnp->cn_namelen + 1); +relookup: + err = zfsctl_root_lookup(dvp, nm, vpp, NULL, 0, NULL, cr, NULL, NULL, NULL); + if (err == 0 && (nm[0] != '.' || nm[1] != '\0')) { + if (flags & ISDOTDOT) { + VOP_UNLOCK(dvp, 0); + err = vn_lock(*vpp, lkflags); + if (err != 0) { + vrele(*vpp); + *vpp = NULL; + } + vn_lock(dvp, LK_EXCLUSIVE | LK_RETRY); + } else { + err = vn_lock(*vpp, LK_EXCLUSIVE); + if (err != 0) { + VERIFY3S(err, ==, ENOENT); + goto relookup; + } + } + } + return (err); +} + +static int +zfsctl_root_print(ap) + struct vop_print_args /* { + struct vnode *a_vp; + } */ *ap; +{ + printf(" .zfs node\n"); + zfsctl_common_print(ap); + return (0); +} + #ifdef illumos static int zfsctl_pathconf(vnode_t *vp, int cmd, ulong_t *valp, cred_t *cr, @@ -585,49 +646,6 @@ static const fs_operation_def_t zfsctl_tops_root[] = { }; #endif /* illumos */ -/* - * Special case the handling of "..". - */ -/* ARGSUSED */ -int -zfsctl_freebsd_root_lookup(ap) - struct vop_lookup_args /* { - struct vnode *a_dvp; - struct vnode **a_vpp; - struct componentname *a_cnp; - } */ *ap; -{ - vnode_t *dvp = ap->a_dvp; - vnode_t **vpp = ap->a_vpp; - cred_t *cr = ap->a_cnp->cn_cred; - int flags = ap->a_cnp->cn_flags; - int nameiop = ap->a_cnp->cn_nameiop; - char nm[NAME_MAX + 1]; - int err; - int ltype; - - if ((flags & ISLASTCN) && (nameiop == RENAME || nameiop == CREATE)) - return (EOPNOTSUPP); - - ASSERT(ap->a_cnp->cn_namelen < sizeof(nm)); - strlcpy(nm, ap->a_cnp->cn_nameptr, ap->a_cnp->cn_namelen + 1); - err = zfsctl_root_lookup(dvp, nm, vpp, NULL, 0, NULL, cr, NULL, NULL, NULL); - if (err == 0 && (nm[0] != '.' || nm[1] != '\0')) { - ltype = VOP_ISLOCKED(dvp); - if (flags & ISDOTDOT) { - VN_HOLD(*vpp); - VOP_UNLOCK(dvp, 0); - } - vn_lock(*vpp, LK_EXCLUSIVE | LK_RETRY); - if (flags & ISDOTDOT) { - VN_RELE(*vpp); - vn_lock(dvp, ltype| LK_RETRY); - } - } - - return (err); -} - static struct vop_vector zfsctl_ops_root = { .vop_default = &default_vnodeops, .vop_open = zfsctl_common_open, @@ -643,6 +661,7 @@ static struct vop_vector zfsctl_ops_root = { .vop_pathconf = zfsctl_pathconf, #endif .vop_fid = zfsctl_common_fid, + .vop_print = zfsctl_root_print, }; /* @@ -987,6 +1006,11 @@ zfsctl_snapdir_lookup(ap) ZFS_ENTER(zfsvfs); if (gfs_lookup_dot(vpp, dvp, zfsvfs->z_ctldir, nm) == 0) { + if (nm[0] == '.' && nm[1] == '.' && nm[2] =='\0') { + VOP_UNLOCK(dvp, 0); + VERIFY0(vn_lock(*vpp, LK_EXCLUSIVE)); + VERIFY0(vn_lock(dvp, LK_EXCLUSIVE)); + } ZFS_EXIT(zfsvfs); return (0); } @@ -1011,6 +1035,7 @@ zfsctl_snapdir_lookup(ap) #endif } +relookup: mutex_enter(&sdp->sd_lock); search.se_name = (char *)nm; if ((sep = avl_find(&sdp->sd_snaps, &search, &where)) != NULL) { @@ -1018,7 +1043,6 @@ zfsctl_snapdir_lookup(ap) VN_HOLD(*vpp); err = traverse(vpp, LK_EXCLUSIVE | LK_RETRY); if (err != 0) { - VN_RELE(*vpp); *vpp = NULL; } else if (*vpp == sep->se_root) { /* @@ -1086,6 +1110,16 @@ domount: (void) snprintf(mountpoint, mountpoint_len, "%s/" ZFS_CTLDIR_NAME "/snapshot/%s", dvp->v_vfsp->mnt_stat.f_mntonname, nm); + mutex_exit(&sdp->sd_lock); + + /* + * The vnode may get reclaimed between dropping sd_lock and + * getting the vnode lock. + * */ + err = vn_lock(*vpp, LK_EXCLUSIVE); + if (err == ENOENT) + goto relookup; + VERIFY0(err); err = mount_snapshot(curthread, vpp, "zfs", mountpoint, snapname, 0); kmem_free(mountpoint, mountpoint_len); if (err == 0) { @@ -1100,7 +1134,6 @@ domount: VTOZ(*vpp)->z_zfsvfs->z_parent = zfsvfs; (*vpp)->v_flag &= ~VROOT; } - mutex_exit(&sdp->sd_lock); ZFS_EXIT(zfsvfs); #ifdef illumos @@ -1142,6 +1175,11 @@ zfsctl_shares_lookup(ap) strlcpy(nm, cnp->cn_nameptr, cnp->cn_namelen + 1); if (gfs_lookup_dot(vpp, dvp, zfsvfs->z_ctldir, nm) == 0) { + if (nm[0] == '.' && nm[1] == '.' && nm[2] =='\0') { + VOP_UNLOCK(dvp, 0); + VERIFY0(vn_lock(*vpp, LK_EXCLUSIVE)); + VERIFY0(vn_lock(dvp, LK_EXCLUSIVE)); + } ZFS_EXIT(zfsvfs); return (0); } @@ -1348,8 +1386,8 @@ zfsctl_snapdir_getattr(ap) /* ARGSUSED */ static int -zfsctl_snapdir_inactive(ap) - struct vop_inactive_args /* { +zfsctl_snapdir_reclaim(ap) + struct vop_reclaim_args /* { struct vnode *a_vp; struct thread *a_td; } */ *ap; @@ -1358,22 +1396,37 @@ zfsctl_snapdir_inactive(ap) zfsctl_snapdir_t *sdp = vp->v_data; zfs_snapentry_t *sep; - /* - * On forced unmount we have to free snapshots from here. - */ - mutex_enter(&sdp->sd_lock); - while ((sep = avl_first(&sdp->sd_snaps)) != NULL) { - avl_remove(&sdp->sd_snaps, sep); - kmem_free(sep->se_name, strlen(sep->se_name) + 1); - kmem_free(sep, sizeof (zfs_snapentry_t)); - } - mutex_exit(&sdp->sd_lock); - gfs_dir_inactive(vp); ASSERT(avl_numnodes(&sdp->sd_snaps) == 0); mutex_destroy(&sdp->sd_lock); avl_destroy(&sdp->sd_snaps); - kmem_free(sdp, sizeof (zfsctl_snapdir_t)); + gfs_vop_reclaim(ap); + + return (0); +} +static int +zfsctl_shares_print(ap) + struct vop_print_args /* { + struct vnode *a_vp; + } */ *ap; +{ + printf(" .zfs/shares node\n"); + zfsctl_common_print(ap); + return (0); +} + +static int +zfsctl_snapdir_print(ap) + struct vop_print_args /* { + struct vnode *a_vp; + } */ *ap; +{ + vnode_t *vp = ap->a_vp; + zfsctl_snapdir_t *sdp = vp->v_data; + + printf(" .zfs/snapshot node\n"); + printf(" number of children = %lu\n", avl_numnodes(&sdp->sd_snaps)); + zfsctl_common_print(ap); return (0); } @@ -1419,9 +1472,10 @@ static struct vop_vector zfsctl_ops_snapdir = { .vop_mkdir = zfsctl_freebsd_snapdir_mkdir, .vop_readdir = gfs_vop_readdir, .vop_lookup = zfsctl_snapdir_lookup, - .vop_inactive = zfsctl_snapdir_inactive, - .vop_reclaim = zfsctl_common_reclaim, + .vop_inactive = VOP_NULL, + .vop_reclaim = zfsctl_snapdir_reclaim, .vop_fid = zfsctl_common_fid, + .vop_print = zfsctl_snapdir_print, }; static struct vop_vector zfsctl_ops_shares = { @@ -1436,6 +1490,7 @@ static struct vop_vector zfsctl_ops_shares = { .vop_inactive = VOP_NULL, .vop_reclaim = gfs_vop_reclaim, .vop_fid = zfsctl_shares_fid, + .vop_print = zfsctl_shares_print, }; #endif /* illumos */ @@ -1461,17 +1516,28 @@ zfsctl_snapshot_mknode(vnode_t *pvp, uint64_t objset) return (vp); } +static int +zfsctl_snapshot_inactive(ap) + struct vop_inactive_args /* { + struct vnode *a_vp; + struct thread *a_td; + } */ *ap; +{ + vnode_t *vp = ap->a_vp; + + vrecycle(vp); + return (0); +} static int zfsctl_snapshot_reclaim(ap) - struct vop_inactive_args /* { + struct vop_reclaim_args /* { struct vnode *a_vp; struct thread *a_td; } */ *ap; { vnode_t *vp = ap->a_vp; cred_t *cr = ap->a_td->td_ucred; - struct vop_reclaim_args iap; zfsctl_snapdir_t *sdp; zfs_snapentry_t *sep, *next; int locked; @@ -1479,7 +1545,6 @@ zfsctl_snapshot_reclaim(ap) VERIFY(gfs_dir_lookup(vp, "..", &dvp, cr, 0, NULL, NULL) == 0); sdp = dvp->v_data; - VOP_UNLOCK(dvp, 0); /* this may already have been unmounted */ if (sdp == NULL) { VN_RELE(dvp); @@ -1515,8 +1580,7 @@ zfsctl_snapshot_reclaim(ap) * "active". If we lookup the same name again we will end up * creating a new vnode. */ - iap.a_vp = vp; - gfs_vop_reclaim(&iap); + gfs_vop_reclaim(ap); return (0); } @@ -1563,15 +1627,31 @@ zfsctl_snapshot_vptocnp(struct vop_vptocnp_args *ap) return (error); } +static int +zfsctl_snaphot_print(ap) + struct vop_print_args /* { + struct vnode *a_vp; + } */ *ap; +{ + vnode_t *vp = ap->a_vp; + zfsctl_node_t *zcp = vp->v_data; + + printf(" .zfs/snapshot/<snap> node\n"); + printf(" id = %ju\n", (uintmax_t)zcp->zc_id); + zfsctl_common_print(ap); + return (0); +} + /* * These VP's should never see the light of day. They should always * be covered. */ static struct vop_vector zfsctl_ops_snapshot = { .vop_default = &default_vnodeops, - .vop_inactive = VOP_NULL, + .vop_inactive = zfsctl_snapshot_inactive, .vop_reclaim = zfsctl_snapshot_reclaim, .vop_vptocnp = zfsctl_snapshot_vptocnp, + .vop_print = zfsctl_snaphot_print, }; int @@ -1612,16 +1692,15 @@ zfsctl_lookup_objset(vfs_t *vfsp, uint64_t objsetid, zfsvfs_t **zfsvfsp) */ error = traverse(&vp, LK_SHARED | LK_RETRY); if (error == 0) { - if (vp == sep->se_root) + if (vp == sep->se_root) { + VN_RELE(vp); /* release covered vp */ error = SET_ERROR(EINVAL); - else + } else { *zfsvfsp = VTOZ(vp)->z_zfsvfs; + VN_URELE(vp); /* put snapshot's root vp */ + } } mutex_exit(&sdp->sd_lock); - if (error == 0) - VN_URELE(vp); - else - VN_RELE(vp); } else { error = SET_ERROR(EINVAL); mutex_exit(&sdp->sd_lock); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c index 430ed34..740eacd 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c @@ -3791,7 +3791,7 @@ zfs_ioc_rename(zfs_cmd_t *zc) if (strncmp(zc->zc_name, zc->zc_value, at - zc->zc_name + 1)) return (SET_ERROR(EXDEV)); *at = '\0'; - if (zc->zc_objset_type == DMU_OST_ZFS && allow_mounted) { + if (zc->zc_objset_type == DMU_OST_ZFS && !allow_mounted) { error = dmu_objset_find(zc->zc_name, recursive_unmount, at + 1, recursive ? DS_FIND_CHILDREN : 0); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c index 6969993..e39859c5 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c @@ -1780,11 +1780,8 @@ zfs_root(vfs_t *vfsp, int flags, vnode_t **vpp) ZFS_EXIT(zfsvfs); - if (error == 0) { + if (error == 0) error = vn_lock(*vpp, flags); - if (error == 0) - (*vpp)->v_vflag |= VV_ROOT; - } if (error != 0) *vpp = NULL; diff --git a/sys/compat/cloudabi/cloudabi_thread.c b/sys/compat/cloudabi/cloudabi_thread.c index 37dc794..dd54e89 100644 --- a/sys/compat/cloudabi/cloudabi_thread.c +++ b/sys/compat/cloudabi/cloudabi_thread.c @@ -30,6 +30,7 @@ __FBSDID("$FreeBSD$"); #include <sys/proc.h> #include <sys/sched.h> #include <sys/syscallsubr.h> +#include <sys/umtx.h> #include <contrib/cloudabi/cloudabi_types_common.h> @@ -44,6 +45,8 @@ cloudabi_sys_thread_exit(struct thread *td, .scope = uap->scope, }; + umtx_thread_exit(td); + /* Wake up joining thread. */ cloudabi_sys_lock_unlock(td, &cloudabi_sys_lock_unlock_args); diff --git a/sys/compat/linux/linux_fork.c b/sys/compat/linux/linux_fork.c index de1d041..4c30c9a 100644 --- a/sys/compat/linux/linux_fork.c +++ b/sys/compat/linux/linux_fork.c @@ -42,6 +42,7 @@ __FBSDID("$FreeBSD$"); #include <sys/sched.h> #include <sys/syscallsubr.h> #include <sys/sx.h> +#include <sys/umtx.h> #include <sys/unistd.h> #include <sys/wait.h> @@ -410,6 +411,8 @@ linux_exit(struct thread *td, struct linux_exit_args *args) LINUX_CTR2(exit, "thread(%d) (%d)", em->em_tid, args->rval); + umtx_thread_exit(td); + linux_thread_detach(td); /* diff --git a/sys/compat/linuxkpi/common/include/linux/device.h b/sys/compat/linuxkpi/common/include/linux/device.h index ccee7b4..2f43d81 100644 --- a/sys/compat/linuxkpi/common/include/linux/device.h +++ b/sys/compat/linuxkpi/common/include/linux/device.h @@ -333,10 +333,11 @@ device_unregister(struct device *dev) bsddev = dev->bsddev; dev->bsddev = NULL; - mtx_lock(&Giant); - if (bsddev != NULL) + if (bsddev != NULL) { + mtx_lock(&Giant); device_delete_child(device_get_parent(bsddev), bsddev); - mtx_unlock(&Giant); + mtx_unlock(&Giant); + } put_device(dev); } @@ -348,10 +349,11 @@ device_del(struct device *dev) bsddev = dev->bsddev; dev->bsddev = NULL; - mtx_lock(&Giant); - if (bsddev != NULL) + if (bsddev != NULL) { + mtx_lock(&Giant); device_delete_child(device_get_parent(bsddev), bsddev); - mtx_unlock(&Giant); + mtx_unlock(&Giant); + } } struct device *device_create(struct class *class, struct device *parent, diff --git a/sys/conf/Makefile.mips b/sys/conf/Makefile.mips index 09eca75..d1e6923 100644 --- a/sys/conf/Makefile.mips +++ b/sys/conf/Makefile.mips @@ -62,6 +62,7 @@ ASM_CFLAGS+=${CFLAGS} -D_LOCORE -DLOCORE .if !defined(WITHOUT_KERNEL_TRAMPOLINE) KERNEL_EXTRA=trampoline +KERNEL_EXTRA_INSTALL=${KERNEL_KO}.tramp.bin trampoline: ${KERNEL_KO}.tramp.bin ${KERNEL_KO}.tramp.bin: ${KERNEL_KO} $S/$M/$M/elf_trampoline.c \ $S/$M/$M/inckern.S @@ -72,7 +73,7 @@ ${KERNEL_KO}.tramp.bin: ${KERNEL_KO} $S/$M/$M/elf_trampoline.c \ ${CC} -O -nostdlib -I. -I$S ${TRAMP_EXTRA_FLAGS} ${TRAMP_LDFLAGS} -Xlinker \ -T -Xlinker ${LDSCRIPT_NAME}.tramp.noheader \ -DKERNNAME="\"${KERNEL_KO}.tmp\"" -DELFSIZE=${TRAMP_ELFSIZE} \ - $S/$M/$M/elf_trampoline.c $S/$M/$M/inckern.S \ + $S/$M/$M/inckern.S $S/$M/$M/elf_trampoline.c \ -o ${KERNEL_KO}.tramp.elf ${OBJCOPY} -S -O binary ${KERNEL_KO}.tramp.elf \ ${KERNEL_KO}.tramp.bin diff --git a/sys/conf/NOTES b/sys/conf/NOTES index 45732da..fd66dfd 100644 --- a/sys/conf/NOTES +++ b/sys/conf/NOTES @@ -298,7 +298,6 @@ options SX_NOINLINE # performance and increase the frequency of kernel panics by # design. If you aren't sure that you need it then you don't. # Relies on the PREEMPTION option. DON'T TURN THIS ON. -# MUTEX_DEBUG enables various extra assertions in the mutex code. # SLEEPQUEUE_PROFILING enables rudimentary profiling of the hash table # used to hold active sleep queues as well as sleep wait message # frequency. @@ -314,7 +313,6 @@ options SX_NOINLINE # WITNESS_SKIPSPIN disables the witness checks on spin mutexes. options PREEMPTION options FULL_PREEMPTION -options MUTEX_DEBUG options WITNESS options WITNESS_KDB options WITNESS_SKIPSPIN @@ -1139,12 +1137,6 @@ options NFS_DEBUG # Enable NFS Debugging # options EXT2FS -# -# Add support for the ReiserFS filesystem (used in Linux). Currently, -# this is limited to read-only access. -# -options REISERFS - # Cryptographically secure random number generator; /dev/random device random @@ -3061,3 +3053,6 @@ options EM_MULTIQUEUE # Activate multiqueue features/disable MSI-X # zlib I/O stream support # This enables support for compressed core dumps. options GZIO + +# BHND(4) drivers +options BHND_LOGLEVEL # Logging threshold level diff --git a/sys/conf/files b/sys/conf/files index f172a52..0968026 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -1142,6 +1142,9 @@ dev/bhnd/cores/chipc/bhnd_chipc_if.m optional bhndbus | bhnd dev/bhnd/cores/pci/bhnd_pci.c optional bhndbus pci | bhnd pci dev/bhnd/cores/pci/bhnd_pci_hostb.c optional bhndbus pci | bhndb pci dev/bhnd/cores/pci/bhnd_pcib.c optional bhnd_pcib bhnd pci +dev/bhnd/cores/pcie2/bhnd_pcie2.c optional bhndbus pci | bhnd pci +dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c optional bhndbus pci | bhndb pci +dev/bhnd/cores/pcie2/bhnd_pcie2b.c optional bhnd_pcie2b bhnd pci dev/bhnd/nvram/bhnd_nvram_if.m optional bhndbus | bhnd dev/bhnd/nvram/bhnd_sprom.c optional bhndbus | bhnd dev/bhnd/nvram/nvram_subr.c optional bhndbus | bhnd @@ -1176,6 +1179,7 @@ dev/bwn/if_bwn_phy_g.c optional bwn siba_bwn \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/bwn/if_bwn_phy_lp.c optional bwn siba_bwn \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" +dev/bwn/if_bwn_phy_n.c optional bwn siba_bwn dev/bwn/if_bwn_util.c optional bwn siba_bwn dev/bwn/bwn_mac.c optional bwn bhnd | bwn bhndbus dev/cardbus/cardbus.c optional cardbus @@ -1625,8 +1629,8 @@ ipw_monitor.fw optional ipwmonitorfw | ipwfw \ clean "ipw_monitor.fw" dev/iscsi/icl.c optional iscsi | ctl dev/iscsi/icl_conn_if.m optional iscsi | ctl -dev/iscsi/icl_proxy.c optional iscsi | ctl dev/iscsi/icl_soft.c optional iscsi | ctl +dev/iscsi/icl_soft_proxy.c optional iscsi | ctl dev/iscsi/iscsi.c optional iscsi scbus dev/iscsi_initiator/iscsi.c optional iscsi_initiator scbus dev/iscsi_initiator/iscsi_subr.c optional iscsi_initiator scbus @@ -3151,15 +3155,6 @@ fs/ext2fs/ext2_lookup.c optional ext2fs fs/ext2fs/ext2_subr.c optional ext2fs fs/ext2fs/ext2_vfsops.c optional ext2fs fs/ext2fs/ext2_vnops.c optional ext2fs -gnu/fs/reiserfs/reiserfs_hashes.c optional reiserfs \ - warning "kernel contains GPL contaminated ReiserFS filesystem" -gnu/fs/reiserfs/reiserfs_inode.c optional reiserfs -gnu/fs/reiserfs/reiserfs_item_ops.c optional reiserfs -gnu/fs/reiserfs/reiserfs_namei.c optional reiserfs -gnu/fs/reiserfs/reiserfs_prints.c optional reiserfs -gnu/fs/reiserfs/reiserfs_stree.c optional reiserfs -gnu/fs/reiserfs/reiserfs_vfsops.c optional reiserfs -gnu/fs/reiserfs/reiserfs_vnops.c optional reiserfs # isa/isa_if.m standard isa/isa_common.c optional isa @@ -3528,6 +3523,9 @@ net/if_tun.c optional tun net/if_tap.c optional tap net/if_vlan.c optional vlan net/if_vxlan.c optional vxlan inet | vxlan inet6 +net/ifdi_if.m optional ether pci +net/iflib.c optional ether pci +net/mp_ring.c optional ether net/mppcc.c optional netgraph_mppc_compression net/mppcd.c optional netgraph_mppc_compression net/netisr.c standard diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index b398ff2..436eded 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -1,5 +1,6 @@ # $FreeBSD$ arm/arm/generic_timer.c standard +arm/arm/gic.c optional intrng arm/arm/pmu.c standard arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi @@ -24,14 +25,14 @@ arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard -arm64/arm64/gic.c standard -arm64/arm64/gic_acpi.c optional acpi -arm64/arm64/gic_fdt.c optional fdt +arm64/arm64/gic.c optional !intrng +arm64/arm64/gic_acpi.c optional !intrng acpi +arm64/arm64/gic_fdt.c optional !intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_fdt.c optional fdt -arm64/arm64/gic_v3_its.c standard +arm64/arm64/gic_v3_its.c optional !intrng arm64/arm64/identcpu.c standard -arm64/arm64/intr_machdep.c standard +arm64/arm64/intr_machdep.c optional !intrng arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard @@ -40,7 +41,7 @@ arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt -arm64/arm64/pic_if.m standard +arm64/arm64/pic_if.m optional !intrng arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard @@ -83,7 +84,10 @@ dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional vnic kern/kern_clocksource.c standard +kern/msi_if.m optional intrng +kern/pic_if.m optional intrng kern/subr_devmap.c standard +kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard diff --git a/sys/conf/options b/sys/conf/options index f06a092..7735f37 100644 --- a/sys/conf/options +++ b/sys/conf/options @@ -139,6 +139,7 @@ GEOM_VINUM opt_geom.h GEOM_VIRSTOR opt_geom.h GEOM_VOL opt_geom.h GEOM_ZERO opt_geom.h +IFLIB opt_iflib.h KDTRACE_HOOKS opt_global.h KDTRACE_FRAME opt_kdtrace.h KN_HASHSIZE opt_kqueue.h @@ -242,7 +243,6 @@ NANDFS opt_dontuse.h NULLFS opt_dontuse.h PROCFS opt_dontuse.h PSEUDOFS opt_dontuse.h -REISERFS opt_dontuse.h SMBFS opt_dontuse.h TMPFS opt_dontuse.h UDF opt_dontuse.h @@ -591,7 +591,6 @@ MAXCPU opt_global.h MAXMEMDOM opt_global.h MAXPHYS opt_global.h MCLSHIFT opt_global.h -MUTEX_DEBUG opt_global.h MUTEX_NOINLINE opt_global.h LOCK_PROFILING opt_global.h LOCK_PROFILING_FAST opt_global.h @@ -856,6 +855,10 @@ BWI_DEBUG_VERBOSE opt_bwi.h # options for the Brodacom BCM43xx driver (bwn) BWN_DEBUG opt_bwn.h +BWN_GPL_PHY opt_bwn.h + +# Options for the SIBA driver +SIBA_DEBUG opt_siba.h # options for the Marvell 8335 wireless driver MALO_DEBUG opt_malo.h @@ -976,3 +979,6 @@ RANDOM_ENABLE_UMA opt_global.h # Intel em(4) driver EM_MULTIQUEUE opt_em.h + +# BHND(4) driver +BHND_LOGLEVEL opt_global.h diff --git a/sys/conf/options.arm64 b/sys/conf/options.arm64 index bc42c82..f5c276c 100644 --- a/sys/conf/options.arm64 +++ b/sys/conf/options.arm64 @@ -1,6 +1,7 @@ # $FreeBSD$ ARM64 opt_global.h +INTRNG opt_global.h SOCDEV_PA opt_global.h SOCDEV_VA opt_global.h THUNDERX_PASS_1_1_ERRATA opt_global.h diff --git a/sys/ddb/db_examine.c b/sys/ddb/db_examine.c index a41fcb5..de2bbe4 100644 --- a/sys/ddb/db_examine.c +++ b/sys/ddb/db_examine.c @@ -225,6 +225,10 @@ db_print_cmd(db_expr_t addr, bool have_addr, db_expr_t count, char *modif) else db_printf("\\%03o", (int)value); break; + default: + db_print_format = 'x'; + db_error("Syntax error: unsupported print modifier\n"); + /*NOTREACHED*/ } db_printf("\n"); } diff --git a/sys/ddb/db_expr.c b/sys/ddb/db_expr.c index 8588676..db17f36 100644 --- a/sys/ddb/db_expr.c +++ b/sys/ddb/db_expr.c @@ -43,6 +43,9 @@ static bool db_mult_expr(db_expr_t *valuep); static bool db_shift_expr(db_expr_t *valuep); static bool db_term(db_expr_t *valuep); static bool db_unary(db_expr_t *valuep); +static bool db_logical_or_expr(db_expr_t *valuep); +static bool db_logical_and_expr(db_expr_t *valuep); +static bool db_logical_relation_expr(db_expr_t *valuep); static bool db_term(db_expr_t *valuep) @@ -108,19 +111,40 @@ db_unary(db_expr_t *valuep) t = db_read_token(); if (t == tMINUS) { if (!db_unary(valuep)) { - db_error("Syntax error\n"); + db_printf("Expression syntax error after '%c'\n", '-'); + db_error(NULL); /*NOTREACHED*/ } *valuep = -*valuep; return (true); } + if (t == tEXCL) { + if(!db_unary(valuep)) { + db_printf("Expression syntax error after '%c'\n", '!'); + db_error(NULL); + /* NOTREACHED */ + } + *valuep = (!(*valuep)); + return (true); + } + if (t == tBIT_NOT) { + if(!db_unary(valuep)) { + db_printf("Expression syntax error after '%c'\n", '~'); + db_error(NULL); + /* NOTREACHED */ + } + *valuep = (~(*valuep)); + return (true); + } if (t == tSTAR) { /* indirection */ if (!db_unary(valuep)) { - db_error("Syntax error\n"); + db_printf("Expression syntax error after '%c'\n", '*'); + db_error(NULL); /*NOTREACHED*/ } - *valuep = db_get_value((db_addr_t)*valuep, sizeof(void *), false); + *valuep = db_get_value((db_addr_t)*valuep, sizeof(void *), + false); return (true); } db_unread_token(t); @@ -137,24 +161,31 @@ db_mult_expr(db_expr_t *valuep) return (false); t = db_read_token(); - while (t == tSTAR || t == tSLASH || t == tPCT || t == tHASH) { + while (t == tSTAR || t == tSLASH || t == tPCT || t == tHASH || + t == tBIT_AND ) { if (!db_term(&rhs)) { - db_error("Syntax error\n"); + db_printf("Expression syntax error after '%c'\n", '!'); + db_error(NULL); /*NOTREACHED*/ } - if (t == tSTAR) - lhs *= rhs; - else { - if (rhs == 0) { - db_error("Divide by 0\n"); - /*NOTREACHED*/ - } - if (t == tSLASH) - lhs /= rhs; - else if (t == tPCT) - lhs %= rhs; - else - lhs = roundup(lhs, rhs); + switch(t) { + case tSTAR: + lhs *= rhs; + break; + case tBIT_AND: + lhs &= rhs; + break; + default: + if (rhs == 0) { + db_error("Divide by 0\n"); + /*NOTREACHED*/ + } + if (t == tSLASH) + lhs /= rhs; + else if (t == tPCT) + lhs %= rhs; + else + lhs = roundup(lhs, rhs); } t = db_read_token(); } @@ -168,20 +199,32 @@ db_add_expr(db_expr_t *valuep) { db_expr_t lhs, rhs; int t; + char c; if (!db_mult_expr(&lhs)) return (false); t = db_read_token(); - while (t == tPLUS || t == tMINUS) { + while (t == tPLUS || t == tMINUS || t == tBIT_OR) { if (!db_mult_expr(&rhs)) { - db_error("Syntax error\n"); + c = db_tok_string[0]; + db_printf("Expression syntax error after '%c'\n", c); + db_error(NULL); /*NOTREACHED*/ } - if (t == tPLUS) + switch (t) { + case tPLUS: lhs += rhs; - else + break; + case tMINUS: lhs -= rhs; + break; + case tBIT_OR: + lhs |= rhs; + break; + default: + __unreachable(); + } t = db_read_token(); } db_unread_token(t); @@ -196,8 +239,7 @@ db_shift_expr(db_expr_t *valuep) int t; if (!db_add_expr(&lhs)) - return (false); - + return (false); t = db_read_token(); while (t == tSHIFT_L || t == tSHIFT_R) { if (!db_add_expr(&rhs)) { @@ -221,8 +263,109 @@ db_shift_expr(db_expr_t *valuep) return (true); } +static bool +db_logical_relation_expr( + db_expr_t *valuep) +{ + db_expr_t lhs, rhs; + int t; + char op[3]; + + if (!db_shift_expr(&lhs)) + return (false); + + t = db_read_token(); + while (t == tLOG_EQ || t == tLOG_NOT_EQ || t == tGREATER || + t == tGREATER_EQ || t == tLESS || t == tLESS_EQ) { + op[0] = db_tok_string[0]; + op[1] = db_tok_string[1]; + op[2] = 0; + if (!db_shift_expr(&rhs)) { + db_printf("Expression syntax error after \"%s\"\n", op); + db_error(NULL); + /*NOTREACHED*/ + } + switch(t) { + case tLOG_EQ: + lhs = (lhs == rhs); + break; + case tLOG_NOT_EQ: + lhs = (lhs != rhs); + break; + case tGREATER: + lhs = (lhs > rhs); + break; + case tGREATER_EQ: + lhs = (lhs >= rhs); + break; + case tLESS: + lhs = (lhs < rhs); + break; + case tLESS_EQ: + lhs = (lhs <= rhs); + break; + default: + __unreachable(); + } + t = db_read_token(); + } + db_unread_token(t); + *valuep = lhs; + return (true); +} + +static bool +db_logical_and_expr( + db_expr_t *valuep) +{ + db_expr_t lhs, rhs; + int t; + + if (!db_logical_relation_expr(&lhs)) + return (false); + + t = db_read_token(); + while (t == tLOG_AND) { + if (!db_logical_relation_expr(&rhs)) { + db_printf("Expression syntax error after '%s'\n", "&&"); + db_error(NULL); + /*NOTREACHED*/ + } + lhs = (lhs && rhs); + t = db_read_token(); + } + db_unread_token(t); + *valuep = lhs; + return (true); +} + +static bool +db_logical_or_expr( + db_expr_t *valuep) +{ + db_expr_t lhs, rhs; + int t; + + if (!db_logical_and_expr(&lhs)) + return(false); + + t = db_read_token(); + while (t == tLOG_OR) { + if (!db_logical_and_expr(&rhs)) { + db_printf("Expression syntax error after '%s'\n", "||"); + db_error(NULL); + /*NOTREACHED*/ + } + lhs = (lhs || rhs); + t = db_read_token(); + } + db_unread_token(t); + *valuep = lhs; + return (true); +} + int db_expression(db_expr_t *valuep) { - return (db_shift_expr(valuep)); + return (db_logical_or_expr(valuep)); } diff --git a/sys/ddb/db_lex.c b/sys/ddb/db_lex.c index 8a81046..4fdfa31 100644 --- a/sys/ddb/db_lex.c +++ b/sys/ddb/db_lex.c @@ -274,6 +274,10 @@ db_lex(void) case '/': return (tSLASH); case '=': + c = db_read_char(); + if (c == '=') + return (tLOG_EQ); + db_unread_char(c); return (tEQ); case '%': return (tPCT); @@ -290,21 +294,46 @@ db_lex(void) case '$': return (tDOLLAR); case '!': + c = db_read_char(); + if (c == '='){ + return (tLOG_NOT_EQ); + } + db_unread_char(c); return (tEXCL); case ';': return (tSEMI); + case '&': + c = db_read_char(); + if (c == '&') + return (tLOG_AND); + db_unread_char(c); + return (tBIT_AND); + case '|': + c = db_read_char(); + if (c == '|') + return (tLOG_OR); + db_unread_char(c); + return (tBIT_OR); case '<': c = db_read_char(); if (c == '<') return (tSHIFT_L); + if (c == '=') + return (tLESS_EQ); db_unread_char(c); - break; + return (tLESS); case '>': c = db_read_char(); if (c == '>') return (tSHIFT_R); + if (c == '=') + return (tGREATER_EQ); db_unread_char(c); - break; + return (tGREATER); + case '?': + return (tQUESTION); + case '~': + return (tBIT_NOT); case -1: return (tEOF); } diff --git a/sys/ddb/db_lex.h b/sys/ddb/db_lex.h index 8713a27..e20907d 100644 --- a/sys/ddb/db_lex.h +++ b/sys/ddb/db_lex.h @@ -69,5 +69,18 @@ extern char db_tok_string[TOK_STRING_SIZE]; #define tSHIFT_R 19 #define tDOTDOT 20 #define tSEMI 21 +#define tLOG_EQ 22 +#define tLOG_NOT_EQ 23 +#define tLESS 24 +#define tLESS_EQ 25 +#define tGREATER 26 +#define tGREATER_EQ 27 +#define tBIT_AND 28 +#define tBIT_OR 29 +#define tLOG_AND 30 +#define tLOG_OR 31 +#define tSTRING 32 +#define tQUESTION 33 +#define tBIT_NOT 34 #endif /* !_DDB_DB_LEX_H_ */ diff --git a/sys/dev/acpica/Osd/OsdSynch.c b/sys/dev/acpica/Osd/OsdSynch.c index 99a69ec..db29239 100644 --- a/sys/dev/acpica/Osd/OsdSynch.c +++ b/sys/dev/acpica/Osd/OsdSynch.c @@ -188,6 +188,23 @@ AcpiOsWaitSemaphore(ACPI_SEMAPHORE Handle, UINT32 Units, UINT16 Timeout) } break; default: + if (cold) { + /* + * Just spin polling the semaphore once a + * millisecond. + */ + while (!ACPISEM_AVAIL(as, Units)) { + if (Timeout == 0) { + status = AE_TIME; + break; + } + Timeout--; + mtx_unlock(&as->as_lock); + DELAY(1000); + mtx_lock(&as->as_lock); + } + break; + } tmo = timeout2hz(Timeout); while (!ACPISEM_AVAIL(as, Units)) { prevtick = ticks; @@ -381,6 +398,23 @@ AcpiOsAcquireMutex(ACPI_MUTEX Handle, UINT16 Timeout) } break; default: + if (cold) { + /* + * Just spin polling the mutex once a + * millisecond. + */ + while (!ACPIMTX_AVAIL(am)) { + if (Timeout == 0) { + status = AE_TIME; + break; + } + Timeout--; + mtx_unlock(&am->am_lock); + DELAY(1000); + mtx_lock(&am->am_lock); + } + break; + } tmo = timeout2hz(Timeout); while (!ACPIMTX_AVAIL(am)) { prevtick = ticks; diff --git a/sys/dev/atkbdc/atkbdc_ebus.c b/sys/dev/atkbdc/atkbdc_ebus.c index fd6443e..7662ee1 100644 --- a/sys/dev/atkbdc/atkbdc_ebus.c +++ b/sys/dev/atkbdc/atkbdc_ebus.c @@ -242,14 +242,14 @@ atkbdc_ebus_attach(device_t dev) device_printf(dev, "<%s>: only two children per 8042 supported\n", cname); - free(cname, M_OFWPROP); + OF_prop_free(cname); continue; } adi = malloc(sizeof(struct atkbdc_device), M_ATKBDDEV, M_NOWAIT | M_ZERO); if (adi == NULL) { device_printf(dev, "<%s>: malloc failed\n", cname); - free(cname, M_OFWPROP); + OF_prop_free(cname); continue; } if (strcmp(cname, "kb_ps2") == 0) { @@ -261,7 +261,7 @@ atkbdc_ebus_attach(device_t dev) } else { device_printf(dev, "<%s>: unknown device\n", cname); free(adi, M_ATKBDDEV); - free(cname, M_OFWPROP); + OF_prop_free(cname); continue; } intr = bus_get_resource_start(dev, SYS_RES_IRQ, adi->rid); @@ -270,7 +270,7 @@ atkbdc_ebus_attach(device_t dev) "<%s>: cannot determine interrupt resource\n", cname); free(adi, M_ATKBDDEV); - free(cname, M_OFWPROP); + OF_prop_free(cname); continue; } resource_list_init(&adi->resources); @@ -281,7 +281,7 @@ atkbdc_ebus_attach(device_t dev) cname); resource_list_free(&adi->resources); free(adi, M_ATKBDDEV); - free(cname, M_OFWPROP); + OF_prop_free(cname); continue; } device_set_ivars(cdev, adi); diff --git a/sys/dev/bhnd/bcma/bcma_bhndb.c b/sys/dev/bhnd/bcma/bcma_bhndb.c index 88a5a28..aa612f3 100644 --- a/sys/dev/bhnd/bcma/bcma_bhndb.c +++ b/sys/dev/bhnd/bcma/bcma_bhndb.c @@ -166,6 +166,20 @@ bcma_bhndb_resume_child(device_t dev, device_t child) return (0); } +static int +bcma_bhndb_read_board_info(device_t dev, device_t child, + struct bhnd_board_info *info) +{ + int error; + + /* Initialize with NVRAM-derived values */ + if ((error = bhnd_bus_generic_read_board_info(dev, child, info))) + return (error); + + /* Let the bridge fill in any additional data */ + return (BHNDB_POPULATE_BOARD_INFO(device_get_parent(dev), dev, info)); +} + static device_method_t bcma_bhndb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcma_bhndb_probe), @@ -175,6 +189,9 @@ static device_method_t bcma_bhndb_methods[] = { DEVMETHOD(bus_suspend_child, bcma_bhndb_suspend_child), DEVMETHOD(bus_resume_child, bcma_bhndb_resume_child), + /* BHND interface */ + DEVMETHOD(bhnd_bus_read_board_info, bcma_bhndb_read_board_info), + DEVMETHOD_END }; diff --git a/sys/dev/bhnd/bhnd.c b/sys/dev/bhnd/bhnd.c index 3be15b2..11e34dd 100644 --- a/sys/dev/bhnd/bhnd.c +++ b/sys/dev/bhnd/bhnd.c @@ -58,11 +58,6 @@ __FBSDID("$FreeBSD$"); #include <sys/rman.h> #include <machine/resource.h> -#include "nvram/bhnd_nvram.h" - -#include "bhnd_chipc_if.h" -#include "bhnd_nvram_if.h" - #include "bhnd.h" #include "bhndvar.h" @@ -85,8 +80,6 @@ static const struct bhnd_nomatch { { BHND_MFGID_INVALID, BHND_COREID_INVALID, false } }; -static device_t find_nvram_child(device_t dev); - static int compare_ascending_probe_order(const void *lhs, const void *rhs); static int compare_descending_probe_order(const void *lhs, @@ -124,7 +117,7 @@ bhnd_generic_attach(device_t dev) /** * Default bhnd(4) bus driver implementation of DEVICE_DETACH(). * - * This implementation calls device_detach() for each of the the device's + * This implementation calls device_detach() for each of the device's * children, in reverse bhnd probe order, terminating if any call to * device_detach() fails. */ @@ -314,7 +307,9 @@ bhnd_generic_get_probe_order(device_t dev, device_t child) { switch (bhnd_get_class(child)) { case BHND_DEVCLASS_CC: - return (BHND_PROBE_BUS + BHND_PROBE_ORDER_FIRST); + /* Must be early enough to provide NVRAM access to the + * host bridge */ + return (BHND_PROBE_ROOT + BHND_PROBE_ORDER_FIRST); case BHND_DEVCLASS_CC_B: /* fall through */ @@ -381,68 +376,6 @@ bhnd_generic_is_region_valid(device_t dev, device_t child, } /** - * Find an NVRAM child device on @p dev, if any. - * - * @retval device_t An NVRAM device. - * @retval NULL If no NVRAM device is found. - */ -static device_t -find_nvram_child(device_t dev) -{ - device_t chipc, nvram; - - /* Look for a directly-attached NVRAM child */ - nvram = device_find_child(dev, "bhnd_nvram", 0); - if (nvram != NULL) - return (nvram); - - /* Remaining checks are only applicable when searching a bhnd(4) - * bus. */ - if (device_get_devclass(dev) != bhnd_devclass) - return (NULL); - - /* Look for a ChipCommon device */ - if ((chipc = bhnd_find_child(dev, BHND_DEVCLASS_CC, -1)) != NULL) { - bhnd_nvram_src_t src; - - /* Query the NVRAM source and determine whether it's - * accessible via the ChipCommon device */ - src = BHND_CHIPC_NVRAM_SRC(chipc); - if (BHND_NVRAM_SRC_CC(src)) - return (chipc); - } - - /* Not found */ - return (NULL); -} - -/** - * Default bhnd(4) bus driver implementation of BHND_BUS_GET_NVRAM_VAR(). - * - * This implementation searches @p dev for a usable NVRAM child device: - * - The first child device implementing the bhnd_nvram devclass is - * returned, otherwise - * - If @p dev is a bhnd(4) bus, a ChipCommon core that advertises an - * attached NVRAM source. - * - * If no usable child device is found on @p dev, the request is delegated to - * the BHND_BUS_GET_NVRAM_VAR() method on the parent of @p dev. - */ -static int -bhnd_generic_get_nvram_var(device_t dev, device_t child, const char *name, - void *buf, size_t *size) -{ - device_t nvram; - - /* Try to find an NVRAM device applicable to @p child */ - if ((nvram = find_nvram_child(dev)) == NULL) - return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), child, - name, buf, size)); - - return BHND_NVRAM_GETVAR(nvram, name, buf, size); -} - -/** * Default bhnd(4) bus driver implementation of BUS_PRINT_CHILD(). * * This implementation requests the device's struct resource_list via @@ -693,7 +626,7 @@ static device_method_t bhnd_methods[] = { DEVMETHOD(bhnd_bus_get_probe_order, bhnd_generic_get_probe_order), DEVMETHOD(bhnd_bus_is_region_valid, bhnd_generic_is_region_valid), DEVMETHOD(bhnd_bus_is_hw_disabled, bhnd_bus_generic_is_hw_disabled), - DEVMETHOD(bhnd_bus_get_nvram_var, bhnd_generic_get_nvram_var), + DEVMETHOD(bhnd_bus_get_nvram_var, bhnd_bus_generic_get_nvram_var), DEVMETHOD(bhnd_bus_read_1, bhnd_read_1), DEVMETHOD(bhnd_bus_read_2, bhnd_read_2), DEVMETHOD(bhnd_bus_read_4, bhnd_read_4), diff --git a/sys/dev/bhnd/bhnd.h b/sys/dev/bhnd/bhnd.h index dca9867..d01903f 100644 --- a/sys/dev/bhnd/bhnd.h +++ b/sys/dev/bhnd/bhnd.h @@ -39,6 +39,7 @@ #include "bhnd_ids.h" #include "bhnd_types.h" +#include "bhnd_debug.h" #include "bhnd_bus_if.h" extern devclass_t bhnd_devclass; @@ -109,6 +110,34 @@ BHND_ACCESSOR(core_unit, CORE_UNIT, int); #undef BHND_ACCESSOR /** + * A bhnd(4) board descriptor. + */ +struct bhnd_board_info { + uint16_t board_vendor; /**< PCI-SIG vendor ID (even on non-PCI + * devices). + * + * On PCI devices, this will generally + * be the subsystem vendor ID, but the + * value may be overridden in device + * NVRAM. + */ + uint16_t board_type; /**< Board type (See BHND_BOARD_*) + * + * On PCI devices, this will generally + * be the subsystem device ID, but the + * value may be overridden in device + * NVRAM. + */ + uint16_t board_rev; /**< Board revision. */ + uint8_t board_srom_rev; /**< Board SROM format revision */ + + uint32_t board_flags; /**< Board flags (see BHND_BFL_*) */ + uint32_t board_flags2; /**< Board flags 2 (see BHND_BFL2_*) */ + uint32_t board_flags3; /**< Board flags 3 (see BHND_BFL3_*) */ +}; + + +/** * Chip Identification * * This is read from the ChipCommon ID register; on earlier bhnd(4) devices @@ -130,23 +159,10 @@ struct bhnd_chipid { }; /** -* A bhnd(4) bus resource. -* -* This provides an abstract interface to per-core resources that may require -* bus-level remapping of address windows prior to access. -*/ -struct bhnd_resource { - struct resource *res; /**< the system resource. */ - bool direct; /**< false if the resource requires - * bus window remapping before it - * is MMIO accessible. */ -}; - -/** * A bhnd(4) core descriptor. */ struct bhnd_core_info { - uint16_t vendor; /**< vendor */ + uint16_t vendor; /**< JEP-106 vendor (BHND_MFGID_*) */ uint16_t device; /**< device */ uint16_t hwrev; /**< hardware revision */ u_int core_idx; /**< bus-assigned core index */ @@ -164,6 +180,19 @@ struct bhnd_hwrev_match { to match on any revision. */ }; +/** +* A bhnd(4) bus resource. +* +* This provides an abstract interface to per-core resources that may require +* bus-level remapping of address windows prior to access. +*/ +struct bhnd_resource { + struct resource *res; /**< the system resource. */ + bool direct; /**< false if the resource requires + * bus window remapping before it + * is MMIO accessible. */ +}; + /** * Wildcard hardware revision match descriptor. */ @@ -232,31 +261,51 @@ struct bhnd_core_match { .unit = -1 \ } -/** A chipset match descriptor. */ +/** + * A chipset match descriptor. + * + * @warning Matching on board/nvram attributes relies on NVRAM access, and will + * fail if a valid NVRAM device cannot be found, or is not yet attached. + */ struct bhnd_chip_match { /** Select fields to be matched */ - uint8_t + uint16_t match_id:1, match_rev:1, match_pkg:1, - match_flags_unused:5; + match_bvendor:1, + match_btype:1, + match_brev:1, + match_srom_rev:1, + match_any:1, + match_flags_unused:8; uint16_t chip_id; /**< required chip id */ struct bhnd_hwrev_match chip_rev; /**< matching chip revisions */ uint8_t chip_pkg; /**< required package */ + + uint16_t board_vendor; /**< required board vendor */ + uint16_t board_type; /**< required board type */ + struct bhnd_hwrev_match board_rev; /**< matching board revisions */ + + struct bhnd_hwrev_match board_srom_rev; /**< matching board srom revisions */ }; #define BHND_CHIP_MATCH_ANY \ - { .match_id = 0, .match_rev = 0, .match_pkg = 0 } + { .match_any = 1 } #define BHND_CHIP_MATCH_IS_ANY(_m) \ - ((_m)->match_id == 0 && (_m)->match_rev == 0 && (_m)->match_pkg == 0) + ((_m)->match_any == 1) + +#define BHND_CHIP_MATCH_REQ_BOARD_INFO(_m) \ + ((_m)->match_srom_rev || (_m)->match_bvendor || \ + (_m)->match_btype || (_m)->match_brev) /** Set the required chip ID within a bhnd_chip_match instance */ #define BHND_CHIP_ID(_cid) \ .match_id = 1, .chip_id = BHND_CHIPID_BCM ## _cid -/** Set the required revision range within a bhnd_chip_match instance */ +/** Set the required chip revision range within a bhnd_chip_match instance */ #define BHND_CHIP_REV(_rev) \ .match_rev = 1, .chip_rev = BHND_ ## _rev @@ -264,6 +313,31 @@ struct bhnd_chip_match { #define BHND_CHIP_PKG(_pkg) \ .match_pkg = 1, .chip_pkg = BHND_PKGID_BCM ## _pkg +/** Set the required board vendor within a bhnd_chip_match instance */ +#define BHND_CHIP_BVENDOR(_vend) \ + .match_bvendor = 1, .board_vendor = _vend + +/** Set the required board type within a bhnd_chip_match instance */ +#define BHND_CHIP_BTYPE(_btype) \ + .match_btype = 1, .board_type = BHND_BOARD_ ## _btype + +/** Set the required SROM revision range within a bhnd_chip_match instance */ +#define BHND_CHIP_SROMREV(_rev) \ + .match_srom_rev = 1, .board_srom_rev = BHND_ ## _rev + +/** Set the required board revision range within a bhnd_chip_match instance */ +#define BHND_CHIP_BREV(_rev) \ + .match_brev = 1, .board_rev = BHND_ ## _rev + +/** Set the required board vendor and type within a bhnd_chip_match instance */ +#define BHND_CHIP_BVT(_vend, _type) \ + BHND_CHIP_BVENDOR(_vend), BHND_CHIP_BTYPE(_type) + +/** Set the required board vendor, type, and revision within a bhnd_chip_match + * instance */ +#define BHND_CHIP_BVTR(_vend, _type, _rev) \ + BHND_CHIP_BVT(_vend, _type), BHND_CHIP_BREV(_rev) + /** Set the required chip and package ID within a bhnd_chip_match instance */ #define BHND_CHIP_IP(_cid, _pkg) \ BHND_CHIP_ID(_cid), BHND_CHIP_PKG(_pkg) @@ -313,17 +387,29 @@ struct bhnd_device { const struct bhnd_core_match core; /**< core match descriptor */ const char *desc; /**< device description, or NULL. */ const struct bhnd_device_quirk *quirks_table; /**< quirks table for this device, or NULL */ + const struct bhnd_chip_quirk *chip_quirks_table; /**< chipset-specific quirks for this device, or NULL */ uint32_t device_flags; /**< required BHND_DF_* flags */ }; -#define _BHND_DEVICE(_device, _desc, _quirks, _flags, ...) \ - { BHND_CORE_MATCH(BHND_MFGID_BCM, BHND_COREID_ ## _device, \ - BHND_HWREV_ANY), _desc, _quirks, _flags } +#define _BHND_DEVICE(_vendor, _device, _desc, _quirks, _chip_quirks, \ + _flags, ...) \ + { BHND_CORE_MATCH(BHND_MFGID_ ## _vendor, \ + BHND_COREID_ ## _device, BHND_HWREV_ANY), _desc, _quirks, \ + _chip_quirks, _flags } + +#define BHND_MIPS_DEVICE(_device, _desc, _quirks, _chip_quirks, ...) \ + _BHND_DEVICE(MIPS, _device, _desc, _quirks, _chip_quirks, \ + ## __VA_ARGS__, 0) -#define BHND_DEVICE(_device, _desc, _quirks, ...) \ - _BHND_DEVICE(_device, _desc, _quirks, ## __VA_ARGS__, 0) +#define BHND_ARM_DEVICE(_device, _desc, _quirks, _chip_quirks, ...) \ + _BHND_DEVICE(ARM, _device, _desc, _quirks, _chip_quirks, \ + ## __VA_ARGS__, 0) -#define BHND_DEVICE_END { BHND_CORE_MATCH_ANY, NULL, NULL, 0 } +#define BHND_DEVICE(_device, _desc, _quirks, _chip_quirks, ...) \ + _BHND_DEVICE(BCM, _device, _desc, _quirks, _chip_quirks, \ + ## __VA_ARGS__, 0) + +#define BHND_DEVICE_END { BHND_CORE_MATCH_ANY, NULL, NULL, NULL, 0 } const char *bhnd_vendor_name(uint16_t vendor); const char *bhnd_port_type_name(bhnd_port_type port_type); @@ -343,6 +429,9 @@ device_t bhnd_match_child(device_t dev, device_t bhnd_find_child(device_t dev, bhnd_devclass_t class, int unit); +device_t bhnd_find_bridge_root(device_t dev, + devclass_t bus_class); + const struct bhnd_core_info *bhnd_match_core( const struct bhnd_core_info *cores, u_int num_cores, @@ -358,6 +447,7 @@ bool bhnd_core_matches( bool bhnd_chip_matches( const struct bhnd_chipid *chipid, + const struct bhnd_board_info *binfo, const struct bhnd_chip_match *desc); bool bhnd_hwrev_matches(uint16_t hwrev, @@ -411,6 +501,12 @@ int bhnd_bus_generic_read_nvram_var(device_t dev, void *buf, size_t *size); const struct bhnd_chipid *bhnd_bus_generic_get_chipid(device_t dev, device_t child); +int bhnd_bus_generic_read_board_info(device_t dev, + device_t child, + struct bhnd_board_info *info); +int bhnd_bus_generic_get_nvram_var(device_t dev, + device_t child, const char *name, + void *buf, size_t *size); struct bhnd_resource *bhnd_bus_generic_alloc_resource (device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, @@ -465,6 +561,28 @@ bhnd_get_chipid(device_t dev) { }; /** + * Attempt to read the BHND board identification from the bhnd bus. + * + * This relies on NVRAM access, and will fail if a valid NVRAM device cannot + * be found, or is not yet attached. + * + * @param dev The parent of @p child. + * @param child The bhnd device requesting board info. + * @param[out] info On success, will be populated with the bhnd(4) device's + * board information. + * + * @retval 0 success + * @retval ENODEV No valid NVRAM source could be found. + * @retval non-zero If reading @p name otherwise fails, a regular unix + * error code will be returned. + */ +static inline int +bhnd_read_board_info(device_t dev, struct bhnd_board_info *info) +{ + return (BHND_BUS_READ_BOARD_INFO(device_get_parent(dev), dev, info)); +} + +/** * Determine an NVRAM variable's expected size. * * @param dev A bhnd bus child device. @@ -473,6 +591,7 @@ bhnd_get_chipid(device_t dev) { * * @retval 0 success * @retval ENOENT The requested variable was not found. + * @retval ENODEV No valid NVRAM source could be found. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ @@ -495,6 +614,7 @@ bhnd_nvram_getvarlen(device_t dev, const char *name, size_t *len) * @retval 0 success * @retval ENOENT The requested variable was not found. * @retval EINVAL If @p len does not match the actual variable size. + * @retval ENODEV No valid NVRAM source could be found. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ diff --git a/sys/dev/bhnd/bhnd_bus_if.m b/sys/dev/bhnd/bhnd_bus_if.m index 9762288..35402a4 100644 --- a/sys/dev/bhnd/bhnd_bus_if.m +++ b/sys/dev/bhnd/bhnd_bus_if.m @@ -38,10 +38,10 @@ INTERFACE bhnd_bus; HEADER { /* forward declarations */ + struct bhnd_board_info; struct bhnd_core_info; struct bhnd_chipid; struct bhnd_resource; - struct bhnd_bus_ctx; } CODE { @@ -54,7 +54,14 @@ CODE { { panic("bhnd_bus_get_chipid unimplemented"); } - + + static int + bhnd_bus_null_read_board_info(device_t dev, device_t child, + struct bhnd_board_info *info) + { + panic("bhnd_bus_read_boardinfo unimplemented"); + } + static device_t bhnd_bus_null_find_hostb_device(device_t dev) { @@ -99,7 +106,7 @@ CODE { bhnd_bus_null_get_nvram_var(device_t dev, device_t child, const char *name, void *buf, size_t *size) { - return (ENOENT); + return (ENODEV); } } @@ -177,6 +184,28 @@ METHOD const struct bhnd_chipid * get_chipid { } DEFAULT bhnd_bus_null_get_chipid; /** + * Attempt to read the BHND board identification from the parent bus. + * + * This relies on NVRAM access, and will fail if a valid NVRAM device cannot + * be found, or is not yet attached. + * + * @param dev The parent of @p child. + * @param child The bhnd device requesting board info. + * @param[out] info On success, will be populated with the bhnd(4) device's + * board information. + * + * @retval 0 success + * @retval ENODEV No valid NVRAM source could be found. + * @retval non-zero If reading @p name otherwise fails, a regular unix + * error code will be returned. + */ +METHOD int read_board_info { + device_t dev; + device_t child; + struct bhnd_board_info *info; +} DEFAULT bhnd_bus_null_read_board_info; + +/** * Reset the device's hardware core. * * @param dev The parent of @p child. @@ -400,6 +429,7 @@ METHOD int get_region_addr { * @retval ENOENT The requested variable was not found. * @retval ENOMEM If @p buf is non-NULL and a buffer of @p size is too * small to hold the requested value. + * @retval ENODEV No valid NVRAM source could be found. * @retval non-zero If reading @p name otherwise fails, a regular unix * error code will be returned. */ diff --git a/sys/dev/bhnd/bhnd_debug.h b/sys/dev/bhnd/bhnd_debug.h new file mode 100644 index 0000000..dfe0bd2 --- /dev/null +++ b/sys/dev/bhnd/bhnd_debug.h @@ -0,0 +1,192 @@ +/*- + * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +/* $FreeBSD$ */ + +/* + * This file provides set of macros for logging: + * - BHND_<LEVEL> and + * - BHND_<LEVEL>_DEV + * where LEVEL = {ERROR,WARN,INFO,DEBUG} + * + * BHND_<LEVEL> macros is proxies to printf call and accept same parameters, + * for instance: + * BHND_INFO("register %d has value %d", reg, val); + * + * BHND_<LEVEL>_DEV macros is proxies to device_printf call and accept + * same parameters, for instance: + * BHND_INFO_DEV(dev, "register %d has value %d", reg, val); + * + * All macros contains newline char at the end of each call + * + * ERROR, WARN, INFO messages are printed only if: + * - log message level is lower than BHND_LOGGING (logging threshold) + * + * DEBUG, TRACE messages are printed only if: + * - bootverbose and + * - log message level is lower than BHND_LOGGING (logging threshold) + * + * In addition, for debugging purpose log message contains information about + * file name and line number if BHND_LOGGING is more than BHND_INFO_LEVEL + * + * NOTE: macros starting with underscore (_) are private and should be not used + * + * To override logging (for instance, force tracing), you can use: + * - "options BHND_LOGLEVEL=BHND_TRACE_LEVEL" in kernel configuration + * - "#define BHND_LOGGING BHND_TRACE_LEVEL" in source code file + * + * NOTE: kernel config option doesn't override log level defined on file level, + * so try to avoid "#define BHND_LOGGING" + */ + +#ifndef _BHND_BHND_DEBUG_H_ +#define _BHND_BHND_DEBUG_H_ + +#include <sys/systm.h> + +#include "opt_global.h" + +#define BHND_ERROR_LEVEL 0x00 +#define BHND_ERROR_MSG "ERROR" +#define BHND_WARN_LEVEL 0x10 +#define BHND_WARN_MSG "!WARN" +#define BHND_INFO_LEVEL 0x20 +#define BHND_INFO_MSG " info" +#define BHND_DEBUG_LEVEL 0x30 +#define BHND_DEBUG_MSG "debug" +#define BHND_TRACE_LEVEL 0x40 +#define BHND_TRACE_MSG "trace" + +#if !(defined(BHND_LOGGING)) +#if !(defined(BHND_LOGLEVEL)) +/* By default logging will print only INFO+ message*/ +#define BHND_LOGGING BHND_INFO_LEVEL +#else /* defined(BHND_LOGLEVEL) */ +/* Kernel configuration specifies logging level */ +#define BHND_LOGGING BHND_LOGLEVEL +#endif /* !(defined(BHND_LOGLEVEL)) */ +#endif /* !(defined(BHND_LOGGING)) */ + +#if BHND_LOGGING > BHND_INFO_LEVEL +#define _BHND_PRINT(fn, level, fmt, ...) \ + do { \ + if (level##LEVEL < BHND_DEBUG_LEVEL || bootverbose) \ + fn "[BHND " level##MSG "] %s:%d => " fmt "\n", \ + __func__, __LINE__, ## __VA_ARGS__); \ + } while(0); +#else /* BHND_LOGGING <= BHND_INFO_LEVEL */ +#define _BHND_PRINT(fn, level, fmt, ...) \ + do { \ + if (level##LEVEL < BHND_DEBUG_LEVEL || bootverbose) \ + fn "bhnd: " fmt "\n", ## __VA_ARGS__); \ + } while(0); +#endif /* BHND_LOGGING > BHND_INFO_LEVEL */ + + +#define _BHND_RAWPRINTFN printf( +#define _BHND_DEVPRINTFN(dev) device_printf(dev, + +#define _BHND_LOGPRINT(level, fmt, ...) \ + _BHND_PRINT(_BHND_RAWPRINTFN, level, fmt, ## __VA_ARGS__) +#define _BHND_DEVPRINT(dev, level, fmt, ...) \ + _BHND_PRINT(_BHND_DEVPRINTFN(dev), level, fmt, ## __VA_ARGS__) + +#define BHND_ERROR(fmt, ...) \ + _BHND_LOGPRINT(BHND_ERROR_, fmt, ## __VA_ARGS__); +#define BHND_ERROR_DEV(dev, fmt, ...) \ + _BHND_DEVPRINT(dev, BHND_ERROR_, fmt, ## __VA_ARGS__) + +#if BHND_LOGGING >= BHND_WARN_LEVEL +#define BHND_WARN(fmt, ...) \ + _BHND_LOGPRINT(BHND_WARN_, fmt, ## __VA_ARGS__) +#define BHND_WARN_DEV(dev, fmt, ...) \ + _BHND_DEVPRINT(dev, BHND_WARN_, fmt, ## __VA_ARGS__) + +#if BHND_LOGGING >= BHND_INFO_LEVEL +#define BHND_INFO(fmt, ...) \ + _BHND_LOGPRINT(BHND_INFO_, fmt, ## __VA_ARGS__) +#define BHND_INFO_DEV(dev, fmt, ...) \ + _BHND_DEVPRINT(dev, BHND_INFO_, fmt, ## __VA_ARGS__) + +#if BHND_LOGGING >= BHND_DEBUG_LEVEL +#define BHND_DEBUG(fmt, ...) \ + _BHND_LOGPRINT(BHND_DEBUG_, fmt, ## __VA_ARGS__) +#define BHND_DEBUG_DEV(dev, fmt, ...) \ + _BHND_DEVPRINT(dev, BHND_DEBUG_, fmt, ## __VA_ARGS__) + +#if BHND_LOGGING >= BHND_TRACE_LEVEL +#define BHND_TRACE(fmt, ...) \ + _BHND_LOGPRINT(BHND_TRACE_, fmt, ## __VA_ARGS__) +#define BHND_TRACE_DEV(dev, fmt, ...) \ + _BHND_DEVPRINT(dev, BHND_TRACE_, fmt, ## __VA_ARGS__) + +#endif /* BHND_LOGGING >= BHND_TRACE_LEVEL */ +#endif /* BHND_LOGGING >= BHND_DEBUG_LEVEL */ +#endif /* BHND_LOGGING >= BHND_INFO_LEVEL */ +#endif /* BHND_LOGGING >= BHND_WARN_LEVEL */ + +/* + * Empty defines without device context + */ +#if !(defined(BHND_WARN)) +#define BHND_WARN(fmt, ...); +#endif + +#if !(defined(BHND_INFO)) +#define BHND_INFO(fmt, ...); +#endif + +#if !(defined(BHND_DEBUG)) +#define BHND_DEBUG(fmt, ...); +#endif + +#if !(defined(BHND_TRACE)) +#define BHND_TRACE(fmt, ...); +#endif + +/* + * Empty defines with device context + */ +#if !(defined(BHND_WARN_DEV)) +#define BHND_WARN_DEV(dev, fmt, ...); +#endif + +#if !(defined(BHND_INFO_DEV)) +#define BHND_INFO_DEV(dev, fmt, ...); +#endif + +#if !(defined(BHND_DEBUG_DEV)) +#define BHND_DEBUG_DEV(dev, fmt, ...); +#endif + +#if !(defined(BHND_TRACE_DEV)) +#define BHND_TRACE_DEV(dev, fmt, ...); +#endif + +#endif /* _BHND_BHND_DEBUG_H_ */ diff --git a/sys/dev/bhnd/bhnd_ids.h b/sys/dev/bhnd/bhnd_ids.h index 5000cf7..9a3d807 100644 --- a/sys/dev/bhnd/bhnd_ids.h +++ b/sys/dev/bhnd/bhnd_ids.h @@ -1,10 +1,12 @@ /*- - * Copyright (C) 1999-2013, Broadcom Corporation + * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> + * Copyright (c) 1999-2015, Broadcom Corporation * * This file is derived from the bcmdevs.h header contributed by Broadcom - * to Android's bcmdhd driver module, and the hndsoc.h header distributed with - * with Broadcom's initial brcm80211 Linux driver release, as contributed to - * the Linux staging repository. + * to Android's bcmdhd driver module, later revisions of bcmdevs.h distributed + * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's + * initial brcm80211 Linux driver release as contributed to the Linux staging + * repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -18,16 +20,12 @@ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: bcmdevs.h 387183 2013-02-24 07:42:07Z $ - * * $FreeBSD$ */ #ifndef _BHND_BHND_IDS_H_ #define _BHND_BHND_IDS_H_ - - /* * JEDEC JEP-106 Core Vendor IDs * @@ -669,22 +667,22 @@ /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ -#define BHND_BOARD_GPIO_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */ -#define BHND_BOARD_GPIO_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */ -#define BHND_BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */ -#define BHND_BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */ -#define BHND_BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */ -#define BHND_BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */ -#define BHND_BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ -#define BHND_BOARD_GPIO_12 0x1000 /* gpio 12 */ -#define BHND_BOARD_GPIO_13 0x2000 /* gpio 13 */ -#define BHND_BOARD_GPIO_BTC4_IN 0x0800 /* gpio 11, coex4, in */ -#define BHND_BOARD_GPIO_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */ -#define BHND_BOARD_GPIO_BTC4_STAT 0x4000 /* gpio 14, coex4, status */ -#define BHND_BOARD_GPIO_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */ -#define BHND_BOARD_GPIO_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */ -#define BHND_BOARD_GPIO_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */ -#define BHND_BOARD_GPIO_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */ +#define BHND_GPIO_BOARD_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */ +#define BHND_GPIO_BOARD_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */ +#define BHND_GPIO_BOARD_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */ +#define BHND_GPIO_BOARD_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */ +#define BHND_GPIO_BOARD_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */ +#define BHND_GPIO_BOARD_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */ +#define BHND_GPIO_BOARD_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ +#define BHND_GPIO_BOARD_12 0x1000 /* gpio 12 */ +#define BHND_GPIO_BOARD_13 0x2000 /* gpio 13 */ +#define BHND_GPIO_BOARD_BTC4_IN 0x0800 /* gpio 11, coex4, in */ +#define BHND_GPIO_BOARD_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */ +#define BHND_GPIO_BOARD_BTC4_STAT 0x4000 /* gpio 14, coex4, status */ +#define BHND_GPIO_BOARD_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */ +#define BHND_GPIO_BOARD_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */ +#define BHND_GPIO_BOARD_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */ +#define BHND_GPIO_BOARD_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */ #define BHND_GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43224 0x020 /* bit 5 is BT_IODISABLE */ @@ -700,11 +698,385 @@ #define BHND_CHIPC_MIN_SLOW_CLK 32 /* us Slow clock period */ #define BHND_CHIPC_XTAL_ON_DELAY 1000 /* us crystal power-on delay */ +/* Board Types */ +#define BHND_BOARD_BU4710 0x0400 +#define BHND_BOARD_VSIM4710 0x0401 +#define BHND_BOARD_QT4710 0x0402 + +#define BHND_BOARD_BU4309 0x040a +#define BHND_BOARD_BCM94309CB 0x040b +#define BHND_BOARD_BCM94309MP 0x040c +#define BHND_BOARD_BCM4309AP 0x040d + +#define BHND_BOARD_BCM94302MP 0x040e + +#define BHND_BOARD_BU4306 0x0416 +#define BHND_BOARD_BCM94306CB 0x0417 +#define BHND_BOARD_BCM94306MP 0x0418 + +#define BHND_BOARD_BCM94710D 0x041a +#define BHND_BOARD_BCM94710R1 0x041b +#define BHND_BOARD_BCM94710R4 0x041c +#define BHND_BOARD_BCM94710AP 0x041d + +#define BHND_BOARD_BU2050 0x041f + + +#define BHND_BOARD_BCM94309G 0x0421 + +#define BHND_BOARD_BU4704 0x0423 +#define BHND_BOARD_BU4702 0x0424 + +#define BHND_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */ + + +#define BHND_BOARD_BCM94702MN 0x0428 + +/* BCM4702 1U CompactPCI Board */ +#define BHND_BOARD_BCM94702CPCI 0x0429 + +/* BCM4702 with BCM95380 VLAN Router */ +#define BHND_BOARD_BCM95380RR 0x042a + +/* cb4306 with SiGe PA */ +#define BHND_BOARD_BCM94306CBSG 0x042b + +/* cb4306 with SiGe PA */ +#define BHND_BOARD_PCSG94306 0x042d + +/* bu4704 with sdram */ +#define BHND_BOARD_BU4704SD 0x042e + +/* Dual 11a/11g Router */ +#define BHND_BOARD_BCM94704AGR 0x042f + +/* 11a-only minipci */ +#define BHND_BOARD_BCM94308MP 0x0430 + + + +#define BHND_BOARD_BU4712 0x0444 +#define BHND_BOARD_BU4712SD 0x045d +#define BHND_BOARD_BU4712L 0x045f + +/* BCM4712 boards */ +#define BHND_BOARD_BCM94712AP 0x0445 +#define BHND_BOARD_BCM94712P 0x0446 + +/* BCM4318 boards */ +#define BHND_BOARD_BU4318 0x0447 +#define BHND_BOARD_CB4318 0x0448 +#define BHND_BOARD_MPG4318 0x0449 +#define BHND_BOARD_MP4318 0x044a +#define BHND_BOARD_SD4318 0x044b + +/* BCM4313 boards */ +#define BHND_BOARD_BCM94313BU 0x050f +#define BHND_BOARD_BCM94313HM 0x0510 +#define BHND_BOARD_BCM94313EPA 0x0511 +#define BHND_BOARD_BCM94313HMG 0x051C + +/* BCM63XX boards */ +#define BHND_BOARD_BCM96338 0x6338 +#define BHND_BOARD_BCM96348 0x6348 +#define BHND_BOARD_BCM96358 0x6358 +#define BHND_BOARD_BCM96368 0x6368 + +/* Another mp4306 with SiGe */ +#define BHND_BOARD_BCM94306P 0x044c + +/* mp4303 */ +#define BHND_BOARD_BCM94303MP 0x044e + +/* mpsgh4306 */ +#define BHND_BOARD_BCM94306MPSGH 0x044f + +/* BRCM 4306 w/ Front End Modules */ +#define BHND_BOARD_BCM94306MPM 0x0450 +#define BHND_BOARD_BCM94306MPL 0x0453 + +/* 4712agr */ +#define BHND_BOARD_BCM94712AGR 0x0451 + +/* pcmcia 4303 */ +#define BHND_BOARD_PC4303 0x0454 + +/* 5350K */ +#define BHND_BOARD_BCM95350K 0x0455 + +/* 5350R */ +#define BHND_BOARD_BCM95350R 0x0456 + +/* 4306mplna */ +#define BHND_BOARD_BCM94306MPLNA 0x0457 + +/* 4320 boards */ +#define BHND_BOARD_BU4320 0x0458 +#define BHND_BOARD_BU4320S 0x0459 +#define BHND_BOARD_BCM94320PH 0x045a + +/* 4306mph */ +#define BHND_BOARD_BCM94306MPH 0x045b + +/* 4306pciv */ +#define BHND_BOARD_BCM94306PCIV 0x045c + +#define BHND_BOARD_BU4712SD 0x045d + +#define BHND_BOARD_BCM94320PFLSH 0x045e + +#define BHND_BOARD_BU4712L 0x045f +#define BHND_BOARD_BCM94712LGR 0x0460 +#define BHND_BOARD_BCM94320R 0x0461 + +#define BHND_BOARD_BU5352 0x0462 + +#define BHND_BOARD_BCM94318MPGH 0x0463 + +#define BHND_BOARD_BU4311 0x0464 +#define BHND_BOARD_BCM94311MC 0x0465 +#define BHND_BOARD_BCM94311MCAG 0x0466 + +#define BHND_BOARD_BCM95352GR 0x0467 + +/* bcm95351agr */ +#define BHND_BOARD_BCM95351AGR 0x0470 + +/* bcm94704mpcb */ +#define BHND_BOARD_BCM94704MPCB 0x0472 + +/* 4785 boards */ +#define BHND_BOARD_BU4785 0x0478 + +/* 4321 boards */ +#define BHND_BOARD_BCM4321BU 0x046b +#define BHND_BOARD_BCM4321BUE 0x047c +#define BHND_BOARD_BCM4321MP 0x046c +#define BHND_BOARD_BCM4321CB2 0x046d +#define BHND_BOARD_BCM4321CB2_AG 0x0066 +#define BHND_BOARD_BCM4321MC 0x046e + +/* 4328 boards */ +#define BHND_BOARD_BU4328 0x0481 +#define BHND_BOARD_BCM4328SDG 0x0482 +#define BHND_BOARD_BCM4328SDAG 0x0483 +#define BHND_BOARD_BCM4328UG 0x0484 +#define BHND_BOARD_BCM4328UAG 0x0485 +#define BHND_BOARD_BCM4328PC 0x0486 +#define BHND_BOARD_BCM4328CF 0x0487 + +/* 4325 boards */ +#define BHND_BOARD_BCM94325DEVBU 0x0490 +#define BHND_BOARD_BCM94325BGABU 0x0491 + +#define BHND_BOARD_BCM94325SDGWB 0x0492 + +#define BHND_BOARD_BCM94325SDGMDL 0x04aa +#define BHND_BOARD_BCM94325SDGMDL2 0x04c6 +#define BHND_BOARD_BCM94325SDGMDL3 0x04c9 + +#define BHND_BOARD_BCM94325SDABGWBA 0x04e1 + +/* 4322 boards */ +#define BHND_BOARD_BCM94322MC 0x04a4 +#define BHND_BOARD_BCM94322USB 0x04a8 /* dualband */ +#define BHND_BOARD_BCM94322HM 0x04b0 +#define BHND_BOARD_BCM94322USB2D 0x04bf /* single band discrete front end */ + +/* 4312 boards */ +#define BHND_BOARD_BCM4312MCGSG 0x04b5 + +/* 4315 boards */ +#define BHND_BOARD_BCM94315DEVBU 0x04c2 +#define BHND_BOARD_BCM94315USBGP 0x04c7 +#define BHND_BOARD_BCM94315BGABU 0x04ca +#define BHND_BOARD_BCM94315USBGP41 0x04cb + +/* 4319 boards */ +#define BHND_BOARD_BCM94319DEVBU 0X04e5 +#define BHND_BOARD_BCM94319USB 0X04e6 +#define BHND_BOARD_BCM94319SD 0X04e7 + +/* 4716 boards */ +#define BHND_BOARD_BCM94716NR2 0x04cd + +/* 4319 boards */ +#define BHND_BOARD_BCM94319DEVBU 0X04e5 +#define BHND_BOARD_BCM94319USBNP4L 0X04e6 +#define BHND_BOARD_BCM94319WLUSBN4L 0X04e7 +#define BHND_BOARD_BCM94319SDG 0X04ea +#define BHND_BOARD_BCM94319LCUSBSDN4L 0X04eb +#define BHND_BOARD_BCM94319USBB 0x04ee +#define BHND_BOARD_BCM94319LCSDN4L 0X0507 +#define BHND_BOARD_BCM94319LSUSBN4L 0X0508 +#define BHND_BOARD_BCM94319SDNA4L 0X0517 +#define BHND_BOARD_BCM94319SDELNA4L 0X0518 +#define BHND_BOARD_BCM94319SDELNA6L 0X0539 +#define BHND_BOARD_BCM94319ARCADYAN 0X0546 +#define BHND_BOARD_BCM94319WINDSOR 0x0561 +#define BHND_BOARD_BCM94319MLAP 0x0562 +#define BHND_BOARD_BCM94319SDNA 0x058b +#define BHND_BOARD_BCM94319BHEMU3 0x0563 +#define BHND_BOARD_BCM94319SDHMB 0x058c +#define BHND_BOARD_BCM94319SDBREF 0x05a1 +#define BHND_BOARD_BCM94319USBSDB 0x05a2 + +/* 4329 boards */ +#define BHND_BOARD_BCM94329AGB 0X04b9 +#define BHND_BOARD_BCM94329TDKMDL1 0X04ba +#define BHND_BOARD_BCM94329TDKMDL11 0X04fc +#define BHND_BOARD_BCM94329OLYMPICN18 0X04fd +#define BHND_BOARD_BCM94329OLYMPICN90 0X04fe +#define BHND_BOARD_BCM94329OLYMPICN90U 0X050c +#define BHND_BOARD_BCM94329OLYMPICN90M 0X050b +#define BHND_BOARD_BCM94329AGBF 0X04ff +#define BHND_BOARD_BCM94329OLYMPICX17 0X0504 +#define BHND_BOARD_BCM94329OLYMPICX17M 0X050a +#define BHND_BOARD_BCM94329OLYMPICX17U 0X0509 +#define BHND_BOARD_BCM94329OLYMPICUNO 0X0564 +#define BHND_BOARD_BCM94329MOTOROLA 0X0565 +#define BHND_BOARD_BCM94329OLYMPICLOCO 0X0568 + +/* 4336 SDIO board types */ +#define BHND_BOARD_BCM94336SD_WLBGABU 0x0511 +#define BHND_BOARD_BCM94336SD_WLBGAREF 0x0519 +#define BHND_BOARD_BCM94336SDGP 0x0538 +#define BHND_BOARD_BCM94336SDG 0x0519 +#define BHND_BOARD_BCM94336SDGN 0x0538 +#define BHND_BOARD_BCM94336SDGFC 0x056B + +/* 4330 SDIO board types */ +#define BHND_BOARD_BCM94330SDG 0x0528 +#define BHND_BOARD_BCM94330SD_FCBGABU 0x052e +#define BHND_BOARD_BCM94330SD_WLBGABU 0x052f +#define BHND_BOARD_BCM94330SD_FCBGA 0x0530 +#define BHND_BOARD_BCM94330FCSDAGB 0x0532 +#define BHND_BOARD_BCM94330OLYMPICAMG 0x0549 +#define BHND_BOARD_BCM94330OLYMPICAMGEPA 0x054F +#define BHND_BOARD_BCM94330OLYMPICUNO3 0x0551 +#define BHND_BOARD_BCM94330WLSDAGB 0x0547 +#define BHND_BOARD_BCM94330CSPSDAGBB 0x054A + +/* 43224 boards */ +#define BHND_BOARD_BCM943224X21 0x056e +#define BHND_BOARD_BCM943224X21_FCC 0x00d1 +#define BHND_BOARD_BCM943224X21B 0x00e9 +#define BHND_BOARD_BCM943224M93 0x008b +#define BHND_BOARD_BCM943224M93A 0x0090 +#define BHND_BOARD_BCM943224X16 0x0093 +#define BHND_BOARD_BCM94322X9 0x008d +#define BHND_BOARD_BCM94322M35e 0x008e + +/* 43228 Boards */ +#define BHND_BOARD_BCM943228BU8 0x0540 +#define BHND_BOARD_BCM943228BU9 0x0541 +#define BHND_BOARD_BCM943228BU 0x0542 +#define BHND_BOARD_BCM943227HM4L 0x0543 +#define BHND_BOARD_BCM943227HMB 0x0544 +#define BHND_BOARD_BCM943228HM4L 0x0545 +#define BHND_BOARD_BCM943228SD 0x0573 + +/* 43239 Boards */ +#define BHND_BOARD_BCM943239MOD 0x05ac +#define BHND_BOARD_BCM943239REF 0x05aa + +/* 4331 boards */ +#define BHND_BOARD_BCM94331X19 0x00D6 /* X19B */ +#define BHND_BOARD_BCM94331X28 0x00E4 /* X28 */ +#define BHND_BOARD_BCM94331X28B 0x010E /* X28B */ +#define BHND_BOARD_BCM94331PCIEBT3Ax BCM94331X28 +#define BHND_BOARD_BCM94331X12_2G 0x00EC /* X12 2G */ +#define BHND_BOARD_BCM94331X12_5G 0x00ED /* X12 5G */ +#define BHND_BOARD_BCM94331X29B 0x00EF /* X29B */ +#define BHND_BOARD_BCM94331X29D 0x010F /* X29D */ +#define BHND_BOARD_BCM94331CSAX BCM94331X29B +#define BHND_BOARD_BCM94331X19C 0x00F5 /* X19C */ +#define BHND_BOARD_BCM94331X33 0x00F4 /* X33 */ +#define BHND_BOARD_BCM94331BU 0x0523 +#define BHND_BOARD_BCM94331S9BU 0x0524 +#define BHND_BOARD_BCM94331MC 0x0525 +#define BHND_BOARD_BCM94331MCI 0x0526 +#define BHND_BOARD_BCM94331PCIEBT4 0x0527 +#define BHND_BOARD_BCM94331HM 0x0574 +#define BHND_BOARD_BCM94331PCIEDUAL 0x059B +#define BHND_BOARD_BCM94331MCH5 0x05A9 +#define BHND_BOARD_BCM94331CS 0x05C6 +#define BHND_BOARD_BCM94331CD 0x05DA + +/* 4314 Boards */ +#define BHND_BOARD_BCM94314BU 0x05b1 + +/* 53572 Boards */ +#define BHND_BOARD_BCM953572BU 0x058D +#define BHND_BOARD_BCM953572NR2 0x058E +#define BHND_BOARD_BCM947188NR2 0x058F +#define BHND_BOARD_BCM953572SDRNR2 0x0590 + +/* 43236 boards */ +#define BHND_BOARD_BCM943236OLYMPICSULLEY 0x594 +#define BHND_BOARD_BCM943236PREPROTOBLU2O3 0x5b9 +#define BHND_BOARD_BCM943236USBELNA 0x5f8 + +/* 4314 Boards */ +#define BHND_BOARD_BCM94314BUSDIO 0x05c8 +#define BHND_BOARD_BCM94314BGABU 0x05c9 +#define BHND_BOARD_BCM94314HMEPA 0x05ca +#define BHND_BOARD_BCM94314HMEPABK 0x05cb +#define BHND_BOARD_BCM94314SUHMEPA 0x05cc +#define BHND_BOARD_BCM94314SUHM 0x05cd +#define BHND_BOARD_BCM94314HM 0x05d1 + +/* 4334 Boards */ +#define BHND_BOARD_BCM94334FCAGBI 0x05df +#define BHND_BOARD_BCM94334WLAGBI 0x05dd + +/* 4335 Boards */ +#define BHND_BOARD_BCM94335X52 0x0114 + +/* 4345 Boards */ +#define BHND_BOARD_BCM94345 0x0687 + +/* 4360 Boards */ +#define BHND_BOARD_BCM94360X52C 0X0117 +#define BHND_BOARD_BCM94360X52D 0X0137 +#define BHND_BOARD_BCM94360X29C 0X0112 +#define BHND_BOARD_BCM94360X29CP2 0X0134 +#define BHND_BOARD_BCM94360X51 0x0111 +#define BHND_BOARD_BCM94360X51P2 0x0129 +#define BHND_BOARD_BCM94360X51A 0x0135 +#define BHND_BOARD_BCM94360X51B 0x0136 +#define BHND_BOARD_BCM94360CS 0x061B +#define BHND_BOARD_BCM94360J28_D11AC2G 0x0c00 +#define BHND_BOARD_BCM94360J28_D11AC5G 0x0c01 +#define BHND_BOARD_BCM94360USBH5_D11AC5G 0x06aa + +/* 4350 Boards */ +#define BHND_BOARD_BCM94350X52B 0X0116 +#define BHND_BOARD_BCM94350X14 0X0131 + +/* 43217 Boards */ +#define BHND_BOARD_BCM943217BU 0x05d5 +#define BHND_BOARD_BCM943217HM2L 0x05d6 +#define BHND_BOARD_BCM943217HMITR2L 0x05d7 + +/* 43142 Boards */ +#define BHND_BOARD_BCM943142HM 0x05e0 + /* 43341 Boards */ -#define BCM943341WLABGS_SSID 0x062d +#define BHND_BOARD_BCM943341WLABGS 0x062d /* 43342 Boards */ -#define BCM943342FCAGBI_SSID 0x0641 +#define BHND_BOARD_BCM943342FCAGBI 0x0641 + +/* 43602 Boards, unclear yet what boards will be created. */ +#define BHND_BOARD_BCM943602RSVD1 0x06a5 +#define BHND_BOARD_BCM943602RSVD2 0x06a6 +#define BHND_BOARD_BCM943602X87 0X0133 +#define BHND_BOARD_BCM943602X238 0X0132 + +/* 4354 board types */ +#define BHND_BOARD_BCM94354WLSAGBI 0x06db +#define BHND_BOARD_BCM94354Z 0x0707 /* # of GPIO pins */ #define BHND_BCM43XX_GPIO_NUMPINS 32 diff --git a/sys/dev/bhnd/bhnd_subr.c b/sys/dev/bhnd/bhnd_subr.c index ac8fb0d..ee807b4 100644 --- a/sys/dev/bhnd/bhnd_subr.c +++ b/sys/dev/bhnd/bhnd_subr.c @@ -41,9 +41,18 @@ __FBSDID("$FreeBSD$"); #include <dev/bhnd/cores/chipc/chipcreg.h> +#include "nvram/bhnd_nvram.h" + +#include "bhnd_chipc_if.h" + +#include "bhnd_nvram_if.h" +#include "bhnd_nvram_map.h" + #include "bhndreg.h" #include "bhndvar.h" +static device_t find_nvram_child(device_t dev); + /* BHND core device description table. */ static const struct bhnd_core_desc { uint16_t vendor; @@ -341,6 +350,56 @@ done: } /** + * Walk up the bhnd device hierarchy to locate the root device + * to which the bhndb bridge is attached. + * + * This can be used from within bhnd host bridge drivers to locate the + * actual upstream host device. + * + * @param dev A bhnd device. + * @param bus_class The expected bus (e.g. "pci") to which the bridge root + * should be attached. + * + * @retval device_t if a matching parent device is found. + * @retval NULL @p dev is not attached via a bhndb bus + * @retval NULL no parent device is attached via @p bus_class. + */ +device_t +bhnd_find_bridge_root(device_t dev, devclass_t bus_class) +{ + devclass_t bhndb_class; + device_t parent; + + KASSERT(device_get_devclass(device_get_parent(dev)) == bhnd_devclass, + ("%s not a bhnd device", device_get_nameunit(dev))); + + bhndb_class = devclass_find("bhndb"); + + /* Walk the device tree until we hit a bridge */ + parent = dev; + while ((parent = device_get_parent(parent)) != NULL) { + if (device_get_devclass(parent) == bhndb_class) + break; + } + + /* No bridge? */ + if (parent == NULL) + return (NULL); + + /* Search for a parent attached to the expected bus class */ + while ((parent = device_get_parent(parent)) != NULL) { + device_t bus; + + bus = device_get_parent(parent); + if (bus != NULL && device_get_devclass(bus) == bus_class) + return (parent); + } + + /* Not found */ + return (NULL); +} + +/** * Find the first core in @p cores that matches @p desc. * * @param cores The table to search. @@ -427,6 +486,7 @@ bhnd_core_matches(const struct bhnd_core_info *core, * Return true if the @p chip matches @p desc. * * @param chip A bhnd chip identifier. + * @param board The bhnd board info, or NULL if unavailable. * @param desc A match descriptor to compare against @p chip. * * @retval true if @p chip matches @p match @@ -434,8 +494,19 @@ bhnd_core_matches(const struct bhnd_core_info *core, */ bool bhnd_chip_matches(const struct bhnd_chipid *chip, + const struct bhnd_board_info *board, const struct bhnd_chip_match *desc) { + /* Explicit wildcard match */ + if (desc->match_any) + return (true); + + /* If board_info is missing, but required, we cannot match. */ + if (BHND_CHIP_MATCH_REQ_BOARD_INFO(desc) && board == NULL) + return (false); + + + /* Chip matching */ if (desc->match_id && chip->chip_id != desc->chip_id) return (false); @@ -446,6 +517,23 @@ bhnd_chip_matches(const struct bhnd_chipid *chip, !bhnd_hwrev_matches(chip->chip_rev, &desc->chip_rev)) return (false); + + /* Board info matching */ + if (desc->match_srom_rev && + !bhnd_hwrev_matches(board->board_srom_rev, &desc->board_srom_rev)) + return (false); + + if (desc->match_bvendor && board->board_vendor != desc->board_vendor) + return (false); + + if (desc->match_btype && board->board_type != desc->board_type) + return (false); + + if (desc->match_brev && + !bhnd_hwrev_matches(board->board_rev, &desc->board_rev)) + return (false); + + return (true); } @@ -547,15 +635,43 @@ bhnd_device_lookup(device_t dev, const struct bhnd_device *table, uint32_t bhnd_chip_quirks(device_t dev, const struct bhnd_chip_quirk *table) { + struct bhnd_board_info bi, *board; const struct bhnd_chipid *cid; const struct bhnd_chip_quirk *qent; uint32_t quirks; - + int error; + bool need_boardinfo; + cid = bhnd_get_chipid(dev); quirks = 0; + need_boardinfo = 0; + board = NULL; + + /* Determine whether quirk matching requires board_info; we want to + * avoid fetching board_info for early devices (e.g. ChipCommon) + * that are brought up prior to NVRAM being readable. */ + for (qent = table; !BHND_CHIP_QUIRK_IS_END(qent); qent++) { + if (!BHND_CHIP_MATCH_REQ_BOARD_INFO(&qent->chip)) + continue; + + need_boardinfo = true; + break; + } + /* If required, fetch board info */ + if (need_boardinfo) { + error = bhnd_read_board_info(dev, &bi); + if (!error) { + board = &bi; + } else { + device_printf(dev, "failed to read required board info " + "during quirk matching: %d\n", error); + } + } + + /* Apply all matching quirk flags */ for (qent = table; !BHND_CHIP_QUIRK_IS_END(qent); qent++) { - if (bhnd_chip_matches(cid, &qent->chip)) + if (bhnd_chip_matches(cid, board, &qent->chip)) quirks |= qent->quirks; } @@ -590,16 +706,18 @@ bhnd_device_quirks(device_t dev, const struct bhnd_device *table, return (0); } - /* Quirks aren't a mandatory field */ - if ((qtable = dent->quirks_table) == NULL) - return (0); - - /* Collect matching quirk entries */ - for (qent = qtable; !BHND_DEVICE_QUIRK_IS_END(qent); qent++) { - if (bhnd_hwrev_matches(hwrev, &qent->hwrev)) - quirks |= qent->quirks; + /* Collect matching device quirk entries */ + if ((qtable = dent->quirks_table) != NULL) { + for (qent = qtable; !BHND_DEVICE_QUIRK_IS_END(qent); qent++) { + if (bhnd_hwrev_matches(hwrev, &qent->hwrev)) + quirks |= qent->quirks; + } } + /* Collect matching chip quirk entries */ + if (dent->chip_quirks_table != NULL) + quirks |= bhnd_chip_quirks(dev, dent->chip_quirks_table); + return (quirks); } @@ -824,6 +942,130 @@ bhnd_bus_generic_get_chipid(device_t dev, device_t child) panic("missing BHND_BUS_GET_CHIPID()"); } +/* nvram board_info population macros for bhnd_bus_generic_read_board_info() */ +#define BHND_GV(_dest, _name) \ + bhnd_nvram_getvar(child, BHND_NVAR_ ## _name, &_dest, sizeof(_dest)) + +#define REQ_BHND_GV(_dest, _name) do { \ + if ((error = BHND_GV(_dest, _name))) { \ + device_printf(dev, \ + "error reading " __STRING(_name) ": %d\n", error); \ + return (error); \ + } \ +} while(0) + +#define OPT_BHND_GV(_dest, _name, _default) do { \ + if ((error = BHND_GV(_dest, _name))) { \ + if (error != ENOENT) { \ + device_printf(dev, \ + "error reading " \ + __STRING(_name) ": %d\n", error); \ + return (error); \ + } \ + _dest = _default; \ + } \ +} while(0) + +/** + * Helper function for implementing BHND_BUS_READ_BOARDINFO(). + * + * This implementation populates @p info with information from NVRAM, + * defaulting board_vendor and board_type fields to 0 if the + * requested variables cannot be found. + * + * This behavior is correct for most SoCs, but must be overridden on + * bridged (PCI, PCMCIA, etc) devices to produce a complete bhnd_board_info + * result. + */ +int +bhnd_bus_generic_read_board_info(device_t dev, device_t child, + struct bhnd_board_info *info) +{ + int error; + + OPT_BHND_GV(info->board_vendor, BOARDVENDOR, 0); + OPT_BHND_GV(info->board_type, BOARDTYPE, 0); /* srom >= 2 */ + REQ_BHND_GV(info->board_rev, BOARDREV); + REQ_BHND_GV(info->board_srom_rev,SROMREV); + REQ_BHND_GV(info->board_flags, BOARDFLAGS); + OPT_BHND_GV(info->board_flags2, BOARDFLAGS2, 0); /* srom >= 4 */ + OPT_BHND_GV(info->board_flags3, BOARDFLAGS3, 0); /* srom >= 11 */ + + return (0); +} + +#undef BHND_GV +#undef BHND_GV_REQ +#undef BHND_GV_OPT + + +/** + * Find an NVRAM child device on @p dev, if any. + * + * @retval device_t An NVRAM device. + * @retval NULL If no NVRAM device is found. + */ +static device_t +find_nvram_child(device_t dev) +{ + device_t chipc, nvram; + + /* Look for a directly-attached NVRAM child */ + nvram = device_find_child(dev, "bhnd_nvram", 0); + if (nvram != NULL) + return (nvram); + + /* Remaining checks are only applicable when searching a bhnd(4) + * bus. */ + if (device_get_devclass(dev) != bhnd_devclass) + return (NULL); + + /* Look for a ChipCommon device */ + if ((chipc = bhnd_find_child(dev, BHND_DEVCLASS_CC, -1)) != NULL) { + bhnd_nvram_src_t src; + + /* Query the NVRAM source and determine whether it's + * accessible via the ChipCommon device */ + src = BHND_CHIPC_NVRAM_SRC(chipc); + if (BHND_NVRAM_SRC_CC(src)) + return (chipc); + } + + /* Not found */ + return (NULL); +} + +/** + * Helper function for implementing BHND_BUS_GET_NVRAM_VAR(). + * + * This implementation searches @p dev for a usable NVRAM child device: + * - The first child device implementing the bhnd_nvram devclass is + * returned, otherwise + * - If @p dev is a bhnd(4) bus, a ChipCommon core that advertises an + * attached NVRAM source. + * + * If no usable child device is found on @p dev, the request is delegated to + * the BHND_BUS_GET_NVRAM_VAR() method on the parent of @p dev. + */ +int +bhnd_bus_generic_get_nvram_var(device_t dev, device_t child, const char *name, + void *buf, size_t *size) +{ + device_t nvram; + device_t parent; + + /* Try to find an NVRAM device applicable to @p child */ + if ((nvram = find_nvram_child(dev)) != NULL) + return BHND_NVRAM_GETVAR(nvram, name, buf, size); + + /* Try to delegate to parent */ + if ((parent = device_get_parent(dev)) == NULL) + return (ENODEV); + + return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), child, + name, buf, size)); +} + /** * Helper function for implementing BHND_BUS_ALLOC_RESOURCE(). * diff --git a/sys/dev/bhnd/bhndb/bhndb.c b/sys/dev/bhnd/bhndb/bhndb.c index b75c04a..218827f 100644 --- a/sys/dev/bhnd/bhndb/bhndb.c +++ b/sys/dev/bhnd/bhndb/bhndb.c @@ -1714,26 +1714,6 @@ bhndb_io_resource(struct bhndb_softc *sc, bus_addr_t addr, bus_size_t size, return (dwa); } -/** - * Default bhndb(4) implementation of BHND_BUS_GET_NVRAM_VAR(). - */ -static int -bhndb_get_nvram_var(device_t dev, device_t child, const char *name, - void *buf, size_t *size) -{ - device_t nvram; - - /* Look for a directly-attached NVRAM child */ - nvram = device_find_child(dev, devclass_get_name(bhnd_nvram_devclass), - 0); - if (nvram != NULL) - return (BHND_NVRAM_GETVAR(nvram, name, buf, size)); - - /* Otherwise, delegate to our parent */ - return (BHND_BUS_GET_NVRAM_VAR(device_get_parent(dev), child, - name, buf, size)); -} - /* * BHND_BUS_(READ|WRITE_* implementations */ @@ -1961,7 +1941,7 @@ static device_method_t bhndb_methods[] = { DEVMETHOD(bhnd_bus_get_chipid, bhndb_get_chipid), DEVMETHOD(bhnd_bus_activate_resource, bhndb_activate_bhnd_resource), DEVMETHOD(bhnd_bus_deactivate_resource, bhndb_deactivate_bhnd_resource), - DEVMETHOD(bhnd_bus_get_nvram_var, bhndb_get_nvram_var), + DEVMETHOD(bhnd_bus_get_nvram_var, bhnd_bus_generic_get_nvram_var), DEVMETHOD(bhnd_bus_read_1, bhndb_bus_read_1), DEVMETHOD(bhnd_bus_read_2, bhndb_bus_read_2), DEVMETHOD(bhnd_bus_read_4, bhndb_bus_read_4), diff --git a/sys/dev/bhnd/bhndb/bhndb_if.m b/sys/dev/bhnd/bhndb/bhndb_if.m index ce13a9e..dd03383 100644 --- a/sys/dev/bhnd/bhndb/bhndb_if.m +++ b/sys/dev/bhnd/bhndb/bhndb_if.m @@ -56,6 +56,13 @@ CODE { } static int + bhndb_null_populate_board_info(device_t dev, device_t child, + struct bhnd_board_info *info) + { + panic("bhndb_populate_board_info unimplemented"); + } + + static int bhndb_null_init_full_config(device_t dev, device_t child, const struct bhndb_hw_priority *priority_table) { @@ -102,6 +109,21 @@ METHOD const struct bhnd_chipid * get_chipid { } DEFAULT bhndb_null_get_chipid; /** + * Populate @p info with board info known only to the bridge, + * deferring to any existing initialized fields in @p info. + * + * @param dev The parent device of @p child. + * @param child The bhndb-attached device. + * @param[in,out] info A board info structure previously initialized with any + * information available from NVRAM. + */ +METHOD int populate_board_info { + device_t dev; + device_t child; + struct bhnd_board_info *info; +} DEFAULT bhndb_null_populate_board_info; + +/** * Perform final bridge hardware configuration after @p child has fully * enumerated its children. * diff --git a/sys/dev/bhnd/bhndb/bhndb_pci.c b/sys/dev/bhnd/bhndb/bhndb_pci.c index baf28473..3cadb14 100644 --- a/sys/dev/bhnd/bhndb/bhndb_pci.c +++ b/sys/dev/bhnd/bhndb/bhndb_pci.c @@ -37,9 +37,10 @@ __FBSDID("$FreeBSD$"); * bus (e.g. bcma or siba) via a Broadcom PCI core configured in end-point * mode. * - * This driver handles all host-level PCI interactions with a PCI/PCIe bridge - * core operating in endpoint mode. On the bridged bhnd bus, the PCI core - * device will be managed by a bhnd_pci_hostb driver. + * This driver handles all initial generic host-level PCI interactions with a + * PCI/PCIe bridge core operating in endpoint mode. Once the bridged bhnd(4) + * bus has been enumerated, this driver works in tandem with a core-specific + * bhnd_pci_hostb driver to manage the PCI core. */ #include <sys/param.h> @@ -474,6 +475,54 @@ bhndb_pci_fast_setregwin(struct bhndb_pci_softc *sc, return (0); } +static int +bhndb_pci_populate_board_info(device_t dev, device_t child, + struct bhnd_board_info *info) +{ + struct bhndb_pci_softc *sc; + + sc = device_get_softc(dev); + + /* + * On a subset of Apple BCM4360 modules, always prefer the + * PCI subdevice to the SPROM-supplied boardtype. + * + * TODO: + * + * Broadcom's own drivers implement this override, and then later use + * the remapped BCM4360 board type to determine the required + * board-specific workarounds. + * + * Without access to this hardware, it's unclear why this mapping + * is done, and we must do the same. If we can survey the hardware + * in question, it may be possible to replace this behavior with + * explicit references to the SPROM-supplied boardtype(s) in our + * quirk definitions. + */ + if (pci_get_subvendor(sc->parent) == PCI_VENDOR_APPLE) { + switch (info->board_type) { + case BHND_BOARD_BCM94360X29C: + case BHND_BOARD_BCM94360X29CP2: + case BHND_BOARD_BCM94360X51: + case BHND_BOARD_BCM94360X51P2: + info->board_type = 0; /* allow override below */ + break; + default: + break; + } + } + + /* If NVRAM did not supply vendor/type info, provide the PCI + * subvendor/subdevice values. */ + if (info->board_vendor == 0) + info->board_vendor = pci_get_subvendor(sc->parent); + + if (info->board_type == 0) + info->board_type = pci_get_subdevice(sc->parent); + + return (0); +} + /** * Enable externally managed clocks, if required. * @@ -541,10 +590,6 @@ bhndb_disable_pci_clocks(struct bhndb_pci_softc *sc) if (sc->pci_devclass != BHND_DEVCLASS_PCI) return (0); - // TODO: Check board flags for BFL2_XTALBUFOUTEN? - // TODO: Check PCI core revision? - // TODO: Switch to 'slow' clock? - /* Fetch current config */ gpio_out = pci_read_config(sc->parent, BHNDB_PCI_GPIO_OUT, 4); gpio_en = pci_read_config(sc->parent, BHNDB_PCI_GPIO_OUTEN, 4); @@ -572,6 +617,7 @@ static device_method_t bhndb_pci_methods[] = { /* BHNDB interface */ DEVMETHOD(bhndb_init_full_config, bhndb_pci_init_full_config), DEVMETHOD(bhndb_set_window_addr, bhndb_pci_set_window_addr), + DEVMETHOD(bhndb_populate_board_info, bhndb_pci_populate_board_info), DEVMETHOD_END }; @@ -581,6 +627,7 @@ DEFINE_CLASS_1(bhndb, bhndb_pci_driver, bhndb_pci_methods, MODULE_VERSION(bhndb_pci, 1); MODULE_DEPEND(bhndb_pci, bhnd_pci_hostb, 1, 1, 1); +MODULE_DEPEND(bhndb_pci, bhnd_pcie2_hostb, 1, 1, 1); MODULE_DEPEND(bhndb_pci, pci, 1, 1, 1); MODULE_DEPEND(bhndb_pci, bhndb, 1, 1, 1); MODULE_DEPEND(bhndb_pci, bhnd, 1, 1, 1); diff --git a/sys/dev/bhnd/bhndb/bhndb_pcireg.h b/sys/dev/bhnd/bhndb/bhndb_pcireg.h index eb2dc66..e398cc4 100644 --- a/sys/dev/bhnd/bhndb/bhndb_pcireg.h +++ b/sys/dev/bhnd/bhndb/bhndb_pcireg.h @@ -29,13 +29,13 @@ * * = MAJOR CORE REVISIONS = * - * There have been four revisions to the BAR0/BAR1 memory mappings used + * There have been four revisions to the BAR0 memory mappings used * in BHND PCI/PCIE bridge cores: * * == PCI_V0 == * Applies to: * - PCI (cid=0x804, revision <= 12) - * BAR size: 8KB + * BAR0 size: 8KB * Address Map: * [offset+ size] type description * [0x0000+0x1000] dynamic mapped backplane address space (window 0). @@ -46,7 +46,7 @@ * Applies to: * - PCI (cid=0x804, revision >= 13) * - PCIE (cid=0x820) with ChipCommon (revision <= 31) - * BAR size: 16KB + * BAR0 size: 16KB * Address Map: * [offset+ size] type description * [0x0000+0x1000] dynamic mapped backplane address space (window 0). @@ -57,7 +57,7 @@ * == PCI_V2 == * Applies to: * - PCIE (cid=0x820) with ChipCommon (revision >= 32) - * BAR size: 16KB + * BAR0 size: 16KB * Address Map: * [offset+ size] type description * [0x0000+0x1000] dynamic mapped backplane address space (window 0). @@ -68,7 +68,7 @@ * == PCI_V3 == * Applies to: * - PCIE Gen 2 (cid=0x83c) - * BAR size: 32KB? + * BAR0 size: 32KB * Address Map: * [offset+ size] type description * [0x0000+0x1000] dynamic mapped backplane address space (window 0). @@ -76,6 +76,12 @@ * [0x2000+0x1000] fixed pci/pcie core registers * [0x3000+0x1000] fixed chipcommon core registers * [???] + * BAR1 size: varies + * Address Map: + * [offset+ size] type description + * [0x0000+0x????] fixed ARM tightly-coupled memory (TCM). + * While fullmac chipsets provided a fixed + * 4KB mapping, newer devices will vary. * * = MINOR CORE REVISIONS = * @@ -86,28 +92,6 @@ * == PCI/PCIE Cores Revision >= 14 == * - Mapped the clock CSR into the PCI config space. Refer to * BHND_PCI_CLK_CTL_ST - * - * = Hardware Bugs = - * == BAR1 == - * - * The BHND PCI(e) cores hypothetically support an additional memory mapping - * of the backplane address space via BAR1, but this appears to be subject - * to a hardware bug in which BAR1 is initially configured with a 4 byte - * length. - * - * A work-around for this bug may be possible by writing to the PCI core's - * BAR1 config register (0x4e0), but this requires further research -- I've - * found three sources for information on the BAR1 PCI core configuration that - * may be relevant: - * - The QLogix NetXTreme 10GB PCIe NIC seems to use the same PCIE - * core IP block as is used in other BHND devices. The bxe(4) driver - * contains example initialization code and register constants - * that may apply (e.g. GRC_BAR2_CONFIG/PCI_CONFIG_2_BAR2_SIZE). - * - The publicly available Broadcom BCM440X data sheet (440X-PG02-R) - * appears to (partially) document a Broadcom PCI(e) core that has a - * seemingly compatible programming model. - * - The Android bcmdhd driver sources include a possible work-around - * implementation (writing to 0x4e0) in dhd_pcie.c */ /* Common PCI/PCIE Config Registers */ @@ -181,12 +165,11 @@ #define BHNDB_PCI_V2_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ #define BHNDB_PCI_V2_BAR0_CCREGS_SIZE 0x1000 -/* PCI_V3 */ +/* PCI_V3 (PCIe-G2) */ #define BHNDB_PCI_V3_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ -#define BHNDB_PCI_V3_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ #define BHNDB_PCI_V3_BAR0_WIN1_CONTROL 0x70 /* backplane address space accessed by BAR0/WIN1 */ -#define BHNDB_PCI_V3_BAR0_SIZE 0x8000 /* 32KB BAR0 (?) */ +#define BHNDB_PCI_V3_BAR0_SIZE 0x8000 /* 32KB BAR0 */ #define BHNDB_PCI_V3_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ #define BHNDB_PCI_V3_BAR0_WIN0_SIZE 0x1000 #define BHNDB_PCI_V3_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */ diff --git a/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m b/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m index 0ecaba5..dfaeeef 100644 --- a/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m +++ b/sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m @@ -43,4 +43,23 @@ INTERFACE bhnd_chipc; */ METHOD bhnd_nvram_src_t nvram_src { device_t dev; -}
\ No newline at end of file +} + +/** + * Write @p value with @p mask directly to the chipctrl register. + * + * @param dev A bhnd(4) ChipCommon device. + * @param value The value to write. + * @param mask The mask of bits to be written from @p value. + * + * Drivers should only use function for functionality that is not + * available via another bhnd_chipc() function. + * + * Currently, the only known valid use-case is in implementing a hardware + * work-around for the BCM4321 PCIe rev7 core revision. + */ +METHOD void write_chipctrl { + device_t dev; + uint32_t value; + uint32_t mask; +} diff --git a/sys/dev/bhnd/cores/chipc/chipc.c b/sys/dev/bhnd/cores/chipc/chipc.c index 2f698ce..ea1d7c2 100644 --- a/sys/dev/bhnd/cores/chipc/chipc.c +++ b/sys/dev/bhnd/cores/chipc/chipc.c @@ -65,10 +65,11 @@ static const struct resource_spec chipc_rspec[CHIPC_MAX_RSPEC] = { }; static struct bhnd_device_quirk chipc_quirks[]; +static struct bhnd_chip_quirk chipc_chip_quirks[]; /* Supported device identifiers */ static const struct bhnd_device chipc_devices[] = { - BHND_DEVICE(CC, "CC", chipc_quirks), + BHND_DEVICE(CC, "CC", chipc_quirks, chipc_chip_quirks), BHND_DEVICE_END }; @@ -158,7 +159,6 @@ chipc_attach(device_t dev) sc->dev = dev; sc->quirks = bhnd_device_quirks(dev, chipc_devices, sizeof(chipc_devices[0])); - sc->quirks |= bhnd_chip_quirks(dev, chipc_chip_quirks); CHIPC_LOCK_INIT(sc); @@ -489,20 +489,38 @@ chipc_nvram_setvar(device_t dev, const char *name, const void *buf, return (ENODEV); } +static void +chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) +{ + struct chipc_softc *sc; + uint32_t cctrl; + + sc = device_get_softc(dev); + + CHIPC_LOCK(sc); + + cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); + cctrl = (cctrl & ~mask) | (value | mask); + bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); + + CHIPC_UNLOCK(sc); +} + static device_method_t chipc_methods[] = { /* Device interface */ - DEVMETHOD(device_probe, chipc_probe), - DEVMETHOD(device_attach, chipc_attach), - DEVMETHOD(device_detach, chipc_detach), - DEVMETHOD(device_suspend, chipc_suspend), - DEVMETHOD(device_resume, chipc_resume), + DEVMETHOD(device_probe, chipc_probe), + DEVMETHOD(device_attach, chipc_attach), + DEVMETHOD(device_detach, chipc_detach), + DEVMETHOD(device_suspend, chipc_suspend), + DEVMETHOD(device_resume, chipc_resume), /* ChipCommon interface */ - DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src), + DEVMETHOD(bhnd_chipc_nvram_src, chipc_nvram_src), + DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), /* NVRAM interface */ - DEVMETHOD(bhnd_nvram_getvar, chipc_nvram_getvar), - DEVMETHOD(bhnd_nvram_setvar, chipc_nvram_setvar), + DEVMETHOD(bhnd_nvram_getvar, chipc_nvram_getvar), + DEVMETHOD(bhnd_nvram_setvar, chipc_nvram_setvar), DEVMETHOD_END }; diff --git a/sys/dev/bhnd/cores/pci/bhnd_pci.c b/sys/dev/bhnd/cores/pci/bhnd_pci.c index 3b14ba2..f9adad2 100644 --- a/sys/dev/bhnd/cores/pci/bhnd_pci.c +++ b/sys/dev/bhnd/cores/pci/bhnd_pci.c @@ -68,8 +68,8 @@ static struct bhnd_device_quirk bhnd_pcie_quirks[]; #define BHND_PCI_QUIRKS bhnd_pci_quirks #define BHND_PCIE_QUIRKS bhnd_pcie_quirks -#define BHND_PCI_DEV(_core, _desc, ...) \ - { BHND_DEVICE(_core, _desc, BHND_ ## _core ## _QUIRKS, \ +#define BHND_PCI_DEV(_core, _desc, ...) \ + { BHND_DEVICE(_core, _desc, BHND_ ## _core ## _QUIRKS, NULL, \ ## __VA_ARGS__), BHND_PCI_REGFMT_ ## _core } static const struct bhnd_pci_device { @@ -429,8 +429,7 @@ bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy, int devaddr, int reg) { uint32_t cmd; - uint16_t blk, val; - uint8_t blk_reg; + uint16_t val; int error; if (devaddr == MDIO_DEVADDR_NONE) @@ -438,27 +437,23 @@ bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy, int devaddr, /* Extended register access is only supported for the SerDes device, * using the non-standard C22 extended address mechanism */ - if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR)) + if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) || + phy != BHND_PCIE_PHYADDR_SD) + { return (~0U); - if (phy != BHND_PCIE_PHYADDR_SD || devaddr != BHND_PCIE_DEVAD_SD) - return (~0U); + } /* Enable MDIO access */ BHND_PCI_LOCK(sc); bhnd_pcie_mdio_enable(sc); - /* Determine the block and register values */ - blk = (reg & BHND_PCIE_SD_ADDREXT_BLK_MASK); - blk_reg = (reg & BHND_PCIE_SD_ADDREXT_REG_MASK); - /* Write the block address to the address extension register */ - cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | - (blk & BHND_PCIE_MDIODATA_DATA_MASK); + cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr; if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd))) goto cleanup; /* Issue the read */ - cmd = BHND_PCIE_MDIODATA_ADDR(phy, blk_reg); + cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg); error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val); cleanup: @@ -476,8 +471,6 @@ bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy, int devaddr, int reg, int val) { uint32_t cmd; - uint16_t blk; - uint8_t blk_reg; int error; if (devaddr == MDIO_DEVADDR_NONE) @@ -485,27 +478,23 @@ bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy, int devaddr, /* Extended register access is only supported for the SerDes device, * using the non-standard C22 extended address mechanism */ - if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR)) + if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) || + phy != BHND_PCIE_PHYADDR_SD) + { return (~0U); - if (phy != BHND_PCIE_PHYADDR_SD || devaddr != BHND_PCIE_DEVAD_SD) - return (~0U); + } /* Enable MDIO access */ BHND_PCI_LOCK(sc); bhnd_pcie_mdio_enable(sc); - /* Determine the block and register values */ - blk = (reg & BHND_PCIE_SD_ADDREXT_BLK_MASK); - blk_reg = (reg & BHND_PCIE_SD_ADDREXT_REG_MASK); - /* Write the block address to the address extension register */ - cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | - (blk & BHND_PCIE_MDIODATA_DATA_MASK); + cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr; if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd))) goto cleanup; /* Issue the write */ - cmd = BHND_PCIE_MDIODATA_ADDR(phy, blk_reg) | + cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) | (val & BHND_PCIE_MDIODATA_DATA_MASK); error = bhnd_pcie_mdio_cmd_write(sc, cmd); diff --git a/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c b/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c index 7d1cb9f..119ab8a 100644 --- a/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c +++ b/sys/dev/bhnd/cores/pci/bhnd_pci_hostb.c @@ -56,28 +56,44 @@ __FBSDID("$FreeBSD$"); #include <dev/bhnd/bhnd.h> -#include "bhnd_pcireg.h" -#include "bhnd_pci_hostbvar.h" +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> -#define BHND_PCI_ASSERT_QUIRK(_sc, _name) \ - KASSERT((_sc)->quirks & (_name), ("quirk " __STRING(_name) " not set")) +#include <dev/bhnd/cores/chipc/chipc.h> +#include <dev/bhnd/cores/chipc/chipcreg.h> -#define BHND_PCI_DEV(_core, _quirks) \ - BHND_DEVICE(_core, "", _quirks, BHND_DF_HOSTB) +#include "bhnd_pcireg.h" +#include "bhnd_pci_hostbvar.h" static const struct bhnd_device_quirk bhnd_pci_quirks[]; static const struct bhnd_device_quirk bhnd_pcie_quirks[]; +static const struct bhnd_chip_quirk bhnd_pci_chip_quirks[]; +static const struct bhnd_chip_quirk bhnd_pcie_chip_quirks[]; + +/* Device driver work-around variations */ +typedef enum { + BHND_PCI_WAR_ATTACH, /**< apply attach workarounds */ + BHND_PCI_WAR_RESUME, /**< apply resume workarounds */ + BHND_PCI_WAR_SUSPEND, /**< apply suspend workarounds */ + BHND_PCI_WAR_DETACH /**< apply detach workarounds */ +} bhnd_pci_war_state; static int bhnd_pci_wars_early_once(struct bhnd_pcihb_softc *sc); -static int bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc); -static int bhnd_pci_wars_hwdown(struct bhnd_pcihb_softc *sc); +static int bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc, + bhnd_pci_war_state state); +static int bhnd_pci_wars_hwdown(struct bhnd_pcihb_softc *sc, + bhnd_pci_war_state state); /* * device/quirk tables */ + +#define BHND_PCI_DEV(_core, _quirks, _chip_quirks) \ + BHND_DEVICE(_core, "", _quirks, _chip_quirks, BHND_DF_HOSTB) + static const struct bhnd_device bhnd_pci_devs[] = { - BHND_PCI_DEV(PCI, bhnd_pci_quirks), - BHND_PCI_DEV(PCIE, bhnd_pcie_quirks), + BHND_PCI_DEV(PCI, bhnd_pci_quirks, bhnd_pci_chip_quirks), + BHND_PCI_DEV(PCIE, bhnd_pcie_quirks, bhnd_pcie_chip_quirks), BHND_DEVICE_END }; @@ -88,12 +104,22 @@ static const struct bhnd_device_quirk bhnd_pci_quirks[] = { BHND_DEVICE_QUIRK_END }; +static const struct bhnd_chip_quirk bhnd_pci_chip_quirks[] = { + /* BCM4321CB2 boards that require 960ns latency timer override */ + {{ BHND_CHIP_BTYPE(BCM4321CB2) }, + BHND_PCI_QUIRK_960NS_LATTIM_OVR }, + {{ BHND_CHIP_BTYPE(BCM4321CB2_AG) }, + BHND_PCI_QUIRK_960NS_LATTIM_OVR }, + + BHND_CHIP_QUIRK_END +}; + static const struct bhnd_device_quirk bhnd_pcie_quirks[] = { { BHND_HWREV_EQ (0), BHND_PCIE_QUIRK_SDR9_L0s_HANG }, - { BHND_HWREV_RANGE (0, 1), BHND_PCIE_QUIRK_UR_STATUS_FIX }, + { BHND_HWREV_RANGE (0,1), BHND_PCIE_QUIRK_UR_STATUS_FIX }, { BHND_HWREV_EQ (1), BHND_PCIE_QUIRK_PCIPM_REQEN }, - { BHND_HWREV_RANGE (3, 5), BHND_PCIE_QUIRK_ASPM_OVR | + { BHND_HWREV_RANGE (3,5), BHND_PCIE_QUIRK_ASPM_OVR | BHND_PCIE_QUIRK_SDR9_POLARITY | BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY }, @@ -101,24 +127,49 @@ static const struct bhnd_device_quirk bhnd_pcie_quirks[] = { { BHND_HWREV_GTE (6), BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET }, { BHND_HWREV_EQ (7), BHND_PCIE_QUIRK_SERDES_NOPLLDOWN }, { BHND_HWREV_GTE (8), BHND_PCIE_QUIRK_L1_TIMER_PERF }, - { BHND_HWREV_GTE (10), BHND_PCIE_QUIRK_SD_C22_EXTADDR }, + + { BHND_HWREV_LTE (17), BHND_PCIE_QUIRK_MAX_MRRS_128 }, + BHND_DEVICE_QUIRK_END }; -// Quirk handling TODO -// WARs for the following are not yet implemented: -// - BHND_PCIE_QUIRK_ASPM_OVR -// - BHND_PCIE_QUIRK_SERDES_NOPLLDOWN -// Quirks (and WARs) for the following are not yet defined: -// - Power savings via MDIO BLK1/PWR_MGMT3 on PCIe hwrev 15-20, 21-22 -// - WOWL PME enable/disable -// - 4360 PCIe SerDes Tx amplitude/deemphasis (vendor Apple, boards -// BCM94360X51P2, BCM94360X51A). -// - PCI latency timer (boards CB2_4321_BOARD, CB2_4321_AG_BOARD) -// - Max SerDes TX drive strength (vendor Apple, pcie >= rev10, -// board BCM94322X9) -// - 700mV SerDes TX drive strength (chipid BCM4331, boards BCM94331X19, -// BCM94331X28, BCM94331X29B, BCM94331X19C) +static const struct bhnd_chip_quirk bhnd_pcie_chip_quirks[] = { + /* Apple boards on which BHND_BFL2_PCIEWAR_OVR should be assumed + * to be set. */ + {{ BHND_CHIP_BVENDOR (PCI_VENDOR_APPLE), + BHND_CHIP_SROMREV (HWREV_EQ(4)), + BHND_CHIP_BREV (HWREV_LTE(0x71)) }, + BHND_PCIE_QUIRK_BFL2_PCIEWAR_EN }, + + /* Apple BCM4322 boards that require 700mV SerDes TX drive strength. */ + {{ BHND_CHIP_BVT (PCI_VENDOR_APPLE, BCM94322X9) }, + BHND_PCIE_QUIRK_SERDES_TXDRV_700MV }, + + /* Apple BCM4331 board-specific quirks */ +#define BHND_APPLE_4331_QUIRK(_board, ...) \ + {{ BHND_CHIP_ID (4331), \ + BHND_CHIP_BVT (PCI_VENDOR_APPLE, _board), }, \ + __VA_ARGS__ } + + BHND_APPLE_4331_QUIRK(BCM94331X19, + BHND_PCIE_QUIRK_SERDES_TXDRV_MAX|BHND_PCIE_QUIRK_DEFAULT_MRRS_512), + + BHND_APPLE_4331_QUIRK(BCM94331X28, + BHND_PCIE_QUIRK_SERDES_TXDRV_MAX|BHND_PCIE_QUIRK_DEFAULT_MRRS_512), + BHND_APPLE_4331_QUIRK(BCM94331X28B, BHND_PCIE_QUIRK_DEFAULT_MRRS_512), + + BHND_APPLE_4331_QUIRK(BCM94331X29B, + BHND_PCIE_QUIRK_SERDES_TXDRV_MAX|BHND_PCIE_QUIRK_DEFAULT_MRRS_512), + + BHND_APPLE_4331_QUIRK(BCM94331X19C, + BHND_PCIE_QUIRK_SERDES_TXDRV_MAX|BHND_PCIE_QUIRK_DEFAULT_MRRS_512), + + BHND_APPLE_4331_QUIRK(BCM94331X29D, BHND_PCIE_QUIRK_DEFAULT_MRRS_512), + BHND_APPLE_4331_QUIRK(BCM94331X33, BHND_PCIE_QUIRK_DEFAULT_MRRS_512), +#undef BHND_APPLE_4331_QUIRK + + BHND_CHIP_QUIRK_END +}; #define BHND_PCI_SOFTC(_sc) (&((_sc)->common)) @@ -146,6 +197,13 @@ static const struct bhnd_device_quirk bhnd_pcie_quirks[] = { #define BHND_PCI_MDIO_WRITE(_sc, _phy, _reg, _val) \ bhnd_pcie_mdio_write(BHND_PCI_SOFTC(_sc), (_phy), (_reg), (_val)) +#define BHND_PCI_MDIO_READ_EXT(_sc, _phy, _devaddr, _reg) \ + bhnd_pcie_mdio_read_ext(BHND_PCI_SOFTC(_sc), (_phy), (_devaddr), (_reg)) + +#define BHND_PCI_MDIO_WRITE_EXT(_sc, _phy, _devaddr, _reg, _val) \ + bhnd_pcie_mdio_write_ext(BHND_PCI_SOFTC(_sc), (_phy), \ + (_devaddr), (_reg), (_val)) + #define BPCI_REG_SET(_regv, _attr, _val) \ BHND_PCI_REG_SET((_regv), BHND_ ## _attr, (_val)) @@ -167,26 +225,34 @@ bhnd_pci_hostb_attach(device_t dev) int error; sc = device_get_softc(dev); + sc->dev = dev; sc->quirks = bhnd_device_quirks(dev, bhnd_pci_devs, sizeof(bhnd_pci_devs[0])); + /* Find the host PCI bridge device */ + sc->pci_dev = bhnd_find_bridge_root(dev, devclass_find("pci")); + if (sc->pci_dev == NULL) { + device_printf(dev, "parent pci bridge device not found\n"); + return (ENXIO); + } + + /* Common setup */ if ((error = bhnd_pci_generic_attach(dev))) return (error); /* Apply early single-shot work-arounds */ - if ((error = bhnd_pci_wars_early_once(sc))) { - bhnd_pci_generic_detach(dev); - return (error); - } + if ((error = bhnd_pci_wars_early_once(sc))) + goto failed; /* Apply attach/resume work-arounds */ - if ((error = bhnd_pci_wars_hwup(sc))) { - bhnd_pci_generic_detach(dev); - return (error); - } - + if ((error = bhnd_pci_wars_hwup(sc, BHND_PCI_WAR_ATTACH))) + goto failed; return (0); + +failed: + bhnd_pci_generic_detach(dev); + return (error); } static int @@ -198,7 +264,7 @@ bhnd_pci_hostb_detach(device_t dev) sc = device_get_softc(dev); /* Apply suspend/detach work-arounds */ - if ((error = bhnd_pci_wars_hwdown(sc))) + if ((error = bhnd_pci_wars_hwdown(sc, BHND_PCI_WAR_DETACH))) return (error); return (bhnd_pci_generic_detach(dev)); @@ -213,7 +279,7 @@ bhnd_pci_hostb_suspend(device_t dev) sc = device_get_softc(dev); /* Apply suspend/detach work-arounds */ - if ((error = bhnd_pci_wars_hwdown(sc))) + if ((error = bhnd_pci_wars_hwdown(sc, BHND_PCI_WAR_SUSPEND))) return (error); return (bhnd_pci_generic_suspend(dev)); @@ -231,7 +297,7 @@ bhnd_pci_hostb_resume(device_t dev) return (error); /* Apply attach/resume work-arounds */ - if ((error = bhnd_pci_wars_hwup(sc))) { + if ((error = bhnd_pci_wars_hwup(sc, BHND_PCI_WAR_RESUME))) { bhnd_pci_generic_detach(dev); return (error); } @@ -250,6 +316,36 @@ bhnd_pci_hostb_resume(device_t dev) static int bhnd_pci_wars_early_once(struct bhnd_pcihb_softc *sc) { + int error; + + /* Set PCI latency timer */ + if (sc->quirks & BHND_PCI_QUIRK_960NS_LATTIM_OVR) { + pci_write_config(sc->pci_dev, PCIR_LATTIMER, 0x20 /* 960ns */, + 1); + } + + /* Determine whether ASPM/CLKREQ should be forced on, or forced off. */ + if (sc->quirks & BHND_PCIE_QUIRK_ASPM_OVR) { + struct bhnd_board_info board; + bool aspm_en; + + /* Fetch board info */ + if ((error = bhnd_read_board_info(sc->dev, &board))) + return (error); + + /* Check board flags */ + aspm_en = true; + if (board.board_flags2 & BHND_BFL2_PCIEWAR_OVR) + aspm_en = false; + + /* Early Apple devices did not (but should have) set + * BHND_BFL2_PCIEWAR_OVR in SPROM. */ + if (sc->quirks & BHND_PCIE_QUIRK_BFL2_PCIEWAR_EN) + aspm_en = false; + + sc->aspm_quirk_override.aspm_en = aspm_en; + } + /* Determine correct polarity by observing the attach-time PCIe PHY * link status. This is used later to reset/force the SerDes * polarity */ @@ -257,12 +353,23 @@ bhnd_pci_wars_early_once(struct bhnd_pcihb_softc *sc) uint32_t st; bool inv; - st = BHND_PCI_PROTO_READ_4(sc, BHND_PCIE_PLP_STATUSREG); inv = ((st & BHND_PCIE_PLP_POLARITY_INV) != 0); sc->sdr9_quirk_polarity.inv = inv; } + /* Override maximum read request size */ + if (bhnd_get_class(sc->dev) == BHND_DEVCLASS_PCIE) { + int msize; + + msize = 128; /* compatible with all PCIe-G1 core revisions */ + if (sc->quirks & BHND_PCIE_QUIRK_DEFAULT_MRRS_512) + msize = 512; + + if (pci_set_max_read_req(sc->pci_dev, msize) == 0) + panic("set mrrs on non-PCIe device"); + } + return (0); } @@ -271,7 +378,7 @@ bhnd_pci_wars_early_once(struct bhnd_pcihb_softc *sc) * of the bridge device. */ static int -bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc) +bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc, bhnd_pci_war_state state) { /* Note that the order here matters; these work-arounds * should not be re-ordered without careful review of their @@ -394,6 +501,47 @@ bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc) BHND_PCI_PROTO_WRITE_4(sc, BHND_PCIE_DLLP_PMTHRESHREG, pmt); } + /* Override ASPM/ECPM settings in SPROM shadow and PCIER_LINK_CTL */ + if (sc->quirks & BHND_PCIE_QUIRK_ASPM_OVR) { + bus_size_t reg; + uint16_t cfg; + + /* Set ASPM L1/L0s flags in SPROM shadow */ + reg = BHND_PCIE_SPROM_SHADOW + BHND_PCIE_SRSH_ASPM_OFFSET; + cfg = BHND_PCI_READ_2(sc, reg); + + if (sc->aspm_quirk_override.aspm_en) + cfg |= BHND_PCIE_SRSH_ASPM_ENB; + else + cfg &= ~BHND_PCIE_SRSH_ASPM_ENB; + + BHND_PCI_WRITE_2(sc, reg, cfg); + + + /* Set ASPM/ECPM (CLKREQ) flags in PCIe link control register */ + cfg = pcie_read_config(sc->pci_dev, PCIER_LINK_CTL, 2); + + if (sc->aspm_quirk_override.aspm_en) + cfg |= PCIEM_LINK_CTL_ASPMC; + else + cfg &= ~PCIEM_LINK_CTL_ASPMC; + + cfg &= ~PCIEM_LINK_CTL_ECPM; /* CLKREQ# */ + + pcie_write_config(sc->pci_dev, PCIER_LINK_CTL, cfg, 2); + + /* Set CLKREQ (ECPM) flags in SPROM shadow */ + reg = BHND_PCIE_SPROM_SHADOW + BHND_PCIE_SRSH_CLKREQ_OFFSET_R5; + cfg = BHND_PCI_READ_2(sc, reg); + + if (sc->aspm_quirk_override.aspm_en) + cfg |= BHND_PCIE_SRSH_CLKREQ_ENB; + else + cfg &= ~BHND_PCIE_SRSH_CLKREQ_ENB; + + BHND_PCI_WRITE_2(sc, reg, cfg); + } + /* Enable L23READY_EXIT_NOPRST if not already set in SPROM. */ if (sc->quirks & BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET) { bus_size_t reg; @@ -410,6 +558,54 @@ bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc) } } + /* Disable SerDes PLL down */ + if (sc->quirks & BHND_PCIE_QUIRK_SERDES_NOPLLDOWN) { + device_t bhnd, chipc; + bus_size_t reg; + + bhnd = device_get_parent(sc->dev); + chipc = bhnd_find_child(bhnd, BHND_DEVCLASS_CC, 0); + KASSERT(chipc != NULL, ("missing chipcommon device")); + + /* Write SerDes PLL disable flag to the ChipCommon core */ + BHND_CHIPC_WRITE_CHIPCTRL(chipc, CHIPCTRL_4321_PLL_DOWN, + CHIPCTRL_4321_PLL_DOWN); + + /* Clear SPROM shadow backdoor register */ + reg = BHND_PCIE_SPROM_SHADOW + BHND_PCIE_SRSH_BD_OFFSET; + BHND_PCI_WRITE_2(sc, reg, 0); + } + + /* Adjust TX drive strength and pre-emphasis coefficient */ + if (sc->quirks & BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST) { + uint16_t txdrv; + + /* Fetch current TX driver parameters */ + txdrv = BHND_PCI_MDIO_READ_EXT(sc, BHND_PCIE_PHYADDR_SD, + BHND_PCIE_SD_REGS_TX0, BHND_PCIE_SD_TX_DRIVER); + + /* Set 700mV drive strength */ + if (sc->quirks & BHND_PCIE_QUIRK_SERDES_TXDRV_700MV) { + txdrv = BPCI_REG_SET(txdrv, PCIE_SD_TX_DRIVER_P2_COEFF, + BHND_PCIE_APPLE_TX_P2_COEFF_700MV); + + txdrv = BPCI_REG_SET(txdrv, PCIE_SD_TX_DRIVER_IDRIVER, + BHND_PCIE_APPLE_TX_IDRIVER_700MV); + } + + /* ... or, set max drive strength */ + if (sc->quirks & BHND_PCIE_QUIRK_SERDES_TXDRV_MAX) { + txdrv = BPCI_REG_SET(txdrv, PCIE_SD_TX_DRIVER_P2_COEFF, + BHND_PCIE_APPLE_TX_P2_COEFF_MAX); + + txdrv = BPCI_REG_SET(txdrv, PCIE_SD_TX_DRIVER_IDRIVER, + BHND_PCIE_APPLE_TX_IDRIVER_MAX); + } + + BHND_PCI_MDIO_WRITE_EXT(sc, BHND_PCIE_PHYADDR_SD, + BHND_PCIE_SD_REGS_TX0, BHND_PCIE_SD_TX_DRIVER, txdrv); + } + return (0); } @@ -418,8 +614,8 @@ bhnd_pci_wars_hwup(struct bhnd_pcihb_softc *sc) * of the bridge device. */ static int -bhnd_pci_wars_hwdown(struct bhnd_pcihb_softc *sc) -{ +bhnd_pci_wars_hwdown(struct bhnd_pcihb_softc *sc, bhnd_pci_war_state state) +{ /* Reduce L1 timer for better power savings. * TODO: We could enable/disable this on demand for better power * savings if we tie this to HT clock request handling */ @@ -430,6 +626,19 @@ bhnd_pci_wars_hwdown(struct bhnd_pcihb_softc *sc) BHND_PCI_PROTO_WRITE_4(sc, BHND_PCIE_DLLP_PMTHRESHREG, pmt); } + /* Enable CLKREQ (ECPM). If suspending, also disable ASPM L1 entry */ + if (sc->quirks & BHND_PCIE_QUIRK_ASPM_OVR) { + uint16_t lcreg; + + lcreg = pcie_read_config(sc->pci_dev, PCIER_LINK_CTL, 2); + + lcreg |= PCIEM_LINK_CTL_ECPM; /* CLKREQ# */ + if (state == BHND_PCI_WAR_SUSPEND) + lcreg &= ~PCIEM_LINK_CTL_ASPMC_L1; + + pcie_write_config(sc->pci_dev, PCIER_LINK_CTL, lcreg, 2); + } + return (0); } @@ -443,10 +652,9 @@ static device_method_t bhnd_pci_hostb_methods[] = { DEVMETHOD_END }; -DEFINE_CLASS_1(bhnd_pci_hostb, bhnd_pci_hostb_driver, bhnd_pci_hostb_methods, +DEFINE_CLASS_1(bhnd_hostb, bhnd_pci_hostb_driver, bhnd_pci_hostb_methods, sizeof(struct bhnd_pcihb_softc), bhnd_pci_driver); - -DRIVER_MODULE(bhnd_hostb, bhnd, bhnd_pci_hostb_driver, bhnd_hostb_devclass, 0, 0); +DRIVER_MODULE(bhnd_pci_hostb, bhnd, bhnd_pci_hostb_driver, bhnd_hostb_devclass, 0, 0); MODULE_VERSION(bhnd_pci_hostb, 1); MODULE_DEPEND(bhnd_pci_hostb, bhnd, 1, 1, 1); diff --git a/sys/dev/bhnd/cores/pci/bhnd_pci_hostbvar.h b/sys/dev/bhnd/cores/pci/bhnd_pci_hostbvar.h index 3e7bb57..9fab99e 100644 --- a/sys/dev/bhnd/cores/pci/bhnd_pci_hostbvar.h +++ b/sys/dev/bhnd/cores/pci/bhnd_pci_hostbvar.h @@ -43,7 +43,7 @@ DECLARE_CLASS(bhnd_pci_hostb_driver); -/* +/** * PCI/PCIe-Gen1 endpoint-mode device quirks */ enum { @@ -56,7 +56,6 @@ enum { */ BHND_PCI_QUIRK_SBTOPCI2_PREF_BURST = (1<<1), - /** * SBTOPCI_RC_READMULTI must be set on the SSB_PCICORE_SBTOPCI2 * register. @@ -74,18 +73,24 @@ enum { BHND_PCI_QUIRK_CLKRUN_DSBL = (1<<3), /** + * On PCI-attached BCM4321CB* boards, the PCI latency timer must be set + * to 960ns on initial attach. + */ + BHND_PCI_QUIRK_960NS_LATTIM_OVR = (1<<4), + + /** * TLP workaround for unmatched address handling is required. * * This TLP workaround will enable setting of the PCIe UR status bit * on memory access to an unmatched address. */ - BHND_PCIE_QUIRK_UR_STATUS_FIX = (1<<4), + BHND_PCIE_QUIRK_UR_STATUS_FIX = (1<<5), /** * PCI-PM power management must be explicitly enabled via * the data link control register. */ - BHND_PCIE_QUIRK_PCIPM_REQEN = (1<<5), + BHND_PCIE_QUIRK_PCIPM_REQEN = (1<<6), /** * Fix L0s to L0 exit transition on SerDes <= rev9 devices. @@ -98,53 +103,64 @@ enum { * filters must be tweaked to ensure the CDR has fully stabilized * before asserting receive sequencer completion. */ - BHND_PCIE_QUIRK_SDR9_L0s_HANG = (1<<6), + BHND_PCIE_QUIRK_SDR9_L0s_HANG = (1<<7), /** * The idle time for entering L1 low-power state must be * explicitly set (to 114ns) to fix slow L1->L0 transition issues. */ - BHND_PCIE_QUIRK_L1_IDLE_THRESH = (1<<7), + BHND_PCIE_QUIRK_L1_IDLE_THRESH = (1<<8), /** * The ASPM L1 entry timer should be extended for better performance, * and restored for better power savings. */ - BHND_PCIE_QUIRK_L1_TIMER_PERF = (1<<8), + BHND_PCIE_QUIRK_L1_TIMER_PERF = (1<<9), /** * ASPM and ECPM settings must be overridden manually. + * Applies to 4311B0/4321B1 chipset revisions. * * The override behavior is controlled by the BHND_BFL2_PCIEWAR_OVR - * flag. If this flag is set, ASPM/CLKREQ should be overridden as - * enabled; otherwise, they should be overridden as disabled. + * flag; if set, ASPM and CLKREQ should be explicitly disabled. If not + * set, they should be explicitly enabled. * * Attach/Resume: - * - Set SRSH_ASPM_ENB flag in the SPROM ASPM register. - * - Set ASPM L0S/L1 in the PCIER_LINK_CTL register. - * - Set SRSH_CLKREQ_ENB flag in the SPROM CLKREQ_REV5 register. - * - Clear ECPM in the PCIER_LINK_CTL register. + * - Update SRSH_ASPM_ENB flag in the SPROM ASPM register. + * - Update SRSH_CLKREQ_ENB flag in the SPROM CLKREQ_REV5 + * register. + * - Update ASPM L0S/L1 flags in PCIER_LINK_CTL register. + * - Clear CLKREQ (ECPM) flag in PCIER_LINK_CTL register. * - * Detach/Suspend: - * - - * - When the device enters D3 state, or system enters S3/S4 state, - * clear ASPM L1 in the PCIER_LINK_CTL register. + * Suspend: + * - Clear ASPM L1 flag in the PCIER_LINK_CTL register. + * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. + * + * Detach: + * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. */ - BHND_PCIE_QUIRK_ASPM_OVR = (1<<9), - + BHND_PCIE_QUIRK_ASPM_OVR = (1<<10), + + /** + * A subset of Apple devices did not set the BHND_BFL2_PCIEWAR_OVR + * flag in SPROM; on these devices, the BHND_BFL2_PCIEWAR_OVR flag + * should always be treated as if set. + */ + BHND_PCIE_QUIRK_BFL2_PCIEWAR_EN = (1<<11), + /** * Fix SerDes polarity on SerDes <= rev9 devices. * * The SerDes polarity must be saved at device attachment, and * restored on suspend/resume. */ - BHND_PCIE_QUIRK_SDR9_POLARITY = (1<<10), + BHND_PCIE_QUIRK_SDR9_POLARITY = (1<<12), /** * SerDes PLL down flag must be manually disabled (by ChipCommon) on * resume. */ - BHND_PCIE_QUIRK_SERDES_NOPLLDOWN = (1<<11), + BHND_PCIE_QUIRK_SERDES_NOPLLDOWN = (1<<13), /** * On attach and resume, consult the SPROM to determine whether @@ -152,31 +168,77 @@ enum { * * If L23READY_EXIT_NOPRST is not already set in the SPROM, set it */ - BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET = (1<<12), + BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET = (1<<14), /** - * The PCIe SerDes supports non-standard extended MDIO register access. + * The PCIe SerDes PLL must be configured to not retry the startup + * sequence upon frequency detection failure on SerDes <= rev9 devices * - * The PCIe SerDes supports access to extended MDIO registers via - * a non-standard Clause 22 address extension mechanism. + * The issue this workaround resolves is unknown. */ - BHND_PCIE_QUIRK_SD_C22_EXTADDR = (1<<13), - + BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY = (1<<15), + /** - * The PCIe SerDes PLL must be configured to not retry the startup - * sequence upon frequency detection failure on SerDes <= rev9 devices + * Common flag for quirks that require PCIe SerDes TX + * drive strength adjustment. * - * The issue this workaround resolves has not be determined. + * Only applies to PCIe >= rev10 devices. */ - BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY = (1<<14), + BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST = (1<<16), + + /** + * On Apple BCM94322X9 devices, the PCIe SerDes TX drive strength + * should be set to 700mV. + * + * The exact issue is unknown, but presumably this workaround + * resolves signal integrity issues with these devices. + * + * Only applies to PCIe >= rev10 devices. + */ + BHND_PCIE_QUIRK_SERDES_TXDRV_700MV = (1<<17) | + BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, + + /** + * On some Apple BCM4331-based devices, the PCIe SerDes TX drive + * strength should be set to its maximum. + * + * The exact issue is unknown, but presumably this workaround + * resolves signal integrity issues with these devices. + */ + BHND_PCIE_QUIRK_SERDES_TXDRV_MAX = (1<<18) | + BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, + + /** + * PCIe cores prior to rev18 do not support an MRRS larger than + * 128 bytes. + */ + BHND_PCIE_QUIRK_MAX_MRRS_128 = (1<<19), + + /** + * The PCIe core should be configured with an MRRS of 512 bytes. + */ + BHND_PCIE_QUIRK_DEFAULT_MRRS_512 = (1<<20), }; /** * bhnd_pci_hostb driver instance state. */ struct bhnd_pcihb_softc { - struct bhnd_pci_softc common; /**< common bhnd_pci state */ - uint32_t quirks; /**< hostb device quirks */ + struct bhnd_pci_softc common; /**< common bhnd_pci state */ + device_t dev; + device_t pci_dev; /**< host PCI device */ + uint32_t quirks; /**< hostb device quirks */ + + /** BHND_PCIE_QUIRK_ASPM_OVR state. */ + struct { + /** + * ASPM/CLKREQ override setting. + * + * If true, ASPM/CLKREQ should be overridden as enabled. + * If false, ASPM/CLKREQ should be overridden as disabled. + */ + bool aspm_en; + } aspm_quirk_override; /** BHND_PCIE_QUIRK_SDR9_POLARITY state. */ struct { @@ -191,4 +253,4 @@ struct bhnd_pcihb_softc { }; -#endif /* _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ */
\ No newline at end of file +#endif /* _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ */ diff --git a/sys/dev/bhnd/cores/pci/bhnd_pcib.c b/sys/dev/bhnd/cores/pci/bhnd_pcib.c index 7549a0e..4983a38 100644 --- a/sys/dev/bhnd/cores/pci/bhnd_pcib.c +++ b/sys/dev/bhnd/cores/pci/bhnd_pcib.c @@ -86,8 +86,10 @@ static device_method_t bhnd_pcib_methods[] = { DEVMETHOD_END }; -DEFINE_CLASS_1(bhnd_pcib, bhnd_pcib_driver, bhnd_pcib_methods, sizeof(struct bhnd_pcib_softc), bhnd_pci_driver); -DRIVER_MODULE(bhnd_pcib, bhnd, bhnd_pcib_driver, bhnd_hostb_devclass, 0, 0); +DEFINE_CLASS_1(pcib, bhnd_pcib_driver, bhnd_pcib_methods, sizeof(struct bhnd_pcib_softc), bhnd_pci_driver); + +static devclass_t pcib_devclass; +DRIVER_MODULE(bhnd_pcib, bhnd, bhnd_pcib_driver, pcib_devclass, 0, 0); MODULE_VERSION(bhnd_pcib, 1); MODULE_DEPEND(bhnd_pcib, bhnd, 1, 1, 1); diff --git a/sys/dev/bhnd/cores/pci/bhnd_pcireg.h b/sys/dev/bhnd/cores/pci/bhnd_pcireg.h index d55fdd8..9b3e526 100644 --- a/sys/dev/bhnd/cores/pci/bhnd_pcireg.h +++ b/sys/dev/bhnd/cores/pci/bhnd_pcireg.h @@ -321,12 +321,8 @@ * PCIe-G1 SerDes MDIO Registers (>= rev10) */ #define BHND_PCIE_PHYADDR_SD 0x0 /* serdes PHY address */ -#define BHND_PCIE_DEVAD_SD 0x1 /* serdes pseudo-devad (PMA) recognized by - the bhnd_mdio_pcie driver */ #define BHND_PCIE_SD_ADDREXT 0x1F /* serdes address extension register */ -#define BHND_PCIE_SD_ADDREXT_BLK_MASK 0xFFF0 /* register block mask */ -#define BHND_PCIE_SD_ADDREXT_REG_MASK 0x000F /* register address mask */ #define BHND_PCIE_SD_REGS_IEEE0 0x0000 /* IEEE0 AN CTRL block */ #define BHND_PCIE_SD_REGS_IEEE1 0x0010 /* IEEE1 AN ADV block */ @@ -335,10 +331,30 @@ #define BHND_PCIE_SD_REGS_BLK2 0x8020 /* ??? */ #define BHND_PCIE_SD_REGS_BLK3 0x8030 /* ??? */ #define BHND_PCIE_SD_REGS_BLK4 0x8040 /* ??? */ -#define BHND_PCIE_SD_REGS_TXPLL 0x8080 /* TXPLL register block */ -#define BHND_PCIE_SD_REGS_TXCTRL0 0x8200 /* ??? */ -#define BHND_PCIE_SD_REGS_SERDESID 0x8310 /* ??? */ -#define BHND_PCIE_SD_REGS_RXCTRL0 0x8400 /* ??? */ +#define BHND_PCIE_SD_REGS_PLL 0x8080 /* (?) PLL register block */ +#define BHND_PCIE_SD_REGS_TX0 0x8200 /* (?) Transmit 0 block */ +#define BHND_PCIE_SD_REGS_SERDESID 0x8310 /* ??? */ +#define BHND_PCIE_SD_REGS_RX0 0x8400 /* (?) Receive 0 register block */ + +/* The interpretation of these registers and values are just guesses based on + * the limited available documentation from other (likely similar) Broadcom + * SerDes IP. */ +#define BHND_PCIE_SD_TX_DRIVER 0x17 /* TX transmit driver register */ +#define BHND_PCIE_SD_TX_DRIVER_IFIR_MASK 0x000E /* unconfirmed */ +#define BHND_PCIE_SD_TX_DRIVER_IFIR_SHIFT 1 /* unconfirmed */ +#define BHND_PCIE_SD_TX_DRIVER_IPRE_MASK 0x00F0 /* unconfirmed */ +#define BHND_PCIE_SD_TX_DRIVER_IPRE_SHIFT 4 /* unconfirmed */ +#define BHND_PCIE_SD_TX_DRIVER_IDRIVER_MASK 0x0F00 /* unconfirmed */ +#define BHND_PCIE_SD_TX_DRIVER_IDRIVER_SHIFT 8 /* unconfirmed */ +#define BHND_PCIE_SD_TX_DRIVER_P2_COEFF_SHIFT 12 /* unconfirmed */ +#define BHND_PCIE_SD_TX_DRIVER_P2_COEFF_MASK 0xF000 /* unconfirmed */ + +/* Constants used with host bridge quirk handling */ +#define BHND_PCIE_APPLE_TX_P2_COEFF_MAX 0x7 /* 9.6dB pre-emphassis coeff (???) */ +#define BHND_PCIE_APPLE_TX_IDRIVER_MAX 0xF /* 1400mV voltage range (???) */ + +#define BHND_PCIE_APPLE_TX_P2_COEFF_700MV 0x7 /* 2.3dB pre-emphassis coeff (???) */ +#define BHND_PCIE_APPLE_TX_IDRIVER_700MV 0x0 /* 670mV voltage range (???) */ /* * PCIe-G1 SerDes-R9 MDIO Registers (<= rev9) @@ -389,23 +405,12 @@ #define BHND_PCIE_SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */ #define BHND_PCIE_SRSH_PCIE_MISC_CONFIG 10 /* word 5 */ #define BHND_PCIE_SRSH_L23READY_EXIT_NOPRST 0x8000 /* bit 15 */ -#define BHND_PCIE_SRSH_CLKREQ_OFFSET_REV5 40 /* word 20 for srom rev <= 5 */ -#define BHND_PCIE_SRSH_CLKREQ_OFFSET_REV8 104 /* word 52 for srom rev 8 */ +#define BHND_PCIE_SRSH_CLKREQ_OFFSET_R5 40 /* word 20 for srom rev <= 5 */ +#define BHND_PCIE_SRSH_CLKREQ_OFFSET_R8 104 /* word 52 for srom rev 8 */ #define BHND_PCIE_SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ #define BHND_PCIE_SRSH_BD_OFFSET 12 /* word 6 */ #define BHND_PCIE_SRSH_AUTOINIT_OFFSET 36 /* auto initialization enable */ -/* Linkcontrol reg offset in PCIE Cap */ -#define BHND_PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */ -#define BHND_PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */ -#define BHND_PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */ -#define BHND_PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */ - -#define BHND_PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */ -#define BHND_PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */ -#define BHND_PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */ -#define BHND_PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */ - /* Status reg PCIE_PLP_STATUSREG */ #define BHND_PCIE_PLP_POLARITY_INV 0x10 /* lane polarity is inverted */ diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c new file mode 100644 index 0000000..1dc3005 --- /dev/null +++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2.c @@ -0,0 +1,289 @@ +/*- + * Copyright (c) 2015 Landon Fuller <landon@landonf.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * Broadcom Common PCIe-G2 Support. + * + * This base driver implementation is shared by the bhnd_pcib_g2 (root complex) + * and bhnd_pci_hostb_g2 (host bridge) drivers. + */ + +#include <sys/param.h> +#include <sys/malloc.h> +#include <sys/kernel.h> +#include <sys/bus.h> +#include <sys/module.h> +#include <sys/systm.h> + +#include <machine/bus.h> +#include <sys/rman.h> +#include <machine/resource.h> + +#include <dev/bhnd/bhnd.h> +#include <dev/mdio/mdio.h> + +#include "bhnd_pcie2_reg.h" +#include "bhnd_pcie2_var.h" + +static struct bhnd_device_quirk bhnd_pcie2_quirks[]; + +#define BHND_PCIE_DEV(_core, _desc, ...) \ + BHND_DEVICE(_core, _desc, bhnd_pcie2_quirks, NULL, ## __VA_ARGS__) + +static const struct bhnd_device bhnd_pcie2_devs[] = { + BHND_PCIE_DEV(PCIE2, "PCIe-G2 Host-PCI bridge", BHND_DF_HOSTB), + BHND_PCIE_DEV(PCIE2, "PCIe-G2 PCI-BHND bridge"), + + BHND_DEVICE_END +}; + +/* Device quirks tables */ +static struct bhnd_device_quirk bhnd_pcie2_quirks[] = { + BHND_DEVICE_QUIRK_END +}; + +int +bhnd_pcie2_generic_probe(device_t dev) +{ + const struct bhnd_device *id; + + id = bhnd_device_lookup(dev, bhnd_pcie2_devs, + sizeof(bhnd_pcie2_devs[0])); + if (id == NULL) + return (ENXIO); + + bhnd_set_custom_core_desc(dev, id->desc); + return (BUS_PROBE_DEFAULT); +} + +int +bhnd_pcie2_generic_attach(device_t dev) +{ + struct bhnd_pcie2_softc *sc; + int error; + + sc = device_get_softc(dev); + sc->dev = dev; + sc->quirks = bhnd_device_quirks(dev, bhnd_pcie2_devs, + sizeof(bhnd_pcie2_devs[0])); + + /* Allocate bus resources */ + sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, + RF_ACTIVE); + if (sc->mem_res == NULL) + return (ENXIO); + + BHND_PCIE2_LOCK_INIT(sc); + + /* Probe and attach children */ + if ((error = bus_generic_attach(dev))) + goto cleanup; + + return (0); + +cleanup: + bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); + BHND_PCIE2_LOCK_DESTROY(sc); + + return (error); +} + +int +bhnd_pcie2_generic_detach(device_t dev) +{ + struct bhnd_pcie2_softc *sc; + int error; + + sc = device_get_softc(dev); + + if ((error = bus_generic_detach(dev))) + return (error); + + bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); + + BHND_PCIE2_LOCK_DESTROY(sc); + + return (0); +} + +static struct resource_list * +bhnd_pcie2_get_resource_list(device_t dev, device_t child) +{ + struct bhnd_pcie2_devinfo *dinfo; + + if (device_get_parent(child) != dev) + return (NULL); + + dinfo = device_get_ivars(child); + return (&dinfo->resources); +} + +static device_t +bhnd_pcie2_add_child(device_t dev, u_int order, const char *name, int unit) +{ + struct bhnd_pcie2_devinfo *dinfo; + device_t child; + + child = device_add_child_ordered(dev, order, name, unit); + if (child == NULL) + return (NULL); + + dinfo = malloc(sizeof(struct bhnd_pcie2_devinfo), M_DEVBUF, M_NOWAIT); + if (dinfo == NULL) { + device_delete_child(dev, child); + return (NULL); + } + + resource_list_init(&dinfo->resources); + + device_set_ivars(child, dinfo); + return (child); +} + +static void +bhnd_pcie2_child_deleted(device_t dev, device_t child) +{ + struct bhnd_pcie2_devinfo *dinfo; + + if (device_get_parent(child) != dev) + return; + + dinfo = device_get_ivars(child); + if (dinfo != NULL) { + resource_list_free(&dinfo->resources); + free(dinfo, M_DEVBUF); + } + + device_set_ivars(child, NULL); +} + +int +bhnd_pcie2_generic_suspend(device_t dev) +{ + return (bus_generic_suspend(dev)); +} + +int +bhnd_pcie2_generic_resume(device_t dev) +{ + return (bus_generic_resume(dev)); +} + +/** + * Read a 32-bit PCIe TLP/DLLP/PLP protocol register. + * + * @param sc The bhndb_pci driver state. + * @param addr The protocol register offset. + */ +uint32_t +bhnd_pcie2_read_proto_reg(struct bhnd_pcie2_softc *sc, uint32_t addr) +{ + // TODO + return (ENXIO); +} + +/** + * Write a 32-bit PCIe TLP/DLLP/PLP protocol register value. + * + * @param sc The bhndb_pci driver state. + * @param addr The protocol register offset. + * @param val The value to write to @p addr. + */ +void +bhnd_pcie2_write_proto_reg(struct bhnd_pcie2_softc *sc, uint32_t addr, + uint32_t val) +{ + // TODO + panic("unimplemented"); +} + +int +bhnd_pcie2_mdio_read(struct bhnd_pcie2_softc *sc, int phy, int reg) +{ + // TODO + return (ENXIO); +} + +int +bhnd_pcie2_mdio_write(struct bhnd_pcie2_softc *sc, int phy, int reg, int val) +{ + // TODO + return (ENXIO); +} + +int +bhnd_pcie2_mdio_read_ext(struct bhnd_pcie2_softc *sc, int phy, int devaddr, + int reg) +{ + // TODO + return (ENXIO); +} + +int +bhnd_pcie2_mdio_write_ext(struct bhnd_pcie2_softc *sc, int phy, int devaddr, + int reg, int val) +{ + // TODO + return (ENXIO); +} + +static device_method_t bhnd_pcie2_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bhnd_pcie2_generic_probe), + DEVMETHOD(device_attach, bhnd_pcie2_generic_attach), + DEVMETHOD(device_detach, bhnd_pcie2_generic_detach), + DEVMETHOD(device_suspend, bhnd_pcie2_generic_suspend), + DEVMETHOD(device_resume, bhnd_pcie2_generic_resume), + + /* Bus interface */ + DEVMETHOD(bus_add_child, bhnd_pcie2_add_child), + DEVMETHOD(bus_child_deleted, bhnd_pcie2_child_deleted), + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_get_resource_list, bhnd_pcie2_get_resource_list), + DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), + DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), + DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), + + DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), + DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), + DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), + DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), + DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), + + DEVMETHOD_END +}; + +DEFINE_CLASS_0(bhnd_pcie2, bhnd_pcie2_driver, bhnd_pcie2_methods, + sizeof(struct bhnd_pcie2_softc)); +MODULE_DEPEND(bhnd_pcie2, bhnd, 1, 1, 1); +MODULE_DEPEND(bhnd_pcie2, pci, 1, 1, 1); +MODULE_VERSION(bhnd_pcie2, 1); diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c new file mode 100644 index 0000000..aa5b86b --- /dev/null +++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c @@ -0,0 +1,254 @@ +/*- + * Copyright (c) 2015 Landon Fuller <landon@landonf.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * Broadcom BHND PCIe-Gen2 PCI-Host Bridge. + * + * This driver handles all interactions with PCIe-G2 bridge cores operating in + * endpoint mode. + * + * Host-level PCI operations are handled at the bhndb bridge level by the + * bhndb_pci driver. + */ + +// TODO +// +// A full survey of known quirks/work-arounds has not been completed. +// +// Work-arounds for the following are not yet implemented: +// - BHND_PCIE2_QUIRK_SERDES_TXDRV_DEEMPH +// 4360 PCIe SerDes Tx amplitude/deemphasis (vendor Apple, boards +// BCM94360X51P2, BCM94360X51A) + +#include <sys/param.h> +#include <sys/kernel.h> + +#include <sys/malloc.h> + +#include <sys/bus.h> +#include <sys/module.h> + +#include <sys/systm.h> + +#include <machine/bus.h> +#include <sys/rman.h> +#include <machine/resource.h> + +#include <dev/bhnd/bhnd.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> + +#include "bhnd_pcie2_reg.h" +#include "bhnd_pcie2_hostbvar.h" + +static const struct bhnd_device_quirk bhnd_pcie2_quirks[]; +static const struct bhnd_chip_quirk bhnd_pcie2_chip_quirks[]; + + +static int bhnd_pcie2_wars_early_once(struct bhnd_pcie2hb_softc *sc); +static int bhnd_pcie2_wars_hwup(struct bhnd_pcie2hb_softc *sc); +static int bhnd_pcie2_wars_hwdown(struct bhnd_pcie2hb_softc *sc); + +/* + * device/quirk tables + */ + +#define BHND_PCI_DEV(_core, _quirks, _chip_quirks) \ + BHND_DEVICE(_core, "", _quirks, _chip_quirks, BHND_DF_HOSTB) + +static const struct bhnd_device bhnd_pcie2_devs[] = { + BHND_PCI_DEV(PCIE2, bhnd_pcie2_quirks, bhnd_pcie2_chip_quirks), + BHND_DEVICE_END +}; + +static const struct bhnd_device_quirk bhnd_pcie2_quirks[] = { + BHND_DEVICE_QUIRK_END +}; + +static const struct bhnd_chip_quirk bhnd_pcie2_chip_quirks[] = { + /* Apple BCM4360 boards that require adjusting TX amplitude and + * differential output de-emphasis of the PCIe SerDes */ + {{ BHND_CHIP_BVT (PCI_VENDOR_APPLE, BCM94360X51P2) }, + BHND_PCIE2_QUIRK_SERDES_TXDRV_DEEMPH }, + {{ BHND_CHIP_BVT (PCI_VENDOR_APPLE, BCM94360X51A) }, + BHND_PCIE2_QUIRK_SERDES_TXDRV_DEEMPH }, + + BHND_CHIP_QUIRK_END +}; + +static int +bhnd_pcie2_hostb_attach(device_t dev) +{ + struct bhnd_pcie2hb_softc *sc; + int error; + + sc = device_get_softc(dev); + sc->dev = dev; + sc->quirks = bhnd_device_quirks(dev, bhnd_pcie2_devs, + sizeof(bhnd_pcie2_devs[0])); + + /* Find the host PCI bridge device */ + sc->pci_dev = bhnd_find_bridge_root(dev, devclass_find("pci")); + if (sc->pci_dev == NULL) { + device_printf(dev, "parent pci bridge device not found\n"); + return (ENXIO); + } + + /* Common setup */ + if ((error = bhnd_pcie2_generic_attach(dev))) + return (error); + + + /* Apply early single-shot work-arounds */ + if ((error = bhnd_pcie2_wars_early_once(sc))) + goto failed; + + + /* Apply attach/resume work-arounds */ + if ((error = bhnd_pcie2_wars_hwup(sc))) + goto failed; + + + return (0); + +failed: + bhnd_pcie2_generic_detach(dev); + return (error); +} + +static int +bhnd_pcie2_hostb_detach(device_t dev) +{ + struct bhnd_pcie2hb_softc *sc; + int error; + + sc = device_get_softc(dev); + + /* Apply suspend/detach work-arounds */ + if ((error = bhnd_pcie2_wars_hwdown(sc))) + return (error); + + return (bhnd_pcie2_generic_detach(dev)); +} + +static int +bhnd_pcie2_hostb_suspend(device_t dev) +{ + struct bhnd_pcie2hb_softc *sc; + int error; + + sc = device_get_softc(dev); + + /* Apply suspend/detach work-arounds */ + if ((error = bhnd_pcie2_wars_hwdown(sc))) + return (error); + + return (bhnd_pcie2_generic_suspend(dev)); +} + +static int +bhnd_pcie2_hostb_resume(device_t dev) +{ + struct bhnd_pcie2hb_softc *sc; + int error; + + sc = device_get_softc(dev); + + if ((error = bhnd_pcie2_generic_resume(dev))) + return (error); + + /* Apply attach/resume work-arounds */ + if ((error = bhnd_pcie2_wars_hwup(sc))) { + bhnd_pcie2_generic_detach(dev); + return (error); + } + + return (0); +} + +/** + * Apply any hardware work-arounds that must be executed exactly once, early in + * the attach process. + * + * This must be called after core enumeration and discovery of all applicable + * quirks, but prior to probe/attach of any cores, parsing of + * SPROM, etc. + */ +static int +bhnd_pcie2_wars_early_once(struct bhnd_pcie2hb_softc *sc) +{ + // TODO + return (ENXIO); +} + +/** + * Apply any hardware workarounds that are required upon attach or resume + * of the bridge device. + */ +static int +bhnd_pcie2_wars_hwup(struct bhnd_pcie2hb_softc *sc) +{ + // TODO + return (ENXIO); +} + +/** + * Apply any hardware workarounds that are required upon detach or suspend + * of the bridge device. + */ +static int +bhnd_pcie2_wars_hwdown(struct bhnd_pcie2hb_softc *sc) +{ + // TODO + return (ENXIO); +} + +static device_method_t bhnd_pcie2_hostb_methods[] = { + /* Device interface */ + DEVMETHOD(device_attach, bhnd_pcie2_hostb_attach), + DEVMETHOD(device_detach, bhnd_pcie2_hostb_detach), + DEVMETHOD(device_suspend, bhnd_pcie2_hostb_suspend), + DEVMETHOD(device_resume, bhnd_pcie2_hostb_resume), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(bhnd_hostb, bhnd_pcie2_hostb_driver, + bhnd_pcie2_hostb_methods, sizeof(struct bhnd_pcie2hb_softc), + bhnd_pcie2_driver); + +DRIVER_MODULE(bhnd_pcie2_hostb, bhnd, bhnd_pcie2_hostb_driver, bhnd_hostb_devclass, 0, 0); + +MODULE_VERSION(bhnd_pcie2_hostb, 1); +MODULE_DEPEND(bhnd_pcie2_hostb, bhnd, 1, 1, 1); +MODULE_DEPEND(bhnd_pcie2_hostb, bhnd_pcie2, 1, 1, 1); diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostbvar.h b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostbvar.h new file mode 100644 index 0000000..97bbba7 --- /dev/null +++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_hostbvar.h @@ -0,0 +1,72 @@ +/*- + * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef _BHND_CORES_PCIE2_BHND_PCI_HOSTBVAR_H_ +#define _BHND_CORES_PCIE2_BHND_PCI_HOSTBVAR_H_ + +/* + * PCIe-Gen2 Host Bridge definitions. + */ + +#include <sys/param.h> +#include <sys/bus.h> + +#include "bhnd_pcie2_var.h" + +DECLARE_CLASS(bhnd_pcie2_hostb_driver); + + +/* + * PCIe-Gen2 endpoint-mode device quirks + */ +enum { + /** + * The PCIe SerDes output should be configured with an amplitude of + * 1214mVpp and a differential output de-emphasis of -8.46dB. + * + * The exact issue this workaround resolves is unknown. + */ + BHND_PCIE2_QUIRK_SERDES_TXDRV_DEEMPH = (1<<0), +}; + + +/** + * bhnd_pci_hostb driver instance state. + */ +struct bhnd_pcie2hb_softc { + struct bhnd_pcie2_softc common; /**< common bhnd_pcie2 state */ + device_t dev; + device_t pci_dev; /**< host PCI device */ + uint32_t quirks; /**< hostb device quirks */ +}; + + +#endif /* _BHND_CORES_PCIE2_BHND_PCI_HOSTBVAR_H_ */
\ No newline at end of file diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h new file mode 100644 index 0000000..c6c5518 --- /dev/null +++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h @@ -0,0 +1,228 @@ +/*- + * Copyright (c) 2016 Landon Fuller <landon@landonf.org> + * Copyright (c) 2015 Broadcom Corporation + * All rights reserved. + * + * This file is derived from the pcie_core.h and pcie2_core.h headers + * from Broadcom's Linux driver sources as distributed by dd-wrt. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD$ + */ + +#ifndef _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ +#define _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ + +#define BHND_PCIE2_CLK_CONTROL 0x000 + +#define BHND_PCIE2_RC_PM_CONTROL 0x004 +#define BHND_PCIE2_RC_PM_STATUS 0x008 +#define BHND_PCIE2_EP_PM_CONTROL 0x00C +#define BHND_PCIE2_EP_PM_STATUS 0x010 +#define BHND_PCIE2_EP_LTR_CONTROL 0x014 +#define BHND_PCIE2_EP_LTR_STATUS 0x018 +#define BHND_PCIE2_EP_OBFF_STATUS 0x01C +#define BHND_PCIE2_PCIE_ERR_STATUS 0x020 +#define BHND_PCIE2_RC_AXI_CONFIG 0x100 +#define BHND_PCIE2_EP_AXI_CONFIG 0x104 +#define BHND_PCIE2_RXDEBUG_STATUS0 0x108 +#define BHND_PCIE2_RXDEBUG_CONTROL0 0x10C + +#define BHND_PCIE2_CONFIGINDADDR 0x120 +#define BHND_PCIE2_CONFIGINDDATA 0x124 + +#define BHND_PCIE2_CFG_ADDR 0x1F8 +#define BHND_PCIE2_CFG_DATA 0x1FC + +#define BHND_PCIE2_SYS_EQ_PAGE 0x200 +#define BHND_PCIE2_SYS_MSI_PAGE 0x204 +#define BHND_PCIE2_SYS_MSI_INTREN 0x208 +#define BHND_PCIE2_SYS_MSI_CTRL0 0x210 +#define BHND_PCIE2_SYS_MSI_CTRL1 0x214 +#define BHND_PCIE2_SYS_MSI_CTRL2 0x218 +#define BHND_PCIE2_SYS_MSI_CTRL3 0x21C +#define BHND_PCIE2_SYS_MSI_CTRL4 0x220 +#define BHND_PCIE2_SYS_MSI_CTRL5 0x224 + +#define BHND_PCIE2_SYS_EQ_HEAD0 0x250 +#define BHND_PCIE2_SYS_EQ_TAIL0 0x254 +#define BHND_PCIE2_SYS_EQ_HEAD1 0x258 +#define BHND_PCIE2_SYS_EQ_TAIL1 0x25C +#define BHND_PCIE2_SYS_EQ_HEAD2 0x260 +#define BHND_PCIE2_SYS_EQ_TAIL2 0x264 +#define BHND_PCIE2_SYS_EQ_HEAD3 0x268 +#define BHND_PCIE2_SYS_EQ_TAIL3 0x26C +#define BHND_PCIE2_SYS_EQ_HEAD4 0x270 +#define BHND_PCIE2_SYS_EQ_TAIL4 0x274 +#define BHND_PCIE2_SYS_EQ_HEAD5 0x278 +#define BHND_PCIE2_SYS_EQ_TAIL5 0x27C + +#define BHND_PCIE2_SYS_RC_INTX_EN 0x330 +#define BHND_PCIE2_SYS_RC_INTX_CSR 0x334 +#define BHND_PCIE2_SYS_MSI_REQ 0x340 +#define BHND_PCIE2_SYS_HOST_INTR_EN 0x344 +#define BHND_PCIE2_SYS_HOST_INTR_CSR 0x348 +#define BHND_PCIE2_SYS_HOST_INTR0 0x350 +#define BHND_PCIE2_SYS_HOST_INTR1 0x354 +#define BHND_PCIE2_SYS_HOST_INTR2 0x358 +#define BHND_PCIE2_SYS_HOST_INTR3 0x35C +#define BHND_PCIE2_SYS_EP_INT_EN0 0x360 +#define BHND_PCIE2_SYS_EP_INT_EN1 0x364 +#define BHND_PCIE2_SYS_EP_INT_CSR0 0x370 +#define BHND_PCIE2_SYS_EP_INT_CSR1 0x374 + +#define BHND_PCIE2_MDIO_CTL 0x128 /**< mdio control */ +#define BHND_PCIE2_MDIO_WRDATA 0x12C /**< mdio data write */ +#define BHND_PCIE2_MDIO_RDDATA 0x130 /**< mdio data read */ + + +/* DMA doorbell registers (>= rev5) */ +#define BHND_PCIE2_DB0_HOST2DEV0 0x140 +#define BHND_PCIE2_DB0_HOST2DEV1 0x144 +#define BHND_PCIE2_DB0_DEV2HOST0 0x148 +#define BHND_PCIE2_DB0_DEV2HOST1 0x14C + +#define BHND_PCIE2_DB1_HOST2DEV0 0x150 +#define BHND_PCIE2_DB1_HOST2DEV1 0x154 +#define BHND_PCIE2_DB1_DEV2HOST0 0x158 +#define BHND_PCIE2_DB1_DEV2HOST1 0x15C + +#define BHND_PCIE2_DB2_HOST2DEV0 0x160 +#define BHND_PCIE2_DB2_HOST2DEV1 0x164 +#define BHND_PCIE2_DB2_DEV2HOST0 0x168 +#define BHND_PCIE2_DB2_DEV2HOST1 0x16C + +#define BHND_PCIE2_DB3_HOST2DEV0 0x170 +#define BHND_PCIE2_DB3_HOST2DEV1 0x174 +#define BHND_PCIE2_DB3_DEV2HOST0 0x178 +#define BHND_PCIE2_DB3_DEV2HOST1 0x17C + +#define BHND_PCIE2_DATAINTF 0x180 +#define BHND_PCIE2_INTRLAZY0_DEV2HOST 0x188 +#define BHND_PCIE2_INTRLAZY0_HOST2DEV 0x18c +#define BHND_PCIE2_INTSTAT0_HOST2DEV 0x190 +#define BHND_PCIE2_INTMASK0_HOST2DEV 0x194 +#define BHND_PCIE2_INTSTAT0_DEV2HOST 0x198 +#define BHND_PCIE2_INTMASK0_DEV2HOST 0x19c +#define BHND_PCIE2_LTR_STATE 0x1A0 +#define BHND_PCIE2_PWR_INT_STATUS 0x1A4 +#define BHND_PCIE2_PWR_INT_MASK 0x1A8 + +/* DMA channel registers */ +#define BHND_PCIE2_DMA0_HOST2DEV_TX 0x200 +#define BHND_PCIE2_DMA0_HOST2DEV_RX 0x220 +#define BHND_PCIE2_DMA0_DEV2HOST_TX 0x240 +#define BHND_PCIE2_DMA0_DEV2HOST_RX 0x260 + +#define BHND_PCIE2_DMA1_HOST2DEV_TX 0x280 +#define BHND_PCIE2_DMA1_HOST2DEV_RX 0x2A0 +#define BHND_PCIE2_DMA1_DEV2HOST_TX 0x2C0 +#define BHND_PCIE2_DMA1_DEV2HOST_RX 0x2E0 + +#define BHND_PCIE2_DMA2_HOST2DEV_TX 0x300 +#define BHND_PCIE2_DMA2_HOST2DEV_RX 0x320 +#define BHND_PCIE2_DMA2_DEV2HOST_TX 0x340 +#define BHND_PCIE2_DMA2_DEV2HOST_RX 0x360 + +#define BHND_PCIE2_DMA3_HOST2DEV_TX 0x380 +#define BHND_PCIE2_DMA3_HOST2DEV_RX 0x3A0 +#define BHND_PCIE2_DMA3_DEV2HOST_TX 0x3C0 +#define BHND_PCIE2_DMA3_DEV2HOST_RX 0x3E0 + +#define BHND_PCIE2_PCIE_FUNC0_CFG 0x400 /**< PCIe function 0 config space */ +#define BHND_PCIE2_PCIE_FUNC1_CFG 0x500 /**< PCIe function 1 config space */ +#define BHND_PCIE2_PCIE_FUNC2_CFG 0x600 /**< PCIe function 2 config space */ +#define BHND_PCIE2_PCIE_FUNC3_CFG 0x700 /**< PCIe function 3 config space */ +#define BHND_PCIE2_SPROM 0x800 /**< SPROM shadow */ + +#define BHND_PCIE2_FUNC0_IMAP0_0 0xC00 +#define BHND_PCIE2_FUNC0_IMAP0_1 0xC04 +#define BHND_PCIE2_FUNC0_IMAP0_2 0xC08 +#define BHND_PCIE2_FUNC0_IMAP0_3 0xC0C +#define BHND_PCIE2_FUNC0_IMAP0_4 0xC10 +#define BHND_PCIE2_FUNC0_IMAP0_5 0xC14 +#define BHND_PCIE2_FUNC0_IMAP0_6 0xC18 +#define BHND_PCIE2_FUNC0_IMAP0_7 0xC1C + +#define BHND_PCIE2_FUNC1_IMAP0_0 0xC20 +#define BHND_PCIE2_FUNC1_IMAP0_1 0xC24 +#define BHND_PCIE2_FUNC1_IMAP0_2 0xC28 +#define BHND_PCIE2_FUNC1_IMAP0_3 0xC2C +#define BHND_PCIE2_FUNC1_IMAP0_4 0xC30 +#define BHND_PCIE2_FUNC1_IMAP0_5 0xC34 +#define BHND_PCIE2_FUNC1_IMAP0_6 0xC38 +#define BHND_PCIE2_FUNC1_IMAP0_7 0xC3C + +#define BHND_PCIE2_FUNC0_IMAP1 0xC80 +#define BHND_PCIE2_FUNC1_IMAP1 0xC88 +#define BHND_PCIE2_FUNC0_IMAP2 0xCC0 +#define BHND_PCIE2_FUNC1_IMAP2 0xCC8 + +#define BHND_PCIE2_IARR0_LOWER 0xD00 +#define BHND_PCIE2_IARR0_UPPER 0xD04 +#define BHND_PCIE2_IARR1_LOWER 0xD08 +#define BHND_PCIE2_IARR1_UPPER 0xD0C +#define BHND_PCIE2_IARR2_LOWER 0xD10 +#define BHND_PCIE2_IARR2_UPPER 0xD14 +#define BHND_PCIE2_OARR0 0xD20 +#define BHND_PCIE2_OARR1 0xD28 +#define BHND_PCIE2_OARR2 0xD30 +#define BHND_PCIE2_OMAP0_LOWER 0xD40 +#define BHND_PCIE2_OMAP0_UPPER 0xD44 +#define BHND_PCIE2_OMAP1_LOWER 0xD48 +#define BHND_PCIE2_OMAP1_UPPER 0xD4C +#define BHND_PCIE2_OMAP2_LOWER 0xD50 +#define BHND_PCIE2_OMAP2_UPPER 0xD54 +#define BHND_PCIE2_FUNC1_IARR1_SIZE 0xD58 +#define BHND_PCIE2_FUNC1_IARR2_SIZE 0xD5C +#define BHND_PCIE2_MEM_CONTROL 0xF00 +#define BHND_PCIE2_MEM_ECC_ERRLOG0 0xF04 +#define BHND_PCIE2_MEM_ECC_ERRLOG1 0xF08 +#define BHND_PCIE2_LINK_STATUS 0xF0C +#define BHND_PCIE2_STRAP_STATUS 0xF10 +#define BHND_PCIE2_RESET_STATUS 0xF14 +#define BHND_PCIE2_RESETEN_IN_LINKDOWN 0xF18 +#define BHND_PCIE2_MISC_INTR_EN 0xF1C +#define BHND_PCIE2_TX_DEBUG_CFG 0xF20 +#define BHND_PCIE2_MISC_CONFIG 0xF24 +#define BHND_PCIE2_MISC_STATUS 0xF28 +#define BHND_PCIE2_INTR_EN 0xF30 +#define BHND_PCIE2_INTR_CLEAR 0xF34 +#define BHND_PCIE2_INTR_STATUS 0xF38 + +/* BHND_PCIE2_MDIO_CTL */ +#define BHND_PCIE2_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */ +#define BHND_PCIE2_MDIOCTL_DIVISOR_VAL 0x2 +#define BHND_PCIE2_MDIOCTL_REGADDR_SHIFT 8 /* Regaddr shift */ +#define BHND_PCIE2_MDIOCTL_REGADDR_MASK 0x00FFFF00 /* Regaddr Mask */ +#define BHND_PCIE2_MDIOCTL_DEVADDR_SHIFT 24 /* Physmedia devaddr shift */ +#define BHND_PCIE2_MDIOCTL_DEVADDR_MASK 0x0f000000 /* Physmedia devaddr Mask */ +#define BHND_PCIE2_MDIOCTL_SLAVE_BYPASS 0x10000000 /* IP slave bypass */ +#define BHND_PCIE2_MDIOCTL_READ 0x20000000 /* IP slave bypass */ + +/* BHND_PCIE2_MDIO_DATA */ +#define BHND_PCIE2_MDIODATA_DONE 0x80000000 /* rd/wr transaction done */ +#define BHND_PCIE2_MDIODATA_MASK 0x7FFFFFFF /* rd/wr transaction data */ +#define BHND_PCIE2_MDIODATA_DEVADDR_SHIFT 4 /* Physmedia devaddr shift */ + +/* BHND_PCIE2_DMA[0-4]_HOST2DEV_(TX|RX) per-channel register offsets */ +#define BHND_PCIE2_DMA_CTRL 0x0 /**< enable, et al */ +#define BHND_PCIE2_DMA_PTR 0x4 /**< last descriptor posted to chip */ +#define BHND_PCIE2_DMA_ADDRL 0x8 /**< descriptor ring base address low 32-bits (8K aligned) */ +#define BHND_PCIE2_DMA_ADDRH 0xC /**< descriptor ring base address bits 63:32 (8K aligned) */ +#define BHND_PCIE2_DMA_STATUS0 0x10 /**< current descriptor, xmt state */ +#define BHND_PCIE2_DMA_STATUS1 0x10 /**< active descriptor, xmt error */ + + +#endif /* _BHND_CORES_PCIE2_BHND_PCIE2_REG_H_ */ diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h new file mode 100644 index 0000000..154b059 --- /dev/null +++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2_var.h @@ -0,0 +1,98 @@ +/*- + * Copyright (c) 2015 Landon Fuller <landon@landonf.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef _BHND_CORES_PCIE2_BHND_PCIE2_VAR_H_ +#define _BHND_CORES_PCIE2_BHND_PCIE2_VAR_H_ + +#include <sys/param.h> +#include <sys/bus.h> + +/* + * Shared PCIe-G2 Bridge/Host Bridge definitions. + */ + +DECLARE_CLASS(bhnd_pcie2_driver); +struct bhnd_pcie2_softc; + +int bhnd_pcie2_generic_probe(device_t dev); +int bhnd_pcie2_generic_attach(device_t dev); +int bhnd_pcie2_generic_detach(device_t dev); +int bhnd_pcie2_generic_suspend(device_t dev); +int bhnd_pcie2_generic_resume(device_t dev); + + +uint32_t bhnd_pcie2_read_proto_reg(struct bhnd_pcie2_softc *sc, + uint32_t addr); +void bhnd_pcie2_write_proto_reg(struct bhnd_pcie2_softc *sc, + uint32_t addr, uint32_t val); +int bhnd_pcie2_mdio_read(struct bhnd_pcie2_softc *sc, int phy, + int reg); +int bhnd_pcie2_mdio_write(struct bhnd_pcie2_softc *sc, int phy, + int reg, int val); +int bhnd_pcie2_mdio_read_ext(struct bhnd_pcie2_softc *sc, int phy, + int devaddr, int reg); +int bhnd_pcie2_mdio_write_ext(struct bhnd_pcie2_softc *sc, + int phy, int devaddr, int reg, int val); + +/** + * bhnd_pcie2 child device info + */ +struct bhnd_pcie2_devinfo { + struct resource_list resources; +}; + +/* + * Generic PCIe-G2 bridge/end-point driver state. + * + * Must be first member of all subclass softc structures. + */ +struct bhnd_pcie2_softc { + device_t dev; /**< pci device */ + uint32_t quirks; /**< quirk flags */ + + struct mtx mtx; /**< state mutex used to protect + interdependent register + accesses. */ + + struct bhnd_resource *mem_res; /**< device register block. */ + int mem_rid; /**< register block RID */ +}; + + +#define BHND_PCIE2_LOCK_INIT(sc) \ + mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ + "BHND PCIe-G2 driver lock", MTX_DEF) +#define BHND_PCIE2_LOCK(sc) mtx_lock(&(sc)->mtx) +#define BHND_PCIE2_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define BHND_PCIE2_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) +#define BHND_PCIE2_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) + +#endif /* _BHND_CORES_PCIE2_BHND_PCIE2_VAR_H_ */
\ No newline at end of file diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2b.c b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2b.c new file mode 100644 index 0000000..90d84eb --- /dev/null +++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2b.c @@ -0,0 +1,98 @@ +/*- + * Copyright (c) 2015 Landon Fuller <landon@landonf.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * Broadcom PCI/PCIe-Gen1 Host-PCI bridge. + * + * This driver handles all interactions with PCI bridge cores operating in + * root complex mode. + */ + +#include <sys/param.h> +#include <sys/kernel.h> +#include <sys/bus.h> +#include <sys/module.h> + +#include <machine/bus.h> +#include <sys/rman.h> +#include <machine/resource.h> + +#include <dev/bhnd/bhnd.h> + +#include "bhnd_pcie2_reg.h" +#include "bhnd_pcie2b_var.h" + +static int +bhnd_pcie2b_attach(device_t dev) +{ + // TODO + return (bhnd_pcie2_generic_attach(dev)); +} + +static int +bhnd_pcie2b_detach(device_t dev) +{ + // TODO + return (bhnd_pcie2_generic_detach(dev)); +} + +static int +bhnd_pcie2b_suspend(device_t dev) +{ + return (bhnd_pcie2_generic_suspend(dev)); +} + +static int +bhnd_pcie2b_resume(device_t dev) +{ + return (bhnd_pcie2_generic_resume(dev)); +} + +static device_method_t bhnd_pcie2b_methods[] = { + /* Device interface */ + DEVMETHOD(device_attach, bhnd_pcie2b_attach), + DEVMETHOD(device_detach, bhnd_pcie2b_detach), + DEVMETHOD(device_suspend, bhnd_pcie2b_suspend), + DEVMETHOD(device_resume, bhnd_pcie2b_resume), + DEVMETHOD_END +}; + +DEFINE_CLASS_1(pcib, bhnd_pcie2b_driver, bhnd_pcie2b_methods, + sizeof(struct bhnd_pcie2b_softc), bhnd_pcie2_driver); + +static devclass_t pcib_devclass; +DRIVER_MODULE(bhnd_pcie2b, bhnd, bhnd_pcie2b_driver, pcib_devclass, 0, 0); + +MODULE_VERSION(bhnd_pcie2b, 1); +MODULE_DEPEND(bhnd_pcie2b, bhnd, 1, 1, 1); +MODULE_DEPEND(bhnd_pcie2b, bhnd_pcie2, 1, 1, 1); +MODULE_DEPEND(bhnd_pcie2b, pci, 1, 1, 1); diff --git a/sys/dev/bhnd/cores/pcie2/bhnd_pcie2b_var.h b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2b_var.h new file mode 100644 index 0000000..aeddfb5 --- /dev/null +++ b/sys/dev/bhnd/cores/pcie2/bhnd_pcie2b_var.h @@ -0,0 +1,42 @@ +/*- + * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef _BHND_CORES_PCIE2_BHND_PCIE2BVAR_H_ +#define _BHND_CORES_PCIE2_BHND_PCIE2BVAR_H_ + +#include "bhnd_pcie2_var.h" + +/* PCIe-G2 bridge driver-specific state */ +struct bhnd_pcie2b_softc { + struct bhnd_pcie2_softc sc_common; +}; + +#endif /* _BHND_CORES_PCIE2_BHND_PCIE2BVAR_H_ */
\ No newline at end of file diff --git a/sys/dev/bhnd/nvram/nvram_map b/sys/dev/bhnd/nvram/nvram_map index a716280..09230ee 100644 --- a/sys/dev/bhnd/nvram/nvram_map +++ b/sys/dev/bhnd/nvram/nvram_map @@ -30,6 +30,60 @@ # available ISC-licensed CIS and SROM code and associated headers. # +# Board Info +# + +u16 boardvendor {} # PCI vendor ID (SoC NVRAM-only) +u16 subvid { srom >= 2 0x6 } # PCI subvendor ID +u16 devid { srom >= 8 0x60 } # PCI device ID + +u32 boardflags { + srom 1 u16 0x72 + srom 2 u16 0x72 | u16 0x38 (<<16) + srom 3 u16 0x72 | u16 0x7A (<<16) + srom 4 0x44 + srom 5-7 0x4A + srom >= 8 0x84 +} +u32 boardflags2 { + srom 4 0x48 + srom 5-7 0x4E + srom >= 8 0x88 +} +u32 boardflags3 { + srom >= 11 0x8C +} + +# Board serial number, independent of mac addr +u16 boardnum { + srom 1-2 0x4C + srom 3 0x4E + srom 4 0x50 + srom 5-7 0x56 + srom 8-10 0x90 + srom >= 11 0x94 +} + +# Board revision +u16 boardrev { + srom 1-3 u8 0x5D + srom 4-7 0x42 + srom >= 8 0x82 +} + +# Board type +u16 boardtype { + srom >= 2 0x4 +} + +# SROM revision +u8 sromrev { + srom 1-3 0x74 + srom 4-9 0x1B6 + srom 10 0x1CA + srom 11 0x1D2 +} + # Antennas available u8 aa2g { srom 1-3 0x5C (&0x30, >>4) @@ -184,46 +238,6 @@ u8 aga2 { srom >= 11 0xA7 } -# board flags -u32 boardflags { - srom 1 u16 0x72 - srom 2 u16 0x72 | u16 0x38 (<<16) - srom 3 u16 0x72 | u16 0x7A (<<16) - srom 4 0x44 - srom 5-7 0x4A - srom >= 8 0x84 -} -u32 boardflags2 { - srom 4 0x48 - srom 5-7 0x4E - srom >= 8 0x88 -} -u32 boardflags3 { - srom >= 11 0x8C -} - -# board serial number, independent of mac addr -u16 boardnum { - srom 1-2 0x4C - srom 3 0x4E - srom 4 0x50 - srom 5-7 0x56 - srom 8-10 0x90 - srom >= 11 0x94 -} - -# One byte board revision -u16 boardrev { - srom 1-3 u8 0x5D - srom 4-7 0x42 - srom >= 8 0x82 -} - -# 2 bytes; boardtype -u16 boardtype { - srom >= 2 0x4 -} - # Default country code (sromrev == 1) u8 cc { srom 1 0x5C (&0xF) @@ -274,11 +288,6 @@ u16 antswitch { srom >= 11 u8 0xA8 } -# PCI device id -private u16 devid { - srom >= 8 u16 0x60 -} - u8 elna2g { srom 8-10 0xBB } @@ -1269,10 +1278,6 @@ u8 sar5g { srom >= 11 0x1BA } -u16 subvid { - srom >= 2 0x6 -} - u32[5] swctrlmap_2g { srom 10 u32[4] 0x1B8, u16 0x1C8 } diff --git a/sys/dev/bhnd/siba/siba.c b/sys/dev/bhnd/siba/siba.c index 9fc87ff..c34fc4f 100644 --- a/sys/dev/bhnd/siba/siba.c +++ b/sys/dev/bhnd/siba/siba.c @@ -55,15 +55,13 @@ int siba_attach(device_t dev) { struct siba_devinfo *dinfo; + struct siba_softc *sc; device_t *devs; int ndevs; int error; - - // TODO: We need to set the initiator timeout for the - // core that will be issuing requests to non-memory locations. - // - // In the case of a bridged device, this is the hostb core. - // On a non-bridged device, this will be the CPU. + + sc = device_get_softc(dev); + sc->dev = dev; /* Fetch references to the siba SIBA_CFG* blocks for all * registered devices */ @@ -144,6 +142,18 @@ siba_detach(device_t dev) return (bhnd_generic_detach(dev)); } +int +siba_resume(device_t dev) +{ + return (bhnd_generic_resume(dev)); +} + +int +siba_suspend(device_t dev) +{ + return (bhnd_generic_suspend(dev)); +} + static int siba_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) { @@ -663,6 +673,8 @@ static device_method_t siba_methods[] = { DEVMETHOD(device_probe, siba_probe), DEVMETHOD(device_attach, siba_attach), DEVMETHOD(device_detach, siba_detach), + DEVMETHOD(device_resume, siba_resume), + DEVMETHOD(device_suspend, siba_suspend), /* Bus interface */ DEVMETHOD(bus_child_deleted, siba_child_deleted), diff --git a/sys/dev/bhnd/siba/siba_bhndb.c b/sys/dev/bhnd/siba/siba_bhndb.c index 8a0e149..4055c12 100644 --- a/sys/dev/bhnd/siba/siba_bhndb.c +++ b/sys/dev/bhnd/siba/siba_bhndb.c @@ -34,11 +34,13 @@ __FBSDID("$FreeBSD$"); #include <sys/kernel.h> #include <sys/bus.h> #include <sys/module.h> +#include <sys/systm.h> #include <dev/bhnd/bhnd_ids.h> #include <dev/bhnd/bhndb/bhndbvar.h> #include <dev/bhnd/bhndb/bhndb_hwdata.h> +#include "sibareg.h" #include "sibavar.h" /* @@ -56,6 +58,20 @@ __FBSDID("$FreeBSD$"); // than delegating to our parent bhndb device. // +static int siba_bhndb_wars_hwup(struct siba_softc *sc); + +enum { + /** When PCIe-bridged, the D11 core's initiator request + * timeout must be disabled to prevent D11 from entering a + * RESP_TIMEOUT error state. */ + SIBA_QUIRK_PCIE_D11_SB_TIMEOUT = (1<<0) +}; + +static struct bhnd_chip_quirk chip_quirks[] = { + {{ BHND_CHIP_IR(4311, HWREV_EQ(2)) }, SIBA_QUIRK_PCIE_D11_SB_TIMEOUT }, + {{ BHND_CHIP_IR(4312, HWREV_EQ(0)) }, SIBA_QUIRK_PCIE_D11_SB_TIMEOUT }, +}; + static int siba_bhndb_probe(device_t dev) { @@ -94,7 +110,30 @@ siba_bhndb_attach(device_t dev) sc->hostb_dev = BHNDB_FIND_HOSTB_DEVICE(device_get_parent(dev), dev); /* Call our superclass' implementation */ - return (siba_attach(dev)); + if ((error = siba_attach(dev))) + return (error); + + /* Apply attach/resume work-arounds */ + if ((error = siba_bhndb_wars_hwup(sc))) + return (error); + + return (0); +} + +static int +siba_bhndb_resume(device_t dev) +{ + struct siba_softc *sc; + int error; + + sc = device_get_softc(dev); + + /* Apply attach/resume work-arounds */ + if ((error = siba_bhndb_wars_hwup(sc))) + return (error); + + /* Call our superclass' implementation */ + return (siba_resume(dev)); } /* Suspend all references to the device's cfg register blocks */ @@ -166,15 +205,89 @@ siba_bhndb_resume_child(device_t dev, device_t child) return (0); } +static int +siba_bhndb_read_board_info(device_t dev, device_t child, + struct bhnd_board_info *info) +{ + int error; + + /* Initialize with NVRAM-derived values */ + if ((error = bhnd_bus_generic_read_board_info(dev, child, info))) + return (error); + + /* Let the bridge fill in any additional data */ + return (BHNDB_POPULATE_BOARD_INFO(device_get_parent(dev), dev, info)); +} + +/* Work-around implementation for SIBA_QUIRK_PCIE_D11_SB_TIMEOUT */ +static int +siba_bhndb_wars_pcie_clear_d11_timeout(struct siba_softc *sc) +{ + struct siba_devinfo *dinfo; + device_t d11; + uint32_t imcfg; + + /* Only applies when bridged by PCIe */ + if (bhnd_get_class(sc->hostb_dev) != BHND_DEVCLASS_PCIE) + return (0); + + /* Only applies if there's a D11 core */ + d11 = bhnd_match_child(sc->dev, &(struct bhnd_core_match){ + .vendor = BHND_MFGID_BCM, + .device = BHND_COREID_D11, + .hwrev = BHND_HWREV_ANY, + .class = BHND_DEVCLASS_INVALID, + .unit = 0 + }); + if (d11 == NULL) + return (0); + + /* Clear initiator timeout in D11's CFG0 block */ + dinfo = device_get_ivars(d11); + KASSERT(dinfo->cfg[0] != NULL, ("missing core config mapping")); + + imcfg = bhnd_bus_read_4(dinfo->cfg[0], SIBA_CFG0_IMCONFIGLOW); + imcfg &= ~SIBA_IMCL_RTO_MASK; + + bhnd_bus_write_4(dinfo->cfg[0], SIBA_CFG0_IMCONFIGLOW, imcfg); + + return (0); +} + +/** + * Apply any hardware workarounds that are required upon attach or resume + * of the bus. + */ +static int +siba_bhndb_wars_hwup(struct siba_softc *sc) +{ + uint32_t quirks; + int error; + + quirks = bhnd_chip_quirks(sc->hostb_dev, chip_quirks); + + if (quirks & SIBA_QUIRK_PCIE_D11_SB_TIMEOUT) { + if ((error = siba_bhndb_wars_pcie_clear_d11_timeout(sc))) + return (error); + } + + return (0); +} + + static device_method_t siba_bhndb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, siba_bhndb_probe), DEVMETHOD(device_attach, siba_bhndb_attach), + DEVMETHOD(device_resume, siba_bhndb_resume), /* Bus interface */ DEVMETHOD(bus_suspend_child, siba_bhndb_suspend_child), DEVMETHOD(bus_resume_child, siba_bhndb_resume_child), + /* BHND interface */ + DEVMETHOD(bhnd_bus_read_board_info, siba_bhndb_read_board_info), + DEVMETHOD_END }; diff --git a/sys/dev/bhnd/siba/sibavar.h b/sys/dev/bhnd/siba/sibavar.h index f2b648a..784803c 100644 --- a/sys/dev/bhnd/siba/sibavar.h +++ b/sys/dev/bhnd/siba/sibavar.h @@ -53,6 +53,8 @@ struct siba_core_id; int siba_probe(device_t dev); int siba_attach(device_t dev); int siba_detach(device_t dev); +int siba_resume(device_t dev); +int siba_suspend(device_t dev); uint16_t siba_get_bhnd_mfgid(uint16_t ocp_vendor); @@ -145,6 +147,7 @@ struct siba_devinfo { /** siba(4) per-instance state */ struct siba_softc { struct bhnd_softc bhnd_sc; /**< bhnd state */ + device_t dev; /**< siba device */ device_t hostb_dev; /**< host bridge core, or NULL */ }; diff --git a/sys/dev/bwn/bwn_mac.c b/sys/dev/bwn/bwn_mac.c index 8b2e962..cba49ba 100644 --- a/sys/dev/bwn/bwn_mac.c +++ b/sys/dev/bwn/bwn_mac.c @@ -30,6 +30,9 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); +#include "opt_bwn.h" +#include "opt_wlan.h" + #include <sys/param.h> #include <sys/kernel.h> #include <sys/module.h> diff --git a/sys/dev/bwn/if_bwn.c b/sys/dev/bwn/if_bwn.c index 85a4164..615a3ad 100644 --- a/sys/dev/bwn/if_bwn.c +++ b/sys/dev/bwn/if_bwn.c @@ -34,6 +34,9 @@ __FBSDID("$FreeBSD$"); * The Broadcom Wireless LAN controller driver. */ +#include "opt_bwn.h" +#include "opt_wlan.h" + #include <sys/param.h> #include <sys/systm.h> #include <sys/kernel.h> @@ -81,6 +84,7 @@ __FBSDID("$FreeBSD$"); #include <dev/bwn/if_bwn_phy_common.h> #include <dev/bwn/if_bwn_phy_g.h> #include <dev/bwn/if_bwn_phy_lp.h> +#include <dev/bwn/if_bwn_phy_n.h> static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0, "Broadcom driver parameters"); @@ -128,7 +132,7 @@ static int bwn_setup_channels(struct bwn_mac *, int, int); static void bwn_shm_ctlword(struct bwn_mac *, uint16_t, uint16_t); static void bwn_addchannels(struct ieee80211_channel [], int, int *, - const struct bwn_channelinfo *, int); + const struct bwn_channelinfo *, const uint8_t []); static int bwn_raw_xmit(struct ieee80211_node *, struct mbuf *, const struct ieee80211_bpf_params *); static void bwn_updateslot(struct ieee80211com *); @@ -560,6 +564,11 @@ bwn_attach(device_t dev) else device_printf(sc->sc_dev, "PIO\n"); +#ifdef BWN_GPL_PHY + device_printf(sc->sc_dev, + "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n"); +#endif + /* * setup PCI resources and interrupt. */ @@ -1147,15 +1156,32 @@ bwn_attach_core(struct bwn_mac *mac) siba_powerup(sc->sc_dev, 0); high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); + + /* + * Guess at whether it has A-PHY or G-PHY. + * This is just used for resetting the core to probe things; + * we will re-guess once it's all up and working. + * + * XXX TODO: there's the TGSHIGH DUALPHY flag based on + * the PHY revision. + */ bwn_reset_core(mac, !!(high & BWN_TGSHIGH_HAVE_2GHZ)); + + /* + * Get the PHY version. + */ error = bwn_phy_getinfo(mac, high); if (error) goto fail; - /* XXX need bhnd */ + /* XXX TODO need bhnd */ if (bwn_is_bus_siba(mac)) { have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0; have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0; + if (high & BWN_TGSHIGH_DUALPHY) { + have_bg = 1; + have_a = 1; + } } else { device_printf(sc->sc_dev, "%s: not siba; bailing\n", __func__); error = ENXIO; @@ -1175,7 +1201,9 @@ bwn_attach_core(struct bwn_mac *mac) if (siba_get_pci_device(sc->sc_dev) != 0x4312 && siba_get_pci_device(sc->sc_dev) != 0x4319 && - siba_get_pci_device(sc->sc_dev) != 0x4324) { + siba_get_pci_device(sc->sc_dev) != 0x4324 && + siba_get_pci_device(sc->sc_dev) != 0x4328 && + siba_get_pci_device(sc->sc_dev) != 0x432b) { have_a = have_bg = 0; if (mac->mac_phy.type == BWN_PHYTYPE_A) have_a = 1; @@ -1187,13 +1215,21 @@ bwn_attach_core(struct bwn_mac *mac) KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__, mac->mac_phy.type)); } - /* XXX turns off PHY A because it's not supported */ + + /* + * XXX The PHY-G support doesn't do 5GHz operation. + */ if (mac->mac_phy.type != BWN_PHYTYPE_LP && mac->mac_phy.type != BWN_PHYTYPE_N) { + device_printf(sc->sc_dev, + "%s: forcing 2GHz only; no dual-band support for PHY\n", + __func__); have_a = 0; have_bg = 1; } + mac->mac_phy.phy_n = NULL; + if (mac->mac_phy.type == BWN_PHYTYPE_G) { mac->mac_phy.attach = bwn_phy_g_attach; mac->mac_phy.detach = bwn_phy_g_detach; @@ -1230,6 +1266,28 @@ bwn_attach_core(struct bwn_mac *mac) mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan; mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna; mac->mac_phy.task_60s = bwn_phy_lp_task_60s; + } else if (mac->mac_phy.type == BWN_PHYTYPE_N) { + mac->mac_phy.attach = bwn_phy_n_attach; + mac->mac_phy.detach = bwn_phy_n_detach; + mac->mac_phy.prepare_hw = bwn_phy_n_prepare_hw; + mac->mac_phy.init_pre = bwn_phy_n_init_pre; + mac->mac_phy.init = bwn_phy_n_init; + mac->mac_phy.exit = bwn_phy_n_exit; + mac->mac_phy.phy_read = bwn_phy_n_read; + mac->mac_phy.phy_write = bwn_phy_n_write; + mac->mac_phy.rf_read = bwn_phy_n_rf_read; + mac->mac_phy.rf_write = bwn_phy_n_rf_write; + mac->mac_phy.use_hwpctl = bwn_phy_n_hwpctl; + mac->mac_phy.rf_onoff = bwn_phy_n_rf_onoff; + mac->mac_phy.switch_analog = bwn_phy_n_switch_analog; + mac->mac_phy.switch_channel = bwn_phy_n_switch_channel; + mac->mac_phy.get_default_chan = bwn_phy_n_get_default_chan; + mac->mac_phy.set_antenna = bwn_phy_n_set_antenna; + mac->mac_phy.set_im = bwn_phy_n_im; + mac->mac_phy.recalc_txpwr = bwn_phy_n_recalc_txpwr; + mac->mac_phy.set_txpwr = bwn_phy_n_set_txpwr; + mac->mac_phy.task_15s = bwn_phy_n_task_15s; + mac->mac_phy.task_60s = bwn_phy_n_task_60s; } else { device_printf(sc->sc_dev, "unsupported PHY type (%d)\n", mac->mac_phy.type); @@ -1301,13 +1359,15 @@ bwn_reset_core(struct bwn_mac *mac, int g_mode) /* Take PHY out of reset */ low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) & - ~BWN_TGSLOW_PHYRESET; + ~(BWN_TGSLOW_PHYRESET | BWN_TGSLOW_PHYCLOCK_ENABLE); siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); siba_read_4(sc->sc_dev, SIBA_TGSLOW); - DELAY(1000); - siba_write_4(sc->sc_dev, SIBA_TGSLOW, low & ~SIBA_TGSLOW_FGC); + DELAY(2000); + low &= ~SIBA_TGSLOW_FGC; + low |= BWN_TGSLOW_PHYCLOCK_ENABLE; + siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); siba_read_4(sc->sc_dev, SIBA_TGSLOW); - DELAY(1000); + DELAY(2000); if (mac->mac_phy.switch_analog != NULL) mac->mac_phy.switch_analog(mac, 1); @@ -1433,14 +1493,12 @@ error: return (ENODEV); } -#define IEEE80211_CHAN_HTG (IEEE80211_CHAN_HT | IEEE80211_CHAN_G) -#define IEEE80211_CHAN_HTA (IEEE80211_CHAN_HT | IEEE80211_CHAN_A) - static int bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; + uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)]; memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); ic->ic_nchans = 0; @@ -1450,26 +1508,20 @@ bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a) have_bg, have_a); - if (have_bg) + if (have_bg) { + memset(bands, 0, sizeof(bands)); + setbit(bands, IEEE80211_MODE_11B); + setbit(bands, IEEE80211_MODE_11G); bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, - &ic->ic_nchans, &bwn_chantable_bg, IEEE80211_CHAN_G); -#if 0 - if (mac->mac_phy.type == BWN_PHYTYPE_N) { - if (have_a) - bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, - &ic->ic_nchans, &bwn_chantable_n, - IEEE80211_CHAN_HTA); - } else { - if (have_a) - bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, - &ic->ic_nchans, &bwn_chantable_a, - IEEE80211_CHAN_A); + &ic->ic_nchans, &bwn_chantable_bg, bands); } -#endif - if (have_a) + + if (have_a) { + memset(bands, 0, sizeof(bands)); + setbit(bands, IEEE80211_MODE_11A); bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, - &ic->ic_nchans, &bwn_chantable_a, - IEEE80211_CHAN_A); + &ic->ic_nchans, &bwn_chantable_a, bands); + } mac->mac_phy.supports_2ghz = have_bg; mac->mac_phy.supports_5ghz = have_a; @@ -1583,63 +1635,16 @@ bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset, } static void -bwn_addchan(struct ieee80211_channel *c, int freq, int flags, int ieee, - int txpow) -{ - - c->ic_freq = freq; - c->ic_flags = flags; - c->ic_ieee = ieee; - c->ic_minpower = 0; - c->ic_maxpower = 2 * txpow; - c->ic_maxregpower = txpow; -} - -static void bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans, - const struct bwn_channelinfo *ci, int flags) + const struct bwn_channelinfo *ci, const uint8_t bands[]) { - struct ieee80211_channel *c; - int i; + int i, error; - c = &chans[*nchans]; + for (i = 0, error = 0; i < ci->nchannels && error == 0; i++) { + const struct bwn_channel *hc = &ci->channels[i]; - for (i = 0; i < ci->nchannels; i++) { - const struct bwn_channel *hc; - - hc = &ci->channels[i]; - if (*nchans >= maxchans) - break; - bwn_addchan(c, hc->freq, flags, hc->ieee, hc->maxTxPow); - c++, (*nchans)++; - if (flags == IEEE80211_CHAN_G || flags == IEEE80211_CHAN_HTG) { - /* g channel have a separate b-only entry */ - if (*nchans >= maxchans) - break; - c[0] = c[-1]; - c[-1].ic_flags = IEEE80211_CHAN_B; - c++, (*nchans)++; - } - if (flags == IEEE80211_CHAN_HTG) { - /* HT g channel have a separate g-only entry */ - if (*nchans >= maxchans) - break; - c[-1].ic_flags = IEEE80211_CHAN_G; - c[0] = c[-1]; - c[0].ic_flags &= ~IEEE80211_CHAN_HT; - c[0].ic_flags |= IEEE80211_CHAN_HT20; /* HT20 */ - c++, (*nchans)++; - } - if (flags == IEEE80211_CHAN_HTA) { - /* HT a channel have a separate a-only entry */ - if (*nchans >= maxchans) - break; - c[-1].ic_flags = IEEE80211_CHAN_A; - c[0] = c[-1]; - c[0].ic_flags &= ~IEEE80211_CHAN_HT; - c[0].ic_flags |= IEEE80211_CHAN_HT20; /* HT20 */ - c++, (*nchans)++; - } + error = ieee80211_add_channel(chans, maxchans, nchans, + hc->ieee, hc->freq, hc->maxTxPow, 0, bands); } } @@ -2003,6 +2008,8 @@ bwn_core_init(struct bwn_mac *mac) KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, ("%s:%d: fail", __func__, __LINE__)); + DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); + siba_powerup(sc->sc_dev, 0); if (!siba_dev_isup(sc->sc_dev)) bwn_reset_core(mac, mac->mac_phy.gmode); @@ -2036,6 +2043,7 @@ bwn_core_init(struct bwn_mac *mac) if (error) goto fail0; } + DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: chip_init\n", __func__); error = bwn_chip_init(mac); if (error) goto fail0; @@ -2063,6 +2071,19 @@ bwn_core_init(struct bwn_mac *mac) hf &= ~BWN_HF_SKIP_CFP_UPDATE; bwn_hf_write(mac, hf); + /* Tell the firmware about the MAC capabilities */ + if (siba_get_revid(sc->sc_dev) >= 13) { + uint32_t cap; + cap = BWN_READ_4(mac, BWN_MAC_HW_CAP); + DPRINTF(sc, BWN_DEBUG_RESET, + "%s: hw capabilities: 0x%08x\n", + __func__, cap); + bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_L, + cap & 0xffff); + bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_H, + (cap >> 16) & 0xffff); + } + bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2); @@ -2083,6 +2104,7 @@ bwn_core_init(struct bwn_mac *mac) bwn_spu_setdelay(mac, 1); bwn_bt_enable(mac); + DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__); siba_powerup(sc->sc_dev, !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)); bwn_set_macaddr(mac); @@ -2092,12 +2114,14 @@ bwn_core_init(struct bwn_mac *mac) mac->mac_status = BWN_MAC_STATUS_INITED; + DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: done\n", __func__); return (error); fail0: siba_powerdown(sc->sc_dev); KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, ("%s:%d: fail", __func__, __LINE__)); + DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__); return (error); } @@ -2657,8 +2681,21 @@ bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index, dr->dr_curslot = -1; } else { if (dr->dr_index == 0) { - dr->dr_rx_bufsize = BWN_DMA0_RX_BUFFERSIZE; - dr->dr_frameoffset = BWN_DMA0_RX_FRAMEOFFSET; + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + case BWN_FW_HDR_410: + dr->dr_rx_bufsize = + BWN_DMA0_RX_BUFFERSIZE_FW351; + dr->dr_frameoffset = + BWN_DMA0_RX_FRAMEOFFSET_FW351; + break; + case BWN_FW_HDR_598: + dr->dr_rx_bufsize = + BWN_DMA0_RX_BUFFERSIZE_FW598; + dr->dr_frameoffset = + BWN_DMA0_RX_FRAMEOFFSET_FW598; + break; + } } else KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } @@ -2677,7 +2714,7 @@ bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index, dr->dr_txhdr_cache = contigmalloc( (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * - BWN_HDRSIZE(mac), M_DEVBUF, M_ZERO, + BWN_MAXTXHDRSIZE, M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR, 8, 0); if (dr->dr_txhdr_cache == NULL) { device_printf(sc->sc_dev, @@ -2774,7 +2811,7 @@ fail2: if (dr->dr_txhdr_cache != NULL) { contigfree(dr->dr_txhdr_cache, (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * - BWN_HDRSIZE(mac), M_DEVBUF); + BWN_MAXTXHDRSIZE, M_DEVBUF); } fail1: free(dr->dr_meta, M_DEVBUF); @@ -2796,7 +2833,7 @@ bwn_dma_ringfree(struct bwn_dma_ring **dr) if ((*dr)->dr_txhdr_cache != NULL) { contigfree((*dr)->dr_txhdr_cache, ((*dr)->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * - BWN_HDRSIZE((*dr)->dr_mac), M_DEVBUF); + BWN_MAXTXHDRSIZE, M_DEVBUF); } free((*dr)->dr_meta, M_DEVBUF); free(*dr, M_DEVBUF); @@ -3698,6 +3735,9 @@ bwn_mac_suspend(struct bwn_mac *mac) KASSERT(mac->mac_suspended >= 0, ("%s:%d: fail", __func__, __LINE__)); + DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", + __func__, mac->mac_suspended); + if (mac->mac_suspended == 0) { bwn_psctl(mac, BWN_PS_AWAKE); BWN_WRITE_4(mac, BWN_MACCTL, @@ -3728,11 +3768,17 @@ bwn_mac_enable(struct bwn_mac *mac) struct bwn_softc *sc = mac->mac_sc; uint16_t state; + DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", + __func__, mac->mac_suspended); + state = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODESTAT); if (state != BWN_SHARED_UCODESTAT_SUSPEND && - state != BWN_SHARED_UCODESTAT_SLEEP) - device_printf(sc->sc_dev, "warn: firmware state (%d)\n", state); + state != BWN_SHARED_UCODESTAT_SLEEP) { + DPRINTF(sc, BWN_DEBUG_FW, + "%s: warn: firmware state (%d)\n", + __func__, state); + } mac->mac_suspended--; KASSERT(mac->mac_suspended >= 0, @@ -3774,6 +3820,8 @@ bwn_psctl(struct bwn_mac *mac, uint32_t flags) DELAY(10); } } + DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: ucstat=%d\n", __func__, + ucstat); } static int @@ -4169,12 +4217,14 @@ bwn_fw_loaducode(struct bwn_mac *mac) * So, complain this is the case and exit out, rather * than attaching and then failing. */ +#if 0 if (mac->mac_fw.fw_hdr_format == BWN_FW_HDR_598) { device_printf(sc->sc_dev, "firmware is too new (>=598); not supported\n"); error = EOPNOTSUPP; goto error; } +#endif mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_PATCH); @@ -4761,12 +4811,15 @@ bwn_intr(void *arg) (sc->sc_flags & BWN_FLAG_INVALID)) return (FILTER_STRAY); + DPRINTF(sc, BWN_DEBUG_INTR, "%s: called\n", __func__); + reason = BWN_READ_4(mac, BWN_INTR_REASON); if (reason == 0xffffffff) /* shared IRQ */ return (FILTER_STRAY); reason &= mac->mac_intr_mask; if (reason == 0) return (FILTER_HANDLED); + DPRINTF(sc, BWN_DEBUG_INTR, "%s: reason=0x%08x\n", __func__, reason); mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00; mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00; @@ -5334,7 +5387,17 @@ bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot) len, dr->dr_rx_bufsize, cnt); return; } - macstat = le32toh(rxhdr->mac_status); + + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + case BWN_FW_HDR_410: + macstat = le32toh(rxhdr->ps4.r351.mac_status); + break; + case BWN_FW_HDR_598: + macstat = le32toh(rxhdr->ps4.r598.mac_status); + break; + } + if (macstat & BWN_RX_MAC_FCSERR) { if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { device_printf(sc->sc_dev, "RX drop\n"); @@ -5435,7 +5498,16 @@ ready: goto error; } - macstat = le32toh(rxhdr.mac_status); + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + case BWN_FW_HDR_410: + macstat = le32toh(rxhdr.ps4.r351.mac_status); + break; + case BWN_FW_HDR_598: + macstat = le32toh(rxhdr.ps4.r598.mac_status); + break; + } + if (macstat & BWN_RX_MAC_FCSERR) { if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { device_printf(sc->sc_dev, "%s: FCS error", __func__); @@ -5689,11 +5761,25 @@ bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr) BWN_ASSERT_LOCKED(sc); phystat0 = le16toh(rxhdr->phy_status0); - phystat3 = le16toh(rxhdr->phy_status3); - /* XXX Note: mactime, macstat, chanstat need fixing for fw 598 */ - macstat = le32toh(rxhdr->mac_status); - chanstat = le16toh(rxhdr->channel); + /* + * XXX Note: phy_status3 doesn't exist for HT-PHY; it's only + * used for LP-PHY. + */ + phystat3 = le16toh(rxhdr->ps3.lp.phy_status3); + + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + case BWN_FW_HDR_410: + macstat = le32toh(rxhdr->ps4.r351.mac_status); + chanstat = le16toh(rxhdr->ps4.r351.channel); + break; + case BWN_FW_HDR_598: + macstat = le32toh(rxhdr->ps4.r598.mac_status); + chanstat = le16toh(rxhdr->ps4.r598.channel); + break; + } + phytype = chanstat & BWN_RX_CHAN_PHYTYPE; @@ -5753,13 +5839,25 @@ bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr) rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2); else rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1); +#if 0 + DPRINTF(mac->mac_sc, BWN_DEBUG_RECV, + "%s: power0=%d, power1=%d, power2=%d\n", + __func__, + rxhdr->phy.n.power0, + rxhdr->phy.n.power1, + rxhdr->ps2.n.power2); +#endif break; default: /* XXX TODO: implement rssi for other PHYs */ break; } + /* + * RSSI here is absolute, not relative to the noise floor. + */ noise = mac->mac_stats.link_noise; + rssi = rssi - noise; /* RX radio tap */ if (ieee80211_radiotap_active(ic)) @@ -6152,10 +6250,22 @@ bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, m->m_pkthdr.len, rate, isshort); /* XXX TX encryption */ - bwn_plcp_genhdr(BWN_ISOLDFMT(mac) ? - (struct bwn_plcp4 *)(&txhdr->body.old.plcp) : - (struct bwn_plcp4 *)(&txhdr->body.new.plcp), - m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); + + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r351.plcp), + m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); + break; + case BWN_FW_HDR_410: + bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r410.plcp), + m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); + break; + case BWN_FW_HDR_598: + bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r598.plcp), + m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); + break; + } + bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb), m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb); @@ -6214,9 +6324,22 @@ bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, + ieee80211_ack_duration(ic->ic_rt, rate, isshort); if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { - cts = (struct ieee80211_frame_cts *)(BWN_ISOLDFMT(mac) ? - (txhdr->body.old.rts_frame) : - (txhdr->body.new.rts_frame)); + + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + cts = (struct ieee80211_frame_cts *) + txhdr->body.r351.rts_frame; + break; + case BWN_FW_HDR_410: + cts = (struct ieee80211_frame_cts *) + txhdr->body.r410.rts_frame; + break; + case BWN_FW_HDR_598: + cts = (struct ieee80211_frame_cts *) + txhdr->body.r598.rts_frame; + break; + } + mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, protdur); KASSERT(mprot != NULL, ("failed to alloc mbuf\n")); @@ -6226,9 +6349,21 @@ bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, macctl |= BWN_TX_MAC_SEND_CTSTOSELF; len = sizeof(struct ieee80211_frame_cts); } else { - rts = (struct ieee80211_frame_rts *)(BWN_ISOLDFMT(mac) ? - (txhdr->body.old.rts_frame) : - (txhdr->body.new.rts_frame)); + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + rts = (struct ieee80211_frame_rts *) + txhdr->body.r351.rts_frame; + break; + case BWN_FW_HDR_410: + rts = (struct ieee80211_frame_rts *) + txhdr->body.r410.rts_frame; + break; + case BWN_FW_HDR_598: + rts = (struct ieee80211_frame_rts *) + txhdr->body.r598.rts_frame; + break; + } + /* XXX rate/rate_fb is the hardware rate */ protdur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); @@ -6242,15 +6377,40 @@ bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, len = sizeof(struct ieee80211_frame_rts); } len += IEEE80211_CRC_LEN; - bwn_plcp_genhdr((struct bwn_plcp4 *)((BWN_ISOLDFMT(mac)) ? - &txhdr->body.old.rts_plcp : - &txhdr->body.new.rts_plcp), len, rts_rate); + + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + bwn_plcp_genhdr((struct bwn_plcp4 *) + &txhdr->body.r351.rts_plcp, len, rts_rate); + break; + case BWN_FW_HDR_410: + bwn_plcp_genhdr((struct bwn_plcp4 *) + &txhdr->body.r410.rts_plcp, len, rts_rate); + break; + case BWN_FW_HDR_598: + bwn_plcp_genhdr((struct bwn_plcp4 *) + &txhdr->body.r598.rts_plcp, len, rts_rate); + break; + } + bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len, rts_rate_fb); - protwh = (struct ieee80211_frame *)(BWN_ISOLDFMT(mac) ? - (&txhdr->body.old.rts_frame) : - (&txhdr->body.new.rts_frame)); + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + protwh = (struct ieee80211_frame *) + &txhdr->body.r351.rts_frame; + break; + case BWN_FW_HDR_410: + protwh = (struct ieee80211_frame *) + &txhdr->body.r410.rts_frame; + break; + case BWN_FW_HDR_598: + protwh = (struct ieee80211_frame *) + &txhdr->body.r598.rts_frame; + break; + } + txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur; if (BWN_ISOFDMRATE(rts_rate)) { @@ -6274,10 +6434,17 @@ bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, txhdr->phyctl_1fb = htole16(bwn_set_txhdr_phyctl1(mac, rate_fb)); } - if (BWN_ISOLDFMT(mac)) - txhdr->body.old.cookie = htole16(cookie); - else - txhdr->body.new.cookie = htole16(cookie); + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + txhdr->body.r351.cookie = htole16(cookie); + break; + case BWN_FW_HDR_410: + txhdr->body.r410.cookie = htole16(cookie); + break; + case BWN_FW_HDR_598: + txhdr->body.r598.cookie = htole16(cookie); + break; + } txhdr->macctl = htole32(macctl); txhdr->phyctl = htole16(phyctl); @@ -6710,6 +6877,7 @@ bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m, const struct ieee80211_frame_min *wh; uint64_t tsf; uint16_t low_mactime_now; + uint16_t mt; if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL) sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; @@ -6721,8 +6889,19 @@ bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m, bwn_tsf_read(mac, &tsf); low_mactime_now = tsf; tsf = tsf & ~0xffffULL; - tsf += le16toh(rxhdr->mac_time); - if (low_mactime_now < le16toh(rxhdr->mac_time)) + + switch (mac->mac_fw.fw_hdr_format) { + case BWN_FW_HDR_351: + case BWN_FW_HDR_410: + mt = le16toh(rxhdr->ps4.r351.mac_time); + break; + case BWN_FW_HDR_598: + mt = le16toh(rxhdr->ps4.r598.mac_time); + break; + } + + tsf += mt; + if (low_mactime_now < mt) tsf -= 0x10000; sc->sc_rx_th.wr_tsf = tsf; diff --git a/sys/dev/bwn/if_bwn_debug.h b/sys/dev/bwn/if_bwn_debug.h index 70f5541..d7a636d 100644 --- a/sys/dev/bwn/if_bwn_debug.h +++ b/sys/dev/bwn/if_bwn_debug.h @@ -32,8 +32,6 @@ #ifndef __IF_BWN_DEBUG_H__ #define __IF_BWN_DEBUG_H__ -#define BWN_DEBUG - enum { BWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ BWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ diff --git a/sys/dev/bwn/if_bwn_pci.c b/sys/dev/bwn/if_bwn_pci.c index 7e145c5..7a794b8 100644 --- a/sys/dev/bwn/if_bwn_pci.c +++ b/sys/dev/bwn/if_bwn_pci.c @@ -30,6 +30,9 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); +#include "opt_bwn.h" +#include "opt_wlan.h" + #include <sys/param.h> #include <sys/kernel.h> #include <sys/bus.h> diff --git a/sys/dev/bwn/if_bwn_phy_common.c b/sys/dev/bwn/if_bwn_phy_common.c index 04fb283..bcc9dc9 100644 --- a/sys/dev/bwn/if_bwn_phy_common.c +++ b/sys/dev/bwn/if_bwn_phy_common.c @@ -31,6 +31,9 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); +#include "opt_bwn.h" +#include "opt_wlan.h" + /* * The Broadcom Wireless LAN controller driver. */ @@ -183,9 +186,9 @@ bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled) if (bwn_is_bus_siba(mac)) { val = siba_read_4(sc->sc_dev, SIBA_TGSLOW); if (enabled) - val |= BWN_TMSLOW_MACPHYCLKEN; + val |= BWN_TGSLOW_MACPHYCLKEN; else - val &= ~BWN_TMSLOW_MACPHYCLKEN; + val &= ~BWN_TGSLOW_MACPHYCLKEN; siba_write_4(sc->sc_dev, SIBA_TGSLOW, val); } } diff --git a/sys/dev/bwn/if_bwn_phy_g.c b/sys/dev/bwn/if_bwn_phy_g.c index 1a21dac..5cc4cb9 100644 --- a/sys/dev/bwn/if_bwn_phy_g.c +++ b/sys/dev/bwn/if_bwn_phy_g.c @@ -30,6 +30,9 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); +#include "opt_bwn.h" +#include "opt_wlan.h" + /* * The Broadcom Wireless LAN controller driver. */ diff --git a/sys/dev/bwn/if_bwn_phy_lp.c b/sys/dev/bwn/if_bwn_phy_lp.c index 79a986f..0ca1b6a 100644 --- a/sys/dev/bwn/if_bwn_phy_lp.c +++ b/sys/dev/bwn/if_bwn_phy_lp.c @@ -30,6 +30,9 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); +#include "opt_bwn.h" +#include "opt_wlan.h" + /* * The Broadcom Wireless LAN controller driver. */ diff --git a/sys/dev/bwn/if_bwn_phy_n.c b/sys/dev/bwn/if_bwn_phy_n.c new file mode 100644 index 0000000..090d8ad --- /dev/null +++ b/sys/dev/bwn/if_bwn_phy_n.c @@ -0,0 +1,281 @@ +/*- + * Copyright (c) 2016 Adrian Chadd <adrian@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * This is the top-level N-PHY support for the Broadcom softmac driver. + */ + +#include "opt_bwn.h" +#include "opt_wlan.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/endian.h> +#include <sys/errno.h> +#include <sys/firmware.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/socket.h> +#include <sys/sockio.h> + +#include <net/ethernet.h> +#include <net/if.h> +#include <net/if_var.h> +#include <net/if_arp.h> +#include <net/if_dl.h> +#include <net/if_llc.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <dev/pci/pcivar.h> +#include <dev/pci/pcireg.h> +#include <dev/siba/siba_ids.h> +#include <dev/siba/sibareg.h> +#include <dev/siba/sibavar.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> +#include <net80211/ieee80211_regdomain.h> +#include <net80211/ieee80211_phy.h> +#include <net80211/ieee80211_ratectl.h> + +#include <dev/bwn/if_bwnreg.h> +#include <dev/bwn/if_bwnvar.h> + +#include <dev/bwn/if_bwn_debug.h> +#include <dev/bwn/if_bwn_misc.h> +#include <dev/bwn/if_bwn_phy_n.h> + +#ifdef BWN_GPL_PHY +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h> +#endif + +/* + * This module is always compiled into the kernel, regardless of + * whether the GPL PHY is enabled. If the GPL PHY isn't enabled + * then it'll just be stubs that will fail to attach. + */ + +int +bwn_phy_n_attach(struct bwn_mac *mac) +{ + +#ifdef BWN_GPL_PHY + return bwn_nphy_op_allocate(mac); +#else + return (ENXIO); +#endif +} + +void +bwn_phy_n_detach(struct bwn_mac *mac) +{ + +#ifdef BWN_GPL_PHY + return bwn_nphy_op_free(mac); +#endif +} + +int +bwn_phy_n_prepare_hw(struct bwn_mac *mac) +{ + +#ifdef BWN_GPL_PHY + bwn_nphy_op_prepare_structs(mac); + return (0); +#else + return (ENXIO); +#endif +} + +void +bwn_phy_n_init_pre(struct bwn_mac *mac) +{ + + /* XXX TODO */ +} + +int +bwn_phy_n_init(struct bwn_mac *mac) +{ +#ifdef BWN_GPL_PHY + return bwn_nphy_op_init(mac); +#else + return (ENXIO); +#endif +} + +void +bwn_phy_n_exit(struct bwn_mac *mac) +{ + + /* XXX TODO */ +} + +uint16_t +bwn_phy_n_read(struct bwn_mac *mac, uint16_t reg) +{ + + BWN_WRITE_2(mac, BWN_PHYCTL, reg); + return BWN_READ_2(mac, BWN_PHYDATA); +} + +void +bwn_phy_n_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) +{ + + BWN_WRITE_2(mac, BWN_PHYCTL, reg); + BWN_WRITE_2(mac, BWN_PHYDATA, value); +} + +uint16_t +bwn_phy_n_rf_read(struct bwn_mac *mac, uint16_t reg) +{ + + /* Register 1 is a 32-bit register. */ + if (mac->mac_phy.rev < 7 && reg == 1) { + BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__); + } + + if (mac->mac_phy.rev >= 7) + reg |= 0x200; /* radio 0x2057 */ + else + reg |= 0x100; + + BWN_WRITE_2(mac, BWN_RFCTL, reg); + return BWN_READ_2(mac, BWN_RFDATALO); +} + +void +bwn_phy_n_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) +{ + + /* Register 1 is a 32-bit register. */ + if (mac->mac_phy.rev < 7 && reg == 1) { + BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__); + } + + BWN_WRITE_2(mac, BWN_RFCTL, reg); + BWN_WRITE_2(mac, BWN_RFDATALO, value); +} + +int +bwn_phy_n_hwpctl(struct bwn_mac *mac) +{ + + return (0); +} + +void +bwn_phy_n_rf_onoff(struct bwn_mac *mac, int on) +{ +#ifdef BWN_GPL_PHY + bwn_nphy_op_software_rfkill(mac, on); +#endif +} + +void +bwn_phy_n_switch_analog(struct bwn_mac *mac, int on) +{ +#ifdef BWN_GPL_PHY + bwn_nphy_op_switch_analog(mac, on); +#endif +} + +int +bwn_phy_n_switch_channel(struct bwn_mac *mac, uint32_t newchan) +{ +#ifdef BWN_GPL_PHY + return bwn_nphy_op_switch_channel(mac, newchan); +#else + return (ENXIO); +#endif +} + +uint32_t +bwn_phy_n_get_default_chan(struct bwn_mac *mac) +{ + + if (bwn_current_band(mac) == BWN_BAND_2G) + return (1); + return (36); +} + +void +bwn_phy_n_set_antenna(struct bwn_mac *mac, int antenna) +{ + /* XXX TODO */ +} + +int +bwn_phy_n_im(struct bwn_mac *mac, int mode) +{ + /* XXX TODO */ + return (0); +} + +bwn_txpwr_result_t +bwn_phy_n_recalc_txpwr(struct bwn_mac *mac, int ignore_tssi) +{ +#ifdef BWN_GPL_PHY + return bwn_nphy_op_recalc_txpower(mac, ignore_tssi); +#else + return (BWN_TXPWR_RES_DONE); +#endif +} + +void +bwn_phy_n_set_txpwr(struct bwn_mac *mac) +{ + +} + +void +bwn_phy_n_task_15s(struct bwn_mac *mac) +{ + +} + +void +bwn_phy_n_task_60s(struct bwn_mac *mac) +{ + +} diff --git a/sys/dev/bwn/if_bwn_phy_n.h b/sys/dev/bwn/if_bwn_phy_n.h new file mode 100644 index 0000000..652f222 --- /dev/null +++ b/sys/dev/bwn/if_bwn_phy_n.h @@ -0,0 +1,57 @@ +/*- + * Copyright (c) 2016 Adrian Chadd <adrian@FreeBSD.org>. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef __IF_BWN_PHY_N_H__ +#define __IF_BWN_PHY_N_H__ + +extern int bwn_phy_n_attach(struct bwn_mac *mac); +extern void bwn_phy_n_detach(struct bwn_mac *mac); +extern int bwn_phy_n_prepare_hw(struct bwn_mac *mac); +extern void bwn_phy_n_init_pre(struct bwn_mac *mac); +extern int bwn_phy_n_init(struct bwn_mac *mac); +extern void bwn_phy_n_exit(struct bwn_mac *mac); +extern uint16_t bwn_phy_n_read(struct bwn_mac *mac, uint16_t reg); +extern void bwn_phy_n_write(struct bwn_mac *mac, uint16_t reg, uint16_t value); +extern uint16_t bwn_phy_n_rf_read(struct bwn_mac *mac, uint16_t reg); +extern void bwn_phy_n_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value); +extern int bwn_phy_n_hwpctl(struct bwn_mac *mac); +extern void bwn_phy_n_rf_onoff(struct bwn_mac *mac, int on); +extern void bwn_phy_n_switch_analog(struct bwn_mac *mac, int on); +extern int bwn_phy_n_switch_channel(struct bwn_mac *mac, uint32_t newchan); +extern uint32_t bwn_phy_n_get_default_chan(struct bwn_mac *mac); +extern void bwn_phy_n_set_antenna(struct bwn_mac *mac, int antenna); +extern int bwn_phy_n_im(struct bwn_mac *mac, int mode); +extern bwn_txpwr_result_t bwn_phy_n_recalc_txpwr(struct bwn_mac *mac, int ignore_tssi); +extern void bwn_phy_n_set_txpwr(struct bwn_mac *mac); +extern void bwn_phy_n_task_15s(struct bwn_mac *mac); +extern void bwn_phy_n_task_60s(struct bwn_mac *mac); + +#endif /* __IF_BWN_PHY_N_H__ */ diff --git a/sys/dev/bwn/if_bwn_util.c b/sys/dev/bwn/if_bwn_util.c index d1846d5..08da5aa 100644 --- a/sys/dev/bwn/if_bwn_util.c +++ b/sys/dev/bwn/if_bwn_util.c @@ -34,6 +34,9 @@ __FBSDID("$FreeBSD$"); * The Broadcom Wireless LAN controller driver. */ +#include "opt_bwn.h" +#include "opt_wlan.h" + #include <sys/param.h> #include <sys/systm.h> #include <sys/kernel.h> diff --git a/sys/dev/bwn/if_bwnreg.h b/sys/dev/bwn/if_bwnreg.h index 38f35a9..5bebdef 100644 --- a/sys/dev/bwn/if_bwnreg.h +++ b/sys/dev/bwn/if_bwnreg.h @@ -97,8 +97,8 @@ /* SIBA control registers */ #define BWN_TGSLOW_PHYCLOCK_ENABLE 0x00040000 #define BWN_TGSLOW_PHYRESET 0x00080000 -#define BWN_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ -#define BWN_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ +#define BWN_TGSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ +#define BWN_TGSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ /* PHY_BANDWIDTH: N-PHY only */ #define BWN_TGSLOW_PHY_BANDWIDTH 0x00C00000 #define BWN_TGSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 @@ -169,6 +169,7 @@ #define BWN_RAM_CONTROL 0x130 #define BWN_RAM_DATA 0x134 #define BWN_PS_STATUS 0x140 +#define BWN_MAC_HW_CAP 0x15c /* core rev >= 13 */ #define BWN_RF_HWENABLED_HI 0x158 #define BWN_RF_HWENABLED_HI_MASK (1 << 16) #define BWN_SHM_CONTROL 0x160 @@ -284,6 +285,8 @@ #define BWN_SHARED_SPU_WAKEUP 0x0094 #define BWN_SHARED_PRETBTT 0x0096 #define BWN_SHARED_CHAN 0x00a0 +#define BWN_SHARED_MACHW_L 0x00c0 +#define BWN_SHARED_MACHW_H 0x00c2 #define BWN_SHARED_AUTOINC 0x0100 #define BWN_SHARED_PROBE_RESP_PHYCTL 0x0188 #define BWN_SHARED_EDCFQ 0x0240 @@ -453,11 +456,13 @@ #define BWN_DMA64_RXSTAT 0xf0000000 #define BWN_DMA64_RXSTAT_DISABLED 0x00000000 #define BWN_DMA_RINGMEMSIZE PAGE_SIZE -#define BWN_DMA0_RX_FRAMEOFFSET 30 +#define BWN_DMA0_RX_FRAMEOFFSET_FW351 30 +#define BWN_DMA0_RX_FRAMEOFFSET_FW598 38 #define BWN_TXRING_SLOTS 64 #define BWN_RXRING_SLOTS 64 -#define BWN_DMA0_RX_BUFFERSIZE IEEE80211_MAX_LEN +#define BWN_DMA0_RX_BUFFERSIZE_FW351 (IEEE80211_MAX_LEN + BWN_DMA0_RX_FRAMEOFFSET_FW351) +#define BWN_DMA0_RX_BUFFERSIZE_FW598 (IEEE80211_MAX_LEN + BWN_DMA0_RX_FRAMEOFFSET_FW598) #define BWN_PHYROUTE_BASE 0x0000 #define BWN_PHYROUTE_MASK 0x0c00 diff --git a/sys/dev/bwn/if_bwnvar.h b/sys/dev/bwn/if_bwnvar.h index 6743af1..f4934ea 100644 --- a/sys/dev/bwn/if_bwnvar.h +++ b/sys/dev/bwn/if_bwnvar.h @@ -59,6 +59,7 @@ struct bwn_mac; #define BWN_TSSI2DBM(num, den) \ ((int32_t)((num < 0) ? num / den : (num + den / 2) / den)) #define BWN_HDRSIZE(mac) bwn_tx_hdrsize(mac) +#define BWN_MAXTXHDRSIZE (112 + (sizeof(struct bwn_plcp6))) #define BWN_PIO_COOKIE(tq, tp) \ ((uint16_t)((((uint16_t)tq->tq_index + 1) << 12) | tp->tp_index)) @@ -270,10 +271,29 @@ struct bwn_rxhdr4 { } __packed ht; uint16_t phy_status2; } __packed ps2; - uint16_t phy_status3; - uint32_t mac_status; - uint16_t mac_time; - uint16_t channel; + union { + struct { + uint16_t phy_status3; + } __packed lp; + struct { + int8_t phy_ht_power1; + int8_t phy_ht_power2; + } __packed ht; + } __packed ps3; + union { + struct { + uint32_t mac_status; + uint16_t mac_time; + uint16_t channel; + } __packed r351; + struct { + uint16_t phy_status4; + uint16_t phy_status5; + uint32_t mac_status; + uint16_t mac_time; + uint16_t channel; + } __packed r598; + } __packed ps4; } __packed; struct bwn_txstatus { @@ -764,19 +784,34 @@ struct bwn_txhdr { uint8_t rts_frame[16]; uint8_t pad1[2]; struct bwn_plcp6 plcp; - } __packed old; - /* format > r410 */ + } __packed r351; + /* format > r410 < r598 */ + struct { + uint16_t mimo_antenna; + uint16_t preload_size; + uint8_t pad0[2]; + uint16_t cookie; + uint16_t tx_status; + struct bwn_plcp6 rts_plcp; + uint8_t rts_frame[16]; + uint8_t pad1[2]; + struct bwn_plcp6 plcp; + } __packed r410; struct { uint16_t mimo_antenna; uint16_t preload_size; uint8_t pad0[2]; uint16_t cookie; uint16_t tx_status; + uint16_t max_n_mpdus; + uint16_t max_a_bytes_mrt; + uint16_t max_a_bytes_fbr; + uint16_t min_m_bytes; struct bwn_plcp6 rts_plcp; uint8_t rts_frame[16]; uint8_t pad1[2]; struct bwn_plcp6 plcp; - } __packed new; + } __packed r598; } __packed body; } __packed; diff --git a/sys/dev/bxe/ecore_hsi.h b/sys/dev/bxe/ecore_hsi.h index d1924a7..a3b4c4b 100644 --- a/sys/dev/bxe/ecore_hsi.h +++ b/sys/dev/bxe/ecore_hsi.h @@ -3709,9 +3709,9 @@ struct cstorm_toe_ag_context uint32_t snd_max /* The ACK sequence number received in the last completed DDP */; #if defined(__BIG_ENDIAN) uint16_t __agg_vars3 /* Various aggregative variables*/; - uint16_t __reserved67 /* A counter for the number of RQ WQEs with invalidate the the USTORM encountered */; + uint16_t __reserved67 /* A counter for the number of RQ WQEs with invalidate the USTORM encountered */; #elif defined(__LITTLE_ENDIAN) - uint16_t __reserved67 /* A counter for the number of RQ WQEs with invalidate the the USTORM encountered */; + uint16_t __reserved67 /* A counter for the number of RQ WQEs with invalidate the USTORM encountered */; uint16_t __agg_vars3 /* Various aggregative variables*/; #endif #if defined(__BIG_ENDIAN) diff --git a/sys/dev/cxgbe/cxgbei/icl_cxgbei.c b/sys/dev/cxgbe/cxgbei/icl_cxgbei.c index 6f20281..6332747 100644 --- a/sys/dev/cxgbe/cxgbei/icl_cxgbei.c +++ b/sys/dev/cxgbe/cxgbei/icl_cxgbei.c @@ -777,8 +777,8 @@ icl_cxgbei_conn_close(struct icl_conn *ic) } int -icl_cxgbei_conn_task_setup(struct icl_conn *ic, struct ccb_scsiio *csio, - uint32_t *task_tagp, void **prvp) +icl_cxgbei_conn_task_setup(struct icl_conn *ic, struct icl_pdu *ip, + struct ccb_scsiio *csio, uint32_t *task_tagp, void **prvp) { void *prv; diff --git a/sys/dev/drm2/i915/intel_crt.c b/sys/dev/drm2/i915/intel_crt.c index 56c2120..1360a7b 100644 --- a/sys/dev/drm2/i915/intel_crt.c +++ b/sys/dev/drm2/i915/intel_crt.c @@ -794,7 +794,7 @@ void intel_crt_init(struct drm_device *dev) dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; /* - * TODO: find a proper way to discover whether we need to set the the + * TODO: find a proper way to discover whether we need to set the * polarity and link reversal bits or not, instead of relying on the * BIOS. */ diff --git a/sys/dev/drm2/i915/intel_display.c b/sys/dev/drm2/i915/intel_display.c index 0a03f22..9899449 100644 --- a/sys/dev/drm2/i915/intel_display.c +++ b/sys/dev/drm2/i915/intel_display.c @@ -7971,7 +7971,7 @@ bool intel_set_mode(struct drm_crtc *crtc, crtc->mode = *mode; /* Only after disabling all output pipelines that will be changed can we - * update the the output configuration. */ + * update the output configuration. */ intel_modeset_update_state(dev, prepare_pipes); if (dev_priv->display.modeset_global_resources) diff --git a/sys/dev/drm2/radeon/atombios.h b/sys/dev/drm2/radeon/atombios.h index 16119f4..6843977 100644 --- a/sys/dev/drm2/radeon/atombios.h +++ b/sys/dev/drm2/radeon/atombios.h @@ -2734,8 +2734,8 @@ ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of t ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. -usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. -usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. +usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. +usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. */ diff --git a/sys/dev/drm2/radeon/r300_reg.h b/sys/dev/drm2/radeon/r300_reg.h index 3dc2b43..136f816 100644 --- a/sys/dev/drm2/radeon/r300_reg.h +++ b/sys/dev/drm2/radeon/r300_reg.h @@ -356,7 +356,7 @@ __FBSDID("$FreeBSD$"); # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 # define R300_PVS_CNTL_1_POS_END_SHIFT 10 # define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20 -/* Addresses are relative the the vertex program parameters area. */ +/* Addresses are relative the vertex program parameters area. */ #define R300_VAP_PVS_CNTL_2 0x22D4 # define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 # define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 diff --git a/sys/dev/drm2/radeon/radeon_device.c b/sys/dev/drm2/radeon/radeon_device.c index 76b4cd7..860b962 100644 --- a/sys/dev/drm2/radeon/radeon_device.c +++ b/sys/dev/drm2/radeon/radeon_device.c @@ -191,7 +191,7 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) /* * radeon_wb_*() - * Writeback is the the method by which the the GPU updates special pages + * Writeback is the method by which the GPU updates special pages * in memory with the status of certain GPU events (fences, ring pointers, * etc.). */ diff --git a/sys/dev/drm2/radeon/radeon_fence.c b/sys/dev/drm2/radeon/radeon_fence.c index 6b1763b..560eea9 100644 --- a/sys/dev/drm2/radeon/radeon_fence.c +++ b/sys/dev/drm2/radeon/radeon_fence.c @@ -45,7 +45,7 @@ __FBSDID("$FreeBSD$"); * for GPU/CPU synchronization. When the fence is written, * it is expected that all buffers associated with that fence * are no longer in use by the associated ring on the GPU and - * that the the relevant GPU caches have been flushed. Whether + * that the relevant GPU caches have been flushed. Whether * we use a scratch register or memory location depends on the asic * and whether writeback is enabled. */ diff --git a/sys/dev/drm2/radeon/radeon_gart.c b/sys/dev/drm2/radeon/radeon_gart.c index cf5609a..37b1783 100644 --- a/sys/dev/drm2/radeon/radeon_gart.c +++ b/sys/dev/drm2/radeon/radeon_gart.c @@ -413,7 +413,7 @@ void radeon_gart_fini(struct radeon_device *rdev) * (uncached system pages). * Each VM has an ID associated with it and there is a page table * associated with each VMID. When execting a command buffer, - * the kernel tells the the ring what VMID to use for that command + * the kernel tells the ring what VMID to use for that command * buffer. VMIDs are allocated dynamically as commands are submitted. * The userspace drivers maintain their own address space and the kernel * sets up their pages tables accordingly when they submit their diff --git a/sys/dev/e1000/e1000_82575.c b/sys/dev/e1000/e1000_82575.c index 38770a3..24538ca 100644 --- a/sys/dev/e1000/e1000_82575.c +++ b/sys/dev/e1000/e1000_82575.c @@ -2416,7 +2416,7 @@ out: * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits * @hw: pointer to the HW structure * - * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on + * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on * the values found in the EEPROM. This addresses an issue in which these * bits are not restored from EEPROM after reset. **/ diff --git a/sys/dev/e1000/e1000_ich8lan.c b/sys/dev/e1000/e1000_ich8lan.c index 9b9a090..ae97a8c 100644 --- a/sys/dev/e1000/e1000_ich8lan.c +++ b/sys/dev/e1000/e1000_ich8lan.c @@ -4904,7 +4904,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) * @hw: pointer to the HW structure * * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability - * register, so the the bus width is hard coded. + * register, so the bus width is hard coded. **/ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) { diff --git a/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c b/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c index b4fbe91..cbcdff9 100644 --- a/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c +++ b/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.c @@ -119,7 +119,6 @@ static uint32_t mtkswitch_reg_read32(struct mtkswitch_softc *sc, int reg) { - MTKSWITCH_LOCK_ASSERT(sc, MA_OWNED); return (MTKSWITCH_READ(sc, reg)); } @@ -127,7 +126,6 @@ static uint32_t mtkswitch_reg_write32(struct mtkswitch_softc *sc, int reg, uint32_t val) { - MTKSWITCH_LOCK_ASSERT(sc, MA_OWNED); MTKSWITCH_WRITE(sc, reg, val); return (0); } @@ -230,15 +228,21 @@ mtkswitch_port_init(struct mtkswitch_softc *sc, int port) /* Called early and hence unlocked */ /* Set the port to secure mode */ - sc->hal.mtkswitch_write(sc, MTKSWITCH_PCR(port), PCR_PORT_VLAN_SECURE); + val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PCR(port)); + val |= PCR_PORT_VLAN_SECURE; + sc->hal.mtkswitch_write(sc, MTKSWITCH_PCR(port), val); /* Set port's vlan_attr to user port */ val = sc->hal.mtkswitch_read(sc, MTKSWITCH_PVC(port)); - val &= PVC_VLAN_ATTR_MASK; + val &= ~PVC_VLAN_ATTR_MASK; sc->hal.mtkswitch_write(sc, MTKSWITCH_PVC(port), val); + val = PMCR_CFG_DEFAULT; + if (port == sc->cpuport) + val |= PMCR_FORCE_LINK | PMCR_FORCE_DPX | PMCR_FORCE_SPD_1000 | + PMCR_FORCE_MODE; /* Set port's MAC to default settings */ - sc->hal.mtkswitch_write(sc, MTKSWITCH_PMCR(port), PMCR_CFG_DEFAULT); + sc->hal.mtkswitch_write(sc, MTKSWITCH_PMCR(port), val); } static uint32_t @@ -353,13 +357,12 @@ mtkswitch_vlan_init_hw(struct mtkswitch_softc *sc) MTKSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); MTKSWITCH_LOCK(sc); - /* Reset all VLANs to defaults first */ for (i = 0; i < sc->info.es_nvlangroups; i++) { mtkswitch_invalidate_vlan(sc, i); if (sc->sc_switchtype == MTK_SWITCH_MT7620) { val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VTIM(i)); - val &= (VTIM_MASK << VTIM_OFF(i)); + val &= ~(VTIM_MASK << VTIM_OFF(i)); val |= ((i + 1) << VTIM_OFF(i)); sc->hal.mtkswitch_write(sc, MTKSWITCH_VTIM(i), val); } @@ -464,7 +467,7 @@ mtkswitch_vlan_setvgroup(struct mtkswitch_softc *sc, etherswitch_vlangroup_t *v) if (sc->sc_switchtype == MTK_SWITCH_MT7620) { val = sc->hal.mtkswitch_read(sc, MTKSWITCH_VTIM(v->es_vlangroup)); - val &= (VTIM_MASK << VTIM_OFF(v->es_vlangroup)); + val &= ~(VTIM_MASK << VTIM_OFF(v->es_vlangroup)); val |= ((v->es_vid & VTIM_MASK) << VTIM_OFF(v->es_vlangroup)); sc->hal.mtkswitch_write(sc, MTKSWITCH_VTIM(v->es_vlangroup), val); diff --git a/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.h b/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.h index 718118b..c526c28 100644 --- a/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.h +++ b/sys/dev/etherswitch/mtkswitch/mtkswitch_mt7620.h @@ -85,13 +85,21 @@ #define PPBV_VID_MASK 0xfff #define MTKSWITCH_PMCR(x) MTKSWITCH_PORTREG(0x3000, (x)) +#define PMCR_FORCE_LINK (1u<<0) +#define PMCR_FORCE_DPX (1u<<1) +#define PMCR_FORCE_SPD_1000 (2u<<2) +#define PMCR_FORCE_TX_FC (1u<<4) +#define PMCR_FORCE_RX_FC (1u<<5) #define PMCR_BACKPR_EN (1u<<8) #define PMCR_BKOFF_EN (1u<<9) #define PMCR_MAC_RX_EN (1u<<13) #define PMCR_MAC_TX_EN (1u<<14) +#define PMCR_FORCE_MODE (1u<<15) +#define PMCR_RES_1 (1u<<16) #define PMCR_IPG_CFG_RND (1u<<18) #define PMCR_CFG_DEFAULT (PMCR_BACKPR_EN | PMCR_BKOFF_EN | \ - PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_IPG_CFG_RND) + PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_IPG_CFG_RND | \ + PMCR_FORCE_RX_FC | PMCR_FORCE_TX_FC | PMCR_RES_1) #define MTKSWITCH_PMSR(x) MTKSWITCH_PORTREG(0x3008, (x)) #define PMSR_MAC_LINK_STS (1u<<0) diff --git a/sys/dev/fb/vesa.c b/sys/dev/fb/vesa.c index 4ab83c3..bd6b759 100644 --- a/sys/dev/fb/vesa.c +++ b/sys/dev/fb/vesa.c @@ -1025,7 +1025,8 @@ vesa_bios_init(void) ++modes; } - vesa_vmode[modes].vi_mode = EOT; + if (vesa_vmode != NULL) + vesa_vmode[modes].vi_mode = EOT; if (bootverbose) printf("VESA: %d mode(s) found\n", modes); diff --git a/sys/dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c b/sys/dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c index f0f0733..c0c4563 100644 --- a/sys/dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c +++ b/sys/dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c @@ -304,7 +304,7 @@ MODULE_DEPEND(storvsc, vmbus, 1, 1, 1); * We address this issue by implementing a sequentially * consistent protocol: * - * 1. Channel callback is invoked while holding the the channel lock + * 1. Channel callback is invoked while holding the channel lock * and an unloading driver will reset the channel callback under * the protection of this channel lock. * diff --git a/sys/dev/hyperv/vmbus/hv_channel.c b/sys/dev/hyperv/vmbus/hv_channel.c index 6da0643..d85da43 100644 --- a/sys/dev/hyperv/vmbus/hv_channel.c +++ b/sys/dev/hyperv/vmbus/hv_channel.c @@ -42,7 +42,8 @@ __FBSDID("$FreeBSD$"); #include <vm/vm_param.h> #include <vm/pmap.h> -#include "hv_vmbus_priv.h" +#include <dev/hyperv/vmbus/hv_vmbus_priv.h> +#include <dev/hyperv/vmbus/vmbus_var.h> static int vmbus_channel_create_gpadl_header( /* must be phys and virt contiguous*/ @@ -199,6 +200,8 @@ hv_vmbus_channel_open( new_channel->on_channel_callback = pfn_on_channel_callback; new_channel->channel_callback_context = context; + vmbus_on_channel_open(new_channel); + new_channel->rxq = hv_vmbus_g_context.hv_event_queue[new_channel->target_cpu]; TASK_INIT(&new_channel->channel_task, 0, VmbusProcessChannelEvent, new_channel); diff --git a/sys/dev/hyperv/vmbus/hv_connection.c b/sys/dev/hyperv/vmbus/hv_connection.c index 321e6ab..5cd474a 100644 --- a/sys/dev/hyperv/vmbus/hv_connection.c +++ b/sys/dev/hyperv/vmbus/hv_connection.c @@ -38,7 +38,8 @@ #include <vm/vm_param.h> #include <vm/pmap.h> -#include "hv_vmbus_priv.h" +#include <dev/hyperv/vmbus/hv_vmbus_priv.h> +#include <dev/hyperv/vmbus/vmbus_var.h> /* * Globals @@ -148,7 +149,8 @@ hv_vmbus_negotiate_version(hv_vmbus_channel_msg_info *msg_info, * Send a connect request on the partition service connection */ int -hv_vmbus_connect(void) { +hv_vmbus_connect(void) +{ int ret = 0; uint32_t version; hv_vmbus_channel_msg_info* msg_info = NULL; @@ -270,7 +272,8 @@ hv_vmbus_connect(void) { * Send a disconnect request on the partition service connection */ int -hv_vmbus_disconnect(void) { +hv_vmbus_disconnect(void) +{ int ret = 0; hv_vmbus_channel_unload msg; @@ -288,76 +291,71 @@ hv_vmbus_disconnect(void) { return (ret); } -/** - * Handler for events - */ -void -hv_vmbus_on_events(int cpu) +static __inline void +vmbus_event_flags_proc(unsigned long *event_flags, int flag_cnt) { - int bit; - int dword; - void *page_addr; - uint32_t* recv_interrupt_page = NULL; - int rel_id; - int maxdword; - hv_vmbus_synic_event_flags *event; + int f; + + for (f = 0; f < flag_cnt; ++f) { + uint32_t rel_id_base; + unsigned long flags; + int bit; + + if (event_flags[f] == 0) + continue; + + flags = atomic_swap_long(&event_flags[f], 0); + rel_id_base = f << HV_CHANNEL_ULONG_SHIFT; + + while ((bit = ffsl(flags)) != 0) { + struct hv_vmbus_channel *channel; + uint32_t rel_id; - KASSERT(cpu <= mp_maxid, ("VMBUS: hv_vmbus_on_events: " - "cpu out of range!")); - - page_addr = hv_vmbus_g_context.syn_ic_event_page[cpu]; - event = (hv_vmbus_synic_event_flags *) - page_addr + HV_VMBUS_MESSAGE_SINT; - if ((hv_vmbus_protocal_version == HV_VMBUS_VERSION_WS2008) || - (hv_vmbus_protocal_version == HV_VMBUS_VERSION_WIN7)) { - maxdword = HV_MAX_NUM_CHANNELS_SUPPORTED >> 5; - /* - * receive size is 1/2 page and divide that by 4 bytes - */ - if (atomic_testandclear_int(&event->flags32[0], 0)) { - recv_interrupt_page = - hv_vmbus_g_connection.recv_interrupt_page; - } else { - return; + --bit; /* NOTE: ffsl is 1-based */ + flags &= ~(1UL << bit); + + rel_id = rel_id_base + bit; + channel = hv_vmbus_g_connection.channels[rel_id]; + + /* if channel is closed or closing */ + if (channel == NULL || channel->rxq == NULL) + continue; + + if (channel->batched_reading) + hv_ring_buffer_read_begin(&channel->inbound); + taskqueue_enqueue(channel->rxq, &channel->channel_task); } - } else { - /* - * On Host with Win8 or above, the event page can be - * checked directly to get the id of the channel - * that has the pending interrupt. - */ - maxdword = HV_EVENT_FLAGS_DWORD_COUNT; - recv_interrupt_page = event->flags32; } +} + +void +vmbus_event_proc(struct vmbus_softc *sc, int cpu) +{ + hv_vmbus_synic_event_flags *event; + + event = ((hv_vmbus_synic_event_flags *) + hv_vmbus_g_context.syn_ic_event_page[cpu]) + HV_VMBUS_MESSAGE_SINT; /* - * Check events + * On Host with Win8 or above, the event page can be checked directly + * to get the id of the channel that has the pending interrupt. */ - for (dword = 0; dword < maxdword; dword++) { - if (recv_interrupt_page[dword] == 0) - continue; + vmbus_event_flags_proc(event->flagsul, + VMBUS_SC_PCPU_GET(sc, event_flag_cnt, cpu)); +} - for (bit = 0; bit < HV_CHANNEL_DWORD_LEN; bit++) { - if (atomic_testandclear_int( - &recv_interrupt_page[dword], bit)) { - struct hv_vmbus_channel *channel; - - rel_id = (dword << 5) + bit; - channel = - hv_vmbus_g_connection.channels[rel_id]; - - /* if channel is closed or closing */ - if (channel == NULL || channel->rxq == NULL) - continue; - - if (channel->batched_reading) { - hv_ring_buffer_read_begin( - &channel->inbound); - } - taskqueue_enqueue(channel->rxq, - &channel->channel_task); - } - } +void +vmbus_event_proc_compat(struct vmbus_softc *sc __unused, int cpu) +{ + hv_vmbus_synic_event_flags *event; + + event = ((hv_vmbus_synic_event_flags *) + hv_vmbus_g_context.syn_ic_event_page[cpu]) + HV_VMBUS_MESSAGE_SINT; + + if (atomic_testandclear_int(&event->flags32[0], 0)) { + vmbus_event_flags_proc( + hv_vmbus_g_connection.recv_interrupt_page, + HV_MAX_NUM_CHANNELS_SUPPORTED >> HV_CHANNEL_ULONG_SHIFT); } } @@ -399,7 +397,8 @@ int hv_vmbus_post_message(void *buffer, size_t bufferLen) * Send an event notification to the parent */ int -hv_vmbus_set_event(hv_vmbus_channel *channel) { +hv_vmbus_set_event(hv_vmbus_channel *channel) +{ int ret = 0; uint32_t child_rel_id = channel->offer_msg.child_rel_id; @@ -412,3 +411,30 @@ hv_vmbus_set_event(hv_vmbus_channel *channel) { return (ret); } + +void +vmbus_on_channel_open(const struct hv_vmbus_channel *chan) +{ + volatile int *flag_cnt_ptr; + int flag_cnt; + + flag_cnt = (chan->offer_msg.child_rel_id / HV_CHANNEL_ULONG_LEN) + 1; + flag_cnt_ptr = VMBUS_PCPU_PTR(event_flag_cnt, chan->target_cpu); + + for (;;) { + int old_flag_cnt; + + old_flag_cnt = *flag_cnt_ptr; + if (old_flag_cnt >= flag_cnt) + break; + if (atomic_cmpset_int(flag_cnt_ptr, old_flag_cnt, flag_cnt)) { + if (bootverbose) { + printf("VMBUS: channel%u update " + "cpu%d flag_cnt to %d\n", + chan->offer_msg.child_rel_id, + chan->target_cpu, flag_cnt); + } + break; + } + } +} diff --git a/sys/dev/hyperv/vmbus/hv_hv.c b/sys/dev/hyperv/vmbus/hv_hv.c index 70a5608..6e3f713 100644 --- a/sys/dev/hyperv/vmbus/hv_hv.c +++ b/sys/dev/hyperv/vmbus/hv_hv.c @@ -501,8 +501,12 @@ hyperv_identify(void) static void hyperv_init(void *dummy __unused) { - if (!hyperv_identify()) + if (!hyperv_identify()) { + /* Not Hyper-V; reset guest id to the generic one. */ + if (vm_guest == VM_GUEST_HV) + vm_guest = VM_GUEST_VM; return; + } if (hyperv_features & HV_FEATURE_MSR_TIME_REFCNT) { /* Register virtual timecount */ diff --git a/sys/dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c b/sys/dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c index d0bdfc4..7d51f61 100644 --- a/sys/dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c +++ b/sys/dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c @@ -60,39 +60,32 @@ __FBSDID("$FreeBSD$"); #include <x86/apicvar.h> #include <dev/hyperv/include/hyperv.h> -#include "hv_vmbus_priv.h" +#include <dev/hyperv/vmbus/hv_vmbus_priv.h> +#include <dev/hyperv/vmbus/vmbus_var.h> #include <contrib/dev/acpica/include/acpi.h> #include "acpi_if.h" +struct vmbus_softc *vmbus_sc; + static device_t vmbus_devp; static int vmbus_inited; static hv_setup_args setup_args; /* only CPU 0 supported at this time */ static char *vmbus_ids[] = { "VMBUS", NULL }; -/** - * @brief Software interrupt thread routine to handle channel messages from - * the hypervisor. - */ static void -vmbus_msg_swintr(void *arg, int pending __unused) +vmbus_msg_task(void *arg __unused, int pending __unused) { - int cpu; - void* page_addr; - hv_vmbus_channel_msg_header *hdr; - hv_vmbus_channel_msg_table_entry *entry; - hv_vmbus_channel_msg_type msg_type; - hv_vmbus_message* msg; - - cpu = (int)(long)arg; - KASSERT(cpu <= mp_maxid, ("VMBUS: vmbus_msg_swintr: " - "cpu out of range!")); - - page_addr = hv_vmbus_g_context.syn_ic_msg_page[cpu]; - msg = (hv_vmbus_message*) page_addr + HV_VMBUS_MESSAGE_SINT; + hv_vmbus_message *msg; + msg = ((hv_vmbus_message *)hv_vmbus_g_context.syn_ic_msg_page[curcpu]) + + HV_VMBUS_MESSAGE_SINT; for (;;) { + const hv_vmbus_channel_msg_table_entry *entry; + hv_vmbus_channel_msg_header *hdr; + hv_vmbus_channel_msg_type msg_type; + if (msg->header.message_type == HV_MESSAGE_TYPE_NONE) break; /* no message */ @@ -105,32 +98,29 @@ vmbus_msg_swintr(void *arg, int pending __unused) } entry = &g_channel_message_table[msg_type]; - if (entry->messageHandler) entry->messageHandler(hdr); handled: - msg->header.message_type = HV_MESSAGE_TYPE_NONE; - - /* - * Make sure the write to message_type (ie set to - * HV_MESSAGE_TYPE_NONE) happens before we read the - * message_pending and EOMing. Otherwise, the EOMing will - * not deliver any more messages - * since there is no empty slot - * - * NOTE: - * mb() is used here, since atomic_thread_fence_seq_cst() - * will become compiler fence on UP kernel. - */ - mb(); - - if (msg->header.message_flags.u.message_pending) { + msg->header.message_type = HV_MESSAGE_TYPE_NONE; + /* + * Make sure the write to message_type (ie set to + * HV_MESSAGE_TYPE_NONE) happens before we read the + * message_pending and EOMing. Otherwise, the EOMing will + * not deliver any more messages + * since there is no empty slot + * + * NOTE: + * mb() is used here, since atomic_thread_fence_seq_cst() + * will become compiler fence on UP kernel. + */ + mb(); + if (msg->header.message_flags.u.message_pending) { /* * This will cause message queue rescan to possibly * deliver another msg from the hypervisor */ wrmsr(HV_X64_MSR_EOM, 0); - } + } } } @@ -143,23 +133,21 @@ handled: static inline int hv_vmbus_isr(struct trapframe *frame) { - int cpu; - hv_vmbus_message* msg; - void* page_addr; - - cpu = PCPU_GET(cpuid); + struct vmbus_softc *sc = vmbus_get_softc(); + int cpu = curcpu; + hv_vmbus_message *msg; + void *page_addr; /* * The Windows team has advised that we check for events * before checking for messages. This is the way they do it * in Windows when running as a guest in Hyper-V */ - - hv_vmbus_on_events(cpu); + sc->vmbus_event_proc(sc, cpu); /* Check if there are actual msgs to be process */ page_addr = hv_vmbus_g_context.syn_ic_msg_page[cpu]; - msg = (hv_vmbus_message*) page_addr + HV_VMBUS_TIMER_SINT; + msg = ((hv_vmbus_message *)page_addr) + HV_VMBUS_TIMER_SINT; /* we call eventtimer process the message */ if (msg->header.message_type == HV_MESSAGE_TIMER_EXPIRED) { @@ -190,7 +178,7 @@ hv_vmbus_isr(struct trapframe *frame) } } - msg = (hv_vmbus_message*) page_addr + HV_VMBUS_MESSAGE_SINT; + msg = ((hv_vmbus_message *)page_addr) + HV_VMBUS_MESSAGE_SINT; if (msg->header.message_type != HV_MESSAGE_TYPE_NONE) { taskqueue_enqueue(hv_vmbus_g_context.hv_msg_tq[cpu], &hv_vmbus_g_context.hv_msg_task[cpu]); @@ -358,12 +346,13 @@ hv_vmbus_child_device_unregister(struct hv_device *child_dev) } static int -vmbus_probe(device_t dev) { +vmbus_probe(device_t dev) +{ if (ACPI_ID_PROBE(device_get_parent(dev), dev, vmbus_ids) == NULL || device_get_unit(dev) != 0) return (ENXIO); - device_set_desc(dev, "Vmbus Devices"); + device_set_desc(dev, "Hyper-V Vmbus"); return (BUS_PROBE_DEFAULT); } @@ -385,6 +374,7 @@ extern inthand_t IDTVEC(hv_vmbus_callback); static int vmbus_bus_init(void) { + struct vmbus_softc *sc; int i, j, n, ret; char buf[MAXCOMLEN + 1]; cpuset_t cpu_mask; @@ -393,6 +383,7 @@ vmbus_bus_init(void) return (0); vmbus_inited = 1; + sc = vmbus_get_softc(); ret = hv_vmbus_init(); @@ -453,7 +444,7 @@ vmbus_bus_init(void) taskqueue_start_threads_cpuset(&hv_vmbus_g_context.hv_msg_tq[j], 1, PI_NET, &cpu_mask, "hvmsg%d", j); TASK_INIT(&hv_vmbus_g_context.hv_msg_task[j], 0, - vmbus_msg_swintr, (void *)(long)j); + vmbus_msg_task, NULL); /* * Prepare the per cpu msg and event pages to be called on each cpu. @@ -478,6 +469,12 @@ vmbus_bus_init(void) if (ret != 0) goto cleanup1; + if (hv_vmbus_protocal_version == HV_VMBUS_VERSION_WS2008 || + hv_vmbus_protocal_version == HV_VMBUS_VERSION_WIN7) + sc->vmbus_event_proc = vmbus_event_proc_compat; + else + sc->vmbus_event_proc = vmbus_event_proc; + hv_vmbus_request_channel_offers(); vmbus_scan(); @@ -512,12 +509,26 @@ vmbus_bus_init(void) return (ret); } +static void +vmbus_event_proc_dummy(struct vmbus_softc *sc __unused, int cpu __unused) +{ +} + static int vmbus_attach(device_t dev) { if(bootverbose) device_printf(dev, "VMBUS: attach dev: %p\n", dev); + vmbus_devp = dev; + vmbus_sc = device_get_softc(dev); + + /* + * Event processing logic will be configured: + * - After the vmbus protocol version negotiation. + * - Before we request channel offers. + */ + vmbus_sc->vmbus_event_proc = vmbus_event_proc_dummy; #ifndef EARLY_AP_STARTUP /* @@ -535,9 +546,9 @@ vmbus_attach(device_t dev) } static void -vmbus_init(void) +vmbus_sysinit(void *arg __unused) { - if (vm_guest != VM_GUEST_HV) + if (vm_guest != VM_GUEST_HV || vmbus_get_softc() == NULL) return; #ifndef EARLY_AP_STARTUP @@ -552,8 +563,8 @@ vmbus_init(void) vmbus_bus_init(); } -static void -vmbus_bus_exit(void) +static int +vmbus_detach(device_t dev) { int i; @@ -579,84 +590,45 @@ vmbus_bus_exit(void) lapic_ipi_free(hv_vmbus_g_context.hv_cb_vector); - return; -} - -static void -vmbus_exit(void) -{ - vmbus_bus_exit(); -} - -static int -vmbus_detach(device_t dev) -{ - vmbus_exit(); - return (0); -} - -static void -vmbus_mod_load(void) -{ - if(bootverbose) - printf("VMBUS: load\n"); -} - -static void -vmbus_mod_unload(void) -{ - if(bootverbose) - printf("VMBUS: unload\n"); -} - -static int -vmbus_modevent(module_t mod, int what, void *arg) -{ - switch (what) { - - case MOD_LOAD: -#ifdef EARLY_AP_STARTUP - vmbus_init(); -#endif - vmbus_mod_load(); - break; - case MOD_UNLOAD: - vmbus_mod_unload(); - break; - } - return (0); } static device_method_t vmbus_methods[] = { - /** Device interface */ - DEVMETHOD(device_probe, vmbus_probe), - DEVMETHOD(device_attach, vmbus_attach), - DEVMETHOD(device_detach, vmbus_detach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - - /** Bus interface */ - DEVMETHOD(bus_add_child, bus_generic_add_child), - DEVMETHOD(bus_print_child, bus_generic_print_child), - DEVMETHOD(bus_read_ivar, vmbus_read_ivar), - DEVMETHOD(bus_write_ivar, vmbus_write_ivar), - DEVMETHOD(bus_child_pnpinfo_str, vmbus_child_pnpinfo_str), - - { 0, 0 } }; - -static char driver_name[] = "vmbus"; -static driver_t vmbus_driver = { driver_name, vmbus_methods,0, }; - - -devclass_t vmbus_devclass; - -DRIVER_MODULE(vmbus, acpi, vmbus_driver, vmbus_devclass, vmbus_modevent, 0); + /* Device interface */ + DEVMETHOD(device_probe, vmbus_probe), + DEVMETHOD(device_attach, vmbus_attach), + DEVMETHOD(device_detach, vmbus_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + + /* Bus interface */ + DEVMETHOD(bus_add_child, bus_generic_add_child), + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_read_ivar, vmbus_read_ivar), + DEVMETHOD(bus_write_ivar, vmbus_write_ivar), + DEVMETHOD(bus_child_pnpinfo_str, vmbus_child_pnpinfo_str), + + DEVMETHOD_END +}; + +static driver_t vmbus_driver = { + "vmbus", + vmbus_methods, + sizeof(struct vmbus_softc) +}; + +static devclass_t vmbus_devclass; + +DRIVER_MODULE(vmbus, acpi, vmbus_driver, vmbus_devclass, NULL, NULL); MODULE_DEPEND(vmbus, acpi, 1, 1, 1); MODULE_VERSION(vmbus, 1); #ifndef EARLY_AP_STARTUP -/* We want to be started after SMP is initialized */ -SYSINIT(vmb_init, SI_SUB_SMP + 1, SI_ORDER_FIRST, vmbus_init, NULL); +/* + * NOTE: + * We have to start as the last step of SI_SUB_SMP, i.e. after SMP is + * initialized. + */ +SYSINIT(vmbus_initialize, SI_SUB_SMP, SI_ORDER_ANY, vmbus_sysinit, NULL); #endif diff --git a/sys/dev/hyperv/vmbus/hv_vmbus_priv.h b/sys/dev/hyperv/vmbus/hv_vmbus_priv.h index 0b8ad68..563c18a 100644 --- a/sys/dev/hyperv/vmbus/hv_vmbus_priv.h +++ b/sys/dev/hyperv/vmbus/hv_vmbus_priv.h @@ -57,10 +57,18 @@ typedef uint16_t hv_vmbus_status; #define HV_EVENT_FLAGS_COUNT (256 * 8) #define HV_EVENT_FLAGS_BYTE_COUNT (256) #define HV_EVENT_FLAGS_DWORD_COUNT (256 / sizeof(uint32_t)) +#define HV_EVENT_FLAGS_ULONG_COUNT (256 / sizeof(unsigned long)) /** * max channel count <== event_flags_dword_count * bit_of_dword */ +#ifdef __LP64__ +#define HV_CHANNEL_ULONG_LEN (64) +#define HV_CHANNEL_ULONG_SHIFT (6) +#else +#define HV_CHANNEL_ULONG_LEN (32) +#define HV_CHANNEL_ULONG_SHIFT (5) +#endif #define HV_CHANNEL_DWORD_LEN (32) #define HV_CHANNEL_MAX_COUNT \ ((HV_EVENT_FLAGS_DWORD_COUNT) * HV_CHANNEL_DWORD_LEN) @@ -575,7 +583,9 @@ typedef struct { typedef union { uint8_t flags8[HV_EVENT_FLAGS_BYTE_COUNT]; uint32_t flags32[HV_EVENT_FLAGS_DWORD_COUNT]; + unsigned long flagsul[HV_EVENT_FLAGS_ULONG_COUNT]; } hv_vmbus_synic_event_flags; +CTASSERT(sizeof(hv_vmbus_synic_event_flags) == HV_EVENT_FLAGS_BYTE_COUNT); #define HV_X64_CPUID_MIN (0x40000005) #define HV_X64_CPUID_MAX (0x4000ffff) @@ -743,7 +753,6 @@ int hv_vmbus_connect(void); int hv_vmbus_disconnect(void); int hv_vmbus_post_message(void *buffer, size_t buf_size); int hv_vmbus_set_event(hv_vmbus_channel *channel); -void hv_vmbus_on_events(int cpu); /** * Event Timer interfaces diff --git a/sys/dev/hyperv/vmbus/vmbus_var.h b/sys/dev/hyperv/vmbus/vmbus_var.h new file mode 100644 index 0000000..a3c790b --- /dev/null +++ b/sys/dev/hyperv/vmbus/vmbus_var.h @@ -0,0 +1,62 @@ +/*- + * Copyright (c) 2016 Microsoft Corp. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _VMBUS_VAR_H_ +#define _VMBUS_VAR_H_ + +#include <sys/param.h> + +struct vmbus_pcpu_data { + int event_flag_cnt; /* # of event flags */ +} __aligned(CACHE_LINE_SIZE); + +struct vmbus_softc { + void (*vmbus_event_proc)(struct vmbus_softc *, int); + struct vmbus_pcpu_data vmbus_pcpu[MAXCPU]; +}; + +extern struct vmbus_softc *vmbus_sc; + +static __inline struct vmbus_softc * +vmbus_get_softc(void) +{ + return vmbus_sc; +} + +#define VMBUS_SC_PCPU_GET(sc, field, cpu) (sc)->vmbus_pcpu[(cpu)].field +#define VMBUS_SC_PCPU_PTR(sc, field, cpu) &(sc)->vmbus_pcpu[(cpu)].field +#define VMBUS_PCPU_GET(field, cpu) \ + VMBUS_SC_PCPU_GET(vmbus_get_softc(), field, (cpu)) +#define VMBUS_PCPU_PTR(field, cpu) \ + VMBUS_SC_PCPU_PTR(vmbus_get_softc(), field, (cpu)) + +void vmbus_on_channel_open(const struct hv_vmbus_channel *); +void vmbus_event_proc(struct vmbus_softc *, int); +void vmbus_event_proc_compat(struct vmbus_softc *, int); + +#endif /* !_VMBUS_VAR_H_ */ diff --git a/sys/dev/iscsi/icl.c b/sys/dev/iscsi/icl.c index c679523..921fc2a 100644 --- a/sys/dev/iscsi/icl.c +++ b/sys/dev/iscsi/icl.c @@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$"); #include <sys/module.h> #include <sys/queue.h> #include <sys/sbuf.h> +#include <sys/socket.h> #include <sys/sysctl.h> #include <sys/systm.h> #include <sys/sx.h> diff --git a/sys/dev/iscsi/icl.h b/sys/dev/iscsi/icl.h index 86dfb9a..735e5db 100644 --- a/sys/dev/iscsi/icl.h +++ b/sys/dev/iscsi/icl.h @@ -138,28 +138,6 @@ int icl_unregister(const char *offload); struct sockaddr; struct icl_listen; -struct icl_listen_sock { - TAILQ_ENTRY(icl_listen_sock) ils_next; - struct icl_listen *ils_listen; - struct socket *ils_socket; - bool ils_running; - bool ils_disconnecting; - int ils_id; -}; - -struct icl_listen { - TAILQ_HEAD(, icl_listen_sock) il_sockets; - struct sx il_lock; - void (*il_accept)(struct socket *, - struct sockaddr *, int); -}; - -/* - * Initiator part. - */ -int icl_conn_connect(struct icl_conn *ic, bool rdma, - int domain, int socktype, int protocol, - struct sockaddr *from_sa, struct sockaddr *to_sa); /* * Target part. */ @@ -172,10 +150,12 @@ int icl_listen_add(struct icl_listen *il, bool rdma, int icl_listen_remove(struct icl_listen *il, struct sockaddr *sa); /* - * This one is not a public API; only to be used by icl_proxy.c. + * Those two are not a public API; only to be used between icl_soft.c + * and icl_soft_proxy.c. */ -int icl_conn_handoff_sock(struct icl_conn *ic, struct socket *so); - +int icl_soft_handoff_sock(struct icl_conn *ic, struct socket *so); +int icl_soft_proxy_connect(struct icl_conn *ic, int domain, + int socktype, int protocol, struct sockaddr *from_sa, + struct sockaddr *to_sa); #endif /* ICL_KERNEL_PROXY */ - #endif /* !ICL_H */ diff --git a/sys/dev/iscsi/icl_conn_if.m b/sys/dev/iscsi/icl_conn_if.m index 077fabe..11df311 100644 --- a/sys/dev/iscsi/icl_conn_if.m +++ b/sys/dev/iscsi/icl_conn_if.m @@ -29,6 +29,7 @@ # $FreeBSD$ # +#include <sys/socket.h> #include <dev/iscsi/icl.h> INTERFACE icl_conn; @@ -84,6 +85,7 @@ METHOD void close { METHOD int task_setup { struct icl_conn *_ic; + struct icl_pdu *_ip; struct ccb_scsiio *_csio; uint32_t *_task_tag; void **_prvp; @@ -105,3 +107,15 @@ METHOD void transfer_done { struct icl_conn *_ic; void *_prv; }; + +# +# The function below is only used with ICL_KERNEL_PROXY. +# +METHOD int connect { + struct icl_conn *_ic; + int _domain; + int _socktype; + int _protocol; + struct sockaddr *_from_sa; + struct sockaddr *_to_sa; +}; diff --git a/sys/dev/iscsi/icl_soft.c b/sys/dev/iscsi/icl_soft.c index bf8bec7..1216375 100644 --- a/sys/dev/iscsi/icl_soft.c +++ b/sys/dev/iscsi/icl_soft.c @@ -101,6 +101,9 @@ static icl_conn_task_setup_t icl_soft_conn_task_setup; static icl_conn_task_done_t icl_soft_conn_task_done; static icl_conn_transfer_setup_t icl_soft_conn_transfer_setup; static icl_conn_transfer_done_t icl_soft_conn_transfer_done; +#ifdef ICL_KERNEL_PROXY +static icl_conn_connect_t icl_soft_conn_connect; +#endif static kobj_method_t icl_soft_methods[] = { KOBJMETHOD(icl_conn_new_pdu, icl_soft_conn_new_pdu), @@ -117,6 +120,9 @@ static kobj_method_t icl_soft_methods[] = { KOBJMETHOD(icl_conn_task_done, icl_soft_conn_task_done), KOBJMETHOD(icl_conn_transfer_setup, icl_soft_conn_transfer_setup), KOBJMETHOD(icl_conn_transfer_done, icl_soft_conn_transfer_done), +#ifdef ICL_KERNEL_PROXY + KOBJMETHOD(icl_conn_connect, icl_soft_conn_connect), +#endif { 0, 0 } }; @@ -1424,8 +1430,8 @@ icl_soft_conn_close(struct icl_conn *ic) } int -icl_soft_conn_task_setup(struct icl_conn *ic, struct ccb_scsiio *csio, - uint32_t *task_tagp, void **prvp) +icl_soft_conn_task_setup(struct icl_conn *ic, struct icl_pdu *ip, + struct ccb_scsiio *csio, uint32_t *task_tagp, void **prvp) { return (0); @@ -1460,7 +1466,16 @@ icl_soft_limits(size_t *limitp) #ifdef ICL_KERNEL_PROXY int -icl_conn_handoff_sock(struct icl_conn *ic, struct socket *so) +icl_soft_conn_connect(struct icl_conn *ic, int domain, int socktype, + int protocol, struct sockaddr *from_sa, struct sockaddr *to_sa) +{ + + return (icl_soft_proxy_connect(ic, domain, socktype, protocol, + from_sa, to_sa)); +} + +int +icl_soft_handoff_sock(struct icl_conn *ic, struct socket *so) { int error; diff --git a/sys/dev/iscsi/icl_proxy.c b/sys/dev/iscsi/icl_soft_proxy.c index 3a8db66..f91bea3 100644 --- a/sys/dev/iscsi/icl_proxy.c +++ b/sys/dev/iscsi/icl_soft_proxy.c @@ -84,35 +84,29 @@ __FBSDID("$FreeBSD$"); #include <sys/systm.h> #include <netinet/in.h> #include <netinet/tcp.h> -#include <linux/types.h> -#include <rdma/rdma_cm.h> #include <dev/iscsi/icl.h> -static int debug = 1; - -#define ICL_DEBUG(X, ...) \ - if (debug > 1) { \ - printf("%s: " X "\n", __func__, ## __VA_ARGS__);\ - } while (0) - -#define ICL_WARN(X, ...) \ - if (debug > 0) { \ - printf("WARNING: %s: " X "\n", \ - __func__, ## __VA_ARGS__); \ - } while (0) +struct icl_listen_sock { + TAILQ_ENTRY(icl_listen_sock) ils_next; + struct icl_listen *ils_listen; + struct socket *ils_socket; + bool ils_running; + bool ils_disconnecting; + int ils_id; +}; + +struct icl_listen { + TAILQ_HEAD(, icl_listen_sock) il_sockets; + struct sx il_lock; + void (*il_accept)(struct socket *, + struct sockaddr *, int); +}; static MALLOC_DEFINE(M_ICL_PROXY, "ICL_PROXY", "iSCSI common layer proxy"); -#ifdef ICL_RDMA -static int icl_conn_connect_rdma(struct icl_conn *ic, int domain, int socktype, - int protocol, struct sockaddr *from_sa, struct sockaddr *to_sa); -static int icl_listen_add_rdma(struct icl_listen *il, int domain, int socktype, int protocol, - struct sockaddr *sa); -#endif /* ICL_RDMA */ - -static int -icl_conn_connect_tcp(struct icl_conn *ic, int domain, int socktype, +int +icl_soft_proxy_connect(struct icl_conn *ic, int domain, int socktype, int protocol, struct sockaddr *from_sa, struct sockaddr *to_sa) { struct socket *so; @@ -159,30 +153,13 @@ icl_conn_connect_tcp(struct icl_conn *ic, int domain, int socktype, return (error); } - error = icl_conn_handoff_sock(ic, so); + error = icl_soft_handoff_sock(ic, so); if (error != 0) soclose(so); return (error); } -int -icl_conn_connect(struct icl_conn *ic, bool rdma, int domain, int socktype, - int protocol, struct sockaddr *from_sa, struct sockaddr *to_sa) -{ - - if (rdma) { -#ifdef ICL_RDMA - return (icl_conn_connect_rdma(ic, domain, socktype, protocol, from_sa, to_sa)); -#else - ICL_DEBUG("RDMA not supported"); - return (EOPNOTSUPP); -#endif - } - - return (icl_conn_connect_tcp(ic, domain, socktype, protocol, from_sa, to_sa)); -} - struct icl_listen * icl_listen_new(void (*accept_cb)(struct socket *, struct sockaddr *, int)) { @@ -375,13 +352,8 @@ icl_listen_add(struct icl_listen *il, bool rdma, int domain, int socktype, { if (rdma) { -#ifndef ICL_RDMA ICL_DEBUG("RDMA not supported"); return (EOPNOTSUPP); -#else - return (icl_listen_add_rdma(il, domain, socktype, protocol, - sa, portal_id)); -#endif } diff --git a/sys/dev/iscsi/icl_wrappers.h b/sys/dev/iscsi/icl_wrappers.h index 1ed72ae..cb22d16 100644 --- a/sys/dev/iscsi/icl_wrappers.h +++ b/sys/dev/iscsi/icl_wrappers.h @@ -106,11 +106,11 @@ icl_conn_close(struct icl_conn *ic) } static inline int -icl_conn_task_setup(struct icl_conn *ic, struct ccb_scsiio *csio, - uint32_t *task_tagp, void **prvp) +icl_conn_task_setup(struct icl_conn *ic, struct icl_pdu *ip, + struct ccb_scsiio *csio, uint32_t *task_tagp, void **prvp) { - return (ICL_CONN_TASK_SETUP(ic, csio, task_tagp, prvp)); + return (ICL_CONN_TASK_SETUP(ic, ip, csio, task_tagp, prvp)); } static inline void @@ -135,4 +135,16 @@ icl_conn_transfer_done(struct icl_conn *ic, void *prv) ICL_CONN_TRANSFER_DONE(ic, prv); } +/* + * The function below is only used with ICL_KERNEL_PROXY. + */ +static inline int +icl_conn_connect(struct icl_conn *ic, int domain, int socktype, + int protocol, struct sockaddr *from_sa, struct sockaddr *to_sa) +{ + + return (ICL_CONN_CONNECT(ic, domain, socktype, protocol, + from_sa, to_sa)); +} + #endif /* !ICL_WRAPPERS_H */ diff --git a/sys/dev/iscsi/iscsi.c b/sys/dev/iscsi/iscsi.c index 7172ec0..62a9c32 100644 --- a/sys/dev/iscsi/iscsi.c +++ b/sys/dev/iscsi/iscsi.c @@ -43,6 +43,7 @@ __FBSDID("$FreeBSD$"); #include <sys/malloc.h> #include <sys/mutex.h> #include <sys/module.h> +#include <sys/socket.h> #include <sys/sysctl.h> #include <sys/systm.h> #include <sys/sx.h> @@ -172,7 +173,8 @@ static void iscsi_poll(struct cam_sim *sim); static struct iscsi_outstanding *iscsi_outstanding_find(struct iscsi_session *is, uint32_t initiator_task_tag); static struct iscsi_outstanding *iscsi_outstanding_add(struct iscsi_session *is, - union ccb *ccb, uint32_t *initiator_task_tagp); + struct icl_pdu *request, union ccb *ccb, + uint32_t *initiator_task_tagp); static void iscsi_outstanding_remove(struct iscsi_session *is, struct iscsi_outstanding *io); @@ -1558,7 +1560,7 @@ iscsi_ioctl_daemon_connect(struct iscsi_softc *sc, is->is_timeout = 0; ISCSI_SESSION_UNLOCK(is); - error = icl_conn_connect(is->is_conn, idc->idc_iser, idc->idc_domain, + error = icl_conn_connect(is->is_conn, idc->idc_domain, idc->idc_socktype, idc->idc_protocol, from_sa, to_sa); free(from_sa, M_SONAME); free(to_sa, M_SONAME); @@ -1618,7 +1620,9 @@ iscsi_ioctl_daemon_send(struct iscsi_softc *sc, KASSERT(error == 0, ("icl_pdu_append_data(..., M_WAITOK) failed")); free(data, M_ISCSI); } + ISCSI_SESSION_LOCK(is); icl_pdu_queue(ip); + ISCSI_SESSION_UNLOCK(is); return (0); } @@ -2012,7 +2016,7 @@ iscsi_outstanding_find_ccb(struct iscsi_session *is, union ccb *ccb) } static struct iscsi_outstanding * -iscsi_outstanding_add(struct iscsi_session *is, +iscsi_outstanding_add(struct iscsi_session *is, struct icl_pdu *request, union ccb *ccb, uint32_t *initiator_task_tagp) { struct iscsi_outstanding *io; @@ -2027,7 +2031,7 @@ iscsi_outstanding_add(struct iscsi_session *is, return (NULL); } - error = icl_conn_task_setup(is->is_conn, &ccb->csio, + error = icl_conn_task_setup(is->is_conn, request, &ccb->csio, initiator_task_tagp, &io->io_icl_prv); if (error != 0) { ISCSI_SESSION_WARN(is, @@ -2093,7 +2097,7 @@ iscsi_action_abort(struct iscsi_session *is, union ccb *ccb) initiator_task_tag = is->is_initiator_task_tag++; - io = iscsi_outstanding_add(is, NULL, &initiator_task_tag); + io = iscsi_outstanding_add(is, request, NULL, &initiator_task_tag); if (io == NULL) { icl_pdu_free(request); ccb->ccb_h.status = CAM_RESRC_UNAVAIL; @@ -2152,7 +2156,7 @@ iscsi_action_scsiio(struct iscsi_session *is, union ccb *ccb) } initiator_task_tag = is->is_initiator_task_tag++; - io = iscsi_outstanding_add(is, ccb, &initiator_task_tag); + io = iscsi_outstanding_add(is, request, ccb, &initiator_task_tag); if (io == NULL) { icl_pdu_free(request); if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { diff --git a/sys/dev/isp/isp.c b/sys/dev/isp/isp.c index ff1d29f..920b43b 100644 --- a/sys/dev/isp/isp.c +++ b/sys/dev/isp/isp.c @@ -3206,7 +3206,7 @@ isp_pdb_sync(ispsoftc_t *isp, int chan) case FC_PORTDB_STATE_DEAD: lp->state = FC_PORTDB_STATE_NIL; isp_async(isp, ISPASYNC_DEV_GONE, chan, lp); - if (lp->autologin == 0) { + if ((lp->portid & 0xffff00) != 0) { (void) isp_plogx(isp, chan, lp->handle, lp->portid, PLOGX_FLG_CMD_LOGO | @@ -3304,7 +3304,6 @@ isp_pdb_add_update(ispsoftc_t *isp, int chan, isp_pdb_t *pdb) } ISP_MEMZERO(lp, sizeof (fcportdb_t)); - lp->autologin = 1; lp->probational = 0; lp->state = FC_PORTDB_STATE_NEW; lp->portid = lp->new_portid = pdb->portid; @@ -3808,6 +3807,9 @@ fail: goto fail; } + if (lp->state == FC_PORTDB_STATE_ZOMBIE) + goto relogin; + /* * See if we're still logged into it. * @@ -6515,6 +6517,8 @@ isp_parse_status(ispsoftc_t *isp, ispstatusreq_t *sp, XS_T *xs, long *rp) { const char *reason; uint8_t sts = sp->req_completion_status & 0xff; + fcparam *fcp = FCPARAM(isp, 0); + fcportdb_t *lp; /* * It was there (maybe)- treat as a selection timeout. @@ -6532,8 +6536,8 @@ isp_parse_status(ispsoftc_t *isp, ispstatusreq_t *sp, XS_T *xs, long *rp) * to force a re-login of this unit. If we're on fabric, * then we'll have to log in again as a matter of course. */ - if (FCPARAM(isp, 0)->isp_topo == TOPO_NL_PORT || - FCPARAM(isp, 0)->isp_topo == TOPO_FL_PORT) { + if (fcp->isp_topo == TOPO_NL_PORT || + fcp->isp_topo == TOPO_FL_PORT) { mbreg_t mbs; MBSINIT(&mbs, MBOX_INIT_LIP, MBLOGALL, 0); if (ISP_CAP_2KLOGIN(isp)) { @@ -6542,7 +6546,12 @@ isp_parse_status(ispsoftc_t *isp, ispstatusreq_t *sp, XS_T *xs, long *rp) isp_mboxcmd_qnw(isp, &mbs, 1); } if (XS_NOERR(xs)) { - XS_SETERR(xs, HBA_SELTIMEOUT); + lp = &fcp->portdb[XS_TGT(xs)]; + if (lp->state == FC_PORTDB_STATE_ZOMBIE) { + *XS_STSP(xs) = SCSI_BUSY; + XS_SETERR(xs, HBA_TGTBSY); + } else + XS_SETERR(xs, HBA_SELTIMEOUT); } return; } @@ -6666,6 +6675,8 @@ isp_parse_status_24xx(ispsoftc_t *isp, isp24xx_statusreq_t *sp, XS_T *xs, long * { const char *reason; uint8_t sts = sp->req_completion_status & 0xff; + fcparam *fcp = FCPARAM(isp, XS_CHANNEL(xs)); + fcportdb_t *lp; /* * It was there (maybe)- treat as a selection timeout. @@ -6683,7 +6694,12 @@ isp_parse_status_24xx(ispsoftc_t *isp, isp24xx_statusreq_t *sp, XS_T *xs, long * * There is no MBOX_INIT_LIP for the 24XX. */ if (XS_NOERR(xs)) { - XS_SETERR(xs, HBA_SELTIMEOUT); + lp = &fcp->portdb[XS_TGT(xs)]; + if (lp->state == FC_PORTDB_STATE_ZOMBIE) { + *XS_STSP(xs) = SCSI_BUSY; + XS_SETERR(xs, HBA_TGTBSY); + } else + XS_SETERR(xs, HBA_SELTIMEOUT); } return; } diff --git a/sys/dev/isp/isp_freebsd.c b/sys/dev/isp/isp_freebsd.c index 8787d94..a734e55 100644 --- a/sys/dev/isp/isp_freebsd.c +++ b/sys/dev/isp/isp_freebsd.c @@ -1363,7 +1363,7 @@ isp_target_start_ctio(ispsoftc_t *isp, union ccb *ccb, enum Start_Ctio_How how) * and status, don't do it again and do the status portion now. */ if (atp->sendst) { - isp_prt(isp, ISP_LOGTINFO, "[0x%x] now sending synthesized status orig_dl=%u xfered=%u bit=%u", + isp_prt(isp, ISP_LOGTDEBUG0, "[0x%x] now sending synthesized status orig_dl=%u xfered=%u bit=%u", cso->tag_id, atp->orig_datalen, atp->bytes_xfered, atp->bytes_in_transit); xfrlen = 0; /* we already did the data transfer */ atp->sendst = 0; diff --git a/sys/dev/isp/isp_library.c b/sys/dev/isp/isp_library.c index 48e0535..f186e50 100644 --- a/sys/dev/isp/isp_library.c +++ b/sys/dev/isp/isp_library.c @@ -437,8 +437,8 @@ isp_dump_portdb(ispsoftc_t *isp, int chan) } isp_gen_role_str(buf1, sizeof (buf1), lp->prli_word3); isp_gen_role_str(buf2, sizeof (buf2), lp->new_prli_word3); - isp_prt(isp, ISP_LOGALL, "Chan %d [%d]: hdl 0x%x %s al%d %s 0x%06x =>%s 0x%06x; WWNN 0x%08x%08x WWPN 0x%08x%08x", - chan, i, lp->handle, dbs[lp->state], lp->autologin, buf1, lp->portid, buf2, lp->new_portid, + isp_prt(isp, ISP_LOGALL, "Chan %d [%d]: hdl 0x%x %s %s 0x%06x =>%s 0x%06x; WWNN 0x%08x%08x WWPN 0x%08x%08x", + chan, i, lp->handle, dbs[lp->state], buf1, lp->portid, buf2, lp->new_portid, (uint32_t) (lp->node_wwn >> 32), (uint32_t) (lp->node_wwn), (uint32_t) (lp->port_wwn >> 32), (uint32_t) (lp->port_wwn)); } } diff --git a/sys/dev/isp/isp_target.c b/sys/dev/isp/isp_target.c index 07c9b59..702bcf9 100644 --- a/sys/dev/isp/isp_target.c +++ b/sys/dev/isp/isp_target.c @@ -775,18 +775,17 @@ isp_got_tmf_24xx(ispsoftc_t *isp, at7_entry_t *aep) notify.nt_tagval |= (((uint64_t)(isp->isp_serno++)) << 32); notify.nt_lreserved = aep; sid = (aep->at_hdr.s_id[0] << 16) | (aep->at_hdr.s_id[1] << 8) | (aep->at_hdr.s_id[2]); - - /* Channel has to derived from D_ID */ did = (aep->at_hdr.d_id[0] << 16) | (aep->at_hdr.d_id[1] << 8) | aep->at_hdr.d_id[2]; - for (chan = 0; chan < isp->isp_nchan; chan++) { - if (FCPARAM(isp, chan)->isp_portid == did) { - break; + if (ISP_CAP_MULTI_ID(isp) && isp->isp_nchan > 1) { + /* Channel has to be derived from D_ID */ + isp_find_chan_by_did(isp, did, &chan); + if (chan == ISP_NOCHAN) { + isp_prt(isp, ISP_LOGWARN, "%s: D_ID 0x%x not found on any channel", __func__, did); + /* just drop on the floor */ + return; } - } - if (chan == isp->isp_nchan) { - isp_prt(isp, ISP_LOGWARN, "%s: D_ID 0x%x not found on any channel", __func__, did); - /* just drop on the floor */ - return; + } else { + chan = 0; } notify.nt_nphdl = NIL_HANDLE; /* unknown here */ notify.nt_sid = sid; diff --git a/sys/dev/isp/ispvar.h b/sys/dev/isp/ispvar.h index fe06a98..fef13e3 100644 --- a/sys/dev/isp/ispvar.h +++ b/sys/dev/isp/ispvar.h @@ -380,9 +380,6 @@ typedef struct { uint16_t handle; /* - * A device is 'autologin' if the firmware automatically logs into - * it (re-logins as needed). Basically, local private loop devices. - * * PRLI word 3 parameters contains role as well as other things. * * The state is the current state of this entry. @@ -396,8 +393,7 @@ typedef struct { */ uint16_t prli_word3; /* PRLI parameters */ uint16_t new_prli_word3; /* Incoming new PRLI parameters */ - uint16_t : 11, - autologin : 1, /* F/W does PLOGI/PLOGO */ + uint16_t : 12, probational : 1, state : 3; uint32_t : 6, diff --git a/sys/dev/iwm/if_iwmreg.h b/sys/dev/iwm/if_iwmreg.h index 1fc438b..bbfb36ee 100644 --- a/sys/dev/iwm/if_iwmreg.h +++ b/sys/dev/iwm/if_iwmreg.h @@ -3923,7 +3923,7 @@ enum iwm_tx_flags { * cleared. Combination of IWM_RATE_MCS_* * @sta_id: index of destination station in FW station table * @sec_ctl: security control, IWM_TX_CMD_SEC_* - * @initial_rate_index: index into the the rate table for initial TX attempt. + * @initial_rate_index: index into the rate table for initial TX attempt. * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. * @key: security key * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* @@ -4274,7 +4274,7 @@ struct iwm_beacon_notif { /** * enum iwm_dump_control - dump (flush) control flags - * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the the FIFO is empty + * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty * and the TFD queues are empty. */ enum iwm_dump_control { diff --git a/sys/dev/kbd/kbd.c b/sys/dev/kbd/kbd.c index 389ef75..6a38608 100644 --- a/sys/dev/kbd/kbd.c +++ b/sys/dev/kbd/kbd.c @@ -996,7 +996,7 @@ genkbd_commonioctl(keyboard_t *kbd, u_long cmd, caddr_t arg) splx(s); return (error); } - kbd->kb_fkeytab[fkeyp->keynum].len = imin(fkeyp->flen, MAXFK); + kbd->kb_fkeytab[fkeyp->keynum].len = min(fkeyp->flen, MAXFK); bcopy(fkeyp->keydef, kbd->kb_fkeytab[fkeyp->keynum].str, kbd->kb_fkeytab[fkeyp->keynum].len); break; diff --git a/sys/dev/le/lebuffer_sbus.c b/sys/dev/le/lebuffer_sbus.c index f2c7c5f..1dc9488 100644 --- a/sys/dev/le/lebuffer_sbus.c +++ b/sys/dev/le/lebuffer_sbus.c @@ -197,7 +197,7 @@ lebuffer_setup_dinfo(device_t dev, phandle_t node) if (slot != -1 && slot != rslot) { device_printf(dev, "<%s>: multiple slots\n", ldi->ldi_obdinfo.obd_name); - free(reg, M_OFWPROP); + OF_prop_free(reg); goto fail; } slot = rslot; @@ -205,7 +205,7 @@ lebuffer_setup_dinfo(device_t dev, phandle_t node) resource_list_add(&ldi->ldi_rl, SYS_RES_MEMORY, i, base, base + reg[i].sbr_size, reg[i].sbr_size); } - free(reg, M_OFWPROP); + OF_prop_free(reg); if (slot != sbus_get_slot(dev)) { device_printf(dev, "<%s>: parent and child slot do not match\n", ldi->ldi_obdinfo.obd_name); @@ -231,7 +231,7 @@ lebuffer_setup_dinfo(device_t dev, phandle_t node) resource_list_add(&ldi->ldi_rl, SYS_RES_IRQ, i, iv, iv, 1); } - free(intr, M_OFWPROP); + OF_prop_free(intr); } return (ldi); diff --git a/sys/dev/mwl/mwlhal.c b/sys/dev/mwl/mwlhal.c index 092f5f8..41f1b8f 100644 --- a/sys/dev/mwl/mwlhal.c +++ b/sys/dev/mwl/mwlhal.c @@ -1440,7 +1440,7 @@ mwl_hal_bastream_alloc(struct mwl_hal_vap *vap, int ba_policy, sp->setup = 0; sp->ba_policy = ba_policy; MWL_HAL_UNLOCK(mh); - return sp != NULL ? &sp->public : NULL; + return &sp->public; } const MWL_HAL_BASTREAM * diff --git a/sys/dev/netmap/netmap.c b/sys/dev/netmap/netmap.c index ee38452..aff757b 100644 --- a/sys/dev/netmap/netmap.c +++ b/sys/dev/netmap/netmap.c @@ -2700,7 +2700,7 @@ netmap_detach_common(struct netmap_adapter *na) } /* Wrapper for the register callback provided hardware drivers. - * na->ifp == NULL means the the driver module has been + * na->ifp == NULL means the driver module has been * unloaded, so we cannot call into it. * Note that module unloading, in our patched linux drivers, * happens under NMG_LOCK and after having stopped all the diff --git a/sys/dev/ntb/ntb_hw/ntb_hw.c b/sys/dev/ntb/ntb_hw/ntb_hw.c index c1949f7..456dd61 100644 --- a/sys/dev/ntb/ntb_hw/ntb_hw.c +++ b/sys/dev/ntb/ntb_hw/ntb_hw.c @@ -364,6 +364,8 @@ static bool ntb_poll_link(struct ntb_softc *ntb); static void save_bar_parameters(struct ntb_pci_bar_info *bar); static void ntb_sysctl_init(struct ntb_softc *); static int sysctl_handle_features(SYSCTL_HANDLER_ARGS); +static int sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS); +static int sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS); static int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); static int sysctl_handle_register(SYSCTL_HANDLER_ARGS); @@ -2132,6 +2134,8 @@ ntb_link_enable(struct ntb_softc *ntb, enum ntb_speed s __unused, { uint32_t cntl; + ntb_printf(2, "%s\n", __func__); + if (ntb->type == NTB_ATOM) { pci_write_config(ntb->device, NTB_PPD_OFFSET, ntb->ppd | ATOM_PPD_INIT_LINK, 4); @@ -2170,6 +2174,8 @@ ntb_link_disable(struct ntb_softc *ntb) { uint32_t cntl; + ntb_printf(2, "%s\n", __func__); + if (ntb->conn_type == NTB_CONN_TRANSPARENT) { ntb_link_event(ntb); return (0); @@ -2185,6 +2191,23 @@ ntb_link_disable(struct ntb_softc *ntb) return (0); } +bool +ntb_link_enabled(struct ntb_softc *ntb) +{ + uint32_t cntl; + + if (ntb->type == NTB_ATOM) { + cntl = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); + return ((cntl & ATOM_PPD_INIT_LINK) != 0); + } + + if (ntb->conn_type == NTB_CONN_TRANSPARENT) + return (true); + + cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); + return ((cntl & NTB_CNTL_LINK_DISABLE) == 0); +} + static void recover_atom_link(void *arg) { @@ -2304,16 +2327,26 @@ SYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0, static void ntb_sysctl_init(struct ntb_softc *ntb) { - struct sysctl_oid_list *tree_par, *regpar, *statpar, *errpar; + struct sysctl_oid_list *globals, *tree_par, *regpar, *statpar, *errpar; struct sysctl_ctx_list *ctx; struct sysctl_oid *tree, *tmptree; ctx = device_get_sysctl_ctx(ntb->device); - - tree = SYSCTL_ADD_NODE(ctx, - SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)), OID_AUTO, - "debug_info", CTLFLAG_RD, NULL, - "Driver state, statistics, and HW registers"); + globals = SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)); + + SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "link_status", + CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, + sysctl_handle_link_status_human, "A", + "Link status (human readable)"); + SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "active", + CTLFLAG_RD | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_status, + "IU", "Link status (1=active, 0=inactive)"); + SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "admin_up", + CTLFLAG_RW | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_admin, + "IU", "Set/get interface status (1=UP, 0=DOWN)"); + + tree = SYSCTL_ADD_NODE(ctx, globals, OID_AUTO, "debug_info", + CTLFLAG_RD, NULL, "Driver state, statistics, and HW registers"); tree_par = SYSCTL_CHILDREN(tree); SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, @@ -2343,10 +2376,6 @@ ntb_sysctl_init(struct ntb_softc *ntb) __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0, "LNK STA register (cached)"); - SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "link_status", - CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_link_status, - "A", "Link status"); - SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, &ntb->mw_count, 0, "MW count"); SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, @@ -2592,7 +2621,37 @@ sysctl_handle_features(SYSCTL_HANDLER_ARGS) } static int -sysctl_handle_link_status(SYSCTL_HANDLER_ARGS) +sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS) +{ + struct ntb_softc *ntb; + unsigned old, new; + int error; + + error = 0; + ntb = arg1; + + old = ntb_link_enabled(ntb); + + error = SYSCTL_OUT(req, &old, sizeof(old)); + if (error != 0 || req->newptr == NULL) + return (error); + + error = SYSCTL_IN(req, &new, sizeof(new)); + if (error != 0) + return (error); + + ntb_printf(0, "Admin set interface state to '%sabled'\n", + (new != 0)? "en" : "dis"); + + if (new != 0) + error = ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); + else + error = ntb_link_disable(ntb); + return (error); +} + +static int +sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS) { struct ntb_softc *ntb; struct sbuf sb; @@ -2620,6 +2679,24 @@ sysctl_handle_link_status(SYSCTL_HANDLER_ARGS) } static int +sysctl_handle_link_status(SYSCTL_HANDLER_ARGS) +{ + struct ntb_softc *ntb; + unsigned res; + int error; + + error = 0; + ntb = arg1; + + res = ntb_link_is_up(ntb, NULL, NULL); + + error = SYSCTL_OUT(req, &res, sizeof(res)); + if (error || !req->newptr) + return (error); + return (EINVAL); +} + +static int sysctl_handle_register(SYSCTL_HANDLER_ARGS) { struct ntb_softc *ntb; diff --git a/sys/dev/ntb/ntb_hw/ntb_hw.h b/sys/dev/ntb/ntb_hw/ntb_hw.h index e2f45b2..f05acda 100644 --- a/sys/dev/ntb/ntb_hw/ntb_hw.h +++ b/sys/dev/ntb/ntb_hw/ntb_hw.h @@ -70,6 +70,7 @@ bool ntb_link_is_up(struct ntb_softc *, enum ntb_speed *, enum ntb_width *); void ntb_link_event(struct ntb_softc *); int ntb_link_enable(struct ntb_softc *, enum ntb_speed, enum ntb_width); int ntb_link_disable(struct ntb_softc *); +bool ntb_link_enabled(struct ntb_softc *); int ntb_set_ctx(struct ntb_softc *, void *, const struct ntb_ctx_ops *); void *ntb_get_ctx(struct ntb_softc *, const struct ntb_ctx_ops **); diff --git a/sys/dev/ow/ow.c b/sys/dev/ow/ow.c index f5b5c6b..66db4b7 100644 --- a/sys/dev/ow/ow.c +++ b/sys/dev/ow/ow.c @@ -343,7 +343,7 @@ again: * See AN397 section 5.II.C.3 for the algorithm (though a bit * poorly stated). The search command forces each device to * send ROM ID bits one at a time (first the bit, then the - * complement) the the master (us) sends back a bit. If the + * complement) the master (us) sends back a bit. If the * device's bit doesn't match what we send back, that device * stops sending bits back. So each time through we remember * where we made the last decision (always 0). If there's a @@ -401,6 +401,8 @@ again: if (++retries > 5) return (EIO); goto again; + default: /* NOTREACHED */ + __unreachable(); } if (dir) { OWLL_WRITE_ONE(lldev, &timing_regular); diff --git a/sys/dev/pci/pci_host_generic.c b/sys/dev/pci/pci_host_generic.c index 9be0a03..8cc0b79 100644 --- a/sys/dev/pci/pci_host_generic.c +++ b/sys/dev/pci/pci_host_generic.c @@ -235,10 +235,6 @@ pci_host_generic_attach(device_t dev) node = ofw_bus_get_node(dev); ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); - /* Find the MSI interrupt handler */ - OF_searchencprop(node, "msi-parent", &sc->msi_parent, - sizeof(sc->msi_parent)); - device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); } @@ -671,10 +667,11 @@ generic_pcie_alloc_msi(device_t pci, device_t child, int count, int maxcount, int *irqs) { #if defined(INTRNG) - struct generic_pcie_softc *sc; + phandle_t msi_parent; - sc = device_get_softc(pci); - return (intr_alloc_msi(pci, child, sc->msi_parent, count, maxcount, + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, irqs)); #elif defined(__aarch64__) return (arm_alloc_msi(pci, child, count, maxcount, irqs)); @@ -687,10 +684,11 @@ static int generic_pcie_release_msi(device_t pci, device_t child, int count, int *irqs) { #if defined(INTRNG) - struct generic_pcie_softc *sc; + phandle_t msi_parent; - sc = device_get_softc(pci); - return (intr_release_msi(pci, child, sc->msi_parent, count, irqs)); + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_release_msi(pci, child, msi_parent, count, irqs)); #elif defined(__aarch64__) return (arm_release_msi(pci, child, count, irqs)); #else @@ -703,10 +701,11 @@ generic_pcie_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, uint32_t *data) { #if defined(INTRNG) - struct generic_pcie_softc *sc; + phandle_t msi_parent; - sc = device_get_softc(pci); - return (intr_map_msi(pci, child, sc->msi_parent, irq, addr, data)); + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); #elif defined(__aarch64__) return (arm_map_msi(pci, child, irq, addr, data)); #else @@ -718,10 +717,11 @@ static int generic_pcie_alloc_msix(device_t pci, device_t child, int *irq) { #if defined(INTRNG) - struct generic_pcie_softc *sc; + phandle_t msi_parent; - sc = device_get_softc(pci); - return (intr_alloc_msix(pci, child, sc->msi_parent, irq)); + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_alloc_msix(pci, child, msi_parent, irq)); #elif defined(__aarch64__) return (arm_alloc_msix(pci, child, irq)); #else @@ -733,10 +733,11 @@ static int generic_pcie_release_msix(device_t pci, device_t child, int irq) { #if defined(INTRNG) - struct generic_pcie_softc *sc; + phandle_t msi_parent; - sc = device_get_softc(pci); - return (intr_release_msix(pci, child, sc->msi_parent, irq)); + ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, + NULL); + return (intr_release_msix(pci, child, msi_parent, irq)); #elif defined(__aarch64__) return (arm_release_msix(pci, child, irq)); #else diff --git a/sys/dev/pci/pci_host_generic.h b/sys/dev/pci/pci_host_generic.h index 050ac6d..2f8bd83 100644 --- a/sys/dev/pci/pci_host_generic.h +++ b/sys/dev/pci/pci_host_generic.h @@ -60,7 +60,6 @@ struct generic_pcie_softc { bus_space_handle_t ioh; #ifdef FDT struct ofw_bus_iinfo pci_iinfo; - phandle_t msi_parent; #endif }; diff --git a/sys/dev/pci/pci_pci.c b/sys/dev/pci/pci_pci.c index 5e14e95..afc0a08 100644 --- a/sys/dev/pci/pci_pci.c +++ b/sys/dev/pci/pci_pci.c @@ -874,8 +874,11 @@ pcib_probe_hotplug(struct pcib_softc *sc) /* * Send a HotPlug command to the slot control register. If this slot - * uses command completion interrupts, these updates will be buffered - * while a previous command is completing. + * uses command completion interrupts and a previous command is still + * in progress, then the command is dropped. Once the previous + * command completes or times out, pcib_pcie_hotplug_update() will be + * invoked to post a new command based on the slot's state at that + * time. */ static void pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) @@ -884,28 +887,20 @@ pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) uint16_t ctl, new; dev = sc->dev; - if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) { - ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); - new = (ctl & ~mask) | val; - if (new != ctl) - pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); + + if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) return; - } - if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { - sc->pcie_pending_link_ctl_val &= ~mask; - sc->pcie_pending_link_ctl_val |= val; - sc->pcie_pending_link_ctl_mask |= mask; - } else { - ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); - new = (ctl & ~mask) | val; - if (new != ctl) { - pcie_write_config(dev, PCIER_SLOT_CTL, ctl, 2); - sc->flags |= PCIB_HOTPLUG_CMD_PENDING; - if (!cold) - callout_reset(&sc->pcie_cc_timer, hz, - pcib_pcie_cc_timeout, sc); - } + ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); + new = (ctl & ~mask) | val; + if (new == ctl) + return; + pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); + if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) { + sc->flags |= PCIB_HOTPLUG_CMD_PENDING; + if (!cold) + callout_reset(&sc->pcie_cc_timer, hz, + pcib_pcie_cc_timeout, sc); } } @@ -913,7 +908,6 @@ static void pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) { device_t dev; - uint16_t ctl, new; dev = sc->dev; @@ -921,23 +915,8 @@ pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) device_printf(dev, "Command Completed\n"); if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) return; - if (sc->pcie_pending_link_ctl_mask != 0) { - ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); - new = ctl & ~sc->pcie_pending_link_ctl_mask; - new |= sc->pcie_pending_link_ctl_val; - if (new != ctl) { - pcie_write_config(dev, PCIER_SLOT_CTL, ctl, 2); - if (!cold) - callout_reset(&sc->pcie_cc_timer, hz, - pcib_pcie_cc_timeout, sc); - } else - sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; - sc->pcie_pending_link_ctl_mask = 0; - sc->pcie_pending_link_ctl_val = 0; - } else { - callout_stop(&sc->pcie_cc_timer); - sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; - } + callout_stop(&sc->pcie_cc_timer); + sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; } /* @@ -1041,11 +1020,10 @@ pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, * Interlock. */ if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) { + mask |= PCIEM_SLOT_CTL_EIC; if (card_inserted != - !(sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS)) { - mask |= PCIEM_SLOT_CTL_EIC; + !(sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS)) val |= PCIEM_SLOT_CTL_EIC; - } } /* diff --git a/sys/dev/pci/pcib_private.h b/sys/dev/pci/pcib_private.h index 7d43e60..2d805a9 100644 --- a/sys/dev/pci/pcib_private.h +++ b/sys/dev/pci/pcib_private.h @@ -134,8 +134,6 @@ struct pcib_softc uint16_t pcie_slot_sta; uint32_t pcie_link_cap; uint32_t pcie_slot_cap; - uint16_t pcie_pending_link_ctl_mask; - uint16_t pcie_pending_link_ctl_val; struct resource *pcie_irq; void *pcie_ihand; struct task pcie_hp_task; diff --git a/sys/dev/pms/RefTisa/sallsdk/spc/mpi.c b/sys/dev/pms/RefTisa/sallsdk/spc/mpi.c index 1c5800e..3e9fc3d 100644 --- a/sys/dev/pms/RefTisa/sallsdk/spc/mpi.c +++ b/sys/dev/pms/RefTisa/sallsdk/spc/mpi.c @@ -806,7 +806,7 @@ mpiMsgConsume( * \param messagePtr1 Pointer to the returned message buffer to free * \param messagePtr2 Pointer to the returned message buffer to free if bc > 1 * - * Returns consumed and processed message to the the specified outbounf queue + * Returns consumed and processed message to the specified outbounf queue * * Return: * AGSA_RC_SUCCESS if the message has been returned succesfully diff --git a/sys/dev/pms/RefTisa/sat/src/smsat.c b/sys/dev/pms/RefTisa/sat/src/smsat.c index 8b6aaeb..2860188 100644 --- a/sys/dev/pms/RefTisa/sat/src/smsat.c +++ b/sys/dev/pms/RefTisa/sat/src/smsat.c @@ -10883,7 +10883,7 @@ smsatReadCapacity10( /* * Setting RETURNED LOGICAL BLOCK ADDRESS in READ CAPACITY(10) response data: * SBC-2 specifies that if the capacity exceeded the 4-byte RETURNED LOGICAL - * BLOCK ADDRESS in READ CAPACITY(10) parameter data, the the RETURNED LOGICAL + * BLOCK ADDRESS in READ CAPACITY(10) parameter data, the RETURNED LOGICAL * BLOCK ADDRESS should be set to 0xFFFFFFFF so the application client would * then issue a READ CAPACITY(16) command. */ diff --git a/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.c b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.c index e46fb32..2b0ae73 100644 --- a/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.c +++ b/sys/dev/pms/RefTisa/tisa/sassata/sata/host/sat.c @@ -5975,7 +5975,7 @@ GLOBAL bit32 satReadCapacity10( /* * Setting RETURNED LOGICAL BLOCK ADDRESS in READ CAPACITY(10) response data: * SBC-2 specifies that if the capacity exceeded the 4-byte RETURNED LOGICAL - * BLOCK ADDRESS in READ CAPACITY(10) parameter data, the the RETURNED LOGICAL + * BLOCK ADDRESS in READ CAPACITY(10) parameter data, the RETURNED LOGICAL * BLOCK ADDRESS should be set to 0xFFFFFFFF so the application client would * then issue a READ CAPACITY(16) command. */ diff --git a/sys/dev/ral/rt2860.c b/sys/dev/ral/rt2860.c index bcd276e..e58abc1 100644 --- a/sys/dev/ral/rt2860.c +++ b/sys/dev/ral/rt2860.c @@ -165,7 +165,7 @@ static void rt2860_delete_key(struct ieee80211com *, struct ieee80211_node *, struct ieee80211_key *); #endif static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); -static const char *rt2860_get_rf(uint8_t); +static const char *rt2860_get_rf(uint16_t); static int rt2860_read_eeprom(struct rt2860_softc *, uint8_t macaddr[IEEE80211_ADDR_LEN]); static int rt2860_bbp_init(struct rt2860_softc *); @@ -3307,7 +3307,7 @@ b4inc(uint32_t b32, int8_t delta) } static const char * -rt2860_get_rf(uint8_t rev) +rt2860_get_rf(uint16_t rev) { switch (rev) { case RT2860_RF_2820: return "RT2820"; @@ -3321,6 +3321,7 @@ rt2860_get_rf(uint8_t rev) case RT3070_RF_3052: return "RT3052"; case RT3070_RF_3320: return "RT3320"; case RT3070_RF_3053: return "RT3053"; + case RT5390_RF_5360: return "RT5360"; case RT5390_RF_5390: return "RT5390"; default: return "unknown"; } @@ -3343,9 +3344,11 @@ rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) sc->sc_srom_read = rt3090_efuse_read_2; } +#ifdef RAL_DEBUG /* read EEPROM version */ val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); +#endif /* read MAC address */ val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); @@ -3358,9 +3361,11 @@ rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) macaddr[4] = val & 0xff; macaddr[5] = val >> 8; +#ifdef RAL_DEBUG /* read country code */ val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); DPRINTF(("EEPROM region code=0x%04x\n", val)); +#endif /* read vendor BBP settings */ for (i = 0; i < 8; i++) { @@ -3402,39 +3407,12 @@ rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) /* read RF information */ val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); - if (val == 0xffff) { - DPRINTF(("invalid EEPROM antenna info, using default\n")); - if (sc->mac_ver >= 0x5390) { - /* default to RF5390 */ - sc->rf_rev = RT5390_RF_5390; - sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1; - sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1; - } else if (sc->mac_ver == 0x3593) { - /* default to RF3053 3T3R */ - sc->rf_rev = RT3070_RF_3053; - sc->ntxchains = 3; - sc->nrxchains = 3; - } else if (sc->mac_ver >= 0x3071) { - /* default to RF3020 1T1R */ - sc->rf_rev = RT3070_RF_3020; - sc->ntxchains = 1; - sc->nrxchains = 1; - } else { - /* default to RF2820 1T2R */ - sc->rf_rev = RT2860_RF_2820; - sc->ntxchains = 1; - sc->nrxchains = 2; - } - } else { + if (sc->mac_ver >= 0x5390) + sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); + else sc->rf_rev = (val >> 8) & 0xf; - if (sc->mac_ver >= 0x5390) { - sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1; - sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1; - } else { - sc->ntxchains = (val >> 4) & 0xf; - sc->nrxchains = val & 0xf; - } - } + sc->ntxchains = (val >> 4) & 0xf; + sc->nrxchains = val & 0xf; DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", sc->rf_rev, sc->ntxchains, sc->nrxchains)); diff --git a/sys/dev/ral/rt2860reg.h b/sys/dev/ral/rt2860reg.h index 3d507be..5bd7dbb 100644 --- a/sys/dev/ral/rt2860reg.h +++ b/sys/dev/ral/rt2860reg.h @@ -900,18 +900,19 @@ struct rt2860_rxwi { #define RT2860_RF3 1 #define RT2860_RF4 3 -#define RT2860_RF_2820 1 /* 2T3R */ -#define RT2860_RF_2850 2 /* dual-band 2T3R */ -#define RT2860_RF_2720 3 /* 1T2R */ -#define RT2860_RF_2750 4 /* dual-band 1T2R */ -#define RT3070_RF_3020 5 /* 1T1R */ -#define RT3070_RF_2020 6 /* b/g */ -#define RT3070_RF_3021 7 /* 1T2R */ -#define RT3070_RF_3022 8 /* 2T2R */ -#define RT3070_RF_3052 9 /* dual-band 2T2R */ -#define RT3070_RF_3320 11 /* 1T1R */ -#define RT3070_RF_3053 13 /* dual-band 3T3R */ -#define RT5390_RF_5390 15 /* b/g/n */ +#define RT2860_RF_2820 0x0001 /* 2T3R */ +#define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ +#define RT2860_RF_2720 0x0003 /* 1T2R */ +#define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ +#define RT3070_RF_3020 0x0005 /* 1T1R */ +#define RT3070_RF_2020 0x0006 /* b/g */ +#define RT3070_RF_3021 0x0007 /* 1T2R */ +#define RT3070_RF_3022 0x0008 /* 2T2R */ +#define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ +#define RT3070_RF_3320 0x000b /* 1T1R */ +#define RT3070_RF_3053 0x000d /* dual-band 3T3R */ +#define RT5390_RF_5360 0x5360 /* 1T1R */ +#define RT5390_RF_5390 0x5390 /* 1T1R */ /* USB commands for RT2870 only */ #define RT2870_RESET 1 @@ -922,6 +923,7 @@ struct rt2860_rxwi { #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ +#define RT2860_EEPROM_CHIPID 0x00 #define RT2860_EEPROM_VERSION 0x01 #define RT2860_EEPROM_MAC01 0x02 #define RT2860_EEPROM_MAC23 0x03 diff --git a/sys/dev/ral/rt2860var.h b/sys/dev/ral/rt2860var.h index 6d3765a..71b4fde 100644 --- a/sys/dev/ral/rt2860var.h +++ b/sys/dev/ral/rt2860var.h @@ -159,7 +159,7 @@ struct rt2860_softc { uint16_t mac_ver; uint16_t mac_rev; - uint8_t rf_rev; + uint16_t rf_rev; uint8_t freq; uint8_t ntxchains; uint8_t nrxchains; diff --git a/sys/dev/random/fortuna.c b/sys/dev/random/fortuna.c index 3ae0fe0..e300c6f 100644 --- a/sys/dev/random/fortuna.c +++ b/sys/dev/random/fortuna.c @@ -234,7 +234,7 @@ random_fortuna_process_event(struct harvest_event *event) pl = event->he_destination % RANDOM_FORTUNA_NPOOLS; randomdev_hash_iterate(&fortuna_state.fs_pool[pl].fsp_hash, event, sizeof(*event)); /*- - * Don't wrap the length. Doing the the hard way so as not to wrap at MAXUINT. + * Don't wrap the length. Doing this the hard way so as not to wrap at MAXUINT. * This is a "saturating" add. * XXX: FIX!!: We don't actually need lengths for anything but fs_pool[0], * but it's been useful debugging to see them all. diff --git a/sys/dev/rtwn/if_rtwn.c b/sys/dev/rtwn/if_rtwn.c index f24fa1d..b00be6c 100644 --- a/sys/dev/rtwn/if_rtwn.c +++ b/sys/dev/rtwn/if_rtwn.c @@ -1789,7 +1789,6 @@ rtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, } if (rtwn_tx(sc, m, ni) != 0) { - m_freem(m); RTWN_UNLOCK(sc); return (EIO); } diff --git a/sys/dev/sfxge/common/ef10_ev.c b/sys/dev/sfxge/common/ef10_ev.c index 839ec5e..548b9a1 100644 --- a/sys/dev/sfxge/common/ef10_ev.c +++ b/sys/dev/sfxge/common/ef10_ev.c @@ -547,7 +547,7 @@ ef10_ev_rx( flags |= EFX_PKT_PREFIX_LEN; } - /* Calculate the index of the the last descriptor consumed */ + /* Calculate the index of the last descriptor consumed */ last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask; /* Check for errors that invalidate checksum and L3/L4 fields */ diff --git a/sys/dev/sfxge/common/ef10_impl.h b/sys/dev/sfxge/common/ef10_impl.h index 8f4bd27..eb29fe7 100644 --- a/sys/dev/sfxge/common/ef10_impl.h +++ b/sys/dev/sfxge/common/ef10_impl.h @@ -236,6 +236,11 @@ ef10_mac_pdu_set( __in efx_nic_t *enp); extern __checkReturn efx_rc_t +ef10_mac_pdu_get( + __in efx_nic_t *enp, + __out size_t *pdu); + +extern __checkReturn efx_rc_t ef10_mac_reconfigure( __in efx_nic_t *enp); @@ -1056,7 +1061,9 @@ efx_mcdi_get_mac_address_vf( extern __checkReturn efx_rc_t efx_mcdi_get_clock( __in efx_nic_t *enp, - __out uint32_t *sys_freqp); + __out uint32_t *sys_freqp, + __out uint32_t *dpcpu_freqp); + extern __checkReturn efx_rc_t efx_mcdi_get_vector_cfg( diff --git a/sys/dev/sfxge/common/ef10_mac.c b/sys/dev/sfxge/common/ef10_mac.c index 6546ef1..ccd27c3 100644 --- a/sys/dev/sfxge/common/ef10_mac.c +++ b/sys/dev/sfxge/common/ef10_mac.c @@ -199,6 +199,53 @@ fail1: return (rc); } +static __checkReturn efx_rc_t +efx_mcdi_mtu_get( + __in efx_nic_t *enp, + __out size_t *mtu) +{ + efx_mcdi_req_t req; + uint8_t payload[MAX(MC_CMD_SET_MAC_EXT_IN_LEN, + MC_CMD_SET_MAC_V2_OUT_LEN)]; + efx_rc_t rc; + + (void) memset(payload, 0, sizeof (payload)); + req.emr_cmd = MC_CMD_SET_MAC; + req.emr_in_buf = payload; + req.emr_in_length = MC_CMD_SET_MAC_EXT_IN_LEN; + req.emr_out_buf = payload; + req.emr_out_length = MC_CMD_SET_MAC_V2_OUT_LEN; + + /* + * With MC_CMD_SET_MAC_EXT_IN_CONTROL set to 0, this just queries the + * MTU. This should always be supported on Medford, but it is not + * supported on older Huntington firmware. + */ + MCDI_IN_SET_DWORD(req, SET_MAC_EXT_IN_CONTROL, 0); + + efx_mcdi_execute(enp, &req); + + if (req.emr_rc != 0) { + rc = req.emr_rc; + goto fail1; + } + if (req.emr_out_length_used < MC_CMD_SET_MAC_V2_OUT_MTU_OFST + 4) { + rc = EMSGSIZE; + goto fail2; + } + + *mtu = MCDI_OUT_DWORD(req, SET_MAC_V2_OUT_MTU); + + return (0); + +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + __checkReturn efx_rc_t ef10_mac_pdu_set( __in efx_nic_t *enp) @@ -230,6 +277,24 @@ fail1: return (rc); } + __checkReturn efx_rc_t +ef10_mac_pdu_get( + __in efx_nic_t *enp, + __out size_t *pdu) +{ + efx_rc_t rc; + + if ((rc = efx_mcdi_mtu_get(enp, pdu)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + __checkReturn efx_rc_t ef10_mac_reconfigure( __in efx_nic_t *enp) diff --git a/sys/dev/sfxge/common/ef10_nic.c b/sys/dev/sfxge/common/ef10_nic.c index 507aad5..25f6fea 100644 --- a/sys/dev/sfxge/common/ef10_nic.c +++ b/sys/dev/sfxge/common/ef10_nic.c @@ -389,7 +389,8 @@ fail1: __checkReturn efx_rc_t efx_mcdi_get_clock( __in efx_nic_t *enp, - __out uint32_t *sys_freqp) + __out uint32_t *sys_freqp, + __out uint32_t *dpcpu_freqp) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN, @@ -423,9 +424,16 @@ efx_mcdi_get_clock( rc = EINVAL; goto fail3; } + *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ); + if (*dpcpu_freqp == 0) { + rc = EINVAL; + goto fail4; + } return (0); +fail4: + EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: diff --git a/sys/dev/sfxge/common/efx.h b/sys/dev/sfxge/common/efx.h index a554065..705792d 100644 --- a/sys/dev/sfxge/common/efx.h +++ b/sys/dev/sfxge/common/efx.h @@ -442,18 +442,30 @@ typedef enum efx_link_mode_e { #define EFX_MAC_SDU_MAX 9202 -#define EFX_MAC_PDU(_sdu) \ - P2ROUNDUP(((_sdu) \ - + /* EtherII */ 14 \ - + /* VLAN */ 4 \ - + /* CRC */ 4 \ - + /* bug16011 */ 16), \ - (1 << 3)) +#define EFX_MAC_PDU_ADJUSTMENT \ + (/* EtherII */ 14 \ + + /* VLAN */ 4 \ + + /* CRC */ 4 \ + + /* bug16011 */ 16) \ + +#define EFX_MAC_PDU(_sdu) \ + P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) + +/* + * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give + * the SDU rounded up slightly. + */ +#define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) #define EFX_MAC_PDU_MIN 60 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) extern __checkReturn efx_rc_t +efx_mac_pdu_get( + __in efx_nic_t *enp, + __out size_t *pdu); + +extern __checkReturn efx_rc_t efx_mac_pdu_set( __in efx_nic_t *enp, __in size_t pdu); @@ -2314,6 +2326,10 @@ extern void efx_lic_fini( __in efx_nic_t *enp); +extern __checkReturn boolean_t +efx_lic_check_support( + __in efx_nic_t *enp); + extern __checkReturn efx_rc_t efx_lic_update_licenses( __in efx_nic_t *enp); diff --git a/sys/dev/sfxge/common/efx_impl.h b/sys/dev/sfxge/common/efx_impl.h index b4652b4..00e6e81 100644 --- a/sys/dev/sfxge/common/efx_impl.h +++ b/sys/dev/sfxge/common/efx_impl.h @@ -183,6 +183,7 @@ typedef struct efx_mac_ops_s { efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); efx_rc_t (*emo_addr_set)(efx_nic_t *); efx_rc_t (*emo_pdu_set)(efx_nic_t *); + efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); efx_rc_t (*emo_reconfigure)(efx_nic_t *); efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, @@ -636,6 +637,7 @@ struct efx_nic_s { uint32_t en_vport_id; #if EFSYS_OPT_LICENSING const efx_lic_ops_t *en_elop; + boolean_t en_licensing_supported; #endif union { #if EFSYS_OPT_SIENA diff --git a/sys/dev/sfxge/common/efx_lic.c b/sys/dev/sfxge/common/efx_lic.c index 95e32b9..480f195 100644 --- a/sys/dev/sfxge/common/efx_lic.c +++ b/sys/dev/sfxge/common/efx_lic.c @@ -1330,6 +1330,7 @@ efx_lic_init( __in efx_nic_t *enp) { const efx_lic_ops_t *elop; + efx_key_stats_t eks; efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); @@ -1365,6 +1366,13 @@ efx_lic_init( enp->en_elop = elop; enp->en_mod_flags |= EFX_MOD_LIC; + /* Probe for support */ + if (efx_lic_get_key_stats(enp, &eks) == 0) { + enp->en_licensing_supported = B_TRUE; + } else { + enp->en_licensing_supported = B_FALSE; + } + return (0); fail1: @@ -1373,6 +1381,17 @@ fail1: return (rc); } +extern __checkReturn boolean_t +efx_lic_check_support( + __in efx_nic_t *enp) +{ + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_LIC); + + return enp->en_licensing_supported; +} + void efx_lic_fini( __in efx_nic_t *enp) diff --git a/sys/dev/sfxge/common/efx_mac.c b/sys/dev/sfxge/common/efx_mac.c index 84f2fbc..2b1f0bd 100644 --- a/sys/dev/sfxge/common/efx_mac.c +++ b/sys/dev/sfxge/common/efx_mac.c @@ -48,6 +48,7 @@ static const efx_mac_ops_t __efx_siena_mac_ops = { siena_mac_up, /* emo_up */ siena_mac_reconfigure, /* emo_addr_set */ siena_mac_reconfigure, /* emo_pdu_set */ + siena_mac_pdu_get, /* emo_pdu_get */ siena_mac_reconfigure, /* emo_reconfigure */ siena_mac_multicast_list_set, /* emo_multicast_list_set */ NULL, /* emo_filter_set_default_rxq */ @@ -69,6 +70,7 @@ static const efx_mac_ops_t __efx_ef10_mac_ops = { ef10_mac_up, /* emo_up */ ef10_mac_addr_set, /* emo_addr_set */ ef10_mac_pdu_set, /* emo_pdu_set */ + ef10_mac_pdu_get, /* emo_pdu_get */ ef10_mac_reconfigure, /* emo_reconfigure */ ef10_mac_multicast_list_set, /* emo_multicast_list_set */ ef10_mac_filter_default_rxq_set, /* emo_filter_default_rxq_set */ @@ -85,7 +87,6 @@ static const efx_mac_ops_t __efx_ef10_mac_ops = { }; #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - __checkReturn efx_rc_t efx_mac_pdu_set( __in efx_nic_t *enp, @@ -130,6 +131,26 @@ fail1: return (rc); } + __checkReturn efx_rc_t +efx_mac_pdu_get( + __in efx_nic_t *enp, + __out size_t *pdu) +{ + efx_port_t *epp = &(enp->en_port); + const efx_mac_ops_t *emop = epp->ep_emop; + efx_rc_t rc; + + if ((rc = emop->emo_pdu_get(enp, pdu)) != 0) + goto fail1; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + __checkReturn efx_rc_t efx_mac_addr_set( __in efx_nic_t *enp, diff --git a/sys/dev/sfxge/common/efx_mcdi.c b/sys/dev/sfxge/common/efx_mcdi.c index 6a38157..1a12b656 100644 --- a/sys/dev/sfxge/common/efx_mcdi.c +++ b/sys/dev/sfxge/common/efx_mcdi.c @@ -519,6 +519,11 @@ efx_mcdi_request_poll( if ((rc = efx_mcdi_poll_reboot(enp)) != 0) { emip->emi_pending_req = NULL; EFSYS_UNLOCK(enp->en_eslp, state); + + /* Reboot/Assertion */ + if (rc == EIO || rc == EINTR) + efx_mcdi_raise_exception(enp, emrp, rc); + goto fail1; } } @@ -535,6 +540,9 @@ efx_mcdi_request_poll( /* Request complete */ emip->emi_pending_req = NULL; + /* Ensure stale MCDI requests fail after an MC reboot. */ + emip->emi_new_epoch = B_FALSE; + EFSYS_UNLOCK(enp->en_eslp, state); if ((rc = emrp->emr_rc) != 0) @@ -550,10 +558,6 @@ fail1: if (!emrp->emr_quiet) EFSYS_PROBE1(fail1, efx_rc_t, rc); - /* Reboot/Assertion */ - if (rc == EIO || rc == EINTR) - efx_mcdi_raise_exception(enp, emrp, rc); - return (B_TRUE); } diff --git a/sys/dev/sfxge/common/efx_nic.c b/sys/dev/sfxge/common/efx_nic.c index 4f2aedd..b50e16d 100644 --- a/sys/dev/sfxge/common/efx_nic.c +++ b/sys/dev/sfxge/common/efx_nic.c @@ -580,7 +580,7 @@ efx_nic_reset( EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); /* - * All modules except the MCDI, PROBE, NVRAM, VPD, MON, LIC + * All modules except the MCDI, PROBE, NVRAM, VPD, MON * (which we do not reset here) must have been shut down or never * initialized. * @@ -590,7 +590,7 @@ efx_nic_reset( */ mod_flags = enp->en_mod_flags; mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM | - EFX_MOD_VPD | EFX_MOD_MON | EFX_MOD_LIC); + EFX_MOD_VPD | EFX_MOD_MON); EFSYS_ASSERT3U(mod_flags, ==, 0); if (mod_flags != 0) { rc = EINVAL; diff --git a/sys/dev/sfxge/common/hunt_nic.c b/sys/dev/sfxge/common/hunt_nic.c index 335f8d5..0497f07 100644 --- a/sys/dev/sfxge/common/hunt_nic.c +++ b/sys/dev/sfxge/common/hunt_nic.c @@ -114,7 +114,7 @@ hunt_board_cfg( uint32_t vf; uint32_t mask; uint32_t flags; - uint32_t sysclk; + uint32_t sysclk, dpcpu_clk; uint32_t base, nvec; uint32_t bandwidth; efx_rc_t rc; @@ -274,13 +274,13 @@ hunt_board_cfg( goto fail10; } - /* Get sysclk frequency (in MHz). */ - if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0) + /* Get clock frequencies (in MHz). */ + if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) goto fail11; /* - * The timer quantum is 1536 sysclk cycles, documented for the - * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. + * The Huntington timer quantum is 1536 sysclk cycles, documented for + * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. */ encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */ if (encp->enc_bug35388_workaround) { diff --git a/sys/dev/sfxge/common/medford_nic.c b/sys/dev/sfxge/common/medford_nic.c index 260124f..2211023 100644 --- a/sys/dev/sfxge/common/medford_nic.c +++ b/sys/dev/sfxge/common/medford_nic.c @@ -141,7 +141,7 @@ medford_board_cfg( uint32_t pf; uint32_t vf; uint32_t mask; - uint32_t sysclk; + uint32_t sysclk, dpcpu_clk; uint32_t base, nvec; uint32_t end_padding; uint32_t bandwidth; @@ -231,15 +231,15 @@ medford_board_cfg( /* Chained multicast is always enabled on Medford */ encp->enc_bug26807_workaround = B_TRUE; - /* Get sysclk frequency (in MHz). */ - if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0) + /* Get clock frequencies (in MHz). */ + if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) goto fail8; /* - * The timer quantum is 1536 sysclk cycles, documented for the - * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. + * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for + * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. */ - encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */ + encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */ encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; diff --git a/sys/dev/sfxge/common/siena_impl.h b/sys/dev/sfxge/common/siena_impl.h index 742266d..cde802d 100644 --- a/sys/dev/sfxge/common/siena_impl.h +++ b/sys/dev/sfxge/common/siena_impl.h @@ -388,6 +388,11 @@ extern __checkReturn efx_rc_t siena_mac_reconfigure( __in efx_nic_t *enp); +extern __checkReturn efx_rc_t +siena_mac_pdu_get( + __in efx_nic_t *enp, + __out size_t *pdu); + #if EFSYS_OPT_LOOPBACK extern __checkReturn efx_rc_t diff --git a/sys/dev/sfxge/common/siena_mac.c b/sys/dev/sfxge/common/siena_mac.c index ad61ad7..f7b6ede 100644 --- a/sys/dev/sfxge/common/siena_mac.c +++ b/sys/dev/sfxge/common/siena_mac.c @@ -432,4 +432,12 @@ siena_mac_stats_update( #endif /* EFSYS_OPT_MAC_STATS */ + __checkReturn efx_rc_t +siena_mac_pdu_get( + __in efx_nic_t *enp, + __out size_t *pdu) +{ + return (ENOTSUP); +} + #endif /* EFSYS_OPT_SIENA */ diff --git a/sys/dev/sfxge/sfxge_rx.c b/sys/dev/sfxge/sfxge_rx.c index 4424c9b..bdee824 100644 --- a/sys/dev/sfxge/sfxge_rx.c +++ b/sys/dev/sfxge/sfxge_rx.c @@ -833,7 +833,7 @@ sfxge_rx_qcomplete(struct sfxge_rxq *rxq, boolean_t eop) if (rx_desc->flags & EFX_PKT_PREFIX_LEN) { uint16_t tmp_size; int rc; - rc = efx_psuedo_hdr_pkt_length_get(sc->enp, + rc = efx_psuedo_hdr_pkt_length_get(sc->enp, mtod(m, uint8_t *), &tmp_size); KASSERT(rc == 0, ("cannot get packet length: %d", rc)); @@ -1100,7 +1100,7 @@ sfxge_rx_start(struct sfxge_softc *sc) EFSYS_ASSERT(ISP2(align)); sc->rx_buffer_size = P2ROUNDUP(sc->rx_buffer_size, align); - /* + /* * Standard mbuf zones only guarantee pointer-size alignment; * we need extra space to align to the cache line */ diff --git a/sys/dev/siba/siba_core.c b/sys/dev/siba/siba_core.c index 6a1749f..6674878 100644 --- a/sys/dev/siba/siba_core.c +++ b/sys/dev/siba/siba_core.c @@ -34,6 +34,8 @@ __FBSDID("$FreeBSD$"); * the Sonics Silicon Backplane driver. */ +#include "opt_siba.h" + #include <sys/param.h> #include <sys/systm.h> #include <sys/malloc.h> @@ -60,7 +62,6 @@ __FBSDID("$FreeBSD$"); #include <dev/siba/sibareg.h> #include <dev/siba/sibavar.h> -#ifdef SIBA_DEBUG enum { SIBA_DEBUG_SCAN = 0x00000001, /* scan */ SIBA_DEBUG_PMU = 0x00000002, /* PMU */ @@ -68,15 +69,19 @@ enum { SIBA_DEBUG_SWITCHCORE = 0x00000008, /* switching core */ SIBA_DEBUG_SPROM = 0x00000010, /* SPROM */ SIBA_DEBUG_CORE = 0x00000020, /* handling cores */ + SIBA_DEBUG_DMA = 0x00000040, /* DMA bits */ SIBA_DEBUG_ANY = 0xffffffff }; -#define DPRINTF(siba, m, fmt, ...) do { \ - if (siba->siba_debug & (m)) \ - printf(fmt, __VA_ARGS__); \ + +#ifdef SIBA_DEBUG +#define DPRINTF(siba, m, ...) do { \ + if (siba->siba_debug & (m)) \ + device_printf(siba->siba_dev, __VA_ARGS__); \ } while (0) #else -#define DPRINTF(siba, m, fmt, ...) do { (void) siba; } while (0) +#define DPRINTF(siba, m, ...) do { (void) siba; } while (0) #endif + #define N(a) (sizeof(a) / sizeof(a[0])) static void siba_pci_gpio(struct siba_softc *, uint32_t, int); @@ -330,9 +335,10 @@ siba_scan(struct siba_softc *siba) sd->sd_coreidx = i; DPRINTF(siba, SIBA_DEBUG_SCAN, - "core %d (%s) found (cc %#xrev %#x vendor %#x)\n", + "core %d (%s) found (cc %#x rev %#x vendor %#x)\n", i, siba_core_name(sd->sd_id.sd_device), - sd->sd_id.sd_device, sd->sd_id.sd_rev, sd->sd_id.vendor); + sd->sd_id.sd_device, sd->sd_id.sd_rev, + sd->sd_id.sd_vendor); switch (sd->sd_id.sd_device) { case SIBA_DEVID_CHIPCOMMON: @@ -424,6 +430,7 @@ siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx) return (0); DELAY(10); } + DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "%s: idx %d, failed\n", __func__, idx); return (ENODEV); #undef RETRY_MAX } @@ -767,6 +774,13 @@ siba_cc_clock(struct siba_cc *scc, enum siba_clock clock) if (sd == NULL) return; siba = sd->sd_bus; + + /* + * PMU controls clockmode; separate function is needed + */ + if (scc->scc_caps & SIBA_CC_CAPS_PMU) + return; + /* * chipcommon < r6 (no dynamic clock control) * chipcommon >= r10 (unknown) @@ -923,6 +937,7 @@ siba_cc_pmu_init(struct siba_cc *scc) DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n", scc->scc_pmu.rev, pmucap); +#if 0 if (scc->scc_pmu.rev >= 1) { if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325) SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, @@ -931,6 +946,12 @@ siba_cc_pmu_init(struct siba_cc *scc) SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_NOILP); } +#endif + if (scc->scc_pmu.rev == 1) { + SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, ~SIBA_CC_PMUCTL_NOILP); + } else { + SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_NOILP); + } /* initialize PLL & PMU resources */ switch (siba->siba_chipid) { @@ -938,6 +959,17 @@ siba_cc_pmu_init(struct siba_cc *scc) siba_cc_pmu1_pll0_init(scc, 0 /* use default */); /* use the default: min = 0xcbb max = 0x7ffff */ break; + case 0x4322: + if (scc->scc_pmu.rev == 2) { + DPRINTF(siba, SIBA_DEBUG_PMU, "%s: chipid 0x4322; PLLing\n", + __func__); + SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, 0x0000000a); + SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, 0x380005c0); + } + /* use the default: min = 0xcbb max = 0x7ffff */ + break; + case 43222: + break; case 0x4325: siba_cc_pmu1_pll0_init(scc, 0 /* use default */); @@ -1052,8 +1084,22 @@ siba_cc_powerup_delay(struct siba_cc *scc) struct siba_softc *siba = scc->scc_dev->sd_bus; int min; - if (siba->siba_type != SIBA_TYPE_PCI || - !(scc->scc_caps & SIBA_CC_CAPS_PWCTL)) + if (siba->siba_type != SIBA_TYPE_PCI) + return; + + if (scc->scc_caps & SIBA_CC_CAPS_PMU) { + if ((siba->siba_chipid == 0x4312) || + (siba->siba_chipid == 0x4322) || + (siba->siba_chipid == 0x4328)) { + scc->scc_powerup_delay = 7000; + } else { + /* 0x4325 is marked as TODO */ + scc->scc_powerup_delay = 15000; + } + return; + } + + if (!(scc->scc_caps & SIBA_CC_CAPS_PWCTL)) return; min = siba_cc_clockfreq(scc, 0); @@ -1781,26 +1827,26 @@ siba_sprom_r8(struct siba_sprom *out, const uint16_t *in) /* FEM */ SIBA_SHIFTOUT(fem.ghz2.tssipos, SIBA_SPROM8_FEM2G, - SSB_SROM8_FEM_TSSIPOS); + SIBA_SROM8_FEM_TSSIPOS); SIBA_SHIFTOUT(fem.ghz2.extpa_gain, SIBA_SPROM8_FEM2G, - SSB_SROM8_FEM_EXTPA_GAIN); + SIBA_SROM8_FEM_EXTPA_GAIN); SIBA_SHIFTOUT(fem.ghz2.pdet_range, SIBA_SPROM8_FEM2G, - SSB_SROM8_FEM_PDET_RANGE); + SIBA_SROM8_FEM_PDET_RANGE); SIBA_SHIFTOUT(fem.ghz2.tr_iso, SIBA_SPROM8_FEM2G, - SSB_SROM8_FEM_TR_ISO); + SIBA_SROM8_FEM_TR_ISO); SIBA_SHIFTOUT(fem.ghz2.antswlut, SIBA_SPROM8_FEM2G, - SSB_SROM8_FEM_ANTSWLUT); + SIBA_SROM8_FEM_ANTSWLUT); SIBA_SHIFTOUT(fem.ghz5.tssipos, SIBA_SPROM8_FEM5G, - SSB_SROM8_FEM_TSSIPOS); + SIBA_SROM8_FEM_TSSIPOS); SIBA_SHIFTOUT(fem.ghz5.extpa_gain, SIBA_SPROM8_FEM5G, - SSB_SROM8_FEM_EXTPA_GAIN); + SIBA_SROM8_FEM_EXTPA_GAIN); SIBA_SHIFTOUT(fem.ghz5.pdet_range, SIBA_SPROM8_FEM5G, - SSB_SROM8_FEM_PDET_RANGE); + SIBA_SROM8_FEM_PDET_RANGE); SIBA_SHIFTOUT(fem.ghz5.tr_iso, SIBA_SPROM8_FEM5G, - SSB_SROM8_FEM_TR_ISO); + SIBA_SROM8_FEM_TR_ISO); SIBA_SHIFTOUT(fem.ghz5.antswlut, SIBA_SPROM8_FEM5G, - SSB_SROM8_FEM_ANTSWLUT); + SIBA_SROM8_FEM_ANTSWLUT); /* Extract cores power info info */ for (i = 0; i < nitems(pwr_info_offset); i++) { @@ -2178,6 +2224,8 @@ siba_dma_translation(device_t dev) KASSERT(siba->siba_type == SIBA_TYPE_PCI, ("unsupported bustype %d\n", siba->siba_type)); #endif + + /* Default */ return (SIBA_PCI_DMA); } diff --git a/sys/dev/siba/sibareg.h b/sys/dev/siba/sibareg.h index 5e57321..1b10a91 100644 --- a/sys/dev/siba/sibareg.h +++ b/sys/dev/siba/sibareg.h @@ -399,10 +399,10 @@ #define SIBA_SPROM4_GPIOB_P3 0xff00 /* The following four blocks share the same structure */ -#define SIBA_SPROM4_PWR_INFO_CORE0 0x0080 -#define SIBA_SPROM4_PWR_INFO_CORE1 0x00AE -#define SIBA_SPROM4_PWR_INFO_CORE2 0x00DC -#define SIBA_SPROM4_PWR_INFO_CORE3 0x010A +#define SIBA_SPROM4_PWR_INFO_CORE0 0x1080 +#define SIBA_SPROM4_PWR_INFO_CORE1 0x10AE +#define SIBA_SPROM4_PWR_INFO_CORE2 0x10DC +#define SIBA_SPROM4_PWR_INFO_CORE3 0x110A #define SIBA_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */ #define SIBA_SPROM4_2G_MAXP 0x00FF @@ -486,13 +486,13 @@ #define SIBA_SPROM8_RXPO5G 0xff00 /* The FEM blocks share the same structure */ -#define SIBA_SPROM8_FEM2G 0x00AE -#define SIBA_SPROM8_FEM5G 0x00B0 -#define SSB_SROM8_FEM_TSSIPOS 0x0001 -#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006 -#define SSB_SROM8_FEM_PDET_RANGE 0x00F8 -#define SSB_SROM8_FEM_TR_ISO 0x0700 -#define SSB_SROM8_FEM_ANTSWLUT 0xF800 +#define SIBA_SPROM8_FEM2G 0x10ae +#define SIBA_SPROM8_FEM5G 0x10b0 +#define SIBA_SROM8_FEM_TSSIPOS 0x0001 +#define SIBA_SROM8_FEM_EXTPA_GAIN 0x0006 +#define SIBA_SROM8_FEM_PDET_RANGE 0x00F8 +#define SIBA_SROM8_FEM_TR_ISO 0x0700 +#define SIBA_SROM8_FEM_ANTSWLUT 0xF800 #define SIBA_SPROM8_MAXP_BG 0x10c0 #define SIBA_SPROM8_MAXP_BG_MASK 0x00ff @@ -526,10 +526,10 @@ #define SIBA_SPROM8_BWDUPPO 0x0198 /* There are 4 blocks with power info sharing the same layout */ -#define SIBA_SROM8_PWR_INFO_CORE0 0x00C0 -#define SIBA_SROM8_PWR_INFO_CORE1 0x00E0 -#define SIBA_SROM8_PWR_INFO_CORE2 0x0100 -#define SIBA_SROM8_PWR_INFO_CORE3 0x0120 +#define SIBA_SROM8_PWR_INFO_CORE0 0x10C0 +#define SIBA_SROM8_PWR_INFO_CORE1 0x10E0 +#define SIBA_SROM8_PWR_INFO_CORE2 0x1100 +#define SIBA_SROM8_PWR_INFO_CORE3 0x1120 #define SIBA_SROM8_2G_MAXP_ITSSI 0x00 #define SIBA_SPROM8_2G_MAXP 0x00FF diff --git a/sys/dev/siba/sibavar.h b/sys/dev/siba/sibavar.h index d5823b4..c4b3417 100644 --- a/sys/dev/siba/sibavar.h +++ b/sys/dev/siba/sibavar.h @@ -604,6 +604,7 @@ struct siba_softc { bus_addr_t siba_maddr; bus_size_t siba_msize; uint8_t siba_ncores; + uint32_t siba_debug; /* * the following variables are only used for siba_bwn bridge. diff --git a/sys/dev/tsec/if_tsec_fdt.c b/sys/dev/tsec/if_tsec_fdt.c index ab4bffc..ce18cca 100644 --- a/sys/dev/tsec/if_tsec_fdt.c +++ b/sys/dev/tsec/if_tsec_fdt.c @@ -115,7 +115,8 @@ tsec_fdt_probe(device_t dev) strcmp(ofw_bus_get_type(dev), "network") != 0) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "gianfar")) + if (!ofw_bus_is_compatible(dev, "gianfar") && + !ofw_bus_is_compatible(dev, "fsl,etsec2")) return (ENXIO); sc = device_get_softc(dev); diff --git a/sys/dev/urtwn/if_urtwn.c b/sys/dev/urtwn/if_urtwn.c index dce9d19..efbdaba 100644 --- a/sys/dev/urtwn/if_urtwn.c +++ b/sys/dev/urtwn/if_urtwn.c @@ -356,6 +356,8 @@ static void urtwn_update_slot(struct ieee80211com *); static void urtwn_update_slot_cb(struct urtwn_softc *, union sec_param *); static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); +static uint8_t urtwn_get_multi_pos(const uint8_t[]); +static void urtwn_set_multi(struct urtwn_softc *); static void urtwn_set_promisc(struct urtwn_softc *); static void urtwn_update_promisc(struct ieee80211com *); static void urtwn_update_mcast(struct ieee80211com *); @@ -4359,9 +4361,8 @@ urtwn_rxfilter_init(struct urtwn_softc *sc) URTWN_ASSERT_LOCKED(sc); - /* Accept all multicast frames. */ - urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); - urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); + /* Setup multicast filter. */ + urtwn_set_multi(sc); /* Filter for management frames. */ filter = 0x7f3f; @@ -4822,6 +4823,67 @@ urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) } } +static uint8_t +urtwn_get_multi_pos(const uint8_t maddr[]) +{ + uint64_t mask = 0x00004d101df481b4; + uint8_t pos = 0x27; /* initial value */ + int i, j; + + for (i = 0; i < IEEE80211_ADDR_LEN; i++) + for (j = (i == 0) ? 1 : 0; j < 8; j++) + if ((maddr[i] >> j) & 1) + pos ^= (mask >> (i * 8 + j - 1)); + + pos &= 0x3f; + + return (pos); +} + +static void +urtwn_set_multi(struct urtwn_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + uint32_t mfilt[2]; + + URTWN_ASSERT_LOCKED(sc); + + /* general structure was copied from ath(4). */ + if (ic->ic_allmulti == 0) { + struct ieee80211vap *vap; + struct ifnet *ifp; + struct ifmultiaddr *ifma; + + /* + * Merge multicast addresses to form the hardware filter. + */ + mfilt[0] = mfilt[1] = 0; + TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { + ifp = vap->iv_ifp; + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + caddr_t dl; + uint8_t pos; + + dl = LLADDR((struct sockaddr_dl *) + ifma->ifma_addr); + pos = urtwn_get_multi_pos(dl); + + mfilt[pos / 32] |= (1 << (pos % 32)); + } + if_maddr_runlock(ifp); + } + } else + mfilt[0] = mfilt[1] = ~0; + + + urtwn_write_4(sc, R92C_MAR + 0, mfilt[0]); + urtwn_write_4(sc, R92C_MAR + 4, mfilt[1]); + + URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n", + __func__, mfilt[0], mfilt[1]); +} + static void urtwn_set_promisc(struct urtwn_softc *sc) { @@ -4877,7 +4939,12 @@ urtwn_update_promisc(struct ieee80211com *ic) static void urtwn_update_mcast(struct ieee80211com *ic) { - /* XXX do nothing? */ + struct urtwn_softc *sc = ic->ic_softc; + + URTWN_LOCK(sc); + if (sc->sc_flags & URTWN_RUNNING) + urtwn_set_multi(sc); + URTWN_UNLOCK(sc); } static struct ieee80211_node * diff --git a/sys/dev/usb/controller/generic_ohci.c b/sys/dev/usb/controller/generic_ohci.c new file mode 100644 index 0000000..5d00c52 --- /dev/null +++ b/sys/dev/usb/controller/generic_ohci.c @@ -0,0 +1,308 @@ +/*- + * Copyright (c) 2006 M. Warner Losh. All rights reserved. + * Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Generic OHCI driver based on AT91 OHCI + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/condvar.h> +#include <sys/kernel.h> +#include <sys/module.h> + +#include <machine/bus.h> +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dev/usb/usb.h> +#include <dev/usb/usbdi.h> + +#include <dev/usb/usb_core.h> +#include <dev/usb/usb_busdma.h> +#include <dev/usb/usb_process.h> +#include <dev/usb/usb_util.h> + +#include <dev/usb/usb_controller.h> +#include <dev/usb/usb_bus.h> +#include <dev/usb/controller/ohci.h> +#include <dev/usb/controller/ohcireg.h> + +#ifdef EXT_RESOURCES +#include <dev/extres/clk/clk.h> +#include <dev/extres/hwreset/hwreset.h> +#endif + +#include "generic_usb_if.h" + +#ifdef EXT_RESOURCES +struct clk_list { + TAILQ_ENTRY(clk_list) next; + clk_t clk; +}; +#endif + +struct generic_ohci_softc { + ohci_softc_t ohci_sc; + +#ifdef EXT_RESOURCES + hwreset_t rst; + TAILQ_HEAD(, clk_list) clk_list; +#endif +}; + +static int generic_ohci_detach(device_t); + +static int +generic_ohci_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "generic-ohci")) + return (ENXIO); + + device_set_desc(dev, "Generic OHCI Controller"); + + return (BUS_PROBE_DEFAULT); +} + +static int +generic_ohci_attach(device_t dev) +{ + struct generic_ohci_softc *sc = device_get_softc(dev); + int err, rid; +#ifdef EXT_RESOURCES + int off; + struct clk_list *clkp; + clk_t clk; +#endif + + sc->ohci_sc.sc_bus.parent = dev; + sc->ohci_sc.sc_bus.devices = sc->ohci_sc.sc_devices; + sc->ohci_sc.sc_bus.devices_max = OHCI_MAX_DEVICES; + sc->ohci_sc.sc_bus.dma_bits = 32; + + /* get all DMA memory */ + if (usb_bus_mem_alloc_all(&sc->ohci_sc.sc_bus, + USB_GET_DMA_TAG(dev), &ohci_iterate_hw_softc)) { + return (ENOMEM); + } + + rid = 0; + sc->ohci_sc.sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &rid, RF_ACTIVE); + if (sc->ohci_sc.sc_io_res == 0) { + err = ENOMEM; + goto error; + } + + sc->ohci_sc.sc_io_tag = rman_get_bustag(sc->ohci_sc.sc_io_res); + sc->ohci_sc.sc_io_hdl = rman_get_bushandle(sc->ohci_sc.sc_io_res); + sc->ohci_sc.sc_io_size = rman_get_size(sc->ohci_sc.sc_io_res); + + rid = 0; + sc->ohci_sc.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (sc->ohci_sc.sc_irq_res == 0) { + err = ENXIO; + goto error; + } + sc->ohci_sc.sc_bus.bdev = device_add_child(dev, "usbus", -1); + if (sc->ohci_sc.sc_bus.bdev == 0) { + err = ENXIO; + goto error; + } + device_set_ivars(sc->ohci_sc.sc_bus.bdev, &sc->ohci_sc.sc_bus); + + strlcpy(sc->ohci_sc.sc_vendor, "Generic", + sizeof(sc->ohci_sc.sc_vendor)); + + err = bus_setup_intr(dev, sc->ohci_sc.sc_irq_res, + INTR_TYPE_BIO | INTR_MPSAFE, NULL, + (driver_intr_t *)ohci_interrupt, sc, &sc->ohci_sc.sc_intr_hdl); + if (err) { + sc->ohci_sc.sc_intr_hdl = NULL; + goto error; + } + +#ifdef EXT_RESOURCES + TAILQ_INIT(&sc->clk_list); + /* Enable clock */ + for (off = 0; clk_get_by_ofw_index(dev, off, &clk) == 0; off++) { + err = clk_enable(clk); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(clk)); + goto error; + } + clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO); + clkp->clk = clk; + TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next); + } + + /* De-assert reset */ + if (hwreset_get_by_ofw_idx(dev, 0, &sc->rst) == 0) { + err = hwreset_deassert(sc->rst); + if (err != 0) { + device_printf(dev, "Could not de-assert reset %d\n", + off); + goto error; + } + } +#endif + + if (GENERIC_USB_INIT(dev) != 0) { + err = ENXIO; + goto error; + } + + err = ohci_init(&sc->ohci_sc); + if (err == 0) + err = device_probe_and_attach(sc->ohci_sc.sc_bus.bdev); + if (err) + goto error; + + return (0); +error: + generic_ohci_detach(dev); + return (err); +} + +static int +generic_ohci_detach(device_t dev) +{ + struct generic_ohci_softc *sc = device_get_softc(dev); + device_t bdev; + int err; +#ifdef EXT_RESOURCES + struct clk_list *clk, *clk_tmp; +#endif + + if (sc->ohci_sc.sc_bus.bdev) { + bdev = sc->ohci_sc.sc_bus.bdev; + device_detach(bdev); + device_delete_child(dev, bdev); + } + + /* during module unload there are lots of children leftover */ + device_delete_children(dev); + + /* + * Put the controller into reset, then disable clocks and do + * the MI tear down. We have to disable the clocks/hardware + * after we do the rest of the teardown. We also disable the + * clocks in the opposite order we acquire them, but that + * doesn't seem to be absolutely necessary. We free up the + * clocks after we disable them, so the system could, in + * theory, reuse them. + */ + bus_space_write_4(sc->ohci_sc.sc_io_tag, sc->ohci_sc.sc_io_hdl, + OHCI_CONTROL, 0); + + if (sc->ohci_sc.sc_irq_res && sc->ohci_sc.sc_intr_hdl) { + /* + * only call ohci_detach() after ohci_init() + */ + ohci_detach(&sc->ohci_sc); + + err = bus_teardown_intr(dev, sc->ohci_sc.sc_irq_res, + sc->ohci_sc.sc_intr_hdl); + sc->ohci_sc.sc_intr_hdl = NULL; + } + if (sc->ohci_sc.sc_irq_res) { + bus_release_resource(dev, SYS_RES_IRQ, 0, + sc->ohci_sc.sc_irq_res); + sc->ohci_sc.sc_irq_res = NULL; + } + if (sc->ohci_sc.sc_io_res) { + bus_release_resource(dev, SYS_RES_MEMORY, 0, + sc->ohci_sc.sc_io_res); + sc->ohci_sc.sc_io_res = NULL; + } + usb_bus_mem_free_all(&sc->ohci_sc.sc_bus, &ohci_iterate_hw_softc); + +#ifdef EXT_RESOURCES + /* Disable clock */ + TAILQ_FOREACH_SAFE(clk, &sc->clk_list, next, clk_tmp) { + err = clk_disable(clk->clk); + if (err != 0) + device_printf(dev, "Could not disable clock %s\n", + clk_get_name(clk->clk)); + err = clk_release(clk->clk); + if (err != 0) + device_printf(dev, "Could not release clock %s\n", + clk_get_name(clk->clk)); + TAILQ_REMOVE(&sc->clk_list, clk, next); + free(clk, M_DEVBUF); + } + + /* De-assert reset */ + if (sc->rst) { + err = hwreset_assert(sc->rst); + if (err != 0) + device_printf(dev, "Could not assert reset\n"); + hwreset_release(sc->rst); + } +#endif + + if (GENERIC_USB_DEINIT(dev) != 0) + return (ENXIO); + + return (0); +} + +static device_method_t generic_ohci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, generic_ohci_probe), + DEVMETHOD(device_attach, generic_ohci_attach), + DEVMETHOD(device_detach, generic_ohci_detach), + + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + + DEVMETHOD_END +}; + +driver_t generic_ohci_driver = { + .name = "ohci", + .methods = generic_ohci_methods, + .size = sizeof(struct generic_ohci_softc), +}; + +static devclass_t generic_ohci_devclass; + +DRIVER_MODULE(ohci, simplebus, generic_ohci_driver, + generic_ohci_devclass, 0, 0); +MODULE_DEPEND(ohci, usb, 1, 1, 1); diff --git a/sys/dev/usb/controller/generic_usb_if.m b/sys/dev/usb/controller/generic_usb_if.m new file mode 100644 index 0000000..78b73cc --- /dev/null +++ b/sys/dev/usb/controller/generic_usb_if.m @@ -0,0 +1,60 @@ +#- +# Copyright (c) 2016 Emmanuel Vadot <manu@freebsd.org> +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +# $FreeBSD$ +# + +INTERFACE generic_usb; + +CODE { + static int + generic_usb_default_init(device_t dev) + { + return (0); + } + + static int + generic_usb_default_deinit(device_t dev) + { + return (0); + } +}; + +HEADER { +}; + +# +# Initialize the SoC bits +# +METHOD int init { + device_t dev; +} DEFAULT generic_usb_default_init; + +# +# Deinitialize the SoC bits +# +METHOD int deinit { + device_t dev; +} DEFAULT generic_usb_default_deinit; diff --git a/sys/fs/autofs/autofs_vnops.c b/sys/fs/autofs/autofs_vnops.c index 0ab6ec1..781338b 100644 --- a/sys/fs/autofs/autofs_vnops.c +++ b/sys/fs/autofs/autofs_vnops.c @@ -686,7 +686,7 @@ autofs_node_vn(struct autofs_node *anp, struct mount *mp, int flags, error = insmntque(vp, mp); if (error != 0) { - AUTOFS_WARN("insmntque() failed with error %d", error); + AUTOFS_DEBUG("insmntque() failed with error %d", error); sx_xunlock(&anp->an_vnode_lock); return (error); } diff --git a/sys/fs/fuse/fuse_vnops.c b/sys/fs/fuse/fuse_vnops.c index 6672f42..71d7422 100644 --- a/sys/fs/fuse/fuse_vnops.c +++ b/sys/fs/fuse/fuse_vnops.c @@ -335,8 +335,9 @@ fuse_vnop_create(struct vop_create_args *ap) /* XXX: Will we ever want devices ? */ if ((vap->va_type != VREG)) { - MPASS(vap->va_type != VFIFO); - goto bringup; + printf("fuse_vnop_create: unsupported va_type %d\n", + vap->va_type); + return (EINVAL); } debug_printf("parent nid = %ju, mode = %x\n", (uintmax_t)parentnid, mode); @@ -364,7 +365,7 @@ fuse_vnop_create(struct vop_create_args *ap) debug_printf("create: got err=%d from daemon\n", err); goto out; } -bringup: + feo = fdip->answ; if ((err = fuse_internal_checkentry(feo, VREG))) { diff --git a/sys/fs/nfsclient/nfs_clvfsops.c b/sys/fs/nfsclient/nfs_clvfsops.c index 1441f03..db1ee9d 100644 --- a/sys/fs/nfsclient/nfs_clvfsops.c +++ b/sys/fs/nfsclient/nfs_clvfsops.c @@ -841,7 +841,7 @@ nfs_mount_parse_from(struct vfsoptlist *opts, char **hostnamep, * mount system call * It seems a bit dumb to copyinstr() the host and path here and then * bcopy() them in mountnfs(), but I wanted to detect errors before - * doing the sockargs() call because sockargs() allocates an mbuf and + * doing the getsockaddr() call because getsockaddr() allocates an mbuf and * an error after that means that I have to release the mbuf. */ /* ARGSUSED */ @@ -1228,7 +1228,7 @@ nfs_mount(struct mount *mp) goto out; bzero(&hst[hstlen], MNAMELEN - hstlen); args.hostname = hst; - /* sockargs() call must be after above copyin() calls */ + /* getsockaddr() call must be after above copyin() calls */ error = getsockaddr(&nam, (caddr_t)args.addr, args.addrlen); if (error != 0) @@ -1332,7 +1332,7 @@ out: * mount system call * It seems a bit dumb to copyinstr() the host and path here and then * bcopy() them in mountnfs(), but I wanted to detect errors before - * doing the sockargs() call because sockargs() allocates an mbuf and + * doing the getsockaddr() call because getsockaddr() allocates an mbuf and * an error after that means that I have to release the mbuf. */ /* ARGSUSED */ diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c new file mode 100644 index 0000000..1169585 --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c @@ -0,0 +1,6850 @@ + +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * The Broadcom Wireless LAN controller driver. + */ + +#include "opt_wlan.h" +#include "opt_bwn.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/endian.h> +#include <sys/errno.h> +#include <sys/firmware.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/socket.h> +#include <sys/sockio.h> + +#include <net/ethernet.h> +#include <net/if.h> +#include <net/if_var.h> +#include <net/if_arp.h> +#include <net/if_dl.h> +#include <net/if_llc.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <dev/pci/pcivar.h> +#include <dev/pci/pcireg.h> +#include <dev/siba/siba_ids.h> +#include <dev/siba/sibareg.h> +#include <dev/siba/sibavar.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> +#include <net80211/ieee80211_regdomain.h> +#include <net80211/ieee80211_phy.h> +#include <net80211/ieee80211_ratectl.h> + +#include <dev/bwn/if_bwnreg.h> +#include <dev/bwn/if_bwnvar.h> +#include <dev/bwn/if_bwn_misc.h> +#include <dev/bwn/if_bwn_util.h> +#include <dev/bwn/if_bwn_debug.h> +#include <dev/bwn/if_bwn_phy_common.h> +#include <dev/bwn/if_bwn_chipid.h> +#include <dev/bwn/if_bwn_cordic.h> + +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h> +#include <gnu/dev/bwn/phy_n/if_bwn_radio_2055.h> +#include <gnu/dev/bwn/phy_n/if_bwn_radio_2056.h> +#include <gnu/dev/bwn/phy_n/if_bwn_radio_2057.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h> + +struct bwn_nphy_txgains { + uint16_t tx_lpf[2]; + uint16_t txgm[2]; + uint16_t pga[2]; + uint16_t pad[2]; + uint16_t ipa[2]; +}; + +struct bwn_nphy_iqcal_params { + uint16_t tx_lpf; + uint16_t txgm; + uint16_t pga; + uint16_t pad; + uint16_t ipa; + uint16_t cal_gain; + uint16_t ncorr[5]; +}; + +struct bwn_nphy_iq_est { + int32_t iq0_prod; + uint32_t i0_pwr; + uint32_t q0_pwr; + int32_t iq1_prod; + uint32_t i1_pwr; + uint32_t q1_pwr; +}; + +enum bwn_nphy_rf_sequence { + BWN_RFSEQ_RX2TX, + BWN_RFSEQ_TX2RX, + BWN_RFSEQ_RESET2RX, + BWN_RFSEQ_UPDATE_GAINH, + BWN_RFSEQ_UPDATE_GAINL, + BWN_RFSEQ_UPDATE_GAINU, +}; + +enum n_rf_ctl_over_cmd { + N_RF_CTL_OVER_CMD_RXRF_PU = 0, + N_RF_CTL_OVER_CMD_RX_PU = 1, + N_RF_CTL_OVER_CMD_TX_PU = 2, + N_RF_CTL_OVER_CMD_RX_GAIN = 3, + N_RF_CTL_OVER_CMD_TX_GAIN = 4, +}; + +enum n_intc_override { + N_INTC_OVERRIDE_OFF = 0, + N_INTC_OVERRIDE_TRSW = 1, + N_INTC_OVERRIDE_PA = 2, + N_INTC_OVERRIDE_EXT_LNA_PU = 3, + N_INTC_OVERRIDE_EXT_LNA_GAIN = 4, +}; + +enum n_rssi_type { + N_RSSI_W1 = 0, + N_RSSI_W2, + N_RSSI_NB, + N_RSSI_IQ, + N_RSSI_TSSI_2G, + N_RSSI_TSSI_5G, + N_RSSI_TBD, +}; + +enum n_rail_type { + N_RAIL_I = 0, + N_RAIL_Q = 1, +}; + +static inline bool bwn_nphy_ipa(struct bwn_mac *mac) +{ + bwn_band_t band = bwn_current_band(mac); + return ((mac->mac_phy.phy_n->ipa2g_on && band == BWN_BAND_2G) || + (mac->mac_phy.phy_n->ipa5g_on && band == BWN_BAND_5G)); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */ +static uint8_t bwn_nphy_get_rx_core_state(struct bwn_mac *mac) +{ + return (BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA) & BWN_NPHY_RFSEQCA_RXEN) >> + BWN_NPHY_RFSEQCA_RXEN_SHIFT; +} + +/************************************************** + * RF (just without bwn_nphy_rf_ctl_intc_override) + **************************************************/ + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ +static void bwn_nphy_force_rf_sequence(struct bwn_mac *mac, + enum bwn_nphy_rf_sequence seq) +{ + static const uint16_t trigger[] = { + [BWN_RFSEQ_RX2TX] = BWN_NPHY_RFSEQTR_RX2TX, + [BWN_RFSEQ_TX2RX] = BWN_NPHY_RFSEQTR_TX2RX, + [BWN_RFSEQ_RESET2RX] = BWN_NPHY_RFSEQTR_RST2RX, + [BWN_RFSEQ_UPDATE_GAINH] = BWN_NPHY_RFSEQTR_UPGH, + [BWN_RFSEQ_UPDATE_GAINL] = BWN_NPHY_RFSEQTR_UPGL, + [BWN_RFSEQ_UPDATE_GAINU] = BWN_NPHY_RFSEQTR_UPGU, + }; + int i; + uint16_t seq_mode = BWN_PHY_READ(mac, BWN_NPHY_RFSEQMODE); + + if (seq >= nitems(trigger)) { + BWN_WARNPRINTF(mac->mac_sc, "%s: seq %d > max", __func__, seq); + } + + BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE, + BWN_NPHY_RFSEQMODE_CAOVER | BWN_NPHY_RFSEQMODE_TROVER); + BWN_PHY_SET(mac, BWN_NPHY_RFSEQTR, trigger[seq]); + for (i = 0; i < 200; i++) { + if (!(BWN_PHY_READ(mac, BWN_NPHY_RFSEQST) & trigger[seq])) + goto ok; + DELAY(1000); + } + BWN_ERRPRINTF(mac->mac_sc, "RF sequence status timeout\n"); +ok: + BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQMODE, seq_mode); +} + +static void bwn_nphy_rf_ctl_override_rev19(struct bwn_mac *mac, uint16_t field, + uint16_t value, uint8_t core, bool off, + uint8_t override_id) +{ + /* TODO */ +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */ +static void bwn_nphy_rf_ctl_override_rev7(struct bwn_mac *mac, uint16_t field, + uint16_t value, uint8_t core, bool off, + uint8_t override) +{ + struct bwn_phy *phy = &mac->mac_phy; + const struct bwn_nphy_rf_control_override_rev7 *e; + uint16_t en_addrs[3][2] = { + { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 } + }; + uint16_t en_addr; + uint16_t en_mask = field; + uint16_t val_addr; + uint8_t i; + + if (phy->rev >= 19 || phy->rev < 3) { + BWN_WARNPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", + __func__, + phy->rev); + return; + } + + /* Remember: we can get NULL! */ + e = bwn_nphy_get_rf_ctl_over_rev7(mac, field, override); + + for (i = 0; i < 2; i++) { + if (override >= nitems(en_addrs)) { + BWN_ERRPRINTF(mac->mac_sc, "Invalid override value %d\n", override); + return; + } + en_addr = en_addrs[override][i]; + + if (e) + val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1; + + if (off) { + BWN_PHY_MASK(mac, en_addr, ~en_mask); + if (e) /* Do it safer, better than wl */ + BWN_PHY_MASK(mac, val_addr, ~e->val_mask); + } else { + if (!core || (core & (1 << i))) { + BWN_PHY_SET(mac, en_addr, en_mask); + if (e) + BWN_PHY_SETMASK(mac, val_addr, ~e->val_mask, (value << e->val_shift)); + } + } + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */ +static void bwn_nphy_rf_ctl_override_one_to_many(struct bwn_mac *mac, + enum n_rf_ctl_over_cmd cmd, + uint16_t value, uint8_t core, bool off) +{ + struct bwn_phy *phy = &mac->mac_phy; + uint16_t tmp; + + if (phy->rev < 7) { + BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", + __func__, + phy->rev); + } + + switch (cmd) { + case N_RF_CTL_OVER_CMD_RXRF_PU: + bwn_nphy_rf_ctl_override_rev7(mac, 0x20, value, core, off, 1); + bwn_nphy_rf_ctl_override_rev7(mac, 0x10, value, core, off, 1); + bwn_nphy_rf_ctl_override_rev7(mac, 0x08, value, core, off, 1); + break; + case N_RF_CTL_OVER_CMD_RX_PU: + bwn_nphy_rf_ctl_override_rev7(mac, 0x4, value, core, off, 1); + bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 1); + bwn_nphy_rf_ctl_override_rev7(mac, 0x1, value, core, off, 1); + bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 2); + bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, 0, core, off, 1); + break; + case N_RF_CTL_OVER_CMD_TX_PU: + bwn_nphy_rf_ctl_override_rev7(mac, 0x4, value, core, off, 0); + bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 1); + bwn_nphy_rf_ctl_override_rev7(mac, 0x1, value, core, off, 2); + bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, 1, core, off, 1); + break; + case N_RF_CTL_OVER_CMD_RX_GAIN: + tmp = value & 0xFF; + bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, tmp, core, off, 0); + tmp = value >> 8; + bwn_nphy_rf_ctl_override_rev7(mac, 0x6000, tmp, core, off, 0); + break; + case N_RF_CTL_OVER_CMD_TX_GAIN: + tmp = value & 0x7FFF; + bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, tmp, core, off, 0); + tmp = value >> 14; + bwn_nphy_rf_ctl_override_rev7(mac, 0x4000, tmp, core, off, 0); + break; + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ +static void bwn_nphy_rf_ctl_override(struct bwn_mac *mac, uint16_t field, + uint16_t value, uint8_t core, bool off) +{ + int i; + uint8_t index = fls(field); + uint8_t addr, en_addr, val_addr; + + /* we expect only one bit set */ + if (field & (~(1 << (index - 1)))) { + BWN_ERRPRINTF(mac->mac_sc, "%s: field 0x%04x has >1 bit set\n", + __func__, + field); + } + + if (mac->mac_phy.rev >= 3) { + const struct bwn_nphy_rf_control_override_rev3 *rf_ctrl; + for (i = 0; i < 2; i++) { + if (index == 0 || index == 16) { + BWN_ERRPRINTF(mac->mac_sc, + "Unsupported RF Ctrl Override call\n"); + return; + } + + rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; + en_addr = BWN_PHY_N((i == 0) ? + rf_ctrl->en_addr0 : rf_ctrl->en_addr1); + val_addr = BWN_PHY_N((i == 0) ? + rf_ctrl->val_addr0 : rf_ctrl->val_addr1); + + if (off) { + BWN_PHY_MASK(mac, en_addr, ~(field)); + BWN_PHY_MASK(mac, val_addr, + ~(rf_ctrl->val_mask)); + } else { + if (core == 0 || ((1 << i) & core)) { + BWN_PHY_SET(mac, en_addr, field); + BWN_PHY_SETMASK(mac, val_addr, + ~(rf_ctrl->val_mask), + (value << rf_ctrl->val_shift)); + } + } + } + } else { + const struct bwn_nphy_rf_control_override_rev2 *rf_ctrl; + if (off) { + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~(field)); + value = 0; + } else { + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, field); + } + + for (i = 0; i < 2; i++) { + if (index <= 1 || index == 16) { + BWN_ERRPRINTF(mac->mac_sc, + "Unsupported RF Ctrl Override call\n"); + return; + } + + if (index == 2 || index == 10 || + (index >= 13 && index <= 15)) { + core = 1; + } + + rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; + addr = BWN_PHY_N((i == 0) ? + rf_ctrl->addr0 : rf_ctrl->addr1); + + if ((1 << i) & core) + BWN_PHY_SETMASK(mac, addr, ~(rf_ctrl->bmask), + (value << rf_ctrl->shift)); + + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, 0x1); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_CMD_START); + DELAY(1); + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, 0xFFFE); + } + } +} + +static void bwn_nphy_rf_ctl_intc_override_rev7(struct bwn_mac *mac, + enum n_intc_override intc_override, + uint16_t value, uint8_t core_sel) +{ + uint16_t reg, tmp, tmp2, val; + int core; + + /* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */ + + for (core = 0; core < 2; core++) { + if ((core_sel == 1 && core != 0) || + (core_sel == 2 && core != 1)) + continue; + + reg = (core == 0) ? BWN_NPHY_RFCTL_INTC1 : BWN_NPHY_RFCTL_INTC2; + + switch (intc_override) { + case N_INTC_OVERRIDE_OFF: + BWN_PHY_WRITE(mac, reg, 0); + BWN_PHY_MASK(mac, 0x2ff, ~0x2000); + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); + break; + case N_INTC_OVERRIDE_TRSW: + BWN_PHY_SETMASK(mac, reg, ~0xC0, value << 6); + BWN_PHY_SET(mac, reg, 0x400); + + BWN_PHY_MASK(mac, 0x2ff, ~0xC000 & 0xFFFF); + BWN_PHY_SET(mac, 0x2ff, 0x2000); + BWN_PHY_SET(mac, 0x2ff, 0x0001); + break; + case N_INTC_OVERRIDE_PA: + tmp = 0x0030; + if (bwn_current_band(mac) == BWN_BAND_5G) + val = value << 5; + else + val = value << 4; + BWN_PHY_SETMASK(mac, reg, ~tmp, val); + BWN_PHY_SET(mac, reg, 0x1000); + break; + case N_INTC_OVERRIDE_EXT_LNA_PU: + if (bwn_current_band(mac) == BWN_BAND_5G) { + tmp = 0x0001; + tmp2 = 0x0004; + val = value; + } else { + tmp = 0x0004; + tmp2 = 0x0001; + val = value << 2; + } + BWN_PHY_SETMASK(mac, reg, ~tmp, val); + BWN_PHY_MASK(mac, reg, ~tmp2); + break; + case N_INTC_OVERRIDE_EXT_LNA_GAIN: + if (bwn_current_band(mac) == BWN_BAND_5G) { + tmp = 0x0002; + tmp2 = 0x0008; + val = value << 1; + } else { + tmp = 0x0008; + tmp2 = 0x0002; + val = value << 3; + } + BWN_PHY_SETMASK(mac, reg, ~tmp, val); + BWN_PHY_MASK(mac, reg, ~tmp2); + break; + } + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ +static void bwn_nphy_rf_ctl_intc_override(struct bwn_mac *mac, + enum n_intc_override intc_override, + uint16_t value, uint8_t core) +{ + uint8_t i, j; + uint16_t reg, tmp, val; + + if (mac->mac_phy.rev >= 7) { + bwn_nphy_rf_ctl_intc_override_rev7(mac, intc_override, value, + core); + return; + } + + if (mac->mac_phy.rev < 3) { + BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", + __func__, + mac->mac_phy.rev); + } + + for (i = 0; i < 2; i++) { + if ((core == 1 && i == 1) || (core == 2 && !i)) + continue; + + reg = (i == 0) ? + BWN_NPHY_RFCTL_INTC1 : BWN_NPHY_RFCTL_INTC2; + BWN_PHY_SET(mac, reg, 0x400); + + switch (intc_override) { + case N_INTC_OVERRIDE_OFF: + BWN_PHY_WRITE(mac, reg, 0); + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); + break; + case N_INTC_OVERRIDE_TRSW: + if (!i) { + BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_INTC1, + 0xFC3F, (value << 6)); + BWN_PHY_SETMASK(mac, BWN_NPHY_TXF_40CO_B1S1, + 0xFFFE, 1); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_CMD_START); + for (j = 0; j < 100; j++) { + if (!(BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD) & BWN_NPHY_RFCTL_CMD_START)) { + j = 0; + break; + } + DELAY(10); + } + if (j) + BWN_ERRPRINTF(mac->mac_sc, + "intc override timeout\n"); + BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S1, + 0xFFFE); + } else { + BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_INTC2, + 0xFC3F, (value << 6)); + BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_OVER, + 0xFFFE, 1); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_CMD_RXTX); + for (j = 0; j < 100; j++) { + if (!(BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD) & BWN_NPHY_RFCTL_CMD_RXTX)) { + j = 0; + break; + } + DELAY(10); + } + if (j) + BWN_ERRPRINTF(mac->mac_sc, + "intc override timeout\n"); + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, + 0xFFFE); + } + break; + case N_INTC_OVERRIDE_PA: + if (bwn_current_band(mac) == BWN_BAND_5G) { + tmp = 0x0020; + val = value << 5; + } else { + tmp = 0x0010; + val = value << 4; + } + BWN_PHY_SETMASK(mac, reg, ~tmp, val); + break; + case N_INTC_OVERRIDE_EXT_LNA_PU: + if (bwn_current_band(mac) == BWN_BAND_5G) { + tmp = 0x0001; + val = value; + } else { + tmp = 0x0004; + val = value << 2; + } + BWN_PHY_SETMASK(mac, reg, ~tmp, val); + break; + case N_INTC_OVERRIDE_EXT_LNA_GAIN: + if (bwn_current_band(mac) == BWN_BAND_5G) { + tmp = 0x0002; + val = value << 1; + } else { + tmp = 0x0008; + val = value << 3; + } + BWN_PHY_SETMASK(mac, reg, ~tmp, val); + break; + } + } +} + +/************************************************** + * Various PHY ops + **************************************************/ + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ +static void bwn_nphy_write_clip_detection(struct bwn_mac *mac, + const uint16_t *clip_st) +{ + BWN_PHY_WRITE(mac, BWN_NPHY_C1_CLIP1THRES, clip_st[0]); + BWN_PHY_WRITE(mac, BWN_NPHY_C2_CLIP1THRES, clip_st[1]); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ +static void bwn_nphy_read_clip_detection(struct bwn_mac *mac, uint16_t *clip_st) +{ + clip_st[0] = BWN_PHY_READ(mac, BWN_NPHY_C1_CLIP1THRES); + clip_st[1] = BWN_PHY_READ(mac, BWN_NPHY_C2_CLIP1THRES); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ +static uint16_t bwn_nphy_classifier(struct bwn_mac *mac, uint16_t mask, uint16_t val) +{ + struct bwn_softc *sc = mac->mac_sc; + uint16_t tmp; + + if (siba_get_revid(sc->sc_dev) == 16) + bwn_mac_suspend(mac); + + tmp = BWN_PHY_READ(mac, BWN_NPHY_CLASSCTL); + tmp &= (BWN_NPHY_CLASSCTL_CCKEN | BWN_NPHY_CLASSCTL_OFDMEN | + BWN_NPHY_CLASSCTL_WAITEDEN); + tmp &= ~mask; + tmp |= (val & mask); + BWN_PHY_SETMASK(mac, BWN_NPHY_CLASSCTL, 0xFFF8, tmp); + + if (siba_get_revid(sc->sc_dev) == 16) + bwn_mac_enable(mac); + + return tmp; +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ +static void bwn_nphy_reset_cca(struct bwn_mac *mac) +{ + uint16_t bbcfg; + + bwn_phy_force_clock(mac, 1); + bbcfg = BWN_PHY_READ(mac, BWN_NPHY_BBCFG); + BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, bbcfg | BWN_NPHY_BBCFG_RSTCCA); + DELAY(1); + BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, bbcfg & ~BWN_NPHY_BBCFG_RSTCCA); + bwn_phy_force_clock(mac, 0); + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ +static void bwn_nphy_stay_in_carrier_search(struct bwn_mac *mac, bool enable) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = phy->phy_n; + + if (enable) { + static const uint16_t clip[] = { 0xFFFF, 0xFFFF }; + if (nphy->deaf_count++ == 0) { + nphy->classifier_state = bwn_nphy_classifier(mac, 0, 0); + bwn_nphy_classifier(mac, 0x7, + BWN_NPHY_CLASSCTL_WAITEDEN); + bwn_nphy_read_clip_detection(mac, nphy->clip_state); + bwn_nphy_write_clip_detection(mac, clip); + } + bwn_nphy_reset_cca(mac); + } else { + if (--nphy->deaf_count == 0) { + bwn_nphy_classifier(mac, 0x7, nphy->classifier_state); + bwn_nphy_write_clip_detection(mac, nphy->clip_state); + } + } +} + +/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */ +static uint16_t bwn_nphy_read_lpf_ctl(struct bwn_mac *mac, uint16_t offset) +{ + if (!offset) + offset = bwn_is_40mhz(mac) ? 0x159 : 0x154; + return bwn_ntab_read(mac, BWN_NTAB16(7, offset)) & 0x7; +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ +static void bwn_nphy_adjust_lna_gain_table(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint8_t i; + int16_t tmp; + uint16_t data[4]; + int16_t gain[2]; + uint16_t minmax[2]; + static const uint16_t lna_gain[4] = { -2, 10, 19, 25 }; + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 1); + + if (nphy->gain_boost) { + if (bwn_current_band(mac) == BWN_BAND_2G) { + gain[0] = 6; + gain[1] = 6; + } else { + tmp = 40370 - 315 * bwn_get_chan(mac); + gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); + tmp = 23242 - 224 * bwn_get_chan(mac); + gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1)); + } + } else { + gain[0] = 0; + gain[1] = 0; + } + + for (i = 0; i < 2; i++) { + if (nphy->elna_gain_config) { + data[0] = 19 + gain[i]; + data[1] = 25 + gain[i]; + data[2] = 25 + gain[i]; + data[3] = 25 + gain[i]; + } else { + data[0] = lna_gain[0] + gain[i]; + data[1] = lna_gain[1] + gain[i]; + data[2] = lna_gain[2] + gain[i]; + data[3] = lna_gain[3] + gain[i]; + } + bwn_ntab_write_bulk(mac, BWN_NTAB16(i, 8), 4, data); + + minmax[i] = 23 + gain[i]; + } + + BWN_PHY_SETMASK(mac, BWN_NPHY_C1_MINMAX_GAIN, ~BWN_NPHY_C1_MINGAIN, + minmax[0] << BWN_NPHY_C1_MINGAIN_SHIFT); + BWN_PHY_SETMASK(mac, BWN_NPHY_C2_MINMAX_GAIN, ~BWN_NPHY_C2_MINGAIN, + minmax[1] << BWN_NPHY_C2_MINGAIN_SHIFT); + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 0); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ +static void bwn_nphy_set_rf_sequence(struct bwn_mac *mac, uint8_t cmd, + uint8_t *events, uint8_t *delays, uint8_t length) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + uint8_t i; + uint8_t end = (mac->mac_phy.rev >= 3) ? 0x1F : 0x0F; + uint16_t offset1 = cmd << 4; + uint16_t offset2 = offset1 + 0x80; + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, true); + + bwn_ntab_write_bulk(mac, BWN_NTAB8(7, offset1), length, events); + bwn_ntab_write_bulk(mac, BWN_NTAB8(7, offset2), length, delays); + + for (i = length; i < 16; i++) { + bwn_ntab_write(mac, BWN_NTAB8(7, offset1 + i), end); + bwn_ntab_write(mac, BWN_NTAB8(7, offset2 + i), 1); + } + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, false); +} + +/************************************************** + * Radio 0x2057 + **************************************************/ + +static void bwn_radio_2057_chantab_upload(struct bwn_mac *mac, + const struct bwn_nphy_chantabent_rev7 *e_r7, + const struct bwn_nphy_chantabent_rev7_2g *e_r7_2g) +{ + if (e_r7_2g) { + BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0); + BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1); + BWN_RF_WRITE(mac, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1); + BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac); + BWN_RF_WRITE(mac, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0); + BWN_RF_WRITE(mac, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1); + BWN_RF_WRITE(mac, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune); + BWN_RF_WRITE(mac, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune); + BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune); + BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0); + BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0); + BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0); + BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1); + BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1); + BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1); + + } else { + BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0); + BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1); + BWN_RF_WRITE(mac, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1); + BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac); + BWN_RF_WRITE(mac, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0); + BWN_RF_WRITE(mac, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1); + BWN_RF_WRITE(mac, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune); + BWN_RF_WRITE(mac, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune); + BWN_RF_WRITE(mac, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune); + BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune); + BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune); + BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0); + BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0); + BWN_RF_WRITE(mac, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0); + BWN_RF_WRITE(mac, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0); + BWN_RF_WRITE(mac, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0); + BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0); + BWN_RF_WRITE(mac, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0); + BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1); + BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1); + BWN_RF_WRITE(mac, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1); + BWN_RF_WRITE(mac, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1); + BWN_RF_WRITE(mac, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1); + BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1); + BWN_RF_WRITE(mac, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1); + } +} + +static void bwn_radio_2057_setup(struct bwn_mac *mac, + const struct bwn_nphy_chantabent_rev7 *tabent_r7, + const struct bwn_nphy_chantabent_rev7_2g *tabent_r7_2g) +{ + struct bwn_phy *phy = &mac->mac_phy; + + bwn_radio_2057_chantab_upload(mac, tabent_r7, tabent_r7_2g); + + switch (phy->rf_rev) { + case 0 ... 4: + case 6: + if (bwn_current_band(mac) == BWN_BAND_2G) { + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x3f); + BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x8); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x8); + } else { + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x1f); + BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x8); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x8); + } + break; + case 9: /* e.g. PHY rev 16 */ + BWN_RF_WRITE(mac, R2057_LOGEN_PTAT_RESETS, 0x20); + BWN_RF_WRITE(mac, R2057_VCOBUF_IDACS, 0x18); + if (bwn_current_band(mac) == BWN_BAND_5G) { + BWN_RF_WRITE(mac, R2057_LOGEN_PTAT_RESETS, 0x38); + BWN_RF_WRITE(mac, R2057_VCOBUF_IDACS, 0x0f); + + if (bwn_is_40mhz(mac)) { + /* TODO */ + } else { + BWN_RF_WRITE(mac, + R2057_PAD_BIAS_FILTER_BWS_CORE0, + 0x3c); + BWN_RF_WRITE(mac, + R2057_PAD_BIAS_FILTER_BWS_CORE1, + 0x3c); + } + } + break; + case 14: /* 2 GHz only */ + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x1b); + BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x1f); + BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x1f); + break; + } + + if (bwn_current_band(mac) == BWN_BAND_2G) { + uint16_t txmix2g_tune_boost_pu = 0; + uint16_t pad2g_tune_pus = 0; + + if (bwn_nphy_ipa(mac)) { + switch (phy->rf_rev) { + case 9: + txmix2g_tune_boost_pu = 0x0041; + /* TODO */ + break; + case 14: + txmix2g_tune_boost_pu = 0x21; + pad2g_tune_pus = 0x23; + break; + } + } + + if (txmix2g_tune_boost_pu) + BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, + txmix2g_tune_boost_pu); + if (pad2g_tune_pus) + BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, + pad2g_tune_pus); + if (txmix2g_tune_boost_pu) + BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, + txmix2g_tune_boost_pu); + if (pad2g_tune_pus) + BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, + pad2g_tune_pus); + } + + /* 50..100 */ + DELAY(100); + + /* VCO calibration */ + BWN_RF_MASK(mac, R2057_RFPLL_MISC_EN, ~0x01); + BWN_RF_MASK(mac, R2057_RFPLL_MISC_CAL_RESETN, ~0x04); + BWN_RF_SET(mac, R2057_RFPLL_MISC_CAL_RESETN, 0x4); + BWN_RF_SET(mac, R2057_RFPLL_MISC_EN, 0x01); + /* 300..600 */ + DELAY(600); +} + +/* Calibrate resistors in LPF of PLL? + * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal + */ +static uint8_t bwn_radio_2057_rcal(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + uint16_t saved_regs_phy[12]; + uint16_t saved_regs_phy_rf[6]; + uint16_t saved_regs_radio[2] = { }; + static const uint16_t phy_to_store[] = { + BWN_NPHY_RFCTL_RSSIO1, BWN_NPHY_RFCTL_RSSIO2, + BWN_NPHY_RFCTL_LUT_TRSW_LO1, BWN_NPHY_RFCTL_LUT_TRSW_LO2, + BWN_NPHY_RFCTL_RXG1, BWN_NPHY_RFCTL_RXG2, + BWN_NPHY_RFCTL_TXG1, BWN_NPHY_RFCTL_TXG2, + BWN_NPHY_REV7_RF_CTL_MISC_REG3, BWN_NPHY_REV7_RF_CTL_MISC_REG4, + BWN_NPHY_REV7_RF_CTL_MISC_REG5, BWN_NPHY_REV7_RF_CTL_MISC_REG6, + }; + static const uint16_t phy_to_store_rf[] = { + BWN_NPHY_REV3_RFCTL_OVER0, BWN_NPHY_REV3_RFCTL_OVER1, + BWN_NPHY_REV7_RF_CTL_OVER3, BWN_NPHY_REV7_RF_CTL_OVER4, + BWN_NPHY_REV7_RF_CTL_OVER5, BWN_NPHY_REV7_RF_CTL_OVER6, + }; + uint16_t tmp; + int i; + + /* Save */ + for (i = 0; i < nitems(phy_to_store); i++) + saved_regs_phy[i] = BWN_PHY_READ(mac, phy_to_store[i]); + for (i = 0; i < nitems(phy_to_store_rf); i++) + saved_regs_phy_rf[i] = BWN_PHY_READ(mac, phy_to_store_rf[i]); + + /* Set */ + for (i = 0; i < nitems(phy_to_store); i++) + BWN_PHY_WRITE(mac, phy_to_store[i], 0); + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_RFCTL_OVER0, 0x07ff); + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_RFCTL_OVER1, 0x07ff); + BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x07ff); + BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER4, 0x07ff); + BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER5, 0x007f); + BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER6, 0x007f); + + switch (phy->rf_rev) { + case 5: + BWN_PHY_MASK(mac, BWN_NPHY_REV7_RF_CTL_OVER3, ~0x2); + DELAY(10); + BWN_RF_SET(mac, R2057_IQTEST_SEL_PU, 0x1); + BWN_RF_SETMASK(mac, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1); + break; + case 9: + BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x2); + BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); + saved_regs_radio[0] = BWN_RF_READ(mac, R2057_IQTEST_SEL_PU); + BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, 0x11); + break; + case 14: + saved_regs_radio[0] = BWN_RF_READ(mac, R2057_IQTEST_SEL_PU); + saved_regs_radio[1] = BWN_RF_READ(mac, R2057v7_IQTEST_SEL_PU2); + BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); + BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x2); + BWN_RF_WRITE(mac, R2057v7_IQTEST_SEL_PU2, 0x2); + BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, 0x1); + break; + } + + /* Enable */ + BWN_RF_SET(mac, R2057_RCAL_CONFIG, 0x1); + DELAY(10); + + /* Start */ + BWN_RF_SET(mac, R2057_RCAL_CONFIG, 0x2); + /* 100..200 */ + DELAY(200); + + /* Stop */ + BWN_RF_MASK(mac, R2057_RCAL_CONFIG, ~0x2); + + /* Wait and check for result */ + if (!bwn_radio_wait_value(mac, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) { + BWN_ERRPRINTF(mac->mac_sc, "Radio 0x2057 rcal timeout\n"); + return 0; + } + tmp = BWN_RF_READ(mac, R2057_RCAL_STATUS) & 0x3E; + + /* Disable */ + BWN_RF_MASK(mac, R2057_RCAL_CONFIG, ~0x1); + + /* Restore */ + for (i = 0; i < nitems(phy_to_store_rf); i++) + BWN_PHY_WRITE(mac, phy_to_store_rf[i], saved_regs_phy_rf[i]); + for (i = 0; i < nitems(phy_to_store); i++) + BWN_PHY_WRITE(mac, phy_to_store[i], saved_regs_phy[i]); + + switch (phy->rf_rev) { + case 0 ... 4: + case 6: + BWN_RF_SETMASK(mac, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp); + BWN_RF_SETMASK(mac, R2057_BANDGAP_RCAL_TRIM, ~0xF0, + tmp << 2); + break; + case 5: + BWN_RF_MASK(mac, R2057_IPA2G_CASCONV_CORE0, ~0x1); + BWN_RF_MASK(mac, R2057v7_IQTEST_SEL_PU2, ~0x2); + break; + case 9: + BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); + break; + case 14: + BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); + BWN_RF_WRITE(mac, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]); + break; + } + + return tmp & 0x3e; +} + +/* Calibrate the internal RC oscillator? + * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal + */ +static uint16_t bwn_radio_2057_rccal(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + bool special = (phy->rf_rev == 3 || phy->rf_rev == 4 || + phy->rf_rev == 6); + uint16_t tmp; + + /* Setup cal */ + if (special) { + BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x61); + BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xC0); + } else { + BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x61); + BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xE9); + } + BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E); + + /* Start, wait, stop */ + BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55); + if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, + 5000000)) + BWN_DBGPRINTF(mac, "Radio 0x2057 rccal timeout\n"); + /* 35..70 */ + DELAY(70); + BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15); + /* 70..140 */ + DELAY(140); + + /* Setup cal */ + if (special) { + BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x69); + BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xB0); + } else { + BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x69); + BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xD5); + } + BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E); + + /* Start, wait, stop */ + /* 35..70 */ + DELAY(70); + BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55); + /* 70..140 */ + DELAY(140); + if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, + 5000000)) + BWN_DBGPRINTF(mac, "Radio 0x2057 rccal timeout\n"); + /* 35..70 */ + DELAY(70); + BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15); + /* 70..140 */ + DELAY(140); + + /* Setup cal */ + if (special) { + BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x73); + BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x28); + BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xB0); + } else { + BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x73); + BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E); + BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0x99); + } + + /* Start, wait, stop */ + /* 35..70 */ + DELAY(70); + BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55); + /* 70..140 */ + DELAY(140); + if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, + 5000000)) { + BWN_ERRPRINTF(mac->mac_sc, "Radio 0x2057 rcal timeout\n"); + return 0; + } + tmp = BWN_RF_READ(mac, R2057_RCCAL_DONE_OSCCAP); + /* 35..70 */ + DELAY(70); + BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15); + /* 70..140 */ + DELAY(140); + + if (special) + BWN_RF_MASK(mac, R2057_RCCAL_MASTER, ~0x1); + else + BWN_RF_MASK(mac, R2057v7_RCCAL_MASTER, ~0x1); + + return tmp; +} + +static void bwn_radio_2057_init_pre(struct bwn_mac *mac) +{ + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_CHIP0PU); + /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_OEPORFORCE); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_OEPORFORCE); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_CHIP0PU); +} + +static void bwn_radio_2057_init_post(struct bwn_mac *mac) +{ + BWN_RF_SET(mac, R2057_XTALPUOVR_PINCTRL, 0x1); + + if (0) /* FIXME: Is this BCM43217 specific? */ + BWN_RF_SET(mac, R2057_XTALPUOVR_PINCTRL, 0x2); + + BWN_RF_SET(mac, R2057_RFPLL_MISC_CAL_RESETN, 0x78); + BWN_RF_SET(mac, R2057_XTAL_CONFIG2, 0x80); + DELAY(2000); + BWN_RF_MASK(mac, R2057_RFPLL_MISC_CAL_RESETN, ~0x78); + BWN_RF_MASK(mac, R2057_XTAL_CONFIG2, ~0x80); + + if (mac->mac_phy.phy_do_full_init) { + bwn_radio_2057_rcal(mac); + bwn_radio_2057_rccal(mac); + } + BWN_RF_MASK(mac, R2057_RFPLL_MASTER, ~0x8); +} + +/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */ +static void bwn_radio_2057_init(struct bwn_mac *mac) +{ + bwn_radio_2057_init_pre(mac); + r2057_upload_inittabs(mac); + bwn_radio_2057_init_post(mac); +} + +/************************************************** + * Radio 0x2056 + **************************************************/ + +static void bwn_chantab_radio_2056_upload(struct bwn_mac *mac, + const struct bwn_nphy_channeltab_entry_rev3 *e) +{ + BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1); + BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2); + BWN_RF_WRITE(mac, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv); + BWN_RF_WRITE(mac, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2); + BWN_RF_WRITE(mac, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, + e->radio_syn_pll_loopfilter1); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, + e->radio_syn_pll_loopfilter2); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER3, + e->radio_syn_pll_loopfilter3); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, + e->radio_syn_pll_loopfilter4); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER5, + e->radio_syn_pll_loopfilter5); + BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR27, + e->radio_syn_reserved_addr27); + BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR28, + e->radio_syn_reserved_addr28); + BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR29, + e->radio_syn_reserved_addr29); + BWN_RF_WRITE(mac, B2056_SYN_LOGEN_VCOBUF1, + e->radio_syn_logen_vcobuf1); + BWN_RF_WRITE(mac, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2); + BWN_RF_WRITE(mac, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3); + BWN_RF_WRITE(mac, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4); + + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAA_TUNE, + e->radio_rx0_lnaa_tune); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAG_TUNE, + e->radio_rx0_lnag_tune); + + BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE, + e->radio_tx0_intpaa_boost_tune); + BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE, + e->radio_tx0_intpag_boost_tune); + BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE, + e->radio_tx0_pada_boost_tune); + BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE, + e->radio_tx0_padg_boost_tune); + BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE, + e->radio_tx0_pgaa_boost_tune); + BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE, + e->radio_tx0_pgag_boost_tune); + BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE, + e->radio_tx0_mixa_boost_tune); + BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE, + e->radio_tx0_mixg_boost_tune); + + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAA_TUNE, + e->radio_rx1_lnaa_tune); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAG_TUNE, + e->radio_rx1_lnag_tune); + + BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE, + e->radio_tx1_intpaa_boost_tune); + BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE, + e->radio_tx1_intpag_boost_tune); + BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE, + e->radio_tx1_pada_boost_tune); + BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE, + e->radio_tx1_padg_boost_tune); + BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE, + e->radio_tx1_pgaa_boost_tune); + BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE, + e->radio_tx1_pgag_boost_tune); + BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE, + e->radio_tx1_mixa_boost_tune); + BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE, + e->radio_tx1_mixg_boost_tune); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */ +static void bwn_radio_2056_setup(struct bwn_mac *mac, + const struct bwn_nphy_channeltab_entry_rev3 *e) +{ + struct bwn_softc *sc = mac->mac_sc; + bwn_band_t band = bwn_current_band(mac); + uint16_t offset; + uint8_t i; + uint16_t bias, cbias; + uint16_t pag_boost, padg_boost, pgag_boost, mixg_boost; + uint16_t paa_boost, pada_boost, pgaa_boost, mixa_boost; + bool is_pkg_fab_smic; + + DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); + + if (mac->mac_phy.rev < 3) { + BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", + __func__, + mac->mac_phy.rev); + } + + is_pkg_fab_smic = + ((siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM43224 || + siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM43225 || + siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM43421) && + siba_get_chippkg(sc->sc_dev) == BCMA_PKG_ID_BCM43224_FAB_SMIC); + + bwn_chantab_radio_2056_upload(mac, e); + b2056_upload_syn_pll_cp2(mac, band == BWN_BAND_5G); + + if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_GPLL_WAR && + bwn_current_band(mac) == BWN_BAND_2G) { + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F); + if (siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM4716 || + siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM47162) { + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x14); + BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0); + } else { + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x0B); + BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x14); + } + } + if (siba_sprom_get_bf2_hi(sc->sc_dev) & BWN_BFH2_GPLL_WAR2 && + bwn_current_band(mac) == BWN_BAND_2G) { + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1f); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1f); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x0b); + BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x20); + } + if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_APLL_WAR && + bwn_current_band(mac) == BWN_BAND_5G) { + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F); + BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x05); + BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x0C); + } + + if (mac->mac_phy.phy_n->ipa2g_on && band == BWN_BAND_2G) { + for (i = 0; i < 2; i++) { + offset = i ? B2056_TX1 : B2056_TX0; + if (mac->mac_phy.rev >= 5) { + BWN_RF_WRITE(mac, + offset | B2056_TX_PADG_IDAC, 0xcc); + + if (siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM4716 || + siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM47162) { + bias = 0x40; + cbias = 0x45; + pag_boost = 0x5; + pgag_boost = 0x33; + mixg_boost = 0x55; + } else { + bias = 0x25; + cbias = 0x20; + if (is_pkg_fab_smic) { + bias = 0x2a; + cbias = 0x38; + } + pag_boost = 0x4; + pgag_boost = 0x03; + mixg_boost = 0x65; + } + padg_boost = 0x77; + + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAG_IMAIN_STAT, + bias); + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAG_IAUX_STAT, + bias); + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAG_CASCBIAS, + cbias); + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAG_BOOST_TUNE, + pag_boost); + BWN_RF_WRITE(mac, + offset | B2056_TX_PGAG_BOOST_TUNE, + pgag_boost); + BWN_RF_WRITE(mac, + offset | B2056_TX_PADG_BOOST_TUNE, + padg_boost); + BWN_RF_WRITE(mac, + offset | B2056_TX_MIXG_BOOST_TUNE, + mixg_boost); + } else { + bias = bwn_is_40mhz(mac) ? 0x40 : 0x20; + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAG_IMAIN_STAT, + bias); + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAG_IAUX_STAT, + bias); + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAG_CASCBIAS, + 0x30); + } + BWN_RF_WRITE(mac, offset | B2056_TX_PA_SPARE1, 0xee); + } + } else if (mac->mac_phy.phy_n->ipa5g_on && band == BWN_BAND_5G) { + uint16_t freq = bwn_get_centre_freq(mac); + /* XXX 5g low/med/high? */ + if (freq < 5100) { + paa_boost = 0xA; + pada_boost = 0x77; + pgaa_boost = 0xF; + mixa_boost = 0xF; + } else if (freq < 5340) { + paa_boost = 0x8; + pada_boost = 0x77; + pgaa_boost = 0xFB; + mixa_boost = 0xF; + } else if (freq < 5650) { + paa_boost = 0x0; + pada_boost = 0x77; + pgaa_boost = 0xB; + mixa_boost = 0xF; + } else { + paa_boost = 0x0; + pada_boost = 0x77; + if (freq != 5825) + pgaa_boost = -(freq - 18) / 36 + 168; + else + pgaa_boost = 6; + mixa_boost = 0xF; + } + + cbias = is_pkg_fab_smic ? 0x35 : 0x30; + + for (i = 0; i < 2; i++) { + offset = i ? B2056_TX1 : B2056_TX0; + + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost); + BWN_RF_WRITE(mac, + offset | B2056_TX_PADA_BOOST_TUNE, pada_boost); + BWN_RF_WRITE(mac, + offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost); + BWN_RF_WRITE(mac, + offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost); + BWN_RF_WRITE(mac, + offset | B2056_TX_TXSPARE1, 0x30); + BWN_RF_WRITE(mac, + offset | B2056_TX_PA_SPARE2, 0xee); + BWN_RF_WRITE(mac, + offset | B2056_TX_PADA_CASCBIAS, 0x03); + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAA_IAUX_STAT, 0x30); + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30); + BWN_RF_WRITE(mac, + offset | B2056_TX_INTPAA_CASCBIAS, cbias); + } + } + + DELAY(50); + /* VCO calibration */ + BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL12, 0x00); + BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x38); + BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x18); + BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x38); + BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x39); + DELAY(300); +} + +static uint8_t bwn_radio_2056_rcal(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + uint16_t mast2, tmp; + + if (phy->rev != 3) + return 0; + DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); + + mast2 = BWN_RF_READ(mac, B2056_SYN_PLL_MAST2); + BWN_RF_WRITE(mac, B2056_SYN_PLL_MAST2, mast2 | 0x7); + + DELAY(10); + BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x01); + DELAY(10); + BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x09); + + if (!bwn_radio_wait_value(mac, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100, + 1000000)) { + BWN_ERRPRINTF(mac->mac_sc, "Radio recalibration timeout\n"); + return 0; + } + + BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x01); + tmp = BWN_RF_READ(mac, B2056_SYN_RCAL_CODE_OUT); + BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x00); + + BWN_RF_WRITE(mac, B2056_SYN_PLL_MAST2, mast2); + + return tmp & 0x1f; +} + +static void bwn_radio_init2056_pre(struct bwn_mac *mac) +{ + DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); + + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, + ~BWN_NPHY_RFCTL_CMD_CHIP0PU); + /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_CMD_OEPORFORCE); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, + ~BWN_NPHY_RFCTL_CMD_OEPORFORCE); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_CMD_CHIP0PU); +} + +static void bwn_radio_init2056_post(struct bwn_mac *mac) +{ + DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); + + BWN_RF_SET(mac, B2056_SYN_COM_CTRL, 0xB); + BWN_RF_SET(mac, B2056_SYN_COM_PU, 0x2); + BWN_RF_SET(mac, B2056_SYN_COM_RESET, 0x2); + DELAY(1000); + BWN_RF_MASK(mac, B2056_SYN_COM_RESET, ~0x2); + BWN_RF_MASK(mac, B2056_SYN_PLL_MAST2, ~0xFC); + BWN_RF_MASK(mac, B2056_SYN_RCCAL_CTRL0, ~0x1); + if (mac->mac_phy.phy_do_full_init) + bwn_radio_2056_rcal(mac); +} + +/* + * Initialize a Broadcom 2056 N-radio + * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init + */ +static void bwn_radio_init2056(struct bwn_mac *mac) +{ + DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); + + bwn_radio_init2056_pre(mac); + b2056_upload_inittabs(mac, 0, 0); + bwn_radio_init2056_post(mac); +} + +/************************************************** + * Radio 0x2055 + **************************************************/ + +static void bwn_chantab_radio_upload(struct bwn_mac *mac, + const struct bwn_nphy_channeltab_entry_rev2 *e) +{ + BWN_RF_WRITE(mac, B2055_PLL_REF, e->radio_pll_ref); + BWN_RF_WRITE(mac, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); + BWN_RF_WRITE(mac, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); + BWN_RF_WRITE(mac, B2055_VCO_CAPTAIL, e->radio_vco_captail); + BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ + + BWN_RF_WRITE(mac, B2055_VCO_CAL1, e->radio_vco_cal1); + BWN_RF_WRITE(mac, B2055_VCO_CAL2, e->radio_vco_cal2); + BWN_RF_WRITE(mac, B2055_PLL_LFC1, e->radio_pll_lfc1); + BWN_RF_WRITE(mac, B2055_PLL_LFR1, e->radio_pll_lfr1); + BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ + + BWN_RF_WRITE(mac, B2055_PLL_LFC2, e->radio_pll_lfc2); + BWN_RF_WRITE(mac, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); + BWN_RF_WRITE(mac, B2055_LGEN_TUNE1, e->radio_lgen_tune1); + BWN_RF_WRITE(mac, B2055_LGEN_TUNE2, e->radio_lgen_tune2); + BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ + + BWN_RF_WRITE(mac, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); + BWN_RF_WRITE(mac, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); + BWN_RF_WRITE(mac, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); + BWN_RF_WRITE(mac, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); + BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ + + BWN_RF_WRITE(mac, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); + BWN_RF_WRITE(mac, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); + BWN_RF_WRITE(mac, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); + BWN_RF_WRITE(mac, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); + BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ + + BWN_RF_WRITE(mac, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); + BWN_RF_WRITE(mac, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ +static void bwn_radio_2055_setup(struct bwn_mac *mac, + const struct bwn_nphy_channeltab_entry_rev2 *e) +{ + + if (mac->mac_phy.rev >= 3) { + BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", + __func__, + mac->mac_phy.rev); + } + + DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); + + bwn_chantab_radio_upload(mac, e); + DELAY(50); + BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x05); + BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x45); + BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ + BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x65); + DELAY(300); +} + +static void bwn_radio_init2055_pre(struct bwn_mac *mac) +{ + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, + ~BWN_NPHY_RFCTL_CMD_PORFORCE); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_CMD_CHIP0PU | + BWN_NPHY_RFCTL_CMD_OEPORFORCE); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_CMD_PORFORCE); +} + +static void bwn_radio_init2055_post(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + bool workaround = false; + + if (siba_get_revid(sc->sc_dev) < 4) + workaround = + (siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM) + && (siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BCM4321) + && (siba_sprom_get_brev(sc->sc_dev) >= 0x41); + else + workaround = + !(siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_RXBB_INT_REG_DIS); + + BWN_RF_MASK(mac, B2055_MASTER1, 0xFFF3); + if (workaround) { + BWN_RF_MASK(mac, B2055_C1_RX_BB_REG, 0x7F); + BWN_RF_MASK(mac, B2055_C2_RX_BB_REG, 0x7F); + } + BWN_RF_SETMASK(mac, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); + BWN_RF_WRITE(mac, B2055_CAL_MISC, 0x3C); + BWN_RF_MASK(mac, B2055_CAL_MISC, 0xFFBE); + BWN_RF_SET(mac, B2055_CAL_LPOCTL, 0x80); + BWN_RF_SET(mac, B2055_CAL_MISC, 0x1); + DELAY(1000); + BWN_RF_SET(mac, B2055_CAL_MISC, 0x40); + if (!bwn_radio_wait_value(mac, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000)) + BWN_ERRPRINTF(mac->mac_sc, "radio post init timeout\n"); + BWN_RF_MASK(mac, B2055_CAL_LPOCTL, 0xFF7F); + bwn_switch_channel(mac, bwn_get_chan(mac)); + BWN_RF_WRITE(mac, B2055_C1_RX_BB_LPF, 0x9); + BWN_RF_WRITE(mac, B2055_C2_RX_BB_LPF, 0x9); + BWN_RF_WRITE(mac, B2055_C1_RX_BB_MIDACHP, 0x83); + BWN_RF_WRITE(mac, B2055_C2_RX_BB_MIDACHP, 0x83); + BWN_RF_SETMASK(mac, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); + BWN_RF_SETMASK(mac, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); + if (!nphy->gain_boost) { + BWN_RF_SET(mac, B2055_C1_RX_RFSPC1, 0x2); + BWN_RF_SET(mac, B2055_C2_RX_RFSPC1, 0x2); + } else { + BWN_RF_MASK(mac, B2055_C1_RX_RFSPC1, 0xFFFD); + BWN_RF_MASK(mac, B2055_C2_RX_RFSPC1, 0xFFFD); + } + DELAY(2); +} + +/* + * Initialize a Broadcom 2055 N-radio + * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init + */ +static void bwn_radio_init2055(struct bwn_mac *mac) +{ + bwn_radio_init2055_pre(mac); + if (mac->mac_status < BWN_MAC_STATUS_INITED) { + /* Follow wl, not specs. Do not force uploading all regs */ + b2055_upload_inittab(mac, 0, 0); + } else { + bool ghz5 = bwn_current_band(mac) == BWN_BAND_5G; + b2055_upload_inittab(mac, ghz5, 0); + } + bwn_radio_init2055_post(mac); +} + +/************************************************** + * Samples + **************************************************/ + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ +static int bwn_nphy_load_samples(struct bwn_mac *mac, + struct bwn_c32 *samples, uint16_t len) { + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + uint16_t i; + uint32_t *data; + + data = malloc(len * sizeof(uint32_t), M_DEVBUF, M_NOWAIT | M_ZERO); + if (!data) { + BWN_ERRPRINTF(mac->mac_sc, "allocation for samples loading failed\n"); + return -ENOMEM; + } + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 1); + + for (i = 0; i < len; i++) { + data[i] = (samples[i].i & 0x3FF << 10); + data[i] |= samples[i].q & 0x3FF; + } + bwn_ntab_write_bulk(mac, BWN_NTAB32(17, 0), len, data); + + free(data, M_DEVBUF); + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 0); + return 0; +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ +static uint16_t bwn_nphy_gen_load_samples(struct bwn_mac *mac, uint32_t freq, uint16_t max, + bool test) +{ + int i; + uint16_t bw, len, rot, angle; + struct bwn_c32 *samples; + + bw = bwn_is_40mhz(mac) ? 40 : 20; + len = bw << 3; + + if (test) { + if (BWN_PHY_READ(mac, BWN_NPHY_BBCFG) & BWN_NPHY_BBCFG_RSTRX) + bw = 82; + else + bw = 80; + + if (bwn_is_40mhz(mac)) + bw <<= 1; + + len = bw << 1; + } + + samples = malloc(len * sizeof(struct bwn_c32), M_DEVBUF, M_NOWAIT | M_ZERO); + if (!samples) { + BWN_ERRPRINTF(mac->mac_sc, "allocation for samples generation failed\n"); + return 0; + } + rot = (((freq * 36) / bw) << 16) / 100; + angle = 0; + + for (i = 0; i < len; i++) { + samples[i] = bwn_cordic(angle); + angle += rot; + samples[i].q = CORDIC_CONVERT(samples[i].q * max); + samples[i].i = CORDIC_CONVERT(samples[i].i * max); + } + + i = bwn_nphy_load_samples(mac, samples, len); + free(samples, M_DEVBUF); + return (i < 0) ? 0 : len; +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ +static void bwn_nphy_run_samples(struct bwn_mac *mac, uint16_t samps, uint16_t loops, + uint16_t wait, bool iqmode, bool dac_test, + bool modify_bbmult) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + int i; + uint16_t seq_mode; + uint32_t tmp; + + bwn_nphy_stay_in_carrier_search(mac, true); + + if (phy->rev >= 7) { + bool lpf_bw3, lpf_bw4; + + lpf_bw3 = BWN_PHY_READ(mac, BWN_NPHY_REV7_RF_CTL_OVER3) & 0x80; + lpf_bw4 = BWN_PHY_READ(mac, BWN_NPHY_REV7_RF_CTL_OVER4) & 0x80; + + if (lpf_bw3 || lpf_bw4) { + /* TODO */ + } else { + uint16_t value = bwn_nphy_read_lpf_ctl(mac, 0); + if (phy->rev >= 19) + bwn_nphy_rf_ctl_override_rev19(mac, 0x80, value, + 0, false, 1); + else + bwn_nphy_rf_ctl_override_rev7(mac, 0x80, value, + 0, false, 1); + nphy->lpf_bw_overrode_for_sample_play = true; + } + } + + if ((nphy->bb_mult_save & 0x80000000) == 0) { + tmp = bwn_ntab_read(mac, BWN_NTAB16(15, 87)); + nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; + } + + if (modify_bbmult) { + tmp = !bwn_is_40mhz(mac) ? 0x6464 : 0x4747; + bwn_ntab_write(mac, BWN_NTAB16(15, 87), tmp); + } + + BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_DEPCNT, (samps - 1)); + + if (loops != 0xFFFF) + BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_LOOPCNT, (loops - 1)); + else + BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_LOOPCNT, loops); + + BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_WAITCNT, wait); + + seq_mode = BWN_PHY_READ(mac, BWN_NPHY_RFSEQMODE); + + BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE, BWN_NPHY_RFSEQMODE_CAOVER); + if (iqmode) { + BWN_PHY_MASK(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); + BWN_PHY_SET(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8000); + } else { + tmp = dac_test ? 5 : 1; + BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_CMD, tmp); + } + for (i = 0; i < 100; i++) { + if (!(BWN_PHY_READ(mac, BWN_NPHY_RFSEQST) & 1)) { + i = 0; + break; + } + DELAY(10); + } + if (i) + BWN_ERRPRINTF(mac->mac_sc, "run samples timeout\n"); + + BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQMODE, seq_mode); + + bwn_nphy_stay_in_carrier_search(mac, false); +} + +/************************************************** + * RSSI + **************************************************/ + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ +static void bwn_nphy_scale_offset_rssi(struct bwn_mac *mac, uint16_t scale, + int8_t offset, uint8_t core, + enum n_rail_type rail, + enum n_rssi_type rssi_type) +{ + uint16_t tmp; + bool core1or5 = (core == 1) || (core == 5); + bool core2or5 = (core == 2) || (core == 5); + + offset = bwn_clamp_val(offset, -32, 31); + tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); + + switch (rssi_type) { + case N_RSSI_NB: + if (core1or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z, tmp); + if (core1or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z, tmp); + if (core2or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z, tmp); + if (core2or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z, tmp); + break; + case N_RSSI_W1: + if (core1or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_X, tmp); + if (core1or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X, tmp); + if (core2or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_X, tmp); + if (core2or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X, tmp); + break; + case N_RSSI_W2: + if (core1or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y, tmp); + if (core1or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y, tmp); + if (core2or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y, tmp); + if (core2or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y, tmp); + break; + case N_RSSI_TBD: + if (core1or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_TBD, tmp); + if (core1or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_TBD, tmp); + if (core2or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_TBD, tmp); + if (core2or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_TBD, tmp); + break; + case N_RSSI_IQ: + if (core1or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_PWRDET, tmp); + if (core1or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_PWRDET, tmp); + if (core2or5 && rail == N_RAIL_I) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_PWRDET, tmp); + if (core2or5 && rail == N_RAIL_Q) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_PWRDET, tmp); + break; + case N_RSSI_TSSI_2G: + if (core1or5) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_TSSI, tmp); + if (core2or5) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_TSSI, tmp); + break; + case N_RSSI_TSSI_5G: + if (core1or5) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_TSSI, tmp); + if (core2or5) + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_TSSI, tmp); + break; + } +} + +static void bwn_nphy_rssi_select_rev19(struct bwn_mac *mac, uint8_t code, + enum n_rssi_type rssi_type) +{ + /* TODO */ +} + +static void bwn_nphy_rev3_rssi_select(struct bwn_mac *mac, uint8_t code, + enum n_rssi_type rssi_type) +{ + uint8_t i; + uint16_t reg, val; + + if (code == 0) { + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, 0xFDFF); + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, 0xFDFF); + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, 0xFCFF); + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, 0xFCFF); + BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S0, 0xFFDF); + BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B32S1, 0xFFDF); + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); + } else { + for (i = 0; i < 2; i++) { + if ((code == 1 && i == 1) || (code == 2 && !i)) + continue; + + reg = (i == 0) ? + BWN_NPHY_AFECTL_OVER1 : BWN_NPHY_AFECTL_OVER; + BWN_PHY_SETMASK(mac, reg, 0xFDFF, 0x0200); + + if (rssi_type == N_RSSI_W1 || + rssi_type == N_RSSI_W2 || + rssi_type == N_RSSI_NB) { + reg = (i == 0) ? + BWN_NPHY_AFECTL_C1 : + BWN_NPHY_AFECTL_C2; + BWN_PHY_SETMASK(mac, reg, 0xFCFF, 0); + + reg = (i == 0) ? + BWN_NPHY_RFCTL_LUT_TRSW_UP1 : + BWN_NPHY_RFCTL_LUT_TRSW_UP2; + BWN_PHY_SETMASK(mac, reg, 0xFFC3, 0); + + if (rssi_type == N_RSSI_W1) + val = (bwn_current_band(mac) == BWN_BAND_5G) ? 4 : 8; + else if (rssi_type == N_RSSI_W2) + val = 16; + else + val = 32; + BWN_PHY_SET(mac, reg, val); + + reg = (i == 0) ? + BWN_NPHY_TXF_40CO_B1S0 : + BWN_NPHY_TXF_40CO_B32S1; + BWN_PHY_SET(mac, reg, 0x0020); + } else { + if (rssi_type == N_RSSI_TBD) + val = 0x0100; + else if (rssi_type == N_RSSI_IQ) + val = 0x0200; + else + val = 0x0300; + + reg = (i == 0) ? + BWN_NPHY_AFECTL_C1 : + BWN_NPHY_AFECTL_C2; + + BWN_PHY_SETMASK(mac, reg, 0xFCFF, val); + BWN_PHY_SETMASK(mac, reg, 0xF3FF, val << 2); + + if (rssi_type != N_RSSI_IQ && + rssi_type != N_RSSI_TBD) { + bwn_band_t band = + bwn_current_band(mac); + + if (mac->mac_phy.rev < 7) { + if (bwn_nphy_ipa(mac)) + val = (band == BWN_BAND_5G) ? 0xC : 0xE; + else + val = 0x11; + reg = (i == 0) ? B2056_TX0 : B2056_TX1; + reg |= B2056_TX_TX_SSI_MUX; + BWN_RF_WRITE(mac, reg, val); + } + + reg = (i == 0) ? + BWN_NPHY_AFECTL_OVER1 : + BWN_NPHY_AFECTL_OVER; + BWN_PHY_SET(mac, reg, 0x0200); + } + } + } + } +} + +static void bwn_nphy_rev2_rssi_select(struct bwn_mac *mac, uint8_t code, + enum n_rssi_type rssi_type) +{ + uint16_t val; + bool rssi_w1_w2_nb = false; + + switch (rssi_type) { + case N_RSSI_W1: + case N_RSSI_W2: + case N_RSSI_NB: + val = 0; + rssi_w1_w2_nb = true; + break; + case N_RSSI_TBD: + val = 1; + break; + case N_RSSI_IQ: + val = 2; + break; + default: + val = 3; + } + + val = (val << 12) | (val << 14); + BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, val); + BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, val); + + if (rssi_w1_w2_nb) { + BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_RSSIO1, 0xFFCF, + (rssi_type + 1) << 4); + BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_RSSIO2, 0xFFCF, + (rssi_type + 1) << 4); + } + + if (code == 0) { + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x3000); + if (rssi_w1_w2_nb) { + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, + ~(BWN_NPHY_RFCTL_CMD_RXEN | + BWN_NPHY_RFCTL_CMD_CORESEL)); + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, + ~(0x1 << 12 | + 0x1 << 5 | + 0x1 << 1 | + 0x1)); + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, + ~BWN_NPHY_RFCTL_CMD_START); + DELAY(20); + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1); + } + } else { + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x3000); + if (rssi_w1_w2_nb) { + BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_CMD, + ~(BWN_NPHY_RFCTL_CMD_RXEN | + BWN_NPHY_RFCTL_CMD_CORESEL), + (BWN_NPHY_RFCTL_CMD_RXEN | + code << BWN_NPHY_RFCTL_CMD_CORESEL_SHIFT)); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, + (0x1 << 12 | + 0x1 << 5 | + 0x1 << 1 | + 0x1)); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_CMD_START); + DELAY(20); + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1); + } + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ +static void bwn_nphy_rssi_select(struct bwn_mac *mac, uint8_t code, + enum n_rssi_type type) +{ + if (mac->mac_phy.rev >= 19) + bwn_nphy_rssi_select_rev19(mac, code, type); + else if (mac->mac_phy.rev >= 3) + bwn_nphy_rev3_rssi_select(mac, code, type); + else + bwn_nphy_rev2_rssi_select(mac, code, type); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ +static void bwn_nphy_set_rssi_2055_vcm(struct bwn_mac *mac, + enum n_rssi_type rssi_type, uint8_t *buf) +{ + int i; + for (i = 0; i < 2; i++) { + if (rssi_type == N_RSSI_NB) { + if (i == 0) { + BWN_RF_SETMASK(mac, B2055_C1_B0NB_RSSIVCM, + 0xFC, buf[0]); + BWN_RF_SETMASK(mac, B2055_C1_RX_BB_RSSICTL5, + 0xFC, buf[1]); + } else { + BWN_RF_SETMASK(mac, B2055_C2_B0NB_RSSIVCM, + 0xFC, buf[2 * i]); + BWN_RF_SETMASK(mac, B2055_C2_RX_BB_RSSICTL5, + 0xFC, buf[2 * i + 1]); + } + } else { + if (i == 0) + BWN_RF_SETMASK(mac, B2055_C1_RX_BB_RSSICTL5, + 0xF3, buf[0] << 2); + else + BWN_RF_SETMASK(mac, B2055_C2_RX_BB_RSSICTL5, + 0xF3, buf[2 * i + 1] << 2); + } + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ +static int bwn_nphy_poll_rssi(struct bwn_mac *mac, enum n_rssi_type rssi_type, + int32_t *buf, uint8_t nsamp) +{ + int i; + int out; + uint16_t save_regs_phy[9]; + uint16_t s[2]; + + /* TODO: rev7+ is treated like rev3+, what about rev19+? */ + + if (mac->mac_phy.rev >= 3) { + save_regs_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1); + save_regs_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2); + save_regs_phy[2] = BWN_PHY_READ(mac, + BWN_NPHY_RFCTL_LUT_TRSW_UP1); + save_regs_phy[3] = BWN_PHY_READ(mac, + BWN_NPHY_RFCTL_LUT_TRSW_UP2); + save_regs_phy[4] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1); + save_regs_phy[5] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); + save_regs_phy[6] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B1S0); + save_regs_phy[7] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B32S1); + save_regs_phy[8] = 0; + } else { + save_regs_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1); + save_regs_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2); + save_regs_phy[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); + save_regs_phy[3] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD); + save_regs_phy[4] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_OVER); + save_regs_phy[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO1); + save_regs_phy[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO2); + save_regs_phy[7] = 0; + save_regs_phy[8] = 0; + } + + bwn_nphy_rssi_select(mac, 5, rssi_type); + + if (mac->mac_phy.rev < 2) { + save_regs_phy[8] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_SEL); + BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_SEL, 5); + } + + for (i = 0; i < 4; i++) + buf[i] = 0; + + for (i = 0; i < nsamp; i++) { + if (mac->mac_phy.rev < 2) { + s[0] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_LOOUT); + s[1] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_HIOUT); + } else { + s[0] = BWN_PHY_READ(mac, BWN_NPHY_RSSI1); + s[1] = BWN_PHY_READ(mac, BWN_NPHY_RSSI2); + } + + buf[0] += ((int8_t)((s[0] & 0x3F) << 2)) >> 2; + buf[1] += ((int8_t)(((s[0] >> 8) & 0x3F) << 2)) >> 2; + buf[2] += ((int8_t)((s[1] & 0x3F) << 2)) >> 2; + buf[3] += ((int8_t)(((s[1] >> 8) & 0x3F) << 2)) >> 2; + } + out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | + (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); + + if (mac->mac_phy.rev < 2) + BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_SEL, save_regs_phy[8]); + + if (mac->mac_phy.rev >= 3) { + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, save_regs_phy[0]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, save_regs_phy[1]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, + save_regs_phy[2]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, + save_regs_phy[3]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, save_regs_phy[4]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, save_regs_phy[5]); + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); + } else { + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, save_regs_phy[0]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, save_regs_phy[1]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, save_regs_phy[2]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_CMD, save_regs_phy[3]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, save_regs_phy[4]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); + } + + return out; +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ +static void bwn_nphy_rev3_rssi_cal(struct bwn_mac *mac) +{ + //struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint16_t saved_regs_phy_rfctl[2]; + uint16_t saved_regs_phy[22]; + uint16_t regs_to_store_rev3[] = { + BWN_NPHY_AFECTL_OVER1, BWN_NPHY_AFECTL_OVER, + BWN_NPHY_AFECTL_C1, BWN_NPHY_AFECTL_C2, + BWN_NPHY_TXF_40CO_B1S1, BWN_NPHY_RFCTL_OVER, + BWN_NPHY_TXF_40CO_B1S0, BWN_NPHY_TXF_40CO_B32S1, + BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_LUT_TRSW_UP1, BWN_NPHY_RFCTL_LUT_TRSW_UP2, + BWN_NPHY_RFCTL_RSSIO1, BWN_NPHY_RFCTL_RSSIO2 + }; + uint16_t regs_to_store_rev7[] = { + BWN_NPHY_AFECTL_OVER1, BWN_NPHY_AFECTL_OVER, + BWN_NPHY_AFECTL_C1, BWN_NPHY_AFECTL_C2, + BWN_NPHY_TXF_40CO_B1S1, BWN_NPHY_RFCTL_OVER, + BWN_NPHY_REV7_RF_CTL_OVER3, BWN_NPHY_REV7_RF_CTL_OVER4, + BWN_NPHY_REV7_RF_CTL_OVER5, BWN_NPHY_REV7_RF_CTL_OVER6, + 0x2ff, + BWN_NPHY_TXF_40CO_B1S0, BWN_NPHY_TXF_40CO_B32S1, + BWN_NPHY_RFCTL_CMD, + BWN_NPHY_RFCTL_LUT_TRSW_UP1, BWN_NPHY_RFCTL_LUT_TRSW_UP2, + BWN_NPHY_REV7_RF_CTL_MISC_REG3, BWN_NPHY_REV7_RF_CTL_MISC_REG4, + BWN_NPHY_REV7_RF_CTL_MISC_REG5, BWN_NPHY_REV7_RF_CTL_MISC_REG6, + BWN_NPHY_RFCTL_RSSIO1, BWN_NPHY_RFCTL_RSSIO2 + }; + uint16_t *regs_to_store; + int regs_amount; + + uint16_t class; + + uint16_t clip_state[2]; + uint16_t clip_off[2] = { 0xFFFF, 0xFFFF }; + + uint8_t vcm_final = 0; + int32_t offset[4]; + int32_t results[8][4] = { }; + int32_t results_min[4] = { }; + int32_t poll_results[4] = { }; + + uint16_t *rssical_radio_regs = NULL; + uint16_t *rssical_phy_regs = NULL; + + uint16_t r; /* routing */ + uint8_t rx_core_state; + int core, i, j, vcm; + + if (mac->mac_phy.rev >= 7) { + regs_to_store = regs_to_store_rev7; + regs_amount = nitems(regs_to_store_rev7); + } else { + regs_to_store = regs_to_store_rev3; + regs_amount = nitems(regs_to_store_rev3); + } + KASSERT((regs_amount <= nitems(saved_regs_phy)), + ("%s: reg_amount (%d) too large\n", + __func__, + regs_amount)); + + class = bwn_nphy_classifier(mac, 0, 0); + bwn_nphy_classifier(mac, 7, 4); + bwn_nphy_read_clip_detection(mac, clip_state); + bwn_nphy_write_clip_detection(mac, clip_off); + + saved_regs_phy_rfctl[0] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); + saved_regs_phy_rfctl[1] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); + for (i = 0; i < regs_amount; i++) + saved_regs_phy[i] = BWN_PHY_READ(mac, regs_to_store[i]); + + bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_OFF, 0, 7); + bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 1, 7); + + if (mac->mac_phy.rev >= 7) { + bwn_nphy_rf_ctl_override_one_to_many(mac, + N_RF_CTL_OVER_CMD_RXRF_PU, + 0, 0, false); + bwn_nphy_rf_ctl_override_one_to_many(mac, + N_RF_CTL_OVER_CMD_RX_PU, + 1, 0, false); + bwn_nphy_rf_ctl_override_rev7(mac, 0x80, 1, 0, false, 0); + bwn_nphy_rf_ctl_override_rev7(mac, 0x40, 1, 0, false, 0); + if (bwn_current_band(mac) == BWN_BAND_5G) { + bwn_nphy_rf_ctl_override_rev7(mac, 0x20, 0, 0, false, + 0); + bwn_nphy_rf_ctl_override_rev7(mac, 0x10, 1, 0, false, + 0); + } else { + bwn_nphy_rf_ctl_override_rev7(mac, 0x10, 0, 0, false, + 0); + bwn_nphy_rf_ctl_override_rev7(mac, 0x20, 1, 0, false, + 0); + } + } else { + bwn_nphy_rf_ctl_override(mac, 0x1, 0, 0, false); + bwn_nphy_rf_ctl_override(mac, 0x2, 1, 0, false); + bwn_nphy_rf_ctl_override(mac, 0x80, 1, 0, false); + bwn_nphy_rf_ctl_override(mac, 0x40, 1, 0, false); + if (bwn_current_band(mac) == BWN_BAND_5G) { + bwn_nphy_rf_ctl_override(mac, 0x20, 0, 0, false); + bwn_nphy_rf_ctl_override(mac, 0x10, 1, 0, false); + } else { + bwn_nphy_rf_ctl_override(mac, 0x10, 0, 0, false); + bwn_nphy_rf_ctl_override(mac, 0x20, 1, 0, false); + } + } + + rx_core_state = bwn_nphy_get_rx_core_state(mac); + for (core = 0; core < 2; core++) { + if (!(rx_core_state & (1 << core))) + continue; + r = core ? B2056_RX1 : B2056_RX0; + bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_I, + N_RSSI_NB); + bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_Q, + N_RSSI_NB); + + /* Grab RSSI results for every possible VCM */ + for (vcm = 0; vcm < 8; vcm++) { + if (mac->mac_phy.rev >= 7) + BWN_RF_SETMASK(mac, + core ? R2057_NB_MASTER_CORE1 : + R2057_NB_MASTER_CORE0, + ~R2057_VCM_MASK, vcm); + else + BWN_RF_SETMASK(mac, r | B2056_RX_RSSI_MISC, + 0xE3, vcm << 2); + bwn_nphy_poll_rssi(mac, N_RSSI_NB, results[vcm], 8); + } + + /* Find out which VCM got the best results */ + for (i = 0; i < 4; i += 2) { + int32_t currd; + int32_t mind = 0x100000; + int32_t minpoll = 249; + uint8_t minvcm = 0; + if (2 * core != i) + continue; + for (vcm = 0; vcm < 8; vcm++) { + currd = results[vcm][i] * results[vcm][i] + + results[vcm][i + 1] * results[vcm][i]; + if (currd < mind) { + mind = currd; + minvcm = vcm; + } + if (results[vcm][i] < minpoll) + minpoll = results[vcm][i]; + } + vcm_final = minvcm; + results_min[i] = minpoll; + } + + /* Select the best VCM */ + if (mac->mac_phy.rev >= 7) + BWN_RF_SETMASK(mac, + core ? R2057_NB_MASTER_CORE1 : + R2057_NB_MASTER_CORE0, + ~R2057_VCM_MASK, vcm); + else + BWN_RF_SETMASK(mac, r | B2056_RX_RSSI_MISC, + 0xE3, vcm_final << 2); + + for (i = 0; i < 4; i++) { + if (core != i / 2) + continue; + offset[i] = -results[vcm_final][i]; + if (offset[i] < 0) + offset[i] = -((abs(offset[i]) + 4) / 8); + else + offset[i] = (offset[i] + 4) / 8; + if (results_min[i] == 248) + offset[i] = -32; + bwn_nphy_scale_offset_rssi(mac, 0, offset[i], + (i / 2 == 0) ? 1 : 2, + (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q, + N_RSSI_NB); + } + } + + for (core = 0; core < 2; core++) { + if (!(rx_core_state & (1 << core))) + continue; + for (i = 0; i < 2; i++) { + bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, + N_RAIL_I, i); + bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, + N_RAIL_Q, i); + bwn_nphy_poll_rssi(mac, i, poll_results, 8); + for (j = 0; j < 4; j++) { + if (j / 2 == core) { + offset[j] = 232 - poll_results[j]; + if (offset[j] < 0) + offset[j] = -(abs(offset[j] + 4) / 8); + else + offset[j] = (offset[j] + 4) / 8; + bwn_nphy_scale_offset_rssi(mac, 0, + offset[2 * core], core + 1, j % 2, i); + } + } + } + } + + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]); + + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); + + BWN_PHY_SET(mac, BWN_NPHY_TXF_40CO_B1S1, 0x1); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_START); + BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S1, ~0x1); + + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, 0x1); + BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_RXTX); + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1); + + for (i = 0; i < regs_amount; i++) + BWN_PHY_WRITE(mac, regs_to_store[i], saved_regs_phy[i]); + + /* Store for future configuration */ + if (bwn_current_band(mac) == BWN_BAND_2G) { + rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; + rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; + } else { + rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; + rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; + } + if (mac->mac_phy.rev >= 7) { + rssical_radio_regs[0] = BWN_RF_READ(mac, + R2057_NB_MASTER_CORE0); + rssical_radio_regs[1] = BWN_RF_READ(mac, + R2057_NB_MASTER_CORE1); + } else { + rssical_radio_regs[0] = BWN_RF_READ(mac, B2056_RX0 | + B2056_RX_RSSI_MISC); + rssical_radio_regs[1] = BWN_RF_READ(mac, B2056_RX1 | + B2056_RX_RSSI_MISC); + } + rssical_phy_regs[0] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z); + rssical_phy_regs[1] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z); + rssical_phy_regs[2] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z); + rssical_phy_regs[3] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z); + rssical_phy_regs[4] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_X); + rssical_phy_regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X); + rssical_phy_regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_X); + rssical_phy_regs[7] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X); + rssical_phy_regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y); + rssical_phy_regs[9] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y); + rssical_phy_regs[10] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y); + rssical_phy_regs[11] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y); + + /* Remember for which channel we store configuration */ + if (bwn_current_band(mac) == BWN_BAND_2G) + nphy->rssical_chanspec_2G.center_freq = bwn_get_centre_freq(mac); + else + nphy->rssical_chanspec_5G.center_freq = bwn_get_centre_freq(mac); + + /* End of calibration, restore configuration */ + bwn_nphy_classifier(mac, 7, class); + bwn_nphy_write_clip_detection(mac, clip_state); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ +static void bwn_nphy_rev2_rssi_cal(struct bwn_mac *mac, enum n_rssi_type type) +{ + int i, j, vcm; + uint8_t state[4]; + uint8_t code, val; + uint16_t class, override; + uint8_t regs_save_radio[2]; + uint16_t regs_save_phy[2]; + + int32_t offset[4]; + uint8_t core; + uint8_t rail; + + uint16_t clip_state[2]; + uint16_t clip_off[2] = { 0xFFFF, 0xFFFF }; + int32_t results_min[4] = { }; + uint8_t vcm_final[4] = { }; + int32_t results[4][4] = { }; + int32_t miniq[4][2] = { }; + + if (type == N_RSSI_NB) { + code = 0; + val = 6; + } else if (type == N_RSSI_W1 || type == N_RSSI_W2) { + code = 25; + val = 4; + } else { + BWN_ERRPRINTF(mac->mac_sc, "%s: RSSI type %d invalid\n", + __func__, + type); + return; + } + + class = bwn_nphy_classifier(mac, 0, 0); + bwn_nphy_classifier(mac, 7, 4); + bwn_nphy_read_clip_detection(mac, clip_state); + bwn_nphy_write_clip_detection(mac, clip_off); + + if (bwn_current_band(mac) == BWN_BAND_5G) + override = 0x140; + else + override = 0x110; + + regs_save_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); + regs_save_radio[0] = BWN_RF_READ(mac, B2055_C1_PD_RXTX); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, override); + BWN_RF_WRITE(mac, B2055_C1_PD_RXTX, val); + + regs_save_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); + regs_save_radio[1] = BWN_RF_READ(mac, B2055_C2_PD_RXTX); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, override); + BWN_RF_WRITE(mac, B2055_C2_PD_RXTX, val); + + state[0] = BWN_RF_READ(mac, B2055_C1_PD_RSSIMISC) & 0x07; + state[1] = BWN_RF_READ(mac, B2055_C2_PD_RSSIMISC) & 0x07; + BWN_RF_MASK(mac, B2055_C1_PD_RSSIMISC, 0xF8); + BWN_RF_MASK(mac, B2055_C2_PD_RSSIMISC, 0xF8); + state[2] = BWN_RF_READ(mac, B2055_C1_SP_RSSI) & 0x07; + state[3] = BWN_RF_READ(mac, B2055_C2_SP_RSSI) & 0x07; + + bwn_nphy_rssi_select(mac, 5, type); + bwn_nphy_scale_offset_rssi(mac, 0, 0, 5, N_RAIL_I, type); + bwn_nphy_scale_offset_rssi(mac, 0, 0, 5, N_RAIL_Q, type); + + for (vcm = 0; vcm < 4; vcm++) { + uint8_t tmp[4]; + for (j = 0; j < 4; j++) + tmp[j] = vcm; + if (type != N_RSSI_W2) + bwn_nphy_set_rssi_2055_vcm(mac, type, tmp); + bwn_nphy_poll_rssi(mac, type, results[vcm], 8); + if (type == N_RSSI_W1 || type == N_RSSI_W2) + for (j = 0; j < 2; j++) + miniq[vcm][j] = min(results[vcm][2 * j], + results[vcm][2 * j + 1]); + } + + for (i = 0; i < 4; i++) { + int32_t mind = 0x100000; + uint8_t minvcm = 0; + int32_t minpoll = 249; + int32_t currd; + for (vcm = 0; vcm < 4; vcm++) { + if (type == N_RSSI_NB) + currd = abs(results[vcm][i] - code * 8); + else + currd = abs(miniq[vcm][i / 2] - code * 8); + + if (currd < mind) { + mind = currd; + minvcm = vcm; + } + + if (results[vcm][i] < minpoll) + minpoll = results[vcm][i]; + } + results_min[i] = minpoll; + vcm_final[i] = minvcm; + } + + if (type != N_RSSI_W2) + bwn_nphy_set_rssi_2055_vcm(mac, type, vcm_final); + + for (i = 0; i < 4; i++) { + offset[i] = (code * 8) - results[vcm_final[i]][i]; + + if (offset[i] < 0) + offset[i] = -((abs(offset[i]) + 4) / 8); + else + offset[i] = (offset[i] + 4) / 8; + + if (results_min[i] == 248) + offset[i] = code - 32; + + core = (i / 2) ? 2 : 1; + rail = (i % 2) ? N_RAIL_Q : N_RAIL_I; + + bwn_nphy_scale_offset_rssi(mac, 0, offset[i], core, rail, + type); + } + + BWN_RF_SETMASK(mac, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); + BWN_RF_SETMASK(mac, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); + + switch (state[2]) { + case 1: + bwn_nphy_rssi_select(mac, 1, N_RSSI_NB); + break; + case 4: + bwn_nphy_rssi_select(mac, 1, N_RSSI_W1); + break; + case 2: + bwn_nphy_rssi_select(mac, 1, N_RSSI_W2); + break; + default: + bwn_nphy_rssi_select(mac, 1, N_RSSI_W2); + break; + } + + switch (state[3]) { + case 1: + bwn_nphy_rssi_select(mac, 2, N_RSSI_NB); + break; + case 4: + bwn_nphy_rssi_select(mac, 2, N_RSSI_W1); + break; + default: + bwn_nphy_rssi_select(mac, 2, N_RSSI_W2); + break; + } + + bwn_nphy_rssi_select(mac, 0, type); + + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs_save_phy[0]); + BWN_RF_WRITE(mac, B2055_C1_PD_RXTX, regs_save_radio[0]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs_save_phy[1]); + BWN_RF_WRITE(mac, B2055_C2_PD_RXTX, regs_save_radio[1]); + + bwn_nphy_classifier(mac, 7, class); + bwn_nphy_write_clip_detection(mac, clip_state); + /* Specs don't say about reset here, but it makes wl and b43 dumps + identical, it really seems wl performs this */ + bwn_nphy_reset_cca(mac); +} + +/* + * RSSI Calibration + * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal + */ +static void bwn_nphy_rssi_cal(struct bwn_mac *mac) +{ + if (mac->mac_phy.rev >= 19) { + /* TODO */ + } else if (mac->mac_phy.rev >= 3) { + bwn_nphy_rev3_rssi_cal(mac); + } else { + bwn_nphy_rev2_rssi_cal(mac, N_RSSI_NB); + bwn_nphy_rev2_rssi_cal(mac, N_RSSI_W1); + bwn_nphy_rev2_rssi_cal(mac, N_RSSI_W2); + } +} + +/************************************************** + * Workarounds + **************************************************/ + +static void bwn_nphy_gain_ctl_workarounds_rev19(struct bwn_mac *mac) +{ + /* TODO */ +} + +static void bwn_nphy_gain_ctl_workarounds_rev7(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + + switch (phy->rev) { + /* TODO */ + } +} + +static void bwn_nphy_gain_ctl_workarounds_rev3(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + bool ghz5; + bool ext_lna; + uint16_t rssi_gain; + struct bwn_nphy_gain_ctl_workaround_entry *e; + uint8_t lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; + uint8_t lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; + + /* Prepare values */ + ghz5 = BWN_PHY_READ(mac, BWN_NPHY_BANDCTL) + & BWN_NPHY_BANDCTL_5GHZ; + ext_lna = ghz5 ? siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_EXTLNA_5GHZ : + siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA; + e = bwn_nphy_get_gain_ctl_workaround_ent(mac, ghz5, ext_lna); + if (ghz5 && mac->mac_phy.rev >= 5) + rssi_gain = 0x90; + else + rssi_gain = 0x50; + + BWN_PHY_SET(mac, BWN_NPHY_RXCTL, 0x0040); + + /* Set Clip 2 detect */ + BWN_PHY_SET(mac, BWN_NPHY_C1_CGAINI, BWN_NPHY_C1_CGAINI_CL2DETECT); + BWN_PHY_SET(mac, BWN_NPHY_C2_CGAINI, BWN_NPHY_C2_CGAINI_CL2DETECT); + + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, + 0x17); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC, + 0x17); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_RSSI_GAIN, + rssi_gain); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_RSSI_GAIN, + rssi_gain); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC, + 0x17); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC, + 0x17); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF); + + bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 8), 4, e->lna1_gain); + bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 8), 4, e->lna1_gain); + bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 16), 4, e->lna2_gain); + bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 16), 4, e->lna2_gain); + bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 32), 10, e->gain_db); + bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 32), 10, e->gain_db); + bwn_ntab_write_bulk(mac, BWN_NTAB8(2, 32), 10, e->gain_bits); + bwn_ntab_write_bulk(mac, BWN_NTAB8(3, 32), 10, e->gain_bits); + bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 0x40), 6, lpf_gain); + bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 0x40), 6, lpf_gain); + bwn_ntab_write_bulk(mac, BWN_NTAB8(2, 0x40), 6, lpf_bits); + bwn_ntab_write_bulk(mac, BWN_NTAB8(3, 0x40), 6, lpf_bits); + + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_INITGAIN_A, e->init_gain); + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_INITGAIN_A, e->init_gain); + + bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x106), 2, + e->rfseq_init); + + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain); + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain); + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain); + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain); + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain); + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain); + + BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin); + BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl); + BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu); + BWN_PHY_WRITE(mac, BWN_NPHY_C1_NBCLIPTHRES, e->nbclip); + BWN_PHY_WRITE(mac, BWN_NPHY_C2_NBCLIPTHRES, e->nbclip); + BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CLIPWBTHRES, + ~BWN_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip); + BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CLIPWBTHRES, + ~BWN_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip); + BWN_PHY_WRITE(mac, BWN_NPHY_CCK_SHIFTB_REF, 0x809C); +} + +static void bwn_nphy_gain_ctl_workarounds_rev1_2(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint8_t i, j; + uint8_t code; + uint16_t tmp; + uint8_t rfseq_events[3] = { 6, 8, 7 }; + uint8_t rfseq_delays[3] = { 10, 30, 1 }; + + /* Set Clip 2 detect */ + BWN_PHY_SET(mac, BWN_NPHY_C1_CGAINI, BWN_NPHY_C1_CGAINI_CL2DETECT); + BWN_PHY_SET(mac, BWN_NPHY_C2_CGAINI, BWN_NPHY_C2_CGAINI_CL2DETECT); + + /* Set narrowband clip threshold */ + BWN_PHY_WRITE(mac, BWN_NPHY_C1_NBCLIPTHRES, 0x84); + BWN_PHY_WRITE(mac, BWN_NPHY_C2_NBCLIPTHRES, 0x84); + + if (!bwn_is_40mhz(mac)) { + /* Set dwell lengths */ + BWN_PHY_WRITE(mac, BWN_NPHY_CLIP1_NBDWELL_LEN, 0x002B); + BWN_PHY_WRITE(mac, BWN_NPHY_CLIP2_NBDWELL_LEN, 0x002B); + BWN_PHY_WRITE(mac, BWN_NPHY_W1CLIP1_DWELL_LEN, 0x0009); + BWN_PHY_WRITE(mac, BWN_NPHY_W1CLIP2_DWELL_LEN, 0x0009); + } + + /* Set wideband clip 2 threshold */ + BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CLIPWBTHRES, + ~BWN_NPHY_C1_CLIPWBTHRES_CLIP2, 21); + BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CLIPWBTHRES, + ~BWN_NPHY_C2_CLIPWBTHRES_CLIP2, 21); + + if (!bwn_is_40mhz(mac)) { + BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CGAINI, + ~BWN_NPHY_C1_CGAINI_GAINBKOFF, 0x1); + BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CGAINI, + ~BWN_NPHY_C2_CGAINI_GAINBKOFF, 0x1); + BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CCK_CGAINI, + ~BWN_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); + BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CCK_CGAINI, + ~BWN_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); + } + + BWN_PHY_WRITE(mac, BWN_NPHY_CCK_SHIFTB_REF, 0x809C); + + if (nphy->gain_boost) { + if (bwn_current_band(mac) == BWN_BAND_2G && + bwn_is_40mhz(mac)) + code = 4; + else + code = 5; + } else { + code = bwn_is_40mhz(mac) ? 6 : 7; + } + + /* Set HPVGA2 index */ + BWN_PHY_SETMASK(mac, BWN_NPHY_C1_INITGAIN, ~BWN_NPHY_C1_INITGAIN_HPVGA2, + code << BWN_NPHY_C1_INITGAIN_HPVGA2_SHIFT); + BWN_PHY_SETMASK(mac, BWN_NPHY_C2_INITGAIN, ~BWN_NPHY_C2_INITGAIN_HPVGA2, + code << BWN_NPHY_C2_INITGAIN_HPVGA2_SHIFT); + + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x1D06); + /* specs say about 2 loops, but wl does 4 */ + for (i = 0; i < 4; i++) + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); + + bwn_nphy_adjust_lna_gain_table(mac); + + if (nphy->elna_gain_config) { + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x0808); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x0); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); + + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x0C08); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x0); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); + + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x1D06); + /* specs say about 2 loops, but wl does 4 */ + for (i = 0; i < 4; i++) + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, + (code << 8 | 0x74)); + } + + if (mac->mac_phy.rev == 2) { + for (i = 0; i < 4; i++) { + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, + (0x0400 * i) + 0x0020); + for (j = 0; j < 21; j++) { + tmp = j * (i < 2 ? 3 : 1); + BWN_PHY_WRITE(mac, + BWN_NPHY_TABLE_DATALO, tmp); + } + } + } + + bwn_nphy_set_rf_sequence(mac, 5, rfseq_events, rfseq_delays, 3); + BWN_PHY_SETMASK(mac, BWN_NPHY_OVER_DGAIN1, + ~BWN_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF, + 0x5A << BWN_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); + + if (bwn_current_band(mac) == BWN_BAND_2G) + BWN_PHY_SETMASK(mac, BWN_PHY_N(0xC5D), 0xFF80, 4); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ +static void bwn_nphy_gain_ctl_workarounds(struct bwn_mac *mac) +{ + if (mac->mac_phy.rev >= 19) + bwn_nphy_gain_ctl_workarounds_rev19(mac); + else if (mac->mac_phy.rev >= 7) + bwn_nphy_gain_ctl_workarounds_rev7(mac); + else if (mac->mac_phy.rev >= 3) + bwn_nphy_gain_ctl_workarounds_rev3(mac); + else + bwn_nphy_gain_ctl_workarounds_rev1_2(mac); +} + +static void bwn_nphy_workarounds_rev7plus(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy *phy = &mac->mac_phy; + + /* TX to RX */ + uint8_t tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, }; + uint8_t tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, }; + /* RX to TX */ + uint8_t rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, + 0x1F }; + uint8_t rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; + + static const uint16_t ntab7_15e_16e[] = { 0, 0x10f, 0x10f }; + uint8_t ntab7_138_146[] = { 0x11, 0x11 }; + uint8_t ntab7_133[] = { 0x77, 0x11, 0x11 }; + + uint16_t lpf_ofdm_20mhz[2], lpf_ofdm_40mhz[2], lpf_11b[2]; + uint16_t bcap_val; + int16_t bcap_val_11b[2], bcap_val_11n_20[2], bcap_val_11n_40[2]; + uint16_t scap_val; + int16_t scap_val_11b[2], scap_val_11n_20[2], scap_val_11n_40[2]; + bool rccal_ovrd = false; + + uint16_t bias, conv, filt; + + uint32_t noise_tbl[2]; + + uint32_t tmp32; + uint8_t core; + + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x0125); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x01b3); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x0105); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x016e); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0x00cd); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x0020); + + if (phy->rev == 7) { + BWN_PHY_SET(mac, BWN_NPHY_FINERX2_CGC, 0x10); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN0, 0xFF80, 0x0020); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN0, 0x80FF, 0x2700); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN1, 0xFF80, 0x002E); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN1, 0x80FF, 0x3300); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN2, 0xFF80, 0x0037); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN2, 0x80FF, 0x3A00); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN3, 0xFF80, 0x003C); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN3, 0x80FF, 0x3E00); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN4, 0xFF80, 0x003E); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN4, 0x80FF, 0x3F00); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN5, 0xFF80, 0x0040); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN5, 0x80FF, 0x4000); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN6, 0xFF80, 0x0040); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN6, 0x80FF, 0x4000); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN7, 0xFF80, 0x0040); + BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN7, 0x80FF, 0x4000); + } + + if (phy->rev >= 16) { + BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x7ff); + BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x7ff); + } else if (phy->rev <= 8) { + BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x1B0); + BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x1B0); + } + + if (phy->rev >= 16) + BWN_PHY_SETMASK(mac, BWN_NPHY_TXTAILCNT, ~0xFF, 0xa0); + else if (phy->rev >= 8) + BWN_PHY_SETMASK(mac, BWN_NPHY_TXTAILCNT, ~0xFF, 0x72); + + bwn_ntab_write(mac, BWN_NTAB16(8, 0x00), 2); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x10), 2); + tmp32 = bwn_ntab_read(mac, BWN_NTAB32(30, 0)); + tmp32 &= 0xffffff; + bwn_ntab_write(mac, BWN_NTAB32(30, 0), tmp32); + bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x15d), 3, ntab7_15e_16e); + bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x16d), 3, ntab7_15e_16e); + + bwn_nphy_set_rf_sequence(mac, 1, tx2rx_events, tx2rx_delays, + nitems(tx2rx_events)); + if (bwn_nphy_ipa(mac)) + bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events_ipa, + rx2tx_delays_ipa, nitems(rx2tx_events_ipa)); + + BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); + BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); + + for (core = 0; core < 2; core++) { + lpf_ofdm_20mhz[core] = bwn_nphy_read_lpf_ctl(mac, 0x154 + core * 0x10); + lpf_ofdm_40mhz[core] = bwn_nphy_read_lpf_ctl(mac, 0x159 + core * 0x10); + lpf_11b[core] = bwn_nphy_read_lpf_ctl(mac, 0x152 + core * 0x10); + } + + bcap_val = BWN_RF_READ(mac, R2057_RCCAL_BCAP_VAL); + scap_val = BWN_RF_READ(mac, R2057_RCCAL_SCAP_VAL); + + if (bwn_nphy_ipa(mac)) { + bool ghz2 = bwn_current_band(mac) == BWN_BAND_2G; + + switch (phy->rf_rev) { + case 5: + /* Check radio version (to be 0) by PHY rev for now */ + if (phy->rev == 8 && bwn_is_40mhz(mac)) { + for (core = 0; core < 2; core++) { + scap_val_11b[core] = scap_val; + bcap_val_11b[core] = bcap_val; + scap_val_11n_20[core] = scap_val; + bcap_val_11n_20[core] = bcap_val; + scap_val_11n_40[core] = 0xc; + bcap_val_11n_40[core] = 0xc; + } + + rccal_ovrd = true; + } + if (phy->rev == 9) { + /* TODO: Radio version 1 (e.g. BCM5357B0) */ + } + break; + case 7: + case 8: + for (core = 0; core < 2; core++) { + scap_val_11b[core] = scap_val; + bcap_val_11b[core] = bcap_val; + lpf_ofdm_20mhz[core] = 4; + lpf_11b[core] = 1; + if (bwn_current_band(mac) == BWN_BAND_2G) { + scap_val_11n_20[core] = 0xc; + bcap_val_11n_20[core] = 0xc; + scap_val_11n_40[core] = 0xa; + bcap_val_11n_40[core] = 0xa; + } else { + scap_val_11n_20[core] = 0x14; + bcap_val_11n_20[core] = 0x14; + scap_val_11n_40[core] = 0xf; + bcap_val_11n_40[core] = 0xf; + } + } + + rccal_ovrd = true; + break; + case 9: + for (core = 0; core < 2; core++) { + bcap_val_11b[core] = bcap_val; + scap_val_11b[core] = scap_val; + lpf_11b[core] = 1; + + if (ghz2) { + bcap_val_11n_20[core] = bcap_val + 13; + scap_val_11n_20[core] = scap_val + 15; + } else { + bcap_val_11n_20[core] = bcap_val + 14; + scap_val_11n_20[core] = scap_val + 15; + } + lpf_ofdm_20mhz[core] = 4; + + if (ghz2) { + bcap_val_11n_40[core] = bcap_val - 7; + scap_val_11n_40[core] = scap_val - 5; + } else { + bcap_val_11n_40[core] = bcap_val + 2; + scap_val_11n_40[core] = scap_val + 4; + } + lpf_ofdm_40mhz[core] = 4; + } + + rccal_ovrd = true; + break; + case 14: + for (core = 0; core < 2; core++) { + bcap_val_11b[core] = bcap_val; + scap_val_11b[core] = scap_val; + lpf_11b[core] = 1; + } + + bcap_val_11n_20[0] = bcap_val + 20; + scap_val_11n_20[0] = scap_val + 20; + lpf_ofdm_20mhz[0] = 3; + + bcap_val_11n_20[1] = bcap_val + 16; + scap_val_11n_20[1] = scap_val + 16; + lpf_ofdm_20mhz[1] = 3; + + bcap_val_11n_40[0] = bcap_val + 20; + scap_val_11n_40[0] = scap_val + 20; + lpf_ofdm_40mhz[0] = 4; + + bcap_val_11n_40[1] = bcap_val + 10; + scap_val_11n_40[1] = scap_val + 10; + lpf_ofdm_40mhz[1] = 4; + + rccal_ovrd = true; + break; + } + } else { + if (phy->rf_rev == 5) { + for (core = 0; core < 2; core++) { + lpf_ofdm_20mhz[core] = 1; + lpf_ofdm_40mhz[core] = 3; + scap_val_11b[core] = scap_val; + bcap_val_11b[core] = bcap_val; + scap_val_11n_20[core] = 0x11; + scap_val_11n_40[core] = 0x11; + bcap_val_11n_20[core] = 0x13; + bcap_val_11n_40[core] = 0x13; + } + + rccal_ovrd = true; + } + } + if (rccal_ovrd) { + uint16_t rx2tx_lut_20_11b[2], rx2tx_lut_20_11n[2], rx2tx_lut_40_11n[2]; + uint8_t rx2tx_lut_extra = 1; + + for (core = 0; core < 2; core++) { + bcap_val_11b[core] = bwn_clamp_val(bcap_val_11b[core], 0, 0x1f); + scap_val_11b[core] = bwn_clamp_val(scap_val_11b[core], 0, 0x1f); + bcap_val_11n_20[core] = bwn_clamp_val(bcap_val_11n_20[core], 0, 0x1f); + scap_val_11n_20[core] = bwn_clamp_val(scap_val_11n_20[core], 0, 0x1f); + bcap_val_11n_40[core] = bwn_clamp_val(bcap_val_11n_40[core], 0, 0x1f); + scap_val_11n_40[core] = bwn_clamp_val(scap_val_11n_40[core], 0, 0x1f); + + rx2tx_lut_20_11b[core] = (rx2tx_lut_extra << 13) | + (bcap_val_11b[core] << 8) | + (scap_val_11b[core] << 3) | + lpf_11b[core]; + rx2tx_lut_20_11n[core] = (rx2tx_lut_extra << 13) | + (bcap_val_11n_20[core] << 8) | + (scap_val_11n_20[core] << 3) | + lpf_ofdm_20mhz[core]; + rx2tx_lut_40_11n[core] = (rx2tx_lut_extra << 13) | + (bcap_val_11n_40[core] << 8) | + (scap_val_11n_40[core] << 3) | + lpf_ofdm_40mhz[core]; + } + + for (core = 0; core < 2; core++) { + bwn_ntab_write(mac, BWN_NTAB16(7, 0x152 + core * 16), + rx2tx_lut_20_11b[core]); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x153 + core * 16), + rx2tx_lut_20_11n[core]); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x154 + core * 16), + rx2tx_lut_20_11n[core]); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x155 + core * 16), + rx2tx_lut_40_11n[core]); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x156 + core * 16), + rx2tx_lut_40_11n[core]); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x157 + core * 16), + rx2tx_lut_40_11n[core]); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x158 + core * 16), + rx2tx_lut_40_11n[core]); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x159 + core * 16), + rx2tx_lut_40_11n[core]); + } + } + + BWN_PHY_WRITE(mac, 0x32F, 0x3); + + if (phy->rf_rev == 4 || phy->rf_rev == 6) + bwn_nphy_rf_ctl_override_rev7(mac, 4, 1, 3, false, 0); + + if (phy->rf_rev == 3 || phy->rf_rev == 4 || phy->rf_rev == 6) { + if (siba_sprom_get_rev(sc->sc_dev) && + siba_sprom_get_bf2_hi(sc->sc_dev) & BWN_BFH2_IPALVLSHIFT_3P3) { + BWN_RF_WRITE(mac, 0x5, 0x05); + BWN_RF_WRITE(mac, 0x6, 0x30); + BWN_RF_WRITE(mac, 0x7, 0x00); + BWN_RF_SET(mac, 0x4f, 0x1); + BWN_RF_SET(mac, 0xd4, 0x1); + bias = 0x1f; + conv = 0x6f; + filt = 0xaa; + } else { + bias = 0x2b; + conv = 0x7f; + filt = 0xee; + } + if (bwn_current_band(mac) == BWN_BAND_2G) { + for (core = 0; core < 2; core++) { + if (core == 0) { + BWN_RF_WRITE(mac, 0x5F, bias); + BWN_RF_WRITE(mac, 0x64, conv); + BWN_RF_WRITE(mac, 0x66, filt); + } else { + BWN_RF_WRITE(mac, 0xE8, bias); + BWN_RF_WRITE(mac, 0xE9, conv); + BWN_RF_WRITE(mac, 0xEB, filt); + } + } + } + } + + if (bwn_nphy_ipa(mac)) { + if (bwn_current_band(mac) == BWN_BAND_2G) { + if (phy->rf_rev == 3 || phy->rf_rev == 4 || + phy->rf_rev == 6) { + for (core = 0; core < 2; core++) { + if (core == 0) + BWN_RF_WRITE(mac, 0x51, + 0x7f); + else + BWN_RF_WRITE(mac, 0xd6, + 0x7f); + } + } + switch (phy->rf_rev) { + case 3: + for (core = 0; core < 2; core++) { + if (core == 0) { + BWN_RF_WRITE(mac, 0x64, + 0x13); + BWN_RF_WRITE(mac, 0x5F, + 0x1F); + BWN_RF_WRITE(mac, 0x66, + 0xEE); + BWN_RF_WRITE(mac, 0x59, + 0x8A); + BWN_RF_WRITE(mac, 0x80, + 0x3E); + } else { + BWN_RF_WRITE(mac, 0x69, + 0x13); + BWN_RF_WRITE(mac, 0xE8, + 0x1F); + BWN_RF_WRITE(mac, 0xEB, + 0xEE); + BWN_RF_WRITE(mac, 0xDE, + 0x8A); + BWN_RF_WRITE(mac, 0x105, + 0x3E); + } + } + break; + case 7: + case 8: + if (!bwn_is_40mhz(mac)) { + BWN_RF_WRITE(mac, 0x5F, 0x14); + BWN_RF_WRITE(mac, 0xE8, 0x12); + } else { + BWN_RF_WRITE(mac, 0x5F, 0x16); + BWN_RF_WRITE(mac, 0xE8, 0x16); + } + break; + case 14: + for (core = 0; core < 2; core++) { + int o = core ? 0x85 : 0; + + BWN_RF_WRITE(mac, o + R2057_IPA2G_CASCONV_CORE0, 0x13); + BWN_RF_WRITE(mac, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21); + BWN_RF_WRITE(mac, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff); + BWN_RF_WRITE(mac, o + R2057_PAD2G_IDACS_CORE0, 0x88); + BWN_RF_WRITE(mac, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23); + BWN_RF_WRITE(mac, o + R2057_IPA2G_IMAIN_CORE0, 0x16); + BWN_RF_WRITE(mac, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e); + BWN_RF_WRITE(mac, o + R2057_BACKUP1_CORE0, 0x10); + } + break; + } + } else { + uint16_t freq = bwn_get_centre_freq(mac); + if ((freq >= 5180 && freq <= 5230) || + (freq >= 5745 && freq <= 5805)) { + BWN_RF_WRITE(mac, 0x7D, 0xFF); + BWN_RF_WRITE(mac, 0xFE, 0xFF); + } + } + } else { + if (phy->rf_rev != 5) { + for (core = 0; core < 2; core++) { + if (core == 0) { + BWN_RF_WRITE(mac, 0x5c, 0x61); + BWN_RF_WRITE(mac, 0x51, 0x70); + } else { + BWN_RF_WRITE(mac, 0xe1, 0x61); + BWN_RF_WRITE(mac, 0xd6, 0x70); + } + } + } + } + + if (phy->rf_rev == 4) { + bwn_ntab_write(mac, BWN_NTAB16(8, 0x05), 0x20); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x15), 0x20); + for (core = 0; core < 2; core++) { + if (core == 0) { + BWN_RF_WRITE(mac, 0x1a1, 0x00); + BWN_RF_WRITE(mac, 0x1a2, 0x3f); + BWN_RF_WRITE(mac, 0x1a6, 0x3f); + } else { + BWN_RF_WRITE(mac, 0x1a7, 0x00); + BWN_RF_WRITE(mac, 0x1ab, 0x3f); + BWN_RF_WRITE(mac, 0x1ac, 0x3f); + } + } + } else { + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_C1, 0x4); + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x4); + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_C2, 0x4); + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4); + + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x1); + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x1); + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x1); + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x1); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x05), 0); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x15), 0); + + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x4); + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, ~0x4); + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x4); + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x4); + } + + BWN_PHY_WRITE(mac, BWN_NPHY_ENDROP_TLEN, 0x2); + + bwn_ntab_write(mac, BWN_NTAB32(16, 0x100), 20); + bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x138), 2, ntab7_138_146); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x141), 0x77); + bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x133), 3, ntab7_133); + bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x146), 2, ntab7_138_146); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x123), 0x77); + bwn_ntab_write(mac, BWN_NTAB16(7, 0x12A), 0x77); + + bwn_ntab_read_bulk(mac, BWN_NTAB32(16, 0x02), 1, noise_tbl); + noise_tbl[1] = bwn_is_40mhz(mac) ? 0x14D : 0x18D; + bwn_ntab_write_bulk(mac, BWN_NTAB32(16, 0x02), 2, noise_tbl); + + bwn_ntab_read_bulk(mac, BWN_NTAB32(16, 0x7E), 1, noise_tbl); + noise_tbl[1] = bwn_is_40mhz(mac) ? 0x14D : 0x18D; + bwn_ntab_write_bulk(mac, BWN_NTAB32(16, 0x7E), 2, noise_tbl); + + bwn_nphy_gain_ctl_workarounds(mac); + + /* TODO + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, + aux_adc_vmid_rev7_core0); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, + aux_adc_vmid_rev7_core1); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0C), 4, + aux_adc_gain_rev7); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1C), 4, + aux_adc_gain_rev7); + */ +} + +static void bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + /* TX to RX */ + uint8_t tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F }; + uint8_t tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 }; + /* RX to TX */ + uint8_t rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, + 0x1F }; + uint8_t rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; + uint8_t rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F }; + uint8_t rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 }; + + uint16_t vmids[5][4] = { + { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */ + { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */ + { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */ + { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */ + { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */ + }; + uint16_t gains[5][4] = { + { 0x02, 0x02, 0x02, 0x00, }, /* 0 */ + { 0x02, 0x02, 0x02, 0x02, }, /* 1 */ + { 0x02, 0x02, 0x02, 0x04, }, /* 2 */ + { 0x02, 0x02, 0x02, 0x00, }, /* 3 */ + { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */ + }; + uint16_t *vmid, *gain; + + uint8_t pdet_range; + uint16_t tmp16; + uint32_t tmp32; + + BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x1f8); + BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x1f8); + + tmp32 = bwn_ntab_read(mac, BWN_NTAB32(30, 0)); + tmp32 &= 0xffffff; + bwn_ntab_write(mac, BWN_NTAB32(30, 0), tmp32); + + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x0125); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x01B3); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x0105); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x016E); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0x00CD); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x0020); + + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C); + BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C); + + /* TX to RX */ + bwn_nphy_set_rf_sequence(mac, 1, tx2rx_events, tx2rx_delays, + nitems(tx2rx_events)); + + /* RX to TX */ + if (bwn_nphy_ipa(mac)) + bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events_ipa, + rx2tx_delays_ipa, nitems(rx2tx_events_ipa)); + if (nphy->hw_phyrxchain != 3 && + nphy->hw_phyrxchain != nphy->hw_phytxchain) { + if (bwn_nphy_ipa(mac)) { + rx2tx_delays[5] = 59; + rx2tx_delays[6] = 1; + rx2tx_events[7] = 0x1F; + } + bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events, rx2tx_delays, + nitems(rx2tx_events)); + } + + tmp16 = (bwn_current_band(mac) == BWN_BAND_2G) ? + 0x2 : 0x9C40; + BWN_PHY_WRITE(mac, BWN_NPHY_ENDROP_TLEN, tmp16); + + BWN_PHY_SETMASK(mac, BWN_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); + + if (!bwn_is_40mhz(mac)) { + bwn_ntab_write(mac, BWN_NTAB32(16, 3), 0x18D); + bwn_ntab_write(mac, BWN_NTAB32(16, 127), 0x18D); + } else { + bwn_ntab_write(mac, BWN_NTAB32(16, 3), 0x14D); + bwn_ntab_write(mac, BWN_NTAB32(16, 127), 0x14D); + } + + bwn_nphy_gain_ctl_workarounds(mac); + + bwn_ntab_write(mac, BWN_NTAB16(8, 0), 2); + bwn_ntab_write(mac, BWN_NTAB16(8, 16), 2); + + if (bwn_current_band(mac) == BWN_BAND_2G) + pdet_range = siba_sprom_get_fem_2ghz_pdet_range(sc->sc_dev); + else + pdet_range = siba_sprom_get_fem_5ghz_pdet_range(sc->sc_dev); + /* uint16_t min() */ + vmid = vmids[min(pdet_range, 4)]; + gain = gains[min(pdet_range, 4)]; + switch (pdet_range) { + case 3: + if (!(mac->mac_phy.rev >= 4 && + bwn_current_band(mac) == BWN_BAND_2G)) + break; + /* FALL THROUGH */ + case 0: + case 1: + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain); + break; + case 2: + if (mac->mac_phy.rev >= 6) { + if (bwn_current_band(mac) == BWN_BAND_2G) + vmid[3] = 0x94; + else + vmid[3] = 0x8e; + gain[3] = 3; + } else if (mac->mac_phy.rev == 5) { + vmid[3] = 0x84; + gain[3] = 2; + } + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain); + break; + case 4: + case 5: + if (bwn_current_band(mac) != BWN_BAND_2G) { + if (pdet_range == 4) { + vmid[3] = 0x8e; + tmp16 = 0x96; + gain[3] = 0x2; + } else { + vmid[3] = 0x89; + tmp16 = 0x89; + gain[3] = 0; + } + } else { + if (pdet_range == 4) { + vmid[3] = 0x89; + tmp16 = 0x8b; + gain[3] = 0x2; + } else { + vmid[3] = 0x74; + tmp16 = 0x70; + gain[3] = 0; + } + } + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain); + vmid[3] = tmp16; + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid); + bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain); + break; + } + + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00); + BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); + BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); + + /* N PHY WAR TX Chain Update with hw_phytxchain as argument */ + + if ((siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_APLL_WAR && + bwn_current_band(mac) == BWN_BAND_5G) || + (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_GPLL_WAR && + bwn_current_band(mac) == BWN_BAND_2G)) + tmp32 = 0x00088888; + else + tmp32 = 0x88888888; + bwn_ntab_write(mac, BWN_NTAB32(30, 1), tmp32); + bwn_ntab_write(mac, BWN_NTAB32(30, 2), tmp32); + bwn_ntab_write(mac, BWN_NTAB32(30, 3), tmp32); + + if (mac->mac_phy.rev == 4 && + bwn_current_band(mac) == BWN_BAND_5G) { + BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_GMBB_IDAC, + 0x70); + BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_GMBB_IDAC, + 0x70); + } + + /* Dropped probably-always-true condition */ + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381); + BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381); + + if (mac->mac_phy.rev >= 6 && siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_SINGLEANT_CCK) + ; /* TODO: 0x0080000000000000 HF */ +} + +static void bwn_nphy_workarounds_rev1_2(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = phy->phy_n; + + uint8_t events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; + uint8_t delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; + + uint8_t events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; + uint8_t delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; + + if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_SKWRKFEM_BRD || + siba_get_pci_subdevice(sc->sc_dev)== BCMA_BOARD_TYPE_BCM943224M93) { + delays1[0] = 0x1; + delays1[5] = 0x14; + } + + if (bwn_current_band(mac) == BWN_BAND_5G && + nphy->band5g_pwrgain) { + BWN_RF_MASK(mac, B2055_C1_TX_RF_SPARE, ~0x8); + BWN_RF_MASK(mac, B2055_C2_TX_RF_SPARE, ~0x8); + } else { + BWN_RF_SET(mac, B2055_C1_TX_RF_SPARE, 0x8); + BWN_RF_SET(mac, B2055_C2_TX_RF_SPARE, 0x8); + } + + bwn_ntab_write(mac, BWN_NTAB16(8, 0x00), 0x000A); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x10), 0x000A); + if (mac->mac_phy.rev < 3) { + bwn_ntab_write(mac, BWN_NTAB16(8, 0x02), 0xCDAA); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x12), 0xCDAA); + } + + if (mac->mac_phy.rev < 2) { + bwn_ntab_write(mac, BWN_NTAB16(8, 0x08), 0x0000); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x18), 0x0000); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x07), 0x7AAB); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x17), 0x7AAB); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x06), 0x0800); + bwn_ntab_write(mac, BWN_NTAB16(8, 0x16), 0x0800); + } + + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); + + bwn_nphy_set_rf_sequence(mac, 0, events1, delays1, 7); + bwn_nphy_set_rf_sequence(mac, 1, events2, delays2, 7); + + bwn_nphy_gain_ctl_workarounds(mac); + + if (mac->mac_phy.rev < 2) { + if (BWN_PHY_READ(mac, BWN_NPHY_RXCTL) & 0x2) + bwn_hf_write(mac, bwn_hf_read(mac) | + BWN_HF_MLADVW); + } else if (mac->mac_phy.rev == 2) { + BWN_PHY_WRITE(mac, BWN_NPHY_CRSCHECK2, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_CRSCHECK3, 0); + } + + if (mac->mac_phy.rev < 2) + BWN_PHY_MASK(mac, BWN_NPHY_SCRAM_SIGCTL, + ~BWN_NPHY_SCRAM_SIGCTL_SCM); + + /* Set phase track alpha and beta */ + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x125); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x1B3); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x105); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x16E); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0xCD); + BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x20); + + if (mac->mac_phy.rev < 3) { + BWN_PHY_MASK(mac, BWN_NPHY_PIL_DW1, + ~BWN_NPHY_PIL_DW_64QAM & 0xFFFF); + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B1, 0xB5); + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B2, 0xA4); + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B3, 0x00); + } + + if (mac->mac_phy.rev == 2) + BWN_PHY_SET(mac, BWN_NPHY_FINERX2_CGC, + BWN_NPHY_FINERX2_CGC_DECGC); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ +static void bwn_nphy_workarounds(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = phy->phy_n; + + if (bwn_current_band(mac) == BWN_BAND_5G) + bwn_nphy_classifier(mac, 1, 0); + else + bwn_nphy_classifier(mac, 1, 1); + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 1); + + BWN_PHY_SET(mac, BWN_NPHY_IQFLIP, + BWN_NPHY_IQFLIP_ADC1 | BWN_NPHY_IQFLIP_ADC2); + + /* TODO: rev19+ */ + if (mac->mac_phy.rev >= 7) + bwn_nphy_workarounds_rev7plus(mac); + else if (mac->mac_phy.rev >= 3) + bwn_nphy_workarounds_rev3plus(mac); + else + bwn_nphy_workarounds_rev1_2(mac); + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 0); +} + +/************************************************** + * Tx/Rx common + **************************************************/ + +/* + * Transmits a known value for LO calibration + * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone + */ +static int bwn_nphy_tx_tone(struct bwn_mac *mac, uint32_t freq, uint16_t max_val, + bool iqmode, bool dac_test, bool modify_bbmult) +{ + uint16_t samp = bwn_nphy_gen_load_samples(mac, freq, max_val, dac_test); + if (samp == 0) + return -1; + bwn_nphy_run_samples(mac, samp, 0xFFFF, 0, iqmode, dac_test, + modify_bbmult); + return 0; +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ +static void bwn_nphy_update_txrx_chain(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + bool override = false; + uint16_t chain = 0x33; + + if (nphy->txrx_chain == 0) { + chain = 0x11; + override = true; + } else if (nphy->txrx_chain == 1) { + chain = 0x22; + override = true; + } + + BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, + ~(BWN_NPHY_RFSEQCA_TXEN | BWN_NPHY_RFSEQCA_RXEN), + chain); + + if (override) + BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE, + BWN_NPHY_RFSEQMODE_CAOVER); + else + BWN_PHY_MASK(mac, BWN_NPHY_RFSEQMODE, + ~BWN_NPHY_RFSEQMODE_CAOVER); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ +static void bwn_nphy_stop_playback(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + uint16_t tmp; + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 1); + + tmp = BWN_PHY_READ(mac, BWN_NPHY_SAMP_STAT); + if (tmp & 0x1) + BWN_PHY_SET(mac, BWN_NPHY_SAMP_CMD, BWN_NPHY_SAMP_CMD_STOP); + else if (tmp & 0x2) + BWN_PHY_MASK(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); + + BWN_PHY_MASK(mac, BWN_NPHY_SAMP_CMD, ~0x0004); + + if (nphy->bb_mult_save & 0x80000000) { + tmp = nphy->bb_mult_save & 0xFFFF; + bwn_ntab_write(mac, BWN_NTAB16(15, 87), tmp); + nphy->bb_mult_save = 0; + } + + if (phy->rev >= 7 && nphy->lpf_bw_overrode_for_sample_play) { + if (phy->rev >= 19) + bwn_nphy_rf_ctl_override_rev19(mac, 0x80, 0, 0, true, + 1); + else + bwn_nphy_rf_ctl_override_rev7(mac, 0x80, 0, 0, true, 1); + nphy->lpf_bw_overrode_for_sample_play = false; + } + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 0); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ +static void bwn_nphy_iq_cal_gain_params(struct bwn_mac *mac, uint16_t core, + struct bwn_nphy_txgains target, + struct bwn_nphy_iqcal_params *params) +{ + struct bwn_phy *phy = &mac->mac_phy; + int i, j, indx; + uint16_t gain; + + if (mac->mac_phy.rev >= 3) { + params->tx_lpf = target.tx_lpf[core]; /* Rev 7+ */ + params->txgm = target.txgm[core]; + params->pga = target.pga[core]; + params->pad = target.pad[core]; + params->ipa = target.ipa[core]; + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 7) { + params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15); + } else { + params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa); + } + for (j = 0; j < 5; j++) + params->ncorr[j] = 0x79; + } else { + gain = (target.pad[core]) | (target.pga[core] << 4) | + (target.txgm[core] << 8); + + indx = (bwn_current_band(mac) == BWN_BAND_5G) ? + 1 : 0; + for (i = 0; i < 9; i++) + if (tbl_iqcal_gainparams[indx][i][0] == gain) + break; + i = min(i, 8); + + params->txgm = tbl_iqcal_gainparams[indx][i][1]; + params->pga = tbl_iqcal_gainparams[indx][i][2]; + params->pad = tbl_iqcal_gainparams[indx][i][3]; + params->cal_gain = (params->txgm << 7) | (params->pga << 4) | + (params->pad << 2); + for (j = 0; j < 4; j++) + params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; + } +} + +/************************************************** + * Tx and Rx + **************************************************/ + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */ +static void bwn_nphy_tx_power_ctrl(struct bwn_mac *mac, bool enable) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + uint8_t i; + uint16_t bmask, val, tmp; + bwn_band_t band = bwn_current_band(mac); + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 1); + + nphy->txpwrctrl = enable; + if (!enable) { + if (mac->mac_phy.rev >= 3 && + (BWN_PHY_READ(mac, BWN_NPHY_TXPCTL_CMD) & + (BWN_NPHY_TXPCTL_CMD_COEFF | + BWN_NPHY_TXPCTL_CMD_HWPCTLEN | + BWN_NPHY_TXPCTL_CMD_PCTLEN))) { + /* We disable enabled TX pwr ctl, save it's state */ + nphy->tx_pwr_idx[0] = BWN_PHY_READ(mac, + BWN_NPHY_C1_TXPCTL_STAT) & 0x7f; + nphy->tx_pwr_idx[1] = BWN_PHY_READ(mac, + BWN_NPHY_C2_TXPCTL_STAT) & 0x7f; + } + + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x6840); + for (i = 0; i < 84; i++) + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0); + + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x6C40); + for (i = 0; i < 84; i++) + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0); + + tmp = BWN_NPHY_TXPCTL_CMD_COEFF | BWN_NPHY_TXPCTL_CMD_HWPCTLEN; + if (mac->mac_phy.rev >= 3) + tmp |= BWN_NPHY_TXPCTL_CMD_PCTLEN; + BWN_PHY_MASK(mac, BWN_NPHY_TXPCTL_CMD, ~tmp); + + if (mac->mac_phy.rev >= 3) { + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0100); + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0100); + } else { + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4000); + } + + if (mac->mac_phy.rev == 2) + BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, + ~BWN_NPHY_BPHY_CTL3_SCALE, 0x53); + else if (mac->mac_phy.rev < 2) + BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, + ~BWN_NPHY_BPHY_CTL3_SCALE, 0x5A); + + if (mac->mac_phy.rev < 2 && bwn_is_40mhz(mac)) + bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_TSSI_RESET_PSM_WORKAROUN); + } else { + bwn_ntab_write_bulk(mac, BWN_NTAB16(26, 64), 84, + nphy->adj_pwr_tbl); + bwn_ntab_write_bulk(mac, BWN_NTAB16(27, 64), 84, + nphy->adj_pwr_tbl); + + bmask = BWN_NPHY_TXPCTL_CMD_COEFF | + BWN_NPHY_TXPCTL_CMD_HWPCTLEN; + /* wl does useless check for "enable" param here */ + val = BWN_NPHY_TXPCTL_CMD_COEFF | BWN_NPHY_TXPCTL_CMD_HWPCTLEN; + if (mac->mac_phy.rev >= 3) { + bmask |= BWN_NPHY_TXPCTL_CMD_PCTLEN; + if (val) + val |= BWN_NPHY_TXPCTL_CMD_PCTLEN; + } + BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, ~(bmask), val); + + if (band == BWN_BAND_5G) { + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 7) { + BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, + ~BWN_NPHY_TXPCTL_CMD_INIT, + 0x32); + BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT, + ~BWN_NPHY_TXPCTL_INIT_PIDXI1, + 0x32); + } else { + BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, + ~BWN_NPHY_TXPCTL_CMD_INIT, + 0x64); + if (phy->rev > 1) + BWN_PHY_SETMASK(mac, + BWN_NPHY_TXPCTL_INIT, + ~BWN_NPHY_TXPCTL_INIT_PIDXI1, + 0x64); + } + } + + if (mac->mac_phy.rev >= 3) { + if (nphy->tx_pwr_idx[0] != 128 && + nphy->tx_pwr_idx[1] != 128) { + /* Recover TX pwr ctl state */ + BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, + ~BWN_NPHY_TXPCTL_CMD_INIT, + nphy->tx_pwr_idx[0]); + if (mac->mac_phy.rev > 1) + BWN_PHY_SETMASK(mac, + BWN_NPHY_TXPCTL_INIT, + ~0xff, nphy->tx_pwr_idx[1]); + } + } + + if (phy->rev >= 7) { + /* TODO */ + } + + if (mac->mac_phy.rev >= 3) { + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, ~0x100); + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x100); + } else { + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x4000); + } + + if (mac->mac_phy.rev == 2) + BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~0xFF, 0x3b); + else if (mac->mac_phy.rev < 2) + BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~0xFF, 0x40); + + if (mac->mac_phy.rev < 2 && bwn_is_40mhz(mac)) + bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_TSSI_RESET_PSM_WORKAROUN); + + if (bwn_nphy_ipa(mac)) { + BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x4); + BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x4); + } + } + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 0); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */ +static void bwn_nphy_tx_power_fix(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint8_t txpi[2], bbmult, i; + uint16_t tmp, radio_gain, dac_gain; + uint16_t freq = bwn_get_centre_freq(mac); + uint32_t txgain; + /* uint32_t gaintbl; rev3+ */ + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 1); + + /* TODO: rev19+ */ + if (mac->mac_phy.rev >= 7) { + txpi[0] = txpi[1] = 30; + } else if (mac->mac_phy.rev >= 3) { + txpi[0] = 40; + txpi[1] = 40; + } else if (siba_sprom_get_rev(sc->sc_dev) < 4) { + txpi[0] = 72; + txpi[1] = 72; + } else { + if (bwn_current_band(mac) == BWN_BAND_2G) { + txpi[0] = siba_sprom_get_txpid_2g_0(sc->sc_dev); + txpi[1] = siba_sprom_get_txpid_2g_1(sc->sc_dev); + } else if (freq >= 4900 && freq < 5100) { + txpi[0] = siba_sprom_get_txpid_5gl_0(sc->sc_dev); + txpi[1] = siba_sprom_get_txpid_5gl_1(sc->sc_dev); + } else if (freq >= 5100 && freq < 5500) { + txpi[0] = siba_sprom_get_txpid_5g_0(sc->sc_dev); + txpi[1] = siba_sprom_get_txpid_5g_1(sc->sc_dev); + } else if (freq >= 5500) { + txpi[0] = siba_sprom_get_txpid_5gh_0(sc->sc_dev); + txpi[1] = siba_sprom_get_txpid_5gh_1(sc->sc_dev); + } else { + txpi[0] = 91; + txpi[1] = 91; + } + } + if (mac->mac_phy.rev < 7 && + (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100)) + txpi[0] = txpi[1] = 91; + + /* + for (i = 0; i < 2; i++) { + nphy->txpwrindex[i].index_internal = txpi[i]; + nphy->txpwrindex[i].index_internal_save = txpi[i]; + } + */ + + for (i = 0; i < 2; i++) { + const uint32_t *table = bwn_nphy_get_tx_gain_table(mac); + + if (!table) + break; + txgain = *(table + txpi[i]); + + if (mac->mac_phy.rev >= 3) + radio_gain = (txgain >> 16) & 0x1FFFF; + else + radio_gain = (txgain >> 16) & 0x1FFF; + + if (mac->mac_phy.rev >= 7) + dac_gain = (txgain >> 8) & 0x7; + else + dac_gain = (txgain >> 8) & 0x3F; + bbmult = txgain & 0xFF; + + if (mac->mac_phy.rev >= 3) { + if (i == 0) + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0100); + else + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0100); + } else { + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4000); + } + + if (i == 0) + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_DACGAIN1, dac_gain); + else + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_DACGAIN2, dac_gain); + + bwn_ntab_write(mac, BWN_NTAB16(0x7, 0x110 + i), radio_gain); + + tmp = bwn_ntab_read(mac, BWN_NTAB16(0xF, 0x57)); + if (i == 0) + tmp = (tmp & 0x00FF) | (bbmult << 8); + else + tmp = (tmp & 0xFF00) | bbmult; + bwn_ntab_write(mac, BWN_NTAB16(0xF, 0x57), tmp); + + if (bwn_nphy_ipa(mac)) { + uint32_t tmp32; + uint16_t reg = (i == 0) ? + BWN_NPHY_PAPD_EN0 : BWN_NPHY_PAPD_EN1; + tmp32 = bwn_ntab_read(mac, BWN_NTAB32(26 + i, + 576 + txpi[i])); + BWN_PHY_SETMASK(mac, reg, 0xE00F, (uint32_t) tmp32 << 4); + BWN_PHY_SET(mac, reg, 0x4); + } + } + + BWN_PHY_MASK(mac, BWN_NPHY_BPHY_CTL2, ~BWN_NPHY_BPHY_CTL2_LUT); + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 0); +} + +static void bwn_nphy_ipa_internal_tssi_setup(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + + uint8_t core; + uint16_t r; /* routing */ + + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 7) { + for (core = 0; core < 2; core++) { + r = core ? 0x190 : 0x170; + if (bwn_current_band(mac) == BWN_BAND_2G) { + BWN_RF_WRITE(mac, r + 0x5, 0x5); + BWN_RF_WRITE(mac, r + 0x9, 0xE); + if (phy->rev != 5) + BWN_RF_WRITE(mac, r + 0xA, 0); + if (phy->rev != 7) + BWN_RF_WRITE(mac, r + 0xB, 1); + else + BWN_RF_WRITE(mac, r + 0xB, 0x31); + } else { + BWN_RF_WRITE(mac, r + 0x5, 0x9); + BWN_RF_WRITE(mac, r + 0x9, 0xC); + BWN_RF_WRITE(mac, r + 0xB, 0x0); + if (phy->rev != 5) + BWN_RF_WRITE(mac, r + 0xA, 1); + else + BWN_RF_WRITE(mac, r + 0xA, 0x31); + } + BWN_RF_WRITE(mac, r + 0x6, 0); + BWN_RF_WRITE(mac, r + 0x7, 0); + BWN_RF_WRITE(mac, r + 0x8, 3); + BWN_RF_WRITE(mac, r + 0xC, 0); + } + } else { + if (bwn_current_band(mac) == BWN_BAND_2G) + BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR31, 0x128); + else + BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR31, 0x80); + BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR30, 0); + BWN_RF_WRITE(mac, B2056_SYN_GPIO_MASTER1, 0x29); + + for (core = 0; core < 2; core++) { + r = core ? B2056_TX1 : B2056_TX0; + + BWN_RF_WRITE(mac, r | B2056_TX_IQCAL_VCM_HG, 0); + BWN_RF_WRITE(mac, r | B2056_TX_IQCAL_IDAC, 0); + BWN_RF_WRITE(mac, r | B2056_TX_TSSI_VCM, 3); + BWN_RF_WRITE(mac, r | B2056_TX_TX_AMP_DET, 0); + BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC1, 8); + BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC2, 0); + BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC3, 0); + if (bwn_current_band(mac) == BWN_BAND_2G) { + BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MASTER, + 0x5); + if (phy->rev != 5) + BWN_RF_WRITE(mac, r | B2056_TX_TSSIA, + 0x00); + if (phy->rev >= 5) + BWN_RF_WRITE(mac, r | B2056_TX_TSSIG, + 0x31); + else + BWN_RF_WRITE(mac, r | B2056_TX_TSSIG, + 0x11); + BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MUX, + 0xE); + } else { + BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MASTER, + 0x9); + BWN_RF_WRITE(mac, r | B2056_TX_TSSIA, 0x31); + BWN_RF_WRITE(mac, r | B2056_TX_TSSIG, 0x0); + BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MUX, + 0xC); + } + } + } +} + +/* + * Stop radio and transmit known signal. Then check received signal strength to + * get TSSI (Transmit Signal Strength Indicator). + * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi + */ +static void bwn_nphy_tx_power_ctl_idle_tssi(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint32_t tmp; + int32_t rssi[4] = { }; + + if (bwn_is_chan_passive(mac)) + return; + + if (bwn_nphy_ipa(mac)) + bwn_nphy_ipa_internal_tssi_setup(mac); + + if (phy->rev >= 19) + bwn_nphy_rf_ctl_override_rev19(mac, 0x1000, 0, 3, false, 0); + else if (phy->rev >= 7) + bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, 0, 3, false, 0); + else if (phy->rev >= 3) + bwn_nphy_rf_ctl_override(mac, 0x2000, 0, 3, false); + + bwn_nphy_stop_playback(mac); + bwn_nphy_tx_tone(mac, 4000, 0, false, false, false); + DELAY(20); + tmp = bwn_nphy_poll_rssi(mac, N_RSSI_TSSI_2G, rssi, 1); + bwn_nphy_stop_playback(mac); + + bwn_nphy_rssi_select(mac, 0, N_RSSI_W1); + + if (phy->rev >= 19) + bwn_nphy_rf_ctl_override_rev19(mac, 0x1000, 0, 3, true, 0); + else if (phy->rev >= 7) + bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, 0, 3, true, 0); + else if (phy->rev >= 3) + bwn_nphy_rf_ctl_override(mac, 0x2000, 0, 3, true); + + if (phy->rev >= 19) { + /* TODO */ + return; + } else if (phy->rev >= 3) { + nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF; + nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF; + } else { + nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF; + nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF; + } + nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF; + nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF; +} + +/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */ +static void bwn_nphy_tx_prepare_adjusted_power_table(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint8_t idx, delta; + uint8_t i, stf_mode; + + /* Array adj_pwr_tbl corresponds to the hardware table. It consists of + * 21 groups, each containing 4 entries. + * + * First group has entries for CCK modulation. + * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM). + * + * Group 0 is for CCK + * Groups 1..4 use BPSK (group per coding rate) + * Groups 5..8 use QPSK (group per coding rate) + * Groups 9..12 use 16-QAM (group per coding rate) + * Groups 13..16 use 64-QAM (group per coding rate) + * Groups 17..20 are unknown + */ + + for (i = 0; i < 4; i++) + nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i]; + + for (stf_mode = 0; stf_mode < 4; stf_mode++) { + delta = 0; + switch (stf_mode) { + case 0: + if (bwn_is_40mhz(mac) && mac->mac_phy.rev >= 5) { + idx = 68; + } else { + delta = 1; + idx = bwn_is_40mhz(mac) ? 52 : 4; + } + break; + case 1: + idx = bwn_is_40mhz(mac) ? 76 : 28; + break; + case 2: + idx = bwn_is_40mhz(mac) ? 84 : 36; + break; + case 3: + idx = bwn_is_40mhz(mac) ? 92 : 44; + break; + } + + for (i = 0; i < 20; i++) { + nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] = + nphy->tx_power_offset[idx]; + if (i == 0) + idx += delta; + if (i == 14) + idx += 1 - delta; + if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 || + i == 13) + idx += 1; + } + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */ +static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + struct siba_sprom_core_pwr_info core_pwr_info[4]; + int n; + + int16_t a1[2], b0[2], b1[2]; + uint8_t idle[2]; + uint8_t ppr_max; + int8_t target[2]; + int32_t num, den, pwr; + uint32_t regval[64]; + + uint16_t freq = bwn_get_centre_freq(mac); + uint16_t tmp; + uint16_t r; /* routing */ + uint8_t i, c; + + for (n = 0; n < 4; n++) { + bzero(&core_pwr_info[n], sizeof(core_pwr_info[n])); + if (siba_sprom_get_core_power_info(sc->sc_dev, n, + &core_pwr_info[n]) != 0) { + BWN_ERRPRINTF(mac->mac_sc, + "%s: failed to get core_pwr_info for core %d\n", + __func__, + n); + } + } + + if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) { + BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000); + BWN_READ_4(mac, BWN_MACCTL); + DELAY(1); + } + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, true); + + BWN_PHY_SET(mac, BWN_NPHY_TSSIMODE, BWN_NPHY_TSSIMODE_EN); + if (mac->mac_phy.rev >= 3) + BWN_PHY_MASK(mac, BWN_NPHY_TXPCTL_CMD, + ~BWN_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF); + else + BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_CMD, + BWN_NPHY_TXPCTL_CMD_PCTLEN); + + if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) + BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0); + + /* + * XXX TODO: see if those bandsbelow map to 5g-lo, 5g-mid, 5g-hi in + * any way. + */ + if (siba_sprom_get_rev(sc->sc_dev) < 4) { + idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g; + idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g; + target[0] = target[1] = 52; + a1[0] = a1[1] = -424; + b0[0] = b0[1] = 5612; + b1[0] = b1[1] = -1393; + } else { + if (bwn_current_band(mac) == BWN_BAND_2G) { + for (c = 0; c < 2; c++) { + idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g; + target[c] = core_pwr_info[c].maxpwr_2g; + a1[c] = core_pwr_info[c].pa_2g[0]; + b0[c] = core_pwr_info[c].pa_2g[1]; + b1[c] = core_pwr_info[c].pa_2g[2]; + } + } else if (freq >= 4900 && freq < 5100) { + for (c = 0; c < 2; c++) { + idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; + target[c] = core_pwr_info[c].maxpwr_5gl; + a1[c] = core_pwr_info[c].pa_5gl[0]; + b0[c] = core_pwr_info[c].pa_5gl[1]; + b1[c] = core_pwr_info[c].pa_5gl[2]; + } + } else if (freq >= 5100 && freq < 5500) { + for (c = 0; c < 2; c++) { + idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; + target[c] = core_pwr_info[c].maxpwr_5g; + a1[c] = core_pwr_info[c].pa_5g[0]; + b0[c] = core_pwr_info[c].pa_5g[1]; + b1[c] = core_pwr_info[c].pa_5g[2]; + } + } else if (freq >= 5500) { + for (c = 0; c < 2; c++) { + idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; + target[c] = core_pwr_info[c].maxpwr_5gh; + a1[c] = core_pwr_info[c].pa_5gh[0]; + b0[c] = core_pwr_info[c].pa_5gh[1]; + b1[c] = core_pwr_info[c].pa_5gh[2]; + } + } else { + idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g; + idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g; + target[0] = target[1] = 52; + a1[0] = a1[1] = -424; + b0[0] = b0[1] = 5612; + b1[0] = b1[1] = -1393; + } + } + + ppr_max = bwn_ppr_get_max(mac, &nphy->tx_pwr_max_ppr); + if (ppr_max) { + target[0] = ppr_max; + target[1] = ppr_max; + } + + if (mac->mac_phy.rev >= 3) { + if (siba_sprom_get_fem_2ghz_tssipos(sc->sc_dev)) + BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_ITSSI, 0x4000); + if (mac->mac_phy.rev >= 7) { + for (c = 0; c < 2; c++) { + r = c ? 0x190 : 0x170; + if (bwn_nphy_ipa(mac)) + BWN_RF_WRITE(mac, r + 0x9, (bwn_current_band(mac) == BWN_BAND_2G) ? 0xE : 0xC); + } + } else { + if (bwn_nphy_ipa(mac)) { + tmp = (bwn_current_band(mac) == BWN_BAND_5G) ? 0xC : 0xE; + BWN_RF_WRITE(mac, + B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp); + BWN_RF_WRITE(mac, + B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp); + } else { + BWN_RF_WRITE(mac, + B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11); + BWN_RF_WRITE(mac, + B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11); + } + } + } + + if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) { + BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000); + BWN_READ_4(mac, BWN_MACCTL); + DELAY(1); + } + + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 7) { + BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, + ~BWN_NPHY_TXPCTL_CMD_INIT, 0x19); + BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT, + ~BWN_NPHY_TXPCTL_INIT_PIDXI1, 0x19); + } else { + BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, + ~BWN_NPHY_TXPCTL_CMD_INIT, 0x40); + if (mac->mac_phy.rev > 1) + BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT, + ~BWN_NPHY_TXPCTL_INIT_PIDXI1, 0x40); + } + + if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) + BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0); + + BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_N, + 0xF0 << BWN_NPHY_TXPCTL_N_TSSID_SHIFT | + 3 << BWN_NPHY_TXPCTL_N_NPTIL2_SHIFT); + BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_ITSSI, + idle[0] << BWN_NPHY_TXPCTL_ITSSI_0_SHIFT | + idle[1] << BWN_NPHY_TXPCTL_ITSSI_1_SHIFT | + BWN_NPHY_TXPCTL_ITSSI_BINF); + BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_TPWR, + target[0] << BWN_NPHY_TXPCTL_TPWR_0_SHIFT | + target[1] << BWN_NPHY_TXPCTL_TPWR_1_SHIFT); + + for (c = 0; c < 2; c++) { + for (i = 0; i < 64; i++) { + num = 8 * (16 * b0[c] + b1[c] * i); + den = 32768 + a1[c] * i; + pwr = max((4 * num + den / 2) / den, -8); + if (mac->mac_phy.rev < 3 && (i <= (31 - idle[c] + 1))) + pwr = max(pwr, target[c] + 1); + regval[i] = pwr; + } + bwn_ntab_write_bulk(mac, BWN_NTAB32(26 + c, 0), 64, regval); + } + + bwn_nphy_tx_prepare_adjusted_power_table(mac); + bwn_ntab_write_bulk(mac, BWN_NTAB16(26, 64), 84, nphy->adj_pwr_tbl); + bwn_ntab_write_bulk(mac, BWN_NTAB16(27, 64), 84, nphy->adj_pwr_tbl); + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, false); +} + +static void bwn_nphy_tx_gain_table_upload(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + + const uint32_t *table = NULL; + uint32_t rfpwr_offset; + uint8_t pga_gain, pad_gain; + int i; + const int16_t *rf_pwr_offset_table = NULL; + + table = bwn_nphy_get_tx_gain_table(mac); + if (!table) + return; + + bwn_ntab_write_bulk(mac, BWN_NTAB32(26, 192), 128, table); + bwn_ntab_write_bulk(mac, BWN_NTAB32(27, 192), 128, table); + + if (phy->rev < 3) + return; + +#if 0 + nphy->gmval = (table[0] >> 16) & 0x7000; +#endif + + if (phy->rev >= 19) { + return; + } else if (phy->rev >= 7) { + rf_pwr_offset_table = bwn_ntab_get_rf_pwr_offset_table(mac); + if (!rf_pwr_offset_table) + return; + /* TODO: Enable this once we have gains configured */ + return; + } + + for (i = 0; i < 128; i++) { + if (phy->rev >= 19) { + /* TODO */ + return; + } else if (phy->rev >= 7) { + pga_gain = (table[i] >> 24) & 0xf; + pad_gain = (table[i] >> 19) & 0x1f; + if (bwn_current_band(mac) == BWN_BAND_2G) + rfpwr_offset = rf_pwr_offset_table[pad_gain]; + else + rfpwr_offset = rf_pwr_offset_table[pga_gain]; + } else { + pga_gain = (table[i] >> 24) & 0xF; + if (bwn_current_band(mac) == BWN_BAND_2G) + rfpwr_offset = bwn_ntab_papd_pga_gain_delta_ipa_2g[pga_gain]; + else + rfpwr_offset = 0; /* FIXME */ + } + + bwn_ntab_write(mac, BWN_NTAB32(26, 576 + i), rfpwr_offset); + bwn_ntab_write(mac, BWN_NTAB32(27, 576 + i), rfpwr_offset); + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ +static void bwn_nphy_pa_override(struct bwn_mac *mac, bool enable) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + bwn_band_t band; + uint16_t tmp; + + if (!enable) { + nphy->rfctrl_intc1_save = BWN_PHY_READ(mac, + BWN_NPHY_RFCTL_INTC1); + nphy->rfctrl_intc2_save = BWN_PHY_READ(mac, + BWN_NPHY_RFCTL_INTC2); + band = bwn_current_band(mac); + if (mac->mac_phy.rev >= 7) { + tmp = 0x1480; + } else if (mac->mac_phy.rev >= 3) { + if (band == BWN_BAND_5G) + tmp = 0x600; + else + tmp = 0x480; + } else { + if (band == BWN_BAND_5G) + tmp = 0x180; + else + tmp = 0x120; + } + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, tmp); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, tmp); + } else { + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, + nphy->rfctrl_intc1_save); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, + nphy->rfctrl_intc2_save); + } +} + +/* + * TX low-pass filter bandwidth setup + * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw + */ +static void bwn_nphy_tx_lpf_bw(struct bwn_mac *mac) +{ + uint16_t tmp; + + if (mac->mac_phy.rev < 3 || mac->mac_phy.rev >= 7) + return; + + if (bwn_nphy_ipa(mac)) + tmp = bwn_is_40mhz(mac) ? 5 : 4; + else + tmp = bwn_is_40mhz(mac) ? 3 : 1; + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S2, + (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); + + if (bwn_nphy_ipa(mac)) { + tmp = bwn_is_40mhz(mac) ? 4 : 1; + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S2, + (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ +static void bwn_nphy_rx_iq_est(struct bwn_mac *mac, struct bwn_nphy_iq_est *est, + uint16_t samps, uint8_t time, bool wait) +{ + int i; + uint16_t tmp; + + BWN_PHY_WRITE(mac, BWN_NPHY_IQEST_SAMCNT, samps); + BWN_PHY_SETMASK(mac, BWN_NPHY_IQEST_WT, ~BWN_NPHY_IQEST_WT_VAL, time); + if (wait) + BWN_PHY_SET(mac, BWN_NPHY_IQEST_CMD, BWN_NPHY_IQEST_CMD_MODE); + else + BWN_PHY_MASK(mac, BWN_NPHY_IQEST_CMD, ~BWN_NPHY_IQEST_CMD_MODE); + + BWN_PHY_SET(mac, BWN_NPHY_IQEST_CMD, BWN_NPHY_IQEST_CMD_START); + + for (i = 1000; i; i--) { + tmp = BWN_PHY_READ(mac, BWN_NPHY_IQEST_CMD); + if (!(tmp & BWN_NPHY_IQEST_CMD_START)) { + est->i0_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_HI0) << 16) | + BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_LO0); + est->q0_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_HI0) << 16) | + BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_LO0); + est->iq0_prod = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_HI0) << 16) | + BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_LO0); + + est->i1_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_HI1) << 16) | + BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_LO1); + est->q1_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_HI1) << 16) | + BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_LO1); + est->iq1_prod = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_HI1) << 16) | + BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_LO1); + return; + } + DELAY(10); + } + memset(est, 0, sizeof(*est)); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ +static void bwn_nphy_rx_iq_coeffs(struct bwn_mac *mac, bool write, + struct bwn_phy_n_iq_comp *pcomp) +{ + if (write) { + BWN_PHY_WRITE(mac, BWN_NPHY_C1_RXIQ_COMPA0, pcomp->a0); + BWN_PHY_WRITE(mac, BWN_NPHY_C1_RXIQ_COMPB0, pcomp->b0); + BWN_PHY_WRITE(mac, BWN_NPHY_C2_RXIQ_COMPA1, pcomp->a1); + BWN_PHY_WRITE(mac, BWN_NPHY_C2_RXIQ_COMPB1, pcomp->b1); + } else { + pcomp->a0 = BWN_PHY_READ(mac, BWN_NPHY_C1_RXIQ_COMPA0); + pcomp->b0 = BWN_PHY_READ(mac, BWN_NPHY_C1_RXIQ_COMPB0); + pcomp->a1 = BWN_PHY_READ(mac, BWN_NPHY_C2_RXIQ_COMPA1); + pcomp->b1 = BWN_PHY_READ(mac, BWN_NPHY_C2_RXIQ_COMPB1); + } +} + +#if 0 +/* Ready but not used anywhere */ +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ +static void bwn_nphy_rx_cal_phy_cleanup(struct bwn_mac *mac, uint8_t core) +{ + uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs; + + BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQCA, regs[0]); + if (core == 0) { + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, regs[1]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, regs[2]); + } else { + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, regs[1]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[2]); + } + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[3]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[4]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO1, regs[5]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO2, regs[6]); + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S1, regs[7]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, regs[8]); + BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN0, regs[9]); + BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN1, regs[10]); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ +static void bwn_nphy_rx_cal_phy_setup(struct bwn_mac *mac, uint8_t core) +{ + uint8_t rxval, txval; + uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs; + + regs[0] = BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA); + if (core == 0) { + regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1); + regs[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1); + } else { + regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2); + regs[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); + } + regs[3] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); + regs[4] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); + regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO1); + regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO2); + regs[7] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B1S1); + regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_OVER); + regs[9] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN0); + regs[10] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN1); + + BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x0001); + BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x0001); + + BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, + ~BWN_NPHY_RFSEQCA_RXDIS & 0xFFFF, + ((1 - core) << BWN_NPHY_RFSEQCA_RXDIS_SHIFT)); + BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXEN, + ((1 - core) << BWN_NPHY_RFSEQCA_TXEN_SHIFT)); + BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXEN, + (core << BWN_NPHY_RFSEQCA_RXEN_SHIFT)); + BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXDIS, + (core << BWN_NPHY_RFSEQCA_TXDIS_SHIFT)); + + if (core == 0) { + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x0007); + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0007); + } else { + BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x0007); + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0007); + } + + bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA, 0, 3); + bwn_nphy_rf_ctl_override(mac, 8, 0, 3, false); + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RX2TX); + + if (core == 0) { + rxval = 1; + txval = 8; + } else { + rxval = 4; + txval = 2; + } + bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, rxval, + core + 1); + bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, txval, + 2 - core); +} +#endif + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ +static void bwn_nphy_calc_rx_iq_comp(struct bwn_mac *mac, uint8_t mask) +{ + int i; + int32_t iq; + uint32_t ii; + uint32_t qq; + int iq_nbits, qq_nbits; + int arsh, brsh; + uint16_t tmp, a, b; + + struct bwn_nphy_iq_est est; + struct bwn_phy_n_iq_comp old; + struct bwn_phy_n_iq_comp new = { }; + bool error = false; + + if (mask == 0) + return; + + bwn_nphy_rx_iq_coeffs(mac, false, &old); + bwn_nphy_rx_iq_coeffs(mac, true, &new); + bwn_nphy_rx_iq_est(mac, &est, 0x4000, 32, false); + new = old; + + for (i = 0; i < 2; i++) { + if (i == 0 && (mask & 1)) { + iq = est.iq0_prod; + ii = est.i0_pwr; + qq = est.q0_pwr; + } else if (i == 1 && (mask & 2)) { + iq = est.iq1_prod; + ii = est.i1_pwr; + qq = est.q1_pwr; + } else { + continue; + } + + if (ii + qq < 2) { + error = true; + break; + } + + iq_nbits = fls(abs(iq)); + qq_nbits = fls(qq); + + arsh = iq_nbits - 20; + if (arsh >= 0) { + a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); + tmp = ii >> arsh; + } else { + a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); + tmp = ii << -arsh; + } + if (tmp == 0) { + error = true; + break; + } + a /= tmp; + + brsh = qq_nbits - 11; + if (brsh >= 0) { + b = (qq << (31 - qq_nbits)); + tmp = ii >> brsh; + } else { + b = (qq << (31 - qq_nbits)); + tmp = ii << -brsh; + } + if (tmp == 0) { + error = true; + break; + } + b = bwn_sqrt(mac, b / tmp - a * a) - (1 << 10); + + if (i == 0 && (mask & 0x1)) { + if (mac->mac_phy.rev >= 3) { + new.a0 = a & 0x3FF; + new.b0 = b & 0x3FF; + } else { + new.a0 = b & 0x3FF; + new.b0 = a & 0x3FF; + } + } else if (i == 1 && (mask & 0x2)) { + if (mac->mac_phy.rev >= 3) { + new.a1 = a & 0x3FF; + new.b1 = b & 0x3FF; + } else { + new.a1 = b & 0x3FF; + new.b1 = a & 0x3FF; + } + } + } + + if (error) + new = old; + + bwn_nphy_rx_iq_coeffs(mac, true, &new); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ +static void bwn_nphy_tx_iq_workaround(struct bwn_mac *mac) +{ + uint16_t array[4]; + bwn_ntab_read_bulk(mac, BWN_NTAB16(0xF, 0x50), 4, array); + + bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW0, array[0]); + bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW1, array[1]); + bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW2, array[2]); + bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW3, array[3]); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ +static void bwn_nphy_spur_workaround(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint8_t channel = bwn_get_chan(mac); + int tone[2] = { 57, 58 }; + uint32_t noise[2] = { 0x3FF, 0x3FF }; + + if (mac->mac_phy.rev < 3) { + BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", + __func__, + mac->mac_phy.rev); + } + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 1); + + if (nphy->gband_spurwar_en) { + /* TODO: N PHY Adjust Analog Pfbw (7) */ + if (channel == 11 && bwn_is_40mhz(mac)) + ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ + else + ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ + /* TODO: N PHY Adjust CRS Min Power (0x1E) */ + } + + if (nphy->aband_spurwar_en) { + if (channel == 54) { + tone[0] = 0x20; + noise[0] = 0x25F; + } else if (channel == 38 || channel == 102 || channel == 118) { + if (0 /* FIXME */) { + tone[0] = 0x20; + noise[0] = 0x21F; + } else { + tone[0] = 0; + noise[0] = 0; + } + } else if (channel == 134) { + tone[0] = 0x20; + noise[0] = 0x21F; + } else if (channel == 151) { + tone[0] = 0x10; + noise[0] = 0x23F; + } else if (channel == 153 || channel == 161) { + tone[0] = 0x30; + noise[0] = 0x23F; + } else { + tone[0] = 0; + noise[0] = 0; + } + + if (!tone[0] && !noise[0]) + ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ + else + ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ + } + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 0); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ +static void bwn_nphy_tx_pwr_ctrl_coef_setup(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + int i, j; + uint32_t tmp; + uint32_t cur_real, cur_imag, real_part, imag_part; + + uint16_t buffer[7]; + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, true); + + bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 7, buffer); + + for (i = 0; i < 2; i++) { + tmp = ((buffer[i * 2] & 0x3FF) << 10) | + (buffer[i * 2 + 1] & 0x3FF); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, + (((i + 26) << 10) | 320)); + for (j = 0; j < 128; j++) { + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI, + ((tmp >> 16) & 0xFFFF)); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, + (tmp & 0xFFFF)); + } + } + + for (i = 0; i < 2; i++) { + tmp = buffer[5 + i]; + real_part = (tmp >> 8) & 0xFF; + imag_part = (tmp & 0xFF); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, + (((i + 26) << 10) | 448)); + + if (mac->mac_phy.rev >= 3) { + cur_real = real_part; + cur_imag = imag_part; + tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); + } + + for (j = 0; j < 128; j++) { + if (mac->mac_phy.rev < 3) { + cur_real = (real_part * loscale[j] + 128) >> 8; + cur_imag = (imag_part * loscale[j] + 128) >> 8; + tmp = ((cur_real & 0xFF) << 8) | + (cur_imag & 0xFF); + } + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI, + ((tmp >> 16) & 0xFFFF)); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, + (tmp & 0xFFFF)); + } + } + + if (mac->mac_phy.rev >= 3) { + bwn_shm_write_2(mac, BWN_SHARED, + BWN_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); + bwn_shm_write_2(mac, BWN_SHARED, + BWN_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); + } + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, false); +} + +/* + * Restore RSSI Calibration + * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal + */ +static void bwn_nphy_restore_rssi_cal(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint16_t *rssical_radio_regs = NULL; + uint16_t *rssical_phy_regs = NULL; + + if (bwn_current_band(mac) == BWN_BAND_2G) { + if (!nphy->rssical_chanspec_2G.center_freq) + return; + rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; + rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; + } else { + if (!nphy->rssical_chanspec_5G.center_freq) + return; + rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; + rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; + } + + if (mac->mac_phy.rev >= 19) { + /* TODO */ + } else if (mac->mac_phy.rev >= 7) { + BWN_RF_SETMASK(mac, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, + rssical_radio_regs[0]); + BWN_RF_SETMASK(mac, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK, + rssical_radio_regs[1]); + } else { + BWN_RF_SETMASK(mac, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, + rssical_radio_regs[0]); + BWN_RF_SETMASK(mac, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3, + rssical_radio_regs[1]); + } + + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); + + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); + + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); + BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); +} + +static void bwn_nphy_tx_cal_radio_setup_rev19(struct bwn_mac *mac) +{ + /* TODO */ +} + +static void bwn_nphy_tx_cal_radio_setup_rev7(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + uint16_t *save = nphy->tx_rx_cal_radio_saveregs; + int core, off; + uint16_t r, tmp; + + for (core = 0; core < 2; core++) { + r = core ? 0x20 : 0; + off = core * 11; + + save[off + 0] = BWN_RF_READ(mac, r + R2057_TX0_TX_SSI_MASTER); + save[off + 1] = BWN_RF_READ(mac, r + R2057_TX0_IQCAL_VCM_HG); + save[off + 2] = BWN_RF_READ(mac, r + R2057_TX0_IQCAL_IDAC); + save[off + 3] = BWN_RF_READ(mac, r + R2057_TX0_TSSI_VCM); + save[off + 4] = 0; + save[off + 5] = BWN_RF_READ(mac, r + R2057_TX0_TX_SSI_MUX); + if (phy->rf_rev != 5) + save[off + 6] = BWN_RF_READ(mac, r + R2057_TX0_TSSIA); + save[off + 7] = BWN_RF_READ(mac, r + R2057_TX0_TSSIG); + save[off + 8] = BWN_RF_READ(mac, r + R2057_TX0_TSSI_MISC1); + + if (bwn_current_band(mac) == BWN_BAND_5G) { + BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MASTER, 0xA); + BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_VCM_HG, 0x43); + BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_IDAC, 0x55); + BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_VCM, 0); + BWN_RF_WRITE(mac, r + R2057_TX0_TSSIG, 0); + if (nphy->use_int_tx_iq_lo_cal) { + BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MUX, 0x4); + tmp = true ? 0x31 : 0x21; /* TODO */ + BWN_RF_WRITE(mac, r + R2057_TX0_TSSIA, tmp); + } + BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_MISC1, 0x00); + } else { + BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MASTER, 0x6); + BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_VCM_HG, 0x43); + BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_IDAC, 0x55); + BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_VCM, 0); + + if (phy->rf_rev != 5) + BWN_RF_WRITE(mac, r + R2057_TX0_TSSIA, 0); + if (nphy->use_int_tx_iq_lo_cal) { + BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MUX, 0x6); + tmp = true ? 0x31 : 0x21; /* TODO */ + BWN_RF_WRITE(mac, r + R2057_TX0_TSSIG, tmp); + } + BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_MISC1, 0); + } + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ +static void bwn_nphy_tx_cal_radio_setup(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + uint16_t *save = nphy->tx_rx_cal_radio_saveregs; + uint16_t tmp; + uint8_t offset, i; + + if (phy->rev >= 19) { + bwn_nphy_tx_cal_radio_setup_rev19(mac); + } else if (phy->rev >= 7) { + bwn_nphy_tx_cal_radio_setup_rev7(mac); + } else if (phy->rev >= 3) { + for (i = 0; i < 2; i++) { + tmp = (i == 0) ? 0x2000 : 0x3000; + offset = i * 11; + + save[offset + 0] = BWN_RF_READ(mac, B2055_CAL_RVARCTL); + save[offset + 1] = BWN_RF_READ(mac, B2055_CAL_LPOCTL); + save[offset + 2] = BWN_RF_READ(mac, B2055_CAL_TS); + save[offset + 3] = BWN_RF_READ(mac, B2055_CAL_RCCALRTS); + save[offset + 4] = BWN_RF_READ(mac, B2055_CAL_RCALRTS); + save[offset + 5] = BWN_RF_READ(mac, B2055_PADDRV); + save[offset + 6] = BWN_RF_READ(mac, B2055_XOCTL1); + save[offset + 7] = BWN_RF_READ(mac, B2055_XOCTL2); + save[offset + 8] = BWN_RF_READ(mac, B2055_XOREGUL); + save[offset + 9] = BWN_RF_READ(mac, B2055_XOMISC); + save[offset + 10] = BWN_RF_READ(mac, B2055_PLL_LFC1); + + if (bwn_current_band(mac) == BWN_BAND_5G) { + BWN_RF_WRITE(mac, tmp | B2055_CAL_RVARCTL, 0x0A); + BWN_RF_WRITE(mac, tmp | B2055_CAL_LPOCTL, 0x40); + BWN_RF_WRITE(mac, tmp | B2055_CAL_TS, 0x55); + BWN_RF_WRITE(mac, tmp | B2055_CAL_RCCALRTS, 0); + BWN_RF_WRITE(mac, tmp | B2055_CAL_RCALRTS, 0); + if (nphy->ipa5g_on) { + BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 4); + BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 1); + } else { + BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 0); + BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 0x2F); + } + BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, 0); + } else { + BWN_RF_WRITE(mac, tmp | B2055_CAL_RVARCTL, 0x06); + BWN_RF_WRITE(mac, tmp | B2055_CAL_LPOCTL, 0x40); + BWN_RF_WRITE(mac, tmp | B2055_CAL_TS, 0x55); + BWN_RF_WRITE(mac, tmp | B2055_CAL_RCCALRTS, 0); + BWN_RF_WRITE(mac, tmp | B2055_CAL_RCALRTS, 0); + BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 0); + if (nphy->ipa2g_on) { + BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 6); + BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, + (mac->mac_phy.rev < 5) ? 0x11 : 0x01); + } else { + BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 0); + BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, 0); + } + } + BWN_RF_WRITE(mac, tmp | B2055_XOREGUL, 0); + BWN_RF_WRITE(mac, tmp | B2055_XOMISC, 0); + BWN_RF_WRITE(mac, tmp | B2055_PLL_LFC1, 0); + } + } else { + save[0] = BWN_RF_READ(mac, B2055_C1_TX_RF_IQCAL1); + BWN_RF_WRITE(mac, B2055_C1_TX_RF_IQCAL1, 0x29); + + save[1] = BWN_RF_READ(mac, B2055_C1_TX_RF_IQCAL2); + BWN_RF_WRITE(mac, B2055_C1_TX_RF_IQCAL2, 0x54); + + save[2] = BWN_RF_READ(mac, B2055_C2_TX_RF_IQCAL1); + BWN_RF_WRITE(mac, B2055_C2_TX_RF_IQCAL1, 0x29); + + save[3] = BWN_RF_READ(mac, B2055_C2_TX_RF_IQCAL2); + BWN_RF_WRITE(mac, B2055_C2_TX_RF_IQCAL2, 0x54); + + save[3] = BWN_RF_READ(mac, B2055_C1_PWRDET_RXTX); + save[4] = BWN_RF_READ(mac, B2055_C2_PWRDET_RXTX); + + if (!(BWN_PHY_READ(mac, BWN_NPHY_BANDCTL) & + BWN_NPHY_BANDCTL_5GHZ)) { + BWN_RF_WRITE(mac, B2055_C1_PWRDET_RXTX, 0x04); + BWN_RF_WRITE(mac, B2055_C2_PWRDET_RXTX, 0x04); + } else { + BWN_RF_WRITE(mac, B2055_C1_PWRDET_RXTX, 0x20); + BWN_RF_WRITE(mac, B2055_C2_PWRDET_RXTX, 0x20); + } + + if (mac->mac_phy.rev < 2) { + BWN_RF_SET(mac, B2055_C1_TX_BB_MXGM, 0x20); + BWN_RF_SET(mac, B2055_C2_TX_BB_MXGM, 0x20); + } else { + BWN_RF_MASK(mac, B2055_C1_TX_BB_MXGM, ~0x20); + BWN_RF_MASK(mac, B2055_C2_TX_BB_MXGM, ~0x20); + } + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ +static void bwn_nphy_update_tx_cal_ladder(struct bwn_mac *mac, uint16_t core) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + int i; + uint16_t scale, entry; + + uint16_t tmp = nphy->txcal_bbmult; + if (core == 0) + tmp >>= 8; + tmp &= 0xff; + + for (i = 0; i < 18; i++) { + scale = (ladder_lo[i].percent * tmp) / 100; + entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; + bwn_ntab_write(mac, BWN_NTAB16(15, i), entry); + + scale = (ladder_iq[i].percent * tmp) / 100; + entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; + bwn_ntab_write(mac, BWN_NTAB16(15, i + 32), entry); + } +} + +static void bwn_nphy_pa_set_tx_dig_filter(struct bwn_mac *mac, uint16_t offset, + const int16_t *filter) +{ + int i; + + offset = BWN_PHY_N(offset); + + for (i = 0; i < 15; i++, offset++) + BWN_PHY_WRITE(mac, offset, filter[i]); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ +static void bwn_nphy_ext_pa_set_tx_dig_filters(struct bwn_mac *mac) +{ + bwn_nphy_pa_set_tx_dig_filter(mac, 0x2C5, + tbl_tx_filter_coef_rev4[2]); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ +static void bwn_nphy_int_pa_set_tx_dig_filters(struct bwn_mac *mac) +{ + /* BWN_NPHY_TXF_20CO_S0A1, BWN_NPHY_TXF_40CO_S0A1, unknown */ + static const uint16_t offset[] = { 0x186, 0x195, 0x2C5 }; + static const int16_t dig_filter_phy_rev16[] = { + -375, 136, -407, 208, -1527, + 956, 93, 186, 93, 230, + -44, 230, 201, -191, 201, + }; + int i; + + for (i = 0; i < 3; i++) + bwn_nphy_pa_set_tx_dig_filter(mac, offset[i], + tbl_tx_filter_coef_rev4[i]); + + /* Verified with BCM43227 and BCM43228 */ + if (mac->mac_phy.rev == 16) + bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, dig_filter_phy_rev16); + + /* Verified with BCM43131 and BCM43217 */ + if (mac->mac_phy.rev == 17) { + bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, dig_filter_phy_rev16); + bwn_nphy_pa_set_tx_dig_filter(mac, 0x195, + tbl_tx_filter_coef_rev4[1]); + } + + if (bwn_is_40mhz(mac)) { + bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, + tbl_tx_filter_coef_rev4[3]); + } else { + if (bwn_current_band(mac) == BWN_BAND_5G) + bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, + tbl_tx_filter_coef_rev4[5]); + if (bwn_get_chan(mac) == 14) + bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, + tbl_tx_filter_coef_rev4[6]); + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ +static struct bwn_nphy_txgains bwn_nphy_get_tx_gains(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint16_t curr_gain[2]; + struct bwn_nphy_txgains target; + const uint32_t *table = NULL; + + if (!nphy->txpwrctrl) { + int i; + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, true); + bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, curr_gain); + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, false); + + for (i = 0; i < 2; ++i) { + if (mac->mac_phy.rev >= 7) { + target.ipa[i] = curr_gain[i] & 0x0007; + target.pad[i] = (curr_gain[i] & 0x00F8) >> 3; + target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; + target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; + target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15; + } else if (mac->mac_phy.rev >= 3) { + target.ipa[i] = curr_gain[i] & 0x000F; + target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; + target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; + target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; + } else { + target.ipa[i] = curr_gain[i] & 0x0003; + target.pad[i] = (curr_gain[i] & 0x000C) >> 2; + target.pga[i] = (curr_gain[i] & 0x0070) >> 4; + target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; + } + } + } else { + int i; + uint16_t index[2]; + index[0] = (BWN_PHY_READ(mac, BWN_NPHY_C1_TXPCTL_STAT) & + BWN_NPHY_TXPCTL_STAT_BIDX) >> + BWN_NPHY_TXPCTL_STAT_BIDX_SHIFT; + index[1] = (BWN_PHY_READ(mac, BWN_NPHY_C2_TXPCTL_STAT) & + BWN_NPHY_TXPCTL_STAT_BIDX) >> + BWN_NPHY_TXPCTL_STAT_BIDX_SHIFT; + + for (i = 0; i < 2; ++i) { + table = bwn_nphy_get_tx_gain_table(mac); + if (!table) + break; + + if (mac->mac_phy.rev >= 7) { + target.ipa[i] = (table[index[i]] >> 16) & 0x7; + target.pad[i] = (table[index[i]] >> 19) & 0x1F; + target.pga[i] = (table[index[i]] >> 24) & 0xF; + target.txgm[i] = (table[index[i]] >> 28) & 0x7; + target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1; + } else if (mac->mac_phy.rev >= 3) { + target.ipa[i] = (table[index[i]] >> 16) & 0xF; + target.pad[i] = (table[index[i]] >> 20) & 0xF; + target.pga[i] = (table[index[i]] >> 24) & 0xF; + target.txgm[i] = (table[index[i]] >> 28) & 0xF; + } else { + target.ipa[i] = (table[index[i]] >> 16) & 0x3; + target.pad[i] = (table[index[i]] >> 18) & 0x3; + target.pga[i] = (table[index[i]] >> 20) & 0x7; + target.txgm[i] = (table[index[i]] >> 23) & 0x7; + } + } + } + + return target; +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ +static void bwn_nphy_tx_cal_phy_cleanup(struct bwn_mac *mac) +{ + uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs; + + if (mac->mac_phy.rev >= 3) { + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, regs[0]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, regs[1]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, regs[2]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[3]); + BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, regs[4]); + bwn_ntab_write(mac, BWN_NTAB16(8, 3), regs[5]); + bwn_ntab_write(mac, BWN_NTAB16(8, 19), regs[6]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[7]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[8]); + BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN0, regs[9]); + BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN1, regs[10]); + bwn_nphy_reset_cca(mac); + } else { + BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, regs[0]); + BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, regs[1]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[2]); + bwn_ntab_write(mac, BWN_NTAB16(8, 2), regs[3]); + bwn_ntab_write(mac, BWN_NTAB16(8, 18), regs[4]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[5]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[6]); + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ +static void bwn_nphy_tx_cal_phy_setup(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs; + uint16_t tmp; + + regs[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1); + regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2); + if (mac->mac_phy.rev >= 3) { + BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); + BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); + + tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1); + regs[2] = tmp; + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, tmp | 0x0600); + + tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); + regs[3] = tmp; + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp | 0x0600); + + regs[4] = BWN_PHY_READ(mac, BWN_NPHY_BBCFG); + BWN_PHY_MASK(mac, BWN_NPHY_BBCFG, + ~BWN_NPHY_BBCFG_RSTRX & 0xFFFF); + + tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 3)); + regs[5] = tmp; + bwn_ntab_write(mac, BWN_NTAB16(8, 3), 0); + + tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 19)); + regs[6] = tmp; + bwn_ntab_write(mac, BWN_NTAB16(8, 19), 0); + regs[7] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); + regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); + + if (!nphy->use_int_tx_iq_lo_cal) + bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA, + 1, 3); + else + bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA, + 0, 3); + bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 2, 1); + bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 8, 2); + + regs[9] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN0); + regs[10] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN1); + BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x0001); + BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x0001); + + tmp = bwn_nphy_read_lpf_ctl(mac, 0); + if (phy->rev >= 19) + bwn_nphy_rf_ctl_override_rev19(mac, 0x80, tmp, 0, false, + 1); + else if (phy->rev >= 7) + bwn_nphy_rf_ctl_override_rev7(mac, 0x80, tmp, 0, false, + 1); + + if (nphy->use_int_tx_iq_lo_cal && true /* FIXME */) { + if (phy->rev >= 19) { + bwn_nphy_rf_ctl_override_rev19(mac, 0x8, 0, 0x3, + false, 0); + } else if (phy->rev >= 8) { + bwn_nphy_rf_ctl_override_rev7(mac, 0x8, 0, 0x3, + false, 0); + } else if (phy->rev == 7) { + BWN_RF_SETMASK(mac, R2057_OVR_REG0, 1 << 4, 1 << 4); + if (bwn_current_band(mac) == BWN_BAND_2G) { + BWN_RF_SETMASK(mac, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); + BWN_RF_SETMASK(mac, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); + } else { + BWN_RF_SETMASK(mac, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); + BWN_RF_SETMASK(mac, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); + } + } + } + } else { + BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, 0xA000); + BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, 0xA000); + tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); + regs[2] = tmp; + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp | 0x3000); + tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 2)); + regs[3] = tmp; + tmp |= 0x2000; + bwn_ntab_write(mac, BWN_NTAB16(8, 2), tmp); + tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 18)); + regs[4] = tmp; + tmp |= 0x2000; + bwn_ntab_write(mac, BWN_NTAB16(8, 18), tmp); + regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); + regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); + if (bwn_current_band(mac) == BWN_BAND_5G) + tmp = 0x0180; + else + tmp = 0x0120; + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, tmp); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, tmp); + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ +static void bwn_nphy_save_cal(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + struct bwn_phy_n_iq_comp *rxcal_coeffs = NULL; + uint16_t *txcal_radio_regs = NULL; + struct bwn_chanspec *iqcal_chanspec; + uint16_t *table = NULL; + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 1); + + if (bwn_current_band(mac) == BWN_BAND_2G) { + rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; + txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; + iqcal_chanspec = &nphy->iqcal_chanspec_2G; + table = nphy->cal_cache.txcal_coeffs_2G; + } else { + rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; + txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; + iqcal_chanspec = &nphy->iqcal_chanspec_5G; + table = nphy->cal_cache.txcal_coeffs_5G; + } + + bwn_nphy_rx_iq_coeffs(mac, false, rxcal_coeffs); + /* TODO use some definitions */ + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 7) { + txcal_radio_regs[0] = BWN_RF_READ(mac, + R2057_TX0_LOFT_FINE_I); + txcal_radio_regs[1] = BWN_RF_READ(mac, + R2057_TX0_LOFT_FINE_Q); + txcal_radio_regs[4] = BWN_RF_READ(mac, + R2057_TX0_LOFT_COARSE_I); + txcal_radio_regs[5] = BWN_RF_READ(mac, + R2057_TX0_LOFT_COARSE_Q); + txcal_radio_regs[2] = BWN_RF_READ(mac, + R2057_TX1_LOFT_FINE_I); + txcal_radio_regs[3] = BWN_RF_READ(mac, + R2057_TX1_LOFT_FINE_Q); + txcal_radio_regs[6] = BWN_RF_READ(mac, + R2057_TX1_LOFT_COARSE_I); + txcal_radio_regs[7] = BWN_RF_READ(mac, + R2057_TX1_LOFT_COARSE_Q); + } else if (phy->rev >= 3) { + txcal_radio_regs[0] = BWN_RF_READ(mac, 0x2021); + txcal_radio_regs[1] = BWN_RF_READ(mac, 0x2022); + txcal_radio_regs[2] = BWN_RF_READ(mac, 0x3021); + txcal_radio_regs[3] = BWN_RF_READ(mac, 0x3022); + txcal_radio_regs[4] = BWN_RF_READ(mac, 0x2023); + txcal_radio_regs[5] = BWN_RF_READ(mac, 0x2024); + txcal_radio_regs[6] = BWN_RF_READ(mac, 0x3023); + txcal_radio_regs[7] = BWN_RF_READ(mac, 0x3024); + } else { + txcal_radio_regs[0] = BWN_RF_READ(mac, 0x8B); + txcal_radio_regs[1] = BWN_RF_READ(mac, 0xBA); + txcal_radio_regs[2] = BWN_RF_READ(mac, 0x8D); + txcal_radio_regs[3] = BWN_RF_READ(mac, 0xBC); + } + iqcal_chanspec->center_freq = bwn_get_centre_freq(mac); + iqcal_chanspec->channel_type = bwn_get_chan_type(mac, NULL); + bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 8, table); + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, 0); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ +static void bwn_nphy_restore_cal(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + + uint16_t coef[4]; + uint16_t *loft = NULL; + uint16_t *table = NULL; + + int i; + uint16_t *txcal_radio_regs = NULL; + struct bwn_phy_n_iq_comp *rxcal_coeffs = NULL; + + if (bwn_current_band(mac) == BWN_BAND_2G) { + if (!nphy->iqcal_chanspec_2G.center_freq) + return; + table = nphy->cal_cache.txcal_coeffs_2G; + loft = &nphy->cal_cache.txcal_coeffs_2G[5]; + } else { + if (!nphy->iqcal_chanspec_5G.center_freq) + return; + table = nphy->cal_cache.txcal_coeffs_5G; + loft = &nphy->cal_cache.txcal_coeffs_5G[5]; + } + + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 80), 4, table); + + for (i = 0; i < 4; i++) { + if (mac->mac_phy.rev >= 3) + table[i] = coef[i]; + else + coef[i] = 0; + } + + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4, coef); + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2, loft); + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2, loft); + + if (mac->mac_phy.rev < 2) + bwn_nphy_tx_iq_workaround(mac); + + if (bwn_current_band(mac) == BWN_BAND_2G) { + txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; + rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; + } else { + txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; + rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; + } + + /* TODO use some definitions */ + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 7) { + BWN_RF_WRITE(mac, R2057_TX0_LOFT_FINE_I, + txcal_radio_regs[0]); + BWN_RF_WRITE(mac, R2057_TX0_LOFT_FINE_Q, + txcal_radio_regs[1]); + BWN_RF_WRITE(mac, R2057_TX0_LOFT_COARSE_I, + txcal_radio_regs[4]); + BWN_RF_WRITE(mac, R2057_TX0_LOFT_COARSE_Q, + txcal_radio_regs[5]); + BWN_RF_WRITE(mac, R2057_TX1_LOFT_FINE_I, + txcal_radio_regs[2]); + BWN_RF_WRITE(mac, R2057_TX1_LOFT_FINE_Q, + txcal_radio_regs[3]); + BWN_RF_WRITE(mac, R2057_TX1_LOFT_COARSE_I, + txcal_radio_regs[6]); + BWN_RF_WRITE(mac, R2057_TX1_LOFT_COARSE_Q, + txcal_radio_regs[7]); + } else if (phy->rev >= 3) { + BWN_RF_WRITE(mac, 0x2021, txcal_radio_regs[0]); + BWN_RF_WRITE(mac, 0x2022, txcal_radio_regs[1]); + BWN_RF_WRITE(mac, 0x3021, txcal_radio_regs[2]); + BWN_RF_WRITE(mac, 0x3022, txcal_radio_regs[3]); + BWN_RF_WRITE(mac, 0x2023, txcal_radio_regs[4]); + BWN_RF_WRITE(mac, 0x2024, txcal_radio_regs[5]); + BWN_RF_WRITE(mac, 0x3023, txcal_radio_regs[6]); + BWN_RF_WRITE(mac, 0x3024, txcal_radio_regs[7]); + } else { + BWN_RF_WRITE(mac, 0x8B, txcal_radio_regs[0]); + BWN_RF_WRITE(mac, 0xBA, txcal_radio_regs[1]); + BWN_RF_WRITE(mac, 0x8D, txcal_radio_regs[2]); + BWN_RF_WRITE(mac, 0xBC, txcal_radio_regs[3]); + } + bwn_nphy_rx_iq_coeffs(mac, true, rxcal_coeffs); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ +static int bwn_nphy_cal_tx_iq_lo(struct bwn_mac *mac, + struct bwn_nphy_txgains target, + bool full, bool mphase) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + int i; + int error = 0; + int freq; + bool avoid = false; + uint8_t length; + uint16_t tmp, core, type, count, max, numb, last = 0, cmd; + const uint16_t *table; + bool phy6or5x; + + uint16_t buffer[11]; + uint16_t diq_start = 0; + uint16_t save[2]; + uint16_t gain[2]; + struct bwn_nphy_iqcal_params params[2]; + bool updated[2] = { }; + + bwn_nphy_stay_in_carrier_search(mac, true); + + if (mac->mac_phy.rev >= 4) { + avoid = nphy->hang_avoid; + nphy->hang_avoid = false; + } + + bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, save); + + for (i = 0; i < 2; i++) { + bwn_nphy_iq_cal_gain_params(mac, i, target, ¶ms[i]); + gain[i] = params[i].cal_gain; + } + + bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain); + + bwn_nphy_tx_cal_radio_setup(mac); + bwn_nphy_tx_cal_phy_setup(mac); + + phy6or5x = mac->mac_phy.rev >= 6 || + (mac->mac_phy.rev == 5 && nphy->ipa2g_on && + bwn_current_band(mac) == BWN_BAND_2G); + if (phy6or5x) { + if (bwn_is_40mhz(mac)) { + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 0), 18, + tbl_tx_iqlo_cal_loft_ladder_40); + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 32), 18, + tbl_tx_iqlo_cal_iqimb_ladder_40); + } else { + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 0), 18, + tbl_tx_iqlo_cal_loft_ladder_20); + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 32), 18, + tbl_tx_iqlo_cal_iqimb_ladder_20); + } + } + + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 7) { + BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); + } else { + BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); + } + + if (!bwn_is_40mhz(mac)) + freq = 2500; + else + freq = 5000; + + if (nphy->mphase_cal_phase_id > 2) + bwn_nphy_run_samples(mac, (bwn_is_40mhz(mac) ? 40 : 20) * 8, + 0xFFFF, 0, true, false, false); + else + error = bwn_nphy_tx_tone(mac, freq, 250, true, false, false); + + if (error == 0) { + if (nphy->mphase_cal_phase_id > 2) { + table = nphy->mphase_txcal_bestcoeffs; + length = 11; + if (mac->mac_phy.rev < 3) + length -= 2; + } else { + if (!full && nphy->txiqlocal_coeffsvalid) { + table = nphy->txiqlocal_bestc; + length = 11; + if (mac->mac_phy.rev < 3) + length -= 2; + } else { + full = true; + if (mac->mac_phy.rev >= 3) { + table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; + length = BWN_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; + } else { + table = tbl_tx_iqlo_cal_startcoefs; + length = BWN_NTAB_TX_IQLO_CAL_STARTCOEFS; + } + } + } + + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 64), length, table); + + if (full) { + if (mac->mac_phy.rev >= 3) + max = BWN_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; + else + max = BWN_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; + } else { + if (mac->mac_phy.rev >= 3) + max = BWN_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; + else + max = BWN_NTAB_TX_IQLO_CAL_CMDS_RECAL; + } + + if (mphase) { + count = nphy->mphase_txcal_cmdidx; + numb = min(max, + (uint16_t)(count + nphy->mphase_txcal_numcmds)); + } else { + count = 0; + numb = max; + } + + for (; count < numb; count++) { + if (full) { + if (mac->mac_phy.rev >= 3) + cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; + else + cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; + } else { + if (mac->mac_phy.rev >= 3) + cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; + else + cmd = tbl_tx_iqlo_cal_cmds_recal[count]; + } + + core = (cmd & 0x3000) >> 12; + type = (cmd & 0x0F00) >> 8; + + if (phy6or5x && updated[core] == 0) { + bwn_nphy_update_tx_cal_ladder(mac, core); + updated[core] = true; + } + + tmp = (params[core].ncorr[type] << 8) | 0x66; + BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDNNUM, tmp); + + if (type == 1 || type == 3 || type == 4) { + buffer[0] = bwn_ntab_read(mac, + BWN_NTAB16(15, 69 + core)); + diq_start = buffer[0]; + buffer[0] = 0; + bwn_ntab_write(mac, BWN_NTAB16(15, 69 + core), + 0); + } + + BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMD, cmd); + for (i = 0; i < 2000; i++) { + tmp = BWN_PHY_READ(mac, BWN_NPHY_IQLOCAL_CMD); + if (tmp & 0xC000) + break; + DELAY(10); + } + + bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length, + buffer); + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 64), length, + buffer); + + if (type == 1 || type == 3 || type == 4) + buffer[0] = diq_start; + } + + if (mphase) + nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; + + last = (mac->mac_phy.rev < 3) ? 6 : 7; + + if (!mphase || nphy->mphase_cal_phase_id == last) { + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 96), 4, buffer); + bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 4, buffer); + if (mac->mac_phy.rev < 3) { + buffer[0] = 0; + buffer[1] = 0; + buffer[2] = 0; + buffer[3] = 0; + } + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4, + buffer); + bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 101), 2, + buffer); + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2, + buffer); + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2, + buffer); + length = 11; + if (mac->mac_phy.rev < 3) + length -= 2; + bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length, + nphy->txiqlocal_bestc); + nphy->txiqlocal_coeffsvalid = true; + nphy->txiqlocal_chanspec.center_freq = + bwn_get_centre_freq(mac); + nphy->txiqlocal_chanspec.channel_type = bwn_get_chan_type(mac, NULL); + } else { + length = 11; + if (mac->mac_phy.rev < 3) + length -= 2; + bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length, + nphy->mphase_txcal_bestcoeffs); + } + + bwn_nphy_stop_playback(mac); + BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0); + } + + bwn_nphy_tx_cal_phy_cleanup(mac); + bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, save); + + if (mac->mac_phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) + bwn_nphy_tx_iq_workaround(mac); + + if (mac->mac_phy.rev >= 4) + nphy->hang_avoid = avoid; + + bwn_nphy_stay_in_carrier_search(mac, false); + + return error; +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ +static void bwn_nphy_reapply_tx_cal_coeffs(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + uint8_t i; + uint16_t buffer[7]; + bool equal = true; + + if (!nphy->txiqlocal_coeffsvalid || + nphy->txiqlocal_chanspec.center_freq != bwn_get_centre_freq(mac) || + nphy->txiqlocal_chanspec.channel_type != bwn_get_chan_type(mac, NULL)) + return; + + bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 7, buffer); + for (i = 0; i < 4; i++) { + if (buffer[i] != nphy->txiqlocal_bestc[i]) { + equal = false; + break; + } + } + + if (!equal) { + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 80), 4, + nphy->txiqlocal_bestc); + for (i = 0; i < 4; i++) + buffer[i] = 0; + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4, + buffer); + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2, + &nphy->txiqlocal_bestc[5]); + bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2, + &nphy->txiqlocal_bestc[5]); + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ +static int bwn_nphy_rev2_cal_rx_iq(struct bwn_mac *mac, + struct bwn_nphy_txgains target, uint8_t type, bool debug) +{ + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + int i, j, index; + uint8_t rfctl[2]; + uint8_t afectl_core; + uint16_t tmp[6]; + uint16_t cur_hpf1, cur_hpf2, cur_lna; + uint32_t real, imag; + bwn_band_t band; + + uint8_t use; + uint16_t cur_hpf; + uint16_t lna[3] = { 3, 3, 1 }; + uint16_t hpf1[3] = { 7, 2, 0 }; + uint16_t hpf2[3] = { 2, 0, 0 }; + uint32_t power[3] = { }; + uint16_t gain_save[2]; + uint16_t cal_gain[2]; + struct bwn_nphy_iqcal_params cal_params[2]; + struct bwn_nphy_iq_est est; + int ret = 0; + bool playtone = true; + int desired = 13; + + bwn_nphy_stay_in_carrier_search(mac, 1); + + if (mac->mac_phy.rev < 2) + bwn_nphy_reapply_tx_cal_coeffs(mac); + bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain_save); + for (i = 0; i < 2; i++) { + bwn_nphy_iq_cal_gain_params(mac, i, target, &cal_params[i]); + cal_gain[i] = cal_params[i].cal_gain; + } + bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, cal_gain); + + for (i = 0; i < 2; i++) { + if (i == 0) { + rfctl[0] = BWN_NPHY_RFCTL_INTC1; + rfctl[1] = BWN_NPHY_RFCTL_INTC2; + afectl_core = BWN_NPHY_AFECTL_C1; + } else { + rfctl[0] = BWN_NPHY_RFCTL_INTC2; + rfctl[1] = BWN_NPHY_RFCTL_INTC1; + afectl_core = BWN_NPHY_AFECTL_C2; + } + + tmp[1] = BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA); + tmp[2] = BWN_PHY_READ(mac, afectl_core); + tmp[3] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); + tmp[4] = BWN_PHY_READ(mac, rfctl[0]); + tmp[5] = BWN_PHY_READ(mac, rfctl[1]); + + BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, + ~BWN_NPHY_RFSEQCA_RXDIS & 0xFFFF, + ((1 - i) << BWN_NPHY_RFSEQCA_RXDIS_SHIFT)); + BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXEN, + (1 - i)); + BWN_PHY_SET(mac, afectl_core, 0x0006); + BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0006); + + band = bwn_current_band(mac); + + if (nphy->rxcalparams & 0xFF000000) { + if (band == BWN_BAND_5G) + BWN_PHY_WRITE(mac, rfctl[0], 0x140); + else + BWN_PHY_WRITE(mac, rfctl[0], 0x110); + } else { + if (band == BWN_BAND_5G) + BWN_PHY_WRITE(mac, rfctl[0], 0x180); + else + BWN_PHY_WRITE(mac, rfctl[0], 0x120); + } + + if (band == BWN_BAND_5G) + BWN_PHY_WRITE(mac, rfctl[1], 0x148); + else + BWN_PHY_WRITE(mac, rfctl[1], 0x114); + + if (nphy->rxcalparams & 0x10000) { + BWN_RF_SETMASK(mac, B2055_C1_GENSPARE2, 0xFC, + (i + 1)); + BWN_RF_SETMASK(mac, B2055_C2_GENSPARE2, 0xFC, + (2 - i)); + } + + for (j = 0; j < 4; j++) { + if (j < 3) { + cur_lna = lna[j]; + cur_hpf1 = hpf1[j]; + cur_hpf2 = hpf2[j]; + } else { + if (power[1] > 10000) { + use = 1; + cur_hpf = cur_hpf1; + index = 2; + } else { + if (power[0] > 10000) { + use = 1; + cur_hpf = cur_hpf1; + index = 1; + } else { + index = 0; + use = 2; + cur_hpf = cur_hpf2; + } + } + cur_lna = lna[index]; + cur_hpf1 = hpf1[index]; + cur_hpf2 = hpf2[index]; + cur_hpf += desired - bwn_hweight32(power[index]); + cur_hpf = bwn_clamp_val(cur_hpf, 0, 10); + if (use == 1) + cur_hpf1 = cur_hpf; + else + cur_hpf2 = cur_hpf; + } + + tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | + (cur_lna << 2)); + bwn_nphy_rf_ctl_override(mac, 0x400, tmp[0], 3, + false); + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); + bwn_nphy_stop_playback(mac); + + if (playtone) { + ret = bwn_nphy_tx_tone(mac, 4000, + (nphy->rxcalparams & 0xFFFF), + false, false, true); + playtone = false; + } else { + bwn_nphy_run_samples(mac, 160, 0xFFFF, 0, false, + false, true); + } + + if (ret == 0) { + if (j < 3) { + bwn_nphy_rx_iq_est(mac, &est, 1024, 32, + false); + if (i == 0) { + real = est.i0_pwr; + imag = est.q0_pwr; + } else { + real = est.i1_pwr; + imag = est.q1_pwr; + } + power[i] = ((real + imag) / 1024) + 1; + } else { + bwn_nphy_calc_rx_iq_comp(mac, 1 << i); + } + bwn_nphy_stop_playback(mac); + } + + if (ret != 0) + break; + } + + BWN_RF_MASK(mac, B2055_C1_GENSPARE2, 0xFC); + BWN_RF_MASK(mac, B2055_C2_GENSPARE2, 0xFC); + BWN_PHY_WRITE(mac, rfctl[1], tmp[5]); + BWN_PHY_WRITE(mac, rfctl[0], tmp[4]); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp[3]); + BWN_PHY_WRITE(mac, afectl_core, tmp[2]); + BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQCA, tmp[1]); + + if (ret != 0) + break; + } + + bwn_nphy_rf_ctl_override(mac, 0x400, 0, 3, true); + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); + bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain_save); + + bwn_nphy_stay_in_carrier_search(mac, 0); + + return ret; +} + +static int bwn_nphy_rev3_cal_rx_iq(struct bwn_mac *mac, + struct bwn_nphy_txgains target, uint8_t type, bool debug) +{ + return -1; +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ +static int bwn_nphy_cal_rx_iq(struct bwn_mac *mac, + struct bwn_nphy_txgains target, uint8_t type, bool debug) +{ + if (mac->mac_phy.rev >= 7) + type = 0; + + if (mac->mac_phy.rev >= 3) + return bwn_nphy_rev3_cal_rx_iq(mac, target, type, debug); + else + return bwn_nphy_rev2_cal_rx_iq(mac, target, type, debug); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */ +static void bwn_nphy_set_rx_core_state(struct bwn_mac *mac, uint8_t mask) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = phy->phy_n; + /* uint16_t buf[16]; it's rev3+ */ + + nphy->phyrxchain = mask; + + if (0 /* FIXME clk */) + return; + + bwn_mac_suspend(mac); + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, true); + + BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXEN, + (mask & 0x3) << BWN_NPHY_RFSEQCA_RXEN_SHIFT); + + if ((mask & 0x3) != 0x3) { + BWN_PHY_WRITE(mac, BWN_NPHY_HPANT_SWTHRES, 1); + if (mac->mac_phy.rev >= 3) { + /* TODO */ + } + } else { + BWN_PHY_WRITE(mac, BWN_NPHY_HPANT_SWTHRES, 0x1E); + if (mac->mac_phy.rev >= 3) { + /* TODO */ + } + } + + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); + + if (nphy->hang_avoid) + bwn_nphy_stay_in_carrier_search(mac, false); + + bwn_mac_enable(mac); +} + +bwn_txpwr_result_t +bwn_nphy_op_recalc_txpower(struct bwn_mac *mac, bool ignore_tssi) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + struct ieee80211_channel *channel = bwn_get_channel(mac); + struct bwn_softc *sc = mac->mac_sc; + struct bwn_ppr *ppr = &nphy->tx_pwr_max_ppr; + uint8_t max; /* qdBm */ + bool tx_pwr_state; + + if (nphy->tx_pwr_last_recalc_freq == bwn_get_centre_freq(mac) && + nphy->tx_pwr_last_recalc_limit == phy->txpower) + return BWN_TXPWR_RES_DONE; + + /* Make sure we have a clean PPR */ + bwn_ppr_clear(mac, ppr); + + /* HW limitations */ + bwn_ppr_load_max_from_sprom(mac, ppr, BWN_PHY_BAND_2G); + /* XXX TODO: other bands? */ + + /* Regulatory & user settings */ + max = INT_TO_Q52(bwn_get_chan_power(mac, channel)); + /* uint8_t */ + if (phy->txpower) + max = min(max, INT_TO_Q52(phy->txpower)); + bwn_ppr_apply_max(mac, ppr, max); + DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT_POWER, + "Calculated TX power: " Q52_FMT "\n", + Q52_ARG(bwn_ppr_get_max(mac, ppr))); + + /* TODO: Enable this once we get gains working */ +#if 0 + /* Some extra gains */ + hw_gain = 6; /* N-PHY specific */ + if (bwn_current_band(mac) == BWN_BAND_2G) + hw_gain += sprom->antenna_gain.a0; + else + hw_gain += sprom->antenna_gain.a1; + bwn_ppr_add(mac, ppr, -hw_gain); +#endif + + /* Make sure we didn't go too low */ + bwn_ppr_apply_min(mac, ppr, INT_TO_Q52(8)); + + /* Apply */ + tx_pwr_state = nphy->txpwrctrl; + bwn_mac_suspend(mac); + bwn_nphy_tx_power_ctl_setup(mac); + if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) { + BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, BWN_MACCTL_PHY_LOCK); + BWN_READ_4(mac, BWN_MACCTL); + DELAY(1); + } + bwn_nphy_tx_power_ctrl(mac, nphy->txpwrctrl); + if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) + BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_PHY_LOCK, 0); + bwn_mac_enable(mac); + + nphy->tx_pwr_last_recalc_freq = bwn_get_centre_freq(mac); + nphy->tx_pwr_last_recalc_limit = phy->txpower; + + return BWN_TXPWR_RES_DONE; +} + +/************************************************** + * N-PHY init + **************************************************/ + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ +static void bwn_nphy_update_mimo_config(struct bwn_mac *mac, int32_t preamble) +{ + uint16_t mimocfg = BWN_PHY_READ(mac, BWN_NPHY_MIMOCFG); + + mimocfg |= BWN_NPHY_MIMOCFG_AUTO; + if (preamble == 1) + mimocfg |= BWN_NPHY_MIMOCFG_GFMIX; + else + mimocfg &= ~BWN_NPHY_MIMOCFG_GFMIX; + + BWN_PHY_WRITE(mac, BWN_NPHY_MIMOCFG, mimocfg); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */ +static void bwn_nphy_bphy_init(struct bwn_mac *mac) +{ + unsigned int i; + uint16_t val; + + val = 0x1E1F; + for (i = 0; i < 16; i++) { + BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x88 + i), val); + val -= 0x202; + } + val = 0x3E3F; + for (i = 0; i < 16; i++) { + BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x98 + i), val); + val -= 0x202; + } + BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x38), 0x668); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ +static void bwn_nphy_superswitch_init(struct bwn_mac *mac, bool init) +{ + struct bwn_softc *sc = mac->mac_sc; + + if (mac->mac_phy.rev >= 7) + return; + + if (mac->mac_phy.rev >= 3) { + if (!init) + return; + if (0 /* FIXME */) { + bwn_ntab_write(mac, BWN_NTAB16(9, 2), 0x211); + bwn_ntab_write(mac, BWN_NTAB16(9, 3), 0x222); + bwn_ntab_write(mac, BWN_NTAB16(9, 8), 0x144); + bwn_ntab_write(mac, BWN_NTAB16(9, 12), 0x188); + } + } else { + BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_LOOEN, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_HIOEN, 0); + + /* XXX handle bhnd bus */ + if (bwn_is_bus_siba(mac)) { + siba_gpio_set(sc->sc_dev, 0xfc00); + } + + BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_GPOUT_MASK, 0); + BWN_WRITE_SETMASK2(mac, BWN_GPIO_MASK, ~0, 0xFC00); + BWN_WRITE_SETMASK2(mac, BWN_GPIO_CONTROL, (~0xFC00 & 0xFFFF), + 0); + + if (init) { + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); + } + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */ +static int bwn_phy_initn(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = phy->phy_n; + uint8_t tx_pwr_state; + struct bwn_nphy_txgains target; + uint16_t tmp; + bwn_band_t tmp2; + bool do_rssi_cal; + + uint16_t clip[2]; + bool do_cal = false; + + if ((mac->mac_phy.rev >= 3) && + (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) && + (bwn_current_band(mac) == BWN_BAND_2G)) { + /* XXX bhnd bus */ + if (bwn_is_bus_siba(mac)) { + siba_cc_set32(sc->sc_dev, SIBA_CC_CHIPCTL, 0x40); + } + } + nphy->use_int_tx_iq_lo_cal = bwn_nphy_ipa(mac) || + phy->rev >= 7 || + (phy->rev >= 5 && + siba_sprom_get_bf2_hi(sc->sc_dev) & BWN_BFH2_INTERNDET_TXIQCAL); + nphy->deaf_count = 0; + bwn_nphy_tables_init(mac); + nphy->crsminpwr_adjusted = false; + nphy->noisevars_adjusted = false; + + /* Clear all overrides */ + if (mac->mac_phy.rev >= 3) { + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S1, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, 0); + if (phy->rev >= 7) { + BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER4, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER5, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER6, 0); + } + if (phy->rev >= 19) { + /* TODO */ + } + + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S0, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S1, 0); + } else { + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, 0); + } + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, 0); + if (mac->mac_phy.rev < 6) { + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC3, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC4, 0); + } + BWN_PHY_MASK(mac, BWN_NPHY_RFSEQMODE, + ~(BWN_NPHY_RFSEQMODE_CAOVER | + BWN_NPHY_RFSEQMODE_TROVER)); + if (mac->mac_phy.rev >= 3) + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, 0); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, 0); + + if (mac->mac_phy.rev <= 2) { + tmp = (mac->mac_phy.rev == 2) ? 0x3B : 0x40; + BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, + ~BWN_NPHY_BPHY_CTL3_SCALE, + tmp << BWN_NPHY_BPHY_CTL3_SCALE_SHIFT); + } + BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); + BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); + + if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_SKWRKFEM_BRD || + (siba_get_pci_subvendor(sc->sc_dev) == PCI_VENDOR_APPLE && + siba_get_pci_subdevice(sc->sc_dev) == BCMA_BOARD_TYPE_BCM943224M93)) + BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xA0); + else + BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xB8); + BWN_PHY_WRITE(mac, BWN_NPHY_MIMO_CRSTXEXT, 0xC8); + BWN_PHY_WRITE(mac, BWN_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); + BWN_PHY_WRITE(mac, BWN_NPHY_TXRIFS_FRDEL, 0x30); + + if (phy->rev < 8) + bwn_nphy_update_mimo_config(mac, nphy->preamble_override); + + bwn_nphy_update_txrx_chain(mac); + + if (phy->rev < 2) { + BWN_PHY_WRITE(mac, BWN_NPHY_DUP40_GFBL, 0xAA8); + BWN_PHY_WRITE(mac, BWN_NPHY_DUP40_BL, 0x9A4); + } + + tmp2 = bwn_current_band(mac); + if (bwn_nphy_ipa(mac)) { + BWN_PHY_SET(mac, BWN_NPHY_PAPD_EN0, 0x1); + BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_TABLE_ADJ0, 0x007F, + nphy->papd_epsilon_offset[0] << 7); + BWN_PHY_SET(mac, BWN_NPHY_PAPD_EN1, 0x1); + BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_TABLE_ADJ1, 0x007F, + nphy->papd_epsilon_offset[1] << 7); + bwn_nphy_int_pa_set_tx_dig_filters(mac); + } else if (phy->rev >= 5) { + bwn_nphy_ext_pa_set_tx_dig_filters(mac); + } + + bwn_nphy_workarounds(mac); + + /* Reset CCA, in init code it differs a little from standard way */ + bwn_phy_force_clock(mac, 1); + tmp = BWN_PHY_READ(mac, BWN_NPHY_BBCFG); + BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, tmp | BWN_NPHY_BBCFG_RSTCCA); + BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, tmp & ~BWN_NPHY_BBCFG_RSTCCA); + bwn_phy_force_clock(mac, 0); + + bwn_mac_phy_clock_set(mac, true); + + if (phy->rev < 7) { + bwn_nphy_pa_override(mac, false); + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RX2TX); + bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); + bwn_nphy_pa_override(mac, true); + } + + bwn_nphy_classifier(mac, 0, 0); + bwn_nphy_read_clip_detection(mac, clip); + if (bwn_current_band(mac) == BWN_BAND_2G) + bwn_nphy_bphy_init(mac); + + tx_pwr_state = nphy->txpwrctrl; + bwn_nphy_tx_power_ctrl(mac, false); + bwn_nphy_tx_power_fix(mac); + bwn_nphy_tx_power_ctl_idle_tssi(mac); + bwn_nphy_tx_power_ctl_setup(mac); + bwn_nphy_tx_gain_table_upload(mac); + + if (nphy->phyrxchain != 3) + bwn_nphy_set_rx_core_state(mac, nphy->phyrxchain); + if (nphy->mphase_cal_phase_id > 0) + ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ + + do_rssi_cal = false; + if (phy->rev >= 3) { + if (bwn_current_band(mac) == BWN_BAND_2G) + do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq; + else + do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq; + + if (do_rssi_cal) + bwn_nphy_rssi_cal(mac); + else + bwn_nphy_restore_rssi_cal(mac); + } else { + bwn_nphy_rssi_cal(mac); + } + + if (!((nphy->measure_hold & 0x6) != 0)) { + if (bwn_current_band(mac) == BWN_BAND_2G) + do_cal = !nphy->iqcal_chanspec_2G.center_freq; + else + do_cal = !nphy->iqcal_chanspec_5G.center_freq; + + if (nphy->mute) + do_cal = false; + + if (do_cal) { + target = bwn_nphy_get_tx_gains(mac); + + if (nphy->antsel_type == 2) + bwn_nphy_superswitch_init(mac, true); + if (nphy->perical != 2) { + bwn_nphy_rssi_cal(mac); + if (phy->rev >= 3) { + nphy->cal_orig_pwr_idx[0] = + nphy->txpwrindex[0].index_internal; + nphy->cal_orig_pwr_idx[1] = + nphy->txpwrindex[1].index_internal; + /* TODO N PHY Pre Calibrate TX Gain */ + target = bwn_nphy_get_tx_gains(mac); + } + if (!bwn_nphy_cal_tx_iq_lo(mac, target, true, false)) + if (bwn_nphy_cal_rx_iq(mac, target, 2, 0) == 0) + bwn_nphy_save_cal(mac); + } else if (nphy->mphase_cal_phase_id == 0) + ;/* N PHY Periodic Calibration with arg 3 */ + } else { + bwn_nphy_restore_cal(mac); + } + } + + bwn_nphy_tx_pwr_ctrl_coef_setup(mac); + bwn_nphy_tx_power_ctrl(mac, tx_pwr_state); + BWN_PHY_WRITE(mac, BWN_NPHY_TXMACIF_HOLDOFF, 0x0015); + BWN_PHY_WRITE(mac, BWN_NPHY_TXMACDELAY, 0x0320); + if (phy->rev >= 3 && phy->rev <= 6) + BWN_PHY_WRITE(mac, BWN_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032); + bwn_nphy_tx_lpf_bw(mac); + if (phy->rev >= 3) + bwn_nphy_spur_workaround(mac); + + return 0; +} + +/************************************************** + * Channel switching ops. + **************************************************/ + +static void bwn_chantab_phy_upload(struct bwn_mac *mac, + const struct bwn_phy_n_sfo_cfg *e) +{ + BWN_PHY_WRITE(mac, BWN_NPHY_BW1A, e->phy_bw1a); + BWN_PHY_WRITE(mac, BWN_NPHY_BW2, e->phy_bw2); + BWN_PHY_WRITE(mac, BWN_NPHY_BW3, e->phy_bw3); + BWN_PHY_WRITE(mac, BWN_NPHY_BW4, e->phy_bw4); + BWN_PHY_WRITE(mac, BWN_NPHY_BW5, e->phy_bw5); + BWN_PHY_WRITE(mac, BWN_NPHY_BW6, e->phy_bw6); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */ +static void bwn_nphy_pmu_spur_avoid(struct bwn_mac *mac, bool avoid) +{ + struct bwn_softc *sc = mac->mac_sc; + + /* XXX bhnd */ + if (bwn_is_bus_siba(mac)) { + DPRINTF(sc, BWN_DEBUG_RESET, "%s: spuravoid %d\n", __func__, avoid); + siba_pmu_spuravoid_pllupdate(sc->sc_dev, avoid); + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */ +static void bwn_nphy_channel_setup(struct bwn_mac *mac, + const struct bwn_phy_n_sfo_cfg *e, + struct ieee80211_channel *new_channel) +{ + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = mac->mac_phy.phy_n; + int ch = new_channel->ic_ieee; + uint16_t tmp16; + + if (bwn_channel_band(mac, new_channel) == BWN_BAND_5G) { + DPRINTF(sc, BWN_DEBUG_RESET, "%s: BAND_5G; chan=%d\n", __func__, ch); + /* Switch to 2 GHz for a moment to access BWN_PHY_B_BBCFG */ + BWN_PHY_MASK(mac, BWN_NPHY_BANDCTL, ~BWN_NPHY_BANDCTL_5GHZ); + + tmp16 = BWN_READ_2(mac, BWN_PSM_PHY_HDR); + BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16 | 4); + /* Put BPHY in the reset */ + BWN_PHY_SET(mac, BWN_PHY_B_BBCFG, + BWN_PHY_B_BBCFG_RSTCCA | BWN_PHY_B_BBCFG_RSTRX); + BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16); + BWN_PHY_SET(mac, BWN_NPHY_BANDCTL, BWN_NPHY_BANDCTL_5GHZ); + } else if (bwn_channel_band(mac, new_channel) == BWN_BAND_2G) { + DPRINTF(sc, BWN_DEBUG_RESET, "%s: BAND_2G; chan=%d\n", __func__, ch); + BWN_PHY_MASK(mac, BWN_NPHY_BANDCTL, ~BWN_NPHY_BANDCTL_5GHZ); + tmp16 = BWN_READ_2(mac, BWN_PSM_PHY_HDR); + BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16 | 4); + /* Take BPHY out of the reset */ + BWN_PHY_MASK(mac, BWN_PHY_B_BBCFG, + (uint16_t)~(BWN_PHY_B_BBCFG_RSTCCA | BWN_PHY_B_BBCFG_RSTRX)); + BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16); + } else { + BWN_ERRPRINTF(mac->mac_sc, "%s: unknown band?\n", __func__); + } + + bwn_chantab_phy_upload(mac, e); + + if (new_channel->ic_ieee == 14) { + bwn_nphy_classifier(mac, 2, 0); + BWN_PHY_SET(mac, BWN_PHY_B_TEST, 0x0800); + } else { + bwn_nphy_classifier(mac, 2, 2); + if (bwn_channel_band(mac, new_channel) == BWN_BAND_2G) + BWN_PHY_MASK(mac, BWN_PHY_B_TEST, ~0x840); + } + + if (!nphy->txpwrctrl) + bwn_nphy_tx_power_fix(mac); + + if (mac->mac_phy.rev < 3) + bwn_nphy_adjust_lna_gain_table(mac); + + bwn_nphy_tx_lpf_bw(mac); + + if (mac->mac_phy.rev >= 3 && + mac->mac_phy.phy_n->spur_avoid != BWN_SPUR_AVOID_DISABLE) { + uint8_t spuravoid = 0; + + if (mac->mac_phy.phy_n->spur_avoid == BWN_SPUR_AVOID_FORCE) { + spuravoid = 1; + } else if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 18) { + /* TODO */ + } else if (phy->rev >= 17) { + /* TODO: Off for channels 1-11, but check 12-14! */ + } else if (phy->rev >= 16) { + /* TODO: Off for 2 GHz, but check 5 GHz! */ + } else if (phy->rev >= 7) { + if (!bwn_is_40mhz(mac)) { /* 20MHz */ + if (ch == 13 || ch == 14 || ch == 153) + spuravoid = 1; + } else { /* 40 MHz */ + if (ch == 54) + spuravoid = 1; + } + } else { + if (!bwn_is_40mhz(mac)) { /* 20MHz */ + if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14) + spuravoid = 1; + } else { /* 40MHz */ + if (nphy->aband_spurwar_en && + (ch == 38 || ch == 102 || ch == 118)) + spuravoid = siba_get_chipid(sc->sc_dev) == 0x4716; + } + } + + bwn_nphy_pmu_spur_avoid(mac, spuravoid); + + bwn_mac_switch_freq(mac, spuravoid); + + if (mac->mac_phy.rev == 3 || mac->mac_phy.rev == 4) + bwn_wireless_core_phy_pll_reset(mac); + + if (spuravoid) + BWN_PHY_SET(mac, BWN_NPHY_BBCFG, BWN_NPHY_BBCFG_RSTRX); + else + BWN_PHY_MASK(mac, BWN_NPHY_BBCFG, + ~BWN_NPHY_BBCFG_RSTRX & 0xFFFF); + + bwn_nphy_reset_cca(mac); + + /* wl sets useless phy_isspuravoid here */ + } + + BWN_PHY_WRITE(mac, BWN_NPHY_NDATAT_DUP40, 0x3830); + + if (phy->rev >= 3) + bwn_nphy_spur_workaround(mac); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */ +static int bwn_nphy_set_channel(struct bwn_mac *mac, + struct ieee80211_channel *channel, + bwn_chan_type_t channel_type) +{ + struct bwn_phy *phy = &mac->mac_phy; + + const struct bwn_nphy_channeltab_entry_rev2 *tabent_r2 = NULL; + const struct bwn_nphy_channeltab_entry_rev3 *tabent_r3 = NULL; + const struct bwn_nphy_chantabent_rev7 *tabent_r7 = NULL; + const struct bwn_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL; + + uint8_t tmp; + + if (phy->rev >= 19) { + return -ESRCH; + /* TODO */ + } else if (phy->rev >= 7) { + r2057_get_chantabent_rev7(mac, bwn_get_chan_centre_freq(mac, channel), + &tabent_r7, &tabent_r7_2g); + if (!tabent_r7 && !tabent_r7_2g) + return -ESRCH; + } else if (phy->rev >= 3) { + tabent_r3 = bwn_nphy_get_chantabent_rev3(mac, + bwn_get_chan_centre_freq(mac, channel)); + if (!tabent_r3) + return -ESRCH; + } else { + tabent_r2 = bwn_nphy_get_chantabent_rev2(mac, + channel->ic_ieee); + if (!tabent_r2) + return -ESRCH; + } + + /* Channel is set later in common code, but we need to set it on our + own to let this function's subcalls work properly. */ +#if 0 + phy->channel = channel->ic_ieee; +#endif + +#if 0 + if (bwn_channel_type_is_40mhz(phy->channel_type) != + bwn_channel_type_is_40mhz(channel_type)) + ; /* TODO: BMAC BW Set (channel_type) */ +#endif + + if (channel_type == BWN_CHAN_TYPE_40_HT_U) { + BWN_PHY_SET(mac, BWN_NPHY_RXCTL, BWN_NPHY_RXCTL_BSELU20); + if (phy->rev >= 7) + BWN_PHY_SET(mac, 0x310, 0x8000); + } else if (channel_type == BWN_CHAN_TYPE_40_HT_D) { + BWN_PHY_MASK(mac, BWN_NPHY_RXCTL, ~BWN_NPHY_RXCTL_BSELU20); + if (phy->rev >= 7) + BWN_PHY_MASK(mac, 0x310, (uint16_t)~0x8000); + } + + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 7) { + const struct bwn_phy_n_sfo_cfg *phy_regs = tabent_r7 ? + &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs); + + if (phy->rf_rev <= 4 || phy->rf_rev == 6) { + tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 2 : 0; + BWN_RF_SETMASK(mac, R2057_TIA_CONFIG_CORE0, ~2, tmp); + BWN_RF_SETMASK(mac, R2057_TIA_CONFIG_CORE1, ~2, tmp); + } + + bwn_radio_2057_setup(mac, tabent_r7, tabent_r7_2g); + bwn_nphy_channel_setup(mac, phy_regs, channel); + } else if (phy->rev >= 3) { + tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 4 : 0; + BWN_RF_SETMASK(mac, 0x08, 0xFFFB, tmp); + bwn_radio_2056_setup(mac, tabent_r3); + bwn_nphy_channel_setup(mac, &(tabent_r3->phy_regs), channel); + } else { + tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 0x0020 : 0x0050; + BWN_RF_SETMASK(mac, B2055_MASTER1, 0xFF8F, tmp); + bwn_radio_2055_setup(mac, tabent_r2); + bwn_nphy_channel_setup(mac, &(tabent_r2->phy_regs), channel); + } + + return 0; +} + +/************************************************** + * Basic PHY ops. + **************************************************/ + +int +bwn_nphy_op_allocate(struct bwn_mac *mac) +{ + struct bwn_phy_n *nphy; + + nphy = malloc(sizeof(*nphy), M_DEVBUF, M_ZERO | M_NOWAIT); + if (!nphy) + return -ENOMEM; + + mac->mac_phy.phy_n = nphy; + + return 0; +} + +void +bwn_nphy_op_prepare_structs(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = phy->phy_n; + + memset(nphy, 0, sizeof(*nphy)); + + nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4); + nphy->spur_avoid = (phy->rev >= 3) ? + BWN_SPUR_AVOID_AUTO : BWN_SPUR_AVOID_DISABLE; + nphy->gain_boost = true; /* this way we follow wl, assume it is true */ + nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ + nphy->phyrxchain = 3; /* to avoid bwn_nphy_set_rx_core_state like wl */ + nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */ + /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is + * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */ + nphy->tx_pwr_idx[0] = 128; + nphy->tx_pwr_idx[1] = 128; + + /* Hardware TX power control and 5GHz power gain */ + nphy->txpwrctrl = false; + nphy->pwg_gain_5ghz = false; + if (mac->mac_phy.rev >= 3 || + (siba_get_pci_subvendor(sc->sc_dev) == PCI_VENDOR_APPLE && + (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12))) { + nphy->txpwrctrl = true; + nphy->pwg_gain_5ghz = true; + } else if (siba_sprom_get_rev(sc->sc_dev) >= 4) { + if (mac->mac_phy.rev >= 2 && + (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_TXPWRCTRL_EN)) { + nphy->txpwrctrl = true; +#ifdef CONFIG_BWN_SSB + if (dev->dev->bus_type == BWN_BUS_SSB && + dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) { + struct pci_dev *pdev = + dev->dev->sdev->bus->host_pci; + if (pdev->device == 0x4328 || + pdev->device == 0x432a) + nphy->pwg_gain_5ghz = true; + } +#endif + } else if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_5G_PWRGAIN) { + nphy->pwg_gain_5ghz = true; + } + } + + if (mac->mac_phy.rev >= 3) { + nphy->ipa2g_on = siba_sprom_get_fem_2ghz_extpa_gain(sc->sc_dev) == 2; + nphy->ipa5g_on = siba_sprom_get_fem_5ghz_extpa_gain(sc->sc_dev) == 2; + } +} + +void +bwn_nphy_op_free(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_phy_n *nphy = phy->phy_n; + + free(nphy, M_DEVBUF); + phy->phy_n = NULL; +} + +int +bwn_nphy_op_init(struct bwn_mac *mac) +{ + return bwn_phy_initn(mac); +} + +static inline void check_phyreg(struct bwn_mac *mac, uint16_t offset) +{ +#ifdef BWN_DEBUG + if ((offset & BWN_PHYROUTE_MASK) == BWN_PHYROUTE_OFDM_GPHY) { + /* OFDM registers are onnly available on A/G-PHYs */ + BWN_ERRPRINTF(mac->mac_sc, "Invalid OFDM PHY access at " + "0x%04X on N-PHY\n", offset); + } + if ((offset & BWN_PHYROUTE_MASK) == BWN_PHYROUTE_EXT_GPHY) { + /* Ext-G registers are only available on G-PHYs */ + BWN_ERRPRINTF(mac->mac_sc, "Invalid EXT-G PHY access at " + "0x%04X on N-PHY\n", offset); + } +#endif /* BWN_DEBUG */ +} + +void +bwn_nphy_op_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask, + uint16_t set) +{ + check_phyreg(mac, reg); + BWN_WRITE_2_F(mac, BWN_PHYCTL, reg); + BWN_WRITE_SETMASK2(mac, BWN_PHYDATA, mask, set); +} + +#if 0 +uint16_t +bwn_nphy_op_radio_read(struct bwn_mac *mac, uint16_t reg) +{ + /* Register 1 is a 32-bit register. */ + if (mac->mac_phy.rev < 7 && reg == 1) { + BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__); + } + + if (mac->mac_phy.rev >= 7) + reg |= 0x200; /* Radio 0x2057 */ + else + reg |= 0x100; + + BWN_WRITE_2_F(mac, BWN_RFCTL, reg); + return BWN_READ_2(mac, BWN_RFDATALO); +} +#endif + +#if 0 +void +bwn_nphy_op_radio_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) +{ + /* Register 1 is a 32-bit register. */ + if (mac->mac_phy.rev < 7 && reg == 1) { + BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__); + } + + BWN_WRITE_2_F(mac, BWN_RFCTL, reg); + BWN_WRITE_2(mac, BWN_RFDATALO, value); +} +#endif + +/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ +void +bwn_nphy_op_software_rfkill(struct bwn_mac *mac, bool active) +{ + struct bwn_phy *phy = &mac->mac_phy; + + if (BWN_READ_4(mac, BWN_MACCTL) & BWN_MACCTL_ON) + BWN_ERRPRINTF(mac->mac_sc, "MAC not suspended\n"); + + DPRINTF(mac->mac_sc, BWN_DEBUG_RESET | BWN_DEBUG_PHY, + "%s: called; rev=%d, rf_on=%d, active=%d\n", __func__, + phy->rev, mac->mac_phy.rf_on, active); + + /* + * XXX TODO: don't bother doing RF programming if it's + * already done. But, bwn(4) currently sets rf_on in the + * PHY setup and leaves it on after startup, which causes + * the below to not init the 2056/2057 radios. + */ + if (active) { + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 7) { +// if (!mac->mac_phy.rf_on) + bwn_radio_2057_init(mac); + bwn_switch_channel(mac, bwn_get_chan(mac)); + } else if (phy->rev >= 3) { +// if (!mac->mac_phy.rf_on) + bwn_radio_init2056(mac); + bwn_switch_channel(mac, bwn_get_chan(mac)); + } else { + bwn_radio_init2055(mac); + } + } else { + if (phy->rev >= 19) { + /* TODO */ + } else if (phy->rev >= 8) { + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, + ~BWN_NPHY_RFCTL_CMD_CHIP0PU); + } else if (phy->rev >= 7) { + /* Nothing needed */ + } else if (phy->rev >= 3) { + BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, + ~BWN_NPHY_RFCTL_CMD_CHIP0PU); + + BWN_RF_MASK(mac, 0x09, ~0x2); + + BWN_RF_WRITE(mac, 0x204D, 0); + BWN_RF_WRITE(mac, 0x2053, 0); + BWN_RF_WRITE(mac, 0x2058, 0); + BWN_RF_WRITE(mac, 0x205E, 0); + BWN_RF_MASK(mac, 0x2062, ~0xF0); + BWN_RF_WRITE(mac, 0x2064, 0); + + BWN_RF_WRITE(mac, 0x304D, 0); + BWN_RF_WRITE(mac, 0x3053, 0); + BWN_RF_WRITE(mac, 0x3058, 0); + BWN_RF_WRITE(mac, 0x305E, 0); + BWN_RF_MASK(mac, 0x3062, ~0xF0); + BWN_RF_WRITE(mac, 0x3064, 0); + } + } +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */ +void +bwn_nphy_op_switch_analog(struct bwn_mac *mac, bool on) +{ + struct bwn_phy *phy = &mac->mac_phy; + uint16_t override = on ? 0x0 : 0x7FFF; + uint16_t core = on ? 0xD : 0x00FD; + + if (phy->rev >= 19) { + /* TODO */ + device_printf(mac->mac_sc->sc_dev, "%s: TODO\n", __func__); + } else if (phy->rev >= 3) { + if (on) { + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, core); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, override); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, core); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override); + } else { + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, override); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, core); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override); + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, core); + } + } else { + BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override); + } +} + +int +bwn_nphy_op_switch_channel(struct bwn_mac *mac, unsigned int new_channel) +{ + struct ieee80211_channel *channel = bwn_get_channel(mac); + bwn_chan_type_t channel_type = bwn_get_chan_type(mac, NULL); + + if (bwn_current_band(mac) == BWN_BAND_2G) { + if ((new_channel < 1) || (new_channel > 14)) + return -EINVAL; + } else { + if (new_channel > 200) + return -EINVAL; + } + + return bwn_nphy_set_channel(mac, channel, channel_type); +} + +#if 0 +unsigned int +bwn_nphy_op_get_default_chan(struct bwn_mac *mac) +{ + if (bwn_current_band(mac) == BWN_BAND_2G) + return 1; + return 36; +} +#endif diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h new file mode 100644 index 0000000..3876a3e --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h @@ -0,0 +1,181 @@ +/* + + Broadcom B43 wireless driver + + N-PHY core code. + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + Copyright (c) 2016 Adrian Chadd <adrian@FreeBSD.org> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +/* + * $FreeBSD$ + */ + +#ifndef __IF_BWN_PHY_N_CORE_H__ +#define __IF_BWN_PHY_N_CORE_H__ + +struct bwn_mac; + +enum b43_nphy_spur_avoid { + BWN_SPUR_AVOID_DISABLE, + BWN_SPUR_AVOID_AUTO, + BWN_SPUR_AVOID_FORCE, +}; + +/* + * TODO: determine whether center_freq is the primary + * channel centre frequency or the actual centre centre + * frequency (eg radio tuning.) It /looks/ like it's + * actual channel centre. + */ +struct bwn_chanspec { + uint16_t center_freq; + /* This is HT40U, HT40D, HT20, no-HT 20, etc */ + bwn_chan_type_t channel_type; +}; + +struct bwn_phy_n_iq_comp { + int16_t a0; + int16_t b0; + int16_t a1; + int16_t b1; +}; + +struct bwn_phy_n_rssical_cache { + uint16_t rssical_radio_regs_2G[2]; + uint16_t rssical_phy_regs_2G[12]; + + uint16_t rssical_radio_regs_5G[2]; + uint16_t rssical_phy_regs_5G[12]; +}; + +struct bwn_phy_n_cal_cache { + uint16_t txcal_radio_regs_2G[8]; + uint16_t txcal_coeffs_2G[8]; + struct bwn_phy_n_iq_comp rxcal_coeffs_2G; + + uint16_t txcal_radio_regs_5G[8]; + uint16_t txcal_coeffs_5G[8]; + struct bwn_phy_n_iq_comp rxcal_coeffs_5G; +}; + +struct bwn_phy_n_txpwrindex { + int8_t index; + int8_t index_internal; + int8_t index_internal_save; + uint16_t AfectrlOverride; + uint16_t AfeCtrlDacGain; + uint16_t rad_gain; + uint8_t bbmult; + uint16_t iqcomp_a; + uint16_t iqcomp_b; + uint16_t locomp; +}; + +struct bwn_phy_n_pwr_ctl_info { + uint8_t idle_tssi_2g; + uint8_t idle_tssi_5g; +}; + +struct bwn_phy_n { + uint8_t antsel_type; + uint8_t cal_orig_pwr_idx[2]; + uint8_t measure_hold; + uint8_t phyrxchain; + uint8_t hw_phyrxchain; + uint8_t hw_phytxchain; + uint8_t perical; + uint32_t deaf_count; + uint32_t rxcalparams; + bool hang_avoid; + bool mute; + uint16_t papd_epsilon_offset[2]; + int32_t preamble_override; + uint32_t bb_mult_save; + + bool gain_boost; + bool elna_gain_config; + bool band5g_pwrgain; + bool use_int_tx_iq_lo_cal; + bool lpf_bw_overrode_for_sample_play; + + uint8_t mphase_cal_phase_id; + uint16_t mphase_txcal_cmdidx; + uint16_t mphase_txcal_numcmds; + uint16_t mphase_txcal_bestcoeffs[11]; + + bool txpwrctrl; + bool pwg_gain_5ghz; + uint8_t tx_pwr_idx[2]; + int8_t tx_power_offset[101]; + uint16_t adj_pwr_tbl[84]; + uint16_t txcal_bbmult; + uint16_t txiqlocal_bestc[11]; + bool txiqlocal_coeffsvalid; + struct bwn_phy_n_txpwrindex txpwrindex[2]; + struct bwn_phy_n_pwr_ctl_info pwr_ctl_info[2]; + struct bwn_chanspec txiqlocal_chanspec; + struct bwn_ppr tx_pwr_max_ppr; + uint16_t tx_pwr_last_recalc_freq; + int tx_pwr_last_recalc_limit; + + uint8_t txrx_chain; + uint16_t tx_rx_cal_phy_saveregs[11]; + uint16_t tx_rx_cal_radio_saveregs[22]; + + uint16_t rfctrl_intc1_save; + uint16_t rfctrl_intc2_save; + + uint16_t classifier_state; + uint16_t clip_state[2]; + + enum b43_nphy_spur_avoid spur_avoid; + bool aband_spurwar_en; + bool gband_spurwar_en; + + bool ipa2g_on; + struct bwn_chanspec iqcal_chanspec_2G; + struct bwn_chanspec rssical_chanspec_2G; + + bool ipa5g_on; + struct bwn_chanspec iqcal_chanspec_5G; + struct bwn_chanspec rssical_chanspec_5G; + + struct bwn_phy_n_rssical_cache rssical_cache; + struct bwn_phy_n_cal_cache cal_cache; + bool crsminpwr_adjusted; + bool noisevars_adjusted; +}; + +extern bwn_txpwr_result_t bwn_nphy_op_recalc_txpower(struct bwn_mac *mac, bool ignore_tssi); +extern int bwn_nphy_op_allocate(struct bwn_mac *mac); +extern void bwn_nphy_op_prepare_structs(struct bwn_mac *mac); +extern void bwn_nphy_op_free(struct bwn_mac *mac); +extern int bwn_nphy_op_init(struct bwn_mac *mac); +extern void bwn_nphy_op_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask, uint16_t set); +extern uint16_t bwn_nphy_op_radio_read(struct bwn_mac *mac, uint16_t reg); +extern void bwn_nphy_op_radio_write(struct bwn_mac *mac, uint16_t reg, uint16_t value); +extern void bwn_nphy_op_software_rfkill(struct bwn_mac *mac, bool blocked); +extern void bwn_nphy_op_switch_analog(struct bwn_mac *mac, bool on); +extern int bwn_nphy_op_switch_channel(struct bwn_mac *mac, unsigned int new_channel); +extern unsigned int bwn_nphy_op_get_default_chan(struct bwn_mac *mac); + +#endif /* __IF_BWN_PHY_N_CORE_H__ */ diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c new file mode 100644 index 0000000..5545031 --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c @@ -0,0 +1,274 @@ +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * The Broadcom Wireless LAN controller driver. + */ +#include "opt_wlan.h" +#include "opt_bwn.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/endian.h> +#include <sys/errno.h> +#include <sys/firmware.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/socket.h> +#include <sys/sockio.h> + +#include <net/ethernet.h> +#include <net/if.h> +#include <net/if_var.h> +#include <net/if_arp.h> +#include <net/if_dl.h> +#include <net/if_llc.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <dev/pci/pcivar.h> +#include <dev/pci/pcireg.h> +#include <dev/siba/siba_ids.h> +#include <dev/siba/sibareg.h> +#include <dev/siba/sibavar.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> +#include <net80211/ieee80211_regdomain.h> +#include <net80211/ieee80211_phy.h> +#include <net80211/ieee80211_ratectl.h> + +#include <dev/bwn/if_bwnreg.h> +#include <dev/bwn/if_bwnvar.h> +#include <dev/bwn/if_bwn_debug.h> +#include <dev/bwn/if_bwn_util.h> +#include <dev/bwn/if_bwn_phy_common.h> + +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h> + +#define ppr_for_each_entry(ppr, i, entry) \ + for (i = 0, entry = &(ppr)->__all_rates[i]; \ + i < BWN_PPR_RATES_NUM; \ + i++, entry++) + +void bwn_ppr_clear(struct bwn_mac *mac, struct bwn_ppr *ppr) +{ + memset(ppr, 0, sizeof(*ppr)); + + /* Compile-time PPR check */ + CTASSERT(sizeof(struct bwn_ppr) == BWN_PPR_RATES_NUM * sizeof(uint8_t)); +} + +void bwn_ppr_add(struct bwn_mac *mac, struct bwn_ppr *ppr, int diff) +{ + int i; + uint8_t *rate; + + ppr_for_each_entry(ppr, i, rate) { + *rate = bwn_clamp_val(*rate + diff, 0, 127); + } +} + +void bwn_ppr_apply_max(struct bwn_mac *mac, struct bwn_ppr *ppr, uint8_t max) +{ + int i; + uint8_t *rate; + + ppr_for_each_entry(ppr, i, rate) { + *rate = min(*rate, max); + } +} + +void bwn_ppr_apply_min(struct bwn_mac *mac, struct bwn_ppr *ppr, uint8_t min) +{ + int i; + uint8_t *rate; + + ppr_for_each_entry(ppr, i, rate) { + *rate = max(*rate, min); + } +} + +uint8_t bwn_ppr_get_max(struct bwn_mac *mac, struct bwn_ppr *ppr) +{ + uint8_t res = 0; + int i; + uint8_t *rate; + + ppr_for_each_entry(ppr, i, rate) { + res = max(*rate, res); + } + + return res; +} + +bool bwn_ppr_load_max_from_sprom(struct bwn_mac *mac, struct bwn_ppr *ppr, + bwn_phy_band_t band) +{ + struct bwn_softc *sc = mac->mac_sc; + struct siba_sprom_core_pwr_info core_pwr_info[4]; + struct bwn_ppr_rates *rates = &ppr->rates; + struct bwn_phy *phy = &mac->mac_phy; + uint8_t maxpwr, off; + uint32_t sprom_ofdm_po; + uint16_t sprom_mcs_po[8]; + uint8_t extra_cdd_po, extra_stbc_po; + int i; + + for (i = 0; i < 4; i++) { + bzero(&core_pwr_info[i], sizeof(core_pwr_info[i])); + if (siba_sprom_get_core_power_info(sc->sc_dev, i, + &core_pwr_info[i]) != 0) { + BWN_ERRPRINTF(mac->mac_sc, + "%s: failed to get core_pwr_info for core %d\n", + __func__, + i); + } + } + + switch (band) { + case BWN_PHY_BAND_2G: + maxpwr = min(core_pwr_info[0].maxpwr_2g, + core_pwr_info[1].maxpwr_2g); + sprom_ofdm_po = siba_sprom_get_ofdm2gpo(sc->sc_dev); + siba_sprom_get_mcs2gpo(sc->sc_dev, sprom_mcs_po); + extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 0) & 0xf; + extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 0) & 0xf; + break; + case BWN_PHY_BAND_5G_LO: + maxpwr = min(core_pwr_info[0].maxpwr_5gl, + core_pwr_info[1].maxpwr_5gl); + sprom_ofdm_po = siba_sprom_get_ofdm5glpo(sc->sc_dev); + siba_sprom_get_mcs5glpo(sc->sc_dev, sprom_mcs_po); + extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 8) & 0xf; + extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 8) & 0xf; + break; + case BWN_PHY_BAND_5G_MI: + maxpwr = min(core_pwr_info[0].maxpwr_5g, + core_pwr_info[1].maxpwr_5g); + sprom_ofdm_po = siba_sprom_get_ofdm5gpo(sc->sc_dev); + siba_sprom_get_mcs5gpo(sc->sc_dev, sprom_mcs_po); + extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 4) & 0xf; + extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 4) & 0xf; + break; + case BWN_PHY_BAND_5G_HI: + maxpwr = min(core_pwr_info[0].maxpwr_5gh, + core_pwr_info[1].maxpwr_5gh); + sprom_ofdm_po = siba_sprom_get_ofdm5ghpo(sc->sc_dev); + siba_sprom_get_mcs5ghpo(sc->sc_dev, sprom_mcs_po); + extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 12) & 0xf; + extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 12) & 0xf; + break; + default: + device_printf(mac->mac_sc->sc_dev, "%s: invalid band (%d)\n", + __func__, + band); + return false; + } + + if (band == BWN_BAND_2G) { + for (i = 0; i < 4; i++) { + off = ((siba_sprom_get_cck2gpo(sc->sc_dev) >> (i * 4)) & 0xf) * 2; + rates->cck[i] = maxpwr - off; + } + } + + /* OFDM */ + for (i = 0; i < 8; i++) { + off = ((sprom_ofdm_po >> (i * 4)) & 0xf) * 2; + rates->ofdm[i] = maxpwr - off; + } + + /* MCS 20 SISO */ + rates->mcs_20[0] = rates->ofdm[0]; + rates->mcs_20[1] = rates->ofdm[2]; + rates->mcs_20[2] = rates->ofdm[3]; + rates->mcs_20[3] = rates->ofdm[4]; + rates->mcs_20[4] = rates->ofdm[5]; + rates->mcs_20[5] = rates->ofdm[6]; + rates->mcs_20[6] = rates->ofdm[7]; + rates->mcs_20[7] = rates->ofdm[7]; + + /* MCS 20 CDD */ + for (i = 0; i < 4; i++) { + off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2; + rates->mcs_20_cdd[i] = maxpwr - off; + if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3) + rates->mcs_20_cdd[i] -= extra_cdd_po; + } + for (i = 0; i < 4; i++) { + off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2; + rates->mcs_20_cdd[4 + i] = maxpwr - off; + if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3) + rates->mcs_20_cdd[4 + i] -= extra_cdd_po; + } + + /* OFDM 20 CDD */ + rates->ofdm_20_cdd[0] = rates->mcs_20_cdd[0]; + rates->ofdm_20_cdd[1] = rates->mcs_20_cdd[0]; + rates->ofdm_20_cdd[2] = rates->mcs_20_cdd[1]; + rates->ofdm_20_cdd[3] = rates->mcs_20_cdd[2]; + rates->ofdm_20_cdd[4] = rates->mcs_20_cdd[3]; + rates->ofdm_20_cdd[5] = rates->mcs_20_cdd[4]; + rates->ofdm_20_cdd[6] = rates->mcs_20_cdd[5]; + rates->ofdm_20_cdd[7] = rates->mcs_20_cdd[6]; + + /* MCS 20 STBC */ + for (i = 0; i < 4; i++) { + off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2; + rates->mcs_20_stbc[i] = maxpwr - off; + if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3) + rates->mcs_20_stbc[i] -= extra_stbc_po; + } + for (i = 0; i < 4; i++) { + off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2; + rates->mcs_20_stbc[4 + i] = maxpwr - off; + if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3) + rates->mcs_20_stbc[4 + i] -= extra_stbc_po; + } + + /* MCS 20 SDM */ + for (i = 0; i < 4; i++) { + off = ((sprom_mcs_po[2] >> (i * 4)) & 0xf) * 2; + rates->mcs_20_sdm[i] = maxpwr - off; + } + for (i = 0; i < 4; i++) { + off = ((sprom_mcs_po[3] >> (i * 4)) & 0xf) * 2; + rates->mcs_20_sdm[4 + i] = maxpwr - off; + } + + return true; +} diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h new file mode 100644 index 0000000..48d08e1 --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h @@ -0,0 +1,69 @@ +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +/* + * $FreeBSD$ + */ + +#ifndef __IF_BWN_PHY_PPR_H__ +#define __IF_BWN_PHY_PPR_H__ + +#define BWN_PPR_CCK_RATES_NUM 4 +#define BWN_PPR_OFDM_RATES_NUM 8 +#define BWN_PPR_MCS_RATES_NUM 8 + +#define BWN_PPR_RATES_NUM (BWN_PPR_CCK_RATES_NUM + \ + BWN_PPR_OFDM_RATES_NUM * 2 + \ + BWN_PPR_MCS_RATES_NUM * 4) + +struct bwn_ppr_rates { + uint8_t cck[BWN_PPR_CCK_RATES_NUM]; + uint8_t ofdm[BWN_PPR_OFDM_RATES_NUM]; + uint8_t ofdm_20_cdd[BWN_PPR_OFDM_RATES_NUM]; + uint8_t mcs_20[BWN_PPR_MCS_RATES_NUM]; /* single stream rates */ + uint8_t mcs_20_cdd[BWN_PPR_MCS_RATES_NUM]; + uint8_t mcs_20_stbc[BWN_PPR_MCS_RATES_NUM]; + uint8_t mcs_20_sdm[BWN_PPR_MCS_RATES_NUM]; +}; + +struct bwn_ppr { + /* All powers are in 1/4 dBm (Q5.2) */ + union { + uint8_t __all_rates[BWN_PPR_RATES_NUM]; + struct bwn_ppr_rates rates; + }; +}; + +extern void bwn_ppr_clear(struct bwn_mac *mac, struct bwn_ppr *ppr); +extern void bwn_ppr_add(struct bwn_mac *mac, struct bwn_ppr *ppr, int diff); +extern void bwn_ppr_apply_max(struct bwn_mac *mac, struct bwn_ppr *ppr, + uint8_t max); +extern void bwn_ppr_apply_min(struct bwn_mac *mac, struct bwn_ppr *ppr, + uint8_t min); +extern uint8_t bwn_ppr_get_max(struct bwn_mac *mac, struct bwn_ppr *ppr); +extern bool bwn_ppr_load_max_from_sprom(struct bwn_mac *mac, + struct bwn_ppr *ppr, bwn_phy_band_t band); + +#endif diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h new file mode 100644 index 0000000..50267f7 --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h @@ -0,0 +1,903 @@ +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +/* + * $FreeBSD$ + */ + +#ifndef __IF_BWN_PHY_N_REGS_H__ +#define __IF_BWN_PHY_N_REGS_H__ + +/* N-PHY registers. */ + +#define BWN_NPHY_BBCFG BWN_PHY_N(0x001) /* BB config */ +#define BWN_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */ +#define BWN_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */ +#define BWN_NPHY_CHANNEL BWN_PHY_N(0x005) /* Channel */ +#define BWN_NPHY_TXERR BWN_PHY_N(0x007) /* TX error */ +#define BWN_NPHY_BANDCTL BWN_PHY_N(0x009) /* Band control */ +#define BWN_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ +#define BWN_NPHY_4WI_ADDR BWN_PHY_N(0x00B) /* Four-wire bus address */ +#define BWN_NPHY_4WI_DATAHI BWN_PHY_N(0x00C) /* Four-wire bus data high */ +#define BWN_NPHY_4WI_DATALO BWN_PHY_N(0x00D) /* Four-wire bus data low */ +#define BWN_NPHY_BIST_STAT0 BWN_PHY_N(0x00E) /* Built-in self test status 0 */ +#define BWN_NPHY_BIST_STAT1 BWN_PHY_N(0x00F) /* Built-in self test status 1 */ + +#define BWN_NPHY_C1_DESPWR BWN_PHY_N(0x018) /* Core 1 desired power */ +#define BWN_NPHY_C1_CCK_DESPWR BWN_PHY_N(0x019) /* Core 1 CCK desired power */ +#define BWN_NPHY_C1_BCLIPBKOFF BWN_PHY_N(0x01A) /* Core 1 barely clip backoff */ +#define BWN_NPHY_C1_CCK_BCLIPBKOFF BWN_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */ +#define BWN_NPHY_C1_CGAINI BWN_PHY_N(0x01C) /* Core 1 compute gain info */ +#define BWN_NPHY_C1_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ +#define BWN_NPHY_C1_CGAINI_GAINBKOFF_SHIFT 0 +#define BWN_NPHY_C1_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */ +#define BWN_NPHY_C1_CGAINI_CLIPGBKOFF_SHIFT 5 +#define BWN_NPHY_C1_CGAINI_GAINSTEP 0x1C00 /* Gain step */ +#define BWN_NPHY_C1_CGAINI_GAINSTEP_SHIFT 10 +#define BWN_NPHY_C1_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */ +#define BWN_NPHY_C1_CCK_CGAINI BWN_PHY_N(0x01D) /* Core 1 CCK compute gain info */ +#define BWN_NPHY_C1_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ +#define BWN_NPHY_C1_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */ +#define BWN_NPHY_C1_MINMAX_GAIN BWN_PHY_N(0x01E) /* Core 1 min/max gain */ +#define BWN_NPHY_C1_MINGAIN 0x00FF /* Minimum gain */ +#define BWN_NPHY_C1_MINGAIN_SHIFT 0 +#define BWN_NPHY_C1_MAXGAIN 0xFF00 /* Maximum gain */ +#define BWN_NPHY_C1_MAXGAIN_SHIFT 8 +#define BWN_NPHY_C1_CCK_MINMAX_GAIN BWN_PHY_N(0x01F) /* Core 1 CCK min/max gain */ +#define BWN_NPHY_C1_CCK_MINGAIN 0x00FF /* Minimum gain */ +#define BWN_NPHY_C1_CCK_MINGAIN_SHIFT 0 +#define BWN_NPHY_C1_CCK_MAXGAIN 0xFF00 /* Maximum gain */ +#define BWN_NPHY_C1_CCK_MAXGAIN_SHIFT 8 +#define BWN_NPHY_C1_INITGAIN BWN_PHY_N(0x020) /* Core 1 initial gain code */ +#define BWN_NPHY_C1_INITGAIN_EXTLNA 0x0001 /* External LNA index */ +#define BWN_NPHY_C1_INITGAIN_LNA 0x0006 /* LNA index */ +#define BWN_NPHY_C1_INITGAIN_LNAIDX_SHIFT 1 +#define BWN_NPHY_C1_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */ +#define BWN_NPHY_C1_INITGAIN_HPVGA1_SHIFT 3 +#define BWN_NPHY_C1_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */ +#define BWN_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7 +#define BWN_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */ +#define BWN_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */ +#define BWN_NPHY_REV3_C1_INITGAIN_A BWN_PHY_N(0x020) +#define BWN_NPHY_C1_CLIP1_HIGAIN BWN_PHY_N(0x021) /* Core 1 clip1 high gain code */ +#define BWN_NPHY_REV3_C1_INITGAIN_B BWN_PHY_N(0x021) +#define BWN_NPHY_C1_CLIP1_MEDGAIN BWN_PHY_N(0x022) /* Core 1 clip1 medium gain code */ +#define BWN_NPHY_REV3_C1_CLIP_HIGAIN_A BWN_PHY_N(0x022) +#define BWN_NPHY_C1_CLIP1_LOGAIN BWN_PHY_N(0x023) /* Core 1 clip1 low gain code */ +#define BWN_NPHY_REV3_C1_CLIP_HIGAIN_B BWN_PHY_N(0x023) +#define BWN_NPHY_C1_CLIP2_GAIN BWN_PHY_N(0x024) /* Core 1 clip2 gain code */ +#define BWN_NPHY_REV3_C1_CLIP_MEDGAIN_A BWN_PHY_N(0x024) +#define BWN_NPHY_C1_FILTERGAIN BWN_PHY_N(0x025) /* Core 1 filter gain */ +#define BWN_NPHY_C1_LPF_QHPF_BW BWN_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */ +#define BWN_NPHY_C1_CLIPWBTHRES BWN_PHY_N(0x027) /* Core 1 clip wideband threshold */ +#define BWN_NPHY_C1_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */ +#define BWN_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT 0 +#define BWN_NPHY_C1_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */ +#define BWN_NPHY_C1_CLIPWBTHRES_CLIP1_SHIFT 6 +#define BWN_NPHY_C1_W1THRES BWN_PHY_N(0x028) /* Core 1 W1 threshold */ +#define BWN_NPHY_C1_EDTHRES BWN_PHY_N(0x029) /* Core 1 ED threshold */ +#define BWN_NPHY_C1_SMSIGTHRES BWN_PHY_N(0x02A) /* Core 1 small sig threshold */ +#define BWN_NPHY_C1_NBCLIPTHRES BWN_PHY_N(0x02B) /* Core 1 NB clip threshold */ +#define BWN_NPHY_C1_CLIP1THRES BWN_PHY_N(0x02C) /* Core 1 clip1 threshold */ +#define BWN_NPHY_C1_CLIP2THRES BWN_PHY_N(0x02D) /* Core 1 clip2 threshold */ + +#define BWN_NPHY_C2_DESPWR BWN_PHY_N(0x02E) /* Core 2 desired power */ +#define BWN_NPHY_C2_CCK_DESPWR BWN_PHY_N(0x02F) /* Core 2 CCK desired power */ +#define BWN_NPHY_C2_BCLIPBKOFF BWN_PHY_N(0x030) /* Core 2 barely clip backoff */ +#define BWN_NPHY_C2_CCK_BCLIPBKOFF BWN_PHY_N(0x031) /* Core 2 CCK barely clip backoff */ +#define BWN_NPHY_C2_CGAINI BWN_PHY_N(0x032) /* Core 2 compute gain info */ +#define BWN_NPHY_C2_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ +#define BWN_NPHY_C2_CGAINI_GAINBKOFF_SHIFT 0 +#define BWN_NPHY_C2_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */ +#define BWN_NPHY_C2_CGAINI_CLIPGBKOFF_SHIFT 5 +#define BWN_NPHY_C2_CGAINI_GAINSTEP 0x1C00 /* Gain step */ +#define BWN_NPHY_C2_CGAINI_GAINSTEP_SHIFT 10 +#define BWN_NPHY_C2_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */ +#define BWN_NPHY_C2_CCK_CGAINI BWN_PHY_N(0x033) /* Core 2 CCK compute gain info */ +#define BWN_NPHY_C2_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ +#define BWN_NPHY_C2_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */ +#define BWN_NPHY_C2_MINMAX_GAIN BWN_PHY_N(0x034) /* Core 2 min/max gain */ +#define BWN_NPHY_C2_MINGAIN 0x00FF /* Minimum gain */ +#define BWN_NPHY_C2_MINGAIN_SHIFT 0 +#define BWN_NPHY_C2_MAXGAIN 0xFF00 /* Maximum gain */ +#define BWN_NPHY_C2_MAXGAIN_SHIFT 8 +#define BWN_NPHY_C2_CCK_MINMAX_GAIN BWN_PHY_N(0x035) /* Core 2 CCK min/max gain */ +#define BWN_NPHY_C2_CCK_MINGAIN 0x00FF /* Minimum gain */ +#define BWN_NPHY_C2_CCK_MINGAIN_SHIFT 0 +#define BWN_NPHY_C2_CCK_MAXGAIN 0xFF00 /* Maximum gain */ +#define BWN_NPHY_C2_CCK_MAXGAIN_SHIFT 8 +#define BWN_NPHY_C2_INITGAIN BWN_PHY_N(0x036) /* Core 2 initial gain code */ +#define BWN_NPHY_C2_INITGAIN_EXTLNA 0x0001 /* External LNA index */ +#define BWN_NPHY_C2_INITGAIN_LNA 0x0006 /* LNA index */ +#define BWN_NPHY_C2_INITGAIN_LNAIDX_SHIFT 1 +#define BWN_NPHY_C2_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */ +#define BWN_NPHY_C2_INITGAIN_HPVGA1_SHIFT 3 +#define BWN_NPHY_C2_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */ +#define BWN_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7 +#define BWN_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */ +#define BWN_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */ +#define BWN_NPHY_REV3_C1_CLIP_MEDGAIN_B BWN_PHY_N(0x036) +#define BWN_NPHY_C2_CLIP1_HIGAIN BWN_PHY_N(0x037) /* Core 2 clip1 high gain code */ +#define BWN_NPHY_REV3_C1_CLIP_LOGAIN_A BWN_PHY_N(0x037) +#define BWN_NPHY_C2_CLIP1_MEDGAIN BWN_PHY_N(0x038) /* Core 2 clip1 medium gain code */ +#define BWN_NPHY_REV3_C1_CLIP_LOGAIN_B BWN_PHY_N(0x038) +#define BWN_NPHY_C2_CLIP1_LOGAIN BWN_PHY_N(0x039) /* Core 2 clip1 low gain code */ +#define BWN_NPHY_REV3_C1_CLIP2_GAIN_A BWN_PHY_N(0x039) +#define BWN_NPHY_C2_CLIP2_GAIN BWN_PHY_N(0x03A) /* Core 2 clip2 gain code */ +#define BWN_NPHY_REV3_C1_CLIP2_GAIN_B BWN_PHY_N(0x03A) +#define BWN_NPHY_C2_FILTERGAIN BWN_PHY_N(0x03B) /* Core 2 filter gain */ +#define BWN_NPHY_C2_LPF_QHPF_BW BWN_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */ +#define BWN_NPHY_C2_CLIPWBTHRES BWN_PHY_N(0x03D) /* Core 2 clip wideband threshold */ +#define BWN_NPHY_C2_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */ +#define BWN_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT 0 +#define BWN_NPHY_C2_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */ +#define BWN_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT 6 +#define BWN_NPHY_C2_W1THRES BWN_PHY_N(0x03E) /* Core 2 W1 threshold */ +#define BWN_NPHY_C2_EDTHRES BWN_PHY_N(0x03F) /* Core 2 ED threshold */ +#define BWN_NPHY_C2_SMSIGTHRES BWN_PHY_N(0x040) /* Core 2 small sig threshold */ +#define BWN_NPHY_C2_NBCLIPTHRES BWN_PHY_N(0x041) /* Core 2 NB clip threshold */ +#define BWN_NPHY_C2_CLIP1THRES BWN_PHY_N(0x042) /* Core 2 clip1 threshold */ +#define BWN_NPHY_C2_CLIP2THRES BWN_PHY_N(0x043) /* Core 2 clip2 threshold */ + +#define BWN_NPHY_CRS_THRES1 BWN_PHY_N(0x044) /* CRS threshold 1 */ +#define BWN_NPHY_CRS_THRES2 BWN_PHY_N(0x045) /* CRS threshold 2 */ +#define BWN_NPHY_CRS_THRES3 BWN_PHY_N(0x046) /* CRS threshold 3 */ +#define BWN_NPHY_CRSCTL BWN_PHY_N(0x047) /* CRS control */ +#define BWN_NPHY_DCFADDR BWN_PHY_N(0x048) /* DC filter address */ +#define BWN_NPHY_RXF20_NUM0 BWN_PHY_N(0x049) /* RX filter 20 numerator 0 */ +#define BWN_NPHY_RXF20_NUM1 BWN_PHY_N(0x04A) /* RX filter 20 numerator 1 */ +#define BWN_NPHY_RXF20_NUM2 BWN_PHY_N(0x04B) /* RX filter 20 numerator 2 */ +#define BWN_NPHY_RXF20_DENOM0 BWN_PHY_N(0x04C) /* RX filter 20 denominator 0 */ +#define BWN_NPHY_RXF20_DENOM1 BWN_PHY_N(0x04D) /* RX filter 20 denominator 1 */ +#define BWN_NPHY_RXF20_NUM10 BWN_PHY_N(0x04E) /* RX filter 20 numerator 10 */ +#define BWN_NPHY_RXF20_NUM11 BWN_PHY_N(0x04F) /* RX filter 20 numerator 11 */ +#define BWN_NPHY_RXF20_NUM12 BWN_PHY_N(0x050) /* RX filter 20 numerator 12 */ +#define BWN_NPHY_RXF20_DENOM10 BWN_PHY_N(0x051) /* RX filter 20 denominator 10 */ +#define BWN_NPHY_RXF20_DENOM11 BWN_PHY_N(0x052) /* RX filter 20 denominator 11 */ +#define BWN_NPHY_RXF40_NUM0 BWN_PHY_N(0x053) /* RX filter 40 numerator 0 */ +#define BWN_NPHY_RXF40_NUM1 BWN_PHY_N(0x054) /* RX filter 40 numerator 1 */ +#define BWN_NPHY_RXF40_NUM2 BWN_PHY_N(0x055) /* RX filter 40 numerator 2 */ +#define BWN_NPHY_RXF40_DENOM0 BWN_PHY_N(0x056) /* RX filter 40 denominator 0 */ +#define BWN_NPHY_RXF40_DENOM1 BWN_PHY_N(0x057) /* RX filter 40 denominator 1 */ +#define BWN_NPHY_RXF40_NUM10 BWN_PHY_N(0x058) /* RX filter 40 numerator 10 */ +#define BWN_NPHY_RXF40_NUM11 BWN_PHY_N(0x059) /* RX filter 40 numerator 11 */ +#define BWN_NPHY_RXF40_NUM12 BWN_PHY_N(0x05A) /* RX filter 40 numerator 12 */ +#define BWN_NPHY_RXF40_DENOM10 BWN_PHY_N(0x05B) /* RX filter 40 denominator 10 */ +#define BWN_NPHY_RXF40_DENOM11 BWN_PHY_N(0x05C) /* RX filter 40 denominator 11 */ +#define BWN_NPHY_PPROC_RSTLEN BWN_PHY_N(0x060) /* Packet processing reset length */ +#define BWN_NPHY_INITCARR_DLEN BWN_PHY_N(0x061) /* Initial carrier detection length */ +#define BWN_NPHY_CLIP1CARR_DLEN BWN_PHY_N(0x062) /* Clip1 carrier detection length */ +#define BWN_NPHY_CLIP2CARR_DLEN BWN_PHY_N(0x063) /* Clip2 carrier detection length */ +#define BWN_NPHY_INITGAIN_SLEN BWN_PHY_N(0x064) /* Initial gain settle length */ +#define BWN_NPHY_CLIP1GAIN_SLEN BWN_PHY_N(0x065) /* Clip1 gain settle length */ +#define BWN_NPHY_CLIP2GAIN_SLEN BWN_PHY_N(0x066) /* Clip2 gain settle length */ +#define BWN_NPHY_PACKGAIN_SLEN BWN_PHY_N(0x067) /* Packet gain settle length */ +#define BWN_NPHY_CARRSRC_TLEN BWN_PHY_N(0x068) /* Carrier search timeout length */ +#define BWN_NPHY_TISRC_TLEN BWN_PHY_N(0x069) /* Timing search timeout length */ +#define BWN_NPHY_ENDROP_TLEN BWN_PHY_N(0x06A) /* Energy drop timeout length */ +#define BWN_NPHY_CLIP1_NBDWELL_LEN BWN_PHY_N(0x06B) /* Clip1 NB dwell length */ +#define BWN_NPHY_CLIP2_NBDWELL_LEN BWN_PHY_N(0x06C) /* Clip2 NB dwell length */ +#define BWN_NPHY_W1CLIP1_DWELL_LEN BWN_PHY_N(0x06D) /* W1 clip1 dwell length */ +#define BWN_NPHY_W1CLIP2_DWELL_LEN BWN_PHY_N(0x06E) /* W1 clip2 dwell length */ +#define BWN_NPHY_W2CLIP1_DWELL_LEN BWN_PHY_N(0x06F) /* W2 clip1 dwell length */ +#define BWN_NPHY_PLOAD_CSENSE_EXTLEN BWN_PHY_N(0x070) /* Payload carrier sense extension length */ +#define BWN_NPHY_EDROP_CSENSE_EXTLEN BWN_PHY_N(0x071) /* Energy drop carrier sense extension length */ +#define BWN_NPHY_TABLE_ADDR BWN_PHY_N(0x072) /* Table address */ +#define BWN_NPHY_TABLE_DATALO BWN_PHY_N(0x073) /* Table data low */ +#define BWN_NPHY_TABLE_DATAHI BWN_PHY_N(0x074) /* Table data high */ +#define BWN_NPHY_WWISE_LENIDX BWN_PHY_N(0x075) /* WWiSE length index */ +#define BWN_NPHY_TGNSYNC_LENIDX BWN_PHY_N(0x076) /* TGNsync length index */ +#define BWN_NPHY_TXMACIF_HOLDOFF BWN_PHY_N(0x077) /* TX MAC IF Hold off */ +#define BWN_NPHY_RFCTL_CMD BWN_PHY_N(0x078) /* RF control (command) */ +#define BWN_NPHY_RFCTL_CMD_START 0x0001 /* Start sequence */ +#define BWN_NPHY_RFCTL_CMD_RXTX 0x0002 /* RX/TX */ +#define BWN_NPHY_RFCTL_CMD_CORESEL 0x0038 /* Core select */ +#define BWN_NPHY_RFCTL_CMD_CORESEL_SHIFT 3 +#define BWN_NPHY_RFCTL_CMD_PORFORCE 0x0040 /* POR force */ +#define BWN_NPHY_RFCTL_CMD_OEPORFORCE 0x0080 /* OE POR force */ +#define BWN_NPHY_RFCTL_CMD_RXEN 0x0100 /* RX enable */ +#define BWN_NPHY_RFCTL_CMD_TXEN 0x0200 /* TX enable */ +#define BWN_NPHY_RFCTL_CMD_CHIP0PU 0x0400 /* Chip0 PU */ +#define BWN_NPHY_RFCTL_CMD_EN 0x0800 /* Radio enabled */ +#define BWN_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */ +#define BWN_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12 +#define BWN_NPHY_RFCTL_RSSIO1 BWN_PHY_N(0x07A) /* RF control (RSSI others 1) */ +#define BWN_NPHY_RFCTL_RSSIO1_RXPD 0x0001 /* RX PD */ +#define BWN_NPHY_RFCTL_RSSIO1_TXPD 0x0002 /* TX PD */ +#define BWN_NPHY_RFCTL_RSSIO1_PAPD 0x0004 /* PA PD */ +#define BWN_NPHY_RFCTL_RSSIO1_RSSICTL 0x0030 /* RSSI control */ +#define BWN_NPHY_RFCTL_RSSIO1_LPFBW 0x00C0 /* LPF bandwidth */ +#define BWN_NPHY_RFCTL_RSSIO1_HPFBWHI 0x0100 /* HPF bandwidth high */ +#define BWN_NPHY_RFCTL_RSSIO1_HIQDISCO 0x0200 /* HIQ dis core */ +#define BWN_NPHY_RFCTL_RXG1 BWN_PHY_N(0x07B) /* RF control (RX gain 1) */ +#define BWN_NPHY_RFCTL_TXG1 BWN_PHY_N(0x07C) /* RF control (TX gain 1) */ +#define BWN_NPHY_RFCTL_RSSIO2 BWN_PHY_N(0x07D) /* RF control (RSSI others 2) */ +#define BWN_NPHY_RFCTL_RSSIO2_RXPD 0x0001 /* RX PD */ +#define BWN_NPHY_RFCTL_RSSIO2_TXPD 0x0002 /* TX PD */ +#define BWN_NPHY_RFCTL_RSSIO2_PAPD 0x0004 /* PA PD */ +#define BWN_NPHY_RFCTL_RSSIO2_RSSICTL 0x0030 /* RSSI control */ +#define BWN_NPHY_RFCTL_RSSIO2_LPFBW 0x00C0 /* LPF bandwidth */ +#define BWN_NPHY_RFCTL_RSSIO2_HPFBWHI 0x0100 /* HPF bandwidth high */ +#define BWN_NPHY_RFCTL_RSSIO2_HIQDISCO 0x0200 /* HIQ dis core */ +#define BWN_NPHY_RFCTL_RXG2 BWN_PHY_N(0x07E) /* RF control (RX gain 2) */ +#define BWN_NPHY_RFCTL_TXG2 BWN_PHY_N(0x07F) /* RF control (TX gain 2) */ +#define BWN_NPHY_RFCTL_RSSIO3 BWN_PHY_N(0x080) /* RF control (RSSI others 3) */ +#define BWN_NPHY_RFCTL_RSSIO3_RXPD 0x0001 /* RX PD */ +#define BWN_NPHY_RFCTL_RSSIO3_TXPD 0x0002 /* TX PD */ +#define BWN_NPHY_RFCTL_RSSIO3_PAPD 0x0004 /* PA PD */ +#define BWN_NPHY_RFCTL_RSSIO3_RSSICTL 0x0030 /* RSSI control */ +#define BWN_NPHY_RFCTL_RSSIO3_LPFBW 0x00C0 /* LPF bandwidth */ +#define BWN_NPHY_RFCTL_RSSIO3_HPFBWHI 0x0100 /* HPF bandwidth high */ +#define BWN_NPHY_RFCTL_RSSIO3_HIQDISCO 0x0200 /* HIQ dis core */ +#define BWN_NPHY_RFCTL_RXG3 BWN_PHY_N(0x081) /* RF control (RX gain 3) */ +#define BWN_NPHY_RFCTL_TXG3 BWN_PHY_N(0x082) /* RF control (TX gain 3) */ +#define BWN_NPHY_RFCTL_RSSIO4 BWN_PHY_N(0x083) /* RF control (RSSI others 4) */ +#define BWN_NPHY_RFCTL_RSSIO4_RXPD 0x0001 /* RX PD */ +#define BWN_NPHY_RFCTL_RSSIO4_TXPD 0x0002 /* TX PD */ +#define BWN_NPHY_RFCTL_RSSIO4_PAPD 0x0004 /* PA PD */ +#define BWN_NPHY_RFCTL_RSSIO4_RSSICTL 0x0030 /* RSSI control */ +#define BWN_NPHY_RFCTL_RSSIO4_LPFBW 0x00C0 /* LPF bandwidth */ +#define BWN_NPHY_RFCTL_RSSIO4_HPFBWHI 0x0100 /* HPF bandwidth high */ +#define BWN_NPHY_RFCTL_RSSIO4_HIQDISCO 0x0200 /* HIQ dis core */ +#define BWN_NPHY_RFCTL_RXG4 BWN_PHY_N(0x084) /* RF control (RX gain 4) */ +#define BWN_NPHY_RFCTL_TXG4 BWN_PHY_N(0x085) /* RF control (TX gain 4) */ +#define BWN_NPHY_C1_TXIQ_COMP_OFF BWN_PHY_N(0x087) /* Core 1 TX I/Q comp offset */ +#define BWN_NPHY_C2_TXIQ_COMP_OFF BWN_PHY_N(0x088) /* Core 2 TX I/Q comp offset */ +#define BWN_NPHY_C1_TXCTL BWN_PHY_N(0x08B) /* Core 1 TX control */ +#define BWN_NPHY_C2_TXCTL BWN_PHY_N(0x08C) /* Core 2 TX control */ +#define BWN_NPHY_AFECTL_OVER1 BWN_PHY_N(0x08F) /* AFE control override 1 */ +#define BWN_NPHY_SCRAM_SIGCTL BWN_PHY_N(0x090) /* Scram signal control */ +#define BWN_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */ +#define BWN_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0 +#define BWN_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */ +#define BWN_NPHY_SCRAM_SIGCTL_SICE 0x0100 /* Scram index control enable */ +#define BWN_NPHY_SCRAM_SIGCTL_START 0xFE00 /* Scram start bit */ +#define BWN_NPHY_SCRAM_SIGCTL_START_SHIFT 9 +#define BWN_NPHY_RFCTL_INTC1 BWN_PHY_N(0x091) /* RF control (intc 1) */ +#define BWN_NPHY_RFCTL_INTC2 BWN_PHY_N(0x092) /* RF control (intc 2) */ +#define BWN_NPHY_RFCTL_INTC3 BWN_PHY_N(0x093) /* RF control (intc 3) */ +#define BWN_NPHY_RFCTL_INTC4 BWN_PHY_N(0x094) /* RF control (intc 4) */ +#define BWN_NPHY_NRDTO_WWISE BWN_PHY_N(0x095) /* # datatones WWiSE */ +#define BWN_NPHY_NRDTO_TGNSYNC BWN_PHY_N(0x096) /* # datatones TGNsync */ +#define BWN_NPHY_SIGFMOD_WWISE BWN_PHY_N(0x097) /* Signal field mod WWiSE */ +#define BWN_NPHY_LEG_SIGFMOD_11N BWN_PHY_N(0x098) /* Legacy signal field mod 11n */ +#define BWN_NPHY_HT_SIGFMOD_11N BWN_PHY_N(0x099) /* HT signal field mod 11n */ +#define BWN_NPHY_C1_RXIQ_COMPA0 BWN_PHY_N(0x09A) /* Core 1 RX I/Q comp A0 */ +#define BWN_NPHY_C1_RXIQ_COMPB0 BWN_PHY_N(0x09B) /* Core 1 RX I/Q comp B0 */ +#define BWN_NPHY_C2_RXIQ_COMPA1 BWN_PHY_N(0x09C) /* Core 2 RX I/Q comp A1 */ +#define BWN_NPHY_C2_RXIQ_COMPB1 BWN_PHY_N(0x09D) /* Core 2 RX I/Q comp B1 */ +#define BWN_NPHY_RXCTL BWN_PHY_N(0x0A0) /* RX control */ +#define BWN_NPHY_RXCTL_BSELU20 0x0010 /* Band select upper 20 */ +#define BWN_NPHY_RXCTL_RIFSEN 0x0080 /* RIFS enable */ +#define BWN_NPHY_RFSEQMODE BWN_PHY_N(0x0A1) /* RF seq mode */ +#define BWN_NPHY_RFSEQMODE_CAOVER 0x0001 /* Core active override */ +#define BWN_NPHY_RFSEQMODE_TROVER 0x0002 /* Trigger override */ +#define BWN_NPHY_RFSEQCA BWN_PHY_N(0x0A2) /* RF seq core active */ +#define BWN_NPHY_RFSEQCA_TXEN 0x000F /* TX enable */ +#define BWN_NPHY_RFSEQCA_TXEN_SHIFT 0 +#define BWN_NPHY_RFSEQCA_RXEN 0x00F0 /* RX enable */ +#define BWN_NPHY_RFSEQCA_RXEN_SHIFT 4 +#define BWN_NPHY_RFSEQCA_TXDIS 0x0F00 /* TX disable */ +#define BWN_NPHY_RFSEQCA_TXDIS_SHIFT 8 +#define BWN_NPHY_RFSEQCA_RXDIS 0xF000 /* RX disable */ +#define BWN_NPHY_RFSEQCA_RXDIS_SHIFT 12 +#define BWN_NPHY_RFSEQTR BWN_PHY_N(0x0A3) /* RF seq trigger */ +#define BWN_NPHY_RFSEQTR_RX2TX 0x0001 /* RX2TX */ +#define BWN_NPHY_RFSEQTR_TX2RX 0x0002 /* TX2RX */ +#define BWN_NPHY_RFSEQTR_UPGH 0x0004 /* Update gain H */ +#define BWN_NPHY_RFSEQTR_UPGL 0x0008 /* Update gain L */ +#define BWN_NPHY_RFSEQTR_UPGU 0x0010 /* Update gain U */ +#define BWN_NPHY_RFSEQTR_RST2RX 0x0020 /* Reset to RX */ +#define BWN_NPHY_RFSEQST BWN_PHY_N(0x0A4) /* RF seq status. Values same as trigger. */ +#define BWN_NPHY_AFECTL_OVER BWN_PHY_N(0x0A5) /* AFE control override */ +#define BWN_NPHY_AFECTL_C1 BWN_PHY_N(0x0A6) /* AFE control core 1 */ +#define BWN_NPHY_AFECTL_C2 BWN_PHY_N(0x0A7) /* AFE control core 2 */ +#define BWN_NPHY_AFECTL_C3 BWN_PHY_N(0x0A8) /* AFE control core 3 */ +#define BWN_NPHY_AFECTL_C4 BWN_PHY_N(0x0A9) /* AFE control core 4 */ +#define BWN_NPHY_AFECTL_DACGAIN1 BWN_PHY_N(0x0AA) /* AFE control DAC gain 1 */ +#define BWN_NPHY_AFECTL_DACGAIN2 BWN_PHY_N(0x0AB) /* AFE control DAC gain 2 */ +#define BWN_NPHY_AFECTL_DACGAIN3 BWN_PHY_N(0x0AC) /* AFE control DAC gain 3 */ +#define BWN_NPHY_AFECTL_DACGAIN4 BWN_PHY_N(0x0AD) /* AFE control DAC gain 4 */ +#define BWN_NPHY_STR_ADDR1 BWN_PHY_N(0x0AE) /* STR address 1 */ +#define BWN_NPHY_STR_ADDR2 BWN_PHY_N(0x0AF) /* STR address 2 */ +#define BWN_NPHY_CLASSCTL BWN_PHY_N(0x0B0) /* Classifier control */ +#define BWN_NPHY_CLASSCTL_CCKEN 0x0001 /* CCK enable */ +#define BWN_NPHY_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */ +#define BWN_NPHY_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */ +#define BWN_NPHY_IQFLIP BWN_PHY_N(0x0B1) /* I/Q flip */ +#define BWN_NPHY_IQFLIP_ADC1 0x0001 /* ADC1 */ +#define BWN_NPHY_IQFLIP_ADC2 0x0010 /* ADC2 */ +#define BWN_NPHY_SISO_SNR_THRES BWN_PHY_N(0x0B2) /* SISO SNR threshold */ +#define BWN_NPHY_SIGMA_N_MULT BWN_PHY_N(0x0B3) /* Sigma N multiplier */ +#define BWN_NPHY_TXMACDELAY BWN_PHY_N(0x0B4) /* TX MAC delay */ +#define BWN_NPHY_TXFRAMEDELAY BWN_PHY_N(0x0B5) /* TX frame delay */ +#define BWN_NPHY_MLPARM BWN_PHY_N(0x0B6) /* ML parameters */ +#define BWN_NPHY_MLCTL BWN_PHY_N(0x0B7) /* ML control */ +#define BWN_NPHY_WWISE_20NCYCDAT BWN_PHY_N(0x0B8) /* WWiSE 20 N cyc data */ +#define BWN_NPHY_WWISE_40NCYCDAT BWN_PHY_N(0x0B9) /* WWiSE 40 N cyc data */ +#define BWN_NPHY_TGNSYNC_20NCYCDAT BWN_PHY_N(0x0BA) /* TGNsync 20 N cyc data */ +#define BWN_NPHY_TGNSYNC_40NCYCDAT BWN_PHY_N(0x0BB) /* TGNsync 40 N cyc data */ +#define BWN_NPHY_INITSWIZP BWN_PHY_N(0x0BC) /* Initial swizzle pattern */ +#define BWN_NPHY_TXTAILCNT BWN_PHY_N(0x0BD) /* TX tail count value */ +#define BWN_NPHY_BPHY_CTL1 BWN_PHY_N(0x0BE) /* B PHY control 1 */ +#define BWN_NPHY_BPHY_CTL2 BWN_PHY_N(0x0BF) /* B PHY control 2 */ +#define BWN_NPHY_BPHY_CTL2_LUT 0x001F /* LUT index */ +#define BWN_NPHY_BPHY_CTL2_LUT_SHIFT 0 +#define BWN_NPHY_BPHY_CTL2_MACDEL 0x7FE0 /* MAC delay */ +#define BWN_NPHY_BPHY_CTL2_MACDEL_SHIFT 5 +#define BWN_NPHY_IQLOCAL_CMD BWN_PHY_N(0x0C0) /* I/Q LO cal command */ +#define BWN_NPHY_IQLOCAL_CMD_EN 0x8000 +#define BWN_NPHY_IQLOCAL_CMDNNUM BWN_PHY_N(0x0C1) /* I/Q LO cal command N num */ +#define BWN_NPHY_IQLOCAL_CMDGCTL BWN_PHY_N(0x0C2) /* I/Q LO cal command G control */ +#define BWN_NPHY_SAMP_CMD BWN_PHY_N(0x0C3) /* Sample command */ +#define BWN_NPHY_SAMP_CMD_STOP 0x0002 /* Stop */ +#define BWN_NPHY_SAMP_LOOPCNT BWN_PHY_N(0x0C4) /* Sample loop count */ +#define BWN_NPHY_SAMP_WAITCNT BWN_PHY_N(0x0C5) /* Sample wait count */ +#define BWN_NPHY_SAMP_DEPCNT BWN_PHY_N(0x0C6) /* Sample depth count */ +#define BWN_NPHY_SAMP_STAT BWN_PHY_N(0x0C7) /* Sample status */ +#define BWN_NPHY_GPIO_LOOEN BWN_PHY_N(0x0C8) /* GPIO low out enable */ +#define BWN_NPHY_GPIO_HIOEN BWN_PHY_N(0x0C9) /* GPIO high out enable */ +#define BWN_NPHY_GPIO_SEL BWN_PHY_N(0x0CA) /* GPIO select */ +#define BWN_NPHY_GPIO_CLKCTL BWN_PHY_N(0x0CB) /* GPIO clock control */ +#define BWN_NPHY_TXF_20CO_AS0 BWN_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */ +#define BWN_NPHY_TXF_20CO_AS1 BWN_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */ +#define BWN_NPHY_TXF_20CO_AS2 BWN_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */ +#define BWN_NPHY_TXF_20CO_B32S0 BWN_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */ +#define BWN_NPHY_TXF_20CO_B1S0 BWN_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */ +#define BWN_NPHY_TXF_20CO_B32S1 BWN_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */ +#define BWN_NPHY_TXF_20CO_B1S1 BWN_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */ +#define BWN_NPHY_TXF_20CO_B32S2 BWN_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */ +#define BWN_NPHY_TXF_20CO_B1S2 BWN_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */ +#define BWN_NPHY_SIGFLDTOL BWN_PHY_N(0x0D5) /* Signal fld tolerance */ +#define BWN_NPHY_TXSERFLD BWN_PHY_N(0x0D6) /* TX service field */ +#define BWN_NPHY_AFESEQ_RX2TX_PUD BWN_PHY_N(0x0D7) /* AFE seq RX2TX power up/down delay */ +#define BWN_NPHY_AFESEQ_TX2RX_PUD BWN_PHY_N(0x0D8) /* AFE seq TX2RX power up/down delay */ +#define BWN_NPHY_TGNSYNC_SCRAMI0 BWN_PHY_N(0x0D9) /* TGNsync scram init 0 */ +#define BWN_NPHY_TGNSYNC_SCRAMI1 BWN_PHY_N(0x0DA) /* TGNsync scram init 1 */ +#define BWN_NPHY_INITSWIZPATTLEG BWN_PHY_N(0x0DB) /* Initial swizzle pattern leg */ +#define BWN_NPHY_BPHY_CTL3 BWN_PHY_N(0x0DC) /* B PHY control 3 */ +#define BWN_NPHY_BPHY_CTL3_SCALE 0x00FF /* Scale */ +#define BWN_NPHY_BPHY_CTL3_SCALE_SHIFT 0 +#define BWN_NPHY_BPHY_CTL3_FSC 0xFF00 /* Frame start count value */ +#define BWN_NPHY_BPHY_CTL3_FSC_SHIFT 8 +#define BWN_NPHY_BPHY_CTL4 BWN_PHY_N(0x0DD) /* B PHY control 4 */ +#define BWN_NPHY_C1_TXBBMULT BWN_PHY_N(0x0DE) /* Core 1 TX BB multiplier */ +#define BWN_NPHY_C2_TXBBMULT BWN_PHY_N(0x0DF) /* Core 2 TX BB multiplier */ +#define BWN_NPHY_TXF_40CO_AS0 BWN_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */ +#define BWN_NPHY_TXF_40CO_AS1 BWN_PHY_N(0x0E2) /* TX filter 40 coeff A stage 1 */ +#define BWN_NPHY_TXF_40CO_AS2 BWN_PHY_N(0x0E3) /* TX filter 40 coeff A stage 2 */ +#define BWN_NPHY_TXF_40CO_B32S0 BWN_PHY_N(0x0E4) /* TX filter 40 coeff B32 stage 0 */ +#define BWN_NPHY_TXF_40CO_B1S0 BWN_PHY_N(0x0E5) /* TX filter 40 coeff B1 stage 0 */ +#define BWN_NPHY_TXF_40CO_B32S1 BWN_PHY_N(0x0E6) /* TX filter 40 coeff B32 stage 1 */ +#define BWN_NPHY_TXF_40CO_B1S1 BWN_PHY_N(0x0E7) /* TX filter 40 coeff B1 stage 1 */ +#define BWN_NPHY_REV3_RFCTL_OVER0 BWN_PHY_N(0x0E7) +#define BWN_NPHY_TXF_40CO_B32S2 BWN_PHY_N(0x0E8) /* TX filter 40 coeff B32 stage 2 */ +#define BWN_NPHY_TXF_40CO_B1S2 BWN_PHY_N(0x0E9) /* TX filter 40 coeff B1 stage 2 */ +#define BWN_NPHY_BIST_STAT2 BWN_PHY_N(0x0EA) /* BIST status 2 */ +#define BWN_NPHY_BIST_STAT3 BWN_PHY_N(0x0EB) /* BIST status 3 */ +#define BWN_NPHY_RFCTL_OVER BWN_PHY_N(0x0EC) /* RF control override */ +#define BWN_NPHY_REV3_RFCTL_OVER1 BWN_PHY_N(0x0EC) +#define BWN_NPHY_MIMOCFG BWN_PHY_N(0x0ED) /* MIMO config */ +#define BWN_NPHY_MIMOCFG_GFMIX 0x0004 /* Greenfield or mixed mode */ +#define BWN_NPHY_MIMOCFG_AUTO 0x0100 /* Greenfield/mixed mode auto */ +#define BWN_NPHY_RADAR_BLNKCTL BWN_PHY_N(0x0EE) /* Radar blank control */ +#define BWN_NPHY_A0RADAR_FIFOCTL BWN_PHY_N(0x0EF) /* Antenna 0 radar FIFO control */ +#define BWN_NPHY_A1RADAR_FIFOCTL BWN_PHY_N(0x0F0) /* Antenna 1 radar FIFO control */ +#define BWN_NPHY_A0RADAR_FIFODAT BWN_PHY_N(0x0F1) /* Antenna 0 radar FIFO data */ +#define BWN_NPHY_A1RADAR_FIFODAT BWN_PHY_N(0x0F2) /* Antenna 1 radar FIFO data */ +#define BWN_NPHY_RADAR_THRES0 BWN_PHY_N(0x0F3) /* Radar threshold 0 */ +#define BWN_NPHY_RADAR_THRES1 BWN_PHY_N(0x0F4) /* Radar threshold 1 */ +#define BWN_NPHY_RADAR_THRES0R BWN_PHY_N(0x0F5) /* Radar threshold 0R */ +#define BWN_NPHY_RADAR_THRES1R BWN_PHY_N(0x0F6) /* Radar threshold 1R */ +#define BWN_NPHY_CSEN_20IN40_DLEN BWN_PHY_N(0x0F7) /* Carrier sense 20 in 40 dwell length */ +#define BWN_NPHY_RFCTL_LUT_TRSW_LO1 BWN_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */ +#define BWN_NPHY_RFCTL_LUT_TRSW_UP1 BWN_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */ +#define BWN_NPHY_RFCTL_LUT_TRSW_LO2 BWN_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */ +#define BWN_NPHY_RFCTL_LUT_TRSW_UP2 BWN_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */ +#define BWN_NPHY_RFCTL_LUT_TRSW_LO3 BWN_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */ +#define BWN_NPHY_RFCTL_LUT_TRSW_UP3 BWN_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */ +#define BWN_NPHY_RFCTL_LUT_TRSW_LO4 BWN_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */ +#define BWN_NPHY_RFCTL_LUT_TRSW_UP4 BWN_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */ +#define BWN_NPHY_RFCTL_LUT_LNAPA1 BWN_PHY_N(0x100) /* RF control LUT LNA PA 1 */ +#define BWN_NPHY_RFCTL_LUT_LNAPA2 BWN_PHY_N(0x101) /* RF control LUT LNA PA 2 */ +#define BWN_NPHY_RFCTL_LUT_LNAPA3 BWN_PHY_N(0x102) /* RF control LUT LNA PA 3 */ +#define BWN_NPHY_RFCTL_LUT_LNAPA4 BWN_PHY_N(0x103) /* RF control LUT LNA PA 4 */ +#define BWN_NPHY_TGNSYNC_CRCM0 BWN_PHY_N(0x104) /* TGNsync CRC mask 0 */ +#define BWN_NPHY_TGNSYNC_CRCM1 BWN_PHY_N(0x105) /* TGNsync CRC mask 1 */ +#define BWN_NPHY_TGNSYNC_CRCM2 BWN_PHY_N(0x106) /* TGNsync CRC mask 2 */ +#define BWN_NPHY_TGNSYNC_CRCM3 BWN_PHY_N(0x107) /* TGNsync CRC mask 3 */ +#define BWN_NPHY_TGNSYNC_CRCM4 BWN_PHY_N(0x108) /* TGNsync CRC mask 4 */ +#define BWN_NPHY_CRCPOLY BWN_PHY_N(0x109) /* CRC polynomial */ +#define BWN_NPHY_SIGCNT BWN_PHY_N(0x10A) /* # sig count */ +#define BWN_NPHY_SIGSTARTBIT_CTL BWN_PHY_N(0x10B) /* Sig start bit control */ +#define BWN_NPHY_CRCPOLY_ORDER BWN_PHY_N(0x10C) /* CRC polynomial order */ +#define BWN_NPHY_RFCTL_CST0 BWN_PHY_N(0x10D) /* RF control core swap table 0 */ +#define BWN_NPHY_RFCTL_CST1 BWN_PHY_N(0x10E) /* RF control core swap table 1 */ +#define BWN_NPHY_RFCTL_CST2O BWN_PHY_N(0x10F) /* RF control core swap table 2 + others */ +#define BWN_NPHY_BPHY_CTL5 BWN_PHY_N(0x111) /* B PHY control 5 */ +#define BWN_NPHY_RFSEQ_LPFBW BWN_PHY_N(0x112) /* RF seq LPF bandwidth */ +#define BWN_NPHY_TSSIBIAS1 BWN_PHY_N(0x114) /* TSSI bias val 1 */ +#define BWN_NPHY_TSSIBIAS2 BWN_PHY_N(0x115) /* TSSI bias val 2 */ +#define BWN_NPHY_TSSIBIAS_BIAS 0x00FF /* Bias */ +#define BWN_NPHY_TSSIBIAS_BIAS_SHIFT 0 +#define BWN_NPHY_TSSIBIAS_VAL 0xFF00 /* Value */ +#define BWN_NPHY_TSSIBIAS_VAL_SHIFT 8 +#define BWN_NPHY_ESTPWR1 BWN_PHY_N(0x118) /* Estimated power 1 */ +#define BWN_NPHY_ESTPWR2 BWN_PHY_N(0x119) /* Estimated power 2 */ +#define BWN_NPHY_ESTPWR_PWR 0x00FF /* Estimated power */ +#define BWN_NPHY_ESTPWR_PWR_SHIFT 0 +#define BWN_NPHY_ESTPWR_VALID 0x0100 /* Estimated power valid */ +#define BWN_NPHY_TSSI_MAXTXFDT BWN_PHY_N(0x11C) /* TSSI max TX frame delay time */ +#define BWN_NPHY_TSSI_MAXTXFDT_VAL 0x00FF /* max TX frame delay time */ +#define BWN_NPHY_TSSI_MAXTXFDT_VAL_SHIFT 0 +#define BWN_NPHY_TSSI_MAXTDT BWN_PHY_N(0x11D) /* TSSI max TSSI delay time */ +#define BWN_NPHY_TSSI_MAXTDT_VAL 0x00FF /* max TSSI delay time */ +#define BWN_NPHY_TSSI_MAXTDT_VAL_SHIFT 0 +#define BWN_NPHY_ITSSI1 BWN_PHY_N(0x11E) /* TSSI idle 1 */ +#define BWN_NPHY_ITSSI2 BWN_PHY_N(0x11F) /* TSSI idle 2 */ +#define BWN_NPHY_ITSSI_VAL 0x00FF /* Idle TSSI */ +#define BWN_NPHY_ITSSI_VAL_SHIFT 0 +#define BWN_NPHY_TSSIMODE BWN_PHY_N(0x122) /* TSSI mode */ +#define BWN_NPHY_TSSIMODE_EN 0x0001 /* TSSI enable */ +#define BWN_NPHY_TSSIMODE_PDEN 0x0002 /* Power det enable */ +#define BWN_NPHY_RXMACIFM BWN_PHY_N(0x123) /* RX Macif mode */ +#define BWN_NPHY_CRSIT_COCNT_LO BWN_PHY_N(0x124) /* CRS idle time CRS-on count (low) */ +#define BWN_NPHY_CRSIT_COCNT_HI BWN_PHY_N(0x125) /* CRS idle time CRS-on count (high) */ +#define BWN_NPHY_CRSIT_MTCNT_LO BWN_PHY_N(0x126) /* CRS idle time measure time count (low) */ +#define BWN_NPHY_CRSIT_MTCNT_HI BWN_PHY_N(0x127) /* CRS idle time measure time count (high) */ +#define BWN_NPHY_SAMTWC BWN_PHY_N(0x128) /* Sample tail wait count */ +#define BWN_NPHY_IQEST_CMD BWN_PHY_N(0x129) /* I/Q estimate command */ +#define BWN_NPHY_IQEST_CMD_START 0x0001 /* Start */ +#define BWN_NPHY_IQEST_CMD_MODE 0x0002 /* Mode */ +#define BWN_NPHY_IQEST_WT BWN_PHY_N(0x12A) /* I/Q estimate wait time */ +#define BWN_NPHY_IQEST_WT_VAL 0x00FF /* Wait time */ +#define BWN_NPHY_IQEST_WT_VAL_SHIFT 0 +#define BWN_NPHY_IQEST_SAMCNT BWN_PHY_N(0x12B) /* I/Q estimate sample count */ +#define BWN_NPHY_IQEST_IQACC_LO0 BWN_PHY_N(0x12C) /* I/Q estimate I/Q acc lo 0 */ +#define BWN_NPHY_IQEST_IQACC_HI0 BWN_PHY_N(0x12D) /* I/Q estimate I/Q acc hi 0 */ +#define BWN_NPHY_IQEST_IPACC_LO0 BWN_PHY_N(0x12E) /* I/Q estimate I power acc lo 0 */ +#define BWN_NPHY_IQEST_IPACC_HI0 BWN_PHY_N(0x12F) /* I/Q estimate I power acc hi 0 */ +#define BWN_NPHY_IQEST_QPACC_LO0 BWN_PHY_N(0x130) /* I/Q estimate Q power acc lo 0 */ +#define BWN_NPHY_IQEST_QPACC_HI0 BWN_PHY_N(0x131) /* I/Q estimate Q power acc hi 0 */ +#define BWN_NPHY_IQEST_IQACC_LO1 BWN_PHY_N(0x134) /* I/Q estimate I/Q acc lo 1 */ +#define BWN_NPHY_IQEST_IQACC_HI1 BWN_PHY_N(0x135) /* I/Q estimate I/Q acc hi 1 */ +#define BWN_NPHY_IQEST_IPACC_LO1 BWN_PHY_N(0x136) /* I/Q estimate I power acc lo 1 */ +#define BWN_NPHY_IQEST_IPACC_HI1 BWN_PHY_N(0x137) /* I/Q estimate I power acc hi 1 */ +#define BWN_NPHY_IQEST_QPACC_LO1 BWN_PHY_N(0x138) /* I/Q estimate Q power acc lo 1 */ +#define BWN_NPHY_IQEST_QPACC_HI1 BWN_PHY_N(0x139) /* I/Q estimate Q power acc hi 1 */ +#define BWN_NPHY_MIMO_CRSTXEXT BWN_PHY_N(0x13A) /* MIMO PHY CRS TX extension */ +#define BWN_NPHY_PWRDET1 BWN_PHY_N(0x13B) /* Power det 1 */ +#define BWN_NPHY_PWRDET2 BWN_PHY_N(0x13C) /* Power det 2 */ +#define BWN_NPHY_MAXRSSI_DTIME BWN_PHY_N(0x13F) /* RSSI max RSSI delay time */ +#define BWN_NPHY_PIL_DW0 BWN_PHY_N(0x141) /* Pilot data weight 0 */ +#define BWN_NPHY_PIL_DW1 BWN_PHY_N(0x142) /* Pilot data weight 1 */ +#define BWN_NPHY_PIL_DW2 BWN_PHY_N(0x143) /* Pilot data weight 2 */ +#define BWN_NPHY_PIL_DW_BPSK 0x000F /* BPSK */ +#define BWN_NPHY_PIL_DW_BPSK_SHIFT 0 +#define BWN_NPHY_PIL_DW_QPSK 0x00F0 /* QPSK */ +#define BWN_NPHY_PIL_DW_QPSK_SHIFT 4 +#define BWN_NPHY_PIL_DW_16QAM 0x0F00 /* 16-QAM */ +#define BWN_NPHY_PIL_DW_16QAM_SHIFT 8 +#define BWN_NPHY_PIL_DW_64QAM 0xF000 /* 64-QAM */ +#define BWN_NPHY_PIL_DW_64QAM_SHIFT 12 +#define BWN_NPHY_FMDEM_CFG BWN_PHY_N(0x144) /* FM demodulation config */ +#define BWN_NPHY_PHASETR_A0 BWN_PHY_N(0x145) /* Phase track alpha 0 */ +#define BWN_NPHY_PHASETR_A1 BWN_PHY_N(0x146) /* Phase track alpha 1 */ +#define BWN_NPHY_PHASETR_A2 BWN_PHY_N(0x147) /* Phase track alpha 2 */ +#define BWN_NPHY_PHASETR_B0 BWN_PHY_N(0x148) /* Phase track beta 0 */ +#define BWN_NPHY_PHASETR_B1 BWN_PHY_N(0x149) /* Phase track beta 1 */ +#define BWN_NPHY_PHASETR_B2 BWN_PHY_N(0x14A) /* Phase track beta 2 */ +#define BWN_NPHY_PHASETR_CHG0 BWN_PHY_N(0x14B) /* Phase track change 0 */ +#define BWN_NPHY_PHASETR_CHG1 BWN_PHY_N(0x14C) /* Phase track change 1 */ +#define BWN_NPHY_PHASETW_OFF BWN_PHY_N(0x14D) /* Phase track offset */ +#define BWN_NPHY_RFCTL_DBG BWN_PHY_N(0x14E) /* RF control debug */ +#define BWN_NPHY_CCK_SHIFTB_REF BWN_PHY_N(0x150) /* CCK shiftbits reference var */ +#define BWN_NPHY_OVER_DGAIN0 BWN_PHY_N(0x152) /* Override digital gain 0 */ +#define BWN_NPHY_OVER_DGAIN1 BWN_PHY_N(0x153) /* Override digital gain 1 */ +#define BWN_NPHY_OVER_DGAIN_FDGV 0x0007 /* Force digital gain value */ +#define BWN_NPHY_OVER_DGAIN_FDGV_SHIFT 0 +#define BWN_NPHY_OVER_DGAIN_FDGEN 0x0008 /* Force digital gain enable */ +#define BWN_NPHY_OVER_DGAIN_CCKDGECV 0xFF00 /* CCK digital gain enable count value */ +#define BWN_NPHY_OVER_DGAIN_CCKDGECV_SHIFT 8 +#define BWN_NPHY_BIST_STAT4 BWN_PHY_N(0x156) /* BIST status 4 */ +#define BWN_NPHY_RADAR_MAL BWN_PHY_N(0x157) /* Radar MA length */ +#define BWN_NPHY_RADAR_SRCCTL BWN_PHY_N(0x158) /* Radar search control */ +#define BWN_NPHY_VLD_DTSIG BWN_PHY_N(0x159) /* VLD data tones sig */ +#define BWN_NPHY_VLD_DTDAT BWN_PHY_N(0x15A) /* VLD data tones data */ +#define BWN_NPHY_C1_BPHY_RXIQCA0 BWN_PHY_N(0x15B) /* Core 1 B PHY RX I/Q comp A0 */ +#define BWN_NPHY_C1_BPHY_RXIQCB0 BWN_PHY_N(0x15C) /* Core 1 B PHY RX I/Q comp B0 */ +#define BWN_NPHY_C2_BPHY_RXIQCA1 BWN_PHY_N(0x15D) /* Core 2 B PHY RX I/Q comp A1 */ +#define BWN_NPHY_C2_BPHY_RXIQCB1 BWN_PHY_N(0x15E) /* Core 2 B PHY RX I/Q comp B1 */ +#define BWN_NPHY_FREQGAIN0 BWN_PHY_N(0x160) /* Frequency gain 0 */ +#define BWN_NPHY_FREQGAIN1 BWN_PHY_N(0x161) /* Frequency gain 1 */ +#define BWN_NPHY_FREQGAIN2 BWN_PHY_N(0x162) /* Frequency gain 2 */ +#define BWN_NPHY_FREQGAIN3 BWN_PHY_N(0x163) /* Frequency gain 3 */ +#define BWN_NPHY_FREQGAIN4 BWN_PHY_N(0x164) /* Frequency gain 4 */ +#define BWN_NPHY_FREQGAIN5 BWN_PHY_N(0x165) /* Frequency gain 5 */ +#define BWN_NPHY_FREQGAIN6 BWN_PHY_N(0x166) /* Frequency gain 6 */ +#define BWN_NPHY_FREQGAIN7 BWN_PHY_N(0x167) /* Frequency gain 7 */ +#define BWN_NPHY_FREQGAIN_BYPASS BWN_PHY_N(0x168) /* Frequency gain bypass */ +#define BWN_NPHY_TRLOSS BWN_PHY_N(0x169) /* TR loss value */ +#define BWN_NPHY_C1_ADCCLIP BWN_PHY_N(0x16A) /* Core 1 ADC clip */ +#define BWN_NPHY_C2_ADCCLIP BWN_PHY_N(0x16B) /* Core 2 ADC clip */ +#define BWN_NPHY_LTRN_OFFGAIN BWN_PHY_N(0x16F) /* LTRN offset gain */ +#define BWN_NPHY_LTRN_OFF BWN_PHY_N(0x170) /* LTRN offset */ +#define BWN_NPHY_NRDATAT_WWISE20SIG BWN_PHY_N(0x171) /* # data tones WWiSE 20 sig */ +#define BWN_NPHY_NRDATAT_WWISE40SIG BWN_PHY_N(0x172) /* # data tones WWiSE 40 sig */ +#define BWN_NPHY_NRDATAT_TGNSYNC20SIG BWN_PHY_N(0x173) /* # data tones TGNsync 20 sig */ +#define BWN_NPHY_NRDATAT_TGNSYNC40SIG BWN_PHY_N(0x174) /* # data tones TGNsync 40 sig */ +#define BWN_NPHY_WWISE_CRCM0 BWN_PHY_N(0x175) /* WWiSE CRC mask 0 */ +#define BWN_NPHY_WWISE_CRCM1 BWN_PHY_N(0x176) /* WWiSE CRC mask 1 */ +#define BWN_NPHY_WWISE_CRCM2 BWN_PHY_N(0x177) /* WWiSE CRC mask 2 */ +#define BWN_NPHY_WWISE_CRCM3 BWN_PHY_N(0x178) /* WWiSE CRC mask 3 */ +#define BWN_NPHY_WWISE_CRCM4 BWN_PHY_N(0x179) /* WWiSE CRC mask 4 */ +#define BWN_NPHY_CHANEST_CDDSH BWN_PHY_N(0x17A) /* Channel estimate CDD shift */ +#define BWN_NPHY_HTAGC_WCNT BWN_PHY_N(0x17B) /* HT ADC wait counters */ +#define BWN_NPHY_SQPARM BWN_PHY_N(0x17C) /* SQ params */ +#define BWN_NPHY_MCSDUP6M BWN_PHY_N(0x17D) /* MCS dup 6M */ +#define BWN_NPHY_NDATAT_DUP40 BWN_PHY_N(0x17E) /* # data tones dup 40 */ +#define BWN_NPHY_DUP40_TGNSYNC_CYCD BWN_PHY_N(0x17F) /* Dup40 TGNsync cycle data */ +#define BWN_NPHY_DUP40_GFBL BWN_PHY_N(0x180) /* Dup40 GF format BL address */ +#define BWN_NPHY_DUP40_BL BWN_PHY_N(0x181) /* Dup40 format BL address */ +#define BWN_NPHY_LEGDUP_FTA BWN_PHY_N(0x182) /* Legacy dup frm table address */ +#define BWN_NPHY_PACPROC_DBG BWN_PHY_N(0x183) /* Packet processing debug */ +#define BWN_NPHY_PIL_CYC1 BWN_PHY_N(0x184) /* Pilot cycle counter 1 */ +#define BWN_NPHY_PIL_CYC2 BWN_PHY_N(0x185) /* Pilot cycle counter 2 */ +#define BWN_NPHY_TXF_20CO_S0A1 BWN_PHY_N(0x186) /* TX filter 20 coeff stage 0 A1 */ +#define BWN_NPHY_TXF_20CO_S0A2 BWN_PHY_N(0x187) /* TX filter 20 coeff stage 0 A2 */ +#define BWN_NPHY_TXF_20CO_S1A1 BWN_PHY_N(0x188) /* TX filter 20 coeff stage 1 A1 */ +#define BWN_NPHY_TXF_20CO_S1A2 BWN_PHY_N(0x189) /* TX filter 20 coeff stage 1 A2 */ +#define BWN_NPHY_TXF_20CO_S2A1 BWN_PHY_N(0x18A) /* TX filter 20 coeff stage 2 A1 */ +#define BWN_NPHY_TXF_20CO_S2A2 BWN_PHY_N(0x18B) /* TX filter 20 coeff stage 2 A2 */ +#define BWN_NPHY_TXF_20CO_S0B1 BWN_PHY_N(0x18C) /* TX filter 20 coeff stage 0 B1 */ +#define BWN_NPHY_TXF_20CO_S0B2 BWN_PHY_N(0x18D) /* TX filter 20 coeff stage 0 B2 */ +#define BWN_NPHY_TXF_20CO_S0B3 BWN_PHY_N(0x18E) /* TX filter 20 coeff stage 0 B3 */ +#define BWN_NPHY_TXF_20CO_S1B1 BWN_PHY_N(0x18F) /* TX filter 20 coeff stage 1 B1 */ +#define BWN_NPHY_TXF_20CO_S1B2 BWN_PHY_N(0x190) /* TX filter 20 coeff stage 1 B2 */ +#define BWN_NPHY_TXF_20CO_S1B3 BWN_PHY_N(0x191) /* TX filter 20 coeff stage 1 B3 */ +#define BWN_NPHY_TXF_20CO_S2B1 BWN_PHY_N(0x192) /* TX filter 20 coeff stage 2 B1 */ +#define BWN_NPHY_TXF_20CO_S2B2 BWN_PHY_N(0x193) /* TX filter 20 coeff stage 2 B2 */ +#define BWN_NPHY_TXF_20CO_S2B3 BWN_PHY_N(0x194) /* TX filter 20 coeff stage 2 B3 */ +#define BWN_NPHY_TXF_40CO_S0A1 BWN_PHY_N(0x195) /* TX filter 40 coeff stage 0 A1 */ +#define BWN_NPHY_TXF_40CO_S0A2 BWN_PHY_N(0x196) /* TX filter 40 coeff stage 0 A2 */ +#define BWN_NPHY_TXF_40CO_S1A1 BWN_PHY_N(0x197) /* TX filter 40 coeff stage 1 A1 */ +#define BWN_NPHY_TXF_40CO_S1A2 BWN_PHY_N(0x198) /* TX filter 40 coeff stage 1 A2 */ +#define BWN_NPHY_TXF_40CO_S2A1 BWN_PHY_N(0x199) /* TX filter 40 coeff stage 2 A1 */ +#define BWN_NPHY_TXF_40CO_S2A2 BWN_PHY_N(0x19A) /* TX filter 40 coeff stage 2 A2 */ +#define BWN_NPHY_TXF_40CO_S0B1 BWN_PHY_N(0x19B) /* TX filter 40 coeff stage 0 B1 */ +#define BWN_NPHY_TXF_40CO_S0B2 BWN_PHY_N(0x19C) /* TX filter 40 coeff stage 0 B2 */ +#define BWN_NPHY_TXF_40CO_S0B3 BWN_PHY_N(0x19D) /* TX filter 40 coeff stage 0 B3 */ +#define BWN_NPHY_TXF_40CO_S1B1 BWN_PHY_N(0x19E) /* TX filter 40 coeff stage 1 B1 */ +#define BWN_NPHY_TXF_40CO_S1B2 BWN_PHY_N(0x19F) /* TX filter 40 coeff stage 1 B2 */ +#define BWN_NPHY_TXF_40CO_S1B3 BWN_PHY_N(0x1A0) /* TX filter 40 coeff stage 1 B3 */ +#define BWN_NPHY_TXF_40CO_S2B1 BWN_PHY_N(0x1A1) /* TX filter 40 coeff stage 2 B1 */ +#define BWN_NPHY_TXF_40CO_S2B2 BWN_PHY_N(0x1A2) /* TX filter 40 coeff stage 2 B2 */ +#define BWN_NPHY_TXF_40CO_S2B3 BWN_PHY_N(0x1A3) /* TX filter 40 coeff stage 2 B3 */ +#define BWN_NPHY_RSSIMC_0I_RSSI_X BWN_PHY_N(0x1A4) /* RSSI multiplication coefficient 0 I RSSI X */ +#define BWN_NPHY_RSSIMC_0I_RSSI_Y BWN_PHY_N(0x1A5) /* RSSI multiplication coefficient 0 I RSSI Y */ +#define BWN_NPHY_RSSIMC_0I_RSSI_Z BWN_PHY_N(0x1A6) /* RSSI multiplication coefficient 0 I RSSI Z */ +#define BWN_NPHY_RSSIMC_0I_TBD BWN_PHY_N(0x1A7) /* RSSI multiplication coefficient 0 I TBD */ +#define BWN_NPHY_RSSIMC_0I_PWRDET BWN_PHY_N(0x1A8) /* RSSI multiplication coefficient 0 I power det */ +#define BWN_NPHY_RSSIMC_0I_TSSI BWN_PHY_N(0x1A9) /* RSSI multiplication coefficient 0 I TSSI */ +#define BWN_NPHY_RSSIMC_0Q_RSSI_X BWN_PHY_N(0x1AA) /* RSSI multiplication coefficient 0 Q RSSI X */ +#define BWN_NPHY_RSSIMC_0Q_RSSI_Y BWN_PHY_N(0x1AB) /* RSSI multiplication coefficient 0 Q RSSI Y */ +#define BWN_NPHY_RSSIMC_0Q_RSSI_Z BWN_PHY_N(0x1AC) /* RSSI multiplication coefficient 0 Q RSSI Z */ +#define BWN_NPHY_RSSIMC_0Q_TBD BWN_PHY_N(0x1AD) /* RSSI multiplication coefficient 0 Q TBD */ +#define BWN_NPHY_RSSIMC_0Q_PWRDET BWN_PHY_N(0x1AE) /* RSSI multiplication coefficient 0 Q power det */ +#define BWN_NPHY_RSSIMC_0Q_TSSI BWN_PHY_N(0x1AF) /* RSSI multiplication coefficient 0 Q TSSI */ +#define BWN_NPHY_RSSIMC_1I_RSSI_X BWN_PHY_N(0x1B0) /* RSSI multiplication coefficient 1 I RSSI X */ +#define BWN_NPHY_RSSIMC_1I_RSSI_Y BWN_PHY_N(0x1B1) /* RSSI multiplication coefficient 1 I RSSI Y */ +#define BWN_NPHY_RSSIMC_1I_RSSI_Z BWN_PHY_N(0x1B2) /* RSSI multiplication coefficient 1 I RSSI Z */ +#define BWN_NPHY_RSSIMC_1I_TBD BWN_PHY_N(0x1B3) /* RSSI multiplication coefficient 1 I TBD */ +#define BWN_NPHY_RSSIMC_1I_PWRDET BWN_PHY_N(0x1B4) /* RSSI multiplication coefficient 1 I power det */ +#define BWN_NPHY_RSSIMC_1I_TSSI BWN_PHY_N(0x1B5) /* RSSI multiplication coefficient 1 I TSSI */ +#define BWN_NPHY_RSSIMC_1Q_RSSI_X BWN_PHY_N(0x1B6) /* RSSI multiplication coefficient 1 Q RSSI X */ +#define BWN_NPHY_RSSIMC_1Q_RSSI_Y BWN_PHY_N(0x1B7) /* RSSI multiplication coefficient 1 Q RSSI Y */ +#define BWN_NPHY_RSSIMC_1Q_RSSI_Z BWN_PHY_N(0x1B8) /* RSSI multiplication coefficient 1 Q RSSI Z */ +#define BWN_NPHY_RSSIMC_1Q_TBD BWN_PHY_N(0x1B9) /* RSSI multiplication coefficient 1 Q TBD */ +#define BWN_NPHY_RSSIMC_1Q_PWRDET BWN_PHY_N(0x1BA) /* RSSI multiplication coefficient 1 Q power det */ +#define BWN_NPHY_RSSIMC_1Q_TSSI BWN_PHY_N(0x1BB) /* RSSI multiplication coefficient 1 Q TSSI */ +#define BWN_NPHY_SAMC_WCNT BWN_PHY_N(0x1BC) /* Sample collect wait counter */ +#define BWN_NPHY_PTHROUGH_CNT BWN_PHY_N(0x1BD) /* Pass-through counter */ +#define BWN_NPHY_LTRN_OFF_G20L BWN_PHY_N(0x1C4) /* LTRN offset gain 20L */ +#define BWN_NPHY_LTRN_OFF_20L BWN_PHY_N(0x1C5) /* LTRN offset 20L */ +#define BWN_NPHY_LTRN_OFF_G20U BWN_PHY_N(0x1C6) /* LTRN offset gain 20U */ +#define BWN_NPHY_LTRN_OFF_20U BWN_PHY_N(0x1C7) /* LTRN offset 20U */ +#define BWN_NPHY_DSSSCCK_GAINSL BWN_PHY_N(0x1C8) /* DSSS/CCK gain settle length */ +#define BWN_NPHY_GPIO_LOOUT BWN_PHY_N(0x1C9) /* GPIO low out */ +#define BWN_NPHY_GPIO_HIOUT BWN_PHY_N(0x1CA) /* GPIO high out */ +#define BWN_NPHY_CRS_CHECK BWN_PHY_N(0x1CB) /* CRS check */ +#define BWN_NPHY_ML_LOGSS_RAT BWN_PHY_N(0x1CC) /* ML/logss ratio */ +#define BWN_NPHY_DUPSCALE BWN_PHY_N(0x1CD) /* Dup scale */ +#define BWN_NPHY_BW1A BWN_PHY_N(0x1CE) /* BW 1A */ +#define BWN_NPHY_BW2 BWN_PHY_N(0x1CF) /* BW 2 */ +#define BWN_NPHY_BW3 BWN_PHY_N(0x1D0) /* BW 3 */ +#define BWN_NPHY_BW4 BWN_PHY_N(0x1D1) /* BW 4 */ +#define BWN_NPHY_BW5 BWN_PHY_N(0x1D2) /* BW 5 */ +#define BWN_NPHY_BW6 BWN_PHY_N(0x1D3) /* BW 6 */ +#define BWN_NPHY_COALEN0 BWN_PHY_N(0x1D4) /* Coarse length 0 */ +#define BWN_NPHY_COALEN1 BWN_PHY_N(0x1D5) /* Coarse length 1 */ +#define BWN_NPHY_CRSTHRES_1U BWN_PHY_N(0x1D6) /* CRS threshold 1 U */ +#define BWN_NPHY_CRSTHRES_2U BWN_PHY_N(0x1D7) /* CRS threshold 2 U */ +#define BWN_NPHY_CRSTHRES_3U BWN_PHY_N(0x1D8) /* CRS threshold 3 U */ +#define BWN_NPHY_CRSCTL_U BWN_PHY_N(0x1D9) /* CRS control U */ +#define BWN_NPHY_CRSTHRES_1L BWN_PHY_N(0x1DA) /* CRS threshold 1 L */ +#define BWN_NPHY_CRSTHRES_2L BWN_PHY_N(0x1DB) /* CRS threshold 2 L */ +#define BWN_NPHY_CRSTHRES_3L BWN_PHY_N(0x1DC) /* CRS threshold 3 L */ +#define BWN_NPHY_CRSCTL_L BWN_PHY_N(0x1DD) /* CRS control L */ +#define BWN_NPHY_STRA_1U BWN_PHY_N(0x1DE) /* STR address 1 U */ +#define BWN_NPHY_STRA_2U BWN_PHY_N(0x1DF) /* STR address 2 U */ +#define BWN_NPHY_STRA_1L BWN_PHY_N(0x1E0) /* STR address 1 L */ +#define BWN_NPHY_STRA_2L BWN_PHY_N(0x1E1) /* STR address 2 L */ +#define BWN_NPHY_CRSCHECK1 BWN_PHY_N(0x1E2) /* CRS check 1 */ +#define BWN_NPHY_CRSCHECK2 BWN_PHY_N(0x1E3) /* CRS check 2 */ +#define BWN_NPHY_CRSCHECK3 BWN_PHY_N(0x1E4) /* CRS check 3 */ +#define BWN_NPHY_JMPSTP0 BWN_PHY_N(0x1E5) /* Jump step 0 */ +#define BWN_NPHY_JMPSTP1 BWN_PHY_N(0x1E6) /* Jump step 1 */ +#define BWN_NPHY_TXPCTL_CMD BWN_PHY_N(0x1E7) /* TX power control command */ +#define BWN_NPHY_TXPCTL_CMD_INIT 0x007F /* Init */ +#define BWN_NPHY_TXPCTL_CMD_INIT_SHIFT 0 +#define BWN_NPHY_TXPCTL_CMD_COEFF 0x2000 /* Power control coefficients */ +#define BWN_NPHY_TXPCTL_CMD_HWPCTLEN 0x4000 /* Hardware TX power control enable */ +#define BWN_NPHY_TXPCTL_CMD_PCTLEN 0x8000 /* TX power control enable */ +#define BWN_NPHY_TXPCTL_N BWN_PHY_N(0x1E8) /* TX power control N num */ +#define BWN_NPHY_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */ +#define BWN_NPHY_TXPCTL_N_TSSID_SHIFT 0 +#define BWN_NPHY_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */ +#define BWN_NPHY_TXPCTL_N_NPTIL2_SHIFT 8 +#define BWN_NPHY_TXPCTL_ITSSI BWN_PHY_N(0x1E9) /* TX power control idle TSSI */ +#define BWN_NPHY_TXPCTL_ITSSI_0 0x003F /* Idle TSSI 0 */ +#define BWN_NPHY_TXPCTL_ITSSI_0_SHIFT 0 +#define BWN_NPHY_TXPCTL_ITSSI_1 0x3F00 /* Idle TSSI 1 */ +#define BWN_NPHY_TXPCTL_ITSSI_1_SHIFT 8 +#define BWN_NPHY_TXPCTL_ITSSI_BINF 0x8000 /* Raw TSSI offset bin format */ +#define BWN_NPHY_TXPCTL_TPWR BWN_PHY_N(0x1EA) /* TX power control target power */ +#define BWN_NPHY_TXPCTL_TPWR_0 0x00FF /* Power 0 */ +#define BWN_NPHY_TXPCTL_TPWR_0_SHIFT 0 +#define BWN_NPHY_TXPCTL_TPWR_1 0xFF00 /* Power 1 */ +#define BWN_NPHY_TXPCTL_TPWR_1_SHIFT 8 +#define BWN_NPHY_TXPCTL_BIDX BWN_PHY_N(0x1EB) /* TX power control base index */ +#define BWN_NPHY_TXPCTL_BIDX_0 0x007F /* uC base index 0 */ +#define BWN_NPHY_TXPCTL_BIDX_0_SHIFT 0 +#define BWN_NPHY_TXPCTL_BIDX_1 0x7F00 /* uC base index 1 */ +#define BWN_NPHY_TXPCTL_BIDX_1_SHIFT 8 +#define BWN_NPHY_TXPCTL_BIDX_LOAD 0x8000 /* Load base index */ +#define BWN_NPHY_TXPCTL_PIDX BWN_PHY_N(0x1EC) /* TX power control power index */ +#define BWN_NPHY_TXPCTL_PIDX_0 0x007F /* uC power index 0 */ +#define BWN_NPHY_TXPCTL_PIDX_0_SHIFT 0 +#define BWN_NPHY_TXPCTL_PIDX_1 0x7F00 /* uC power index 1 */ +#define BWN_NPHY_TXPCTL_PIDX_1_SHIFT 8 +#define BWN_NPHY_C1_TXPCTL_STAT BWN_PHY_N(0x1ED) /* Core 1 TX power control status */ +#define BWN_NPHY_C2_TXPCTL_STAT BWN_PHY_N(0x1EE) /* Core 2 TX power control status */ +#define BWN_NPHY_TXPCTL_STAT_EST 0x00FF /* Estimated power */ +#define BWN_NPHY_TXPCTL_STAT_EST_SHIFT 0 +#define BWN_NPHY_TXPCTL_STAT_BIDX 0x7F00 /* Base index */ +#define BWN_NPHY_TXPCTL_STAT_BIDX_SHIFT 8 +#define BWN_NPHY_TXPCTL_STAT_ESTVALID 0x8000 /* Estimated power valid */ +#define BWN_NPHY_SMALLSGS_LEN BWN_PHY_N(0x1EF) /* Small sig gain settle length */ +#define BWN_NPHY_PHYSTAT_GAIN0 BWN_PHY_N(0x1F0) /* PHY stats gain info 0 */ +#define BWN_NPHY_PHYSTAT_GAIN1 BWN_PHY_N(0x1F1) /* PHY stats gain info 1 */ +#define BWN_NPHY_PHYSTAT_FREQEST BWN_PHY_N(0x1F2) /* PHY stats frequency estimate */ +#define BWN_NPHY_PHYSTAT_ADVRET BWN_PHY_N(0x1F3) /* PHY stats ADV retard */ +#define BWN_NPHY_PHYLB_MODE BWN_PHY_N(0x1F4) /* PHY loopback mode */ +#define BWN_NPHY_TONE_MIDX20_1 BWN_PHY_N(0x1F5) /* Tone map index 20/1 */ +#define BWN_NPHY_TONE_MIDX20_2 BWN_PHY_N(0x1F6) /* Tone map index 20/2 */ +#define BWN_NPHY_TONE_MIDX20_3 BWN_PHY_N(0x1F7) /* Tone map index 20/3 */ +#define BWN_NPHY_TONE_MIDX40_1 BWN_PHY_N(0x1F8) /* Tone map index 40/1 */ +#define BWN_NPHY_TONE_MIDX40_2 BWN_PHY_N(0x1F9) /* Tone map index 40/2 */ +#define BWN_NPHY_TONE_MIDX40_3 BWN_PHY_N(0x1FA) /* Tone map index 40/3 */ +#define BWN_NPHY_TONE_MIDX40_4 BWN_PHY_N(0x1FB) /* Tone map index 40/4 */ +#define BWN_NPHY_PILTONE_MIDX1 BWN_PHY_N(0x1FC) /* Pilot tone map index 1 */ +#define BWN_NPHY_PILTONE_MIDX2 BWN_PHY_N(0x1FD) /* Pilot tone map index 2 */ +#define BWN_NPHY_PILTONE_MIDX3 BWN_PHY_N(0x1FE) /* Pilot tone map index 3 */ +#define BWN_NPHY_TXRIFS_FRDEL BWN_PHY_N(0x1FF) /* TX RIFS frame delay */ +#define BWN_NPHY_AFESEQ_RX2TX_PUD_40M BWN_PHY_N(0x200) /* AFE seq rx2tx power up/down delay 40M */ +#define BWN_NPHY_AFESEQ_TX2RX_PUD_40M BWN_PHY_N(0x201) /* AFE seq tx2rx power up/down delay 40M */ +#define BWN_NPHY_AFESEQ_RX2TX_PUD_20M BWN_PHY_N(0x202) /* AFE seq rx2tx power up/down delay 20M */ +#define BWN_NPHY_AFESEQ_TX2RX_PUD_20M BWN_PHY_N(0x203) /* AFE seq tx2rx power up/down delay 20M */ +#define BWN_NPHY_RX_SIGCTL BWN_PHY_N(0x204) /* RX signal control */ +#define BWN_NPHY_RXPIL_CYCNT0 BWN_PHY_N(0x205) /* RX pilot cycle counter 0 */ +#define BWN_NPHY_RXPIL_CYCNT1 BWN_PHY_N(0x206) /* RX pilot cycle counter 1 */ +#define BWN_NPHY_RXPIL_CYCNT2 BWN_PHY_N(0x207) /* RX pilot cycle counter 2 */ +#define BWN_NPHY_AFESEQ_RX2TX_PUD_10M BWN_PHY_N(0x208) /* AFE seq rx2tx power up/down delay 10M */ +#define BWN_NPHY_AFESEQ_TX2RX_PUD_10M BWN_PHY_N(0x209) /* AFE seq tx2rx power up/down delay 10M */ +#define BWN_NPHY_DSSSCCK_CRSEXTL BWN_PHY_N(0x20A) /* DSSS/CCK CRS extension length */ +#define BWN_NPHY_ML_LOGSS_RATSLOPE BWN_PHY_N(0x20B) /* ML/logss ratio slope */ +#define BWN_NPHY_RIFS_SRCTL BWN_PHY_N(0x20C) /* RIFS search timeout length */ +#define BWN_NPHY_TXREALFD BWN_PHY_N(0x20D) /* TX real frame delay */ +#define BWN_NPHY_HPANT_SWTHRES BWN_PHY_N(0x20E) /* High power antenna switch threshold */ +#define BWN_NPHY_EDCRS_ASSTHRES0 BWN_PHY_N(0x210) /* ED CRS assert threshold 0 */ +#define BWN_NPHY_EDCRS_ASSTHRES1 BWN_PHY_N(0x211) /* ED CRS assert threshold 1 */ +#define BWN_NPHY_EDCRS_DEASSTHRES0 BWN_PHY_N(0x212) /* ED CRS deassert threshold 0 */ +#define BWN_NPHY_EDCRS_DEASSTHRES1 BWN_PHY_N(0x213) /* ED CRS deassert threshold 1 */ +#define BWN_NPHY_STR_WTIME20U BWN_PHY_N(0x214) /* STR wait time 20U */ +#define BWN_NPHY_STR_WTIME20L BWN_PHY_N(0x215) /* STR wait time 20L */ +#define BWN_NPHY_TONE_MIDX657M BWN_PHY_N(0x216) /* Tone map index 657M */ +#define BWN_NPHY_HTSIGTONES BWN_PHY_N(0x217) /* HT signal tones */ +#define BWN_NPHY_RSSI1 BWN_PHY_N(0x219) /* RSSI value 1 */ +#define BWN_NPHY_RSSI2 BWN_PHY_N(0x21A) /* RSSI value 2 */ +#define BWN_NPHY_CHAN_ESTHANG BWN_PHY_N(0x21D) /* Channel estimate hang */ +#define BWN_NPHY_FINERX2_CGC BWN_PHY_N(0x221) /* Fine RX 2 clock gate control */ +#define BWN_NPHY_FINERX2_CGC_DECGC 0x0008 /* Decode gated clocks */ +#define BWN_NPHY_TXPCTL_INIT BWN_PHY_N(0x222) /* TX power control init */ +#define BWN_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ +#define BWN_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 +#define BWN_NPHY_ED_CRSEN BWN_PHY_N(0x223) +#define BWN_NPHY_ED_CRS40ASSERTTHRESH0 BWN_PHY_N(0x224) +#define BWN_NPHY_ED_CRS40ASSERTTHRESH1 BWN_PHY_N(0x225) +#define BWN_NPHY_ED_CRS40DEASSERTTHRESH0 BWN_PHY_N(0x226) +#define BWN_NPHY_ED_CRS40DEASSERTTHRESH1 BWN_PHY_N(0x227) +#define BWN_NPHY_ED_CRS20LASSERTTHRESH0 BWN_PHY_N(0x228) +#define BWN_NPHY_ED_CRS20LASSERTTHRESH1 BWN_PHY_N(0x229) +#define BWN_NPHY_ED_CRS20LDEASSERTTHRESH0 BWN_PHY_N(0x22A) +#define BWN_NPHY_ED_CRS20LDEASSERTTHRESH1 BWN_PHY_N(0x22B) +#define BWN_NPHY_ED_CRS20UASSERTTHRESH0 BWN_PHY_N(0x22C) +#define BWN_NPHY_ED_CRS20UASSERTTHRESH1 BWN_PHY_N(0x22D) +#define BWN_NPHY_ED_CRS20UDEASSERTTHRESH0 BWN_PHY_N(0x22E) +#define BWN_NPHY_ED_CRS20UDEASSERTTHRESH1 BWN_PHY_N(0x22F) +#define BWN_NPHY_ED_CRS BWN_PHY_N(0x230) +#define BWN_NPHY_TIMEOUTEN BWN_PHY_N(0x231) +#define BWN_NPHY_OFDMPAYDECODETIMEOUTLEN BWN_PHY_N(0x232) +#define BWN_NPHY_CCKPAYDECODETIMEOUTLEN BWN_PHY_N(0x233) +#define BWN_NPHY_NONPAYDECODETIMEOUTLEN BWN_PHY_N(0x234) +#define BWN_NPHY_TIMEOUTSTATUS BWN_PHY_N(0x235) +#define BWN_NPHY_RFCTRLCORE0GPIO0 BWN_PHY_N(0x236) +#define BWN_NPHY_RFCTRLCORE0GPIO1 BWN_PHY_N(0x237) +#define BWN_NPHY_RFCTRLCORE0GPIO2 BWN_PHY_N(0x238) +#define BWN_NPHY_RFCTRLCORE0GPIO3 BWN_PHY_N(0x239) +#define BWN_NPHY_RFCTRLCORE1GPIO0 BWN_PHY_N(0x23A) +#define BWN_NPHY_RFCTRLCORE1GPIO1 BWN_PHY_N(0x23B) +#define BWN_NPHY_RFCTRLCORE1GPIO2 BWN_PHY_N(0x23C) +#define BWN_NPHY_RFCTRLCORE1GPIO3 BWN_PHY_N(0x23D) +#define BWN_NPHY_BPHYTESTCONTROL BWN_PHY_N(0x23E) + +/* REV3+ */ +#define BWN_NPHY_FORCEFRONT0 BWN_PHY_N(0x23F) +#define BWN_NPHY_FORCEFRONT1 BWN_PHY_N(0x240) +#define BWN_NPHY_NORMVARHYSTTH BWN_PHY_N(0x241) +#define BWN_NPHY_TXCCKERROR BWN_PHY_N(0x242) +#define BWN_NPHY_AFESEQINITDACGAIN BWN_PHY_N(0x243) +#define BWN_NPHY_TXANTSWLUT BWN_PHY_N(0x244) +#define BWN_NPHY_CORECONFIG BWN_PHY_N(0x245) +#define BWN_NPHY_ANTENNADIVDWELLTIME BWN_PHY_N(0x246) +#define BWN_NPHY_ANTENNACCKDIVDWELLTIME BWN_PHY_N(0x247) +#define BWN_NPHY_ANTENNADIVBACKOFFGAIN BWN_PHY_N(0x248) +#define BWN_NPHY_ANTENNADIVMINGAIN BWN_PHY_N(0x249) +#define BWN_NPHY_BRDSEL_NORMVARHYSTTH BWN_PHY_N(0x24A) +#define BWN_NPHY_RXANTSWITCHCTRL BWN_PHY_N(0x24B) +#define BWN_NPHY_ENERGYDROPTIMEOUTLEN2 BWN_PHY_N(0x24C) +#define BWN_NPHY_ML_LOG_TXEVM0 BWN_PHY_N(0x250) +#define BWN_NPHY_ML_LOG_TXEVM1 BWN_PHY_N(0x251) +#define BWN_NPHY_ML_LOG_TXEVM2 BWN_PHY_N(0x252) +#define BWN_NPHY_ML_LOG_TXEVM3 BWN_PHY_N(0x253) +#define BWN_NPHY_ML_LOG_TXEVM4 BWN_PHY_N(0x254) +#define BWN_NPHY_ML_LOG_TXEVM5 BWN_PHY_N(0x255) +#define BWN_NPHY_ML_LOG_TXEVM6 BWN_PHY_N(0x256) +#define BWN_NPHY_ML_LOG_TXEVM7 BWN_PHY_N(0x257) +#define BWN_NPHY_ML_SCALE_TWEAK BWN_PHY_N(0x258) +#define BWN_NPHY_MLUA BWN_PHY_N(0x259) +#define BWN_NPHY_ZFUA BWN_PHY_N(0x25A) +#define BWN_NPHY_CHANUPSYM01 BWN_PHY_N(0x25B) +#define BWN_NPHY_CHANUPSYM2 BWN_PHY_N(0x25C) +#define BWN_NPHY_RXSTRNFILT20NUM00 BWN_PHY_N(0x25D) +#define BWN_NPHY_RXSTRNFILT20NUM01 BWN_PHY_N(0x25E) +#define BWN_NPHY_RXSTRNFILT20NUM02 BWN_PHY_N(0x25F) +#define BWN_NPHY_RXSTRNFILT20DEN00 BWN_PHY_N(0x260) +#define BWN_NPHY_RXSTRNFILT20DEN01 BWN_PHY_N(0x261) +#define BWN_NPHY_RXSTRNFILT20NUM10 BWN_PHY_N(0x262) +#define BWN_NPHY_RXSTRNFILT20NUM11 BWN_PHY_N(0x263) +#define BWN_NPHY_RXSTRNFILT20NUM12 BWN_PHY_N(0x264) +#define BWN_NPHY_RXSTRNFILT20DEN10 BWN_PHY_N(0x265) +#define BWN_NPHY_RXSTRNFILT20DEN11 BWN_PHY_N(0x266) +#define BWN_NPHY_RXSTRNFILT40NUM00 BWN_PHY_N(0x267) +#define BWN_NPHY_RXSTRNFILT40NUM01 BWN_PHY_N(0x268) +#define BWN_NPHY_RXSTRNFILT40NUM02 BWN_PHY_N(0x269) +#define BWN_NPHY_RXSTRNFILT40DEN00 BWN_PHY_N(0x26A) +#define BWN_NPHY_RXSTRNFILT40DEN01 BWN_PHY_N(0x26B) +#define BWN_NPHY_RXSTRNFILT40NUM10 BWN_PHY_N(0x26C) +#define BWN_NPHY_RXSTRNFILT40NUM11 BWN_PHY_N(0x26D) +#define BWN_NPHY_RXSTRNFILT40NUM12 BWN_PHY_N(0x26E) +#define BWN_NPHY_RXSTRNFILT40DEN10 BWN_PHY_N(0x26F) +#define BWN_NPHY_RXSTRNFILT40DEN11 BWN_PHY_N(0x270) +#define BWN_NPHY_CRSHIGHPOWTHRESHOLD1 BWN_PHY_N(0x271) +#define BWN_NPHY_CRSHIGHPOWTHRESHOLD2 BWN_PHY_N(0x272) +#define BWN_NPHY_CRSHIGHLOWPOWTHRESHOLD BWN_PHY_N(0x273) +#define BWN_NPHY_CRSHIGHPOWTHRESHOLD1L BWN_PHY_N(0x274) +#define BWN_NPHY_CRSHIGHPOWTHRESHOLD2L BWN_PHY_N(0x275) +#define BWN_NPHY_CRSHIGHLOWPOWTHRESHOLDL BWN_PHY_N(0x276) +#define BWN_NPHY_CRSHIGHPOWTHRESHOLD1U BWN_PHY_N(0x277) +#define BWN_NPHY_CRSHIGHPOWTHRESHOLD2U BWN_PHY_N(0x278) +#define BWN_NPHY_CRSHIGHLOWPOWTHRESHOLDU BWN_PHY_N(0x279) +#define BWN_NPHY_CRSACIDETECTTHRESH BWN_PHY_N(0x27A) +#define BWN_NPHY_CRSACIDETECTTHRESHL BWN_PHY_N(0x27B) +#define BWN_NPHY_CRSACIDETECTTHRESHU BWN_PHY_N(0x27C) +#define BWN_NPHY_CRSMINPOWER0 BWN_PHY_N(0x27D) +#define BWN_NPHY_CRSMINPOWER1 BWN_PHY_N(0x27E) +#define BWN_NPHY_CRSMINPOWER2 BWN_PHY_N(0x27F) +#define BWN_NPHY_CRSMINPOWERL0 BWN_PHY_N(0x280) +#define BWN_NPHY_CRSMINPOWERL1 BWN_PHY_N(0x281) +#define BWN_NPHY_CRSMINPOWERL2 BWN_PHY_N(0x282) +#define BWN_NPHY_CRSMINPOWERU0 BWN_PHY_N(0x283) +#define BWN_NPHY_CRSMINPOWERU1 BWN_PHY_N(0x284) +#define BWN_NPHY_CRSMINPOWERU2 BWN_PHY_N(0x285) +#define BWN_NPHY_STRPARAM BWN_PHY_N(0x286) +#define BWN_NPHY_STRPARAML BWN_PHY_N(0x287) +#define BWN_NPHY_STRPARAMU BWN_PHY_N(0x288) +#define BWN_NPHY_BPHYCRSMINPOWER0 BWN_PHY_N(0x289) +#define BWN_NPHY_BPHYCRSMINPOWER1 BWN_PHY_N(0x28A) +#define BWN_NPHY_BPHYCRSMINPOWER2 BWN_PHY_N(0x28B) +#define BWN_NPHY_BPHYFILTDEN0COEF BWN_PHY_N(0x28C) +#define BWN_NPHY_BPHYFILTDEN1COEF BWN_PHY_N(0x28D) +#define BWN_NPHY_BPHYFILTDEN2COEF BWN_PHY_N(0x28E) +#define BWN_NPHY_BPHYFILTNUM0COEF BWN_PHY_N(0x28F) +#define BWN_NPHY_BPHYFILTNUM1COEF BWN_PHY_N(0x290) +#define BWN_NPHY_BPHYFILTNUM2COEF BWN_PHY_N(0x291) +#define BWN_NPHY_BPHYFILTNUM01COEF2 BWN_PHY_N(0x292) +#define BWN_NPHY_BPHYFILTBYPASS BWN_PHY_N(0x293) +#define BWN_NPHY_SGILTRNOFFSET BWN_PHY_N(0x294) +#define BWN_NPHY_RADAR_T2_MIN BWN_PHY_N(0x295) +#define BWN_NPHY_TXPWRCTRLDAMPING BWN_PHY_N(0x296) +#define BWN_NPHY_PAPD_EN0 BWN_PHY_N(0x297) /* PAPD Enable0 TBD */ +#define BWN_NPHY_EPS_TABLE_ADJ0 BWN_PHY_N(0x298) /* EPS Table Adj0 TBD */ +#define BWN_NPHY_EPS_OVERRIDEI_0 BWN_PHY_N(0x299) +#define BWN_NPHY_EPS_OVERRIDEQ_0 BWN_PHY_N(0x29A) +#define BWN_NPHY_PAPD_EN1 BWN_PHY_N(0x29B) /* PAPD Enable1 TBD */ +#define BWN_NPHY_EPS_TABLE_ADJ1 BWN_PHY_N(0x29C) /* EPS Table Adj1 TBD */ +#define BWN_NPHY_EPS_OVERRIDEI_1 BWN_PHY_N(0x29D) +#define BWN_NPHY_EPS_OVERRIDEQ_1 BWN_PHY_N(0x29E) +#define BWN_NPHY_PAPD_CAL_ADDRESS BWN_PHY_N(0x29F) +#define BWN_NPHY_PAPD_CAL_YREFEPSILON BWN_PHY_N(0x2A0) +#define BWN_NPHY_PAPD_CAL_SETTLE BWN_PHY_N(0x2A1) +#define BWN_NPHY_PAPD_CAL_CORRELATE BWN_PHY_N(0x2A2) +#define BWN_NPHY_PAPD_CAL_SHIFTS0 BWN_PHY_N(0x2A3) +#define BWN_NPHY_PAPD_CAL_SHIFTS1 BWN_PHY_N(0x2A4) +#define BWN_NPHY_SAMPLE_START_ADDR BWN_PHY_N(0x2A5) +#define BWN_NPHY_RADAR_ADC_TO_DBM BWN_PHY_N(0x2A6) +#define BWN_NPHY_REV3_C2_INITGAIN_A BWN_PHY_N(0x2A7) +#define BWN_NPHY_REV3_C2_INITGAIN_B BWN_PHY_N(0x2A8) +#define BWN_NPHY_REV3_C2_CLIP_HIGAIN_A BWN_PHY_N(0x2A9) +#define BWN_NPHY_REV3_C2_CLIP_HIGAIN_B BWN_PHY_N(0x2AA) +#define BWN_NPHY_REV3_C2_CLIP_MEDGAIN_A BWN_PHY_N(0x2AB) +#define BWN_NPHY_REV3_C2_CLIP_MEDGAIN_B BWN_PHY_N(0x2AC) +#define BWN_NPHY_REV3_C2_CLIP_LOGAIN_A BWN_PHY_N(0x2AD) +#define BWN_NPHY_REV3_C2_CLIP_LOGAIN_B BWN_PHY_N(0x2AE) +#define BWN_NPHY_REV3_C2_CLIP2_GAIN_A BWN_PHY_N(0x2AF) +#define BWN_NPHY_REV3_C2_CLIP2_GAIN_B BWN_PHY_N(0x2B0) + +#define BWN_NPHY_REV7_RF_CTL_MISC_REG3 BWN_PHY_N(0x340) +#define BWN_NPHY_REV7_RF_CTL_MISC_REG4 BWN_PHY_N(0x341) +#define BWN_NPHY_REV7_RF_CTL_OVER3 BWN_PHY_N(0x342) +#define BWN_NPHY_REV7_RF_CTL_OVER4 BWN_PHY_N(0x343) +#define BWN_NPHY_REV7_RF_CTL_MISC_REG5 BWN_PHY_N(0x344) +#define BWN_NPHY_REV7_RF_CTL_MISC_REG6 BWN_PHY_N(0x345) +#define BWN_NPHY_REV7_RF_CTL_OVER5 BWN_PHY_N(0x346) +#define BWN_NPHY_REV7_RF_CTL_OVER6 BWN_PHY_N(0x347) + +#define BWN_PHY_B_BBCFG BWN_PHY_N_BMODE(0x001) /* BB config */ +#define BWN_PHY_B_BBCFG_RSTCCA 0x4000 /* Reset CCA */ +#define BWN_PHY_B_BBCFG_RSTRX 0x8000 /* Reset RX */ +#define BWN_PHY_B_TEST BWN_PHY_N_BMODE(0x00A) + +#endif /* __IF_BWN_PHY_N_REGS_H__ */ diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c new file mode 100644 index 0000000..883989b --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c @@ -0,0 +1,3965 @@ +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * The Broadcom Wireless LAN controller driver. + */ + +#include "opt_wlan.h" +#include "opt_bwn.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/endian.h> +#include <sys/errno.h> +#include <sys/firmware.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/socket.h> +#include <sys/sockio.h> + +#include <net/ethernet.h> +#include <net/if.h> +#include <net/if_var.h> +#include <net/if_arp.h> +#include <net/if_dl.h> +#include <net/if_llc.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <dev/pci/pcivar.h> +#include <dev/pci/pcireg.h> +#include <dev/siba/siba_ids.h> +#include <dev/siba/sibareg.h> +#include <dev/siba/sibavar.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> +#include <net80211/ieee80211_regdomain.h> +#include <net80211/ieee80211_phy.h> +#include <net80211/ieee80211_ratectl.h> + +#include <dev/bwn/if_bwnreg.h> +#include <dev/bwn/if_bwnvar.h> +#include <dev/bwn/if_bwn_debug.h> + +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h> + +static const uint8_t bwn_ntab_adjustpower0[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const uint8_t bwn_ntab_adjustpower1[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const uint16_t bwn_ntab_bdi[] = { + 0x0070, 0x0126, 0x012C, 0x0246, 0x048D, 0x04D2, +}; + +static const uint32_t bwn_ntab_channelest[] = { + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, +}; + +static const uint8_t bwn_ntab_estimatepowerlt0[] = { + 0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49, + 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, + 0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, + 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, + 0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, + 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, + 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, + 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, +}; + +static const uint8_t bwn_ntab_estimatepowerlt1[] = { + 0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49, + 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, + 0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, + 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, + 0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, + 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, + 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, + 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, +}; + +static const uint8_t bwn_ntab_framelookup[] = { + 0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16, + 0x0A, 0x0C, 0x1C, 0x1C, 0x0B, 0x0D, 0x1E, 0x1E, + 0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1A, 0x1A, + 0x0E, 0x10, 0x20, 0x28, 0x0F, 0x11, 0x22, 0x2A, +}; + +static const uint32_t bwn_ntab_framestruct[] = { + 0x08004A04, 0x00100000, 0x01000A05, 0x00100020, + 0x09804506, 0x00100030, 0x09804507, 0x00100030, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08004A0C, 0x00100004, 0x01000A0D, 0x00100024, + 0x0980450E, 0x00100034, 0x0980450F, 0x00100034, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000A04, 0x00100000, 0x11008A05, 0x00100020, + 0x1980C506, 0x00100030, 0x21810506, 0x00100030, + 0x21810506, 0x00100030, 0x01800504, 0x00100030, + 0x11808505, 0x00100030, 0x29814507, 0x01100030, + 0x00000A04, 0x00100000, 0x11008A05, 0x00100020, + 0x21810506, 0x00100030, 0x21810506, 0x00100030, + 0x29814507, 0x01100030, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028, + 0x1980C50E, 0x00100038, 0x2181050E, 0x00100038, + 0x2181050E, 0x00100038, 0x0180050C, 0x00100038, + 0x1180850D, 0x00100038, 0x2981450F, 0x01100038, + 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028, + 0x2181050E, 0x00100038, 0x2181050E, 0x00100038, + 0x2981450F, 0x01100038, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08004A04, 0x00100000, 0x01000A05, 0x00100020, + 0x1980C506, 0x00100030, 0x1980C506, 0x00100030, + 0x11808504, 0x00100030, 0x3981CA05, 0x00100030, + 0x29814507, 0x01100030, 0x00000000, 0x00000000, + 0x10008A04, 0x00100000, 0x3981CA05, 0x00100030, + 0x1980C506, 0x00100030, 0x29814507, 0x01100030, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08004A0C, 0x00100008, 0x01000A0D, 0x00100028, + 0x1980C50E, 0x00100038, 0x1980C50E, 0x00100038, + 0x1180850C, 0x00100038, 0x3981CA0D, 0x00100038, + 0x2981450F, 0x01100038, 0x00000000, 0x00000000, + 0x10008A0C, 0x00100008, 0x3981CA0D, 0x00100038, + 0x1980C50E, 0x00100038, 0x2981450F, 0x01100038, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x40021404, 0x00100000, 0x02001405, 0x00100040, + 0x0B004A06, 0x01900060, 0x13008A06, 0x01900060, + 0x13008A06, 0x01900060, 0x43020A04, 0x00100060, + 0x1B00CA05, 0x00100060, 0x23010A07, 0x01500060, + 0x40021404, 0x00100000, 0x1A00D405, 0x00100040, + 0x13008A06, 0x01900060, 0x13008A06, 0x01900060, + 0x23010A07, 0x01500060, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140C, 0x00100010, 0x0200140D, 0x00100050, + 0x0B004A0E, 0x01900070, 0x13008A0E, 0x01900070, + 0x13008A0E, 0x01900070, 0x43020A0C, 0x00100070, + 0x1B00CA0D, 0x00100070, 0x23010A0F, 0x01500070, + 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, + 0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070, + 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x50029404, 0x00100000, 0x32019405, 0x00100040, + 0x0B004A06, 0x01900060, 0x0B004A06, 0x01900060, + 0x5B02CA04, 0x00100060, 0x3B01D405, 0x00100060, + 0x23010A07, 0x01500060, 0x00000000, 0x00000000, + 0x5802D404, 0x00100000, 0x3B01D405, 0x00100060, + 0x0B004A06, 0x01900060, 0x23010A07, 0x01500060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x5002940C, 0x00100010, 0x3201940D, 0x00100050, + 0x0B004A0E, 0x01900070, 0x0B004A0E, 0x01900070, + 0x5B02CA0C, 0x00100070, 0x3B01D40D, 0x00100070, + 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, + 0x5802D40C, 0x00100010, 0x3B01D40D, 0x00100070, + 0x0B004A0E, 0x01900070, 0x23010A0F, 0x01500070, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x40021404, 0x000F4800, 0x62031405, 0x00100040, + 0x53028A06, 0x01900060, 0x53028A07, 0x01900060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140C, 0x000F4808, 0x6203140D, 0x00100048, + 0x53028A0E, 0x01900068, 0x53028A0F, 0x01900068, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000A0C, 0x00100004, 0x11008A0D, 0x00100024, + 0x1980C50E, 0x00100034, 0x2181050E, 0x00100034, + 0x2181050E, 0x00100034, 0x0180050C, 0x00100038, + 0x1180850D, 0x00100038, 0x1181850D, 0x00100038, + 0x2981450F, 0x01100038, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028, + 0x2181050E, 0x00100038, 0x2181050E, 0x00100038, + 0x1181850D, 0x00100038, 0x2981450F, 0x01100038, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08004A04, 0x00100000, 0x01000A05, 0x00100020, + 0x0180C506, 0x00100030, 0x0180C506, 0x00100030, + 0x2180C50C, 0x00100030, 0x49820A0D, 0x0016A130, + 0x41824A0D, 0x0016A130, 0x2981450F, 0x01100030, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x2000CA0C, 0x00100000, 0x49820A0D, 0x0016A130, + 0x1980C50E, 0x00100030, 0x41824A0D, 0x0016A130, + 0x2981450F, 0x01100030, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140C, 0x00100008, 0x0200140D, 0x00100048, + 0x0B004A0E, 0x01900068, 0x13008A0E, 0x01900068, + 0x13008A0E, 0x01900068, 0x43020A0C, 0x00100070, + 0x1B00CA0D, 0x00100070, 0x1B014A0D, 0x00100070, + 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, + 0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070, + 0x1B014A0D, 0x00100070, 0x23010A0F, 0x01500070, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x50029404, 0x00100000, 0x32019405, 0x00100040, + 0x03004A06, 0x01900060, 0x03004A06, 0x01900060, + 0x6B030A0C, 0x00100060, 0x4B02140D, 0x0016A160, + 0x4302540D, 0x0016A160, 0x23010A0F, 0x01500060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x6B03140C, 0x00100060, 0x4B02140D, 0x0016A160, + 0x0B004A0E, 0x01900060, 0x4302540D, 0x0016A160, + 0x23010A0F, 0x01500060, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x40021404, 0x00100000, 0x1A00D405, 0x00100040, + 0x53028A06, 0x01900060, 0x5B02CA06, 0x01900060, + 0x5B02CA06, 0x01900060, 0x43020A04, 0x00100060, + 0x1B00CA05, 0x00100060, 0x53028A07, 0x0190C060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, + 0x53028A0E, 0x01900070, 0x5B02CA0E, 0x01900070, + 0x5B02CA0E, 0x01900070, 0x43020A0C, 0x00100070, + 0x1B00CA0D, 0x00100070, 0x53028A0F, 0x0190C070, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x40021404, 0x00100000, 0x1A00D405, 0x00100040, + 0x5B02CA06, 0x01900060, 0x5B02CA06, 0x01900060, + 0x53028A07, 0x0190C060, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, + 0x5B02CA0E, 0x01900070, 0x5B02CA0E, 0x01900070, + 0x53028A0F, 0x0190C070, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_gainctl0[] = { + 0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E, + 0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42, + 0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B, + 0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34, + 0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E, + 0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38, + 0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32, + 0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44, + 0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D, + 0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36, + 0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40, + 0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39, + 0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33, + 0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D, + 0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E, + 0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38, + 0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42, + 0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B, + 0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34, + 0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44, + 0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D, + 0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36, + 0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30, + 0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B, + 0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26, + 0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22, + 0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E, + 0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B, + 0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18, + 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, + 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, + 0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00, +}; + +static const uint32_t bwn_ntab_gainctl1[] = { + 0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E, + 0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42, + 0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B, + 0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34, + 0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E, + 0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38, + 0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32, + 0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44, + 0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D, + 0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36, + 0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40, + 0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39, + 0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33, + 0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D, + 0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E, + 0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38, + 0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42, + 0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B, + 0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34, + 0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44, + 0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D, + 0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36, + 0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30, + 0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B, + 0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26, + 0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22, + 0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E, + 0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B, + 0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18, + 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, + 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, + 0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00, +}; + +static const uint32_t bwn_ntab_intlevel[] = { + 0x00802070, 0x0671188D, 0x0A60192C, 0x0A300E46, + 0x00C1188D, 0x080024D2, 0x00000070, +}; + +static const uint32_t bwn_ntab_iqlt0[] = { + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, +}; + +static const uint32_t bwn_ntab_iqlt1[] = { + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, + 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, +}; + +static const uint16_t bwn_ntab_loftlt0[] = { + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, +}; + +static const uint16_t bwn_ntab_loftlt1[] = { + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, + 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, + 0x0002, 0x0103, +}; + +static const uint8_t bwn_ntab_mcs[] = { + 0x00, 0x08, 0x0A, 0x10, 0x12, 0x19, 0x1A, 0x1C, + 0x40, 0x48, 0x4A, 0x50, 0x52, 0x59, 0x5A, 0x5C, + 0x80, 0x88, 0x8A, 0x90, 0x92, 0x99, 0x9A, 0x9C, + 0xC0, 0xC8, 0xCA, 0xD0, 0xD2, 0xD9, 0xDA, 0xDC, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x02, 0x04, 0x08, 0x09, 0x0A, 0x0C, + 0x10, 0x11, 0x12, 0x14, 0x18, 0x19, 0x1A, 0x1C, + 0x20, 0x21, 0x22, 0x24, 0x40, 0x41, 0x42, 0x44, + 0x48, 0x49, 0x4A, 0x4C, 0x50, 0x51, 0x52, 0x54, + 0x58, 0x59, 0x5A, 0x5C, 0x60, 0x61, 0x62, 0x64, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const uint32_t bwn_ntab_noisevar10[] = { + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, +}; + +static const uint32_t bwn_ntab_noisevar11[] = { + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, + 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, +}; + +static const uint16_t bwn_ntab_pilot[] = { + 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, + 0xFF08, 0xFF08, 0x80D5, 0x80D5, 0x80D5, 0x80D5, + 0x80D5, 0x80D5, 0x80D5, 0x80D5, 0xFF0A, 0xFF82, + 0xFFA0, 0xFF28, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFF82, 0xFFA0, 0xFF28, 0xFF0A, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xF83F, 0xFA1F, 0xFA97, 0xFAB5, + 0xF2BD, 0xF0BF, 0xFFFF, 0xFFFF, 0xF017, 0xF815, + 0xF215, 0xF095, 0xF035, 0xF01D, 0xFFFF, 0xFFFF, + 0xFF08, 0xFF02, 0xFF80, 0xFF20, 0xFF08, 0xFF02, + 0xFF80, 0xFF20, 0xF01F, 0xF817, 0xFA15, 0xF295, + 0xF0B5, 0xF03D, 0xFFFF, 0xFFFF, 0xF82A, 0xFA0A, + 0xFA82, 0xFAA0, 0xF2A8, 0xF0AA, 0xFFFF, 0xFFFF, + 0xF002, 0xF800, 0xF200, 0xF080, 0xF020, 0xF008, + 0xFFFF, 0xFFFF, 0xF00A, 0xF802, 0xFA00, 0xF280, + 0xF0A0, 0xF028, 0xFFFF, 0xFFFF, +}; + +static const uint32_t bwn_ntab_pilotlt[] = { + 0x76540123, 0x62407351, 0x76543201, 0x76540213, + 0x76540123, 0x76430521, +}; + +static const uint32_t bwn_ntab_tdi20a0[] = { + 0x00091226, 0x000A1429, 0x000B56AD, 0x000C58B0, + 0x000D5AB3, 0x000E9CB6, 0x000F9EBA, 0x0000C13D, + 0x00020301, 0x00030504, 0x00040708, 0x0005090B, + 0x00064B8E, 0x00095291, 0x000A5494, 0x000B9718, + 0x000C9927, 0x000D9B2A, 0x000EDD2E, 0x000FDF31, + 0x000101B4, 0x000243B7, 0x000345BB, 0x000447BE, + 0x00058982, 0x00068C05, 0x00099309, 0x000A950C, + 0x000BD78F, 0x000CD992, 0x000DDB96, 0x000F1D99, + 0x00005FA8, 0x0001422C, 0x0002842F, 0x00038632, + 0x00048835, 0x0005CA38, 0x0006CCBC, 0x0009D3BF, + 0x000B1603, 0x000C1806, 0x000D1A0A, 0x000E1C0D, + 0x000F5E10, 0x00008093, 0x00018297, 0x0002C49A, + 0x0003C680, 0x0004C880, 0x00060B00, 0x00070D00, + 0x00000000, 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_tdi20a1[] = { + 0x00014B26, 0x00028D29, 0x000393AD, 0x00049630, + 0x0005D833, 0x0006DA36, 0x00099C3A, 0x000A9E3D, + 0x000BC081, 0x000CC284, 0x000DC488, 0x000F068B, + 0x0000488E, 0x00018B91, 0x0002D214, 0x0003D418, + 0x0004D6A7, 0x000618AA, 0x00071AAE, 0x0009DCB1, + 0x000B1EB4, 0x000C0137, 0x000D033B, 0x000E053E, + 0x000F4702, 0x00008905, 0x00020C09, 0x0003128C, + 0x0004148F, 0x00051712, 0x00065916, 0x00091B19, + 0x000A1D28, 0x000B5F2C, 0x000C41AF, 0x000D43B2, + 0x000E85B5, 0x000F87B8, 0x0000C9BC, 0x00024CBF, + 0x00035303, 0x00045506, 0x0005978A, 0x0006998D, + 0x00095B90, 0x000A5D93, 0x000B9F97, 0x000C821A, + 0x000D8400, 0x000EC600, 0x000FC800, 0x00010A00, + 0x00000000, 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_tdi40a0[] = { + 0x0011A346, 0x00136CCF, 0x0014F5D9, 0x001641E2, + 0x0017CB6B, 0x00195475, 0x001B2383, 0x001CAD0C, + 0x001E7616, 0x0000821F, 0x00020BA8, 0x0003D4B2, + 0x00056447, 0x00072DD0, 0x0008B6DA, 0x000A02E3, + 0x000B8C6C, 0x000D15F6, 0x0011E484, 0x0013AE0D, + 0x00153717, 0x00168320, 0x00180CA9, 0x00199633, + 0x001B6548, 0x001CEED1, 0x001EB7DB, 0x0000C3E4, + 0x00024D6D, 0x000416F7, 0x0005A585, 0x00076F0F, + 0x0008F818, 0x000A4421, 0x000BCDAB, 0x000D9734, + 0x00122649, 0x0013EFD2, 0x001578DC, 0x0016C4E5, + 0x00184E6E, 0x001A17F8, 0x001BA686, 0x001D3010, + 0x001EF999, 0x00010522, 0x00028EAC, 0x00045835, + 0x0005E74A, 0x0007B0D3, 0x00093A5D, 0x000A85E6, + 0x000C0F6F, 0x000DD8F9, 0x00126787, 0x00143111, + 0x0015BA9A, 0x00170623, 0x00188FAD, 0x001A5936, + 0x001BE84B, 0x001DB1D4, 0x001F3B5E, 0x000146E7, + 0x00031070, 0x000499FA, 0x00062888, 0x0007F212, + 0x00097B9B, 0x000AC7A4, 0x000C50AE, 0x000E1A37, + 0x0012A94C, 0x001472D5, 0x0015FC5F, 0x00174868, + 0x0018D171, 0x001A9AFB, 0x001C2989, 0x001DF313, + 0x001F7C9C, 0x000188A5, 0x000351AF, 0x0004DB38, + 0x0006AA4D, 0x000833D7, 0x0009BD60, 0x000B0969, + 0x000C9273, 0x000E5BFC, 0x00132A8A, 0x0014B414, + 0x00163D9D, 0x001789A6, 0x001912B0, 0x001ADC39, + 0x001C6BCE, 0x001E34D8, 0x001FBE61, 0x0001CA6A, + 0x00039374, 0x00051CFD, 0x0006EC0B, 0x00087515, + 0x0009FE9E, 0x000B4AA7, 0x000CD3B1, 0x000E9D3A, + 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_tdi40a1[] = { + 0x001EDB36, 0x000129CA, 0x0002B353, 0x00047CDD, + 0x0005C8E6, 0x000791EF, 0x00091BF9, 0x000AAA07, + 0x000C3391, 0x000DFD1A, 0x00120923, 0x0013D22D, + 0x00155C37, 0x0016EACB, 0x00187454, 0x001A3DDE, + 0x001B89E7, 0x001D12F0, 0x001F1CFA, 0x00016B88, + 0x00033492, 0x0004BE1B, 0x00060A24, 0x0007D32E, + 0x00095D38, 0x000AEC4C, 0x000C7555, 0x000E3EDF, + 0x00124AE8, 0x001413F1, 0x0015A37B, 0x00172C89, + 0x0018B593, 0x001A419C, 0x001BCB25, 0x001D942F, + 0x001F63B9, 0x0001AD4D, 0x00037657, 0x0004C260, + 0x00068BE9, 0x000814F3, 0x0009A47C, 0x000B2D8A, + 0x000CB694, 0x000E429D, 0x00128C26, 0x001455B0, + 0x0015E4BA, 0x00176E4E, 0x0018F758, 0x001A8361, + 0x001C0CEA, 0x001DD674, 0x001FA57D, 0x0001EE8B, + 0x0003B795, 0x0005039E, 0x0006CD27, 0x000856B1, + 0x0009E5C6, 0x000B6F4F, 0x000CF859, 0x000E8462, + 0x00130DEB, 0x00149775, 0x00162603, 0x0017AF8C, + 0x00193896, 0x001AC49F, 0x001C4E28, 0x001E17B2, + 0x0000A6C7, 0x00023050, 0x0003F9DA, 0x00054563, + 0x00070EEC, 0x00089876, 0x000A2704, 0x000BB08D, + 0x000D3A17, 0x001185A0, 0x00134F29, 0x0014D8B3, + 0x001667C8, 0x0017F151, 0x00197ADB, 0x001B0664, + 0x001C8FED, 0x001E5977, 0x0000E805, 0x0002718F, + 0x00043B18, 0x000586A1, 0x0007502B, 0x0008D9B4, + 0x000A68C9, 0x000BF252, 0x000DBBDC, 0x0011C7E5, + 0x001390EE, 0x00151A78, 0x0016A906, 0x00183290, + 0x0019BC19, 0x001B4822, 0x001CD12C, 0x001E9AB5, + 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_tdtrn[] = { + 0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6, + 0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68, + 0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52, + 0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050, + 0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6, + 0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68, + 0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52, + 0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050, + 0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246, + 0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C, + 0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61, + 0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D, + 0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246, + 0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C, + 0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61, + 0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D, + 0xFA58FA58, 0xF895043B, 0xFF4C09C0, 0xFBC6FFA8, + 0xFB84F384, 0x0798F6F9, 0x05760122, 0x058409F6, + 0x0B500000, 0x05B7F542, 0x08860432, 0x06DDFEE7, + 0xFB84F384, 0xF9D90664, 0xF7E8025C, 0x00FFF7BD, + 0x05A805A8, 0xF7BD00FF, 0x025CF7E8, 0x0664F9D9, + 0xF384FB84, 0xFEE706DD, 0x04320886, 0xF54205B7, + 0x00000B50, 0x09F60584, 0x01220576, 0xF6F90798, + 0xF384FB84, 0xFFA8FBC6, 0x09C0FF4C, 0x043BF895, + 0x02D402D4, 0x07DE0270, 0xFC96079C, 0xF90AFE94, + 0xFE00FF2C, 0x02D4065D, 0x092A0096, 0x0014FBB8, + 0xFD2CFD2C, 0x076AFB3C, 0x0096F752, 0xF991FD87, + 0xFB2C0200, 0xFEB8F960, 0x08E0FC96, 0x049802A8, + 0xFD2CFD2C, 0x02A80498, 0xFC9608E0, 0xF960FEB8, + 0x0200FB2C, 0xFD87F991, 0xF7520096, 0xFB3C076A, + 0xFD2CFD2C, 0xFBB80014, 0x0096092A, 0x065D02D4, + 0xFF2CFE00, 0xFE94F90A, 0x079CFC96, 0x027007DE, + 0x02D402D4, 0x027007DE, 0x079CFC96, 0xFE94F90A, + 0xFF2CFE00, 0x065D02D4, 0x0096092A, 0xFBB80014, + 0xFD2CFD2C, 0xFB3C076A, 0xF7520096, 0xFD87F991, + 0x0200FB2C, 0xF960FEB8, 0xFC9608E0, 0x02A80498, + 0xFD2CFD2C, 0x049802A8, 0x08E0FC96, 0xFEB8F960, + 0xFB2C0200, 0xF991FD87, 0x0096F752, 0x076AFB3C, + 0xFD2CFD2C, 0x0014FBB8, 0x092A0096, 0x02D4065D, + 0xFE00FF2C, 0xF90AFE94, 0xFC96079C, 0x07DE0270, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D, + 0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF, + 0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8, + 0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7, + 0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3, + 0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841, + 0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608, + 0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759, + 0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D, + 0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF, + 0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8, + 0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7, + 0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3, + 0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841, + 0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608, + 0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759, + 0x061C061C, 0xFF30009D, 0xFFB21141, 0xFD87FB54, + 0xF65DFE59, 0x02EEF99E, 0x0166F03C, 0xFFF809B6, + 0x000008A4, 0x000AF42B, 0x00EFF577, 0xFA840BF2, + 0xFC02FF51, 0x08260F67, 0xFFF0036F, 0x0842F9C3, + 0x00000000, 0x063DF7BE, 0xFC910010, 0xF099F7DA, + 0x00AF03FE, 0xF40E057C, 0x0A89FF11, 0x0BD5FFF6, + 0xF75C0000, 0xF64A0008, 0x0FC4FE9A, 0x0662FD12, + 0x01A709A3, 0x04AC0279, 0xEEBF004E, 0xFF6300D0, + 0xF9E4F9E4, 0x00D0FF63, 0x004EEEBF, 0x027904AC, + 0x09A301A7, 0xFD120662, 0xFE9A0FC4, 0x0008F64A, + 0x0000F75C, 0xFFF60BD5, 0xFF110A89, 0x057CF40E, + 0x03FE00AF, 0xF7DAF099, 0x0010FC91, 0xF7BE063D, + 0x00000000, 0xF9C30842, 0x036FFFF0, 0x0F670826, + 0xFF51FC02, 0x0BF2FA84, 0xF57700EF, 0xF42B000A, + 0x08A40000, 0x09B6FFF8, 0xF03C0166, 0xF99E02EE, + 0xFE59F65D, 0xFB54FD87, 0x1141FFB2, 0x009DFF30, + 0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59, + 0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766, + 0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986, + 0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB, + 0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7, + 0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A, + 0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A, + 0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705, + 0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59, + 0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766, + 0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986, + 0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB, + 0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7, + 0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A, + 0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A, + 0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705, + 0xFA58FA58, 0xF8F0FE00, 0x0448073D, 0xFDC9FE46, + 0xF9910258, 0x089D0407, 0xFD5CF71A, 0x02AFFDE0, + 0x083E0496, 0xFF5A0740, 0xFF7AFD97, 0x00FE01F1, + 0x0009082E, 0xFA94FF75, 0xFECDF8EA, 0xFFB0F693, + 0xFD2CFA58, 0x0433FF16, 0xFBA405DD, 0xFA610341, + 0x06A606CB, 0x0039FD2D, 0x0677FA97, 0x01FA05E0, + 0xF896003E, 0x075A068B, 0x012CFC3E, 0xFA23F98D, + 0xFC7CFD43, 0xFF90FC0D, 0x01C10982, 0x00C601D6, + 0xFD2CFD2C, 0x01D600C6, 0x098201C1, 0xFC0DFF90, + 0xFD43FC7C, 0xF98DFA23, 0xFC3E012C, 0x068B075A, + 0x003EF896, 0x05E001FA, 0xFA970677, 0xFD2D0039, + 0x06CB06A6, 0x0341FA61, 0x05DDFBA4, 0xFF160433, + 0xFA58FD2C, 0xF693FFB0, 0xF8EAFECD, 0xFF75FA94, + 0x082E0009, 0x01F100FE, 0xFD97FF7A, 0x0740FF5A, + 0x0496083E, 0xFDE002AF, 0xF71AFD5C, 0x0407089D, + 0x0258F991, 0xFE46FDC9, 0x073D0448, 0xFE00F8F0, + 0xFD2CFD2C, 0xFCE00500, 0xFC09FDDC, 0xFE680157, + 0x04C70571, 0xFC3AFF21, 0xFCD70228, 0x056D0277, + 0x0200FE00, 0x0022F927, 0xFE3C032B, 0xFC44FF3C, + 0x03E9FBDB, 0x04570313, 0x04C9FF5C, 0x000D03B8, + 0xFA580000, 0xFBE900D2, 0xF9D0FE0B, 0x0125FDF9, + 0x042501BF, 0x0328FA2B, 0xFFA902F0, 0xFA250157, + 0x0200FE00, 0x03740438, 0xFF0405FD, 0x030CFE52, + 0x0037FB39, 0xFF6904C5, 0x04F8FD23, 0xFD31FC1B, + 0xFD2CFD2C, 0xFC1BFD31, 0xFD2304F8, 0x04C5FF69, + 0xFB390037, 0xFE52030C, 0x05FDFF04, 0x04380374, + 0xFE000200, 0x0157FA25, 0x02F0FFA9, 0xFA2B0328, + 0x01BF0425, 0xFDF90125, 0xFE0BF9D0, 0x00D2FBE9, + 0x0000FA58, 0x03B8000D, 0xFF5C04C9, 0x03130457, + 0xFBDB03E9, 0xFF3CFC44, 0x032BFE3C, 0xF9270022, + 0xFE000200, 0x0277056D, 0x0228FCD7, 0xFF21FC3A, + 0x057104C7, 0x0157FE68, 0xFDDCFC09, 0x0500FCE0, + 0xFD2CFD2C, 0x0500FCE0, 0xFDDCFC09, 0x0157FE68, + 0x057104C7, 0xFF21FC3A, 0x0228FCD7, 0x0277056D, + 0xFE000200, 0xF9270022, 0x032BFE3C, 0xFF3CFC44, + 0xFBDB03E9, 0x03130457, 0xFF5C04C9, 0x03B8000D, + 0x0000FA58, 0x00D2FBE9, 0xFE0BF9D0, 0xFDF90125, + 0x01BF0425, 0xFA2B0328, 0x02F0FFA9, 0x0157FA25, + 0xFE000200, 0x04380374, 0x05FDFF04, 0xFE52030C, + 0xFB390037, 0x04C5FF69, 0xFD2304F8, 0xFC1BFD31, + 0xFD2CFD2C, 0xFD31FC1B, 0x04F8FD23, 0xFF6904C5, + 0x0037FB39, 0x030CFE52, 0xFF0405FD, 0x03740438, + 0x0200FE00, 0xFA250157, 0xFFA902F0, 0x0328FA2B, + 0x042501BF, 0x0125FDF9, 0xF9D0FE0B, 0xFBE900D2, + 0xFA580000, 0x000D03B8, 0x04C9FF5C, 0x04570313, + 0x03E9FBDB, 0xFC44FF3C, 0xFE3C032B, 0x0022F927, + 0x0200FE00, 0x056D0277, 0xFCD70228, 0xFC3AFF21, + 0x04C70571, 0xFE680157, 0xFC09FDDC, 0xFCE00500, + 0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E, + 0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C, + 0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926, + 0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942, + 0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382, + 0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4, + 0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA, + 0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE, + 0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E, + 0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C, + 0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926, + 0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942, + 0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382, + 0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4, + 0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA, + 0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE, +}; + +static const uint32_t bwn_ntab_tmap[] = { + 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, + 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0xF1111110, 0x11111111, 0x11F11111, 0x00000111, + 0x11000000, 0x1111F111, 0x11111111, 0x111111F1, + 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x000AA888, + 0x88880000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, + 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, + 0xA2222220, 0x22222222, 0x22C22222, 0x00000222, + 0x22000000, 0x2222A222, 0x22222222, 0x222222A2, + 0xF1111110, 0x11111111, 0x11F11111, 0x00011111, + 0x11110000, 0x1111F111, 0x11111111, 0x111111F1, + 0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00088AAA, + 0xAAAA0000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A, + 0xAAA8AAA0, 0x8AAA8AAA, 0xAA8A8A8A, 0x000AAA88, + 0x8AAA0000, 0xAAA8A888, 0x8AA88A8A, 0x8A88A888, + 0x08080A00, 0x0A08080A, 0x080A0A08, 0x00080808, + 0x080A0000, 0x080A0808, 0x080A0808, 0x0A0A0A08, + 0xA0A0A0A0, 0x80A0A080, 0x8080A0A0, 0x00008080, + 0x80A00000, 0x80A080A0, 0xA080A0A0, 0x8080A0A0, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x99999000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9, + 0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999, + 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888, + 0x22000000, 0x2222B222, 0x22222222, 0x222222B2, + 0xB2222220, 0x22222222, 0x22D22222, 0x00000222, + 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, + 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, + 0x33000000, 0x3333B333, 0x33333333, 0x333333B3, + 0xB3333330, 0x33333333, 0x33D33333, 0x00000333, + 0x22000000, 0x2222A222, 0x22222222, 0x222222A2, + 0xA2222220, 0x22222222, 0x22C22222, 0x00000222, + 0x99B99B00, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9, + 0x9B99BB99, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999, + 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888, + 0x22222200, 0x2222F222, 0x22222222, 0x222222F2, + 0x22222222, 0x22222222, 0x22F22222, 0x00000222, + 0x11000000, 0x1111F111, 0x11111111, 0x11111111, + 0xF1111111, 0x11111111, 0x11F11111, 0x01111111, + 0xBB9BB900, 0xB9B9BB99, 0xB99BBBBB, 0xBBBB9B9B, + 0xB9BB99BB, 0xB99999B9, 0xB9B9B99B, 0x00000BBB, + 0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A, + 0xA8AA88AA, 0xA88888A8, 0xA8A8A88A, 0x0A888AAA, + 0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A, + 0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00000AAA, + 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, + 0xBBBBBB00, 0x999BBBBB, 0x9BB99B9B, 0xB9B9B9BB, + 0xB9B99BBB, 0xB9B9B9BB, 0xB9BB9B99, 0x00000999, + 0x8A000000, 0xAA88A888, 0xA88888AA, 0xA88A8A88, + 0xA88AA88A, 0x88A8AAAA, 0xA8AA8AAA, 0x0888A88A, + 0x0B0B0B00, 0x090B0B0B, 0x0B090B0B, 0x0909090B, + 0x09090B0B, 0x09090B0B, 0x09090B09, 0x00000909, + 0x0A000000, 0x0A080808, 0x080A080A, 0x080A0A08, + 0x080A080A, 0x0808080A, 0x0A0A0A08, 0x0808080A, + 0xB0B0B000, 0x9090B0B0, 0x90B09090, 0xB0B0B090, + 0xB0B090B0, 0x90B0B0B0, 0xB0B09090, 0x00000090, + 0x80000000, 0xA080A080, 0xA08080A0, 0xA0808080, + 0xA080A080, 0x80A0A0A0, 0xA0A080A0, 0x00A0A0A0, + 0x22000000, 0x2222F222, 0x22222222, 0x222222F2, + 0xF2222220, 0x22222222, 0x22F22222, 0x00000222, + 0x11000000, 0x1111F111, 0x11111111, 0x111111F1, + 0xF1111110, 0x11111111, 0x11F11111, 0x00000111, + 0x33000000, 0x3333F333, 0x33333333, 0x333333F3, + 0xF3333330, 0x33333333, 0x33F33333, 0x00000333, + 0x22000000, 0x2222F222, 0x22222222, 0x222222F2, + 0xF2222220, 0x22222222, 0x22F22222, 0x00000222, + 0x99000000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9, + 0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999, + 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, + 0x88888000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, + 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888, + 0x88A88A00, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, + 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888, + 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, + 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, + 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, + 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, + 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, + 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, + 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +/* static tables, PHY revision >= 3 */ +static const uint32_t bwn_ntab_framestruct_r3[] = { + 0x08004a04, 0x00100000, 0x01000a05, 0x00100020, + 0x09804506, 0x00100030, 0x09804507, 0x00100030, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08004a0c, 0x00100004, 0x01000a0d, 0x00100024, + 0x0980450e, 0x00100034, 0x0980450f, 0x00100034, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000a04, 0x00100000, 0x11008a05, 0x00100020, + 0x1980c506, 0x00100030, 0x21810506, 0x00100030, + 0x21810506, 0x00100030, 0x01800504, 0x00100030, + 0x11808505, 0x00100030, 0x29814507, 0x01100030, + 0x00000a04, 0x00100000, 0x11008a05, 0x00100020, + 0x21810506, 0x00100030, 0x21810506, 0x00100030, + 0x29814507, 0x01100030, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028, + 0x1980c50e, 0x00100038, 0x2181050e, 0x00100038, + 0x2181050e, 0x00100038, 0x0180050c, 0x00100038, + 0x1180850d, 0x00100038, 0x2981450f, 0x01100038, + 0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028, + 0x2181050e, 0x00100038, 0x2181050e, 0x00100038, + 0x2981450f, 0x01100038, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08004a04, 0x00100000, 0x01000a05, 0x00100020, + 0x1980c506, 0x00100030, 0x1980c506, 0x00100030, + 0x11808504, 0x00100030, 0x3981ca05, 0x00100030, + 0x29814507, 0x01100030, 0x00000000, 0x00000000, + 0x10008a04, 0x00100000, 0x3981ca05, 0x00100030, + 0x1980c506, 0x00100030, 0x29814507, 0x01100030, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08004a0c, 0x00100008, 0x01000a0d, 0x00100028, + 0x1980c50e, 0x00100038, 0x1980c50e, 0x00100038, + 0x1180850c, 0x00100038, 0x3981ca0d, 0x00100038, + 0x2981450f, 0x01100038, 0x00000000, 0x00000000, + 0x10008a0c, 0x00100008, 0x3981ca0d, 0x00100038, + 0x1980c50e, 0x00100038, 0x2981450f, 0x01100038, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x40021404, 0x00100000, 0x02001405, 0x00100040, + 0x0b004a06, 0x01900060, 0x13008a06, 0x01900060, + 0x13008a06, 0x01900060, 0x43020a04, 0x00100060, + 0x1b00ca05, 0x00100060, 0x23010a07, 0x01500060, + 0x40021404, 0x00100000, 0x1a00d405, 0x00100040, + 0x13008a06, 0x01900060, 0x13008a06, 0x01900060, + 0x23010a07, 0x01500060, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140c, 0x00100010, 0x0200140d, 0x00100050, + 0x0b004a0e, 0x01900070, 0x13008a0e, 0x01900070, + 0x13008a0e, 0x01900070, 0x43020a0c, 0x00100070, + 0x1b00ca0d, 0x00100070, 0x23010a0f, 0x01500070, + 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, + 0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070, + 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x50029404, 0x00100000, 0x32019405, 0x00100040, + 0x0b004a06, 0x01900060, 0x0b004a06, 0x01900060, + 0x5b02ca04, 0x00100060, 0x3b01d405, 0x00100060, + 0x23010a07, 0x01500060, 0x00000000, 0x00000000, + 0x5802d404, 0x00100000, 0x3b01d405, 0x00100060, + 0x0b004a06, 0x01900060, 0x23010a07, 0x01500060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x5002940c, 0x00100010, 0x3201940d, 0x00100050, + 0x0b004a0e, 0x01900070, 0x0b004a0e, 0x01900070, + 0x5b02ca0c, 0x00100070, 0x3b01d40d, 0x00100070, + 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, + 0x5802d40c, 0x00100010, 0x3b01d40d, 0x00100070, + 0x0b004a0e, 0x01900070, 0x23010a0f, 0x01500070, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x40021404, 0x000f4800, 0x62031405, 0x00100040, + 0x53028a06, 0x01900060, 0x53028a07, 0x01900060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140c, 0x000f4808, 0x6203140d, 0x00100048, + 0x53028a0e, 0x01900068, 0x53028a0f, 0x01900068, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000a0c, 0x00100004, 0x11008a0d, 0x00100024, + 0x1980c50e, 0x00100034, 0x2181050e, 0x00100034, + 0x2181050e, 0x00100034, 0x0180050c, 0x00100038, + 0x1180850d, 0x00100038, 0x1181850d, 0x00100038, + 0x2981450f, 0x01100038, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028, + 0x2181050e, 0x00100038, 0x2181050e, 0x00100038, + 0x1181850d, 0x00100038, 0x2981450f, 0x01100038, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08004a04, 0x00100000, 0x01000a05, 0x00100020, + 0x0180c506, 0x00100030, 0x0180c506, 0x00100030, + 0x2180c50c, 0x00100030, 0x49820a0d, 0x0016a130, + 0x41824a0d, 0x0016a130, 0x2981450f, 0x01100030, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x2000ca0c, 0x00100000, 0x49820a0d, 0x0016a130, + 0x1980c50e, 0x00100030, 0x41824a0d, 0x0016a130, + 0x2981450f, 0x01100030, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140c, 0x00100008, 0x0200140d, 0x00100048, + 0x0b004a0e, 0x01900068, 0x13008a0e, 0x01900068, + 0x13008a0e, 0x01900068, 0x43020a0c, 0x00100070, + 0x1b00ca0d, 0x00100070, 0x1b014a0d, 0x00100070, + 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, + 0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070, + 0x1b014a0d, 0x00100070, 0x23010a0f, 0x01500070, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x50029404, 0x00100000, 0x32019405, 0x00100040, + 0x03004a06, 0x01900060, 0x03004a06, 0x01900060, + 0x6b030a0c, 0x00100060, 0x4b02140d, 0x0016a160, + 0x4302540d, 0x0016a160, 0x23010a0f, 0x01500060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x6b03140c, 0x00100060, 0x4b02140d, 0x0016a160, + 0x0b004a0e, 0x01900060, 0x4302540d, 0x0016a160, + 0x23010a0f, 0x01500060, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x40021404, 0x00100000, 0x1a00d405, 0x00100040, + 0x53028a06, 0x01900060, 0x5b02ca06, 0x01900060, + 0x5b02ca06, 0x01900060, 0x43020a04, 0x00100060, + 0x1b00ca05, 0x00100060, 0x53028a07, 0x0190c060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, + 0x53028a0e, 0x01900070, 0x5b02ca0e, 0x01900070, + 0x5b02ca0e, 0x01900070, 0x43020a0c, 0x00100070, + 0x1b00ca0d, 0x00100070, 0x53028a0f, 0x0190c070, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x40021404, 0x00100000, 0x1a00d405, 0x00100040, + 0x5b02ca06, 0x01900060, 0x5b02ca06, 0x01900060, + 0x53028a07, 0x0190c060, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, + 0x5b02ca0e, 0x01900070, 0x5b02ca0e, 0x01900070, + 0x53028a0f, 0x0190c070, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const uint16_t bwn_ntab_pilot_r3[] = { + 0xff08, 0xff08, 0xff08, 0xff08, 0xff08, 0xff08, + 0xff08, 0xff08, 0x80d5, 0x80d5, 0x80d5, 0x80d5, + 0x80d5, 0x80d5, 0x80d5, 0x80d5, 0xff0a, 0xff82, + 0xffa0, 0xff28, 0xffff, 0xffff, 0xffff, 0xffff, + 0xff82, 0xffa0, 0xff28, 0xff0a, 0xffff, 0xffff, + 0xffff, 0xffff, 0xf83f, 0xfa1f, 0xfa97, 0xfab5, + 0xf2bd, 0xf0bf, 0xffff, 0xffff, 0xf017, 0xf815, + 0xf215, 0xf095, 0xf035, 0xf01d, 0xffff, 0xffff, + 0xff08, 0xff02, 0xff80, 0xff20, 0xff08, 0xff02, + 0xff80, 0xff20, 0xf01f, 0xf817, 0xfa15, 0xf295, + 0xf0b5, 0xf03d, 0xffff, 0xffff, 0xf82a, 0xfa0a, + 0xfa82, 0xfaa0, 0xf2a8, 0xf0aa, 0xffff, 0xffff, + 0xf002, 0xf800, 0xf200, 0xf080, 0xf020, 0xf008, + 0xffff, 0xffff, 0xf00a, 0xf802, 0xfa00, 0xf280, + 0xf0a0, 0xf028, 0xffff, 0xffff, +}; + +static const uint32_t bwn_ntab_tmap_r3[] = { + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, + 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888, + 0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, + 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, + 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, + 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, + 0xf1111110, 0x11111111, 0x11f11111, 0x00011111, + 0x11110000, 0x1111f111, 0x11111111, 0x111111f1, + 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00088aaa, + 0xaaaa0000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, + 0xaaa8aaa0, 0x8aaa8aaa, 0xaa8a8a8a, 0x000aaa88, + 0x8aaa0000, 0xaaa8a888, 0x8aa88a8a, 0x8a88a888, + 0x08080a00, 0x0a08080a, 0x080a0a08, 0x00080808, + 0x080a0000, 0x080a0808, 0x080a0808, 0x0a0a0a08, + 0xa0a0a0a0, 0x80a0a080, 0x8080a0a0, 0x00008080, + 0x80a00000, 0x80a080a0, 0xa080a0a0, 0x8080a0a0, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x99999000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, + 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, + 0x22000000, 0x2222b222, 0x22222222, 0x222222b2, + 0xb2222220, 0x22222222, 0x22d22222, 0x00000222, + 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, + 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, + 0x33000000, 0x3333b333, 0x33333333, 0x333333b3, + 0xb3333330, 0x33333333, 0x33d33333, 0x00000333, + 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, + 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, + 0x99b99b00, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, + 0x9b99bb99, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, + 0x22222200, 0x2222f222, 0x22222222, 0x222222f2, + 0x22222222, 0x22222222, 0x22f22222, 0x00000222, + 0x11000000, 0x1111f111, 0x11111111, 0x11111111, + 0xf1111111, 0x11111111, 0x11f11111, 0x01111111, + 0xbb9bb900, 0xb9b9bb99, 0xb99bbbbb, 0xbbbb9b9b, + 0xb9bb99bb, 0xb99999b9, 0xb9b9b99b, 0x00000bbb, + 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, + 0xa8aa88aa, 0xa88888a8, 0xa8a8a88a, 0x0a888aaa, + 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, + 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00000aaa, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0xbbbbbb00, 0x999bbbbb, 0x9bb99b9b, 0xb9b9b9bb, + 0xb9b99bbb, 0xb9b9b9bb, 0xb9bb9b99, 0x00000999, + 0x8a000000, 0xaa88a888, 0xa88888aa, 0xa88a8a88, + 0xa88aa88a, 0x88a8aaaa, 0xa8aa8aaa, 0x0888a88a, + 0x0b0b0b00, 0x090b0b0b, 0x0b090b0b, 0x0909090b, + 0x09090b0b, 0x09090b0b, 0x09090b09, 0x00000909, + 0x0a000000, 0x0a080808, 0x080a080a, 0x080a0a08, + 0x080a080a, 0x0808080a, 0x0a0a0a08, 0x0808080a, + 0xb0b0b000, 0x9090b0b0, 0x90b09090, 0xb0b0b090, + 0xb0b090b0, 0x90b0b0b0, 0xb0b09090, 0x00000090, + 0x80000000, 0xa080a080, 0xa08080a0, 0xa0808080, + 0xa080a080, 0x80a0a0a0, 0xa0a080a0, 0x00a0a0a0, + 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, + 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, + 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, + 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, + 0x33000000, 0x3333f333, 0x33333333, 0x333333f3, + 0xf3333330, 0x33333333, 0x33f33333, 0x00000333, + 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, + 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, + 0x99000000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, + 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x88888000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, + 0x88a88a00, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, + 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, + 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, + 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, + 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_intlevel_r3[] = { + 0x00802070, 0x0671188d, 0x0a60192c, 0x0a300e46, + 0x00c1188d, 0x080024d2, 0x00000070, +}; + +static const uint32_t bwn_ntab_tdtrn_r3[] = { + 0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6, + 0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68, + 0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52, + 0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050, + 0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6, + 0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68, + 0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52, + 0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050, + 0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246, + 0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c, + 0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61, + 0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d, + 0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246, + 0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c, + 0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61, + 0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d, + 0xfa58fa58, 0xf895043b, 0xff4c09c0, 0xfbc6ffa8, + 0xfb84f384, 0x0798f6f9, 0x05760122, 0x058409f6, + 0x0b500000, 0x05b7f542, 0x08860432, 0x06ddfee7, + 0xfb84f384, 0xf9d90664, 0xf7e8025c, 0x00fff7bd, + 0x05a805a8, 0xf7bd00ff, 0x025cf7e8, 0x0664f9d9, + 0xf384fb84, 0xfee706dd, 0x04320886, 0xf54205b7, + 0x00000b50, 0x09f60584, 0x01220576, 0xf6f90798, + 0xf384fb84, 0xffa8fbc6, 0x09c0ff4c, 0x043bf895, + 0x02d402d4, 0x07de0270, 0xfc96079c, 0xf90afe94, + 0xfe00ff2c, 0x02d4065d, 0x092a0096, 0x0014fbb8, + 0xfd2cfd2c, 0x076afb3c, 0x0096f752, 0xf991fd87, + 0xfb2c0200, 0xfeb8f960, 0x08e0fc96, 0x049802a8, + 0xfd2cfd2c, 0x02a80498, 0xfc9608e0, 0xf960feb8, + 0x0200fb2c, 0xfd87f991, 0xf7520096, 0xfb3c076a, + 0xfd2cfd2c, 0xfbb80014, 0x0096092a, 0x065d02d4, + 0xff2cfe00, 0xfe94f90a, 0x079cfc96, 0x027007de, + 0x02d402d4, 0x027007de, 0x079cfc96, 0xfe94f90a, + 0xff2cfe00, 0x065d02d4, 0x0096092a, 0xfbb80014, + 0xfd2cfd2c, 0xfb3c076a, 0xf7520096, 0xfd87f991, + 0x0200fb2c, 0xf960feb8, 0xfc9608e0, 0x02a80498, + 0xfd2cfd2c, 0x049802a8, 0x08e0fc96, 0xfeb8f960, + 0xfb2c0200, 0xf991fd87, 0x0096f752, 0x076afb3c, + 0xfd2cfd2c, 0x0014fbb8, 0x092a0096, 0x02d4065d, + 0xfe00ff2c, 0xf90afe94, 0xfc96079c, 0x07de0270, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d, + 0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf, + 0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8, + 0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7, + 0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3, + 0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841, + 0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608, + 0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759, + 0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d, + 0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf, + 0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8, + 0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7, + 0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3, + 0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841, + 0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608, + 0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759, + 0x061c061c, 0xff30009d, 0xffb21141, 0xfd87fb54, + 0xf65dfe59, 0x02eef99e, 0x0166f03c, 0xfff809b6, + 0x000008a4, 0x000af42b, 0x00eff577, 0xfa840bf2, + 0xfc02ff51, 0x08260f67, 0xfff0036f, 0x0842f9c3, + 0x00000000, 0x063df7be, 0xfc910010, 0xf099f7da, + 0x00af03fe, 0xf40e057c, 0x0a89ff11, 0x0bd5fff6, + 0xf75c0000, 0xf64a0008, 0x0fc4fe9a, 0x0662fd12, + 0x01a709a3, 0x04ac0279, 0xeebf004e, 0xff6300d0, + 0xf9e4f9e4, 0x00d0ff63, 0x004eeebf, 0x027904ac, + 0x09a301a7, 0xfd120662, 0xfe9a0fc4, 0x0008f64a, + 0x0000f75c, 0xfff60bd5, 0xff110a89, 0x057cf40e, + 0x03fe00af, 0xf7daf099, 0x0010fc91, 0xf7be063d, + 0x00000000, 0xf9c30842, 0x036ffff0, 0x0f670826, + 0xff51fc02, 0x0bf2fa84, 0xf57700ef, 0xf42b000a, + 0x08a40000, 0x09b6fff8, 0xf03c0166, 0xf99e02ee, + 0xfe59f65d, 0xfb54fd87, 0x1141ffb2, 0x009dff30, + 0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59, + 0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766, + 0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986, + 0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb, + 0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7, + 0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a, + 0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a, + 0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705, + 0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59, + 0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766, + 0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986, + 0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb, + 0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7, + 0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a, + 0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a, + 0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705, + 0xfa58fa58, 0xf8f0fe00, 0x0448073d, 0xfdc9fe46, + 0xf9910258, 0x089d0407, 0xfd5cf71a, 0x02affde0, + 0x083e0496, 0xff5a0740, 0xff7afd97, 0x00fe01f1, + 0x0009082e, 0xfa94ff75, 0xfecdf8ea, 0xffb0f693, + 0xfd2cfa58, 0x0433ff16, 0xfba405dd, 0xfa610341, + 0x06a606cb, 0x0039fd2d, 0x0677fa97, 0x01fa05e0, + 0xf896003e, 0x075a068b, 0x012cfc3e, 0xfa23f98d, + 0xfc7cfd43, 0xff90fc0d, 0x01c10982, 0x00c601d6, + 0xfd2cfd2c, 0x01d600c6, 0x098201c1, 0xfc0dff90, + 0xfd43fc7c, 0xf98dfa23, 0xfc3e012c, 0x068b075a, + 0x003ef896, 0x05e001fa, 0xfa970677, 0xfd2d0039, + 0x06cb06a6, 0x0341fa61, 0x05ddfba4, 0xff160433, + 0xfa58fd2c, 0xf693ffb0, 0xf8eafecd, 0xff75fa94, + 0x082e0009, 0x01f100fe, 0xfd97ff7a, 0x0740ff5a, + 0x0496083e, 0xfde002af, 0xf71afd5c, 0x0407089d, + 0x0258f991, 0xfe46fdc9, 0x073d0448, 0xfe00f8f0, + 0xfd2cfd2c, 0xfce00500, 0xfc09fddc, 0xfe680157, + 0x04c70571, 0xfc3aff21, 0xfcd70228, 0x056d0277, + 0x0200fe00, 0x0022f927, 0xfe3c032b, 0xfc44ff3c, + 0x03e9fbdb, 0x04570313, 0x04c9ff5c, 0x000d03b8, + 0xfa580000, 0xfbe900d2, 0xf9d0fe0b, 0x0125fdf9, + 0x042501bf, 0x0328fa2b, 0xffa902f0, 0xfa250157, + 0x0200fe00, 0x03740438, 0xff0405fd, 0x030cfe52, + 0x0037fb39, 0xff6904c5, 0x04f8fd23, 0xfd31fc1b, + 0xfd2cfd2c, 0xfc1bfd31, 0xfd2304f8, 0x04c5ff69, + 0xfb390037, 0xfe52030c, 0x05fdff04, 0x04380374, + 0xfe000200, 0x0157fa25, 0x02f0ffa9, 0xfa2b0328, + 0x01bf0425, 0xfdf90125, 0xfe0bf9d0, 0x00d2fbe9, + 0x0000fa58, 0x03b8000d, 0xff5c04c9, 0x03130457, + 0xfbdb03e9, 0xff3cfc44, 0x032bfe3c, 0xf9270022, + 0xfe000200, 0x0277056d, 0x0228fcd7, 0xff21fc3a, + 0x057104c7, 0x0157fe68, 0xfddcfc09, 0x0500fce0, + 0xfd2cfd2c, 0x0500fce0, 0xfddcfc09, 0x0157fe68, + 0x057104c7, 0xff21fc3a, 0x0228fcd7, 0x0277056d, + 0xfe000200, 0xf9270022, 0x032bfe3c, 0xff3cfc44, + 0xfbdb03e9, 0x03130457, 0xff5c04c9, 0x03b8000d, + 0x0000fa58, 0x00d2fbe9, 0xfe0bf9d0, 0xfdf90125, + 0x01bf0425, 0xfa2b0328, 0x02f0ffa9, 0x0157fa25, + 0xfe000200, 0x04380374, 0x05fdff04, 0xfe52030c, + 0xfb390037, 0x04c5ff69, 0xfd2304f8, 0xfc1bfd31, + 0xfd2cfd2c, 0xfd31fc1b, 0x04f8fd23, 0xff6904c5, + 0x0037fb39, 0x030cfe52, 0xff0405fd, 0x03740438, + 0x0200fe00, 0xfa250157, 0xffa902f0, 0x0328fa2b, + 0x042501bf, 0x0125fdf9, 0xf9d0fe0b, 0xfbe900d2, + 0xfa580000, 0x000d03b8, 0x04c9ff5c, 0x04570313, + 0x03e9fbdb, 0xfc44ff3c, 0xfe3c032b, 0x0022f927, + 0x0200fe00, 0x056d0277, 0xfcd70228, 0xfc3aff21, + 0x04c70571, 0xfe680157, 0xfc09fddc, 0xfce00500, + 0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e, + 0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c, + 0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926, + 0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942, + 0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382, + 0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4, + 0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da, + 0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be, + 0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e, + 0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c, + 0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926, + 0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942, + 0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382, + 0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4, + 0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da, + 0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be, +}; + +static const uint32_t bwn_ntab_noisevar_r3[] = { + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, + 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, +}; + +static const uint16_t bwn_ntab_mcs_r3[] = { + 0x0000, 0x0008, 0x000a, 0x0010, 0x0012, 0x0019, + 0x001a, 0x001c, 0x0080, 0x0088, 0x008a, 0x0090, + 0x0092, 0x0099, 0x009a, 0x009c, 0x0100, 0x0108, + 0x010a, 0x0110, 0x0112, 0x0119, 0x011a, 0x011c, + 0x0180, 0x0188, 0x018a, 0x0190, 0x0192, 0x0199, + 0x019a, 0x019c, 0x0000, 0x0098, 0x00a0, 0x00a8, + 0x009a, 0x00a2, 0x00aa, 0x0120, 0x0128, 0x0128, + 0x0130, 0x0138, 0x0138, 0x0140, 0x0122, 0x012a, + 0x012a, 0x0132, 0x013a, 0x013a, 0x0142, 0x01a8, + 0x01b0, 0x01b8, 0x01b0, 0x01b8, 0x01c0, 0x01c8, + 0x01c0, 0x01c8, 0x01d0, 0x01d0, 0x01d8, 0x01aa, + 0x01b2, 0x01ba, 0x01b2, 0x01ba, 0x01c2, 0x01ca, + 0x01c2, 0x01ca, 0x01d2, 0x01d2, 0x01da, 0x0001, + 0x0002, 0x0004, 0x0009, 0x000c, 0x0011, 0x0014, + 0x0018, 0x0020, 0x0021, 0x0022, 0x0024, 0x0081, + 0x0082, 0x0084, 0x0089, 0x008c, 0x0091, 0x0094, + 0x0098, 0x00a0, 0x00a1, 0x00a2, 0x00a4, 0x0007, + 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, + 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, + 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, + 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, + 0x0007, 0x0007, +}; + +static const uint32_t bwn_ntab_tdi20a0_r3[] = { + 0x00091226, 0x000a1429, 0x000b56ad, 0x000c58b0, + 0x000d5ab3, 0x000e9cb6, 0x000f9eba, 0x0000c13d, + 0x00020301, 0x00030504, 0x00040708, 0x0005090b, + 0x00064b8e, 0x00095291, 0x000a5494, 0x000b9718, + 0x000c9927, 0x000d9b2a, 0x000edd2e, 0x000fdf31, + 0x000101b4, 0x000243b7, 0x000345bb, 0x000447be, + 0x00058982, 0x00068c05, 0x00099309, 0x000a950c, + 0x000bd78f, 0x000cd992, 0x000ddb96, 0x000f1d99, + 0x00005fa8, 0x0001422c, 0x0002842f, 0x00038632, + 0x00048835, 0x0005ca38, 0x0006ccbc, 0x0009d3bf, + 0x000b1603, 0x000c1806, 0x000d1a0a, 0x000e1c0d, + 0x000f5e10, 0x00008093, 0x00018297, 0x0002c49a, + 0x0003c680, 0x0004c880, 0x00060b00, 0x00070d00, + 0x00000000, 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_tdi20a1_r3[] = { + 0x00014b26, 0x00028d29, 0x000393ad, 0x00049630, + 0x0005d833, 0x0006da36, 0x00099c3a, 0x000a9e3d, + 0x000bc081, 0x000cc284, 0x000dc488, 0x000f068b, + 0x0000488e, 0x00018b91, 0x0002d214, 0x0003d418, + 0x0004d6a7, 0x000618aa, 0x00071aae, 0x0009dcb1, + 0x000b1eb4, 0x000c0137, 0x000d033b, 0x000e053e, + 0x000f4702, 0x00008905, 0x00020c09, 0x0003128c, + 0x0004148f, 0x00051712, 0x00065916, 0x00091b19, + 0x000a1d28, 0x000b5f2c, 0x000c41af, 0x000d43b2, + 0x000e85b5, 0x000f87b8, 0x0000c9bc, 0x00024cbf, + 0x00035303, 0x00045506, 0x0005978a, 0x0006998d, + 0x00095b90, 0x000a5d93, 0x000b9f97, 0x000c821a, + 0x000d8400, 0x000ec600, 0x000fc800, 0x00010a00, + 0x00000000, 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_tdi40a0_r3[] = { + 0x0011a346, 0x00136ccf, 0x0014f5d9, 0x001641e2, + 0x0017cb6b, 0x00195475, 0x001b2383, 0x001cad0c, + 0x001e7616, 0x0000821f, 0x00020ba8, 0x0003d4b2, + 0x00056447, 0x00072dd0, 0x0008b6da, 0x000a02e3, + 0x000b8c6c, 0x000d15f6, 0x0011e484, 0x0013ae0d, + 0x00153717, 0x00168320, 0x00180ca9, 0x00199633, + 0x001b6548, 0x001ceed1, 0x001eb7db, 0x0000c3e4, + 0x00024d6d, 0x000416f7, 0x0005a585, 0x00076f0f, + 0x0008f818, 0x000a4421, 0x000bcdab, 0x000d9734, + 0x00122649, 0x0013efd2, 0x001578dc, 0x0016c4e5, + 0x00184e6e, 0x001a17f8, 0x001ba686, 0x001d3010, + 0x001ef999, 0x00010522, 0x00028eac, 0x00045835, + 0x0005e74a, 0x0007b0d3, 0x00093a5d, 0x000a85e6, + 0x000c0f6f, 0x000dd8f9, 0x00126787, 0x00143111, + 0x0015ba9a, 0x00170623, 0x00188fad, 0x001a5936, + 0x001be84b, 0x001db1d4, 0x001f3b5e, 0x000146e7, + 0x00031070, 0x000499fa, 0x00062888, 0x0007f212, + 0x00097b9b, 0x000ac7a4, 0x000c50ae, 0x000e1a37, + 0x0012a94c, 0x001472d5, 0x0015fc5f, 0x00174868, + 0x0018d171, 0x001a9afb, 0x001c2989, 0x001df313, + 0x001f7c9c, 0x000188a5, 0x000351af, 0x0004db38, + 0x0006aa4d, 0x000833d7, 0x0009bd60, 0x000b0969, + 0x000c9273, 0x000e5bfc, 0x00132a8a, 0x0014b414, + 0x00163d9d, 0x001789a6, 0x001912b0, 0x001adc39, + 0x001c6bce, 0x001e34d8, 0x001fbe61, 0x0001ca6a, + 0x00039374, 0x00051cfd, 0x0006ec0b, 0x00087515, + 0x0009fe9e, 0x000b4aa7, 0x000cd3b1, 0x000e9d3a, + 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_tdi40a1_r3[] = { + 0x001edb36, 0x000129ca, 0x0002b353, 0x00047cdd, + 0x0005c8e6, 0x000791ef, 0x00091bf9, 0x000aaa07, + 0x000c3391, 0x000dfd1a, 0x00120923, 0x0013d22d, + 0x00155c37, 0x0016eacb, 0x00187454, 0x001a3dde, + 0x001b89e7, 0x001d12f0, 0x001f1cfa, 0x00016b88, + 0x00033492, 0x0004be1b, 0x00060a24, 0x0007d32e, + 0x00095d38, 0x000aec4c, 0x000c7555, 0x000e3edf, + 0x00124ae8, 0x001413f1, 0x0015a37b, 0x00172c89, + 0x0018b593, 0x001a419c, 0x001bcb25, 0x001d942f, + 0x001f63b9, 0x0001ad4d, 0x00037657, 0x0004c260, + 0x00068be9, 0x000814f3, 0x0009a47c, 0x000b2d8a, + 0x000cb694, 0x000e429d, 0x00128c26, 0x001455b0, + 0x0015e4ba, 0x00176e4e, 0x0018f758, 0x001a8361, + 0x001c0cea, 0x001dd674, 0x001fa57d, 0x0001ee8b, + 0x0003b795, 0x0005039e, 0x0006cd27, 0x000856b1, + 0x0009e5c6, 0x000b6f4f, 0x000cf859, 0x000e8462, + 0x00130deb, 0x00149775, 0x00162603, 0x0017af8c, + 0x00193896, 0x001ac49f, 0x001c4e28, 0x001e17b2, + 0x0000a6c7, 0x00023050, 0x0003f9da, 0x00054563, + 0x00070eec, 0x00089876, 0x000a2704, 0x000bb08d, + 0x000d3a17, 0x001185a0, 0x00134f29, 0x0014d8b3, + 0x001667c8, 0x0017f151, 0x00197adb, 0x001b0664, + 0x001c8fed, 0x001e5977, 0x0000e805, 0x0002718f, + 0x00043b18, 0x000586a1, 0x0007502b, 0x0008d9b4, + 0x000a68c9, 0x000bf252, 0x000dbbdc, 0x0011c7e5, + 0x001390ee, 0x00151a78, 0x0016a906, 0x00183290, + 0x0019bc19, 0x001b4822, 0x001cd12c, 0x001e9ab5, + 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_pilotlt_r3[] = { + 0x76540213, 0x62407351, 0x76543210, 0x76540213, + 0x76540213, 0x76430521, +}; + +static const uint32_t bwn_ntab_channelest_r3[] = { + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x44444444, 0x44444444, 0x44444444, 0x44444444, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, + 0x10101010, 0x10101010, 0x10101010, 0x10101010, +}; + +static const uint8_t bwn_ntab_framelookup_r3[] = { + 0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16, + 0x0a, 0x0c, 0x1c, 0x1c, 0x0b, 0x0d, 0x1e, 0x1e, + 0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1a, 0x1a, + 0x0e, 0x10, 0x20, 0x28, 0x0f, 0x11, 0x22, 0x2a, +}; + +static const uint8_t bwn_ntab_estimatepowerlt0_r3[] = { + 0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51, + 0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c, + 0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46, + 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f, + 0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36, + 0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b, + 0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a, + 0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd, +}; + +static const uint8_t bwn_ntab_estimatepowerlt1_r3[] = { + 0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51, + 0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c, + 0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46, + 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f, + 0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36, + 0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b, + 0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a, + 0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd, +}; + +static const uint8_t bwn_ntab_adjustpower0_r3[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const uint8_t bwn_ntab_adjustpower1_r3[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const uint32_t bwn_ntab_gainctl0_r3[] = { + 0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e, + 0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037, + 0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031, + 0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040, + 0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039, + 0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033, + 0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e, + 0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037, + 0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031, + 0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c, + 0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e, + 0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037, + 0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031, + 0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c, + 0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042, + 0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b, + 0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034, + 0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f, + 0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e, + 0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037, + 0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031, + 0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c, + 0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027, + 0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023, + 0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e, + 0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037, + 0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031, + 0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c, + 0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027, + 0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023, + 0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f, + 0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c, +}; + +static const uint32_t bwn_ntab_gainctl1_r3[] = { + 0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e, + 0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037, + 0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031, + 0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040, + 0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039, + 0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033, + 0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e, + 0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037, + 0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031, + 0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c, + 0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e, + 0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037, + 0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031, + 0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c, + 0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042, + 0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b, + 0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034, + 0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f, + 0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e, + 0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037, + 0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031, + 0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c, + 0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027, + 0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023, + 0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e, + 0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037, + 0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031, + 0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c, + 0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027, + 0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023, + 0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f, + 0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c, +}; + +static const uint32_t bwn_ntab_iqlt0_r3[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const uint32_t bwn_ntab_iqlt1_r3[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const uint16_t bwn_ntab_loftlt0_r3[] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, +}; + +static const uint16_t bwn_ntab_loftlt1_r3[] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, +}; + +/* volatile tables, PHY revision >= 3 */ + +/* indexed by antswctl2g */ +static const uint16_t bwn_ntab_antswctl_r3[4][32] = { + { + 0x0082, 0x0082, 0x0211, 0x0222, 0x0328, + 0x0000, 0x0000, 0x0000, 0x0144, 0x0000, + 0x0000, 0x0000, 0x0188, 0x0000, 0x0000, + 0x0000, 0x0082, 0x0082, 0x0211, 0x0222, + 0x0328, 0x0000, 0x0000, 0x0000, 0x0144, + 0x0000, 0x0000, 0x0000, 0x0188, 0x0000, + 0x0000, 0x0000, + }, + { + 0x0022, 0x0022, 0x0011, 0x0022, 0x0022, + 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, + 0x0000, 0x0000, 0x0022, 0x0000, 0x0000, + 0x0000, 0x0022, 0x0022, 0x0011, 0x0022, + 0x0022, 0x0000, 0x0000, 0x0000, 0x0011, + 0x0000, 0x0000, 0x0000, 0x0022, 0x0000, + 0x0000, 0x0000, + }, + { + 0x0088, 0x0088, 0x0044, 0x0088, 0x0088, + 0x0000, 0x0000, 0x0000, 0x0044, 0x0000, + 0x0000, 0x0000, 0x0088, 0x0000, 0x0000, + 0x0000, 0x0088, 0x0088, 0x0044, 0x0088, + 0x0088, 0x0000, 0x0000, 0x0000, 0x0044, + 0x0000, 0x0000, 0x0000, 0x0088, 0x0000, + 0x0000, 0x0000, + }, + { + 0x0022, 0x0022, 0x0011, 0x0022, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, + 0x0000, 0x0000, 0x0022, 0x0000, 0x0000, + 0x03cc, 0x0022, 0x0022, 0x0011, 0x0022, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0011, + 0x0000, 0x0000, 0x0000, 0x0022, 0x0000, + 0x0000, 0x03cc, + } +}; + +/* static tables, PHY revision >= 7 */ + +/* Copied from brcmsmac (5.75.11) */ +static const uint32_t bwn_ntab_tmap_r7[] = { + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, + 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888, + 0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, + 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, + 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, + 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, + 0xf1111110, 0x11111111, 0x11f11111, 0x00011111, + 0x11110000, 0x1111f111, 0x11111111, 0x111111f1, + 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00088aaa, + 0xaaaa0000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, + 0xaaa8aaa0, 0x8aaa8aaa, 0xaa8a8a8a, 0x000aaa88, + 0x8aaa0000, 0xaaa8a888, 0x8aa88a8a, 0x8a88a888, + 0x08080a00, 0x0a08080a, 0x080a0a08, 0x00080808, + 0x080a0000, 0x080a0808, 0x080a0808, 0x0a0a0a08, + 0xa0a0a0a0, 0x80a0a080, 0x8080a0a0, 0x00008080, + 0x80a00000, 0x80a080a0, 0xa080a0a0, 0x8080a0a0, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x99999000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, + 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, + 0x22000000, 0x2222b222, 0x22222222, 0x222222b2, + 0xb2222220, 0x22222222, 0x22d22222, 0x00000222, + 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, + 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, + 0x33000000, 0x3333b333, 0x33333333, 0x333333b3, + 0xb3333330, 0x33333333, 0x33d33333, 0x00000333, + 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, + 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, + 0x99b99b00, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, + 0x9b99bb99, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, + 0x22222200, 0x2222f222, 0x22222222, 0x222222f2, + 0x22222222, 0x22222222, 0x22f22222, 0x00000222, + 0x11000000, 0x1111f111, 0x11111111, 0x11111111, + 0xf1111111, 0x11111111, 0x11f11111, 0x01111111, + 0xbb9bb900, 0xb9b9bb99, 0xb99bbbbb, 0xbbbb9b9b, + 0xb9bb99bb, 0xb99999b9, 0xb9b9b99b, 0x00000bbb, + 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, + 0xa8aa88aa, 0xa88888a8, 0xa8a8a88a, 0x0a888aaa, + 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, + 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00000aaa, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0xbbbbbb00, 0x999bbbbb, 0x9bb99b9b, 0xb9b9b9bb, + 0xb9b99bbb, 0xb9b9b9bb, 0xb9bb9b99, 0x00000999, + 0x8a000000, 0xaa88a888, 0xa88888aa, 0xa88a8a88, + 0xa88aa88a, 0x88a8aaaa, 0xa8aa8aaa, 0x0888a88a, + 0x0b0b0b00, 0x090b0b0b, 0x0b090b0b, 0x0909090b, + 0x09090b0b, 0x09090b0b, 0x09090b09, 0x00000909, + 0x0a000000, 0x0a080808, 0x080a080a, 0x080a0a08, + 0x080a080a, 0x0808080a, 0x0a0a0a08, 0x0808080a, + 0xb0b0b000, 0x9090b0b0, 0x90b09090, 0xb0b0b090, + 0xb0b090b0, 0x90b0b0b0, 0xb0b09090, 0x00000090, + 0x80000000, 0xa080a080, 0xa08080a0, 0xa0808080, + 0xa080a080, 0x80a0a0a0, 0xa0a080a0, 0x00a0a0a0, + 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, + 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, + 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, + 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, + 0x33000000, 0x3333f333, 0x33333333, 0x333333f3, + 0xf3333330, 0x33333333, 0x33f33333, 0x00000333, + 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, + 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, + 0x99000000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, + 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x88888000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, + 0x88a88a00, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888, + 0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, + 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, + 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, + 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, + 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, + 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +/* Extracted from MMIO dump of 6.30.223.141 */ +static const uint32_t bwn_ntab_noisevar_r7[] = { + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, + 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, +}; + +/************************************************** + * TX gain tables + **************************************************/ + +static const uint32_t bwn_ntab_tx_gain_rev0_1_2[] = { + 0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42, + 0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44, + 0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844, + 0x03c82842, 0x03c42b44, 0x03c42b42, 0x03c42a44, + 0x03c42a42, 0x03c42944, 0x03c42942, 0x03c42844, + 0x03c42842, 0x03c42744, 0x03c42742, 0x03c42644, + 0x03c42642, 0x03c42544, 0x03c42542, 0x03c42444, + 0x03c42442, 0x03c02b44, 0x03c02b42, 0x03c02a44, + 0x03c02a42, 0x03c02944, 0x03c02942, 0x03c02844, + 0x03c02842, 0x03c02744, 0x03c02742, 0x03b02b44, + 0x03b02b42, 0x03b02a44, 0x03b02a42, 0x03b02944, + 0x03b02942, 0x03b02844, 0x03b02842, 0x03b02744, + 0x03b02742, 0x03b02644, 0x03b02642, 0x03b02544, + 0x03b02542, 0x03a02b44, 0x03a02b42, 0x03a02a44, + 0x03a02a42, 0x03a02944, 0x03a02942, 0x03a02844, + 0x03a02842, 0x03a02744, 0x03a02742, 0x03902b44, + 0x03902b42, 0x03902a44, 0x03902a42, 0x03902944, + 0x03902942, 0x03902844, 0x03902842, 0x03902744, + 0x03902742, 0x03902644, 0x03902642, 0x03902544, + 0x03902542, 0x03802b44, 0x03802b42, 0x03802a44, + 0x03802a42, 0x03802944, 0x03802942, 0x03802844, + 0x03802842, 0x03802744, 0x03802742, 0x03802644, + 0x03802642, 0x03802544, 0x03802542, 0x03802444, + 0x03802442, 0x03802344, 0x03802342, 0x03802244, + 0x03802242, 0x03802144, 0x03802142, 0x03802044, + 0x03802042, 0x03801f44, 0x03801f42, 0x03801e44, + 0x03801e42, 0x03801d44, 0x03801d42, 0x03801c44, + 0x03801c42, 0x03801b44, 0x03801b42, 0x03801a44, + 0x03801a42, 0x03801944, 0x03801942, 0x03801844, + 0x03801842, 0x03801744, 0x03801742, 0x03801644, + 0x03801642, 0x03801544, 0x03801542, 0x03801444, + 0x03801442, 0x03801344, 0x03801342, 0x00002b00, +}; + +/* EPA 2 GHz */ + +static const uint32_t bwn_ntab_tx_gain_epa_rev3_2g[] = { + 0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e, + 0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037, + 0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e, + 0x1e41003c, 0x1e41003b, 0x1e410039, 0x1e410037, + 0x1d410044, 0x1d410042, 0x1d410040, 0x1d41003e, + 0x1d41003c, 0x1d41003b, 0x1d410039, 0x1d410037, + 0x1c410044, 0x1c410042, 0x1c410040, 0x1c41003e, + 0x1c41003c, 0x1c41003b, 0x1c410039, 0x1c410037, + 0x1b410044, 0x1b410042, 0x1b410040, 0x1b41003e, + 0x1b41003c, 0x1b41003b, 0x1b410039, 0x1b410037, + 0x1a410044, 0x1a410042, 0x1a410040, 0x1a41003e, + 0x1a41003c, 0x1a41003b, 0x1a410039, 0x1a410037, + 0x19410044, 0x19410042, 0x19410040, 0x1941003e, + 0x1941003c, 0x1941003b, 0x19410039, 0x19410037, + 0x18410044, 0x18410042, 0x18410040, 0x1841003e, + 0x1841003c, 0x1841003b, 0x18410039, 0x18410037, + 0x17410044, 0x17410042, 0x17410040, 0x1741003e, + 0x1741003c, 0x1741003b, 0x17410039, 0x17410037, + 0x16410044, 0x16410042, 0x16410040, 0x1641003e, + 0x1641003c, 0x1641003b, 0x16410039, 0x16410037, + 0x15410044, 0x15410042, 0x15410040, 0x1541003e, + 0x1541003c, 0x1541003b, 0x15410039, 0x15410037, + 0x14410044, 0x14410042, 0x14410040, 0x1441003e, + 0x1441003c, 0x1441003b, 0x14410039, 0x14410037, + 0x13410044, 0x13410042, 0x13410040, 0x1341003e, + 0x1341003c, 0x1341003b, 0x13410039, 0x13410037, + 0x12410044, 0x12410042, 0x12410040, 0x1241003e, + 0x1241003c, 0x1241003b, 0x12410039, 0x12410037, + 0x11410044, 0x11410042, 0x11410040, 0x1141003e, + 0x1141003c, 0x1141003b, 0x11410039, 0x11410037, + 0x10410044, 0x10410042, 0x10410040, 0x1041003e, + 0x1041003c, 0x1041003b, 0x10410039, 0x10410037, +}; + +static const uint32_t bwn_ntab_tx_gain_epa_rev3_hi_pwr_2g[] = { + 0x0f410044, 0x0f410042, 0x0f410040, 0x0f41003e, + 0x0f41003c, 0x0f41003b, 0x0f410039, 0x0f410037, + 0x0e410044, 0x0e410042, 0x0e410040, 0x0e41003e, + 0x0e41003c, 0x0e41003b, 0x0e410039, 0x0e410037, + 0x0d410044, 0x0d410042, 0x0d410040, 0x0d41003e, + 0x0d41003c, 0x0d41003b, 0x0d410039, 0x0d410037, + 0x0c410044, 0x0c410042, 0x0c410040, 0x0c41003e, + 0x0c41003c, 0x0c41003b, 0x0c410039, 0x0c410037, + 0x0b410044, 0x0b410042, 0x0b410040, 0x0b41003e, + 0x0b41003c, 0x0b41003b, 0x0b410039, 0x0b410037, + 0x0a410044, 0x0a410042, 0x0a410040, 0x0a41003e, + 0x0a41003c, 0x0a41003b, 0x0a410039, 0x0a410037, + 0x09410044, 0x09410042, 0x09410040, 0x0941003e, + 0x0941003c, 0x0941003b, 0x09410039, 0x09410037, + 0x08410044, 0x08410042, 0x08410040, 0x0841003e, + 0x0841003c, 0x0841003b, 0x08410039, 0x08410037, + 0x07410044, 0x07410042, 0x07410040, 0x0741003e, + 0x0741003c, 0x0741003b, 0x07410039, 0x07410037, + 0x06410044, 0x06410042, 0x06410040, 0x0641003e, + 0x0641003c, 0x0641003b, 0x06410039, 0x06410037, + 0x05410044, 0x05410042, 0x05410040, 0x0541003e, + 0x0541003c, 0x0541003b, 0x05410039, 0x05410037, + 0x04410044, 0x04410042, 0x04410040, 0x0441003e, + 0x0441003c, 0x0441003b, 0x04410039, 0x04410037, + 0x03410044, 0x03410042, 0x03410040, 0x0341003e, + 0x0341003c, 0x0341003b, 0x03410039, 0x03410037, + 0x02410044, 0x02410042, 0x02410040, 0x0241003e, + 0x0241003c, 0x0241003b, 0x02410039, 0x02410037, + 0x01410044, 0x01410042, 0x01410040, 0x0141003e, + 0x0141003c, 0x0141003b, 0x01410039, 0x01410037, + 0x00410044, 0x00410042, 0x00410040, 0x0041003e, + 0x0041003c, 0x0041003b, 0x00410039, 0x00410037 +}; + +/* EPA 5 GHz */ + +static const uint32_t bwn_ntab_tx_gain_epa_rev3_5g[] = { + 0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e, + 0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037, + 0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e, + 0xcef7003c, 0xcef7003b, 0xcef70039, 0xcef70037, + 0xcdf70044, 0xcdf70042, 0xcdf70040, 0xcdf7003e, + 0xcdf7003c, 0xcdf7003b, 0xcdf70039, 0xcdf70037, + 0xccf70044, 0xccf70042, 0xccf70040, 0xccf7003e, + 0xccf7003c, 0xccf7003b, 0xccf70039, 0xccf70037, + 0xcbf70044, 0xcbf70042, 0xcbf70040, 0xcbf7003e, + 0xcbf7003c, 0xcbf7003b, 0xcbf70039, 0xcbf70037, + 0xcaf70044, 0xcaf70042, 0xcaf70040, 0xcaf7003e, + 0xcaf7003c, 0xcaf7003b, 0xcaf70039, 0xcaf70037, + 0xc9f70044, 0xc9f70042, 0xc9f70040, 0xc9f7003e, + 0xc9f7003c, 0xc9f7003b, 0xc9f70039, 0xc9f70037, + 0xc8f70044, 0xc8f70042, 0xc8f70040, 0xc8f7003e, + 0xc8f7003c, 0xc8f7003b, 0xc8f70039, 0xc8f70037, + 0xc7f70044, 0xc7f70042, 0xc7f70040, 0xc7f7003e, + 0xc7f7003c, 0xc7f7003b, 0xc7f70039, 0xc7f70037, + 0xc6f70044, 0xc6f70042, 0xc6f70040, 0xc6f7003e, + 0xc6f7003c, 0xc6f7003b, 0xc6f70039, 0xc6f70037, + 0xc5f70044, 0xc5f70042, 0xc5f70040, 0xc5f7003e, + 0xc5f7003c, 0xc5f7003b, 0xc5f70039, 0xc5f70037, + 0xc4f70044, 0xc4f70042, 0xc4f70040, 0xc4f7003e, + 0xc4f7003c, 0xc4f7003b, 0xc4f70039, 0xc4f70037, + 0xc3f70044, 0xc3f70042, 0xc3f70040, 0xc3f7003e, + 0xc3f7003c, 0xc3f7003b, 0xc3f70039, 0xc3f70037, + 0xc2f70044, 0xc2f70042, 0xc2f70040, 0xc2f7003e, + 0xc2f7003c, 0xc2f7003b, 0xc2f70039, 0xc2f70037, + 0xc1f70044, 0xc1f70042, 0xc1f70040, 0xc1f7003e, + 0xc1f7003c, 0xc1f7003b, 0xc1f70039, 0xc1f70037, + 0xc0f70044, 0xc0f70042, 0xc0f70040, 0xc0f7003e, + 0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037, +}; + +static const uint32_t bwn_ntab_tx_gain_epa_rev4_5g[] = { + 0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e, + 0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037, + 0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e, + 0x2ef2003c, 0x2ef2003b, 0x2ef20039, 0x2ef20037, + 0x2df20044, 0x2df20042, 0x2df20040, 0x2df2003e, + 0x2df2003c, 0x2df2003b, 0x2df20039, 0x2df20037, + 0x2cf20044, 0x2cf20042, 0x2cf20040, 0x2cf2003e, + 0x2cf2003c, 0x2cf2003b, 0x2cf20039, 0x2cf20037, + 0x2bf20044, 0x2bf20042, 0x2bf20040, 0x2bf2003e, + 0x2bf2003c, 0x2bf2003b, 0x2bf20039, 0x2bf20037, + 0x2af20044, 0x2af20042, 0x2af20040, 0x2af2003e, + 0x2af2003c, 0x2af2003b, 0x2af20039, 0x2af20037, + 0x29f20044, 0x29f20042, 0x29f20040, 0x29f2003e, + 0x29f2003c, 0x29f2003b, 0x29f20039, 0x29f20037, + 0x28f20044, 0x28f20042, 0x28f20040, 0x28f2003e, + 0x28f2003c, 0x28f2003b, 0x28f20039, 0x28f20037, + 0x27f20044, 0x27f20042, 0x27f20040, 0x27f2003e, + 0x27f2003c, 0x27f2003b, 0x27f20039, 0x27f20037, + 0x26f20044, 0x26f20042, 0x26f20040, 0x26f2003e, + 0x26f2003c, 0x26f2003b, 0x26f20039, 0x26f20037, + 0x25f20044, 0x25f20042, 0x25f20040, 0x25f2003e, + 0x25f2003c, 0x25f2003b, 0x25f20039, 0x25f20037, + 0x24f20044, 0x24f20042, 0x24f20040, 0x24f2003e, + 0x24f2003c, 0x24f2003b, 0x24f20039, 0x24f20038, + 0x23f20041, 0x23f20040, 0x23f2003f, 0x23f2003e, + 0x23f2003c, 0x23f2003b, 0x23f20039, 0x23f20037, + 0x22f20044, 0x22f20042, 0x22f20040, 0x22f2003e, + 0x22f2003c, 0x22f2003b, 0x22f20039, 0x22f20037, + 0x21f20044, 0x21f20042, 0x21f20040, 0x21f2003e, + 0x21f2003c, 0x21f2003b, 0x21f20039, 0x21f20037, + 0x20d20043, 0x20d20041, 0x20d2003e, 0x20d2003c, + 0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034, +}; + +static const uint32_t bwn_ntab_tx_gain_epa_rev4_hi_pwr_5g[] = { + 0x2ff10044, 0x2ff10042, 0x2ff10040, 0x2ff1003e, + 0x2ff1003c, 0x2ff1003b, 0x2ff10039, 0x2ff10037, + 0x2ef10044, 0x2ef10042, 0x2ef10040, 0x2ef1003e, + 0x2ef1003c, 0x2ef1003b, 0x2ef10039, 0x2ef10037, + 0x2df10044, 0x2df10042, 0x2df10040, 0x2df1003e, + 0x2df1003c, 0x2df1003b, 0x2df10039, 0x2df10037, + 0x2cf10044, 0x2cf10042, 0x2cf10040, 0x2cf1003e, + 0x2cf1003c, 0x2cf1003b, 0x2cf10039, 0x2cf10037, + 0x2bf10044, 0x2bf10042, 0x2bf10040, 0x2bf1003e, + 0x2bf1003c, 0x2bf1003b, 0x2bf10039, 0x2bf10037, + 0x2af10044, 0x2af10042, 0x2af10040, 0x2af1003e, + 0x2af1003c, 0x2af1003b, 0x2af10039, 0x2af10037, + 0x29f10044, 0x29f10042, 0x29f10040, 0x29f1003e, + 0x29f1003c, 0x29f1003b, 0x29f10039, 0x29f10037, + 0x28f10044, 0x28f10042, 0x28f10040, 0x28f1003e, + 0x28f1003c, 0x28f1003b, 0x28f10039, 0x28f10037, + 0x27f10044, 0x27f10042, 0x27f10040, 0x27f1003e, + 0x27f1003c, 0x27f1003b, 0x27f10039, 0x27f10037, + 0x26f10044, 0x26f10042, 0x26f10040, 0x26f1003e, + 0x26f1003c, 0x26f1003b, 0x26f10039, 0x26f10037, + 0x25f10044, 0x25f10042, 0x25f10040, 0x25f1003e, + 0x25f1003c, 0x25f1003b, 0x25f10039, 0x25f10037, + 0x24f10044, 0x24f10042, 0x24f10040, 0x24f1003e, + 0x24f1003c, 0x24f1003b, 0x24f10039, 0x24f10038, + 0x23f10041, 0x23f10040, 0x23f1003f, 0x23f1003e, + 0x23f1003c, 0x23f1003b, 0x23f10039, 0x23f10037, + 0x22f10044, 0x22f10042, 0x22f10040, 0x22f1003e, + 0x22f1003c, 0x22f1003b, 0x22f10039, 0x22f10037, + 0x21f10044, 0x21f10042, 0x21f10040, 0x21f1003e, + 0x21f1003c, 0x21f1003b, 0x21f10039, 0x21f10037, + 0x20d10043, 0x20d10041, 0x20d1003e, 0x20d1003c, + 0x20d1003a, 0x20d10038, 0x20d10036, 0x20d10034 +}; + +static const uint32_t bwn_ntab_tx_gain_epa_rev5_5g[] = { + 0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044, + 0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c, + 0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e, + 0x0e62003c, 0x0e62003d, 0x0e62003b, 0x0e62003a, + 0x0d620043, 0x0d620041, 0x0d620040, 0x0d62003e, + 0x0d62003d, 0x0d62003c, 0x0d62003b, 0x0d62003a, + 0x0c620041, 0x0c620040, 0x0c62003f, 0x0c62003e, + 0x0c62003c, 0x0c62003b, 0x0c620039, 0x0c620037, + 0x0b620046, 0x0b620044, 0x0b620042, 0x0b620040, + 0x0b62003e, 0x0b62003c, 0x0b62003b, 0x0b62003a, + 0x0a620041, 0x0a620040, 0x0a62003e, 0x0a62003c, + 0x0a62003b, 0x0a62003a, 0x0a620039, 0x0a620038, + 0x0962003e, 0x0962003d, 0x0962003c, 0x0962003b, + 0x09620039, 0x09620037, 0x09620035, 0x09620033, + 0x08620044, 0x08620042, 0x08620040, 0x0862003e, + 0x0862003c, 0x0862003b, 0x0862003a, 0x08620039, + 0x07620043, 0x07620042, 0x07620040, 0x0762003f, + 0x0762003d, 0x0762003b, 0x0762003a, 0x07620039, + 0x0662003e, 0x0662003d, 0x0662003c, 0x0662003b, + 0x06620039, 0x06620037, 0x06620035, 0x06620033, + 0x05620046, 0x05620044, 0x05620042, 0x05620040, + 0x0562003e, 0x0562003c, 0x0562003b, 0x05620039, + 0x04620044, 0x04620042, 0x04620040, 0x0462003e, + 0x0462003c, 0x0462003b, 0x04620039, 0x04620038, + 0x0362003c, 0x0362003b, 0x0362003a, 0x03620039, + 0x03620038, 0x03620037, 0x03620035, 0x03620033, + 0x0262004c, 0x0262004a, 0x02620048, 0x02620047, + 0x02620046, 0x02620044, 0x02620043, 0x02620042, + 0x0162004a, 0x01620048, 0x01620046, 0x01620044, + 0x01620043, 0x01620042, 0x01620041, 0x01620040, + 0x00620042, 0x00620040, 0x0062003e, 0x0062003c, + 0x0062003b, 0x00620039, 0x00620037, 0x00620035, +}; + +/* IPA 2 GHz */ + +static const uint32_t bwn_ntab_tx_gain_ipa_rev3_2g[] = { + 0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029, + 0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025, + 0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029, + 0x5ef70028, 0x5ef70027, 0x5ef70026, 0x5ef70025, + 0x5df7002d, 0x5df7002b, 0x5df7002a, 0x5df70029, + 0x5df70028, 0x5df70027, 0x5df70026, 0x5df70025, + 0x5cf7002d, 0x5cf7002b, 0x5cf7002a, 0x5cf70029, + 0x5cf70028, 0x5cf70027, 0x5cf70026, 0x5cf70025, + 0x5bf7002d, 0x5bf7002b, 0x5bf7002a, 0x5bf70029, + 0x5bf70028, 0x5bf70027, 0x5bf70026, 0x5bf70025, + 0x5af7002d, 0x5af7002b, 0x5af7002a, 0x5af70029, + 0x5af70028, 0x5af70027, 0x5af70026, 0x5af70025, + 0x59f7002d, 0x59f7002b, 0x59f7002a, 0x59f70029, + 0x59f70028, 0x59f70027, 0x59f70026, 0x59f70025, + 0x58f7002d, 0x58f7002b, 0x58f7002a, 0x58f70029, + 0x58f70028, 0x58f70027, 0x58f70026, 0x58f70025, + 0x57f7002d, 0x57f7002b, 0x57f7002a, 0x57f70029, + 0x57f70028, 0x57f70027, 0x57f70026, 0x57f70025, + 0x56f7002d, 0x56f7002b, 0x56f7002a, 0x56f70029, + 0x56f70028, 0x56f70027, 0x56f70026, 0x56f70025, + 0x55f7002d, 0x55f7002b, 0x55f7002a, 0x55f70029, + 0x55f70028, 0x55f70027, 0x55f70026, 0x55f70025, + 0x54f7002d, 0x54f7002b, 0x54f7002a, 0x54f70029, + 0x54f70028, 0x54f70027, 0x54f70026, 0x54f70025, + 0x53f7002d, 0x53f7002b, 0x53f7002a, 0x53f70029, + 0x53f70028, 0x53f70027, 0x53f70026, 0x53f70025, + 0x52f7002d, 0x52f7002b, 0x52f7002a, 0x52f70029, + 0x52f70028, 0x52f70027, 0x52f70026, 0x52f70025, + 0x51f7002d, 0x51f7002b, 0x51f7002a, 0x51f70029, + 0x51f70028, 0x51f70027, 0x51f70026, 0x51f70025, + 0x50f7002d, 0x50f7002b, 0x50f7002a, 0x50f70029, + 0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025, +}; + +static const uint32_t bwn_ntab_tx_gain_ipa_rev5_2g[] = { + 0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029, + 0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025, + 0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029, + 0x1ef70028, 0x1ef70027, 0x1ef70026, 0x1ef70025, + 0x1df7002d, 0x1df7002b, 0x1df7002a, 0x1df70029, + 0x1df70028, 0x1df70027, 0x1df70026, 0x1df70025, + 0x1cf7002d, 0x1cf7002b, 0x1cf7002a, 0x1cf70029, + 0x1cf70028, 0x1cf70027, 0x1cf70026, 0x1cf70025, + 0x1bf7002d, 0x1bf7002b, 0x1bf7002a, 0x1bf70029, + 0x1bf70028, 0x1bf70027, 0x1bf70026, 0x1bf70025, + 0x1af7002d, 0x1af7002b, 0x1af7002a, 0x1af70029, + 0x1af70028, 0x1af70027, 0x1af70026, 0x1af70025, + 0x19f7002d, 0x19f7002b, 0x19f7002a, 0x19f70029, + 0x19f70028, 0x19f70027, 0x19f70026, 0x19f70025, + 0x18f7002d, 0x18f7002b, 0x18f7002a, 0x18f70029, + 0x18f70028, 0x18f70027, 0x18f70026, 0x18f70025, + 0x17f7002d, 0x17f7002b, 0x17f7002a, 0x17f70029, + 0x17f70028, 0x17f70027, 0x17f70026, 0x17f70025, + 0x16f7002d, 0x16f7002b, 0x16f7002a, 0x16f70029, + 0x16f70028, 0x16f70027, 0x16f70026, 0x16f70025, + 0x15f7002d, 0x15f7002b, 0x15f7002a, 0x15f70029, + 0x15f70028, 0x15f70027, 0x15f70026, 0x15f70025, + 0x14f7002d, 0x14f7002b, 0x14f7002a, 0x14f70029, + 0x14f70028, 0x14f70027, 0x14f70026, 0x14f70025, + 0x13f7002d, 0x13f7002b, 0x13f7002a, 0x13f70029, + 0x13f70028, 0x13f70027, 0x13f70026, 0x13f70025, + 0x12f7002d, 0x12f7002b, 0x12f7002a, 0x12f70029, + 0x12f70028, 0x12f70027, 0x12f70026, 0x12f70025, + 0x11f7002d, 0x11f7002b, 0x11f7002a, 0x11f70029, + 0x11f70028, 0x11f70027, 0x11f70026, 0x11f70025, + 0x10f7002d, 0x10f7002b, 0x10f7002a, 0x10f70029, + 0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025, +}; + +static const uint32_t bwn_ntab_tx_gain_ipa_rev6_2g[] = { + 0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029, + 0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025, + 0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029, + 0x0ef70028, 0x0ef70027, 0x0ef70026, 0x0ef70025, + 0x0df7002d, 0x0df7002b, 0x0df7002a, 0x0df70029, + 0x0df70028, 0x0df70027, 0x0df70026, 0x0df70025, + 0x0cf7002d, 0x0cf7002b, 0x0cf7002a, 0x0cf70029, + 0x0cf70028, 0x0cf70027, 0x0cf70026, 0x0cf70025, + 0x0bf7002d, 0x0bf7002b, 0x0bf7002a, 0x0bf70029, + 0x0bf70028, 0x0bf70027, 0x0bf70026, 0x0bf70025, + 0x0af7002d, 0x0af7002b, 0x0af7002a, 0x0af70029, + 0x0af70028, 0x0af70027, 0x0af70026, 0x0af70025, + 0x09f7002d, 0x09f7002b, 0x09f7002a, 0x09f70029, + 0x09f70028, 0x09f70027, 0x09f70026, 0x09f70025, + 0x08f7002d, 0x08f7002b, 0x08f7002a, 0x08f70029, + 0x08f70028, 0x08f70027, 0x08f70026, 0x08f70025, + 0x07f7002d, 0x07f7002b, 0x07f7002a, 0x07f70029, + 0x07f70028, 0x07f70027, 0x07f70026, 0x07f70025, + 0x06f7002d, 0x06f7002b, 0x06f7002a, 0x06f70029, + 0x06f70028, 0x06f70027, 0x06f70026, 0x06f70025, + 0x05f7002d, 0x05f7002b, 0x05f7002a, 0x05f70029, + 0x05f70028, 0x05f70027, 0x05f70026, 0x05f70025, + 0x04f7002d, 0x04f7002b, 0x04f7002a, 0x04f70029, + 0x04f70028, 0x04f70027, 0x04f70026, 0x04f70025, + 0x03f7002d, 0x03f7002b, 0x03f7002a, 0x03f70029, + 0x03f70028, 0x03f70027, 0x03f70026, 0x03f70025, + 0x02f7002d, 0x02f7002b, 0x02f7002a, 0x02f70029, + 0x02f70028, 0x02f70027, 0x02f70026, 0x02f70025, + 0x01f7002d, 0x01f7002b, 0x01f7002a, 0x01f70029, + 0x01f70028, 0x01f70027, 0x01f70026, 0x01f70025, + 0x00f7002d, 0x00f7002b, 0x00f7002a, 0x00f70029, + 0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025, +}; + +/* Copied from brcmsmac (5.75.11): nphy_tpc_txgain_ipa_2g_2057rev5 */ +static const uint32_t bwn_ntab_tx_gain_ipa_2057_rev5_2g[] = { + 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e, + 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033, + 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e, + 0x3067002e, 0x305f002f, 0x30570030, 0x3057002d, + 0x304f002e, 0x30470031, 0x3047002e, 0x3047002c, + 0x30470029, 0x303f002c, 0x303f0029, 0x3037002d, + 0x3037002a, 0x30370028, 0x302f002c, 0x302f002a, + 0x302f0028, 0x302f0026, 0x3027002c, 0x30270029, + 0x30270027, 0x30270025, 0x30270023, 0x301f002c, + 0x301f002a, 0x301f0028, 0x301f0025, 0x301f0024, + 0x301f0022, 0x301f001f, 0x3017002d, 0x3017002b, + 0x30170028, 0x30170026, 0x30170024, 0x30170022, + 0x30170020, 0x3017001e, 0x3017001d, 0x3017001b, + 0x3017001a, 0x30170018, 0x30170017, 0x30170015, + 0x300f002c, 0x300f0029, 0x300f0027, 0x300f0024, + 0x300f0022, 0x300f0021, 0x300f001f, 0x300f001d, + 0x300f001b, 0x300f001a, 0x300f0018, 0x300f0017, + 0x300f0016, 0x300f0015, 0x300f0115, 0x300f0215, + 0x300f0315, 0x300f0415, 0x300f0515, 0x300f0615, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, + 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, +}; + +/* Extracted from MMIO dump of 6.30.223.141 */ +static const uint32_t bwn_ntab_tx_gain_ipa_2057_rev9_2g[] = { + 0x60ff0031, 0x60e7002c, 0x60cf002a, 0x60c70029, + 0x60b70029, 0x60a70029, 0x609f002a, 0x6097002b, + 0x6087002e, 0x60770031, 0x606f0032, 0x60670034, + 0x60670031, 0x605f0033, 0x605f0031, 0x60570033, + 0x60570030, 0x6057002d, 0x6057002b, 0x604f002d, + 0x604f002b, 0x604f0029, 0x604f0026, 0x60470029, + 0x60470027, 0x603f0029, 0x603f0027, 0x603f0025, + 0x60370029, 0x60370027, 0x60370024, 0x602f002a, + 0x602f0028, 0x602f0026, 0x602f0024, 0x6027002a, + 0x60270028, 0x60270026, 0x60270024, 0x60270022, + 0x601f002b, 0x601f0029, 0x601f0027, 0x601f0024, + 0x601f0022, 0x601f0020, 0x601f001f, 0x601f001d, + 0x60170029, 0x60170027, 0x60170025, 0x60170023, + 0x60170021, 0x6017001f, 0x6017001d, 0x6017001c, + 0x6017001a, 0x60170018, 0x60170018, 0x60170016, + 0x60170015, 0x600f0029, 0x600f0027, 0x600f0025, + 0x600f0023, 0x600f0021, 0x600f001f, 0x600f001d, + 0x600f001c, 0x600f001a, 0x600f0019, 0x600f0018, + 0x600f0016, 0x600f0015, 0x600f0115, 0x600f0215, + 0x600f0315, 0x600f0415, 0x600f0515, 0x600f0615, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, + 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, +}; + +/* Extracted from MMIO dump of 6.30.223.248 */ +static const uint32_t bwn_ntab_tx_gain_ipa_2057_rev14_2g[] = { + 0x50df002e, 0x50cf002d, 0x50bf002c, 0x50b7002b, + 0x50af002a, 0x50a70029, 0x509f0029, 0x50970028, + 0x508f0027, 0x50870027, 0x507f0027, 0x50770027, + 0x506f0027, 0x50670027, 0x505f0028, 0x50570029, + 0x504f002b, 0x5047002e, 0x5047002b, 0x50470029, + 0x503f002c, 0x503f0029, 0x5037002c, 0x5037002a, + 0x50370028, 0x502f002d, 0x502f002b, 0x502f0028, + 0x502f0026, 0x5027002d, 0x5027002a, 0x50270028, + 0x50270026, 0x50270024, 0x501f002e, 0x501f002b, + 0x501f0029, 0x501f0027, 0x501f0024, 0x501f0022, + 0x501f0020, 0x501f001f, 0x5017002c, 0x50170029, + 0x50170027, 0x50170024, 0x50170022, 0x50170021, + 0x5017001f, 0x5017001d, 0x5017001b, 0x5017001a, + 0x50170018, 0x50170017, 0x50170015, 0x500f002c, + 0x500f002a, 0x500f0027, 0x500f0025, 0x500f0023, + 0x500f0022, 0x500f001f, 0x500f001e, 0x500f001c, + 0x500f001a, 0x500f0019, 0x500f0018, 0x500f0016, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, + 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, +}; + +/* IPA 2 5Hz */ + +static const uint32_t bwn_ntab_tx_gain_ipa_rev3_5g[] = { + 0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031, + 0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b, + 0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027, + 0x7ff70026, 0x7ff70024, 0x7ff70023, 0x7ff70022, + 0x7ef70028, 0x7ef70027, 0x7ef70026, 0x7ef70025, + 0x7ef70024, 0x7ef70023, 0x7df70028, 0x7df70027, + 0x7df70026, 0x7df70025, 0x7df70024, 0x7df70023, + 0x7df70022, 0x7cf70029, 0x7cf70028, 0x7cf70027, + 0x7cf70026, 0x7cf70025, 0x7cf70023, 0x7cf70022, + 0x7bf70029, 0x7bf70028, 0x7bf70026, 0x7bf70025, + 0x7bf70024, 0x7bf70023, 0x7bf70022, 0x7bf70021, + 0x7af70029, 0x7af70028, 0x7af70027, 0x7af70026, + 0x7af70025, 0x7af70024, 0x7af70023, 0x7af70022, + 0x79f70029, 0x79f70028, 0x79f70027, 0x79f70026, + 0x79f70025, 0x79f70024, 0x79f70023, 0x79f70022, + 0x78f70029, 0x78f70028, 0x78f70027, 0x78f70026, + 0x78f70025, 0x78f70024, 0x78f70023, 0x78f70022, + 0x77f70029, 0x77f70028, 0x77f70027, 0x77f70026, + 0x77f70025, 0x77f70024, 0x77f70023, 0x77f70022, + 0x76f70029, 0x76f70028, 0x76f70027, 0x76f70026, + 0x76f70024, 0x76f70023, 0x76f70022, 0x76f70021, + 0x75f70029, 0x75f70028, 0x75f70027, 0x75f70026, + 0x75f70025, 0x75f70024, 0x75f70023, 0x74f70029, + 0x74f70028, 0x74f70026, 0x74f70025, 0x74f70024, + 0x74f70023, 0x74f70022, 0x73f70029, 0x73f70027, + 0x73f70026, 0x73f70025, 0x73f70024, 0x73f70023, + 0x73f70022, 0x72f70028, 0x72f70027, 0x72f70026, + 0x72f70025, 0x72f70024, 0x72f70023, 0x72f70022, + 0x71f70028, 0x71f70027, 0x71f70026, 0x71f70025, + 0x71f70024, 0x71f70023, 0x70f70028, 0x70f70027, + 0x70f70026, 0x70f70024, 0x70f70023, 0x70f70022, + 0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f, +}; + +/* Extracted from MMIO dump of 6.30.223.141 */ +static const uint32_t bwn_ntab_tx_gain_ipa_2057_rev9_5g[] = { + 0x7f7f0053, 0x7f7f004b, 0x7f7f0044, 0x7f7f003f, + 0x7f7f0039, 0x7f7f0035, 0x7f7f0032, 0x7f7f0030, + 0x7f7f002d, 0x7e7f0030, 0x7e7f002d, 0x7d7f0032, + 0x7d7f002f, 0x7d7f002c, 0x7c7f0032, 0x7c7f0030, + 0x7c7f002d, 0x7b7f0030, 0x7b7f002e, 0x7b7f002b, + 0x7a7f0032, 0x7a7f0030, 0x7a7f002d, 0x7a7f002b, + 0x797f0030, 0x797f002e, 0x797f002b, 0x797f0029, + 0x787f0030, 0x787f002d, 0x787f002b, 0x777f0032, + 0x777f0030, 0x777f002d, 0x777f002b, 0x767f0031, + 0x767f002f, 0x767f002c, 0x767f002a, 0x757f0031, + 0x757f002f, 0x757f002c, 0x757f002a, 0x747f0030, + 0x747f002d, 0x747f002b, 0x737f0032, 0x737f002f, + 0x737f002c, 0x737f002a, 0x727f0030, 0x727f002d, + 0x727f002b, 0x727f0029, 0x717f0030, 0x717f002d, + 0x717f002b, 0x707f0031, 0x707f002f, 0x707f002c, + 0x707f002a, 0x707f0027, 0x707f0025, 0x707f0023, + 0x707f0021, 0x707f001f, 0x707f001d, 0x707f001c, + 0x707f001a, 0x707f0019, 0x707f0017, 0x707f0016, + 0x707f0015, 0x707f0014, 0x707f0012, 0x707f0012, + 0x707f0011, 0x707f0010, 0x707f000f, 0x707f000e, + 0x707f000d, 0x707f000d, 0x707f000c, 0x707f000b, + 0x707f000a, 0x707f000a, 0x707f0009, 0x707f0008, + 0x707f0008, 0x707f0008, 0x707f0008, 0x707f0007, + 0x707f0007, 0x707f0006, 0x707f0006, 0x707f0006, + 0x707f0005, 0x707f0005, 0x707f0005, 0x707f0004, + 0x707f0004, 0x707f0004, 0x707f0003, 0x707f0003, + 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, + 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, + 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, + 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, + 0x707f0002, 0x707f0001, 0x707f0001, 0x707f0001, + 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001, +}; + +const int8_t bwn_ntab_papd_pga_gain_delta_ipa_2g[] = { + -114, -108, -98, -91, -84, -78, -70, -62, + -54, -46, -39, -31, -23, -15, -8, 0 +}; + +/* Extracted from MMIO dump of 6.30.223.248 + * Entries: 0, 15, 17, 21, 24, 26, 27, 29, 30 were guessed + */ +static const int16_t bwn_ntab_rf_pwr_offset_2057_rev9_2g[] = { + -133, -133, -107, -92, -81, + -73, -66, -61, -56, -52, + -48, -44, -41, -37, -34, + -31, -28, -25, -22, -19, + -17, -14, -12, -10, -9, + -7, -5, -4, -3, -2, + -1, 0, +}; + +/* Extracted from MMIO dump of 6.30.223.248 */ +static const int16_t bwn_ntab_rf_pwr_offset_2057_rev9_5g[] = { + -101, -94, -86, -79, -72, + -65, -57, -50, -42, -35, + -28, -21, -16, -9, -4, + 0, +}; + +/* Extracted from MMIO dump of 6.30.223.248 + * Entries: 0, 26, 28, 29, 30, 31 were guessed + */ +static const int16_t bwn_ntab_rf_pwr_offset_2057_rev14_2g[] = { + -111, -111, -111, -84, -70, + -59, -52, -45, -40, -36, + -32, -29, -26, -23, -21, + -18, -16, -15, -13, -11, + -10, -8, -7, -6, -5, + -4, -4, -3, -3, -2, + -2, -1, +}; + +const uint16_t tbl_iqcal_gainparams[2][9][8] = { + { + { 0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69 }, + { 0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69 }, + { 0x710, 7, 1, 0, 0x68, 0x68, 0x68, 0x68 }, + { 0x720, 7, 2, 0, 0x67, 0x67, 0x67, 0x67 }, + { 0x730, 7, 3, 0, 0x66, 0x66, 0x66, 0x66 }, + { 0x740, 7, 4, 0, 0x65, 0x65, 0x65, 0x65 }, + { 0x741, 7, 4, 1, 0x65, 0x65, 0x65, 0x65 }, + { 0x742, 7, 4, 2, 0x65, 0x65, 0x65, 0x65 }, + { 0x743, 7, 4, 3, 0x65, 0x65, 0x65, 0x65 } + }, + { + { 0x000, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 }, + { 0x700, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 }, + { 0x710, 7, 1, 0, 0x79, 0x79, 0x79, 0x79 }, + { 0x720, 7, 2, 0, 0x78, 0x78, 0x78, 0x78 }, + { 0x730, 7, 3, 0, 0x78, 0x78, 0x78, 0x78 }, + { 0x740, 7, 4, 0, 0x78, 0x78, 0x78, 0x78 }, + { 0x741, 7, 4, 1, 0x78, 0x78, 0x78, 0x78 }, + { 0x742, 7, 4, 2, 0x78, 0x78, 0x78, 0x78 }, + { 0x743, 7, 4, 3, 0x78, 0x78, 0x78, 0x78 } + } +}; + +const struct bwn_nphy_txiqcal_ladder ladder_lo[] = { + { 3, 0 }, + { 4, 0 }, + { 6, 0 }, + { 9, 0 }, + { 13, 0 }, + { 18, 0 }, + { 25, 0 }, + { 25, 1 }, + { 25, 2 }, + { 25, 3 }, + { 25, 4 }, + { 25, 5 }, + { 25, 6 }, + { 25, 7 }, + { 35, 7 }, + { 50, 7 }, + { 71, 7 }, + { 100, 7 } +}; + +const struct bwn_nphy_txiqcal_ladder ladder_iq[] = { + { 3, 0 }, + { 4, 0 }, + { 6, 0 }, + { 9, 0 }, + { 13, 0 }, + { 18, 0 }, + { 25, 0 }, + { 35, 0 }, + { 50, 0 }, + { 71, 0 }, + { 100, 0 }, + { 100, 1 }, + { 100, 2 }, + { 100, 3 }, + { 100, 4 }, + { 100, 5 }, + { 100, 6 }, + { 100, 7 } +}; + +const uint16_t loscale[] = { + 256, 256, 271, 271, + 287, 256, 256, 271, + 271, 287, 287, 304, + 304, 256, 256, 271, + 271, 287, 287, 304, + 304, 322, 322, 341, + 341, 362, 362, 383, + 383, 256, 256, 271, + 271, 287, 287, 304, + 304, 322, 322, 256, + 256, 271, 271, 287, + 287, 304, 304, 322, + 322, 341, 341, 362, + 362, 256, 256, 271, + 271, 287, 287, 304, + 304, 322, 322, 256, + 256, 271, 271, 287, + 287, 304, 304, 322, + 322, 341, 341, 362, + 362, 256, 256, 271, + 271, 287, 287, 304, + 304, 322, 322, 341, + 341, 362, 362, 383, + 383, 406, 406, 430, + 430, 455, 455, 482, + 482, 511, 511, 541, + 541, 573, 573, 607, + 607, 643, 643, 681, + 681, 722, 722, 764, + 764, 810, 810, 858, + 858, 908, 908, 962, + 962, 1019, 1019, 256 +}; + +const uint16_t tbl_tx_iqlo_cal_loft_ladder_40[] = { + 0x0200, 0x0300, 0x0400, 0x0700, + 0x0900, 0x0c00, 0x1200, 0x1201, + 0x1202, 0x1203, 0x1204, 0x1205, + 0x1206, 0x1207, 0x1907, 0x2307, + 0x3207, 0x4707 +}; + +const uint16_t tbl_tx_iqlo_cal_loft_ladder_20[] = { + 0x0300, 0x0500, 0x0700, 0x0900, + 0x0d00, 0x1100, 0x1900, 0x1901, + 0x1902, 0x1903, 0x1904, 0x1905, + 0x1906, 0x1907, 0x2407, 0x3207, + 0x4607, 0x6407 +}; + +const uint16_t tbl_tx_iqlo_cal_iqimb_ladder_40[] = { + 0x0100, 0x0200, 0x0400, 0x0700, + 0x0900, 0x0c00, 0x1200, 0x1900, + 0x2300, 0x3200, 0x4700, 0x4701, + 0x4702, 0x4703, 0x4704, 0x4705, + 0x4706, 0x4707 +}; + +const uint16_t tbl_tx_iqlo_cal_iqimb_ladder_20[] = { + 0x0200, 0x0300, 0x0600, 0x0900, + 0x0d00, 0x1100, 0x1900, 0x2400, + 0x3200, 0x4600, 0x6400, 0x6401, + 0x6402, 0x6403, 0x6404, 0x6405, + 0x6406, 0x6407 +}; + +const uint16_t tbl_tx_iqlo_cal_startcoefs_nphyrev3[BWN_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3] = { }; + +const uint16_t tbl_tx_iqlo_cal_startcoefs[BWN_NTAB_TX_IQLO_CAL_STARTCOEFS] = { }; + +const uint16_t tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = { + 0x8423, 0x8323, 0x8073, 0x8256, + 0x8045, 0x8223, 0x9423, 0x9323, + 0x9073, 0x9256, 0x9045, 0x9223 +}; + +const uint16_t tbl_tx_iqlo_cal_cmds_recal[] = { + 0x8101, 0x8253, 0x8053, 0x8234, + 0x8034, 0x9101, 0x9253, 0x9053, + 0x9234, 0x9034 +}; + +const uint16_t tbl_tx_iqlo_cal_cmds_fullcal[] = { + 0x8123, 0x8264, 0x8086, 0x8245, + 0x8056, 0x9123, 0x9264, 0x9086, + 0x9245, 0x9056 +}; + +const uint16_t tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = { + 0x8434, 0x8334, 0x8084, 0x8267, + 0x8056, 0x8234, 0x9434, 0x9334, + 0x9084, 0x9267, 0x9056, 0x9234 +}; + +const int16_t tbl_tx_filter_coef_rev4[7][15] = { + { -377, 137, -407, 208, -1527, + 956, 93, 186, 93, 230, + -44, 230, 201, -191, 201 }, + { -77, 20, -98, 49, -93, + 60, 56, 111, 56, 26, + -5, 26, 34, -32, 34 }, + { -360, 164, -376, 164, -1533, + 576, 308, -314, 308, 121, + -73, 121, 91, 124, 91 }, + { -295, 200, -363, 142, -1391, + 826, 151, 301, 151, 151, + 301, 151, 602, -752, 602 }, + { -92, 58, -96, 49, -104, + 44, 17, 35, 17, 12, + 25, 12, 13, 27, 13 }, + { -375, 136, -399, 209, -1479, + 949, 130, 260, 130, 230, + -44, 230, 201, -191, 201 }, + { 0xed9, 0xc8, 0xe95, 0x8e, 0xa91, + 0x33a, 0x97, 0x12d, 0x97, 0x97, + 0x12d, 0x97, 0x25a, 0xd10, 0x25a } +}; + +/* addr0, addr1, bmask, shift */ +const struct bwn_nphy_rf_control_override_rev2 tbl_rf_control_override_rev2[] = { + { 0x78, 0x78, 0x0038, 3 }, /* for field == 0x0002 (fls == 2) */ + { 0x7A, 0x7D, 0x0001, 0 }, /* for field == 0x0004 (fls == 3) */ + { 0x7A, 0x7D, 0x0002, 1 }, /* for field == 0x0008 (fls == 4) */ + { 0x7A, 0x7D, 0x0004, 2 }, /* for field == 0x0010 (fls == 5) */ + { 0x7A, 0x7D, 0x0030, 4 }, /* for field == 0x0020 (fls == 6) */ + { 0x7A, 0x7D, 0x00C0, 6 }, /* for field == 0x0040 (fls == 7) */ + { 0x7A, 0x7D, 0x0100, 8 }, /* for field == 0x0080 (fls == 8) */ + { 0x7A, 0x7D, 0x0200, 9 }, /* for field == 0x0100 (fls == 9) */ + { 0x78, 0x78, 0x0004, 2 }, /* for field == 0x0200 (fls == 10) */ + { 0x7B, 0x7E, 0x01FF, 0 }, /* for field == 0x0400 (fls == 11) */ + { 0x7C, 0x7F, 0x01FF, 0 }, /* for field == 0x0800 (fls == 12) */ + { 0x78, 0x78, 0x0100, 8 }, /* for field == 0x1000 (fls == 13) */ + { 0x78, 0x78, 0x0200, 9 }, /* for field == 0x2000 (fls == 14) */ + { 0x78, 0x78, 0xF000, 12 } /* for field == 0x4000 (fls == 15) */ +}; + +/* val_mask, val_shift, en_addr0, val_addr0, en_addr1, val_addr1 */ +const struct bwn_nphy_rf_control_override_rev3 tbl_rf_control_override_rev3[] = { + { 0x8000, 15, 0xE5, 0xF9, 0xE6, 0xFB }, /* field == 0x0001 (fls 1) */ + { 0x0001, 0, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0002 (fls 2) */ + { 0x0002, 1, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0004 (fls 3) */ + { 0x0004, 2, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0008 (fls 4) */ + { 0x0010, 4, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0010 (fls 5) */ + { 0x0020, 5, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0020 (fls 6) */ + { 0x0040, 6, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0040 (fls 7) */ + { 0x0080, 7, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0080 (fls 8) */ + { 0x0100, 8, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0100 (fls 9) */ + { 0x0007, 0, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0200 (fls 10) */ + { 0x0070, 4, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0400 (fls 11) */ + { 0xE000, 13, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0800 (fls 12) */ + { 0xFFFF, 0, 0xE7, 0x7B, 0xEC, 0x7E }, /* field == 0x1000 (fls 13) */ + { 0xFFFF, 0, 0xE7, 0x7C, 0xEC, 0x7F }, /* field == 0x2000 (fls 14) */ + { 0x00C0, 6, 0xE7, 0xF9, 0xEC, 0xFB } /* field == 0x4000 (fls 15) */ +}; + +/* field, val_addr_core0, val_addr_core1, val_mask, val_shift */ +static const struct bwn_nphy_rf_control_override_rev7 + tbl_rf_control_override_rev7_over0[] = { + { 0x0004, 0x07A, 0x07D, 0x0002, 1 }, + { 0x0008, 0x07A, 0x07D, 0x0004, 2 }, + { 0x0010, 0x07A, 0x07D, 0x0010, 4 }, + { 0x0020, 0x07A, 0x07D, 0x0020, 5 }, + { 0x0040, 0x07A, 0x07D, 0x0040, 6 }, + { 0x0080, 0x07A, 0x07D, 0x0080, 7 }, + { 0x0400, 0x0F8, 0x0FA, 0x0070, 4 }, + { 0x0800, 0x07B, 0x07E, 0xFFFF, 0 }, + { 0x1000, 0x07C, 0x07F, 0xFFFF, 0 }, + { 0x6000, 0x348, 0x349, 0x00FF, 0 }, + { 0x2000, 0x348, 0x349, 0x000F, 0 }, +}; + +/* field, val_addr_core0, val_addr_core1, val_mask, val_shift */ +static const struct bwn_nphy_rf_control_override_rev7 + tbl_rf_control_override_rev7_over1[] = { + { 0x0002, 0x340, 0x341, 0x0002, 1 }, + { 0x0008, 0x340, 0x341, 0x0008, 3 }, + { 0x0020, 0x340, 0x341, 0x0020, 5 }, + { 0x0010, 0x340, 0x341, 0x0010, 4 }, + { 0x0004, 0x340, 0x341, 0x0004, 2 }, + { 0x0080, 0x340, 0x341, 0x0700, 8 }, + { 0x0800, 0x340, 0x341, 0x4000, 14 }, + { 0x0400, 0x340, 0x341, 0x2000, 13 }, + { 0x0200, 0x340, 0x341, 0x0800, 12 }, + { 0x0100, 0x340, 0x341, 0x0100, 11 }, + { 0x0040, 0x340, 0x341, 0x0040, 6 }, + { 0x0001, 0x340, 0x341, 0x0001, 0 }, +}; + +/* field, val_addr_core0, val_addr_core1, val_mask, val_shift */ +static const struct bwn_nphy_rf_control_override_rev7 + tbl_rf_control_override_rev7_over2[] = { + { 0x0008, 0x344, 0x345, 0x0008, 3 }, + { 0x0002, 0x344, 0x345, 0x0002, 1 }, + { 0x0001, 0x344, 0x345, 0x0001, 0 }, + { 0x0004, 0x344, 0x345, 0x0004, 2 }, + { 0x0010, 0x344, 0x345, 0x0010, 4 }, +}; + +static struct bwn_nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = { + { 10, 14, 19, 27 }, + { -5, 6, 10, 15 }, + { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, + { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, + 0x427E, + { 0x413F, 0x413F, 0x413F, 0x413F }, + 0x007E, 0x0066, 0x1074, + 0x18, 0x18, 0x18, + 0x01D0, 0x5, +}; +static struct bwn_nphy_gain_ctl_workaround_entry nphy_gain_ctl_workaround[2][4] = { + { /* 2GHz */ + { /* PHY rev 3 */ + { 7, 11, 16, 23 }, + { -5, 6, 10, 14 }, + { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, + { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, + 0x627E, + { 0x613F, 0x613F, 0x613F, 0x613F }, + 0x107E, 0x0066, 0x0074, + 0x18, 0x18, 0x18, + 0x020D, 0x5, + }, + { /* PHY rev 4 */ + { 8, 12, 17, 25 }, + { -5, 6, 10, 14 }, + { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, + { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, + 0x527E, + { 0x513F, 0x513F, 0x513F, 0x513F }, + 0x007E, 0x0066, 0x0074, + 0x18, 0x18, 0x18, + 0x01A1, 0x5, + }, + { /* PHY rev 5 */ + { 9, 13, 18, 26 }, + { -3, 7, 11, 16 }, + { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, + { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, + 0x427E, /* invalid for external LNA! */ + { 0x413F, 0x413F, 0x413F, 0x413F }, /* invalid for external LNA! */ + 0x1076, 0x0066, 0x0000, /* low is invalid (the last one) */ + 0x18, 0x18, 0x18, + 0x01D0, 0x9, + }, + { /* PHY rev 6+ */ + { 8, 13, 18, 25 }, + { -5, 6, 10, 14 }, + { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, + { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, + 0x527E, /* invalid for external LNA! */ + { 0x513F, 0x513F, 0x513F, 0x513F }, /* invalid for external LNA! */ + 0x007E, 0x0066, 0x0000, /* low is invalid (the last one) */ + 0x18, 0x18, 0x18, + 0x01D0, 0x5, + }, + }, + { /* 5GHz */ + { /* PHY rev 3 */ + { 7, 11, 17, 23 }, + { -6, 2, 6, 10 }, + { 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 }, + { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }, + 0x52DE, + { 0x516F, 0x516F, 0x516F, 0x516F }, + 0x00DE, 0x00CA, 0x00CC, + 0x1E, 0x1E, 0x1E, + 0x01A1, 25, + }, + { /* PHY rev 4 */ + { 8, 12, 18, 23 }, + { -5, 2, 6, 10 }, + { 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD }, + { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 }, + 0x629E, + { 0x614F, 0x614F, 0x614F, 0x614F }, + 0x029E, 0x1084, 0x0086, + 0x24, 0x24, 0x24, + 0x0107, 25, + }, + { /* PHY rev 5 */ + { 6, 10, 16, 21 }, + { -7, 0, 4, 8 }, + { 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD }, + { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 }, + 0x729E, + { 0x714F, 0x714F, 0x714F, 0x714F }, + 0x029E, 0x2084, 0x2086, + 0x24, 0x24, 0x24, + 0x00A9, 25, + }, + { /* PHY rev 6+ */ + { 6, 10, 16, 21 }, + { -7, 0, 4, 8 }, + { 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD }, + { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 }, + 0x729E, + { 0x714F, 0x714F, 0x714F, 0x714F }, + 0x029E, 0x2084, 0x2086, + 0x24, 0x24, 0x24, /* low is invalid for radio rev 11! */ + 0x00F0, 25, + }, + }, +}; + +static inline void assert_ntab_array_sizes(void) +{ +#undef check +#define check(table, size) \ + CTASSERT(nitems(bwn_ntab_##table) == BWN_NTAB_##size##_SIZE) + + check(adjustpower0, C0_ADJPLT); + check(adjustpower1, C1_ADJPLT); + check(bdi, BDI); + check(channelest, CHANEST); + check(estimatepowerlt0, C0_ESTPLT); + check(estimatepowerlt1, C1_ESTPLT); + check(framelookup, FRAMELT); + check(framestruct, FRAMESTRUCT); + check(gainctl0, C0_GAINCTL); + check(gainctl1, C1_GAINCTL); + check(intlevel, INTLEVEL); + check(iqlt0, C0_IQLT); + check(iqlt1, C1_IQLT); + check(loftlt0, C0_LOFEEDTH); + check(loftlt1, C1_LOFEEDTH); + check(mcs, MCS); + check(noisevar10, NOISEVAR10); + check(noisevar11, NOISEVAR11); + check(pilot, PILOT); + check(pilotlt, PILOTLT); + check(tdi20a0, TDI20A0); + check(tdi20a1, TDI20A1); + check(tdi40a0, TDI40A0); + check(tdi40a1, TDI40A1); + check(tdtrn, TDTRN); + check(tmap, TMAP); + +#undef check +} + +uint32_t bwn_ntab_read(struct bwn_mac *mac, uint32_t offset) +{ + uint32_t type, value; + + type = offset & BWN_NTAB_TYPEMASK; + offset &= ~BWN_NTAB_TYPEMASK; + + KASSERT(offset <= 0xFFFF, ("%s: invalid offset (%d)\n", + __func__, offset)); + + switch (type) { + case BWN_NTAB_8BIT: + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); + value = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO) & 0xFF; + break; + case BWN_NTAB_16BIT: + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); + value = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); + break; + case BWN_NTAB_32BIT: + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); + value = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); + value |= BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATAHI) << 16; + break; + default: + KASSERT(0, ("%s: invalid type", __func__)); + value = 0; + } + + return value; +} + +void bwn_ntab_read_bulk(struct bwn_mac *mac, uint32_t offset, + unsigned int nr_elements, void *_data) +{ + struct bwn_softc *sc = mac->mac_sc; + uint32_t type; + uint8_t *data = _data; + unsigned int i; + + type = offset & BWN_NTAB_TYPEMASK; + offset &= ~BWN_NTAB_TYPEMASK; + KASSERT(offset <= 0xFFFF, ("%s: invalid offset (%d)\n", + __func__, offset)); + + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); + + for (i = 0; i < nr_elements; i++) { + /* Auto increment broken + caching issue on BCM43224? */ + if (siba_get_chipid(sc->sc_dev) == 43224 && + siba_get_revid(sc->sc_dev) == 1) { + BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset + i); + } + + switch (type) { + case BWN_NTAB_8BIT: + *data = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO) & 0xFF; + data++; + break; + case BWN_NTAB_16BIT: + *((uint16_t *)data) = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); + data += 2; + break; + case BWN_NTAB_32BIT: + *((uint32_t *)data) = + BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); + *((uint32_t *)data) |= + BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATAHI) << 16; + data += 4; + break; + default: + KASSERT(0, ("%s: called; invalid type (%d)\n", + __func__, type)); + } + } +} + +void bwn_ntab_write(struct bwn_mac *mac, uint32_t offset, uint32_t value) +{ + uint32_t type, orig; + + type = offset & BWN_NTAB_TYPEMASK; + orig = offset; + offset &= 0xFFFF; + + switch (type) { + case BWN_NTAB_8BIT: + KASSERT(value <= 0xFF, ("%s: 8bit: invalid value (%d) (0x%08x)\n", + __func__, value, orig)); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value); + break; + case BWN_NTAB_16BIT: + KASSERT(value <= 0xFFFF, ("%s: 8bit: invalid value (%d) (0x%08x)\n", + __func__, value, orig)); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value); + break; + case BWN_NTAB_32BIT: + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI, value >> 16); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value & 0xFFFF); + break; + default: + KASSERT(0, ("%s: called; invalid type (%d)\n", + __func__, type)); + } + + return; + + /* Some compiletime assertions... */ + assert_ntab_array_sizes(); +} + +void bwn_ntab_write_bulk(struct bwn_mac *mac, uint32_t offset, + unsigned int nr_elements, const void *_data) +{ + struct bwn_softc *sc = mac->mac_sc; + uint32_t type, value; + uint32_t orig; + const uint8_t *data = _data; + unsigned int i; + + type = offset & BWN_NTAB_TYPEMASK; + orig = offset; + offset &= ~BWN_NTAB_TYPEMASK; + KASSERT(offset <= 0xFFFF, ("%s: invalid offset (%d)\n", + __func__, offset)); + + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); + + for (i = 0; i < nr_elements; i++) { + /* Auto increment broken + caching issue on BCM43224? */ + if ((offset >> 10) == 9 && + siba_get_chipid(sc->sc_dev) == 43224 && + siba_get_revid(sc->sc_dev) == 1) { + BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset + i); + } + + switch (type) { + case BWN_NTAB_8BIT: + value = *data; + data++; + KASSERT(value <= 0xFF, ("%s: 8bit: invalid value (%d) (0x%08x)\n", + __func__, value, orig)); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value); + break; + case BWN_NTAB_16BIT: + value = *((const uint16_t *)data); + data += 2; + KASSERT(value <= 0xFFFF, ("%s: 16bit: invalid value (%d) (0x%08x)\n", + __func__, value, orig)); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value); + break; + case BWN_NTAB_32BIT: + value = *((const uint32_t *)data); + data += 4; + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI, value >> 16); + BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, + value & 0xFFFF); + break; + default: + KASSERT(0, ("%s: invalid type (%d)\n", __func__, + type)); + } + } +} + +#define ntab_upload(mac, offset, data) do { \ + bwn_ntab_write_bulk(mac, offset, nitems(data), data); \ + } while (0) + +static void bwn_nphy_tables_init_shared_lut(struct bwn_mac *mac) +{ + ntab_upload(mac, BWN_NTAB_C0_ESTPLT_R3, bwn_ntab_estimatepowerlt0_r3); + ntab_upload(mac, BWN_NTAB_C1_ESTPLT_R3, bwn_ntab_estimatepowerlt1_r3); + ntab_upload(mac, BWN_NTAB_C0_ADJPLT_R3, bwn_ntab_adjustpower0_r3); + ntab_upload(mac, BWN_NTAB_C1_ADJPLT_R3, bwn_ntab_adjustpower1_r3); + ntab_upload(mac, BWN_NTAB_C0_GAINCTL_R3, bwn_ntab_gainctl0_r3); + ntab_upload(mac, BWN_NTAB_C1_GAINCTL_R3, bwn_ntab_gainctl1_r3); + ntab_upload(mac, BWN_NTAB_C0_IQLT_R3, bwn_ntab_iqlt0_r3); + ntab_upload(mac, BWN_NTAB_C1_IQLT_R3, bwn_ntab_iqlt1_r3); + ntab_upload(mac, BWN_NTAB_C0_LOFEEDTH_R3, bwn_ntab_loftlt0_r3); + ntab_upload(mac, BWN_NTAB_C1_LOFEEDTH_R3, bwn_ntab_loftlt1_r3); +} + +static void bwn_nphy_tables_init_rev7_volatile(struct bwn_mac *mac) +{ + struct ieee80211com *ic = &mac->mac_sc->sc_ic; + struct bwn_softc *sc = mac->mac_sc; + uint8_t antswlut; + int core, offset, i; + + const int antswlut0_offsets[] = { 0, 4, 8, }; /* Offsets for values */ + const uint8_t antswlut0_values[][3] = { + { 0x2, 0x12, 0x8 }, /* Core 0 */ + { 0x2, 0x18, 0x2 }, /* Core 1 */ + }; + + if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) + antswlut = siba_sprom_get_fem_5ghz_antswlut(sc->sc_dev); + else + antswlut = siba_sprom_get_fem_2ghz_antswlut(sc->sc_dev); + + switch (antswlut) { + case 0: + for (core = 0; core < 2; core++) { + for (i = 0; i < nitems(antswlut0_values[0]); i++) { + offset = core ? 0x20 : 0x00; + offset += antswlut0_offsets[i]; + bwn_ntab_write(mac, BWN_NTAB8(9, offset), + antswlut0_values[core][i]); + } + } + break; + default: + BWN_ERRPRINTF(mac->mac_sc, "Unsupported antswlut: %d\n", antswlut); + break; + } +} + +static void bwn_nphy_tables_init_rev16(struct bwn_mac *mac) +{ + /* Static tables */ + if (mac->mac_phy.phy_do_full_init) { + ntab_upload(mac, BWN_NTAB_NOISEVAR_R7, bwn_ntab_noisevar_r7); + bwn_nphy_tables_init_shared_lut(mac); + } + + /* Volatile tables */ + bwn_nphy_tables_init_rev7_volatile(mac); +} + +static void bwn_nphy_tables_init_rev7(struct bwn_mac *mac) +{ + /* Static tables */ + if (mac->mac_phy.phy_do_full_init) { + ntab_upload(mac, BWN_NTAB_FRAMESTRUCT_R3, bwn_ntab_framestruct_r3); + ntab_upload(mac, BWN_NTAB_PILOT_R3, bwn_ntab_pilot_r3); + ntab_upload(mac, BWN_NTAB_TMAP_R7, bwn_ntab_tmap_r7); + ntab_upload(mac, BWN_NTAB_INTLEVEL_R3, bwn_ntab_intlevel_r3); + ntab_upload(mac, BWN_NTAB_TDTRN_R3, bwn_ntab_tdtrn_r3); + ntab_upload(mac, BWN_NTAB_NOISEVAR_R7, bwn_ntab_noisevar_r7); + ntab_upload(mac, BWN_NTAB_MCS_R3, bwn_ntab_mcs_r3); + ntab_upload(mac, BWN_NTAB_TDI20A0_R3, bwn_ntab_tdi20a0_r3); + ntab_upload(mac, BWN_NTAB_TDI20A1_R3, bwn_ntab_tdi20a1_r3); + ntab_upload(mac, BWN_NTAB_TDI40A0_R3, bwn_ntab_tdi40a0_r3); + ntab_upload(mac, BWN_NTAB_TDI40A1_R3, bwn_ntab_tdi40a1_r3); + ntab_upload(mac, BWN_NTAB_PILOTLT_R3, bwn_ntab_pilotlt_r3); + ntab_upload(mac, BWN_NTAB_CHANEST_R3, bwn_ntab_channelest_r3); + ntab_upload(mac, BWN_NTAB_FRAMELT_R3, bwn_ntab_framelookup_r3); + bwn_nphy_tables_init_shared_lut(mac); + } + + /* Volatile tables */ + bwn_nphy_tables_init_rev7_volatile(mac); +} + +static void bwn_nphy_tables_init_rev3(struct bwn_mac *mac) +{ + struct ieee80211com *ic = &mac->mac_sc->sc_ic; + struct bwn_softc *sc = mac->mac_sc; + uint8_t antswlut; + + if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) + antswlut = siba_sprom_get_fem_5ghz_antswlut(sc->sc_dev); + else + antswlut = siba_sprom_get_fem_2ghz_antswlut(sc->sc_dev); + + /* Static tables */ + if (mac->mac_phy.phy_do_full_init) { + ntab_upload(mac, BWN_NTAB_FRAMESTRUCT_R3, bwn_ntab_framestruct_r3); + ntab_upload(mac, BWN_NTAB_PILOT_R3, bwn_ntab_pilot_r3); + ntab_upload(mac, BWN_NTAB_TMAP_R3, bwn_ntab_tmap_r3); + ntab_upload(mac, BWN_NTAB_INTLEVEL_R3, bwn_ntab_intlevel_r3); + ntab_upload(mac, BWN_NTAB_TDTRN_R3, bwn_ntab_tdtrn_r3); + ntab_upload(mac, BWN_NTAB_NOISEVAR_R3, bwn_ntab_noisevar_r3); + ntab_upload(mac, BWN_NTAB_MCS_R3, bwn_ntab_mcs_r3); + ntab_upload(mac, BWN_NTAB_TDI20A0_R3, bwn_ntab_tdi20a0_r3); + ntab_upload(mac, BWN_NTAB_TDI20A1_R3, bwn_ntab_tdi20a1_r3); + ntab_upload(mac, BWN_NTAB_TDI40A0_R3, bwn_ntab_tdi40a0_r3); + ntab_upload(mac, BWN_NTAB_TDI40A1_R3, bwn_ntab_tdi40a1_r3); + ntab_upload(mac, BWN_NTAB_PILOTLT_R3, bwn_ntab_pilotlt_r3); + ntab_upload(mac, BWN_NTAB_CHANEST_R3, bwn_ntab_channelest_r3); + ntab_upload(mac, BWN_NTAB_FRAMELT_R3, bwn_ntab_framelookup_r3); + bwn_nphy_tables_init_shared_lut(mac); + } + + /* Volatile tables */ + if (antswlut < nitems(bwn_ntab_antswctl_r3)) + ntab_upload(mac, BWN_NTAB_ANT_SW_CTL_R3, + bwn_ntab_antswctl_r3[antswlut]); + else + KASSERT(0, ("%s: antswlut out of bounds (%d)\n", + __func__, antswlut)); +} + +static void bwn_nphy_tables_init_rev0(struct bwn_mac *mac) +{ + /* Static tables */ + if (mac->mac_phy.phy_do_full_init) { + ntab_upload(mac, BWN_NTAB_FRAMESTRUCT, bwn_ntab_framestruct); + ntab_upload(mac, BWN_NTAB_FRAMELT, bwn_ntab_framelookup); + ntab_upload(mac, BWN_NTAB_TMAP, bwn_ntab_tmap); + ntab_upload(mac, BWN_NTAB_TDTRN, bwn_ntab_tdtrn); + ntab_upload(mac, BWN_NTAB_INTLEVEL, bwn_ntab_intlevel); + ntab_upload(mac, BWN_NTAB_PILOT, bwn_ntab_pilot); + ntab_upload(mac, BWN_NTAB_TDI20A0, bwn_ntab_tdi20a0); + ntab_upload(mac, BWN_NTAB_TDI20A1, bwn_ntab_tdi20a1); + ntab_upload(mac, BWN_NTAB_TDI40A0, bwn_ntab_tdi40a0); + ntab_upload(mac, BWN_NTAB_TDI40A1, bwn_ntab_tdi40a1); + ntab_upload(mac, BWN_NTAB_CHANEST, bwn_ntab_channelest); + ntab_upload(mac, BWN_NTAB_MCS, bwn_ntab_mcs); + ntab_upload(mac, BWN_NTAB_NOISEVAR10, bwn_ntab_noisevar10); + ntab_upload(mac, BWN_NTAB_NOISEVAR11, bwn_ntab_noisevar11); + } + + /* Volatile tables */ + ntab_upload(mac, BWN_NTAB_BDI, bwn_ntab_bdi); + ntab_upload(mac, BWN_NTAB_PILOTLT, bwn_ntab_pilotlt); + ntab_upload(mac, BWN_NTAB_C0_GAINCTL, bwn_ntab_gainctl0); + ntab_upload(mac, BWN_NTAB_C1_GAINCTL, bwn_ntab_gainctl1); + ntab_upload(mac, BWN_NTAB_C0_ESTPLT, bwn_ntab_estimatepowerlt0); + ntab_upload(mac, BWN_NTAB_C1_ESTPLT, bwn_ntab_estimatepowerlt1); + ntab_upload(mac, BWN_NTAB_C0_ADJPLT, bwn_ntab_adjustpower0); + ntab_upload(mac, BWN_NTAB_C1_ADJPLT, bwn_ntab_adjustpower1); + ntab_upload(mac, BWN_NTAB_C0_IQLT, bwn_ntab_iqlt0); + ntab_upload(mac, BWN_NTAB_C1_IQLT, bwn_ntab_iqlt1); + ntab_upload(mac, BWN_NTAB_C0_LOFEEDTH, bwn_ntab_loftlt0); + ntab_upload(mac, BWN_NTAB_C1_LOFEEDTH, bwn_ntab_loftlt1); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables */ +void bwn_nphy_tables_init(struct bwn_mac *mac) +{ + if (mac->mac_phy.rev >= 16) + bwn_nphy_tables_init_rev16(mac); + else if (mac->mac_phy.rev >= 7) + bwn_nphy_tables_init_rev7(mac); + else if (mac->mac_phy.rev >= 3) + bwn_nphy_tables_init_rev3(mac); + else + bwn_nphy_tables_init_rev0(mac); +} + +/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ +static const uint32_t *bwn_nphy_get_ipa_gain_table(struct bwn_mac *mac) +{ + struct bwn_softc *sc = mac->mac_sc; + struct ieee80211com *ic = &mac->mac_sc->sc_ic; + struct bwn_phy *phy = &mac->mac_phy; + + if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { + switch (phy->rev) { + case 17: + if (phy->rf_rev == 14) + return bwn_ntab_tx_gain_ipa_2057_rev14_2g; + break; + case 16: + if (phy->rf_rev == 9) + return bwn_ntab_tx_gain_ipa_2057_rev9_2g; + break; + case 8: + if (phy->rf_rev == 5) + return bwn_ntab_tx_gain_ipa_2057_rev5_2g; + break; + case 6: + if (siba_get_chipid(sc->sc_dev) == 47162) /* BCM47612 */ + return bwn_ntab_tx_gain_ipa_rev5_2g; + return bwn_ntab_tx_gain_ipa_rev6_2g; + case 5: + return bwn_ntab_tx_gain_ipa_rev5_2g; + case 4: + case 3: + return bwn_ntab_tx_gain_ipa_rev3_2g; + } + + BWN_ERRPRINTF(mac->mac_sc, + "No 2GHz IPA gain table available for this device\n"); + return NULL; + } else { + switch (phy->rev) { + case 16: + if (phy->rf_rev == 9) + return bwn_ntab_tx_gain_ipa_2057_rev9_5g; + break; + case 3 ... 6: + return bwn_ntab_tx_gain_ipa_rev3_5g; + } + + BWN_ERRPRINTF(mac->mac_sc, + "No 5GHz IPA gain table available for this device\n"); + return NULL; + } +} + +const uint32_t *bwn_nphy_get_tx_gain_table(struct bwn_mac *mac) +{ + struct ieee80211com *ic = &mac->mac_sc->sc_ic; + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy *phy = &mac->mac_phy; + int is_5ghz; + + /* XXX ideally we'd have is2, is5, etc */ + is_5ghz = !! IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan); + + if (mac->mac_phy.rev < 3) + return bwn_ntab_tx_gain_rev0_1_2; + + /* rev 3+ */ + if ((mac->mac_phy.phy_n->ipa2g_on && is_5ghz == 0) || + (mac->mac_phy.phy_n->ipa5g_on && is_5ghz == 1)) { + return bwn_nphy_get_ipa_gain_table(mac); + } else if (is_5ghz == 1) { + switch (phy->rev) { + case 6: + case 5: + return bwn_ntab_tx_gain_epa_rev5_5g; + case 4: + return siba_sprom_get_fem_5ghz_extpa_gain(sc->sc_dev) == 3 ? + bwn_ntab_tx_gain_epa_rev4_5g : + bwn_ntab_tx_gain_epa_rev4_hi_pwr_5g; + case 3: + return bwn_ntab_tx_gain_epa_rev3_5g; + default: + BWN_ERRPRINTF(mac->mac_sc, + "No 5GHz EPA gain table available for this device\n"); + return NULL; + } + } else { + switch (phy->rev) { + case 6: + case 5: + if (siba_sprom_get_fem_5ghz_extpa_gain(sc->sc_dev) == 3) + return bwn_ntab_tx_gain_epa_rev3_hi_pwr_2g; + /* fall through */ + case 4: + case 3: + return bwn_ntab_tx_gain_epa_rev3_2g; + default: + BWN_ERRPRINTF(mac->mac_sc, + "No 2GHz EPA gain table available for this device\n"); + return NULL; + } + } +} + +const int16_t *bwn_ntab_get_rf_pwr_offset_table(struct bwn_mac *mac) +{ + struct ieee80211com *ic = &mac->mac_sc->sc_ic; + struct bwn_phy *phy = &mac->mac_phy; + + if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { + switch (phy->rev) { + case 17: + if (phy->rf_rev == 14) + return bwn_ntab_rf_pwr_offset_2057_rev14_2g; + break; + case 16: + if (phy->rf_rev == 9) + return bwn_ntab_rf_pwr_offset_2057_rev9_2g; + break; + } + + BWN_ERRPRINTF(mac->mac_sc, + "No 2GHz RF power table available for this device\n"); + return NULL; + } else { + switch (phy->rev) { + case 16: + if (phy->rf_rev == 9) + return bwn_ntab_rf_pwr_offset_2057_rev9_5g; + break; + } + + BWN_ERRPRINTF(mac->mac_sc, + "No 5GHz RF power table available for this device\n"); + return NULL; + } +} + +struct bwn_nphy_gain_ctl_workaround_entry *bwn_nphy_get_gain_ctl_workaround_ent( + struct bwn_mac *mac, bool ghz5, bool ext_lna) +{ + struct ieee80211com *ic = &mac->mac_sc->sc_ic; + struct bwn_softc *sc = mac->mac_sc; + struct bwn_phy *phy = &mac->mac_phy; + struct bwn_nphy_gain_ctl_workaround_entry *e; + uint8_t phy_idx; + + if (!ghz5 && mac->mac_phy.rev >= 6 && mac->mac_phy.rf_rev == 11) + return &nphy_gain_ctl_wa_phy6_radio11_ghz2; + + KASSERT(mac->mac_phy.rev >= 3, + ("%s: called; too early phy rev (%d)\n", + __func__, mac->mac_phy.rev)); + if (mac->mac_phy.rev >= 6) + phy_idx = 3; + else if (mac->mac_phy.rev == 5) + phy_idx = 2; + else if (mac->mac_phy.rev == 4) + phy_idx = 1; + else + phy_idx = 0; + e = &nphy_gain_ctl_workaround[ghz5][phy_idx]; + + /* Some workarounds to the workarounds... */ + if (!ghz5) { + uint8_t tr_iso = siba_sprom_get_fem_2ghz_tr_iso(sc->sc_dev); + + if (tr_iso > 7) + tr_iso = 3; + + if (phy->rev >= 6) { + static const int gain_data[] = { 0x106a, 0x106c, 0x1074, + 0x107c, 0x007e, 0x107e, + 0x207e, 0x307e, }; + + e->cliplo_gain = gain_data[tr_iso]; + } else if (phy->rev == 5) { + static const int gain_data[] = { 0x0062, 0x0064, 0x006a, + 0x106a, 0x106c, 0x1074, + 0x107c, 0x207c, }; + + e->cliplo_gain = gain_data[tr_iso]; + } + + if (phy->rev >= 5 && ext_lna) { + e->rfseq_init[0] &= ~0x4000; + e->rfseq_init[1] &= ~0x4000; + e->rfseq_init[2] &= ~0x4000; + e->rfseq_init[3] &= ~0x4000; + e->init_gain &= ~0x4000; + } + } else { + if (phy->rev >= 6) { + /* XXX 40MHz HT only? No static-40MHz? */ + if (phy->rf_rev == 11 && + IEEE80211_IS_CHAN_HT40(ic->ic_curchan)) + e->crsminu = 0x2d; + } else if (phy->rev == 4 && ext_lna) { + e->rfseq_init[0] &= ~0x4000; + e->rfseq_init[1] &= ~0x4000; + e->rfseq_init[2] &= ~0x4000; + e->rfseq_init[3] &= ~0x4000; + e->init_gain &= ~0x4000; + e->rfseq_init[0] |= 0x1000; + e->rfseq_init[1] |= 0x1000; + e->rfseq_init[2] |= 0x1000; + e->rfseq_init[3] |= 0x1000; + e->init_gain |= 0x1000; + } + } + + return e; +} + +const struct bwn_nphy_rf_control_override_rev7 * +bwn_nphy_get_rf_ctl_over_rev7(struct bwn_mac *mac, uint16_t field, + uint8_t override) +{ + const struct bwn_nphy_rf_control_override_rev7 *e; + uint8_t size, i; + + switch (override) { + case 0: + e = tbl_rf_control_override_rev7_over0; + size = nitems(tbl_rf_control_override_rev7_over0); + break; + case 1: + e = tbl_rf_control_override_rev7_over1; + size = nitems(tbl_rf_control_override_rev7_over1); + break; + case 2: + e = tbl_rf_control_override_rev7_over2; + size = nitems(tbl_rf_control_override_rev7_over2); + break; + default: + BWN_ERRPRINTF(mac->mac_sc, "Invalid override value %d\n", override); + return NULL; + } + + for (i = 0; i < size; i++) { + if (e[i].field == field) + return &e[i]; + } + + return NULL; +} diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h new file mode 100644 index 0000000..523cc3c --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h @@ -0,0 +1,249 @@ +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +/* + * $FreeBSD$ + */ + +#ifndef __IF_BWN_TABLES_NPHY_H__ +#define __IF_BWN_TABLES_NPHY_H__ + +struct bwn_phy_n_sfo_cfg { + uint16_t phy_bw1a; + uint16_t phy_bw2; + uint16_t phy_bw3; + uint16_t phy_bw4; + uint16_t phy_bw5; + uint16_t phy_bw6; +}; + +struct bwn_mac; + +struct bwn_nphy_txiqcal_ladder { + uint8_t percent; + uint8_t g_env; +}; + +struct bwn_nphy_rf_control_override_rev2 { + uint8_t addr0; + uint8_t addr1; + uint16_t bmask; + uint8_t shift; +}; + +struct bwn_nphy_rf_control_override_rev3 { + uint16_t val_mask; + uint8_t val_shift; + uint8_t en_addr0; + uint8_t val_addr0; + uint8_t en_addr1; + uint8_t val_addr1; +}; + +struct bwn_nphy_rf_control_override_rev7 { + uint16_t field; + uint16_t val_addr_core0; + uint16_t val_addr_core1; + uint16_t val_mask; + uint8_t val_shift; +}; + +struct bwn_nphy_gain_ctl_workaround_entry { + int8_t lna1_gain[4]; + int8_t lna2_gain[4]; + uint8_t gain_db[10]; + uint8_t gain_bits[10]; + + uint16_t init_gain; + uint16_t rfseq_init[4]; + + uint16_t cliphi_gain; + uint16_t clipmd_gain; + uint16_t cliplo_gain; + + uint16_t crsmin; + uint16_t crsminl; + uint16_t crsminu; + + uint16_t nbclip; + uint16_t wlclip; +}; + +/* Get entry with workaround values for gain ctl. Does not return NULL. */ +struct bwn_nphy_gain_ctl_workaround_entry *bwn_nphy_get_gain_ctl_workaround_ent( + struct bwn_mac *mac, bool ghz5, bool ext_lna); + + +/* The N-PHY tables. */ +#define BWN_NTAB_TYPEMASK 0xF0000000 +#define BWN_NTAB_8BIT 0x10000000 +#define BWN_NTAB_16BIT 0x20000000 +#define BWN_NTAB_32BIT 0x30000000 +#define BWN_NTAB8(table, offset) (((table) << 10) | (offset) | BWN_NTAB_8BIT) +#define BWN_NTAB16(table, offset) (((table) << 10) | (offset) | BWN_NTAB_16BIT) +#define BWN_NTAB32(table, offset) (((table) << 10) | (offset) | BWN_NTAB_32BIT) + +/* Static N-PHY tables */ +#define BWN_NTAB_FRAMESTRUCT BWN_NTAB32(0x0A, 0x000) /* Frame Struct Table */ +#define BWN_NTAB_FRAMESTRUCT_SIZE 832 +#define BWN_NTAB_FRAMELT BWN_NTAB8 (0x18, 0x000) /* Frame Lookup Table */ +#define BWN_NTAB_FRAMELT_SIZE 32 +#define BWN_NTAB_TMAP BWN_NTAB32(0x0C, 0x000) /* T Map Table */ +#define BWN_NTAB_TMAP_SIZE 448 +#define BWN_NTAB_TDTRN BWN_NTAB32(0x0E, 0x000) /* TDTRN Table */ +#define BWN_NTAB_TDTRN_SIZE 704 +#define BWN_NTAB_INTLEVEL BWN_NTAB32(0x0D, 0x000) /* Int Level Table */ +#define BWN_NTAB_INTLEVEL_SIZE 7 +#define BWN_NTAB_PILOT BWN_NTAB16(0x0B, 0x000) /* Pilot Table */ +#define BWN_NTAB_PILOT_SIZE 88 +#define BWN_NTAB_PILOTLT BWN_NTAB32(0x14, 0x000) /* Pilot Lookup Table */ +#define BWN_NTAB_PILOTLT_SIZE 6 +#define BWN_NTAB_TDI20A0 BWN_NTAB32(0x13, 0x080) /* TDI Table 20 Antenna 0 */ +#define BWN_NTAB_TDI20A0_SIZE 55 +#define BWN_NTAB_TDI20A1 BWN_NTAB32(0x13, 0x100) /* TDI Table 20 Antenna 1 */ +#define BWN_NTAB_TDI20A1_SIZE 55 +#define BWN_NTAB_TDI40A0 BWN_NTAB32(0x13, 0x280) /* TDI Table 40 Antenna 0 */ +#define BWN_NTAB_TDI40A0_SIZE 110 +#define BWN_NTAB_TDI40A1 BWN_NTAB32(0x13, 0x300) /* TDI Table 40 Antenna 1 */ +#define BWN_NTAB_TDI40A1_SIZE 110 +#define BWN_NTAB_BDI BWN_NTAB16(0x15, 0x000) /* BDI Table */ +#define BWN_NTAB_BDI_SIZE 6 +#define BWN_NTAB_CHANEST BWN_NTAB32(0x16, 0x000) /* Channel Estimate Table */ +#define BWN_NTAB_CHANEST_SIZE 96 +#define BWN_NTAB_MCS BWN_NTAB8 (0x12, 0x000) /* MCS Table */ +#define BWN_NTAB_MCS_SIZE 128 + +/* Volatile N-PHY tables */ +#define BWN_NTAB_NOISEVAR10 BWN_NTAB32(0x10, 0x000) /* Noise Var Table 10 */ +#define BWN_NTAB_NOISEVAR10_SIZE 256 +#define BWN_NTAB_NOISEVAR11 BWN_NTAB32(0x10, 0x080) /* Noise Var Table 11 */ +#define BWN_NTAB_NOISEVAR11_SIZE 256 +#define BWN_NTAB_C0_ESTPLT BWN_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */ +#define BWN_NTAB_C0_ESTPLT_SIZE 64 +#define BWN_NTAB_C0_ADJPLT BWN_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */ +#define BWN_NTAB_C0_ADJPLT_SIZE 128 +#define BWN_NTAB_C0_GAINCTL BWN_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */ +#define BWN_NTAB_C0_GAINCTL_SIZE 128 +#define BWN_NTAB_C0_IQLT BWN_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */ +#define BWN_NTAB_C0_IQLT_SIZE 128 +#define BWN_NTAB_C0_LOFEEDTH BWN_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */ +#define BWN_NTAB_C0_LOFEEDTH_SIZE 128 +#define BWN_NTAB_C1_ESTPLT BWN_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */ +#define BWN_NTAB_C1_ESTPLT_SIZE 64 +#define BWN_NTAB_C1_ADJPLT BWN_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */ +#define BWN_NTAB_C1_ADJPLT_SIZE 128 +#define BWN_NTAB_C1_GAINCTL BWN_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */ +#define BWN_NTAB_C1_GAINCTL_SIZE 128 +#define BWN_NTAB_C1_IQLT BWN_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */ +#define BWN_NTAB_C1_IQLT_SIZE 128 +#define BWN_NTAB_C1_LOFEEDTH BWN_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */ +#define BWN_NTAB_C1_LOFEEDTH_SIZE 128 + +/* Volatile N-PHY tables, PHY revision >= 3 */ +#define BWN_NTAB_ANT_SW_CTL_R3 BWN_NTAB16( 9, 0) /* antenna software control */ + +/* Static N-PHY tables, PHY revision >= 3 */ +#define BWN_NTAB_FRAMESTRUCT_R3 BWN_NTAB32(10, 0) /* frame struct */ +#define BWN_NTAB_PILOT_R3 BWN_NTAB16(11, 0) /* pilot */ +#define BWN_NTAB_TMAP_R3 BWN_NTAB32(12, 0) /* TM AP */ +#define BWN_NTAB_INTLEVEL_R3 BWN_NTAB32(13, 0) /* INT LV */ +#define BWN_NTAB_TDTRN_R3 BWN_NTAB32(14, 0) /* TD TRN */ +#define BWN_NTAB_NOISEVAR_R3 BWN_NTAB32(16, 0) /* noise variance */ +#define BWN_NTAB_MCS_R3 BWN_NTAB16(18, 0) /* MCS */ +#define BWN_NTAB_TDI20A0_R3 BWN_NTAB32(19, 128) /* TDI 20/0 */ +#define BWN_NTAB_TDI20A1_R3 BWN_NTAB32(19, 256) /* TDI 20/1 */ +#define BWN_NTAB_TDI40A0_R3 BWN_NTAB32(19, 640) /* TDI 40/0 */ +#define BWN_NTAB_TDI40A1_R3 BWN_NTAB32(19, 768) /* TDI 40/1 */ +#define BWN_NTAB_PILOTLT_R3 BWN_NTAB32(20, 0) /* PLT lookup */ +#define BWN_NTAB_CHANEST_R3 BWN_NTAB32(22, 0) /* channel estimate */ +#define BWN_NTAB_FRAMELT_R3 BWN_NTAB8(24, 0) /* frame lookup */ +#define BWN_NTAB_C0_ESTPLT_R3 BWN_NTAB8(26, 0) /* estimated power lookup 0 */ +#define BWN_NTAB_C0_ADJPLT_R3 BWN_NTAB8(26, 64) /* adjusted power lookup 0 */ +#define BWN_NTAB_C0_GAINCTL_R3 BWN_NTAB32(26, 192) /* gain control lookup 0 */ +#define BWN_NTAB_C0_IQLT_R3 BWN_NTAB32(26, 320) /* I/Q lookup 0 */ +#define BWN_NTAB_C0_LOFEEDTH_R3 BWN_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */ +#define BWN_NTAB_C0_PAPD_COMP_R3 BWN_NTAB16(26, 576) +#define BWN_NTAB_C1_ESTPLT_R3 BWN_NTAB8(27, 0) /* estimated power lookup 1 */ +#define BWN_NTAB_C1_ADJPLT_R3 BWN_NTAB8(27, 64) /* adjusted power lookup 1 */ +#define BWN_NTAB_C1_GAINCTL_R3 BWN_NTAB32(27, 192) /* gain control lookup 1 */ +#define BWN_NTAB_C1_IQLT_R3 BWN_NTAB32(27, 320) /* I/Q lookup 1 */ +#define BWN_NTAB_C1_LOFEEDTH_R3 BWN_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */ +#define BWN_NTAB_C1_PAPD_COMP_R3 BWN_NTAB16(27, 576) + +/* Static N-PHY tables, PHY revision >= 7 */ +#define BWN_NTAB_TMAP_R7 BWN_NTAB32(12, 0) /* TM AP */ +#define BWN_NTAB_NOISEVAR_R7 BWN_NTAB32(16, 0) /* noise variance */ + +#define BWN_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18 +#define BWN_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18 +#define BWN_NTAB_TX_IQLO_CAL_IQIMB_LADDER_40_SIZE 18 +#define BWN_NTAB_TX_IQLO_CAL_IQIMB_LADDER_20_SIZE 18 +#define BWN_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3 11 +#define BWN_NTAB_TX_IQLO_CAL_STARTCOEFS 9 +#define BWN_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3 12 +#define BWN_NTAB_TX_IQLO_CAL_CMDS_RECAL 10 +#define BWN_NTAB_TX_IQLO_CAL_CMDS_FULLCAL 10 +#define BWN_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3 12 + +uint32_t bwn_ntab_read(struct bwn_mac *mac, uint32_t offset); +void bwn_ntab_read_bulk(struct bwn_mac *mac, uint32_t offset, + unsigned int nr_elements, void *_data); +void bwn_ntab_write(struct bwn_mac *mac, uint32_t offset, uint32_t value); +void bwn_ntab_write_bulk(struct bwn_mac *mac, uint32_t offset, + unsigned int nr_elements, const void *_data); + +void bwn_nphy_tables_init(struct bwn_mac *mac); + +const uint32_t *bwn_nphy_get_tx_gain_table(struct bwn_mac *mac); + +const int16_t *bwn_ntab_get_rf_pwr_offset_table(struct bwn_mac *mac); + +extern const int8_t bwn_ntab_papd_pga_gain_delta_ipa_2g[]; + +extern const uint16_t tbl_iqcal_gainparams[2][9][8]; +extern const struct bwn_nphy_txiqcal_ladder ladder_lo[]; +extern const struct bwn_nphy_txiqcal_ladder ladder_iq[]; +extern const uint16_t loscale[]; + +extern const uint16_t tbl_tx_iqlo_cal_loft_ladder_40[]; +extern const uint16_t tbl_tx_iqlo_cal_loft_ladder_20[]; +extern const uint16_t tbl_tx_iqlo_cal_iqimb_ladder_40[]; +extern const uint16_t tbl_tx_iqlo_cal_iqimb_ladder_20[]; +extern const uint16_t tbl_tx_iqlo_cal_startcoefs_nphyrev3[]; +extern const uint16_t tbl_tx_iqlo_cal_startcoefs[]; +extern const uint16_t tbl_tx_iqlo_cal_cmds_recal_nphyrev3[]; +extern const uint16_t tbl_tx_iqlo_cal_cmds_recal[]; +extern const uint16_t tbl_tx_iqlo_cal_cmds_fullcal[]; +extern const uint16_t tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[]; +extern const int16_t tbl_tx_filter_coef_rev4[7][15]; + +extern const struct bwn_nphy_rf_control_override_rev2 + tbl_rf_control_override_rev2[]; +extern const struct bwn_nphy_rf_control_override_rev3 + tbl_rf_control_override_rev3[]; +const struct bwn_nphy_rf_control_override_rev7 *bwn_nphy_get_rf_ctl_over_rev7( + struct bwn_mac *mac, uint16_t field, uint8_t override); + +#endif /* __IF_BWN_PHY_TABLES_N_H__ */ diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2055.c b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2055.c new file mode 100644 index 0000000..f22ed1a --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2055.c @@ -0,0 +1,1389 @@ +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * The Broadcom Wireless LAN controller driver. + */ + +#include "opt_wlan.h" +#include "opt_bwn.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/endian.h> +#include <sys/errno.h> +#include <sys/firmware.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/socket.h> +#include <sys/sockio.h> + +#include <net/ethernet.h> +#include <net/if.h> +#include <net/if_var.h> +#include <net/if_arp.h> +#include <net/if_dl.h> +#include <net/if_llc.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <dev/pci/pcivar.h> +#include <dev/pci/pcireg.h> +#include <dev/siba/siba_ids.h> +#include <dev/siba/sibareg.h> +#include <dev/siba/sibavar.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> +#include <net80211/ieee80211_regdomain.h> +#include <net80211/ieee80211_phy.h> +#include <net80211/ieee80211_ratectl.h> + +#include <dev/bwn/if_bwnreg.h> +#include <dev/bwn/if_bwnvar.h> +#include <dev/bwn/if_bwn_debug.h> + +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h> +#include <gnu/dev/bwn/phy_n/if_bwn_radio_2055.h> + +struct b2055_inittab_entry { + /* Value to write if we use the 5GHz band. */ + uint16_t ghz5; + /* Value to write if we use the 2.4GHz band. */ + uint16_t ghz2; + /* Flags */ + uint8_t flags; +#define B2055_INITTAB_ENTRY_OK 0x01 +#define B2055_INITTAB_UPLOAD 0x02 +}; +#define UPLOAD .flags = B2055_INITTAB_ENTRY_OK | B2055_INITTAB_UPLOAD +#define NOUPLOAD .flags = B2055_INITTAB_ENTRY_OK + +static const struct b2055_inittab_entry b2055_inittab [] = { + [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, }, + [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, }, + [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, }, + [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, }, + [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, }, + [B2055_C2_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2055_C1_SP_LPFBWSEL] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2055_C2_SP_LPFBWSEL] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2055_C1_SP_TXGC1] = { .ghz5 = 0x004F, .ghz2 = 0x004F, UPLOAD, }, + [B2055_C1_SP_TXGC2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, + [B2055_C2_SP_TXGC1] = { .ghz5 = 0x004F, .ghz2 = 0x004F, UPLOAD, }, + [B2055_C2_SP_TXGC2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, + [B2055_MASTER1] = { .ghz5 = 0x00D0, .ghz2 = 0x00D0, NOUPLOAD, }, + [B2055_MASTER2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2055_PD_LGEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_PD_PLLTS] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, + [B2055_C1_PD_LGBUF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C1_PD_TX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C1_PD_RXTX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C1_PD_RSSIMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_PD_LGBUF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_PD_TX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_PD_RXTX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_PD_RSSIMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_PWRDET_LGEN] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, }, + [B2055_C1_PWRDET_LGBUF] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, }, + [B2055_C1_PWRDET_RXTX] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, }, + [B2055_C2_PWRDET_LGBUF] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, }, + [B2055_C2_PWRDET_RXTX] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, }, + [B2055_RRCCAL_CS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_RRCCAL_NOPTSEL] = { .ghz5 = 0x002C, .ghz2 = 0x002C, NOUPLOAD, }, + [B2055_CAL_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_CAL_COUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_CAL_COUT2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_CAL_CVARCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_CAL_RVARCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_CAL_LPOCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_CAL_TS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_CAL_RCCALRTS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_CAL_RCALRTS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_PADDRV] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, }, + [B2055_XOCTL1] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, + [B2055_XOCTL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_XOREGUL] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, + [B2055_XOMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_PLL_LFC1] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, + [B2055_PLL_CALVTH] = { .ghz5 = 0x0087, .ghz2 = 0x0087, NOUPLOAD, }, + [B2055_PLL_LFC2] = { .ghz5 = 0x0009, .ghz2 = 0x0009, NOUPLOAD, }, + [B2055_PLL_REF] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2055_PLL_LFR1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2055_PLL_PFDCP] = { .ghz5 = 0x0018, .ghz2 = 0x0018, UPLOAD, }, + [B2055_PLL_IDAC_CPOPAMP] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_PLL_CPREG] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, + [B2055_PLL_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_RF_PLLMOD0] = { .ghz5 = 0x009E, .ghz2 = 0x009E, NOUPLOAD, }, + [B2055_RF_PLLMOD1] = { .ghz5 = 0x0009, .ghz2 = 0x0009, NOUPLOAD, }, + [B2055_RF_MMDIDAC1] = { .ghz5 = 0x00C8, .ghz2 = 0x00C8, UPLOAD, }, + [B2055_RF_MMDIDAC0] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_RF_MMDSP] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_VCO_CAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_VCO_CAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_VCO_CAL3] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2055_VCO_CAL4] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2055_VCO_CAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, + [B2055_VCO_CAL6] = { .ghz5 = 0x003E, .ghz2 = 0x003E, NOUPLOAD, }, + [B2055_VCO_CAL7] = { .ghz5 = 0x003E, .ghz2 = 0x003E, NOUPLOAD, }, + [B2055_VCO_CAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2055_VCO_CAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2055_VCO_CAL10] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2055_VCO_CAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2055_VCO_CAL12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_VCO_CAL13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_VCO_CAL14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_VCO_CAL15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_VCO_CAL16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_VCO_KVCO] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2055_VCO_CAPTAIL] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2055_VCO_IDACVCO] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_VCO_REG] = { .ghz5 = 0x0084, .ghz2 = 0x0084, UPLOAD, }, + [B2055_PLL_RFVTH] = { .ghz5 = 0x00C3, .ghz2 = 0x00C3, NOUPLOAD, }, + [B2055_LGBUF_CENBUF] = { .ghz5 = 0x008F, .ghz2 = 0x008F, NOUPLOAD, }, + [B2055_LGEN_TUNE1] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, }, + [B2055_LGEN_TUNE2] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, }, + [B2055_LGEN_IDAC1] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_LGEN_IDAC2] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_LGEN_BIASC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_LGEN_BIASIDAC] = { .ghz5 = 0x00CC, .ghz2 = 0x00CC, NOUPLOAD, }, + [B2055_LGEN_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_LGEN_DIV] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, }, + [B2055_LGEN_SPARE2] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, }, + [B2055_C1_LGBUF_ATUNE] = { .ghz5 = 0x00F8, .ghz2 = 0x00F8, NOUPLOAD, }, + [B2055_C1_LGBUF_GTUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_C1_LGBUF_DIV] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_C1_LGBUF_AIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0008, UPLOAD, }, + [B2055_C1_LGBUF_GIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_C1_LGBUF_IDACFO] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C1_LGBUF_SPARE] = { .ghz5 = 0x0001, .ghz2 = 0x0001, UPLOAD, }, + [B2055_C1_RX_RFSPC1] = { .ghz5 = 0x008A, .ghz2 = 0x008A, NOUPLOAD, }, + [B2055_C1_RX_RFR1] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2055_C1_RX_RFR2] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, + [B2055_C1_RX_RFRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_C1_RX_BB_BLCMP] = { .ghz5 = 0x00A0, .ghz2 = 0x00A0, NOUPLOAD, }, + [B2055_C1_RX_BB_LPF] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, + [B2055_C1_RX_BB_MIDACHP] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, }, + [B2055_C1_RX_BB_VGA1IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C1_RX_BB_VGA2IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C1_RX_BB_VGA3IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C1_RX_BB_BUFOCTL] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C1_RX_BB_RCCALCTL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2055_C1_RX_BB_RSSICTL1] = { .ghz5 = 0x006A, .ghz2 = 0x006A, UPLOAD, }, + [B2055_C1_RX_BB_RSSICTL2] = { .ghz5 = 0x00AB, .ghz2 = 0x00AB, UPLOAD, }, + [B2055_C1_RX_BB_RSSICTL3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, UPLOAD, }, + [B2055_C1_RX_BB_RSSICTL4] = { .ghz5 = 0x00C1, .ghz2 = 0x00C1, UPLOAD, }, + [B2055_C1_RX_BB_RSSICTL5] = { .ghz5 = 0x00AA, .ghz2 = 0x00AA, UPLOAD, }, + [B2055_C1_RX_BB_REG] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, }, + [B2055_C1_RX_BB_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C1_RX_TXBBRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_C1_TX_RF_SPGA] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2055_C1_TX_RF_SPAD] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2055_C1_TX_RF_CNTPGA1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2055_C1_TX_RF_CNTPAD1] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2055_C1_TX_RF_PGAIDAC] = { .ghz5 = 0x0097, .ghz2 = 0x0097, UPLOAD, }, + [B2055_C1_TX_PGAPADTN] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2055_C1_TX_PADIDAC1] = { .ghz5 = 0x0014, .ghz2 = 0x0014, UPLOAD, }, + [B2055_C1_TX_PADIDAC2] = { .ghz5 = 0x0033, .ghz2 = 0x0033, NOUPLOAD, }, + [B2055_C1_TX_MXBGTRIM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_C1_TX_RF_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_C1_TX_RF_PADTSSI1] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, }, + [B2055_C1_TX_RF_PADTSSI2] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, + [B2055_C1_TX_RF_SPARE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, }, + [B2055_C1_TX_RF_IQCAL1] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C1_TX_RF_IQCAL2] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, }, + [B2055_C1_TXBB_RCCAL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2055_C1_TXBB_LPF1] = { .ghz5 = 0x0028, .ghz2 = 0x0028, NOUPLOAD, }, + [B2055_C1_TX_VOSCNCL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C1_TX_LPF_MXGMIDAC] = { .ghz5 = 0x004A, .ghz2 = 0x004A, NOUPLOAD, }, + [B2055_C1_TX_BB_MXGM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_LGBUF_ATUNE] = { .ghz5 = 0x00F8, .ghz2 = 0x00F8, NOUPLOAD, }, + [B2055_C2_LGBUF_GTUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_C2_LGBUF_DIV] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_C2_LGBUF_AIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0008, UPLOAD, }, + [B2055_C2_LGBUF_GIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_C2_LGBUF_IDACFO] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_LGBUF_SPARE] = { .ghz5 = 0x0001, .ghz2 = 0x0001, UPLOAD, }, + [B2055_C2_RX_RFSPC1] = { .ghz5 = 0x008A, .ghz2 = 0x008A, NOUPLOAD, }, + [B2055_C2_RX_RFR1] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2055_C2_RX_RFR2] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, + [B2055_C2_RX_RFRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_C2_RX_BB_BLCMP] = { .ghz5 = 0x00A0, .ghz2 = 0x00A0, NOUPLOAD, }, + [B2055_C2_RX_BB_LPF] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, + [B2055_C2_RX_BB_MIDACHP] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, }, + [B2055_C2_RX_BB_VGA1IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C2_RX_BB_VGA2IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C2_RX_BB_VGA3IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C2_RX_BB_BUFOCTL] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C2_RX_BB_RCCALCTL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2055_C2_RX_BB_RSSICTL1] = { .ghz5 = 0x006A, .ghz2 = 0x006A, UPLOAD, }, + [B2055_C2_RX_BB_RSSICTL2] = { .ghz5 = 0x00AB, .ghz2 = 0x00AB, UPLOAD, }, + [B2055_C2_RX_BB_RSSICTL3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, UPLOAD, }, + [B2055_C2_RX_BB_RSSICTL4] = { .ghz5 = 0x00C1, .ghz2 = 0x00C1, UPLOAD, }, + [B2055_C2_RX_BB_RSSICTL5] = { .ghz5 = 0x00AA, .ghz2 = 0x00AA, UPLOAD, }, + [B2055_C2_RX_BB_REG] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, }, + [B2055_C2_RX_BB_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_RX_TXBBRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_C2_TX_RF_SPGA] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2055_C2_TX_RF_SPAD] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2055_C2_TX_RF_CNTPGA1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2055_C2_TX_RF_CNTPAD1] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2055_C2_TX_RF_PGAIDAC] = { .ghz5 = 0x0097, .ghz2 = 0x0097, UPLOAD, }, + [B2055_C2_TX_PGAPADTN] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2055_C2_TX_PADIDAC1] = { .ghz5 = 0x0014, .ghz2 = 0x0014, UPLOAD, }, + [B2055_C2_TX_PADIDAC2] = { .ghz5 = 0x0033, .ghz2 = 0x0033, NOUPLOAD, }, + [B2055_C2_TX_MXBGTRIM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2055_C2_TX_RF_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2055_C2_TX_RF_PADTSSI1] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, }, + [B2055_C2_TX_RF_PADTSSI2] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, + [B2055_C2_TX_RF_SPARE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, }, + [B2055_C2_TX_RF_IQCAL1] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, + [B2055_C2_TX_RF_IQCAL2] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, }, + [B2055_C2_TXBB_RCCAL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2055_C2_TXBB_LPF1] = { .ghz5 = 0x0028, .ghz2 = 0x0028, NOUPLOAD, }, + [B2055_C2_TX_VOSCNCL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_TX_LPF_MXGMIDAC] = { .ghz5 = 0x004A, .ghz2 = 0x004A, NOUPLOAD, }, + [B2055_C2_TX_BB_MXGM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_PRG_GCHP21] = { .ghz5 = 0x0071, .ghz2 = 0x0071, NOUPLOAD, }, + [B2055_PRG_GCHP22] = { .ghz5 = 0x0072, .ghz2 = 0x0072, NOUPLOAD, }, + [B2055_PRG_GCHP23] = { .ghz5 = 0x0073, .ghz2 = 0x0073, NOUPLOAD, }, + [B2055_PRG_GCHP24] = { .ghz5 = 0x0074, .ghz2 = 0x0074, NOUPLOAD, }, + [B2055_PRG_GCHP25] = { .ghz5 = 0x0075, .ghz2 = 0x0075, NOUPLOAD, }, + [B2055_PRG_GCHP26] = { .ghz5 = 0x0076, .ghz2 = 0x0076, NOUPLOAD, }, + [B2055_PRG_GCHP27] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2055_PRG_GCHP28] = { .ghz5 = 0x0078, .ghz2 = 0x0078, NOUPLOAD, }, + [B2055_PRG_GCHP29] = { .ghz5 = 0x0079, .ghz2 = 0x0079, NOUPLOAD, }, + [B2055_PRG_GCHP30] = { .ghz5 = 0x007A, .ghz2 = 0x007A, NOUPLOAD, }, + [0xC7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xC8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xC9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xCA] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xCB] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xCC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C1_LNA_GAINBST] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xCE] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [0xCF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xD0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xD1] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2055_C1_B0NB_RSSIVCM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [0xD3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xD4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xD5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C1_GENSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xD7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xD8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_LNA_GAINBST] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xDA] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [0xDB] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xDC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xDD] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2055_C2_B0NB_RSSIVCM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [0xDF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xE0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [0xE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2055_C2_GENSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +#define RADIOREGS(r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, \ + r12, r13, r14, r15, r16, r17, r18, r19, r20, r21) \ + .radio_pll_ref = r0, \ + .radio_rf_pllmod0 = r1, \ + .radio_rf_pllmod1 = r2, \ + .radio_vco_captail = r3, \ + .radio_vco_cal1 = r4, \ + .radio_vco_cal2 = r5, \ + .radio_pll_lfc1 = r6, \ + .radio_pll_lfr1 = r7, \ + .radio_pll_lfc2 = r8, \ + .radio_lgbuf_cenbuf = r9, \ + .radio_lgen_tune1 = r10, \ + .radio_lgen_tune2 = r11, \ + .radio_c1_lgbuf_atune = r12, \ + .radio_c1_lgbuf_gtune = r13, \ + .radio_c1_rx_rfr1 = r14, \ + .radio_c1_tx_pgapadtn = r15, \ + .radio_c1_tx_mxbgtrim = r16, \ + .radio_c2_lgbuf_atune = r17, \ + .radio_c2_lgbuf_gtune = r18, \ + .radio_c2_rx_rfr1 = r19, \ + .radio_c2_tx_pgapadtn = r20, \ + .radio_c2_tx_mxbgtrim = r21 + +#define PHYREGS(r0, r1, r2, r3, r4, r5) \ + .phy_regs.phy_bw1a = r0, \ + .phy_regs.phy_bw2 = r1, \ + .phy_regs.phy_bw3 = r2, \ + .phy_regs.phy_bw4 = r3, \ + .phy_regs.phy_bw5 = r4, \ + .phy_regs.phy_bw6 = r5 + +static const struct bwn_nphy_channeltab_entry_rev2 bwn_nphy_channeltab_rev2[] = { + { .channel = 184, + .freq = 4920, /* MHz */ + .unk2 = 3280, + RADIOREGS(0x71, 0xEC, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07B4, 0x07B0, 0x07AC, 0x0214, 0x0215, 0x0216), + }, + { .channel = 186, + .freq = 4930, /* MHz */ + .unk2 = 3287, + RADIOREGS(0x71, 0xED, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07B8, 0x07B4, 0x07B0, 0x0213, 0x0214, 0x0215), + }, + { .channel = 188, + .freq = 4940, /* MHz */ + .unk2 = 3293, + RADIOREGS(0x71, 0xEE, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07BC, 0x07B8, 0x07B4, 0x0212, 0x0213, 0x0214), + }, + { .channel = 190, + .freq = 4950, /* MHz */ + .unk2 = 3300, + RADIOREGS(0x71, 0xEF, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07C0, 0x07BC, 0x07B8, 0x0211, 0x0212, 0x0213), + }, + { .channel = 192, + .freq = 4960, /* MHz */ + .unk2 = 3307, + RADIOREGS(0x71, 0xF0, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07C4, 0x07C0, 0x07BC, 0x020F, 0x0211, 0x0212), + }, + { .channel = 194, + .freq = 4970, /* MHz */ + .unk2 = 3313, + RADIOREGS(0x71, 0xF1, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07C8, 0x07C4, 0x07C0, 0x020E, 0x020F, 0x0211), + }, + { .channel = 196, + .freq = 4980, /* MHz */ + .unk2 = 3320, + RADIOREGS(0x71, 0xF2, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07CC, 0x07C8, 0x07C4, 0x020D, 0x020E, 0x020F), + }, + { .channel = 198, + .freq = 4990, /* MHz */ + .unk2 = 3327, + RADIOREGS(0x71, 0xF3, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07D0, 0x07CC, 0x07C8, 0x020C, 0x020D, 0x020E), + }, + { .channel = 200, + .freq = 5000, /* MHz */ + .unk2 = 3333, + RADIOREGS(0x71, 0xF4, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07D4, 0x07D0, 0x07CC, 0x020B, 0x020C, 0x020D), + }, + { .channel = 202, + .freq = 5010, /* MHz */ + .unk2 = 3340, + RADIOREGS(0x71, 0xF5, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07D8, 0x07D4, 0x07D0, 0x020A, 0x020B, 0x020C), + }, + { .channel = 204, + .freq = 5020, /* MHz */ + .unk2 = 3347, + RADIOREGS(0x71, 0xF6, 0x01, 0x0E, 0xF7, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07DC, 0x07D8, 0x07D4, 0x0209, 0x020A, 0x020B), + }, + { .channel = 206, + .freq = 5030, /* MHz */ + .unk2 = 3353, + RADIOREGS(0x71, 0xF7, 0x01, 0x0E, 0xF7, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07E0, 0x07DC, 0x07D8, 0x0208, 0x0209, 0x020A), + }, + { .channel = 208, + .freq = 5040, /* MHz */ + .unk2 = 3360, + RADIOREGS(0x71, 0xF8, 0x01, 0x0D, 0xEF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07E4, 0x07E0, 0x07DC, 0x0207, 0x0208, 0x0209), + }, + { .channel = 210, + .freq = 5050, /* MHz */ + .unk2 = 3367, + RADIOREGS(0x71, 0xF9, 0x01, 0x0D, 0xEF, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, + 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), + PHYREGS(0x07E8, 0x07E4, 0x07E0, 0x0206, 0x0207, 0x0208), + }, + { .channel = 212, + .freq = 5060, /* MHz */ + .unk2 = 3373, + RADIOREGS(0x71, 0xFA, 0x01, 0x0D, 0xE6, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, + 0x8E, 0xFF, 0x00, 0x0E, 0x0F, 0x8E), + PHYREGS(0x07EC, 0x07E8, 0x07E4, 0x0205, 0x0206, 0x0207), + }, + { .channel = 214, + .freq = 5070, /* MHz */ + .unk2 = 3380, + RADIOREGS(0x71, 0xFB, 0x01, 0x0D, 0xE6, 0x01, 0x04, 0x0A, + 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, + 0x8E, 0xFF, 0x00, 0x0E, 0x0F, 0x8E), + PHYREGS(0x07F0, 0x07EC, 0x07E8, 0x0204, 0x0205, 0x0206), + }, + { .channel = 216, + .freq = 5080, /* MHz */ + .unk2 = 3387, + RADIOREGS(0x71, 0xFC, 0x01, 0x0D, 0xDE, 0x01, 0x04, 0x0A, + 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, + 0x8D, 0xEE, 0x00, 0x0E, 0x0F, 0x8D), + PHYREGS(0x07F4, 0x07F0, 0x07EC, 0x0203, 0x0204, 0x0205), + }, + { .channel = 218, + .freq = 5090, /* MHz */ + .unk2 = 3393, + RADIOREGS(0x71, 0xFD, 0x01, 0x0D, 0xDE, 0x01, 0x04, 0x0A, + 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, + 0x8D, 0xEE, 0x00, 0x0E, 0x0F, 0x8D), + PHYREGS(0x07F8, 0x07F4, 0x07F0, 0x0202, 0x0203, 0x0204), + }, + { .channel = 220, + .freq = 5100, /* MHz */ + .unk2 = 3400, + RADIOREGS(0x71, 0xFE, 0x01, 0x0C, 0xD6, 0x01, 0x04, 0x0A, + 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, + 0x8D, 0xEE, 0x00, 0x0D, 0x0F, 0x8D), + PHYREGS(0x07FC, 0x07F8, 0x07F4, 0x0201, 0x0202, 0x0203), + }, + { .channel = 222, + .freq = 5110, /* MHz */ + .unk2 = 3407, + RADIOREGS(0x71, 0xFF, 0x01, 0x0C, 0xD6, 0x01, 0x04, 0x0A, + 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, + 0x8D, 0xEE, 0x00, 0x0D, 0x0F, 0x8D), + PHYREGS(0x0800, 0x07FC, 0x07F8, 0x0200, 0x0201, 0x0202), + }, + { .channel = 224, + .freq = 5120, /* MHz */ + .unk2 = 3413, + RADIOREGS(0x71, 0x00, 0x02, 0x0C, 0xCE, 0x01, 0x04, 0x0A, + 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, + 0x8C, 0xDD, 0x00, 0x0D, 0x0F, 0x8C), + PHYREGS(0x0804, 0x0800, 0x07FC, 0x01FF, 0x0200, 0x0201), + }, + { .channel = 226, + .freq = 5130, /* MHz */ + .unk2 = 3420, + RADIOREGS(0x71, 0x01, 0x02, 0x0C, 0xCE, 0x01, 0x04, 0x0A, + 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, + 0x8C, 0xDD, 0x00, 0x0D, 0x0F, 0x8C), + PHYREGS(0x0808, 0x0804, 0x0800, 0x01FE, 0x01FF, 0x0200), + }, + { .channel = 228, + .freq = 5140, /* MHz */ + .unk2 = 3427, + RADIOREGS(0x71, 0x02, 0x02, 0x0C, 0xC6, 0x01, 0x04, 0x0A, + 0x00, 0x8D, 0x99, 0x99, 0xDD, 0x00, 0x0C, 0x0E, + 0x8B, 0xDD, 0x00, 0x0C, 0x0E, 0x8B), + PHYREGS(0x080C, 0x0808, 0x0804, 0x01FD, 0x01FE, 0x01FF), + }, + { .channel = 32, + .freq = 5160, /* MHz */ + .unk2 = 3440, + RADIOREGS(0x71, 0x04, 0x02, 0x0B, 0xBE, 0x01, 0x04, 0x0A, + 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, + 0x8A, 0xCC, 0x00, 0x0B, 0x0D, 0x8A), + PHYREGS(0x0814, 0x0810, 0x080C, 0x01FB, 0x01FC, 0x01FD), + }, + { .channel = 34, + .freq = 5170, /* MHz */ + .unk2 = 3447, + RADIOREGS(0x71, 0x05, 0x02, 0x0B, 0xBE, 0x01, 0x04, 0x0A, + 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, + 0x8A, 0xCC, 0x00, 0x0B, 0x0D, 0x8A), + PHYREGS(0x0818, 0x0814, 0x0810, 0x01FA, 0x01FB, 0x01FC), + }, + { .channel = 36, + .freq = 5180, /* MHz */ + .unk2 = 3453, + RADIOREGS(0x71, 0x06, 0x02, 0x0B, 0xB6, 0x01, 0x04, 0x0A, + 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, + 0x89, 0xCC, 0x00, 0x0B, 0x0C, 0x89), + PHYREGS(0x081C, 0x0818, 0x0814, 0x01F9, 0x01FA, 0x01FB), + }, + { .channel = 38, + .freq = 5190, /* MHz */ + .unk2 = 3460, + RADIOREGS(0x71, 0x07, 0x02, 0x0B, 0xB6, 0x01, 0x04, 0x0A, + 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, + 0x89, 0xCC, 0x00, 0x0B, 0x0C, 0x89), + PHYREGS(0x0820, 0x081C, 0x0818, 0x01F8, 0x01F9, 0x01FA), + }, + { .channel = 40, + .freq = 5200, /* MHz */ + .unk2 = 3467, + RADIOREGS(0x71, 0x08, 0x02, 0x0B, 0xAF, 0x01, 0x04, 0x0A, + 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, + 0x89, 0xBB, 0x00, 0x0A, 0x0B, 0x89), + PHYREGS(0x0824, 0x0820, 0x081C, 0x01F7, 0x01F8, 0x01F9), + }, + { .channel = 42, + .freq = 5210, /* MHz */ + .unk2 = 3473, + RADIOREGS(0x71, 0x09, 0x02, 0x0B, 0xAF, 0x01, 0x04, 0x0A, + 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, + 0x89, 0xBB, 0x00, 0x0A, 0x0B, 0x89), + PHYREGS(0x0828, 0x0824, 0x0820, 0x01F6, 0x01F7, 0x01F8), + }, + { .channel = 44, + .freq = 5220, /* MHz */ + .unk2 = 3480, + RADIOREGS(0x71, 0x0A, 0x02, 0x0A, 0xA7, 0x01, 0x04, 0x0A, + 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A, + 0x88, 0xBB, 0x00, 0x09, 0x0A, 0x88), + PHYREGS(0x082C, 0x0828, 0x0824, 0x01F5, 0x01F6, 0x01F7), + }, + { .channel = 46, + .freq = 5230, /* MHz */ + .unk2 = 3487, + RADIOREGS(0x71, 0x0B, 0x02, 0x0A, 0xA7, 0x01, 0x04, 0x0A, + 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A, + 0x88, 0xBB, 0x00, 0x09, 0x0A, 0x88), + PHYREGS(0x0830, 0x082C, 0x0828, 0x01F4, 0x01F5, 0x01F6), + }, + { .channel = 48, + .freq = 5240, /* MHz */ + .unk2 = 3493, + RADIOREGS(0x71, 0x0C, 0x02, 0x0A, 0xA0, 0x01, 0x04, 0x0A, + 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A, + 0x87, 0xAA, 0x00, 0x09, 0x0A, 0x87), + PHYREGS(0x0834, 0x0830, 0x082C, 0x01F3, 0x01F4, 0x01F5), + }, + { .channel = 50, + .freq = 5250, /* MHz */ + .unk2 = 3500, + RADIOREGS(0x71, 0x0D, 0x02, 0x0A, 0xA0, 0x01, 0x04, 0x0A, + 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A, + 0x87, 0xAA, 0x00, 0x09, 0x0A, 0x87), + PHYREGS(0x0838, 0x0834, 0x0830, 0x01F2, 0x01F3, 0x01F4), + }, + { .channel = 52, + .freq = 5260, /* MHz */ + .unk2 = 3507, + RADIOREGS(0x71, 0x0E, 0x02, 0x0A, 0x98, 0x01, 0x04, 0x0A, + 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09, + 0x87, 0xAA, 0x00, 0x08, 0x09, 0x87), + PHYREGS(0x083C, 0x0838, 0x0834, 0x01F1, 0x01F2, 0x01F3), + }, + { .channel = 54, + .freq = 5270, /* MHz */ + .unk2 = 3513, + RADIOREGS(0x71, 0x0F, 0x02, 0x0A, 0x98, 0x01, 0x04, 0x0A, + 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09, + 0x87, 0xAA, 0x00, 0x08, 0x09, 0x87), + PHYREGS(0x0840, 0x083C, 0x0838, 0x01F0, 0x01F1, 0x01F2), + }, + { .channel = 56, + .freq = 5280, /* MHz */ + .unk2 = 3520, + RADIOREGS(0x71, 0x10, 0x02, 0x09, 0x91, 0x01, 0x04, 0x0A, + 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08, + 0x86, 0x99, 0x00, 0x08, 0x08, 0x86), + PHYREGS(0x0844, 0x0840, 0x083C, 0x01F0, 0x01F0, 0x01F1), + }, + { .channel = 58, + .freq = 5290, /* MHz */ + .unk2 = 3527, + RADIOREGS(0x71, 0x11, 0x02, 0x09, 0x91, 0x01, 0x04, 0x0A, + 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08, + 0x86, 0x99, 0x00, 0x08, 0x08, 0x86), + PHYREGS(0x0848, 0x0844, 0x0840, 0x01EF, 0x01F0, 0x01F0), + }, + { .channel = 60, + .freq = 5300, /* MHz */ + .unk2 = 3533, + RADIOREGS(0x71, 0x12, 0x02, 0x09, 0x8A, 0x01, 0x04, 0x0A, + 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07, + 0x85, 0x99, 0x00, 0x08, 0x07, 0x85), + PHYREGS(0x084C, 0x0848, 0x0844, 0x01EE, 0x01EF, 0x01F0), + }, + { .channel = 62, + .freq = 5310, /* MHz */ + .unk2 = 3540, + RADIOREGS(0x71, 0x13, 0x02, 0x09, 0x8A, 0x01, 0x04, 0x0A, + 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07, + 0x85, 0x99, 0x00, 0x08, 0x07, 0x85), + PHYREGS(0x0850, 0x084C, 0x0848, 0x01ED, 0x01EE, 0x01EF), + }, + { .channel = 64, + .freq = 5320, /* MHz */ + .unk2 = 3547, + RADIOREGS(0x71, 0x14, 0x02, 0x09, 0x83, 0x01, 0x04, 0x0A, + 0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07, + 0x84, 0x88, 0x00, 0x07, 0x07, 0x84), + PHYREGS(0x0854, 0x0850, 0x084C, 0x01EC, 0x01ED, 0x01EE), + }, + { .channel = 66, + .freq = 5330, /* MHz */ + .unk2 = 3553, + RADIOREGS(0x71, 0x15, 0x02, 0x09, 0x83, 0x01, 0x04, 0x0A, + 0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07, + 0x84, 0x88, 0x00, 0x07, 0x07, 0x84), + PHYREGS(0x0858, 0x0854, 0x0850, 0x01EB, 0x01EC, 0x01ED), + }, + { .channel = 68, + .freq = 5340, /* MHz */ + .unk2 = 3560, + RADIOREGS(0x71, 0x16, 0x02, 0x08, 0x7C, 0x01, 0x04, 0x0A, + 0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06, + 0x84, 0x88, 0x00, 0x07, 0x06, 0x84), + PHYREGS(0x085C, 0x0858, 0x0854, 0x01EA, 0x01EB, 0x01EC), + }, + { .channel = 70, + .freq = 5350, /* MHz */ + .unk2 = 3567, + RADIOREGS(0x71, 0x17, 0x02, 0x08, 0x7C, 0x01, 0x04, 0x0A, + 0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06, + 0x84, 0x88, 0x00, 0x07, 0x06, 0x84), + PHYREGS(0x0860, 0x085C, 0x0858, 0x01E9, 0x01EA, 0x01EB), + }, + { .channel = 72, + .freq = 5360, /* MHz */ + .unk2 = 3573, + RADIOREGS(0x71, 0x18, 0x02, 0x08, 0x75, 0x01, 0x04, 0x0A, + 0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05, + 0x83, 0x77, 0x00, 0x06, 0x05, 0x83), + PHYREGS(0x0864, 0x0860, 0x085C, 0x01E8, 0x01E9, 0x01EA), + }, + { .channel = 74, + .freq = 5370, /* MHz */ + .unk2 = 3580, + RADIOREGS(0x71, 0x19, 0x02, 0x08, 0x75, 0x01, 0x04, 0x0A, + 0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05, + 0x83, 0x77, 0x00, 0x06, 0x05, 0x83), + PHYREGS(0x0868, 0x0864, 0x0860, 0x01E7, 0x01E8, 0x01E9), + }, + { .channel = 76, + .freq = 5380, /* MHz */ + .unk2 = 3587, + RADIOREGS(0x71, 0x1A, 0x02, 0x08, 0x6E, 0x01, 0x04, 0x0A, + 0x00, 0x87, 0x33, 0x33, 0x77, 0x00, 0x06, 0x04, + 0x82, 0x77, 0x00, 0x06, 0x04, 0x82), + PHYREGS(0x086C, 0x0868, 0x0864, 0x01E6, 0x01E7, 0x01E8), + }, + { .channel = 78, + .freq = 5390, /* MHz */ + .unk2 = 3593, + RADIOREGS(0x71, 0x1B, 0x02, 0x08, 0x6E, 0x01, 0x04, 0x0A, + 0x00, 0x87, 0x33, 0x33, 0x77, 0x00, 0x06, 0x04, + 0x82, 0x77, 0x00, 0x06, 0x04, 0x82), + PHYREGS(0x0870, 0x086C, 0x0868, 0x01E5, 0x01E6, 0x01E7), + }, + { .channel = 80, + .freq = 5400, /* MHz */ + .unk2 = 3600, + RADIOREGS(0x71, 0x1C, 0x02, 0x07, 0x67, 0x01, 0x04, 0x0A, + 0x00, 0x86, 0x33, 0x33, 0x66, 0x00, 0x05, 0x04, + 0x81, 0x66, 0x00, 0x05, 0x04, 0x81), + PHYREGS(0x0874, 0x0870, 0x086C, 0x01E5, 0x01E5, 0x01E6), + }, + { .channel = 82, + .freq = 5410, /* MHz */ + .unk2 = 3607, + RADIOREGS(0x71, 0x1D, 0x02, 0x07, 0x67, 0x01, 0x04, 0x0A, + 0x00, 0x86, 0x33, 0x33, 0x66, 0x00, 0x05, 0x04, + 0x81, 0x66, 0x00, 0x05, 0x04, 0x81), + PHYREGS(0x0878, 0x0874, 0x0870, 0x01E4, 0x01E5, 0x01E5), + }, + { .channel = 84, + .freq = 5420, /* MHz */ + .unk2 = 3613, + RADIOREGS(0x71, 0x1E, 0x02, 0x07, 0x61, 0x01, 0x04, 0x0A, + 0x00, 0x86, 0x22, 0x22, 0x66, 0x00, 0x05, 0x03, + 0x80, 0x66, 0x00, 0x05, 0x03, 0x80), + PHYREGS(0x087C, 0x0878, 0x0874, 0x01E3, 0x01E4, 0x01E5), + }, + { .channel = 86, + .freq = 5430, /* MHz */ + .unk2 = 3620, + RADIOREGS(0x71, 0x1F, 0x02, 0x07, 0x61, 0x01, 0x04, 0x0A, + 0x00, 0x86, 0x22, 0x22, 0x66, 0x00, 0x05, 0x03, + 0x80, 0x66, 0x00, 0x05, 0x03, 0x80), + PHYREGS(0x0880, 0x087C, 0x0878, 0x01E2, 0x01E3, 0x01E4), + }, + { .channel = 88, + .freq = 5440, /* MHz */ + .unk2 = 3627, + RADIOREGS(0x71, 0x20, 0x02, 0x07, 0x5A, 0x01, 0x04, 0x0A, + 0x00, 0x85, 0x22, 0x22, 0x55, 0x00, 0x04, 0x02, + 0x80, 0x55, 0x00, 0x04, 0x02, 0x80), + PHYREGS(0x0884, 0x0880, 0x087C, 0x01E1, 0x01E2, 0x01E3), + }, + { .channel = 90, + .freq = 5450, /* MHz */ + .unk2 = 3633, + RADIOREGS(0x71, 0x21, 0x02, 0x07, 0x5A, 0x01, 0x04, 0x0A, + 0x00, 0x85, 0x22, 0x22, 0x55, 0x00, 0x04, 0x02, + 0x80, 0x55, 0x00, 0x04, 0x02, 0x80), + PHYREGS(0x0888, 0x0884, 0x0880, 0x01E0, 0x01E1, 0x01E2), + }, + { .channel = 92, + .freq = 5460, /* MHz */ + .unk2 = 3640, + RADIOREGS(0x71, 0x22, 0x02, 0x06, 0x53, 0x01, 0x04, 0x0A, + 0x00, 0x85, 0x11, 0x11, 0x55, 0x00, 0x04, 0x01, + 0x80, 0x55, 0x00, 0x04, 0x01, 0x80), + PHYREGS(0x088C, 0x0888, 0x0884, 0x01DF, 0x01E0, 0x01E1), + }, + { .channel = 94, + .freq = 5470, /* MHz */ + .unk2 = 3647, + RADIOREGS(0x71, 0x23, 0x02, 0x06, 0x53, 0x01, 0x04, 0x0A, + 0x00, 0x85, 0x11, 0x11, 0x55, 0x00, 0x04, 0x01, + 0x80, 0x55, 0x00, 0x04, 0x01, 0x80), + PHYREGS(0x0890, 0x088C, 0x0888, 0x01DE, 0x01DF, 0x01E0), + }, + { .channel = 96, + .freq = 5480, /* MHz */ + .unk2 = 3653, + RADIOREGS(0x71, 0x24, 0x02, 0x06, 0x4D, 0x01, 0x04, 0x0A, + 0x00, 0x84, 0x11, 0x11, 0x44, 0x00, 0x03, 0x00, + 0x80, 0x44, 0x00, 0x03, 0x00, 0x80), + PHYREGS(0x0894, 0x0890, 0x088C, 0x01DD, 0x01DE, 0x01DF), + }, + { .channel = 98, + .freq = 5490, /* MHz */ + .unk2 = 3660, + RADIOREGS(0x71, 0x25, 0x02, 0x06, 0x4D, 0x01, 0x04, 0x0A, + 0x00, 0x84, 0x11, 0x11, 0x44, 0x00, 0x03, 0x00, + 0x80, 0x44, 0x00, 0x03, 0x00, 0x80), + PHYREGS(0x0898, 0x0894, 0x0890, 0x01DD, 0x01DD, 0x01DE), + }, + { .channel = 100, + .freq = 5500, /* MHz */ + .unk2 = 3667, + RADIOREGS(0x71, 0x26, 0x02, 0x06, 0x47, 0x01, 0x04, 0x0A, + 0x00, 0x84, 0x00, 0x00, 0x44, 0x00, 0x03, 0x00, + 0x80, 0x44, 0x00, 0x03, 0x00, 0x80), + PHYREGS(0x089C, 0x0898, 0x0894, 0x01DC, 0x01DD, 0x01DD), + }, + { .channel = 102, + .freq = 5510, /* MHz */ + .unk2 = 3673, + RADIOREGS(0x71, 0x27, 0x02, 0x06, 0x47, 0x01, 0x04, 0x0A, + 0x00, 0x84, 0x00, 0x00, 0x44, 0x00, 0x03, 0x00, + 0x80, 0x44, 0x00, 0x03, 0x00, 0x80), + PHYREGS(0x08A0, 0x089C, 0x0898, 0x01DB, 0x01DC, 0x01DD), + }, + { .channel = 104, + .freq = 5520, /* MHz */ + .unk2 = 3680, + RADIOREGS(0x71, 0x28, 0x02, 0x05, 0x40, 0x01, 0x04, 0x0A, + 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, + 0x80, 0x33, 0x00, 0x02, 0x00, 0x80), + PHYREGS(0x08A4, 0x08A0, 0x089C, 0x01DA, 0x01DB, 0x01DC), + }, + { .channel = 106, + .freq = 5530, /* MHz */ + .unk2 = 3687, + RADIOREGS(0x71, 0x29, 0x02, 0x05, 0x40, 0x01, 0x04, 0x0A, + 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, + 0x80, 0x33, 0x00, 0x02, 0x00, 0x80), + PHYREGS(0x08A8, 0x08A4, 0x08A0, 0x01D9, 0x01DA, 0x01DB), + }, + { .channel = 108, + .freq = 5540, /* MHz */ + .unk2 = 3693, + RADIOREGS(0x71, 0x2A, 0x02, 0x05, 0x3A, 0x01, 0x04, 0x0A, + 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, + 0x80, 0x33, 0x00, 0x02, 0x00, 0x80), + PHYREGS(0x08AC, 0x08A8, 0x08A4, 0x01D8, 0x01D9, 0x01DA), + }, + { .channel = 110, + .freq = 5550, /* MHz */ + .unk2 = 3700, + RADIOREGS(0x71, 0x2B, 0x02, 0x05, 0x3A, 0x01, 0x04, 0x0A, + 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, + 0x80, 0x33, 0x00, 0x02, 0x00, 0x80), + PHYREGS(0x08B0, 0x08AC, 0x08A8, 0x01D7, 0x01D8, 0x01D9), + }, + { .channel = 112, + .freq = 5560, /* MHz */ + .unk2 = 3707, + RADIOREGS(0x71, 0x2C, 0x02, 0x05, 0x34, 0x01, 0x04, 0x0A, + 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00, + 0x80, 0x22, 0x00, 0x01, 0x00, 0x80), + PHYREGS(0x08B4, 0x08B0, 0x08AC, 0x01D7, 0x01D7, 0x01D8), + }, + { .channel = 114, + .freq = 5570, /* MHz */ + .unk2 = 3713, + RADIOREGS(0x71, 0x2D, 0x02, 0x05, 0x34, 0x01, 0x04, 0x0A, + 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00, + 0x80, 0x22, 0x00, 0x01, 0x00, 0x80), + PHYREGS(0x08B8, 0x08B4, 0x08B0, 0x01D6, 0x01D7, 0x01D7), + }, + { .channel = 116, + .freq = 5580, /* MHz */ + .unk2 = 3720, + RADIOREGS(0x71, 0x2E, 0x02, 0x04, 0x2E, 0x01, 0x04, 0x0A, + 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00, + 0x80, 0x22, 0x00, 0x01, 0x00, 0x80), + PHYREGS(0x08BC, 0x08B8, 0x08B4, 0x01D5, 0x01D6, 0x01D7), + }, + { .channel = 118, + .freq = 5590, /* MHz */ + .unk2 = 3727, + RADIOREGS(0x71, 0x2F, 0x02, 0x04, 0x2E, 0x01, 0x04, 0x0A, + 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00, + 0x80, 0x22, 0x00, 0x01, 0x00, 0x80), + PHYREGS(0x08C0, 0x08BC, 0x08B8, 0x01D4, 0x01D5, 0x01D6), + }, + { .channel = 120, + .freq = 5600, /* MHz */ + .unk2 = 3733, + RADIOREGS(0x71, 0x30, 0x02, 0x04, 0x28, 0x01, 0x04, 0x0A, + 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00, + 0x80, 0x11, 0x00, 0x01, 0x00, 0x80), + PHYREGS(0x08C4, 0x08C0, 0x08BC, 0x01D3, 0x01D4, 0x01D5), + }, + { .channel = 122, + .freq = 5610, /* MHz */ + .unk2 = 3740, + RADIOREGS(0x71, 0x31, 0x02, 0x04, 0x28, 0x01, 0x04, 0x0A, + 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00, + 0x80, 0x11, 0x00, 0x01, 0x00, 0x80), + PHYREGS(0x08C8, 0x08C4, 0x08C0, 0x01D2, 0x01D3, 0x01D4), + }, + { .channel = 124, + .freq = 5620, /* MHz */ + .unk2 = 3747, + RADIOREGS(0x71, 0x32, 0x02, 0x04, 0x21, 0x01, 0x04, 0x0A, + 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, + 0x80, 0x11, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08CC, 0x08C8, 0x08C4, 0x01D2, 0x01D2, 0x01D3), + }, + { .channel = 126, + .freq = 5630, /* MHz */ + .unk2 = 3753, + RADIOREGS(0x71, 0x33, 0x02, 0x04, 0x21, 0x01, 0x04, 0x0A, + 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, + 0x80, 0x11, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08D0, 0x08CC, 0x08C8, 0x01D1, 0x01D2, 0x01D2), + }, + { .channel = 128, + .freq = 5640, /* MHz */ + .unk2 = 3760, + RADIOREGS(0x71, 0x34, 0x02, 0x03, 0x1C, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08D4, 0x08D0, 0x08CC, 0x01D0, 0x01D1, 0x01D2), + }, + { .channel = 130, + .freq = 5650, /* MHz */ + .unk2 = 3767, + RADIOREGS(0x71, 0x35, 0x02, 0x03, 0x1C, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08D8, 0x08D4, 0x08D0, 0x01CF, 0x01D0, 0x01D1), + }, + { .channel = 132, + .freq = 5660, /* MHz */ + .unk2 = 3773, + RADIOREGS(0x71, 0x36, 0x02, 0x03, 0x16, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08DC, 0x08D8, 0x08D4, 0x01CE, 0x01CF, 0x01D0), + }, + { .channel = 134, + .freq = 5670, /* MHz */ + .unk2 = 3780, + RADIOREGS(0x71, 0x37, 0x02, 0x03, 0x16, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08E0, 0x08DC, 0x08D8, 0x01CE, 0x01CE, 0x01CF), + }, + { .channel = 136, + .freq = 5680, /* MHz */ + .unk2 = 3787, + RADIOREGS(0x71, 0x38, 0x02, 0x03, 0x10, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08E4, 0x08E0, 0x08DC, 0x01CD, 0x01CE, 0x01CE), + }, + { .channel = 138, + .freq = 5690, /* MHz */ + .unk2 = 3793, + RADIOREGS(0x71, 0x39, 0x02, 0x03, 0x10, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08E8, 0x08E4, 0x08E0, 0x01CC, 0x01CD, 0x01CE), + }, + { .channel = 140, + .freq = 5700, /* MHz */ + .unk2 = 3800, + RADIOREGS(0x71, 0x3A, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08EC, 0x08E8, 0x08E4, 0x01CB, 0x01CC, 0x01CD), + }, + { .channel = 142, + .freq = 5710, /* MHz */ + .unk2 = 3807, + RADIOREGS(0x71, 0x3B, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08F0, 0x08EC, 0x08E8, 0x01CA, 0x01CB, 0x01CC), + }, + { .channel = 144, + .freq = 5720, /* MHz */ + .unk2 = 3813, + RADIOREGS(0x71, 0x3C, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08F4, 0x08F0, 0x08EC, 0x01C9, 0x01CA, 0x01CB), + }, + { .channel = 145, + .freq = 5725, /* MHz */ + .unk2 = 3817, + RADIOREGS(0x72, 0x79, 0x04, 0x02, 0x03, 0x01, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08F6, 0x08F2, 0x08EE, 0x01C9, 0x01CA, 0x01CB), + }, + { .channel = 146, + .freq = 5730, /* MHz */ + .unk2 = 3820, + RADIOREGS(0x71, 0x3D, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08F8, 0x08F4, 0x08F0, 0x01C9, 0x01C9, 0x01CA), + }, + { .channel = 147, + .freq = 5735, /* MHz */ + .unk2 = 3823, + RADIOREGS(0x72, 0x7B, 0x04, 0x02, 0x03, 0x01, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08FA, 0x08F6, 0x08F2, 0x01C8, 0x01C9, 0x01CA), + }, + { .channel = 148, + .freq = 5740, /* MHz */ + .unk2 = 3827, + RADIOREGS(0x71, 0x3E, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08FC, 0x08F8, 0x08F4, 0x01C8, 0x01C9, 0x01C9), + }, + { .channel = 149, + .freq = 5745, /* MHz */ + .unk2 = 3830, + RADIOREGS(0x72, 0x7D, 0x04, 0x02, 0xFE, 0x00, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x08FE, 0x08FA, 0x08F6, 0x01C8, 0x01C8, 0x01C9), + }, + { .channel = 150, + .freq = 5750, /* MHz */ + .unk2 = 3833, + RADIOREGS(0x71, 0x3F, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0900, 0x08FC, 0x08F8, 0x01C7, 0x01C8, 0x01C9), + }, + { .channel = 151, + .freq = 5755, /* MHz */ + .unk2 = 3837, + RADIOREGS(0x72, 0x7F, 0x04, 0x02, 0xFE, 0x00, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0902, 0x08FE, 0x08FA, 0x01C7, 0x01C8, 0x01C8), + }, + { .channel = 152, + .freq = 5760, /* MHz */ + .unk2 = 3840, + RADIOREGS(0x71, 0x40, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0904, 0x0900, 0x08FC, 0x01C6, 0x01C7, 0x01C8), + }, + { .channel = 153, + .freq = 5765, /* MHz */ + .unk2 = 3843, + RADIOREGS(0x72, 0x81, 0x04, 0x02, 0xF8, 0x00, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0906, 0x0902, 0x08FE, 0x01C6, 0x01C7, 0x01C8), + }, + { .channel = 154, + .freq = 5770, /* MHz */ + .unk2 = 3847, + RADIOREGS(0x71, 0x41, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0908, 0x0904, 0x0900, 0x01C6, 0x01C6, 0x01C7), + }, + { .channel = 155, + .freq = 5775, /* MHz */ + .unk2 = 3850, + RADIOREGS(0x72, 0x83, 0x04, 0x02, 0xF8, 0x00, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x090A, 0x0906, 0x0902, 0x01C5, 0x01C6, 0x01C7), + }, + { .channel = 156, + .freq = 5780, /* MHz */ + .unk2 = 3853, + RADIOREGS(0x71, 0x42, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x090C, 0x0908, 0x0904, 0x01C5, 0x01C6, 0x01C6), + }, + { .channel = 157, + .freq = 5785, /* MHz */ + .unk2 = 3857, + RADIOREGS(0x72, 0x85, 0x04, 0x02, 0xF2, 0x00, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x090E, 0x090A, 0x0906, 0x01C4, 0x01C5, 0x01C6), + }, + { .channel = 158, + .freq = 5790, /* MHz */ + .unk2 = 3860, + RADIOREGS(0x71, 0x43, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0910, 0x090C, 0x0908, 0x01C4, 0x01C5, 0x01C6), + }, + { .channel = 159, + .freq = 5795, /* MHz */ + .unk2 = 3863, + RADIOREGS(0x72, 0x87, 0x04, 0x02, 0xF2, 0x00, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0912, 0x090E, 0x090A, 0x01C4, 0x01C4, 0x01C5), + }, + { .channel = 160, + .freq = 5800, /* MHz */ + .unk2 = 3867, + RADIOREGS(0x71, 0x44, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0914, 0x0910, 0x090C, 0x01C3, 0x01C4, 0x01C5), + }, + { .channel = 161, + .freq = 5805, /* MHz */ + .unk2 = 3870, + RADIOREGS(0x72, 0x89, 0x04, 0x01, 0xED, 0x00, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0916, 0x0912, 0x090E, 0x01C3, 0x01C4, 0x01C4), + }, + { .channel = 162, + .freq = 5810, /* MHz */ + .unk2 = 3873, + RADIOREGS(0x71, 0x45, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0918, 0x0914, 0x0910, 0x01C2, 0x01C3, 0x01C4), + }, + { .channel = 163, + .freq = 5815, /* MHz */ + .unk2 = 3877, + RADIOREGS(0x72, 0x8B, 0x04, 0x01, 0xED, 0x00, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x091A, 0x0916, 0x0912, 0x01C2, 0x01C3, 0x01C4), + }, + { .channel = 164, + .freq = 5820, /* MHz */ + .unk2 = 3880, + RADIOREGS(0x71, 0x46, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x091C, 0x0918, 0x0914, 0x01C2, 0x01C2, 0x01C3), + }, + { .channel = 165, + .freq = 5825, /* MHz */ + .unk2 = 3883, + RADIOREGS(0x72, 0x8D, 0x04, 0x01, 0xED, 0x00, 0x03, 0x14, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x091E, 0x091A, 0x0916, 0x01C1, 0x01C2, 0x01C3), + }, + { .channel = 166, + .freq = 5830, /* MHz */ + .unk2 = 3887, + RADIOREGS(0x71, 0x47, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0920, 0x091C, 0x0918, 0x01C1, 0x01C2, 0x01C2), + }, + { .channel = 168, + .freq = 5840, /* MHz */ + .unk2 = 3893, + RADIOREGS(0x71, 0x48, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0924, 0x0920, 0x091C, 0x01C0, 0x01C1, 0x01C2), + }, + { .channel = 170, + .freq = 5850, /* MHz */ + .unk2 = 3900, + RADIOREGS(0x71, 0x49, 0x02, 0x01, 0xE0, 0x00, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0928, 0x0924, 0x0920, 0x01BF, 0x01C0, 0x01C1), + }, + { .channel = 172, + .freq = 5860, /* MHz */ + .unk2 = 3907, + RADIOREGS(0x71, 0x4A, 0x02, 0x01, 0xDE, 0x00, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x092C, 0x0928, 0x0924, 0x01BF, 0x01BF, 0x01C0), + }, + { .channel = 174, + .freq = 5870, /* MHz */ + .unk2 = 3913, + RADIOREGS(0x71, 0x4B, 0x02, 0x00, 0xDB, 0x00, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0930, 0x092C, 0x0928, 0x01BE, 0x01BF, 0x01BF), + }, + { .channel = 176, + .freq = 5880, /* MHz */ + .unk2 = 3920, + RADIOREGS(0x71, 0x4C, 0x02, 0x00, 0xD8, 0x00, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0934, 0x0930, 0x092C, 0x01BD, 0x01BE, 0x01BF), + }, + { .channel = 178, + .freq = 5890, /* MHz */ + .unk2 = 3927, + RADIOREGS(0x71, 0x4D, 0x02, 0x00, 0xD6, 0x00, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0938, 0x0934, 0x0930, 0x01BC, 0x01BD, 0x01BE), + }, + { .channel = 180, + .freq = 5900, /* MHz */ + .unk2 = 3933, + RADIOREGS(0x71, 0x4E, 0x02, 0x00, 0xD3, 0x00, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x093C, 0x0938, 0x0934, 0x01BC, 0x01BC, 0x01BD), + }, + { .channel = 182, + .freq = 5910, /* MHz */ + .unk2 = 3940, + RADIOREGS(0x71, 0x4F, 0x02, 0x00, 0xD6, 0x00, 0x04, 0x0A, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), + PHYREGS(0x0940, 0x093C, 0x0938, 0x01BB, 0x01BC, 0x01BC), + }, + { .channel = 1, + .freq = 2412, /* MHz */ + .unk2 = 3216, + RADIOREGS(0x73, 0x6C, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0D, 0x0C, + 0x80, 0xFF, 0x88, 0x0D, 0x0C, 0x80), + PHYREGS(0x03C9, 0x03C5, 0x03C1, 0x043A, 0x043F, 0x0443), + }, + { .channel = 2, + .freq = 2417, /* MHz */ + .unk2 = 3223, + RADIOREGS(0x73, 0x71, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0B, + 0x80, 0xFF, 0x88, 0x0C, 0x0B, 0x80), + PHYREGS(0x03CB, 0x03C7, 0x03C3, 0x0438, 0x043D, 0x0441), + }, + { .channel = 3, + .freq = 2422, /* MHz */ + .unk2 = 3229, + RADIOREGS(0x73, 0x76, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, + 0x80, 0xFF, 0x88, 0x0C, 0x0A, 0x80), + PHYREGS(0x03CD, 0x03C9, 0x03C5, 0x0436, 0x043A, 0x043F), + }, + { .channel = 4, + .freq = 2427, /* MHz */ + .unk2 = 3236, + RADIOREGS(0x73, 0x7B, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, + 0x80, 0xFF, 0x88, 0x0C, 0x0A, 0x80), + PHYREGS(0x03CF, 0x03CB, 0x03C7, 0x0434, 0x0438, 0x043D), + }, + { .channel = 5, + .freq = 2432, /* MHz */ + .unk2 = 3243, + RADIOREGS(0x73, 0x80, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x09, + 0x80, 0xFF, 0x88, 0x0C, 0x09, 0x80), + PHYREGS(0x03D1, 0x03CD, 0x03C9, 0x0431, 0x0436, 0x043A), + }, + { .channel = 6, + .freq = 2437, /* MHz */ + .unk2 = 3249, + RADIOREGS(0x73, 0x85, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0B, 0x08, + 0x80, 0xFF, 0x88, 0x0B, 0x08, 0x80), + PHYREGS(0x03D3, 0x03CF, 0x03CB, 0x042F, 0x0434, 0x0438), + }, + { .channel = 7, + .freq = 2442, /* MHz */ + .unk2 = 3256, + RADIOREGS(0x73, 0x8A, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x07, + 0x80, 0xFF, 0x88, 0x0A, 0x07, 0x80), + PHYREGS(0x03D5, 0x03D1, 0x03CD, 0x042D, 0x0431, 0x0436), + }, + { .channel = 8, + .freq = 2447, /* MHz */ + .unk2 = 3263, + RADIOREGS(0x73, 0x8F, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x06, + 0x80, 0xFF, 0x88, 0x0A, 0x06, 0x80), + PHYREGS(0x03D7, 0x03D3, 0x03CF, 0x042B, 0x042F, 0x0434), + }, + { .channel = 9, + .freq = 2452, /* MHz */ + .unk2 = 3269, + RADIOREGS(0x73, 0x94, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x09, 0x06, + 0x80, 0xFF, 0x88, 0x09, 0x06, 0x80), + PHYREGS(0x03D9, 0x03D5, 0x03D1, 0x0429, 0x042D, 0x0431), + }, + { .channel = 10, + .freq = 2457, /* MHz */ + .unk2 = 3276, + RADIOREGS(0x73, 0x99, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x05, + 0x80, 0xFF, 0x88, 0x08, 0x05, 0x80), + PHYREGS(0x03DB, 0x03D7, 0x03D3, 0x0427, 0x042B, 0x042F), + }, + { .channel = 11, + .freq = 2462, /* MHz */ + .unk2 = 3283, + RADIOREGS(0x73, 0x9E, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x04, + 0x80, 0xFF, 0x88, 0x08, 0x04, 0x80), + PHYREGS(0x03DD, 0x03D9, 0x03D5, 0x0424, 0x0429, 0x042D), + }, + { .channel = 12, + .freq = 2467, /* MHz */ + .unk2 = 3289, + RADIOREGS(0x73, 0xA3, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x03, + 0x80, 0xFF, 0x88, 0x08, 0x03, 0x80), + PHYREGS(0x03DF, 0x03DB, 0x03D7, 0x0422, 0x0427, 0x042B), + }, + { .channel = 13, + .freq = 2472, /* MHz */ + .unk2 = 3296, + RADIOREGS(0x73, 0xA8, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x03, + 0x80, 0xFF, 0x88, 0x07, 0x03, 0x80), + PHYREGS(0x03E1, 0x03DD, 0x03D9, 0x0420, 0x0424, 0x0429), + }, + { .channel = 14, + .freq = 2484, /* MHz */ + .unk2 = 3312, + RADIOREGS(0x73, 0xB4, 0x09, 0x0F, 0xFF, 0x01, 0x07, 0x15, + 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x01, + 0x80, 0xFF, 0x88, 0x07, 0x01, 0x80), + PHYREGS(0x03E6, 0x03E2, 0x03DE, 0x041B, 0x041F, 0x0424), + }, +}; + +void b2055_upload_inittab(struct bwn_mac *mac, + bool ghz5, bool ignore_uploadflag) +{ + const struct b2055_inittab_entry *e; + unsigned int i, writes = 0; + uint16_t value; + + for (i = 0; i < nitems(b2055_inittab); i++) { + e = &(b2055_inittab[i]); + if (!(e->flags & B2055_INITTAB_ENTRY_OK)) + continue; + if ((e->flags & B2055_INITTAB_UPLOAD) || ignore_uploadflag) { + if (ghz5) + value = e->ghz5; + else + value = e->ghz2; + BWN_RF_WRITE(mac, i, value); + if (++writes % 4 == 0) + BWN_READ_4(mac, BWN_MACCTL); /* flush */ + } + } + /* One final flush */ + BWN_READ_4(mac, BWN_MACCTL); +} + +const struct bwn_nphy_channeltab_entry_rev2 * +bwn_nphy_get_chantabent_rev2(struct bwn_mac *mac, uint8_t channel) +{ + const struct bwn_nphy_channeltab_entry_rev2 *e; + unsigned int i; + + for (i = 0; i < nitems(bwn_nphy_channeltab_rev2); i++) { + e = &(bwn_nphy_channeltab_rev2[i]); + if (e->channel == channel) + return e; + } + + return NULL; +} diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2055.h b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2055.h new file mode 100644 index 0000000..a47e9c8 --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2055.h @@ -0,0 +1,285 @@ +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +/* + * $FreeBSD$ + */ + +#ifndef __IF_BWN_RADIO_2055_H__ +#define __IF_BWN_RADIO_2055_H__ + +#define B2055_GEN_SPARE 0x00 /* GEN spare */ +#define B2055_SP_PINPD 0x02 /* SP PIN PD */ +#define B2055_C1_SP_RSSI 0x03 /* SP RSSI Core 1 */ +#define B2055_C1_SP_PDMISC 0x04 /* SP PD MISC Core 1 */ +#define B2055_C2_SP_RSSI 0x05 /* SP RSSI Core 2 */ +#define B2055_C2_SP_PDMISC 0x06 /* SP PD MISC Core 2 */ +#define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */ +#define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */ +#define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */ +#define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */ +#define B2055_C1_SP_LPFBWSEL 0x0B /* SP LPF BW select Core 1 */ +#define B2055_C2_SP_LPFBWSEL 0x0C /* SP LPF BW select Core 2 */ +#define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */ +#define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */ +#define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */ +#define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */ +#define B2055_MASTER1 0x11 /* Master control 1 */ +#define B2055_MASTER2 0x12 /* Master control 2 */ +#define B2055_PD_LGEN 0x13 /* PD LGEN */ +#define B2055_PD_PLLTS 0x14 /* PD PLL TS */ +#define B2055_C1_PD_LGBUF 0x15 /* PD Core 1 LGBUF */ +#define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */ +#define B2055_C1_PD_RXTX 0x17 /* PD Core 1 RXTX */ +#define B2055_C1_PD_RSSIMISC 0x18 /* PD Core 1 RSSI MISC */ +#define B2055_C2_PD_LGBUF 0x19 /* PD Core 2 LGBUF */ +#define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */ +#define B2055_C2_PD_RXTX 0x1B /* PD Core 2 RXTX */ +#define B2055_C2_PD_RSSIMISC 0x1C /* PD Core 2 RSSI MISC */ +#define B2055_PWRDET_LGEN 0x1D /* PWRDET LGEN */ +#define B2055_C1_PWRDET_LGBUF 0x1E /* PWRDET LGBUF Core 1 */ +#define B2055_C1_PWRDET_RXTX 0x1F /* PWRDET RXTX Core 1 */ +#define B2055_C2_PWRDET_LGBUF 0x20 /* PWRDET LGBUF Core 2 */ +#define B2055_C2_PWRDET_RXTX 0x21 /* PWRDET RXTX Core 2 */ +#define B2055_RRCCAL_CS 0x22 /* RRCCAL Control spare */ +#define B2055_RRCCAL_NOPTSEL 0x23 /* RRCCAL N OPT SEL */ +#define B2055_CAL_MISC 0x24 /* CAL MISC */ +#define B2055_CAL_COUT 0x25 /* CAL Counter out */ +#define B2055_CAL_COUT2 0x26 /* CAL Counter out 2 */ +#define B2055_CAL_CVARCTL 0x27 /* CAL CVAR Control */ +#define B2055_CAL_RVARCTL 0x28 /* CAL RVAR Control */ +#define B2055_CAL_LPOCTL 0x29 /* CAL LPO Control */ +#define B2055_CAL_TS 0x2A /* CAL TS */ +#define B2055_CAL_RCCALRTS 0x2B /* CAL RCCAL READ TS */ +#define B2055_CAL_RCALRTS 0x2C /* CAL RCAL READ TS */ +#define B2055_PADDRV 0x2D /* PAD driver */ +#define B2055_XOCTL1 0x2E /* XO Control 1 */ +#define B2055_XOCTL2 0x2F /* XO Control 2 */ +#define B2055_XOREGUL 0x30 /* XO Regulator */ +#define B2055_XOMISC 0x31 /* XO misc */ +#define B2055_PLL_LFC1 0x32 /* PLL LF C1 */ +#define B2055_PLL_CALVTH 0x33 /* PLL CAL VTH */ +#define B2055_PLL_LFC2 0x34 /* PLL LF C2 */ +#define B2055_PLL_REF 0x35 /* PLL reference */ +#define B2055_PLL_LFR1 0x36 /* PLL LF R1 */ +#define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */ +#define B2055_PLL_IDAC_CPOPAMP 0x38 /* PLL IDAC CPOPAMP */ +#define B2055_PLL_CPREG 0x39 /* PLL CP Regulator */ +#define B2055_PLL_RCAL 0x3A /* PLL RCAL */ +#define B2055_RF_PLLMOD0 0x3B /* RF PLL MOD0 */ +#define B2055_RF_PLLMOD1 0x3C /* RF PLL MOD1 */ +#define B2055_RF_MMDIDAC1 0x3D /* RF MMD IDAC 1 */ +#define B2055_RF_MMDIDAC0 0x3E /* RF MMD IDAC 0 */ +#define B2055_RF_MMDSP 0x3F /* RF MMD spare */ +#define B2055_VCO_CAL1 0x40 /* VCO cal 1 */ +#define B2055_VCO_CAL2 0x41 /* VCO cal 2 */ +#define B2055_VCO_CAL3 0x42 /* VCO cal 3 */ +#define B2055_VCO_CAL4 0x43 /* VCO cal 4 */ +#define B2055_VCO_CAL5 0x44 /* VCO cal 5 */ +#define B2055_VCO_CAL6 0x45 /* VCO cal 6 */ +#define B2055_VCO_CAL7 0x46 /* VCO cal 7 */ +#define B2055_VCO_CAL8 0x47 /* VCO cal 8 */ +#define B2055_VCO_CAL9 0x48 /* VCO cal 9 */ +#define B2055_VCO_CAL10 0x49 /* VCO cal 10 */ +#define B2055_VCO_CAL11 0x4A /* VCO cal 11 */ +#define B2055_VCO_CAL12 0x4B /* VCO cal 12 */ +#define B2055_VCO_CAL13 0x4C /* VCO cal 13 */ +#define B2055_VCO_CAL14 0x4D /* VCO cal 14 */ +#define B2055_VCO_CAL15 0x4E /* VCO cal 15 */ +#define B2055_VCO_CAL16 0x4F /* VCO cal 16 */ +#define B2055_VCO_KVCO 0x50 /* VCO KVCO */ +#define B2055_VCO_CAPTAIL 0x51 /* VCO CAP TAIL */ +#define B2055_VCO_IDACVCO 0x52 /* VCO IDAC VCO */ +#define B2055_VCO_REG 0x53 /* VCO Regulator */ +#define B2055_PLL_RFVTH 0x54 /* PLL RF VTH */ +#define B2055_LGBUF_CENBUF 0x55 /* LGBUF CEN BUF */ +#define B2055_LGEN_TUNE1 0x56 /* LGEN tune 1 */ +#define B2055_LGEN_TUNE2 0x57 /* LGEN tune 2 */ +#define B2055_LGEN_IDAC1 0x58 /* LGEN IDAC 1 */ +#define B2055_LGEN_IDAC2 0x59 /* LGEN IDAC 2 */ +#define B2055_LGEN_BIASC 0x5A /* LGEN BIAS counter */ +#define B2055_LGEN_BIASIDAC 0x5B /* LGEN BIAS IDAC */ +#define B2055_LGEN_RCAL 0x5C /* LGEN RCAL */ +#define B2055_LGEN_DIV 0x5D /* LGEN div */ +#define B2055_LGEN_SPARE2 0x5E /* LGEN spare 2 */ +#define B2055_C1_LGBUF_ATUNE 0x5F /* Core 1 LGBUF A tune */ +#define B2055_C1_LGBUF_GTUNE 0x60 /* Core 1 LGBUF G tune */ +#define B2055_C1_LGBUF_DIV 0x61 /* Core 1 LGBUF div */ +#define B2055_C1_LGBUF_AIDAC 0x62 /* Core 1 LGBUF A IDAC */ +#define B2055_C1_LGBUF_GIDAC 0x63 /* Core 1 LGBUF G IDAC */ +#define B2055_C1_LGBUF_IDACFO 0x64 /* Core 1 LGBUF IDAC filter override */ +#define B2055_C1_LGBUF_SPARE 0x65 /* Core 1 LGBUF spare */ +#define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */ +#define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */ +#define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */ +#define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */ +#define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */ +#define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */ +#define B2055_C1_RX_BB_MIDACHP 0x6C /* Core 1 RX Baseband MIDAC High-pass */ +#define B2055_C1_RX_BB_VGA1IDAC 0x6D /* Core 1 RX Baseband VGA1 IDAC */ +#define B2055_C1_RX_BB_VGA2IDAC 0x6E /* Core 1 RX Baseband VGA2 IDAC */ +#define B2055_C1_RX_BB_VGA3IDAC 0x6F /* Core 1 RX Baseband VGA3 IDAC */ +#define B2055_C1_RX_BB_BUFOCTL 0x70 /* Core 1 RX Baseband BUFO Control */ +#define B2055_C1_RX_BB_RCCALCTL 0x71 /* Core 1 RX Baseband RCCAL Control */ +#define B2055_C1_RX_BB_RSSICTL1 0x72 /* Core 1 RX Baseband RSSI Control 1 */ +#define B2055_C1_RX_BB_RSSICTL2 0x73 /* Core 1 RX Baseband RSSI Control 2 */ +#define B2055_C1_RX_BB_RSSICTL3 0x74 /* Core 1 RX Baseband RSSI Control 3 */ +#define B2055_C1_RX_BB_RSSICTL4 0x75 /* Core 1 RX Baseband RSSI Control 4 */ +#define B2055_C1_RX_BB_RSSICTL5 0x76 /* Core 1 RX Baseband RSSI Control 5 */ +#define B2055_C1_RX_BB_REG 0x77 /* Core 1 RX Baseband Regulator */ +#define B2055_C1_RX_BB_SPARE1 0x78 /* Core 1 RX Baseband spare 1 */ +#define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */ +#define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */ +#define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */ +#define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */ +#define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */ +#define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */ +#define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */ +#define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */ +#define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */ +#define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */ +#define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */ +#define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */ +#define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */ +#define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */ +#define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */ +#define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */ +#define B2055_C1_TXBB_RCCAL 0x89 /* Core 1 TXBB RC CAL Control */ +#define B2055_C1_TXBB_LPF1 0x8A /* Core 1 TXBB LPF 1 */ +#define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */ +#define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */ +#define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */ +#define B2055_C2_LGBUF_ATUNE 0x8E /* Core 2 LGBUF A tune */ +#define B2055_C2_LGBUF_GTUNE 0x8F /* Core 2 LGBUF G tune */ +#define B2055_C2_LGBUF_DIV 0x90 /* Core 2 LGBUF div */ +#define B2055_C2_LGBUF_AIDAC 0x91 /* Core 2 LGBUF A IDAC */ +#define B2055_C2_LGBUF_GIDAC 0x92 /* Core 2 LGBUF G IDAC */ +#define B2055_C2_LGBUF_IDACFO 0x93 /* Core 2 LGBUF IDAC filter override */ +#define B2055_C2_LGBUF_SPARE 0x94 /* Core 2 LGBUF spare */ +#define B2055_C2_RX_RFSPC1 0x95 /* Core 2 RX RF SPC1 */ +#define B2055_C2_RX_RFR1 0x96 /* Core 2 RX RF reg 1 */ +#define B2055_C2_RX_RFR2 0x97 /* Core 2 RX RF reg 2 */ +#define B2055_C2_RX_RFRCAL 0x98 /* Core 2 RX RF RCAL */ +#define B2055_C2_RX_BB_BLCMP 0x99 /* Core 2 RX Baseband BUFI LPF CMP */ +#define B2055_C2_RX_BB_LPF 0x9A /* Core 2 RX Baseband LPF */ +#define B2055_C2_RX_BB_MIDACHP 0x9B /* Core 2 RX Baseband MIDAC High-pass */ +#define B2055_C2_RX_BB_VGA1IDAC 0x9C /* Core 2 RX Baseband VGA1 IDAC */ +#define B2055_C2_RX_BB_VGA2IDAC 0x9D /* Core 2 RX Baseband VGA2 IDAC */ +#define B2055_C2_RX_BB_VGA3IDAC 0x9E /* Core 2 RX Baseband VGA3 IDAC */ +#define B2055_C2_RX_BB_BUFOCTL 0x9F /* Core 2 RX Baseband BUFO Control */ +#define B2055_C2_RX_BB_RCCALCTL 0xA0 /* Core 2 RX Baseband RCCAL Control */ +#define B2055_C2_RX_BB_RSSICTL1 0xA1 /* Core 2 RX Baseband RSSI Control 1 */ +#define B2055_C2_RX_BB_RSSICTL2 0xA2 /* Core 2 RX Baseband RSSI Control 2 */ +#define B2055_C2_RX_BB_RSSICTL3 0xA3 /* Core 2 RX Baseband RSSI Control 3 */ +#define B2055_C2_RX_BB_RSSICTL4 0xA4 /* Core 2 RX Baseband RSSI Control 4 */ +#define B2055_C2_RX_BB_RSSICTL5 0xA5 /* Core 2 RX Baseband RSSI Control 5 */ +#define B2055_C2_RX_BB_REG 0xA6 /* Core 2 RX Baseband Regulator */ +#define B2055_C2_RX_BB_SPARE1 0xA7 /* Core 2 RX Baseband spare 1 */ +#define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */ +#define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */ +#define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */ +#define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */ +#define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */ +#define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */ +#define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */ +#define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */ +#define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */ +#define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */ +#define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */ +#define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */ +#define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */ +#define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */ +#define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */ +#define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */ +#define B2055_C2_TXBB_RCCAL 0xB8 /* Core 2 TXBB RC CAL Control */ +#define B2055_C2_TXBB_LPF1 0xB9 /* Core 2 TXBB LPF 1 */ +#define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */ +#define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */ +#define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */ +#define B2055_PRG_GCHP21 0xBD /* PRG GC HPVGA23 21 */ +#define B2055_PRG_GCHP22 0xBE /* PRG GC HPVGA23 22 */ +#define B2055_PRG_GCHP23 0xBF /* PRG GC HPVGA23 23 */ +#define B2055_PRG_GCHP24 0xC0 /* PRG GC HPVGA23 24 */ +#define B2055_PRG_GCHP25 0xC1 /* PRG GC HPVGA23 25 */ +#define B2055_PRG_GCHP26 0xC2 /* PRG GC HPVGA23 26 */ +#define B2055_PRG_GCHP27 0xC3 /* PRG GC HPVGA23 27 */ +#define B2055_PRG_GCHP28 0xC4 /* PRG GC HPVGA23 28 */ +#define B2055_PRG_GCHP29 0xC5 /* PRG GC HPVGA23 29 */ +#define B2055_PRG_GCHP30 0xC6 /* PRG GC HPVGA23 30 */ +#define B2055_C1_LNA_GAINBST 0xCD /* Core 1 LNA GAINBST */ +#define B2055_C1_B0NB_RSSIVCM 0xD2 /* Core 1 B0 narrow-band RSSI VCM */ +#define B2055_C1_GENSPARE2 0xD6 /* Core 1 GEN spare 2 */ +#define B2055_C2_LNA_GAINBST 0xD9 /* Core 2 LNA GAINBST */ +#define B2055_C2_B0NB_RSSIVCM 0xDE /* Core 2 B0 narrow-band RSSI VCM */ +#define B2055_C2_GENSPARE2 0xE2 /* Core 2 GEN spare 2 */ + +struct bwn_nphy_channeltab_entry_rev2 { + /* The channel number */ + uint8_t channel; + /* The channel frequency in MHz */ + uint16_t freq; + /* An unknown value */ + uint16_t unk2; + /* Radio register values on channelswitch */ + uint8_t radio_pll_ref; + uint8_t radio_rf_pllmod0; + uint8_t radio_rf_pllmod1; + uint8_t radio_vco_captail; + uint8_t radio_vco_cal1; + uint8_t radio_vco_cal2; + uint8_t radio_pll_lfc1; + uint8_t radio_pll_lfr1; + uint8_t radio_pll_lfc2; + uint8_t radio_lgbuf_cenbuf; + uint8_t radio_lgen_tune1; + uint8_t radio_lgen_tune2; + uint8_t radio_c1_lgbuf_atune; + uint8_t radio_c1_lgbuf_gtune; + uint8_t radio_c1_rx_rfr1; + uint8_t radio_c1_tx_pgapadtn; + uint8_t radio_c1_tx_mxbgtrim; + uint8_t radio_c2_lgbuf_atune; + uint8_t radio_c2_lgbuf_gtune; + uint8_t radio_c2_rx_rfr1; + uint8_t radio_c2_tx_pgapadtn; + uint8_t radio_c2_tx_mxbgtrim; + /* PHY register values on channelswitch */ + struct bwn_phy_n_sfo_cfg phy_regs; +}; + +/* Upload the default register value table. + * If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz + * table is uploaded. If "ignore_uploadflag" is true, we upload any value + * and ignore the "UPLOAD" flag. */ +void b2055_upload_inittab(struct bwn_mac *mac, + bool ghz5, bool ignore_uploadflag); + +/* Get the NPHY Channel Switch Table entry for a channel. + * Returns NULL on failure to find an entry. */ +extern const struct bwn_nphy_channeltab_entry_rev2 * + bwn_nphy_get_chantabent_rev2(struct bwn_mac *mac, + uint8_t channel); + +#endif /* __IF_BWN_RADIO_2055_H__ */ diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2056.c b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2056.c new file mode 100644 index 0000000..cbb6d91 --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2056.c @@ -0,0 +1,10378 @@ + +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * The Broadcom Wireless LAN controller driver. + */ + +#include "opt_wlan.h" +#include "opt_bwn.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/endian.h> +#include <sys/errno.h> +#include <sys/firmware.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/socket.h> +#include <sys/sockio.h> + +#include <net/ethernet.h> +#include <net/if.h> +#include <net/if_var.h> +#include <net/if_arp.h> +#include <net/if_dl.h> +#include <net/if_llc.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <dev/pci/pcivar.h> +#include <dev/pci/pcireg.h> +#include <dev/siba/siba_ids.h> +#include <dev/siba/sibareg.h> +#include <dev/siba/sibavar.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> +#include <net80211/ieee80211_regdomain.h> +#include <net80211/ieee80211_phy.h> +#include <net80211/ieee80211_ratectl.h> + +#include <dev/bwn/if_bwnreg.h> +#include <dev/bwn/if_bwnvar.h> +#include <dev/bwn/if_bwn_debug.h> + +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h> +#include <gnu/dev/bwn/phy_n/if_bwn_radio_2056.h> + +struct b2056_inittab_entry { + /* Value to write if we use the 5GHz band. */ + uint16_t ghz5; + /* Value to write if we use the 2.4GHz band. */ + uint16_t ghz2; + /* Flags */ + uint8_t flags; +}; +#define B2056_INITTAB_ENTRY_OK 0x01 +#define B2056_INITTAB_UPLOAD 0x02 +#define UPLOAD .flags = B2056_INITTAB_ENTRY_OK | B2056_INITTAB_UPLOAD +#define NOUPLOAD .flags = B2056_INITTAB_ENTRY_OK + +struct b2056_inittabs_pts { + const struct b2056_inittab_entry *syn; + unsigned int syn_length; + const struct b2056_inittab_entry *tx; + unsigned int tx_length; + const struct b2056_inittab_entry *rx; + unsigned int rx_length; +}; + +static const struct b2056_inittab_entry b2056_inittab_phy_rev3_syn[] = { + [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, + [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, + [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, + [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, + [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_phy_rev3_tx[] = { + [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, + [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_TX_PA_SPARE2] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x002d, .ghz2 = 0x002d, NOUPLOAD, }, + [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, + [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, + [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0074, .ghz2 = 0x0074, UPLOAD, }, + [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, + [B2056_TX_TXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_phy_rev3_rx[] = { + [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0099, .ghz2 = 0x0099, NOUPLOAD, }, + [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0044, .ghz2 = 0x0044, UPLOAD, }, + [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0099, .ghz2 = 0x0099, NOUPLOAD, }, + [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_RX_TIA_IMISC] = { .ghz5 = 0x0057, .ghz2 = 0x0057, NOUPLOAD, }, + [B2056_RX_TIA_QMISC] = { .ghz5 = 0x0057, .ghz2 = 0x0057, NOUPLOAD, }, + [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, + [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, + [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, + [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_phy_rev4_syn[] = { + [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, + [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, + [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, + [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, + [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_phy_rev4_tx[] = { + [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, + [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_TX_PA_SPARE2] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x002d, .ghz2 = 0x002d, NOUPLOAD, }, + [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, + [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, + [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0072, .ghz2 = 0x0072, UPLOAD, }, + [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, + [B2056_TX_TXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_phy_rev4_rx[] = { + [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0044, .ghz2 = 0x0044, UPLOAD, }, + [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x002f, .ghz2 = 0x002f, UPLOAD, }, + [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, + [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, + [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev5_syn[] = { + [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, + [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, + [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, + [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, + [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev5_tx[] = { + [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, + [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_TX_PA_SPARE2] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x002d, .ghz2 = 0x002d, NOUPLOAD, }, + [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, + [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, + [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, + [B2056_TX_TXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC0] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC1] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC2] = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, }, + [B2056_TX_GMBB_IDAC3] = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, }, + [B2056_TX_GMBB_IDAC4] = { .ghz5 = 0x0072, .ghz2 = 0x0072, UPLOAD, }, + [B2056_TX_GMBB_IDAC5] = { .ghz5 = 0x0073, .ghz2 = 0x0073, UPLOAD, }, + [B2056_TX_GMBB_IDAC6] = { .ghz5 = 0x0074, .ghz2 = 0x0074, UPLOAD, }, + [B2056_TX_GMBB_IDAC7] = { .ghz5 = 0x0075, .ghz2 = 0x0075, UPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev5_rx[] = { + [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, + [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, + [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, + [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, + [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev6_syn[] = { + [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, + [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_CP2] = { .ghz5 = 0x003f, .ghz2 = 0x003f, UPLOAD, }, + [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x002b, .ghz2 = 0x002b, UPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, + [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, + [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, + [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, + [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev6_tx[] = { + [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, + [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_TX_PA_SPARE2] = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, }, + [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, + [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, + [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, + [B2056_TX_TXSPARE1] = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, }, + [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC0] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC1] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC2] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC3] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC4] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC5] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC6] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC7] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev6_rx[] = { + [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, + [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, + [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, + [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, + [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE3] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, + [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev7_9_syn[] = { + [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, + [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, + [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, + [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, + [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev7_9_tx[] = { + [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, + [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_TX_PA_SPARE2] = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, }, + [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, + [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, + [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, + [B2056_TX_TXSPARE1] = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, }, + [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC0] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC1] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC2] = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, }, + [B2056_TX_GMBB_IDAC3] = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, }, + [B2056_TX_GMBB_IDAC4] = { .ghz5 = 0x0072, .ghz2 = 0x0072, UPLOAD, }, + [B2056_TX_GMBB_IDAC5] = { .ghz5 = 0x0073, .ghz2 = 0x0073, UPLOAD, }, + [B2056_TX_GMBB_IDAC6] = { .ghz5 = 0x0074, .ghz2 = 0x0074, UPLOAD, }, + [B2056_TX_GMBB_IDAC7] = { .ghz5 = 0x0075, .ghz2 = 0x0075, UPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev7_9_rx[] = { + [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, + [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, + [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, + [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, + [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev8_syn[] = { + [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, + [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, + [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, + [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, + [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, + [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, + [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, + [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev8_tx[] = { + [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, + [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_TX_PA_SPARE2] = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, }, + [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, + [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, + [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, + [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, + [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, + [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, + [B2056_TX_TXSPARE1] = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, }, + [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC0] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC1] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC2] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC3] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC4] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC5] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC6] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, + [B2056_TX_GMBB_IDAC7] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev8_rx[] = { + [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, + [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, + [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, + [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, + [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, + [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, + [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, + [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, + [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, + [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, + [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, + [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, + [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, + [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, + [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, + [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, + [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, + [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, + [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, + [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, + [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, + [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, + [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, + [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, + [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE3] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, + [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, + [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev11_syn[] = { + [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, + [B2056_SYN_PLL_CP2] = { .ghz5 = 0x003f, .ghz2 = 0x003f, UPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, + [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x002b, .ghz2 = 0x002b, UPLOAD, }, + [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, + [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev11_tx[] = { + [B2056_TX_PA_SPARE2] = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, }, + [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, + [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, + [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, + [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_TX_TXSPARE1] = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, }, +}; + +static const struct b2056_inittab_entry b2056_inittab_radio_rev11_rx[] = { + [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, + [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, + [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, + [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, + [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, + [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, + [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, + [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, + [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, + [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, + [B2056_RX_RXSPARE3] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, +}; + +#define INITTABSPTS(prefix) \ + static const struct b2056_inittabs_pts prefix = { \ + .syn = prefix##_syn, \ + .syn_length = nitems(prefix##_syn), \ + .tx = prefix##_tx, \ + .tx_length = nitems(prefix##_tx), \ + .rx = prefix##_rx, \ + .rx_length = nitems(prefix##_rx), \ + } + +INITTABSPTS(b2056_inittab_phy_rev3); +INITTABSPTS(b2056_inittab_phy_rev4); +INITTABSPTS(b2056_inittab_radio_rev5); +INITTABSPTS(b2056_inittab_radio_rev6); +INITTABSPTS(b2056_inittab_radio_rev7_9); +INITTABSPTS(b2056_inittab_radio_rev8); +INITTABSPTS(b2056_inittab_radio_rev11); + +#define RADIOREGS3(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ + r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ + r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, \ + r30, r31, r32, r33, r34, r35, r36) \ + .radio_syn_pll_vcocal1 = r00, \ + .radio_syn_pll_vcocal2 = r01, \ + .radio_syn_pll_refdiv = r02, \ + .radio_syn_pll_mmd2 = r03, \ + .radio_syn_pll_mmd1 = r04, \ + .radio_syn_pll_loopfilter1 = r05, \ + .radio_syn_pll_loopfilter2 = r06, \ + .radio_syn_pll_loopfilter3 = r07, \ + .radio_syn_pll_loopfilter4 = r08, \ + .radio_syn_pll_loopfilter5 = r09, \ + .radio_syn_reserved_addr27 = r10, \ + .radio_syn_reserved_addr28 = r11, \ + .radio_syn_reserved_addr29 = r12, \ + .radio_syn_logen_vcobuf1 = r13, \ + .radio_syn_logen_mixer2 = r14, \ + .radio_syn_logen_buf3 = r15, \ + .radio_syn_logen_buf4 = r16, \ + .radio_rx0_lnaa_tune = r17, \ + .radio_rx0_lnag_tune = r18, \ + .radio_tx0_intpaa_boost_tune = r19, \ + .radio_tx0_intpag_boost_tune = r20, \ + .radio_tx0_pada_boost_tune = r21, \ + .radio_tx0_padg_boost_tune = r22, \ + .radio_tx0_pgaa_boost_tune = r23, \ + .radio_tx0_pgag_boost_tune = r24, \ + .radio_tx0_mixa_boost_tune = r25, \ + .radio_tx0_mixg_boost_tune = r26, \ + .radio_rx1_lnaa_tune = r27, \ + .radio_rx1_lnag_tune = r28, \ + .radio_tx1_intpaa_boost_tune = r29, \ + .radio_tx1_intpag_boost_tune = r30, \ + .radio_tx1_pada_boost_tune = r31, \ + .radio_tx1_padg_boost_tune = r32, \ + .radio_tx1_pgaa_boost_tune = r33, \ + .radio_tx1_pgag_boost_tune = r34, \ + .radio_tx1_mixa_boost_tune = r35, \ + .radio_tx1_mixg_boost_tune = r36 + +#define PHYREGS(r0, r1, r2, r3, r4, r5) \ + .phy_regs.phy_bw1a = r0, \ + .phy_regs.phy_bw2 = r1, \ + .phy_regs.phy_bw3 = r2, \ + .phy_regs.phy_bw4 = r3, \ + .phy_regs.phy_bw5 = r4, \ + .phy_regs.phy_bw6 = r5 + +/* http://bcm-v4.sipsolutions.net/802.11/Radio/2056/ChannelTable */ +static const struct bwn_nphy_channeltab_entry_rev3 bwn_nphy_channeltab_phy_rev3[] = { + { .freq = 4920, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), + }, + { .freq = 4930, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), + }, + { .freq = 4940, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), + }, + { .freq = 4950, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), + }, + { .freq = 4960, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), + }, + { .freq = 4970, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), + }, + { .freq = 4980, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), + }, + { .freq = 4990, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), + }, + { .freq = 5000, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), + }, + { .freq = 5010, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), + }, + { .freq = 5020, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), + }, + { .freq = 5030, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), + }, + { .freq = 5040, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), + }, + { .freq = 5050, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), + }, + { .freq = 5060, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), + }, + { .freq = 5070, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), + }, + { .freq = 5080, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), + }, + { .freq = 5090, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), + }, + { .freq = 5100, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xff, 0x00), + PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), + }, + { .freq = 5110, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xfc, 0x00), + PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), + }, + { .freq = 5120, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xfc, 0x00), + PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), + }, + { .freq = 5130, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xfc, 0x00), + PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), + }, + { .freq = 5140, + RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xfc, 0x00), + PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), + }, + { .freq = 5160, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xfc, 0x00), + PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), + }, + { .freq = 5170, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xfc, 0x00), + PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), + }, + { .freq = 5180, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xef, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xfc, 0x00, 0xef, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xfc, 0x00), + PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), + }, + { .freq = 5190, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xef, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xfc, 0x00, 0xef, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xfc, 0x00), + PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), + }, + { .freq = 5200, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xef, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xef, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), + }, + { .freq = 5210, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), + }, + { .freq = 5220, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), + }, + { .freq = 5230, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), + }, + { .freq = 5240, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), + }, + { .freq = 5250, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), + }, + { .freq = 5260, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), + }, + { .freq = 5270, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, + 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), + }, + { .freq = 5280, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, + 0xff, 0xbf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), + }, + { .freq = 5290, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, + 0xff, 0xbf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xfc, 0x00), + PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), + }, + { .freq = 5300, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfc, 0x00), + PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), + }, + { .freq = 5310, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfa, 0x00), + PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), + }, + { .freq = 5320, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfa, 0x00), + PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), + }, + { .freq = 5330, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xaf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfa, 0x00), + PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), + }, + { .freq = 5340, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xaf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfa, 0x00), + PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), + }, + { .freq = 5350, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfa, 0x00), + PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), + }, + { .freq = 5360, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfa, 0x00), + PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), + }, + { .freq = 5370, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfa, 0x00), + PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), + }, + { .freq = 5380, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfa, 0x00), + PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), + }, + { .freq = 5390, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x8f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x05, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xfa, 0x00), + PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), + }, + { .freq = 5400, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x8f, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xfa, 0x00), + PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), + }, + { .freq = 5410, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x8f, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xfa, 0x00), + PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), + }, + { .freq = 5420, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x8e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xfa, 0x00, 0x8e, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xfa, 0x00), + PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), + }, + { .freq = 5430, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x8e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xfa, 0x00, 0x8e, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xfa, 0x00), + PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), + }, + { .freq = 5440, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x7e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xfa, 0x00, 0x7e, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xfa, 0x00), + PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), + }, + { .freq = 5450, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x7d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xfa, 0x00, 0x7d, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xfa, 0x00), + PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), + }, + { .freq = 5460, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x6d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xf8, 0x00, 0x6d, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xf8, 0x00), + PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), + }, + { .freq = 5470, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x6d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xf8, 0x00, 0x6d, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xf8, 0x00), + PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), + }, + { .freq = 5480, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x5d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xf8, 0x00, 0x5d, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xf8, 0x00), + PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), + }, + { .freq = 5490, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x5c, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, + 0x00, 0xf8, 0x00, 0x5c, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x08, 0x00, 0xf8, 0x00), + PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), + }, + { .freq = 5500, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x5c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x5c, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), + }, + { .freq = 5510, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x4c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x4c, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), + }, + { .freq = 5520, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x4c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x4c, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), + }, + { .freq = 5530, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), + }, + { .freq = 5540, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), + }, + { .freq = 5550, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), + }, + { .freq = 5560, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x2b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x2b, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), + }, + { .freq = 5570, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x2a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x2a, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), + }, + { .freq = 5580, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), + }, + { .freq = 5590, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), + }, + { .freq = 5600, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), + }, + { .freq = 5610, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x19, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x19, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), + }, + { .freq = 5620, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x19, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x19, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), + }, + { .freq = 5630, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x09, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x09, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), + }, + { .freq = 5640, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x09, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x09, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), + }, + { .freq = 5650, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf8, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf8, 0x00), + PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), + }, + { .freq = 5660, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf6, 0x00), + PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), + }, + { .freq = 5670, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf6, 0x00), + PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), + }, + { .freq = 5680, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf6, 0x00), + PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), + }, + { .freq = 5690, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf6, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf6, 0x00), + PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), + }, + { .freq = 5700, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf6, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf6, 0x00), + PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), + }, + { .freq = 5710, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), + }, + { .freq = 5720, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5725, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5730, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), + }, + { .freq = 5735, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), + }, + { .freq = 5740, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), + }, + { .freq = 5745, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), + }, + { .freq = 5750, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), + }, + { .freq = 5755, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), + }, + { .freq = 5760, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5765, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5770, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), + }, + { .freq = 5775, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), + }, + { .freq = 5780, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), + }, + { .freq = 5785, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, + 0x40, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5790, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, + 0x40, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5795, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, + 0x40, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), + }, + { .freq = 5800, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), + }, + { .freq = 5805, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), + }, + { .freq = 5810, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5815, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5820, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), + }, + { .freq = 5825, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), + }, + { .freq = 5830, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), + }, + { .freq = 5840, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), + }, + { .freq = 5850, + RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf4, 0x00), + PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), + }, + { .freq = 5860, + RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf2, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf2, 0x00), + PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), + }, + { .freq = 5870, + RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf2, 0x00), + PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), + }, + { .freq = 5880, + RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf2, 0x00), + PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), + }, + { .freq = 5890, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, + 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x06, 0x00, 0xf2, 0x00), + PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), + }, + { .freq = 5900, + RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05, + 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x05, 0x00, 0xf2, 0x00), + PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), + }, + { .freq = 5910, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05, + 0x00, 0xf2, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x05, 0x00, 0xf2, 0x00), + PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), + }, + { .freq = 2412, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0f), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { .freq = 2417, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0f), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { .freq = 2422, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0f), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { .freq = 2427, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xfd, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0f, 0x00, 0xfd, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0f), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { .freq = 2432, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xfb, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0f, 0x00, 0xfb, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0f), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { .freq = 2437, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xfa, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0f, 0x00, 0xfa, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0f), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { .freq = 2442, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf8, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0f, 0x00, 0xf8, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0f), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { .freq = 2447, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf7, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0f, 0x00, 0xf7, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0f), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { .freq = 2452, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf6, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0f, 0x00, 0xf6, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0f), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { .freq = 2457, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf5, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0d, 0x00, 0xf5, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0d), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { .freq = 2462, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0d, 0x00, 0xf4, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0d), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, + { .freq = 2467, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf3, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0d, 0x00, 0xf3, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0d), + PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), + }, + { .freq = 2472, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0d, 0x00, 0xf2, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0d), + PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), + }, + { .freq = 2484, + RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf0, 0x00, 0x05, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0d, 0x00, 0xf0, 0x00, 0x05, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0d), + PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), + }, +}; + +static const struct bwn_nphy_channeltab_entry_rev3 bwn_nphy_channeltab_phy_rev4[] = { + { .freq = 4920, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), + }, + { .freq = 4930, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), + }, + { .freq = 4940, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), + }, + { .freq = 4950, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), + }, + { .freq = 4960, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), + }, + { .freq = 4970, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), + }, + { .freq = 4980, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), + }, + { .freq = 4990, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), + }, + { .freq = 5000, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), + }, + { .freq = 5010, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), + }, + { .freq = 5020, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), + }, + { .freq = 5030, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), + }, + { .freq = 5040, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), + }, + { .freq = 5050, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), + }, + { .freq = 5060, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), + }, + { .freq = 5070, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), + }, + { .freq = 5080, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), + }, + { .freq = 5090, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xff, 0x00), + PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), + }, + { .freq = 5100, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfe, 0x00), + PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), + }, + { .freq = 5110, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfe, 0x00), + PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), + }, + { .freq = 5120, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfe, 0x00), + PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), + }, + { .freq = 5130, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfe, 0x00), + PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), + }, + { .freq = 5140, + RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfe, 0x00), + PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), + }, + { .freq = 5160, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfe, 0x00), + PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), + }, + { .freq = 5170, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfe, 0x00), + PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), + }, + { .freq = 5180, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xef, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfe, 0x00, 0xef, 0x00, 0x0c, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfe, 0x00), + PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), + }, + { .freq = 5190, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xef, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfe, 0x00, 0xef, 0x00, 0x0c, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfe, 0x00), + PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), + }, + { .freq = 5200, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xef, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xef, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), + }, + { .freq = 5210, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), + }, + { .freq = 5220, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), + }, + { .freq = 5230, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), + }, + { .freq = 5240, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), + }, + { .freq = 5250, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), + }, + { .freq = 5260, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), + }, + { .freq = 5270, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, + 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), + }, + { .freq = 5280, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, + 0xff, 0xbf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), + }, + { .freq = 5290, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, + 0xff, 0xbf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x0a, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfc, 0x00), + PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), + }, + { .freq = 5300, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), + }, + { .freq = 5310, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), + }, + { .freq = 5320, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), + }, + { .freq = 5330, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xaf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), + }, + { .freq = 5340, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xaf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), + }, + { .freq = 5350, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), + }, + { .freq = 5360, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), + }, + { .freq = 5370, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), + }, + { .freq = 5380, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), + }, + { .freq = 5390, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x8f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x08, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xfa, 0x00), + PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), + }, + { .freq = 5400, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x8f, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x8f, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), + }, + { .freq = 5410, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x8f, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x8f, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), + }, + { .freq = 5420, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x8e, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x8e, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), + }, + { .freq = 5430, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x8e, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x8e, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), + }, + { .freq = 5440, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x7e, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x7e, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), + }, + { .freq = 5450, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x7d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x7d, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), + }, + { .freq = 5460, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x6d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x6d, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), + }, + { .freq = 5470, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x6d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x6d, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), + }, + { .freq = 5480, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x5d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x5d, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), + }, + { .freq = 5490, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x5c, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, + 0x00, 0xf8, 0x00, 0x5c, 0x00, 0x07, 0x00, 0x7f, + 0x00, 0x0f, 0x00, 0xf8, 0x00), + PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), + }, + { .freq = 5500, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x5c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x5c, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), + }, + { .freq = 5510, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x4c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x4c, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), + }, + { .freq = 5520, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x4c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x4c, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), + }, + { .freq = 5530, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), + }, + { .freq = 5540, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), + }, + { .freq = 5550, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), + }, + { .freq = 5560, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x2b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x2b, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), + }, + { .freq = 5570, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x2a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x2a, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), + }, + { .freq = 5580, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x1a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x1a, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), + }, + { .freq = 5590, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x1a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, + 0x00, 0xf6, 0x00, 0x1a, 0x00, 0x06, 0x00, 0x7f, + 0x00, 0x0d, 0x00, 0xf6, 0x00), + PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), + }, + { .freq = 5600, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x1a, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x1a, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), + }, + { .freq = 5610, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x19, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x19, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), + }, + { .freq = 5620, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x19, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x19, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), + }, + { .freq = 5630, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x09, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x09, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), + }, + { .freq = 5640, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x09, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x09, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), + }, + { .freq = 5650, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), + }, + { .freq = 5660, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), + }, + { .freq = 5670, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), + }, + { .freq = 5680, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), + }, + { .freq = 5690, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x07, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, + 0x00, 0xf4, 0x00, 0x07, 0x00, 0x04, 0x00, 0x7f, + 0x00, 0x0b, 0x00, 0xf4, 0x00), + PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), + }, + { .freq = 5700, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), + }, + { .freq = 5710, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), + }, + { .freq = 5720, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5725, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5730, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), + }, + { .freq = 5735, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), + }, + { .freq = 5740, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), + }, + { .freq = 5745, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), + }, + { .freq = 5750, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), + }, + { .freq = 5755, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), + }, + { .freq = 5760, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5765, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5770, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), + }, + { .freq = 5775, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), + }, + { .freq = 5780, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), + }, + { .freq = 5785, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, + 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5790, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, + 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5795, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, + 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, + 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, + 0x00, 0x0a, 0x00, 0xf2, 0x00), + PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), + }, + { .freq = 5800, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), + }, + { .freq = 5805, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), + }, + { .freq = 5810, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5815, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5820, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), + }, + { .freq = 5825, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), + }, + { .freq = 5830, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), + }, + { .freq = 5840, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), + }, + { .freq = 5850, + RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), + }, + { .freq = 5860, + RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), + }, + { .freq = 5870, + RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), + }, + { .freq = 5880, + RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), + }, + { .freq = 5890, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, + 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, + 0x00, 0x09, 0x00, 0xf0, 0x00), + PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), + }, + { .freq = 5900, + RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf0, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf0, 0x00), + PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), + }, + { .freq = 5910, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07, + 0x00, 0xf0, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, + 0x00, 0x07, 0x00, 0xf0, 0x00), + PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), + }, + { .freq = 2412, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { .freq = 2417, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { .freq = 2422, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { .freq = 2427, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xfd, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xfd, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { .freq = 2432, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xfb, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xfb, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { .freq = 2437, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { .freq = 2442, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf8, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xf8, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { .freq = 2447, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf7, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xf7, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { .freq = 2452, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf6, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xf6, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { .freq = 2457, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf5, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xf5, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { .freq = 2462, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xf4, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, + { .freq = 2467, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf3, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xf3, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), + }, + { .freq = 2472, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xf2, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), + }, + { .freq = 2484, + RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0e, 0x00, 0xf0, 0x00, 0x04, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0e), + PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), + }, +}; + +static const struct bwn_nphy_channeltab_entry_rev3 bwn_nphy_channeltab_radio_rev5[] = { + { .freq = 4920, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), + }, + { .freq = 4930, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), + }, + { .freq = 4940, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), + }, + { .freq = 4950, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), + }, + { .freq = 4960, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), + }, + { .freq = 4970, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), + }, + { .freq = 4980, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), + }, + { .freq = 4990, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), + }, + { .freq = 5000, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), + }, + { .freq = 5010, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), + }, + { .freq = 5020, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), + }, + { .freq = 5030, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), + }, + { .freq = 5040, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, + 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), + }, + { .freq = 5050, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, + 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), + }, + { .freq = 5060, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, + 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), + }, + { .freq = 5070, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), + }, + { .freq = 5080, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), + }, + { .freq = 5090, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), + }, + { .freq = 5100, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), + }, + { .freq = 5110, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), + }, + { .freq = 5120, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), + }, + { .freq = 5130, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0a, + 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), + }, + { .freq = 5140, + RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x0a, + 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), + }, + { .freq = 5160, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), + }, + { .freq = 5170, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), + }, + { .freq = 5180, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), + }, + { .freq = 5190, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), + }, + { .freq = 5200, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), + }, + { .freq = 5210, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), + }, + { .freq = 5220, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), + }, + { .freq = 5230, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xea, 0x00, 0x06, 0x00, 0x70, 0x00, 0x08, + 0x00, 0x9e, 0x00, 0xea, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x08, 0x00, 0x6e, 0x00), + PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), + }, + { .freq = 5240, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, + 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, + 0x00, 0x08, 0x00, 0x6d, 0x00), + PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), + }, + { .freq = 5250, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, + 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, + 0x00, 0x08, 0x00, 0x6d, 0x00), + PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), + }, + { .freq = 5260, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xd9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, + 0x00, 0x9d, 0x00, 0xd9, 0x00, 0x05, 0x00, 0x70, + 0x00, 0x08, 0x00, 0x6d, 0x00), + PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), + }, + { .freq = 5270, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, + 0xff, 0xd8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xd8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), + }, + { .freq = 5280, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, + 0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), + }, + { .freq = 5290, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, + 0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), + }, + { .freq = 5300, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), + }, + { .freq = 5310, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), + }, + { .freq = 5320, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xb8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xb8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), + }, + { .freq = 5330, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xb7, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9b, 0x00, 0xb7, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6b, 0x00), + PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), + }, + { .freq = 5340, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xb7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9b, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6b, 0x00), + PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), + }, + { .freq = 5350, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xa7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9b, 0x00, 0xa7, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x6b, 0x00), + PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), + }, + { .freq = 5360, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x6b, 0x00), + PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), + }, + { .freq = 5370, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x5b, 0x00), + PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), + }, + { .freq = 5380, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x96, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9a, 0x00, 0x96, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x5a, 0x00), + PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), + }, + { .freq = 5390, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, + 0xff, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x5a, 0x00), + PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), + }, + { .freq = 5400, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x5a, 0x00), + PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), + }, + { .freq = 5410, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x5a, 0x00), + PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), + }, + { .freq = 5420, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x5a, 0x00), + PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), + }, + { .freq = 5430, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xc8, 0x85, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x99, 0x00, 0x85, 0x00, 0x02, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x59, 0x00), + PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), + }, + { .freq = 5440, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x59, 0x00), + PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), + }, + { .freq = 5450, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x59, 0x00), + PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), + }, + { .freq = 5460, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), + }, + { .freq = 5470, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x74, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x99, 0x00, 0x74, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), + }, + { .freq = 5480, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), + }, + { .freq = 5490, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, + 0xc8, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), + }, + { .freq = 5500, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x78, 0x00), + PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), + }, + { .freq = 5510, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x78, 0x00), + PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), + }, + { .freq = 5520, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x78, 0x00), + PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), + }, + { .freq = 5530, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x63, 0x00, 0x01, 0x00, 0x70, 0x00, 0x03, + 0x00, 0x98, 0x00, 0x63, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x03, 0x00, 0x78, 0x00), + PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), + }, + { .freq = 5540, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, + 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x03, 0x00, 0x77, 0x00), + PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), + }, + { .freq = 5550, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, + 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x03, 0x00, 0x77, 0x00), + PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), + }, + { .freq = 5560, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, + 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x03, 0x00, 0x77, 0x00), + PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), + }, + { .freq = 5570, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x76, 0x00), + PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), + }, + { .freq = 5580, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x76, 0x00), + PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), + }, + { .freq = 5590, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, + 0x84, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x76, 0x00), + PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), + }, + { .freq = 5600, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x76, 0x00), + PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), + }, + { .freq = 5610, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x76, 0x00), + PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), + }, + { .freq = 5620, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x76, 0x00), + PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), + }, + { .freq = 5630, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x76, 0x00), + PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), + }, + { .freq = 5640, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x95, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x75, 0x00), + PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), + }, + { .freq = 5650, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x75, 0x00), + PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), + }, + { .freq = 5660, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x75, 0x00), + PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), + }, + { .freq = 5670, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x74, 0x00), + PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), + }, + { .freq = 5680, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x74, 0x00), + PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), + }, + { .freq = 5690, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, + 0x70, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x74, 0x00), + PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), + }, + { .freq = 5700, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x74, 0x00), + PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), + }, + { .freq = 5710, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x74, 0x00), + PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), + }, + { .freq = 5720, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x74, 0x00), + PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5725, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x74, 0x00), + PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5730, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x84, 0x00), + PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), + }, + { .freq = 5735, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x83, 0x00), + PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), + }, + { .freq = 5740, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x83, 0x00), + PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), + }, + { .freq = 5745, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x83, 0x00), + PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), + }, + { .freq = 5750, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x83, 0x00), + PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), + }, + { .freq = 5755, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x83, 0x00), + PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), + }, + { .freq = 5760, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x83, 0x00), + PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5765, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5770, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), + }, + { .freq = 5775, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), + }, + { .freq = 5780, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, + 0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), + }, + { .freq = 5785, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, + 0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5790, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, + 0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5795, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, + 0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), + }, + { .freq = 5800, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), + }, + { .freq = 5805, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), + }, + { .freq = 5810, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5815, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5820, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), + }, + { .freq = 5825, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x82, 0x00), + PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), + }, + { .freq = 5830, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x72, 0x00), + PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), + }, + { .freq = 5840, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x72, 0x00), + PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), + }, + { .freq = 5850, + RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x72, 0x00), + PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), + }, + { .freq = 5860, + RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x72, 0x00), + PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), + }, + { .freq = 5870, + RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x71, 0x00), + PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), + }, + { .freq = 5880, + RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x71, 0x00), + PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), + }, + { .freq = 5890, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x71, 0x00), + PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), + }, + { .freq = 5900, + RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x71, 0x00), + PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), + }, + { .freq = 5910, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x71, 0x00), + PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), + }, + { .freq = 2412, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0b, 0x00, 0x1f, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0b), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { .freq = 2417, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0a, 0x00, 0x1f, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0a), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { .freq = 2422, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0a, 0x00, 0x0e, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0a), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { .freq = 2427, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x0d, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x0a), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { .freq = 2432, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x0c, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x0a, 0x00, 0x0c, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x0a), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { .freq = 2437, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x0b, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x0a, 0x00, 0x0b, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x0a), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { .freq = 2442, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x0a), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { .freq = 2447, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x08, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x09, 0x00, 0x08, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x09), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { .freq = 2452, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x07, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x09, 0x00, 0x07, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x09), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { .freq = 2457, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x06, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x09, 0x00, 0x06, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x09), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { .freq = 2462, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x05, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x09, 0x00, 0x05, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x09), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, + { .freq = 2467, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x08, 0x00, 0x04, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x08), + PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), + }, + { .freq = 2472, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x03, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x08), + PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), + }, + { .freq = 2484, + RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x08), + PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), + }, +}; + +static const struct bwn_nphy_channeltab_entry_rev3 bwn_nphy_channeltab_radio_rev6[] = { + { .freq = 4920, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), + }, + { .freq = 4930, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), + }, + { .freq = 4940, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), + }, + { .freq = 4950, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), + }, + { .freq = 4960, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), + }, + { .freq = 4970, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), + }, + { .freq = 4980, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), + }, + { .freq = 4990, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), + }, + { .freq = 5000, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), + }, + { .freq = 5010, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), + }, + { .freq = 5020, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), + }, + { .freq = 5030, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), + }, + { .freq = 5040, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), + }, + { .freq = 5050, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), + }, + { .freq = 5060, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), + }, + { .freq = 5070, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), + }, + { .freq = 5080, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), + }, + { .freq = 5090, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), + }, + { .freq = 5100, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), + }, + { .freq = 5110, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), + }, + { .freq = 5120, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), + }, + { .freq = 5130, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), + }, + { .freq = 5140, + RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), + }, + { .freq = 5160, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, + 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), + }, + { .freq = 5170, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, + 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), + }, + { .freq = 5180, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), + }, + { .freq = 5190, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), + }, + { .freq = 5200, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), + }, + { .freq = 5210, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), + }, + { .freq = 5220, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), + }, + { .freq = 5230, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), + }, + { .freq = 5240, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xee, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), + }, + { .freq = 5250, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xed, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), + }, + { .freq = 5260, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, + 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), + }, + { .freq = 5270, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, + 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), + }, + { .freq = 5280, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), + }, + { .freq = 5290, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), + }, + { .freq = 5300, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), + }, + { .freq = 5310, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), + }, + { .freq = 5320, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdb, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), + }, + { .freq = 5330, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xcb, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, + 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), + }, + { .freq = 5340, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, + 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), + }, + { .freq = 5350, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, + 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), + }, + { .freq = 5360, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), + }, + { .freq = 5370, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), + }, + { .freq = 5380, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), + }, + { .freq = 5390, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), + }, + { .freq = 5400, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), + }, + { .freq = 5410, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), + }, + { .freq = 5420, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xa7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), + }, + { .freq = 5430, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00, + 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), + }, + { .freq = 5440, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), + }, + { .freq = 5450, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), + }, + { .freq = 5460, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), + }, + { .freq = 5470, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x94, 0x73, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x01, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), + }, + { .freq = 5480, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x84, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), + }, + { .freq = 5490, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x83, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), + }, + { .freq = 5500, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), + }, + { .freq = 5510, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), + }, + { .freq = 5520, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), + }, + { .freq = 5530, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, + 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), + }, + { .freq = 5540, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, + 0x71, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), + }, + { .freq = 5550, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), + }, + { .freq = 5560, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), + }, + { .freq = 5570, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), + }, + { .freq = 5580, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, + 0x60, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), + }, + { .freq = 5590, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, + 0x50, 0x61, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x61, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), + }, + { .freq = 5600, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), + }, + { .freq = 5610, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), + }, + { .freq = 5620, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), + }, + { .freq = 5630, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), + }, + { .freq = 5640, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), + }, + { .freq = 5650, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), + }, + { .freq = 5660, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), + }, + { .freq = 5670, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), + }, + { .freq = 5680, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), + }, + { .freq = 5690, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), + }, + { .freq = 5700, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), + }, + { .freq = 5710, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), + }, + { .freq = 5720, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5725, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5730, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), + }, + { .freq = 5735, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6d, 0x00), + PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), + }, + { .freq = 5740, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6d, 0x00), + PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), + }, + { .freq = 5745, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6d, 0x00), + PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), + }, + { .freq = 5750, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6d, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6d, 0x00), + PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), + }, + { .freq = 5755, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6c, 0x00), + PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), + }, + { .freq = 5760, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6c, 0x00), + PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5765, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6c, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6c, 0x00), + PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5770, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), + }, + { .freq = 5775, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), + }, + { .freq = 5780, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), + }, + { .freq = 5785, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5790, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5795, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), + }, + { .freq = 5800, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), + }, + { .freq = 5805, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), + }, + { .freq = 5810, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5815, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5820, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), + }, + { .freq = 5825, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x69, 0x00), + PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), + }, + { .freq = 5830, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x69, 0x00), + PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), + }, + { .freq = 5840, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), + }, + { .freq = 5850, + RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), + }, + { .freq = 5860, + RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), + }, + { .freq = 5870, + RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), + }, + { .freq = 5880, + RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), + }, + { .freq = 5890, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), + }, + { .freq = 5900, + RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), + }, + { .freq = 5910, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), + }, + { .freq = 2412, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0b, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0b, 0x00, 0x0a), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { .freq = 2417, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0b, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0b, 0x00, 0x0a), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { .freq = 2422, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x67, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0b, 0x00, 0x0a, 0x00, 0x67, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0b, 0x00, 0x0a), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { .freq = 2427, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x57, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x57, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { .freq = 2432, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x56, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x56, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { .freq = 2437, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x46, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x46, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { .freq = 2442, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x45, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { .freq = 2447, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x09), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { .freq = 2452, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x09, 0x00, 0x23, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x09), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { .freq = 2457, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x09, 0x00, 0x12, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x09), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { .freq = 2462, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x02, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, + { .freq = 2467, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), + }, + { .freq = 2472, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), + }, + { .freq = 2484, + RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), + }, +}; + +static const struct bwn_nphy_channeltab_entry_rev3 bwn_nphy_channeltab_radio_rev7_9[] = { + { .freq = 4920, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), + }, + { .freq = 4930, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), + }, + { .freq = 4940, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), + }, + { .freq = 4950, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), + }, + { .freq = 4960, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), + }, + { .freq = 4970, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), + }, + { .freq = 4980, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), + }, + { .freq = 4990, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), + }, + { .freq = 5000, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), + }, + { .freq = 5010, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), + }, + { .freq = 5020, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), + }, + { .freq = 5030, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, + 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), + }, + { .freq = 5040, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, + 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), + }, + { .freq = 5050, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, + 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), + }, + { .freq = 5060, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, + 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x70, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), + }, + { .freq = 5070, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), + }, + { .freq = 5080, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), + }, + { .freq = 5090, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), + }, + { .freq = 5100, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), + }, + { .freq = 5110, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), + }, + { .freq = 5120, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, + 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), + }, + { .freq = 5130, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0a, + 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x70, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), + }, + { .freq = 5140, + RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x0a, + 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), + }, + { .freq = 5160, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), + }, + { .freq = 5170, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), + }, + { .freq = 5180, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), + }, + { .freq = 5190, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), + }, + { .freq = 5200, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), + }, + { .freq = 5210, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), + }, + { .freq = 5220, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xfe, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, + 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x09, 0x00, 0x6e, 0x00), + PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), + }, + { .freq = 5230, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xee, 0xea, 0x00, 0x06, 0x00, 0x70, 0x00, 0x08, + 0x00, 0x9e, 0x00, 0xea, 0x00, 0x06, 0x00, 0x70, + 0x00, 0x08, 0x00, 0x6e, 0x00), + PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), + }, + { .freq = 5240, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xee, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, + 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, + 0x00, 0x08, 0x00, 0x6d, 0x00), + PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), + }, + { .freq = 5250, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xed, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, + 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, + 0x00, 0x08, 0x00, 0x6d, 0x00), + PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), + }, + { .freq = 5260, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, + 0xed, 0xd9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, + 0x00, 0x9d, 0x00, 0xd9, 0x00, 0x05, 0x00, 0x70, + 0x00, 0x08, 0x00, 0x6d, 0x00), + PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), + }, + { .freq = 5270, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, + 0xed, 0xd8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xd8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), + }, + { .freq = 5280, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), + }, + { .freq = 5290, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), + }, + { .freq = 5300, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), + }, + { .freq = 5310, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), + }, + { .freq = 5320, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdb, 0xb8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9c, 0x00, 0xb8, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6c, 0x00), + PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), + }, + { .freq = 5330, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xcb, 0xb7, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9b, 0x00, 0xb7, 0x00, 0x04, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6b, 0x00), + PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), + }, + { .freq = 5340, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xca, 0xb7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x07, + 0x00, 0x9b, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x07, 0x00, 0x6b, 0x00), + PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), + }, + { .freq = 5350, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xca, 0xa7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9b, 0x00, 0xa7, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x6b, 0x00), + PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), + }, + { .freq = 5360, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xc9, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x6b, 0x00), + PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), + }, + { .freq = 5370, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xc9, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x7b, 0x00), + PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), + }, + { .freq = 5380, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x96, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9a, 0x00, 0x96, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x7a, 0x00), + PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), + }, + { .freq = 5390, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x7a, 0x00), + PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), + }, + { .freq = 5400, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, + 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x06, 0x00, 0x7a, 0x00), + PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), + }, + { .freq = 5410, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb7, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x7a, 0x00), + PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), + }, + { .freq = 5420, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xa7, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x7a, 0x00), + PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), + }, + { .freq = 5430, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00, + 0xa6, 0x85, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x99, 0x00, 0x85, 0x00, 0x02, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x79, 0x00), + PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), + }, + { .freq = 5440, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0xa6, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x79, 0x00), + PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), + }, + { .freq = 5450, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x95, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, + 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, + 0x00, 0x05, 0x00, 0x79, 0x00), + PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), + }, + { .freq = 5460, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x95, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x79, 0x00), + PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), + }, + { .freq = 5470, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x94, 0x74, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x99, 0x00, 0x74, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x79, 0x00), + PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), + }, + { .freq = 5480, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x78, 0x00), + PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), + }, + { .freq = 5490, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x83, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x78, 0x00), + PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), + }, + { .freq = 5500, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x82, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x78, 0x00), + PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), + }, + { .freq = 5510, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x82, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x78, 0x00), + PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), + }, + { .freq = 5520, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x72, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, + 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x04, 0x00, 0x78, 0x00), + PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), + }, + { .freq = 5530, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, + 0x72, 0x63, 0x00, 0x01, 0x00, 0x70, 0x00, 0x03, + 0x00, 0x98, 0x00, 0x63, 0x00, 0x01, 0x00, 0x70, + 0x00, 0x03, 0x00, 0x78, 0x00), + PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), + }, + { .freq = 5540, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, + 0x71, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, + 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x03, 0x00, 0x77, 0x00), + PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), + }, + { .freq = 5550, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, + 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x03, 0x00, 0x77, 0x00), + PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), + }, + { .freq = 5560, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, + 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x03, 0x00, 0x77, 0x00), + PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), + }, + { .freq = 5570, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x76, 0x00), + PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), + }, + { .freq = 5580, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, + 0x60, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x86, 0x00), + PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), + }, + { .freq = 5590, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x86, 0x00), + PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), + }, + { .freq = 5600, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x86, 0x00), + PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), + }, + { .freq = 5610, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x86, 0x00), + PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), + }, + { .freq = 5620, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x86, 0x00), + PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), + }, + { .freq = 5630, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x86, 0x00), + PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), + }, + { .freq = 5640, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, + 0x00, 0x95, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x02, 0x00, 0x85, 0x00), + PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), + }, + { .freq = 5650, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x85, 0x00), + PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), + }, + { .freq = 5660, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x85, 0x00), + PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), + }, + { .freq = 5670, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x84, 0x00), + PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), + }, + { .freq = 5680, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x84, 0x00), + PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), + }, + { .freq = 5690, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x94, 0x00), + PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), + }, + { .freq = 5700, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x94, 0x00), + PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), + }, + { .freq = 5710, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x94, 0x00), + PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), + }, + { .freq = 5720, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x94, 0x00), + PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5725, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x94, 0x00), + PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5730, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, + 0x00, 0x94, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x01, 0x00, 0x94, 0x00), + PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), + }, + { .freq = 5735, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x93, 0x00), + PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), + }, + { .freq = 5740, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x93, 0x00), + PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), + }, + { .freq = 5745, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x93, 0x00), + PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), + }, + { .freq = 5750, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x93, 0x00), + PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), + }, + { .freq = 5755, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x10, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x93, 0x00), + PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), + }, + { .freq = 5760, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x93, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x93, 0x00), + PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5765, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5770, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), + }, + { .freq = 5775, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), + }, + { .freq = 5780, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), + }, + { .freq = 5785, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5790, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5795, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), + }, + { .freq = 5800, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), + }, + { .freq = 5805, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), + }, + { .freq = 5810, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5815, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5820, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), + }, + { .freq = 5825, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), + }, + { .freq = 5830, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), + }, + { .freq = 5840, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), + }, + { .freq = 5850, + RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), + }, + { .freq = 5860, + RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x92, 0x00), + PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), + }, + { .freq = 5870, + RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x91, 0x00), + PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), + }, + { .freq = 5880, + RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x91, 0x00), + PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), + }, + { .freq = 5890, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x91, 0x00), + PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), + }, + { .freq = 5900, + RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x91, 0x00), + PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), + }, + { .freq = 5910, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, + 0x00, 0x00, 0x00, 0x91, 0x00), + PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), + }, + { .freq = 2412, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0b, 0x00, 0x89, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0b), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { .freq = 2417, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0a), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { .freq = 2422, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0f, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0f, 0x00, 0x0a), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { .freq = 2427, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x0a), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { .freq = 2432, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x0a), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { .freq = 2437, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x0a), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { .freq = 2442, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x66, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x0a), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { .freq = 2447, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x09), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { .freq = 2452, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0e, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0e, 0x00, 0x09), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { .freq = 2457, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x09), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { .freq = 2462, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x09), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, + { .freq = 2467, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x08, 0x00, 0x22, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x08), + PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), + }, + { .freq = 2472, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x08, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x08), + PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), + }, + { .freq = 2484, + RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0d, 0x00, 0x08), + PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), + }, +}; + +static const struct bwn_nphy_channeltab_entry_rev3 bwn_nphy_channeltab_radio_rev8[] = { + { .freq = 4920, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), + }, + { .freq = 4930, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), + }, + { .freq = 4940, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), + }, + { .freq = 4950, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), + }, + { .freq = 4960, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), + }, + { .freq = 4970, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), + }, + { .freq = 4980, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), + }, + { .freq = 4990, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), + }, + { .freq = 5000, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), + }, + { .freq = 5010, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), + }, + { .freq = 5020, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), + }, + { .freq = 5030, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), + }, + { .freq = 5040, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), + }, + { .freq = 5050, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), + }, + { .freq = 5060, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), + }, + { .freq = 5070, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), + }, + { .freq = 5080, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), + }, + { .freq = 5090, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), + }, + { .freq = 5100, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), + }, + { .freq = 5110, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), + }, + { .freq = 5120, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), + }, + { .freq = 5130, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), + }, + { .freq = 5140, + RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), + }, + { .freq = 5160, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, + 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), + }, + { .freq = 5170, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, + 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), + }, + { .freq = 5180, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), + }, + { .freq = 5190, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), + }, + { .freq = 5200, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), + }, + { .freq = 5210, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), + }, + { .freq = 5220, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), + }, + { .freq = 5230, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), + }, + { .freq = 5240, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xee, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), + }, + { .freq = 5250, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xed, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), + }, + { .freq = 5260, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, + 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), + }, + { .freq = 5270, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, + 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), + }, + { .freq = 5280, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), + }, + { .freq = 5290, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), + }, + { .freq = 5300, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), + }, + { .freq = 5310, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), + }, + { .freq = 5320, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdb, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), + }, + { .freq = 5330, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xcb, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, + 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), + }, + { .freq = 5340, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, + 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), + }, + { .freq = 5350, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, + 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), + }, + { .freq = 5360, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), + }, + { .freq = 5370, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), + }, + { .freq = 5380, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), + }, + { .freq = 5390, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), + }, + { .freq = 5400, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), + }, + { .freq = 5410, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), + }, + { .freq = 5420, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xa7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), + }, + { .freq = 5430, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00, + 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), + }, + { .freq = 5440, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), + }, + { .freq = 5450, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), + }, + { .freq = 5460, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), + }, + { .freq = 5470, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x94, 0x73, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x01, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), + }, + { .freq = 5480, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x84, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), + }, + { .freq = 5490, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x83, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), + }, + { .freq = 5500, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), + }, + { .freq = 5510, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), + }, + { .freq = 5520, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), + }, + { .freq = 5530, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, + 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), + }, + { .freq = 5540, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, + 0x71, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), + }, + { .freq = 5550, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), + }, + { .freq = 5560, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), + }, + { .freq = 5570, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), + }, + { .freq = 5580, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, + 0x60, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), + }, + { .freq = 5590, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, + 0x50, 0x61, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x61, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), + }, + { .freq = 5600, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), + }, + { .freq = 5610, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), + }, + { .freq = 5620, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), + }, + { .freq = 5630, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), + }, + { .freq = 5640, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), + }, + { .freq = 5650, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), + }, + { .freq = 5660, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), + }, + { .freq = 5670, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), + }, + { .freq = 5680, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), + }, + { .freq = 5690, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), + }, + { .freq = 5700, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), + }, + { .freq = 5710, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), + }, + { .freq = 5720, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5725, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), + }, + { .freq = 5730, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), + }, + { .freq = 5735, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6d, 0x00), + PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), + }, + { .freq = 5740, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6d, 0x00), + PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), + }, + { .freq = 5745, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6d, 0x00), + PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), + }, + { .freq = 5750, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6d, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6d, 0x00), + PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), + }, + { .freq = 5755, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6c, 0x00), + PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), + }, + { .freq = 5760, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6c, 0x00), + PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5765, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6c, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6c, 0x00), + PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), + }, + { .freq = 5770, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), + }, + { .freq = 5775, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), + }, + { .freq = 5780, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), + }, + { .freq = 5785, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5790, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), + }, + { .freq = 5795, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), + }, + { .freq = 5800, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), + }, + { .freq = 5805, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), + }, + { .freq = 5810, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5815, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), + }, + { .freq = 5820, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), + }, + { .freq = 5825, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, + 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x69, 0x00), + PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), + }, + { .freq = 5830, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x69, 0x00), + PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), + }, + { .freq = 5840, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), + }, + { .freq = 5850, + RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), + }, + { .freq = 5860, + RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), + }, + { .freq = 5870, + RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), + }, + { .freq = 5880, + RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), + }, + { .freq = 5890, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), + }, + { .freq = 5900, + RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), + }, + { .freq = 5910, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), + }, + { .freq = 2412, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0b, 0x00, 0x0a), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { .freq = 2417, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0b, 0x00, 0x0a), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { .freq = 2422, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x67, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0b, 0x00, 0x0a), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { .freq = 2427, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x57, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { .freq = 2432, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x56, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { .freq = 2437, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x46, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { .freq = 2442, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { .freq = 2447, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x09), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { .freq = 2452, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x09), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { .freq = 2457, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x09), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { .freq = 2462, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, + { .freq = 2467, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), + }, + { .freq = 2472, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), + }, + { .freq = 2484, + RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, + 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), + }, +}; + +static const struct bwn_nphy_channeltab_entry_rev3 bwn_nphy_channeltab_radio_rev11[] = { + { + .freq = 4920, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), + }, + { + .freq = 4930, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), + }, + { + .freq = 4940, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), + }, + { + .freq = 4950, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), + }, + { + .freq = 4960, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), + }, + { + .freq = 4970, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), + }, + { + .freq = 4980, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), + }, + { + .freq = 4990, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), + }, + { + .freq = 5000, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), + }, + { + .freq = 5010, + RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), + }, + { + .freq = 5020, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), + }, + { + .freq = 5030, + RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), + }, + { + .freq = 5040, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), + }, + { + .freq = 5050, + RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), + }, + { + .freq = 5060, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), + }, + { + .freq = 5070, + RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), + }, + { + .freq = 5080, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), + }, + { + .freq = 5090, + RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), + }, + { + .freq = 5100, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), + }, + { + .freq = 5110, + RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), + }, + { + .freq = 5120, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), + }, + { + .freq = 5130, + RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), + }, + { + .freq = 5140, + RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, + 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, + 0x00, 0x0f, 0x00, 0x6f, 0x00), + PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), + }, + { + .freq = 5160, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, + 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), + }, + { + .freq = 5170, + RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, + 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), + }, + { + .freq = 5180, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, + 0x00, 0x0e, 0x00, 0x6f, 0x00), + PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), + }, + { + .freq = 5190, + RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), + }, + { + .freq = 5200, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), + }, + { + .freq = 5210, + RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, + 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), + }, + { + .freq = 5220, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), + }, + { + .freq = 5230, + RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), + }, + { + .freq = 5240, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xee, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), + }, + { + .freq = 5250, + RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, + 0xed, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), + }, + { + .freq = 5260, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, + 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d, + 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, + 0x00, 0x0d, 0x00, 0x6f, 0x00), + PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), + }, + { + .freq = 5270, + RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, + 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), + }, + { + .freq = 5280, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), + }, + { + .freq = 5290, + RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), + }, + { + .freq = 5300, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), + }, + { + .freq = 5310, + RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), + }, + { + .freq = 5320, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, + 0xdb, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, + 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0c, 0x00, 0x6f, 0x00), + PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), + }, + { + .freq = 5330, + RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xcb, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, + 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), + }, + { + .freq = 5340, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, + 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, + 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), + }, + { + .freq = 5350, + RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, + 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0b, 0x00, 0x6f, 0x00), + PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), + }, + { + .freq = 5360, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), + }, + { + .freq = 5370, + RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, + 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), + }, + { + .freq = 5380, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), + }, + { + .freq = 5390, + RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), + }, + { + .freq = 5400, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), + }, + { + .freq = 5410, + RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xb7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), + }, + { + .freq = 5420, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, + 0xa7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), + }, + { + .freq = 5430, + RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00, + 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x0a, 0x00, 0x6f, 0x00), + PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), + }, + { + .freq = 5440, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), + }, + { + .freq = 5450, + RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), + }, + { + .freq = 5460, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), + }, + { + .freq = 5470, + RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, + 0x94, 0x73, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x01, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), + }, + { + .freq = 5480, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x84, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), + }, + { + .freq = 5490, + RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x83, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), + }, + { + .freq = 5500, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), + }, + { + .freq = 5510, + RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), + }, + { + .freq = 5520, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, + 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), + }, + { + .freq = 5530, + RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, + 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), + }, + { + .freq = 5540, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, + 0x71, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), + }, + { + .freq = 5550, + RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), + }, + { + .freq = 5560, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), + }, + { + .freq = 5570, + RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, + 0x61, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, + 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x09, 0x00, 0x6f, 0x00), + PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), + }, + { + .freq = 5580, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, + 0x60, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), + }, + { + .freq = 5590, + RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, + 0x50, 0x61, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x61, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), + }, + { + .freq = 5600, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), + }, + { + .freq = 5610, + RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, + 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x08, 0x00, 0x6f, 0x00), + PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), + }, + { + .freq = 5620, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, + 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), + }, + { + .freq = 5630, + RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), + }, + { + .freq = 5640, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), + }, + { + .freq = 5650, + RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, + 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x07, 0x00, 0x6f, 0x00), + PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), + }, + { + .freq = 5660, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), + }, + { + .freq = 5670, + RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, + 0x40, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), + }, + { + .freq = 5680, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), + }, + { + .freq = 5690, + RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6f, 0x00), + PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), + }, + { + .freq = 5700, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), + }, + { + .freq = 5710, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), + }, + { + .freq = 5720, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), + }, + { + .freq = 5725, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, + 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), + }, + { + .freq = 5730, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6e, 0x00), + PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), + }, + { + .freq = 5735, + RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6d, 0x00), + PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), + }, + { + .freq = 5740, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6d, 0x00), + PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), + }, + { + .freq = 5745, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, + 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x06, 0x00, 0x6d, 0x00), + PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), + }, + { + .freq = 5750, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x20, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6d, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6d, 0x00), + PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), + }, + { + .freq = 5755, + RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6c, 0x00), + PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), + }, + { + .freq = 5760, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, + 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6c, 0x00), + PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), + }, + { + .freq = 5765, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6c, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6c, 0x00), + PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), + }, + { + .freq = 5770, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), + }, + { + .freq = 5775, + RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), + }, + { + .freq = 5780, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, + 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), + }, + { + .freq = 5785, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), + }, + { + .freq = 5790, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), + }, + { + .freq = 5795, + RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), + }, + { + .freq = 5800, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6b, 0x00), + PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), + }, + { + .freq = 5805, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), + }, + { + .freq = 5810, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), + }, + { + .freq = 5815, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), + }, + { + .freq = 5820, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x6a, 0x00), + PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), + }, + { + .freq = 5825, + RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x05, 0x05, 0x02, + 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x69, 0x00), + PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), + }, + { + .freq = 5830, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x05, 0x00, 0x69, 0x00), + PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), + }, + { + .freq = 5840, + RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), + }, + { + .freq = 5850, + RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), + }, + { + .freq = 5860, + RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x69, 0x00), + PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), + }, + { + .freq = 5870, + RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), + }, + { + .freq = 5880, + RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), + }, + { + .freq = 5890, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), + }, + { + .freq = 5900, + RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), + }, + { + .freq = 5910, + RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x02, + 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, + 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x04, 0x00, 0x68, 0x00), + PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), + }, + { + .freq = 2412, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0b, 0x00, 0x0a), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { + .freq = 2417, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0b, 0x00, 0x0a), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { + .freq = 2422, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x67, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0b, 0x00, 0x0a), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { + .freq = 2427, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x57, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { + .freq = 2432, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x56, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { + .freq = 2437, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x46, 0x00, 0x03, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { + .freq = 2442, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x0a), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { + .freq = 2447, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x09), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { + .freq = 2452, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x09), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { + .freq = 2457, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x0a, 0x00, 0x09), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { + .freq = 2462, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, + { + .freq = 2467, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), + }, + { + .freq = 2472, + RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), + }, + { + .freq = 2484, + RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x06, 0x06, 0x04, + 0x2b, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, + 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x09, 0x00, 0x09), + PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), + }, +}; + +static const struct b2056_inittabs_pts +*bwn_nphy_get_inittabs_rev3(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + + switch (phy->rev) { + case 3: + return &b2056_inittab_phy_rev3; + case 4: + return &b2056_inittab_phy_rev4; + default: + switch (phy->rf_rev) { + case 5: + return &b2056_inittab_radio_rev5; + case 6: + return &b2056_inittab_radio_rev6; + case 7: + case 9: + return &b2056_inittab_radio_rev7_9; + case 8: + return &b2056_inittab_radio_rev8; + case 11: + return &b2056_inittab_radio_rev11; + } + } + + return NULL; +} + +static void b2056_upload_inittab(struct bwn_mac *mac, bool ghz5, + bool ignore_uploadflag, uint16_t routing, + const struct b2056_inittab_entry *e, + unsigned int length) +{ + unsigned int i; + uint16_t value; + + for (i = 0; i < length; i++, e++) { + if (!(e->flags & B2056_INITTAB_ENTRY_OK)) + continue; + if ((e->flags & B2056_INITTAB_UPLOAD) || ignore_uploadflag) { + if (ghz5) + value = e->ghz5; + else + value = e->ghz2; + BWN_RF_WRITE(mac, routing | i, value); + } + } +} + +void b2056_upload_inittabs(struct bwn_mac *mac, + bool ghz5, bool ignore_uploadflag) +{ + const struct b2056_inittabs_pts *pts; + + pts = bwn_nphy_get_inittabs_rev3(mac); + if (!pts) { + device_printf(mac->mac_sc->sc_dev, "%s: pts=NULL\n", + __func__); + return; + } + + b2056_upload_inittab(mac, ghz5, ignore_uploadflag, + B2056_SYN, pts->syn, pts->syn_length); + b2056_upload_inittab(mac, ghz5, ignore_uploadflag, + B2056_TX0, pts->tx, pts->tx_length); + b2056_upload_inittab(mac, ghz5, ignore_uploadflag, + B2056_TX1, pts->tx, pts->tx_length); + b2056_upload_inittab(mac, ghz5, ignore_uploadflag, + B2056_RX0, pts->rx, pts->rx_length); + b2056_upload_inittab(mac, ghz5, ignore_uploadflag, + B2056_RX1, pts->rx, pts->rx_length); +} + +void b2056_upload_syn_pll_cp2(struct bwn_mac *mac, bool ghz5) +{ + const struct b2056_inittabs_pts *pts; + const struct b2056_inittab_entry *e; + + pts = bwn_nphy_get_inittabs_rev3(mac); + if (!pts) { + device_printf(mac->mac_sc->sc_dev, "%s: pts=NULL\n", + __func__); + return; + } + + e = &pts->syn[B2056_SYN_PLL_CP2]; + + BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, ghz5 ? e->ghz5 : e->ghz2); +} + +const struct bwn_nphy_channeltab_entry_rev3 * +bwn_nphy_get_chantabent_rev3(struct bwn_mac *mac, uint16_t freq) +{ + struct bwn_phy *phy = &mac->mac_phy; + const struct bwn_nphy_channeltab_entry_rev3 *e; + unsigned int length, i; + + switch (phy->rev) { + case 3: + e = bwn_nphy_channeltab_phy_rev3; + length = nitems(bwn_nphy_channeltab_phy_rev3); + break; + case 4: + e = bwn_nphy_channeltab_phy_rev4; + length = nitems(bwn_nphy_channeltab_phy_rev4); + break; + default: + switch (phy->rf_rev) { + case 5: + e = bwn_nphy_channeltab_radio_rev5; + length = nitems(bwn_nphy_channeltab_radio_rev5); + break; + case 6: + e = bwn_nphy_channeltab_radio_rev6; + length = nitems(bwn_nphy_channeltab_radio_rev6); + break; + case 7: + case 9: + e = bwn_nphy_channeltab_radio_rev7_9; + length = nitems(bwn_nphy_channeltab_radio_rev7_9); + break; + case 8: + e = bwn_nphy_channeltab_radio_rev8; + length = nitems(bwn_nphy_channeltab_radio_rev8); + break; + case 11: + e = bwn_nphy_channeltab_radio_rev11; + length = nitems(bwn_nphy_channeltab_radio_rev11); + break; + default: + device_printf(mac->mac_sc->sc_dev, + "%s: unknown rf_rev %d\n", + __func__, + phy->rf_rev); + return NULL; + } + } + + for (i = 0; i < length; i++, e++) { + if (e->freq == freq) + return e; + } + + return NULL; +} diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2056.h b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2056.h new file mode 100644 index 0000000..da9363b --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2056.h @@ -0,0 +1,1125 @@ +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +/* + * $FreeBSD$ + */ + +#ifndef __IF_BWN_RADIO_2056_H__ +#define __IF_BWN_RADIO_2056_H__ + +#define B2056_SYN (0x0 << 12) +#define B2056_TX0 (0x2 << 12) +#define B2056_TX1 (0x3 << 12) +#define B2056_RX0 (0x6 << 12) +#define B2056_RX1 (0x7 << 12) +#define B2056_ALLTX (0xE << 12) +#define B2056_ALLRX (0xF << 12) + +#define B2056_SYN_RESERVED_ADDR0 0x00 +#define B2056_SYN_IDCODE 0x01 +#define B2056_SYN_RESERVED_ADDR2 0x02 +#define B2056_SYN_RESERVED_ADDR3 0x03 +#define B2056_SYN_RESERVED_ADDR4 0x04 +#define B2056_SYN_RESERVED_ADDR5 0x05 +#define B2056_SYN_RESERVED_ADDR6 0x06 +#define B2056_SYN_RESERVED_ADDR7 0x07 +#define B2056_SYN_COM_CTRL 0x08 +#define B2056_SYN_COM_PU 0x09 +#define B2056_SYN_COM_OVR 0x0A +#define B2056_SYN_COM_RESET 0x0B +#define B2056_SYN_COM_RCAL 0x0C +#define B2056_SYN_COM_RC_RXLPF 0x0D +#define B2056_SYN_COM_RC_TXLPF 0x0E +#define B2056_SYN_COM_RC_RXHPF 0x0F +#define B2056_SYN_RESERVED_ADDR16 0x10 +#define B2056_SYN_RESERVED_ADDR17 0x11 +#define B2056_SYN_RESERVED_ADDR18 0x12 +#define B2056_SYN_RESERVED_ADDR19 0x13 +#define B2056_SYN_RESERVED_ADDR20 0x14 +#define B2056_SYN_RESERVED_ADDR21 0x15 +#define B2056_SYN_RESERVED_ADDR22 0x16 +#define B2056_SYN_RESERVED_ADDR23 0x17 +#define B2056_SYN_RESERVED_ADDR24 0x18 +#define B2056_SYN_RESERVED_ADDR25 0x19 +#define B2056_SYN_RESERVED_ADDR26 0x1A +#define B2056_SYN_RESERVED_ADDR27 0x1B +#define B2056_SYN_RESERVED_ADDR28 0x1C +#define B2056_SYN_RESERVED_ADDR29 0x1D +#define B2056_SYN_RESERVED_ADDR30 0x1E +#define B2056_SYN_RESERVED_ADDR31 0x1F +#define B2056_SYN_GPIO_MASTER1 0x20 +#define B2056_SYN_GPIO_MASTER2 0x21 +#define B2056_SYN_TOPBIAS_MASTER 0x22 +#define B2056_SYN_TOPBIAS_RCAL 0x23 +#define B2056_SYN_AFEREG 0x24 +#define B2056_SYN_TEMPPROCSENSE 0x25 +#define B2056_SYN_TEMPPROCSENSEIDAC 0x26 +#define B2056_SYN_TEMPPROCSENSERCAL 0x27 +#define B2056_SYN_LPO 0x28 +#define B2056_SYN_VDDCAL_MASTER 0x29 +#define B2056_SYN_VDDCAL_IDAC 0x2A +#define B2056_SYN_VDDCAL_STATUS 0x2B +#define B2056_SYN_RCAL_MASTER 0x2C +#define B2056_SYN_RCAL_CODE_OUT 0x2D +#define B2056_SYN_RCCAL_CTRL0 0x2E +#define B2056_SYN_RCCAL_CTRL1 0x2F +#define B2056_SYN_RCCAL_CTRL2 0x30 +#define B2056_SYN_RCCAL_CTRL3 0x31 +#define B2056_SYN_RCCAL_CTRL4 0x32 +#define B2056_SYN_RCCAL_CTRL5 0x33 +#define B2056_SYN_RCCAL_CTRL6 0x34 +#define B2056_SYN_RCCAL_CTRL7 0x35 +#define B2056_SYN_RCCAL_CTRL8 0x36 +#define B2056_SYN_RCCAL_CTRL9 0x37 +#define B2056_SYN_RCCAL_CTRL10 0x38 +#define B2056_SYN_RCCAL_CTRL11 0x39 +#define B2056_SYN_ZCAL_SPARE1 0x3A +#define B2056_SYN_ZCAL_SPARE2 0x3B +#define B2056_SYN_PLL_MAST1 0x3C +#define B2056_SYN_PLL_MAST2 0x3D +#define B2056_SYN_PLL_MAST3 0x3E +#define B2056_SYN_PLL_BIAS_RESET 0x3F +#define B2056_SYN_PLL_XTAL0 0x40 +#define B2056_SYN_PLL_XTAL1 0x41 +#define B2056_SYN_PLL_XTAL3 0x42 +#define B2056_SYN_PLL_XTAL4 0x43 +#define B2056_SYN_PLL_XTAL5 0x44 +#define B2056_SYN_PLL_XTAL6 0x45 +#define B2056_SYN_PLL_REFDIV 0x46 +#define B2056_SYN_PLL_PFD 0x47 +#define B2056_SYN_PLL_CP1 0x48 +#define B2056_SYN_PLL_CP2 0x49 +#define B2056_SYN_PLL_CP3 0x4A +#define B2056_SYN_PLL_LOOPFILTER1 0x4B +#define B2056_SYN_PLL_LOOPFILTER2 0x4C +#define B2056_SYN_PLL_LOOPFILTER3 0x4D +#define B2056_SYN_PLL_LOOPFILTER4 0x4E +#define B2056_SYN_PLL_LOOPFILTER5 0x4F +#define B2056_SYN_PLL_MMD1 0x50 +#define B2056_SYN_PLL_MMD2 0x51 +#define B2056_SYN_PLL_VCO1 0x52 +#define B2056_SYN_PLL_VCO2 0x53 +#define B2056_SYN_PLL_MONITOR1 0x54 +#define B2056_SYN_PLL_MONITOR2 0x55 +#define B2056_SYN_PLL_VCOCAL1 0x56 +#define B2056_SYN_PLL_VCOCAL2 0x57 +#define B2056_SYN_PLL_VCOCAL4 0x58 +#define B2056_SYN_PLL_VCOCAL5 0x59 +#define B2056_SYN_PLL_VCOCAL6 0x5A +#define B2056_SYN_PLL_VCOCAL7 0x5B +#define B2056_SYN_PLL_VCOCAL8 0x5C +#define B2056_SYN_PLL_VCOCAL9 0x5D +#define B2056_SYN_PLL_VCOCAL10 0x5E +#define B2056_SYN_PLL_VCOCAL11 0x5F +#define B2056_SYN_PLL_VCOCAL12 0x60 +#define B2056_SYN_PLL_VCOCAL13 0x61 +#define B2056_SYN_PLL_VREG 0x62 +#define B2056_SYN_PLL_STATUS1 0x63 +#define B2056_SYN_PLL_STATUS2 0x64 +#define B2056_SYN_PLL_STATUS3 0x65 +#define B2056_SYN_LOGEN_PU0 0x66 +#define B2056_SYN_LOGEN_PU1 0x67 +#define B2056_SYN_LOGEN_PU2 0x68 +#define B2056_SYN_LOGEN_PU3 0x69 +#define B2056_SYN_LOGEN_PU5 0x6A +#define B2056_SYN_LOGEN_PU6 0x6B +#define B2056_SYN_LOGEN_PU7 0x6C +#define B2056_SYN_LOGEN_PU8 0x6D +#define B2056_SYN_LOGEN_BIAS_RESET 0x6E +#define B2056_SYN_LOGEN_RCCR1 0x6F +#define B2056_SYN_LOGEN_VCOBUF1 0x70 +#define B2056_SYN_LOGEN_MIXER1 0x71 +#define B2056_SYN_LOGEN_MIXER2 0x72 +#define B2056_SYN_LOGEN_BUF1 0x73 +#define B2056_SYN_LOGENBUF2 0x74 +#define B2056_SYN_LOGEN_BUF3 0x75 +#define B2056_SYN_LOGEN_BUF4 0x76 +#define B2056_SYN_LOGEN_DIV1 0x77 +#define B2056_SYN_LOGEN_DIV2 0x78 +#define B2056_SYN_LOGEN_DIV3 0x79 +#define B2056_SYN_LOGEN_ACL1 0x7A +#define B2056_SYN_LOGEN_ACL2 0x7B +#define B2056_SYN_LOGEN_ACL3 0x7C +#define B2056_SYN_LOGEN_ACL4 0x7D +#define B2056_SYN_LOGEN_ACL5 0x7E +#define B2056_SYN_LOGEN_ACL6 0x7F +#define B2056_SYN_LOGEN_ACLOUT 0x80 +#define B2056_SYN_LOGEN_ACLCAL1 0x81 +#define B2056_SYN_LOGEN_ACLCAL2 0x82 +#define B2056_SYN_LOGEN_ACLCAL3 0x83 +#define B2056_SYN_CALEN 0x84 +#define B2056_SYN_LOGEN_PEAKDET1 0x85 +#define B2056_SYN_LOGEN_CORE_ACL_OVR 0x86 +#define B2056_SYN_LOGEN_RX_DIFF_ACL_OVR 0x87 +#define B2056_SYN_LOGEN_TX_DIFF_ACL_OVR 0x88 +#define B2056_SYN_LOGEN_RX_CMOS_ACL_OVR 0x89 +#define B2056_SYN_LOGEN_TX_CMOS_ACL_OVR 0x8A +#define B2056_SYN_LOGEN_VCOBUF2 0x8B +#define B2056_SYN_LOGEN_MIXER3 0x8C +#define B2056_SYN_LOGEN_BUF5 0x8D +#define B2056_SYN_LOGEN_BUF6 0x8E +#define B2056_SYN_LOGEN_CBUFRX1 0x8F +#define B2056_SYN_LOGEN_CBUFRX2 0x90 +#define B2056_SYN_LOGEN_CBUFRX3 0x91 +#define B2056_SYN_LOGEN_CBUFRX4 0x92 +#define B2056_SYN_LOGEN_CBUFTX1 0x93 +#define B2056_SYN_LOGEN_CBUFTX2 0x94 +#define B2056_SYN_LOGEN_CBUFTX3 0x95 +#define B2056_SYN_LOGEN_CBUFTX4 0x96 +#define B2056_SYN_LOGEN_CMOSRX1 0x97 +#define B2056_SYN_LOGEN_CMOSRX2 0x98 +#define B2056_SYN_LOGEN_CMOSRX3 0x99 +#define B2056_SYN_LOGEN_CMOSRX4 0x9A +#define B2056_SYN_LOGEN_CMOSTX1 0x9B +#define B2056_SYN_LOGEN_CMOSTX2 0x9C +#define B2056_SYN_LOGEN_CMOSTX3 0x9D +#define B2056_SYN_LOGEN_CMOSTX4 0x9E +#define B2056_SYN_LOGEN_VCOBUF2_OVRVAL 0x9F +#define B2056_SYN_LOGEN_MIXER3_OVRVAL 0xA0 +#define B2056_SYN_LOGEN_BUF5_OVRVAL 0xA1 +#define B2056_SYN_LOGEN_BUF6_OVRVAL 0xA2 +#define B2056_SYN_LOGEN_CBUFRX1_OVRVAL 0xA3 +#define B2056_SYN_LOGEN_CBUFRX2_OVRVAL 0xA4 +#define B2056_SYN_LOGEN_CBUFRX3_OVRVAL 0xA5 +#define B2056_SYN_LOGEN_CBUFRX4_OVRVAL 0xA6 +#define B2056_SYN_LOGEN_CBUFTX1_OVRVAL 0xA7 +#define B2056_SYN_LOGEN_CBUFTX2_OVRVAL 0xA8 +#define B2056_SYN_LOGEN_CBUFTX3_OVRVAL 0xA9 +#define B2056_SYN_LOGEN_CBUFTX4_OVRVAL 0xAA +#define B2056_SYN_LOGEN_CMOSRX1_OVRVAL 0xAB +#define B2056_SYN_LOGEN_CMOSRX2_OVRVAL 0xAC +#define B2056_SYN_LOGEN_CMOSRX3_OVRVAL 0xAD +#define B2056_SYN_LOGEN_CMOSRX4_OVRVAL 0xAE +#define B2056_SYN_LOGEN_CMOSTX1_OVRVAL 0xAF +#define B2056_SYN_LOGEN_CMOSTX2_OVRVAL 0xB0 +#define B2056_SYN_LOGEN_CMOSTX3_OVRVAL 0xB1 +#define B2056_SYN_LOGEN_CMOSTX4_OVRVAL 0xB2 +#define B2056_SYN_LOGEN_ACL_WAITCNT 0xB3 +#define B2056_SYN_LOGEN_CORE_CALVALID 0xB4 +#define B2056_SYN_LOGEN_RX_CMOS_CALVALID 0xB5 +#define B2056_SYN_LOGEN_TX_CMOS_VALID 0xB6 + +#define B2056_TX_RESERVED_ADDR0 0x00 +#define B2056_TX_IDCODE 0x01 +#define B2056_TX_RESERVED_ADDR2 0x02 +#define B2056_TX_RESERVED_ADDR3 0x03 +#define B2056_TX_RESERVED_ADDR4 0x04 +#define B2056_TX_RESERVED_ADDR5 0x05 +#define B2056_TX_RESERVED_ADDR6 0x06 +#define B2056_TX_RESERVED_ADDR7 0x07 +#define B2056_TX_COM_CTRL 0x08 +#define B2056_TX_COM_PU 0x09 +#define B2056_TX_COM_OVR 0x0A +#define B2056_TX_COM_RESET 0x0B +#define B2056_TX_COM_RCAL 0x0C +#define B2056_TX_COM_RC_RXLPF 0x0D +#define B2056_TX_COM_RC_TXLPF 0x0E +#define B2056_TX_COM_RC_RXHPF 0x0F +#define B2056_TX_RESERVED_ADDR16 0x10 +#define B2056_TX_RESERVED_ADDR17 0x11 +#define B2056_TX_RESERVED_ADDR18 0x12 +#define B2056_TX_RESERVED_ADDR19 0x13 +#define B2056_TX_RESERVED_ADDR20 0x14 +#define B2056_TX_RESERVED_ADDR21 0x15 +#define B2056_TX_RESERVED_ADDR22 0x16 +#define B2056_TX_RESERVED_ADDR23 0x17 +#define B2056_TX_RESERVED_ADDR24 0x18 +#define B2056_TX_RESERVED_ADDR25 0x19 +#define B2056_TX_RESERVED_ADDR26 0x1A +#define B2056_TX_RESERVED_ADDR27 0x1B +#define B2056_TX_RESERVED_ADDR28 0x1C +#define B2056_TX_RESERVED_ADDR29 0x1D +#define B2056_TX_RESERVED_ADDR30 0x1E +#define B2056_TX_RESERVED_ADDR31 0x1F +#define B2056_TX_IQCAL_GAIN_BW 0x20 +#define B2056_TX_LOFT_FINE_I 0x21 +#define B2056_TX_LOFT_FINE_Q 0x22 +#define B2056_TX_LOFT_COARSE_I 0x23 +#define B2056_TX_LOFT_COARSE_Q 0x24 +#define B2056_TX_TX_COM_MASTER1 0x25 +#define B2056_TX_TX_COM_MASTER2 0x26 +#define B2056_TX_RXIQCAL_TXMUX 0x27 +#define B2056_TX_TX_SSI_MASTER 0x28 +#define B2056_TX_IQCAL_VCM_HG 0x29 +#define B2056_TX_IQCAL_IDAC 0x2A +#define B2056_TX_TSSI_VCM 0x2B +#define B2056_TX_TX_AMP_DET 0x2C +#define B2056_TX_TX_SSI_MUX 0x2D +#define B2056_TX_TSSIA 0x2E +#define B2056_TX_TSSIG 0x2F +#define B2056_TX_TSSI_MISC1 0x30 +#define B2056_TX_TSSI_MISC2 0x31 +#define B2056_TX_TSSI_MISC3 0x32 +#define B2056_TX_PA_SPARE1 0x33 +#define B2056_TX_PA_SPARE2 0x34 +#define B2056_TX_INTPAA_MASTER 0x35 +#define B2056_TX_INTPAA_GAIN 0x36 +#define B2056_TX_INTPAA_BOOST_TUNE 0x37 +#define B2056_TX_INTPAA_IAUX_STAT 0x38 +#define B2056_TX_INTPAA_IAUX_DYN 0x39 +#define B2056_TX_INTPAA_IMAIN_STAT 0x3A +#define B2056_TX_INTPAA_IMAIN_DYN 0x3B +#define B2056_TX_INTPAA_CASCBIAS 0x3C +#define B2056_TX_INTPAA_PASLOPE 0x3D +#define B2056_TX_INTPAA_PA_MISC 0x3E +#define B2056_TX_INTPAG_MASTER 0x3F +#define B2056_TX_INTPAG_GAIN 0x40 +#define B2056_TX_INTPAG_BOOST_TUNE 0x41 +#define B2056_TX_INTPAG_IAUX_STAT 0x42 +#define B2056_TX_INTPAG_IAUX_DYN 0x43 +#define B2056_TX_INTPAG_IMAIN_STAT 0x44 +#define B2056_TX_INTPAG_IMAIN_DYN 0x45 +#define B2056_TX_INTPAG_CASCBIAS 0x46 +#define B2056_TX_INTPAG_PASLOPE 0x47 +#define B2056_TX_INTPAG_PA_MISC 0x48 +#define B2056_TX_PADA_MASTER 0x49 +#define B2056_TX_PADA_IDAC 0x4A +#define B2056_TX_PADA_CASCBIAS 0x4B +#define B2056_TX_PADA_GAIN 0x4C +#define B2056_TX_PADA_BOOST_TUNE 0x4D +#define B2056_TX_PADA_SLOPE 0x4E +#define B2056_TX_PADG_MASTER 0x4F +#define B2056_TX_PADG_IDAC 0x50 +#define B2056_TX_PADG_CASCBIAS 0x51 +#define B2056_TX_PADG_GAIN 0x52 +#define B2056_TX_PADG_BOOST_TUNE 0x53 +#define B2056_TX_PADG_SLOPE 0x54 +#define B2056_TX_PGAA_MASTER 0x55 +#define B2056_TX_PGAA_IDAC 0x56 +#define B2056_TX_PGAA_GAIN 0x57 +#define B2056_TX_PGAA_BOOST_TUNE 0x58 +#define B2056_TX_PGAA_SLOPE 0x59 +#define B2056_TX_PGAA_MISC 0x5A +#define B2056_TX_PGAG_MASTER 0x5B +#define B2056_TX_PGAG_IDAC 0x5C +#define B2056_TX_PGAG_GAIN 0x5D +#define B2056_TX_PGAG_BOOST_TUNE 0x5E +#define B2056_TX_PGAG_SLOPE 0x5F +#define B2056_TX_PGAG_MISC 0x60 +#define B2056_TX_MIXA_MASTER 0x61 +#define B2056_TX_MIXA_BOOST_TUNE 0x62 +#define B2056_TX_MIXG 0x63 +#define B2056_TX_MIXG_BOOST_TUNE 0x64 +#define B2056_TX_BB_GM_MASTER 0x65 +#define B2056_TX_GMBB_GM 0x66 +#define B2056_TX_GMBB_IDAC 0x67 +#define B2056_TX_TXLPF_MASTER 0x68 +#define B2056_TX_TXLPF_RCCAL 0x69 +#define B2056_TX_TXLPF_RCCAL_OFF0 0x6A +#define B2056_TX_TXLPF_RCCAL_OFF1 0x6B +#define B2056_TX_TXLPF_RCCAL_OFF2 0x6C +#define B2056_TX_TXLPF_RCCAL_OFF3 0x6D +#define B2056_TX_TXLPF_RCCAL_OFF4 0x6E +#define B2056_TX_TXLPF_RCCAL_OFF5 0x6F +#define B2056_TX_TXLPF_RCCAL_OFF6 0x70 +#define B2056_TX_TXLPF_BW 0x71 +#define B2056_TX_TXLPF_GAIN 0x72 +#define B2056_TX_TXLPF_IDAC 0x73 +#define B2056_TX_TXLPF_IDAC_0 0x74 +#define B2056_TX_TXLPF_IDAC_1 0x75 +#define B2056_TX_TXLPF_IDAC_2 0x76 +#define B2056_TX_TXLPF_IDAC_3 0x77 +#define B2056_TX_TXLPF_IDAC_4 0x78 +#define B2056_TX_TXLPF_IDAC_5 0x79 +#define B2056_TX_TXLPF_IDAC_6 0x7A +#define B2056_TX_TXLPF_OPAMP_IDAC 0x7B +#define B2056_TX_TXLPF_MISC 0x7C +#define B2056_TX_TXSPARE1 0x7D +#define B2056_TX_TXSPARE2 0x7E +#define B2056_TX_TXSPARE3 0x7F +#define B2056_TX_TXSPARE4 0x80 +#define B2056_TX_TXSPARE5 0x81 +#define B2056_TX_TXSPARE6 0x82 +#define B2056_TX_TXSPARE7 0x83 +#define B2056_TX_TXSPARE8 0x84 +#define B2056_TX_TXSPARE9 0x85 +#define B2056_TX_TXSPARE10 0x86 +#define B2056_TX_TXSPARE11 0x87 +#define B2056_TX_TXSPARE12 0x88 +#define B2056_TX_TXSPARE13 0x89 +#define B2056_TX_TXSPARE14 0x8A +#define B2056_TX_TXSPARE15 0x8B +#define B2056_TX_TXSPARE16 0x8C +#define B2056_TX_STATUS_INTPA_GAIN 0x8D +#define B2056_TX_STATUS_PAD_GAIN 0x8E +#define B2056_TX_STATUS_PGA_GAIN 0x8F +#define B2056_TX_STATUS_GM_TXLPF_GAIN 0x90 +#define B2056_TX_STATUS_TXLPF_BW 0x91 +#define B2056_TX_STATUS_TXLPF_RC 0x92 +#define B2056_TX_GMBB_IDAC0 0x93 +#define B2056_TX_GMBB_IDAC1 0x94 +#define B2056_TX_GMBB_IDAC2 0x95 +#define B2056_TX_GMBB_IDAC3 0x96 +#define B2056_TX_GMBB_IDAC4 0x97 +#define B2056_TX_GMBB_IDAC5 0x98 +#define B2056_TX_GMBB_IDAC6 0x99 +#define B2056_TX_GMBB_IDAC7 0x9A + +#define B2056_RX_RESERVED_ADDR0 0x00 +#define B2056_RX_IDCODE 0x01 +#define B2056_RX_RESERVED_ADDR2 0x02 +#define B2056_RX_RESERVED_ADDR3 0x03 +#define B2056_RX_RESERVED_ADDR4 0x04 +#define B2056_RX_RESERVED_ADDR5 0x05 +#define B2056_RX_RESERVED_ADDR6 0x06 +#define B2056_RX_RESERVED_ADDR7 0x07 +#define B2056_RX_COM_CTRL 0x08 +#define B2056_RX_COM_PU 0x09 +#define B2056_RX_COM_OVR 0x0A +#define B2056_RX_COM_RESET 0x0B +#define B2056_RX_COM_RCAL 0x0C +#define B2056_RX_COM_RC_RXLPF 0x0D +#define B2056_RX_COM_RC_TXLPF 0x0E +#define B2056_RX_COM_RC_RXHPF 0x0F +#define B2056_RX_RESERVED_ADDR16 0x10 +#define B2056_RX_RESERVED_ADDR17 0x11 +#define B2056_RX_RESERVED_ADDR18 0x12 +#define B2056_RX_RESERVED_ADDR19 0x13 +#define B2056_RX_RESERVED_ADDR20 0x14 +#define B2056_RX_RESERVED_ADDR21 0x15 +#define B2056_RX_RESERVED_ADDR22 0x16 +#define B2056_RX_RESERVED_ADDR23 0x17 +#define B2056_RX_RESERVED_ADDR24 0x18 +#define B2056_RX_RESERVED_ADDR25 0x19 +#define B2056_RX_RESERVED_ADDR26 0x1A +#define B2056_RX_RESERVED_ADDR27 0x1B +#define B2056_RX_RESERVED_ADDR28 0x1C +#define B2056_RX_RESERVED_ADDR29 0x1D +#define B2056_RX_RESERVED_ADDR30 0x1E +#define B2056_RX_RESERVED_ADDR31 0x1F +#define B2056_RX_RXIQCAL_RXMUX 0x20 +#define B2056_RX_RSSI_PU 0x21 +#define B2056_RX_RSSI_SEL 0x22 +#define B2056_RX_RSSI_GAIN 0x23 +#define B2056_RX_RSSI_NB_IDAC 0x24 +#define B2056_RX_RSSI_WB2I_IDAC_1 0x25 +#define B2056_RX_RSSI_WB2I_IDAC_2 0x26 +#define B2056_RX_RSSI_WB2Q_IDAC_1 0x27 +#define B2056_RX_RSSI_WB2Q_IDAC_2 0x28 +#define B2056_RX_RSSI_POLE 0x29 +#define B2056_RX_RSSI_WB1_IDAC 0x2A +#define B2056_RX_RSSI_MISC 0x2B +#define B2056_RX_LNAA_MASTER 0x2C +#define B2056_RX_LNAA_TUNE 0x2D +#define B2056_RX_LNAA_GAIN 0x2E +#define B2056_RX_LNA_A_SLOPE 0x2F +#define B2056_RX_BIASPOLE_LNAA1_IDAC 0x30 +#define B2056_RX_LNAA2_IDAC 0x31 +#define B2056_RX_LNA1A_MISC 0x32 +#define B2056_RX_LNAG_MASTER 0x33 +#define B2056_RX_LNAG_TUNE 0x34 +#define B2056_RX_LNAG_GAIN 0x35 +#define B2056_RX_LNA_G_SLOPE 0x36 +#define B2056_RX_BIASPOLE_LNAG1_IDAC 0x37 +#define B2056_RX_LNAG2_IDAC 0x38 +#define B2056_RX_LNA1G_MISC 0x39 +#define B2056_RX_MIXA_MASTER 0x3A +#define B2056_RX_MIXA_VCM 0x3B +#define B2056_RX_MIXA_CTRLPTAT 0x3C +#define B2056_RX_MIXA_LOB_BIAS 0x3D +#define B2056_RX_MIXA_CORE_IDAC 0x3E +#define B2056_RX_MIXA_CMFB_IDAC 0x3F +#define B2056_RX_MIXA_BIAS_AUX 0x40 +#define B2056_RX_MIXA_BIAS_MAIN 0x41 +#define B2056_RX_MIXA_BIAS_MISC 0x42 +#define B2056_RX_MIXA_MAST_BIAS 0x43 +#define B2056_RX_MIXG_MASTER 0x44 +#define B2056_RX_MIXG_VCM 0x45 +#define B2056_RX_MIXG_CTRLPTAT 0x46 +#define B2056_RX_MIXG_LOB_BIAS 0x47 +#define B2056_RX_MIXG_CORE_IDAC 0x48 +#define B2056_RX_MIXG_CMFB_IDAC 0x49 +#define B2056_RX_MIXG_BIAS_AUX 0x4A +#define B2056_RX_MIXG_BIAS_MAIN 0x4B +#define B2056_RX_MIXG_BIAS_MISC 0x4C +#define B2056_RX_MIXG_MAST_BIAS 0x4D +#define B2056_RX_TIA_MASTER 0x4E +#define B2056_RX_TIA_IOPAMP 0x4F +#define B2056_RX_TIA_QOPAMP 0x50 +#define B2056_RX_TIA_IMISC 0x51 +#define B2056_RX_TIA_QMISC 0x52 +#define B2056_RX_TIA_GAIN 0x53 +#define B2056_RX_TIA_SPARE1 0x54 +#define B2056_RX_TIA_SPARE2 0x55 +#define B2056_RX_BB_LPF_MASTER 0x56 +#define B2056_RX_AACI_MASTER 0x57 +#define B2056_RX_RXLPF_IDAC 0x58 +#define B2056_RX_RXLPF_OPAMPBIAS_LOWQ 0x59 +#define B2056_RX_RXLPF_OPAMPBIAS_HIGHQ 0x5A +#define B2056_RX_RXLPF_BIAS_DCCANCEL 0x5B +#define B2056_RX_RXLPF_OUTVCM 0x5C +#define B2056_RX_RXLPF_INVCM_BODY 0x5D +#define B2056_RX_RXLPF_CC_OP 0x5E +#define B2056_RX_RXLPF_GAIN 0x5F +#define B2056_RX_RXLPF_Q_BW 0x60 +#define B2056_RX_RXLPF_HP_CORNER_BW 0x61 +#define B2056_RX_RXLPF_RCCAL_HPC 0x62 +#define B2056_RX_RXHPF_OFF0 0x63 +#define B2056_RX_RXHPF_OFF1 0x64 +#define B2056_RX_RXHPF_OFF2 0x65 +#define B2056_RX_RXHPF_OFF3 0x66 +#define B2056_RX_RXHPF_OFF4 0x67 +#define B2056_RX_RXHPF_OFF5 0x68 +#define B2056_RX_RXHPF_OFF6 0x69 +#define B2056_RX_RXHPF_OFF7 0x6A +#define B2056_RX_RXLPF_RCCAL_LPC 0x6B +#define B2056_RX_RXLPF_OFF_0 0x6C +#define B2056_RX_RXLPF_OFF_1 0x6D +#define B2056_RX_RXLPF_OFF_2 0x6E +#define B2056_RX_RXLPF_OFF_3 0x6F +#define B2056_RX_RXLPF_OFF_4 0x70 +#define B2056_RX_UNUSED 0x71 +#define B2056_RX_VGA_MASTER 0x72 +#define B2056_RX_VGA_BIAS 0x73 +#define B2056_RX_VGA_BIAS_DCCANCEL 0x74 +#define B2056_RX_VGA_GAIN 0x75 +#define B2056_RX_VGA_HP_CORNER_BW 0x76 +#define B2056_RX_VGABUF_BIAS 0x77 +#define B2056_RX_VGABUF_GAIN_BW 0x78 +#define B2056_RX_TXFBMIX_A 0x79 +#define B2056_RX_TXFBMIX_G 0x7A +#define B2056_RX_RXSPARE1 0x7B +#define B2056_RX_RXSPARE2 0x7C +#define B2056_RX_RXSPARE3 0x7D +#define B2056_RX_RXSPARE4 0x7E +#define B2056_RX_RXSPARE5 0x7F +#define B2056_RX_RXSPARE6 0x80 +#define B2056_RX_RXSPARE7 0x81 +#define B2056_RX_RXSPARE8 0x82 +#define B2056_RX_RXSPARE9 0x83 +#define B2056_RX_RXSPARE10 0x84 +#define B2056_RX_RXSPARE11 0x85 +#define B2056_RX_RXSPARE12 0x86 +#define B2056_RX_RXSPARE13 0x87 +#define B2056_RX_RXSPARE14 0x88 +#define B2056_RX_RXSPARE15 0x89 +#define B2056_RX_RXSPARE16 0x8A +#define B2056_RX_STATUS_LNAA_GAIN 0x8B +#define B2056_RX_STATUS_LNAG_GAIN 0x8C +#define B2056_RX_STATUS_MIXTIA_GAIN 0x8D +#define B2056_RX_STATUS_RXLPF_GAIN 0x8E +#define B2056_RX_STATUS_VGA_BUF_GAIN 0x8F +#define B2056_RX_STATUS_RXLPF_Q 0x90 +#define B2056_RX_STATUS_RXLPF_BUF_BW 0x91 +#define B2056_RX_STATUS_RXLPF_VGA_HPC 0x92 +#define B2056_RX_STATUS_RXLPF_RC 0x93 +#define B2056_RX_STATUS_HPC_RC 0x94 + +#define B2056_LNA1_A_PU 0x01 +#define B2056_LNA2_A_PU 0x02 +#define B2056_LNA1_G_PU 0x01 +#define B2056_LNA2_G_PU 0x02 +#define B2056_MIXA_PU_I 0x01 +#define B2056_MIXA_PU_Q 0x02 +#define B2056_MIXA_PU_GM 0x10 +#define B2056_MIXG_PU_I 0x01 +#define B2056_MIXG_PU_Q 0x02 +#define B2056_MIXG_PU_GM 0x10 +#define B2056_TIA_PU 0x01 +#define B2056_BB_LPF_PU 0x20 +#define B2056_W1_PU 0x02 +#define B2056_W2_PU 0x04 +#define B2056_NB_PU 0x08 +#define B2056_RSSI_W1_SEL 0x02 +#define B2056_RSSI_W2_SEL 0x04 +#define B2056_RSSI_NB_SEL 0x08 +#define B2056_VCM_MASK 0x1C +#define B2056_RSSI_VCM_SHIFT 0x02 + +#define B2056_SYN (0x0 << 12) +#define B2056_TX0 (0x2 << 12) +#define B2056_TX1 (0x3 << 12) +#define B2056_RX0 (0x6 << 12) +#define B2056_RX1 (0x7 << 12) +#define B2056_ALLTX (0xE << 12) +#define B2056_ALLRX (0xF << 12) + +#define B2056_SYN_RESERVED_ADDR0 0x00 +#define B2056_SYN_IDCODE 0x01 +#define B2056_SYN_RESERVED_ADDR2 0x02 +#define B2056_SYN_RESERVED_ADDR3 0x03 +#define B2056_SYN_RESERVED_ADDR4 0x04 +#define B2056_SYN_RESERVED_ADDR5 0x05 +#define B2056_SYN_RESERVED_ADDR6 0x06 +#define B2056_SYN_RESERVED_ADDR7 0x07 +#define B2056_SYN_COM_CTRL 0x08 +#define B2056_SYN_COM_PU 0x09 +#define B2056_SYN_COM_OVR 0x0A +#define B2056_SYN_COM_RESET 0x0B +#define B2056_SYN_COM_RCAL 0x0C +#define B2056_SYN_COM_RC_RXLPF 0x0D +#define B2056_SYN_COM_RC_TXLPF 0x0E +#define B2056_SYN_COM_RC_RXHPF 0x0F +#define B2056_SYN_RESERVED_ADDR16 0x10 +#define B2056_SYN_RESERVED_ADDR17 0x11 +#define B2056_SYN_RESERVED_ADDR18 0x12 +#define B2056_SYN_RESERVED_ADDR19 0x13 +#define B2056_SYN_RESERVED_ADDR20 0x14 +#define B2056_SYN_RESERVED_ADDR21 0x15 +#define B2056_SYN_RESERVED_ADDR22 0x16 +#define B2056_SYN_RESERVED_ADDR23 0x17 +#define B2056_SYN_RESERVED_ADDR24 0x18 +#define B2056_SYN_RESERVED_ADDR25 0x19 +#define B2056_SYN_RESERVED_ADDR26 0x1A +#define B2056_SYN_RESERVED_ADDR27 0x1B +#define B2056_SYN_RESERVED_ADDR28 0x1C +#define B2056_SYN_RESERVED_ADDR29 0x1D +#define B2056_SYN_RESERVED_ADDR30 0x1E +#define B2056_SYN_RESERVED_ADDR31 0x1F +#define B2056_SYN_GPIO_MASTER1 0x20 +#define B2056_SYN_GPIO_MASTER2 0x21 +#define B2056_SYN_TOPBIAS_MASTER 0x22 +#define B2056_SYN_TOPBIAS_RCAL 0x23 +#define B2056_SYN_AFEREG 0x24 +#define B2056_SYN_TEMPPROCSENSE 0x25 +#define B2056_SYN_TEMPPROCSENSEIDAC 0x26 +#define B2056_SYN_TEMPPROCSENSERCAL 0x27 +#define B2056_SYN_LPO 0x28 +#define B2056_SYN_VDDCAL_MASTER 0x29 +#define B2056_SYN_VDDCAL_IDAC 0x2A +#define B2056_SYN_VDDCAL_STATUS 0x2B +#define B2056_SYN_RCAL_MASTER 0x2C +#define B2056_SYN_RCAL_CODE_OUT 0x2D +#define B2056_SYN_RCCAL_CTRL0 0x2E +#define B2056_SYN_RCCAL_CTRL1 0x2F +#define B2056_SYN_RCCAL_CTRL2 0x30 +#define B2056_SYN_RCCAL_CTRL3 0x31 +#define B2056_SYN_RCCAL_CTRL4 0x32 +#define B2056_SYN_RCCAL_CTRL5 0x33 +#define B2056_SYN_RCCAL_CTRL6 0x34 +#define B2056_SYN_RCCAL_CTRL7 0x35 +#define B2056_SYN_RCCAL_CTRL8 0x36 +#define B2056_SYN_RCCAL_CTRL9 0x37 +#define B2056_SYN_RCCAL_CTRL10 0x38 +#define B2056_SYN_RCCAL_CTRL11 0x39 +#define B2056_SYN_ZCAL_SPARE1 0x3A +#define B2056_SYN_ZCAL_SPARE2 0x3B +#define B2056_SYN_PLL_MAST1 0x3C +#define B2056_SYN_PLL_MAST2 0x3D +#define B2056_SYN_PLL_MAST3 0x3E +#define B2056_SYN_PLL_BIAS_RESET 0x3F +#define B2056_SYN_PLL_XTAL0 0x40 +#define B2056_SYN_PLL_XTAL1 0x41 +#define B2056_SYN_PLL_XTAL3 0x42 +#define B2056_SYN_PLL_XTAL4 0x43 +#define B2056_SYN_PLL_XTAL5 0x44 +#define B2056_SYN_PLL_XTAL6 0x45 +#define B2056_SYN_PLL_REFDIV 0x46 +#define B2056_SYN_PLL_PFD 0x47 +#define B2056_SYN_PLL_CP1 0x48 +#define B2056_SYN_PLL_CP2 0x49 +#define B2056_SYN_PLL_CP3 0x4A +#define B2056_SYN_PLL_LOOPFILTER1 0x4B +#define B2056_SYN_PLL_LOOPFILTER2 0x4C +#define B2056_SYN_PLL_LOOPFILTER3 0x4D +#define B2056_SYN_PLL_LOOPFILTER4 0x4E +#define B2056_SYN_PLL_LOOPFILTER5 0x4F +#define B2056_SYN_PLL_MMD1 0x50 +#define B2056_SYN_PLL_MMD2 0x51 +#define B2056_SYN_PLL_VCO1 0x52 +#define B2056_SYN_PLL_VCO2 0x53 +#define B2056_SYN_PLL_MONITOR1 0x54 +#define B2056_SYN_PLL_MONITOR2 0x55 +#define B2056_SYN_PLL_VCOCAL1 0x56 +#define B2056_SYN_PLL_VCOCAL2 0x57 +#define B2056_SYN_PLL_VCOCAL4 0x58 +#define B2056_SYN_PLL_VCOCAL5 0x59 +#define B2056_SYN_PLL_VCOCAL6 0x5A +#define B2056_SYN_PLL_VCOCAL7 0x5B +#define B2056_SYN_PLL_VCOCAL8 0x5C +#define B2056_SYN_PLL_VCOCAL9 0x5D +#define B2056_SYN_PLL_VCOCAL10 0x5E +#define B2056_SYN_PLL_VCOCAL11 0x5F +#define B2056_SYN_PLL_VCOCAL12 0x60 +#define B2056_SYN_PLL_VCOCAL13 0x61 +#define B2056_SYN_PLL_VREG 0x62 +#define B2056_SYN_PLL_STATUS1 0x63 +#define B2056_SYN_PLL_STATUS2 0x64 +#define B2056_SYN_PLL_STATUS3 0x65 +#define B2056_SYN_LOGEN_PU0 0x66 +#define B2056_SYN_LOGEN_PU1 0x67 +#define B2056_SYN_LOGEN_PU2 0x68 +#define B2056_SYN_LOGEN_PU3 0x69 +#define B2056_SYN_LOGEN_PU5 0x6A +#define B2056_SYN_LOGEN_PU6 0x6B +#define B2056_SYN_LOGEN_PU7 0x6C +#define B2056_SYN_LOGEN_PU8 0x6D +#define B2056_SYN_LOGEN_BIAS_RESET 0x6E +#define B2056_SYN_LOGEN_RCCR1 0x6F +#define B2056_SYN_LOGEN_VCOBUF1 0x70 +#define B2056_SYN_LOGEN_MIXER1 0x71 +#define B2056_SYN_LOGEN_MIXER2 0x72 +#define B2056_SYN_LOGEN_BUF1 0x73 +#define B2056_SYN_LOGENBUF2 0x74 +#define B2056_SYN_LOGEN_BUF3 0x75 +#define B2056_SYN_LOGEN_BUF4 0x76 +#define B2056_SYN_LOGEN_DIV1 0x77 +#define B2056_SYN_LOGEN_DIV2 0x78 +#define B2056_SYN_LOGEN_DIV3 0x79 +#define B2056_SYN_LOGEN_ACL1 0x7A +#define B2056_SYN_LOGEN_ACL2 0x7B +#define B2056_SYN_LOGEN_ACL3 0x7C +#define B2056_SYN_LOGEN_ACL4 0x7D +#define B2056_SYN_LOGEN_ACL5 0x7E +#define B2056_SYN_LOGEN_ACL6 0x7F +#define B2056_SYN_LOGEN_ACLOUT 0x80 +#define B2056_SYN_LOGEN_ACLCAL1 0x81 +#define B2056_SYN_LOGEN_ACLCAL2 0x82 +#define B2056_SYN_LOGEN_ACLCAL3 0x83 +#define B2056_SYN_CALEN 0x84 +#define B2056_SYN_LOGEN_PEAKDET1 0x85 +#define B2056_SYN_LOGEN_CORE_ACL_OVR 0x86 +#define B2056_SYN_LOGEN_RX_DIFF_ACL_OVR 0x87 +#define B2056_SYN_LOGEN_TX_DIFF_ACL_OVR 0x88 +#define B2056_SYN_LOGEN_RX_CMOS_ACL_OVR 0x89 +#define B2056_SYN_LOGEN_TX_CMOS_ACL_OVR 0x8A +#define B2056_SYN_LOGEN_VCOBUF2 0x8B +#define B2056_SYN_LOGEN_MIXER3 0x8C +#define B2056_SYN_LOGEN_BUF5 0x8D +#define B2056_SYN_LOGEN_BUF6 0x8E +#define B2056_SYN_LOGEN_CBUFRX1 0x8F +#define B2056_SYN_LOGEN_CBUFRX2 0x90 +#define B2056_SYN_LOGEN_CBUFRX3 0x91 +#define B2056_SYN_LOGEN_CBUFRX4 0x92 +#define B2056_SYN_LOGEN_CBUFTX1 0x93 +#define B2056_SYN_LOGEN_CBUFTX2 0x94 +#define B2056_SYN_LOGEN_CBUFTX3 0x95 +#define B2056_SYN_LOGEN_CBUFTX4 0x96 +#define B2056_SYN_LOGEN_CMOSRX1 0x97 +#define B2056_SYN_LOGEN_CMOSRX2 0x98 +#define B2056_SYN_LOGEN_CMOSRX3 0x99 +#define B2056_SYN_LOGEN_CMOSRX4 0x9A +#define B2056_SYN_LOGEN_CMOSTX1 0x9B +#define B2056_SYN_LOGEN_CMOSTX2 0x9C +#define B2056_SYN_LOGEN_CMOSTX3 0x9D +#define B2056_SYN_LOGEN_CMOSTX4 0x9E +#define B2056_SYN_LOGEN_VCOBUF2_OVRVAL 0x9F +#define B2056_SYN_LOGEN_MIXER3_OVRVAL 0xA0 +#define B2056_SYN_LOGEN_BUF5_OVRVAL 0xA1 +#define B2056_SYN_LOGEN_BUF6_OVRVAL 0xA2 +#define B2056_SYN_LOGEN_CBUFRX1_OVRVAL 0xA3 +#define B2056_SYN_LOGEN_CBUFRX2_OVRVAL 0xA4 +#define B2056_SYN_LOGEN_CBUFRX3_OVRVAL 0xA5 +#define B2056_SYN_LOGEN_CBUFRX4_OVRVAL 0xA6 +#define B2056_SYN_LOGEN_CBUFTX1_OVRVAL 0xA7 +#define B2056_SYN_LOGEN_CBUFTX2_OVRVAL 0xA8 +#define B2056_SYN_LOGEN_CBUFTX3_OVRVAL 0xA9 +#define B2056_SYN_LOGEN_CBUFTX4_OVRVAL 0xAA +#define B2056_SYN_LOGEN_CMOSRX1_OVRVAL 0xAB +#define B2056_SYN_LOGEN_CMOSRX2_OVRVAL 0xAC +#define B2056_SYN_LOGEN_CMOSRX3_OVRVAL 0xAD +#define B2056_SYN_LOGEN_CMOSRX4_OVRVAL 0xAE +#define B2056_SYN_LOGEN_CMOSTX1_OVRVAL 0xAF +#define B2056_SYN_LOGEN_CMOSTX2_OVRVAL 0xB0 +#define B2056_SYN_LOGEN_CMOSTX3_OVRVAL 0xB1 +#define B2056_SYN_LOGEN_CMOSTX4_OVRVAL 0xB2 +#define B2056_SYN_LOGEN_ACL_WAITCNT 0xB3 +#define B2056_SYN_LOGEN_CORE_CALVALID 0xB4 +#define B2056_SYN_LOGEN_RX_CMOS_CALVALID 0xB5 +#define B2056_SYN_LOGEN_TX_CMOS_VALID 0xB6 + +#define B2056_TX_RESERVED_ADDR0 0x00 +#define B2056_TX_IDCODE 0x01 +#define B2056_TX_RESERVED_ADDR2 0x02 +#define B2056_TX_RESERVED_ADDR3 0x03 +#define B2056_TX_RESERVED_ADDR4 0x04 +#define B2056_TX_RESERVED_ADDR5 0x05 +#define B2056_TX_RESERVED_ADDR6 0x06 +#define B2056_TX_RESERVED_ADDR7 0x07 +#define B2056_TX_COM_CTRL 0x08 +#define B2056_TX_COM_PU 0x09 +#define B2056_TX_COM_OVR 0x0A +#define B2056_TX_COM_RESET 0x0B +#define B2056_TX_COM_RCAL 0x0C +#define B2056_TX_COM_RC_RXLPF 0x0D +#define B2056_TX_COM_RC_TXLPF 0x0E +#define B2056_TX_COM_RC_RXHPF 0x0F +#define B2056_TX_RESERVED_ADDR16 0x10 +#define B2056_TX_RESERVED_ADDR17 0x11 +#define B2056_TX_RESERVED_ADDR18 0x12 +#define B2056_TX_RESERVED_ADDR19 0x13 +#define B2056_TX_RESERVED_ADDR20 0x14 +#define B2056_TX_RESERVED_ADDR21 0x15 +#define B2056_TX_RESERVED_ADDR22 0x16 +#define B2056_TX_RESERVED_ADDR23 0x17 +#define B2056_TX_RESERVED_ADDR24 0x18 +#define B2056_TX_RESERVED_ADDR25 0x19 +#define B2056_TX_RESERVED_ADDR26 0x1A +#define B2056_TX_RESERVED_ADDR27 0x1B +#define B2056_TX_RESERVED_ADDR28 0x1C +#define B2056_TX_RESERVED_ADDR29 0x1D +#define B2056_TX_RESERVED_ADDR30 0x1E +#define B2056_TX_RESERVED_ADDR31 0x1F +#define B2056_TX_IQCAL_GAIN_BW 0x20 +#define B2056_TX_LOFT_FINE_I 0x21 +#define B2056_TX_LOFT_FINE_Q 0x22 +#define B2056_TX_LOFT_COARSE_I 0x23 +#define B2056_TX_LOFT_COARSE_Q 0x24 +#define B2056_TX_TX_COM_MASTER1 0x25 +#define B2056_TX_TX_COM_MASTER2 0x26 +#define B2056_TX_RXIQCAL_TXMUX 0x27 +#define B2056_TX_TX_SSI_MASTER 0x28 +#define B2056_TX_IQCAL_VCM_HG 0x29 +#define B2056_TX_IQCAL_IDAC 0x2A +#define B2056_TX_TSSI_VCM 0x2B +#define B2056_TX_TX_AMP_DET 0x2C +#define B2056_TX_TX_SSI_MUX 0x2D +#define B2056_TX_TSSIA 0x2E +#define B2056_TX_TSSIG 0x2F +#define B2056_TX_TSSI_MISC1 0x30 +#define B2056_TX_TSSI_MISC2 0x31 +#define B2056_TX_TSSI_MISC3 0x32 +#define B2056_TX_PA_SPARE1 0x33 +#define B2056_TX_PA_SPARE2 0x34 +#define B2056_TX_INTPAA_MASTER 0x35 +#define B2056_TX_INTPAA_GAIN 0x36 +#define B2056_TX_INTPAA_BOOST_TUNE 0x37 +#define B2056_TX_INTPAA_IAUX_STAT 0x38 +#define B2056_TX_INTPAA_IAUX_DYN 0x39 +#define B2056_TX_INTPAA_IMAIN_STAT 0x3A +#define B2056_TX_INTPAA_IMAIN_DYN 0x3B +#define B2056_TX_INTPAA_CASCBIAS 0x3C +#define B2056_TX_INTPAA_PASLOPE 0x3D +#define B2056_TX_INTPAA_PA_MISC 0x3E +#define B2056_TX_INTPAG_MASTER 0x3F +#define B2056_TX_INTPAG_GAIN 0x40 +#define B2056_TX_INTPAG_BOOST_TUNE 0x41 +#define B2056_TX_INTPAG_IAUX_STAT 0x42 +#define B2056_TX_INTPAG_IAUX_DYN 0x43 +#define B2056_TX_INTPAG_IMAIN_STAT 0x44 +#define B2056_TX_INTPAG_IMAIN_DYN 0x45 +#define B2056_TX_INTPAG_CASCBIAS 0x46 +#define B2056_TX_INTPAG_PASLOPE 0x47 +#define B2056_TX_INTPAG_PA_MISC 0x48 +#define B2056_TX_PADA_MASTER 0x49 +#define B2056_TX_PADA_IDAC 0x4A +#define B2056_TX_PADA_CASCBIAS 0x4B +#define B2056_TX_PADA_GAIN 0x4C +#define B2056_TX_PADA_BOOST_TUNE 0x4D +#define B2056_TX_PADA_SLOPE 0x4E +#define B2056_TX_PADG_MASTER 0x4F +#define B2056_TX_PADG_IDAC 0x50 +#define B2056_TX_PADG_CASCBIAS 0x51 +#define B2056_TX_PADG_GAIN 0x52 +#define B2056_TX_PADG_BOOST_TUNE 0x53 +#define B2056_TX_PADG_SLOPE 0x54 +#define B2056_TX_PGAA_MASTER 0x55 +#define B2056_TX_PGAA_IDAC 0x56 +#define B2056_TX_PGAA_GAIN 0x57 +#define B2056_TX_PGAA_BOOST_TUNE 0x58 +#define B2056_TX_PGAA_SLOPE 0x59 +#define B2056_TX_PGAA_MISC 0x5A +#define B2056_TX_PGAG_MASTER 0x5B +#define B2056_TX_PGAG_IDAC 0x5C +#define B2056_TX_PGAG_GAIN 0x5D +#define B2056_TX_PGAG_BOOST_TUNE 0x5E +#define B2056_TX_PGAG_SLOPE 0x5F +#define B2056_TX_PGAG_MISC 0x60 +#define B2056_TX_MIXA_MASTER 0x61 +#define B2056_TX_MIXA_BOOST_TUNE 0x62 +#define B2056_TX_MIXG 0x63 +#define B2056_TX_MIXG_BOOST_TUNE 0x64 +#define B2056_TX_BB_GM_MASTER 0x65 +#define B2056_TX_GMBB_GM 0x66 +#define B2056_TX_GMBB_IDAC 0x67 +#define B2056_TX_TXLPF_MASTER 0x68 +#define B2056_TX_TXLPF_RCCAL 0x69 +#define B2056_TX_TXLPF_RCCAL_OFF0 0x6A +#define B2056_TX_TXLPF_RCCAL_OFF1 0x6B +#define B2056_TX_TXLPF_RCCAL_OFF2 0x6C +#define B2056_TX_TXLPF_RCCAL_OFF3 0x6D +#define B2056_TX_TXLPF_RCCAL_OFF4 0x6E +#define B2056_TX_TXLPF_RCCAL_OFF5 0x6F +#define B2056_TX_TXLPF_RCCAL_OFF6 0x70 +#define B2056_TX_TXLPF_BW 0x71 +#define B2056_TX_TXLPF_GAIN 0x72 +#define B2056_TX_TXLPF_IDAC 0x73 +#define B2056_TX_TXLPF_IDAC_0 0x74 +#define B2056_TX_TXLPF_IDAC_1 0x75 +#define B2056_TX_TXLPF_IDAC_2 0x76 +#define B2056_TX_TXLPF_IDAC_3 0x77 +#define B2056_TX_TXLPF_IDAC_4 0x78 +#define B2056_TX_TXLPF_IDAC_5 0x79 +#define B2056_TX_TXLPF_IDAC_6 0x7A +#define B2056_TX_TXLPF_OPAMP_IDAC 0x7B +#define B2056_TX_TXLPF_MISC 0x7C +#define B2056_TX_TXSPARE1 0x7D +#define B2056_TX_TXSPARE2 0x7E +#define B2056_TX_TXSPARE3 0x7F +#define B2056_TX_TXSPARE4 0x80 +#define B2056_TX_TXSPARE5 0x81 +#define B2056_TX_TXSPARE6 0x82 +#define B2056_TX_TXSPARE7 0x83 +#define B2056_TX_TXSPARE8 0x84 +#define B2056_TX_TXSPARE9 0x85 +#define B2056_TX_TXSPARE10 0x86 +#define B2056_TX_TXSPARE11 0x87 +#define B2056_TX_TXSPARE12 0x88 +#define B2056_TX_TXSPARE13 0x89 +#define B2056_TX_TXSPARE14 0x8A +#define B2056_TX_TXSPARE15 0x8B +#define B2056_TX_TXSPARE16 0x8C +#define B2056_TX_STATUS_INTPA_GAIN 0x8D +#define B2056_TX_STATUS_PAD_GAIN 0x8E +#define B2056_TX_STATUS_PGA_GAIN 0x8F +#define B2056_TX_STATUS_GM_TXLPF_GAIN 0x90 +#define B2056_TX_STATUS_TXLPF_BW 0x91 +#define B2056_TX_STATUS_TXLPF_RC 0x92 +#define B2056_TX_GMBB_IDAC0 0x93 +#define B2056_TX_GMBB_IDAC1 0x94 +#define B2056_TX_GMBB_IDAC2 0x95 +#define B2056_TX_GMBB_IDAC3 0x96 +#define B2056_TX_GMBB_IDAC4 0x97 +#define B2056_TX_GMBB_IDAC5 0x98 +#define B2056_TX_GMBB_IDAC6 0x99 +#define B2056_TX_GMBB_IDAC7 0x9A + +#define B2056_RX_RESERVED_ADDR0 0x00 +#define B2056_RX_IDCODE 0x01 +#define B2056_RX_RESERVED_ADDR2 0x02 +#define B2056_RX_RESERVED_ADDR3 0x03 +#define B2056_RX_RESERVED_ADDR4 0x04 +#define B2056_RX_RESERVED_ADDR5 0x05 +#define B2056_RX_RESERVED_ADDR6 0x06 +#define B2056_RX_RESERVED_ADDR7 0x07 +#define B2056_RX_COM_CTRL 0x08 +#define B2056_RX_COM_PU 0x09 +#define B2056_RX_COM_OVR 0x0A +#define B2056_RX_COM_RESET 0x0B +#define B2056_RX_COM_RCAL 0x0C +#define B2056_RX_COM_RC_RXLPF 0x0D +#define B2056_RX_COM_RC_TXLPF 0x0E +#define B2056_RX_COM_RC_RXHPF 0x0F +#define B2056_RX_RESERVED_ADDR16 0x10 +#define B2056_RX_RESERVED_ADDR17 0x11 +#define B2056_RX_RESERVED_ADDR18 0x12 +#define B2056_RX_RESERVED_ADDR19 0x13 +#define B2056_RX_RESERVED_ADDR20 0x14 +#define B2056_RX_RESERVED_ADDR21 0x15 +#define B2056_RX_RESERVED_ADDR22 0x16 +#define B2056_RX_RESERVED_ADDR23 0x17 +#define B2056_RX_RESERVED_ADDR24 0x18 +#define B2056_RX_RESERVED_ADDR25 0x19 +#define B2056_RX_RESERVED_ADDR26 0x1A +#define B2056_RX_RESERVED_ADDR27 0x1B +#define B2056_RX_RESERVED_ADDR28 0x1C +#define B2056_RX_RESERVED_ADDR29 0x1D +#define B2056_RX_RESERVED_ADDR30 0x1E +#define B2056_RX_RESERVED_ADDR31 0x1F +#define B2056_RX_RXIQCAL_RXMUX 0x20 +#define B2056_RX_RSSI_PU 0x21 +#define B2056_RX_RSSI_SEL 0x22 +#define B2056_RX_RSSI_GAIN 0x23 +#define B2056_RX_RSSI_NB_IDAC 0x24 +#define B2056_RX_RSSI_WB2I_IDAC_1 0x25 +#define B2056_RX_RSSI_WB2I_IDAC_2 0x26 +#define B2056_RX_RSSI_WB2Q_IDAC_1 0x27 +#define B2056_RX_RSSI_WB2Q_IDAC_2 0x28 +#define B2056_RX_RSSI_POLE 0x29 +#define B2056_RX_RSSI_WB1_IDAC 0x2A +#define B2056_RX_RSSI_MISC 0x2B +#define B2056_RX_LNAA_MASTER 0x2C +#define B2056_RX_LNAA_TUNE 0x2D +#define B2056_RX_LNAA_GAIN 0x2E +#define B2056_RX_LNA_A_SLOPE 0x2F +#define B2056_RX_BIASPOLE_LNAA1_IDAC 0x30 +#define B2056_RX_LNAA2_IDAC 0x31 +#define B2056_RX_LNA1A_MISC 0x32 +#define B2056_RX_LNAG_MASTER 0x33 +#define B2056_RX_LNAG_TUNE 0x34 +#define B2056_RX_LNAG_GAIN 0x35 +#define B2056_RX_LNA_G_SLOPE 0x36 +#define B2056_RX_BIASPOLE_LNAG1_IDAC 0x37 +#define B2056_RX_LNAG2_IDAC 0x38 +#define B2056_RX_LNA1G_MISC 0x39 +#define B2056_RX_MIXA_MASTER 0x3A +#define B2056_RX_MIXA_VCM 0x3B +#define B2056_RX_MIXA_CTRLPTAT 0x3C +#define B2056_RX_MIXA_LOB_BIAS 0x3D +#define B2056_RX_MIXA_CORE_IDAC 0x3E +#define B2056_RX_MIXA_CMFB_IDAC 0x3F +#define B2056_RX_MIXA_BIAS_AUX 0x40 +#define B2056_RX_MIXA_BIAS_MAIN 0x41 +#define B2056_RX_MIXA_BIAS_MISC 0x42 +#define B2056_RX_MIXA_MAST_BIAS 0x43 +#define B2056_RX_MIXG_MASTER 0x44 +#define B2056_RX_MIXG_VCM 0x45 +#define B2056_RX_MIXG_CTRLPTAT 0x46 +#define B2056_RX_MIXG_LOB_BIAS 0x47 +#define B2056_RX_MIXG_CORE_IDAC 0x48 +#define B2056_RX_MIXG_CMFB_IDAC 0x49 +#define B2056_RX_MIXG_BIAS_AUX 0x4A +#define B2056_RX_MIXG_BIAS_MAIN 0x4B +#define B2056_RX_MIXG_BIAS_MISC 0x4C +#define B2056_RX_MIXG_MAST_BIAS 0x4D +#define B2056_RX_TIA_MASTER 0x4E +#define B2056_RX_TIA_IOPAMP 0x4F +#define B2056_RX_TIA_QOPAMP 0x50 +#define B2056_RX_TIA_IMISC 0x51 +#define B2056_RX_TIA_QMISC 0x52 +#define B2056_RX_TIA_GAIN 0x53 +#define B2056_RX_TIA_SPARE1 0x54 +#define B2056_RX_TIA_SPARE2 0x55 +#define B2056_RX_BB_LPF_MASTER 0x56 +#define B2056_RX_AACI_MASTER 0x57 +#define B2056_RX_RXLPF_IDAC 0x58 +#define B2056_RX_RXLPF_OPAMPBIAS_LOWQ 0x59 +#define B2056_RX_RXLPF_OPAMPBIAS_HIGHQ 0x5A +#define B2056_RX_RXLPF_BIAS_DCCANCEL 0x5B +#define B2056_RX_RXLPF_OUTVCM 0x5C +#define B2056_RX_RXLPF_INVCM_BODY 0x5D +#define B2056_RX_RXLPF_CC_OP 0x5E +#define B2056_RX_RXLPF_GAIN 0x5F +#define B2056_RX_RXLPF_Q_BW 0x60 +#define B2056_RX_RXLPF_HP_CORNER_BW 0x61 +#define B2056_RX_RXLPF_RCCAL_HPC 0x62 +#define B2056_RX_RXHPF_OFF0 0x63 +#define B2056_RX_RXHPF_OFF1 0x64 +#define B2056_RX_RXHPF_OFF2 0x65 +#define B2056_RX_RXHPF_OFF3 0x66 +#define B2056_RX_RXHPF_OFF4 0x67 +#define B2056_RX_RXHPF_OFF5 0x68 +#define B2056_RX_RXHPF_OFF6 0x69 +#define B2056_RX_RXHPF_OFF7 0x6A +#define B2056_RX_RXLPF_RCCAL_LPC 0x6B +#define B2056_RX_RXLPF_OFF_0 0x6C +#define B2056_RX_RXLPF_OFF_1 0x6D +#define B2056_RX_RXLPF_OFF_2 0x6E +#define B2056_RX_RXLPF_OFF_3 0x6F +#define B2056_RX_RXLPF_OFF_4 0x70 +#define B2056_RX_UNUSED 0x71 +#define B2056_RX_VGA_MASTER 0x72 +#define B2056_RX_VGA_BIAS 0x73 +#define B2056_RX_VGA_BIAS_DCCANCEL 0x74 +#define B2056_RX_VGA_GAIN 0x75 +#define B2056_RX_VGA_HP_CORNER_BW 0x76 +#define B2056_RX_VGABUF_BIAS 0x77 +#define B2056_RX_VGABUF_GAIN_BW 0x78 +#define B2056_RX_TXFBMIX_A 0x79 +#define B2056_RX_TXFBMIX_G 0x7A +#define B2056_RX_RXSPARE1 0x7B +#define B2056_RX_RXSPARE2 0x7C +#define B2056_RX_RXSPARE3 0x7D +#define B2056_RX_RXSPARE4 0x7E +#define B2056_RX_RXSPARE5 0x7F +#define B2056_RX_RXSPARE6 0x80 +#define B2056_RX_RXSPARE7 0x81 +#define B2056_RX_RXSPARE8 0x82 +#define B2056_RX_RXSPARE9 0x83 +#define B2056_RX_RXSPARE10 0x84 +#define B2056_RX_RXSPARE11 0x85 +#define B2056_RX_RXSPARE12 0x86 +#define B2056_RX_RXSPARE13 0x87 +#define B2056_RX_RXSPARE14 0x88 +#define B2056_RX_RXSPARE15 0x89 +#define B2056_RX_RXSPARE16 0x8A +#define B2056_RX_STATUS_LNAA_GAIN 0x8B +#define B2056_RX_STATUS_LNAG_GAIN 0x8C +#define B2056_RX_STATUS_MIXTIA_GAIN 0x8D +#define B2056_RX_STATUS_RXLPF_GAIN 0x8E +#define B2056_RX_STATUS_VGA_BUF_GAIN 0x8F +#define B2056_RX_STATUS_RXLPF_Q 0x90 +#define B2056_RX_STATUS_RXLPF_BUF_BW 0x91 +#define B2056_RX_STATUS_RXLPF_VGA_HPC 0x92 +#define B2056_RX_STATUS_RXLPF_RC 0x93 +#define B2056_RX_STATUS_HPC_RC 0x94 + +#define B2056_LNA1_A_PU 0x01 +#define B2056_LNA2_A_PU 0x02 +#define B2056_LNA1_G_PU 0x01 +#define B2056_LNA2_G_PU 0x02 +#define B2056_MIXA_PU_I 0x01 +#define B2056_MIXA_PU_Q 0x02 +#define B2056_MIXA_PU_GM 0x10 +#define B2056_MIXG_PU_I 0x01 +#define B2056_MIXG_PU_Q 0x02 +#define B2056_MIXG_PU_GM 0x10 +#define B2056_TIA_PU 0x01 +#define B2056_BB_LPF_PU 0x20 +#define B2056_W1_PU 0x02 +#define B2056_W2_PU 0x04 +#define B2056_NB_PU 0x08 +#define B2056_RSSI_W1_SEL 0x02 +#define B2056_RSSI_W2_SEL 0x04 +#define B2056_RSSI_NB_SEL 0x08 +#define B2056_VCM_MASK 0x1C +#define B2056_RSSI_VCM_SHIFT 0x02 + +struct bwn_nphy_channeltab_entry_rev3 { + /* The channel frequency in MHz */ + uint16_t freq; + /* Radio register values on channelswitch */ + uint8_t radio_syn_pll_vcocal1; + uint8_t radio_syn_pll_vcocal2; + uint8_t radio_syn_pll_refdiv; + uint8_t radio_syn_pll_mmd2; + uint8_t radio_syn_pll_mmd1; + uint8_t radio_syn_pll_loopfilter1; + uint8_t radio_syn_pll_loopfilter2; + uint8_t radio_syn_pll_loopfilter3; + uint8_t radio_syn_pll_loopfilter4; + uint8_t radio_syn_pll_loopfilter5; + uint8_t radio_syn_reserved_addr27; + uint8_t radio_syn_reserved_addr28; + uint8_t radio_syn_reserved_addr29; + uint8_t radio_syn_logen_vcobuf1; + uint8_t radio_syn_logen_mixer2; + uint8_t radio_syn_logen_buf3; + uint8_t radio_syn_logen_buf4; + uint8_t radio_rx0_lnaa_tune; + uint8_t radio_rx0_lnag_tune; + uint8_t radio_tx0_intpaa_boost_tune; + uint8_t radio_tx0_intpag_boost_tune; + uint8_t radio_tx0_pada_boost_tune; + uint8_t radio_tx0_padg_boost_tune; + uint8_t radio_tx0_pgaa_boost_tune; + uint8_t radio_tx0_pgag_boost_tune; + uint8_t radio_tx0_mixa_boost_tune; + uint8_t radio_tx0_mixg_boost_tune; + uint8_t radio_rx1_lnaa_tune; + uint8_t radio_rx1_lnag_tune; + uint8_t radio_tx1_intpaa_boost_tune; + uint8_t radio_tx1_intpag_boost_tune; + uint8_t radio_tx1_pada_boost_tune; + uint8_t radio_tx1_padg_boost_tune; + uint8_t radio_tx1_pgaa_boost_tune; + uint8_t radio_tx1_pgag_boost_tune; + uint8_t radio_tx1_mixa_boost_tune; + uint8_t radio_tx1_mixg_boost_tune; + /* PHY register values on channelswitch */ + struct bwn_phy_n_sfo_cfg phy_regs; +}; + +void b2056_upload_inittabs(struct bwn_mac *mac, + bool ghz5, bool ignore_uploadflag); +void b2056_upload_syn_pll_cp2(struct bwn_mac *mac, bool ghz5); + +/* Get the NPHY Channel Switch Table entry for a channel. + * Returns NULL on failure to find an entry. */ +const struct bwn_nphy_channeltab_entry_rev3 * +bwn_nphy_get_chantabent_rev3(struct bwn_mac *mac, uint16_t freq); + +#endif /* __IF_BWN_RADIO_2056_H__ */ diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2057.c b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2057.c new file mode 100644 index 0000000..156514f --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2057.c @@ -0,0 +1,701 @@ + +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * The Broadcom Wireless LAN controller driver. + */ + +#include "opt_wlan.h" +#include "opt_bwn.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/endian.h> +#include <sys/errno.h> +#include <sys/firmware.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/socket.h> +#include <sys/sockio.h> + +#include <net/ethernet.h> +#include <net/if.h> +#include <net/if_var.h> +#include <net/if_arp.h> +#include <net/if_dl.h> +#include <net/if_llc.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <dev/pci/pcivar.h> +#include <dev/pci/pcireg.h> +#include <dev/siba/siba_ids.h> +#include <dev/siba/sibareg.h> +#include <dev/siba/sibavar.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> +#include <net80211/ieee80211_regdomain.h> +#include <net80211/ieee80211_phy.h> +#include <net80211/ieee80211_ratectl.h> + +#include <dev/bwn/if_bwnreg.h> +#include <dev/bwn/if_bwnvar.h> +#include <dev/bwn/if_bwn_debug.h> + +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_regs.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.h> +#include <gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h> +#include <gnu/dev/bwn/phy_n/if_bwn_radio_2057.h> + +static uint16_t r2057_rev4_init[][2] = { + { 0x0E, 0x20 }, { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, + { 0x35, 0x26 }, { 0x3C, 0xff }, { 0x3D, 0xff }, { 0x3E, 0xff }, + { 0x3F, 0xff }, { 0x62, 0x33 }, { 0x8A, 0xf0 }, { 0x8B, 0x10 }, + { 0x8C, 0xf0 }, { 0x91, 0x3f }, { 0x92, 0x36 }, { 0xA4, 0x8c }, + { 0xA8, 0x55 }, { 0xAF, 0x01 }, { 0x10F, 0xf0 }, { 0x110, 0x10 }, + { 0x111, 0xf0 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x129, 0x8c }, + { 0x12D, 0x55 }, { 0x134, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, + { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, + { 0x169, 0x02 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, + { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, + { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, +}; + +static uint16_t r2057_rev5_init[][2] = { + { 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 }, + { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, + { 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, + { 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 }, + { 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 }, + { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f }, + { 0x117, 0x36 }, { 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, + { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, + { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, + { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, + { 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 }, { 0x1C2, 0x80 }, +}; + +static uint16_t r2057_rev5a_init[][2] = { + { 0x00, 0x15 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 }, + { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, + { 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, + { 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 }, + { 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 }, + { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f }, + { 0x117, 0x36 }, { 0x126, 0x20 }, { 0x14E, 0x01 }, { 0x15E, 0x00 }, + { 0x15F, 0x00 }, { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, + { 0x163, 0x00 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, + { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, + { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 }, + { 0x1C2, 0x80 }, +}; + +static uint16_t r2057_rev7_init[][2] = { + { 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 }, + { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 }, + { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x13 }, + { 0x66, 0xee }, { 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 }, + { 0x7C, 0x14 }, { 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f }, + { 0x92, 0x36 }, { 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, + { 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x13 }, { 0xEB, 0xee }, + { 0xF3, 0x58 }, { 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x14 }, + { 0x102, 0xee }, { 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 }, + { 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 }, + { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 }, + { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, + { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, + { 0x1B7, 0x05 }, { 0x1C2, 0xa0 }, +}; + +/* TODO: Which devices should use it? +static uint16_t r2057_rev8_init[][2] = { + { 0x00, 0x08 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 }, + { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 }, + { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x0f }, + { 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 }, { 0x7C, 0x0f }, + { 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 }, + { 0xA1, 0x20 }, { 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, + { 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0xF3, 0x58 }, + { 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x0f }, { 0x102, 0xee }, + { 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x126, 0x20 }, + { 0x14E, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 }, + { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 }, + { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, + { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, + { 0x1B7, 0x05 }, { 0x1C2, 0xa0 }, +}; +*/ + +/* Extracted from MMIO dump of 6.30.223.141 */ +static uint16_t r2057_rev9_init[][2] = { + { 0x27, 0x1f }, { 0x28, 0x0a }, { 0x29, 0x2f }, { 0x42, 0x1f }, + { 0x48, 0x3f }, { 0x5c, 0x41 }, { 0x63, 0x14 }, { 0x64, 0x12 }, + { 0x66, 0xff }, { 0x74, 0xa3 }, { 0x7b, 0x14 }, { 0x7c, 0x14 }, + { 0x7d, 0xee }, { 0x86, 0xc0 }, { 0xc4, 0x10 }, { 0xc9, 0x01 }, + { 0xe1, 0x41 }, { 0xe8, 0x14 }, { 0xe9, 0x12 }, { 0xeb, 0xff }, + { 0xf5, 0x0a }, { 0xf8, 0x09 }, { 0xf9, 0xa3 }, { 0x100, 0x14 }, + { 0x101, 0x10 }, { 0x102, 0xee }, { 0x10b, 0xc0 }, { 0x149, 0x10 }, + { 0x14e, 0x01 }, { 0x1b7, 0x05 }, { 0x1c2, 0xa0 }, +}; + +/* Extracted from MMIO dump of 6.30.223.248 */ +static uint16_t r2057_rev14_init[][2] = { + { 0x011, 0xfc }, { 0x030, 0x24 }, { 0x040, 0x1c }, { 0x082, 0x08 }, + { 0x0b4, 0x44 }, { 0x0c8, 0x01 }, { 0x0c9, 0x01 }, { 0x107, 0x08 }, + { 0x14d, 0x01 }, { 0x14e, 0x01 }, { 0x1af, 0x40 }, { 0x1b0, 0x40 }, + { 0x1cc, 0x01 }, { 0x1cf, 0x10 }, { 0x1d0, 0x0f }, { 0x1d3, 0x10 }, + { 0x1d4, 0x0f }, +}; + +#define RADIOREGS7(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ + r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ + r20, r21, r22, r23, r24, r25, r26, r27) \ + .radio_vcocal_countval0 = r00, \ + .radio_vcocal_countval1 = r01, \ + .radio_rfpll_refmaster_sparextalsize = r02, \ + .radio_rfpll_loopfilter_r1 = r03, \ + .radio_rfpll_loopfilter_c2 = r04, \ + .radio_rfpll_loopfilter_c1 = r05, \ + .radio_cp_kpd_idac = r06, \ + .radio_rfpll_mmd0 = r07, \ + .radio_rfpll_mmd1 = r08, \ + .radio_vcobuf_tune = r09, \ + .radio_logen_mx2g_tune = r10, \ + .radio_logen_mx5g_tune = r11, \ + .radio_logen_indbuf2g_tune = r12, \ + .radio_logen_indbuf5g_tune = r13, \ + .radio_txmix2g_tune_boost_pu_core0 = r14, \ + .radio_pad2g_tune_pus_core0 = r15, \ + .radio_pga_boost_tune_core0 = r16, \ + .radio_txmix5g_boost_tune_core0 = r17, \ + .radio_pad5g_tune_misc_pus_core0 = r18, \ + .radio_lna2g_tune_core0 = r19, \ + .radio_lna5g_tune_core0 = r20, \ + .radio_txmix2g_tune_boost_pu_core1 = r21, \ + .radio_pad2g_tune_pus_core1 = r22, \ + .radio_pga_boost_tune_core1 = r23, \ + .radio_txmix5g_boost_tune_core1 = r24, \ + .radio_pad5g_tune_misc_pus_core1 = r25, \ + .radio_lna2g_tune_core1 = r26, \ + .radio_lna5g_tune_core1 = r27 + +#define RADIOREGS7_2G(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ + r10, r11, r12, r13, r14, r15, r16, r17) \ + .radio_vcocal_countval0 = r00, \ + .radio_vcocal_countval1 = r01, \ + .radio_rfpll_refmaster_sparextalsize = r02, \ + .radio_rfpll_loopfilter_r1 = r03, \ + .radio_rfpll_loopfilter_c2 = r04, \ + .radio_rfpll_loopfilter_c1 = r05, \ + .radio_cp_kpd_idac = r06, \ + .radio_rfpll_mmd0 = r07, \ + .radio_rfpll_mmd1 = r08, \ + .radio_vcobuf_tune = r09, \ + .radio_logen_mx2g_tune = r10, \ + .radio_logen_indbuf2g_tune = r11, \ + .radio_txmix2g_tune_boost_pu_core0 = r12, \ + .radio_pad2g_tune_pus_core0 = r13, \ + .radio_lna2g_tune_core0 = r14, \ + .radio_txmix2g_tune_boost_pu_core1 = r15, \ + .radio_pad2g_tune_pus_core1 = r16, \ + .radio_lna2g_tune_core1 = r17 + +#define PHYREGS(r0, r1, r2, r3, r4, r5) \ + .phy_regs.phy_bw1a = r0, \ + .phy_regs.phy_bw2 = r1, \ + .phy_regs.phy_bw3 = r2, \ + .phy_regs.phy_bw4 = r3, \ + .phy_regs.phy_bw5 = r4, \ + .phy_regs.phy_bw6 = r5 + +/* Copied from brcmsmac (5.75.11): chan_info_nphyrev8_2057_rev5 */ +static const struct bwn_nphy_chantabent_rev7_2g bwn_nphy_chantab_phy_rev8_radio_rev5[] = { + { + .freq = 2412, + RADIOREGS7_2G(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, + 0x09, 0x0d, 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, + 0x03, 0xff), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { + .freq = 2417, + RADIOREGS7_2G(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, + 0x09, 0x0d, 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, + 0x03, 0xff), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { + .freq = 2422, + RADIOREGS7_2G(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, + 0x09, 0x0d, 0x08, 0x0e, 0x61, 0x03, 0xef, 0x61, + 0x03, 0xef), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { + .freq = 2427, + RADIOREGS7_2G(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, + 0x09, 0x0c, 0x08, 0x0e, 0x61, 0x03, 0xdf, 0x61, + 0x03, 0xdf), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { + .freq = 2432, + RADIOREGS7_2G(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, + 0x09, 0x0c, 0x07, 0x0d, 0x61, 0x03, 0xcf, 0x61, + 0x03, 0xcf), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { + .freq = 2437, + RADIOREGS7_2G(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, + 0x09, 0x0c, 0x07, 0x0d, 0x61, 0x03, 0xbf, 0x61, + 0x03, 0xbf), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { + .freq = 2442, + RADIOREGS7_2G(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, + 0x09, 0x0b, 0x07, 0x0d, 0x61, 0x03, 0xaf, 0x61, + 0x03, 0xaf), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { + .freq = 2447, + RADIOREGS7_2G(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, + 0x09, 0x0b, 0x07, 0x0d, 0x61, 0x03, 0x9f, 0x61, + 0x03, 0x9f), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { + .freq = 2452, + RADIOREGS7_2G(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, + 0x09, 0x0b, 0x07, 0x0d, 0x61, 0x03, 0x8f, 0x61, + 0x03, 0x8f), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { + .freq = 2457, + RADIOREGS7_2G(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, + 0x09, 0x0b, 0x07, 0x0c, 0x61, 0x03, 0x7f, 0x61, + 0x03, 0x7f), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { + .freq = 2462, + RADIOREGS7_2G(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, + 0x09, 0x0b, 0x07, 0x0c, 0x61, 0x03, 0x6f, 0x61, + 0x03, 0x6f), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, + { + .freq = 2467, + RADIOREGS7_2G(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, + 0x09, 0x0b, 0x06, 0x0c, 0x61, 0x03, 0x5f, 0x61, + 0x03, 0x5f), + PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), + }, + { + .freq = 2472, + RADIOREGS7_2G(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, + 0x09, 0x0a, 0x06, 0x0b, 0x61, 0x03, 0x4f, 0x61, + 0x03, 0x4f), + PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), + }, + { + .freq = 2484, + RADIOREGS7_2G(0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, + 0x09, 0x0a, 0x06, 0x0b, 0x61, 0x03, 0x3f, 0x61, + 0x03, 0x3f), + PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), + } +}; + +/* Extracted from MMIO dump of 6.30.223.248 */ +static const struct bwn_nphy_chantabent_rev7_2g bwn_nphy_chantab_phy_rev17_radio_rev14[] = { + { + .freq = 2412, + RADIOREGS7_2G(0x48, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x6c, + 0x09, 0x0d, 0x09, 0x03, 0x21, 0x53, 0xff, 0x21, + 0x53, 0xff), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { + .freq = 2417, + RADIOREGS7_2G(0x4b, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x71, + 0x09, 0x0d, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, + 0x53, 0xff), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { + .freq = 2422, + RADIOREGS7_2G(0x4e, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x76, + 0x09, 0x0d, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, + 0x53, 0xff), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { + .freq = 2427, + RADIOREGS7_2G(0x52, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x7b, + 0x09, 0x0c, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, + 0x53, 0xff), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { + .freq = 2432, + RADIOREGS7_2G(0x55, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x80, + 0x09, 0x0c, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, + 0x53, 0xff), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { + .freq = 2437, + RADIOREGS7_2G(0x58, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x85, + 0x09, 0x0c, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, + 0x53, 0xff), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { + .freq = 2442, + RADIOREGS7_2G(0x5c, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x8a, + 0x09, 0x0c, 0x08, 0x03, 0x21, 0x43, 0xff, 0x21, + 0x43, 0xff), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { + .freq = 2447, + RADIOREGS7_2G(0x5f, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x8f, + 0x09, 0x0c, 0x08, 0x03, 0x21, 0x43, 0xff, 0x21, + 0x43, 0xff), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { + .freq = 2452, + RADIOREGS7_2G(0x62, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x94, + 0x09, 0x0c, 0x08, 0x03, 0x21, 0x43, 0xff, 0x21, + 0x43, 0xff), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { + .freq = 2457, + RADIOREGS7_2G(0x66, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x99, + 0x09, 0x0b, 0x07, 0x03, 0x21, 0x43, 0xff, 0x21, + 0x43, 0xff), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { + .freq = 2462, + RADIOREGS7_2G(0x69, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x9e, + 0x09, 0x0b, 0x07, 0x03, 0x01, 0x43, 0xff, 0x01, + 0x43, 0xff), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, +}; + +/* Extracted from MMIO dump of 6.30.223.141 */ +static const struct bwn_nphy_chantabent_rev7 bwn_nphy_chantab_phy_rev16_radio_rev9[] = { + { + .freq = 2412, + RADIOREGS7(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, + 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), + }, + { + .freq = 2417, + RADIOREGS7(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, + 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), + }, + { + .freq = 2422, + RADIOREGS7(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, + 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), + }, + { + .freq = 2427, + RADIOREGS7(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, + 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), + }, + { + .freq = 2432, + RADIOREGS7(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, + 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), + }, + { + .freq = 2437, + RADIOREGS7(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, + 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), + }, + { + .freq = 2442, + RADIOREGS7(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, + 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), + }, + { + .freq = 2447, + RADIOREGS7(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, + 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), + }, + { + .freq = 2452, + RADIOREGS7(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, + 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), + }, + { + .freq = 2457, + RADIOREGS7(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, + 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), + }, + { + .freq = 2462, + RADIOREGS7(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, + 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x41, 0x63, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, + 0x00, 0x00, 0xf0, 0x00), + PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), + }, + { + .freq = 5180, + RADIOREGS7(0xbe, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x06, + 0x02, 0x0e, 0x00, 0x0e, 0x00, 0x9e, 0x00, 0x00, + 0x9f, 0x2f, 0xa3, 0x00, 0xfc, 0x00, 0x00, 0x4f, + 0x3a, 0x83, 0x00, 0xfc), + PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), + }, + { + .freq = 5200, + RADIOREGS7(0xc5, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x08, + 0x02, 0x0e, 0x00, 0x0e, 0x00, 0x9e, 0x00, 0x00, + 0x7f, 0x2f, 0x83, 0x00, 0xf8, 0x00, 0x00, 0x4c, + 0x4a, 0x83, 0x00, 0xf8), + PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), + }, + { + .freq = 5220, + RADIOREGS7(0xcc, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x0a, + 0x02, 0x0e, 0x00, 0x0e, 0x00, 0x9e, 0x00, 0x00, + 0x6d, 0x3d, 0x83, 0x00, 0xf8, 0x00, 0x00, 0x2d, + 0x2a, 0x73, 0x00, 0xf8), + PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), + }, + { + .freq = 5240, + RADIOREGS7(0xd2, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x0c, + 0x02, 0x0d, 0x00, 0x0d, 0x00, 0x8d, 0x00, 0x00, + 0x4d, 0x1c, 0x73, 0x00, 0xf8, 0x00, 0x00, 0x4d, + 0x2b, 0x73, 0x00, 0xf8), + PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), + }, + { + .freq = 5745, + RADIOREGS7(0x7b, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x7d, + 0x04, 0x08, 0x00, 0x06, 0x00, 0x15, 0x00, 0x00, + 0x08, 0x03, 0x03, 0x00, 0x30, 0x00, 0x00, 0x06, + 0x02, 0x03, 0x00, 0x30), + PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), + }, + { + .freq = 5765, + RADIOREGS7(0x81, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x81, + 0x04, 0x08, 0x00, 0x06, 0x00, 0x15, 0x00, 0x00, + 0x06, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, + 0x02, 0x03, 0x00, 0x00), + PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), + }, + { + .freq = 5785, + RADIOREGS7(0x88, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x85, + 0x04, 0x08, 0x00, 0x06, 0x00, 0x15, 0x00, 0x00, + 0x08, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, + 0x21, 0x03, 0x00, 0x00), + PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), + }, + { + .freq = 5805, + RADIOREGS7(0x8f, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x89, + 0x04, 0x07, 0x00, 0x06, 0x00, 0x04, 0x00, 0x00, + 0x06, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, + 0x00, 0x03, 0x00, 0x00), + PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), + }, + { + .freq = 5825, + RADIOREGS7(0x95, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x8d, + 0x04, 0x07, 0x00, 0x05, 0x00, 0x03, 0x00, 0x00, + 0x05, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, + 0x00, 0x03, 0x00, 0x00), + PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), + }, +}; + +void r2057_upload_inittabs(struct bwn_mac *mac) +{ + struct bwn_phy *phy = &mac->mac_phy; + uint16_t *table = NULL; + uint16_t size, i; + + switch (phy->rev) { + case 7: + table = r2057_rev4_init[0]; + size = nitems(r2057_rev4_init); + break; + case 8: + if (phy->rf_rev == 5) { + table = r2057_rev5_init[0]; + size = nitems(r2057_rev5_init); + } else if (phy->rf_rev == 7) { + table = r2057_rev7_init[0]; + size = nitems(r2057_rev7_init); + } + break; + case 9: + if (phy->rf_rev == 5) { + table = r2057_rev5a_init[0]; + size = nitems(r2057_rev5a_init); + } + break; + case 16: + if (phy->rf_rev == 9) { + table = r2057_rev9_init[0]; + size = nitems(r2057_rev9_init); + } + break; + case 17: + if (phy->rf_rev == 14) { + table = r2057_rev14_init[0]; + size = nitems(r2057_rev14_init); + } + break; + } + + if (! table) { + device_printf(mac->mac_sc->sc_dev, + "%s: couldn't find a suitable table (phy ref=%d, rf_ref=%d)\n", + __func__, + phy->rev, + phy->rf_rev); + } + + if (table) { + for (i = 0; i < size; i++, table += 2) + BWN_RF_WRITE(mac, table[0], table[1]); + } +} + +void r2057_get_chantabent_rev7(struct bwn_mac *mac, uint16_t freq, + const struct bwn_nphy_chantabent_rev7 **tabent_r7, + const struct bwn_nphy_chantabent_rev7_2g **tabent_r7_2g) +{ + struct bwn_phy *phy = &mac->mac_phy; + const struct bwn_nphy_chantabent_rev7 *e_r7 = NULL; + const struct bwn_nphy_chantabent_rev7_2g *e_r7_2g = NULL; + unsigned int len, i; + + *tabent_r7 = NULL; + *tabent_r7_2g = NULL; + + switch (phy->rev) { + case 8: + if (phy->rf_rev == 5) { + e_r7_2g = bwn_nphy_chantab_phy_rev8_radio_rev5; + len = nitems(bwn_nphy_chantab_phy_rev8_radio_rev5); + } + break; + case 16: + if (phy->rf_rev == 9) { + e_r7 = bwn_nphy_chantab_phy_rev16_radio_rev9; + len = nitems(bwn_nphy_chantab_phy_rev16_radio_rev9); + } + break; + case 17: + if (phy->rf_rev == 14) { + e_r7_2g = bwn_nphy_chantab_phy_rev17_radio_rev14; + len = nitems(bwn_nphy_chantab_phy_rev17_radio_rev14); + } + break; + default: + break; + } + + if (e_r7) { + for (i = 0; i < len; i++, e_r7++) { + if (e_r7->freq == freq) { + *tabent_r7 = e_r7; + return; + } + } + } else if (e_r7_2g) { + for (i = 0; i < len; i++, e_r7_2g++) { + if (e_r7_2g->freq == freq) { + *tabent_r7_2g = e_r7_2g; + return; + } + } + } else { + device_printf(mac->mac_sc->sc_dev, + "%s: couldn't find a suitable chantab\n", + __func__); + } +} diff --git a/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2057.h b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2057.h new file mode 100644 index 0000000..5e54490 --- /dev/null +++ b/sys/gnu/dev/bwn/phy_n/if_bwn_radio_2057.h @@ -0,0 +1,531 @@ +/* + + Broadcom B43 wireless driver + IEEE 802.11n PHY data tables + + Copyright (c) 2008 Michael Buesch <m@bues.ch> + Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, + Boston, MA 02110-1301, USA. + +*/ + +/* + * $FreeBSD$ + */ + +#ifndef __IF_BWN_RADIO_2057_H__ +#define __IF_BWN_RADIO_2057_H__ + +#define R2057_DACBUF_VINCM_CORE0 0x000 +#define R2057_IDCODE 0x001 +#define R2057_RCCAL_MASTER 0x002 +#define R2057_RCCAL_CAP_SIZE 0x003 +#define R2057_RCAL_CONFIG 0x004 +#define R2057_GPAIO_CONFIG 0x005 +#define R2057_GPAIO_SEL1 0x006 +#define R2057_GPAIO_SEL0 0x007 +#define R2057_CLPO_CONFIG 0x008 +#define R2057_BANDGAP_CONFIG 0x009 +#define R2057_BANDGAP_RCAL_TRIM 0x00a +#define R2057_AFEREG_CONFIG 0x00b +#define R2057_TEMPSENSE_CONFIG 0x00c +#define R2057_XTAL_CONFIG1 0x00d +#define R2057_XTAL_ICORE_SIZE 0x00e +#define R2057_XTAL_BUF_SIZE 0x00f +#define R2057_XTAL_PULLCAP_SIZE 0x010 +#define R2057_RFPLL_MASTER 0x011 +#define R2057_VCOMONITOR_VTH_L 0x012 +#define R2057_VCOMONITOR_VTH_H 0x013 +#define R2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x014 +#define R2057_VCO_VARCSIZE_IDAC 0x015 +#define R2057_VCOCAL_COUNTVAL0 0x016 +#define R2057_VCOCAL_COUNTVAL1 0x017 +#define R2057_VCOCAL_INTCLK_COUNT 0x018 +#define R2057_VCOCAL_MASTER 0x019 +#define R2057_VCOCAL_NUMCAPCHANGE 0x01a +#define R2057_VCOCAL_WINSIZE 0x01b +#define R2057_VCOCAL_DELAY_AFTER_REFRESH 0x01c +#define R2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x01d +#define R2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x01e +#define R2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x01f +#define R2057_VCO_FORCECAPEN_FORCECAP1 0x020 +#define R2057_VCO_FORCECAP0 0x021 +#define R2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x022 +#define R2057_RFPLL_PFD_RESET_PW 0x023 +#define R2057_RFPLL_LOOPFILTER_R2 0x024 +#define R2057_RFPLL_LOOPFILTER_R1 0x025 +#define R2057_RFPLL_LOOPFILTER_C3 0x026 +#define R2057_RFPLL_LOOPFILTER_C2 0x027 +#define R2057_RFPLL_LOOPFILTER_C1 0x028 +#define R2057_CP_KPD_IDAC 0x029 +#define R2057_RFPLL_IDACS 0x02a +#define R2057_RFPLL_MISC_EN 0x02b +#define R2057_RFPLL_MMD0 0x02c +#define R2057_RFPLL_MMD1 0x02d +#define R2057_RFPLL_MISC_CAL_RESETN 0x02e +#define R2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x02f +#define R2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x030 +#define R2057_VCOCAL_READCAP0 0x031 +#define R2057_VCOCAL_READCAP1 0x032 +#define R2057_VCOCAL_STATUS 0x033 +#define R2057_LOGEN_PUS 0x034 +#define R2057_LOGEN_PTAT_RESETS 0x035 +#define R2057_VCOBUF_IDACS 0x036 +#define R2057_VCOBUF_TUNE 0x037 +#define R2057_CMOSBUF_TX2GQ_IDACS 0x038 +#define R2057_CMOSBUF_TX2GI_IDACS 0x039 +#define R2057_CMOSBUF_TX5GQ_IDACS 0x03a +#define R2057_CMOSBUF_TX5GI_IDACS 0x03b +#define R2057_CMOSBUF_RX2GQ_IDACS 0x03c +#define R2057_CMOSBUF_RX2GI_IDACS 0x03d +#define R2057_CMOSBUF_RX5GQ_IDACS 0x03e +#define R2057_CMOSBUF_RX5GI_IDACS 0x03f +#define R2057_LOGEN_MX2G_IDACS 0x040 +#define R2057_LOGEN_MX2G_TUNE 0x041 +#define R2057_LOGEN_MX5G_IDACS 0x042 +#define R2057_LOGEN_MX5G_TUNE 0x043 +#define R2057_LOGEN_MX5G_RCCR 0x044 +#define R2057_LOGEN_INDBUF2G_IDAC 0x045 +#define R2057_LOGEN_INDBUF2G_IBOOST 0x046 +#define R2057_LOGEN_INDBUF2G_TUNE 0x047 +#define R2057_LOGEN_INDBUF5G_IDAC 0x048 +#define R2057_LOGEN_INDBUF5G_IBOOST 0x049 +#define R2057_LOGEN_INDBUF5G_TUNE 0x04a +#define R2057_CMOSBUF_TX_RCCR 0x04b +#define R2057_CMOSBUF_RX_RCCR 0x04c +#define R2057_LOGEN_SEL_PKDET 0x04d +#define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e + +/* MISC core 0 */ +#define R2057_RXTXBIAS_CONFIG_CORE0 0x04f +#define R2057_TXGM_TXRF_PUS_CORE0 0x050 +#define R2057_TXGM_IDAC_BLEED_CORE0 0x051 +#define R2057_TXGM_GAIN_CORE0 0x056 +#define R2057_TXGM2G_PKDET_PUS_CORE0 0x057 +#define R2057_PAD2G_PTATS_CORE0 0x058 +#define R2057_PAD2G_IDACS_CORE0 0x059 +#define R2057_PAD2G_BOOST_PU_CORE0 0x05a +#define R2057_PAD2G_CASCV_GAIN_CORE0 0x05b +#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x05c +#define R2057_TXMIX2G_LODC_CORE0 0x05d +#define R2057_PAD2G_TUNE_PUS_CORE0 0x05e +#define R2057_IPA2G_GAIN_CORE0 0x05f +#define R2057_TSSI2G_SPARE1_CORE0 0x060 +#define R2057_TSSI2G_SPARE2_CORE0 0x061 +#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x062 +#define R2057_IPA2G_IMAIN_CORE0 0x063 +#define R2057_IPA2G_CASCONV_CORE0 0x064 +#define R2057_IPA2G_CASCOFFV_CORE0 0x065 +#define R2057_IPA2G_BIAS_FILTER_CORE0 0x066 +#define R2057_TX5G_PKDET_CORE0 0x069 +#define R2057_PGA_PTAT_TXGM5G_PU_CORE0 0x06a +#define R2057_PAD5G_PTATS1_CORE0 0x06b +#define R2057_PAD5G_CLASS_PTATS2_CORE0 0x06c +#define R2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x06d +#define R2057_PAD5G_CASCV_IMAIN_CORE0 0x06e +#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x06f +#define R2057_PGA_BOOST_TUNE_CORE0 0x070 +#define R2057_PGA_GAIN_CORE0 0x071 +#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x072 +#define R2057_TXMIX5G_BOOST_TUNE_CORE0 0x073 +#define R2057_PAD5G_TUNE_MISC_PUS_CORE0 0x074 +#define R2057_IPA5G_IAUX_CORE0 0x075 +#define R2057_IPA5G_GAIN_CORE0 0x076 +#define R2057_TSSI5G_SPARE1_CORE0 0x077 +#define R2057_TSSI5G_SPARE2_CORE0 0x078 +#define R2057_IPA5G_CASCOFFV_PU_CORE0 0x079 +#define R2057_IPA5G_PTAT_CORE0 0x07a +#define R2057_IPA5G_IMAIN_CORE0 0x07b +#define R2057_IPA5G_CASCONV_CORE0 0x07c +#define R2057_IPA5G_BIAS_FILTER_CORE0 0x07d +#define R2057_PAD_BIAS_FILTER_BWS_CORE0 0x080 +#define R2057_TR2G_CONFIG1_CORE0_NU 0x081 +#define R2057_TR2G_CONFIG2_CORE0_NU 0x082 +#define R2057_LNA5G_RFEN_CORE0 0x083 +#define R2057_TR5G_CONFIG2_CORE0_NU 0x084 +#define R2057_RXRFBIAS_IBOOST_PU_CORE0 0x085 +#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x086 +#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x087 +#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x088 +#define R2057_RXMIX_CMFBITAIL_PU_CORE0 0x089 +#define R2057_LNA2_IMAIN_PTAT_PU_CORE0 0x08a +#define R2057_LNA2_IAUX_PTAT_CORE0 0x08b +#define R2057_LNA1_IMAIN_PTAT_PU_CORE0 0x08c +#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x08d +#define R2057_RXRFBIAS_BANDSEL_CORE0 0x08e +#define R2057_TIA_CONFIG_CORE0 0x08f +#define R2057_TIA_IQGAIN_CORE0 0x090 +#define R2057_TIA_IBIAS2_CORE0 0x091 +#define R2057_TIA_IBIAS1_CORE0 0x092 +#define R2057_TIA_SPARE_Q_CORE0 0x093 +#define R2057_TIA_SPARE_I_CORE0 0x094 +#define R2057_RXMIX2G_PUS_CORE0 0x095 +#define R2057_RXMIX2G_VCMREFS_CORE0 0x096 +#define R2057_RXMIX2G_LODC_QI_CORE0 0x097 +#define R2057_W12G_BW_LNA2G_PUS_CORE0 0x098 +#define R2057_LNA2G_GAIN_CORE0 0x099 +#define R2057_LNA2G_TUNE_CORE0 0x09a +#define R2057_RXMIX5G_PUS_CORE0 0x09b +#define R2057_RXMIX5G_VCMREFS_CORE0 0x09c +#define R2057_RXMIX5G_LODC_QI_CORE0 0x09d +#define R2057_W15G_BW_LNA5G_PUS_CORE0 0x09e +#define R2057_LNA5G_GAIN_CORE0 0x09f +#define R2057_LNA5G_TUNE_CORE0 0x0a0 +#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0x0a1 +#define R2057_RXBB_BIAS_MASTER_CORE0 0x0a2 +#define R2057_RXBB_VGABUF_IDACS_CORE0 0x0a3 +#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0x0a4 +#define R2057_TXBUF_VINCM_CORE0 0x0a5 +#define R2057_TXBUF_IDACS_CORE0 0x0a6 +#define R2057_LPF_RESP_RXBUF_BW_CORE0 0x0a7 +#define R2057_RXBB_CC_CORE0 0x0a8 +#define R2057_RXBB_SPARE3_CORE0 0x0a9 +#define R2057_RXBB_RCCAL_HPC_CORE0 0x0aa +#define R2057_LPF_IDACS_CORE0 0x0ab +#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0x0ac +#define R2057_TXBUF_GAIN_CORE0 0x0ad +#define R2057_AFELOOPBACK_AACI_RESP_CORE0 0x0ae +#define R2057_RXBUF_DEGEN_CORE0 0x0af +#define R2057_RXBB_SPARE2_CORE0 0x0b0 +#define R2057_RXBB_SPARE1_CORE0 0x0b1 +#define R2057_RSSI_MASTER_CORE0 0x0b2 +#define R2057_W2_MASTER_CORE0 0x0b3 +#define R2057_NB_MASTER_CORE0 0x0b4 +#define R2057_W2_IDACS0_Q_CORE0 0x0b5 +#define R2057_W2_IDACS1_Q_CORE0 0x0b6 +#define R2057_W2_IDACS0_I_CORE0 0x0b7 +#define R2057_W2_IDACS1_I_CORE0 0x0b8 +#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE0 0x0b9 +#define R2057_NB_IDACS_Q_CORE0 0x0ba +#define R2057_NB_IDACS_I_CORE0 0x0bb +#define R2057_BACKUP4_CORE0 0x0c1 +#define R2057_BACKUP3_CORE0 0x0c2 +#define R2057_BACKUP2_CORE0 0x0c3 +#define R2057_BACKUP1_CORE0 0x0c4 +#define R2057_SPARE16_CORE0 0x0c5 +#define R2057_SPARE15_CORE0 0x0c6 +#define R2057_SPARE14_CORE0 0x0c7 +#define R2057_SPARE13_CORE0 0x0c8 +#define R2057_SPARE12_CORE0 0x0c9 +#define R2057_SPARE11_CORE0 0x0ca +#define R2057_TX2G_BIAS_RESETS_CORE0 0x0cb +#define R2057_TX5G_BIAS_RESETS_CORE0 0x0cc +#define R2057_IQTEST_SEL_PU 0x0cd +#define R2057_XTAL_CONFIG2 0x0ce +#define R2057_BUFS_MISC_LPFBW_CORE0 0x0cf +#define R2057_TXLPF_RCCAL_CORE0 0x0d0 +#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1 +#define R2057_LPF_GAIN_CORE0 0x0d2 +#define R2057_DACBUF_IDACS_BW_CORE0 0x0d3 + +/* MISC core 1 */ +#define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4 +#define R2057_TXGM_TXRF_PUS_CORE1 0x0d5 +#define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6 +#define R2057_TXGM_GAIN_CORE1 0x0db +#define R2057_TXGM2G_PKDET_PUS_CORE1 0x0dc +#define R2057_PAD2G_PTATS_CORE1 0x0dd +#define R2057_PAD2G_IDACS_CORE1 0x0de +#define R2057_PAD2G_BOOST_PU_CORE1 0x0df +#define R2057_PAD2G_CASCV_GAIN_CORE1 0x0e0 +#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0x0e1 +#define R2057_TXMIX2G_LODC_CORE1 0x0e2 +#define R2057_PAD2G_TUNE_PUS_CORE1 0x0e3 +#define R2057_IPA2G_GAIN_CORE1 0x0e4 +#define R2057_TSSI2G_SPARE1_CORE1 0x0e5 +#define R2057_TSSI2G_SPARE2_CORE1 0x0e6 +#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0x0e7 +#define R2057_IPA2G_IMAIN_CORE1 0x0e8 +#define R2057_IPA2G_CASCONV_CORE1 0x0e9 +#define R2057_IPA2G_CASCOFFV_CORE1 0x0ea +#define R2057_IPA2G_BIAS_FILTER_CORE1 0x0eb +#define R2057_TX5G_PKDET_CORE1 0x0ee +#define R2057_PGA_PTAT_TXGM5G_PU_CORE1 0x0ef +#define R2057_PAD5G_PTATS1_CORE1 0x0f0 +#define R2057_PAD5G_CLASS_PTATS2_CORE1 0x0f1 +#define R2057_PGA_BOOSTPTAT_IMAIN_CORE1 0x0f2 +#define R2057_PAD5G_CASCV_IMAIN_CORE1 0x0f3 +#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0x0f4 +#define R2057_PGA_BOOST_TUNE_CORE1 0x0f5 +#define R2057_PGA_GAIN_CORE1 0x0f6 +#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0x0f7 +#define R2057_TXMIX5G_BOOST_TUNE_CORE1 0x0f8 +#define R2057_PAD5G_TUNE_MISC_PUS_CORE1 0x0f9 +#define R2057_IPA5G_IAUX_CORE1 0x0fa +#define R2057_IPA5G_GAIN_CORE1 0x0fb +#define R2057_TSSI5G_SPARE1_CORE1 0x0fc +#define R2057_TSSI5G_SPARE2_CORE1 0x0fd +#define R2057_IPA5G_CASCOFFV_PU_CORE1 0x0fe +#define R2057_IPA5G_PTAT_CORE1 0x0ff +#define R2057_IPA5G_IMAIN_CORE1 0x100 +#define R2057_IPA5G_CASCONV_CORE1 0x101 +#define R2057_IPA5G_BIAS_FILTER_CORE1 0x102 +#define R2057_PAD_BIAS_FILTER_BWS_CORE1 0x105 +#define R2057_TR2G_CONFIG1_CORE1_NU 0x106 +#define R2057_TR2G_CONFIG2_CORE1_NU 0x107 +#define R2057_LNA5G_RFEN_CORE1 0x108 +#define R2057_TR5G_CONFIG2_CORE1_NU 0x109 +#define R2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a +#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b +#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c +#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d +#define R2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e +#define R2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f +#define R2057_LNA2_IAUX_PTAT_CORE1 0x110 +#define R2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111 +#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112 +#define R2057_RXRFBIAS_BANDSEL_CORE1 0x113 +#define R2057_TIA_CONFIG_CORE1 0x114 +#define R2057_TIA_IQGAIN_CORE1 0x115 +#define R2057_TIA_IBIAS2_CORE1 0x116 +#define R2057_TIA_IBIAS1_CORE1 0x117 +#define R2057_TIA_SPARE_Q_CORE1 0x118 +#define R2057_TIA_SPARE_I_CORE1 0x119 +#define R2057_RXMIX2G_PUS_CORE1 0x11a +#define R2057_RXMIX2G_VCMREFS_CORE1 0x11b +#define R2057_RXMIX2G_LODC_QI_CORE1 0x11c +#define R2057_W12G_BW_LNA2G_PUS_CORE1 0x11d +#define R2057_LNA2G_GAIN_CORE1 0x11e +#define R2057_LNA2G_TUNE_CORE1 0x11f +#define R2057_RXMIX5G_PUS_CORE1 0x120 +#define R2057_RXMIX5G_VCMREFS_CORE1 0x121 +#define R2057_RXMIX5G_LODC_QI_CORE1 0x122 +#define R2057_W15G_BW_LNA5G_PUS_CORE1 0x123 +#define R2057_LNA5G_GAIN_CORE1 0x124 +#define R2057_LNA5G_TUNE_CORE1 0x125 +#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126 +#define R2057_RXBB_BIAS_MASTER_CORE1 0x127 +#define R2057_RXBB_VGABUF_IDACS_CORE1 0x128 +#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129 +#define R2057_TXBUF_VINCM_CORE1 0x12a +#define R2057_TXBUF_IDACS_CORE1 0x12b +#define R2057_LPF_RESP_RXBUF_BW_CORE1 0x12c +#define R2057_RXBB_CC_CORE1 0x12d +#define R2057_RXBB_SPARE3_CORE1 0x12e +#define R2057_RXBB_RCCAL_HPC_CORE1 0x12f +#define R2057_LPF_IDACS_CORE1 0x130 +#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131 +#define R2057_TXBUF_GAIN_CORE1 0x132 +#define R2057_AFELOOPBACK_AACI_RESP_CORE1 0x133 +#define R2057_RXBUF_DEGEN_CORE1 0x134 +#define R2057_RXBB_SPARE2_CORE1 0x135 +#define R2057_RXBB_SPARE1_CORE1 0x136 +#define R2057_RSSI_MASTER_CORE1 0x137 +#define R2057_W2_MASTER_CORE1 0x138 +#define R2057_NB_MASTER_CORE1 0x139 +#define R2057_W2_IDACS0_Q_CORE1 0x13a +#define R2057_W2_IDACS1_Q_CORE1 0x13b +#define R2057_W2_IDACS0_I_CORE1 0x13c +#define R2057_W2_IDACS1_I_CORE1 0x13d +#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE1 0x13e +#define R2057_NB_IDACS_Q_CORE1 0x13f +#define R2057_NB_IDACS_I_CORE1 0x140 +#define R2057_BACKUP4_CORE1 0x146 +#define R2057_BACKUP3_CORE1 0x147 +#define R2057_BACKUP2_CORE1 0x148 +#define R2057_BACKUP1_CORE1 0x149 +#define R2057_SPARE16_CORE1 0x14a +#define R2057_SPARE15_CORE1 0x14b +#define R2057_SPARE14_CORE1 0x14c +#define R2057_SPARE13_CORE1 0x14d +#define R2057_SPARE12_CORE1 0x14e +#define R2057_SPARE11_CORE1 0x14f +#define R2057_TX2G_BIAS_RESETS_CORE1 0x150 +#define R2057_TX5G_BIAS_RESETS_CORE1 0x151 +#define R2057_SPARE8_CORE1 0x152 +#define R2057_SPARE7_CORE1 0x153 +#define R2057_BUFS_MISC_LPFBW_CORE1 0x154 +#define R2057_TXLPF_RCCAL_CORE1 0x155 +#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156 +#define R2057_LPF_GAIN_CORE1 0x157 +#define R2057_DACBUF_IDACS_BW_CORE1 0x158 + +#define R2057_DACBUF_VINCM_CORE1 0x159 +#define R2057_RCCAL_START_R1_Q1_P1 0x15a +#define R2057_RCCAL_X1 0x15b +#define R2057_RCCAL_TRC0 0x15c +#define R2057_RCCAL_TRC1 0x15d +#define R2057_RCCAL_DONE_OSCCAP 0x15e +#define R2057_RCCAL_N0_0 0x15f +#define R2057_RCCAL_N0_1 0x160 +#define R2057_RCCAL_N1_0 0x161 +#define R2057_RCCAL_N1_1 0x162 +#define R2057_RCAL_STATUS 0x163 +#define R2057_XTALPUOVR_PINCTRL 0x164 +#define R2057_OVR_REG0 0x165 +#define R2057_OVR_REG1 0x166 +#define R2057_OVR_REG2 0x167 +#define R2057_OVR_REG3 0x168 +#define R2057_OVR_REG4 0x169 +#define R2057_RCCAL_SCAP_VAL 0x16a +#define R2057_RCCAL_BCAP_VAL 0x16b +#define R2057_RCCAL_HPC_VAL 0x16c +#define R2057_RCCAL_OVERRIDES 0x16d + +/* TX core 0 */ +#define R2057_TX0_IQCAL_GAIN_BW 0x170 +#define R2057_TX0_LOFT_FINE_I 0x171 +#define R2057_TX0_LOFT_FINE_Q 0x172 +#define R2057_TX0_LOFT_COARSE_I 0x173 +#define R2057_TX0_LOFT_COARSE_Q 0x174 +#define R2057_TX0_TX_SSI_MASTER 0x175 +#define R2057_TX0_IQCAL_VCM_HG 0x176 +#define R2057_TX0_IQCAL_IDAC 0x177 +#define R2057_TX0_TSSI_VCM 0x178 +#define R2057_TX0_TX_SSI_MUX 0x179 +#define R2057_TX0_TSSIA 0x17a +#define R2057_TX0_TSSIG 0x17b +#define R2057_TX0_TSSI_MISC1 0x17c +#define R2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d +#define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e +#define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f +#define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180 + +/* TX core 1 */ +#define R2057_TX1_IQCAL_GAIN_BW 0x190 +#define R2057_TX1_LOFT_FINE_I 0x191 +#define R2057_TX1_LOFT_FINE_Q 0x192 +#define R2057_TX1_LOFT_COARSE_I 0x193 +#define R2057_TX1_LOFT_COARSE_Q 0x194 +#define R2057_TX1_TX_SSI_MASTER 0x195 +#define R2057_TX1_IQCAL_VCM_HG 0x196 +#define R2057_TX1_IQCAL_IDAC 0x197 +#define R2057_TX1_TSSI_VCM 0x198 +#define R2057_TX1_TX_SSI_MUX 0x199 +#define R2057_TX1_TSSIA 0x19a +#define R2057_TX1_TSSIG 0x19b +#define R2057_TX1_TSSI_MISC1 0x19c +#define R2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d +#define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e +#define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f +#define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0 + +#define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1 +#define R2057_AFE_SET_VCM_I_CORE0 0x1a2 +#define R2057_AFE_SET_VCM_Q_CORE0 0x1a3 +#define R2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4 +#define R2057_AFE_STATUS_VCM_I_CORE0 0x1a5 +#define R2057_AFE_STATUS_VCM_Q_CORE0 0x1a6 +#define R2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7 +#define R2057_AFE_SET_VCM_I_CORE1 0x1a8 +#define R2057_AFE_SET_VCM_Q_CORE1 0x1a9 +#define R2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa +#define R2057_AFE_STATUS_VCM_I_CORE1 0x1ab +#define R2057_AFE_STATUS_VCM_Q_CORE1 0x1ac + +#define R2057v7_DACBUF_VINCM_CORE0 0x1ad +#define R2057v7_RCCAL_MASTER 0x1ae +#define R2057v7_TR2G_CONFIG3_CORE0_NU 0x1af +#define R2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0 +#define R2057v7_LOGEN_PUS1 0x1b1 +#define R2057v7_OVR_REG5 0x1b2 +#define R2057v7_OVR_REG6 0x1b3 +#define R2057v7_OVR_REG7 0x1b4 +#define R2057v7_OVR_REG8 0x1b5 +#define R2057v7_OVR_REG9 0x1b6 +#define R2057v7_OVR_REG10 0x1b7 +#define R2057v7_OVR_REG11 0x1b8 +#define R2057v7_OVR_REG12 0x1b9 +#define R2057v7_OVR_REG13 0x1ba +#define R2057v7_OVR_REG14 0x1bb +#define R2057v7_OVR_REG15 0x1bc +#define R2057v7_OVR_REG16 0x1bd +#define R2057v7_OVR_REG1 0x1be +#define R2057v7_OVR_REG18 0x1bf +#define R2057v7_OVR_REG19 0x1c0 +#define R2057v7_OVR_REG20 0x1c1 +#define R2057v7_OVR_REG21 0x1c2 +#define R2057v7_OVR_REG2 0x1c3 +#define R2057v7_OVR_REG23 0x1c4 +#define R2057v7_OVR_REG24 0x1c5 +#define R2057v7_OVR_REG25 0x1c6 +#define R2057v7_OVR_REG26 0x1c7 +#define R2057v7_OVR_REG27 0x1c8 +#define R2057v7_OVR_REG28 0x1c9 +#define R2057v7_IQTEST_SEL_PU2 0x1ca + +#define R2057_VCM_MASK 0x7 + +struct bwn_nphy_chantabent_rev7 { + /* The channel frequency in MHz */ + uint16_t freq; + /* Radio regs values on channelswitch */ + uint8_t radio_vcocal_countval0; + uint8_t radio_vcocal_countval1; + uint8_t radio_rfpll_refmaster_sparextalsize; + uint8_t radio_rfpll_loopfilter_r1; + uint8_t radio_rfpll_loopfilter_c2; + uint8_t radio_rfpll_loopfilter_c1; + uint8_t radio_cp_kpd_idac; + uint8_t radio_rfpll_mmd0; + uint8_t radio_rfpll_mmd1; + uint8_t radio_vcobuf_tune; + uint8_t radio_logen_mx2g_tune; + uint8_t radio_logen_mx5g_tune; + uint8_t radio_logen_indbuf2g_tune; + uint8_t radio_logen_indbuf5g_tune; + uint8_t radio_txmix2g_tune_boost_pu_core0; + uint8_t radio_pad2g_tune_pus_core0; + uint8_t radio_pga_boost_tune_core0; + uint8_t radio_txmix5g_boost_tune_core0; + uint8_t radio_pad5g_tune_misc_pus_core0; + uint8_t radio_lna2g_tune_core0; + uint8_t radio_lna5g_tune_core0; + uint8_t radio_txmix2g_tune_boost_pu_core1; + uint8_t radio_pad2g_tune_pus_core1; + uint8_t radio_pga_boost_tune_core1; + uint8_t radio_txmix5g_boost_tune_core1; + uint8_t radio_pad5g_tune_misc_pus_core1; + uint8_t radio_lna2g_tune_core1; + uint8_t radio_lna5g_tune_core1; + /* PHY res values on channelswitch */ + struct bwn_phy_n_sfo_cfg phy_regs; +}; + +struct bwn_nphy_chantabent_rev7_2g { + /* The channel frequency in MHz */ + uint16_t freq; + /* Radio regs values on channelswitch */ + uint8_t radio_vcocal_countval0; + uint8_t radio_vcocal_countval1; + uint8_t radio_rfpll_refmaster_sparextalsize; + uint8_t radio_rfpll_loopfilter_r1; + uint8_t radio_rfpll_loopfilter_c2; + uint8_t radio_rfpll_loopfilter_c1; + uint8_t radio_cp_kpd_idac; + uint8_t radio_rfpll_mmd0; + uint8_t radio_rfpll_mmd1; + uint8_t radio_vcobuf_tune; + uint8_t radio_logen_mx2g_tune; + uint8_t radio_logen_indbuf2g_tune; + uint8_t radio_txmix2g_tune_boost_pu_core0; + uint8_t radio_pad2g_tune_pus_core0; + uint8_t radio_lna2g_tune_core0; + uint8_t radio_txmix2g_tune_boost_pu_core1; + uint8_t radio_pad2g_tune_pus_core1; + uint8_t radio_lna2g_tune_core1; + /* PHY regs values on channelswitch */ + struct bwn_phy_n_sfo_cfg phy_regs; +}; + +void r2057_upload_inittabs(struct bwn_mac *mac); + +void r2057_get_chantabent_rev7(struct bwn_mac *mac, uint16_t freq, + const struct bwn_nphy_chantabent_rev7 **tabent_r7, + const struct bwn_nphy_chantabent_rev7_2g **tabent_r7_2g); + +#endif /* IF_BWN_RADIO_2057_H_ */ diff --git a/sys/gnu/dts/mips/3G-6200N.dts b/sys/gnu/dts/mips/3G-6200N.dts index 183148a..cd2ba51 100644 --- a/sys/gnu/dts/mips/3G-6200N.dts +++ b/sys/gnu/dts/mips/3G-6200N.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "3G-6200N", "ralink,rt3050-soc"; model = "Edimax 3g-6200n"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -53,18 +44,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -102,8 +81,29 @@ linux,code = <0x100>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/3G-6200NL.dts b/sys/gnu/dts/mips/3G-6200NL.dts index 760dafc..5ae43b8 100644 --- a/sys/gnu/dts/mips/3G-6200NL.dts +++ b/sys/gnu/dts/mips/3G-6200NL.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "3G-6200NL", "ralink,rt3050-soc"; model = "Edimax 3g-6200nl"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -53,18 +44,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -86,8 +65,29 @@ linux,code = <0x211>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/3G150B.dts b/sys/gnu/dts/mips/3G150B.dts index 628a0fa..3c92b94 100644 --- a/sys/gnu/dts/mips/3G150B.dts +++ b/sys/gnu/dts/mips/3G150B.dts @@ -1,83 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "3G150B", "ralink,rt5350-soc"; model = "Tenda 3G150B"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - - gpio1: gpio@660 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf", "led"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -116,3 +44,73 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf", "led"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; + ralink,led-polarity = <1>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/3G300M.dts b/sys/gnu/dts/mips/3G300M.dts index f14eb9e..331e9fe 100644 --- a/sys/gnu/dts/mips/3G300M.dts +++ b/sys/gnu/dts/mips/3G300M.dts @@ -1,58 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "3G300M", "ralink,rt3052-soc"; model = "Tenda 3G300M"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -105,20 +58,65 @@ linux,code = <0x100>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; +&spi0 { + status = "okay"; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/A5-V11.dts b/sys/gnu/dts/mips/A5-V11.dts index 63d9604..6a15458 100644 --- a/sys/gnu/dts/mips/A5-V11.dts +++ b/sys/gnu/dts/mips/A5-V11.dts @@ -1,82 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "A5-V11", "ralink,rt5350-soc"; model = "A5-V11"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "pm25lq032"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - - gpio1: gpio@660 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf", "led"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -121,3 +50,73 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "pm25lq032"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf", "led"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x1>; + mediatek,portdisable = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/AI-BR100.dts b/sys/gnu/dts/mips/AI-BR100.dts index d624864..2c32933 100644 --- a/sys/gnu/dts/mips/AI-BR100.dts +++ b/sys/gnu/dts/mips/AI-BR100.dts @@ -1,85 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "AI-BR100", "ralink,mt7620a-soc"; model = "Aigale Ai-BR100"; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "u-boot-env"; - reg = <0x20000 0x10000>; - read-only; - }; - - factory: partition@30000 { - label = "factory"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x7c0000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -107,3 +33,75 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "u-boot-env"; + reg = <0x20000 0x10000>; + read-only; + }; + + factory: partition@30000 { + label = "factory"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "firmware"; + reg = <0x40000 0x7c0000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/AIR3GII.dts b/sys/gnu/dts/mips/AIR3GII.dts index a3457e6..2b6932d 100644 --- a/sys/gnu/dts/mips/AIR3GII.dts +++ b/sys/gnu/dts/mips/AIR3GII.dts @@ -1,74 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "AIR3GII", "ralink,rt5350-soc"; model = "AirLive Air3GII"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q32b"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -96,3 +33,64 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q32b"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/ALL0239-3G.dts b/sys/gnu/dts/mips/ALL0239-3G.dts index ae09fb9..d1d92e1 100644 --- a/sys/gnu/dts/mips/ALL0239-3G.dts +++ b/sys/gnu/dts/mips/ALL0239-3G.dts @@ -1,19 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "ALL0239-3G", "ralink,rt3052-soc"; model = "Allnet ALL0239-3G"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; cfi@1f000000 { compatible = "cfi-flash"; @@ -47,19 +39,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - status = "okay"; - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -108,8 +87,30 @@ linux,code = <0x211>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + status = "okay"; + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/ALL0256N-4M.dts b/sys/gnu/dts/mips/ALL0256N-4M.dts index 67fdb68..713b735 100644 --- a/sys/gnu/dts/mips/ALL0256N-4M.dts +++ b/sys/gnu/dts/mips/ALL0256N-4M.dts @@ -1,74 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "ALL0256N", "ralink,rt3050-soc"; model = "Allnet ALL0256N"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3c8000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -101,3 +38,64 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3c8000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/ALL0256N-8M.dts b/sys/gnu/dts/mips/ALL0256N-8M.dts index d1b590d..2c4790a 100644 --- a/sys/gnu/dts/mips/ALL0256N-8M.dts +++ b/sys/gnu/dts/mips/ALL0256N-8M.dts @@ -1,74 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "ALL0256N", "ralink,rt3050-soc"; model = "Allnet ALL0256N"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -101,3 +38,64 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/ALL5002.dts b/sys/gnu/dts/mips/ALL5002.dts index 2e6a3ea..efaabc2 100644 --- a/sys/gnu/dts/mips/ALL5002.dts +++ b/sys/gnu/dts/mips/ALL5002.dts @@ -1,82 +1,11 @@ /dts-v1/; -/include/ "rt3352.dtsi" +#include "rt3352.dtsi" / { compatible = "ALL5002", "ralink,rt3352-soc"; model = "Allnet ALL5002"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l25635e"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - i2c-gpio { compatible = "i2c-gpio"; gpios = <&gpio0 1 0 &gpio0 2 0>; @@ -109,3 +38,72 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l25635e"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/ALL5003.dts b/sys/gnu/dts/mips/ALL5003.dts index ec48098..3a6023a 100644 --- a/sys/gnu/dts/mips/ALL5003.dts +++ b/sys/gnu/dts/mips/ALL5003.dts @@ -1,82 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "ALL5003", "ralink,rt5350-soc"; model = "Allnet ALL5003"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l25635e"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - i2c-gpio { compatible = "i2c-gpio"; gpios = <&gpio0 1 0 &gpio0 2 0>; @@ -109,3 +38,72 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l25635e"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/AR670W.dts b/sys/gnu/dts/mips/AR670W.dts index 0e29d89..c1eac43 100644 --- a/sys/gnu/dts/mips/AR670W.dts +++ b/sys/gnu/dts/mips/AR670W.dts @@ -1,50 +1,11 @@ /dts-v1/; -/include/ "rt2880.dtsi" +#include "rt2880.dtsi" / { compatible = "AR670W", "ralink,rt2880-soc"; model = "Airlink101 AR670W"; - palmbus@300000 { - gpio0: gpio@600 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "uartlite"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@400000 { - status = "okay"; - mtd-mac-address = <&factory 0x2004>; - - port@0 { - phy-handle = <&phy0>; - phy-mode = "mii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; - }; - }; - - wmac@480000 { - status = "okay"; - ralink,mtd-eeprom = <&factory 0x2000>; - }; - cfi@bdc00000 { compatible = "cfi-flash"; reg = <0xbc400000 0x800000>; @@ -103,3 +64,40 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi", "uartlite"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x2004>; + + port@0 { + phy-handle = <&phy0>; + phy-mode = "mii"; + }; + + mdio-bus { + status = "okay"; + + phy0: ethernet-phy@0 { + phy-mode = "mii"; + reg = <0>; + }; + }; +}; + +&wmac { + status = "okay"; + ralink,mtd-eeprom = <&factory 0x2000>; +}; diff --git a/sys/gnu/dts/mips/AR725W.dts b/sys/gnu/dts/mips/AR725W.dts index 6f66c3f..3b8cfb3 100644 --- a/sys/gnu/dts/mips/AR725W.dts +++ b/sys/gnu/dts/mips/AR725W.dts @@ -1,50 +1,11 @@ /dts-v1/; -/include/ "rt2880.dtsi" +#include "rt2880.dtsi" / { compatible = "AR725W", "ralink,rt2880-soc"; model = "Airlink101 AR725W"; - palmbus@300000 { - gpio0: gpio@600 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "uartlite"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@400000 { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - phy-handle = <&phy0>; - phy-mode = "mii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; - }; - }; - - wmac@480000 { - status = "okay"; - ralink,mtd-eeprom = <&factory 0>; - }; - cfi@bdc00000 { compatible = "cfi-flash"; reg = <0xbc400000 0x800000>; @@ -113,3 +74,40 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi", "uartlite"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x4>; + + port@0 { + phy-handle = <&phy0>; + phy-mode = "mii"; + }; + + mdio-bus { + status = "okay"; + + phy0: ethernet-phy@0 { + phy-mode = "mii"; + reg = <0>; + }; + }; +}; + +&wmac { + status = "okay"; + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/ASL26555-16M.dts b/sys/gnu/dts/mips/ASL26555-16M.dts index d644b56..2b2c494 100644 --- a/sys/gnu/dts/mips/ASL26555-16M.dts +++ b/sys/gnu/dts/mips/ASL26555-16M.dts @@ -1,96 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "ASL26555", "ralink,rt3050-soc"; model = "Alpha ASL26555"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25sl12801"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@fd0000 { - label = "cert"; - reg = <0xfd0000 0x10000>; - read-only; - }; - - partition@fe0000 { - label = "langpack"; - reg = <0xfe0000 0x10000>; - read-only; - }; - - devdata: partition@ff0000 { - label = "devdata"; - reg = <0xff0000 0x10000>; - read-only; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&devdata 0x4004>; - }; - - esw@10110000 { - mediatek,portmap = <0x1e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&devdata 0x4000>; - }; - - otg@101c0000 { - status = "okay"; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -154,3 +69,86 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25sl12801"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "uboot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xf80000>; + }; + + partition@fd0000 { + label = "cert"; + reg = <0xfd0000 0x10000>; + read-only; + }; + + partition@fe0000 { + label = "langpack"; + reg = <0xfe0000 0x10000>; + read-only; + }; + + devdata: partition@ff0000 { + label = "devdata"; + reg = <0xff0000 0x10000>; + read-only; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&devdata 0x4004>; +}; + +&esw { + mediatek,portmap = <0x1e>; +}; + +&wmac { + ralink,mtd-eeprom = <&devdata 0x4000>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/ASL26555-8M.dts b/sys/gnu/dts/mips/ASL26555-8M.dts index 2780e35..1c40df4 100644 --- a/sys/gnu/dts/mips/ASL26555-8M.dts +++ b/sys/gnu/dts/mips/ASL26555-8M.dts @@ -1,90 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "ASL26555", "ralink,rt3050-soc"; model = "Alpha ASL26555"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25sl064p"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - ubootenv: partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "rgdb"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x790000>; - }; - - partition@7e0000 { - label = "cert"; - reg = <0x7e0000 0x10000>; - read-only; - }; - - partition@7f0000 { - label = "langpack"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&ubootenv 0x4004>; - }; - - esw@10110000 { - mediatek,portmap = <0x1e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&ubootenv 0x4000>; - }; - - otg@101c0000 { - status = "okay"; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -148,3 +69,80 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25sl064p"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + + ubootenv: partition@30000 { + label = "uboot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "rgdb"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x790000>; + }; + + partition@7e0000 { + label = "cert"; + reg = <0x7e0000 0x10000>; + read-only; + }; + + partition@7f0000 { + label = "langpack"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&ubootenv 0x4004>; +}; + +&esw { + mediatek,portmap = <0x1e>; +}; + +&wmac { + ralink,mtd-eeprom = <&ubootenv 0x4000>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/ATP-52B.dts b/sys/gnu/dts/mips/ATP-52B.dts index f7e9ac7..c15d3a4 100644 --- a/sys/gnu/dts/mips/ATP-52B.dts +++ b/sys/gnu/dts/mips/ATP-52B.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "ATP-52B", "ralink,rt3052-soc"; model = "Argus ATP-52B"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -77,20 +68,30 @@ linux,code = <0x198>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - otg@101c0000 { - status = "okay"; - }; +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/AWAPN2403.dts b/sys/gnu/dts/mips/AWAPN2403.dts index 9c10155..d8e69bd 100644 --- a/sys/gnu/dts/mips/AWAPN2403.dts +++ b/sys/gnu/dts/mips/AWAPN2403.dts @@ -1,66 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "AWAPN2403", "ralink,rt3052-soc"; model = "AsiaRF AWAPN2403"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -83,3 +28,56 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/AWM002-4M.dtsi b/sys/gnu/dts/mips/AWM002-4M.dtsi index f770232..69d25bb 100644 --- a/sys/gnu/dts/mips/AWM002-4M.dtsi +++ b/sys/gnu/dts/mips/AWM002-4M.dtsi @@ -1,15 +1,11 @@ -/include/ "AWM002.dtsi" +#include "AWM002.dtsi" / { compatible = "AWM002", "ralink,rt5350-soc"; model = "AsiaRF AWM002"; +}; - palmbus@10000000 { - spi@b00 { - m25p80@0 { - compatible = "jedec,spi-nor"; - linux,modalias = "m25p80", "mx25l3205d"; - }; - }; - }; +&m25p80 { + compatible = "jedec,spi-nor"; + linux,modalias = "m25p80", "mx25l3205d"; }; diff --git a/sys/gnu/dts/mips/AWM002-8M.dtsi b/sys/gnu/dts/mips/AWM002-8M.dtsi index ab2c3ac..1e6970d 100644 --- a/sys/gnu/dts/mips/AWM002-8M.dtsi +++ b/sys/gnu/dts/mips/AWM002-8M.dtsi @@ -1,15 +1,11 @@ -/include/ "AWM002.dtsi" +#include "AWM002.dtsi" / { compatible = "AWM002", "ralink,rt5350-soc"; model = "AsiaRF AWM002"; +}; - palmbus@10000000 { - spi@b00 { - m25p80@0 { - compatible = "jedec,spi-nor"; - linux,modalias = "m25p80", "mx25l6405d"; - }; - }; - }; +&m25p80 { + compatible = "jedec,spi-nor"; + linux,modalias = "m25p80", "mx25l6405d"; }; diff --git a/sys/gnu/dts/mips/AWM002-EVB-4M.dts b/sys/gnu/dts/mips/AWM002-EVB-4M.dts index fe2ff1a..e125232 100644 --- a/sys/gnu/dts/mips/AWM002-EVB-4M.dts +++ b/sys/gnu/dts/mips/AWM002-EVB-4M.dts @@ -1,18 +1,10 @@ /dts-v1/; -/include/ "AWM002-4M.dtsi" +#include "AWM002-4M.dtsi" / { model = "AsiaRF AWM002 EVB"; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -51,3 +43,11 @@ }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/AWM002-EVB-8M.dts b/sys/gnu/dts/mips/AWM002-EVB-8M.dts index d4de3f1..f2f91bb 100644 --- a/sys/gnu/dts/mips/AWM002-EVB-8M.dts +++ b/sys/gnu/dts/mips/AWM002-EVB-8M.dts @@ -1,18 +1,10 @@ /dts-v1/; -/include/ "AWM002-8M.dtsi" +#include "AWM002-8M.dtsi" / { model = "AsiaRF AWM002 EVB"; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -51,3 +43,11 @@ }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/AWM002.dtsi b/sys/gnu/dts/mips/AWM002.dtsi index a360d8c..bf6876b 100644 --- a/sys/gnu/dts/mips/AWM002.dtsi +++ b/sys/gnu/dts/mips/AWM002.dtsi @@ -1,78 +1,76 @@ -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "AWM002", "ralink,rt5350-soc"; model = "AsiaRF AWM002"; - palmbus@10000000 { - spi@b00 { - status = "okay"; + gpio-leds { + compatible = "gpio-leds"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <10000000>; + ld1 { + label = "awm002:green:ld1"; + gpios = <&gpio0 0 1>; + }; - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; + ld2 { + label = "awm002:green:ld2"; + gpios = <&gpio0 1 1>; + }; + }; +}; - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; +&spi0 { + status = "okay"; - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; + m25p80: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <10000000>; - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; }; - }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag"; - ralink,function = "gpio"; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; }; - }; - esw@10110000 { - mediatek,portmap = <0x3f>; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - ehci@101c0000 { - status = "okay"; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; }; +}; - ohci@101c1000 { - status = "okay"; +&pinctrl { + state_default { + gpio { + ralink,group = "i2c", "jtag"; + ralink,function = "gpio"; + }; }; +}; - gpio-leds { - compatible = "gpio-leds"; +&esw { + mediatek,portmap = <0x3f>; +}; - ld1 { - label = "awm002:green:ld1"; - gpios = <&gpio0 0 1>; - }; +&ehci { + status = "okay"; +}; - ld2 { - label = "awm002:green:ld2"; - gpios = <&gpio0 1 1>; - }; - }; +&ohci { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/AWM003-EVB.dts b/sys/gnu/dts/mips/AWM003-EVB.dts index b74dd90..13e6964 100644 --- a/sys/gnu/dts/mips/AWM003-EVB.dts +++ b/sys/gnu/dts/mips/AWM003-EVB.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "AWM002-8M.dtsi" +#include "AWM002-8M.dtsi" / { compatible = "AWM003", "ralink,rt5350-soc"; @@ -11,23 +11,6 @@ reg = <0x0 0x4000000>; }; - palmbus@10000000 { - spi@b00 { - m25p80@0 { - compatible = "jedec,spi-nor"; - linux,modalias = "m25p80", "mx25l6405d"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -66,3 +49,16 @@ }; }; }; + +&m25p80 { + compatible = "jedec,spi-nor"; + linux,modalias = "m25p80", "mx25l6405d"; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/ArcherC20i.dts b/sys/gnu/dts/mips/ArcherC20i.dts index a2a77b4..aab1f9b 100644 --- a/sys/gnu/dts/mips/ArcherC20i.dts +++ b/sys/gnu/dts/mips/ArcherC20i.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-soc"; @@ -10,109 +10,107 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; + gpio-leds { + compatible = "gpio-leds"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x7a0000>; }; - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7a0000>; - }; - - partition@7c0000 { - label = "config"; - reg = <0x7c0000 0x10000>; - }; - - rom: partition@7d0000 { - label = "rom"; - reg = <0x7d0000 0x10000>; - }; - - partition@7e0000 { - label = "romfile"; - reg = <0x7e0000 0x10000>; - }; - - radio: partition@7f0000 { - label = "radio"; - reg = <0x7f0000 0x10000>; - }; - }; + partition@7c0000 { + label = "config"; + reg = <0x7c0000 0x10000>; + }; + + rom: partition@7d0000 { + label = "rom"; + reg = <0x7d0000 0x10000>; + }; + + partition@7e0000 { + label = "romfile"; + reg = <0x7e0000 0x10000>; + }; + + radio: partition@7f0000 { + label = "radio"; + reg = <0x7f0000 0x10000>; }; }; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; - ralink,function = "gpio"; - }; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; + ralink,function = "gpio"; }; }; +}; - ethernet@10100000 { +ðernet { pinctrl-names = "default"; pinctrl-0 = <&ephy_pins>; mtd-mac-address = <&rom 0xf100>; mediatek,portmap = "wllll"; }; - ehci@101c0000 { - status = "okay"; - }; +&ehci { + status = "okay"; +}; - ohci@101c1000 { - status = "okay"; - }; +&ohci { + status = "okay"; +}; - gsw@10110000 { - mediatek,port4 = "ephy"; - }; +&gsw { + mediatek,port4 = "ephy"; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&radio 0>; - }; +&wmac { + ralink,mtd-eeprom = <&radio 0>; +}; - pcie@10140000 { - status = "okay"; +&pcie { + status = "okay"; - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&radio 32768>; - mediatek,2ghz = <0>; - }; + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&radio 32768>; + mediatek,2ghz = <0>; }; }; - - gpio-leds { - compatible = "gpio-leds"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - }; }; diff --git a/sys/gnu/dts/mips/BC2.dts b/sys/gnu/dts/mips/BC2.dts index 0c74ffa..5ae10a3 100644 --- a/sys/gnu/dts/mips/BC2.dts +++ b/sys/gnu/dts/mips/BC2.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "BC2", "ralink,rt3052-soc"; model = "NexAira BC2"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -68,20 +59,29 @@ linux,code = <0x198>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; - otg@101c0000 { - status = "okay"; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/BR-6425.dts b/sys/gnu/dts/mips/BR-6425.dts index a5f9177..b871ead 100644 --- a/sys/gnu/dts/mips/BR-6425.dts +++ b/sys/gnu/dts/mips/BR-6425.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "BR-6425", "ralink,rt3052-soc"; model = "Edimax BR-6425"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -24,18 +15,6 @@ #size-cells = <1>; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -69,3 +48,24 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { +/* mtd-mac-address = <&factory 0x4>; */ +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { +/* ralink,mtd-eeprom = <&factory 0>; */ +}; diff --git a/sys/gnu/dts/mips/BR-6475ND.dts b/sys/gnu/dts/mips/BR-6475ND.dts index fc6d16f..f437ac1 100644 --- a/sys/gnu/dts/mips/BR-6475ND.dts +++ b/sys/gnu/dts/mips/BR-6475ND.dts @@ -1,82 +1,50 @@ /dts-v1/; -/include/ "rt3883.dtsi" +#include "rt3883.dtsi" / { compatible = "BR-6475ND", "ralink,rt3883-soc"; model = "Edimax BR-6475nD"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - palmbus@10000000 { - timer@100 { - status = "okay"; - }; + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; - gpio1: gpio@638 { - status = "okay"; + reset { + label = "reset"; + gpios = <&gpio0 7 1>; + linux,code = <0x198>; }; - uartlite@c00 { - status = "okay"; + rfkill { + label = "rfkill"; + gpios = <&gpio0 9 1>; + linux,input-type = <5>; + linux,code = <0xf7>; }; }; - ethernet@10100000 { - status = "okay"; - mtd-mac-address = <&devdata 0x0d>; + gpio-leds { + compatible = "gpio-leds"; - port@0 { - mediatek,fixed-link = <1000 1 1 1>; + power { + label = "br-6475nd:green:power"; + gpios = <&gpio0 10 1>; }; - }; - wmac@10180000 { - status = "okay"; - ralink,mtd-eeprom = <&factory 0>; - }; - - pci@10140000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_pins>; - - pci_pins: pci { - pci { - ralink,group = "pci"; - ralink,function = "pci-fnc"; - }; + wlan { + label = "br-6475nd:amber:wlan"; + gpios = <&gpio0 11 1>; }; - host-bridge { - pci-bridge@1 { - status = "okay"; - - wmac@0,0 { - ralink,5ghz = <0>; - compatible = "ralink,rt2880-pci", "pciclass060400", "pciclass0604"; - reg = < 0x10000 0 0 0 0 >; - ralink,eeprom = "rt2x00pci_1_0.eeprom"; - }; - }; + wlan_5ghz { + label = "br-6475nd:amber:wlan_5ghz"; + gpios = <&gpio0 14 1>; }; }; - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - nor-flash@1c000000 { compatible = "cfi-flash"; reg = <0x1c000000 0x800000>; @@ -126,58 +94,88 @@ realtek,extif0 = <1 0 1 1 1 1 1 1 2>; }; - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; + /* Unclear if this is the correct gpio setup; the USB ports are + unpopulated on a stock BR-6475nD, even though the hardware exists + and the headers are there. */ + /* + gpio_export { + compatible = "gpio-export"; #size-cells = <0>; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio0 7 1>; - linux,code = <0x198>; + usb { + gpio-export,name="usb"; + gpio-export,output=<0>; + gpios = <&gpio0 19 0>; }; + }; + */ +}; - rfkill { - label = "rfkill"; - gpios = <&gpio0 9 1>; - linux,input-type = <5>; - linux,code = <0xf7>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "jtag", "uartf"; + ralink,function = "gpio"; }; }; +}; - gpio-leds { - compatible = "gpio-leds"; +&timer { + status = "okay"; +}; - power { - label = "br-6475nd:green:power"; - gpios = <&gpio0 10 1>; - }; +&gpio1 { + status = "okay"; +}; - wlan { - label = "br-6475nd:amber:wlan"; - gpios = <&gpio0 11 1>; - }; +&uartlite { + status = "okay"; +}; - wlan_5ghz { - label = "br-6475nd:amber:wlan_5ghz"; - gpios = <&gpio0 14 1>; +ðernet { + status = "okay"; + mtd-mac-address = <&devdata 0x0d>; + + port@0 { + mediatek,fixed-link = <1000 1 1 1>; + }; +}; + +&wmac { + status = "okay"; + ralink,mtd-eeprom = <&factory 0>; +}; + +&pci { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pci_pins>; + + pci_pins: pci { + pci { + ralink,group = "pci"; + ralink,function = "pci-fnc"; }; }; - /* Unclear if this is the correct gpio setup; the USB ports are - unpopulated on a stock BR-6475nD, even though the hardware exists - and the headers are there. */ - /* - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; + host-bridge { + pci-bridge@1 { + status = "okay"; - usb { - gpio-export,name="usb"; - gpio-export,output=<0>; - gpios = <&gpio0 19 0>; + wmac@0,0 { + ralink,5ghz = <0>; + compatible = "ralink,rt2880-pci", "pciclass060400", "pciclass0604"; + reg = < 0x10000 0 0 0 0 >; + ralink,eeprom = "rt2x00pci_1_0.eeprom"; + }; }; }; - */ +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/BROADWAY.dts b/sys/gnu/dts/mips/BROADWAY.dts index df43644..790dcc0 100644 --- a/sys/gnu/dts/mips/BROADWAY.dts +++ b/sys/gnu/dts/mips/BROADWAY.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "BROADWAY", "ralink,rt3052-soc"; model = "Hauppauge Broadway"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -85,8 +64,29 @@ linux,code = <0x198>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/CARAMBOLA.dts b/sys/gnu/dts/mips/CARAMBOLA.dts index 771d4ec..e38c49f 100644 --- a/sys/gnu/dts/mips/CARAMBOLA.dts +++ b/sys/gnu/dts/mips/CARAMBOLA.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "CARAMBOLA", "ralink,rt3050-soc"; @@ -10,15 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -51,25 +42,34 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; + i2c-gpio { + compatible = "i2c-gpio"; + gpios = <&gpio0 1 0 &gpio0 2 0>; + i2c-gpio,delay-us = <10>; }; +}; - esw@10110000 { - mediatek,portmap = <0x3f>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +ðernet { + mtd-mac-address = <&factory 0x28>; +}; - otg@101c0000 { - status = "okay"; - }; +&esw { + mediatek,portmap = <0x3f>; +}; - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&gpio0 1 0 &gpio0 2 0>; - i2c-gpio,delay-us = <10>; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/CF-WR800N.dts b/sys/gnu/dts/mips/CF-WR800N.dts index 66ba926..d076e64 100644 --- a/sys/gnu/dts/mips/CF-WR800N.dts +++ b/sys/gnu/dts/mips/CF-WR800N.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "cf-wr800n", "ralink,mt7620n-soc"; @@ -10,77 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio1: gpio@638 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "spi refclk", "i2c"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -113,3 +42,72 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "ephy", "wled", "spi refclk", "i2c"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/CS-QR10.dts b/sys/gnu/dts/mips/CS-QR10.dts new file mode 100644 index 0000000..a55962f --- /dev/null +++ b/sys/gnu/dts/mips/CS-QR10.dts @@ -0,0 +1,161 @@ +/dts-v1/; + +#include "mt7620a.dtsi" + +/ { + compatible = "ralink,mt7620a-soc"; + model = "Planex CS-QR10"; + + sound { + compatible = "mediatek,mt7620-audio-wm8960"; + model = "mt7620-wm8960"; + i2s-controller = <&i2s>; + audio-routing = + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "cs-qr10:red:power"; + gpios = <&gpio1 4 1>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + s1 { + label = "reset"; + gpios = <&gpio1 1 1>; + linux,code = <0x198>; + }; + + s2 { + label = "wps"; + gpios = <&gpio1 3 1>; + linux,code = <0x211>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&i2c { + status = "okay"; +}; + +&i2s { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcm_i2s_pins>; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pcm { + status = "okay"; +}; + +&gdma { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi refclk", "rgmii1"; + ralink,function = "gpio"; + }; + wdt { + ralink,group = "wdt"; + ralink,function = "wdt refclk"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&gsw { + ralink,port4 = "ephy"; +}; + +&sdhci { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/CY-SWR1100.dts b/sys/gnu/dts/mips/CY-SWR1100.dts index be15d9b..031d8f0 100644 --- a/sys/gnu/dts/mips/CY-SWR1100.dts +++ b/sys/gnu/dts/mips/CY-SWR1100.dts @@ -1,73 +1,11 @@ /dts-v1/; -/include/ "rt3883.dtsi" +#include "rt3883.dtsi" / { compatible = "CY-SWR1100", "ralink,rt3883-soc"; model = "Samsung CY-SWR1100"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - phy-mode = "rgmii"; - }; - }; - - pci@10140000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_pins>; - - pci_pins: pci { - pci { - ralink,group = "pci"; - ralink,function = "pci-fnc"; - }; - }; - - host-bridge { - pci-bridge@1 { - status = "okay"; - - wmac@0,0 { - ralink,5ghz = <0>; - compatible = "ralink,rt2880-pci", "pciclass060400", "pciclass0604"; - reg = < 0x10000 0 0 0 0 >; - ralink,eeprom = "rt2x00pci_1_0.eeprom"; - }; - }; - }; - }; - - wmac@10180000 { - status = "okay"; - ralink,2ghz = <0>; - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - nor-flash@1c000000 { compatible = "cfi-flash"; reg = <0x1c000000 0x800000>; @@ -150,3 +88,63 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + port@0 { + mediatek,fixed-link = <1000 1 1 1>; + phy-mode = "rgmii"; + }; +}; + +&pci { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pci_pins>; + + pci_pins: pci { + pci { + ralink,group = "pci"; + ralink,function = "pci-fnc"; + }; + }; + + host-bridge { + pci-bridge@1 { + status = "okay"; + + wmac@0,0 { + ralink,5ghz = <0>; + compatible = "ralink,rt2880-pci", "pciclass060400", "pciclass0604"; + reg = < 0x10000 0 0 0 0 >; + ralink,eeprom = "rt2x00pci_1_0.eeprom"; + }; + }; + }; +}; + +&wmac { + status = "okay"; + ralink,2ghz = <0>; + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/D105.dts b/sys/gnu/dts/mips/D105.dts index 1a1ea73..2e86d1e 100644 --- a/sys/gnu/dts/mips/D105.dts +++ b/sys/gnu/dts/mips/D105.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "D105", "ralink,rt3050-soc"; model = "Huawei D105"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -73,20 +64,29 @@ linux,code = <0x198>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; - otg@101c0000 { - status = "okay"; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/DAP-1350.dts b/sys/gnu/dts/mips/DAP-1350.dts index e97c551..4628544 100644 --- a/sys/gnu/dts/mips/DAP-1350.dts +++ b/sys/gnu/dts/mips/DAP-1350.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "DAP-1350", "ralink,rt3052-soc"; @@ -10,15 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -57,18 +48,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&devdata 0x2e>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&devdata 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -118,8 +97,29 @@ linux,code = <0x101>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&devdata 0x2e>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&devdata 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/DB-WRT01.dts b/sys/gnu/dts/mips/DB-WRT01.dts index e3a7770..8014859 100644 --- a/sys/gnu/dts/mips/DB-WRT01.dts +++ b/sys/gnu/dts/mips/DB-WRT01.dts @@ -1,81 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-soc"; model = "Planex DB-WRT01"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "en25q64"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi refclk", "rgmii1"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - - gsw@10110000 { - mediatek,port4 = "ephy"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pcie@10140000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -98,3 +28,71 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi refclk", "rgmii1"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&gsw { + mediatek,port4 = "ephy"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/DCS-930.dts b/sys/gnu/dts/mips/DCS-930.dts index b43d4e5..373973c 100644 --- a/sys/gnu/dts/mips/DCS-930.dts +++ b/sys/gnu/dts/mips/DCS-930.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "DCS-930", "ralink,rt3050-soc"; model = "D-Link DCS-930"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x400000>; @@ -94,20 +85,29 @@ linux,code = <0x198>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; - otg@101c0000 { - status = "okay"; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/DCS-930L-B1.dts b/sys/gnu/dts/mips/DCS-930L-B1.dts index 8b53cfd..c1e90b9 100644 --- a/sys/gnu/dts/mips/DCS-930L-B1.dts +++ b/sys/gnu/dts/mips/DCS-930L-B1.dts @@ -1,78 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "DCS-930L-B1", "ralink,rt5350-soc"; model = "D-Link DCS-930L B1"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf", "led"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -106,3 +39,68 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf", "led"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/DIR-300-B1.dts b/sys/gnu/dts/mips/DIR-300-B1.dts index f0298b2..4f0a7ff 100644 --- a/sys/gnu/dts/mips/DIR-300-B1.dts +++ b/sys/gnu/dts/mips/DIR-300-B1.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "DIR-300-B1", "ralink,rt3050-soc"; model = "D-Link DIR-300 B1"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&devdata 0x4004>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&devdata 0x4000>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -107,3 +86,24 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&devdata 0x4004>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&devdata 0x4000>; +}; diff --git a/sys/gnu/dts/mips/DIR-300-B7.dts b/sys/gnu/dts/mips/DIR-300-B7.dts index f3cec7b..a634bb7 100644 --- a/sys/gnu/dts/mips/DIR-300-B7.dts +++ b/sys/gnu/dts/mips/DIR-300-B7.dts @@ -1,67 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "DIR-300-B7", "ralink,rt5350-soc"; model = "D-Link DIR-300 B7"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -94,10 +38,64 @@ linux,code = <0x211>; }; }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; - wmac@10180000 { - status = "okay"; - ralink,led-polarity = <1>; - ralink,mtd-eeprom = <&factory 0>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <0x17>; +}; + +&wmac { + status = "okay"; + ralink,led-polarity = <1>; + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/DIR-320-B1.dts b/sys/gnu/dts/mips/DIR-320-B1.dts index fba590f..1393947 100644 --- a/sys/gnu/dts/mips/DIR-320-B1.dts +++ b/sys/gnu/dts/mips/DIR-320-B1.dts @@ -1,71 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "DIR-320-B1", "ralink,rt5350-soc"; model = "D-Link DIR-320 B1"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -104,14 +44,6 @@ }; }; - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c0000 { - status = "okay"; - }; - gpio_export { compatible = "gpio-export"; #size-cells = <0>; @@ -129,3 +61,69 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <0x17>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/DIR-600-B1.dts b/sys/gnu/dts/mips/DIR-600-B1.dts index ea3d3eb..d45d3c5 100644 --- a/sys/gnu/dts/mips/DIR-600-B1.dts +++ b/sys/gnu/dts/mips/DIR-600-B1.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "DIR-600-B1", "ralink,rt3050-soc"; model = "D-Link DIR-600 B1"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&devdata 0x4004>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&devdata 0x4000>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -107,3 +86,24 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&devdata 0x4004>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&devdata 0x4000>; +}; diff --git a/sys/gnu/dts/mips/DIR-600-B2.dts b/sys/gnu/dts/mips/DIR-600-B2.dts index 2791563..f0269cf 100644 --- a/sys/gnu/dts/mips/DIR-600-B2.dts +++ b/sys/gnu/dts/mips/DIR-600-B2.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "DIR-600-B2", "ralink,rt3050-soc"; model = "D-Link DIR-600 B2"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,14 +38,6 @@ }; }; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&devdata 0x4000>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -103,3 +86,20 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&devdata 0x4000>; +}; diff --git a/sys/gnu/dts/mips/DIR-610-A1.dts b/sys/gnu/dts/mips/DIR-610-A1.dts index cfab89a..83faf00 100644 --- a/sys/gnu/dts/mips/DIR-610-A1.dts +++ b/sys/gnu/dts/mips/DIR-610-A1.dts @@ -1,74 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "DIR-610-A1", "ralink,rt5350-soc"; model = "D-Link DIR-610 A1"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - devdata: partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&devdata 0x4004>; - }; - - esw@10110000 { - status = "okay"; - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; - }; - - wmac@10180000 { - status = "okay"; - ralink,led-polarity = <1>; - ralink,mtd-eeprom = <&devdata 0x4000>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -102,3 +39,64 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + devdata: partition@30000 { + label = "devdata"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&devdata 0x4004>; +}; + +&esw { + status = "okay"; + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <0x17>; +}; + +&wmac { + status = "okay"; + ralink,led-polarity = <1>; + ralink,mtd-eeprom = <&devdata 0x4000>; +}; diff --git a/sys/gnu/dts/mips/DIR-615-D.dts b/sys/gnu/dts/mips/DIR-615-D.dts index 45aeace..cac9d26 100644 --- a/sys/gnu/dts/mips/DIR-615-D.dts +++ b/sys/gnu/dts/mips/DIR-615-D.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "DIR-615-D", "ralink,rt3050-soc"; model = "D-Link DIR-615 D"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,14 +38,6 @@ }; }; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&devdata 0x4000>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -103,3 +86,22 @@ }; }; }; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&devdata 0x4000>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + + diff --git a/sys/gnu/dts/mips/DIR-615-H1.dts b/sys/gnu/dts/mips/DIR-615-H1.dts index d21d7d5..be9cb10 100644 --- a/sys/gnu/dts/mips/DIR-615-H1.dts +++ b/sys/gnu/dts/mips/DIR-615-H1.dts @@ -1,80 +1,11 @@ /dts-v1/; -/include/ "rt3352.dtsi" +#include "rt3352.dtsi" / { compatible = "DIR-615-H1", "ralink,rt3352-soc"; model = "D-Link DIR-615 H1"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - - rgmii { - ralink,group = "rgmii"; - ralink,function = "rgmii"; - }; - - mdio { - ralink,group = "mdio"; - ralink,function = "mdio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -123,3 +54,70 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + + rgmii { + ralink,group = "rgmii"; + ralink,function = "rgmii"; + }; + + mdio { + ralink,group = "mdio"; + ralink,function = "mdio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/DIR-620-A1.dts b/sys/gnu/dts/mips/DIR-620-A1.dts index c72b11b..68a2346 100644 --- a/sys/gnu/dts/mips/DIR-620-A1.dts +++ b/sys/gnu/dts/mips/DIR-620-A1.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "DIR-620-A1", "ralink,rt3050-soc"; model = "D-Link DIR-620 A1"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -111,8 +90,29 @@ gpios = <&gpio0 11 0>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/DIR-620-D1.dts b/sys/gnu/dts/mips/DIR-620-D1.dts index 4737d24c..5392467 100644 --- a/sys/gnu/dts/mips/DIR-620-D1.dts +++ b/sys/gnu/dts/mips/DIR-620-D1.dts @@ -1,80 +1,11 @@ /dts-v1/; -/include/ "rt3352.dtsi" +#include "rt3352.dtsi" / { compatible = "DIR-620-D1", "ralink,rt3352-soc"; model = "D-Link DIR-620 D1"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - - rgmii { - ralink,group = "rgmii"; - ralink,function = "rgmii"; - }; - - mdio { - ralink,group = "mdio"; - ralink,function = "mdio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -101,12 +32,79 @@ linux,code = <0x198>; }; }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; - ehci@101c0000 { - status = "okay"; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + + rgmii { + ralink,group = "rgmii"; + ralink,function = "rgmii"; + }; - ohci@101c1000 { - status = "okay"; + mdio { + ralink,group = "mdio"; + ralink,function = "mdio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/DIR-645.dts b/sys/gnu/dts/mips/DIR-645.dts index 6272324..1cdb321 100644 --- a/sys/gnu/dts/mips/DIR-645.dts +++ b/sys/gnu/dts/mips/DIR-645.dts @@ -1,94 +1,11 @@ /dts-v1/; -/include/ "rt3883.dtsi" +#include "rt3883.dtsi" / { compatible = "DIR-645", "ralink,rt3883-soc"; model = "D-Link DIR-645"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <25000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x4000>; - read-only; - }; - - factory: partition@34000 { - label = "factory"; - reg = <0x34000 0x4000>; - read-only; - }; - - partition@38000 { - label = "nvram"; - reg = <0x38000 0x8000>; - read-only; - }; - - partition@40000 { - label = "devdata"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 0>; - }; - }; - - wmac@10180000 { - ralink,5ghz = <0>; - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - rtl8367b { compatible = "realtek,rtl8367b"; gpio-sda = <&gpio0 1 0>; @@ -140,3 +57,84 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <25000000>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "uboot-env"; + reg = <0x30000 0x4000>; + read-only; + }; + + factory: partition@34000 { + label = "factory"; + reg = <0x34000 0x4000>; + read-only; + }; + + partition@38000 { + label = "nvram"; + reg = <0x38000 0x8000>; + read-only; + }; + + partition@40000 { + label = "devdata"; + reg = <0x40000 0x10000>; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + + port@0 { + mediatek,fixed-link = <1000 1 1 0>; + }; +}; + +&wmac { + ralink,5ghz = <0>; + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/DIR-810L.dts b/sys/gnu/dts/mips/DIR-810L.dts index 91fb018..9e9c16d 100644 --- a/sys/gnu/dts/mips/DIR-810L.dts +++ b/sys/gnu/dts/mips/DIR-810L.dts @@ -1,101 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "dlink,dir-810l", "ralink,mt7620a-soc"; model = "D-Link DIR-810L"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - factory5g: partition@50000 { - label = "factory5g"; - reg = <0x50000 0x10000>; - read-only; - }; - - partition@60000 { - label = "Wolf_Config"; - reg = <0x60000 0x10000>; - read-only; - }; - - partition@70000 { - label = "MyDlink"; - reg = <0x70000 0x80000>; - read-only; - }; - - partition@e0000 { - label = "Jffs2"; - reg = <0xe0000 0x80000>; - read-only; - }; - - partition@170000 { - label = "firmware"; - reg = <0x170000 0x690000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "mdio", "rgmii1", "i2c", "wled", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - mediatek,portmap = "llllw"; - }; - - gsw@10110000 { - mediatek,port4 = "ephy"; - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - }; - - pcie@10140000 { - status = "okay"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -134,3 +44,91 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + factory5g: partition@50000 { + label = "factory5g"; + reg = <0x50000 0x10000>; + read-only; + }; + + partition@60000 { + label = "Wolf_Config"; + reg = <0x60000 0x10000>; + read-only; + }; + + partition@70000 { + label = "MyDlink"; + reg = <0x70000 0x80000>; + read-only; + }; + + partition@e0000 { + label = "Jffs2"; + reg = <0xe0000 0x80000>; + read-only; + }; + + partition@170000 { + label = "firmware"; + reg = <0x170000 0x690000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "mdio", "rgmii1", "i2c", "wled", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; + mediatek,portmap = "llllw"; +}; + +&gsw { + mediatek,port4 = "ephy"; + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; +}; + +&pcie { + status = "okay"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/DIR-860L-B1.dts b/sys/gnu/dts/mips/DIR-860L-B1.dts index a6add70..9ce9aa2 100644 --- a/sys/gnu/dts/mips/DIR-860L-B1.dts +++ b/sys/gnu/dts/mips/DIR-860L-B1.dts @@ -15,87 +15,6 @@ bootargs = "console=ttyS0,57600"; }; - palmbus@1E000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x4000>; - read-only; - }; - - radio: partition@34000 { - label = "radio"; - reg = <0x34000 0x4000>; - read-only; - }; - - factory: partition@38000 { - label = "factory"; - reg = <0x38000 0x8000>; - read-only; - }; - - partition@40000 { - label = "defaults"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; - }; - - pcie@1e140000 { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&radio 0x2000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&radio 0>; - mediatek,5ghz = <0>; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -127,3 +46,82 @@ poll-interval = <20>; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x4000>; + read-only; + }; + + radio: partition@34000 { + label = "radio"; + reg = <0x34000 0x4000>; + read-only; + }; + + factory: partition@38000 { + label = "factory"; + reg = <0x38000 0x8000>; + read-only; + }; + + partition@40000 { + label = "defaults"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&radio 0x2000>; + mediatek,2ghz = <0>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&radio 0>; + mediatek,5ghz = <0>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/E1700.dts b/sys/gnu/dts/mips/E1700.dts index 8b4361a..ed1f178 100644 --- a/sys/gnu/dts/mips/E1700.dts +++ b/sys/gnu/dts/mips/E1700.dts @@ -10,115 +10,12 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "linksys,e1700", "ralink,mt7620a-soc"; model = "Linksys E1700"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "config"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - status = "okay"; - mtd-mac-address = <&factory 0x28>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - - port@5 { - status = "okay"; - mediatek,fixed-link = <1000 1 1 1>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - phy-mode = "rgmii"; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - phy-mode = "rgmii"; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - phy-mode = "rgmii"; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - phy-mode = "rgmii"; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy1f: ethernet-phy@1f { - reg = <0x1f>; - phy-mode = "rgmii"; - }; - }; - }; - - gsw@10110000 { - mediatek,port4 = "gmac"; - mediatek,mt7530 = <1>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -152,3 +49,104 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "config"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x28>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; + + port@5 { + status = "okay"; + mediatek,fixed-link = <1000 1 1 1>; + phy-mode = "rgmii"; + }; + + mdio-bus { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rgmii"; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + phy-mode = "rgmii"; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + phy-mode = "rgmii"; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + phy-mode = "rgmii"; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii"; + }; + + phy1f: ethernet-phy@1f { + reg = <0x1f>; + phy-mode = "rgmii"; + }; + }; +}; + +&gsw { + mediatek,port4 = "gmac"; + mediatek,mt7530 = <1>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/ESR-9753.dts b/sys/gnu/dts/mips/ESR-9753.dts index 67d8539..6869166 100644 --- a/sys/gnu/dts/mips/ESR-9753.dts +++ b/sys/gnu/dts/mips/ESR-9753.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "ESR-9753", "ralink,rt3052-soc"; model = "Senao / EnGenius ESR-9753"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -79,16 +70,25 @@ linux,code = <0x211>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x3e>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; }; diff --git a/sys/gnu/dts/mips/EX2700.dts b/sys/gnu/dts/mips/EX2700.dts index 4b5a01a..8d89a6b 100644 --- a/sys/gnu/dts/mips/EX2700.dts +++ b/sys/gnu/dts/mips/EX2700.dts @@ -10,7 +10,7 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-soc"; @@ -20,73 +20,6 @@ bootargs = "console=ttyS0,57600"; }; - palmbus@10000000 { - - gpio0: gpio@600 { - status = "okay"; - }; - - gpio1: gpio@638 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x3b0000>; - }; - - art: partition@3f0000 { - label = "art"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&art 0x0>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&art 0x1000>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - // spi refclk: pins 37, 38, 39 - // uartf: pins 8, 9, 10, 11, 12, 13, 14 - // i2c: pins 1, 2 - ralink,group = "i2c", "uartf", "spi refclk"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -146,3 +79,67 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "firmware"; + reg = <0x40000 0x3b0000>; + }; + + art: partition@3f0000 { + label = "art"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; +}; + +ðernet { + mtd-mac-address = <&art 0x0>; +}; + +&wmac { + ralink,mtd-eeprom = <&art 0x1000>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + // spi refclk: pins 37, 38, 39 + // uartf: pins 8, 9, 10, 11, 12, 13, 14 + // i2c: pins 1, 2 + ralink,group = "i2c", "uartf", "spi refclk"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/F5D8235_V1.dts b/sys/gnu/dts/mips/F5D8235_V1.dts index f1bfc09..dacdea6 100644 --- a/sys/gnu/dts/mips/F5D8235_V1.dts +++ b/sys/gnu/dts/mips/F5D8235_V1.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt2880.dtsi" +#include "rt2880.dtsi" / { #address-cells = <1>; @@ -8,21 +8,6 @@ compatible = "F5D8235_V1", "ralink,rt2880-soc"; model = "Belkin F5D8235 v1"; - palmbus@300000 { - gpio0: gpio@600 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -55,21 +40,6 @@ }; }; - ethernet@400000 { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; - }; - - /* FIXME: no u-boot partition and 0x40000@uboot is out of boundaries */ -/* wmac@480000 { - status = "okay"; - ralink,mtd-eeprom = <&u-boot 0x40000>; - }; -*/ rtl8366s { compatible = "realtek,rtl8366s"; gpio-sda = <&gpio0 1 0>; @@ -109,3 +79,33 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x4>; + + port@0 { + mediatek,fixed-link = <1000 1 1 1>; + }; +}; + +/* FIXME: no u-boot partition and 0x40000@uboot is out of boundaries */ +/*&wmac { + status = "okay"; + ralink,mtd-eeprom = <&u-boot 0x40000>; +}; +*/ + diff --git a/sys/gnu/dts/mips/F5D8235_V2.dts b/sys/gnu/dts/mips/F5D8235_V2.dts index 38446e6..084ca0f 100644 --- a/sys/gnu/dts/mips/F5D8235_V2.dts +++ b/sys/gnu/dts/mips/F5D8235_V2.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "F5D8235_V2", "ralink,rt3052-soc"; model = "Belkin F5D8235 v2"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -45,22 +36,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&uboot 0x40004>; - }; - - esw@10110000 { - mediatek,portmap = <0x3f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&uboot 0x40000>; - }; - - otg@101c0000 { - status = "okay"; - }; - rtl8366rb { compatible = "rtl8366rb"; gpio-sda = <&gpio0 1 0>; @@ -116,3 +91,28 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&uboot 0x40004>; +}; + +&esw { + mediatek,portmap = <0x3f>; +}; + +&wmac { + ralink,mtd-eeprom = <&uboot 0x40000>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/F7C027.dts b/sys/gnu/dts/mips/F7C027.dts index 7d479ad..8438d12 100644 --- a/sys/gnu/dts/mips/F7C027.dts +++ b/sys/gnu/dts/mips/F7C027.dts @@ -1,87 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "F7C027", "ralink,rt5350-soc"; model = "Belkin F7C027"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l12805d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x770000>; - }; - - partition@7c0000 { - label = "firmware2"; - reg = <0x7c0000 0x770000>; - }; - - partition@f30000 { - label = "belkin_settings"; - reg = <0xf30000 0xa0000>; - }; - - partition@fd0000 { - label = "unknown"; - reg = <0xfd0000 0x10000>; - }; - - partition@fe0000 { - label = "nvram"; - reg = <0xfe0000 0x10000>; - }; - - partition@ff0000 { - label = "user_factory"; - reg = <0xff0000 0x10000>; - }; - }; - }; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -131,3 +55,77 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l12805d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x770000>; + }; + + partition@7c0000 { + label = "firmware2"; + reg = <0x7c0000 0x770000>; + }; + + partition@f30000 { + label = "belkin_settings"; + reg = <0xf30000 0xa0000>; + }; + + partition@fd0000 { + label = "unknown"; + reg = <0xfd0000 0x10000>; + }; + + partition@fe0000 { + label = "nvram"; + reg = <0xfe0000 0x10000>; + }; + + partition@ff0000 { + label = "user_factory"; + reg = <0xff0000 0x10000>; + }; + }; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/FIREWRT.dts b/sys/gnu/dts/mips/FIREWRT.dts index e7cfb11..3e6806e 100644 --- a/sys/gnu/dts/mips/FIREWRT.dts +++ b/sys/gnu/dts/mips/FIREWRT.dts @@ -15,74 +15,6 @@ bootargs = "console=ttyS0,57600"; }; - sdhci@10130000 { - status = "okay"; - }; - - palmbus@1E000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; - }; - - pcie@1e140000 { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; - }; - - ethernet@1e100000 { - mtd-mac-address = <&factory 0xe000>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -110,13 +42,79 @@ linux,code = <116>; }; }; +}; + +&sdhci { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,5ghz = <0>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe000>; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wdt", "rgmii2"; - ralink,function = "gpio"; - }; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "wdt", "rgmii2"; + ralink,function = "gpio"; }; }; }; diff --git a/sys/gnu/dts/mips/FONERA20N.dts b/sys/gnu/dts/mips/FONERA20N.dts index a9d0acd..b7eb91e 100644 --- a/sys/gnu/dts/mips/FONERA20N.dts +++ b/sys/gnu/dts/mips/FONERA20N.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "FONERA20N", "ralink,rt3052-soc"; model = "La Fonera 2.0N"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -85,50 +76,59 @@ linux,input-type = <5>; /* EV_SW */ }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi", "jtag", "mdio", "rgmii", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - - port@0 { - compatible = "swconfig,port"; - swconfig,segment = "lan"; - swconfig,portmap = <0 4>; - }; +ðernet { + mtd-mac-address = <&factory 0x28>; +}; - port@1 { - compatible = "swconfig,port"; - swconfig,segment = "lan"; - swconfig,portmap = <1 3>; - }; +&esw { + mediatek,portmap = <0x2f>; - port@2 { - compatible = "swconfig,port"; - swconfig,segment = "lan"; - swconfig,portmap = <2 2>; - }; + port@0 { + compatible = "swconfig,port"; + swconfig,segment = "lan"; + swconfig,portmap = <0 4>; + }; - port@3 { - compatible = "swconfig,port"; - swconfig,segment = "lan"; - swconfig,portmap = <3 1>; - }; + port@1 { + compatible = "swconfig,port"; + swconfig,segment = "lan"; + swconfig,portmap = <1 3>; + }; - port@4 { - compatible = "swconfig,port"; - swconfig,segment = "wan"; - swconfig,portmap = <4 0>; - }; + port@2 { + compatible = "swconfig,port"; + swconfig,segment = "lan"; + swconfig,portmap = <2 2>; }; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; + port@3 { + compatible = "swconfig,port"; + swconfig,segment = "lan"; + swconfig,portmap = <3 1>; }; - otg@101c0000 { - status = "okay"; + port@4 { + compatible = "swconfig,port"; + swconfig,segment = "wan"; + swconfig,portmap = <4 0>; }; }; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/FREESTATION5.dts b/sys/gnu/dts/mips/FREESTATION5.dts index 0e38c55..425eb2a 100644 --- a/sys/gnu/dts/mips/FREESTATION5.dts +++ b/sys/gnu/dts/mips/FREESTATION5.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "FREESTATION5", "ralink,rt3050-soc"; @@ -10,15 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -51,22 +42,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x01>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - otg@101c0000 { - status = "okay"; - }; - gpio-export { compatible = "gpio-export"; @@ -100,3 +75,28 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x01>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/GL-MT300A.dts b/sys/gnu/dts/mips/GL-MT300A.dts index c1eb0a9..fa3fc44 100644 --- a/sys/gnu/dts/mips/GL-MT300A.dts +++ b/sys/gnu/dts/mips/GL-MT300A.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "GL-MT300A", "ralink,mt7620a-soc"; @@ -10,109 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio1: gpio@638 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q128"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@ff0000 { - label = "art"; - reg = <0xff0000 0x10000>; - }; - }; - }; - }; - - sdhci@10130000 { - status = "okay"; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4000>; - ralink,port-map = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pcie@10140000 { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wled","ephy","uartf","i2c"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -162,3 +59,104 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q128"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xf80000>; + }; + + partition@ff0000 { + label = "art"; + reg = <0xff0000 0x10000>; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4000>; + ralink,port-map = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; + + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "wled","ephy","uartf","i2c"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/GL-MT300N.dts b/sys/gnu/dts/mips/GL-MT300N.dts index 82db37e..6a3600a 100644 --- a/sys/gnu/dts/mips/GL-MT300N.dts +++ b/sys/gnu/dts/mips/GL-MT300N.dts @@ -1,112 +1,15 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620a.dtsi" / { - compatible = "GL-MT300N", "ralink,mt7620n-soc"; + compatible = "GL-MT300N", "ralink,mt7620a-soc"; model = "GL-MT300N"; chosen { bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio1: gpio@638 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q128"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@ff0000 { - label = "art"; - reg = <0xff0000 0x10000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4000>; - ralink,port-map = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pcie@10140000 { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wled","ephy","i2c"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -151,3 +54,98 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q128"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xf80000>; + }; + + partition@ff0000 { + label = "art"; + reg = <0xff0000 0x10000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x4000>; + ralink,port-map = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; + + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "wled","ephy","i2c"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/GL-MT750.dts b/sys/gnu/dts/mips/GL-MT750.dts index a36ae5e..882e870 100644 --- a/sys/gnu/dts/mips/GL-MT750.dts +++ b/sys/gnu/dts/mips/GL-MT750.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "GL-MT750", "ralink,mt7620a-soc"; @@ -10,109 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio1: gpio@638 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q128"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@ff0000 { - label = "art"; - reg = <0xff0000 0x10000>; - }; - }; - }; - }; - - sdhci@10130000 { - status = "okay"; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4000>; - ralink,port-map = "llllw"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pcie@10140000 { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wled","ephy","uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -157,3 +54,104 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q128"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xf80000>; + }; + + partition@ff0000 { + label = "art"; + reg = <0xff0000 0x10000>; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4000>; + ralink,port-map = "llllw"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; + + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "wled","ephy","uartf"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/HC5661.dts b/sys/gnu/dts/mips/HC5661.dts index b9a717b..eb1df34 100644 --- a/sys/gnu/dts/mips/HC5661.dts +++ b/sys/gnu/dts/mips/HC5661.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "HC5XXX.dtsi" +#include "HC5XXX.dtsi" / { compatible = "HC5661", "ralink,mt7620a-soc"; diff --git a/sys/gnu/dts/mips/HC5761.dts b/sys/gnu/dts/mips/HC5761.dts index a10904cc..6b0554a 100644 --- a/sys/gnu/dts/mips/HC5761.dts +++ b/sys/gnu/dts/mips/HC5761.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "HC5XXX.dtsi" +#include "HC5XXX.dtsi" / { compatible = "HC5761", "ralink,mt7620a-soc"; diff --git a/sys/gnu/dts/mips/HC5861.dts b/sys/gnu/dts/mips/HC5861.dts index b279db1..3e812f6 100644 --- a/sys/gnu/dts/mips/HC5861.dts +++ b/sys/gnu/dts/mips/HC5861.dts @@ -1,49 +1,11 @@ /dts-v1/; -/include/ "HC5XXX.dtsi" +#include "HC5XXX.dtsi" / { compatible = "HC5861", "ralink,mt7620a-soc"; model = "HiWiFi HC5861"; - ethernet@10100000 { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "wllll"; - - port@4 { - status = "okay"; - phy-handle = <&phy4>; - phy-mode = "rgmii"; - }; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; - }; - - gsw@10110000 { - mediatek,port4 = "gmac"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -90,3 +52,41 @@ }; }; }; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; + mediatek,portmap = "wllll"; + + port@4 { + status = "okay"; + phy-handle = <&phy4>; + phy-mode = "rgmii"; + }; + + port@5 { + status = "okay"; + phy-handle = <&phy5>; + phy-mode = "rgmii"; + }; + + mdio-bus { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii"; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + phy-mode = "rgmii"; + }; + }; +}; + +&gsw { + mediatek,port4 = "gmac"; +}; diff --git a/sys/gnu/dts/mips/HC5XXX.dtsi b/sys/gnu/dts/mips/HC5XXX.dtsi index 84e2b80..479dd9e 100644 --- a/sys/gnu/dts/mips/HC5XXX.dtsi +++ b/sys/gnu/dts/mips/HC5XXX.dtsi @@ -1,120 +1,10 @@ -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { chosen { bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - sysc@0 { - ralink,gpiomux = "i2c", "jtag"; - ralink,uartmux = "gpio"; - ralink,wdtmux = <1>; - }; - - gpio0: gpio@600 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@fd0000 { - label = "hwf_config"; - reg = <0xfd0000 0x10000>; - }; - - bdinfo: partition@fe0000 { - label = "bdinfo"; - reg = <0xfe0000 0x10000>; - }; - - partition@ff0000 { - label = "backup"; - reg = <0xff0000 0x10000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; - - sdhci@10130000 { - status = "okay"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pcie@10140000 { - status = "okay"; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uartf", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - - pa { - ralink,group = "pa"; - ralink,function = "pa"; - }; - }; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -139,3 +29,111 @@ }; }; }; + +&sysc { + ralink,gpiomux = "i2c", "jtag"; + ralink,uartmux = "gpio"; + ralink,wdtmux = <1>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xf80000>; + }; + + partition@fd0000 { + label = "hwf_config"; + reg = <0xfd0000 0x10000>; + }; + + bdinfo: partition@fe0000 { + label = "bdinfo"; + reg = <0xfe0000 0x10000>; + }; + + partition@ff0000 { + label = "backup"; + reg = <0xff0000 0x10000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; + +&sdhci { + status = "okay"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; +}; + +&pinctrl { + state_default { + gpio { + ralink,group = "uartf", "wled", "nd_sd"; + ralink,function = "gpio"; + }; + + pa { + ralink,group = "pa"; + ralink,function = "pa"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/HG255D.dts b/sys/gnu/dts/mips/HG255D.dts index 00f012c..ee38509 100644 --- a/sys/gnu/dts/mips/HG255D.dts +++ b/sys/gnu/dts/mips/HG255D.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "HG255D", "ralink,rt3052-soc"; model = "HuaWei HG255D"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x1000000>; @@ -111,20 +102,29 @@ linux,code = <0xf7>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +ðernet { + mtd-mac-address = <&factory 0x28>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; - otg@101c0000 { - status = "okay"; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/HLKRM04.dts b/sys/gnu/dts/mips/HLKRM04.dts index 3c9a93c..fb72b6b 100644 --- a/sys/gnu/dts/mips/HLKRM04.dts +++ b/sys/gnu/dts/mips/HLKRM04.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "HLKRM04", "ralink,rt5350-soc"; @@ -15,78 +15,6 @@ bootargs = "console=ttyS1,57600"; }; - palmbus@10000000 { - uart@500 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag"; - ralink,function = "gpio"; - }; - - uartf_gpio { - ralink,group = "uartf"; - ralink,function = "gpio uartf"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-export { compatible = "gpio-export"; #size-cells = <0>; @@ -123,3 +51,73 @@ }; }; }; + +&uart { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag"; + ralink,function = "gpio"; + }; + + uartf_gpio { + ralink,group = "uartf"; + ralink,function = "gpio uartf"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/HPM.dts b/sys/gnu/dts/mips/HPM.dts index c1b8ff3..000750f 100644 --- a/sys/gnu/dts/mips/HPM.dts +++ b/sys/gnu/dts/mips/HPM.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3883.dtsi" +#include "rt3883.dtsi" / { compatible = "HPM", "ralink,rt3883-soc"; @@ -10,78 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <25000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x0030000>; - label = "u-boot"; - read-only; - }; - - partition@30000 { - reg = <0x00030000 0x00010000>; - label = "config"; - read-only; - }; - - factory: partition@40000 { - reg = <0x00040000 0x00010000>; - label = "factory"; - read-only; - }; - - partition@50000 { - reg = <0x00050000 0x00fb0000>; - label = "firmware"; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - phy-handle = <&phy0>; - phy-mode = "rgmii"; - mtd-mac-address = <&factory 0x28>; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@4 { - reg = <4>; - }; - }; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -147,3 +75,73 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x0030000>; + label = "u-boot"; + read-only; + }; + + partition@30000 { + reg = <0x00030000 0x00010000>; + label = "config"; + read-only; + }; + + factory: partition@40000 { + reg = <0x00040000 0x00010000>; + label = "factory"; + read-only; + }; + + partition@50000 { + reg = <0x00050000 0x00fb0000>; + label = "firmware"; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + phy-handle = <&phy0>; + phy-mode = "rgmii"; + mtd-mac-address = <&factory 0x28>; + + mdio-bus { + status = "okay"; + + phy0: ethernet-phy@4 { + reg = <4>; + }; + }; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/HT-TM02.dts b/sys/gnu/dts/mips/HT-TM02.dts index bb7f333..640ce76 100644 --- a/sys/gnu/dts/mips/HT-TM02.dts +++ b/sys/gnu/dts/mips/HT-TM02.dts @@ -1,82 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "HT-TM02", "ralink,rt5350-soc"; model = "HooToo HT-TM02"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x10>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -111,3 +40,73 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x10>; + mediatek,portdisable = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/HW550-3G.dts b/sys/gnu/dts/mips/HW550-3G.dts index 8a88131..0efa8d0 100644 --- a/sys/gnu/dts/mips/HW550-3G.dts +++ b/sys/gnu/dts/mips/HW550-3G.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "HW550-3G", "ralink,rt3052-soc"; model = "Aztech HW550-3G"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -107,8 +86,29 @@ linux,code = <0x211>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/IP2202.dts b/sys/gnu/dts/mips/IP2202.dts index da63045..50d5532 100644 --- a/sys/gnu/dts/mips/IP2202.dts +++ b/sys/gnu/dts/mips/IP2202.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "IP2202", "ralink,rt3052-soc"; model = "Poray IP2202"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,14 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -81,8 +64,25 @@ linux,code = <0x198>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/JHR-N805R.dts b/sys/gnu/dts/mips/JHR-N805R.dts index 9ddab6e..bdc4739 100644 --- a/sys/gnu/dts/mips/JHR-N805R.dts +++ b/sys/gnu/dts/mips/JHR-N805R.dts @@ -1,70 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "JHR-N805R", "ralink,rt3050-soc"; model = "JCG JHR-N805R"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x2e>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -87,3 +28,60 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x2e>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/JHR-N825R.dts b/sys/gnu/dts/mips/JHR-N825R.dts index 2b648c5..1e9acdf 100644 --- a/sys/gnu/dts/mips/JHR-N825R.dts +++ b/sys/gnu/dts/mips/JHR-N825R.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "JHR-N825R", "ralink,rt3052-soc"; model = "JCG JHR-N825R"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x2e>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; system { @@ -79,3 +58,24 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x2e>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/JHR-N926R.dts b/sys/gnu/dts/mips/JHR-N926R.dts index f4dfd10..1a63656 100644 --- a/sys/gnu/dts/mips/JHR-N926R.dts +++ b/sys/gnu/dts/mips/JHR-N926R.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "JHR-N926R", "ralink,rt3052-soc"; model = "JCG JHR-N926R"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x2e>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -125,3 +104,24 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x2e>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/LINKIT7688.dts b/sys/gnu/dts/mips/LINKIT7688.dts index 2dfb98c..ac8b035 100644 --- a/sys/gnu/dts/mips/LINKIT7688.dts +++ b/sys/gnu/dts/mips/LINKIT7688.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7628an.dtsi" +#include "mt7628an.dtsi" / { compatible = "mediatek,linkit", "mediatek,mt7628an-soc"; @@ -10,133 +10,15 @@ bootargs = "console=ttyS2,57600"; }; + aliases { + serial0 = &uart2; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x8000000>; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "gpio"; - ralink,function = "gpio"; - }; - - perst { - ralink,group = "perst"; - ralink,function = "gpio"; - }; - - refclk { - ralink,group = "refclk"; - ralink,function = "gpio"; - }; - - i2s { - ralink,group = "i2s"; - ralink,function = "gpio"; - }; - - spis { - ralink,group = "spis"; - ralink,function = "gpio"; - }; - - wled_kn { - ralink,group = "wled_kn"; - ralink,function = "gpio"; - }; - - wled_an { - ralink,group = "wled_an"; - ralink,function = "wled_an"; - }; - - wdt { - ralink,group = "wdt"; - ralink,function = "gpio"; - }; - }; - }; - - wmac@10300000 { - status = "okay"; - }; - - palmbus@10000000 { - spi@b00 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>, <&spi_cs1_pins>; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l25635e"; - spi-max-frequency = <40000000>; - m25p,chunked-io = <31>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; - - spidev@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spidev"; - reg = <1 0>; - spi-max-frequency = <40000000>; - }; - }; - - i2c@900 { - status = "okay"; - }; - - uart1@d00 { - status = "okay"; - }; - - uart2@e00 { - status = "okay"; - }; - - pwm@5000 { - status = "okay"; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - sdhci@10130000 { - status = "okay"; - mediatek,cd-high; - }; - bootstrap { compatible = "mediatek,linkit"; @@ -145,7 +27,7 @@ gpio-leds { compatible = "gpio-leds"; - + wifi { label = "mediatek:orange:wifi"; gpios = <&wgpio 0 0>; @@ -158,7 +40,7 @@ #address-cells = <1>; #size-cells = <0>; poll-interval = <20>; - + wps { label = "reset"; gpios = <&gpio1 6 1>; @@ -173,5 +55,128 @@ gpio-controller; #gpio-cells = <2>; }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "gpio"; + ralink,function = "gpio"; + }; + + perst { + ralink,group = "perst"; + ralink,function = "gpio"; + }; + + refclk { + ralink,group = "refclk"; + ralink,function = "gpio"; + }; + + i2s { + ralink,group = "i2s"; + ralink,function = "gpio"; + }; + + spis { + ralink,group = "spis"; + ralink,function = "gpio"; + }; + + wled_kn { + ralink,group = "wled_kn"; + ralink,function = "gpio"; + }; + + wled_an { + ralink,group = "wled_an"; + ralink,function = "wled_an"; + }; + + wdt { + ralink,group = "wdt"; + ralink,function = "gpio"; + }; + }; +}; + +&wmac { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>, <&spi_cs1_pins>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l25635e"; + spi-max-frequency = <40000000>; + m25p,chunked-io = <31>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; + }; + + spidev@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spidev"; + reg = <1 0>; + spi-max-frequency = <40000000>; + }; +}; + +&i2c { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&pwm { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&sdhci { + status = "okay"; + mediatek,cd-high; +}; +&wmac { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/M2M.dts b/sys/gnu/dts/mips/M2M.dts index c547b5f..961ad2d 100644 --- a/sys/gnu/dts/mips/M2M.dts +++ b/sys/gnu/dts/mips/M2M.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "M2M", "ralink,rt5350-soc"; @@ -10,53 +10,6 @@ bootargs = "console=ttyS0,57600n8 root=/dev/mtdblock5"; }; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "Bootloader"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "Config"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "Factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -89,24 +42,69 @@ linux,code = <0x198>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; +&spi0 { + status = "okay"; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "Bootloader"; + reg = <0x0 0x30000>; + read-only; + }; - ehci@101c0000 { - status = "okay"; - }; + partition@30000 { + label = "Config"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "Factory"; + reg = <0x40000 0x10000>; + read-only; + }; - ohci@101c1000 { - status = "okay"; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; }; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0x0>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0x0>; +}; diff --git a/sys/gnu/dts/mips/M3.dts b/sys/gnu/dts/mips/M3.dts index 0a78afe..2b56cf7 100644 --- a/sys/gnu/dts/mips/M3.dts +++ b/sys/gnu/dts/mips/M3.dts @@ -1,67 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "M3", "ralink,rt5350-soc"; model = "Poray M3"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q32"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -90,17 +34,71 @@ linux,input-type = <5>; }; }; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; - }; +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q32"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - ehci@101c0000 { - status = "okay"; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; }; +}; - ohci@101c1000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <1>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; + ralink,led-polarity = <1>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/M4-4M.dts b/sys/gnu/dts/mips/M4-4M.dts index d99e37a..b6f869d 100644 --- a/sys/gnu/dts/mips/M4-4M.dts +++ b/sys/gnu/dts/mips/M4-4M.dts @@ -1,67 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "M4", "ralink,rt5350-soc"; model = "Poray M4"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "pm25lq032"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -83,12 +27,66 @@ linux,code = <0x198>; }; }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "pm25lq032"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; - ehci@101c0000 { - status = "okay"; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; }; +}; - ohci@101c1000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <1>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/M4-8M.dts b/sys/gnu/dts/mips/M4-8M.dts index b9a2730..3dff876 100644 --- a/sys/gnu/dts/mips/M4-8M.dts +++ b/sys/gnu/dts/mips/M4-8M.dts @@ -1,67 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "M4", "ralink,rt5350-soc"; model = "Poray M4"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "gd25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -83,17 +27,71 @@ linux,code = <0x198>; }; }; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; - }; +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "gd25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - ehci@101c0000 { - status = "okay"; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; }; +}; - ohci@101c1000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <1>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; + ralink,led-polarity = <1>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/MINIEMBPLUG.dts b/sys/gnu/dts/mips/MINIEMBPLUG.dts index 12ff3b1..146235e 100644 --- a/sys/gnu/dts/mips/MINIEMBPLUG.dts +++ b/sys/gnu/dts/mips/MINIEMBPLUG.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "MINIEMBPLUG", "ralink,rt5350-soc"; model = "Omnima MiniEMBPlug"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -59,62 +50,73 @@ linux,code = <0x211>; }; }; +}; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; }; + }; +}; - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; }; - }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; }; +}; - otg@101c0000 { - status = "okay"; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/MINIEMBWIFI.dts b/sys/gnu/dts/mips/MINIEMBWIFI.dts index 70557f9..1240ade 100644 --- a/sys/gnu/dts/mips/MINIEMBWIFI.dts +++ b/sys/gnu/dts/mips/MINIEMBWIFI.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "MINIEMBWIFI", "ralink,rt3052-soc"; model = "Omnima MiniEMBWiFi"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -73,20 +64,29 @@ reg = <0x50000 0x7b0000>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +ðernet { + mtd-mac-address = <&factory 0x28>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; - otg@101c0000 { - status = "okay"; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/MIWIFI-MINI.dts b/sys/gnu/dts/mips/MIWIFI-MINI.dts index 81a128e..66c8cb2 100644 --- a/sys/gnu/dts/mips/MIWIFI-MINI.dts +++ b/sys/gnu/dts/mips/MIWIFI-MINI.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "xiaomi,miwifi-mini", "ralink,mt7620a-soc"; @@ -10,117 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio1: gpio@638 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf80000>; - }; - - partition@fd0000 { - label = "crash"; - reg = <0xfd0000 0x10000>; - }; - - partition@fe0000 { - label = "reserved"; - reg = <0xfe0000 0x10000>; - read-only; - }; - - partition@ff0000 { - label = "Bdata"; - reg = <0xff0000 0x10000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pcie@10140000 { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "rgmii1"; - ralink,function = "gpio"; - }; - - pa { - ralink,group = "pa"; - ralink,function = "pa"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -153,3 +42,112 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xf80000>; + }; + + partition@fd0000 { + label = "crash"; + reg = <0xfd0000 0x10000>; + }; + + partition@fe0000 { + label = "reserved"; + reg = <0xfe0000 0x10000>; + read-only; + }; + + partition@ff0000 { + label = "Bdata"; + reg = <0xff0000 0x10000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; + + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "rgmii1"; + ralink,function = "gpio"; + }; + + pa { + ralink,group = "pa"; + ralink,function = "pa"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/MIWIFI-NANO.dts b/sys/gnu/dts/mips/MIWIFI-NANO.dts index 363b90d..8a46e6d 100644 --- a/sys/gnu/dts/mips/MIWIFI-NANO.dts +++ b/sys/gnu/dts/mips/MIWIFI-NANO.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7628an.dtsi" +#include "mt7628an.dtsi" / { compatible = "xiaomi,MiWifi Nano", "mediatek,mt7628an-soc"; @@ -15,15 +15,6 @@ reg = <0x0 0x4000000>; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "refclk", "wled", "gpio"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -44,48 +35,54 @@ }; }; +}; - - wmac@10300000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "refclk", "wled", "gpio"; + ralink,function = "gpio"; + }; }; +}; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - m25p,chunked-io = <32>; +&wmac { + status = "okay"; +}; - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + m25p,chunked-io = <32>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; }; }; }; diff --git a/sys/gnu/dts/mips/MLW221.dts b/sys/gnu/dts/mips/MLW221.dts index ab8e4c0..7ac130f 100644 --- a/sys/gnu/dts/mips/MLW221.dts +++ b/sys/gnu/dts/mips/MLW221.dts @@ -1,92 +1,11 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "mlw221", "ralink,mt7620n-soc"; model = "Kingston MLW221"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl129p1"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf60000>; - }; - - partition@fb0000 { - label = "user-config"; - reg = <0xfb0000 0x50000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "ephy", "wled"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -120,3 +39,82 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl129p1"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xf60000>; + }; + + partition@fb0000 { + label = "user-config"; + reg = <0xfb0000 0x50000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "i2c", "ephy", "wled"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/MLWG2.dts b/sys/gnu/dts/mips/MLWG2.dts index e08475e..29a484f 100644 --- a/sys/gnu/dts/mips/MLWG2.dts +++ b/sys/gnu/dts/mips/MLWG2.dts @@ -1,92 +1,11 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "mlwg2", "ralink,mt7620n-soc"; model = "Kingston MLWG2"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf60000>; - }; - - partition@fb0000 { - label = "user-config"; - reg = <0xfb0000 0x50000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "ephy", "wled"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -120,3 +39,82 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xf60000>; + }; + + partition@fb0000 { + label = "user-config"; + reg = <0xfb0000 0x50000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "i2c", "ephy", "wled"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/MOFI3500-3GN.dts b/sys/gnu/dts/mips/MOFI3500-3GN.dts index 9bd1f42..633f20a 100644 --- a/sys/gnu/dts/mips/MOFI3500-3GN.dts +++ b/sys/gnu/dts/mips/MOFI3500-3GN.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "MOFI3500-3GN", "ralink,rt3052-soc"; model = "MoFi Network MOFI3500-3GN"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,10 +38,6 @@ }; }; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -99,13 +86,26 @@ linux,code = <0x211>; }; }; +}; - wmac@10180000 { - status = "okay"; - ralink,mtd-eeprom = <&factory 0>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - otg@101c0000 { - status = "okay"; - }; +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + status = "okay"; + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/MPRA1.dts b/sys/gnu/dts/mips/MPRA1.dts index 9730748..969020c 100644 --- a/sys/gnu/dts/mips/MPRA1.dts +++ b/sys/gnu/dts/mips/MPRA1.dts @@ -1,82 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "MPRA1", "ralink,rt5350-soc"; model = "HAME MPR-A1"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - - gpio1: gpio@660 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf", "led"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -121,3 +50,72 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf", "led"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/MPRA2.dts b/sys/gnu/dts/mips/MPRA2.dts index 86c741f..4d1a53a 100644 --- a/sys/gnu/dts/mips/MPRA2.dts +++ b/sys/gnu/dts/mips/MPRA2.dts @@ -1,78 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "MPRA2", "ralink,rt5350-soc"; model = "HAME MPR-A2"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -117,3 +50,68 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/MR-102N.dts b/sys/gnu/dts/mips/MR-102N.dts index 2b61397..6546601 100644 --- a/sys/gnu/dts/mips/MR-102N.dts +++ b/sys/gnu/dts/mips/MR-102N.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "MR-102N", "ralink,rt3052-soc"; model = "AXIMCom MR-102N"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -57,20 +48,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - status = "okay"; - #mediatek,portmap = <0x3e>; - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -108,8 +85,32 @@ linux,code = <0x211>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + status = "okay"; + #mediatek,portmap = <0x3e>; + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/MT7620a.dts b/sys/gnu/dts/mips/MT7620a.dts index db138e3..debe52e 100644 --- a/sys/gnu/dts/mips/MT7620a.dts +++ b/sys/gnu/dts/mips/MT7620a.dts @@ -1,127 +1,125 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; model = "Ralink MT7620a + MT7610e evaluation board"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; + gpio-keys-polled { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + s2 { + label = "S2"; + gpios = <&gpio0 1 1>; + linux,code = <0x100>; }; - }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf"; - ralink,function = "gpio"; - }; + s3 { + label = "S3"; + gpios = <&gpio0 2 1>; + linux,code = <0x101>; }; }; +}; - ethernet@10100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "llllw"; +&spi0 { + status = "okay"; - port@4 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy4>; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; }; - port@5 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy5>; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; }; - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; }; }; +}; - gsw@10110000 { - mediatek,port4 = "gmac"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf"; + ralink,function = "gpio"; + }; }; +}; + +ðernet { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; + mediatek,portmap = "llllw"; - sdhci@10130000 { + port@4 { status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy4>; }; - pcie@10140000 { + port@5 { status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy5>; }; - gpio-keys-polled { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; + mdio-bus { + status = "okay"; - s2 { - label = "S2"; - gpios = <&gpio0 1 1>; - linux,code = <0x100>; + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii"; }; - s3 { - label = "S3"; - gpios = <&gpio0 2 1>; - linux,code = <0x101>; + phy5: ethernet-phy@5 { + reg = <5>; + phy-mode = "rgmii"; }; }; +}; - ehci@101c0000 { - status = "okay"; - }; +&gsw { + mediatek,port4 = "gmac"; +}; - ohci@101c1000 { - status = "okay"; - }; +&sdhci { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/MT7620a_MT7530.dts b/sys/gnu/dts/mips/MT7620a_MT7530.dts index 784cc98..5fa87fb 100644 --- a/sys/gnu/dts/mips/MT7620a_MT7530.dts +++ b/sys/gnu/dts/mips/MT7620a_MT7530.dts @@ -1,119 +1,117 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; model = "Ralink MT7620a + MT7530 evaluation board"; +}; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; }; - }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf"; - ralink,function = "gpio"; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; }; - }; - - ethernet@10100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "llllw"; - port@5 { - status = "okay"; - mediatek,fixed-link = <1000 1 1 1>; - phy-mode = "rgmii"; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; }; - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - phy-mode = "rgmii"; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - phy-mode = "rgmii"; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - phy-mode = "rgmii"; - }; - - phy3: ethernet-phy@3 { - reg = <3>; - phy-mode = "rgmii"; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy1f: ethernet-phy@1f { - reg = <0x1f>; - phy-mode = "rgmii"; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; }; }; +}; - gsw@10110000 { - mediatek,port4 = "gmac"; - mediatek,mt7530 = <1>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf"; + ralink,function = "gpio"; + }; }; +}; - pcie@10140000 { - status = "okay"; - }; +ðernet { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; + mediatek,portmap = "llllw"; - ehci@101c0000 { + port@5 { status = "okay"; + mediatek,fixed-link = <1000 1 1 1>; + phy-mode = "rgmii"; }; - ohci@101c1000 { + mdio-bus { status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rgmii"; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + phy-mode = "rgmii"; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + phy-mode = "rgmii"; + }; + + phy3: ethernet-phy@3 { + reg = <3>; + phy-mode = "rgmii"; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii"; + }; + + phy1f: ethernet-phy@1f { + reg = <0x1f>; + phy-mode = "rgmii"; + }; }; }; + +&gsw { + mediatek,port4 = "gmac"; + mediatek,mt7530 = <1>; +}; + +&pcie { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/MT7620a_MT7610e.dts b/sys/gnu/dts/mips/MT7620a_MT7610e.dts index 4e3ba1e..99e1f80 100644 --- a/sys/gnu/dts/mips/MT7620a_MT7610e.dts +++ b/sys/gnu/dts/mips/MT7620a_MT7610e.dts @@ -1,72 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; model = "Ralink MT7620A evaluation board"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <1000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - ethernet@10100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mediatek,portmap = "llllw"; - }; - - gsw@10110000 { - mediatek,port4 = "ephy"; - }; - - sdhci@10130000 { - status = "okay"; - }; - - pcie@10140000 { - status = "okay"; - }; - gpio-keys-polled { compatible = "gpio-keys"; #address-cells = <1>; @@ -86,3 +25,62 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <1000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +ðernet { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mediatek,portmap = "llllw"; +}; + +&gsw { + mediatek,port4 = "ephy"; +}; + +&sdhci { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/MT7620a_V22SG.dts b/sys/gnu/dts/mips/MT7620a_V22SG.dts index f56d592..a3e206e 100644 --- a/sys/gnu/dts/mips/MT7620a_V22SG.dts +++ b/sys/gnu/dts/mips/MT7620a_V22SG.dts @@ -1,69 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; model = "Ralink MT7620a V22SG High Power evaluation board"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "spi"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "llllw"; - - port@4 { - status = "okay"; - phy-handle = <&phy4>; - phy-mode = "rgmii"; - }; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; - }; - - gsw@10110000 { - mediatek,port4 = "gmac"; - }; - - pcie@10140000 { - status = "okay"; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -112,3 +54,61 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "spi"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; + mediatek,portmap = "llllw"; + + port@4 { + status = "okay"; + phy-handle = <&phy4>; + phy-mode = "rgmii"; + }; + + port@5 { + status = "okay"; + phy-handle = <&phy5>; + phy-mode = "rgmii"; + }; + + mdio-bus { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii"; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + phy-mode = "rgmii"; + }; + }; +}; + +&gsw { + mediatek,port4 = "gmac"; +}; + +&pcie { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/MT7621.dts b/sys/gnu/dts/mips/MT7621.dts index 341d8f2..4013f3c 100644 --- a/sys/gnu/dts/mips/MT7621.dts +++ b/sys/gnu/dts/mips/MT7621.dts @@ -15,23 +15,6 @@ bootargs = "console=ttyS0,57600"; }; - sdhci@10130000 { - status = "okay"; - }; - - xhci@1E1C0000 { - status = "okay"; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; - ralink,function = "gpio"; - }; - }; - }; - nand@1e003000 { partition@0 { label = "uboot"; @@ -54,3 +37,20 @@ }; }; }; + +&sdhci { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/MT7628.dts b/sys/gnu/dts/mips/MT7628.dts index 5e5b0a1..0f15b4f 100644 --- a/sys/gnu/dts/mips/MT7628.dts +++ b/sys/gnu/dts/mips/MT7628.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7628an.dtsi" +#include "mt7628an.dtsi" / { compatible = "mediatek,mt7628an-eval-board", "mediatek,mt7628an-soc"; @@ -10,56 +10,58 @@ device_type = "memory"; reg = <0x0 0x2000000>; }; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag"; - ralink,function = "gpio"; - }; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag"; + ralink,function = "gpio"; }; }; +}; - wmac@10300000 { - status = "okay"; - }; +&wmac { + status = "okay"; +}; - palmbus@10000000 { - spi@b00 { - status = "okay"; +&spi0 { + status = "okay"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - m25p,chunked-io = <32>; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <10000000>; + m25p,chunked-io = <32>; - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; }; }; }; + +&wmac { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/MZK-750DHP.dts b/sys/gnu/dts/mips/MZK-750DHP.dts index df0b73b..849c02cc 100644 --- a/sys/gnu/dts/mips/MZK-750DHP.dts +++ b/sys/gnu/dts/mips/MZK-750DHP.dts @@ -1,93 +1,28 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-soc"; model = "Planex MZK-750DHP"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "spi refclk", "rgmii1"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - - gsw@10110000 { - mediatek,port4 = "ephy"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pcie@10140000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; wps { label = "mzk-750dhp:green:wps"; - gpios = <&gpio1 11 1>; + gpios = <&gpio2 15 1>; }; power { label = "mzk-750dhp:green:power"; gpios = <&gpio1 15 1>; }; + + wlan5g { + label = "mzk-750dhp:green:wlan5g"; + gpios = <&gpio1 14 1>; + }; }; gpio-keys-polled { @@ -99,13 +34,94 @@ s1 { label = "reset"; gpios = <&gpio0 1 1>; - linux,code = <0x100>; + linux,code = <0x198>; }; s2 { label = "wps"; - gpios = <&gpio0 2 1>; + gpios = <&gpio2 19 1>; linux,code = <0x211>; }; }; }; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi refclk", "rgmii1", "nd_sd"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&gsw { + mediatek,port4 = "ephy"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; + + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; +}; diff --git a/sys/gnu/dts/mips/MZK-DP150N.dts b/sys/gnu/dts/mips/MZK-DP150N.dts index 8211839..c34ecb1 100644 --- a/sys/gnu/dts/mips/MZK-DP150N.dts +++ b/sys/gnu/dts/mips/MZK-DP150N.dts @@ -1,81 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "MZK-DP150N", "ralink,rt5350-soc"; model = "Planex MZK-DP150N"; - palmbus@10000000 { - gpio1: gpio@660 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - - spidev@1 { - compatible = "linux,spidev"; - spi-max-frequency = <10000000>; - reg = <1>; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag", "uartf", "led"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x17>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -98,3 +28,71 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "uboot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; + + spidev@1 { + compatible = "linux,spidev"; + spi-max-frequency = <10000000>; + reg = <1 0>; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "jtag", "uartf", "led"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x17>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; + ralink,led-polarity = <1>; +}; diff --git a/sys/gnu/dts/mips/MZK-EX300NP.dts b/sys/gnu/dts/mips/MZK-EX300NP.dts new file mode 100644 index 0000000..07432e2 --- /dev/null +++ b/sys/gnu/dts/mips/MZK-EX300NP.dts @@ -0,0 +1,130 @@ +/dts-v1/; + +#include "mt7620a.dtsi" + +/ { + compatible = "ralink,mt7620a-soc"; + model = "Planex MZK-EX300NP"; + + gpio-leds { + compatible = "gpio-leds"; + + wifi { + label = "mzk-ex300np:green:wifi"; + gpios = <&gpio3 0 1>; + }; + + wps { + label = "mzk-ex300np:green:wps"; + gpios = <&gpio1 5 1>; + }; + + rep { + label = "mzk-ex300np:blue:rep"; + gpios = <&gpio1 4 1>; + }; + + wifi1 { + label = "mzk-ex300np:blue:wifi1"; + gpios = <&gpio1 1 1>; + }; + + wifi2 { + label = "mzk-ex300np:blue:wifi2"; + gpios = <&gpio1 2 1>; + }; + + wifi3 { + label = "mzk-ex300np:blue:wifi3"; + gpios = <&gpio1 0 1>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 1 1>; + linux,code = <0x198>; + }; + + wps { + label = "wps"; + gpios = <&gpio1 3 0>; + linux,code = <0x211>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x730000>; + }; + + partition@780000 { + label = "Udata"; + reg = <0x780000 0x80000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "spi refclk", "rgmii1", "wled"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/MZK-EX750NP.dts b/sys/gnu/dts/mips/MZK-EX750NP.dts new file mode 100644 index 0000000..cecc58a --- /dev/null +++ b/sys/gnu/dts/mips/MZK-EX750NP.dts @@ -0,0 +1,148 @@ +/dts-v1/; + +#include "mt7620a.dtsi" + +/ { + compatible = "ralink,mt7620a-soc"; + model = "Planex MZK-EX750NP"; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "mzk-ex750np:red:power"; + gpios = <&gpio0 14 1>; + }; + + wifi { + label = "mzk-ex750np:red:wifi"; + gpios = <&gpio3 0 1>; + }; + + wps { + label = "mzk-ex750np:green:wps"; + gpios = <&gpio0 10 1>; + }; + + rep { + label = "mzk-ex750np:blue:rep"; + gpios = <&gpio2 16 1>; + }; + + wifi1 { + label = "mzk-ex750np:blue:wifi1"; + gpios = <&gpio2 19 1>; + }; + + wifi2 { + label = "mzk-ex750np:blue:wifi2"; + gpios = <&gpio2 18 1>; + }; + + wifi3 { + label = "mzk-ex750np:blue:wifi3"; + gpios = <&gpio2 17 1>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 9 1>; + linux,code = <0x198>; + }; + + wps { + label = "wps"; + gpios = <&gpio0 13 0>; + linux,code = <0x211>; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x730000>; + }; + + partition@780000 { + label = "Udata"; + reg = <0x780000 0x80000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "uartf", "nd_sd", "rgmii2", "wled"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; + + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; +}; diff --git a/sys/gnu/dts/mips/MZK-W300NH2.dts b/sys/gnu/dts/mips/MZK-W300NH2.dts index 8b4335e..987d6a7 100644 --- a/sys/gnu/dts/mips/MZK-W300NH2.dts +++ b/sys/gnu/dts/mips/MZK-W300NH2.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "MZK-W300NH2", "ralink,rt3052-soc"; model = "Planex MZK-W300NH2"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -53,18 +44,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -109,3 +88,24 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/MZK-WDPR.dts b/sys/gnu/dts/mips/MZK-WDPR.dts index 1746949..ff26b15 100644 --- a/sys/gnu/dts/mips/MZK-WDPR.dts +++ b/sys/gnu/dts/mips/MZK-WDPR.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "MZK-WDPR", "ralink,rt3052-soc"; @@ -10,15 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -58,22 +49,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - otg@101c0000 { - status = "okay"; - }; - gpio-export { compatible = "gpio-export"; @@ -84,3 +59,28 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/MicroWRT.dts b/sys/gnu/dts/mips/MicroWRT.dts index fb00375..584cd1c 100644 --- a/sys/gnu/dts/mips/MicroWRT.dts +++ b/sys/gnu/dts/mips/MicroWRT.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "microwrt", "ralink,mt7620a-soc"; @@ -10,84 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "u-boot-env"; - reg = <0x20000 0x10000>; - read-only; - }; - - factory: partition@30000 { - label = "factory"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0xfc0000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - pcie@10140000 { - status = "okay"; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "wled", "i2c", "wdt", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -107,3 +29,79 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "u-boot-env"; + reg = <0x20000 0x10000>; + read-only; + }; + + factory: partition@30000 { + label = "factory"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "firmware"; + reg = <0x40000 0xfc0000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "wled", "i2c", "wdt", "uartf"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/NA930.dts b/sys/gnu/dts/mips/NA930.dts index ade3356..4093932 100644 --- a/sys/gnu/dts/mips/NA930.dts +++ b/sys/gnu/dts/mips/NA930.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; @@ -10,34 +10,6 @@ bootargs = "console=ttyS1,57600"; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "rgmii2", "spi", "ephy"; - ralink,function = "gpio"; - }; - - uartf_gpio { - ralink,group = "uartf"; - ralink,function = "gpio uartf"; - }; - }; - }; - - palmbus@10000000 { - uart@500 { - status = "okay"; - }; - - gpio@638 { - status = "okay"; - }; - - gpio@660 { - status = "okay"; - }; - }; - nand { #address-cells = <1>; #size-cells = <1>; @@ -67,39 +39,6 @@ }; }; - ethernet@10100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &mdio_pins>; - mediatek,portmap = "llllw"; - - port@4 { - status = "okay"; - phy-handle = <&phy4>; - phy-mode = "rgmii"; - }; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -159,16 +98,75 @@ gpios = <&gpio0 13 0>; }; }; +}; - gsw@10110000 { - mediatek,port4 = "gmac"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "rgmii2", "spi", "ephy"; + ralink,function = "gpio"; + }; + + uartf_gpio { + ralink,group = "uartf"; + ralink,function = "gpio uartf"; + }; }; +}; + +&uart { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; - ehci@101c0000 { +&gpio2 { + status = "okay"; +}; + +ðernet { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &mdio_pins>; + mediatek,portmap = "llllw"; + + port@4 { status = "okay"; + phy-handle = <&phy4>; + phy-mode = "rgmii"; }; - ohci@101c1000 { + port@5 { status = "okay"; + phy-handle = <&phy5>; + phy-mode = "rgmii"; }; + + mdio-bus { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii"; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + phy-mode = "rgmii"; + }; + }; +}; + +&gsw { + mediatek,port4 = "gmac"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/NBG-419N.dts b/sys/gnu/dts/mips/NBG-419N.dts index 0043812..59ab665 100644 --- a/sys/gnu/dts/mips/NBG-419N.dts +++ b/sys/gnu/dts/mips/NBG-419N.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "NBG-419N", "ralink,rt3052-soc"; model = "ZyXEL NBG-419N"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -92,3 +71,24 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/NCS601W.dts b/sys/gnu/dts/mips/NCS601W.dts index a7f1212e..57b9244 100644 --- a/sys/gnu/dts/mips/NCS601W.dts +++ b/sys/gnu/dts/mips/NCS601W.dts @@ -1,75 +1,73 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "NCS601W", "ralink,rt5350-soc"; model = "Wansview NCS601W"; +}; - palmbus@10000000 { - spi@b00 { - status = "okay"; +&spi0 { + status = "okay"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; }; }; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; - ehci@101c0000 { - status = "okay"; - }; +&ehci { + status = "okay"; +}; - ohci@101c1000 { - status = "okay"; - }; +&ohci { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/NW718.dts b/sys/gnu/dts/mips/NW718.dts index 8405b7a..5480ef3 100644 --- a/sys/gnu/dts/mips/NW718.dts +++ b/sys/gnu/dts/mips/NW718.dts @@ -1,70 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "NW718", "ralink,rt3050-soc"; model = "Netcore NW718"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <25000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "config"; - reg = <0x30000 0x20000>; - read-only; - }; - - factory: partition@50000 { - label = "factory"; - reg = <0x50000 0x10000>; - read-only; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0x3a0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -102,8 +43,65 @@ linux,code = <0x211>; }; }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <25000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "config"; + reg = <0x30000 0x20000>; + read-only; + }; + + factory: partition@50000 { + label = "factory"; + reg = <0x50000 0x10000>; + read-only; + }; + + partition@60000 { + label = "firmware"; + reg = <0x60000 0x3a0000>; + }; + }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/OY-0001.dts b/sys/gnu/dts/mips/OY-0001.dts index c9680d1..ffd9ac7 100644 --- a/sys/gnu/dts/mips/OY-0001.dts +++ b/sys/gnu/dts/mips/OY-0001.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-soc"; @@ -10,76 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mediatek,portmap = "llllw"; - }; - - gsw@10110000 { - mediatek,port4 = "ephy"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -94,22 +24,6 @@ }; }; - sdhci@10130000 { - status = "okay"; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - pcie@10140000 { - status = "okay"; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -123,3 +37,86 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mediatek,portmap = "llllw"; +}; + +&gsw { + mediatek,port4 = "ephy"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&sdhci { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/PBR-M1.dts b/sys/gnu/dts/mips/PBR-M1.dts index 9703a1b..d876e4f 100644 --- a/sys/gnu/dts/mips/PBR-M1.dts +++ b/sys/gnu/dts/mips/PBR-M1.dts @@ -15,55 +15,8 @@ bootargs = "console=ttyS0,115200"; }; - sdhci@10130000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; - }; - - xhci@1E1C0000 { - status = "okay"; - }; - - palmbus@1E000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - - }; - }; - - i2c@900 { + palmbus: palmbus@1E000000 { + i2c: i2c@900 { compatible = "ralink,i2c-mt7621"; reg = <0x900 0x100>; #address-cells = <1>; @@ -80,32 +33,6 @@ }; }; - pcie@1e140000 { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; - }; - - ethernet@1e100000 { - mtd-mac-address = <&factory 0xe000>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -175,13 +102,87 @@ compatible = "gpio-beeper"; gpios = <&gpio0 26 1>; }; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wdt", "rgmii2", "jtag", "mdio"; - ralink,function = "gpio"; - }; +&sdhci { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; +}; + +&xhci { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,5ghz = <0>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe000>; +}; + + + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "wdt", "rgmii2", "jtag", "mdio"; + ralink,function = "gpio"; }; }; }; diff --git a/sys/gnu/dts/mips/PSG1208.dts b/sys/gnu/dts/mips/PSG1208.dts index c3be8ef..92a8de8 100644 --- a/sys/gnu/dts/mips/PSG1208.dts +++ b/sys/gnu/dts/mips/PSG1208.dts @@ -1,90 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "PSG1208", "ralink,mt7620a-soc"; model = "Phicomm PSG1208"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@20000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@30000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - - pcie@10140000 { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -112,3 +33,80 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@20000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@30000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@40000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&pcie { + status = "okay"; + + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/PSR-680W.dts b/sys/gnu/dts/mips/PSR-680W.dts index c5a600a..c4c4522 100644 --- a/sys/gnu/dts/mips/PSR-680W.dts +++ b/sys/gnu/dts/mips/PSR-680W.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "PSR-680W", "ralink,rt3052-soc"; @@ -10,15 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -51,18 +42,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -84,8 +63,29 @@ linux,code = <0x198>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/PWH2004.dts b/sys/gnu/dts/mips/PWH2004.dts index 23ef1ff..51f4392 100644 --- a/sys/gnu/dts/mips/PWH2004.dts +++ b/sys/gnu/dts/mips/PWH2004.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "PWH2004", "ralink,rt3052-soc"; model = "Prolink PWH2004"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -73,12 +64,21 @@ linux,code = <0x198>; }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; }; diff --git a/sys/gnu/dts/mips/PX-4885-4M.dts b/sys/gnu/dts/mips/PX-4885-4M.dts index 10c784c..bd8a5a4 100644 --- a/sys/gnu/dts/mips/PX-4885-4M.dts +++ b/sys/gnu/dts/mips/PX-4885-4M.dts @@ -1,43 +1,39 @@ /dts-v1/; -/include/ "PX-4885.dtsi" +#include "PX-4885.dtsi" -/ { - palmbus@10000000 { - spi@b00 { - status = "okay"; +&spi0 { + status = "okay"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; + partition@0 { + label = "u-boot"; + reg = <0x0 0x20000>; + read-only; + }; - partition@20000 { - label = "devdata"; - reg = <0x20000 0x20000>; - read-only; - }; + partition@20000 { + label = "devdata"; + reg = <0x20000 0x20000>; + read-only; + }; - factory: partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; + factory: partition@40000 { + label = "devconf"; + reg = <0x40000 0x10000>; + read-only; + }; - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; }; }; }; diff --git a/sys/gnu/dts/mips/PX-4885-8M.dts b/sys/gnu/dts/mips/PX-4885-8M.dts index d4a0273..6dd13be 100644 --- a/sys/gnu/dts/mips/PX-4885-8M.dts +++ b/sys/gnu/dts/mips/PX-4885-8M.dts @@ -1,43 +1,39 @@ /dts-v1/; -/include/ "PX-4885.dtsi" +#include "PX-4885.dtsi" -/ { - palmbus@10000000 { - spi@b00 { - status = "okay"; +&spi0 { + status = "okay"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; - partition@0 { - label = "u-boot"; - reg = <0x0 0x20000>; - read-only; - }; + partition@0 { + label = "u-boot"; + reg = <0x0 0x20000>; + read-only; + }; - partition@20000 { - label = "devdata"; - reg = <0x20000 0x20000>; - read-only; - }; + partition@20000 { + label = "devdata"; + reg = <0x20000 0x20000>; + read-only; + }; - factory: partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; + factory: partition@40000 { + label = "devconf"; + reg = <0x40000 0x10000>; + read-only; + }; - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; }; }; }; diff --git a/sys/gnu/dts/mips/PX-4885.dtsi b/sys/gnu/dts/mips/PX-4885.dtsi index 05959ca..ba862fc 100644 --- a/sys/gnu/dts/mips/PX-4885.dtsi +++ b/sys/gnu/dts/mips/PX-4885.dtsi @@ -1,30 +1,9 @@ -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "PX-4885", "ralink,rt5350-soc"; model = "7Links PX-4885"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -52,3 +31,24 @@ }; }; }; + +&pinctrl { + state_default { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/RE6500.dts b/sys/gnu/dts/mips/RE6500.dts index 9887c28..e26b76e 100644 --- a/sys/gnu/dts/mips/RE6500.dts +++ b/sys/gnu/dts/mips/RE6500.dts @@ -15,79 +15,6 @@ bootargs = "console=ttyS0,57600"; }; - palmbus@1E000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2"; - ralink,function = "gpio"; - }; - }; - }; - - pcie@1e140000 { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,5ghz = <0>; - }; - }; - }; - - ethernet@1e100000 { - mtd-mac-address = <&factory 0x2e>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -121,3 +48,74 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uart2", "uart3", "rgmii2"; + ralink,function = "gpio"; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,2ghz = <0>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,5ghz = <0>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x2e>; +}; diff --git a/sys/gnu/dts/mips/RP-N53.dts b/sys/gnu/dts/mips/RP-N53.dts index 8ebceb2..9e56b14 100644 --- a/sys/gnu/dts/mips/RP-N53.dts +++ b/sys/gnu/dts/mips/RP-N53.dts @@ -1,94 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "asus,rp-n53", "ralink,mt7620a-soc"; model = "Asus RP-N53"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - - i2c@900 { - status = "okay"; - }; - - i2s@a00 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pcm_i2s_pins>; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - - pcm@2000 { - status = "okay"; - }; - - gdma@2800 { - status = "okay"; - }; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "mdio", "rgmii1"; - ralink,function = "gpio"; - }; - }; - }; - - gsw@10110000 { - mediatek,port4 = "ephy"; - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - }; - - pcie@10140000 { - status = "okay"; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -164,3 +81,84 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&i2c { + status = "okay"; +}; + +&i2s { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcm_i2s_pins>; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pcm { + status = "okay"; +}; + +&gdma { + status = "okay"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "mdio", "rgmii1"; + ralink,function = "gpio"; + }; + }; +}; + +&gsw { + mediatek,port4 = "ephy"; + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; +}; + +&pcie { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/RT-G32-B1.dts b/sys/gnu/dts/mips/RT-G32-B1.dts index 5dcaf22..886a940 100644 --- a/sys/gnu/dts/mips/RT-G32-B1.dts +++ b/sys/gnu/dts/mips/RT-G32-B1.dts @@ -1,70 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "RT-G32-B1", "ralink,rt3050-soc"; model = "Asus RT-G32 B1"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "devdata"; - reg = <0x30000 0x10000>; - read-only; - }; - - devconf: partition@40000 { - label = "devconf"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&devconf 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&devconf 0>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -84,3 +25,60 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "devdata"; + reg = <0x30000 0x10000>; + read-only; + }; + + devconf: partition@40000 { + label = "devconf"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&devconf 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&devconf 0>; +}; diff --git a/sys/gnu/dts/mips/RT-N10-PLUS.dts b/sys/gnu/dts/mips/RT-N10-PLUS.dts index ecd732e..43535d4 100644 --- a/sys/gnu/dts/mips/RT-N10-PLUS.dts +++ b/sys/gnu/dts/mips/RT-N10-PLUS.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "RT-N10-PLUS", "ralink,rt3050-soc"; @@ -38,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&devconf 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&devconf 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -78,3 +66,15 @@ }; }; }; + +ðernet { + mtd-mac-address = <&devconf 0x4>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&devconf 0>; +}; diff --git a/sys/gnu/dts/mips/RT-N13U.dts b/sys/gnu/dts/mips/RT-N13U.dts index 193bf1a..14cff67 100644 --- a/sys/gnu/dts/mips/RT-N13U.dts +++ b/sys/gnu/dts/mips/RT-N13U.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "RT-N13U", "ralink,rt3052-soc"; model = "Asus RT-N13U"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -79,20 +70,29 @@ linux,code = <0x211>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +ðernet { + mtd-mac-address = <&factory 0x28>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; - otg@101c0000 { - status = "okay"; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/RT-N14U.dts b/sys/gnu/dts/mips/RT-N14U.dts index 4c03c0d..9126f79 100644 --- a/sys/gnu/dts/mips/RT-N14U.dts +++ b/sys/gnu/dts/mips/RT-N14U.dts @@ -1,83 +1,11 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "asus,rt-n14u", "ralink,mt7620n-soc"; model = "Asus RT-N14U"; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "i2c"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -126,3 +54,73 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "ephy", "wled", "i2c"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/RT-N15.dts b/sys/gnu/dts/mips/RT-N15.dts index 8515463..d5bcbe3 100644 --- a/sys/gnu/dts/mips/RT-N15.dts +++ b/sys/gnu/dts/mips/RT-N15.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt2880.dtsi" +#include "rt2880.dtsi" / { #address-cells = <1>; @@ -8,21 +8,6 @@ compatible = "RT-N15", "ralink,rt2880-soc"; model = "Asus RT-N15"; - palmbus@300000 { - gpio0: gpio@600 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartlite", "mdio"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -55,34 +40,12 @@ }; }; - ethernet@400000 { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; - }; - }; - rtl8366s { compatible = "realtek,rtl8366s"; gpio-sda = <&gpio0 1 0>; gpio-sck = <&gpio0 2 0>; }; - wmac@480000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -111,3 +74,38 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartlite", "mdio"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x4>; + + port@0 { + mediatek,fixed-link = <1000 1 1 1>; + }; + + mdio-bus { + status = "okay"; + + phy0: ethernet-phy@0 { + phy-mode = "mii"; + reg = <0>; + }; + }; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/RT-N56U.dts b/sys/gnu/dts/mips/RT-N56U.dts index 0b6857d..d3a1f1b 100644 --- a/sys/gnu/dts/mips/RT-N56U.dts +++ b/sys/gnu/dts/mips/RT-N56U.dts @@ -1,73 +1,11 @@ /dts-v1/; -/include/ "rt3883.dtsi" +#include "rt3883.dtsi" / { compatible = "RT-N56U", "ralink,rt3883-soc"; model = "Asus RT-N56U"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; - }; - - pci@10140000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_pins>; - - pci_pins: pci { - pci { - ralink,group = "pci"; - ralink,function = "pci-fnc"; - }; - }; - - host-bridge { - pci-bridge@1 { - status = "okay"; - - wmac@0,0 { - compatible = "ralink,rt2880-pci", "pciclass060400", "pciclass0604"; - reg = < 0x10000 0 0 0 0 >; - ralink,eeprom = "rt2x00pci_1_0.eeprom"; - }; - }; - }; - }; - - wmac@10180000 { - status = "okay"; - ralink,2ghz = <0>; - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - nor-flash@1c000000 { compatible = "cfi-flash"; reg = <0x1c000000 0x800000>; @@ -149,3 +87,63 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + + port@0 { + mediatek,fixed-link = <1000 1 1 1>; + }; +}; + +&pci { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pci_pins>; + + pci_pins: pci { + pci { + ralink,group = "pci"; + ralink,function = "pci-fnc"; + }; + }; + + host-bridge { + pci-bridge@1 { + status = "okay"; + + wmac@0,0 { + compatible = "ralink,rt2880-pci", "pciclass060400", "pciclass0604"; + reg = < 0x10000 0 0 0 0 >; + ralink,eeprom = "rt2x00pci_1_0.eeprom"; + }; + }; + }; +}; + +&wmac { + status = "okay"; + ralink,2ghz = <0>; + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/RT5350F-OLINUXINO-EVB.dts b/sys/gnu/dts/mips/RT5350F-OLINUXINO-EVB.dts index 8d32230..aa69598 100644 --- a/sys/gnu/dts/mips/RT5350F-OLINUXINO-EVB.dts +++ b/sys/gnu/dts/mips/RT5350F-OLINUXINO-EVB.dts @@ -1,83 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "RT5350F-OLINUXINO-EVB", "ralink,rt5350-soc"; model = "Olimex RT5350F-OLinuXino-EVB"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - - gpio1: gpio@660 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio_export { compatible = "gpio-export"; #size-cells = <0>; @@ -100,3 +28,73 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <0x17>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/RT5350F-OLINUXINO.dts b/sys/gnu/dts/mips/RT5350F-OLINUXINO.dts index 169771e..e5f7650 100644 --- a/sys/gnu/dts/mips/RT5350F-OLINUXINO.dts +++ b/sys/gnu/dts/mips/RT5350F-OLINUXINO.dts @@ -1,80 +1,78 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "RT5350F-OLINUXINO", "ralink,rt5350-soc"; model = "Olimex RT5350F-OLinuXino"; +}; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; +&spi0 { + status = "okay"; - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; }; - gpio1: gpio@660 { - status = "okay"; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; }; }; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; +&gpio1 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <0x17>; - }; +&esw { + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <0x17>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; - ehci@101c0000 { - status = "okay"; - }; +&ehci { + status = "okay"; +}; - ohci@101c1000 { - status = "okay"; - }; +&ohci { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/RUT5XX.dts b/sys/gnu/dts/mips/RUT5XX.dts index fc9f3e4..d841263 100644 --- a/sys/gnu/dts/mips/RUT5XX.dts +++ b/sys/gnu/dts/mips/RUT5XX.dts @@ -1,70 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "RUT5XX", "ralink,rt3050-soc"; model = "Teltonika RUT5XX"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "n25q128a13"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -86,8 +27,65 @@ linux,code = <0x198>; }; }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "n25q128a13"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/SAP-G3200U3.dts b/sys/gnu/dts/mips/SAP-G3200U3.dts index 343742b..02af05d 100644 --- a/sys/gnu/dts/mips/SAP-G3200U3.dts +++ b/sys/gnu/dts/mips/SAP-G3200U3.dts @@ -15,76 +15,6 @@ bootargs = "console=ttyS0,57600"; }; - palmbus@1E000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x1000>; - read-only; - }; - - partition@31000 { - label = "config"; - reg = <0x31000 0xf000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pcie@1e140000 { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; - }; - - ethernet@1e100000 { - mtd-mac-address = <&factory 0xe006>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -112,13 +42,81 @@ linux,code = <0xf7>; }; }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x1000>; + read-only; + }; + + partition@31000 { + label = "config"; + reg = <0x31000 0xf000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,5ghz = <0>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe006>; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uart3", "jtag"; - ralink,function = "gpio"; - }; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "uart3", "jtag"; + ralink,function = "gpio"; }; }; }; diff --git a/sys/gnu/dts/mips/SK-WB8.dts b/sys/gnu/dts/mips/SK-WB8.dts new file mode 100644 index 0000000..bb1e382 --- /dev/null +++ b/sys/gnu/dts/mips/SK-WB8.dts @@ -0,0 +1,124 @@ +/dts-v1/; + +#include "mt7621.dtsi" + +/ { + compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; + model = "SamKnows Whitebox 8"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + wps { + label = "sk-wb8:green:wps"; + gpios = <&gpio1 14 1>; + }; + + usb { + label = "sk-wb8:green:usb"; + gpios = <&gpio1 15 1>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + wps { + label = "wps"; + gpios = <&gpio1 11 1>; + linux,code = <0x211>; + }; + reset { + label = "reset"; + gpios = <&gpio1 9 1>; + linux,code = <0x198>; + }; + }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + + partition@e30000 { + label = "recovery"; + reg = <0xe30000 0x1d0000>; + }; + + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,5ghz = <0>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe000>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/SL-R7205.dts b/sys/gnu/dts/mips/SL-R7205.dts index 9fe7845..f5884fb 100644 --- a/sys/gnu/dts/mips/SL-R7205.dts +++ b/sys/gnu/dts/mips/SL-R7205.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "SL-R7205", "ralink,rt3052-soc"; model = "Skyline SL-R7205 Wireless 3G Router"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -86,8 +65,29 @@ linux,code = <0x211>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/TEW-691GR.dts b/sys/gnu/dts/mips/TEW-691GR.dts index 5bd6444..750c24f 100644 --- a/sys/gnu/dts/mips/TEW-691GR.dts +++ b/sys/gnu/dts/mips/TEW-691GR.dts @@ -1,47 +1,11 @@ /dts-v1/; -/include/ "rt3883.dtsi" +#include "rt3883.dtsi" / { compatible = "TEW-691GR", "ralink,rt3883-soc"; model = "TRENDnet TEW-691GR"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - - port@0 { - phy-handle = <&phy0>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - }; - - wmac@10180000 { - ralink,5ghz = <0>; - }; - nor-flash@1c000000 { compatible = "cfi-flash"; reg = <0x1c000000 0x800000>; @@ -107,3 +71,37 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; + + port@0 { + phy-handle = <&phy0>; + phy-mode = "rgmii"; + }; + + mdio-bus { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&wmac { + ralink,5ghz = <0>; +}; diff --git a/sys/gnu/dts/mips/TEW-692GR.dts b/sys/gnu/dts/mips/TEW-692GR.dts index 17835f6..5bba8a5 100644 --- a/sys/gnu/dts/mips/TEW-692GR.dts +++ b/sys/gnu/dts/mips/TEW-692GR.dts @@ -1,67 +1,11 @@ /dts-v1/; -/include/ "rt3883.dtsi" +#include "rt3883.dtsi" / { compatible = "TEW-692GR", "ralink,rt3883-soc"; model = "TRENDnet TEW-692GR"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - status = "okay"; - mtd-mac-address = <&factory 0x28>; - - port@0 { - phy-handle = <&phy0>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; - }; - - pci@10140000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pci_pins>; - - pci_pins: pci { - pci { - ralink,group = "pci"; - ralink,function = "pci-fnc"; - }; - }; - - host-bridge { - pci-bridge@1 { - status = "okay"; - }; - }; - }; - - wmac@10180000 { - ralink,5ghz = <0>; - }; - nor-flash@1c000000 { compatible = "cfi-flash"; reg = <0x1c000000 0x800000>; @@ -126,3 +70,57 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x28>; + + port@0 { + phy-handle = <&phy0>; + phy-mode = "rgmii"; + }; + + mdio-bus { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&pci { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pci_pins>; + + pci_pins: pci { + pci { + ralink,group = "pci"; + ralink,function = "pci-fnc"; + }; + }; + + host-bridge { + pci-bridge@1 { + status = "okay"; + }; + }; +}; + +&wmac { + ralink,5ghz = <0>; +}; diff --git a/sys/gnu/dts/mips/TINY-AC.dts b/sys/gnu/dts/mips/TINY-AC.dts index ae4c4b5..cd62132 100644 --- a/sys/gnu/dts/mips/TINY-AC.dts +++ b/sys/gnu/dts/mips/TINY-AC.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "TINY-AC", "ralink,mt7620a-soc"; @@ -10,120 +10,6 @@ bootargs = "console=ttyS0,57600"; }; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "llllw"; - - port@4 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy4>; - }; - - port@5 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; - }; - - gsw@10110000 { - mediatek,port4 = "gmac"; - mediatek,mt7530 = <1>; - - }; - - wmac@10180000 { - ralink,eeprom = "rt2x00pci_1_0.eeprom"; - }; - - pcie@10140000 { - status = "okay"; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uartf", "nd_sd", "wled"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -164,3 +50,114 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; + mediatek,portmap = "llllw"; + + port@4 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy4>; + }; + + port@5 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + + mdio-bus { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii"; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + phy-mode = "rgmii"; + }; + }; +}; + +&gsw { + mediatek,port4 = "gmac"; + mediatek,mt7530 = <1>; +}; + +&wmac { + ralink,eeprom = "rt2x00pci_1_0.eeprom"; +}; + +&pcie { + status = "okay"; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "uartf", "nd_sd", "wled"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/UBNT-ERX.dts b/sys/gnu/dts/mips/UBNT-ERX.dts index ec31a37..713519d 100644 --- a/sys/gnu/dts/mips/UBNT-ERX.dts +++ b/sys/gnu/dts/mips/UBNT-ERX.dts @@ -17,30 +17,6 @@ bootargs = "console=ttyS0,57600"; }; - palmbus@1E000000 { - spi@b00 { - /* This board has 2Mb spi flash soldered in and visible - from manufacturer's firmware. - But this SoC shares spi and nand pins, - and current driver does't handle this sharing well */ - status = "disabled"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <1>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "spi"; - reg = <0x0 0x200000>; - read-only; - }; - }; - }; - }; - nand@1e003000 { status = "okay"; @@ -78,27 +54,6 @@ }; - ethernet@1e100000 { - mtd-mac-address = <&factory 0x22>; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag"; - ralink,function = "gpio"; - }; - }; - }; - - sdhci@1E130000 { - status = "disabled"; - }; - - pcie@1e140000 { - status = "disabled"; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -112,3 +67,46 @@ }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x22>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag"; + ralink,function = "gpio"; + }; + }; +}; + +&sdhci { + status = "disabled"; +}; + +&pcie { + status = "disabled"; +}; + +&spi0 { + /* This board has 2Mb spi flash soldered in and visible + from manufacturer's firmware. + But this SoC shares spi and nand pins, + and current driver does't handle this sharing well */ + status = "disabled"; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <1>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "spi"; + reg = <0x0 0x200000>; + read-only; + }; + }; +}; diff --git a/sys/gnu/dts/mips/UR-326N4G.dts b/sys/gnu/dts/mips/UR-326N4G.dts index b95eaf0..d90d77c 100644 --- a/sys/gnu/dts/mips/UR-326N4G.dts +++ b/sys/gnu/dts/mips/UR-326N4G.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "UR-326N4G", "ralink,rt3052-soc"; model = "UPVEL UR-326N4G"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4004>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -106,8 +85,29 @@ linux,code = <0x32>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4004>; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/UR-336UN.dts b/sys/gnu/dts/mips/UR-336UN.dts index 5feaba3..e0325a7 100644 --- a/sys/gnu/dts/mips/UR-336UN.dts +++ b/sys/gnu/dts/mips/UR-336UN.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "UR-336UN", "ralink,rt3052-soc"; model = "UPVEL UR-336UN"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -24,20 +15,6 @@ #size-cells = <1>; }; - /* FIXME: no partitions defined */ -/* ethernet@10100000 { - mtd-mac-address = <&factory 0x4004>; - }; -*/ - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - /* FIXME: no partitions defined */ -/* wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; -*/ gpio-leds { compatible = "gpio-leds"; @@ -85,8 +62,31 @@ linux,code = <0x32>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +/* FIXME: no partitions defined */ +/*ðernet { + mtd-mac-address = <&factory 0x4004>; +}; +*/ +&esw { + mediatek,portmap = <0x2f>; +}; + +/* FIXME: no partitions defined */ +/*&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; +*/ +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/V11STFE.dts b/sys/gnu/dts/mips/V11STFE.dts index 5a43e6d..6f7a5cb 100644 --- a/sys/gnu/dts/mips/V11STFE.dts +++ b/sys/gnu/dts/mips/V11STFE.dts @@ -1,26 +1,12 @@ /dts-v1/; -/include/ "rt2880.dtsi" +#include "rt2880.dtsi" / { compatible = "V11ST-FE", "ralink,rt2880-soc"; model = "Ralink V11ST-FE"; - palmbus@300000 { - gpio0: gpio@600 { - status = "okay"; - }; - }; - - ethernet@400000 { - status = "okay"; - }; - - wmac@480000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pci@10140000 { + pci@440000 { status = "okay"; host-bridge { @@ -83,3 +69,15 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +ðernet { + status = "okay"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/V22RW-2X2.dts b/sys/gnu/dts/mips/V22RW-2X2.dts index 98e8da0..602e170 100644 --- a/sys/gnu/dts/mips/V22RW-2X2.dts +++ b/sys/gnu/dts/mips/V22RW-2X2.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "V22RW-2X2", "ralink,rt3052-soc"; model = "Ralink AP-RT3052-V22RW-2X2"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,14 +38,6 @@ }; }; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -87,8 +70,25 @@ linux,code = <0x211>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/VOCORE-16M.dts b/sys/gnu/dts/mips/VOCORE-16M.dts index 680b486..11ebac7 100644 --- a/sys/gnu/dts/mips/VOCORE-16M.dts +++ b/sys/gnu/dts/mips/VOCORE-16M.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "VOCORE.dtsi" +#include "VOCORE.dtsi" &spi0 { status = "okay"; @@ -9,7 +9,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - reg = <0>; + reg = <0 0>; linux,modalias = "m25p80", "w25q128"; spi-max-frequency = <10000000>; diff --git a/sys/gnu/dts/mips/VOCORE-8M.dts b/sys/gnu/dts/mips/VOCORE-8M.dts index e8f9c2c..ea7185b 100644 --- a/sys/gnu/dts/mips/VOCORE-8M.dts +++ b/sys/gnu/dts/mips/VOCORE-8M.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "VOCORE.dtsi" +#include "VOCORE.dtsi" &spi0 { status = "okay"; @@ -9,7 +9,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - reg = <0>; + reg = <0 0>; linux,modalias = "m25p80", "s25fl064k"; spi-max-frequency = <10000000>; diff --git a/sys/gnu/dts/mips/VOCORE.dtsi b/sys/gnu/dts/mips/VOCORE.dtsi index ab1c53e..93e601c 100644 --- a/sys/gnu/dts/mips/VOCORE.dtsi +++ b/sys/gnu/dts/mips/VOCORE.dtsi @@ -1,48 +1,9 @@ -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "VoCore", "ralink,rt5350-soc"; model = "VoCore"; - palmbus@10000000 { - gpio1: gpio@660 { - status = "okay"; - }; - - i2c@900 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag", "uartf", "led"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x17>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-export { compatible = "gpio-export"; #size-cells = <0>; @@ -186,6 +147,44 @@ }; }; +&gpio1 { + status = "okay"; +}; + +&i2c { + status = "okay"; +}; + +&pinctrl { + state_default { + gpio { + ralink,group = "jtag", "uartf", "led"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x11>; + mediatek,portdisable = <0x2e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + &spi1 { status = "okay"; diff --git a/sys/gnu/dts/mips/W150M.dts b/sys/gnu/dts/mips/W150M.dts index 4979089..679db60 100644 --- a/sys/gnu/dts/mips/W150M.dts +++ b/sys/gnu/dts/mips/W150M.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "W150M", "ralink,rt3050-soc"; model = "Tenda W150M"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -99,16 +90,25 @@ linux,code = <0x100>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; }; diff --git a/sys/gnu/dts/mips/W306R_V20.dts b/sys/gnu/dts/mips/W306R_V20.dts index c6ed940..79ae23d 100644 --- a/sys/gnu/dts/mips/W306R_V20.dts +++ b/sys/gnu/dts/mips/W306R_V20.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "W306R_V20", "ralink,rt3052-soc"; @@ -38,27 +38,6 @@ }; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -86,3 +65,24 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/W502U.dts b/sys/gnu/dts/mips/W502U.dts index 112a4bd..7398170 100644 --- a/sys/gnu/dts/mips/W502U.dts +++ b/sys/gnu/dts/mips/W502U.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "W502U", "ralink,rt3052-soc"; @@ -10,15 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -51,18 +42,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -95,8 +74,29 @@ linux,code = <0x211>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WCR150GN.dts b/sys/gnu/dts/mips/WCR150GN.dts index ed80b6f..541836b218 100644 --- a/sys/gnu/dts/mips/WCR150GN.dts +++ b/sys/gnu/dts/mips/WCR150GN.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WCR150GN", "ralink,rt3050-soc"; model = "Sparklan WCR-150GN"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -79,20 +70,29 @@ linux,code = <0x198>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&esw { + mediatek,portmap = <0x2f>; +}; - otg@101c0000 { - status = "okay"; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/WF-2881.dts b/sys/gnu/dts/mips/WF-2881.dts index d33436c..050bc2e 100644 --- a/sys/gnu/dts/mips/WF-2881.dts +++ b/sys/gnu/dts/mips/WF-2881.dts @@ -11,12 +11,6 @@ reg = <0x0 0x8000000>; }; - palmbus@1E000000 { - spi@b00 { - status="disabled"; - }; - }; - chosen { bootargs = "console=ttyS0,57600"; }; @@ -54,32 +48,6 @@ }; }; - pcie@1e140000 { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; - }; - - ethernet@1e100000 { - mtd-mac-address = <&factory 0xe006>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -106,13 +74,43 @@ linux,code = <0x198>; }; }; +}; + +&spi0 { + status="disabled"; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,5ghz = <0>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe006>; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uart3", "jtag"; - ralink,function = "gpio"; - }; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "uart3", "jtag"; + ralink,function = "gpio"; }; }; }; diff --git a/sys/gnu/dts/mips/WHR-1166D.dts b/sys/gnu/dts/mips/WHR-1166D.dts index d3e9b7a..f6a57ac 100644 --- a/sys/gnu/dts/mips/WHR-1166D.dts +++ b/sys/gnu/dts/mips/WHR-1166D.dts @@ -1,103 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-soc"; model = "Buffalo WHR-1166D"; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &mdio_pins>; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; - }; - - gsw@10110000 { - mediatek,port4 = "ephy"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pcie@10140000 { - status = "okay"; - - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 32768>; - mediatek,2ghz = <0>; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -170,3 +78,93 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "wled", "nd_sd"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &mdio_pins>; + + port@5 { + status = "okay"; + phy-handle = <&phy5>; + phy-mode = "rgmii"; + }; + + mdio-bus { + status = "okay"; + + phy5: ethernet-phy@5 { + reg = <5>; + phy-mode = "rgmii"; + }; + }; +}; + +&gsw { + mediatek,port4 = "ephy"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; + + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 32768>; + mediatek,2ghz = <0>; + }; + }; +}; diff --git a/sys/gnu/dts/mips/WHR-300HP2.dts b/sys/gnu/dts/mips/WHR-300HP2.dts index 638837d..88981bb 100644 --- a/sys/gnu/dts/mips/WHR-300HP2.dts +++ b/sys/gnu/dts/mips/WHR-300HP2.dts @@ -1,81 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-soc"; model = "Buffalo WHR-300HP2"; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - - pa { - ralink,group = "pa"; - ralink,function = "pa"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mediatek,portmap = "llllw"; - }; - - gsw@10110000 { - mediatek,port4 = "ephy"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -148,3 +78,71 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; + ralink,function = "gpio"; + }; + + pa { + ralink,group = "pa"; + ralink,function = "pa"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mediatek,portmap = "llllw"; +}; + +&gsw { + mediatek,port4 = "ephy"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/WHR-600D.dts b/sys/gnu/dts/mips/WHR-600D.dts index 3173342..67e9ba9 100644 --- a/sys/gnu/dts/mips/WHR-600D.dts +++ b/sys/gnu/dts/mips/WHR-600D.dts @@ -1,81 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-soc"; model = "Buffalo WHR-600D"; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l6405d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - - gsw@10110000 { - mediatek,port4 = "ephy"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pcie@10140000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -148,3 +78,71 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l6405d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&gsw { + mediatek,port4 = "ephy"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pcie { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WHR-G300N.dts b/sys/gnu/dts/mips/WHR-G300N.dts index e433e74..4f80f2d 100644 --- a/sys/gnu/dts/mips/WHR-G300N.dts +++ b/sys/gnu/dts/mips/WHR-G300N.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WHR-G300N", "ralink,rt3052-soc"; model = "Buffalo WHR-G300N"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -24,15 +15,6 @@ #size-cells = <1>; }; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - /* FIXME: no partitions defined */ -/* wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; -*/ gpio-leds { compatible = "gpio-leds"; @@ -83,3 +65,22 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +&esw { + mediatek,portmap = <0x2f>; +}; + +/* FIXME: no partitions defined */ +/*&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; +*/ diff --git a/sys/gnu/dts/mips/WITI.dts b/sys/gnu/dts/mips/WITI.dts index 78e2bc9..774483e 100644 --- a/sys/gnu/dts/mips/WITI.dts +++ b/sys/gnu/dts/mips/WITI.dts @@ -15,50 +15,7 @@ bootargs = "console=ttyS0,57600"; }; - sdhci@10130000 { - status = "okay"; - }; - - xhci@1E1C0000 { - status = "okay"; - }; - - palmbus@1E000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; - + palmbus: palmbus@1E000000 { i2c@900 { compatible = "ralink,i2c-mt7621"; reg = <0x900 0x100>; @@ -76,34 +33,6 @@ }; }; - pcie@1e140000 { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - mtd-mac-address = <&factory 0xe000>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - mtd-mac-address = <&factory 0xe000>; - }; - }; - }; - - ethernet@1e100000 { - mtd-mac-address = <&factory 0xe000>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -116,13 +45,85 @@ linux,code = <0x198>; }; }; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wdt", "rgmii2", "jtag", "mdio"; - ralink,function = "gpio"; - }; + +&sdhci { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + mtd-mac-address = <&factory 0xe000>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,5ghz = <0>; + mtd-mac-address = <&factory 0xe000>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe000>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "wdt", "rgmii2", "jtag", "mdio"; + ralink,function = "gpio"; }; }; }; diff --git a/sys/gnu/dts/mips/WIZARD8800.dts b/sys/gnu/dts/mips/WIZARD8800.dts index 7d8243c..819e93a 100644 --- a/sys/gnu/dts/mips/WIZARD8800.dts +++ b/sys/gnu/dts/mips/WIZARD8800.dts @@ -1,83 +1,81 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "WIZARD8800", "ralink,rt5350-soc"; model = "EASYACC WI-STOR WIZARD 8800"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; - palmbus@10000000 { - gpio1@638 { - status = "okay"; +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q32"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; }; - gpio2@660 { - status = "okay"; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; }; - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q32"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; }; - }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; +}; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - ehci@101c0000 { - status = "okay"; - }; +&esw { + mediatek,portmap = <0x2f>; +}; - ohci@101c1000 { - status = "okay"; - }; +&ehci { + status = "okay"; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&ohci { + status = "okay"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; }; diff --git a/sys/gnu/dts/mips/WIZFI630A.dts b/sys/gnu/dts/mips/WIZFI630A.dts index e2a51ec..68af608 100644 --- a/sys/gnu/dts/mips/WIZFI630A.dts +++ b/sys/gnu/dts/mips/WIZFI630A.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "wizfi630a", "ralink,rt5350-soc"; @@ -10,116 +10,6 @@ bootargs = "console=ttyS1,115200"; }; - palmbus@10000000 { - gpio1: gpio@660 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "uboot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; - - uart@500 { - compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0x500 0x100>; - resets = <&rstctrl 12>; - reset-names = "uart"; - interrupt-parent = <&intc>; - interrupts = <5>; - reg-shift = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uartf_pins>; - status = "okay"; - }; - - uartlite@c00 { - compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; - reg = <0xc00 0x100>; - resets = <&rstctrl 19>; - reset-names = "uartl"; - interrupt-parent = <&intc>; - interrupts = <12>; - reg-shift = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uartlite_pins>; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag" ; - ralink,function = "gpio"; - }; - }; - - uartf_gpio_pins: uartf_gpio { - uartf_gpio { - ralink,group = "uartf"; - ralink,function = "uartf"; - }; - }; - - uartlite_pins: uartlite { - uart { - ralink,group = "uartlite"; - ralink,function = "uartlite"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x17>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-export { compatible = "gpio-export"; #size-cells = <0>; @@ -180,3 +70,115 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + #size-cells = <1>; + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + #size-cells = <1>; + label = "uboot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + #size-cells = <1>; + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + #size-cells = <1>; + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&uart { + compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; + reg = <0x500 0x100>; + resets = <&rstctrl 12>; + reset-names = "uart"; + interrupt-parent = <&intc>; + interrupts = <5>; + reg-shift = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uartf_pins>; + status = "okay"; +}; + +&uartlite { + compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; + reg = <0xc00 0x100>; + resets = <&rstctrl 19>; + reset-names = "uartl"; + interrupt-parent = <&intc>; + interrupts = <12>; + reg-shift = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uartlite_pins>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag" ; + ralink,function = "gpio"; + }; + }; + + uartf_gpio_pins: uartf_gpio { + uartf_gpio { + ralink,group = "uartf"; + ralink,function = "uartf"; + }; + }; + + uartlite_pins: uartlite { + uart { + ralink,group = "uartlite"; + ralink,function = "uartlite"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x17>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WL-330N.dts b/sys/gnu/dts/mips/WL-330N.dts index 632d960..f497b24 100644 --- a/sys/gnu/dts/mips/WL-330N.dts +++ b/sys/gnu/dts/mips/WL-330N.dts @@ -1,70 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WL-330N", "ralink,rt3050-soc"; model = "Asus WL-330N"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -98,3 +39,60 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/WL-330N3G.dts b/sys/gnu/dts/mips/WL-330N3G.dts index 1e129ad..d79a757 100644 --- a/sys/gnu/dts/mips/WL-330N3G.dts +++ b/sys/gnu/dts/mips/WL-330N3G.dts @@ -1,70 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WL-330N3G", "ralink,rt3050-soc"; model = "Asus WL-330N3G"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -102,8 +43,65 @@ linux,code = <0x198>; }; }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WL-341V3.dts b/sys/gnu/dts/mips/WL-341V3.dts index debe55e..5f9e1dd 100644 --- a/sys/gnu/dts/mips/WL-341V3.dts +++ b/sys/gnu/dts/mips/WL-341V3.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WL-341V3", "ralink,rt3052-soc"; @@ -38,27 +38,6 @@ }; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&boardnvram 0xffa0>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&boardnvram 0xfd70>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -116,8 +95,29 @@ linux,code = <0x211>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&boardnvram 0xffa0>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&boardnvram 0xfd70>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WL-351.dts b/sys/gnu/dts/mips/WL-351.dts index 7f16631..ecda696 100644 --- a/sys/gnu/dts/mips/WL-351.dts +++ b/sys/gnu/dts/mips/WL-351.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WL-351", "ralink,rt3052-soc"; model = "Sitecom WL-351 v1 002"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,30 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x3f>; - ralink,fct2 = <0x0002500c>; - /* - * ext phy base addr 31, rx/tx clock skew 0, - * turbo mii off, rgmi 3.3v off, port 5 polling off - * port5: enabled, gige, full-duplex, rx/tx-flow-control - * port6: enabled, gige, full-duplex, rx/tx-flow-control - */ - ralink,fpa2 = <0x1f003fff>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - otg@101c0000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -115,3 +82,36 @@ gpio-sck = <&gpio0 2 0>; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x3f>; + ralink,fct2 = <0x0002500c>; + /* + * ext phy base addr 31, rx/tx clock skew 0, + * turbo mii off, rgmi 3.3v off, port 5 polling off + * port5: enabled, gige, full-duplex, rx/tx-flow-control + * port6: enabled, gige, full-duplex, rx/tx-flow-control + */ + ralink,fpa2 = <0x1f003fff>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WLI-TX4-AG300N.dts b/sys/gnu/dts/mips/WLI-TX4-AG300N.dts index 873feab..70521a7 100644 --- a/sys/gnu/dts/mips/WLI-TX4-AG300N.dts +++ b/sys/gnu/dts/mips/WLI-TX4-AG300N.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt2880.dtsi" +#include "rt2880.dtsi" / { #address-cells = <1>; @@ -8,12 +8,6 @@ compatible = "WLI-TX4-AG300N", "ralink,rt2880-soc"; model = "Buffalo WLI-TX4-AG300N"; - palmbus@300000 { - gpio0: gpio@600 { - status = "okay"; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -46,19 +40,6 @@ }; }; - ethernet@400000 { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; - }; - - wmac@480000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -103,3 +84,20 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x4>; + + port@0 { + mediatek,fixed-link = <1000 1 1 1>; + }; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/WMR-300.dts b/sys/gnu/dts/mips/WMR-300.dts index 7097687..9f9d5b7 100644 --- a/sys/gnu/dts/mips/WMR-300.dts +++ b/sys/gnu/dts/mips/WMR-300.dts @@ -1,71 +1,11 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "buffalo,wmr-300", "ralink,mt7620n-soc"; model = "Buffalo WMR-300"; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "ephy"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -104,3 +44,61 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "i2c", "ephy"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/WNCE2001.dts b/sys/gnu/dts/mips/WNCE2001.dts index da094dc..b68f3ba 100644 --- a/sys/gnu/dts/mips/WNCE2001.dts +++ b/sys/gnu/dts/mips/WNCE2001.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WNCE2001", "ralink,rt3052-soc"; @@ -10,78 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "mx25l3205d"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - factory: partition@30000 { - label = "factory"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@40000 { - label = "config"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "language"; - reg = <0x60000 0x30000>; - read-only; - }; - - partition@90000 { - label = "pot"; - reg = <0x90000 0x10000>; - read-only; - }; - - partition@a0000 { - label = "checksum"; - reg = <0xa0000 0x10000>; - }; - - partition@b0000 { - label = "firmware"; - reg = <0xb0000 0x350000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -137,3 +65,73 @@ }; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + factory: partition@30000 { + label = "factory"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "config"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "language"; + reg = <0x60000 0x30000>; + read-only; + }; + + partition@90000 { + label = "pot"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "checksum"; + reg = <0xa0000 0x10000>; + }; + + partition@b0000 { + label = "firmware"; + reg = <0xb0000 0x350000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/WNDR3700V5.dts b/sys/gnu/dts/mips/WNDR3700V5.dts new file mode 100644 index 0000000..8150754 --- /dev/null +++ b/sys/gnu/dts/mips/WNDR3700V5.dts @@ -0,0 +1,137 @@ +/dts-v1/; + +#include "mt7621.dtsi" + +/ { + compatible = "mediatek,mt7621-eval-board","ralink,mt7621-soc"; + model = "Netgear WNDR3700v5"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600 maxcpus=2"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + wps { + label = "wndr3700v5:green:wps"; + gpios = <&gpio0 12 1>; + }; + + power { + label = "wndr3700v5:green:power"; + gpios = <&gpio0 18 1>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + wps { + label = "wndr3700v5:wps"; + gpios = <&gpio0 7 0>; + linux,code = <0x211>; + }; + + wifi { + label = "wndr3700v5:wifi"; + gpios = <&gpio0 8 0>; + linux,code = <0xf7>; + }; + + reset { + label = "wndr3700v5:reset"; + gpios = <&gpio0 14 0>; + linux,code = <0x198>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + usbpower { + gpio-export,name = "usbpower"; + gpio-export,output = <1>; + gpios = <&gpio0 10 1>; + }; + }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mx25l12805d"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@f30000 { + label = "factory"; + reg = <0xf30000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0004>; + mediatek,2ghz = <0>; + }; + }; + + pcie2 { + mt76@2,0 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8004>; + mediatek,5ghz = <0>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x0000000c>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "rgmii2", "mdio", "wdt"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/WR512-3GN-4M.dts b/sys/gnu/dts/mips/WR512-3GN-4M.dts index 531a370..45e1463 100644 --- a/sys/gnu/dts/mips/WR512-3GN-4M.dts +++ b/sys/gnu/dts/mips/WR512-3GN-4M.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WR512-3GN", "ralink,rt3052-soc"; model = "WR512-3GN-like router"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,14 +38,6 @@ }; }; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -102,8 +85,25 @@ linux,code = <0x32>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WR512-3GN-8M.dts b/sys/gnu/dts/mips/WR512-3GN-8M.dts index 5f369f8..7e9a0c2 100644 --- a/sys/gnu/dts/mips/WR512-3GN-8M.dts +++ b/sys/gnu/dts/mips/WR512-3GN-8M.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WR512-3GN", "ralink,rt3052-soc"; model = "WR512-3GN-like router"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,14 +38,6 @@ }; }; - esw@10110000 { - mediatek,portmap = <0x2f>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -102,8 +85,25 @@ linux,code = <0x32>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +&esw { + mediatek,portmap = <0x2f>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WR6202.dts b/sys/gnu/dts/mips/WR6202.dts index 0c80514..534d78d 100644 --- a/sys/gnu/dts/mips/WR6202.dts +++ b/sys/gnu/dts/mips/WR6202.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "WR6202", "ralink,rt3052-soc"; @@ -10,15 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -84,22 +75,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - otg@101c0000 { - status = "okay"; - }; - gpio_export { compatible = "gpio-export"; #size-cells = <0>; @@ -111,3 +86,28 @@ }; }; }; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WRH-300CR.dts b/sys/gnu/dts/mips/WRH-300CR.dts new file mode 100644 index 0000000..d361193 --- /dev/null +++ b/sys/gnu/dts/mips/WRH-300CR.dts @@ -0,0 +1,125 @@ +/dts-v1/; + +#include "mt7620n.dtsi" + +/ { + compatible = "elecom,wrh-300cr", "ralink,mt7620n-soc"; + model = "ELECOM WRH-300CR"; + + gpio-leds { + compatible = "gpio-leds"; + + wps { + label = "wrh-300cr:green:wps"; + gpios = <&gpio2 0 1>; + }; + + ethernet { + label = "wrh-300cr:green:ethernet"; + gpios = <&gpio2 3 1>; + }; + + wlan { + label = "wrh-300cr:green:wlan"; + gpios = <&gpio3 0 1>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 1 1>; + linux,code = <0x198>; + }; + + wps { + label = "wps"; + gpios = <&gpio0 2 1>; + linux,code = <0x211>; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l12805d"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "recover"; + reg = <0x50000 0x1c0000>; + read-only; + }; + + partition@210000 { + label = "firmware"; + reg = <0x210000 0xdf0000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x2e>; + mediatek,portmap = "llllw"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "i2c", "ephy", "wled"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/WRTNODE.dts b/sys/gnu/dts/mips/WRTNODE.dts index d5ff18e..f782f191 100644 --- a/sys/gnu/dts/mips/WRTNODE.dts +++ b/sys/gnu/dts/mips/WRTNODE.dts @@ -1,93 +1,91 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "wrtnode", "ralink,mt7620n-soc"; model = "WRTNODE"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; + gpio-leds { + compatible = "gpio-leds"; - gpio2: gpio@660 { - status = "okay"; + indicator { + label = "wrtnode:blue:indicator"; + gpios = <&gpio1 14 1>; }; + }; +}; - gpio3: gpio@688 { - status = "okay"; +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; }; - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; }; - }; - ehci@101c0000 { - status = "okay"; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - ohci@101c1000 { - status = "okay"; + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; +&ehci { + status = "okay"; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&ohci { + status = "okay"; +}; - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf", "spi refclk"; - ralink,function = "gpio"; - }; - }; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; - gpio-leds { - compatible = "gpio-leds"; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; - indicator { - label = "wrtnode:blue:indicator"; - gpios = <&gpio1 14 1>; +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf", "spi refclk"; + ralink,function = "gpio"; }; }; }; diff --git a/sys/gnu/dts/mips/WRTNODE2.dtsi b/sys/gnu/dts/mips/WRTNODE2.dtsi index d9aaba8..73aa5d1 100644 --- a/sys/gnu/dts/mips/WRTNODE2.dtsi +++ b/sys/gnu/dts/mips/WRTNODE2.dtsi @@ -1,93 +1,90 @@ -/include/ "mt7628an.dtsi" +#include "mt7628an.dtsi" / { chosen { bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - spi-max-frequency = <10000000>; - m25p,chunked-io = <32>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; - - - spidev@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spidev"; - reg = <1 0>; - linux,modalias = "spidev", "spidev"; - spi-max-frequency = <10000000>; - }; + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 5 1>; + linux,code = <0x198>; }; + }; +}; - uart1@d00 { - status = "okay"; +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + spi-max-frequency = <10000000>; + m25p,chunked-io = <32>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; }; - i2c@900 { - status = "okay"; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; }; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - ralink,port-map = "llllw"; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; }; - sdhci@10130000 { - status = "okay"; + spidev@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spidev"; + reg = <1 0>; + linux,modalias = "spidev", "spidev"; + spi-max-frequency = <10000000>; }; +}; - pcie@10140000 { - status = "okay"; - }; +&uart1 { + status = "okay"; +}; +&i2c { + status = "okay"; +}; - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; +ðernet { + mtd-mac-address = <&factory 0x4>; + ralink,port-map = "llllw"; +}; - reset { - label = "reset"; - gpios = <&gpio0 5 1>; - linux,code = <0x198>; - }; - }; +&sdhci { + status = "okay"; +}; +&pcie { + status = "okay"; }; +&wmac { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/WRTNODE2P.dts b/sys/gnu/dts/mips/WRTNODE2P.dts index 153fab2..94c21a4 100644 --- a/sys/gnu/dts/mips/WRTNODE2P.dts +++ b/sys/gnu/dts/mips/WRTNODE2P.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "WRTNODE2.dtsi" +#include "WRTNODE2.dtsi" / { compatible = "mediatek,wrtnode2p", "mediatek,mt7628an-soc"; model = "WRTnode2P"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "gpio", "jtag"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -25,3 +16,11 @@ }; }; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "gpio", "jtag"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/WRTNODE2R.dts b/sys/gnu/dts/mips/WRTNODE2R.dts index e915915..1c25770 100644 --- a/sys/gnu/dts/mips/WRTNODE2R.dts +++ b/sys/gnu/dts/mips/WRTNODE2R.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "WRTNODE2.dtsi" +#include "WRTNODE2.dtsi" / { compatible = "mediatek,wrtnode2r", "mediatek,mt7628an-soc"; model = "WRTnode2R"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "gpio", "wled_an"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -25,3 +16,11 @@ }; }; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "gpio", "wled_an"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/WSR-1166.dts b/sys/gnu/dts/mips/WSR-1166.dts index 9743cee..936edb3 100644 --- a/sys/gnu/dts/mips/WSR-1166.dts +++ b/sys/gnu/dts/mips/WSR-1166.dts @@ -15,58 +15,6 @@ bootargs = "console=ttyS0,57600"; }; - palmbus@1E000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xf90000>; - }; - - partition@fe0000 { - label = "board_data"; - reg = <0xfe0000 0x20000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -161,26 +109,76 @@ compatible = "gpio-poweroff"; gpios = <&gpio0 0 1>; }; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xf90000>; + }; + + partition@fe0000 { + label = "board_data"; + reg = <0xfe0000 0x20000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; + ralink,function = "gpio"; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; - pcie@1e140000 { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,5ghz = <0>; }; }; }; diff --git a/sys/gnu/dts/mips/WSR-600.dts b/sys/gnu/dts/mips/WSR-600.dts index 949572c..56988e4 100644 --- a/sys/gnu/dts/mips/WSR-600.dts +++ b/sys/gnu/dts/mips/WSR-600.dts @@ -15,53 +15,6 @@ bootargs = "console=ttyS0,57600"; }; - palmbus@1E000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -157,3 +110,48 @@ gpios = <&gpio1 11 1>; }; }; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/WT1520-4M.dts b/sys/gnu/dts/mips/WT1520-4M.dts index 9cdff67..b3cff48 100644 --- a/sys/gnu/dts/mips/WT1520-4M.dts +++ b/sys/gnu/dts/mips/WT1520-4M.dts @@ -1,43 +1,39 @@ /dts-v1/; -/include/ "WT1520.dtsi" +#include "WT1520.dtsi" -/ { - palmbus@10000000 { - spi@b00 { - status = "okay"; +&spi0 { + status = "okay"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; }; }; }; diff --git a/sys/gnu/dts/mips/WT1520-8M.dts b/sys/gnu/dts/mips/WT1520-8M.dts index e9549ce..8abd9c7 100644 --- a/sys/gnu/dts/mips/WT1520-8M.dts +++ b/sys/gnu/dts/mips/WT1520-8M.dts @@ -1,43 +1,39 @@ /dts-v1/; -/include/ "WT1520.dtsi" +#include "WT1520.dtsi" -/ { - palmbus@10000000 { - spi@b00 { - status = "okay"; +&spi0 { + status = "okay"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "s25fl064k"; - spi-max-frequency = <10000000>; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "s25fl064k"; + spi-max-frequency = <10000000>; - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; }; }; }; diff --git a/sys/gnu/dts/mips/WT1520.dtsi b/sys/gnu/dts/mips/WT1520.dtsi index 13ff268..e7158ad 100644 --- a/sys/gnu/dts/mips/WT1520.dtsi +++ b/sys/gnu/dts/mips/WT1520.dtsi @@ -1,4 +1,4 @@ -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "NEXXWT1520", "ralink,rt5350-soc"; @@ -12,37 +12,35 @@ chosen { bootargs = "console=ttyS1,57600"; }; +}; - palmbus@10000000 { - uart@500 { - pinctrl-names = "default"; - pinctrl-0 = <&uartf_pins>; - status = "okay"; - }; - }; +&uart { + pinctrl-names = "default"; + pinctrl-0 = <&uartf_pins>; + status = "okay"; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "jtag"; - ralink,function = "gpio"; - }; +&pinctrl { + state_default { + gpio { + ralink,group = "jtag"; + ralink,function = "gpio"; }; }; +}; - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; +ðernet { + mtd-mac-address = <&factory 0x4>; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; - ehci@101c0000 { - status = "okay"; - }; +&ehci { + status = "okay"; +}; - ohci@101c1000 { - status = "okay"; - }; +&ohci { + status = "okay"; }; diff --git a/sys/gnu/dts/mips/WT3020-4M.dts b/sys/gnu/dts/mips/WT3020-4M.dts index 39b52c3..32411210 100644 --- a/sys/gnu/dts/mips/WT3020-4M.dts +++ b/sys/gnu/dts/mips/WT3020-4M.dts @@ -1,83 +1,11 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "wt3020", "ralink,mt7620n-soc"; model = "Nexx WT3020"; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q32"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x3b0000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -100,3 +28,73 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q32"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x3b0000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/WT3020-8M.dts b/sys/gnu/dts/mips/WT3020-8M.dts index 3a24651..e7abb8e 100644 --- a/sys/gnu/dts/mips/WT3020-8M.dts +++ b/sys/gnu/dts/mips/WT3020-8M.dts @@ -1,83 +1,11 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "wt3020", "ralink,mt7620n-soc"; model = "Nexx WT3020"; - palmbus@10000000 { - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -100,3 +28,73 @@ }; }; }; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/WZR-AGL300NH.dts b/sys/gnu/dts/mips/WZR-AGL300NH.dts index 02989be..23fba7c 100644 --- a/sys/gnu/dts/mips/WZR-AGL300NH.dts +++ b/sys/gnu/dts/mips/WZR-AGL300NH.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "rt2880.dtsi" +#include "rt2880.dtsi" / { #address-cells = <1>; @@ -8,19 +8,12 @@ compatible = "WZR-AGL300NH", "ralink,rt2880-soc"; model = "Buffalo WZR-AGL300NH"; - palmbus@300000 { - gpio0: gpio@600 { - status = "okay"; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartlite", "mdio"; - ralink,function = "gpio"; - }; - }; + pci@440000 { + compatible = "ralink,rt288x-pci"; + reg = <0x00440000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + status = "ok"; }; cfi@1f000000 { @@ -55,34 +48,12 @@ }; }; - ethernet@400000 { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - - port@0 { - mediatek,fixed-link = <1000 1 1 1>; - }; - - mdio-bus { - status = "okay"; - - phy0: ethernet-phy@0 { - phy-mode = "mii"; - reg = <0>; - }; - }; - }; - rtl8366s { compatible = "realtek,rtl8366s"; gpio-sda = <&gpio0 1 0>; gpio-sck = <&gpio0 2 0>; }; - wmac@480000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -131,13 +102,39 @@ gpios = <&gpio0 13 1>; }; }; +}; +&gpio0 { + status = "okay"; +}; - pcibus0: pci@00440000 { - compatible = "ralink,rt288x-pci"; - reg = <0x00440000 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - status = "ok"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartlite", "mdio"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x4>; + + port@0 { + mediatek,fixed-link = <1000 1 1 1>; + }; + + mdio-bus { + status = "okay"; + + phy0: ethernet-phy@0 { + phy-mode = "mii"; + reg = <0>; + }; + }; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; diff --git a/sys/gnu/dts/mips/X5.dts b/sys/gnu/dts/mips/X5.dts index 4952c90..26d3cd7 100644 --- a/sys/gnu/dts/mips/X5.dts +++ b/sys/gnu/dts/mips/X5.dts @@ -1,67 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "X5", "ralink,rt5350-soc"; model = "Poray X5"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "gd25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -122,17 +66,71 @@ gpios = <&gpio0 18 0>; }; }; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; - }; +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "gd25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - ehci@101c0000 { - status = "okay"; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; }; +}; - ohci@101c1000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <1>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; + ralink,led-polarity = <1>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/X8.dts b/sys/gnu/dts/mips/X8.dts index ad7f808..1c8b37a 100644 --- a/sys/gnu/dts/mips/X8.dts +++ b/sys/gnu/dts/mips/X8.dts @@ -1,67 +1,11 @@ /dts-v1/; -/include/ "rt5350.dtsi" +#include "rt5350.dtsi" / { compatible = "X8", "ralink,rt5350-soc"; model = "Poray X8"; - palmbus@10000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "gd25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "jtag", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - }; - - esw@10110000 { - mediatek,portmap = <0x2f>; - mediatek,led_polarity = <1>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -83,17 +27,71 @@ linux,code = <0x198>; }; }; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - ralink,led-polarity = <1>; - }; +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "gd25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; - ehci@101c0000 { - status = "okay"; + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; }; +}; - ohci@101c1000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "jtag", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x4>; +}; + +&esw { + mediatek,portmap = <0x2f>; + mediatek,led_polarity = <1>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; + ralink,led-polarity = <1>; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/XDXRN502J.dts b/sys/gnu/dts/mips/XDXRN502J.dts index 97940dd..34a29cc 100644 --- a/sys/gnu/dts/mips/XDXRN502J.dts +++ b/sys/gnu/dts/mips/XDXRN502J.dts @@ -1,20 +1,11 @@ /dts-v1/; -/include/ "rt3050.dtsi" +#include "rt3050.dtsi" / { compatible = "XDXRN502J", "ralink,rt3052-soc"; model = "XDX RN502J"; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; - ralink,function = "gpio"; - }; - }; - }; - cfi@1f000000 { compatible = "cfi-flash"; reg = <0x1f000000 0x800000>; @@ -47,18 +38,6 @@ }; }; - ethernet@10100000 { - mtd-mac-address = <&factory 0x28>; - }; - - esw@10110000 { - mediatek,portmap = <0x3e>; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - gpio-leds { compatible = "gpio-leds"; @@ -85,8 +64,29 @@ linux,code = <0x198>; }; }; +}; - otg@101c0000 { - status = "okay"; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf"; + ralink,function = "gpio"; + }; }; }; + +ðernet { + mtd-mac-address = <&factory 0x28>; +}; + +&esw { + mediatek,portmap = <0x3e>; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&otg { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/Y1.dts b/sys/gnu/dts/mips/Y1.dts index 9022795..ac9b7d5 100644 --- a/sys/gnu/dts/mips/Y1.dts +++ b/sys/gnu/dts/mips/Y1.dts @@ -1,18 +1,11 @@ /dts-v1/; -/include/ "Y1.dtsi" +#include "Y1.dtsi" / { compatible = "lenovo,Y1", "ralink,mt7620a-soc"; model = "Lenovo Y1"; - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -47,3 +40,10 @@ }; }; }; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; diff --git a/sys/gnu/dts/mips/Y1.dtsi b/sys/gnu/dts/mips/Y1.dtsi index 18652f1..25086b0 100644 --- a/sys/gnu/dts/mips/Y1.dtsi +++ b/sys/gnu/dts/mips/Y1.dtsi @@ -1,109 +1,107 @@ -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { chosen { bootargs = "console=ttyS0,115200"; }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 11 1>; + linux,code = <0x198>; + }; + }; +}; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; +&gpio0 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q128"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; }; - gpio2: gpio@660 { - status = "okay"; + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; }; - gpio3: gpio@688 { - status = "okay"; + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; }; - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q128"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; }; }; +}; - ehci@101c0000 { - status = "okay"; - }; +&ehci { + status = "okay"; +}; - ohci@101c1000 { - status = "okay"; - }; +&ohci { + status = "okay"; +}; - pcie@10140000 { - status = "okay"; +&pcie { + status = "okay"; - pcie-bridge { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; + pcie-bridge { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; }; }; +}; - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "uartf", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - - pa { - ralink,group = "pa"; - ralink,function = "pa"; - }; +&pinctrl { + state_default { + gpio { + ralink,group = "uartf", "wled", "nd_sd"; + ralink,function = "gpio"; }; - }; - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio0 11 1>; - linux,code = <0x198>; + pa { + ralink,group = "pa"; + ralink,function = "pa"; }; }; }; diff --git a/sys/gnu/dts/mips/Y1S.dts b/sys/gnu/dts/mips/Y1S.dts index d7f4615..cfa5e21 100644 --- a/sys/gnu/dts/mips/Y1S.dts +++ b/sys/gnu/dts/mips/Y1S.dts @@ -1,45 +1,11 @@ /dts-v1/; -/include/ "Y1.dtsi" +#include "Y1.dtsi" / { compatible = "lenovo,Y1S", "ralink,mt7620a-soc"; model = "Lenovo Y1S"; - ethernet@10100000 { - status = "okay"; - mtd-mac-address = <&factory 0x4>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; - mediatek,portmap = "wllll"; - - port@4 { - status = "okay"; - phy-handle = <&phy4>; - phy-mode = "rgmii"; - }; - - port@5 { - status = "okay"; - phy-handle = <&phy5>; - phy-mode = "rgmii"; - }; - - mdio-bus { - status = "okay"; - - phy4: ethernet-phy@4 { - reg = <4>; - phy-mode = "rgmii"; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - phy-mode = "rgmii"; - }; - }; - }; - gpio_export { compatible = "gpio-export"; #size-cells = <0>; @@ -61,10 +27,6 @@ }; }; - gsw@10110000 { - mediatek,port4 = "gmac"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -104,3 +66,41 @@ }; }; }; + +ðernet { + status = "okay"; + mtd-mac-address = <&factory 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; + mediatek,portmap = "wllll"; + + port@4 { + status = "okay"; + phy-handle = <&phy4>; + phy-mode = "rgmii"; + }; + + port@5 { + status = "okay"; + phy-handle = <&phy5>; + phy-mode = "rgmii"; + }; + + mdio-bus { + status = "okay"; + + phy4: ethernet-phy@4 { + reg = <4>; + phy-mode = "rgmii"; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + phy-mode = "rgmii"; + }; + }; +}; + +&gsw { + mediatek,port4 = "gmac"; +}; diff --git a/sys/gnu/dts/mips/YOUKU-YK1.dts b/sys/gnu/dts/mips/YOUKU-YK1.dts index 47847d0..dc9622f 100644 --- a/sys/gnu/dts/mips/YOUKU-YK1.dts +++ b/sys/gnu/dts/mips/YOUKU-YK1.dts @@ -1,98 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "YOUKU-YK1", "ralink,mt7620a-soc"; model = "YOUKU YK1"; - palmbus@10000000 { - - gpio0: gpio@600 { - status = "okay"; - }; - - gpio1: gpio@638 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "w25q256"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x1fb0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - sdhci@b0130000 { - status = "okay"; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; wan { @@ -125,3 +38,87 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "w25q256"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x1fb0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&sdhci { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/ZBT-WA05.dts b/sys/gnu/dts/mips/ZBT-WA05.dts index f7fca60..bdf301f 100644 --- a/sys/gnu/dts/mips/ZBT-WA05.dts +++ b/sys/gnu/dts/mips/ZBT-WA05.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "zbtlink,zbt-wa05", "ralink,mt7620n-soc"; @@ -10,82 +10,6 @@ bootargs = "console=ttyS0,115200"; }; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - - gpio2: gpio@660 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - en25q64@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x760000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "spi refclk", "wled"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -118,3 +42,77 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + en25q64@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x760000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "i2c", "spi refclk", "wled"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/ZBT-WE826.dts b/sys/gnu/dts/mips/ZBT-WE826.dts index 22bef99..1e3af89 100644 --- a/sys/gnu/dts/mips/ZBT-WE826.dts +++ b/sys/gnu/dts/mips/ZBT-WE826.dts @@ -1,124 +1,122 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { - compatible = "zbtlink,zbt-we826", "ralink,mt7620a-soc"; - model = "ZBT-WE826"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio1: gpio@638 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - en25q128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q128"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - }; - }; - }; - - sdhci@10130000 { - status = "okay"; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - ralink,port-map = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - default { - ralink,group = "i2c", "uartf", "wled", "spi refclk", "pa"; - ralink,function = "gpio"; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power { - label = "zbt-we826:green:power"; - gpios = <&gpio1 14 0>; - }; - usb { - label = "zbt-we826:green:usb"; - gpios = <&gpio1 15 0>; - }; - air { - label = "zbt-we826:green:wifi"; - gpios = <&gpio3 0 1>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - reset { - label = "reset"; - gpios = <&gpio0 1 1>; - linux,code = <0x198>; - }; - }; - - pcie@10140000 { - status = "okay"; - }; -};
\ No newline at end of file + compatible = "zbtlink,zbt-we826", "ralink,mt7620a-soc"; + model = "ZBT-WE826"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "zbt-we826:green:power"; + gpios = <&gpio1 14 0>; + }; + usb { + label = "zbt-we826:green:usb"; + gpios = <&gpio1 15 0>; + }; + air { + label = "zbt-we826:green:wifi"; + gpios = <&gpio3 0 1>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + reset { + label = "reset"; + gpios = <&gpio0 1 1>; + linux,code = <0x198>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + en25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q128"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + ralink,port-map = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + default { + ralink,group = "i2c", "uartf", "wled", "spi refclk", "pa"; + ralink,function = "gpio"; + }; + }; +}; + +&pcie { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/ZBT-WG2626.dts b/sys/gnu/dts/mips/ZBT-WG2626.dts index b18f4c1..239ccd2 100644 --- a/sys/gnu/dts/mips/ZBT-WG2626.dts +++ b/sys/gnu/dts/mips/ZBT-WG2626.dts @@ -15,48 +15,7 @@ bootargs = "console=ttyS0,115200"; }; - sdhci@10130000 { - status = "okay"; - }; - - palmbus@1E000000 { - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0xfb0000>; - }; - - }; - }; - + palmbus: palmbus@1E000000 { i2c@900 { compatible = "ralink,i2c-mt7621"; reg = <0x900 0x100>; @@ -68,32 +27,6 @@ }; }; - pcie@1e140000 { - status = "okay"; - - pcie0 { - mt76@0,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x8000>; - mediatek,2ghz = <0>; - }; - }; - - pcie1 { - mt76@1,0 { - reg = <0x0000 0 0 0 0>; - device_type = "pci"; - mediatek,mtd-eeprom = <&factory 0x0000>; - mediatek,5ghz = <0>; - }; - }; - }; - - ethernet@1e100000 { - mtd-mac-address = <&factory 0xe000>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -115,13 +48,79 @@ gpios = <&gpio0 24 1>; }; }; +}; + +&sdhci { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,5ghz = <0>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe000>; +}; - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "wdt", "rgmii2", "wdt rst", "jtag", "mdio"; - ralink,function = "gpio"; - }; +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "wdt", "rgmii2", "wdt rst", "jtag", "mdio"; + ralink,function = "gpio"; }; }; }; diff --git a/sys/gnu/dts/mips/ZBT-WG3526.dts b/sys/gnu/dts/mips/ZBT-WG3526.dts new file mode 100644 index 0000000..064eb1c --- /dev/null +++ b/sys/gnu/dts/mips/ZBT-WG3526.dts @@ -0,0 +1,126 @@ +/dts-v1/; + +#include "mt7621.dtsi" + +/ { + compatible = "mediatek,mt7621-eval-board", "mediatek,mt7621-soc"; + model = "ZBT-WG3526"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x1c000000>, <0x20000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + palmbus: palmbus@1E000000 { + i2c@900 { + compatible = "ralink,i2c-mt7621"; + reg = <0x900 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 18 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + status { + label = "zbt-wg3526:green:status"; + gpios = <&gpio0 24 1>; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; +}; + +&pcie { + status = "okay"; + + pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x0000>; + mediatek,5ghz = <0>; + }; + }; + + pcie1 { + mt76@1,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + mediatek,mtd-eeprom = <&factory 0x8000>; + mediatek,2ghz = <0>; + }; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe000>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "wdt", "rgmii2", "wdt rst", "jtag", "mdio"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/ZBT-WR8305RT.dts b/sys/gnu/dts/mips/ZBT-WR8305RT.dts index 11efc6f..4f226d9 100644 --- a/sys/gnu/dts/mips/ZBT-WR8305RT.dts +++ b/sys/gnu/dts/mips/ZBT-WR8305RT.dts @@ -1,88 +1,11 @@ /dts-v1/; -/include/ "mt7620n.dtsi" +#include "mt7620n.dtsi" / { compatible = "zbtlink,zbt-wr8305rt", "ralink,mt7620n-soc"; model = "Zbtlink ZBT-WR8305RT"; - palmbus@10000000 { - gpio1: gpio@638 { - status = "okay"; - }; - - gpio3: gpio@688 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - - ethernet@10100000 { - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "llllw"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - pinctrl { - state_default: pinctrl0 { - ephy { - ralink,group = "ephy"; - ralink,function = "ephy"; - }; - - default { - ralink,group = "i2c", "uartf", "spi refclk", "wled"; - ralink,function = "gpio"; - }; - }; - }; - gpio-leds { compatible = "gpio-leds"; @@ -115,3 +38,78 @@ }; }; }; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +ðernet { + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "llllw"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&pinctrl { + state_default: pinctrl0 { + ephy { + ralink,group = "ephy"; + ralink,function = "ephy"; + }; + + default { + ralink,group = "i2c", "uartf", "spi refclk", "wled"; + ralink,function = "gpio"; + }; + }; +}; diff --git a/sys/gnu/dts/mips/ZTE-Q7.dts b/sys/gnu/dts/mips/ZTE-Q7.dts index dd278aa..e90c21e 100644 --- a/sys/gnu/dts/mips/ZTE-Q7.dts +++ b/sys/gnu/dts/mips/ZTE-Q7.dts @@ -1,89 +1,11 @@ /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ZTE-Q7", "ralink,mt7620a-soc"; model = "ZTE Q7"; - palmbus@10000000 { - gpio0: gpio@600 { - status = "okay"; - }; - - gpio1: gpio@638 { - status = "okay"; - }; - - spi@b00 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0 0>; - linux,modalias = "m25p80", "en25q64"; - spi-max-frequency = <10000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "u-boot-env"; - reg = <0x30000 0x10000>; - read-only; - }; - - factory: partition@40000 { - label = "factory"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7b0000>; - }; - }; - }; - }; - - pinctrl { - state_default: pinctrl0 { - gpio { - ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; - ralink,function = "gpio"; - }; - }; - }; - - ethernet@10100000 { - pinctrl-names = "default"; - pinctrl-0 = <&ephy_pins>; - mtd-mac-address = <&factory 0x4>; - mediatek,portmap = "wllll"; - }; - - wmac@10180000 { - ralink,mtd-eeprom = <&factory 0>; - }; - - sdhci@10130000 { - status = "okay"; - }; - - ehci@101c0000 { - status = "okay"; - }; - - ohci@101c1000 { - status = "okay"; - }; - gpio-leds { compatible = "gpio-leds"; @@ -111,3 +33,79 @@ }; }; }; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0 0>; + linux,modalias = "m25p80", "en25q64"; + spi-max-frequency = <10000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + label = "firmware"; + reg = <0x50000 0x7b0000>; + }; + }; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd"; + ralink,function = "gpio"; + }; + }; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <&ephy_pins>; + mtd-mac-address = <&factory 0x4>; + mediatek,portmap = "wllll"; +}; + +&wmac { + ralink,mtd-eeprom = <&factory 0>; +}; + +&sdhci { + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; diff --git a/sys/gnu/dts/mips/mt7620a.dtsi b/sys/gnu/dts/mips/mt7620a.dtsi index 6f0771c..a801dcb 100644 --- a/sys/gnu/dts/mips/mt7620a.dtsi +++ b/sys/gnu/dts/mips/mt7620a.dtsi @@ -23,9 +23,10 @@ aliases { spi0 = &spi0; spi1 = &spi1; + serial0 = &uartlite; }; - palmbus@10000000 { + palmbus: palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; ranges = <0x0 0x10000000 0x1FFFFF>; @@ -33,12 +34,12 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { + sysc: sysc@0 { compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc"; reg = <0x0 0x100>; }; - timer@100 { + timer: timer@100 { compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer"; reg = <0x100 0x20>; @@ -46,7 +47,7 @@ interrupts = <1>; }; - watchdog@120 { + watchdog: watchdog@120 { compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt"; reg = <0x120 0x10>; @@ -71,7 +72,7 @@ interrupts = <2>; }; - memc@300 { + memc: memc@300 { compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; reg = <0x300 0x100>; @@ -82,7 +83,7 @@ interrupts = <3>; }; - uart@500 { + uart: uart@500 { compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0x500 0x100>; @@ -174,7 +175,7 @@ status = "disabled"; }; - i2c@900 { + i2c: i2c@900 { compatible = "link,mt7620a-i2c", "ralink,rt2880-i2c"; reg = <0x900 0x100>; @@ -190,7 +191,7 @@ pinctrl-0 = <&i2c_pins>; }; - i2s@a00 { + i2s: i2s@a00 { compatible = "ralink,mt7620a-i2s"; reg = <0xa00 0x100>; @@ -239,7 +240,7 @@ pinctrl-0 = <&spi_cs1>; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; @@ -255,7 +256,7 @@ pinctrl-0 = <&uartlite_pins>; }; - systick@d00 { + systick: systick@d00 { compatible = "ralink,mt7620a-systick", "ralink,cevt-systick"; reg = <0xd00 0x10>; @@ -266,7 +267,7 @@ interrupts = <7>; }; - pcm@2000 { + pcm: pcm@2000 { compatible = "ralink,mt7620a-pcm"; reg = <0x2000 0x800>; @@ -297,7 +298,7 @@ }; }; - pinctrl { + pinctrl: pinctrl { compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -395,17 +396,25 @@ #reset-cells = <1>; }; + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + usbphy: usbphy { compatible = "mediatek,mt7620-usbphy"; #phy-cells = <1>; resets = <&rstctrl 22 &rstctrl 25>; reset-names = "host", "device"; + + clocks = <&clkctrl 22 &clkctrl 25>; + clock-names = "host", "device"; }; - ethernet@10100000 { + ethernet: ethernet@10100000 { compatible = "mediatek,mt7620-eth"; - reg = <0x10100000 10000>; + reg = <0x10100000 0x10000>; #address-cells = <1>; #size-cells = <0>; @@ -442,7 +451,7 @@ gsw: gsw@10110000 { compatible = "mediatek,mt7620-gsw"; - reg = <0x10110000 8000>; + reg = <0x10110000 0x8000>; resets = <&rstctrl 23>; reset-names = "esw"; @@ -451,9 +460,9 @@ interrupts = <17>; }; - sdhci@10130000 { + sdhci: sdhci@10130000 { compatible = "ralink,mt7620-sdhci"; - reg = <0x10130000 4000>; + reg = <0x10130000 0x4000>; interrupt-parent = <&intc>; interrupts = <14>; @@ -461,7 +470,7 @@ status = "disabled"; }; - ehci@101c0000 { + ehci: ehci@101c0000 { compatible = "generic-ehci"; reg = <0x101c0000 0x1000>; @@ -474,7 +483,7 @@ status = "disabled"; }; - ohci@101c1000 { + ohci: ohci@101c1000 { compatible = "generic-ohci"; reg = <0x101c1000 0x1000>; @@ -487,7 +496,7 @@ status = "disabled"; }; - pcie@10140000 { + pcie: pcie@10140000 { compatible = "mediatek,mt7620-pci"; reg = <0x10140000 0x100 0x10142000 0x100>; @@ -498,6 +507,9 @@ resets = <&rstctrl 26>; reset-names = "pcie0"; + clocks = <&clkctrl 26>; + clock-names = "pcie0"; + interrupt-parent = <&cpuintc>; interrupts = <4>; @@ -524,9 +536,9 @@ }; }; - wmac@10180000 { + wmac: wmac@10180000 { compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 40000>; + reg = <0x10180000 0x40000>; interrupt-parent = <&cpuintc>; interrupts = <6>; @@ -535,4 +547,4 @@ }; }; -/include/ "fbsd-mt7620a.dtsi" +#include "fbsd-mt7620a.dtsi" diff --git a/sys/gnu/dts/mips/mt7620n.dtsi b/sys/gnu/dts/mips/mt7620n.dtsi index 1321cb6..1df9544 100644 --- a/sys/gnu/dts/mips/mt7620n.dtsi +++ b/sys/gnu/dts/mips/mt7620n.dtsi @@ -23,9 +23,10 @@ aliases { spi0 = &spi0; spi1 = &spi1; + serial0 = &uartlite; }; - palmbus@10000000 { + palmbus: palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; ranges = <0x0 0x10000000 0x1FFFFF>; @@ -33,12 +34,12 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { + sysc: sysc@0 { compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc"; reg = <0x0 0x100>; }; - timer@100 { + timer: timer@100 { compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer"; reg = <0x100 0x20>; @@ -46,7 +47,7 @@ interrupts = <1>; }; - watchdog@120 { + watchdog: watchdog@120 { compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt"; reg = <0x120 0x10>; @@ -71,7 +72,7 @@ interrupts = <2>; }; - memc@300 { + memc: memc@300 { compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; reg = <0x300 0x100>; @@ -191,7 +192,7 @@ pinctrl-0 = <&spi_cs1>; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; @@ -207,7 +208,7 @@ pinctrl-0 = <&uartlite_pins>; }; - systick@d00 { + systick: systick@d00 { compatible = "ralink,mt7620a-systick", "ralink,cevt-systick"; reg = <0xd00 0x10>; @@ -219,7 +220,7 @@ }; }; - pinctrl { + pinctrl: pinctrl { compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -254,17 +255,25 @@ #reset-cells = <1>; }; + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + usbphy: usbphy { compatible = "mediatek,mt7620-usbphy"; #phy-cells = <1>; resets = <&rstctrl 22 &rstctrl 25>; reset-names = "host", "device"; + + clocks = <&clkctrl 22 &clkctrl 25>; + clock-names = "host", "device"; }; - ethernet@10100000 { + ethernet: ethernet@10100000 { compatible = "mediatek,mt7620-eth"; - reg = <0x10100000 10000>; + reg = <0x10100000 0x10000>; #address-cells = <1>; #size-cells = <0>; @@ -287,7 +296,7 @@ gsw: gsw@10110000 { compatible = "mediatek,mt7620-gsw"; - reg = <0x10110000 8000>; + reg = <0x10110000 0x8000>; resets = <&rstctrl 23>; reset-names = "esw"; @@ -297,7 +306,7 @@ mediatek,port4 = "gmac"; }; - ehci@101c0000 { + ehci: ehci@101c0000 { compatible = "generic-ehci"; reg = <0x101c0000 0x1000>; @@ -310,7 +319,7 @@ status = "disabled"; }; - ohci@101c1000 { + ohci: ohci@101c1000 { compatible = "generic-ohci"; reg = <0x101c1000 0x1000>; @@ -323,9 +332,9 @@ status = "disabled"; }; - wmac@10180000 { + wmac: wmac@10180000 { compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 40000>; + reg = <0x10180000 0x40000>; interrupt-parent = <&cpuintc>; interrupts = <6>; @@ -333,5 +342,3 @@ ralink,eeprom = "soc_wmac.eeprom"; }; }; - -/include/ "fbsd-mt7620n.dtsi" diff --git a/sys/gnu/dts/mips/mt7621.dtsi b/sys/gnu/dts/mips/mt7621.dtsi index 50ac0a0..32d3ef4 100644 --- a/sys/gnu/dts/mips/mt7621.dtsi +++ b/sys/gnu/dts/mips/mt7621.dtsi @@ -22,6 +22,10 @@ compatible = "mti,cpu-interrupt-controller"; }; + aliases { + serial0 = &uartlite; + }; + cpuclock: cpuclock@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -38,7 +42,7 @@ clock-frequency = <50000000>; }; - palmbus@1E000000 { + palmbus: palmbus@1E000000 { compatible = "palmbus"; reg = <0x1E000000 0x100000>; ranges = <0x0 0x1E000000 0x0FFFFF>; @@ -46,12 +50,12 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { + sysc: sysc@0 { compatible = "mtk,mt7621-sysc"; reg = <0x0 0x100>; }; - wdt@100 { + wdt: wdt@100 { compatible = "mtk,mt7621-wdt"; reg = <0x100 0x100>; }; @@ -85,26 +89,27 @@ }; }; - memc@5000 { + memc: memc@5000 { compatible = "mtk,mt7621-memc"; reg = <0x300 0x100>; }; - cpc@1fbf0000 { + cpc: cpc@1fbf0000 { compatible = "mtk,mt7621-cpc"; reg = <0x1fbf0000 0x8000>; }; - mc@1fbf8000 { + mc: mc@1fbf8000 { compatible = "mtk,mt7621-mc"; reg = <0x1fbf8000 0x8000>; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; clocks = <&sysclock>; + clock-frequency = <50000000>; interrupt-parent = <&gic>; interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; @@ -114,7 +119,7 @@ no-loopback-test; }; - spi@b00 { + spi0: spi@b00 { status = "okay"; compatible = "ralink,mt7621-spi"; @@ -141,7 +146,7 @@ }; }; - pinctrl { + pinctrl: pinctrl { compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -237,15 +242,20 @@ #reset-cells = <1>; }; - sdhci@1E130000 { + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + + sdhci: sdhci@1E130000 { compatible = "ralink,mt7620-sdhci"; - reg = <0x1E130000 4000>; + reg = <0x1E130000 0x4000>; interrupt-parent = <&gic>; interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; }; - xhci@1E1C0000 { + xhci: xhci@1E1C0000 { status = "okay"; compatible = "mediatek,mt8173-xhci"; @@ -275,7 +285,7 @@ }; }; - nand@1e003000 { + nand: nand@1e003000 { status = "disabled"; compatible = "mtk,mt7621-nand"; @@ -286,9 +296,9 @@ #size-cells = <1>; }; - ethernet@1e100000 { + ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; - reg = <0x1e100000 10000>; + reg = <0x1e100000 0x10000>; #address-cells = <1>; #size-cells = <0>; @@ -314,12 +324,12 @@ gsw: gsw@1e110000 { compatible = "mediatek,mt7621-gsw"; - reg = <0x1e110000 8000>; + reg = <0x1e110000 0x8000>; interrupt-parent = <&gic>; interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; }; - pcie@1e140000 { + pcie: pcie@1e140000 { compatible = "mediatek,mt7621-pci"; reg = <0x1e140000 0x100 0x1e142000 0x100>; @@ -345,6 +355,11 @@ status = "okay"; + resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; + reset-names = "pcie0", "pcie1", "pcie2"; + clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; + clock-names = "pcie0", "pcie1", "pcie2"; + pcie0 { reg = <0x0000 0 0 0 0>; @@ -374,4 +389,4 @@ }; }; -/include/ "fbsd-mt7621.dtsi" +#include "fbsd-mt7621.dtsi" diff --git a/sys/gnu/dts/mips/mt7628an.dtsi b/sys/gnu/dts/mips/mt7628an.dtsi index 2b723fa..683b652 100644 --- a/sys/gnu/dts/mips/mt7628an.dtsi +++ b/sys/gnu/dts/mips/mt7628an.dtsi @@ -13,6 +13,10 @@ bootargs = "console=ttyS0,57600"; }; + aliases { + serial0 = &uartlite; + }; + cpuintc: cpuintc@0 { #address-cells = <0>; #interrupt-cells = <1>; @@ -20,7 +24,7 @@ compatible = "mti,cpu-interrupt-controller"; }; - palmbus@10000000 { + palmbus: palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; ranges = <0x0 0x10000000 0x1FFFFF>; @@ -28,12 +32,12 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { + sysc: sysc@0 { compatible = "ralink,mt7620a-sysc"; reg = <0x0 0x100>; }; - watchdog@120 { + watchdog: watchdog@120 { compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt"; reg = <0x120 0x10>; @@ -62,7 +66,7 @@ 0x80 0x78>; }; - memc@300 { + memc: memc@300 { compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; reg = <0x300 0x100>; @@ -105,7 +109,7 @@ }; }; - i2c@900 { + i2c: i2c@900 { compatible = "mediatek,mt7628-i2c"; reg = <0x900 0x100>; @@ -121,7 +125,7 @@ pinctrl-0 = <&i2c_pins>; }; - i2s@a00 { + i2s: i2s@a00 { compatible = "ralink,mt7620a-i2s"; reg = <0xa00 0x100>; @@ -138,7 +142,7 @@ status = "disabled"; }; - spi@b00 { + spi0: spi@b00 { compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; @@ -154,7 +158,7 @@ status = "disabled"; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; @@ -162,6 +166,8 @@ reg-io-width = <4>; no-loopback-test; + clock-frequency = <40000000>; + resets = <&rstctrl 12>; reset-names = "uartl"; @@ -172,7 +178,7 @@ pinctrl-0 = <&uart0_pins>; }; - uart1@d00 { + uart1: uart1@d00 { compatible = "ns16550a"; reg = <0xd00 0x100>; @@ -180,6 +186,8 @@ reg-io-width = <4>; no-loopback-test; + clock-frequency = <40000000>; + resets = <&rstctrl 19>; reset-names = "uart1"; @@ -192,7 +200,7 @@ status = "disabled"; }; - uart2@e00 { + uart2: uart2@e00 { compatible = "ns16550a"; reg = <0xe00 0x100>; @@ -200,6 +208,8 @@ reg-io-width = <4>; no-loopback-test; + clock-frequency = <40000000>; + resets = <&rstctrl 20>; reset-names = "uart2"; @@ -212,7 +222,7 @@ status = "disabled"; }; - pwm@5000 { + pwm: pwm@5000 { compatible = "mediatek,mt7628-pwm"; reg = <0x5000 0x1000>; @@ -225,7 +235,7 @@ status = "disabled"; }; - pcm@2000 { + pcm: pcm@2000 { compatible = "ralink,mt7620a-pcm"; reg = <0x2000 0x800>; @@ -256,7 +266,7 @@ }; }; - pinctrl { + pinctrl: pinctrl { compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -340,18 +350,25 @@ #reset-cells = <1>; }; + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + usbphy: usbphy@10120000 { compatible = "ralink,mt7628an-usbphy", "mediatek,mt7620-usbphy"; - reg = <0x10120000 4000>; + reg = <0x10120000 0x4000>; #phy-cells = <1>; resets = <&rstctrl 22 &rstctrl 25>; reset-names = "host", "device"; + clocks = <&clkctrl 22 &clkctrl 25>; + clock-names = "host", "device"; }; - sdhci@10130000 { + sdhci: sdhci@10130000 { compatible = "ralink,mt7620-sdhci"; - reg = <0x10130000 4000>; + reg = <0x10130000 0x4000>; interrupt-parent = <&intc>; interrupts = <14>; @@ -362,7 +379,7 @@ status = "disabled"; }; - ehci@101c0000 { + ehci: ehci@101c0000 { compatible = "generic-ehci"; reg = <0x101c0000 0x1000>; @@ -373,7 +390,7 @@ interrupts = <18>; }; - ohci@101c1000 { + ohci: ohci@101c1000 { compatible = "generic-ohci"; reg = <0x101c1000 0x1000>; @@ -384,9 +401,9 @@ interrupts = <18>; }; - ethernet@10100000 { + ethernet: ethernet@10100000 { compatible = "ralink,rt5350-eth"; - reg = <0x10100000 10000>; + reg = <0x10100000 0x10000>; interrupt-parent = <&cpuintc>; interrupts = <5>; @@ -398,8 +415,8 @@ }; esw: esw@10110000 { - compatible = "ralink,rt3050-esw"; - reg = <0x10110000 8000>; + compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw"; + reg = <0x10110000 0x8000>; resets = <&rstctrl 23>; reset-names = "esw"; @@ -408,7 +425,7 @@ interrupts = <17>; }; - pcie@10140000 { + pcie: pcie@10140000 { compatible = "mediatek,mt7620-pci"; reg = <0x10140000 0x100 0x10142000 0x100>; @@ -416,12 +433,14 @@ #address-cells = <3>; #size-cells = <2>; - resets = <&rstctrl 26>; - reset-names = "pcie0"; - interrupt-parent = <&cpuintc>; interrupts = <4>; + resets = <&rstctrl 26 &rstctrl 27>; + reset-names = "pcie0", "pcie1"; + clocks = <&clkctrl 26 &clkctrl 27>; + clock-names = "pcie0", "pcie1"; + status = "disabled"; device_type = "pci"; @@ -444,7 +463,7 @@ wmac: wmac@10300000 { compatible = "mediatek,mt7628-wmac"; - reg = <0x10300000 100000>; + reg = <0x10300000 0x100000>; interrupt-parent = <&cpuintc>; interrupts = <6>; @@ -456,4 +475,4 @@ }; }; -/include/ "fbsd-mt7628an.dtsi" +#include "fbsd-mt7628an.dtsi" diff --git a/sys/gnu/dts/mips/rt2880.dtsi b/sys/gnu/dts/mips/rt2880.dtsi index 137b976..ad88254 100644 --- a/sys/gnu/dts/mips/rt2880.dtsi +++ b/sys/gnu/dts/mips/rt2880.dtsi @@ -13,6 +13,10 @@ bootargs = "console=ttyS0,57600"; }; + aliases { + serial0 = &uartlite; + }; + cpuintc: cpuintc@0 { #address-cells = <0>; #interrupt-cells = <1>; @@ -20,7 +24,7 @@ compatible = "mti,cpu-interrupt-controller"; }; - palmbus@300000 { + palmbus: palmbus@300000 { compatible = "palmbus"; reg = <0x300000 0x200000>; ranges = <0x0 0x300000 0x1FFFFF>; @@ -28,12 +32,12 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { + sysc: sysc@0 { compatible = "ralink,rt2880-sysc"; reg = <0x000 0x100>; }; - timer@100 { + timer: timer@100 { compatible = "ralink,rt2880-timer"; reg = <0x100 0x20>; @@ -43,7 +47,7 @@ status = "disabled"; }; - watchdog@120 { + watchdog: watchdog@120 { compatible = "ralink,rt2880-wdt"; reg = <0x120 0x10>; }; @@ -59,7 +63,7 @@ interrupts = <2>; }; - memc@300 { + memc: memc@300 { compatible = "ralink,rt2880-memc"; reg = <0x300 0x100>; }; @@ -110,7 +114,7 @@ status = "disabled"; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; @@ -121,7 +125,7 @@ }; }; - pinctrl { + pinctrl: pinctrl { compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; @@ -154,9 +158,14 @@ #reset-cells = <1>; }; - ethernet@400000 { + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + + ethernet: ethernet@400000 { compatible = "ralink,rt2880-eth"; - reg = <0x00400000 10000>; + reg = <0x00400000 0x10000>; #address-cells = <1>; #size-cells = <0>; @@ -182,9 +191,9 @@ }; }; - wmac@480000 { + wmac: wmac@480000 { compatible = "ralink,rt2880-wmac"; - reg = <0x480000 40000>; + reg = <0x480000 0x40000>; interrupt-parent = <&cpuintc>; interrupts = <6>; @@ -192,5 +201,3 @@ ralink,eeprom = "soc_wmac.eeprom"; }; }; - -/include/ "fbsd-rt2880.dtsi" diff --git a/sys/gnu/dts/mips/rt3050.dtsi b/sys/gnu/dts/mips/rt3050.dtsi index 9ac3efd..caf448b 100644 --- a/sys/gnu/dts/mips/rt3050.dtsi +++ b/sys/gnu/dts/mips/rt3050.dtsi @@ -15,6 +15,7 @@ aliases { spi0 = &spi0; + serial0 = &uartlite; }; cpuintc: cpuintc@0 { @@ -24,7 +25,7 @@ compatible = "mti,cpu-interrupt-controller"; }; - palmbus@10000000 { + palmbus: palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; ranges = <0x0 0x10000000 0x1FFFFF>; @@ -32,12 +33,12 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { + sysc: sysc@0 { compatible = "ralink,rt3050-sysc"; reg = <0x0 0x100>; }; - timer@100 { + timer: timer@100 { compatible = "ralink,rt3050-timer", "ralink,rt2880-timer"; reg = <0x100 0x20>; @@ -45,7 +46,7 @@ interrupts = <1>; }; - watchdog@120 { + watchdog: watchdog@120 { compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt"; reg = <0x120 0x10>; @@ -70,7 +71,7 @@ interrupts = <2>; }; - memc@300 { + memc: memc@300 { compatible = "ralink,rt3050-memc"; reg = <0x300 0x100>; @@ -81,7 +82,7 @@ interrupts = <3>; }; - uart@500 { + uart: uart@500 { compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0x500 0x100>; @@ -164,7 +165,7 @@ status = "disabled"; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; @@ -181,7 +182,7 @@ }; }; - pinctrl { + pinctrl: pinctrl { compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; @@ -214,9 +215,22 @@ #reset-cells = <1>; }; - ethernet@10100000 { + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + + usbphy: usbphy { + compatible = "ralink,rt3050-usbphy"; + resets = <&rstctrl 22>; + reset-names = "host"; + clocks = <&clkctrl 18>; + clock-names = "host"; + }; + + ethernet: ethernet@10100000 { compatible = "ralink,rt3050-eth"; - reg = <0x10100000 10000>; + reg = <0x10100000 0x10000>; resets = <&rstctrl 21>; reset-names = "fe"; @@ -229,7 +243,7 @@ esw: esw@10110000 { compatible = "ralink,rt3050-esw"; - reg = <0x10110000 8000>; + reg = <0x10110000 0x8000>; resets = <&rstctrl 23>; reset-names = "esw"; @@ -238,9 +252,9 @@ interrupts = <17>; }; - wmac@10180000 { + wmac: wmac@10180000 { compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 40000>; + reg = <0x10180000 0x40000>; interrupt-parent = <&cpuintc>; interrupts = <6>; @@ -248,9 +262,9 @@ ralink,eeprom = "soc_wmac.eeprom"; }; - otg@101c0000 { + otg: otg@101c0000 { compatible = "ralink,rt3050-otg", "snps,dwc2"; - reg = <0x101c0000 40000>; + reg = <0x101c0000 0x40000>; interrupt-parent = <&intc>; interrupts = <18>; @@ -261,5 +275,3 @@ status = "disabled"; }; }; - -/include/ "fbsd-rt3050.dtsi" diff --git a/sys/gnu/dts/mips/rt3352.dtsi b/sys/gnu/dts/mips/rt3352.dtsi index 7dc554b..a818a18 100644 --- a/sys/gnu/dts/mips/rt3352.dtsi +++ b/sys/gnu/dts/mips/rt3352.dtsi @@ -23,9 +23,10 @@ aliases { spi0 = &spi0; spi1 = &spi1; + serial0 = &uartlite; }; - palmbus@10000000 { + palmbus: palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; ranges = <0x0 0x10000000 0x1FFFFF>; @@ -33,12 +34,12 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { + sysc: sysc@0 { compatible = "ralink,rt3352-sysc", "ralink,rt3050-sysc"; reg = <0x0 0x100>; }; - timer@100 { + timer: timer@100 { compatible = "ralink,rt3352-timer", "ralink,rt2880-timer"; reg = <0x100 0x20>; @@ -46,7 +47,7 @@ interrupts = <1>; }; - watchdog@120 { + watchdog: watchdog@120 { compatible = "ralink,rt3352-wdt", "ralink,rt2880-wdt"; reg = <0x120 0x10>; @@ -68,7 +69,7 @@ interrupts = <2>; }; - memc@300 { + memc: memc@300 { compatible = "ralink,rt3352-memc", "ralink,rt3050-memc"; reg = <0x300 0x100>; @@ -79,7 +80,7 @@ interrupts = <3>; }; - uart@500 { + uart: uart@500 { compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0x500 0x100>; @@ -175,7 +176,7 @@ status = "disabled"; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; @@ -192,7 +193,7 @@ }; }; - pinctrl { + pinctrl: pinctrl { compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; @@ -228,9 +229,14 @@ #reset-cells = <1>; }; - ethernet@10100000 { + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + + ethernet: ethernet@10100000 { compatible = "ralink,rt3352-eth", "ralink,rt3050-eth"; - reg = <0x10100000 10000>; + reg = <0x10100000 0x10000>; resets = <&rstctrl 21>; reset-names = "fe"; @@ -243,7 +249,7 @@ esw: esw@10110000 { compatible = "ralink,rt3352-esw", "ralink,rt3050-esw"; - reg = <0x10110000 8000>; + reg = <0x10110000 0x8000>; resets = <&rstctrl 23>; reset-names = "esw"; @@ -252,16 +258,19 @@ interrupts = <17>; }; - usbphy { + usbphy: usbphy { compatible = "ralink,rt3352-usbphy"; + #phy-cells = <1>; resets = <&rstctrl 22 &rstctrl 25>; reset-names = "host", "device"; + clocks = <&clkctrl 18 &clkctrl 20>; + clock-names = "host", "device"; }; - wmac@10180000 { + wmac: wmac@10180000 { compatible = "ralink,rt3352-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 40000>; + reg = <0x10180000 0x40000>; interrupt-parent = <&cpuintc>; interrupts = <6>; @@ -269,25 +278,29 @@ ralink,eeprom = "soc_wmac.eeprom"; }; - ehci@101c0000 { + ehci: ehci@101c0000 { compatible = "generic-ehci"; reg = <0x101c0000 0x1000>; + phys = <&usbphy 1>; + phy-names = "usb"; + interrupt-parent = <&intc>; interrupts = <18>; status = "disabled"; }; - ohci@101c1000 { + ohci: ohci@101c1000 { compatible = "generic-ohci"; reg = <0x101c1000 0x1000>; + phys = <&usbphy 1>; + phy-names = "usb"; + interrupt-parent = <&intc>; interrupts = <18>; status = "disabled"; }; }; - -/include/ "fbsd-rt3352.dtsi" diff --git a/sys/gnu/dts/mips/rt3883.dtsi b/sys/gnu/dts/mips/rt3883.dtsi index f52edcf..e4fa2ae 100644 --- a/sys/gnu/dts/mips/rt3883.dtsi +++ b/sys/gnu/dts/mips/rt3883.dtsi @@ -16,6 +16,7 @@ aliases { spi0 = &spi0; spi1 = &spi1; + serial0 = &uartlite; }; cpuintc: cpuintc@0 { @@ -25,7 +26,7 @@ compatible = "mti,cpu-interrupt-controller"; }; - palmbus@10000000 { + palmbus: palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; ranges = <0x0 0x10000000 0x1FFFFF>; @@ -33,12 +34,12 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { + sysc: sysc@0 { compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc"; reg = <0x0 0x100>; }; - timer@100 { + timer: timer@100 { compatible = "ralink,rt3883-timer", "ralink,rt2880-timer"; reg = <0x100 0x20>; @@ -46,7 +47,7 @@ interrupts = <1>; }; - watchdog@120 { + watchdog: watchdog@120 { compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt"; reg = <0x120 0x10>; @@ -71,7 +72,7 @@ interrupts = <2>; }; - memc@300 { + memc: memc@300 { compatible = "ralink,rt3883-memc", "ralink,rt3050-memc"; reg = <0x300 0x100>; @@ -82,7 +83,7 @@ interrupts = <3>; }; - uart@500 { + uart: uart@500 { compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0x500 0x100>; @@ -195,7 +196,7 @@ status = "disabled"; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; @@ -212,7 +213,7 @@ }; }; - pinctrl { + pinctrl: pinctrl { compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; @@ -243,9 +244,9 @@ }; }; - ethernet@10100000 { + ethernet: ethernet@10100000 { compatible = "ralink,rt3883-eth"; - reg = <0x10100000 10000>; + reg = <0x10100000 0x10000>; resets = <&rstctrl 21>; reset-names = "fe"; @@ -271,7 +272,12 @@ #reset-cells = <1>; }; - pci@10140000 { + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + + pci: pci@10140000 { compatible = "ralink,rt3883-pci"; reg = <0x10140000 0x20000>; #address-cells = <1>; @@ -363,11 +369,13 @@ resets = <&rstctrl 22 &rstctrl 25>; reset-names = "host", "device"; + clocks = <&clkctrl 22 &clkctrl 25>; + clock-names = "host", "device"; }; - wmac@10180000 { + wmac: wmac@10180000 { compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 40000>; + reg = <0x10180000 0x40000>; interrupt-parent = <&cpuintc>; interrupts = <6>; @@ -375,7 +383,7 @@ ralink,eeprom = "soc_wmac.eeprom"; }; - ehci@101c0000 { + ehci: ehci@101c0000 { compatible = "generic-ehci"; reg = <0x101c0000 0x1000>; @@ -388,7 +396,7 @@ status = "disabled"; }; - ohci@101c1000 { + ohci: ohci@101c1000 { compatible = "generic-ohci"; reg = <0x101c1000 0x1000>; @@ -402,4 +410,4 @@ }; }; -/include/ "fbsd-rt3883.dtsi" +#include "fbsd-rt3883.dtsi" diff --git a/sys/gnu/dts/mips/rt5350.dtsi b/sys/gnu/dts/mips/rt5350.dtsi index 057758c..c844117 100644 --- a/sys/gnu/dts/mips/rt5350.dtsi +++ b/sys/gnu/dts/mips/rt5350.dtsi @@ -23,9 +23,10 @@ aliases { spi0 = &spi0; spi1 = &spi1; + serial0 = &uartlite; }; - palmbus@10000000 { + palmbus: palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; ranges = <0x0 0x10000000 0x1FFFFF>; @@ -33,12 +34,12 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { + sysc: sysc@0 { compatible = "ralink,rt5350-sysc", "ralink,rt3050-sysc"; reg = <0x0 0x100>; }; - timer@100 { + timer: timer@100 { compatible = "ralink,rt5350-timer", "ralink,rt2880-timer"; reg = <0x100 0x20>; @@ -46,7 +47,7 @@ interrupts = <1>; }; - watchdog@120 { + watchdog: watchdog@120 { compatible = "ralink,rt5350-wdt", "ralink,rt2880-wdt"; reg = <0x120 0x10>; @@ -71,7 +72,7 @@ interrupts = <2>; }; - memc@300 { + memc: memc@300 { compatible = "ralink,rt5350-memc", "ralink,rt3050-memc"; reg = <0x300 0x100>; @@ -82,7 +83,7 @@ interrupts = <3>; }; - uart@500 { + uart: uart@500 { compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0x500 0x100>; @@ -136,7 +137,7 @@ status = "disabled"; }; - i2c@900 { + i2c: i2c@900 { compatible = "link,rt5350-i2c", "ralink,rt2880-i2c"; reg = <0x900 0x100>; @@ -184,7 +185,7 @@ status = "disabled"; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; @@ -200,7 +201,7 @@ reg-shift = <2>; }; - systick@d00 { + systick: systick@d00 { compatible = "ralink,rt5350-systick", "ralink,cevt-systick"; reg = <0xd00 0x10>; @@ -209,7 +210,7 @@ }; }; - pinctrl { + pinctrl: pinctrl { compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; @@ -266,17 +267,24 @@ #reset-cells = <1>; }; + clkctrl: clkctrl { + compatible = "ralink,rt2880-clock"; + #clock-cells = <1>; + }; + usbphy: usbphy { compatible = "ralink,rt3352-usbphy"; #phy-cells = <1>; resets = <&rstctrl 22 &rstctrl 25>; reset-names = "host", "device"; + clocks = <&clkctrl 18>; + clock-names = "host"; }; - ethernet@10100000 { + ethernet: ethernet@10100000 { compatible = "ralink,rt5350-eth"; - reg = <0x10100000 10000>; + reg = <0x10100000 0x10000>; resets = <&rstctrl 21 &rstctrl 23>; reset-names = "fe", "esw"; @@ -288,8 +296,8 @@ }; esw: esw@10110000 { - compatible = "ralink,rt3050-esw"; - reg = <0x10110000 8000>; + compatible = "ralink,rt5350-esw", "ralink,rt3050-esw"; + reg = <0x10110000 0x8000>; resets = <&rstctrl 23>; reset-names = "esw"; @@ -298,9 +306,9 @@ interrupts = <17>; }; - wmac@10180000 { + wmac: wmac@10180000 { compatible = "ralink,rt5350-wmac", "ralink,rt2880-wmac"; - reg = <0x10180000 40000>; + reg = <0x10180000 0x40000>; interrupt-parent = <&cpuintc>; interrupts = <6>; @@ -308,7 +316,7 @@ ralink,eeprom = "soc_wmac.eeprom"; }; - ehci@101c0000 { + ehci: ehci@101c0000 { compatible = "generic-ehci"; reg = <0x101c0000 0x1000>; @@ -319,7 +327,7 @@ interrupts = <18>; }; - ohci@101c1000 { + ohci: ohci@101c1000 { compatible = "generic-ohci"; reg = <0x101c1000 0x1000>; @@ -330,5 +338,3 @@ interrupts = <18>; }; }; - -/include/ "fbsd-rt5350.dtsi" diff --git a/sys/gnu/fs/reiserfs/README b/sys/gnu/fs/reiserfs/README deleted file mode 100644 index f3917c1..0000000 --- a/sys/gnu/fs/reiserfs/README +++ /dev/null @@ -1,163 +0,0 @@ -$FreeBSD$ - -[LICENSING] - -ReiserFS is hereby licensed under the GNU General -Public License version 2. - -Source code files that contain the phrase "licensing governed by -reiserfs/README" are "governed files" throughout this file. Governed -files are licensed under the GPL. The portions of them owned by Hans -Reiser, or authorized to be licensed by him, have been in the past, -and likely will be in the future, licensed to other parties under -other licenses. If you add your code to governed files, and don't -want it to be owned by Hans Reiser, put your copyright label on that -code so the poor blight and his customers can keep things straight. -All portions of governed files not labeled otherwise are owned by Hans -Reiser, and by adding your code to it, widely distributing it to -others or sending us a patch, and leaving the sentence in stating that -licensing is governed by the statement in this file, you accept this. -It will be a kindness if you identify whether Hans Reiser is allowed -to license code labeled as owned by you on your behalf other than -under the GPL, because he wants to know if it is okay to do so and put -a check in the mail to you (for non-trivial improvements) when he -makes his next sale. He makes no guarantees as to the amount if any, -though he feels motivated to motivate contributors, and you can surely -discuss this with him before or after contributing. You have the -right to decline to allow him to license your code contribution other -than under the GPL. - -Further licensing options are available for commercial and/or other -interests directly from Hans Reiser: hans@reiser.to. If you interpret -the GPL as not allowing those additional licensing options, you read -it wrongly, and Richard Stallman agrees with me, when carefully read -you can see that those restrictions on additional terms do not apply -to the owner of the copyright, and my interpretation of this shall -govern for this license. - -Finally, nothing in this license shall be interpreted to allow you to -fail to fairly credit me, or to remove my credits, without my -permission, unless you are an end user not redistributing to others. -If you have doubts about how to properly do that, or about what is -fair, ask. (Last I spoke with him Richard was contemplating how best -to address the fair crediting issue in the next GPL version.) - -[END LICENSING] - -Reiserfs is a file system based on balanced tree algorithms, which is -described at http://devlinux.com/namesys. - -Stop reading here. Go there, then return. - -Send bug reports to yura@namesys.botik.ru. - -mkreiserfs and other utilities are in reiserfs/utils, or wherever your -Linux provider put them. There is some disagreement about how useful -it is for users to get their fsck and mkreiserfs out of sync with the -version of reiserfs that is in their kernel, with many important -distributors wanting them out of sync.:-) Please try to remember to -recompile and reinstall fsck and mkreiserfs with every update of -reiserfs, this is a common source of confusion. Note that some of the -utilities cannot be compiled without accessing the balancing code -which is in the kernel code, and relocating the utilities may require -you to specify where that code can be found. - -Yes, if you update your reiserfs kernel module you do have to -recompile your kernel, most of the time. The errors you get will be -quite cryptic if your forget to do so. - -Real users, as opposed to folks who want to hack and then understand -what went wrong, will want REISERFS_CHECK off. - -Hideous Commercial Pitch: Spread your development costs across other OS -vendors. Select from the best in the world, not the best in your -building, by buying from third party OS component suppliers. Leverage -the software component development power of the internet. Be the most -aggressive in taking advantage of the commercial possibilities of -decentralized internet development, and add value through your branded -integration that you sell as an operating system. Let your competitors -be the ones to compete against the entire internet by themselves. Be -hip, get with the new economic trend, before your competitors do. Send -email to hans@reiser.to. - -To understand the code, after reading the website, start reading the -code by reading reiserfs_fs.h first. - -Hans Reiser was the project initiator, primary architect, source of all -funding for the first 5.5 years, and one of the programmers. He owns -the copyright. - -Vladimir Saveljev was one of the programmers, and he worked long hours -writing the cleanest code. He always made the effort to be the best he -could be, and to make his code the best that it could be. What resulted -was quite remarkable. I don't think that money can ever motivate someone -to work the way he did, he is one of the most selfless men I know. - -Yura helps with benchmarking, coding hashes, and block pre-allocation -code. - -Anatoly Pinchuk is a former member of our team who worked closely with -Vladimir throughout the project's development. He wrote a quite -substantial portion of the total code. He realized that there was a -space problem with packing tails of files for files larger than a node -that start on a node aligned boundary (there are reasons to want to node -align files), and he invented and implemented indirect items and -unformatted nodes as the solution. - -Konstantin Shvachko, with the help of the Russian version of a VC, -tried to put me in a position where I was forced into giving control -of the project to him. (Fortunately, as the person paying the money -for all salaries from my dayjob I owned all copyrights, and you can't -really force takeovers of sole proprietorships.) This was something -curious, because he never really understood the value of our project, -why we should do what we do, or why innovation was possible in -general, but he was sure that he ought to be controlling it. Every -innovation had to be forced past him while he was with us. He added -two years to the time required to complete reiserfs, and was a net -loss for me. Mikhail Gilula was a brilliant innovator who also left -in a destructive way that erased the value of his contributions, and -that he was shown much generosity just makes it more painful. - -Grigory Zaigralin was an extremely effective system administrator for -our group. - -Igor Krasheninnikov was wonderful at hardware procurement, repair, and -network installation. - -Jeremy Fitzhardinge wrote the teahash.c code, and he gives credit to a -textbook he got the algorithm from in the code. Note that his analysis -of how we could use the hashing code in making 32 bit NFS cookies work -was probably more important than the actual algorithm. Colin Plumb also -contributed to it. - -Chris Mason dived right into our code, and in just a few months produced -the journaling code that dramatically increased the value of ReiserFS. -He is just an amazing programmer. - -Igor Zagorovsky is writing much of the new item handler and extent code -for our next major release. - -Alexander Zarochentcev (sometimes known as zam, or sasha), wrote the -resizer, and is hard at work on implementing allocate on flush. SGI -implemented allocate on flush before us for XFS, and generously took -the time to convince me we should do it also. They are great people, -and a great company. - -Yuri Shevchuk and Nikita Danilov are doing squid cache optimization. - -Vitaly Fertman is doing fsck. - -Jeff Mahoney, of SuSE, contributed a few cleanup fixes, most notably -the endian safe patches which allow ReiserFS to run on any platform -supported by the Linux kernel. - -SuSE, IntegratedLinux.com, Ecila, MP3.com, bigstorage.com, and the -Alpha PC Company made it possible for me to not have a day job -anymore, and to dramatically increase our staffing. Ecila funded -hypertext feature development, MP3.com funded journaling, SuSE funded -core development, IntegratedLinux.com funded squid web cache -appliances, bigstorage.com funded HSM, and the alpha PC company funded -the alpha port. Many of these tasks were helped by sponsors other -than the ones just named. SuSE has helped in much more than just -funding.... - diff --git a/sys/gnu/fs/reiserfs/reiserfs_fs.h b/sys/gnu/fs/reiserfs/reiserfs_fs.h deleted file mode 100644 index 7aed2f2..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_fs.h +++ /dev/null @@ -1,1289 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#ifndef _GNU_REISERFS_REISERFS_FS_H -#define _GNU_REISERFS_REISERFS_FS_H - -#include <sys/cdefs.h> -#include <sys/types.h> -#include <sys/endian.h> -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/kernel.h> -#include <sys/mount.h> -#include <sys/namei.h> -#include <sys/priv.h> -#include <sys/proc.h> -#include <sys/vnode.h> -#include <sys/unistd.h> - -#include <sys/bio.h> -#include <sys/buf.h> -#include <sys/conf.h> -#include <sys/fcntl.h> -#include <sys/syslog.h> - -#include <sys/malloc.h> -#include <sys/dirent.h> -#include <sys/stat.h> -//#include <sys/mutex.h> - -#include <sys/ctype.h> -#include <sys/bitstring.h> - -#include <geom/geom.h> -#include <geom/geom_vfs.h> - -#include <gnu/fs/reiserfs/reiserfs_mount.h> -#include <gnu/fs/reiserfs/reiserfs_fs_sb.h> -#include <gnu/fs/reiserfs/reiserfs_fs_i.h> - -/* n must be power of 2 */ -#define _ROUND_UP(x, n) (((x) + (n) - 1u) & ~((n) - 1u)) - -/* To be ok for alpha and others we have to align structures to 8 byte - * boundary. */ -#define ROUND_UP(x) _ROUND_UP(x, 8LL) - -/* ------------------------------------------------------------------- - * Global variables - * -------------------------------------------------------------------*/ - -extern struct vop_vector reiserfs_vnodeops; -extern struct vop_vector reiserfs_specops; - -/* ------------------------------------------------------------------- - * Super block - * -------------------------------------------------------------------*/ - -#define REISERFS_BSIZE 1024 - -/* ReiserFS leaves the first 64k unused, so that partition labels have - * enough space. If someone wants to write a fancy bootloader that needs - * more than 64k, let us know, and this will be increased in size. - * This number must be larger than than the largest block size on any - * platform, or code will break. -Hans */ -#define REISERFS_DISK_OFFSET 64 -#define REISERFS_DISK_OFFSET_IN_BYTES \ - ((REISERFS_DISK_OFFSET) * (REISERFS_BSIZE)) - -/* The spot for the super in versions 3.5 - 3.5.10 (inclusive) */ -#define REISERFS_OLD_DISK_OFFSET 8 -#define REISERFS_OLD_DISK_OFFSET_IN_BYTES \ - ((REISERFS_OLD_DISK_OFFSET) * (REISERFS_BSIZE)) - -/* - * Structure of a super block on disk, a version of which in RAM is - * often accessed as REISERFS_SB(s)->r_rs. The version in RAM is part of - * a larger structure containing fields never written to disk. - */ - -#define UNSET_HASH 0 /* read_super will guess about, what hash names - in directories were sorted with */ -#define TEA_HASH 1 -#define YURA_HASH 2 -#define R5_HASH 3 -#define DEFAULT_HASH R5_HASH - -struct journal_params { - uint32_t jp_journal_1st_block; /* Where does journal start - from on its device */ - uint32_t jp_journal_dev; /* Journal device st_rdev */ - uint32_t jp_journal_size; /* Size of the journal */ - uint32_t jp_journal_trans_max; /* Max number of blocks in - a transaction */ - uint32_t jp_journal_magic; /* Random value made on - fs creation (this was - sb_journal_block_count) */ - uint32_t jp_journal_max_batch; /* Max number of blocks to - batch into a - transaction */ - uint32_t jp_journal_max_commit_age; /* In seconds, how old can - an async commit be */ - uint32_t jp_journal_max_trans_age; /* In seconds, how old a - transaction be */ -}; - -struct reiserfs_super_block_v1 { - uint32_t s_block_count; /* Blocks count */ - uint32_t s_free_blocks; /* Free blocks count */ - uint32_t s_root_block; /* Root block number */ - - struct journal_params s_journal; - - uint16_t s_blocksize; - uint16_t s_oid_maxsize; - uint16_t s_oid_cursize; - uint16_t s_umount_state; - - char s_magic[10]; - - uint16_t s_fs_state; - uint32_t s_hash_function_code; - uint16_t s_tree_height; - uint16_t s_bmap_nr; - uint16_t s_version; - uint16_t s_reserved_for_journal; -} __packed; - -#define SB_SIZE_V1 (sizeof(struct reiserfs_super_block_v1)) - -struct reiserfs_super_block { - struct reiserfs_super_block_v1 s_v1; - uint32_t s_inode_generation; - uint32_t s_flags; - unsigned char s_uuid[16]; - unsigned char s_label[16]; - char s_unused[88]; -} __packed; - -#define SB_SIZE (sizeof(struct reiserfs_super_block)) - -#define REISERFS_VERSION_1 0 -#define REISERFS_VERSION_2 2 - -#define REISERFS_SB(sbi) (sbi) -#define SB_DISK_SUPER_BLOCK(sbi) (REISERFS_SB(sbi)->s_rs) -#define SB_V1_DISK_SUPER_BLOCK(sbi) (&(SB_DISK_SUPER_BLOCK(sbi)->s_v1)) - -#define SB_BLOCKSIZE(sbi) \ - le32toh((SB_V1_DISK_SUPER_BLOCK(sbi)->s_blocksize)) -#define SB_BLOCK_COUNT(sbi) \ - le32toh((SB_V1_DISK_SUPER_BLOCK(sbi)->s_block_count)) -#define SB_FREE_BLOCKS(s) \ - le32toh((SB_V1_DISK_SUPER_BLOCK(sbi)->s_free_blocks)) - -#define SB_REISERFS_MAGIC(sbi) \ - (SB_V1_DISK_SUPER_BLOCK(sbi)->s_magic) - -#define SB_ROOT_BLOCK(sbi) \ - le32toh((SB_V1_DISK_SUPER_BLOCK(sbi)->s_root_block)) - -#define SB_TREE_HEIGHT(sbi) \ - le16toh((SB_V1_DISK_SUPER_BLOCK(sbi)->s_tree_height)) - -#define SB_REISERFS_STATE(sbi) \ - le16toh((SB_V1_DISK_SUPER_BLOCK(sbi)->s_umount_state)) - -#define SB_VERSION(sbi) le16toh((SB_V1_DISK_SUPER_BLOCK(sbi)->s_version)) -#define SB_BMAP_NR(sbi) le16toh((SB_V1_DISK_SUPER_BLOCK(sbi)->s_bmap_nr)) - -#define REISERFS_SUPER_MAGIC_STRING "ReIsErFs" -#define REISER2FS_SUPER_MAGIC_STRING "ReIsEr2Fs" -#define REISER2FS_JR_SUPER_MAGIC_STRING "ReIsEr3Fs" - -extern const char reiserfs_3_5_magic_string[]; -extern const char reiserfs_3_6_magic_string[]; -extern const char reiserfs_jr_magic_string[]; - -int is_reiserfs_3_5(struct reiserfs_super_block *rs); -int is_reiserfs_3_6(struct reiserfs_super_block *rs); -int is_reiserfs_jr(struct reiserfs_super_block *rs); - -/* ReiserFS internal error code (used by search_by_key and fix_nodes) */ -#define IO_ERROR -2 - -typedef uint32_t b_blocknr_t; -typedef uint32_t unp_t; - -struct unfm_nodeinfo { - unp_t unfm_nodenum; - unsigned short unfm_freespace; -}; - -/* There are two formats of keys: 3.5 and 3.6 */ -#define KEY_FORMAT_3_5 0 -#define KEY_FORMAT_3_6 1 - -/* There are two stat datas */ -#define STAT_DATA_V1 0 -#define STAT_DATA_V2 1 - -#define REISERFS_I(ip) (ip) - -#define get_inode_item_key_version(ip) \ - ((REISERFS_I(ip)->i_flags & i_item_key_version_mask) ? \ - KEY_FORMAT_3_6 : KEY_FORMAT_3_5) - -#define set_inode_item_key_version(ip, version) ({ \ - if ((version) == KEY_FORMAT_3_6) \ - REISERFS_I(ip)->i_flags |= i_item_key_version_mask; \ - else \ - REISERFS_I(ip)->i_flags &= ~i_item_key_version_mask; \ -}) - -#define get_inode_sd_version(ip) \ - ((REISERFS_I(ip)->i_flags & i_stat_data_version_mask) ? \ - STAT_DATA_V2 : STAT_DATA_V1) - -#define set_inode_sd_version(inode, version) ({ \ - if((version) == STAT_DATA_V2) \ - REISERFS_I(ip)->i_flags |= i_stat_data_version_mask; \ - else \ - REISERFS_I(ip)->i_flags &= ~i_stat_data_version_mask; \ -}) - -/* Values for s_umount_state field */ -#define REISERFS_VALID_FS 1 -#define REISERFS_ERROR_FS 2 - -/* There are 5 item types currently */ -#define TYPE_STAT_DATA 0 -#define TYPE_INDIRECT 1 -#define TYPE_DIRECT 2 -#define TYPE_DIRENTRY 3 -#define TYPE_MAXTYPE 3 -#define TYPE_ANY 15 - -/* ------------------------------------------------------------------- - * Key & item head - * -------------------------------------------------------------------*/ - -struct offset_v1 { - uint32_t k_offset; - uint32_t k_uniqueness; -} __packed; - -struct offset_v2 { -#if BYTE_ORDER == LITTLE_ENDIAN - /* little endian version */ - uint64_t k_offset:60; - uint64_t k_type:4; -#else - /* big endian version */ - uint64_t k_type:4; - uint64_t k_offset:60; -#endif -} __packed; - -#if (BYTE_ORDER == BIG_ENDIAN) -typedef union { - struct offset_v2 offset_v2; - uint64_t linear; -} __packed offset_v2_esafe_overlay; - -static inline uint16_t -offset_v2_k_type(const struct offset_v2 *v2) -{ - - offset_v2_esafe_overlay tmp = *(const offset_v2_esafe_overlay *)v2; - tmp.linear = le64toh(tmp.linear); - return ((tmp.offset_v2.k_type <= TYPE_MAXTYPE) ? - tmp.offset_v2.k_type : TYPE_ANY); -} - -static inline void -set_offset_v2_k_type(struct offset_v2 *v2, int type) -{ - - offset_v2_esafe_overlay *tmp = (offset_v2_esafe_overlay *)v2; - tmp->linear = le64toh(tmp->linear); - tmp->offset_v2.k_type = type; - tmp->linear = htole64(tmp->linear); -} - -static inline off_t -offset_v2_k_offset(const struct offset_v2 *v2) -{ - - offset_v2_esafe_overlay tmp = *(const offset_v2_esafe_overlay *)v2; - tmp.linear = le64toh(tmp.linear); - return (tmp.offset_v2.k_offset); -} - -static inline void -set_offset_v2_k_offset(struct offset_v2 *v2, off_t offset) -{ - - offset_v2_esafe_overlay *tmp = (offset_v2_esafe_overlay *)v2; - tmp->linear = le64toh(tmp->linear); - tmp->offset_v2.k_offset = offset; - tmp->linear = htole64(tmp->linear); -} -#else /* BYTE_ORDER != BIG_ENDIAN */ -#define offset_v2_k_type(v2) ((v2)->k_type) -#define set_offset_v2_k_type(v2, val) (offset_v2_k_type(v2) = (val)) -#define offset_v2_k_offset(v2) ((v2)->k_offset) -#define set_offset_v2_k_offset(v2, val) (offset_v2_k_offset(v2) = (val)) -#endif /* BYTE_ORDER == BIG_ENDIAN */ - -/* - * Key of an item determines its location in the S+tree, and - * is composed of 4 components - */ -struct key { - uint32_t k_dir_id; /* Packing locality: by default parent - directory object id */ - uint32_t k_objectid; /* Object identifier */ - union { - struct offset_v1 k_offset_v1; - struct offset_v2 k_offset_v2; - } __packed u; -} __packed; - -struct cpu_key { - struct key on_disk_key; - int version; - int key_length; /* 3 in all cases but direct2indirect - and indirect2direct conversion */ -}; - -/* - * Our function for comparing keys can compare keys of different - * lengths. It takes as a parameter the length of the keys it is to - * compare. These defines are used in determining what is to be passed - * to it as that parameter. - */ -#define REISERFS_FULL_KEY_LEN 4 -#define REISERFS_SHORT_KEY_LEN 2 - -#define KEY_SIZE (sizeof(struct key)) -#define SHORT_KEY_SIZE (sizeof(uint32_t) + sizeof(uint32_t)) - -/* Return values for search_by_key and clones */ -#define ITEM_FOUND 1 -#define ITEM_NOT_FOUND 0 -#define ENTRY_FOUND 1 -#define ENTRY_NOT_FOUND 0 -#define DIRECTORY_NOT_FOUND -1 -#define REGULAR_FILE_FOUND -2 -#define DIRECTORY_FOUND -3 -#define BYTE_FOUND 1 -#define BYTE_NOT_FOUND 0 -#define FILE_NOT_FOUND -1 - -#define POSITION_FOUND 1 -#define POSITION_NOT_FOUND 0 - -/* Return values for reiserfs_find_entry and search_by_entry_key */ -#define NAME_FOUND 1 -#define NAME_NOT_FOUND 0 -#define GOTO_PREVIOUS_ITEM 2 -#define NAME_FOUND_INVISIBLE 3 - -/* - * Everything in the filesystem is stored as a set of items. The item - * head contains the key of the item, its free space (for indirect - * items) and specifies the location of the item itself within the - * block. - */ -struct item_head { - /* - * Everything in the tree is found by searching for it based on - * its key. - */ - struct key ih_key; - union { - /* - * The free space in the last unformatted node of an - * indirect item if this is an indirect item. This - * equals 0xFFFF iff this is a direct item or stat data - * item. Note that the key, not this field, is used to - * determine the item type, and thus which field this - * union contains. - */ - uint16_t ih_free_space_reserved; - - /* - * If this is a directory item, this field equals the number of - * directory entries in the directory item. - */ - uint16_t ih_entry_count; - } __packed u; - uint16_t ih_item_len; /* Total size of the item body */ - uint16_t ih_item_location; /* An offset to the item body within - the block */ - uint16_t ih_version; /* 0 for all old items, 2 for new - ones. Highest bit is set by fsck - temporary, cleaned after all - done */ -} __packed; - -/* Size of item header */ -#define IH_SIZE (sizeof(struct item_head)) - -#define ih_free_space(ih) le16toh((ih)->u.ih_free_space_reserved) -#define ih_version(ih) le16toh((ih)->ih_version) -#define ih_entry_count(ih) le16toh((ih)->u.ih_entry_count) -#define ih_location(ih) le16toh((ih)->ih_item_location) -#define ih_item_len(ih) le16toh((ih)->ih_item_len) - -/* - * These operate on indirect items, where you've got an array of ints at - * a possibly unaligned location. These are a noop on IA32. - * - * p is the array of uint32_t, i is the index into the array, v is the - * value to store there. - */ -#define get_unaligned(ptr) \ - ({ __typeof__(*(ptr)) __tmp; \ - memcpy(&__tmp, (ptr), sizeof(*(ptr))); __tmp; }) - -#define put_unaligned(val, ptr) \ - ({ __typeof__(*(ptr)) __tmp = (val); \ - memcpy((ptr), &__tmp, sizeof(*(ptr))); \ - (void)0; }) - -#define get_block_num(p, i) le32toh(get_unaligned((p) + (i))) -#define put_block_num(p, i, v) put_unaligned(htole32(v), (p) + (i)) - -/* In old version uniqueness field shows key type */ -#define V1_SD_UNIQUENESS 0 -#define V1_INDIRECT_UNIQUENESS 0xfffffffe -#define V1_DIRECT_UNIQUENESS 0xffffffff -#define V1_DIRENTRY_UNIQUENESS 500 -#define V1_ANY_UNIQUENESS 555 - -/* Here are conversion routines */ -static inline int uniqueness2type(uint32_t uniqueness); -static inline uint32_t type2uniqueness(int type); - -static inline int -uniqueness2type(uint32_t uniqueness) -{ - - switch ((int)uniqueness) { - case V1_SD_UNIQUENESS: - return (TYPE_STAT_DATA); - case V1_INDIRECT_UNIQUENESS: - return (TYPE_INDIRECT); - case V1_DIRECT_UNIQUENESS: - return (TYPE_DIRECT); - case V1_DIRENTRY_UNIQUENESS: - return (TYPE_DIRENTRY); - default: - log(LOG_NOTICE, "reiserfs: unknown uniqueness (%u)\n", - uniqueness); - case V1_ANY_UNIQUENESS: - return (TYPE_ANY); - } -} - -static inline uint32_t -type2uniqueness(int type) -{ - - switch (type) { - case TYPE_STAT_DATA: - return (V1_SD_UNIQUENESS); - case TYPE_INDIRECT: - return (V1_INDIRECT_UNIQUENESS); - case TYPE_DIRECT: - return (V1_DIRECT_UNIQUENESS); - case TYPE_DIRENTRY: - return (V1_DIRENTRY_UNIQUENESS); - default: - log(LOG_NOTICE, "reiserfs: unknown type (%u)\n", type); - case TYPE_ANY: - return (V1_ANY_UNIQUENESS); - } -} - -/* - * Key is pointer to on disk key which is stored in le, result is cpu, - * there is no way to get version of object from key, so, provide - * version to these defines. - */ -static inline off_t -le_key_k_offset(int version, const struct key *key) -{ - - return ((version == KEY_FORMAT_3_5) ? - le32toh(key->u.k_offset_v1.k_offset) : - offset_v2_k_offset(&(key->u.k_offset_v2))); -} - -static inline off_t -le_ih_k_offset(const struct item_head *ih) -{ - - return (le_key_k_offset(ih_version(ih), &(ih->ih_key))); -} - -static inline off_t -le_key_k_type(int version, const struct key *key) -{ - - return ((version == KEY_FORMAT_3_5) ? - uniqueness2type(le32toh(key->u.k_offset_v1.k_uniqueness)) : - offset_v2_k_type(&(key->u.k_offset_v2))); -} - -static inline off_t -le_ih_k_type(const struct item_head *ih) -{ - return (le_key_k_type(ih_version(ih), &(ih->ih_key))); -} - -static inline void -set_le_key_k_offset(int version, struct key *key, off_t offset) -{ - - (version == KEY_FORMAT_3_5) ? - (key->u.k_offset_v1.k_offset = htole32(offset)) : - (set_offset_v2_k_offset(&(key->u.k_offset_v2), offset)); -} - -static inline void -set_le_ih_k_offset(struct item_head *ih, off_t offset) -{ - - set_le_key_k_offset(ih_version(ih), &(ih->ih_key), offset); -} - -static inline void -set_le_key_k_type(int version, struct key *key, int type) -{ - - (version == KEY_FORMAT_3_5) ? - (key->u.k_offset_v1.k_uniqueness = - htole32(type2uniqueness(type))) : - (set_offset_v2_k_type(&(key->u.k_offset_v2), type)); -} - -static inline void -set_le_ih_k_type(struct item_head *ih, int type) -{ - - set_le_key_k_type(ih_version(ih), &(ih->ih_key), type); -} - -#define is_direntry_le_key(version, key) \ - (le_key_k_type(version, key) == TYPE_DIRENTRY) -#define is_direct_le_key(version, key) \ - (le_key_k_type(version, key) == TYPE_DIRECT) -#define is_indirect_le_key(version, key) \ - (le_key_k_type(version, key) == TYPE_INDIRECT) -#define is_statdata_le_key(version, key) \ - (le_key_k_type(version, key) == TYPE_STAT_DATA) - -/* Item header has version. */ -#define is_direntry_le_ih(ih) \ - is_direntry_le_key(ih_version(ih), &((ih)->ih_key)) -#define is_direct_le_ih(ih) \ - is_direct_le_key(ih_version(ih), &((ih)->ih_key)) -#define is_indirect_le_ih(ih) \ - is_indirect_le_key(ih_version(ih), &((ih)->ih_key)) -#define is_statdata_le_ih(ih) \ - is_statdata_le_key(ih_version(ih), &((ih)->ih_key)) - -static inline void -set_cpu_key_k_offset(struct cpu_key *key, off_t offset) -{ - - (key->version == KEY_FORMAT_3_5) ? - (key->on_disk_key.u.k_offset_v1.k_offset = offset) : - (key->on_disk_key.u.k_offset_v2.k_offset = offset); -} - -static inline void -set_cpu_key_k_type(struct cpu_key *key, int type) -{ - - (key->version == KEY_FORMAT_3_5) ? - (key->on_disk_key.u.k_offset_v1.k_uniqueness = - type2uniqueness(type)): - (key->on_disk_key.u.k_offset_v2.k_type = type); -} - -#define is_direntry_cpu_key(key) (cpu_key_k_type (key) == TYPE_DIRENTRY) -#define is_direct_cpu_key(key) (cpu_key_k_type (key) == TYPE_DIRECT) -#define is_indirect_cpu_key(key) (cpu_key_k_type (key) == TYPE_INDIRECT) -#define is_statdata_cpu_key(key) (cpu_key_k_type (key) == TYPE_STAT_DATA) - -/* Maximal length of item */ -#define MAX_ITEM_LEN(block_size) (block_size - BLKH_SIZE - IH_SIZE) -#define MIN_ITEM_LEN 1 - -/* Object identifier for root dir */ -#define REISERFS_ROOT_OBJECTID 2 -#define REISERFS_ROOT_PARENT_OBJECTID 1 - -/* key is pointer to cpu key, result is cpu */ -static inline off_t -cpu_key_k_offset(const struct cpu_key *key) -{ - - return ((key->version == KEY_FORMAT_3_5) ? - key->on_disk_key.u.k_offset_v1.k_offset : - key->on_disk_key.u.k_offset_v2.k_offset); -} - -static inline off_t -cpu_key_k_type(const struct cpu_key *key) -{ - - return ((key->version == KEY_FORMAT_3_5) ? - uniqueness2type(key->on_disk_key.u.k_offset_v1.k_uniqueness) : - key->on_disk_key.u.k_offset_v2.k_type); -} - -/* - * Header of a disk block. More precisely, header of a formatted leaf - * or internal node, and not the header of an unformatted node. - */ -struct block_head { - uint16_t blk_level; /* Level of a block in the - tree. */ - uint16_t blk_nr_item; /* Number of keys/items in a - block. */ - uint16_t blk_free_space; /* Block free space in bytes. */ - uint16_t blk_reserved; /* Dump this in v4/planA */ - struct key blk_right_delim_key; /* Kept only for compatibility */ -}; - -#define BLKH_SIZE (sizeof(struct block_head)) -#define blkh_level(p_blkh) (le16toh((p_blkh)->blk_level)) -#define blkh_nr_item(p_blkh) (le16toh((p_blkh)->blk_nr_item)) -#define blkh_free_space(p_blkh) (le16toh((p_blkh)->blk_free_space)) - -#define FREE_LEVEL 0 /* When node gets removed from the tree its - blk_level is set to FREE_LEVEL. It is then - used to see whether the node is still in the - tree */ - -/* Values for blk_level field of the struct block_head */ -#define DISK_LEAF_NODE_LEVEL 1 /* Leaf node level.*/ - -/* - * Given the buffer head of a formatted node, resolve to the block head - * of that node. - */ -#define B_BLK_HEAD(p_s_bp) ((struct block_head *)((p_s_bp)->b_data)) -#define B_NR_ITEMS(p_s_bp) (blkh_nr_item(B_BLK_HEAD(p_s_bp))) -#define B_LEVEL(p_s_bp) (blkh_level(B_BLK_HEAD(p_s_bp))) -#define B_FREE_SPACE(p_s_bp) (blkh_free_space(B_BLK_HEAD(p_s_bp))) - -/* ------------------------------------------------------------------- - * Stat data - * -------------------------------------------------------------------*/ - -/* - * Old stat data is 32 bytes long. We are going to distinguish new one - * by different size. - */ -struct stat_data_v1 { - uint16_t sd_mode; /* File type, permissions */ - uint16_t sd_nlink; /* Number of hard links */ - uint16_t sd_uid; /* Owner */ - uint16_t sd_gid; /* Group */ - uint32_t sd_size; /* File size */ - uint32_t sd_atime; /* Time of last access */ - uint32_t sd_mtime; /* Time file was last modified */ - uint32_t sd_ctime; /* Time inode (stat data) was last changed - (except changes to sd_atime and - sd_mtime) */ - union { - uint32_t sd_rdev; - uint32_t sd_blocks; /* Number of blocks file uses */ - } __packed u; - uint32_t sd_first_direct_byte; /* First byte of file which is - stored in a direct item: - except that if it equals 1 - it is a symlink and if it - equals ~(uint32_t)0 there - is no direct item. The - existence of this field - really grates on me. Let's - replace it with a macro based - on sd_size and our tail - suppression policy. Someday. - -Hans */ -} __packed; - -#define SD_V1_SIZE (sizeof(struct stat_data_v1)) -#define stat_data_v1(ih) (ih_version (ih) == KEY_FORMAT_3_5) -#define sd_v1_mode(sdp) (le16toh((sdp)->sd_mode)) -#define set_sd_v1_mode(sdp, v) ((sdp)->sd_mode = htole16(v)) -#define sd_v1_nlink(sdp) (le16toh((sdp)->sd_nlink)) -#define set_sd_v1_nlink(sdp, v) ((sdp)->sd_nlink = htole16(v)) -#define sd_v1_uid(sdp) (le16toh((sdp)->sd_uid)) -#define set_sd_v1_uid(sdp, v) ((sdp)->sd_uid = htole16(v)) -#define sd_v1_gid(sdp) (le16toh((sdp)->sd_gid)) -#define set_sd_v1_gid(sdp, v) ((sdp)->sd_gid = htole16(v)) -#define sd_v1_size(sdp) (le32toh((sdp)->sd_size)) -#define set_sd_v1_size(sdp, v) ((sdp)->sd_size = htole32(v)) -#define sd_v1_atime(sdp) (le32toh((sdp)->sd_atime)) -#define set_sd_v1_atime(sdp, v) ((sdp)->sd_atime = htole32(v)) -#define sd_v1_mtime(sdp) (le32toh((sdp)->sd_mtime)) -#define set_sd_v1_mtime(sdp, v) ((sdp)->sd_mtime = htole32(v)) -#define sd_v1_ctime(sdp) (le32toh((sdp)->sd_ctime)) -#define set_sd_v1_ctime(sdp, v) ((sdp)->sd_ctime = htole32(v)) -#define sd_v1_rdev(sdp) (le32toh((sdp)->u.sd_rdev)) -#define set_sd_v1_rdev(sdp, v) ((sdp)->u.sd_rdev = htole32(v)) -#define sd_v1_blocks(sdp) (le32toh((sdp)->u.sd_blocks)) -#define set_sd_v1_blocks(sdp, v) ((sdp)->u.sd_blocks = htole32(v)) -#define sd_v1_first_direct_byte(sdp) \ - (le32toh((sdp)->sd_first_direct_byte)) -#define set_sd_v1_first_direct_byte(sdp, v) \ - ((sdp)->sd_first_direct_byte = htole32(v)) - -/* - * We want common flags to have the same values as in ext2, - * so chattr(1) will work without problems - */ -#include <fs/ext2fs/ext2fs.h> -#include <fs/ext2fs/ext2_dinode.h> -#define REISERFS_IMMUTABLE_FL EXT2_IMMUTABLE -#define REISERFS_APPEND_FL EXT2_APPEND -#define REISERFS_SYNC_FL EXT2_SYNC -#define REISERFS_NOATIME_FL EXT2_NOATIME -#define REISERFS_NODUMP_FL EXT2_NODUMP -#define REISERFS_SECRM_FL EXT2_SECRM -#define REISERFS_UNRM_FL EXT2_UNRM -#define REISERFS_COMPR_FL EXT2_COMPR -#define REISERFS_NOTAIL_FL EXT2_NOTAIL_FL - -/* - * Stat Data on disk (reiserfs version of UFS disk inode minus the - * address blocks) - */ -struct stat_data { - uint16_t sd_mode; /* File type, permissions */ - uint16_t sd_attrs; /* Persistent inode flags */ - uint32_t sd_nlink; /* Number of hard links */ - uint64_t sd_size; /* File size */ - uint32_t sd_uid; /* Owner */ - uint32_t sd_gid; /* Group */ - uint32_t sd_atime; /* Time of last access */ - uint32_t sd_mtime; /* Time file was last modified */ - uint32_t sd_ctime; /* Time inode (stat data) was last changed - (except changes to sd_atime and - sd_mtime) */ - uint32_t sd_blocks; - union { - uint32_t sd_rdev; - uint32_t sd_generation; - //uint32_t sd_first_direct_byte; - /* - * First byte of file which is stored in a - * direct item: except that if it equals 1 - * it is a symlink and if it equals - * ~(uint32_t)0 there is no direct item. The - * existence of this field really grates - * on me. Let's replace it with a macro - * based on sd_size and our tail - * suppression policy? - */ - } __packed u; -} __packed; - -/* This is 44 bytes long */ -#define SD_SIZE (sizeof(struct stat_data)) -#define SD_V2_SIZE SD_SIZE -#define stat_data_v2(ih) (ih_version (ih) == KEY_FORMAT_3_6) -#define sd_v2_mode(sdp) (le16toh((sdp)->sd_mode)) -#define set_sd_v2_mode(sdp, v) ((sdp)->sd_mode = htole16(v)) -/* sd_reserved */ -/* set_sd_reserved */ -#define sd_v2_nlink(sdp) (le32toh((sdp)->sd_nlink)) -#define set_sd_v2_nlink(sdp, v) ((sdp)->sd_nlink = htole32(v)) -#define sd_v2_size(sdp) (le64toh((sdp)->sd_size)) -#define set_sd_v2_size(sdp, v) ((sdp)->sd_size = cpu_to_le64(v)) -#define sd_v2_uid(sdp) (le32toh((sdp)->sd_uid)) -#define set_sd_v2_uid(sdp, v) ((sdp)->sd_uid = htole32(v)) -#define sd_v2_gid(sdp) (le32toh((sdp)->sd_gid)) -#define set_sd_v2_gid(sdp, v) ((sdp)->sd_gid = htole32(v)) -#define sd_v2_atime(sdp) (le32toh((sdp)->sd_atime)) -#define set_sd_v2_atime(sdp, v) ((sdp)->sd_atime = htole32(v)) -#define sd_v2_mtime(sdp) (le32toh((sdp)->sd_mtime)) -#define set_sd_v2_mtime(sdp, v) ((sdp)->sd_mtime = htole32(v)) -#define sd_v2_ctime(sdp) (le32toh((sdp)->sd_ctime)) -#define set_sd_v2_ctime(sdp, v) ((sdp)->sd_ctime = htole32(v)) -#define sd_v2_blocks(sdp) (le32toh((sdp)->sd_blocks)) -#define set_sd_v2_blocks(sdp, v) ((sdp)->sd_blocks = htole32(v)) -#define sd_v2_rdev(sdp) (le32toh((sdp)->u.sd_rdev)) -#define set_sd_v2_rdev(sdp, v) ((sdp)->u.sd_rdev = htole32(v)) -#define sd_v2_generation(sdp) (le32toh((sdp)->u.sd_generation)) -#define set_sd_v2_generation(sdp, v) ((sdp)->u.sd_generation = htole32(v)) -#define sd_v2_attrs(sdp) (le16toh((sdp)->sd_attrs)) -#define set_sd_v2_attrs(sdp, v) ((sdp)->sd_attrs = htole16(v)) - -/* ------------------------------------------------------------------- - * Directory structure - * -------------------------------------------------------------------*/ - -#define SD_OFFSET 0 -#define SD_UNIQUENESS 0 -#define DOT_OFFSET 1 -#define DOT_DOT_OFFSET 2 -#define DIRENTRY_UNIQUENESS 500 - -#define FIRST_ITEM_OFFSET 1 - -struct reiserfs_de_head { - uint32_t deh_offset; /* Third component of the directory - entry key */ - uint32_t deh_dir_id; /* Objectid of the parent directory of - the object, that is referenced by - directory entry */ - uint32_t deh_objectid; /* Objectid of the object, that is - referenced by directory entry */ - uint16_t deh_location; /* Offset of name in the whole item */ - uint16_t deh_state; /* Whether 1) entry contains stat data - (for future), and 2) whether entry - is hidden (unlinked) */ -} __packed; - -#define DEH_SIZE sizeof(struct reiserfs_de_head) -#define deh_offset(p_deh) (le32toh((p_deh)->deh_offset)) -#define deh_dir_id(p_deh) (le32toh((p_deh)->deh_dir_id)) -#define deh_objectid(p_deh) (le32toh((p_deh)->deh_objectid)) -#define deh_location(p_deh) (le16toh((p_deh)->deh_location)) -#define deh_state(p_deh) (le16toh((p_deh)->deh_state)) - -#define put_deh_offset(p_deh, v) ((p_deh)->deh_offset = htole32((v))) -#define put_deh_dir_id(p_deh, v) ((p_deh)->deh_dir_id = htole32((v))) -#define put_deh_objectid(p_deh, v) ((p_deh)->deh_objectid = htole32((v))) -#define put_deh_location(p_deh, v) ((p_deh)->deh_location = htole16((v))) -#define put_deh_state(p_deh, v) ((p_deh)->deh_state = htole16((v))) - -/* Empty directory contains two entries "." and ".." and their headers */ -#define EMPTY_DIR_SIZE \ - (DEH_SIZE * 2 + ROUND_UP(strlen(".")) + ROUND_UP(strlen(".."))) - -/* Old format directories have this size when empty */ -#define EMPTY_DIR_SIZE_V1 (DEH_SIZE * 2 + 3) - -#define DEH_Statdata 0 /* Not used now */ -#define DEH_Visible 2 - -/* Macro to map Linux' *_bit function to bitstring.h macros */ -#define set_bit(bit, name) bit_set((bitstr_t *)name, bit) -#define clear_bit(bit, name) bit_clear((bitstr_t *)name, bit) -#define test_bit(bit, name) bit_test((bitstr_t *)name, bit) - -#define set_bit_unaligned(bit, name) set_bit(bit, name) -#define clear_bit_unaligned(bit, name) clear_bit(bit, name) -#define test_bit_unaligned(bit, name) test_bit(bit, name) - -#define mark_de_with_sd(deh) \ - set_bit_unaligned(DEH_Statdata, &((deh)->deh_state)) -#define mark_de_without_sd(deh) \ - clear_bit_unaligned(DEH_Statdata, &((deh)->deh_state)) -#define mark_de_visible(deh) \ - set_bit_unaligned (DEH_Visible, &((deh)->deh_state)) -#define mark_de_hidden(deh) \ - clear_bit_unaligned (DEH_Visible, &((deh)->deh_state)) - -#define de_with_sd(deh) \ - test_bit_unaligned(DEH_Statdata, &((deh)->deh_state)) -#define de_visible(deh) \ - test_bit_unaligned(DEH_Visible, &((deh)->deh_state)) -#define de_hidden(deh) \ - !test_bit_unaligned(DEH_Visible, &((deh)->deh_state)) - -/* Two entries per block (at least) */ -#define REISERFS_MAX_NAME(block_size) 255 - -/* - * This structure is used for operations on directory entries. It is not - * a disk structure. When reiserfs_find_entry or search_by_entry_key - * find directory entry, they return filled reiserfs_dir_entry structure - */ -struct reiserfs_dir_entry { - struct buf *de_bp; - int de_item_num; - struct item_head *de_ih; - int de_entry_num; - struct reiserfs_de_head *de_deh; - int de_entrylen; - int de_namelen; - char *de_name; - char *de_gen_number_bit_string; - - uint32_t de_dir_id; - uint32_t de_objectid; - - struct cpu_key de_entry_key; -}; - -/* Pointer to file name, stored in entry */ -#define B_I_DEH_ENTRY_FILE_NAME(bp, ih, deh) \ - (B_I_PITEM(bp, ih) + deh_location(deh)) - -/* Length of name */ -#define I_DEH_N_ENTRY_FILE_NAME_LENGTH(ih, deh, entry_num) \ - (I_DEH_N_ENTRY_LENGTH(ih, deh, entry_num) - \ - (de_with_sd(deh) ? SD_SIZE : 0)) - -/* Hash value occupies bits from 7 up to 30 */ -#define GET_HASH_VALUE(offset) ((offset) & 0x7fffff80LL) - -/* Generation number occupies 7 bits starting from 0 up to 6 */ -#define GET_GENERATION_NUMBER(offset) ((offset) & 0x7fLL) -#define MAX_GENERATION_NUMBER 127 - -/* Get item body */ -#define B_I_PITEM(bp, ih) ((bp)->b_data + ih_location(ih)) -#define B_I_DEH(bp, ih) ((struct reiserfs_de_head *)(B_I_PITEM(bp, ih))) - -/* - * Length of the directory entry in directory item. This define - * calculates length of i-th directory entry using directory entry - * locations from dir entry head. When it calculates length of 0-th - * directory entry, it uses length of whole item in place of entry - * location of the non-existent following entry in the calculation. See - * picture above. - */ -static inline int -entry_length (const struct buf *bp, const struct item_head *ih, - int pos_in_item) -{ - struct reiserfs_de_head *deh; - - deh = B_I_DEH(bp, ih) + pos_in_item; - if (pos_in_item) - return (deh_location(deh - 1) - deh_location(deh)); - - return (ih_item_len(ih) - deh_location(deh)); -} - -/* - * Number of entries in the directory item, depends on ENTRY_COUNT - * being at the start of directory dynamic data. - */ -#define I_ENTRY_COUNT(ih) (ih_entry_count((ih))) - -/* ------------------------------------------------------------------- - * Disk child - * -------------------------------------------------------------------*/ - -/* - * Disk child pointer: The pointer from an internal node of the tree - * to a node that is on disk. - */ -struct disk_child { - uint32_t dc_block_number; /* Disk child's block number. */ - uint16_t dc_size; /* Disk child's used space. */ - uint16_t dc_reserved; -}; - -#define DC_SIZE (sizeof(struct disk_child)) -#define dc_block_number(dc_p) (le32toh((dc_p)->dc_block_number)) -#define dc_size(dc_p) (le16toh((dc_p)->dc_size)) -#define put_dc_block_number(dc_p, val) \ - do { (dc_p)->dc_block_number = htole32(val); } while (0) -#define put_dc_size(dc_p, val) \ - do { (dc_p)->dc_size = htole16(val); } while (0) - -/* Get disk child by buffer header and position in the tree node. */ -#define B_N_CHILD(p_s_bp, n_pos) \ - ((struct disk_child *)((p_s_bp)->b_data + BLKH_SIZE + \ - B_NR_ITEMS(p_s_bp) * KEY_SIZE + \ - DC_SIZE * (n_pos))) - -/* Get disk child number by buffer header and position in the tree node. */ -#define B_N_CHILD_NUM(p_s_bp, n_pos) \ - (dc_block_number(B_N_CHILD(p_s_bp, n_pos))) -#define PUT_B_N_CHILD_NUM(p_s_bp, n_pos, val) \ - (put_dc_block_number(B_N_CHILD(p_s_bp, n_pos), val)) - -/* ------------------------------------------------------------------- - * Path structures and defines - * -------------------------------------------------------------------*/ - -struct path_element { - struct buf *pe_buffer; /* Pointer to the buffer at the path in - the tree. */ - int pe_position; /* Position in the tree node which is - placed in the buffer above. */ -}; - -#define MAX_HEIGHT 5 /* Maximal height of a tree. Don't - change this without changing - JOURNAL_PER_BALANCE_CNT */ -#define EXTENDED_MAX_HEIGHT 7 /* Must be equals MAX_HEIGHT + - FIRST_PATH_ELEMENT_OFFSET */ -#define FIRST_PATH_ELEMENT_OFFSET 2 /* Must be equal to at least 2. */ -#define ILLEGAL_PATH_ELEMENT_OFFSET 1 /* Must be equal to - FIRST_PATH_ELEMENT_OFFSET - 1 */ -#define MAX_FEB_SIZE 6 /* This MUST be MAX_HEIGHT + 1. - See about FEB below */ - -struct path { - /* Length of the array below. */ - int path_length; - /* Array of the path element */ - struct path_element path_elements[EXTENDED_MAX_HEIGHT]; - int pos_in_item; -}; - -#define pos_in_item(path) ((path)->pos_in_item) - -#ifdef __amd64__ -/* To workaround a bug in gcc. He generates a call to memset() which - * is a inline function; this causes a compile time error. */ -#define INITIALIZE_PATH(var) \ - struct path var; \ - bzero(&var, sizeof(var)); \ - var.path_length = ILLEGAL_PATH_ELEMENT_OFFSET; -#else -#define INITIALIZE_PATH(var) \ - struct path var = { ILLEGAL_PATH_ELEMENT_OFFSET, } -#endif - -/* Get path element by path and path position. */ -#define PATH_OFFSET_PELEMENT(p_s_path, n_offset) \ - ((p_s_path)->path_elements + (n_offset)) - -/* Get buffer header at the path by path and path position. */ -#define PATH_OFFSET_PBUFFER(p_s_path, n_offset) \ - (PATH_OFFSET_PELEMENT(p_s_path, n_offset)->pe_buffer) - -/* Get position in the element at the path by path and path position. */ -#define PATH_OFFSET_POSITION(p_s_path, n_offset) \ - (PATH_OFFSET_PELEMENT(p_s_path, n_offset)->pe_position) - -#define PATH_PLAST_BUFFER(p_s_path) \ - (PATH_OFFSET_PBUFFER((p_s_path), (p_s_path)->path_length)) - -#define PATH_LAST_POSITION(p_s_path) \ - (PATH_OFFSET_POSITION((p_s_path), (p_s_path)->path_length)) - -#define PATH_PITEM_HEAD(p_s_path) \ - B_N_PITEM_HEAD(PATH_PLAST_BUFFER(p_s_path), PATH_LAST_POSITION(p_s_path)) - -#define get_last_bp(path) PATH_PLAST_BUFFER(path) -#define get_ih(path) PATH_PITEM_HEAD(path) - -/* ------------------------------------------------------------------- - * Misc. - * -------------------------------------------------------------------*/ - -/* Size of pointer to the unformatted node. */ -#define UNFM_P_SIZE (sizeof(unp_t)) -#define UNFM_P_SHIFT 2 - -/* In in-core inode key is stored on le form */ -#define INODE_PKEY(ip) ((struct key *)(REISERFS_I(ip)->i_key)) - -#define MAX_UL_INT 0xffffffff -#define MAX_INT 0x7ffffff -#define MAX_US_INT 0xffff - -/* The purpose is to detect overflow of an unsigned short */ -#define REISERFS_LINK_MAX (MAX_US_INT - 1000) - -#define fs_generation(sbi) (REISERFS_SB(sbi)->s_generation_counter) -#define get_generation(sbi) (fs_generation(sbi)) - -#define __fs_changed(gen, sbi) (gen != get_generation (sbi)) -/*#define fs_changed(gen, sbi) ({ cond_resched(); \ - __fs_changed(gen, sbi); })*/ -#define fs_changed(gen, sbi) (__fs_changed(gen, sbi)) - -/* ------------------------------------------------------------------- - * Fixate node - * -------------------------------------------------------------------*/ - -/* - * To make any changes in the tree we always first find node, that - * contains item to be changed/deleted or place to insert a new item. - * We call this node S. To do balancing we need to decide what we will - * shift to left/right neighbor, or to a new node, where new item will - * be etc. To make this analysis simpler we build virtual node. Virtual - * node is an array of items, that will replace items of node S. (For - * instance if we are going to delete an item, virtual node does not - * contain it). Virtual node keeps information about item sizes and - * types, mergeability of first and last items, sizes of all entries in - * directory item. We use this array of items when calculating what we - * can shift to neighbors and how many nodes we have to have if we do - * not any shiftings, if we shift to left/right neighbor or to both. - */ -struct virtual_item { - int vi_index; /* Index in the array of item - operations */ - unsigned short vi_type; /* Left/right mergeability */ - unsigned short vi_item_len; /* Length of item that it will - have after balancing */ - struct item_head *vi_ih; - const char *vi_item; /* Body of item (old or new) */ - const void *vi_new_data; /* 0 always but paste mode */ - void *vi_uarea; /* Item specific area */ -}; - -struct virtual_node { - char *vn_free_ptr; /* This is a pointer to the free space - in the buffer */ - unsigned short vn_nr_item; /* Number of items in virtual node */ - short vn_size; /* Size of node , that node would have - if it has unlimited size and no - balancing is performed */ - short vn_mode; /* Mode of balancing (paste, insert, - delete, cut) */ - short vn_affected_item_num; - short vn_pos_in_item; - struct item_head *vn_ins_ih; /* Item header of inserted item, 0 for - other modes */ - const void *vn_data; - struct virtual_item *vn_vi; /* Array of items (including a new one, - excluding item to be deleted) */ -}; - -/* Used by directory items when creating virtual nodes */ -struct direntry_uarea { - int flags; - uint16_t entry_count; - uint16_t entry_sizes[1]; -} __packed; - -/* ------------------------------------------------------------------- - * Tree balance - * -------------------------------------------------------------------*/ - -struct reiserfs_iget_args { - uint32_t objectid; - uint32_t dirid; -}; - -struct item_operations { - int (*bytes_number)(struct item_head * ih, int block_size); - void (*decrement_key)(struct cpu_key *); - int (*is_left_mergeable)(struct key * ih, unsigned long bsize); - void (*print_item)(struct item_head *, char * item); - void (*check_item)(struct item_head *, char * item); - - int (*create_vi)(struct virtual_node * vn, - struct virtual_item * vi, int is_affected, int insert_size); - int (*check_left)(struct virtual_item * vi, int free, - int start_skip, int end_skip); - int (*check_right)(struct virtual_item * vi, int free); - int (*part_size)(struct virtual_item * vi, int from, int to); - int (*unit_num)(struct virtual_item * vi); - void (*print_vi)(struct virtual_item * vi); -}; - -extern struct item_operations *item_ops[TYPE_ANY + 1]; - -#define op_bytes_number(ih, bsize) \ - item_ops[le_ih_k_type(ih)]->bytes_number(ih, bsize) - -#define COMP_KEYS comp_keys -#define COMP_SHORT_KEYS comp_short_keys - -/* Get the item header */ -#define B_N_PITEM_HEAD(bp, item_num) \ - ((struct item_head *)((bp)->b_data + BLKH_SIZE) + (item_num)) - -/* Get key */ -#define B_N_PDELIM_KEY(bp, item_num) \ - ((struct key *)((bp)->b_data + BLKH_SIZE) + (item_num)) - -/* ------------------------------------------------------------------- - * Function declarations - * -------------------------------------------------------------------*/ - -/* reiserfs_stree.c */ -int B_IS_IN_TREE(const struct buf *p_s_bp); - -extern void copy_item_head(struct item_head * p_v_to, - const struct item_head * p_v_from); - -extern int comp_keys(const struct key *le_key, - const struct cpu_key *cpu_key); -extern int comp_short_keys(const struct key *le_key, - const struct cpu_key *cpu_key); - -extern int comp_le_keys(const struct key *, const struct key *); - -static inline int -le_key_version(const struct key *key) -{ - int type; - - type = offset_v2_k_type(&(key->u.k_offset_v2)); - if (type != TYPE_DIRECT && type != TYPE_INDIRECT && - type != TYPE_DIRENTRY) - return (KEY_FORMAT_3_5); - - return (KEY_FORMAT_3_6); -} - -static inline void -copy_key(struct key *to, const struct key *from) -{ - - memcpy(to, from, KEY_SIZE); -} - -const struct key *get_lkey(const struct path *p_s_chk_path, - const struct reiserfs_sb_info *p_s_sbi); -const struct key *get_rkey(const struct path *p_s_chk_path, - const struct reiserfs_sb_info *p_s_sbi); -int bin_search(const void * p_v_key, const void * p_v_base, - int p_n_num, int p_n_width, int * p_n_pos); - -void pathrelse(struct path *p_s_search_path); -int reiserfs_check_path(struct path *p); - -int search_by_key(struct reiserfs_sb_info *p_s_sbi, - const struct cpu_key *p_s_key, - struct path *p_s_search_path, - int n_stop_level); -#define search_item(sbi, key, path) \ - search_by_key(sbi, key, path, DISK_LEAF_NODE_LEVEL) -int search_for_position_by_key(struct reiserfs_sb_info *p_s_sbi, - const struct cpu_key *p_s_cpu_key, - struct path *p_s_search_path); -void decrement_counters_in_path(struct path *p_s_search_path); - -/* reiserfs_inode.c */ -vop_read_t reiserfs_read; -vop_inactive_t reiserfs_inactive; -vop_reclaim_t reiserfs_reclaim; - -int reiserfs_get_block(struct reiserfs_node *ip, long block, - off_t offset, struct uio *uio); - -void make_cpu_key(struct cpu_key *cpu_key, struct reiserfs_node *ip, - off_t offset, int type, int key_length); - -void reiserfs_read_locked_inode(struct reiserfs_node *ip, - struct reiserfs_iget_args *args); -int reiserfs_iget(struct mount *mp, const struct cpu_key *key, - struct vnode **vpp, struct thread *td); - -void sd_attrs_to_i_attrs(uint16_t sd_attrs, struct reiserfs_node *ip); -void i_attrs_to_sd_attrs(struct reiserfs_node *ip, uint16_t *sd_attrs); - -/* reiserfs_namei.c */ -vop_readdir_t reiserfs_readdir; -vop_cachedlookup_t reiserfs_lookup; - -void set_de_name_and_namelen(struct reiserfs_dir_entry * de); -int search_by_entry_key(struct reiserfs_sb_info *sbi, - const struct cpu_key *key, struct path *path, - struct reiserfs_dir_entry *de); - -/* reiserfs_prints.c */ -char *reiserfs_hashname(int code); -void reiserfs_dump_buffer(caddr_t buf, off_t len); - -#if defined(REISERFS_DEBUG) -#define reiserfs_log(lvl, fmt, ...) \ - log(lvl, "ReiserFS/%s: " fmt, __func__, ## __VA_ARGS__) -#elif defined (REISERFS_DEBUG_CONS) -#define reiserfs_log(lvl, fmt, ...) \ - printf("%s:%d: " fmt, __func__, __LINE__, ## __VA_ARGS__) -#else -#define reiserfs_log(lvl, fmt, ...) -#endif - -#define reiserfs_log_0(lvl, fmt, ...) \ - printf("%s:%d: " fmt, __func__, __LINE__, ## __VA_ARGS__) - -/* reiserfs_hashes.c */ -uint32_t keyed_hash(const signed char *msg, int len); -uint32_t yura_hash(const signed char *msg, int len); -uint32_t r5_hash(const signed char *msg, int len); - -#define reiserfs_test_le_bit test_bit - -#endif /* !defined _GNU_REISERFS_REISERFS_FS_H */ diff --git a/sys/gnu/fs/reiserfs/reiserfs_fs_i.h b/sys/gnu/fs/reiserfs/reiserfs_fs_i.h deleted file mode 100644 index e269d92..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_fs_i.h +++ /dev/null @@ -1,90 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#ifndef _GNU_REISERFS_REISERFS_FS_I_H -#define _GNU_REISERFS_REISERFS_FS_I_H - -#include <sys/queue.h> - -/* Bitmasks for i_flags field in reiserfs-specific part of inode */ -typedef enum { - /* - * This says what format of key do all items (but stat data) of - * an object have. If this is set, that format is 3.6 otherwise - * - 3.5 - */ - i_item_key_version_mask = 0x0001, - /* If this is unset, object has 3.5 stat data, otherwise, it has - * 3.6 stat data with 64bit size, 32bit nlink etc. */ - i_stat_data_version_mask = 0x0002, - /* File might need tail packing on close */ - i_pack_on_close_mask = 0x0004, - /* Don't pack tail of file */ - i_nopack_mask = 0x0008, - /* If those is set, "safe link" was created for this file during - * truncate or unlink. Safe link is used to avoid leakage of disk - * space on crash with some files open, but unlinked. */ - i_link_saved_unlink_mask = 0x0010, - i_link_saved_truncate_mask = 0x0020, - i_priv_object = 0x0080, - i_has_xattr_dir = 0x0100, -} reiserfs_inode_flags; - -struct reiserfs_node { - struct vnode *i_vnode; - struct vnode *i_devvp; - struct cdev *i_dev; - ino_t i_number; - - ino_t i_ino; - - struct reiserfs_sb_info *i_reiserfs; - - uint32_t i_flag; /* Flags, see below */ - uint32_t i_key[4]; /* Key is still 4 32 bit - integers */ - uint32_t i_flags; /* Transient inode flags that - are never stored on disk. - Bitmasks for this field - are defined above. */ - uint32_t i_first_direct_byte; /* Offset of first byte stored - in direct item. */ - uint32_t i_attrs; /* Copy of persistent inode - flags read from sd_attrs. */ - - uint16_t i_mode; /* IFMT, permissions. */ - int16_t i_nlink; /* File link count. */ - uint64_t i_size; /* File byte count. */ - uint32_t i_bytes; - uid_t i_uid; /* File owner. */ - gid_t i_gid; /* File group. */ - struct timespec i_atime; /* Last access time. */ - struct timespec i_mtime; /* Last modified time. */ - struct timespec i_ctime; /* Last inode change time. */ - - uint32_t i_blocks; - uint32_t i_generation; -}; - -#define VTOI(vp) ((struct reiserfs_node *)(vp)->v_data) -#define ITOV(ip) ((ip)->i_vnode) - -/* These flags are kept in i_flag. */ -#define IN_HASHED 0x0020 /* Inode is on hash list */ - -/* This overlays the fid structure (see mount.h) */ -struct rfid { - uint16_t rfid_len; /* Length of structure */ - uint16_t rfid_pad; /* Force 32-bit alignment */ - ino_t rfid_dirid; /* File key */ - ino_t rfid_objectid; - uint32_t rfid_gen; /* Generation number */ -}; - -#endif /* !defined _GNU_REISERFS_REISERFS_FS_I_H */ diff --git a/sys/gnu/fs/reiserfs/reiserfs_fs_sb.h b/sys/gnu/fs/reiserfs/reiserfs_fs_sb.h deleted file mode 100644 index 982729b..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_fs_sb.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#ifndef _GNU_REISERFS_REISERFS_FS_SB_H -#define _GNU_REISERFS_REISERFS_FS_SB_H - -typedef uint32_t (*hashf_t)(const signed char *, int); - -#define sb_block_count(sbp) (le32toh((sbp)->s_v1.s_block_count)) -#define set_sb_block_count(sbp,v) ((sbp)->s_v1.s_block_count = htole32(v)) -#define sb_free_blocks(sbp) (le32toh((sbp)->s_v1.s_free_blocks)) -#define set_sb_free_blocks(sbp,v) ((sbp)->s_v1.s_free_blocks = htole32(v)) -#define sb_root_block(sbp) (le32toh((sbp)->s_v1.s_root_block)) - -/* Bitmaps */ -struct reiserfs_bitmap_info { - uint16_t first_zero_hint; - uint16_t free_count; - //struct buf *bp; /* The actual bitmap */ - caddr_t bp_data; /* The actual bitmap */ -}; - -/* ReiserFS union of in-core super block data */ -struct reiserfs_sb_info { - struct reiserfs_super_block *s_rs; - struct reiserfs_bitmap_info *s_ap_bitmap; - struct vnode *s_devvp; - - unsigned short s_mount_state; - - hashf_t s_hash_function; /* Pointer to function which - is used to sort names in - directory. Set on mount */ - unsigned long s_mount_opt; /* ReiserFS's mount options - are set here */ - int s_generation_counter; /* Increased by one every - time the tree gets - re-balanced */ - unsigned long s_properties; /* File system properties. - Currently holds on-disk - FS format */ - uint16_t s_blocksize; - uint16_t s_blocksize_bits; - char s_rd_only; /* Is it read-only ? */ - int s_is_unlinked_ok; -}; - -#define sb_version(sbi) (le16toh((sbi)->s_v1.s_version)) -#define set_sb_version(sbi, v) ((sbi)->s_v1.s_version = htole16(v)) - -#define sb_blocksize(sbi) (le16toh((sbi)->s_v1.s_blocksize)) -#define set_sb_blocksize(sbi, v) ((sbi)->s_v1.s_blocksize = htole16(v)) - -#define sb_hash_function_code(sbi) \ - (le32toh((sbi)->s_v1.s_hash_function_code)) -#define set_sb_hash_function_code(sbi, v) \ - ((sbi)->s_v1.s_hash_function_code = htole32(v)) - -#define sb_bmap_nr(sbi) (le16toh((sbi)->s_v1.s_bmap_nr)) -#define set_sb_bmap_nr(sbi, v) ((sbi)->s_v1.s_bmap_nr = htole16(v)) - -/* Definitions of reiserfs on-disk properties: */ -#define REISERFS_3_5 0 -#define REISERFS_3_6 1 - -enum reiserfs_mount_options { - /* Mount options */ - REISERFS_LARGETAIL, /* Large tails will be created in a session */ - REISERFS_SMALLTAIL, /* Small (for files less than block size) tails - will be created in a session */ - REPLAYONLY, /* Replay journal and return 0. Use by fsck */ - REISERFS_CONVERT, /* -o conv: causes conversion of old format super - block to the new format. If not specified - - old partition will be dealt with in a manner - of 3.5.x */ - - /* - * -o hash={tea, rupasov, r5, detect} is meant for properly mounting - * reiserfs disks from 3.5.19 or earlier. 99% of the time, this option - * is not required. If the normal autodection code can't determine - * which hash to use (because both hases had the same value for a - * file) use this option to force a specific hash. It won't allow you - * to override the existing hash on the FS, so if you have a tea hash - * disk, and mount with -o hash=rupasov, the mount will fail. - */ - FORCE_TEA_HASH, /* try to force tea hash on mount */ - FORCE_RUPASOV_HASH, /* try to force rupasov hash on mount */ - FORCE_R5_HASH, /* try to force rupasov hash on mount */ - FORCE_HASH_DETECT, /* try to detect hash function on mount */ - - REISERFS_DATA_LOG, - REISERFS_DATA_ORDERED, - REISERFS_DATA_WRITEBACK, - - /* - * used for testing experimental features, makes benchmarking new - * features with and without more convenient, should never be used by - * users in any code shipped to users (ideally) - */ - - REISERFS_NO_BORDER, - REISERFS_NO_UNHASHED_RELOCATION, - REISERFS_HASHED_RELOCATION, - REISERFS_ATTRS, - REISERFS_XATTRS, - REISERFS_XATTRS_USER, - REISERFS_POSIXACL, - - REISERFS_TEST1, - REISERFS_TEST2, - REISERFS_TEST3, - REISERFS_TEST4, -}; - -#define reiserfs_r5_hash(sbi) \ - (REISERFS_SB(sbi)->s_mount_opt & (1 << FORCE_R5_HASH)) -#define reiserfs_rupasov_hash(sbi) \ - (REISERFS_SB(sbi)->s_mount_opt & (1 << FORCE_RUPASOV_HASH)) -#define reiserfs_tea_hash(sbi) \ - (REISERFS_SB(sbi)->s_mount_opt & (1 << FORCE_TEA_HASH)) -#define reiserfs_hash_detect(sbi) \ - (REISERFS_SB(sbi)->s_mount_opt & (1 << FORCE_HASH_DETECT)) - -#define reiserfs_attrs(sbi) \ - (REISERFS_SB(sbi)->s_mount_opt & (1 << REISERFS_ATTRS)) - -#define reiserfs_data_log(sbi) \ - (REISERFS_SB(sbi)->s_mount_opt & (1 << REISERFS_DATA_LOG)) -#define reiserfs_data_ordered(sbi) \ - (REISERFS_SB(sbi)->s_mount_opt & (1 << REISERFS_DATA_ORDERED)) -#define reiserfs_data_writeback(sbi) \ - (REISERFS_SB(sbi)->s_mount_opt & (1 << REISERFS_DATA_WRITEBACK)) - -#define SB_BUFFER_WITH_SB(sbi) (REISERFS_SB(sbi)->s_sbh) -#define SB_AP_BITMAP(sbi) (REISERFS_SB(sbi)->s_ap_bitmap) - -#endif /* !defined _GNU_REISERFS_REISERFS_FS_SB_H */ diff --git a/sys/gnu/fs/reiserfs/reiserfs_hashes.c b/sys/gnu/fs/reiserfs/reiserfs_hashes.c deleted file mode 100644 index 3545dbf..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_hashes.c +++ /dev/null @@ -1,217 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#include <gnu/fs/reiserfs/reiserfs_fs.h> - -/* - * Keyed 32-bit hash function using TEA in a Davis-Meyer function - * H0 = Key - * Hi = E Mi(Hi-1) + Hi-1 - * - * (see Applied Cryptography, 2nd edition, p448). - * - * Jeremy Fitzhardinge <jeremy@zip.com.au> 1998 - * - * Jeremy has agreed to the contents of README. -Hans - * Yura's function is added (04/07/2000) - */ - -/* - * keyed_hash - * yura_hash - * r5_hash - */ - -#define DELTA 0x9E3779B9 -#define FULLROUNDS 10 /* 32 is overkill, 16 is strong crypto */ -#define PARTROUNDS 6 /* 6 gets complete mixing */ - -/* a, b, c, d - data; h0, h1 - accumulated hash */ -#define TEACORE(rounds) \ - do { \ - int n; \ - uint32_t b0, b1; \ - uint32_t sum; \ - \ - n = rounds; \ - sum = 0; \ - b0 = h0; \ - b1 = h1; \ - \ - do { \ - sum += DELTA; \ - b0 += ((b1 << 4) + a) ^ (b1+sum) ^ ((b1 >> 5) + b); \ - b1 += ((b0 << 4) + c) ^ (b0+sum) ^ ((b0 >> 5) + d); \ - } while (--n); \ - \ - h0 += b0; \ - h1 += b1; \ - } while (0) - -uint32_t -keyed_hash(const signed char *msg, int len) -{ - uint32_t k[] = { 0x9464a485, 0x542e1a94, 0x3e846bff, 0xb75bcfc3 }; - - uint32_t h0, h1; - uint32_t a, b, c, d; - uint32_t pad; - int i; - - h0 = k[0]; - h1 = k[1]; - - pad = (uint32_t)len | ((uint32_t)len << 8); - pad |= pad << 16; - - while(len >= 16) { - a = (uint32_t)msg[ 0] | - (uint32_t)msg[ 1] << 8 | - (uint32_t)msg[ 2] << 16 | - (uint32_t)msg[ 3] << 24; - b = (uint32_t)msg[ 4] | - (uint32_t)msg[ 5] << 8 | - (uint32_t)msg[ 6] << 16 | - (uint32_t)msg[ 7] << 24; - c = (uint32_t)msg[ 8] | - (uint32_t)msg[ 9] << 8 | - (uint32_t)msg[10] << 16 | - (uint32_t)msg[11] << 24; - d = (uint32_t)msg[12] | - (uint32_t)msg[13] << 8 | - (uint32_t)msg[14] << 16 | - (uint32_t)msg[15] << 24; - - TEACORE(PARTROUNDS); - - len -= 16; - msg += 16; - } - - if (len >= 12) { - a = (uint32_t)msg[ 0] | - (uint32_t)msg[ 1] << 8 | - (uint32_t)msg[ 2] << 16 | - (uint32_t)msg[ 3] << 24; - b = (uint32_t)msg[ 4] | - (uint32_t)msg[ 5] << 8 | - (uint32_t)msg[ 6] << 16 | - (uint32_t)msg[ 7] << 24; - c = (uint32_t)msg[ 8] | - (uint32_t)msg[ 9] << 8 | - (uint32_t)msg[10] << 16 | - (uint32_t)msg[11] << 24; - - d = pad; - for(i = 12; i < len; i++) { - d <<= 8; - d |= msg[i]; - } - } else if (len >= 8) { - a = (uint32_t)msg[ 0] | - (uint32_t)msg[ 1] << 8 | - (uint32_t)msg[ 2] << 16 | - (uint32_t)msg[ 3] << 24; - b = (uint32_t)msg[ 4] | - (uint32_t)msg[ 5] << 8 | - (uint32_t)msg[ 6] << 16 | - (uint32_t)msg[ 7] << 24; - - c = d = pad; - for(i = 8; i < len; i++) { - c <<= 8; - c |= msg[i]; - } - } else if (len >= 4) { - a = (uint32_t)msg[ 0] | - (uint32_t)msg[ 1] << 8 | - (uint32_t)msg[ 2] << 16 | - (uint32_t)msg[ 3] << 24; - - b = c = d = pad; - for(i = 4; i < len; i++) { - b <<= 8; - b |= msg[i]; - } - } else { - a = b = c = d = pad; - for(i = 0; i < len; i++) { - a <<= 8; - a |= msg[i]; - } - } - - TEACORE(FULLROUNDS); - - /* return 0; */ - return (h0 ^ h1); -} - -/* - * What follows in this file is copyright 2000 by Hans Reiser, and the - * licensing of what follows is governed by README - * */ -uint32_t -yura_hash(const signed char *msg, int len) -{ - int i; - int j, pow; - uint32_t a, c; - - for (pow = 1, i = 1; i < len; i++) - pow = pow * 10; - - if (len == 1) - a = msg[0] - 48; - else - a = (msg[0] - 48) * pow; - - for (i = 1; i < len; i++) { - c = msg[i] - 48; - for (pow = 1, j = i; j < len - 1; j++) - pow = pow * 10; - a = a + c * pow; - } - - for (; i < 40; i++) { - c = '0' - 48; - for (pow = 1, j = i; j < len - 1; j++) - pow = pow * 10; - a = a + c * pow; - } - - for (; i < 256; i++) { - c = i; - for (pow = 1, j = i; j < len - 1; j++) - pow = pow * 10; - a = a + c * pow; - } - - a = a << 7; - return (a); -} - -uint32_t -r5_hash(const signed char *msg, int len) -{ - uint32_t a; - const signed char *start; - - a = 0; - start = msg; - - while (*msg && msg < start + len) { - a += *msg << 4; - a += *msg >> 4; - a *= 11; - msg++; - } - - return (a); -} diff --git a/sys/gnu/fs/reiserfs/reiserfs_inode.c b/sys/gnu/fs/reiserfs/reiserfs_inode.c deleted file mode 100644 index 1c5207c..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_inode.c +++ /dev/null @@ -1,912 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <dumbbell@FreeBSD.org> - * - * $FreeBSD$ - */ - -#include <gnu/fs/reiserfs/reiserfs_fs.h> - -static b_strategy_t reiserfs_bufstrategy; - -/* - * Buffer operations for ReiserFS vnodes. - * We punt on VOP_BMAP, so we need to do strategy on the file's vnode - * rather than the underlying device's. - */ -static struct buf_ops reiserfs_vnbufops = { - .bop_name = "ReiserFS", - .bop_strategy = reiserfs_bufstrategy, -}; - -/* Default io size devuned in super.c */ -extern int reiserfs_default_io_size; -void inode_set_bytes(struct reiserfs_node *ip, off_t bytes); - -/* Args for the create parameter of reiserfs_get_block */ -#define GET_BLOCK_NO_CREATE 0 /* Don't create new blocks or convert - tails */ -#define GET_BLOCK_CREATE 1 /* Add anything you need to find block */ -#define GET_BLOCK_NO_HOLE 2 /* Return ENOENT for file holes */ -#define GET_BLOCK_READ_DIRECT 4 /* Read the tail if indirect item not - found */ -#define GET_BLOCK_NO_ISEM 8 /* i_sem is not held, don't preallocate */ -#define GET_BLOCK_NO_DANGLE 16 /* Don't leave any transactions running */ - -/* ------------------------------------------------------------------- - * vnode operations - * -------------------------------------------------------------------*/ - -int -reiserfs_read(struct vop_read_args *ap) -{ - struct uio *uio; - struct vnode *vp; - struct reiserfs_node *ip; - struct reiserfs_sb_info *sbi; - - int error; - long size; - daddr_t lbn; - off_t bytesinfile, offset; - - uio = ap->a_uio; - vp = ap->a_vp; - ip = VTOI(vp); - sbi = ip->i_reiserfs; - - size = sbi->s_blocksize; - - for (error = 0; uio->uio_resid > 0;) { - if ((bytesinfile = ip->i_size - uio->uio_offset) <= 0) - break; - - /* Compute the logical block number and its offset */ - lbn = uio->uio_offset / size; - offset = uio->uio_offset % size; - reiserfs_log(LOG_DEBUG, "logical block number: %ju\n", - (intmax_t)lbn); - reiserfs_log(LOG_DEBUG, "block offset: %ju\n", - (intmax_t)offset); - - /* Read file blocks */ - reiserfs_log(LOG_DEBUG, "reiserfs_get_block(%ju)\n", - (intmax_t)lbn); - if ((error = reiserfs_get_block(ip, lbn, offset, uio)) != 0) { - reiserfs_log(LOG_DEBUG, - "reiserfs_get_block returned the error %d\n", - error); - break; - } - } - - return (error); -} - -static void -reiserfs_bufstrategy(struct bufobj *bo, struct buf *bp) -{ - struct vnode *vp; - int rc; - - vp = bo->bo_private; - KASSERT(bo == &vp->v_bufobj, ("BO/VP mismatch: vp %p bo %p != %p", - vp, &vp->v_bufobj, bo)); - rc = VOP_STRATEGY(vp, bp); - KASSERT(rc == 0, ("ReiserFS VOP_STRATEGY failed: bp=%p, " - "vp=%p, rc=%d", bp, vp, rc)); -} - -int -reiserfs_inactive(struct vop_inactive_args *ap) -{ - int error; - struct vnode *vp; - struct reiserfs_node *ip; - - error = 0; - vp = ap->a_vp; - ip = VTOI(vp); - - reiserfs_log(LOG_DEBUG, "deactivating inode used %d times\n", - vp->v_usecount); - -#if 0 - /* Ignore inodes related to stale file handles. */ - if (ip->i_mode == 0) - goto out; - -out: -#endif - - /* - * If we are done with the inode, reclaim it so that it can be reused - * immediately. - */ - if (ip->i_mode == 0) { - reiserfs_log(LOG_DEBUG, "recyling\n"); - vrecycle(vp); - } - - return (error); -} - -int -reiserfs_reclaim(struct vop_reclaim_args *ap) -{ - struct reiserfs_node *ip; - struct vnode *vp; - - vp = ap->a_vp; - - reiserfs_log(LOG_DEBUG, "reclaiming inode used %d times\n", - vp->v_usecount); - ip = VTOI(vp); - - /* XXX Update this node (write to the disk) */ - - /* Remove the inode from its hash chain. */ - vfs_hash_remove(vp); - - reiserfs_log(LOG_DEBUG, "free private data\n"); - free(vp->v_data, M_REISERFSNODE); - vp->v_data = NULL; - vnode_destroy_vobject(vp); - - return (0); -} - -/* ------------------------------------------------------------------- - * Functions from linux/fs/reiserfs/inode.c - * -------------------------------------------------------------------*/ - -static void -_make_cpu_key(struct cpu_key *key, int version, - uint32_t dirid, uint32_t objectid, off_t offset, int type, int length) -{ - - key->version = version; - - key->on_disk_key.k_dir_id = dirid; - key->on_disk_key.k_objectid = objectid; - set_cpu_key_k_offset(key, offset); - set_cpu_key_k_type(key, type); - key->key_length = length; -} - -/* - * Take base of inode_key (it comes from inode always) (dirid, objectid) - * and version from an inode, set offset and type of key - */ -void -make_cpu_key(struct cpu_key *key, struct reiserfs_node *ip, off_t offset, - int type, int length) -{ - - _make_cpu_key(key, get_inode_item_key_version(ip), - le32toh(INODE_PKEY(ip)->k_dir_id), - le32toh(INODE_PKEY(ip)->k_objectid), - offset, type, length); -} - -int -reiserfs_get_block(struct reiserfs_node *ip, long block, off_t offset, - struct uio *uio) -{ - caddr_t blk = NULL, p; - struct cpu_key key; - /* unsigned long offset; */ - INITIALIZE_PATH(path); - struct buf *bp, *blk_bp; - struct item_head *ih; - struct reiserfs_sb_info *sbi; - int blocknr, chars, done = 0, ret = 0, args = 0; - - sbi = ip->i_reiserfs; - - /* Prepare the key to look for the 'block'-th block of file */ - reiserfs_log(LOG_DEBUG, "prepare cpu key\n"); - make_cpu_key(&key, ip, (off_t)block * sbi->s_blocksize + 1, TYPE_ANY, 3); - - /* research: */ - reiserfs_log(LOG_DEBUG, "search for position\n"); - if (search_for_position_by_key(sbi, &key, &path) != POSITION_FOUND) { - reiserfs_log(LOG_DEBUG, "position not found\n"); - pathrelse(&path); -#if 0 - if (blk) - kunmap(bh_result->b_page); -#endif - /* - * We do not return ENOENT if there is a hole but page is - * uptodate, because it means that there is some MMAPED data - * associated with it that is yet to be written to disk. - */ - if ((args & GET_BLOCK_NO_HOLE)/* && - !PageUptodate(bh_result->b_page)*/) - return (ENOENT); - return (0); - } - reiserfs_log(LOG_DEBUG, "position found\n"); - - bp = get_last_bp(&path); - ih = get_ih(&path); - - if (is_indirect_le_ih(ih)) { - off_t xfersize; - uint32_t *ind_item = (uint32_t *)B_I_PITEM(bp, ih); - - reiserfs_log(LOG_DEBUG, "item is INDIRECT\n"); - - blocknr = get_block_num(ind_item, path.pos_in_item); - reiserfs_log(LOG_DEBUG, "block number: %d " - "(ind_item=%p, pos_in_item=%u)\n", - blocknr, ind_item, path.pos_in_item); - - xfersize = MIN(sbi->s_blocksize - offset, - ip->i_size - uio->uio_offset); - xfersize = MIN(xfersize, uio->uio_resid); - - if (blocknr) { - ret = bread(sbi->s_devvp, - blocknr * btodb(sbi->s_blocksize), - sbi->s_blocksize, NOCRED, &blk_bp); - reiserfs_log(LOG_DEBUG, "xfersize: %ju\n", - (intmax_t)xfersize); - ret = uiomove(blk_bp->b_data + offset, xfersize, uio); - brelse(blk_bp); - } else { - /* - * We do not return ENOENT if there is a hole but - * page is uptodate, because it means That there - * is some MMAPED data associated with it that - * is yet to be written to disk. - */ - if ((args & GET_BLOCK_NO_HOLE)/* && - !PageUptodate(bh_result->b_page)*/) - ret = (ENOENT); - - /* Skip this hole */ - uio->uio_resid -= xfersize; - uio->uio_offset += xfersize; - } - - pathrelse(&path); - return (ret); - } - - reiserfs_log(LOG_DEBUG, "item should be DIRECT\n"); - -#if 0 - /* Requested data are in direct item(s) */ - if (!(args & GET_BLOCK_READ_DIRECT)) { - /* - * We are called by bmap. FIXME: we can not map block of - * file when it is stored in direct item(s) - */ - pathrelse(&path); -#if 0 - if (blk) - kunmap(bh_result->b_page); -#endif - return (ENOENT); - } -#endif - -#if 0 - /* - * If we've got a direct item, and the buffer or page was uptodate, we - * don't want to pull data off disk again. Skip to the end, where we - * map the buffer and return - */ - if (buffer_uptodate(bh_result)) { - goto finished; - } else - /* - * grab_tail_page can trigger calls to reiserfs_get_block - * on up to date pages without any buffers. If the page - * is up to date, we don't want read old data off disk. - * Set the up to date bit on the buffer instead and jump - * to the end - */ - if (!bh_result->b_page || PageUptodate(bh_result->b_page)) { - set_buffer_uptodate(bh_result); - goto finished; - } -#endif - -#if 0 - /* Read file tail into part of page */ - offset = (cpu_key_k_offset(&key) - 1) & (PAGE_CACHE_SIZE - 1); - fs_gen = get_generation(ip->i_reiserfs); - copy_item_head(&tmp_ih, ih); -#endif - -#if 0 - /* - * We only want to kmap if we are reading the tail into the page. this - * is not the common case, so we don't kmap until we are sure we need - * to. But, this means the item might move if kmap schedules - */ - if (!blk) { - blk = (char *)kmap(bh_result->b_page); - if (fs_changed (fs_gen, sbi) && item_moved(&tmp_ih, &path)) - goto research; - } - blk += offset; - memset(blk, 0, sbi->s_blocksize); -#endif - if (!blk) { - reiserfs_log(LOG_DEBUG, "allocating buffer\n"); - blk = malloc(ip->i_size, M_REISERFSNODE, M_WAITOK | M_ZERO); - if (!blk) - return (ENOMEM); - } - /* p += offset; */ - - p = blk; - do { - if (!is_direct_le_ih(ih)) { - reiserfs_log(LOG_ERR, "BUG\n"); - return (ENOENT); /* XXX Wrong error code */ - } - - /* - * Make sure we don't read more bytes than actually exist - * in the file. This can happen in odd cases where i_size - * isn't correct, and when direct item padding results in - * a few extra bytes at the end of the direct item - */ - if ((le_ih_k_offset(ih) + path.pos_in_item) > ip->i_size) - break; - - if ((le_ih_k_offset(ih) - 1 + ih_item_len(ih)) > ip->i_size) { - chars = ip->i_size - (le_ih_k_offset(ih) - 1) - - path.pos_in_item; - done = 1; - } else { - chars = ih_item_len(ih) - path.pos_in_item; - } - reiserfs_log(LOG_DEBUG, "copying %d bytes\n", chars); - memcpy(p, B_I_PITEM(bp, ih) + path.pos_in_item, chars); - if (done) { - reiserfs_log(LOG_DEBUG, "copy done\n"); - break; - } - - p += chars; - - if (PATH_LAST_POSITION(&path) != (B_NR_ITEMS(bp) - 1)) - /* - * We done, if read direct item is not the last - * item of node - * FIXME: we could try to check right delimiting - * key to see whether direct item continues in - * the right neighbor or rely on i_size - */ - break; - - /* Update key to look for the next piece */ - set_cpu_key_k_offset(&key, cpu_key_k_offset(&key) + chars); - if (search_for_position_by_key(sbi, &key, &path) != - POSITION_FOUND) - /* - * We read something from tail, even if now we got - * IO_ERROR - */ - break; - - bp = get_last_bp(&path); - ih = get_ih(&path); - } while (1); - - /* finished: */ - pathrelse(&path); - /* - * This buffer has valid data, but isn't valid for io. mapping it to - * block #0 tells the rest of reiserfs it just has a tail in it - */ - ret = uiomove(blk, ip->i_size, uio); - free(blk, M_REISERFSNODE); - return (ret); -} - -/* - * Compute real number of used bytes by file - * Following three functions can go away when we'll have enough space in - * stat item - */ -static int -real_space_diff(struct reiserfs_node *ip, int sd_size) -{ - int bytes; - off_t blocksize = ip->i_reiserfs->s_blocksize; - - if (S_ISLNK(ip->i_mode) || S_ISDIR(ip->i_mode)) - return (sd_size); - - /* End of file is also in full block with indirect reference, so round - * up to the next block. - * - * There is just no way to know if the tail is actually packed on the - * file, so we have to assume it isn't. When we pack the tail, we add - * 4 bytes to pretend there really is an unformatted node pointer. */ - bytes = ((ip->i_size + (blocksize - 1)) >> - ip->i_reiserfs->s_blocksize_bits) * UNFM_P_SIZE + sd_size; - - return (bytes); -} - -static inline off_t -to_real_used_space(struct reiserfs_node *ip, unsigned long blocks, int sd_size) -{ - - if (S_ISLNK(ip->i_mode) || S_ISDIR(ip->i_mode)) { - return ip->i_size + (off_t)(real_space_diff(ip, sd_size)); - } - - return ((off_t)real_space_diff(ip, sd_size)) + (((off_t)blocks) << 9); -} - -void -inode_set_bytes(struct reiserfs_node *ip, off_t bytes) -{ - - ip->i_blocks = bytes >> 9; - ip->i_bytes = bytes & 511; -} - -/* Called by read_locked_inode */ -static void -init_inode(struct reiserfs_node *ip, struct path *path) -{ - struct buf *bp; - struct item_head *ih; - uint32_t rdev; - - bp = PATH_PLAST_BUFFER(path); - ih = PATH_PITEM_HEAD(path); - - reiserfs_log(LOG_DEBUG, "copy the key (objectid=%d, dirid=%d)\n", - ih->ih_key.k_objectid, ih->ih_key.k_dir_id); - copy_key(INODE_PKEY(ip), &(ih->ih_key)); - /* ip->i_blksize = reiserfs_default_io_size; */ - - reiserfs_log(LOG_DEBUG, "reset some inode structure members\n"); - REISERFS_I(ip)->i_flags = 0; -#if 0 - REISERFS_I(ip)->i_prealloc_block = 0; - REISERFS_I(ip)->i_prealloc_count = 0; - REISERFS_I(ip)->i_trans_id = 0; - REISERFS_I(ip)->i_jl = NULL; - REISERFS_I(ip)->i_acl_access = NULL; - REISERFS_I(ip)->i_acl_default = NULL; -#endif - - if (stat_data_v1(ih)) { - reiserfs_log(LOG_DEBUG, "reiserfs/init_inode: stat data v1\n"); - struct stat_data_v1 *sd; - unsigned long blocks; - - sd = (struct stat_data_v1 *)B_I_PITEM(bp, ih); - - reiserfs_log(LOG_DEBUG, - "reiserfs/init_inode: filling more members\n"); - set_inode_item_key_version(ip, KEY_FORMAT_3_5); - set_inode_sd_version(ip, STAT_DATA_V1); - ip->i_mode = sd_v1_mode(sd); - ip->i_nlink = sd_v1_nlink(sd); - ip->i_uid = sd_v1_uid(sd); - ip->i_gid = sd_v1_gid(sd); - ip->i_size = sd_v1_size(sd); - ip->i_atime.tv_sec = sd_v1_atime(sd); - ip->i_mtime.tv_sec = sd_v1_mtime(sd); - ip->i_ctime.tv_sec = sd_v1_ctime(sd); - ip->i_atime.tv_nsec = 0; - ip->i_ctime.tv_nsec = 0; - ip->i_mtime.tv_nsec = 0; - - reiserfs_log(LOG_DEBUG, " mode = %08x\n", ip->i_mode); - reiserfs_log(LOG_DEBUG, " nlink = %d\n", ip->i_nlink); - reiserfs_log(LOG_DEBUG, " owner = %d:%d\n", ip->i_uid, - ip->i_gid); - reiserfs_log(LOG_DEBUG, " size = %ju\n", - (intmax_t)ip->i_size); - reiserfs_log(LOG_DEBUG, " atime = %jd\n", - (intmax_t)ip->i_atime.tv_sec); - reiserfs_log(LOG_DEBUG, " mtime = %jd\n", - (intmax_t)ip->i_mtime.tv_sec); - reiserfs_log(LOG_DEBUG, " ctime = %jd\n", - (intmax_t)ip->i_ctime.tv_sec); - - ip->i_blocks = sd_v1_blocks(sd); - ip->i_generation = le32toh(INODE_PKEY(ip)->k_dir_id); - blocks = (ip->i_size + 511) >> 9; - blocks = _ROUND_UP(blocks, ip->i_reiserfs->s_blocksize >> 9); - if (ip->i_blocks > blocks) { - /* - * There was a bug in <= 3.5.23 when i_blocks could - * take negative values. Starting from 3.5.17 this - * value could even be stored in stat data. For such - * files we set i_blocks based on file size. Just 2 - * notes: this can be wrong for sparce files. On-disk - * value will be only updated if file's inode will - * ever change. - */ - ip->i_blocks = blocks; - } - - rdev = sd_v1_rdev(sd); - REISERFS_I(ip)->i_first_direct_byte = - sd_v1_first_direct_byte(sd); - - /* - * An early bug in the quota code can give us an odd number - * for the block count. This is incorrect, fix it here. - */ - if (ip->i_blocks & 1) { - ip->i_blocks++ ; - } - inode_set_bytes(ip, to_real_used_space(ip, ip->i_blocks, - SD_V1_SIZE)); - - /* - * nopack is initially zero for v1 objects. For v2 objects, - * nopack is initialised from sd_attrs - */ - REISERFS_I(ip)->i_flags &= ~i_nopack_mask; - reiserfs_log(LOG_DEBUG, "...done\n"); - } else { - reiserfs_log(LOG_DEBUG, "stat data v2\n"); - /* - * New stat data found, but object may have old items - * (directories and symlinks) - */ - struct stat_data *sd = (struct stat_data *)B_I_PITEM(bp, ih); - - reiserfs_log(LOG_DEBUG, "filling more members\n"); - ip->i_mode = sd_v2_mode(sd); - ip->i_nlink = sd_v2_nlink(sd); - ip->i_uid = sd_v2_uid(sd); - ip->i_size = sd_v2_size(sd); - ip->i_gid = sd_v2_gid(sd); - ip->i_mtime.tv_sec = sd_v2_mtime(sd); - ip->i_atime.tv_sec = sd_v2_atime(sd); - ip->i_ctime.tv_sec = sd_v2_ctime(sd); - ip->i_ctime.tv_nsec = 0; - ip->i_mtime.tv_nsec = 0; - ip->i_atime.tv_nsec = 0; - - reiserfs_log(LOG_DEBUG, " mode = %08x\n", ip->i_mode); - reiserfs_log(LOG_DEBUG, " nlink = %d\n", ip->i_nlink); - reiserfs_log(LOG_DEBUG, " owner = %d:%d\n", ip->i_uid, - ip->i_gid); - reiserfs_log(LOG_DEBUG, " size = %ju\n", - (intmax_t)ip->i_size); - reiserfs_log(LOG_DEBUG, " atime = %jd\n", - (intmax_t)ip->i_atime.tv_sec); - reiserfs_log(LOG_DEBUG, " mtime = %jd\n", - (intmax_t)ip->i_mtime.tv_sec); - reiserfs_log(LOG_DEBUG, " ctime = %jd\n", - (intmax_t)ip->i_ctime.tv_sec); - - ip->i_blocks = sd_v2_blocks(sd); - rdev = sd_v2_rdev(sd); - reiserfs_log(LOG_DEBUG, " blocks = %u\n", ip->i_blocks); - - if (S_ISCHR(ip->i_mode) || S_ISBLK(ip->i_mode)) - ip->i_generation = le32toh(INODE_PKEY(ip)->k_dir_id); - else - ip->i_generation = sd_v2_generation(sd); - - if (S_ISDIR(ip->i_mode) || S_ISLNK(ip->i_mode)) - set_inode_item_key_version(ip, KEY_FORMAT_3_5); - else - set_inode_item_key_version(ip, KEY_FORMAT_3_6); - - REISERFS_I(ip)->i_first_direct_byte = 0; - set_inode_sd_version(ip, STAT_DATA_V2); - inode_set_bytes(ip, to_real_used_space(ip, ip->i_blocks, - SD_V2_SIZE)); - - /* - * Read persistent inode attributes from sd and initalise - * generic inode flags from them - */ - REISERFS_I(ip)->i_attrs = sd_v2_attrs(sd); - sd_attrs_to_i_attrs(sd_v2_attrs(sd), ip); - reiserfs_log(LOG_DEBUG, "...done\n"); - } - - pathrelse(path); - if (S_ISREG(ip->i_mode)) { - reiserfs_log(LOG_DEBUG, "this inode is a regular file\n"); - //ip->i_op = &reiserfs_file_ip_operations; - //ip->i_fop = &reiserfs_file_operations; - //ip->i_mapping->a_ops = &reiserfs_address_space_operations ; - } else if (S_ISDIR(ip->i_mode)) { - reiserfs_log(LOG_DEBUG, "this inode is a directory\n"); - //ip->i_op = &reiserfs_dir_ip_operations; - //ip->i_fop = &reiserfs_dir_operations; - } else if (S_ISLNK(ip->i_mode)) { - reiserfs_log(LOG_DEBUG, "this inode is a symlink\n"); - //ip->i_op = &reiserfs_symlink_ip_operations; - //ip->i_mapping->a_ops = &reiserfs_address_space_operations; - } else { - reiserfs_log(LOG_DEBUG, "this inode is something unknown in " - "this universe\n"); - ip->i_blocks = 0; - //ip->i_op = &reiserfs_special_ip_operations; - //init_special_ip(ip, ip->i_mode, new_decode_dev(rdev)); - } -} - -/* - * reiserfs_read_locked_inode is called to read the inode off disk, and - * it does a make_bad_inode when things go wrong. But, we need to make - * sure and clear the key in the private portion of the inode, otherwise - * a corresponding iput might try to delete whatever object the inode - * last represented. - */ -static void -reiserfs_make_bad_inode(struct reiserfs_node *ip) { - - memset(INODE_PKEY(ip), 0, KEY_SIZE); - //make_bad_inode(inode); -} - -void -reiserfs_read_locked_inode(struct reiserfs_node *ip, - struct reiserfs_iget_args *args) -{ - INITIALIZE_PATH(path_to_sd); - struct cpu_key key; - unsigned long dirino; - int retval; - - dirino = args->dirid; - - /* - * Set version 1, version 2 could be used too, because stat data - * key is the same in both versions - */ - key.version = KEY_FORMAT_3_5; - key.on_disk_key.k_dir_id = dirino; - key.on_disk_key.k_objectid = ip->i_number; - key.on_disk_key.u.k_offset_v1.k_offset = SD_OFFSET; - key.on_disk_key.u.k_offset_v1.k_uniqueness = SD_UNIQUENESS; - - /* Look for the object's stat data */ - retval = search_item(ip->i_reiserfs, &key, &path_to_sd); - if (retval == IO_ERROR) { - reiserfs_log(LOG_ERR, - "I/O failure occured trying to find stat" - "data %u/%u\n", - key.on_disk_key.k_dir_id, key.on_disk_key.k_objectid); - reiserfs_make_bad_inode(ip); - return; - } - if (retval != ITEM_FOUND) { - /* - * A stale NFS handle can trigger this without it being - * an error - */ - reiserfs_log(LOG_ERR, - "item not found (objectid=%u, dirid=%u)\n", - key.on_disk_key.k_objectid, key.on_disk_key.k_dir_id); - pathrelse(&path_to_sd); - reiserfs_make_bad_inode(ip); - ip->i_nlink = 0; - return; - } - - init_inode(ip, &path_to_sd); - - /* - * It is possible that knfsd is trying to access inode of a file - * that is being removed from the disk by some other thread. As - * we update sd on unlink all that is required is to check for - * nlink here. This bug was first found by Sizif when debugging - * SquidNG/Butterfly, forgotten, and found again after Philippe - * Gramoulle <philippe.gramoulle@mmania.com> reproduced it. - * - * More logical fix would require changes in fs/inode.c:iput() to - * remove inode from hash-table _after_ fs cleaned disk stuff up and - * in iget() to return NULL if I_FREEING inode is found in hash-table. - */ - /* - * Currently there is one place where it's ok to meet inode with - * nlink == 0: processing of open-unlinked and half-truncated files - * during mount (fs/reiserfs/super.c:finish_unfinished()). - */ - if((ip->i_nlink == 0) && - !REISERFS_SB(ip->i_reiserfs)->s_is_unlinked_ok ) { - reiserfs_log(LOG_WARNING, "dead inode read from disk. This is " - "likely to be race with knfsd. Ignore"); - reiserfs_make_bad_inode(ip); - } - - /* Init inode should be relsing */ - reiserfs_check_path(&path_to_sd); -} - -int -reiserfs_iget( - struct mount *mp, const struct cpu_key *key, - struct vnode **vpp, struct thread *td) -{ - int error, flags; - struct cdev *dev; - struct vnode *vp; - struct reiserfs_node *ip; - struct reiserfs_mount *rmp; - - struct reiserfs_iget_args args; - - //restart: - /* Check if the inode cache contains it */ - // XXX LK_EXCLUSIVE ? - flags = LK_EXCLUSIVE; - error = vfs_hash_get(mp, key->on_disk_key.k_objectid, flags, - td, vpp, NULL, NULL); - if (error || *vpp != NULL) - return (error); - - rmp = VFSTOREISERFS(mp); - dev = rmp->rm_dev; - - reiserfs_log(LOG_DEBUG, "malloc(struct reiserfs_node)\n"); - ip = malloc(sizeof(struct reiserfs_node), M_REISERFSNODE, - M_WAITOK | M_ZERO); - - /* Allocate a new vnode/inode. */ - reiserfs_log(LOG_DEBUG, "getnewvnode\n"); - if ((error = - getnewvnode("reiserfs", mp, &reiserfs_vnodeops, &vp)) != 0) { - *vpp = NULL; - free(ip, M_REISERFSNODE); - reiserfs_log(LOG_DEBUG, "getnewvnode FAILED\n"); - return (error); - } - - args.dirid = key->on_disk_key.k_dir_id; - args.objectid = key->on_disk_key.k_objectid; - - reiserfs_log(LOG_DEBUG, "filling *ip\n"); - vp->v_data = ip; - ip->i_vnode = vp; - ip->i_dev = dev; - ip->i_number = args.objectid; - ip->i_ino = args.dirid; - ip->i_reiserfs = rmp->rm_reiserfs; - - vp->v_bufobj.bo_ops = &reiserfs_vnbufops; - vp->v_bufobj.bo_private = vp; - - /* If this is the root node, set the VV_ROOT flag */ - if (ip->i_number == REISERFS_ROOT_OBJECTID && - ip->i_ino == REISERFS_ROOT_PARENT_OBJECTID) - vp->v_vflag |= VV_ROOT; - -#if 0 - if (VOP_LOCK(vp, LK_EXCLUSIVE) != 0) - panic("reiserfs/iget: unexpected lock failure"); - - /* - * Exclusively lock the vnode before adding to hash. Note, that we - * must not release nor downgrade the lock (despite flags argument - * says) till it is fully initialized. - */ - lockmgr(vp->v_vnlock, LK_EXCLUSIVE, (struct mtx *)0); -#endif - - lockmgr(vp->v_vnlock, LK_EXCLUSIVE, NULL); - error = insmntque(vp, mp); - if (error != 0) { - free(ip, M_REISERFSNODE); - *vpp = NULL; - reiserfs_log(LOG_DEBUG, "insmntque FAILED\n"); - return (error); - } - error = vfs_hash_insert(vp, key->on_disk_key.k_objectid, flags, - td, vpp, NULL, NULL); - if (error || *vpp != NULL) - return (error); - - /* Read the inode */ - reiserfs_log(LOG_DEBUG, "call reiserfs_read_locked_inode (" - "objectid=%d,dirid=%d)\n", args.objectid, args.dirid); - reiserfs_read_locked_inode(ip, &args); - - ip->i_devvp = rmp->rm_devvp; - - switch(vp->v_type = IFTOVT(ip->i_mode)) { - case VBLK: - reiserfs_log(LOG_DEBUG, "vnode type VBLK\n"); - vp->v_op = &reiserfs_specops; - break; -#if 0 - case VCHR: - reiserfs_log(LOG_DEBUG, "vnode type VCHR\n"); - vp->v_op = &reiserfs_specops; - vp = addaliasu(vp, ip->i_rdev); - ip->i_vnode = vp; - break; - case VFIFO: - reiserfs_log(LOG_DEBUG, "vnode type VFIFO\n"); - vp->v_op = reiserfs_fifoop_p; - break; -#endif - default: - break; - } - - *vpp = vp; - return (0); -} - -void -sd_attrs_to_i_attrs(uint16_t sd_attrs, struct reiserfs_node *ip) -{ - - if (reiserfs_attrs(ip->i_reiserfs)) { -#if 0 - if (sd_attrs & REISERFS_SYNC_FL) - ip->i_flags |= S_SYNC; - else - ip->i_flags &= ~S_SYNC; -#endif - if (sd_attrs & REISERFS_IMMUTABLE_FL) - ip->i_flags |= IMMUTABLE; - else - ip->i_flags &= ~IMMUTABLE; - if (sd_attrs & REISERFS_APPEND_FL) - ip->i_flags |= APPEND; - else - ip->i_flags &= ~APPEND; -#if 0 - if (sd_attrs & REISERFS_NOATIME_FL) - ip->i_flags |= S_NOATIME; - else - ip->i_flags &= ~S_NOATIME; - if (sd_attrs & REISERFS_NOTAIL_FL) - REISERFS_I(ip)->i_flags |= i_nopack_mask; - else - REISERFS_I(ip)->i_flags &= ~i_nopack_mask; -#endif - } -} - -void -i_attrs_to_sd_attrs(struct reiserfs_node *ip, uint16_t *sd_attrs) -{ - - if (reiserfs_attrs(ip->i_reiserfs)) { -#if 0 - if (ip->i_flags & S_SYNC) - *sd_attrs |= REISERFS_SYNC_FL; - else - *sd_attrs &= ~REISERFS_SYNC_FL; -#endif - if (ip->i_flags & IMMUTABLE) - *sd_attrs |= REISERFS_IMMUTABLE_FL; - else - *sd_attrs &= ~REISERFS_IMMUTABLE_FL; - if (ip->i_flags & APPEND) - *sd_attrs |= REISERFS_APPEND_FL; - else - *sd_attrs &= ~REISERFS_APPEND_FL; -#if 0 - if (ip->i_flags & S_NOATIME) - *sd_attrs |= REISERFS_NOATIME_FL; - else - *sd_attrs &= ~REISERFS_NOATIME_FL; - if (REISERFS_I(ip)->i_flags & i_nopack_mask) - *sd_attrs |= REISERFS_NOTAIL_FL; - else - *sd_attrs &= ~REISERFS_NOTAIL_FL; -#endif - } -} diff --git a/sys/gnu/fs/reiserfs/reiserfs_item_ops.c b/sys/gnu/fs/reiserfs/reiserfs_item_ops.c deleted file mode 100644 index f3593c3..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_item_ops.c +++ /dev/null @@ -1,158 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#include <gnu/fs/reiserfs/reiserfs_fs.h> - -/* ------------------------------------------------------------------- - * Stat data functions - * -------------------------------------------------------------------*/ - -static int -sd_bytes_number(struct item_head *ih, int block_size) -{ - - return (0); -} - -struct item_operations stat_data_ops = { - .bytes_number = sd_bytes_number, - //.decrement_key = sd_decrement_key, - //.is_left_mergeable = sd_is_left_mergeable, - //.print_item = sd_print_item, - //.check_item = sd_check_item, - - //.create_vi = sd_create_vi, - //.check_left = sd_check_left, - //.check_right = sd_check_right, - //.part_size = sd_part_size, - //.unit_num = sd_unit_num, - //.print_vi = sd_print_vi -}; - -/* ------------------------------------------------------------------- - * Direct item functions - * -------------------------------------------------------------------*/ - -static int -direct_bytes_number(struct item_head *ih, int block_size) -{ - - return (ih_item_len(ih)); -} - -struct item_operations direct_ops = { - .bytes_number = direct_bytes_number, - //.decrement_key = direct_decrement_key, - //.is_left_mergeable = direct_is_left_mergeable, - //.print_item = direct_print_item, - //.check_item = direct_check_item, - - //.create_vi = direct_create_vi, - //.check_left = direct_check_left, - //.check_right = direct_check_right, - //.part_size = direct_part_size, - //.unit_num = direct_unit_num, - //.print_vi = direct_print_vi -}; - -/* ------------------------------------------------------------------- - * Indirect item functions - * -------------------------------------------------------------------*/ - -static int -indirect_bytes_number(struct item_head *ih, int block_size) -{ - - return (ih_item_len(ih) / UNFM_P_SIZE * block_size); -} - -struct item_operations indirect_ops = { - .bytes_number = indirect_bytes_number, - //.decrement_key = indirect_decrement_key, - //.is_left_mergeable = indirect_is_left_mergeable, - //.print_item = indirect_print_item, - //.check_item = indirect_check_item, - - //.create_vi = indirect_create_vi, - //.check_left = indirect_check_left, - //.check_right = indirect_check_right, - //.part_size = indirect_part_size, - //.unit_num = indirect_unit_num, - //.print_vi = indirect_print_vi -}; - -/* ------------------------------------------------------------------- - * Direntry functions - * -------------------------------------------------------------------*/ - -static int -direntry_bytes_number(struct item_head *ih, int block_size) -{ - - reiserfs_log(LOG_WARNING, "bytes number is asked for direntry\n"); - return (0); -} - -struct item_operations direntry_ops = { - .bytes_number = direntry_bytes_number, - //.decrement_key = direntry_decrement_key, - //.is_left_mergeable = direntry_is_left_mergeable, - //.print_item = direntry_print_item, - //.check_item = direntry_check_item, - - //.create_vi = direntry_create_vi, - //.check_left = direntry_check_left, - //.check_right = direntry_check_right, - //.part_size = direntry_part_size, - //.unit_num = direntry_unit_num, - //.print_vi = direntry_print_vi -}; - -/* ------------------------------------------------------------------- - * Error catching functions to catch errors caused by incorrect item - * types. - * -------------------------------------------------------------------*/ - -static int -errcatch_bytes_number(struct item_head *ih, int block_size) -{ - - reiserfs_log(LOG_WARNING, "invalid item type observed, run fsck ASAP"); - return (0); -} - -struct item_operations errcatch_ops = { - errcatch_bytes_number, - //errcatch_decrement_key, - //errcatch_is_left_mergeable, - //errcatch_print_item, - //errcatch_check_item, - - //errcatch_create_vi, - //errcatch_check_left, - //errcatch_check_right, - //errcatch_part_size, - //errcatch_unit_num, - //errcatch_print_vi -}; - -#if !(TYPE_STAT_DATA == 0 && TYPE_INDIRECT == 1 && \ - TYPE_DIRECT == 2 && TYPE_DIRENTRY == 3) -#error -#endif - -struct item_operations *item_ops[TYPE_ANY + 1] = { - &stat_data_ops, - &indirect_ops, - &direct_ops, - &direntry_ops, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - &errcatch_ops /* This is to catch errors with invalid type (15th - entry for TYPE_ANY) */ -}; diff --git a/sys/gnu/fs/reiserfs/reiserfs_mount.h b/sys/gnu/fs/reiserfs/reiserfs_mount.h deleted file mode 100644 index 93b8c7f..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_mount.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#ifndef _GNU_REISERFS_REISERFS_MOUNT_H -#define _GNU_REISERFS_REISERFS_MOUNT_H - -#if defined(_KERNEL) - -#ifdef MALLOC_DECLARE -MALLOC_DECLARE(M_REISERFSMNT); -MALLOC_DECLARE(M_REISERFSPATH); -MALLOC_DECLARE(M_REISERFSNODE); -MALLOC_DECLARE(M_REISERFSCOOKIES); -#endif - -/* This structure describes the ReiserFS specific mount structure data. */ -struct reiserfs_mount { - struct mount *rm_mountp; - struct cdev *rm_dev; - struct vnode *rm_devvp; - - struct reiserfs_sb_info *rm_reiserfs; - - struct g_consumer *rm_cp; - struct bufobj *rm_bo; -}; - -/* Convert mount ptr to reiserfs_mount ptr. */ -#define VFSTOREISERFS(mp) ((struct reiserfs_mount *)((mp)->mnt_data)) - -#endif /* defined(_KERNEL) */ - -/* Arguments to mount ReiserFS filesystems. */ -struct reiserfs_args { - char *fspec; /* blocks special holding the fs to mount */ - struct oexport_args export; /* network export information */ -}; - -#endif /* !defined _GNU_REISERFS_REISERFS_MOUNT_H */ diff --git a/sys/gnu/fs/reiserfs/reiserfs_namei.c b/sys/gnu/fs/reiserfs/reiserfs_namei.c deleted file mode 100644 index cde867a..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_namei.c +++ /dev/null @@ -1,701 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#include <gnu/fs/reiserfs/reiserfs_fs.h> - -static int reiserfs_find_entry(struct reiserfs_node *dp, - const char *name, int namelen, - struct path * path_to_entry, struct reiserfs_dir_entry *de); - -MALLOC_DEFINE(M_REISERFSCOOKIES, "reiserfs_cookies", - "ReiserFS VOP_READDIR cookies"); - -/* ------------------------------------------------------------------- - * Lookup functions - * -------------------------------------------------------------------*/ - -int -reiserfs_lookup(struct vop_cachedlookup_args *ap) -{ - int error, retval; - struct vnode *vdp = ap->a_dvp; - struct vnode **vpp = ap->a_vpp; - struct componentname *cnp = ap->a_cnp; - - int flags = cnp->cn_flags; - struct thread *td = cnp->cn_thread; - struct cpu_key *saved_ino; - - struct vnode *vp; - struct vnode *pdp; /* Saved dp during symlink work */ - struct reiserfs_node *dp; - struct reiserfs_dir_entry de; - INITIALIZE_PATH(path_to_entry); - - char c = cnp->cn_nameptr[cnp->cn_namelen]; - cnp->cn_nameptr[cnp->cn_namelen] = '\0'; - reiserfs_log(LOG_DEBUG, "looking for `%s', %ld (%s)\n", - cnp->cn_nameptr, cnp->cn_namelen, cnp->cn_pnbuf); - cnp->cn_nameptr[cnp->cn_namelen] = c; - - vp = NULL; - dp = VTOI(vdp); - - if (REISERFS_MAX_NAME(dp->i_reiserfs->s_blocksize) < cnp->cn_namelen) - return (ENAMETOOLONG); - - reiserfs_log(LOG_DEBUG, "searching entry\n"); - de.de_gen_number_bit_string = 0; - retval = reiserfs_find_entry(dp, cnp->cn_nameptr, cnp->cn_namelen, - &path_to_entry, &de); - pathrelse(&path_to_entry); - - if (retval == NAME_FOUND) { - reiserfs_log(LOG_DEBUG, "found\n"); - } else { - reiserfs_log(LOG_DEBUG, "not found\n"); - } - - if (retval == NAME_FOUND) { -#if 0 - /* Hide the .reiserfs_priv directory */ - if (reiserfs_xattrs(dp->i_reiserfs) && - !old_format_only(dp->i_reiserfs) && - REISERFS_SB(dp->i_reiserfs)->priv_root && - REISERFS_SB(dp->i_reiserfs)->priv_root->d_inode && - de.de_objectid == le32toh(INODE_PKEY(REISERFS_SB( - dp->i_reiserfs)->priv_root->d_inode)->k_objectid)) { - return (EACCES); - } -#endif - - reiserfs_log(LOG_DEBUG, "reading vnode\n"); - pdp = vdp; - if (flags & ISDOTDOT) { - saved_ino = (struct cpu_key *)&(de.de_dir_id); - VOP_UNLOCK(pdp, 0); - error = reiserfs_iget(vdp->v_mount, - saved_ino, &vp, td); - vn_lock(pdp, LK_EXCLUSIVE | LK_RETRY); - if (error != 0) - return (error); - *vpp = vp; - } else if (de.de_objectid == dp->i_number && - de.de_dir_id == dp->i_ino) { - VREF(vdp); /* We want ourself, ie "." */ - *vpp = vdp; - } else { - if ((error = reiserfs_iget(vdp->v_mount, - (struct cpu_key *)&(de.de_dir_id), &vp, td)) != 0) - return (error); - *vpp = vp; - } - - /* - * Propogate the priv_object flag so we know we're in the - * priv tree - */ - /*if (is_reiserfs_priv_object(dir)) - REISERFS_I(inode)->i_flags |= i_priv_object;*/ - } else { - if (retval == IO_ERROR) { - reiserfs_log(LOG_DEBUG, "IO error\n"); - return (EIO); - } - - return (ENOENT); - } - - /* Insert name into cache if appropriate. */ - if (cnp->cn_flags & MAKEENTRY) - cache_enter(vdp, *vpp, cnp); - - reiserfs_log(LOG_DEBUG, "done\n"); - return (0); -} - -extern struct key MIN_KEY; - -int -reiserfs_readdir(struct vop_readdir_args /* { - struct vnode *a_vp; - struct uio *a_uio; - struct ucred *a_cred; - int *a_eofflag; - int *a_ncookies; - u_long **a_cookies; - } */*ap) -{ - int error = 0; - struct dirent dstdp; - struct uio *uio = ap->a_uio; - - off_t next_pos; - struct buf *bp; - struct item_head *ih; - struct cpu_key pos_key; - const struct key *rkey; - struct reiserfs_node *ip; - struct reiserfs_dir_entry de; - INITIALIZE_PATH(path_to_entry); - int entry_num, item_num, search_res; - - /* The NFS part */ - int ncookies = 0; - u_long *cookies = NULL; - - /* - * Form key for search the next directory entry using f_pos field of - * file structure - */ - ip = VTOI(ap->a_vp); - make_cpu_key(&pos_key, - ip, uio->uio_offset ? uio->uio_offset : DOT_OFFSET, - TYPE_DIRENTRY, 3); - next_pos = cpu_key_k_offset(&pos_key); - - reiserfs_log(LOG_DEBUG, "listing entries for " - "(objectid=%d, dirid=%d)\n", - pos_key.on_disk_key.k_objectid, pos_key.on_disk_key.k_dir_id); - reiserfs_log(LOG_DEBUG, "uio_offset = %jd, uio_resid = %d\n", - (intmax_t)uio->uio_offset, uio->uio_resid); - - if (ap->a_ncookies && ap->a_cookies) { - cookies = (u_long *)malloc( - uio->uio_resid / 16 * sizeof(u_long), - M_REISERFSCOOKIES, M_WAITOK); - } - - while (1) { - //research: - /* - * Search the directory item, containing entry with - * specified key - */ - reiserfs_log(LOG_DEBUG, "search directory to read\n"); - search_res = search_by_entry_key(ip->i_reiserfs, &pos_key, - &path_to_entry, &de); - if (search_res == IO_ERROR) { - error = EIO; - goto out; - } - - entry_num = de.de_entry_num; - item_num = de.de_item_num; - bp = de.de_bp; - ih = de.de_ih; - - if (search_res == POSITION_FOUND || - entry_num < I_ENTRY_COUNT(ih)) { - /* - * Go through all entries in the directory item - * beginning from the entry, that has been found. - */ - struct reiserfs_de_head *deh = B_I_DEH(bp, ih) + - entry_num; - - if (ap->a_ncookies == NULL) { - cookies = NULL; - } else { - //ncookies = - } - - reiserfs_log(LOG_DEBUG, - "walking through directory entries\n"); - for (; entry_num < I_ENTRY_COUNT(ih); - entry_num++, deh++) { - int d_namlen; - char *d_name; - off_t d_off; - ino_t d_ino; - - if (!de_visible(deh)) { - /* It is hidden entry */ - continue; - } - - d_namlen = entry_length(bp, ih, entry_num); - d_name = B_I_DEH_ENTRY_FILE_NAME(bp, ih, deh); - if (!d_name[d_namlen - 1]) - d_namlen = strlen(d_name); - reiserfs_log(LOG_DEBUG, " - `%s' (len=%d)\n", - d_name, d_namlen); - - if (d_namlen > REISERFS_MAX_NAME( - ip->i_reiserfs->s_blocksize)) { - /* Too big to send back to VFS */ - continue; - } - -#if 0 - /* Ignore the .reiserfs_priv entry */ - if (reiserfs_xattrs(ip->i_reiserfs) && - !old_format_only(ip->i_reiserfs) && - filp->f_dentry == ip->i_reiserfs->s_root && - REISERFS_SB(ip->i_reiserfs)->priv_root && - REISERFS_SB(ip->i_reiserfs)->priv_root->d_inode && - deh_objectid(deh) == - le32toh(INODE_PKEY(REISERFS_SB( - ip->i_reiserfs)->priv_root->d_inode)->k_objectid)) { - continue; - } -#endif - - d_off = deh_offset(deh); - d_ino = deh_objectid(deh); - uio->uio_offset = d_off; - - /* Copy to user land */ - dstdp.d_fileno = d_ino; - dstdp.d_type = DT_UNKNOWN; - dstdp.d_namlen = d_namlen; - dstdp.d_reclen = GENERIC_DIRSIZ(&dstdp); - bcopy(d_name, dstdp.d_name, dstdp.d_namlen); - bzero(dstdp.d_name + dstdp.d_namlen, - dstdp.d_reclen - - offsetof(struct dirent, d_name) - - dstdp.d_namlen); - - if (d_namlen > 0) { - if (dstdp.d_reclen <= uio->uio_resid) { - reiserfs_log(LOG_DEBUG, " copying to user land\n"); - error = uiomove(&dstdp, - dstdp.d_reclen, uio); - if (error) - goto end; - if (cookies != NULL) { - cookies[ncookies] = - d_off; - ncookies++; - } - } else - break; - } else { - error = EIO; - break; - } - - next_pos = deh_offset(deh) + 1; - } - reiserfs_log(LOG_DEBUG, "...done\n"); - } - - reiserfs_log(LOG_DEBUG, "checking item num (%d == %d ?)\n", - item_num, B_NR_ITEMS(bp) - 1); - if (item_num != B_NR_ITEMS(bp) - 1) { - /* End of directory has been reached */ - reiserfs_log(LOG_DEBUG, "end reached\n"); - if (ap->a_eofflag) - *ap->a_eofflag = 1; - goto end; - } - - /* - * Item we went through is last item of node. Using right - * delimiting key check is it directory end - */ - reiserfs_log(LOG_DEBUG, "get right key\n"); - rkey = get_rkey(&path_to_entry, ip->i_reiserfs); - reiserfs_log(LOG_DEBUG, "right key = (objectid=%d, dirid=%d)\n", - rkey->k_objectid, rkey->k_dir_id); - - reiserfs_log(LOG_DEBUG, "compare it to MIN_KEY\n"); - reiserfs_log(LOG_DEBUG, "MIN KEY = (objectid=%d, dirid=%d)\n", - MIN_KEY.k_objectid, MIN_KEY.k_dir_id); - if (comp_le_keys(rkey, &MIN_KEY) == 0) { - /* Set pos_key to key, that is the smallest and greater - * that key of the last entry in the item */ - reiserfs_log(LOG_DEBUG, "continuing on the right\n"); - set_cpu_key_k_offset(&pos_key, next_pos); - continue; - } - - reiserfs_log(LOG_DEBUG, "compare it to pos_key\n"); - reiserfs_log(LOG_DEBUG, "pos key = (objectid=%d, dirid=%d)\n", - pos_key.on_disk_key.k_objectid, - pos_key.on_disk_key.k_dir_id); - if (COMP_SHORT_KEYS(rkey, &pos_key)) { - /* End of directory has been reached */ - reiserfs_log(LOG_DEBUG, "end reached (right)\n"); - if (ap->a_eofflag) - *ap->a_eofflag = 1; - goto end; - } - - /* Directory continues in the right neighboring block */ - reiserfs_log(LOG_DEBUG, "continuing with a new offset\n"); - set_cpu_key_k_offset(&pos_key, - le_key_k_offset(KEY_FORMAT_3_5, rkey)); - reiserfs_log(LOG_DEBUG, - "new pos key = (objectid=%d, dirid=%d)\n", - pos_key.on_disk_key.k_objectid, - pos_key.on_disk_key.k_dir_id); - } - -end: - uio->uio_offset = next_pos; - pathrelse(&path_to_entry); - reiserfs_check_path(&path_to_entry); -out: - if (error && cookies != NULL) { - free(cookies, M_REISERFSCOOKIES); - } else if (ap->a_ncookies != NULL && ap->a_cookies != NULL) { - *ap->a_ncookies = ncookies; - *ap->a_cookies = cookies; - } - return (error); -} - -/* ------------------------------------------------------------------- - * Functions from linux/fs/reiserfs/namei.c - * -------------------------------------------------------------------*/ - - -/* - * Directory item contains array of entry headers. This performs binary - * search through that array. - */ -static int -bin_search_in_dir_item(struct reiserfs_dir_entry *de, off_t off) -{ - struct item_head *ih = de->de_ih; - struct reiserfs_de_head *deh = de->de_deh; - int rbound, lbound, j; - - lbound = 0; - rbound = I_ENTRY_COUNT(ih) - 1; - - for (j = (rbound + lbound) / 2; lbound <= rbound; - j = (rbound + lbound) / 2) { - if (off < deh_offset(deh + j)) { - rbound = j - 1; - continue; - } - if (off > deh_offset(deh + j)) { - lbound = j + 1; - continue; - } - - /* This is not name found, but matched third key component */ - de->de_entry_num = j; - return (NAME_FOUND); - } - - de->de_entry_num = lbound; - return (NAME_NOT_FOUND); -} - -/* - * Comment? Maybe something like set de to point to what the path - * points to? - */ -static inline void -set_de_item_location(struct reiserfs_dir_entry *de, struct path *path) -{ - - de->de_bp = get_last_bp(path); - de->de_ih = get_ih(path); - de->de_deh = B_I_DEH(de->de_bp, de->de_ih); - de->de_item_num = PATH_LAST_POSITION(path); -} - -/* - * de_bh, de_ih, de_deh (points to first element of array), de_item_num - * is set - */ -void -set_de_name_and_namelen(struct reiserfs_dir_entry *de) -{ - struct reiserfs_de_head *deh = de->de_deh + de->de_entry_num; - - if (de->de_entry_num >= ih_entry_count(de->de_ih)) { - reiserfs_log(LOG_DEBUG, "BUG\n"); - return; - } - - de->de_entrylen = entry_length(de->de_bp, de->de_ih, de->de_entry_num); - de->de_namelen = de->de_entrylen - (de_with_sd(deh) ? SD_SIZE : 0); - de->de_name = B_I_PITEM(de->de_bp, de->de_ih) + deh_location(deh); - if (de->de_name[de->de_namelen - 1] == 0) - de->de_namelen = strlen(de->de_name); -} - -/* What entry points to */ -static inline void -set_de_object_key(struct reiserfs_dir_entry *de) -{ - - if (de->de_entry_num >= ih_entry_count(de->de_ih)) { - reiserfs_log(LOG_DEBUG, "BUG\n"); - return; - } - de->de_dir_id = deh_dir_id(&(de->de_deh[de->de_entry_num])); - de->de_objectid = deh_objectid(&(de->de_deh[de->de_entry_num])); -} - -static inline void -store_de_entry_key(struct reiserfs_dir_entry *de) -{ - struct reiserfs_de_head *deh = de->de_deh + de->de_entry_num; - - if (de->de_entry_num >= ih_entry_count(de->de_ih)) { - reiserfs_log(LOG_DEBUG, "BUG\n"); - return; - } - - /* Store key of the found entry */ - de->de_entry_key.version = KEY_FORMAT_3_5; - de->de_entry_key.on_disk_key.k_dir_id = - le32toh(de->de_ih->ih_key.k_dir_id); - de->de_entry_key.on_disk_key.k_objectid = - le32toh(de->de_ih->ih_key.k_objectid); - set_cpu_key_k_offset(&(de->de_entry_key), deh_offset(deh)); - set_cpu_key_k_type(&(de->de_entry_key), TYPE_DIRENTRY); -} - -/* - * We assign a key to each directory item, and place multiple entries in - * a single directory item. A directory item has a key equal to the key - * of the first directory entry in it. - * - * This function first calls search_by_key, then, if item whose first - * entry matches is not found it looks for the entry inside directory - * item found by search_by_key. Fills the path to the entry, and to the - * entry position in the item - */ -int -search_by_entry_key(struct reiserfs_sb_info *sbi, - const struct cpu_key *key, struct path *path, - struct reiserfs_dir_entry *de) -{ - int retval; - - reiserfs_log(LOG_DEBUG, "searching in (objectid=%d,dirid=%d)\n", - key->on_disk_key.k_objectid, key->on_disk_key.k_dir_id); - retval = search_item(sbi, key, path); - switch (retval) { - case ITEM_NOT_FOUND: - if (!PATH_LAST_POSITION(path)) { - reiserfs_log(LOG_DEBUG, - "search_by_key returned item position == 0"); - pathrelse(path); - return (IO_ERROR); - } - PATH_LAST_POSITION(path)--; - reiserfs_log(LOG_DEBUG, "search_by_key did not found it\n"); - break; - case ITEM_FOUND: - reiserfs_log(LOG_DEBUG, "search_by_key found it\n"); - break; - case IO_ERROR: - return (retval); - default: - pathrelse(path); - reiserfs_log(LOG_DEBUG, "no path to here"); - return (IO_ERROR); - } - - reiserfs_log(LOG_DEBUG, "set item location\n"); - set_de_item_location(de, path); - - /* - * Binary search in directory item by third component of the - * key. Sets de->de_entry_num of de - */ - reiserfs_log(LOG_DEBUG, "bin_search_in_dir_item\n"); - retval = bin_search_in_dir_item(de, cpu_key_k_offset(key)); - path->pos_in_item = de->de_entry_num; - if (retval != NAME_NOT_FOUND) { - /* - * Ugly, but rename needs de_bp, de_deh, de_name, de_namelen, - * de_objectid set - */ - set_de_name_and_namelen(de); - set_de_object_key(de); - reiserfs_log(LOG_DEBUG, "set (objectid=%d,dirid=%d)\n", - de->de_objectid, de->de_dir_id); - } - - return (retval); -} - -static uint32_t -get_third_component(struct reiserfs_sb_info *sbi, const char *name, int len) -{ - uint32_t res; - - if (!len || (len == 1 && name[0] == '.')) - return (DOT_OFFSET); - - if (len == 2 && name[0] == '.' && name[1] == '.') - return (DOT_DOT_OFFSET); - - res = REISERFS_SB(sbi)->s_hash_function(name, len); - - /* Take bits from 7-th to 30-th including both bounds */ - res = GET_HASH_VALUE(res); - if (res == 0) - /* - * Needed to have no names before "." and ".." those have hash - * value == 0 and generation counters 1 and 2 accordingly - */ - res = 128; - - return (res + MAX_GENERATION_NUMBER); -} - -static int -reiserfs_match(struct reiserfs_dir_entry *de, const char *name, int namelen) -{ - int retval = NAME_NOT_FOUND; - - if ((namelen == de->de_namelen) && - !memcmp(de->de_name, name, de->de_namelen)) - retval = (de_visible(de->de_deh + de->de_entry_num) ? - NAME_FOUND : NAME_FOUND_INVISIBLE); - - return (retval); -} - -/* - * de's de_bh, de_ih, de_deh, de_item_num, de_entry_num are set already - * Used when hash collisions exist - */ -static int -linear_search_in_dir_item(struct cpu_key *key, struct reiserfs_dir_entry *de, - const char *name, int namelen) -{ - int i; - int retval; - struct reiserfs_de_head * deh = de->de_deh; - - i = de->de_entry_num; - - if (i == I_ENTRY_COUNT(de->de_ih) || - GET_HASH_VALUE(deh_offset(deh + i)) != - GET_HASH_VALUE(cpu_key_k_offset(key))) { - i--; - } - - /*RFALSE( de->de_deh != B_I_DEH (de->de_bh, de->de_ih), - "vs-7010: array of entry headers not found");*/ - - deh += i; - - for (; i >= 0; i--, deh--) { - if (GET_HASH_VALUE(deh_offset(deh)) != - GET_HASH_VALUE(cpu_key_k_offset(key))) { - /* - * Hash value does not match, no need to check - * whole name - */ - reiserfs_log(LOG_DEBUG, "name `%s' not found\n", name); - return (NAME_NOT_FOUND); - } - - /* Mark that this generation number is used */ - if (de->de_gen_number_bit_string) - set_bit(GET_GENERATION_NUMBER(deh_offset(deh)), - (unsigned long *)de->de_gen_number_bit_string); - - /* Calculate pointer to name and namelen */ - de->de_entry_num = i; - set_de_name_and_namelen(de); - - if ((retval = reiserfs_match(de, name, namelen)) != - NAME_NOT_FOUND) { - /* - * de's de_name, de_namelen, de_recordlen are set. - * Fill the rest: - */ - /* key of pointed object */ - set_de_object_key(de); - store_de_entry_key(de); - - /* retval can be NAME_FOUND or NAME_FOUND_INVISIBLE */ - reiserfs_log(LOG_DEBUG, - "reiserfs_match answered `%d'\n", - retval); - return (retval); - } - } - - if (GET_GENERATION_NUMBER(le_ih_k_offset(de->de_ih)) == 0) - /* - * We have reached left most entry in the node. In common - * we have to go to the left neighbor, but if generation - * counter is 0 already, we know for sure, that there is - * no name with the same hash value - */ - /* FIXME: this work correctly only because hash value can - * not be 0. Btw, in case of Yura's hash it is probably - * possible, so, this is a bug - */ - return (NAME_NOT_FOUND); - - /*RFALSE(de->de_item_num, - "vs-7015: two diritems of the same directory in one node?");*/ - - return (GOTO_PREVIOUS_ITEM); -} - -/* - * May return NAME_FOUND, NAME_FOUND_INVISIBLE, NAME_NOT_FOUND - * FIXME: should add something like IOERROR - */ -static int -reiserfs_find_entry(struct reiserfs_node *dp, const char *name, int namelen, - struct path * path_to_entry, struct reiserfs_dir_entry *de) -{ - struct cpu_key key_to_search; - int retval; - - if (namelen > REISERFS_MAX_NAME(dp->i_reiserfs->s_blocksize)) - return NAME_NOT_FOUND; - - /* We will search for this key in the tree */ - make_cpu_key(&key_to_search, dp, - get_third_component(dp->i_reiserfs, name, namelen), - TYPE_DIRENTRY, 3); - - while (1) { - reiserfs_log(LOG_DEBUG, "search by entry key\n"); - retval = search_by_entry_key(dp->i_reiserfs, &key_to_search, - path_to_entry, de); - if (retval == IO_ERROR) { - reiserfs_log(LOG_DEBUG, "IO error in %s\n", - __FUNCTION__); - return IO_ERROR; - } - - /* Compare names for all entries having given hash value */ - reiserfs_log(LOG_DEBUG, "linear search for `%s'\n", name); - retval = linear_search_in_dir_item(&key_to_search, de, - name, namelen); - if (retval != GOTO_PREVIOUS_ITEM) { - /* - * There is no need to scan directory anymore. - * Given entry found or does not exist - */ - reiserfs_log(LOG_DEBUG, "linear search returned " - "(objectid=%d,dirid=%d)\n", - de->de_objectid, de->de_dir_id); - path_to_entry->pos_in_item = de->de_entry_num; - return retval; - } - - /* - * There is left neighboring item of this directory and - * given entry can be there - */ - set_cpu_key_k_offset(&key_to_search, - le_ih_k_offset(de->de_ih) - 1); - pathrelse(path_to_entry); - } /* while (1) */ -} diff --git a/sys/gnu/fs/reiserfs/reiserfs_prints.c b/sys/gnu/fs/reiserfs/reiserfs_prints.c deleted file mode 100644 index a3c872d..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_prints.c +++ /dev/null @@ -1,307 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#include <gnu/fs/reiserfs/reiserfs_fs.h> - -#if 0 -static char error_buf[1024]; -static char fmt_buf[1024]; -static char off_buf[80]; - -static char * -reiserfs_cpu_offset(struct cpu_key *key) -{ - - if (cpu_key_k_type(key) == TYPE_DIRENTRY) - sprintf(off_buf, "%Lu(%Lu)", - (unsigned long long)GET_HASH_VALUE(cpu_key_k_offset(key)), - (unsigned long long)GET_GENERATION_NUMBER( - cpu_key_k_offset(key))); - else - sprintf(off_buf, "0x%Lx", - (unsigned long long)cpu_key_k_offset(key)); - - return (off_buf); -} - -static char * -le_offset(struct key *key) -{ - int version; - - version = le_key_version(key); - if (le_key_k_type(version, key) == TYPE_DIRENTRY) - sprintf(off_buf, "%Lu(%Lu)", - (unsigned long long)GET_HASH_VALUE( - le_key_k_offset(version, key)), - (unsigned long long)GET_GENERATION_NUMBER( - le_key_k_offset(version, key))); - else - sprintf(off_buf, "0x%Lx", - (unsigned long long)le_key_k_offset(version, key)); - - return (off_buf); -} - -static char * -cpu_type(struct cpu_key *key) -{ - - if (cpu_key_k_type(key) == TYPE_STAT_DATA) - return ("SD"); - if (cpu_key_k_type(key) == TYPE_DIRENTRY) - return ("DIR"); - if (cpu_key_k_type(key) == TYPE_DIRECT) - return ("DIRECT"); - if (cpu_key_k_type(key) == TYPE_INDIRECT) - return ("IND"); - - return ("UNKNOWN"); -} - -static char * -le_type(struct key *key) -{ - int version; - - version = le_key_version(key); - - if (le_key_k_type(version, key) == TYPE_STAT_DATA) - return ("SD"); - if (le_key_k_type(version, key) == TYPE_DIRENTRY) - return ("DIR"); - if (le_key_k_type(version, key) == TYPE_DIRECT) - return ("DIRECT"); - if (le_key_k_type(version, key) == TYPE_INDIRECT) - return ("IND"); - - return ("UNKNOWN"); -} - -/* %k */ -static void -sprintf_le_key(char *buf, struct key *key) -{ - - if (key) - sprintf(buf, "[%d %d %s %s]", le32toh(key->k_dir_id), - le32toh(key->k_objectid), le_offset(key), le_type(key)); - else - sprintf(buf, "[NULL]"); -} - -/* %K */ -static void -sprintf_cpu_key(char *buf, struct cpu_key *key) -{ - - if (key) - sprintf(buf, "[%d %d %s %s]", key->on_disk_key.k_dir_id, - key->on_disk_key.k_objectid, reiserfs_cpu_offset (key), - cpu_type (key)); - else - sprintf(buf, "[NULL]"); -} - -static void sprintf_de_head(char *buf, struct reiserfs_de_head *deh) -{ - - if (deh) - sprintf(buf, - "[offset=%d dir_id=%d objectid=%d location=%d state=%04x]", - deh_offset(deh), deh_dir_id(deh), - deh_objectid(deh), deh_location(deh), deh_state(deh)); - else - sprintf(buf, "[NULL]"); -} - -static void -sprintf_item_head(char *buf, struct item_head *ih) -{ - - if (ih) { - strcpy(buf, (ih_version(ih) == KEY_FORMAT_3_6) ? - "*3.6* " : "*3.5*"); - sprintf_le_key(buf + strlen(buf), &(ih->ih_key)); - sprintf(buf + strlen(buf), ", item_len %d, item_location %d, " - "free_space(entry_count) %d", - ih_item_len(ih), ih_location(ih), ih_free_space(ih)); - } else - sprintf(buf, "[NULL]"); -} - -static void -sprintf_direntry(char *buf, struct reiserfs_dir_entry *de) -{ - char name[20]; - - memcpy(name, de->de_name, de->de_namelen > 19 ? 19 : de->de_namelen); - name [de->de_namelen > 19 ? 19 : de->de_namelen] = 0; - sprintf(buf, "\"%s\" ==> [%d %d]", - name, de->de_dir_id, de->de_objectid); -} - -static void -sprintf_block_head(char *buf, struct buf *bp) -{ - - sprintf(buf, "level=%d, nr_items=%d, free_space=%d rdkey ", - B_LEVEL(bp), B_NR_ITEMS(bp), B_FREE_SPACE(bp)); -} - -static void -sprintf_disk_child(char *buf, struct disk_child *dc) -{ - - sprintf (buf, "[dc_number=%d, dc_size=%u]", - dc_block_number(dc), dc_size(dc)); -} - -static char * -is_there_reiserfs_struct (char *fmt, int *what, int *skip) -{ - char *k; - - k = fmt; - *skip = 0; - - while ((k = strchr(k, '%')) != NULL) { - if (k[1] == 'k' || k[1] == 'K' || k[1] == 'h' || k[1] == 't' || - k[1] == 'z' || k[1] == 'b' || k[1] == 'y' || k[1] == 'a' ) { - *what = k[1]; - break; - } - (*skip)++; - k++; - } - - return (k); -} - -static void -prepare_error_buf(const char *fmt, va_list args) -{ - char *fmt1, *k, *p; - int i, j, what, skip; - - fmt1 = fmt_buf; - p = error_buf; - strcpy (fmt1, fmt); - - while ((k = is_there_reiserfs_struct(fmt1, &what, &skip)) != NULL) { - *k = 0; - - p += vsprintf (p, fmt1, args); - - for (i = 0; i < skip; i ++) - j = va_arg(args, int); - - switch (what) { - case 'k': - sprintf_le_key(p, va_arg(args, struct key *)); - break; - case 'K': - sprintf_cpu_key(p, va_arg(args, struct cpu_key *)); - break; - case 'h': - sprintf_item_head(p, va_arg(args, struct item_head *)); - break; - case 't': - sprintf_direntry(p, - va_arg(args, struct reiserfs_dir_entry *)); - break; - case 'y': - sprintf_disk_child(p, - va_arg(args, struct disk_child *)); - break; - case 'z': - sprintf_block_head(p, - va_arg(args, struct buffer_head *)); - break; - case 'a': - sprintf_de_head(p, - va_arg(args, struct reiserfs_de_head *)); - break; - } - - p += strlen(p); - fmt1 = k + 2; - } - - vsprintf(p, fmt1, args); -} - -/* - * In addition to usual conversion specifiers this accepts reiserfs - * specific conversion specifiers: - * %k to print little endian key, - * %K to print cpu key, - * %h to print item_head, - * %t to print directory entry, - * %z to print block head (arg must be struct buf *) - */ - -#define do_reiserfs_warning(fmt) \ -{ \ - va_list args; \ - va_start(args, fmt); \ - prepare_error_buf(fmt, args); \ - va_end(args); \ -} - -void -__reiserfs_log(int level, const char * fmt, ...) -{ - - do_reiserfs_warning(fmt); - log(level, "ReiserFS/%s: %s\n", __FUNCTION__, error_buf); -} - -#endif - -char * -reiserfs_hashname(int code) -{ - - if (code == YURA_HASH) - return ("rupasov"); - if (code == TEA_HASH) - return ("tea"); - if (code == R5_HASH) - return ("r5"); - - return ("unknown"); -} - -void -reiserfs_dump_buffer(caddr_t buf, off_t len) -{ - int i, j; - - log(LOG_DEBUG, "reiserfs: dumping a buffer of %jd bytes\n", - (intmax_t)len); - for (i = 0; i < len; i += 16) { - log(LOG_DEBUG, "%08x: ", i); - for (j = 0; j < 16; j += 2) { - if (i + j >= len) - log(LOG_DEBUG, " "); - else - log(LOG_DEBUG, "%02x%02x ", - buf[i + j] & 0xff, - buf[i + j + 1] & 0xff); - } - for (j = 0; j < 16; ++j) { - if (i + j >= len) - break; - log(LOG_DEBUG, "%c", - isprint(buf[i + j]) ? buf[i + j] : '.'); - } - log(LOG_DEBUG, "\n"); - } -} diff --git a/sys/gnu/fs/reiserfs/reiserfs_stree.c b/sys/gnu/fs/reiserfs/reiserfs_stree.c deleted file mode 100644 index d1d775c..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_stree.c +++ /dev/null @@ -1,760 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#include <gnu/fs/reiserfs/reiserfs_fs.h> - -/* Minimal possible key. It is never in the tree. */ -const struct key MIN_KEY = { - 0, - 0, - { {0, 0}, } -}; - -/* Maximal possible key. It is never in the tree. */ -const struct key MAX_KEY = { - 0xffffffff, - 0xffffffff, - { {0xffffffff, 0xffffffff }, } -}; - -/* Does the buffer contain a disk block which is in the tree. */ -int -B_IS_IN_TREE(const struct buf *p_s_bp) -{ - - return (B_LEVEL(p_s_bp) != FREE_LEVEL); -} - -/* To gets item head in le form */ -void -copy_item_head(struct item_head *p_v_to, const struct item_head *p_v_from) -{ - - memcpy(p_v_to, p_v_from, IH_SIZE); -} - -/* - * k1 is pointer to on-disk structure which is stored in little-endian - * form. k2 is pointer to cpu variable. For key of items of the same - * object this returns 0. - * Returns: -1 if key1 < key2, 0 if key1 == key2 or 1 if key1 > key2 - */ -/*inline*/ int -comp_short_keys(const struct key *le_key, const struct cpu_key *cpu_key) -{ - const uint32_t *p_s_le_u32, *p_s_cpu_u32; - int n_key_length = REISERFS_SHORT_KEY_LEN; - - p_s_le_u32 = (const uint32_t *)le_key; - p_s_cpu_u32 = (const uint32_t *)&cpu_key->on_disk_key; - for(; n_key_length--; ++p_s_le_u32, ++p_s_cpu_u32) { - if (le32toh(*p_s_le_u32) < *p_s_cpu_u32) - return (-1); - if (le32toh(*p_s_le_u32) > *p_s_cpu_u32) - return (1); - } - - return (0); -} - -/* - * k1 is pointer to on-disk structure which is stored in little-endian - * form. k2 is pointer to cpu variable. Compare keys using all 4 key - * fields. - * Returns: -1 if key1 < key2, 0 if key1 = key2 or 1 if key1 > key2 - */ -/*inline*/ int -comp_keys(const struct key *le_key, const struct cpu_key *cpu_key) -{ - int retval; - - retval = comp_short_keys(le_key, cpu_key); - if (retval) - return retval; - - if (le_key_k_offset(le_key_version(le_key), le_key) < - cpu_key_k_offset(cpu_key)) - return (-1); - if (le_key_k_offset(le_key_version(le_key), le_key) > - cpu_key_k_offset(cpu_key)) - return (1); - - if (cpu_key->key_length == 3) - return (0); - - /* This part is needed only when tail conversion is in progress */ - if (le_key_k_type(le_key_version(le_key), le_key) < - cpu_key_k_type(cpu_key)) - return (-1); - - if (le_key_k_type(le_key_version(le_key), le_key) > - cpu_key_k_type(cpu_key)) - return (1); - - return (0); -} - -/* Release all buffers in the path. */ -void -pathrelse(struct path *p_s_search_path) -{ - struct buf *bp; - int n_path_offset = p_s_search_path->path_length; - - while (n_path_offset > ILLEGAL_PATH_ELEMENT_OFFSET) { - bp = PATH_OFFSET_PBUFFER(p_s_search_path, n_path_offset--); - free(bp->b_data, M_REISERFSPATH); - free(bp, M_REISERFSPATH); - } - - p_s_search_path->path_length = ILLEGAL_PATH_ELEMENT_OFFSET; -} - -/* - * This does not say which one is bigger, it only returns 1 if keys - * are not equal, 0 otherwise - */ -int -comp_le_keys(const struct key *k1, const struct key *k2) -{ - - return (memcmp(k1, k2, sizeof(struct key))); -} - -/* - * Binary search toolkit function. Search for an item in the array by - * the item key. - * Returns: 1 if found, 0 if not found; - * *p_n_pos = number of the searched element if found, else the - * number of the first element that is larger than p_v_key. - */ -/* - * For those not familiar with binary search: n_lbound is the leftmost - * item that it could be, n_rbound the rightmost item that it could be. - * We examine the item halfway between n_lbound and n_rbound, and that - * tells us either that we can increase n_lbound, or decrease n_rbound, - * or that we have found it, or if n_lbound <= n_rbound that there are - * no possible items, and we have not found it. With each examination we - * cut the number of possible items it could be by one more than half - * rounded down, or we find it. - */ -int -bin_search(const void *p_v_key, /* Key to search for. */ - const void *p_v_base, /* First item in the array. */ - int p_n_num, /* Number of items in the array. */ - int p_n_width, /* Item size in the array. searched. Lest the - reader be confused, note that this is crafted - as a general function, and when it is applied - specifically to the array of item headers in - a node, p_n_width is actually the item header - size not the item size. */ - int *p_n_pos) /* Number of the searched for element. */ -{ - int n_rbound, n_lbound, n_j; - - for (n_j = ((n_rbound = p_n_num - 1) + (n_lbound = 0)) / 2; - n_lbound <= n_rbound; n_j = (n_rbound + n_lbound) / 2) { - switch (COMP_KEYS((const struct key *) - ((const char *)p_v_base + n_j * p_n_width), - (const struct cpu_key *)p_v_key)) { - case -1: - n_lbound = n_j + 1; - continue; - case 1: - n_rbound = n_j - 1; - continue; - case 0: - *p_n_pos = n_j; - return (ITEM_FOUND); /* Key found in the array. */ - } - } - - /* - * bin_search did not find given key, it returns position of key, - * that is minimal and greater than the given one. - */ - *p_n_pos = n_lbound; - return (ITEM_NOT_FOUND); -} - -/* - * Get delimiting key of the buffer by looking for it in the buffers in - * the path, starting from the bottom of the path, and going upwards. We - * must check the path's validity at each step. If the key is not in the - * path, there is no delimiting key in the tree (buffer is first or last - * buffer in tree), and in this case we return a special key, either - * MIN_KEY or MAX_KEY. - */ -const struct key * -get_lkey(const struct path *p_s_chk_path, - const struct reiserfs_sb_info *p_s_sbi) -{ - struct buf *p_s_parent; - int n_position, n_path_offset = p_s_chk_path->path_length; - - /* While not higher in path than first element. */ - while (n_path_offset-- > FIRST_PATH_ELEMENT_OFFSET) { - /* Parent at the path is not in the tree now. */ - if (!B_IS_IN_TREE(p_s_parent = - PATH_OFFSET_PBUFFER(p_s_chk_path, n_path_offset))) - return (&MAX_KEY); - - /* Check whether position in the parent is correct. */ - if ((n_position = PATH_OFFSET_POSITION(p_s_chk_path, - n_path_offset)) > B_NR_ITEMS(p_s_parent)) - return (&MAX_KEY); - - /* - * Check whether parent at the path really points to - * the child. - */ - if (B_N_CHILD_NUM(p_s_parent, n_position) != - (PATH_OFFSET_PBUFFER(p_s_chk_path, - n_path_offset + 1)->b_blkno - / btodb(p_s_sbi->s_blocksize))) - return (&MAX_KEY); - - /* - * Return delimiting key if position in the parent is not - * equal to zero. - */ - if (n_position) - return (B_N_PDELIM_KEY(p_s_parent, n_position - 1)); - } - - /* Return MIN_KEY if we are in the root of the buffer tree. */ - if ((PATH_OFFSET_PBUFFER(p_s_chk_path, - FIRST_PATH_ELEMENT_OFFSET)->b_blkno - / btodb(p_s_sbi->s_blocksize)) == SB_ROOT_BLOCK(p_s_sbi)) - return (&MIN_KEY); - - return (&MAX_KEY); -} - -/* Get delimiting key of the buffer at the path and its right neighbor. */ -const struct key * -get_rkey(const struct path *p_s_chk_path, - const struct reiserfs_sb_info *p_s_sbi) -{ - struct buf *p_s_parent; - int n_position, n_path_offset = p_s_chk_path->path_length; - - while (n_path_offset-- > FIRST_PATH_ELEMENT_OFFSET) { - /* Parent at the path is not in the tree now. */ - if (!B_IS_IN_TREE(p_s_parent = - PATH_OFFSET_PBUFFER(p_s_chk_path, n_path_offset))) - return (&MIN_KEY); - - /* Check whether position in the parent is correct. */ - if ((n_position = PATH_OFFSET_POSITION(p_s_chk_path, - n_path_offset)) > - B_NR_ITEMS(p_s_parent)) - return (&MIN_KEY); - - /* - * Check whether parent at the path really points to the - * child. - */ - if (B_N_CHILD_NUM(p_s_parent, n_position) != - (PATH_OFFSET_PBUFFER(p_s_chk_path, - n_path_offset + 1)->b_blkno - / btodb(p_s_sbi->s_blocksize))) - return (&MIN_KEY); - - /* - * Return delimiting key if position in the parent is not - * the last one. - */ - if (n_position != B_NR_ITEMS(p_s_parent)) - return (B_N_PDELIM_KEY(p_s_parent, n_position)); - } - - /* Return MAX_KEY if we are in the root of the buffer tree. */ - if ((PATH_OFFSET_PBUFFER(p_s_chk_path, - FIRST_PATH_ELEMENT_OFFSET)->b_blkno - / btodb(p_s_sbi->s_blocksize)) == SB_ROOT_BLOCK(p_s_sbi)) - return (&MAX_KEY); - - return (&MIN_KEY); -} - -int -reiserfs_check_path(struct path *p) -{ - - if (p->path_length != ILLEGAL_PATH_ELEMENT_OFFSET) - reiserfs_log(LOG_WARNING, "path not properly relsed\n"); - return (0); -} - -/* - * Check whether a key is contained in the tree rooted from a buffer at - * a path. This works by looking at the left and right delimiting keys - * for the buffer in the last path_element in the path. These delimiting - * keys are stored at least one level above that buffer in the tree. - * If the buffer is the first or last node in the tree order then one - * of the delimiting keys may be absent, and in this case get_lkey and - * get_rkey return a special key which is MIN_KEY or MAX_KEY. - */ -static inline int -key_in_buffer( - struct path *p_s_chk_path, /* Path which should be checked. */ - const struct cpu_key *p_s_key, /* Key which should be checked. */ - struct reiserfs_sb_info *p_s_sbi) /* Super block pointer. */ -{ - - if (COMP_KEYS(get_lkey(p_s_chk_path, p_s_sbi), p_s_key) == 1) - /* left delimiting key is bigger, that the key we look for */ - return (0); - - if (COMP_KEYS(get_rkey(p_s_chk_path, p_s_sbi), p_s_key) != 1) - /* p_s_key must be less than right delimitiing key */ - return (0); - - return (1); -} - -#if 0 -/* XXX Il ne semble pas y avoir de compteur de référence dans struct buf */ -inline void -decrement_bcount(struct buf *p_s_bp) -{ - - if (p_s_bp) { - if (atomic_read(&(p_s_bp->b_count))) { - put_bh(p_s_bp); - return; - } - } -} -#endif - -/* Decrement b_count field of the all buffers in the path. */ -void -decrement_counters_in_path(struct path *p_s_search_path) -{ - - pathrelse(p_s_search_path); -#if 0 - int n_path_offset = p_s_search_path->path_length; - - while (n_path_offset > ILLEGAL_PATH_ELEMENT_OFFSET) { - struct buf *bp; - - bp = PATH_OFFSET_PBUFFER(p_s_search_path, n_path_offset--); - decrement_bcount(bp); - } - - p_s_search_path->path_length = ILLEGAL_PATH_ELEMENT_OFFSET; -#endif -} - -static int -is_leaf(char *buf, int blocksize, struct buf *bp) -{ - struct item_head *ih; - struct block_head *blkh; - int used_space, prev_location, i, nr; - - blkh = (struct block_head *)buf; - if (blkh_level(blkh) != DISK_LEAF_NODE_LEVEL) { - reiserfs_log(LOG_WARNING, "this should be caught earlier"); - return (0); - } - - nr = blkh_nr_item(blkh); - if (nr < 1 || nr > - ((blocksize - BLKH_SIZE) / (IH_SIZE + MIN_ITEM_LEN))) { - /* Item number is too big or too small */ - reiserfs_log(LOG_WARNING, "nr_item seems wrong\n"); - return (0); - } - - ih = (struct item_head *)(buf + BLKH_SIZE) + nr - 1; - used_space = BLKH_SIZE + IH_SIZE * nr + (blocksize - ih_location(ih)); - if (used_space != blocksize - blkh_free_space(blkh)) { - /* - * Free space does not match to calculated amount of - * use space - */ - reiserfs_log(LOG_WARNING, "free space seems wrong\n"); - return (0); - } - - /* FIXME: it is_leaf will hit performance too much - we may have - * return 1 here */ - - /* Check tables of item heads */ - ih = (struct item_head *)(buf + BLKH_SIZE); - prev_location = blocksize; - for (i = 0; i < nr; i++, ih++) { - if (le_ih_k_type(ih) == TYPE_ANY) { - reiserfs_log(LOG_WARNING, - "wrong item type for item\n"); - return (0); - } - if (ih_location(ih) >= blocksize || - ih_location(ih) < IH_SIZE * nr) { - reiserfs_log(LOG_WARNING, - "item location seems wrong\n"); - return (0); - } - if (ih_item_len(ih) < 1 || - ih_item_len(ih) > MAX_ITEM_LEN(blocksize)) { - reiserfs_log(LOG_WARNING, "item length seems wrong\n"); - return (0); - } - if (prev_location - ih_location(ih) != ih_item_len(ih)) { - reiserfs_log(LOG_WARNING, - "item location seems wrong (second one)\n"); - return (0); - } - prev_location = ih_location(ih); - } - - /* One may imagine much more checks */ - return 1; -} - -/* Returns 1 if buf looks like an internal node, 0 otherwise */ -static int -is_internal(char *buf, int blocksize, struct buf *bp) -{ - int nr, used_space; - struct block_head *blkh; - - blkh = (struct block_head *)buf; - nr = blkh_level(blkh); - if (nr <= DISK_LEAF_NODE_LEVEL || nr > MAX_HEIGHT) { - /* This level is not possible for internal nodes */ - reiserfs_log(LOG_WARNING, "this should be caught earlier\n"); - return (0); - } - - nr = blkh_nr_item(blkh); - if (nr > (blocksize - BLKH_SIZE - DC_SIZE) / (KEY_SIZE + DC_SIZE)) { - /* - * For internal which is not root we might check min - * number of keys - */ - reiserfs_log(LOG_WARNING, "number of key seems wrong\n"); - return (0); - } - - used_space = BLKH_SIZE + KEY_SIZE * nr + DC_SIZE * (nr + 1); - if (used_space != blocksize - blkh_free_space(blkh)) { - reiserfs_log(LOG_WARNING, - "is_internal: free space seems wrong\n"); - return (0); - } - - /* One may imagine much more checks */ - return (1); -} - -/* - * Make sure that bh contains formatted node of reiserfs tree of - * 'level'-th level - */ -static int -is_tree_node(struct buf *bp, int level) -{ - if (B_LEVEL(bp) != level) { - reiserfs_log(LOG_WARNING, - "node level (%d) doesn't match to the " - "expected one (%d)\n", B_LEVEL (bp), level); - return (0); - } - - if (level == DISK_LEAF_NODE_LEVEL) - return (is_leaf(bp->b_data, bp->b_bcount, bp)); - - return (is_internal(bp->b_data, bp->b_bcount, bp)); -} - -int -search_by_key(struct reiserfs_sb_info *p_s_sbi, - const struct cpu_key * p_s_key, /* Key to search. */ - struct path * p_s_search_path, /* This structure was allocated and - initialized by the calling function. - It is filled up by this function. */ - int n_stop_level) /* How far down the tree to search. To - stop at leaf level - set to - DISK_LEAF_NODE_LEVEL */ -{ - int error; - int n_node_level, n_retval; - int n_block_number, expected_level, fs_gen; - struct path_element *p_s_last_element; - struct buf *p_s_bp, *tmp_bp; - - /* - * As we add each node to a path we increase its count. This means that - * we must be careful to release all nodes in a path before we either - * discard the path struct or re-use the path struct, as we do here. - */ - decrement_counters_in_path(p_s_search_path); - - /* - * With each iteration of this loop we search through the items in the - * current node, and calculate the next current node(next path element) - * for the next iteration of this loop... - */ - n_block_number = SB_ROOT_BLOCK(p_s_sbi); - expected_level = -1; - - reiserfs_log(LOG_DEBUG, "root block: #%d\n", n_block_number); - - while (1) { - /* Prep path to have another element added to it. */ - reiserfs_log(LOG_DEBUG, "path element #%d\n", - p_s_search_path->path_length); - p_s_last_element = PATH_OFFSET_PELEMENT(p_s_search_path, - ++p_s_search_path->path_length); - fs_gen = get_generation(p_s_sbi); - - /* - * Read the next tree node, and set the last element in the - * path to have a pointer to it. - */ - reiserfs_log(LOG_DEBUG, "reading block #%d\n", - n_block_number); - if ((error = bread(p_s_sbi->s_devvp, - n_block_number * btodb(p_s_sbi->s_blocksize), - p_s_sbi->s_blocksize, NOCRED, &tmp_bp)) != 0) { - reiserfs_log(LOG_DEBUG, "error reading block\n"); - p_s_search_path->path_length--; - pathrelse(p_s_search_path); - return (IO_ERROR); - } - reiserfs_log(LOG_DEBUG, "blkno = %ju, lblkno = %ju\n", - (intmax_t)tmp_bp->b_blkno, (intmax_t)tmp_bp->b_lblkno); - - /* - * As i didn't found a way to handle the lock correctly, - * i copy the data into a fake buffer - */ - reiserfs_log(LOG_DEBUG, "allocating p_s_bp\n"); - p_s_bp = malloc(sizeof *p_s_bp, M_REISERFSPATH, M_WAITOK); - if (!p_s_bp) { - reiserfs_log(LOG_DEBUG, "error allocating memory\n"); - p_s_search_path->path_length--; - pathrelse(p_s_search_path); - brelse(tmp_bp); - return (IO_ERROR); - } - reiserfs_log(LOG_DEBUG, "copying struct buf\n"); - bcopy(tmp_bp, p_s_bp, sizeof(struct buf)); - - reiserfs_log(LOG_DEBUG, "allocating p_s_bp->b_data\n"); - p_s_bp->b_data = malloc(p_s_sbi->s_blocksize, - M_REISERFSPATH, M_WAITOK); - if (!p_s_bp->b_data) { - reiserfs_log(LOG_DEBUG, "error allocating memory\n"); - p_s_search_path->path_length--; - pathrelse(p_s_search_path); - free(p_s_bp, M_REISERFSPATH); - brelse(tmp_bp); - return (IO_ERROR); - } - reiserfs_log(LOG_DEBUG, "copying buffer data\n"); - bcopy(tmp_bp->b_data, p_s_bp->b_data, p_s_sbi->s_blocksize); - brelse(tmp_bp); - tmp_bp = NULL; - - reiserfs_log(LOG_DEBUG, "...done\n"); - p_s_last_element->pe_buffer = p_s_bp; - - if (expected_level == -1) - expected_level = SB_TREE_HEIGHT(p_s_sbi); - expected_level--; - reiserfs_log(LOG_DEBUG, "expected level: %d (%d)\n", - expected_level, SB_TREE_HEIGHT(p_s_sbi)); - - /* XXX */ - /* - * It is possible that schedule occurred. We must check - * whether the key to search is still in the tree rooted - * from the current buffer. If not then repeat search - * from the root. - */ - if (fs_changed(fs_gen, p_s_sbi) && - (!B_IS_IN_TREE(p_s_bp) || - B_LEVEL(p_s_bp) != expected_level || - !key_in_buffer(p_s_search_path, p_s_key, p_s_sbi))) { - reiserfs_log(LOG_DEBUG, - "the key isn't in the tree anymore\n"); - decrement_counters_in_path(p_s_search_path); - - /* - * Get the root block number so that we can repeat - * the search starting from the root. - */ - n_block_number = SB_ROOT_BLOCK(p_s_sbi); - expected_level = -1; - - /* Repeat search from the root */ - continue; - } - - /* - * Make sure, that the node contents look like a node of - * certain level - */ - if (!is_tree_node(p_s_bp, expected_level)) { - reiserfs_log(LOG_WARNING, - "invalid format found in block %ju. Fsck?", - (intmax_t)p_s_bp->b_blkno); - pathrelse (p_s_search_path); - return (IO_ERROR); - } - - /* Ok, we have acquired next formatted node in the tree */ - n_node_level = B_LEVEL(p_s_bp); - reiserfs_log(LOG_DEBUG, "block info:\n"); - reiserfs_log(LOG_DEBUG, " node level: %d\n", - n_node_level); - reiserfs_log(LOG_DEBUG, " nb of items: %d\n", - B_NR_ITEMS(p_s_bp)); - reiserfs_log(LOG_DEBUG, " free space: %d bytes\n", - B_FREE_SPACE(p_s_bp)); - reiserfs_log(LOG_DEBUG, "bin_search with :\n" - " p_s_key = (objectid=%d, dirid=%d)\n" - " B_NR_ITEMS(p_s_bp) = %d\n" - " p_s_last_element->pe_position = %d (path_length = %d)\n", - p_s_key->on_disk_key.k_objectid, - p_s_key->on_disk_key.k_dir_id, - B_NR_ITEMS(p_s_bp), - p_s_last_element->pe_position, - p_s_search_path->path_length); - n_retval = bin_search(p_s_key, B_N_PITEM_HEAD(p_s_bp, 0), - B_NR_ITEMS(p_s_bp), - (n_node_level == DISK_LEAF_NODE_LEVEL) ? IH_SIZE : KEY_SIZE, - &(p_s_last_element->pe_position)); - reiserfs_log(LOG_DEBUG, "bin_search result: %d\n", - n_retval); - if (n_node_level == n_stop_level) { - reiserfs_log(LOG_DEBUG, "stop level reached (%s)\n", - n_retval == ITEM_FOUND ? "found" : "not found"); - return (n_retval); - } - - /* We are not in the stop level */ - if (n_retval == ITEM_FOUND) - /* - * Item has been found, so we choose the pointer - * which is to the right of the found one - */ - p_s_last_element->pe_position++; - - /* - * If item was not found we choose the position which is - * to the left of the found item. This requires no code, - * bin_search did it already. - */ - - /* - * So we have chosen a position in the current node which - * is an internal node. Now we calculate child block number - * by position in the node. - */ - n_block_number = B_N_CHILD_NUM(p_s_bp, - p_s_last_element->pe_position); - } - - reiserfs_log(LOG_DEBUG, "done\n"); - return (0); -} - -/* - * Form the path to an item and position in this item which contains - * file byte defined by p_s_key. If there is no such item corresponding - * to the key, we point the path to the item with maximal key less than - * p_s_key, and *p_n_pos_in_item is set to one past the last entry/byte - * in the item. If searching for entry in a directory item, and it is - * not found, *p_n_pos_in_item is set to one entry more than the entry - * with maximal key which is less than the sought key. - * - * Note that if there is no entry in this same node which is one more, - * then we point to an imaginary entry. For direct items, the position - * is in units of bytes, for indirect items the position is in units - * of blocknr entries, for directory items the position is in units of - * directory entries. - */ - -/* The function is NOT SCHEDULE-SAFE! */ -int -search_for_position_by_key(struct reiserfs_sb_info *p_s_sbi, - const struct cpu_key *p_cpu_key, /* Key to search (cpu variable) */ - struct path *p_s_search_path) /* Filled up by this function. */ -{ - int retval, n_blk_size; - off_t item_offset, offset; - struct item_head *p_le_ih; /* Pointer to on-disk structure */ - struct reiserfs_dir_entry de; - - /* If searching for directory entry. */ - if (is_direntry_cpu_key(p_cpu_key)) - return (search_by_entry_key(p_s_sbi, p_cpu_key, - p_s_search_path, &de)); - - /* If not searching for directory entry. */ - - /* If item is found. */ - retval = search_item(p_s_sbi, p_cpu_key, p_s_search_path); - if (retval == IO_ERROR) - return (retval); - if (retval == ITEM_FOUND) { - if (ih_item_len(B_N_PITEM_HEAD( - PATH_PLAST_BUFFER(p_s_search_path), - PATH_LAST_POSITION(p_s_search_path))) == 0) { - reiserfs_log(LOG_WARNING, "item length equals zero\n"); - } - - pos_in_item(p_s_search_path) = 0; - return (POSITION_FOUND); - } - - if (PATH_LAST_POSITION(p_s_search_path) == 0) { - reiserfs_log(LOG_WARNING, "position equals zero\n"); - } - - /* Item is not found. Set path to the previous item. */ - p_le_ih = B_N_PITEM_HEAD(PATH_PLAST_BUFFER(p_s_search_path), - --PATH_LAST_POSITION(p_s_search_path)); - n_blk_size = p_s_sbi->s_blocksize; - - if (comp_short_keys(&(p_le_ih->ih_key), p_cpu_key)) { - return (FILE_NOT_FOUND); - } - - item_offset = le_ih_k_offset(p_le_ih); - offset = cpu_key_k_offset(p_cpu_key); - - /* Needed byte is contained in the item pointed to by the path.*/ - if (item_offset <= offset && - item_offset + op_bytes_number(p_le_ih, n_blk_size) > offset) { - pos_in_item(p_s_search_path) = offset - item_offset; - if (is_indirect_le_ih(p_le_ih)) { - pos_in_item(p_s_search_path) /= n_blk_size; - } - return (POSITION_FOUND); - } - - /* Needed byte is not contained in the item pointed to by the - * path. Set pos_in_item out of the item. */ - if (is_indirect_le_ih(p_le_ih)) - pos_in_item(p_s_search_path) = - ih_item_len(p_le_ih) / UNFM_P_SIZE; - else - pos_in_item(p_s_search_path) = - ih_item_len(p_le_ih); - - return (POSITION_NOT_FOUND); -} diff --git a/sys/gnu/fs/reiserfs/reiserfs_vfsops.c b/sys/gnu/fs/reiserfs/reiserfs_vfsops.c deleted file mode 100644 index 0c351dc..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_vfsops.c +++ /dev/null @@ -1,1136 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#include <gnu/fs/reiserfs/reiserfs_fs.h> - -const char reiserfs_3_5_magic_string[] = REISERFS_SUPER_MAGIC_STRING; -const char reiserfs_3_6_magic_string[] = REISER2FS_SUPER_MAGIC_STRING; -const char reiserfs_jr_magic_string[] = REISER2FS_JR_SUPER_MAGIC_STRING; - -/* - * Default recommended I/O size is 128k. There might be broken - * applications that are confused by this. Use nolargeio mount option to - * get usual i/o size = PAGE_SIZE. - */ -int reiserfs_default_io_size = 128 * 1024; - -static vfs_cmount_t reiserfs_cmount; -static vfs_fhtovp_t reiserfs_fhtovp; -static vfs_mount_t reiserfs_mount; -static vfs_root_t reiserfs_root; -static vfs_statfs_t reiserfs_statfs; -static vfs_unmount_t reiserfs_unmount; - -static int reiserfs_mountfs(struct vnode *devvp, struct mount *mp, - struct thread *td); -static void load_bitmap_info_data(struct reiserfs_sb_info *sbi, - struct reiserfs_bitmap_info *bi); -static int read_bitmaps(struct reiserfs_mount *rmp); -static int read_old_bitmaps(struct reiserfs_mount *rmp); -static int read_super_block(struct reiserfs_mount *rmp, int offset); -static hashf_t hash_function(struct reiserfs_mount *rmp); - -static int get_root_node(struct reiserfs_mount *rmp, - struct reiserfs_node **root); -uint32_t find_hash_out(struct reiserfs_mount *rmp); - -MALLOC_DEFINE(M_REISERFSMNT, "reiserfs_mount", "ReiserFS mount structure"); -MALLOC_DEFINE(M_REISERFSPATH, "reiserfs_path", "ReiserFS path structure"); -MALLOC_DEFINE(M_REISERFSNODE, "reiserfs_node", "ReiserFS vnode private part"); - -/* ------------------------------------------------------------------- - * VFS operations - * -------------------------------------------------------------------*/ - -static int -reiserfs_cmount(struct mntarg *ma, void *data, uint64_t flags) -{ - struct reiserfs_args args; - struct export_args exp; - int error; - - error = copyin(data, &args, sizeof(args)); - if (error) - return (error); - vfs_oexport_conv(&args.export, &exp); - - ma = mount_argsu(ma, "from", args.fspec, MAXPATHLEN); - ma = mount_arg(ma, "export", &exp, sizeof(exp)); - - error = kernel_mount(ma, flags); - - return (error); -} - -/* - * Mount system call - */ -static int -reiserfs_mount(struct mount *mp) -{ - size_t size; - int error, len; - accmode_t accmode; - char *path, *fspec; - struct vnode *devvp; - struct vfsoptlist *opts; - struct reiserfs_mount *rmp; - struct reiserfs_sb_info *sbi; - struct nameidata nd, *ndp = &nd; - struct thread *td; - - td = curthread; - if (!(mp->mnt_flag & MNT_RDONLY)) - return EROFS; - - /* Get the new options passed to mount */ - opts = mp->mnt_optnew; - - /* `fspath' contains the mount point (eg. /mnt/linux); REQUIRED */ - vfs_getopt(opts, "fspath", (void **)&path, NULL); - reiserfs_log(LOG_INFO, "mount point is `%s'\n", path); - - /* `from' contains the device name (eg. /dev/ad0s1); REQUIRED */ - fspec = NULL; - error = vfs_getopt(opts, "from", (void **)&fspec, &len); - if (!error && fspec[len - 1] != '\0') - return (EINVAL); - reiserfs_log(LOG_INFO, "device is `%s'\n", fspec); - - /* Handle MNT_UPDATE (mp->mnt_flag) */ - if (mp->mnt_flag & MNT_UPDATE) { - /* For now, only NFS export is supported. */ - if (vfs_flagopt(opts, "export", NULL, 0)) - return (0); - } - - /* Not an update, or updating the name: look up the name - * and verify that it refers to a sensible disk device. */ - if (fspec == NULL) - return (EINVAL); - - NDINIT(ndp, LOOKUP, FOLLOW | LOCKLEAF, UIO_SYSSPACE, fspec, td); - if ((error = namei(ndp)) != 0) - return (error); - NDFREE(ndp, NDF_ONLY_PNBUF); - devvp = ndp->ni_vp; - - if (!vn_isdisk(devvp, &error)) { - vput(devvp); - return (error); - } - - /* If mount by non-root, then verify that user has necessary - * permissions on the device. */ - accmode = VREAD; - if ((mp->mnt_flag & MNT_RDONLY) == 0) - accmode |= VWRITE; - error = VOP_ACCESS(devvp, accmode, td->td_ucred, td); - if (error) - error = priv_check(td, PRIV_VFS_MOUNT_PERM); - if (error) { - vput(devvp); - return (error); - } - - if ((mp->mnt_flag & MNT_UPDATE) == 0) { - error = reiserfs_mountfs(devvp, mp, td); - } else { - /* TODO Handle MNT_UPDATE */ - vput(devvp); - return (EOPNOTSUPP); - } - - if (error) { - vrele(devvp); - return (error); - } - - rmp = VFSTOREISERFS(mp); - sbi = rmp->rm_reiserfs; - - /* - * Note that this strncpy() is ok because of a check at the start - * of reiserfs_mount(). - */ - reiserfs_log(LOG_DEBUG, "prepare statfs data\n"); - (void)copystr(fspec, mp->mnt_stat.f_mntfromname, MNAMELEN - 1, &size); - bzero(mp->mnt_stat.f_mntfromname + size, MNAMELEN - size); - (void)reiserfs_statfs(mp, &mp->mnt_stat); - - reiserfs_log(LOG_DEBUG, "done\n"); - return (0); -} - -/* - * Unmount system call - */ -static int -reiserfs_unmount(struct mount *mp, int mntflags) -{ - int error, flags = 0; - struct reiserfs_mount *rmp; - struct reiserfs_sb_info *sbi; - - reiserfs_log(LOG_DEBUG, "get private data\n"); - rmp = VFSTOREISERFS(mp); - sbi = rmp->rm_reiserfs; - - /* Flangs handling */ - reiserfs_log(LOG_DEBUG, "handle mntflags\n"); - if (mntflags & MNT_FORCE) - flags |= FORCECLOSE; - - /* Flush files -> vflush */ - reiserfs_log(LOG_DEBUG, "flush vnodes\n"); - if ((error = vflush(mp, 0, flags, curthread))) - return (error); - - /* XXX Super block update */ - - if (sbi) { - if (SB_AP_BITMAP(sbi)) { - int i; - reiserfs_log(LOG_DEBUG, - "release bitmap buffers (total: %d)\n", - SB_BMAP_NR(sbi)); - for (i = 0; i < SB_BMAP_NR(sbi); i++) { - if (SB_AP_BITMAP(sbi)[i].bp_data) { - free(SB_AP_BITMAP(sbi)[i].bp_data, - M_REISERFSMNT); - SB_AP_BITMAP(sbi)[i].bp_data = NULL; - } - } - - reiserfs_log(LOG_DEBUG, "free bitmaps structure\n"); - free(SB_AP_BITMAP(sbi), M_REISERFSMNT); - SB_AP_BITMAP(sbi) = NULL; - } - - if (sbi->s_rs) { - reiserfs_log(LOG_DEBUG, "free super block data\n"); - free(sbi->s_rs, M_REISERFSMNT); - sbi->s_rs = NULL; - } - } - - reiserfs_log(LOG_DEBUG, "close device\n"); -#if defined(si_mountpoint) - rmp->rm_devvp->v_rdev->si_mountpoint = NULL; -#endif - - DROP_GIANT(); - g_topology_lock(); - g_vfs_close(rmp->rm_cp); - g_topology_unlock(); - PICKUP_GIANT(); - vrele(rmp->rm_devvp); - dev_rel(rmp->rm_dev); - - if (sbi) { - reiserfs_log(LOG_DEBUG, "free sbi\n"); - free(sbi, M_REISERFSMNT); - sbi = rmp->rm_reiserfs = NULL; - } - if (rmp) { - reiserfs_log(LOG_DEBUG, "free rmp\n"); - free(rmp, M_REISERFSMNT); - rmp = NULL; - } - - mp->mnt_data = 0; - MNT_ILOCK(mp); - mp->mnt_flag &= ~MNT_LOCAL; - MNT_IUNLOCK(mp); - - reiserfs_log(LOG_DEBUG, "done\n"); - return (error); -} - -/* - * Return the root of a filesystem. - */ -static int -reiserfs_root(struct mount *mp, int flags, struct vnode **vpp) -{ - int error; - struct vnode *vp; - struct cpu_key rootkey; - - rootkey.on_disk_key.k_dir_id = REISERFS_ROOT_PARENT_OBJECTID; - rootkey.on_disk_key.k_objectid = REISERFS_ROOT_OBJECTID; - - error = reiserfs_iget(mp, &rootkey, &vp, curthread); - - if (error == 0) - *vpp = vp; - return (error); -} - -/* - * The statfs syscall - */ -static int -reiserfs_statfs(struct mount *mp, struct statfs *sbp) -{ - struct reiserfs_mount *rmp; - struct reiserfs_sb_info *sbi; - struct reiserfs_super_block *rs; - - reiserfs_log(LOG_DEBUG, "get private data\n"); - rmp = VFSTOREISERFS(mp); - sbi = rmp->rm_reiserfs; - rs = sbi->s_rs; - - reiserfs_log(LOG_DEBUG, "fill statfs structure\n"); - sbp->f_bsize = sbi->s_blocksize; - sbp->f_iosize = sbp->f_bsize; - sbp->f_blocks = sb_block_count(rs) - sb_bmap_nr(rs) - 1; - sbp->f_bfree = sb_free_blocks(rs); - sbp->f_bavail = sbp->f_bfree; - sbp->f_files = 0; - sbp->f_ffree = 0; - reiserfs_log(LOG_DEBUG, " block size = %ju\n", - (intmax_t)sbp->f_bsize); - reiserfs_log(LOG_DEBUG, " IO size = %ju\n", - (intmax_t)sbp->f_iosize); - reiserfs_log(LOG_DEBUG, " block count = %ju\n", - (intmax_t)sbp->f_blocks); - reiserfs_log(LOG_DEBUG, " free blocks = %ju\n", - (intmax_t)sbp->f_bfree); - reiserfs_log(LOG_DEBUG, " avail blocks = %ju\n", - (intmax_t)sbp->f_bavail); - reiserfs_log(LOG_DEBUG, "...done\n"); - - if (sbp != &mp->mnt_stat) { - reiserfs_log(LOG_DEBUG, "copying monut point info\n"); - sbp->f_type = mp->mnt_vfc->vfc_typenum; - bcopy((caddr_t)mp->mnt_stat.f_mntonname, - (caddr_t)&sbp->f_mntonname[0], MNAMELEN); - bcopy((caddr_t)mp->mnt_stat.f_mntfromname, - (caddr_t)&sbp->f_mntfromname[0], MNAMELEN); - reiserfs_log(LOG_DEBUG, " mount from: %s\n", - sbp->f_mntfromname); - reiserfs_log(LOG_DEBUG, " mount on: %s\n", - sbp->f_mntonname); - reiserfs_log(LOG_DEBUG, "...done\n"); - } - - return (0); -} - -/* - * File handle to vnode - * - * Have to be really careful about stale file handles: - * - check that the inode key is valid - * - call ffs_vget() to get the locked inode - * - check for an unallocated inode (i_mode == 0) - * - check that the given client host has export rights and return - * those rights via. exflagsp and credanonp - */ -static int -reiserfs_fhtovp(struct mount *mp, struct fid *fhp, int flags, - struct vnode **vpp) -{ - int error; - struct rfid *rfhp; - struct vnode *nvp; - struct cpu_key key; - struct reiserfs_node *ip; - struct reiserfs_sb_info *sbi; - struct thread *td = curthread; - - rfhp = (struct rfid *)fhp; - sbi = VFSTOREISERFS(mp)->rm_reiserfs; - - /* Check that the key is valid */ - if (rfhp->rfid_dirid < REISERFS_ROOT_PARENT_OBJECTID && - rfhp->rfid_objectid < REISERFS_ROOT_OBJECTID) - return (ESTALE); - - reiserfs_log(LOG_DEBUG, - "file handle key is (dirid=%d, objectid=%d)\n", - rfhp->rfid_dirid, rfhp->rfid_objectid); - key.on_disk_key.k_dir_id = rfhp->rfid_dirid; - key.on_disk_key.k_objectid = rfhp->rfid_objectid; - - reiserfs_log(LOG_DEBUG, "read this inode\n"); - error = reiserfs_iget(mp, &key, &nvp, td); - if (error) { - *vpp = NULLVP; - return (error); - } - - reiserfs_log(LOG_DEBUG, "check validity\n"); - ip = VTOI(nvp); - if (ip->i_mode == 0 || ip->i_generation != rfhp->rfid_gen) { - vput(nvp); - *vpp = NULLVP; - return (ESTALE); - } - - reiserfs_log(LOG_DEBUG, "return it\n"); - *vpp = nvp; - return (0); -} - -/* ------------------------------------------------------------------- - * Functions for the journal - * -------------------------------------------------------------------*/ - -int -is_reiserfs_3_5(struct reiserfs_super_block *rs) -{ - - return (!strncmp(rs->s_v1.s_magic, reiserfs_3_5_magic_string, - strlen(reiserfs_3_5_magic_string))); -} - -int -is_reiserfs_3_6(struct reiserfs_super_block *rs) -{ - - return (!strncmp(rs->s_v1.s_magic, reiserfs_3_6_magic_string, - strlen(reiserfs_3_6_magic_string))); -} - -int -is_reiserfs_jr(struct reiserfs_super_block *rs) -{ - - return (!strncmp(rs->s_v1.s_magic, reiserfs_jr_magic_string, - strlen(reiserfs_jr_magic_string))); -} - -static int -is_any_reiserfs_magic_string(struct reiserfs_super_block *rs) -{ - - return ((is_reiserfs_3_5(rs) || is_reiserfs_3_6(rs) || - is_reiserfs_jr(rs))); -} - -/* ------------------------------------------------------------------- - * Internal functions - * -------------------------------------------------------------------*/ - -/* - * Common code for mount and mountroot - */ -static int -reiserfs_mountfs(struct vnode *devvp, struct mount *mp, struct thread *td) -{ - int error, old_format = 0; - struct reiserfs_mount *rmp; - struct reiserfs_sb_info *sbi; - struct reiserfs_super_block *rs; - struct cdev *dev; - - struct g_consumer *cp; - struct bufobj *bo; - - //ronly = (mp->mnt_flag & MNT_RDONLY) != 0; - - dev = devvp->v_rdev; - dev_ref(dev); - DROP_GIANT(); - g_topology_lock(); - error = g_vfs_open(devvp, &cp, "reiserfs", /* read-only */ 0); - g_topology_unlock(); - PICKUP_GIANT(); - VOP_UNLOCK(devvp, 0); - if (error) { - dev_rel(dev); - return (error); - } - - bo = &devvp->v_bufobj; - bo->bo_private = cp; - bo->bo_ops = g_vfs_bufops; - - if (devvp->v_rdev->si_iosize_max != 0) - mp->mnt_iosize_max = devvp->v_rdev->si_iosize_max; - if (mp->mnt_iosize_max > MAXPHYS) - mp->mnt_iosize_max = MAXPHYS; - - rmp = NULL; - sbi = NULL; - - /* rmp contains any information about this specific mount */ - rmp = malloc(sizeof *rmp, M_REISERFSMNT, M_WAITOK | M_ZERO); - if (!rmp) { - error = (ENOMEM); - goto out; - } - sbi = malloc(sizeof *sbi, M_REISERFSMNT, M_WAITOK | M_ZERO); - if (!sbi) { - error = (ENOMEM); - goto out; - } - rmp->rm_reiserfs = sbi; - rmp->rm_mountp = mp; - rmp->rm_devvp = devvp; - rmp->rm_dev = dev; - rmp->rm_bo = &devvp->v_bufobj; - rmp->rm_cp = cp; - - /* Set default values for options: non-aggressive tails */ - REISERFS_SB(sbi)->s_mount_opt = (1 << REISERFS_SMALLTAIL); - REISERFS_SB(sbi)->s_rd_only = 1; - REISERFS_SB(sbi)->s_devvp = devvp; - - /* Read the super block */ - if ((error = read_super_block(rmp, REISERFS_OLD_DISK_OFFSET)) == 0) { - /* The read process succeeded, it's an old format */ - old_format = 1; - } else if ((error = read_super_block(rmp, REISERFS_DISK_OFFSET)) != 0) { - reiserfs_log(LOG_ERR, "can not find a ReiserFS filesystem\n"); - goto out; - } - - rs = SB_DISK_SUPER_BLOCK(sbi); - - /* - * Let's do basic sanity check to verify that underlying device is - * not smaller than the filesystem. If the check fails then abort and - * scream, because bad stuff will happen otherwise. - */ -#if 0 - if (s->s_bdev && s->s_bdev->bd_inode && - i_size_read(s->s_bdev->bd_inode) < - sb_block_count(rs) * sb_blocksize(rs)) { - reiserfs_log(LOG_ERR, - "reiserfs: filesystem cannot be mounted because it is " - "bigger than the device.\n"); - reiserfs_log(LOG_ERR, "reiserfs: you may need to run fsck " - "rr may be you forgot to reboot after fdisk when it " - "told you to.\n"); - goto out; - } -#endif - - /* - * XXX This is from the original Linux code, but why affecting 2 values - * to the same variable? - */ - sbi->s_mount_state = SB_REISERFS_STATE(sbi); - sbi->s_mount_state = REISERFS_VALID_FS; - - if ((error = (old_format ? - read_old_bitmaps(rmp) : read_bitmaps(rmp)))) { - reiserfs_log(LOG_ERR, "unable to read bitmap\n"); - goto out; - } - - /* Make data=ordered the default */ - if (!reiserfs_data_log(sbi) && !reiserfs_data_ordered(sbi) && - !reiserfs_data_writeback(sbi)) { - REISERFS_SB(sbi)->s_mount_opt |= (1 << REISERFS_DATA_ORDERED); - } - - if (reiserfs_data_log(sbi)) { - reiserfs_log(LOG_INFO, "using journaled data mode\n"); - } else if (reiserfs_data_ordered(sbi)) { - reiserfs_log(LOG_INFO, "using ordered data mode\n"); - } else { - reiserfs_log(LOG_INFO, "using writeback data mode\n"); - } - - /* TODO Not yet supported */ -#if 0 - if(journal_init(sbi, jdev_name, old_format, commit_max_age)) { - reiserfs_log(LOG_ERR, "unable to initialize journal space\n"); - goto out; - } else { - jinit_done = 1 ; /* once this is set, journal_release must - be called if we error out of the mount */ - } - - if (reread_meta_blocks(sbi)) { - reiserfs_log(LOG_ERR, - "unable to reread meta blocks after journal init\n"); - goto out; - } -#endif - - /* Define and initialize hash function */ - sbi->s_hash_function = hash_function(rmp); - - if (sbi->s_hash_function == NULL) { - reiserfs_log(LOG_ERR, "couldn't determined hash function\n"); - error = (EINVAL); - goto out; - } - - if (is_reiserfs_3_5(rs) || - (is_reiserfs_jr(rs) && SB_VERSION(sbi) == REISERFS_VERSION_1)) - bit_set(&(sbi->s_properties), REISERFS_3_5); - else - bit_set(&(sbi->s_properties), REISERFS_3_6); - - mp->mnt_data = rmp; - mp->mnt_stat.f_fsid.val[0] = dev2udev(dev); - mp->mnt_stat.f_fsid.val[1] = mp->mnt_vfc->vfc_typenum; - MNT_ILOCK(mp); - mp->mnt_flag |= MNT_LOCAL; - MNT_IUNLOCK(mp); -#if defined(si_mountpoint) - devvp->v_rdev->si_mountpoint = mp; -#endif - - return (0); - -out: - reiserfs_log(LOG_INFO, "*** error during mount ***\n"); - if (sbi) { - if (SB_AP_BITMAP(sbi)) { - int i; - for (i = 0; i < SB_BMAP_NR(sbi); i++) { - if (!SB_AP_BITMAP(sbi)[i].bp_data) - break; - free(SB_AP_BITMAP(sbi)[i].bp_data, - M_REISERFSMNT); - } - free(SB_AP_BITMAP(sbi), M_REISERFSMNT); - } - - if (sbi->s_rs) { - free(sbi->s_rs, M_REISERFSMNT); - sbi->s_rs = NULL; - } - } - - if (cp != NULL) { - DROP_GIANT(); - g_topology_lock(); - g_vfs_close(cp); - g_topology_unlock(); - PICKUP_GIANT(); - } - - if (sbi) - free(sbi, M_REISERFSMNT); - if (rmp) - free(rmp, M_REISERFSMNT); - dev_rel(dev); - return (error); -} - -/* - * Read the super block - */ -static int -read_super_block(struct reiserfs_mount *rmp, int offset) -{ - struct buf *bp; - int error, bits; - struct reiserfs_super_block *rs; - struct reiserfs_sb_info *sbi; - uint16_t fs_blocksize; - - if (offset == REISERFS_OLD_DISK_OFFSET) { - reiserfs_log(LOG_DEBUG, - "reiserfs/super: read old format super block\n"); - } else { - reiserfs_log(LOG_DEBUG, - "reiserfs/super: read new format super block\n"); - } - - /* Read the super block */ - if ((error = bread(rmp->rm_devvp, offset * btodb(REISERFS_BSIZE), - REISERFS_BSIZE, NOCRED, &bp)) != 0) { - reiserfs_log(LOG_ERR, "can't read device\n"); - return (error); - } - - /* Get it from the buffer data */ - rs = (struct reiserfs_super_block *)bp->b_data; - if (!is_any_reiserfs_magic_string(rs)) { - brelse(bp); - return (EINVAL); - } - - fs_blocksize = sb_blocksize(rs); - brelse(bp); - bp = NULL; - - if (fs_blocksize <= 0) { - reiserfs_log(LOG_ERR, "unexpected null block size"); - return (EINVAL); - } - - /* Read the super block (for double check) - * We can't read the same blkno with a different size: it causes - * panic() if INVARIANTS is set. So we keep REISERFS_BSIZE */ - if ((error = bread(rmp->rm_devvp, - offset * REISERFS_BSIZE / fs_blocksize * btodb(fs_blocksize), - REISERFS_BSIZE, NOCRED, &bp)) != 0) { - reiserfs_log(LOG_ERR, "can't reread the super block\n"); - return (error); - } - - rs = (struct reiserfs_super_block *)bp->b_data; - if (sb_blocksize(rs) != fs_blocksize) { - reiserfs_log(LOG_ERR, "unexpected block size " - "(found=%u, expected=%u)\n", - sb_blocksize(rs), fs_blocksize); - brelse(bp); - return (EINVAL); - } - - reiserfs_log(LOG_DEBUG, "magic: `%s'\n", rs->s_v1.s_magic); - reiserfs_log(LOG_DEBUG, "label: `%s'\n", rs->s_label); - reiserfs_log(LOG_DEBUG, "block size: %6d\n", sb_blocksize(rs)); - reiserfs_log(LOG_DEBUG, "block count: %6u\n", - rs->s_v1.s_block_count); - reiserfs_log(LOG_DEBUG, "bitmaps number: %6u\n", - rs->s_v1.s_bmap_nr); - - if (rs->s_v1.s_root_block == -1) { - log(LOG_ERR, - "reiserfs: Unfinished reiserfsck --rebuild-tree run " - "detected. Please\n" - "run reiserfsck --rebuild-tree and wait for a " - "completion. If that\n" - "fails, get newer reiserfsprogs package"); - brelse(bp); - return (EINVAL); - } - - sbi = rmp->rm_reiserfs; - sbi->s_blocksize = fs_blocksize; - - for (bits = 9, fs_blocksize >>= 9; fs_blocksize >>= 1; bits++) - ; - sbi->s_blocksize_bits = bits; - - /* Copy the buffer and release it */ - sbi->s_rs = malloc(sizeof *rs, M_REISERFSMNT, M_WAITOK | M_ZERO); - if (!sbi->s_rs) { - reiserfs_log(LOG_ERR, "can not read the super block\n"); - brelse(bp); - return (ENOMEM); - } - bcopy(rs, sbi->s_rs, sizeof(struct reiserfs_super_block)); - brelse(bp); - - if (is_reiserfs_jr(rs)) { - if (sb_version(rs) == REISERFS_VERSION_2) - reiserfs_log(LOG_INFO, "found reiserfs format \"3.6\"" - " with non-standard journal"); - else if (sb_version(rs) == REISERFS_VERSION_1) - reiserfs_log(LOG_INFO, "found reiserfs format \"3.5\"" - " with non-standard journal"); - else { - reiserfs_log(LOG_ERR, "found unknown " - "format \"%u\" of reiserfs with non-standard magic", - sb_version(rs)); - return (EINVAL); - } - } else { - /* - * s_version of standard format may contain incorrect - * information, so we just look at the magic string - */ - reiserfs_log(LOG_INFO, - "found reiserfs format \"%s\" with standard journal\n", - is_reiserfs_3_5(rs) ? "3.5" : "3.6"); - } - - return (0); -} - -/* - * load_bitmap_info_data - Sets up the reiserfs_bitmap_info structure - * from disk. - * @sbi - superblock info for this filesystem - * @bi - the bitmap info to be loaded. Requires that bi->bp is valid. - * - * This routine counts how many free bits there are, finding the first - * zero as a side effect. Could also be implemented as a loop of - * test_bit() calls, or a loop of find_first_zero_bit() calls. This - * implementation is similar to find_first_zero_bit(), but doesn't - * return after it finds the first bit. Should only be called on fs - * mount, but should be fairly efficient anyways. - * - * bi->first_zero_hint is considered unset if it == 0, since the bitmap - * itself will invariably occupt block 0 represented in the bitmap. The - * only exception to this is when free_count also == 0, since there will - * be no free blocks at all. - */ -static void -load_bitmap_info_data(struct reiserfs_sb_info *sbi, - struct reiserfs_bitmap_info *bi) -{ - unsigned long *cur; - - cur = (unsigned long *)bi->bp_data; - while ((char *)cur < (bi->bp_data + sbi->s_blocksize)) { - /* - * No need to scan if all 0's or all 1's. - * Since we're only counting 0's, we can simply ignore - * all 1's - */ - if (*cur == 0) { - if (bi->first_zero_hint == 0) { - bi->first_zero_hint = - ((char *)cur - bi->bp_data) << 3; - } - bi->free_count += sizeof(unsigned long) * 8; - } else if (*cur != ~0L) { - int b; - - for (b = 0; b < sizeof(unsigned long) * 8; b++) { - if (!reiserfs_test_le_bit(b, cur)) { - bi->free_count++; - if (bi->first_zero_hint == 0) - bi->first_zero_hint = - (((char *)cur - - bi->bp_data) << 3) + b; - } - } - } - cur++; - } -} - -/* - * Read the bitmaps - */ -static int -read_bitmaps(struct reiserfs_mount *rmp) -{ - int i, bmap_nr; - struct buf *bp = NULL; - struct reiserfs_sb_info *sbi = rmp->rm_reiserfs; - - /* Allocate memory for the table of bitmaps */ - SB_AP_BITMAP(sbi) = - malloc(sizeof(struct reiserfs_bitmap_info) * SB_BMAP_NR(sbi), - M_REISERFSMNT, M_WAITOK | M_ZERO); - if (!SB_AP_BITMAP(sbi)) - return (ENOMEM); - - /* Read all the bitmaps */ - for (i = 0, - bmap_nr = (REISERFS_DISK_OFFSET_IN_BYTES / sbi->s_blocksize + 1) * - btodb(sbi->s_blocksize); - i < SB_BMAP_NR(sbi); i++, bmap_nr = sbi->s_blocksize * 8 * i) { - SB_AP_BITMAP(sbi)[i].bp_data = malloc(sbi->s_blocksize, - M_REISERFSMNT, M_WAITOK | M_ZERO); - if (!SB_AP_BITMAP(sbi)[i].bp_data) - return (ENOMEM); - bread(rmp->rm_devvp, bmap_nr, sbi->s_blocksize, NOCRED, &bp); - bcopy(bp->b_data, SB_AP_BITMAP(sbi)[i].bp_data, - sbi->s_blocksize); - brelse(bp); - bp = NULL; - - /*if (!buffer_uptodate(SB_AP_BITMAP(s)[i].bh)) - ll_rw_block(READ, 1, &SB_AP_BITMAP(s)[i].bh);*/ - } - - for (i = 0; i < SB_BMAP_NR(sbi); i++) { - /*if (!buffer_uptodate(SB_AP_BITMAP(s)[i].bh)) { - reiserfs_warning(s,"sh-2029: reiserfs read_bitmaps: " - "bitmap block (#%lu) reading failed", - SB_AP_BITMAP(s)[i].bh->b_blocknr); - for (i = 0; i < SB_BMAP_NR(s); i++) - brelse(SB_AP_BITMAP(s)[i].bh); - vfree(SB_AP_BITMAP(s)); - SB_AP_BITMAP(s) = NULL; - return 1; - }*/ - load_bitmap_info_data(sbi, SB_AP_BITMAP(sbi) + i); - reiserfs_log(LOG_DEBUG, - "%d free blocks (starting at block %ld)\n", - SB_AP_BITMAP(sbi)[i].free_count, - (long)SB_AP_BITMAP(sbi)[i].first_zero_hint); - } - - return (0); -} - -// TODO Not supported -static int -read_old_bitmaps(struct reiserfs_mount *rmp) -{ - - return (EOPNOTSUPP); -#if 0 - int i; - struct reiserfs_sb_info *sbi = rmp->rm_reiserfs; - struct reiserfs_super_block *rs = SB_DISK_SUPER_BLOCK(sbi); - - /* First of bitmap blocks */ - int bmp1 = (REISERFS_OLD_DISK_OFFSET / sbi->s_blocksize) * - btodb(sbi->s_blocksize); - - /* Read true bitmap */ - SB_AP_BITMAP(sbi) = - malloc(sizeof (struct reiserfs_buffer_info *) * sb_bmap_nr(rs), - M_REISERFSMNT, M_WAITOK | M_ZERO); - if (!SB_AP_BITMAP(sbi)) - return 1; - - for (i = 0; i < sb_bmap_nr(rs); i ++) { - SB_AP_BITMAP(sbi)[i].bp = getblk(rmp->rm_devvp, - (bmp1 + i) * btodb(sbi->s_blocksize), sbi->s_blocksize, 0, 0, 0); - if (!SB_AP_BITMAP(sbi)[i].bp) - return 1; - load_bitmap_info_data(sbi, SB_AP_BITMAP(sbi) + i); - } - - return 0; -#endif -} - -/* ------------------------------------------------------------------- - * Hash detection stuff - * -------------------------------------------------------------------*/ - -static int -get_root_node(struct reiserfs_mount *rmp, struct reiserfs_node **root) -{ - struct reiserfs_node *ip; - struct reiserfs_iget_args args; - - /* Allocate the node structure */ - reiserfs_log(LOG_DEBUG, "malloc(struct reiserfs_node)\n"); - ip = malloc(sizeof(struct reiserfs_node), - M_REISERFSNODE, M_WAITOK | M_ZERO); - - /* Fill the structure */ - reiserfs_log(LOG_DEBUG, "filling *ip\n"); - ip->i_dev = rmp->rm_dev; - ip->i_number = REISERFS_ROOT_OBJECTID; - ip->i_ino = REISERFS_ROOT_PARENT_OBJECTID; - ip->i_reiserfs = rmp->rm_reiserfs; - - /* Read the inode */ - args.objectid = ip->i_number; - args.dirid = ip->i_ino; - reiserfs_log(LOG_DEBUG, "call reiserfs_read_locked_inode(" - "objectid=%d,dirid=%d)\n", args.objectid, args.dirid); - reiserfs_read_locked_inode(ip, &args); - - ip->i_devvp = rmp->rm_devvp; - //XXX VREF(ip->i_devvp); Is it necessary ? - - *root = ip; - return (0); -} - -/* - * If root directory is empty - we set default - Yura's - hash and warn - * about it. - * FIXME: we look for only one name in a directory. If tea and yura both - * have the same value - we ask user to send report to the mailing list - */ -uint32_t find_hash_out(struct reiserfs_mount *rmp) -{ - int retval; - struct cpu_key key; - INITIALIZE_PATH(path); - struct reiserfs_node *ip; - struct reiserfs_sb_info *sbi; - struct reiserfs_dir_entry de; - uint32_t hash = DEFAULT_HASH; - - get_root_node(rmp, &ip); - if (!ip) - return (UNSET_HASH); - - sbi = rmp->rm_reiserfs; - - do { - uint32_t teahash, r5hash, yurahash; - - reiserfs_log(LOG_DEBUG, "make_cpu_key\n"); - make_cpu_key(&key, ip, ~0, TYPE_DIRENTRY, 3); - reiserfs_log(LOG_DEBUG, "search_by_entry_key for " - "key(objectid=%d,dirid=%d)\n", - key.on_disk_key.k_objectid, key.on_disk_key.k_dir_id); - retval = search_by_entry_key(sbi, &key, &path, &de); - if (retval == IO_ERROR) { - hash = UNSET_HASH; - break; - } - if (retval == NAME_NOT_FOUND) - de.de_entry_num--; - - reiserfs_log(LOG_DEBUG, "name found\n"); - - set_de_name_and_namelen(&de); - - if (deh_offset(&(de.de_deh[de.de_entry_num])) == DOT_DOT_OFFSET) { - /* Allow override in this case */ - if (reiserfs_rupasov_hash(sbi)) { - hash = YURA_HASH; - } - reiserfs_log(LOG_DEBUG, - "FS seems to be empty, autodetect " - "is using the default hash"); - break; - } - - r5hash = GET_HASH_VALUE(r5_hash(de.de_name, de.de_namelen)); - teahash = GET_HASH_VALUE(keyed_hash(de.de_name, - de.de_namelen)); - yurahash = GET_HASH_VALUE(yura_hash(de.de_name, de.de_namelen)); - if (((teahash == r5hash) && - (GET_HASH_VALUE( - deh_offset(&(de.de_deh[de.de_entry_num]))) == r5hash)) || - ((teahash == yurahash) && - (yurahash == - GET_HASH_VALUE( - deh_offset(&(de.de_deh[de.de_entry_num]))))) || - ((r5hash == yurahash) && - (yurahash == - GET_HASH_VALUE( - deh_offset(&(de.de_deh[de.de_entry_num])))))) { - reiserfs_log(LOG_ERR, - "unable to automatically detect hash " - "function. Please mount with -o " - "hash={tea,rupasov,r5}"); - hash = UNSET_HASH; - break; - } - - if (GET_HASH_VALUE( - deh_offset(&(de.de_deh[de.de_entry_num]))) == yurahash) { - reiserfs_log(LOG_DEBUG, "detected YURA hash\n"); - hash = YURA_HASH; - } else if (GET_HASH_VALUE( - deh_offset(&(de.de_deh[de.de_entry_num]))) == teahash) { - reiserfs_log(LOG_DEBUG, "detected TEA hash\n"); - hash = TEA_HASH; - } else if (GET_HASH_VALUE( - deh_offset(&(de.de_deh[de.de_entry_num]))) == r5hash) { - reiserfs_log(LOG_DEBUG, "detected R5 hash\n"); - hash = R5_HASH; - } else { - reiserfs_log(LOG_WARNING, "unrecognised hash function"); - hash = UNSET_HASH; - } - } while (0); - - free(ip, M_REISERFSNODE); - pathrelse(&path); - return (hash); -} - -/* Finds out which hash names are sorted with */ -static int -what_hash(struct reiserfs_mount *rmp) -{ - uint32_t code; - struct reiserfs_sb_info *sbi = rmp->rm_reiserfs; - - find_hash_out(rmp); - code = sb_hash_function_code(SB_DISK_SUPER_BLOCK(sbi)); - - /* - * reiserfs_hash_detect() == true if any of the hash mount options - * were used. We must check them to make sure the user isn't using a - * bad hash value - */ - if (code == UNSET_HASH || reiserfs_hash_detect(sbi)) - code = find_hash_out(rmp); - - if (code != UNSET_HASH && reiserfs_hash_detect(sbi)) { - /* - * Detection has found the hash, and we must check against - * the mount options - */ - if (reiserfs_rupasov_hash(sbi) && code != YURA_HASH) { - reiserfs_log(LOG_ERR, "error, %s hash detected, " - "unable to force rupasov hash", - reiserfs_hashname(code)); - code = UNSET_HASH; - } else if (reiserfs_tea_hash(sbi) && code != TEA_HASH) { - reiserfs_log(LOG_ERR, "error, %s hash detected, " - "unable to force tea hash", - reiserfs_hashname(code)); - code = UNSET_HASH; - } else if (reiserfs_r5_hash(sbi) && code != R5_HASH) { - reiserfs_log(LOG_ERR, "error, %s hash detected, " - "unable to force r5 hash", - reiserfs_hashname(code)); - code = UNSET_HASH; - } - } else { - /* - * Find_hash_out was not called or could not determine - * the hash - */ - if (reiserfs_rupasov_hash(sbi)) { - code = YURA_HASH; - } else if (reiserfs_tea_hash(sbi)) { - code = TEA_HASH; - } else if (reiserfs_r5_hash(sbi)) { - code = R5_HASH; - } - } - - /* TODO Not supported yet */ -#if 0 - /* If we are mounted RW, and we have a new valid hash code, update - * the super */ - if (code != UNSET_HASH && - !(s->s_flags & MS_RDONLY) && - code != sb_hash_function_code(SB_DISK_SUPER_BLOCK(s))) { - set_sb_hash_function_code(SB_DISK_SUPER_BLOCK(s), code); - } -#endif - - return (code); -} - -/* Return pointer to appropriate function */ -static hashf_t -hash_function(struct reiserfs_mount *rmp) -{ - - switch (what_hash(rmp)) { - case TEA_HASH: - reiserfs_log(LOG_INFO, "using tea hash to sort names\n"); - return (keyed_hash); - case YURA_HASH: - reiserfs_log(LOG_INFO, "using rupasov hash to sort names\n"); - return (yura_hash); - case R5_HASH: - reiserfs_log(LOG_INFO, "using r5 hash to sort names\n"); - return (r5_hash); - } - - return (NULL); -} - -/* ------------------------------------------------------------------- - * VFS registration - * -------------------------------------------------------------------*/ - -static struct vfsops reiser_vfsops = { - .vfs_cmount = reiserfs_cmount, - .vfs_mount = reiserfs_mount, - .vfs_unmount = reiserfs_unmount, - //.vfs_checkexp = reiserfs_checkexp, - //.vfs_extattrctl = reiserfs_extattrctl, - .vfs_fhtovp = reiserfs_fhtovp, - //.vfs_quotactl = reiserfs_quotactl, - .vfs_root = reiserfs_root, - //.vfs_start = reiserfs_start, - .vfs_statfs = reiserfs_statfs, - //.vfs_sync = reiserfs_sync, - //.vfs_vget = reiserfs_vget, -}; - -VFS_SET(reiser_vfsops, reiserfs, VFCF_READONLY); diff --git a/sys/gnu/fs/reiserfs/reiserfs_vnops.c b/sys/gnu/fs/reiserfs/reiserfs_vnops.c deleted file mode 100644 index 8ac1910..0000000 --- a/sys/gnu/fs/reiserfs/reiserfs_vnops.c +++ /dev/null @@ -1,387 +0,0 @@ -/*- - * Copyright 2000 Hans Reiser - * See README for licensing and copyright details - * - * Ported to FreeBSD by Jean-Sébastien Pédron <jspedron@club-internet.fr> - * - * $FreeBSD$ - */ - -#include <gnu/fs/reiserfs/reiserfs_fs.h> - -static vop_access_t reiserfs_access; -static vop_bmap_t reiserfs_bmap; -static vop_getattr_t reiserfs_getattr; -static vop_open_t reiserfs_open; -static vop_pathconf_t reiserfs_pathconf; -static vop_readlink_t reiserfs_readlink; -static vop_strategy_t reiserfs_strategy; -static vop_vptofh_t reiserfs_vptofh; - -/* Global vfs data structures for ReiserFS */ -struct vop_vector reiserfs_vnodeops = { - .vop_default = &default_vnodeops, - - .vop_access = reiserfs_access, - .vop_bmap = reiserfs_bmap, - .vop_cachedlookup = reiserfs_lookup, - .vop_getattr = reiserfs_getattr, - .vop_inactive = reiserfs_inactive, - .vop_lookup = vfs_cache_lookup, - .vop_open = reiserfs_open, - .vop_reclaim = reiserfs_reclaim, - .vop_read = reiserfs_read, - .vop_readdir = reiserfs_readdir, - .vop_readlink = reiserfs_readlink, - .vop_pathconf = reiserfs_pathconf, - .vop_strategy = reiserfs_strategy, - .vop_vptofh = reiserfs_vptofh, -}; - -struct vop_vector reiserfs_specops = { - .vop_default = &default_vnodeops, - - .vop_access = reiserfs_access, - .vop_getattr = reiserfs_getattr, - .vop_inactive = reiserfs_inactive, - .vop_reclaim = reiserfs_reclaim, -}; - -/* ------------------------------------------------------------------- - * vnode operations - * -------------------------------------------------------------------*/ - -static int -reiserfs_access(struct vop_access_args *ap) -{ - int error; - struct vnode *vp = ap->a_vp; - struct reiserfs_node *ip = VTOI(vp); - accmode_t accmode = ap->a_accmode; - - /* - * Disallow write attempts on read-only file systems; unless the file - * is a socket, fifo, or a block or character device resident on the - * file system. - */ - if (accmode & VWRITE) { - switch (vp->v_type) { - case VDIR: - case VLNK: - case VREG: - if (vp->v_mount->mnt_flag & MNT_RDONLY) { - reiserfs_log(LOG_DEBUG, - "no write access (read-only fs)\n"); - return (EROFS); - } - break; - default: - break; - } - } - - /* If immutable bit set, nobody gets to write it. */ - if ((accmode & VWRITE) && (ip->i_flags & (IMMUTABLE | SF_SNAPSHOT))) { - reiserfs_log(LOG_DEBUG, "no write access (immutable)\n"); - return (EPERM); - } - - error = vaccess(vp->v_type, ip->i_mode, ip->i_uid, ip->i_gid, - ap->a_accmode, ap->a_cred, NULL); - return (error); -} - -static int -reiserfs_getattr(struct vop_getattr_args *ap) -{ - struct vnode *vp = ap->a_vp; - struct vattr *vap = ap->a_vap; - struct reiserfs_node *ip = VTOI(vp); - - vap->va_fsid = dev2udev(ip->i_dev); - vap->va_fileid = ip->i_number; - vap->va_mode = ip->i_mode & ~S_IFMT; - vap->va_nlink = ip->i_nlink; - vap->va_uid = ip->i_uid; - vap->va_gid = ip->i_gid; - //XXX vap->va_rdev = ip->i_rdev; - vap->va_size = ip->i_size; - vap->va_atime = ip->i_atime; - vap->va_mtime = ip->i_mtime; - vap->va_ctime = ip->i_ctime; - vap->va_flags = ip->i_flags; - vap->va_gen = ip->i_generation; - vap->va_blocksize = vp->v_mount->mnt_stat.f_iosize; - vap->va_bytes = dbtob((u_quad_t)ip->i_blocks); - vap->va_type = vp->v_type; - //XXX vap->va_filerev = ip->i_modrev; - - return (0); -} - -/* Return POSIX pathconf information applicable to ReiserFS filesystems */ -static int -reiserfs_pathconf(struct vop_pathconf_args *ap) -{ - switch (ap->a_name) { - case _PC_LINK_MAX: - *ap->a_retval = REISERFS_LINK_MAX; - return (0); - case _PC_NAME_MAX: - *ap->a_retval = - REISERFS_MAX_NAME(VTOI(ap->a_vp)->i_reiserfs->s_blocksize); - return (0); - case _PC_PATH_MAX: - *ap->a_retval = PATH_MAX; - return (0); - case _PC_PIPE_BUF: - *ap->a_retval = PIPE_BUF; - return (0); - case _PC_CHOWN_RESTRICTED: - *ap->a_retval = 1; - return (0); - case _PC_NO_TRUNC: - *ap->a_retval = 1; - return (0); - default: - return (EINVAL); - } -} - -static int -reiserfs_open(struct vop_open_args *ap) -{ - /* Files marked append-only must be opened for appending. */ - if ((VTOI(ap->a_vp)->i_flags & APPEND) && - (ap->a_mode & (FWRITE | O_APPEND)) == FWRITE) - return (EPERM); - - vnode_create_vobject(ap->a_vp, VTOI(ap->a_vp)->i_size, ap->a_td); - - return (0); -} - -/* Return target name of a symbolic link */ -static int -reiserfs_readlink(struct vop_readlink_args *ap) -{ - struct vnode *vp = ap->a_vp; - - reiserfs_log(LOG_DEBUG, "redirect to VOP_READ()\n"); - return (VOP_READ(vp, ap->a_uio, 0, ap->a_cred)); -} - -/* Bmap converts the logical block number of a file to its physical - * block number on the disk. */ -static int -reiserfs_bmap(ap) - struct vop_bmap_args /* { - struct vnode *a_vp; - daddr_t a_bn; - struct bufobj **a_bop; - daddr_t *a_bnp; - int *a_runp; - int *a_runb; - } */ *ap; -{ - daddr_t blkno; - struct buf *bp; - struct cpu_key key; - struct item_head *ih; - - struct vnode *vp = ap->a_vp; - struct reiserfs_node *ip = VTOI(vp); - struct reiserfs_sb_info *sbi = ip->i_reiserfs; - INITIALIZE_PATH(path); - - /* Prepare the key to look for the 'block'-th block of file - * (XXX we suppose that statfs.f_iosize == sbi->s_blocksize) */ - make_cpu_key(&key, ip, (off_t)ap->a_bn * sbi->s_blocksize + 1, - TYPE_ANY, 3); - - /* Search item */ - if (search_for_position_by_key(sbi, &key, &path) != POSITION_FOUND) { - reiserfs_log(LOG_DEBUG, "position not found\n"); - pathrelse(&path); - return (ENOENT); - } - - bp = get_last_bp(&path); - ih = get_ih(&path); - - if (is_indirect_le_ih(ih)) { - /* Indirect item can be read by the underlying layer, instead of - * VOP_STRATEGY. */ - int i; - uint32_t *ind_item = (uint32_t *)B_I_PITEM(bp, ih); - reiserfs_log(LOG_DEBUG, "found an INDIRECT item\n"); - blkno = get_block_num(ind_item, path.pos_in_item); - - /* Read-ahead */ - if (ap->a_runb) { - uint32_t count = 0; - for (i = path.pos_in_item - 1; i >= 0; --i) { - if ((blkno - get_block_num(ind_item, i)) != - count + 1) - break; - ++count; - } - - /* - * This count isn't expressed in DEV_BSIZE base but - * in fs' own block base - * (see sys/vm/vnode_pager.c:vnode_pager_addr()) - */ - *ap->a_runb = count; - reiserfs_log(LOG_DEBUG, - " read-ahead: %d blocks before\n", *ap->a_runb); - } - if (ap->a_runp) { - uint32_t count = 0; - /* - * ih is an uint32_t array, that's why we use - * its length (in bytes) divided by 4 to know - * the number of items - */ - for (i = path.pos_in_item + 1; - i < ih_item_len(ih) / 4; ++i) { - if ((get_block_num(ind_item, i) - blkno) != - count + 1) - break; - ++count; - } - - /* - * This count isn't expressed in DEV_BSIZE base but - * in fs' own block base - * (see sys/vm/vnode_pager.c:vnode_pager_addr()) */ - *ap->a_runp = count; - reiserfs_log(LOG_DEBUG, - " read-ahead: %d blocks after\n", *ap->a_runp); - } - - /* Indirect items can be read using the device VOP_STRATEGY */ - if (ap->a_bop) - *ap->a_bop = &VTOI(ap->a_vp)->i_devvp->v_bufobj; - - /* Convert the block number into DEV_BSIZE base */ - blkno *= btodb(sbi->s_blocksize); - } else { - /* - * Direct item are not DEV_BSIZE aligned, VOP_STRATEGY will - * have to handle this case specifically - */ - reiserfs_log(LOG_DEBUG, "found a DIRECT item\n"); - blkno = ap->a_bn; - - if (ap->a_runp) - *ap->a_runp = 0; - if (ap->a_runb) - *ap->a_runb = 0; - - /* Direct item must be read by reiserfs_strategy */ - if (ap->a_bop) - *ap->a_bop = &vp->v_bufobj; - } - - if (ap->a_bnp) - *ap->a_bnp = blkno; - - pathrelse(&path); - - if (ap->a_bnp) { - reiserfs_log(LOG_DEBUG, "logical block: %ju (%ju)," - " physical block: %ju (%ju)\n", - (intmax_t)ap->a_bn, - (intmax_t)(ap->a_bn / btodb(sbi->s_blocksize)), - (intmax_t)*ap->a_bnp, - (intmax_t)(*ap->a_bnp / btodb(sbi->s_blocksize))); - } - - return (0); -} - -/* Does simply the same as reiserfs_read. It's called when reiserfs_bmap find - * an direct item. */ -static int -reiserfs_strategy(struct vop_strategy_args /* { - struct vnode *a_vp; - struct buf *a_bp; - } */ *ap) -{ - int error; - struct uio auio; - struct iovec aiov; - struct reiserfs_node *ip; - struct buf *bp = ap->a_bp; - struct vnode *vp = ap->a_vp; - - reiserfs_log(LOG_DEBUG, "logical block: %ju," - " physical block: %ju\n", (intmax_t)bp->b_lblkno, - (intmax_t)bp->b_blkno); - - ip = VTOI(vp); - - if (bp->b_iocmd == BIO_READ) { - /* Prepare the uio structure */ - reiserfs_log(LOG_DEBUG, "prepare uio structure\n"); - aiov.iov_base = bp->b_data; - aiov.iov_len = MIN(bp->b_bcount, ip->i_size); - reiserfs_log(LOG_DEBUG, " vector length: %ju\n", - (intmax_t)aiov.iov_len); - - auio.uio_iov = &aiov; - auio.uio_iovcnt = 1; - auio.uio_offset = 0; - auio.uio_rw = UIO_READ; - auio.uio_segflg = UIO_SYSSPACE; - auio.uio_td = curthread; - auio.uio_resid = bp->b_bcount; - reiserfs_log(LOG_DEBUG, " buffer length: %u\n", - auio.uio_resid); - - reiserfs_log(LOG_DEBUG, "reading block #%ju\n", - (intmax_t)bp->b_blkno); - error = reiserfs_get_block(ip, bp->b_blkno, 0, &auio); - } else { - /* No write support yet */ - error = (EOPNOTSUPP); - bp->b_error = error; - bp->b_ioflags |= BIO_ERROR; - } - - if (error) { - bp->b_ioflags |= BIO_ERROR; - bp->b_error = error; - } - - bufdone(bp); - return (0); -} - -/* - * Vnode pointer to File handle - */ -static int -reiserfs_vptofh(struct vop_vptofh_args /* { - struct vnode *a_vp; - struct fid *a_fhp; - } */ *ap) -{ - struct rfid *rfhp; - struct reiserfs_node *ip; - - ip = VTOI(ap->a_vp); - reiserfs_log(LOG_DEBUG, - "fill *fhp with inode (dirid=%d, objectid=%d)\n", - ip->i_ino, ip->i_number); - - rfhp = (struct rfid *)ap->a_fhp; - rfhp->rfid_len = sizeof(struct rfid); - rfhp->rfid_dirid = ip->i_ino; - rfhp->rfid_objectid = ip->i_number; - rfhp->rfid_gen = ip->i_generation; - - reiserfs_log(LOG_DEBUG, "return it\n"); - return (0); -} diff --git a/sys/kern/bus_if.m b/sys/kern/bus_if.m index f0115e8..8592e9f 100644 --- a/sys/kern/bus_if.m +++ b/sys/kern/bus_if.m @@ -530,8 +530,15 @@ METHOD int child_present { /** * @brief Returns the pnp info for this device. * - * Return it as a string. If the string is insufficient for the - * storage, then return EOVERFLOW. + * Return it as a string. If the storage is insufficient for the + * string, then return EOVERFLOW. + * + * The string must be formatted as a space-separated list of + * name=value pairs. Names may only contain alphanumeric characters, + * underscores ('_') and hyphens ('-'). Values can contain any + * non-whitespace characters. Values containing whitespace can be + * quoted with double quotes ('"'). Double quotes and backslashes in + * quoted values can be escaped with backslashes ('\'). * * @param _dev the parent device of @p _child * @param _child the device which is being examined @@ -549,9 +556,16 @@ METHOD int child_pnpinfo_str { /** * @brief Returns the location for this device. * - * Return it as a string. If the string is insufficient for the - * storage, then return EOVERFLOW. - * + * Return it as a string. If the storage is insufficient for the + * string, then return EOVERFLOW. + * + * The string must be formatted as a space-separated list of + * name=value pairs. Names may only contain alphanumeric characters, + * underscores ('_') and hyphens ('-'). Values can contain any + * non-whitespace characters. Values containing whitespace can be + * quoted with double quotes ('"'). Double quotes and backslashes in + * quoted values can be escaped with backslashes ('\'). + * * @param _dev the parent device of @p _child * @param _child the device which is being examined * @param _buf the address of a buffer to receive the location diff --git a/sys/kern/device_if.m b/sys/kern/device_if.m index a5319c6..305110f 100644 --- a/sys/kern/device_if.m +++ b/sys/kern/device_if.m @@ -62,6 +62,11 @@ CODE { { return 0; } + + static void * null_register(device_t dev) + { + return NULL; + } }; /** @@ -316,3 +321,24 @@ METHOD int resume { METHOD int quiesce { device_t dev; } DEFAULT null_quiesce; + +/** + * @brief This is called when the driver is asked to register handlers. + * + * + * To include this method in a device driver, use a line like this + * in the driver's method list: + * + * @code + * KOBJMETHOD(device_register, foo_register) + * @endcode + * + * @param dev the device for which handlers are being registered + * + * @retval NULL method not implemented + * @retval non-NULL a pointer to implementation specific static driver state + * + */ +METHOD void * register { + device_t dev; +} DEFAULT null_register; diff --git a/sys/kern/kern_clock.c b/sys/kern/kern_clock.c index 17b85bc..e7a7a99 100644 --- a/sys/kern/kern_clock.c +++ b/sys/kern/kern_clock.c @@ -570,9 +570,11 @@ hardclock_cnt(int cnt, int usermode) flags |= TDF_PROFPEND | TDF_ASTPENDING; PROC_ITIMUNLOCK(p); } - thread_lock(td); - td->td_flags |= flags; - thread_unlock(td); + if (flags != 0) { + thread_lock(td); + td->td_flags |= flags; + thread_unlock(td); + } #ifdef HWPMC_HOOKS if (PMC_CPU_HAS_SAMPLES(PCPU_GET(cpuid))) diff --git a/sys/kern/kern_exit.c b/sys/kern/kern_exit.c index 1cd9b62..0a0659d 100644 --- a/sys/kern/kern_exit.c +++ b/sys/kern/kern_exit.c @@ -350,8 +350,11 @@ exit1(struct thread *td, int rval, int signo) KASSERT(!timevalisset(&p->p_realtimer.it_value), ("realtime timer is still armed")); } + PROC_UNLOCK(p); + umtx_thread_exit(td); + /* * Reset any sigio structures pointing to us as a result of * F_SETOWN with our pid. @@ -595,7 +598,6 @@ exit1(struct thread *td, int rval, int signo) wakeup(p->p_pptr); cv_broadcast(&p->p_pwait); sched_exit(p->p_pptr, td); - umtx_thread_exit(td); PROC_SLOCK(p); p->p_state = PRS_ZOMBIE; PROC_UNLOCK(p->p_pptr); diff --git a/sys/kern/kern_mbuf.c b/sys/kern/kern_mbuf.c index 273196b..0d0c1c8 100644 --- a/sys/kern/kern_mbuf.c +++ b/sys/kern/kern_mbuf.c @@ -444,7 +444,7 @@ mb_dtor_mbuf(void *mem, int size, void *arg) flags = (unsigned long)arg; KASSERT((m->m_flags & M_NOFREE) == 0, ("%s: M_NOFREE set", __func__)); - if ((m->m_flags & M_PKTHDR) && !SLIST_EMPTY(&m->m_pkthdr.tags)) + if (!(flags & MB_DTOR_SKIP) && (m->m_flags & M_PKTHDR) && !SLIST_EMPTY(&m->m_pkthdr.tags)) m_tag_delete_chain(m, NULL); #ifdef INVARIANTS trash_dtor(mem, size, arg); @@ -638,9 +638,16 @@ mb_free_ext(struct mbuf *m) * Check if the header is embedded in the cluster. It is * important that we can't touch any of the mbuf fields * after we have freed the external storage, since mbuf - * could have been embedded in it. + * could have been embedded in it. For now, the mbufs + * embedded into the cluster are always of type EXT_EXTREF, + * and for this type we won't free the mref. */ - freembuf = (m->m_flags & M_NOFREE) ? 0 : 1; + if (m->m_flags & M_NOFREE) { + freembuf = 0; + KASSERT(m->m_ext.ext_type == EXT_EXTREF, + ("%s: no-free mbuf %p has wrong type", __func__, m)); + } else + freembuf = 1; /* Free attached storage if this mbuf is the only reference to it. */ if (*refcnt == 1 || atomic_fetchadd_int(refcnt, -1) == 1) { diff --git a/sys/kern/kern_mutex.c b/sys/kern/kern_mutex.c index bec8f6b..3f62d17 100644 --- a/sys/kern/kern_mutex.c +++ b/sys/kern/kern_mutex.c @@ -714,7 +714,10 @@ retry: LOCK_LOG_LOCK("LOCK", &m->lock_object, opts, m->mtx_recurse, file, line); WITNESS_LOCK(&m->lock_object, opts | LOP_EXCLUSIVE, file, line); - LOCKSTAT_RECORD1(thread__spin, m, spin_time); +#ifdef KDTRACE_HOOKS + if (spin_time != 0) + LOCKSTAT_RECORD1(thread__spin, m, spin_time); +#endif } struct mtx * @@ -842,37 +845,6 @@ __mtx_assert(const volatile uintptr_t *c, int what, const char *file, int line) #endif /* - * The MUTEX_DEBUG-enabled mtx_validate() - * - * Most of these checks have been moved off into the LO_INITIALIZED flag - * maintained by the witness code. - */ -#ifdef MUTEX_DEBUG - -void mtx_validate(struct mtx *); - -void -mtx_validate(struct mtx *m) -{ - -/* - * XXX: When kernacc() does not require Giant we can reenable this check - */ -#ifdef notyet - /* - * Can't call kernacc() from early init386(), especially when - * initializing Giant mutex, because some stuff in kernacc() - * requires Giant itself. - */ - if (!cold) - if (!kernacc((caddr_t)m, sizeof(m), - VM_PROT_READ | VM_PROT_WRITE)) - panic("Can't read and write to mutex %p", m); -#endif -} -#endif - -/* * General init routine used by the MTX_SYSINIT() macro. */ void @@ -905,11 +877,6 @@ _mtx_init(volatile uintptr_t *c, const char *name, const char *type, int opts) ("%s: mtx_lock not aligned for %s: %p", __func__, name, &m->mtx_lock)); -#ifdef MUTEX_DEBUG - /* Diagnostic and error correction */ - mtx_validate(m); -#endif - /* Determine lock class and lock flags. */ if (opts & MTX_SPIN) class = &lock_class_mtx_spin; diff --git a/sys/kern/kern_thr.c b/sys/kern/kern_thr.c index 1b226dd..75bd83d 100644 --- a/sys/kern/kern_thr.c +++ b/sys/kern/kern_thr.c @@ -308,6 +308,8 @@ sys_thr_exit(struct thread *td, struct thr_exit_args *uap) /* long *state */ { + umtx_thread_exit(td); + /* Signal userland that it can free the stack. */ if ((void *)uap->state != NULL) { suword_lwpid(uap->state, 1); @@ -367,7 +369,6 @@ kern_thr_exit(struct thread *td) KASSERT(p->p_numthreads > 1, ("too few threads")); racct_sub(p, RACCT_NTHR, 1); tdsigcleanup(td); - umtx_thread_exit(td); PROC_SLOCK(p); thread_stopped(p); thread_exit(); diff --git a/sys/kern/kern_thread.c b/sys/kern/kern_thread.c index 66b6120..21f3587 100644 --- a/sys/kern/kern_thread.c +++ b/sys/kern/kern_thread.c @@ -950,6 +950,7 @@ thread_suspend_check(int return_instead) */ if (__predict_false(p->p_sysent->sv_thread_detach != NULL)) (p->p_sysent->sv_thread_detach)(td); + umtx_thread_exit(td); kern_thr_exit(td); panic("stopped thread did not exit"); } diff --git a/sys/kern/kern_umtx.c b/sys/kern/kern_umtx.c index 7ceb2cc..8471591 100644 --- a/sys/kern/kern_umtx.c +++ b/sys/kern/kern_umtx.c @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2015 The FreeBSD Foundation + * Copyright (c) 2015, 2016 The FreeBSD Foundation * Copyright (c) 2004, David Xu <davidxu@freebsd.org> * Copyright (c) 2002, Jeffrey Roberson <jeff@freebsd.org> * All rights reserved. @@ -212,6 +212,30 @@ struct abs_timeout { struct timespec end; }; +#ifdef COMPAT_FREEBSD32 +struct umutex32 { + volatile __lwpid_t m_owner; /* Owner of the mutex */ + __uint32_t m_flags; /* Flags of the mutex */ + __uint32_t m_ceilings[2]; /* Priority protect ceiling */ + __uint32_t m_rb_lnk; /* Robust linkage */ + __uint32_t m_pad; + __uint32_t m_spare[2]; +}; + +_Static_assert(sizeof(struct umutex) == sizeof(struct umutex32), "umutex32"); +_Static_assert(__offsetof(struct umutex, m_spare[0]) == + __offsetof(struct umutex32, m_spare[0]), "m_spare32"); +#endif + +int umtx_shm_vnobj_persistent = 0; +SYSCTL_INT(_kern_ipc, OID_AUTO, umtx_vnode_persistent, CTLFLAG_RWTUN, + &umtx_shm_vnobj_persistent, 0, + "False forces destruction of umtx attached to file, on last close"); +static int umtx_max_rb = 1000; +SYSCTL_INT(_kern_ipc, OID_AUTO, umtx_max_robust, CTLFLAG_RWTUN, + &umtx_max_rb, 0, + ""); + static uma_zone_t umtx_pi_zone; static struct umtxq_chain umtxq_chains[2][UMTX_CHAINS]; static MALLOC_DEFINE(M_UMTX, "umtx", "UMTX queue memory"); @@ -220,6 +244,10 @@ static int umtx_pi_allocated; static SYSCTL_NODE(_debug, OID_AUTO, umtx, CTLFLAG_RW, 0, "umtx debug"); SYSCTL_INT(_debug_umtx, OID_AUTO, umtx_pi_allocated, CTLFLAG_RD, &umtx_pi_allocated, 0, "Allocated umtx_pi"); +static int umtx_verbose_rb = 1; +SYSCTL_INT(_debug_umtx, OID_AUTO, robust_faults_verbose, CTLFLAG_RWTUN, + &umtx_verbose_rb, 0, + ""); #ifdef UMTX_PROFILING static long max_length; @@ -241,10 +269,11 @@ static int umtxq_sleep(struct umtx_q *uq, const char *wmesg, struct abs_timeout static int umtxq_count(struct umtx_key *key); static struct umtx_pi *umtx_pi_alloc(int); static void umtx_pi_free(struct umtx_pi *pi); -static int do_unlock_pp(struct thread *td, struct umutex *m, uint32_t flags); +static int do_unlock_pp(struct thread *td, struct umutex *m, uint32_t flags, + bool rb); static void umtx_thread_cleanup(struct thread *td); static void umtx_exec_hook(void *arg __unused, struct proc *p __unused, - struct image_params *imgp __unused); + struct image_params *imgp __unused); SYSINIT(umtx, SI_SUB_EVENTHANDLER+1, SI_ORDER_MIDDLE, umtxq_sysinit, NULL); #define umtxq_signal(key, nwake) umtxq_signal_queue((key), (nwake), UMTX_SHARED_QUEUE) @@ -423,7 +452,8 @@ umtxq_alloc(void) struct umtx_q *uq; uq = malloc(sizeof(struct umtx_q), M_UMTX, M_WAITOK | M_ZERO); - uq->uq_spare_queue = malloc(sizeof(struct umtxq_queue), M_UMTX, M_WAITOK | M_ZERO); + uq->uq_spare_queue = malloc(sizeof(struct umtxq_queue), M_UMTX, + M_WAITOK | M_ZERO); TAILQ_INIT(&uq->uq_spare_queue->head); TAILQ_INIT(&uq->uq_pi_contested); uq->uq_inherited_pri = PRI_MAX; @@ -433,6 +463,7 @@ umtxq_alloc(void) void umtxq_free(struct umtx_q *uq) { + MPASS(uq->uq_spare_queue != NULL); free(uq->uq_spare_queue, M_UMTX); free(uq, M_UMTX); @@ -441,13 +472,16 @@ umtxq_free(struct umtx_q *uq) static inline void umtxq_hash(struct umtx_key *key) { - unsigned n = (uintptr_t)key->info.both.a + key->info.both.b; + unsigned n; + + n = (uintptr_t)key->info.both.a + key->info.both.b; key->hash = ((n * GOLDEN_RATIO_PRIME) >> UMTX_SHIFTS) % UMTX_CHAINS; } static inline struct umtxq_chain * umtxq_getchain(struct umtx_key *key) { + if (key->type <= TYPE_SEM) return (&umtxq_chains[1][key->hash]); return (&umtxq_chains[0][key->hash]); @@ -750,13 +784,13 @@ abs_timeout_init2(struct abs_timeout *timo, const struct _umtx_time *umtxtime) { abs_timeout_init(timo, umtxtime->_clockid, - (umtxtime->_flags & UMTX_ABSTIME) != 0, - &umtxtime->_timeout); + (umtxtime->_flags & UMTX_ABSTIME) != 0, &umtxtime->_timeout); } static inline void abs_timeout_update(struct abs_timeout *timo) { + kern_clock_gettime(curthread, timo->clockid, &timo->cur); } @@ -772,6 +806,19 @@ abs_timeout_gethz(struct abs_timeout *timo) return (tstohz(&tts)); } +static uint32_t +umtx_unlock_val(uint32_t flags, bool rb) +{ + + if (rb) + return (UMUTEX_RB_OWNERDEAD); + else if ((flags & UMUTEX_NONCONSISTENT) != 0) + return (UMUTEX_RB_NOTRECOV); + else + return (UMUTEX_UNOWNED); + +} + /* * Put thread into sleep state, before sleeping, check if * thread was removed from umtx queue. @@ -866,7 +913,7 @@ umtx_key_release(struct umtx_key *key) */ static int do_wait(struct thread *td, void *addr, u_long id, - struct _umtx_time *timeout, int compat32, int is_private) + struct _umtx_time *timeout, int compat32, int is_private) { struct abs_timeout timo; struct umtx_q *uq; @@ -925,7 +972,7 @@ kern_umtx_wake(struct thread *td, void *uaddr, int n_wake, int is_private) int ret; if ((ret = umtx_key_get(uaddr, TYPE_SIMPLE_WAIT, - is_private ? THREAD_SHARE : AUTO_SHARE, &key)) != 0) + is_private ? THREAD_SHARE : AUTO_SHARE, &key)) != 0) return (ret); umtxq_lock(&key); umtxq_signal(&key, n_wake); @@ -939,7 +986,7 @@ kern_umtx_wake(struct thread *td, void *uaddr, int n_wake, int is_private) */ static int do_lock_normal(struct thread *td, struct umutex *m, uint32_t flags, - struct _umtx_time *timeout, int mode) + struct _umtx_time *timeout, int mode) { struct abs_timeout timo; struct umtx_q *uq; @@ -961,11 +1008,38 @@ do_lock_normal(struct thread *td, struct umutex *m, uint32_t flags, if (rv == -1) return (EFAULT); if (mode == _UMUTEX_WAIT) { - if (owner == UMUTEX_UNOWNED || owner == UMUTEX_CONTESTED) + if (owner == UMUTEX_UNOWNED || + owner == UMUTEX_CONTESTED || + owner == UMUTEX_RB_OWNERDEAD || + owner == UMUTEX_RB_NOTRECOV) return (0); } else { /* - * Try the uncontested case. This should be done in userland. + * Robust mutex terminated. Kernel duty is to + * return EOWNERDEAD to the userspace. The + * umutex.m_flags UMUTEX_NONCONSISTENT is set + * by the common userspace code. + */ + if (owner == UMUTEX_RB_OWNERDEAD) { + rv = casueword32(&m->m_owner, + UMUTEX_RB_OWNERDEAD, &owner, + id | UMUTEX_CONTESTED); + if (rv == -1) + return (EFAULT); + if (owner == UMUTEX_RB_OWNERDEAD) + return (EOWNERDEAD); /* success */ + rv = umtxq_check_susp(td); + if (rv != 0) + return (rv); + continue; + } + if (owner == UMUTEX_RB_NOTRECOV) + return (ENOTRECOVERABLE); + + + /* + * Try the uncontested case. This should be + * done in userland. */ rv = casueword32(&m->m_owner, UMUTEX_UNOWNED, &owner, id); @@ -977,7 +1051,10 @@ do_lock_normal(struct thread *td, struct umutex *m, uint32_t flags, if (owner == UMUTEX_UNOWNED) return (0); - /* If no one owns it but it is contested try to acquire it. */ + /* + * If no one owns it but it is contested try + * to acquire it. + */ if (owner == UMUTEX_CONTESTED) { rv = casueword32(&m->m_owner, UMUTEX_CONTESTED, &owner, @@ -993,7 +1070,10 @@ do_lock_normal(struct thread *td, struct umutex *m, uint32_t flags, if (rv != 0) return (rv); - /* If this failed the lock has changed, restart. */ + /* + * If this failed the lock has + * changed, restart. + */ continue; } } @@ -1061,12 +1141,11 @@ do_lock_normal(struct thread *td, struct umutex *m, uint32_t flags, * Unlock PTHREAD_PRIO_NONE protocol POSIX mutex. */ static int -do_unlock_normal(struct thread *td, struct umutex *m, uint32_t flags) +do_unlock_normal(struct thread *td, struct umutex *m, uint32_t flags, bool rb) { struct umtx_key key; - uint32_t owner, old, id; - int error; - int count; + uint32_t owner, old, id, newlock; + int error, count; id = td->td_tid; /* @@ -1079,8 +1158,9 @@ do_unlock_normal(struct thread *td, struct umutex *m, uint32_t flags) if ((owner & ~UMUTEX_CONTESTED) != id) return (EPERM); + newlock = umtx_unlock_val(flags, rb); if ((owner & UMUTEX_CONTESTED) == 0) { - error = casueword32(&m->m_owner, owner, &old, UMUTEX_UNOWNED); + error = casueword32(&m->m_owner, owner, &old, newlock); if (error == -1) return (EFAULT); if (old == owner) @@ -1103,10 +1183,11 @@ do_unlock_normal(struct thread *td, struct umutex *m, uint32_t flags) * there is zero or one thread only waiting for it. * Otherwise, it must be marked as contested. */ - error = casueword32(&m->m_owner, owner, &old, - count <= 1 ? UMUTEX_UNOWNED : UMUTEX_CONTESTED); + if (count > 1) + newlock |= UMUTEX_CONTESTED; + error = casueword32(&m->m_owner, owner, &old, newlock); umtxq_lock(&key); - umtxq_signal(&key,1); + umtxq_signal(&key, 1); umtxq_unbusy(&key); umtxq_unlock(&key); umtx_key_release(&key); @@ -1134,7 +1215,8 @@ do_wake_umutex(struct thread *td, struct umutex *m) if (error == -1) return (EFAULT); - if ((owner & ~UMUTEX_CONTESTED) != 0) + if ((owner & ~UMUTEX_CONTESTED) != 0 && owner != UMUTEX_RB_OWNERDEAD && + owner != UMUTEX_RB_NOTRECOV) return (0); error = fueword32(&m->m_flags, &flags); @@ -1151,7 +1233,8 @@ do_wake_umutex(struct thread *td, struct umutex *m) count = umtxq_count(&key); umtxq_unlock(&key); - if (count <= 1) { + if (count <= 1 && owner != UMUTEX_RB_OWNERDEAD && + owner != UMUTEX_RB_NOTRECOV) { error = casueword32(&m->m_owner, UMUTEX_CONTESTED, &owner, UMUTEX_UNOWNED); if (error == -1) @@ -1159,7 +1242,8 @@ do_wake_umutex(struct thread *td, struct umutex *m) } umtxq_lock(&key); - if (error == 0 && count != 0 && (owner & ~UMUTEX_CONTESTED) == 0) + if (error == 0 && count != 0 && ((owner & ~UMUTEX_CONTESTED) == 0 || + owner == UMUTEX_RB_OWNERDEAD || owner == UMUTEX_RB_NOTRECOV)) umtxq_signal(&key, 1); umtxq_unbusy(&key); umtxq_unlock(&key); @@ -1179,21 +1263,28 @@ do_wake2_umutex(struct thread *td, struct umutex *m, uint32_t flags) int error; int count; - switch (flags & (UMUTEX_PRIO_INHERIT | UMUTEX_PRIO_PROTECT)) { + switch (flags & (UMUTEX_PRIO_INHERIT | UMUTEX_PRIO_PROTECT | + UMUTEX_ROBUST)) { case 0: + case UMUTEX_ROBUST: type = TYPE_NORMAL_UMUTEX; break; case UMUTEX_PRIO_INHERIT: type = TYPE_PI_UMUTEX; break; + case (UMUTEX_PRIO_INHERIT | UMUTEX_ROBUST): + type = TYPE_PI_ROBUST_UMUTEX; + break; case UMUTEX_PRIO_PROTECT: type = TYPE_PP_UMUTEX; break; + case (UMUTEX_PRIO_PROTECT | UMUTEX_ROBUST): + type = TYPE_PP_ROBUST_UMUTEX; + break; default: return (EINVAL); } - if ((error = umtx_key_get(m, type, GET_SHARE(flags), - &key)) != 0) + if ((error = umtx_key_get(m, type, GET_SHARE(flags), &key)) != 0) return (error); owner = 0; @@ -1229,7 +1320,7 @@ do_wake2_umutex(struct thread *td, struct umutex *m, uint32_t flags) if (error == -1) error = EFAULT; while (error == 0 && (owner & ~UMUTEX_CONTESTED) != 0 && - (owner & UMUTEX_CONTESTED) == 0) { + (owner & UMUTEX_CONTESTED) == 0) { error = casueword32(&m->m_owner, owner, &old, owner | UMUTEX_CONTESTED); if (error == -1) { @@ -1247,7 +1338,8 @@ do_wake2_umutex(struct thread *td, struct umutex *m, uint32_t flags) umtxq_lock(&key); if (error == EFAULT) { umtxq_signal(&key, INT_MAX); - } else if (count != 0 && (owner & ~UMUTEX_CONTESTED) == 0) + } else if (count != 0 && ((owner & ~UMUTEX_CONTESTED) == 0 || + owner == UMUTEX_RB_OWNERDEAD || owner == UMUTEX_RB_NOTRECOV)) umtxq_signal(&key, 1); umtxq_unbusy(&key); umtxq_unlock(&key); @@ -1481,6 +1573,7 @@ static int umtx_pi_claim(struct umtx_pi *pi, struct thread *owner) { struct umtx_q *uq; + int pri; mtx_lock(&umtx_lock); if (pi->pi_owner == owner) { @@ -1498,8 +1591,6 @@ umtx_pi_claim(struct umtx_pi *pi, struct thread *owner) umtx_pi_setowner(pi, owner); uq = TAILQ_FIRST(&pi->pi_blocked); if (uq != NULL) { - int pri; - pri = UPRI(uq->uq_thread); thread_lock(owner); if (pri < UPRI(owner)) @@ -1537,15 +1628,15 @@ umtx_pi_adjust(struct thread *td, u_char oldpri) * Sleep on a PI mutex. */ static int -umtxq_sleep_pi(struct umtx_q *uq, struct umtx_pi *pi, - uint32_t owner, const char *wmesg, struct abs_timeout *timo) +umtxq_sleep_pi(struct umtx_q *uq, struct umtx_pi *pi, uint32_t owner, + const char *wmesg, struct abs_timeout *timo, bool shared) { struct umtxq_chain *uc; struct thread *td, *td1; struct umtx_q *uq1; - int pri; - int error = 0; + int error, pri; + error = 0; td = uq->uq_thread; KASSERT(td == curthread, ("inconsistent uq_thread")); uc = umtxq_getchain(&uq->uq_key); @@ -1555,8 +1646,7 @@ umtxq_sleep_pi(struct umtx_q *uq, struct umtx_pi *pi, mtx_lock(&umtx_lock); if (pi->pi_owner == NULL) { mtx_unlock(&umtx_lock); - /* XXX Only look up thread in current process. */ - td1 = tdfind(owner, curproc->p_pid); + td1 = tdfind(owner, shared ? -1 : td->td_proc->p_pid); mtx_lock(&umtx_lock); if (td1 != NULL) { if (pi->pi_owner == NULL) @@ -1680,13 +1770,14 @@ do_lock_pi(struct thread *td, struct umutex *m, uint32_t flags, struct abs_timeout timo; struct umtx_q *uq; struct umtx_pi *pi, *new_pi; - uint32_t id, owner, old; + uint32_t id, old_owner, owner, old; int error, rv; id = td->td_tid; uq = td->td_umtxq; - if ((error = umtx_key_get(m, TYPE_PI_UMUTEX, GET_SHARE(flags), + if ((error = umtx_key_get(m, (flags & UMUTEX_ROBUST) != 0 ? + TYPE_PI_ROBUST_UMUTEX : TYPE_PI_UMUTEX, GET_SHARE(flags), &uq->uq_key)) != 0) return (error); @@ -1737,17 +1828,23 @@ do_lock_pi(struct thread *td, struct umutex *m, uint32_t flags, break; } + if (owner == UMUTEX_RB_NOTRECOV) { + error = ENOTRECOVERABLE; + break; + } + /* If no one owns it but it is contested try to acquire it. */ - if (owner == UMUTEX_CONTESTED) { - rv = casueword32(&m->m_owner, - UMUTEX_CONTESTED, &owner, id | UMUTEX_CONTESTED); + if (owner == UMUTEX_CONTESTED || owner == UMUTEX_RB_OWNERDEAD) { + old_owner = owner; + rv = casueword32(&m->m_owner, owner, &owner, + id | UMUTEX_CONTESTED); /* The address was invalid. */ if (rv == -1) { error = EFAULT; break; } - if (owner == UMUTEX_CONTESTED) { + if (owner == old_owner) { umtxq_lock(&uq->uq_key); umtxq_busy(&uq->uq_key); error = umtx_pi_claim(pi, td); @@ -1762,8 +1859,11 @@ do_lock_pi(struct thread *td, struct umutex *m, uint32_t flags, */ (void)casuword32(&m->m_owner, id | UMUTEX_CONTESTED, - UMUTEX_CONTESTED); + old_owner); } + if (error == 0 && + old_owner == UMUTEX_RB_OWNERDEAD) + error = EOWNERDEAD; break; } @@ -1802,8 +1902,8 @@ do_lock_pi(struct thread *td, struct umutex *m, uint32_t flags, * either some one else has acquired the lock or it has been * released. */ - rv = casueword32(&m->m_owner, owner, &old, - owner | UMUTEX_CONTESTED); + rv = casueword32(&m->m_owner, owner, &old, owner | + UMUTEX_CONTESTED); /* The address was invalid. */ if (rv == -1) { @@ -1816,11 +1916,14 @@ do_lock_pi(struct thread *td, struct umutex *m, uint32_t flags, /* * We set the contested bit, sleep. Otherwise the lock changed * and we need to retry or we lost a race to the thread - * unlocking the umtx. + * unlocking the umtx. Note that the UMUTEX_RB_OWNERDEAD + * value for owner is impossible there. */ if (old == owner) { - error = umtxq_sleep_pi(uq, pi, owner & ~UMUTEX_CONTESTED, - "umtxpi", timeout == NULL ? NULL : &timo); + error = umtxq_sleep_pi(uq, pi, + owner & ~UMUTEX_CONTESTED, + "umtxpi", timeout == NULL ? NULL : &timo, + (flags & USYNC_PROCESS_SHARED) != 0); if (error != 0) continue; } else { @@ -1845,15 +1948,13 @@ do_lock_pi(struct thread *td, struct umutex *m, uint32_t flags, * Unlock a PI mutex. */ static int -do_unlock_pi(struct thread *td, struct umutex *m, uint32_t flags) +do_unlock_pi(struct thread *td, struct umutex *m, uint32_t flags, bool rb) { struct umtx_key key; struct umtx_q *uq_first, *uq_first2, *uq_me; struct umtx_pi *pi, *pi2; - uint32_t owner, old, id; - int error; - int count; - int pri; + uint32_t id, new_owner, old, owner; + int count, error, pri; id = td->td_tid; /* @@ -1866,9 +1967,11 @@ do_unlock_pi(struct thread *td, struct umutex *m, uint32_t flags) if ((owner & ~UMUTEX_CONTESTED) != id) return (EPERM); + new_owner = umtx_unlock_val(flags, rb); + /* This should be done in userland */ if ((owner & UMUTEX_CONTESTED) == 0) { - error = casueword32(&m->m_owner, owner, &old, UMUTEX_UNOWNED); + error = casueword32(&m->m_owner, owner, &old, new_owner); if (error == -1) return (EFAULT); if (old == owner) @@ -1877,7 +1980,8 @@ do_unlock_pi(struct thread *td, struct umutex *m, uint32_t flags) } /* We should only ever be in here for contested locks */ - if ((error = umtx_key_get(m, TYPE_PI_UMUTEX, GET_SHARE(flags), + if ((error = umtx_key_get(m, (flags & UMUTEX_ROBUST) != 0 ? + TYPE_PI_ROBUST_UMUTEX : TYPE_PI_UMUTEX, GET_SHARE(flags), &key)) != 0) return (error); @@ -1888,7 +1992,7 @@ do_unlock_pi(struct thread *td, struct umutex *m, uint32_t flags) mtx_lock(&umtx_lock); pi = uq_first->uq_pi_blocked; KASSERT(pi != NULL, ("pi == NULL?")); - if (pi->pi_owner != td) { + if (pi->pi_owner != td && !(rb && pi->pi_owner == NULL)) { mtx_unlock(&umtx_lock); umtxq_unbusy(&key); umtxq_unlock(&key); @@ -1897,11 +2001,12 @@ do_unlock_pi(struct thread *td, struct umutex *m, uint32_t flags) return (EPERM); } uq_me = td->td_umtxq; - umtx_pi_disown(pi); + if (pi->pi_owner == td) + umtx_pi_disown(pi); /* get highest priority thread which is still sleeping. */ uq_first = TAILQ_FIRST(&pi->pi_blocked); while (uq_first != NULL && - (uq_first->uq_flags & UQF_UMTXQ) == 0) { + (uq_first->uq_flags & UQF_UMTXQ) == 0) { uq_first = TAILQ_NEXT(uq_first, uq_lockq); } pri = PRI_MAX; @@ -1945,8 +2050,10 @@ do_unlock_pi(struct thread *td, struct umutex *m, uint32_t flags) * there is zero or one thread only waiting for it. * Otherwise, it must be marked as contested. */ - error = casueword32(&m->m_owner, owner, &old, - count <= 1 ? UMUTEX_UNOWNED : UMUTEX_CONTESTED); + + if (count > 1) + new_owner |= UMUTEX_CONTESTED; + error = casueword32(&m->m_owner, owner, &old, new_owner); umtxq_unbusy_unlocked(&key); umtx_key_release(&key); @@ -1973,7 +2080,8 @@ do_lock_pp(struct thread *td, struct umutex *m, uint32_t flags, id = td->td_tid; uq = td->td_umtxq; - if ((error = umtx_key_get(m, TYPE_PP_UMUTEX, GET_SHARE(flags), + if ((error = umtx_key_get(m, (flags & UMUTEX_ROBUST) != 0 ? + TYPE_PP_ROBUST_UMUTEX : TYPE_PP_UMUTEX, GET_SHARE(flags), &uq->uq_key)) != 0) return (error); @@ -2013,8 +2121,8 @@ do_lock_pp(struct thread *td, struct umutex *m, uint32_t flags, } mtx_unlock(&umtx_lock); - rv = casueword32(&m->m_owner, - UMUTEX_CONTESTED, &owner, id | UMUTEX_CONTESTED); + rv = casueword32(&m->m_owner, UMUTEX_CONTESTED, &owner, + id | UMUTEX_CONTESTED); /* The address was invalid. */ if (rv == -1) { error = EFAULT; @@ -2024,6 +2132,21 @@ do_lock_pp(struct thread *td, struct umutex *m, uint32_t flags, if (owner == UMUTEX_CONTESTED) { error = 0; break; + } else if (owner == UMUTEX_RB_OWNERDEAD) { + rv = casueword32(&m->m_owner, UMUTEX_RB_OWNERDEAD, + &owner, id | UMUTEX_CONTESTED); + if (rv == -1) { + error = EFAULT; + break; + } + if (owner == UMUTEX_RB_OWNERDEAD) { + error = EOWNERDEAD; /* success */ + break; + } + error = 0; + } else if (owner == UMUTEX_RB_NOTRECOV) { + error = ENOTRECOVERABLE; + break; } if (try != 0) { @@ -2064,7 +2187,7 @@ do_lock_pp(struct thread *td, struct umutex *m, uint32_t flags, mtx_unlock(&umtx_lock); } - if (error != 0) { + if (error != 0 && error != EOWNERDEAD) { mtx_lock(&umtx_lock); uq->uq_inherited_pri = old_inherited_pri; pri = PRI_MAX; @@ -2093,13 +2216,12 @@ out: * Unlock a PP mutex. */ static int -do_unlock_pp(struct thread *td, struct umutex *m, uint32_t flags) +do_unlock_pp(struct thread *td, struct umutex *m, uint32_t flags, bool rb) { struct umtx_key key; struct umtx_q *uq, *uq2; struct umtx_pi *pi; - uint32_t owner, id; - uint32_t rceiling; + uint32_t id, owner, rceiling; int error, pri, new_inherited_pri, su; id = td->td_tid; @@ -2129,7 +2251,8 @@ do_unlock_pp(struct thread *td, struct umutex *m, uint32_t flags) new_inherited_pri = PRI_MIN_REALTIME + rceiling; } - if ((error = umtx_key_get(m, TYPE_PP_UMUTEX, GET_SHARE(flags), + if ((error = umtx_key_get(m, (flags & UMUTEX_ROBUST) != 0 ? + TYPE_PP_ROBUST_UMUTEX : TYPE_PP_UMUTEX, GET_SHARE(flags), &key)) != 0) return (error); umtxq_lock(&key); @@ -2141,7 +2264,8 @@ do_unlock_pp(struct thread *td, struct umutex *m, uint32_t flags) * to lock the mutex, it is necessary because thread priority * has to be adjusted for such mutex. */ - error = suword32(&m->m_owner, UMUTEX_CONTESTED); + error = suword32(&m->m_owner, umtx_unlock_val(flags, rb) | + UMUTEX_CONTESTED); umtxq_lock(&key); if (error == 0) @@ -2176,13 +2300,11 @@ do_unlock_pp(struct thread *td, struct umutex *m, uint32_t flags) static int do_set_ceiling(struct thread *td, struct umutex *m, uint32_t ceiling, - uint32_t *old_ceiling) + uint32_t *old_ceiling) { struct umtx_q *uq; - uint32_t save_ceiling; - uint32_t owner, id; - uint32_t flags; - int error, rv; + uint32_t flags, id, owner, save_ceiling; + int error, rv, rv1; error = fueword32(&m->m_flags, &flags); if (error == -1) @@ -2193,8 +2315,9 @@ do_set_ceiling(struct thread *td, struct umutex *m, uint32_t ceiling, return (EINVAL); id = td->td_tid; uq = td->td_umtxq; - if ((error = umtx_key_get(m, TYPE_PP_UMUTEX, GET_SHARE(flags), - &uq->uq_key)) != 0) + if ((error = umtx_key_get(m, (flags & UMUTEX_ROBUST) != 0 ? + TYPE_PP_ROBUST_UMUTEX : TYPE_PP_UMUTEX, GET_SHARE(flags), + &uq->uq_key)) != 0) return (error); for (;;) { umtxq_lock(&uq->uq_key); @@ -2207,23 +2330,31 @@ do_set_ceiling(struct thread *td, struct umutex *m, uint32_t ceiling, break; } - rv = casueword32(&m->m_owner, - UMUTEX_CONTESTED, &owner, id | UMUTEX_CONTESTED); + rv = casueword32(&m->m_owner, UMUTEX_CONTESTED, &owner, + id | UMUTEX_CONTESTED); if (rv == -1) { error = EFAULT; break; } if (owner == UMUTEX_CONTESTED) { - suword32(&m->m_ceilings[0], ceiling); - suword32(&m->m_owner, UMUTEX_CONTESTED); - error = 0; + rv = suword32(&m->m_ceilings[0], ceiling); + rv1 = suword32(&m->m_owner, UMUTEX_CONTESTED); + error = (rv == 0 && rv1 == 0) ? 0: EFAULT; break; } if ((owner & ~UMUTEX_CONTESTED) == id) { - suword32(&m->m_ceilings[0], ceiling); - error = 0; + rv = suword32(&m->m_ceilings[0], ceiling); + error = rv == 0 ? 0 : EFAULT; + break; + } + + if (owner == UMUTEX_RB_OWNERDEAD) { + error = EOWNERDEAD; + break; + } else if (owner == UMUTEX_RB_NOTRECOV) { + error = ENOTRECOVERABLE; break; } @@ -2252,8 +2383,10 @@ do_set_ceiling(struct thread *td, struct umutex *m, uint32_t ceiling, umtxq_unbusy(&uq->uq_key); umtxq_unlock(&uq->uq_key); umtx_key_release(&uq->uq_key); - if (error == 0 && old_ceiling != NULL) - suword32(old_ceiling, save_ceiling); + if (error == 0 && old_ceiling != NULL) { + rv = suword32(old_ceiling, save_ceiling); + error = rv == 0 ? 0 : EFAULT; + } return (error); } @@ -2271,7 +2404,7 @@ do_lock_umutex(struct thread *td, struct umutex *m, if (error == -1) return (EFAULT); - switch(flags & (UMUTEX_PRIO_INHERIT | UMUTEX_PRIO_PROTECT)) { + switch (flags & (UMUTEX_PRIO_INHERIT | UMUTEX_PRIO_PROTECT)) { case 0: error = do_lock_normal(td, m, flags, timeout, mode); break; @@ -2299,7 +2432,7 @@ do_lock_umutex(struct thread *td, struct umutex *m, * Unlock a userland POSIX mutex. */ static int -do_unlock_umutex(struct thread *td, struct umutex *m) +do_unlock_umutex(struct thread *td, struct umutex *m, bool rb) { uint32_t flags; int error; @@ -2308,13 +2441,13 @@ do_unlock_umutex(struct thread *td, struct umutex *m) if (error == -1) return (EFAULT); - switch(flags & (UMUTEX_PRIO_INHERIT | UMUTEX_PRIO_PROTECT)) { + switch (flags & (UMUTEX_PRIO_INHERIT | UMUTEX_PRIO_PROTECT)) { case 0: - return (do_unlock_normal(td, m, flags)); + return (do_unlock_normal(td, m, flags, rb)); case UMUTEX_PRIO_INHERIT: - return (do_unlock_pi(td, m, flags)); + return (do_unlock_pi(td, m, flags, rb)); case UMUTEX_PRIO_PROTECT: - return (do_unlock_pp(td, m, flags)); + return (do_unlock_pp(td, m, flags, rb)); } return (EINVAL); @@ -2322,7 +2455,7 @@ do_unlock_umutex(struct thread *td, struct umutex *m) static int do_cv_wait(struct thread *td, struct ucond *cv, struct umutex *m, - struct timespec *timeout, u_long wflags) + struct timespec *timeout, u_long wflags) { struct abs_timeout timo; struct umtx_q *uq; @@ -2368,11 +2501,11 @@ do_cv_wait(struct thread *td, struct ucond *cv, struct umutex *m, umtxq_unbusy_unlocked(&uq->uq_key); - error = do_unlock_umutex(td, m); + error = do_unlock_umutex(td, m, false); if (timeout != NULL) - abs_timeout_init(&timo, clockid, ((wflags & CVWAIT_ABSTIME) != 0), - timeout); + abs_timeout_init(&timo, clockid, (wflags & CVWAIT_ABSTIME) != 0, + timeout); umtxq_lock(&uq->uq_key); if (error == 0) { @@ -3181,7 +3314,7 @@ __umtx_op_wait(struct thread *td, struct _umtx_op_args *uap) return (error); tm_p = &timeout; } - return do_wait(td, uap->obj, uap->val, tm_p, 0, 0); + return (do_wait(td, uap->obj, uap->val, tm_p, 0, 0)); } static int @@ -3199,7 +3332,7 @@ __umtx_op_wait_uint(struct thread *td, struct _umtx_op_args *uap) return (error); tm_p = &timeout; } - return do_wait(td, uap->obj, uap->val, tm_p, 1, 0); + return (do_wait(td, uap->obj, uap->val, tm_p, 1, 0)); } static int @@ -3217,12 +3350,13 @@ __umtx_op_wait_uint_private(struct thread *td, struct _umtx_op_args *uap) return (error); tm_p = &timeout; } - return do_wait(td, uap->obj, uap->val, tm_p, 1, 1); + return (do_wait(td, uap->obj, uap->val, tm_p, 1, 1)); } static int __umtx_op_wake(struct thread *td, struct _umtx_op_args *uap) { + return (kern_umtx_wake(td, uap->obj, uap->val, 0)); } @@ -3230,24 +3364,20 @@ __umtx_op_wake(struct thread *td, struct _umtx_op_args *uap) static int __umtx_op_nwake_private(struct thread *td, struct _umtx_op_args *uap) { - int count = uap->val; - void *uaddrs[BATCH_SIZE]; - char **upp = (char **)uap->obj; - int tocopy; - int error = 0; - int i, pos = 0; + char *uaddrs[BATCH_SIZE], **upp; + int count, error, i, pos, tocopy; - while (count > 0) { - tocopy = count; - if (tocopy > BATCH_SIZE) - tocopy = BATCH_SIZE; - error = copyin(upp+pos, uaddrs, tocopy * sizeof(char *)); + upp = (char **)uap->obj; + error = 0; + for (count = uap->val, pos = 0; count > 0; count -= tocopy, + pos += tocopy) { + tocopy = MIN(count, BATCH_SIZE); + error = copyin(upp + pos, uaddrs, tocopy * sizeof(char *)); if (error != 0) break; for (i = 0; i < tocopy; ++i) kern_umtx_wake(td, uaddrs[i], INT_MAX, 1); - count -= tocopy; - pos += tocopy; + maybe_yield(); } return (error); } @@ -3255,6 +3385,7 @@ __umtx_op_nwake_private(struct thread *td, struct _umtx_op_args *uap) static int __umtx_op_wake_private(struct thread *td, struct _umtx_op_args *uap) { + return (kern_umtx_wake(td, uap->obj, uap->val, 1)); } @@ -3274,13 +3405,14 @@ __umtx_op_lock_umutex(struct thread *td, struct _umtx_op_args *uap) return (error); tm_p = &timeout; } - return do_lock_umutex(td, uap->obj, tm_p, 0); + return (do_lock_umutex(td, uap->obj, tm_p, 0)); } static int __umtx_op_trylock_umutex(struct thread *td, struct _umtx_op_args *uap) { - return do_lock_umutex(td, uap->obj, NULL, _UMUTEX_TRY); + + return (do_lock_umutex(td, uap->obj, NULL, _UMUTEX_TRY)); } static int @@ -3299,25 +3431,28 @@ __umtx_op_wait_umutex(struct thread *td, struct _umtx_op_args *uap) return (error); tm_p = &timeout; } - return do_lock_umutex(td, uap->obj, tm_p, _UMUTEX_WAIT); + return (do_lock_umutex(td, uap->obj, tm_p, _UMUTEX_WAIT)); } static int __umtx_op_wake_umutex(struct thread *td, struct _umtx_op_args *uap) { - return do_wake_umutex(td, uap->obj); + + return (do_wake_umutex(td, uap->obj)); } static int __umtx_op_unlock_umutex(struct thread *td, struct _umtx_op_args *uap) { - return do_unlock_umutex(td, uap->obj); + + return (do_unlock_umutex(td, uap->obj, false)); } static int __umtx_op_set_ceiling(struct thread *td, struct _umtx_op_args *uap) { - return do_set_ceiling(td, uap->obj, uap->val, uap->uaddr1); + + return (do_set_ceiling(td, uap->obj, uap->val, uap->uaddr1)); } static int @@ -3341,13 +3476,15 @@ __umtx_op_cv_wait(struct thread *td, struct _umtx_op_args *uap) static int __umtx_op_cv_signal(struct thread *td, struct _umtx_op_args *uap) { - return do_cv_signal(td, uap->obj); + + return (do_cv_signal(td, uap->obj)); } static int __umtx_op_cv_broadcast(struct thread *td, struct _umtx_op_args *uap) { - return do_cv_broadcast(td, uap->obj); + + return (do_cv_broadcast(td, uap->obj)); } static int @@ -3392,7 +3529,8 @@ __umtx_op_rw_wrlock(struct thread *td, struct _umtx_op_args *uap) static int __umtx_op_rw_unlock(struct thread *td, struct _umtx_op_args *uap) { - return do_rw_unlock(td, uap->obj); + + return (do_rw_unlock(td, uap->obj)); } #if defined(COMPAT_FREEBSD9) || defined(COMPAT_FREEBSD10) @@ -3760,6 +3898,31 @@ __umtx_op_shm(struct thread *td, struct _umtx_op_args *uap) return (umtx_shm(td, uap->uaddr1, uap->val)); } +static int +umtx_robust_lists(struct thread *td, struct umtx_robust_lists_params *rbp) +{ + + td->td_rb_list = rbp->robust_list_offset; + td->td_rbp_list = rbp->robust_priv_list_offset; + td->td_rb_inact = rbp->robust_inact_offset; + return (0); +} + +static int +__umtx_op_robust_lists(struct thread *td, struct _umtx_op_args *uap) +{ + struct umtx_robust_lists_params rb; + int error; + + if (uap->val > sizeof(rb)) + return (EINVAL); + bzero(&rb, sizeof(rb)); + error = copyin(uap->uaddr1, &rb, uap->val); + if (error != 0) + return (error); + return (umtx_robust_lists(td, &rb)); +} + typedef int (*_umtx_op_func)(struct thread *td, struct _umtx_op_args *uap); static const _umtx_op_func op_table[] = { @@ -3794,6 +3957,7 @@ static const _umtx_op_func op_table[] = { [UMTX_OP_SEM2_WAIT] = __umtx_op_sem2_wait, [UMTX_OP_SEM2_WAKE] = __umtx_op_sem2_wake, [UMTX_OP_SHM] = __umtx_op_shm, + [UMTX_OP_ROBUST_LISTS] = __umtx_op_robust_lists, }; int @@ -3877,7 +4041,7 @@ __umtx_op_wait_compat32(struct thread *td, struct _umtx_op_args *uap) return (error); tm_p = &timeout; } - return do_wait(td, uap->obj, uap->val, tm_p, 1, 0); + return (do_wait(td, uap->obj, uap->val, tm_p, 1, 0)); } static int @@ -3896,7 +4060,7 @@ __umtx_op_lock_umutex_compat32(struct thread *td, struct _umtx_op_args *uap) return (error); tm_p = &timeout; } - return do_lock_umutex(td, uap->obj, tm_p, 0); + return (do_lock_umutex(td, uap->obj, tm_p, 0)); } static int @@ -3915,7 +4079,7 @@ __umtx_op_wait_umutex_compat32(struct thread *td, struct _umtx_op_args *uap) return (error); tm_p = &timeout; } - return do_lock_umutex(td, uap->obj, tm_p, _UMUTEX_WAIT); + return (do_lock_umutex(td, uap->obj, tm_p, _UMUTEX_WAIT)); } static int @@ -3989,7 +4153,7 @@ __umtx_op_wait_uint_private_compat32(struct thread *td, struct _umtx_op_args *ua return (error); tm_p = &timeout; } - return do_wait(td, uap->obj, uap->val, tm_p, 1, 1); + return (do_wait(td, uap->obj, uap->val, tm_p, 1, 1)); } #if defined(COMPAT_FREEBSD9) || defined(COMPAT_FREEBSD10) @@ -4035,34 +4199,56 @@ __umtx_op_sem2_wait_compat32(struct thread *td, struct _umtx_op_args *uap) static int __umtx_op_nwake_private32(struct thread *td, struct _umtx_op_args *uap) { - int count = uap->val; - uint32_t uaddrs[BATCH_SIZE]; - uint32_t **upp = (uint32_t **)uap->obj; - int tocopy; - int error = 0; - int i, pos = 0; + uint32_t uaddrs[BATCH_SIZE], **upp; + int count, error, i, pos, tocopy; - while (count > 0) { - tocopy = count; - if (tocopy > BATCH_SIZE) - tocopy = BATCH_SIZE; - error = copyin(upp+pos, uaddrs, tocopy * sizeof(uint32_t)); + upp = (uint32_t **)uap->obj; + error = 0; + for (count = uap->val, pos = 0; count > 0; count -= tocopy, + pos += tocopy) { + tocopy = MIN(count, BATCH_SIZE); + error = copyin(upp + pos, uaddrs, tocopy * sizeof(uint32_t)); if (error != 0) break; for (i = 0; i < tocopy; ++i) kern_umtx_wake(td, (void *)(intptr_t)uaddrs[i], - INT_MAX, 1); - count -= tocopy; - pos += tocopy; + INT_MAX, 1); + maybe_yield(); } return (error); } +struct umtx_robust_lists_params_compat32 { + uint32_t robust_list_offset; + uint32_t robust_priv_list_offset; + uint32_t robust_inact_offset; +}; + +static int +__umtx_op_robust_lists_compat32(struct thread *td, struct _umtx_op_args *uap) +{ + struct umtx_robust_lists_params rb; + struct umtx_robust_lists_params_compat32 rb32; + int error; + + if (uap->val > sizeof(rb32)) + return (EINVAL); + bzero(&rb, sizeof(rb)); + bzero(&rb32, sizeof(rb32)); + error = copyin(uap->uaddr1, &rb32, uap->val); + if (error != 0) + return (error); + rb.robust_list_offset = rb32.robust_list_offset; + rb.robust_priv_list_offset = rb32.robust_priv_list_offset; + rb.robust_inact_offset = rb32.robust_inact_offset; + return (umtx_robust_lists(td, &rb)); +} + static const _umtx_op_func op_table_compat32[] = { [UMTX_OP_RESERVED0] = __umtx_op_unimpl, [UMTX_OP_RESERVED1] = __umtx_op_unimpl, - [UMTX_OP_WAIT] = __umtx_op_wait_compat32, - [UMTX_OP_WAKE] = __umtx_op_wake, + [UMTX_OP_WAIT] = __umtx_op_wait_compat32, + [UMTX_OP_WAKE] = __umtx_op_wake, [UMTX_OP_MUTEX_TRYLOCK] = __umtx_op_trylock_umutex, [UMTX_OP_MUTEX_LOCK] = __umtx_op_lock_umutex_compat32, [UMTX_OP_MUTEX_UNLOCK] = __umtx_op_unlock_umutex, @@ -4090,6 +4276,7 @@ static const _umtx_op_func op_table_compat32[] = { [UMTX_OP_SEM2_WAIT] = __umtx_op_sem2_wait_compat32, [UMTX_OP_SEM2_WAKE] = __umtx_op_sem2_wake, [UMTX_OP_SHM] = __umtx_op_shm, + [UMTX_OP_ROBUST_LISTS] = __umtx_op_robust_lists_compat32, }; int @@ -4107,6 +4294,7 @@ freebsd32_umtx_op(struct thread *td, struct freebsd32_umtx_op_args *uap) void umtx_thread_init(struct thread *td) { + td->td_umtxq = umtxq_alloc(); td->td_umtxq->uq_thread = td; } @@ -4114,6 +4302,7 @@ umtx_thread_init(struct thread *td) void umtx_thread_fini(struct thread *td) { + umtxq_free(td->td_umtxq); } @@ -4136,12 +4325,32 @@ umtx_thread_alloc(struct thread *td) /* * exec() hook. + * + * Clear robust lists for all process' threads, not delaying the + * cleanup to thread_exit hook, since the relevant address space is + * destroyed right now. */ static void -umtx_exec_hook(void *arg __unused, struct proc *p __unused, - struct image_params *imgp __unused) +umtx_exec_hook(void *arg __unused, struct proc *p, + struct image_params *imgp __unused) { - umtx_thread_cleanup(curthread); + struct thread *td; + + KASSERT(p == curproc, ("need curproc")); + PROC_LOCK(p); + KASSERT((p->p_flag & P_HADTHREADS) == 0 || + (p->p_flag & P_STOPPED_SINGLE) != 0, + ("curproc must be single-threaded")); + FOREACH_THREAD_IN_PROC(p, td) { + KASSERT(td == curthread || + ((td->td_flags & TDF_BOUNDARY) != 0 && TD_IS_SUSPENDED(td)), + ("running thread %p %p", p, td)); + PROC_UNLOCK(p); + umtx_thread_cleanup(td); + PROC_LOCK(p); + td->td_rb_list = td->td_rbp_list = td->td_rb_inact = 0; + } + PROC_UNLOCK(p); } /* @@ -4150,29 +4359,136 @@ umtx_exec_hook(void *arg __unused, struct proc *p __unused, void umtx_thread_exit(struct thread *td) { + umtx_thread_cleanup(td); } +static int +umtx_read_uptr(struct thread *td, uintptr_t ptr, uintptr_t *res) +{ + u_long res1; +#ifdef COMPAT_FREEBSD32 + uint32_t res32; +#endif + int error; + +#ifdef COMPAT_FREEBSD32 + if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) { + error = fueword32((void *)ptr, &res32); + if (error == 0) + res1 = res32; + } else +#endif + { + error = fueword((void *)ptr, &res1); + } + if (error == 0) + *res = res1; + else + error = EFAULT; + return (error); +} + +static void +umtx_read_rb_list(struct thread *td, struct umutex *m, uintptr_t *rb_list) +{ +#ifdef COMPAT_FREEBSD32 + struct umutex32 m32; + + if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) { + memcpy(&m32, m, sizeof(m32)); + *rb_list = m32.m_rb_lnk; + } else +#endif + *rb_list = m->m_rb_lnk; +} + +static int +umtx_handle_rb(struct thread *td, uintptr_t rbp, uintptr_t *rb_list, bool inact) +{ + struct umutex m; + int error; + + KASSERT(td->td_proc == curproc, ("need current vmspace")); + error = copyin((void *)rbp, &m, sizeof(m)); + if (error != 0) + return (error); + if (rb_list != NULL) + umtx_read_rb_list(td, &m, rb_list); + if ((m.m_flags & UMUTEX_ROBUST) == 0) + return (EINVAL); + if ((m.m_owner & ~UMUTEX_CONTESTED) != td->td_tid) + /* inact is cleared after unlock, allow the inconsistency */ + return (inact ? 0 : EINVAL); + return (do_unlock_umutex(td, (struct umutex *)rbp, true)); +} + +static void +umtx_cleanup_rb_list(struct thread *td, uintptr_t rb_list, uintptr_t *rb_inact, + const char *name) +{ + int error, i; + uintptr_t rbp; + bool inact; + + if (rb_list == 0) + return; + error = umtx_read_uptr(td, rb_list, &rbp); + for (i = 0; error == 0 && rbp != 0 && i < umtx_max_rb; i++) { + if (rbp == *rb_inact) { + inact = true; + *rb_inact = 0; + } else + inact = false; + error = umtx_handle_rb(td, rbp, &rbp, inact); + } + if (i == umtx_max_rb && umtx_verbose_rb) { + uprintf("comm %s pid %d: reached umtx %smax rb %d\n", + td->td_proc->p_comm, td->td_proc->p_pid, name, umtx_max_rb); + } + if (error != 0 && umtx_verbose_rb) { + uprintf("comm %s pid %d: handling %srb error %d\n", + td->td_proc->p_comm, td->td_proc->p_pid, name, error); + } +} + /* - * clean up umtx data. + * Clean up umtx data. */ static void umtx_thread_cleanup(struct thread *td) { struct umtx_q *uq; struct umtx_pi *pi; + uintptr_t rb_inact; - if ((uq = td->td_umtxq) == NULL) - return; - - mtx_lock(&umtx_lock); - uq->uq_inherited_pri = PRI_MAX; - while ((pi = TAILQ_FIRST(&uq->uq_pi_contested)) != NULL) { - pi->pi_owner = NULL; - TAILQ_REMOVE(&uq->uq_pi_contested, pi, pi_link); + /* + * Disown pi mutexes. + */ + uq = td->td_umtxq; + if (uq != NULL) { + mtx_lock(&umtx_lock); + uq->uq_inherited_pri = PRI_MAX; + while ((pi = TAILQ_FIRST(&uq->uq_pi_contested)) != NULL) { + pi->pi_owner = NULL; + TAILQ_REMOVE(&uq->uq_pi_contested, pi, pi_link); + } + mtx_unlock(&umtx_lock); + thread_lock(td); + sched_lend_user_prio(td, PRI_MAX); + thread_unlock(td); } - mtx_unlock(&umtx_lock); - thread_lock(td); - sched_lend_user_prio(td, PRI_MAX); - thread_unlock(td); + + /* + * Handle terminated robust mutexes. Must be done after + * robust pi disown, otherwise unlock could see unowned + * entries. + */ + rb_inact = td->td_rb_inact; + if (rb_inact != 0) + (void)umtx_read_uptr(td, rb_inact, &rb_inact); + umtx_cleanup_rb_list(td, td->td_rb_list, &rb_inact, ""); + umtx_cleanup_rb_list(td, td->td_rbp_list, &rb_inact, "priv "); + if (rb_inact != 0) + (void)umtx_handle_rb(td, rb_inact, NULL, true); } diff --git a/sys/kern/subr_bus.c b/sys/kern/subr_bus.c index bda4158..e882553 100644 --- a/sys/kern/subr_bus.c +++ b/sys/kern/subr_bus.c @@ -862,7 +862,7 @@ devctl_safe_quote(char *dst, const char *src, size_t len) return; while (src != NULL && walker < ep) { - if (*src == '"') { + if (*src == '"' || *src == '\\') { if (ep - walker < 2) break; *walker++ = '\\'; diff --git a/sys/kern/subr_intr.c b/sys/kern/subr_intr.c index 16964ef..bb9fbb5 100644 --- a/sys/kern/subr_intr.c +++ b/sys/kern/subr_intr.c @@ -911,22 +911,22 @@ pic_destroy(device_t dev, intptr_t xref) /* * Register interrupt controller. */ -int +struct intr_pic * intr_pic_register(device_t dev, intptr_t xref) { struct intr_pic *pic; if (dev == NULL) - return (EINVAL); + return (NULL); pic = pic_create(dev, xref); if (pic == NULL) - return (ENOMEM); + return (NULL); pic->pic_flags |= FLAG_PIC; debugf("PIC %p registered for %s <dev %p, xref %x>\n", pic, device_get_nameunit(dev), dev, xref); - return (0); + return (pic); } /* diff --git a/sys/kern/subr_sleepqueue.c b/sys/kern/subr_sleepqueue.c index ef06c48..bd782b8 100644 --- a/sys/kern/subr_sleepqueue.c +++ b/sys/kern/subr_sleepqueue.c @@ -865,7 +865,7 @@ int sleepq_broadcast(void *wchan, int flags, int pri, int queue) { struct sleepqueue *sq; - struct thread *td, *tdn; + struct thread *td; int wakeup_swapper; CTR2(KTR_PROC, "sleepq_broadcast(%p, %d)", wchan, flags); @@ -879,10 +879,9 @@ sleepq_broadcast(void *wchan, int flags, int pri, int queue) /* Resume all blocked threads on the sleep queue. */ wakeup_swapper = 0; - TAILQ_FOREACH_SAFE(td, &sq->sq_blocked[queue], td_slpq, tdn) { + while ((td = TAILQ_FIRST(&sq->sq_blocked[queue])) != NULL) { thread_lock(td); - if (sleepq_resume_thread(sq, td, pri)) - wakeup_swapper = 1; + wakeup_swapper |= sleepq_resume_thread(sq, td, pri); thread_unlock(td); } return (wakeup_swapper); diff --git a/sys/kern/subr_taskqueue.c b/sys/kern/subr_taskqueue.c index 96236a9..b370b37 100644 --- a/sys/kern/subr_taskqueue.c +++ b/sys/kern/subr_taskqueue.c @@ -34,12 +34,14 @@ __FBSDID("$FreeBSD$"); #include <sys/interrupt.h> #include <sys/kernel.h> #include <sys/kthread.h> +#include <sys/libkern.h> #include <sys/limits.h> #include <sys/lock.h> #include <sys/malloc.h> #include <sys/mutex.h> #include <sys/proc.h> #include <sys/sched.h> +#include <sys/smp.h> #include <sys/taskqueue.h> #include <sys/unistd.h> #include <machine/stdarg.h> @@ -62,9 +64,11 @@ struct taskqueue { STAILQ_HEAD(, task) tq_queue; taskqueue_enqueue_fn tq_enqueue; void *tq_context; + char *tq_name; TAILQ_HEAD(, taskqueue_busy) tq_active; struct mtx tq_mutex; struct thread **tq_threads; + struct thread *tq_curthread; int tq_tcount; int tq_spin; int tq_flags; @@ -119,11 +123,17 @@ TQ_SLEEP(struct taskqueue *tq, void *p, struct mtx *m, int pri, const char *wm, } static struct taskqueue * -_taskqueue_create(const char *name __unused, int mflags, +_taskqueue_create(const char *name, int mflags, taskqueue_enqueue_fn enqueue, void *context, - int mtxflags, const char *mtxname) + int mtxflags, const char *mtxname __unused) { struct taskqueue *queue; + char *tq_name = NULL; + + if (name != NULL) + tq_name = strndup(name, 32, M_TASKQUEUE); + if (tq_name == NULL) + tq_name = "taskqueue"; queue = malloc(sizeof(struct taskqueue), M_TASKQUEUE, mflags | M_ZERO); if (!queue) @@ -133,6 +143,7 @@ _taskqueue_create(const char *name __unused, int mflags, TAILQ_INIT(&queue->tq_active); queue->tq_enqueue = enqueue; queue->tq_context = context; + queue->tq_name = tq_name; queue->tq_spin = (mtxflags & MTX_SPIN) != 0; queue->tq_flags |= TQ_FLAGS_ACTIVE; if (enqueue == taskqueue_fast_enqueue || @@ -140,7 +151,7 @@ _taskqueue_create(const char *name __unused, int mflags, enqueue == taskqueue_swi_giant_enqueue || enqueue == taskqueue_thread_enqueue) queue->tq_flags |= TQ_FLAGS_UNLOCKED_ENQUEUE; - mtx_init(&queue->tq_mutex, mtxname, NULL, mtxflags); + mtx_init(&queue->tq_mutex, tq_name, NULL, mtxflags); return queue; } @@ -149,8 +160,9 @@ struct taskqueue * taskqueue_create(const char *name, int mflags, taskqueue_enqueue_fn enqueue, void *context) { + return _taskqueue_create(name, mflags, enqueue, context, - MTX_DEF, "taskqueue"); + MTX_DEF, name); } void @@ -194,6 +206,7 @@ taskqueue_free(struct taskqueue *queue) KASSERT(queue->tq_callouts == 0, ("Armed timeout tasks")); mtx_destroy(&queue->tq_mutex); free(queue->tq_threads, M_TASKQUEUE); + free(queue->tq_name, M_TASKQUEUE); free(queue, M_TASKQUEUE); } @@ -203,11 +216,12 @@ taskqueue_enqueue_locked(struct taskqueue *queue, struct task *task) struct task *ins; struct task *prev; + KASSERT(task->ta_func != NULL, ("enqueueing task with NULL func")); /* * Count multiple enqueues. */ if (task->ta_pending) { - if (task->ta_pending < USHRT_MAX) + if (task->ta_pending < UCHAR_MAX) task->ta_pending++; TQ_UNLOCK(queue); return (0); @@ -245,6 +259,22 @@ taskqueue_enqueue_locked(struct taskqueue *queue, struct task *task) } int +grouptaskqueue_enqueue(struct taskqueue *queue, struct task *task) +{ + TQ_LOCK(queue); + if (task->ta_pending) { + TQ_UNLOCK(queue); + return (0); + } + STAILQ_INSERT_TAIL(&queue->tq_queue, task, ta_link); + task->ta_pending = 1; + TQ_UNLOCK(queue); + if ((queue->tq_flags & TQ_FLAGS_BLOCKED) == 0) + queue->tq_enqueue(queue->tq_context); + return (0); +} + +int taskqueue_enqueue(struct taskqueue *queue, struct task *task) { int res; @@ -410,6 +440,7 @@ taskqueue_run_locked(struct taskqueue *queue) struct task *task; int pending; + KASSERT(queue != NULL, ("tq is NULL")); TQ_ASSERT_LOCKED(queue); tb.tb_running = NULL; @@ -421,17 +452,20 @@ taskqueue_run_locked(struct taskqueue *queue) * zero its pending count. */ task = STAILQ_FIRST(&queue->tq_queue); + KASSERT(task != NULL, ("task is NULL")); STAILQ_REMOVE_HEAD(&queue->tq_queue, ta_link); pending = task->ta_pending; task->ta_pending = 0; tb.tb_running = task; TQ_UNLOCK(queue); + KASSERT(task->ta_func != NULL, ("task->ta_func is NULL")); task->ta_func(task->ta_context, pending); TQ_LOCK(queue); tb.tb_running = NULL; - wakeup(task); + if ((task->ta_flags & TASK_SKIP_WAKEUP) == 0) + wakeup(task); TAILQ_REMOVE(&queue->tq_active, &tb, tb_link); tb_first = TAILQ_FIRST(&queue->tq_active); @@ -446,7 +480,9 @@ taskqueue_run(struct taskqueue *queue) { TQ_LOCK(queue); + queue->tq_curthread = curthread; taskqueue_run_locked(queue); + queue->tq_curthread = NULL; TQ_UNLOCK(queue); } @@ -679,7 +715,9 @@ taskqueue_thread_loop(void *arg) tq = *tqp; taskqueue_run_callback(tq, TASKQUEUE_CALLBACK_TYPE_INIT); TQ_LOCK(tq); + tq->tq_curthread = curthread; while ((tq->tq_flags & TQ_FLAGS_ACTIVE) != 0) { + /* XXX ? */ taskqueue_run_locked(tq); /* * Because taskqueue_run() can drop tq_mutex, we need to @@ -691,7 +729,7 @@ taskqueue_thread_loop(void *arg) TQ_SLEEP(tq, tq, &tq->tq_mutex, 0, "-", 0); } taskqueue_run_locked(tq); - + tq->tq_curthread = NULL; /* * This thread is on its way out, so just drop the lock temporarily * in order to call the shutdown callback. This allows the callback @@ -715,8 +753,8 @@ taskqueue_thread_enqueue(void *context) tqp = context; tq = *tqp; - - wakeup_one(tq); + if (tq->tq_curthread != curthread) + wakeup_one(tq); } TASKQUEUE_DEFINE(swi, taskqueue_swi_enqueue, NULL, @@ -772,3 +810,334 @@ taskqueue_member(struct taskqueue *queue, struct thread *td) } return (ret); } + +struct taskqgroup_cpu { + LIST_HEAD(, grouptask) tgc_tasks; + struct taskqueue *tgc_taskq; + int tgc_cnt; + int tgc_cpu; +}; + +struct taskqgroup { + struct taskqgroup_cpu tqg_queue[MAXCPU]; + struct mtx tqg_lock; + char * tqg_name; + int tqg_adjusting; + int tqg_stride; + int tqg_cnt; +}; + +struct taskq_bind_task { + struct task bt_task; + int bt_cpuid; +}; + +static void +taskqgroup_cpu_create(struct taskqgroup *qgroup, int idx) +{ + struct taskqgroup_cpu *qcpu; + + qcpu = &qgroup->tqg_queue[idx]; + LIST_INIT(&qcpu->tgc_tasks); + qcpu->tgc_taskq = taskqueue_create_fast(NULL, M_WAITOK, + taskqueue_thread_enqueue, &qcpu->tgc_taskq); + taskqueue_start_threads(&qcpu->tgc_taskq, 1, PI_SOFT, + "%s_%d", qgroup->tqg_name, idx); + qcpu->tgc_cpu = idx * qgroup->tqg_stride; +} + +static void +taskqgroup_cpu_remove(struct taskqgroup *qgroup, int idx) +{ + + taskqueue_free(qgroup->tqg_queue[idx].tgc_taskq); +} + +/* + * Find the taskq with least # of tasks that doesn't currently have any + * other queues from the uniq identifier. + */ +static int +taskqgroup_find(struct taskqgroup *qgroup, void *uniq) +{ + struct grouptask *n; + int i, idx, mincnt; + int strict; + + mtx_assert(&qgroup->tqg_lock, MA_OWNED); + if (qgroup->tqg_cnt == 0) + return (0); + idx = -1; + mincnt = INT_MAX; + /* + * Two passes; First scan for a queue with the least tasks that + * does not already service this uniq id. If that fails simply find + * the queue with the least total tasks; + */ + for (strict = 1; mincnt == INT_MAX; strict = 0) { + for (i = 0; i < qgroup->tqg_cnt; i++) { + if (qgroup->tqg_queue[i].tgc_cnt > mincnt) + continue; + if (strict) { + LIST_FOREACH(n, + &qgroup->tqg_queue[i].tgc_tasks, gt_list) + if (n->gt_uniq == uniq) + break; + if (n != NULL) + continue; + } + mincnt = qgroup->tqg_queue[i].tgc_cnt; + idx = i; + } + } + if (idx == -1) + panic("taskqgroup_find: Failed to pick a qid."); + + return (idx); +} + +void +taskqgroup_attach(struct taskqgroup *qgroup, struct grouptask *gtask, + void *uniq, int irq, char *name) +{ + cpuset_t mask; + int qid; + + gtask->gt_uniq = uniq; + gtask->gt_name = name; + gtask->gt_irq = irq; + gtask->gt_cpu = -1; + mtx_lock(&qgroup->tqg_lock); + qid = taskqgroup_find(qgroup, uniq); + qgroup->tqg_queue[qid].tgc_cnt++; + LIST_INSERT_HEAD(&qgroup->tqg_queue[qid].tgc_tasks, gtask, gt_list); + gtask->gt_taskqueue = qgroup->tqg_queue[qid].tgc_taskq; + if (irq != -1 && smp_started) { + CPU_ZERO(&mask); + CPU_SET(qgroup->tqg_queue[qid].tgc_cpu, &mask); + mtx_unlock(&qgroup->tqg_lock); + intr_setaffinity(irq, &mask); + } else + mtx_unlock(&qgroup->tqg_lock); +} + +int +taskqgroup_attach_cpu(struct taskqgroup *qgroup, struct grouptask *gtask, + void *uniq, int cpu, int irq, char *name) +{ + cpuset_t mask; + int i, qid; + + qid = -1; + gtask->gt_uniq = uniq; + gtask->gt_name = name; + gtask->gt_irq = irq; + gtask->gt_cpu = cpu; + mtx_lock(&qgroup->tqg_lock); + if (smp_started) { + for (i = 0; i < qgroup->tqg_cnt; i++) + if (qgroup->tqg_queue[i].tgc_cpu == cpu) { + qid = i; + break; + } + if (qid == -1) { + mtx_unlock(&qgroup->tqg_lock); + return (EINVAL); + } + } else + qid = 0; + qgroup->tqg_queue[qid].tgc_cnt++; + LIST_INSERT_HEAD(&qgroup->tqg_queue[qid].tgc_tasks, gtask, gt_list); + gtask->gt_taskqueue = qgroup->tqg_queue[qid].tgc_taskq; + if (irq != -1 && smp_started) { + CPU_ZERO(&mask); + CPU_SET(qgroup->tqg_queue[qid].tgc_cpu, &mask); + mtx_unlock(&qgroup->tqg_lock); + intr_setaffinity(irq, &mask); + } else + mtx_unlock(&qgroup->tqg_lock); + return (0); +} + +void +taskqgroup_detach(struct taskqgroup *qgroup, struct grouptask *gtask) +{ + int i; + + mtx_lock(&qgroup->tqg_lock); + for (i = 0; i < qgroup->tqg_cnt; i++) + if (qgroup->tqg_queue[i].tgc_taskq == gtask->gt_taskqueue) + break; + if (i == qgroup->tqg_cnt) + panic("taskqgroup_detach: task not in group\n"); + qgroup->tqg_queue[i].tgc_cnt--; + LIST_REMOVE(gtask, gt_list); + mtx_unlock(&qgroup->tqg_lock); + gtask->gt_taskqueue = NULL; +} + +static void +taskqgroup_binder(void *ctx, int pending) +{ + struct taskq_bind_task *task = (struct taskq_bind_task *)ctx; + cpuset_t mask; + int error; + + CPU_ZERO(&mask); + CPU_SET(task->bt_cpuid, &mask); + error = cpuset_setthread(curthread->td_tid, &mask); + thread_lock(curthread); + sched_bind(curthread, task->bt_cpuid); + thread_unlock(curthread); + + if (error) + printf("taskqgroup_binder: setaffinity failed: %d\n", + error); + free(task, M_DEVBUF); +} + +static void +taskqgroup_bind(struct taskqgroup *qgroup) +{ + struct taskq_bind_task *task; + int i; + + /* + * Bind taskqueue threads to specific CPUs, if they have been assigned + * one. + */ + for (i = 0; i < qgroup->tqg_cnt; i++) { + task = malloc(sizeof (*task), M_DEVBUF, M_NOWAIT); + TASK_INIT(&task->bt_task, 0, taskqgroup_binder, task); + task->bt_cpuid = qgroup->tqg_queue[i].tgc_cpu; + taskqueue_enqueue(qgroup->tqg_queue[i].tgc_taskq, + &task->bt_task); + } +} + +static int +_taskqgroup_adjust(struct taskqgroup *qgroup, int cnt, int stride) +{ + LIST_HEAD(, grouptask) gtask_head = LIST_HEAD_INITIALIZER(NULL); + cpuset_t mask; + struct grouptask *gtask; + int i, old_cnt, qid; + + mtx_assert(&qgroup->tqg_lock, MA_OWNED); + + if (cnt < 1 || cnt * stride > mp_ncpus || !smp_started) { + printf("taskqgroup_adjust failed cnt: %d stride: %d mp_ncpus: %d smp_started: %d\n", + cnt, stride, mp_ncpus, smp_started); + return (EINVAL); + } + if (qgroup->tqg_adjusting) { + printf("taskqgroup_adjust failed: adjusting\n"); + return (EBUSY); + } + qgroup->tqg_adjusting = 1; + old_cnt = qgroup->tqg_cnt; + mtx_unlock(&qgroup->tqg_lock); + /* + * Set up queue for tasks added before boot. + */ + if (old_cnt == 0) { + LIST_SWAP(>ask_head, &qgroup->tqg_queue[0].tgc_tasks, + grouptask, gt_list); + qgroup->tqg_queue[0].tgc_cnt = 0; + } + + /* + * If new taskq threads have been added. + */ + for (i = old_cnt; i < cnt; i++) + taskqgroup_cpu_create(qgroup, i); + mtx_lock(&qgroup->tqg_lock); + qgroup->tqg_cnt = cnt; + qgroup->tqg_stride = stride; + + /* + * Adjust drivers to use new taskqs. + */ + for (i = 0; i < old_cnt; i++) { + while ((gtask = LIST_FIRST(&qgroup->tqg_queue[i].tgc_tasks))) { + LIST_REMOVE(gtask, gt_list); + qgroup->tqg_queue[i].tgc_cnt--; + LIST_INSERT_HEAD(>ask_head, gtask, gt_list); + } + } + + while ((gtask = LIST_FIRST(>ask_head))) { + LIST_REMOVE(gtask, gt_list); + if (gtask->gt_cpu == -1) + qid = taskqgroup_find(qgroup, gtask->gt_uniq); + else { + for (i = 0; i < qgroup->tqg_cnt; i++) + if (qgroup->tqg_queue[i].tgc_cpu == gtask->gt_cpu) { + qid = i; + break; + } + } + qgroup->tqg_queue[qid].tgc_cnt++; + LIST_INSERT_HEAD(&qgroup->tqg_queue[qid].tgc_tasks, gtask, + gt_list); + gtask->gt_taskqueue = qgroup->tqg_queue[qid].tgc_taskq; + } + /* + * Set new CPU and IRQ affinity + */ + for (i = 0; i < cnt; i++) { + qgroup->tqg_queue[i].tgc_cpu = i * qgroup->tqg_stride; + CPU_ZERO(&mask); + CPU_SET(qgroup->tqg_queue[i].tgc_cpu, &mask); + LIST_FOREACH(gtask, &qgroup->tqg_queue[i].tgc_tasks, gt_list) { + if (gtask->gt_irq == -1) + continue; + intr_setaffinity(gtask->gt_irq, &mask); + } + } + mtx_unlock(&qgroup->tqg_lock); + + /* + * If taskq thread count has been reduced. + */ + for (i = cnt; i < old_cnt; i++) + taskqgroup_cpu_remove(qgroup, i); + + mtx_lock(&qgroup->tqg_lock); + qgroup->tqg_adjusting = 0; + + taskqgroup_bind(qgroup); + + return (0); +} + +int +taskqgroup_adjust(struct taskqgroup *qgroup, int cpu, int stride) +{ + int error; + + mtx_lock(&qgroup->tqg_lock); + error = _taskqgroup_adjust(qgroup, cpu, stride); + mtx_unlock(&qgroup->tqg_lock); + + return (error); +} + +struct taskqgroup * +taskqgroup_create(char *name) +{ + struct taskqgroup *qgroup; + + qgroup = malloc(sizeof(*qgroup), M_TASKQUEUE, M_WAITOK | M_ZERO); + mtx_init(&qgroup->tqg_lock, "taskqgroup", NULL, MTX_DEF); + qgroup->tqg_name = name; + LIST_INIT(&qgroup->tqg_queue[0].tgc_tasks); + + return (qgroup); +} + +void +taskqgroup_destroy(struct taskqgroup *qgroup) +{ + +} diff --git a/sys/kern/uipc_syscalls.c b/sys/kern/uipc_syscalls.c index 05703ef..75044eb 100644 --- a/sys/kern/uipc_syscalls.c +++ b/sys/kern/uipc_syscalls.c @@ -84,6 +84,7 @@ static int getsockname1(struct thread *td, struct getsockname_args *uap, int compat); static int getpeername1(struct thread *td, struct getpeername_args *uap, int compat); +static int sockargs(struct mbuf **, char *, socklen_t, int); /* * Convert a user file descriptor to a kernel file entry and check if required @@ -1689,11 +1690,8 @@ ogetpeername(td, uap) } #endif /* COMPAT_OLDSOCK */ -int -sockargs(mp, buf, buflen, type) - struct mbuf **mp; - caddr_t buf; - int buflen, type; +static int +sockargs(struct mbuf **mp, char *buf, socklen_t buflen, int type) { struct sockaddr *sa; struct mbuf *m; @@ -1710,7 +1708,7 @@ sockargs(mp, buf, buflen, type) } m = m_get2(buflen, M_WAITOK, type, 0); m->m_len = buflen; - error = copyin(buf, mtod(m, caddr_t), (u_int)buflen); + error = copyin(buf, mtod(m, void *), buflen); if (error != 0) (void) m_free(m); else { diff --git a/sys/kern/vfs_vnops.c b/sys/kern/vfs_vnops.c index 0a3a88a..1e42a3d 100644 --- a/sys/kern/vfs_vnops.c +++ b/sys/kern/vfs_vnops.c @@ -1314,6 +1314,8 @@ vn_truncate(struct file *fp, off_t length, struct ucred *active_cred, if (error == 0) { VATTR_NULL(&vattr); vattr.va_size = length; + if ((fp->f_flag & O_FSYNC) != 0) + vattr.va_vaflags |= VA_SYNC; error = VOP_SETATTR(vp, &vattr, fp->f_cred); } out: diff --git a/sys/mips/broadcom/bcm_machdep.c b/sys/mips/broadcom/bcm_machdep.c new file mode 100644 index 0000000..d535db3 --- /dev/null +++ b/sys/mips/broadcom/bcm_machdep.c @@ -0,0 +1,221 @@ +/*- + * Copyright (c) 2007 Bruce M. Simpson. + * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include "opt_ddb.h" + +#include <sys/param.h> +#include <sys/conf.h> +#include <sys/kernel.h> +#include <sys/systm.h> +#include <sys/imgact.h> +#include <sys/bio.h> +#include <sys/buf.h> +#include <sys/bus.h> +#include <sys/cpu.h> +#include <sys/cons.h> +#include <sys/exec.h> +#include <sys/ucontext.h> +#include <sys/proc.h> +#include <sys/kdb.h> +#include <sys/ptrace.h> +#include <sys/reboot.h> +#include <sys/signalvar.h> +#include <sys/sysent.h> +#include <sys/sysproto.h> +#include <sys/user.h> + +#include <vm/vm.h> +#include <vm/vm_object.h> +#include <vm/vm_page.h> + +#include <machine/cache.h> +#include <machine/clock.h> +#include <machine/cpu.h> +#include <machine/cpuinfo.h> +#include <machine/cpufunc.h> +#include <machine/cpuregs.h> +#include <machine/hwfunc.h> +#include <machine/intr_machdep.h> +#include <machine/locore.h> +#include <machine/md_var.h> +#include <machine/pte.h> +#include <machine/sigframe.h> +#include <machine/trap.h> +#include <machine/vmparam.h> + +#include <mips/sentry5/s5reg.h> +#include "bcm_socinfo.h" + +#ifdef CFE +#include <dev/cfe/cfe_api.h> +#endif + +#if 0 +#define BROADCOM_TRACE 0 +#endif + +extern int *edata; +extern int *end; + +void +platform_cpu_init() +{ + /* Nothing special */ +} + +static void +mips_init(void) +{ + int i, j; + + printf("entry: mips_init()\n"); + +#ifdef CFE + /* + * Query DRAM memory map from CFE. + */ + physmem = 0; + for (i = 0; i < 10; i += 2) { + int result; + uint64_t addr, len, type; + + result = cfe_enummem(i / 2, 0, &addr, &len, &type); + if (result < 0) { +#ifdef BROADCOM_TRACE + printf("There is no phys memory for: %d\n", i); +#endif + phys_avail[i] = phys_avail[i + 1] = 0; + break; + } + if (type != CFE_MI_AVAILABLE){ +#ifdef BROADCOM_TRACE + printf("phys memory is not available: %d\n", i); +#endif + continue; + } + + phys_avail[i] = addr; + if (i == 0 && addr == 0) { + /* + * If this is the first physical memory segment probed + * from CFE, omit the region at the start of physical + * memory where the kernel has been loaded. + */ + phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); + } +#ifdef BROADCOM_TRACE + printf("phys memory is available for: %d\n", i); + printf(" => addr = %jx\n", addr); + printf(" => len = %jd\n", len); +#endif + phys_avail[i + 1] = addr + len; + physmem += len; + } + +#ifdef BROADCOM_TRACE + printf("Total phys memory is : %ld\n", physmem); +#endif + + realmem = btoc(physmem); +#endif + + for (j = 0; j < i; j++) + dump_avail[j] = phys_avail[j]; + + physmem = realmem; + + init_param1(); + init_param2(physmem); + mips_cpu_init(); + pmap_bootstrap(); + mips_proc0_init(); + mutex_init(); + kdb_init(); +#ifdef KDB + if (boothowto & RB_KDB) + kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); +#endif +} + +#define BCM_REG_CHIPC 0x18000000 + + +void +platform_reset(void) +{ + printf("bcm::platform_reset()\n"); + intr_disable(); + BCM_WRITE_REG32(BCM_REG_CHIPC_PMUWD_OFFS, 2); /* PMU watchdog */ + for (;;); +} + +void +platform_start(__register_t a0, __register_t a1, __register_t a2, + __register_t a3) +{ + vm_offset_t kernend; + uint64_t platform_counter_freq; + struct bcm_socinfo *socinfo; + + /* clear the BSS and SBSS segments */ + kernend = (vm_offset_t)&end; + memset(&edata, 0, kernend - (vm_offset_t)(&edata)); + + mips_postboot_fixup(); + + /* Initialize pcpu stuff */ + mips_pcpu0_init(); + + socinfo = bcm_get_socinfo(); + platform_counter_freq = socinfo->cpurate * 1000 * 1000; /* BCM4718 is 480MHz */ + + mips_timer_early_init(platform_counter_freq); + +#ifdef CFE + /* + * Initialize CFE firmware trampolines before + * we initialize the low-level console. + * + * CFE passes the following values in registers: + * a0: firmware handle + * a2: firmware entry point + * a3: entry point seal + */ + if (a3 == CFE_EPTSEAL) + cfe_init(a0, a2); +#endif + cninit(); + + mips_init(); + + /* BCM471x timer is 1/2 of Clk */ + mips_timer_init_params(platform_counter_freq, 1); +} diff --git a/sys/mips/broadcom/bcm_mipscore.c b/sys/mips/broadcom/bcm_mipscore.c new file mode 100644 index 0000000..ddd4c80 --- /dev/null +++ b/sys/mips/broadcom/bcm_mipscore.c @@ -0,0 +1,123 @@ +/*- + * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/kernel.h> +#include <sys/bus.h> +#include <sys/module.h> +#include <sys/systm.h> +#include <sys/errno.h> +#include <sys/rman.h> +#include <sys/stddef.h> + +#include <machine/bus.h> +#include <machine/resource.h> + +#include <dev/bhnd/bhnd.h> +#include <dev/bhnd/bhndvar.h> +#include <dev/bhnd/bhnd_ids.h> + +#include "bcm_mipscore.h" + +static const struct resource_spec mipscore_rspec[MIPSCORE_MAX_RSPEC] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { -1, -1, 0 } +}; + +struct bhnd_device mipscore_match[] = { + BHND_MIPS_DEVICE(MIPS, "BHND MIPS processor", NULL), + BHND_MIPS_DEVICE(MIPS33, "BHND MIPS3302 processor", NULL), + BHND_MIPS_DEVICE(MIPS74K, "BHND MIPS74K processor", NULL), + BHND_DEVICE_END +}; + +static int +mipscore_probe(device_t dev) +{ + const struct bhnd_device *id; + + id = bhnd_device_lookup(dev, mipscore_match, sizeof(mipscore_match[0])); + if (id == NULL) + return (ENXIO); + + bhnd_set_default_core_desc(dev); + return (BUS_PROBE_DEFAULT); +} + +static int +mipscore_attach(device_t dev) +{ + struct mipscore_softc *sc; + struct resource *res; + uint32_t intmask; + uint16_t devid; + int error; + + sc = device_get_softc(dev); + devid = bhnd_get_device(dev); + + sc->devid = devid; + sc->dev = dev; + + /* Allocate bus resources */ + memcpy(sc->rspec, mipscore_rspec, sizeof(sc->rspec)); + error = bhnd_alloc_resources(dev, sc->rspec, sc->res); + if (error) + return (error); + + res = sc->res[0]->res; + if (res == NULL) + return (ENXIO); + + if (devid == BHND_COREID_MIPS74K) { + intmask = (1 << 31); + /* Use intmask5 register to route the timer interrupt */ + bus_write_4(res, offsetof(struct mipscore_regs, intmask[5]), + intmask); + } + + return (0); +} + +static device_method_t mipscore_methods[] = { + DEVMETHOD(device_probe, mipscore_probe), + DEVMETHOD(device_attach, mipscore_attach), + DEVMETHOD_END +}; + +devclass_t bhnd_mipscore_devclass; + +DEFINE_CLASS_0(bhnd_mipscore, mipscore_driver, mipscore_methods, + sizeof(struct mipscore_softc)); +DRIVER_MODULE(bhnd_mipscore, bhnd, mipscore_driver, bhnd_mipscore_devclass, + 0, 0); +MODULE_VERSION(bhnd_mipscore, 1); diff --git a/sys/mips/broadcom/bcm_mipscore.h b/sys/mips/broadcom/bcm_mipscore.h new file mode 100644 index 0000000..fd5b5a8 --- /dev/null +++ b/sys/mips/broadcom/bcm_mipscore.h @@ -0,0 +1,60 @@ +/*- + * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#ifndef _BHND_CORES_MIPS_MIPSCOREVAR_H_ +#define _BHND_CORES_MIPS_MIPSCOREVAR_H_ + +#define MIPSCORE_MAX_RSPEC 2 + +struct mipscore_softc { + device_t dev; /* CPU device */ + uint32_t devid; + struct resource_spec rspec[MIPSCORE_MAX_RSPEC]; + struct bhnd_resource *res[MIPSCORE_MAX_RSPEC]; +}; + +struct mipscore_regs { + uint32_t corecontrol; + uint32_t exceptionbase; + uint32_t PAD1[1]; /* unmapped address */ + uint32_t biststatus; + uint32_t intstatus; + uint32_t intmask[6]; + uint32_t nmimask; + uint32_t PAD2[4]; /* unmapped addresses */ + uint32_t gpioselect; + uint32_t gpiooutput; + uint32_t gpioenable; + uint32_t PAD3[101]; /* unmapped addresses */ + uint32_t clkcontrolstatus; +}; + +#endif /* _BHND_CORES_MIPS_MIPSCOREVAR_H_ */ diff --git a/sys/mips/broadcom/bcm_socinfo.c b/sys/mips/broadcom/bcm_socinfo.c new file mode 100644 index 0000000..7e5fa04 --- /dev/null +++ b/sys/mips/broadcom/bcm_socinfo.c @@ -0,0 +1,90 @@ +/*- + * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include "bcm_socinfo.h" + +/* found on https://wireless.wiki.kernel.org/en/users/drivers/b43/soc */ +struct bcm_socinfo bcm_socinfos[] = { + {0x00005300, 600, 25000000}, /* BCM4706 to check */ + {0x0022B83A, 300, 20000000}, /* BCM4716B0 ASUS RT-N12 */ + {0x00914716, 354, 20000000}, /* BCM4717A1 to check */ + {0x00A14716, 480, 20000000}, /* BCM4718A1 ASUS RT-N16 */ + {0x00435356, 300, 25000000}, /* BCM5356A1 (RT-N10, WNR1000v3) */ + {0x00825357, 500, 20000000}, /* BCM5358UB0 ASUS RT-N53A1 */ + {0x00845357, 300, 20000000}, /* BCM5357B0 to check */ + {0x00945357, 500, 20000000}, /* BCM5358 */ + {0x00A45357, 500, 20000000}, /* BCM47186B0 Tenda N60 */ + {0x0085D144, 300, 20000000}, /* BCM5356C0 */ + {0x00B5D144, 300, 20000000}, /* BCM5357C0 */ + {0,0,0} +}; + +/* Most popular BCM SoC info */ +struct bcm_socinfo BCM_DEFAULT_SOCINFO = {0x0, 300, 20000000}; + +struct bcm_socinfo* +bcm_get_socinfo_by_socid(uint32_t key) +{ + struct bcm_socinfo* start; + + if(!key) + return (NULL); + + for(start = bcm_socinfos; start->id > 0; start++) + if(start->id == key) + return (start); + + return (NULL); +} + +struct bcm_socinfo* +bcm_get_socinfo(void) +{ + uint32_t socid; + struct bcm_socinfo *socinfo; + + /* + * We need Chip ID + Revision + Package + * -------------------------------------------------------------- + * | Mask | Usage | + * -------------------------------------------------------------- + * | 0x0000FFFF | Chip ID | + * | 0x000F0000 | Chip Revision | + * | 0x00F00000 | Package Options | + * | 0x0F000000 | Number of Cores (ChipCommon Rev. >= 4)| + * | 0xF0000000 | Chip Type | + * -------------------------------------------------------------- + */ + + socid = BCM_READ_REG32(BCM_REG_CHIPC_ID) & 0x00FFFFFF; + socinfo = bcm_get_socinfo_by_socid(socid); + return (socinfo != NULL) ? socinfo : &BCM_DEFAULT_SOCINFO; +} diff --git a/sys/mips/broadcom/bcm_socinfo.h b/sys/mips/broadcom/bcm_socinfo.h new file mode 100644 index 0000000..adf4124 --- /dev/null +++ b/sys/mips/broadcom/bcm_socinfo.h @@ -0,0 +1,59 @@ +/*- + * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * $FreeBSD$ + */ + +#ifndef _MIPS_BROADCOM_BCM_SOCINFO_H_ +#define _MIPS_BROADCOM_BCM_SOCINFO_H_ + +#include <machine/cpuregs.h> + +struct bcm_socinfo { + uint32_t id; + uint32_t cpurate; /* in MHz */ + uint32_t uartrate; /* in Hz */ +}; + +struct bcm_socinfo* bcm_get_socinfo_by_socid(uint32_t key); +struct bcm_socinfo* bcm_get_socinfo(void); + +#define BCM_SOCADDR 0x18000000 +#define BCM_REG_CHIPC_ID 0x0 +#define BCM_REG_CHIPC_UART 0x300 +#define BCM_REG_CHIPC_PMUWD_OFFS 0x634 +#define BCM_SOCREG(reg) \ + MIPS_PHYS_TO_KSEG1((BCM_SOCADDR + (reg))) +#define BCM_READ_REG32(reg) \ + *((volatile uint32_t *)BCM_SOCREG(reg)) +#define BCM_WRITE_REG32(reg, value) \ + do { \ + writel((void*)BCM_SOCREG((reg)),value); \ + } while (0); + +#endif /* _MIPS_BROADCOM_BCM_SOCINFO_H_ */ diff --git a/sys/mips/broadcom/files.broadcom b/sys/mips/broadcom/files.broadcom new file mode 100644 index 0000000..ac5c645 --- /dev/null +++ b/sys/mips/broadcom/files.broadcom @@ -0,0 +1,47 @@ +# $FreeBSD$ + +# TODO: Add attachment elsewhere in the tree +# for USB 1.1 OHCI, Ethernet and IPSEC cores +# which are believed to be devices we have drivers for +# which just need to be tweaked for attachment to an BHND system bus. +mips/broadcom/bcm_machdep.c standard +mips/mips/tick.c standard +mips/mips/mips_pic.c standard +kern/subr_intr.c standard +kern/pic_if.m standard + +kern/msi_if.m optional intrng + +mips/broadcom/uart_cpu_chipc.c optional uart +mips/broadcom/uart_bus_chipc.c optional uart +mips/broadcom/bcm_socinfo.c standard +mips/broadcom/bcm_mipscore.c standard + +# +geom/geom_flashmap.c standard +# +dev/bhnd/bhnd.c standard +dev/bhnd/bhnd_subr.c standard +dev/bhnd/bhnd_bus_if.m standard +dev/bhnd/bhndb/bhndb_if.m standard +dev/bhnd/bhndb/bhndb_bus_if.m standard +dev/bhnd/bcma/bcma.c standard +dev/bhnd/bcma/bcma_nexus.c standard +#dev/bhnd/bcma/bcma_bhndb.c standard +dev/bhnd/bcma/bcma_erom.c standard +dev/bhnd/bcma/bcma_subr.c standard +dev/bhnd/cores/chipc/chipc_subr.c standard +dev/bhnd/cores/chipc/chipc_cfi.c optional cfi +dev/bhnd/cores/chipc/chipc_spi.c optional spibus +dev/bhnd/cores/chipc/chipc_slicer.c optional cfi | spibus +dev/bhnd/cores/chipc/chipc.c standard +#to remove +#dev/bhnd/cores/chipc/chipcbus.c standard +dev/bhnd/cores/chipc/bhnd_chipc_if.m standard +dev/bhnd/nvram/bhnd_nvram_if.m standard +#dev/bhnd/siba/siba.c standard +#dev/bhnd/siba/siba_bhndb.c standard +#dev/bhnd/siba/siba_nexus.c standard +#dev/bhnd/siba/siba_subr.c standard +dev/bhnd/soc/bhnd_soc.c standard +#
\ No newline at end of file diff --git a/sys/mips/broadcom/std.broadcom b/sys/mips/broadcom/std.broadcom new file mode 100644 index 0000000..448a094 --- /dev/null +++ b/sys/mips/broadcom/std.broadcom @@ -0,0 +1,7 @@ +# $FreeBSD$ +# + +machine mips mipsel + +cpu CPU_MIPS74K +files "../broadcom/files.broadcom" diff --git a/sys/mips/broadcom/uart_bus_chipc.c b/sys/mips/broadcom/uart_bus_chipc.c new file mode 100644 index 0000000..fa2fa2d --- /dev/null +++ b/sys/mips/broadcom/uart_bus_chipc.c @@ -0,0 +1,121 @@ +/*- + * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include "opt_uart.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/conf.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/rman.h> + +#include <machine/bus.h> +#include <machine/resource.h> + +#include <dev/uart/uart.h> +#include <dev/uart/uart_bus.h> +#include <dev/uart/uart_cpu.h> + +#include "uart_if.h" +#include "bhnd_chipc_if.h" + +static int uart_chipc_probe(device_t dev); + +extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; + +static void +uart_chipc_identify(driver_t *driver, device_t parent) +{ + struct chipc_capabilities *caps; + + caps = BHND_CHIPC_GET_CAPABILITIES(parent); + + if (caps->num_uarts == 0) + return; + + /* + * TODO: add more than one UART + */ + BUS_ADD_CHILD(parent, 0, "uart", -1); +} + +static int +uart_chipc_probe(device_t dev) +{ + struct uart_softc *sc; + struct resource *res; + int rid; + + rid = 0; + res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (res == NULL) { + device_printf(dev, "can't allocate main resource\n"); + return (ENXIO); + } + + sc = device_get_softc(dev); + sc->sc_class = &uart_ns8250_class; + sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); + if (sc->sc_sysdev == NULL) { + device_printf(dev, "missing sysdev\n"); + return (EINVAL); + } + + bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); + + sc->sc_sysdev->bas.bst = rman_get_bustag(res); + sc->sc_sysdev->bas.bsh = rman_get_bushandle(res); + sc->sc_bas.bst = sc->sc_sysdev->bas.bst; + sc->sc_bas.bsh = sc->sc_sysdev->bas.bsh; + + bus_release_resource(dev, SYS_RES_MEMORY, rid, res); + + /* We use internal SoC clock generator with non-standart freq MHz */ + return (uart_bus_probe(dev, 0, sc->sc_sysdev->bas.rclk, 0, 0)); +} + +static device_method_t uart_chipc_methods[] = { + /* Device interface */ + DEVMETHOD(device_identify, uart_chipc_identify), + DEVMETHOD(device_probe, uart_chipc_probe), + DEVMETHOD(device_attach, uart_bus_attach), + DEVMETHOD(device_detach, uart_bus_detach), + { 0, 0 } +}; + +static driver_t uart_chipc_driver = { + uart_driver_name, + uart_chipc_methods, + sizeof(struct uart_softc), +}; + +DRIVER_MODULE(uart, bhnd_chipc, uart_chipc_driver, uart_devclass, 0, 0); diff --git a/sys/mips/broadcom/uart_cpu_chipc.c b/sys/mips/broadcom/uart_cpu_chipc.c new file mode 100644 index 0000000..14cc9f3 --- /dev/null +++ b/sys/mips/broadcom/uart_cpu_chipc.c @@ -0,0 +1,78 @@ +/*- + * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include "opt_uart.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/cons.h> +#include <sys/lock.h> +#include <sys/mutex.h> + +#include <machine/bus.h> + +#include <dev/uart/uart.h> +#include <dev/uart/uart_bus.h> +#include <dev/uart/uart_cpu.h> + +#include "bcm_socinfo.h" + +bus_space_tag_t uart_bus_space_io; +bus_space_tag_t uart_bus_space_mem; + +int +uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) +{ + return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); +} + +int +uart_cpu_getdev(int devtype, struct uart_devinfo *di) +{ + struct uart_class *class; + struct bcm_socinfo *socinfo; + + socinfo = bcm_get_socinfo(); + class = &uart_ns8250_class; + di->ops = uart_getops(class); + di->bas.chan = 0; + di->bas.bst = mips_bus_space_generic; + di->bas.bsh = (bus_space_handle_t)BCM_SOCREG(BCM_REG_CHIPC_UART); + di->bas.regshft = 0; + di->bas.rclk = socinfo->uartrate; /* in Hz */ + di->baudrate = 115200; + di->databits = 8; + di->stopbits = 1; + di->parity = UART_PARITY_NONE; + uart_bus_space_io = NULL; + uart_bus_space_mem = mips_bus_space_generic; + return (0); +} diff --git a/sys/mips/conf/AR933X_BASE b/sys/mips/conf/AR933X_BASE index c5619fe..01123a4 100644 --- a/sys/mips/conf/AR933X_BASE +++ b/sys/mips/conf/AR933X_BASE @@ -20,7 +20,7 @@ files "../atheros/files.ar71xx" hints "AR933X_BASE.hints" makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols -makeoptions MODULES_OVERRIDE="gpio ar71xx if_gif if_vlan if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr hwpmc ipfw" +makeoptions MODULES_OVERRIDE="gpio ar71xx if_gif if_vlan if_gre if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr hwpmc ipfw urtwn urtwnfw otus otusfw" options DDB options KDB diff --git a/sys/mips/conf/AR934X_BASE b/sys/mips/conf/AR934X_BASE index 87bea17..054dcf3 100644 --- a/sys/mips/conf/AR934X_BASE +++ b/sys/mips/conf/AR934X_BASE @@ -20,7 +20,7 @@ files "../atheros/files.ar71xx" hints "AR934X_BASE.hints" makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols -makeoptions MODULES_OVERRIDE="gpio ar71xx if_gif if_gre if_vlan if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_ahb hwpmc ipfw ipfw_nat libalias" +makeoptions MODULES_OVERRIDE="gpio ar71xx if_gif if_gre if_vlan if_bridge bridgestp usb wlan wlan_xauth wlan_acl wlan_wep wlan_tkip wlan_ccmp wlan_rssadapt wlan_amrr ath ath_ahb hwpmc ipfw ipfw_nat libalias urtwn urtwnfw otus otusfw" # makeoptions MODULES_OVERRIDE="" options DDB diff --git a/sys/mips/conf/BCM b/sys/mips/conf/BCM new file mode 100644 index 0000000..788bbd8 --- /dev/null +++ b/sys/mips/conf/BCM @@ -0,0 +1,95 @@ +# +# $FreeBSD$ +# +# The Broadcom 470x/471x/535x series of processors and boards is very commonly +# used in COTS hardware including the ASUS RT-N12, RT-N16, RT-N53. +# + +ident BCM + +hints "BCM.hints" +include "../broadcom/std.broadcom" + +# ships with cfe firmware +options CFE +options ALT_BREAK_TO_DEBUGGER +options BREAK_TO_DEBUGGER +options BOOTVERBOSE=0 + +makeoptions INTRNG +options INTRNG + +makeoptions TRAMPLOADADDR=0x80800000 +makeoptions DEBUG="-g3" #Build kernel with gdb(1) debug symbols +makeoptions MODULES_OVERRIDE="" + +options DDB +options KDB + +options SCHED_4BSD #4BSD scheduler +options INET #InterNETworking +options NFSCL #Network Filesystem Client +#options NFS_ROOT #NFS usable as /, requires NFSCL +options PSEUDOFS #Pseudo-filesystem framework +options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions + +options FFS #Berkeley Fast Filesystem +options SOFTUPDATES #Enable FFS soft updates support +options UFS_ACL #Support for access control lists +options UFS_DIRHASH #Improve performance on big directories + +device geom_uzip +options GEOM_UZIP +options GEOM_LABEL # Providers labelization. +options ROOTDEVNAME=\"ufs:ufs/FBSD\" # assumes FW built by + # freebsd-build-wifi + +# Debugging for use in -current +#options DEADLKRES +options INVARIANTS +options INVARIANT_SUPPORT + +#options BHND_LOGLEVEL=BHND_DEBUG_LEVEL +#options BUS_DEBUG +#makeoptions BUS_DEBUG +#options VERBOSE_SYSINIT +#makeoptions VERBOSE_SYSINIT + +device pci + +#device bgmac # Broadcom GMAC - not yet +device bhnd + +device mdio + +#Flash +device spibus +device mx25l # Serial Flash +device cfi # Parallel Flash +device cfid + +#UART +device uart + +#Base +device loop +device ether +device random +device md + +#Performance +#options HWPMC_HOOKS +#device hwpmc +#device hwpmc_mips74k + +#Ethernet +# device bfe # XXX will build both pci and siba +device miibus # attachments + +# pci devices + +# USB is not yet ready +#options USB_DEBUG # enable debug msgs +#device usb # USB Bus (required) +#device uhci # UHCI PCI->USB interface +#device ehci # EHCI PCI->USB interface (USB 2.0) diff --git a/sys/mips/conf/BCM.hints b/sys/mips/conf/BCM.hints new file mode 100644 index 0000000..5fdd240 --- /dev/null +++ b/sys/mips/conf/BCM.hints @@ -0,0 +1,6 @@ +# $FreeBSD$ +hint.bhnd_soc.0.at="nexus0" +# XXX ? +hint.bhnd_soc.0.maddr="0x00000000" +hint.bhnd_soc.0.msize="0x20000000" + diff --git a/sys/mips/conf/DIR-825C1.hints b/sys/mips/conf/DIR-825C1.hints index 7f19be6..60bb1b4 100644 --- a/sys/mips/conf/DIR-825C1.hints +++ b/sys/mips/conf/DIR-825C1.hints @@ -6,7 +6,7 @@ hint.argemdio.0.maddr=0x19000000 hint.argemdio.0.msize=0x1000 hint.argemdio.0.order=0 -# 0x1ffe0004 is the the "unit MAC". +# 0x1ffe0004 is the "unit MAC". # 0x1ffe0018 is the second "MAC". # Right now this doesn't have any option for more than one # "unit MACs", so: diff --git a/sys/mips/mediatek/mtk_gpio_v1.c b/sys/mips/mediatek/mtk_gpio_v1.c index 7ca3a12..e1443b1 100644 --- a/sys/mips/mediatek/mtk_gpio_v1.c +++ b/sys/mips/mediatek/mtk_gpio_v1.c @@ -308,7 +308,7 @@ mtk_gpio_attach(device_t dev) goto fail; } - if (intr_pic_register(dev, OF_xref_from_node(node)) != 0) { + if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { device_printf(dev, "could not register PIC\n"); goto fail; } diff --git a/sys/mips/mediatek/mtk_gpio_v2.c b/sys/mips/mediatek/mtk_gpio_v2.c index 75c7263..cd17082 100644 --- a/sys/mips/mediatek/mtk_gpio_v2.c +++ b/sys/mips/mediatek/mtk_gpio_v2.c @@ -299,7 +299,7 @@ mtk_gpio_attach(device_t dev) goto fail; } - if (intr_pic_register(dev, OF_xref_from_node(node)) != 0) { + if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { device_printf(dev, "could not register PIC\n"); goto fail; } diff --git a/sys/mips/mediatek/mtk_intr_gic.c b/sys/mips/mediatek/mtk_intr_gic.c index ea8c887..98ccdcc 100644 --- a/sys/mips/mediatek/mtk_intr_gic.c +++ b/sys/mips/mediatek/mtk_intr_gic.c @@ -213,7 +213,7 @@ mtk_gic_attach(device_t dev) * Now, when everything is initialized, it's right time to * register interrupt controller to interrupt framefork. */ - if (intr_pic_register(dev, xref) != 0) { + if (intr_pic_register(dev, xref) == NULL) { device_printf(dev, "could not register PIC\n"); goto cleanup; } diff --git a/sys/mips/mediatek/mtk_intr_v1.c b/sys/mips/mediatek/mtk_intr_v1.c index 58b610d..ed79520 100644 --- a/sys/mips/mediatek/mtk_intr_v1.c +++ b/sys/mips/mediatek/mtk_intr_v1.c @@ -201,7 +201,7 @@ mtk_pic_attach(device_t dev) * Now, when everything is initialized, it's right time to * register interrupt controller to interrupt framefork. */ - if (intr_pic_register(dev, xref) != 0) { + if (intr_pic_register(dev, xref) == NULL) { device_printf(dev, "could not register PIC\n"); goto cleanup; } diff --git a/sys/mips/mediatek/mtk_intr_v2.c b/sys/mips/mediatek/mtk_intr_v2.c index 556738f..bb544f5 100644 --- a/sys/mips/mediatek/mtk_intr_v2.c +++ b/sys/mips/mediatek/mtk_intr_v2.c @@ -196,7 +196,7 @@ mtk_pic_attach(device_t dev) * Now, when everything is initialized, it's right time to * register interrupt controller to interrupt framefork. */ - if (intr_pic_register(dev, xref) != 0) { + if (intr_pic_register(dev, xref) == NULL) { device_printf(dev, "could not register PIC\n"); goto cleanup; } diff --git a/sys/mips/mediatek/mtk_pcie.c b/sys/mips/mediatek/mtk_pcie.c index d36f6a4..930c924 100644 --- a/sys/mips/mediatek/mtk_pcie.c +++ b/sys/mips/mediatek/mtk_pcie.c @@ -203,6 +203,7 @@ mtk_pci_ranges(phandle_t node, struct mtk_pci_range *io_space, static struct ofw_compat_data compat_data[] = { { "ralink,rt3883-pci", MTK_SOC_RT3883 }, { "mediatek,mt7620-pci", MTK_SOC_MT7620A }, + { "mediatek,mt7628-pci", MTK_SOC_MT7628 }, { "mediatek,mt7621-pci", MTK_SOC_MT7621 }, { NULL, MTK_SOC_UNKNOWN } }; @@ -318,7 +319,7 @@ mtk_pci_attach(device_t dev) } /* Register ourselves as an interrupt controller */ - if (intr_pic_register(dev, xref) != 0) { + if (intr_pic_register(dev, xref) == NULL) { device_printf(dev, "could not register PIC\n"); goto cleanup_rman; } diff --git a/sys/mips/mediatek/mtk_soc.c b/sys/mips/mediatek/mtk_soc.c index f8e974c..ff40abf 100644 --- a/sys/mips/mediatek/mtk_soc.c +++ b/sys/mips/mediatek/mtk_soc.c @@ -61,9 +61,12 @@ static const struct ofw_compat_data compat_data[] = { { "ralink,rt3883-soc", MTK_SOC_RT3883 }, { "ralink,rt5350-soc", MTK_SOC_RT5350 }, { "ralink,mtk7620a-soc", MTK_SOC_MT7620A }, + { "ralink,mt7620a-soc", MTK_SOC_MT7620A }, { "ralink,mtk7620n-soc", MTK_SOC_MT7620N }, + { "ralink,mt7620n-soc", MTK_SOC_MT7620N }, { "mediatek,mtk7621-soc", MTK_SOC_MT7621 }, { "mediatek,mt7621-soc", MTK_SOC_MT7621 }, + { "ralink,mt7621-soc", MTK_SOC_MT7621 }, { "ralink,mtk7621-soc", MTK_SOC_MT7621 }, { "ralink,mtk7628an-soc", MTK_SOC_MT7628 }, { "mediatek,mt7628an-soc", MTK_SOC_MT7628 }, diff --git a/sys/mips/mips/mips_pic.c b/sys/mips/mips/mips_pic.c index 9b7eeb0..c2e8db7 100644 --- a/sys/mips/mips/mips_pic.c +++ b/sys/mips/mips/mips_pic.c @@ -223,7 +223,7 @@ mips_pic_attach(device_t dev) * Now, when everything is initialized, it's right time to * register interrupt controller to interrupt framefork. */ - if (intr_pic_register(dev, xref) != 0) { + if (intr_pic_register(dev, xref) == NULL) { device_printf(dev, "could not register PIC\n"); goto cleanup; } diff --git a/sys/modules/Makefile b/sys/modules/Makefile index 57e27b0..5548b38 100644 --- a/sys/modules/Makefile +++ b/sys/modules/Makefile @@ -312,7 +312,6 @@ SUBDIR= \ ${_rdma} \ ${_rdrand_rng} \ re \ - reiserfs \ rl \ rtwn \ ${_rtwnfw} \ diff --git a/sys/modules/bhnd/cores/bhnd_pci/Makefile b/sys/modules/bhnd/cores/bhnd_pci/Makefile index c82f68c..fb6ce43 100644 --- a/sys/modules/bhnd/cores/bhnd_pci/Makefile +++ b/sys/modules/bhnd/cores/bhnd_pci/Makefile @@ -1,9 +1,10 @@ # $FreeBSD$ .PATH: ${.CURDIR}/../../../../dev/bhnd/cores/pci +.PATH: ${.CURDIR}/../../../../dev/bhnd/cores/pcie2 KMOD= bhnd_pci -SRCS= bhnd_pci.c +SRCS= bhnd_pci.c bhnd_pcie2.c SRCS+= device_if.h bus_if.h bhnd_bus_if.h .include <bsd.kmod.mk> diff --git a/sys/modules/bhnd/cores/bhnd_pci_hostb/Makefile b/sys/modules/bhnd/cores/bhnd_pci_hostb/Makefile index d7597af..bbfa7b2 100644 --- a/sys/modules/bhnd/cores/bhnd_pci_hostb/Makefile +++ b/sys/modules/bhnd/cores/bhnd_pci_hostb/Makefile @@ -1,9 +1,11 @@ # $FreeBSD$ .PATH: ${.CURDIR}/../../../../dev/bhnd/cores/pci +.PATH: ${.CURDIR}/../../../../dev/bhnd/cores/pcie2 KMOD= bhnd_pci_hostb -SRCS= bhnd_pci_hostb.c -SRCS+= device_if.h bus_if.h bhnd_bus_if.h +SRCS= bhnd_pci_hostb.c bhnd_pcie2_hostb.c +SRCS+= device_if.h bus_if.h pci_if.h \ + bhnd_bus_if.h bhnd_chipc_if.h .include <bsd.kmod.mk> diff --git a/sys/modules/bhnd/cores/bhnd_pcib/Makefile b/sys/modules/bhnd/cores/bhnd_pcib/Makefile index 3e23177..c9bb61d 100644 --- a/sys/modules/bhnd/cores/bhnd_pcib/Makefile +++ b/sys/modules/bhnd/cores/bhnd_pcib/Makefile @@ -1,9 +1,11 @@ # $FreeBSD$ .PATH: ${.CURDIR}/../../../../dev/bhnd/cores/pci +.PATH: ${.CURDIR}/../../../../dev/bhnd/cores/pcie2 KMOD= bhnd_pcib -SRCS= bhnd_pcib.c -SRCS+= device_if.h bus_if.h bhnd_bus_if.h +SRCS= bhnd_pcib.c bhnd_pcie2b.c +SRCS+= device_if.h bus_if.h pci_if.h \ + bhnd_bus_if.h .include <bsd.kmod.mk> diff --git a/sys/modules/bwn/Makefile b/sys/modules/bwn/Makefile index a55ee96..dbad3c3 100644 --- a/sys/modules/bwn/Makefile +++ b/sys/modules/bwn/Makefile @@ -9,10 +9,23 @@ SRCS+= if_bwn_util.c # PHY SRCS+= if_bwn_phy_common.c SRCS+= if_bwn_phy_g.c if_bwn_phy_lp.c +SRCS+= if_bwn_phy_n.c # Other SRCS+= device_if.h bus_if.h pci_if.h +# Uncomment this for the GPL PHY code; this requires the +# module be built with BWN_GPL_PHY set in the kernel +# configuration. + +#.PATH: ${.CURDIR}/../../gnu/dev/bwn/phy_n +#SRCS+= if_bwn_radio_2055.c +#SRCS+= if_bwn_radio_2056.c +#SRCS+= if_bwn_radio_2057.c +#SRCS+= if_bwn_phy_n_tables.c +#SRCS+= if_bwn_phy_n_ppr.c +#SRCS+= if_bwn_phy_n_core.c + .include <bsd.kmod.mk> # XXX Work around clang warning, until maintainer approves fix. diff --git a/sys/modules/iscsi/Makefile b/sys/modules/iscsi/Makefile index 74a971c..1c88363 100644 --- a/sys/modules/iscsi/Makefile +++ b/sys/modules/iscsi/Makefile @@ -5,8 +5,8 @@ KMOD= iscsi SRCS= iscsi.c SRCS+= icl.c -SRCS+= icl_proxy.c SRCS+= icl_soft.c +SRCS+= icl_soft_proxy.c SRCS+= opt_cam.h SRCS+= bus_if.h SRCS+= device_if.h diff --git a/sys/modules/reiserfs/Makefile b/sys/modules/reiserfs/Makefile deleted file mode 100644 index 64d0440..0000000 --- a/sys/modules/reiserfs/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# $FreeBSD$ - -.PATH: ${.CURDIR}/../../gnu/fs/reiserfs -KMOD= reiserfs -SRCS= vnode_if.h \ - reiserfs_fs.h reiserfs_fs_i.h reiserfs_fs_sb.h reiserfs_hashes.c \ - reiserfs_inode.c reiserfs_item_ops.c reiserfs_mount.h \ - reiserfs_namei.c reiserfs_prints.c reiserfs_stree.c \ - reiserfs_vfsops.c reiserfs_vnops.c - -.include <bsd.kmod.mk> diff --git a/sys/net/altq/altq_cbq.c b/sys/net/altq/altq_cbq.c index 56c14d3..32fea17 100644 --- a/sys/net/altq/altq_cbq.c +++ b/sys/net/altq/altq_cbq.c @@ -702,7 +702,7 @@ cbq_modify_class(acp) * * This function create a new traffic class in the CBQ class hierarchy of * given parameters. The class that created is either the root, default, - * or a new dynamic class. If CBQ is not initilaized, the the root class + * or a new dynamic class. If CBQ is not initilaized, the root class * will be created. */ static int diff --git a/sys/net/if.c b/sys/net/if.c index 800cb70..33eb239 100644 --- a/sys/net/if.c +++ b/sys/net/if.c @@ -182,6 +182,9 @@ static int if_getgroupmembers(struct ifgroupreq *); static void if_delgroups(struct ifnet *); static void if_attach_internal(struct ifnet *, int, struct if_clone *); static int if_detach_internal(struct ifnet *, int, struct if_clone **); +#ifdef VIMAGE +static void if_vmove(struct ifnet *, struct vnet *); +#endif #ifdef INET6 /* @@ -392,6 +395,20 @@ vnet_if_uninit(const void *unused __unused) } VNET_SYSUNINIT(vnet_if_uninit, SI_SUB_INIT_IF, SI_ORDER_FIRST, vnet_if_uninit, NULL); + +static void +vnet_if_return(const void *unused __unused) +{ + struct ifnet *ifp, *nifp; + + /* Return all inherited interfaces to their parent vnets. */ + TAILQ_FOREACH_SAFE(ifp, &V_ifnet, if_link, nifp) { + if (ifp->if_home_vnet != ifp->if_vnet) + if_vmove(ifp, ifp->if_home_vnet); + } +} +VNET_SYSUNINIT(vnet_if_return, SI_SUB_VNET_DONE, SI_ORDER_ANY, + vnet_if_return, NULL); #endif static void @@ -3900,6 +3917,19 @@ if_multiaddr_count(if_t ifp, int max) return (count); } +int +if_multi_apply(struct ifnet *ifp, int (*filter)(void *, struct ifmultiaddr *, int), void *arg) +{ + struct ifmultiaddr *ifma; + int cnt = 0; + + if_maddr_rlock(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) + cnt += filter(arg, ifma, cnt); + if_maddr_runlock(ifp); + return (cnt); +} + struct mbuf * if_dequeue(if_t ifp) { diff --git a/sys/net/if_var.h b/sys/net/if_var.h index 54de567..f0766ee 100644 --- a/sys/net/if_var.h +++ b/sys/net/if_var.h @@ -535,7 +535,6 @@ void if_dead(struct ifnet *); int if_delmulti(struct ifnet *, struct sockaddr *); void if_delmulti_ifma(struct ifmultiaddr *); void if_detach(struct ifnet *); -void if_vmove(struct ifnet *, struct vnet *); void if_purgeaddrs(struct ifnet *); void if_delallmulti(struct ifnet *); void if_down(struct ifnet *); @@ -628,6 +627,7 @@ int if_setupmultiaddr(if_t ifp, void *mta, int *cnt, int max); int if_multiaddr_array(if_t ifp, void *mta, int *cnt, int max); int if_multiaddr_count(if_t ifp, int max); +int if_multi_apply(struct ifnet *ifp, int (*filter)(void *, struct ifmultiaddr *, int), void *arg); int if_getamcount(if_t ifp); struct ifaddr * if_getifaddr(if_t ifp); diff --git a/sys/net/ifdi_if.m b/sys/net/ifdi_if.m new file mode 100644 index 0000000..60629e4 --- /dev/null +++ b/sys/net/ifdi_if.m @@ -0,0 +1,334 @@ +# +# Copyright (c) 2014, Matthew Macy (kmacy@freebsd.org) +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Neither the name of Matthew Macy nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# $FreeBSD$ +# + +#include <sys/types.h> +#include <sys/systm.h> +#include <sys/socket.h> + +#include <machine/bus.h> +#include <sys/bus.h> + +#include <net/ethernet.h> +#include <net/if.h> +#include <net/if_var.h> +#include <net/if_media.h> +#include <net/iflib.h> + +INTERFACE ifdi; + +CODE { + + static void + null_void_op(if_ctx_t _ctx __unused) + { + } + + static void + null_timer_op(if_ctx_t _ctx __unused, uint16_t _qsidx __unused) + { + } + + static int + null_int_op(if_ctx_t _ctx __unused) + { + return (0); + } + + static void + null_queue_intr_enable(if_ctx_t _ctx __unused, uint16_t _qid __unused) + { + } + + static void + null_led_func(if_ctx_t _ctx __unused, int _onoff __unused) + { + } + + static void + null_vlan_register_op(if_ctx_t _ctx __unused, uint16_t vtag __unused) + { + } + + static int + null_q_setup(if_ctx_t _ctx __unused, uint32_t _qid __unused) + { + return (0); + } + + static int + null_i2c_req(if_ctx_t _sctx __unused, struct ifi2creq *_i2c __unused) + { + return (ENOTSUP); + } + + static int + null_sysctl_int_delay(if_ctx_t _sctx __unused, if_int_delay_info_t _iidi __unused) + { + return (0); + } + + static int + null_iov_init(if_ctx_t _ctx __unused, uint16_t num_vfs __unused, const nvlist_t *params __unused) + { + return (ENOTSUP); + } + + static int + null_vf_add(if_ctx_t _ctx __unused, uint16_t num_vfs __unused, const nvlist_t *params __unused) + { + return (ENOTSUP); + } + + static int + null_priv_ioctl(if_ctx_t _ctx __unused, u_long command, caddr_t *data __unused) + { + return (ENOTSUP); + } +}; + +# +# bus interfaces +# + +METHOD int attach_pre { + if_ctx_t _ctx; +}; + +METHOD int attach_post { + if_ctx_t _ctx; +}; + +METHOD int detach { + if_ctx_t _ctx; +}; + +METHOD int suspend { + if_ctx_t _ctx; +} DEFAULT null_int_op; + +METHOD int shutdown { + if_ctx_t _ctx; +} DEFAULT null_int_op; + +METHOD int resume { + if_ctx_t _ctx; +} DEFAULT null_int_op; + +# +# downcall to driver to allocate its +# own queue state and tie it to the parent +# + +METHOD int tx_queues_alloc { + if_ctx_t _ctx; + caddr_t *_vaddrs; + uint64_t *_paddrs; + int ntxqs; + int ntxqsets; +}; + +METHOD int rx_queues_alloc { + if_ctx_t _ctx; + caddr_t *_vaddrs; + uint64_t *_paddrs; + int nrxqs; + int nrxqsets; +}; + +METHOD void queues_free { + if_ctx_t _ctx; +}; + +# +# interface reset / stop +# + +METHOD void init { + if_ctx_t _ctx; +}; + +METHOD void stop { + if_ctx_t _ctx; +}; + +# +# interrupt setup and manipulation +# + +METHOD int msix_intr_assign { + if_ctx_t _sctx; + int msix; +}; + +METHOD void intr_enable { + if_ctx_t _ctx; +}; + +METHOD void intr_disable { + if_ctx_t _ctx; +}; + +METHOD void queue_intr_enable { + if_ctx_t _ctx; + uint16_t _qid; +} DEFAULT null_queue_intr_enable; + +METHOD void link_intr_enable { + if_ctx_t _ctx; +} DEFAULT null_void_op; + +# +# interface configuration +# + +METHOD void multi_set { + if_ctx_t _ctx; +}; + +METHOD int mtu_set { + if_ctx_t _ctx; + uint32_t _mtu; +}; + +METHOD void media_set{ + if_ctx_t _ctx; +} DEFAULT null_void_op; + +METHOD int promisc_set { + if_ctx_t _ctx; + int _flags; +}; + +METHOD void crcstrip_set { + if_ctx_t _ctx; + int _onoff; +}; + +# +# IOV handling +# + +METHOD void vflr_handle { + if_ctx_t _ctx; +} DEFAULT null_void_op; + +METHOD int iov_init { + if_ctx_t _ctx; + uint16_t num_vfs; + const nvlist_t * params; +} DEFAULT null_iov_init; + +METHOD void iov_uninit { + if_ctx_t _ctx; +} DEFAULT null_void_op; + +METHOD int iov_vf_add { + if_ctx_t _ctx; + uint16_t num_vfs; + const nvlist_t * params; +} DEFAULT null_vf_add; + + +# +# Device status +# + +METHOD void update_admin_status { + if_ctx_t _ctx; +}; + +METHOD void media_status { + if_ctx_t _ctx; + struct ifmediareq *_ifm; +}; + +METHOD int media_change { + if_ctx_t _ctx; +}; + +METHOD uint64_t get_counter { + if_ctx_t _ctx; + ift_counter cnt; +}; + +METHOD int priv_ioctl { + if_ctx_t _ctx; + u_long _cmd; + caddr_t _data; +} DEFAULT null_priv_ioctl; + +# +# optional methods +# + +METHOD int i2c_req { + if_ctx_t _ctx; + struct ifi2creq *_req; +} DEFAULT null_i2c_req; + +METHOD int txq_setup { + if_ctx_t _ctx; + uint32_t _txqid; +} DEFAULT null_q_setup; + +METHOD int rxq_setup { + if_ctx_t _ctx; + uint32_t _txqid; +} DEFAULT null_q_setup; + +METHOD void timer { + if_ctx_t _ctx; + uint16_t _txqid; +} DEFAULT null_timer_op; + +METHOD void watchdog_reset { + if_ctx_t _ctx; +} DEFAULT null_void_op; + +METHOD void led_func { + if_ctx_t _ctx; + int _onoff; +} DEFAULT null_led_func; + +METHOD void vlan_register { + if_ctx_t _ctx; + uint16_t _vtag; +} DEFAULT null_vlan_register_op; + +METHOD void vlan_unregister { + if_ctx_t _ctx; + uint16_t _vtag; +} DEFAULT null_vlan_register_op; + +METHOD int sysctl_int_delay { + if_ctx_t _sctx; + if_int_delay_info_t _iidi; +} DEFAULT null_sysctl_int_delay; + + diff --git a/sys/net/iflib.c b/sys/net/iflib.c new file mode 100644 index 0000000..be5b85b --- /dev/null +++ b/sys/net/iflib.c @@ -0,0 +1,4795 @@ +/*- + * Copyright (c) 2014-2016, Matthew Macy <mmacy@nextbsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Neither the name of Matthew Macy nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include "opt_inet.h" +#include "opt_inet6.h" +#include "opt_acpi.h" + +#include <sys/param.h> +#include <sys/types.h> +#include <sys/bus.h> +#include <sys/eventhandler.h> +#include <sys/sockio.h> +#include <sys/kernel.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <sys/module.h> +#include <sys/kobj.h> +#include <sys/rman.h> +#include <sys/sbuf.h> +#include <sys/smp.h> +#include <sys/socket.h> +#include <sys/sysctl.h> +#include <sys/syslog.h> +#include <sys/taskqueue.h> + + +#include <net/if.h> +#include <net/if_var.h> +#include <net/if_types.h> +#include <net/if_media.h> +#include <net/bpf.h> +#include <net/ethernet.h> +#include <net/mp_ring.h> + +#include <netinet/in.h> +#include <netinet/in_pcb.h> +#include <netinet/tcp_lro.h> +#include <netinet/in_systm.h> +#include <netinet/if_ether.h> +#include <netinet/ip.h> +#include <netinet/ip6.h> +#include <netinet/tcp.h> + +#include <machine/bus.h> +#include <machine/in_cksum.h> + +#include <vm/vm.h> +#include <vm/pmap.h> + +#include <dev/led/led.h> +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pci_private.h> + +#include <net/iflib.h> + +#include "ifdi_if.h" + +#if defined(__i386__) || defined(__amd64__) +#include <sys/memdesc.h> +#include <machine/bus.h> +#include <machine/md_var.h> +#include <machine/specialreg.h> +#include <x86/include/busdma_impl.h> +#include <x86/iommu/busdma_dmar.h> +#endif + + +/* + * enable accounting of every mbuf as it comes in to and goes out of iflib's software descriptor references + */ +#define MEMORY_LOGGING 0 +/* + * Enable mbuf vectors for compressing long mbuf chains + */ + + +/* + * NB: + * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead + * we prefetch needs to be determined by the time spent in m_free vis a vis + * the cost of a prefetch. This will of course vary based on the workload: + * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which + * is quite expensive, thus suggesting very little prefetch. + * - small packet forwarding which is just returning a single mbuf to + * UMA will typically be very fast vis a vis the cost of a memory + * access. + */ + + +/* + * File organization: + * - private structures + * - iflib private utility functions + * - ifnet functions + * - vlan registry and other exported functions + * - iflib public core functions + * + * + */ +static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); + +struct iflib_txq; +typedef struct iflib_txq *iflib_txq_t; +struct iflib_rxq; +typedef struct iflib_rxq *iflib_rxq_t; +struct iflib_fl; +typedef struct iflib_fl *iflib_fl_t; + +typedef struct iflib_filter_info { + driver_filter_t *ifi_filter; + void *ifi_filter_arg; + struct grouptask *ifi_task; +} *iflib_filter_info_t; + +struct iflib_ctx { + KOBJ_FIELDS; + /* + * Pointer to hardware driver's softc + */ + void *ifc_softc; + device_t ifc_dev; + if_t ifc_ifp; + + cpuset_t ifc_cpus; + if_shared_ctx_t ifc_sctx; + struct if_softc_ctx ifc_softc_ctx; + + struct mtx ifc_mtx; + + uint16_t ifc_nhwtxqs; + uint16_t ifc_nhwrxqs; + + iflib_txq_t ifc_txqs; + iflib_rxq_t ifc_rxqs; + uint32_t ifc_if_flags; + uint32_t ifc_flags; + uint32_t ifc_max_fl_buf_size; + int ifc_in_detach; + + int ifc_link_state; + int ifc_link_irq; + int ifc_pause_frames; + int ifc_watchdog_events; + struct cdev *ifc_led_dev; + struct resource *ifc_msix_mem; + + struct if_irq ifc_legacy_irq; + struct grouptask ifc_admin_task; + struct grouptask ifc_vflr_task; + struct iflib_filter_info ifc_filter_info; + struct ifmedia ifc_media; + + struct sysctl_oid *ifc_sysctl_node; + uint16_t ifc_sysctl_ntxqs; + uint16_t ifc_sysctl_nrxqs; + uint16_t ifc_sysctl_ntxds; + uint16_t ifc_sysctl_nrxds; + struct if_txrx ifc_txrx; +#define isc_txd_encap ifc_txrx.ift_txd_encap +#define isc_txd_flush ifc_txrx.ift_txd_flush +#define isc_txd_credits_update ifc_txrx.ift_txd_credits_update +#define isc_rxd_available ifc_txrx.ift_rxd_available +#define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get +#define isc_rxd_refill ifc_txrx.ift_rxd_refill +#define isc_rxd_flush ifc_txrx.ift_rxd_flush +#define isc_rxd_refill ifc_txrx.ift_rxd_refill +#define isc_rxd_refill ifc_txrx.ift_rxd_refill +#define isc_legacy_intr ifc_txrx.ift_legacy_intr + eventhandler_tag ifc_vlan_attach_event; + eventhandler_tag ifc_vlan_detach_event; + uint8_t ifc_mac[ETHER_ADDR_LEN]; + char ifc_mtx_name[16]; +}; + + +void * +iflib_get_softc(if_ctx_t ctx) +{ + + return (ctx->ifc_softc); +} + +device_t +iflib_get_dev(if_ctx_t ctx) +{ + + return (ctx->ifc_dev); +} + +if_t +iflib_get_ifp(if_ctx_t ctx) +{ + + return (ctx->ifc_ifp); +} + +struct ifmedia * +iflib_get_media(if_ctx_t ctx) +{ + + return (&ctx->ifc_media); +} + +void +iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) +{ + + bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); +} + +if_softc_ctx_t +iflib_get_softc_ctx(if_ctx_t ctx) +{ + + return (&ctx->ifc_softc_ctx); +} + +if_shared_ctx_t +iflib_get_sctx(if_ctx_t ctx) +{ + + return (ctx->ifc_sctx); +} + +#define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) + +#define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) +#define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) + +#define RX_SW_DESC_MAP_CREATED (1 << 0) +#define TX_SW_DESC_MAP_CREATED (1 << 1) +#define RX_SW_DESC_INUSE (1 << 3) +#define TX_SW_DESC_MAPPED (1 << 4) + +typedef struct iflib_sw_rx_desc { + bus_dmamap_t ifsd_map; /* bus_dma map for packet */ + struct mbuf *ifsd_m; /* rx: uninitialized mbuf */ + caddr_t ifsd_cl; /* direct cluster pointer for rx */ + uint16_t ifsd_flags; +} *iflib_rxsd_t; + +typedef struct iflib_sw_tx_desc_val { + bus_dmamap_t ifsd_map; /* bus_dma map for packet */ + struct mbuf *ifsd_m; /* pkthdr mbuf */ + uint8_t ifsd_flags; +} *iflib_txsd_val_t; + +typedef struct iflib_sw_tx_desc_array { + bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ + struct mbuf **ifsd_m; /* pkthdr mbufs */ + uint8_t *ifsd_flags; +} iflib_txsd_array_t; + + +/* magic number that should be high enough for any hardware */ +#define IFLIB_MAX_TX_SEGS 128 +#define IFLIB_MAX_RX_SEGS 32 +#define IFLIB_RX_COPY_THRESH 128 +#define IFLIB_MAX_RX_REFRESH 32 +#define IFLIB_QUEUE_IDLE 0 +#define IFLIB_QUEUE_HUNG 1 +#define IFLIB_QUEUE_WORKING 2 + +/* this should really scale with ring size - 32 is a fairly arbitrary value for this */ +#define TX_BATCH_SIZE 16 + +#define IFLIB_RESTART_BUDGET 8 + +#define IFC_LEGACY 0x1 +#define IFC_QFLUSH 0x2 +#define IFC_MULTISEG 0x4 +#define IFC_DMAR 0x8 + +#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ + CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ + CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) +struct iflib_txq { + uint16_t ift_in_use; + uint16_t ift_cidx; + uint16_t ift_cidx_processed; + uint16_t ift_pidx; + uint8_t ift_gen; + uint8_t ift_db_pending; + uint8_t ift_db_pending_queued; + uint8_t ift_npending; + /* implicit pad */ + uint64_t ift_processed; + uint64_t ift_cleaned; +#if MEMORY_LOGGING + uint64_t ift_enqueued; + uint64_t ift_dequeued; +#endif + uint64_t ift_no_tx_dma_setup; + uint64_t ift_no_desc_avail; + uint64_t ift_mbuf_defrag_failed; + uint64_t ift_mbuf_defrag; + uint64_t ift_map_failed; + uint64_t ift_txd_encap_efbig; + uint64_t ift_pullups; + + struct mtx ift_mtx; + struct mtx ift_db_mtx; + + /* constant values */ + if_ctx_t ift_ctx; + struct ifmp_ring **ift_br; + struct grouptask ift_task; + uint16_t ift_size; + uint16_t ift_id; + struct callout ift_timer; + struct callout ift_db_check; + + iflib_txsd_array_t ift_sds; + uint8_t ift_nbr; + uint8_t ift_qstatus; + uint8_t ift_active; + uint8_t ift_closed; + int ift_watchdog_time; + struct iflib_filter_info ift_filter_info; + bus_dma_tag_t ift_desc_tag; + bus_dma_tag_t ift_tso_desc_tag; + iflib_dma_info_t ift_ifdi; +#define MTX_NAME_LEN 16 + char ift_mtx_name[MTX_NAME_LEN]; + char ift_db_mtx_name[MTX_NAME_LEN]; + bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); +} __aligned(CACHE_LINE_SIZE); + +struct iflib_fl { + uint16_t ifl_cidx; + uint16_t ifl_pidx; + uint16_t ifl_credits; + uint8_t ifl_gen; +#if MEMORY_LOGGING + uint64_t ifl_m_enqueued; + uint64_t ifl_m_dequeued; + uint64_t ifl_cl_enqueued; + uint64_t ifl_cl_dequeued; +#endif + /* implicit pad */ + + /* constant */ + uint16_t ifl_size; + uint16_t ifl_buf_size; + uint16_t ifl_cltype; + uma_zone_t ifl_zone; + iflib_rxsd_t ifl_sds; + iflib_rxq_t ifl_rxq; + uint8_t ifl_id; + bus_dma_tag_t ifl_desc_tag; + iflib_dma_info_t ifl_ifdi; + uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); + caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; +} __aligned(CACHE_LINE_SIZE); + +static inline int +get_inuse(int size, int cidx, int pidx, int gen) +{ + int used; + + if (pidx > cidx) + used = pidx - cidx; + else if (pidx < cidx) + used = size - cidx + pidx; + else if (gen == 0 && pidx == cidx) + used = 0; + else if (gen == 1 && pidx == cidx) + used = size; + else + panic("bad state"); + + return (used); +} + +#define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) + +#define IDXDIFF(head, tail, wrap) \ + ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) + +struct iflib_rxq { + /* If there is a separate completion queue - + * these are the cq cidx and pidx. Otherwise + * these are unused. + */ + uint16_t ifr_size; + uint16_t ifr_cq_cidx; + uint16_t ifr_cq_pidx; + uint8_t ifr_cq_gen; + + if_ctx_t ifr_ctx; + iflib_fl_t ifr_fl; + uint64_t ifr_rx_irq; + uint16_t ifr_id; + uint8_t ifr_lro_enabled; + uint8_t ifr_nfl; + struct lro_ctrl ifr_lc; + struct grouptask ifr_task; + struct iflib_filter_info ifr_filter_info; + iflib_dma_info_t ifr_ifdi; + /* dynamically allocate if any drivers need a value substantially larger than this */ + struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); +} __aligned(CACHE_LINE_SIZE); + +/* + * Only allow a single packet to take up most 1/nth of the tx ring + */ +#define MAX_SINGLE_PACKET_FRACTION 12 +#define IF_BAD_DMA (bus_addr_t)-1 + +static int enable_msix = 1; + +#define mtx_held(m) (((m)->mtx_lock & ~MTX_FLAGMASK) != (uintptr_t)0) + + + +#define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) + +#define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) + +#define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) +#define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) +#define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) + + +#define TXDB_LOCK_INIT(txq) mtx_init(&(txq)->ift_db_mtx, (txq)->ift_db_mtx_name, NULL, MTX_DEF) +#define TXDB_TRYLOCK(txq) mtx_trylock(&(txq)->ift_db_mtx) +#define TXDB_LOCK(txq) mtx_lock(&(txq)->ift_db_mtx) +#define TXDB_UNLOCK(txq) mtx_unlock(&(txq)->ift_db_mtx) +#define TXDB_LOCK_DESTROY(txq) mtx_destroy(&(txq)->ift_db_mtx) + +#define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) +#define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) + + +/* Our boot-time initialization hook */ +static int iflib_module_event_handler(module_t, int, void *); + +static moduledata_t iflib_moduledata = { + "iflib", + iflib_module_event_handler, + NULL +}; + +DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); +MODULE_VERSION(iflib, 1); + +MODULE_DEPEND(iflib, pci, 1, 1, 1); +MODULE_DEPEND(iflib, ether, 1, 1, 1); + +TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); +TASKQGROUP_DEFINE(if_config_tqg, 1, 1); + +#ifndef IFLIB_DEBUG_COUNTERS +#ifdef INVARIANTS +#define IFLIB_DEBUG_COUNTERS 1 +#else +#define IFLIB_DEBUG_COUNTERS 0 +#endif /* !INVARIANTS */ +#endif + +static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, + "iflib driver parameters"); + +/* + * XXX need to ensure that this can't accidentally cause the head to be moved backwards + */ +static int iflib_min_tx_latency = 0; + +SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, + &iflib_min_tx_latency, 0, "minimize transmit latency at the possibel expense of throughput"); + + +#if IFLIB_DEBUG_COUNTERS + +static int iflib_tx_seen; +static int iflib_tx_sent; +static int iflib_tx_encap; +static int iflib_rx_allocs; +static int iflib_fl_refills; +static int iflib_fl_refills_large; +static int iflib_tx_frees; + +SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, + &iflib_tx_seen, 0, "# tx mbufs seen"); +SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, + &iflib_tx_sent, 0, "# tx mbufs sent"); +SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, + &iflib_tx_encap, 0, "# tx mbufs encapped"); +SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, + &iflib_tx_frees, 0, "# tx frees"); +SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, + &iflib_rx_allocs, 0, "# rx allocations"); +SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, + &iflib_fl_refills, 0, "# refills"); +SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, + &iflib_fl_refills_large, 0, "# large refills"); + + +static int iflib_txq_drain_flushing; +static int iflib_txq_drain_oactive; +static int iflib_txq_drain_notready; +static int iflib_txq_drain_encapfail; + +SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, + &iflib_txq_drain_flushing, 0, "# drain flushes"); +SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, + &iflib_txq_drain_oactive, 0, "# drain oactives"); +SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, + &iflib_txq_drain_notready, 0, "# drain notready"); +SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, + &iflib_txq_drain_encapfail, 0, "# drain encap fails"); + + +static int iflib_encap_load_mbuf_fail; +static int iflib_encap_txq_avail_fail; +static int iflib_encap_txd_encap_fail; + +SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, + &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); +SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, + &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); +SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, + &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); + +static int iflib_task_fn_rxs; +static int iflib_rx_intr_enables; +static int iflib_fast_intrs; +static int iflib_intr_link; +static int iflib_intr_msix; +static int iflib_rx_unavail; +static int iflib_rx_ctx_inactive; +static int iflib_rx_zero_len; +static int iflib_rx_if_input; +static int iflib_rx_mbuf_null; +static int iflib_rxd_flush; + +static int iflib_verbose_debug; + +SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, + &iflib_intr_link, 0, "# intr link calls"); +SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, + &iflib_intr_msix, 0, "# intr msix calls"); +SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, + &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); +SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, + &iflib_rx_intr_enables, 0, "# rx intr enables"); +SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, + &iflib_fast_intrs, 0, "# fast_intr calls"); +SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, + &iflib_rx_unavail, 0, "# times rxeof called with no available data"); +SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, + &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); +SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, + &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); +SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, + &iflib_rx_if_input, 0, "# times rxeof called if_input"); +SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, + &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); +SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, + &iflib_rxd_flush, 0, "# times rxd_flush called"); +SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, + &iflib_verbose_debug, 0, "enable verbose debugging"); + +#define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) + +#else +#define DBG_COUNTER_INC(name) + +#endif + + + +#define IFLIB_DEBUG 0 + +static void iflib_tx_structures_free(if_ctx_t ctx); +static void iflib_rx_structures_free(if_ctx_t ctx); +static int iflib_queues_alloc(if_ctx_t ctx); +static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); +static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx); +static int iflib_qset_structures_setup(if_ctx_t ctx); +static int iflib_msix_init(if_ctx_t ctx); +static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); +static void iflib_txq_check_drain(iflib_txq_t txq, int budget); +static uint32_t iflib_txq_can_drain(struct ifmp_ring *); +static int iflib_register(if_ctx_t); +static void iflib_init_locked(if_ctx_t ctx); +static void iflib_add_device_sysctl_pre(if_ctx_t ctx); +static void iflib_add_device_sysctl_post(if_ctx_t ctx); + + +#ifdef DEV_NETMAP +#include <sys/selinfo.h> +#include <net/netmap.h> +#include <dev/netmap/netmap_kern.h> + +MODULE_DEPEND(iflib, netmap, 1, 1, 1); + +/* + * device-specific sysctl variables: + * + * ixl_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. + * During regular operations the CRC is stripped, but on some + * hardware reception of frames not multiple of 64 is slower, + * so using crcstrip=0 helps in benchmarks. + * + * ixl_rx_miss, ixl_rx_miss_bufs: + * count packets that might be missed due to lost interrupts. + */ +SYSCTL_DECL(_dev_netmap); +/* + * The xl driver by default strips CRCs and we do not override it. + */ + +int iflib_crcstrip = 1; +SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, + CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); + +int iflib_rx_miss, iflib_rx_miss_bufs; +SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, + CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); +SYSCTL_INT(_dev_netmap, OID_AUTO, ixl_rx_miss_bufs, + CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); + +/* + * Register/unregister. We are already under netmap lock. + * Only called on the first register or the last unregister. + */ +static int +iflib_netmap_register(struct netmap_adapter *na, int onoff) +{ + struct ifnet *ifp = na->ifp; + if_ctx_t ctx = ifp->if_softc; + + CTX_LOCK(ctx); + IFDI_INTR_DISABLE(ctx); + + /* Tell the stack that the interface is no longer active */ + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + + if (!CTX_IS_VF(ctx)) + IFDI_CRCSTRIP_SET(ctx, onoff); + + /* enable or disable flags and callbacks in na and ifp */ + if (onoff) { + nm_set_native_flags(na); + } else { + nm_clear_native_flags(na); + } + IFDI_INIT(ctx); + IFDI_CRCSTRIP_SET(ctx, onoff); // XXX why twice ? + CTX_UNLOCK(ctx); + return (ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1); +} + +/* + * Reconcile kernel and user view of the transmit ring. + * + * All information is in the kring. + * Userspace wants to send packets up to the one before kring->rhead, + * kernel knows kring->nr_hwcur is the first unsent packet. + * + * Here we push packets out (as many as possible), and possibly + * reclaim buffers from previously completed transmission. + * + * The caller (netmap) guarantees that there is only one instance + * running at any time. Any interference with other driver + * methods should be handled by the individual drivers. + */ +static int +iflib_netmap_txsync(struct netmap_kring *kring, int flags) +{ + struct netmap_adapter *na = kring->na; + struct ifnet *ifp = na->ifp; + struct netmap_ring *ring = kring->ring; + u_int nm_i; /* index into the netmap ring */ + u_int nic_i; /* index into the NIC ring */ + u_int n; + u_int const lim = kring->nkr_num_slots - 1; + u_int const head = kring->rhead; + struct if_pkt_info pi; + + /* + * interrupts on every tx packet are expensive so request + * them every half ring, or where NS_REPORT is set + */ + u_int report_frequency = kring->nkr_num_slots >> 1; + /* device-specific */ + if_ctx_t ctx = ifp->if_softc; + iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; + + pi.ipi_segs = txq->ift_segs; + pi.ipi_qsidx = kring->ring_id; + pi.ipi_ndescs = 0; + + bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + + /* + * First part: process new packets to send. + * nm_i is the current index in the netmap ring, + * nic_i is the corresponding index in the NIC ring. + * + * If we have packets to send (nm_i != head) + * iterate over the netmap ring, fetch length and update + * the corresponding slot in the NIC ring. Some drivers also + * need to update the buffer's physical address in the NIC slot + * even NS_BUF_CHANGED is not set (PNMB computes the addresses). + * + * The netmap_reload_map() calls is especially expensive, + * even when (as in this case) the tag is 0, so do only + * when the buffer has actually changed. + * + * If possible do not set the report/intr bit on all slots, + * but only a few times per ring or when NS_REPORT is set. + * + * Finally, on 10G and faster drivers, it might be useful + * to prefetch the next slot and txr entry. + */ + + nm_i = kring->nr_hwcur; + if (nm_i != head) { /* we have new packets to send */ + nic_i = netmap_idx_k2n(kring, nm_i); + + __builtin_prefetch(&ring->slot[nm_i]); + __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); + __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); + + for (n = 0; nm_i != head; n++) { + struct netmap_slot *slot = &ring->slot[nm_i]; + u_int len = slot->len; + uint64_t paddr; + void *addr = PNMB(na, slot, &paddr); + int flags = (slot->flags & NS_REPORT || + nic_i == 0 || nic_i == report_frequency) ? + IPI_TX_INTR : 0; + + /* device-specific */ + pi.ipi_pidx = nic_i; + pi.ipi_flags = flags; + + /* Fill the slot in the NIC ring. */ + ctx->isc_txd_encap(ctx->ifc_softc, &pi); + + /* prefetch for next round */ + __builtin_prefetch(&ring->slot[nm_i + 1]); + __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); + __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); + + NM_CHECK_ADDR_LEN(na, addr, len); + + if (slot->flags & NS_BUF_CHANGED) { + /* buffer has changed, reload map */ + netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); + } + slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); + + /* make sure changes to the buffer are synced */ + bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], + BUS_DMASYNC_PREWRITE); + + nm_i = nm_next(nm_i, lim); + nic_i = nm_next(nic_i, lim); + } + kring->nr_hwcur = head; + + /* synchronize the NIC ring */ + bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + /* (re)start the tx unit up to slot nic_i (excluded) */ + ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); + } + + /* + * Second part: reclaim buffers for completed transmissions. + */ + if (iflib_tx_credits_update(ctx, txq)) { + /* some tx completed, increment avail */ + nic_i = txq->ift_cidx_processed; + kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); + } + return (0); +} + +/* + * Reconcile kernel and user view of the receive ring. + * Same as for the txsync, this routine must be efficient. + * The caller guarantees a single invocations, but races against + * the rest of the driver should be handled here. + * + * On call, kring->rhead is the first packet that userspace wants + * to keep, and kring->rcur is the wakeup point. + * The kernel has previously reported packets up to kring->rtail. + * + * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective + * of whether or not we received an interrupt. + */ +static int +iflib_netmap_rxsync(struct netmap_kring *kring, int flags) +{ + struct netmap_adapter *na = kring->na; + struct ifnet *ifp = na->ifp; + struct netmap_ring *ring = kring->ring; + u_int nm_i; /* index into the netmap ring */ + u_int nic_i; /* index into the NIC ring */ + u_int i, n; + u_int const lim = kring->nkr_num_slots - 1; + u_int const head = kring->rhead; + int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; + struct if_rxd_info ri; + /* device-specific */ + if_ctx_t ctx = ifp->if_softc; + iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; + iflib_fl_t fl = rxq->ifr_fl; + if (head > lim) + return netmap_ring_reinit(kring); + + bzero(&ri, sizeof(ri)); + ri.iri_qsidx = kring->ring_id; + ri.iri_ifp = ctx->ifc_ifp; + /* XXX check sync modes */ + for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) + bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + /* + * First part: import newly received packets. + * + * nm_i is the index of the next free slot in the netmap ring, + * nic_i is the index of the next received packet in the NIC ring, + * and they may differ in case if_init() has been called while + * in netmap mode. For the receive ring we have + * + * nic_i = rxr->next_check; + * nm_i = kring->nr_hwtail (previous) + * and + * nm_i == (nic_i + kring->nkr_hwofs) % ring_size + * + * rxr->next_check is set to 0 on a ring reinit + */ + if (netmap_no_pendintr || force_update) { + int crclen = iflib_crcstrip ? 0 : 4; + int error, avail; + uint16_t slot_flags = kring->nkr_slot_flags; + + for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { + nic_i = fl->ifl_cidx; + nm_i = netmap_idx_n2k(kring, nic_i); + avail = ctx->isc_rxd_available(ctx->ifc_softc, kring->ring_id, nic_i); + for (n = 0; avail > 0; n++, avail--) { + error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); + if (error) + ring->slot[nm_i].len = 0; + else + ring->slot[nm_i].len = ri.iri_len - crclen; + ring->slot[nm_i].flags = slot_flags; + bus_dmamap_sync(fl->ifl_ifdi->idi_tag, + fl->ifl_sds[nic_i].ifsd_map, BUS_DMASYNC_POSTREAD); + nm_i = nm_next(nm_i, lim); + nic_i = nm_next(nic_i, lim); + } + if (n) { /* update the state variables */ + if (netmap_no_pendintr && !force_update) { + /* diagnostics */ + iflib_rx_miss ++; + iflib_rx_miss_bufs += n; + } + fl->ifl_cidx = nic_i; + kring->nr_hwtail = nm_i; + } + kring->nr_kflags &= ~NKR_PENDINTR; + } + } + /* + * Second part: skip past packets that userspace has released. + * (kring->nr_hwcur to head excluded), + * and make the buffers available for reception. + * As usual nm_i is the index in the netmap ring, + * nic_i is the index in the NIC ring, and + * nm_i == (nic_i + kring->nkr_hwofs) % ring_size + */ + /* XXX not sure how this will work with multiple free lists */ + nm_i = kring->nr_hwcur; + if (nm_i != head) { + nic_i = netmap_idx_k2n(kring, nm_i); + for (n = 0; nm_i != head; n++) { + struct netmap_slot *slot = &ring->slot[nm_i]; + uint64_t paddr; + caddr_t vaddr; + void *addr = PNMB(na, slot, &paddr); + + if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ + goto ring_reset; + + vaddr = addr; + if (slot->flags & NS_BUF_CHANGED) { + /* buffer has changed, reload map */ + netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds[nic_i].ifsd_map, addr); + slot->flags &= ~NS_BUF_CHANGED; + } + /* + * XXX we should be batching this operation - TODO + */ + ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i, &paddr, &vaddr, 1); + bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds[nic_i].ifsd_map, + BUS_DMASYNC_PREREAD); + nm_i = nm_next(nm_i, lim); + nic_i = nm_next(nic_i, lim); + } + kring->nr_hwcur = head; + + bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + /* + * IMPORTANT: we must leave one free slot in the ring, + * so move nic_i back by one unit + */ + nic_i = nm_prev(nic_i, lim); + ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); + } + + return 0; + +ring_reset: + return netmap_ring_reinit(kring); +} + +static int +iflib_netmap_attach(if_ctx_t ctx) +{ + struct netmap_adapter na; + + bzero(&na, sizeof(na)); + + na.ifp = ctx->ifc_ifp; + na.na_flags = NAF_BDG_MAYSLEEP; + MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); + MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); + + na.num_tx_desc = ctx->ifc_sctx->isc_ntxd; + na.num_rx_desc = ctx->ifc_sctx->isc_ntxd; + na.nm_txsync = iflib_netmap_txsync; + na.nm_rxsync = iflib_netmap_rxsync; + na.nm_register = iflib_netmap_register; + na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; + na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; + return (netmap_attach(&na)); +} + +static void +iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) +{ + struct netmap_adapter *na = NA(ctx->ifc_ifp); + struct netmap_slot *slot; + + slot = netmap_reset(na, NR_TX, txq->ift_id, 0); + if (slot == 0) + return; + + for (int i = 0; i < ctx->ifc_sctx->isc_ntxd; i++) { + + /* + * In netmap mode, set the map for the packet buffer. + * NOTE: Some drivers (not this one) also need to set + * the physical buffer address in the NIC ring. + * netmap_idx_n2k() maps a nic index, i, into the corresponding + * netmap slot index, si + */ + int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); + netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); + } +} +static void +iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) +{ + struct netmap_adapter *na = NA(ctx->ifc_ifp); + struct netmap_slot *slot; + iflib_rxsd_t sd; + int nrxd; + + slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); + if (slot == 0) + return; + sd = rxq->ifr_fl[0].ifl_sds; + nrxd = ctx->ifc_sctx->isc_nrxd; + for (int i = 0; i < nrxd; i++, sd++) { + int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); + uint64_t paddr; + void *addr; + caddr_t vaddr; + + vaddr = addr = PNMB(na, slot + sj, &paddr); + netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, sd->ifsd_map, addr); + /* Update descriptor and the cached value */ + ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, i, &paddr, &vaddr, 1); + } + /* preserve queue */ + if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { + struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; + int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); + ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); + } else + ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); +} + +#define iflib_netmap_detach(ifp) netmap_detach(ifp) + +#else +#define iflib_netmap_txq_init(ctx, txq) +#define iflib_netmap_rxq_init(ctx, rxq) +#define iflib_netmap_detach(ifp) + +#define iflib_netmap_attach(ctx) (0) +#define netmap_rx_irq(ifp, qid, budget) (0) + +#endif + +#if defined(__i386__) || defined(__amd64__) +static __inline void +prefetch(void *x) +{ + __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); +} +#else +#define prefetch(x) +#endif + +static void +_iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) +{ + if (err) + return; + *(bus_addr_t *) arg = segs[0].ds_addr; +} + +int +iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) +{ + int err; + if_shared_ctx_t sctx = ctx->ifc_sctx; + device_t dev = ctx->ifc_dev; + + KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); + + err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ + sctx->isc_q_align, 0, /* alignment, bounds */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + size, /* maxsize */ + 1, /* nsegments */ + size, /* maxsegsize */ + BUS_DMA_ALLOCNOW, /* flags */ + NULL, /* lockfunc */ + NULL, /* lockarg */ + &dma->idi_tag); + if (err) { + device_printf(dev, + "%s: bus_dma_tag_create failed: %d\n", + __func__, err); + goto fail_0; + } + + err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, + BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); + if (err) { + device_printf(dev, + "%s: bus_dmamem_alloc(%ju) failed: %d\n", + __func__, (uintmax_t)size, err); + goto fail_1; + } + + dma->idi_paddr = IF_BAD_DMA; + err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, + size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); + if (err || dma->idi_paddr == IF_BAD_DMA) { + device_printf(dev, + "%s: bus_dmamap_load failed: %d\n", + __func__, err); + goto fail_2; + } + + dma->idi_size = size; + return (0); + +fail_2: + bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); +fail_1: + bus_dma_tag_destroy(dma->idi_tag); +fail_0: + dma->idi_tag = NULL; + + return (err); +} + +int +iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) +{ + int i, err; + iflib_dma_info_t *dmaiter; + + dmaiter = dmalist; + for (i = 0; i < count; i++, dmaiter++) { + if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) + break; + } + if (err) + iflib_dma_free_multi(dmalist, i); + return (err); +} + +void +iflib_dma_free(iflib_dma_info_t dma) +{ + if (dma->idi_tag == NULL) + return; + if (dma->idi_paddr != IF_BAD_DMA) { + bus_dmamap_sync(dma->idi_tag, dma->idi_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(dma->idi_tag, dma->idi_map); + dma->idi_paddr = IF_BAD_DMA; + } + if (dma->idi_vaddr != NULL) { + bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); + dma->idi_vaddr = NULL; + } + bus_dma_tag_destroy(dma->idi_tag); + dma->idi_tag = NULL; +} + +void +iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) +{ + int i; + iflib_dma_info_t *dmaiter = dmalist; + + for (i = 0; i < count; i++, dmaiter++) + iflib_dma_free(*dmaiter); +} + +static int +iflib_fast_intr(void *arg) +{ + iflib_filter_info_t info = arg; + struct grouptask *gtask = info->ifi_task; + + DBG_COUNTER_INC(fast_intrs); + if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) + return (FILTER_HANDLED); + + GROUPTASK_ENQUEUE(gtask); + return (FILTER_HANDLED); +} + +static int +_iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, + driver_filter_t filter, driver_intr_t handler, void *arg, + char *name) +{ + int rc; + struct resource *res; + void *tag; + device_t dev = ctx->ifc_dev; + + MPASS(rid < 512); + irq->ii_rid = rid; + res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, + RF_SHAREABLE | RF_ACTIVE); + if (res == NULL) { + device_printf(dev, + "failed to allocate IRQ for rid %d, name %s.\n", rid, name); + return (ENOMEM); + } + irq->ii_res = res; + KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); + rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, + filter, handler, arg, &tag); + if (rc != 0) { + device_printf(dev, + "failed to setup interrupt for rid %d, name %s: %d\n", + rid, name ? name : "unknown", rc); + return (rc); + } else if (name) + bus_describe_intr(dev, res, tag, name); + + irq->ii_tag = tag; + return (0); +} + + +/********************************************************************* + * + * Allocate memory for tx_buffer structures. The tx_buffer stores all + * the information needed to transmit a packet on the wire. This is + * called only once at attach, setup is done every reset. + * + **********************************************************************/ + +static int +iflib_txsd_alloc(iflib_txq_t txq) +{ + if_ctx_t ctx = txq->ift_ctx; + if_shared_ctx_t sctx = ctx->ifc_sctx; + if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; + device_t dev = ctx->ifc_dev; + int err, nsegments, ntsosegments; + + nsegments = scctx->isc_tx_nsegments; + ntsosegments = scctx->isc_tx_tso_segments_max; + MPASS(sctx->isc_ntxd > 0); + MPASS(nsegments > 0); + MPASS(ntsosegments > 0); + /* + * Setup DMA descriptor areas. + */ + if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), + 1, 0, /* alignment, bounds */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + sctx->isc_tx_maxsize, /* maxsize */ + nsegments, /* nsegments */ + sctx->isc_tx_maxsegsize, /* maxsegsize */ + 0, /* flags */ + NULL, /* lockfunc */ + NULL, /* lockfuncarg */ + &txq->ift_desc_tag))) { + device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); + device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n", + sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize); + goto fail; + } +#ifdef INVARIANTS + device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n", + sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize); +#endif + device_printf(dev,"TSO maxsize: %d ntsosegments: %d maxsegsize: %d\n", + scctx->isc_tx_tso_size_max, ntsosegments, + scctx->isc_tx_tso_segsize_max); + if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), + 1, 0, /* alignment, bounds */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + scctx->isc_tx_tso_size_max, /* maxsize */ + ntsosegments, /* nsegments */ + scctx->isc_tx_tso_segsize_max, /* maxsegsize */ + 0, /* flags */ + NULL, /* lockfunc */ + NULL, /* lockfuncarg */ + &txq->ift_tso_desc_tag))) { + device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); + + goto fail; + } +#ifdef INVARIANTS + device_printf(dev,"TSO maxsize: %d ntsosegments: %d maxsegsize: %d\n", + scctx->isc_tx_tso_size_max, ntsosegments, + scctx->isc_tx_tso_segsize_max); +#endif + if (!(txq->ift_sds.ifsd_flags = + (uint8_t *) malloc(sizeof(uint8_t) * + sctx->isc_ntxd, M_IFLIB, M_NOWAIT | M_ZERO))) { + device_printf(dev, "Unable to allocate tx_buffer memory\n"); + err = ENOMEM; + goto fail; + } + if (!(txq->ift_sds.ifsd_m = + (struct mbuf **) malloc(sizeof(struct mbuf *) * + sctx->isc_ntxd, M_IFLIB, M_NOWAIT | M_ZERO))) { + device_printf(dev, "Unable to allocate tx_buffer memory\n"); + err = ENOMEM; + goto fail; + } + + /* Create the descriptor buffer dma maps */ +#if defined(ACPI_DMAR) || (!(defined(__i386__) && !defined(__amd64__))) + if ((ctx->ifc_flags & IFC_DMAR) == 0) + return (0); + + if (!(txq->ift_sds.ifsd_map = + (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * sctx->isc_ntxd, M_IFLIB, M_NOWAIT | M_ZERO))) { + device_printf(dev, "Unable to allocate tx_buffer map memory\n"); + err = ENOMEM; + goto fail; + } + + for (int i = 0; i < sctx->isc_ntxd; i++) { + err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); + if (err != 0) { + device_printf(dev, "Unable to create TX DMA map\n"); + goto fail; + } + } +#endif + return (0); +fail: + /* We free all, it handles case where we are in the middle */ + iflib_tx_structures_free(ctx); + return (err); +} + +static void +iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) +{ + bus_dmamap_t map; + + map = NULL; + if (txq->ift_sds.ifsd_map != NULL) + map = txq->ift_sds.ifsd_map[i]; + if (map != NULL) { + bus_dmamap_unload(txq->ift_desc_tag, map); + bus_dmamap_destroy(txq->ift_desc_tag, map); + txq->ift_sds.ifsd_map[i] = NULL; + } +} + +static void +iflib_txq_destroy(iflib_txq_t txq) +{ + if_ctx_t ctx = txq->ift_ctx; + if_shared_ctx_t sctx = ctx->ifc_sctx; + + for (int i = 0; i < sctx->isc_ntxd; i++) + iflib_txsd_destroy(ctx, txq, i); + if (txq->ift_sds.ifsd_map != NULL) { + free(txq->ift_sds.ifsd_map, M_IFLIB); + txq->ift_sds.ifsd_map = NULL; + } + if (txq->ift_sds.ifsd_m != NULL) { + free(txq->ift_sds.ifsd_m, M_IFLIB); + txq->ift_sds.ifsd_m = NULL; + } + if (txq->ift_sds.ifsd_flags != NULL) { + free(txq->ift_sds.ifsd_flags, M_IFLIB); + txq->ift_sds.ifsd_flags = NULL; + } + if (txq->ift_desc_tag != NULL) { + bus_dma_tag_destroy(txq->ift_desc_tag); + txq->ift_desc_tag = NULL; + } + if (txq->ift_tso_desc_tag != NULL) { + bus_dma_tag_destroy(txq->ift_tso_desc_tag); + txq->ift_tso_desc_tag = NULL; + } +} + +static void +iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) +{ + struct mbuf **mp; + + mp = &txq->ift_sds.ifsd_m[i]; + if (*mp == NULL) + return; + + if (txq->ift_sds.ifsd_map != NULL) { + bus_dmamap_sync(txq->ift_desc_tag, + txq->ift_sds.ifsd_map[i], + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(txq->ift_desc_tag, + txq->ift_sds.ifsd_map[i]); + } + m_freem(*mp); + DBG_COUNTER_INC(tx_frees); + *mp = NULL; +} + +static int +iflib_txq_setup(iflib_txq_t txq) +{ + if_ctx_t ctx = txq->ift_ctx; + if_shared_ctx_t sctx = ctx->ifc_sctx; + iflib_dma_info_t di; + int i; + + /* Set number of descriptors available */ + txq->ift_qstatus = IFLIB_QUEUE_IDLE; + + /* Reset indices */ + txq->ift_cidx_processed = txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; + txq->ift_size = sctx->isc_ntxd; + + for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) + bzero((void *)di->idi_vaddr, di->idi_size); + + IFDI_TXQ_SETUP(ctx, txq->ift_id); + for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) + bus_dmamap_sync(di->idi_tag, di->idi_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + return (0); +} + +/********************************************************************* + * + * Allocate memory for rx_buffer structures. Since we use one + * rx_buffer per received packet, the maximum number of rx_buffer's + * that we'll need is equal to the number of receive descriptors + * that we've allocated. + * + **********************************************************************/ +static int +iflib_rxsd_alloc(iflib_rxq_t rxq) +{ + if_ctx_t ctx = rxq->ifr_ctx; + if_shared_ctx_t sctx = ctx->ifc_sctx; + device_t dev = ctx->ifc_dev; + iflib_fl_t fl; + iflib_rxsd_t rxsd; + int err; + + MPASS(sctx->isc_nrxd > 0); + + fl = rxq->ifr_fl; + for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { + fl->ifl_sds = malloc(sizeof(struct iflib_sw_rx_desc) * + sctx->isc_nrxd, M_IFLIB, M_WAITOK | M_ZERO); + if (fl->ifl_sds == NULL) { + device_printf(dev, "Unable to allocate rx sw desc memory\n"); + return (ENOMEM); + } + fl->ifl_size = sctx->isc_nrxd; /* this isn't necessarily the same */ + err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ + 1, 0, /* alignment, bounds */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + sctx->isc_rx_maxsize, /* maxsize */ + sctx->isc_rx_nsegments, /* nsegments */ + sctx->isc_rx_maxsegsize, /* maxsegsize */ + 0, /* flags */ + NULL, /* lockfunc */ + NULL, /* lockarg */ + &fl->ifl_desc_tag); + if (err) { + device_printf(dev, "%s: bus_dma_tag_create failed %d\n", + __func__, err); + goto fail; + } + + rxsd = fl->ifl_sds; + for (int i = 0; i < sctx->isc_nrxd; i++, rxsd++) { + err = bus_dmamap_create(fl->ifl_desc_tag, 0, &rxsd->ifsd_map); + if (err) { + device_printf(dev, "%s: bus_dmamap_create failed: %d\n", + __func__, err); + goto fail; + } + } + } + return (0); + +fail: + iflib_rx_structures_free(ctx); + return (err); +} + + +/* + * Internal service routines + */ + +struct rxq_refill_cb_arg { + int error; + bus_dma_segment_t seg; + int nseg; +}; + +static void +_rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + struct rxq_refill_cb_arg *cb_arg = arg; + + cb_arg->error = error; + cb_arg->seg = segs[0]; + cb_arg->nseg = nseg; +} + + +#ifdef ACPI_DMAR +#define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) +#else +#define IS_DMAR(ctx) (0) +#endif + +/** + * rxq_refill - refill an rxq free-buffer list + * @ctx: the iflib context + * @rxq: the free-list to refill + * @n: the number of new buffers to allocate + * + * (Re)populate an rxq free-buffer list with up to @n new packet buffers. + * The caller must assure that @n does not exceed the queue's capacity. + */ +static void +_iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) +{ + struct mbuf *m; + int pidx = fl->ifl_pidx; + iflib_rxsd_t rxsd = &fl->ifl_sds[pidx]; + caddr_t cl; + int n, i = 0; + uint64_t bus_addr; + int err; + + n = count; + MPASS(n > 0); + MPASS(fl->ifl_credits + n <= fl->ifl_size); + + if (pidx < fl->ifl_cidx) + MPASS(pidx + n <= fl->ifl_cidx); + if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) + MPASS(fl->ifl_gen == 0); + if (pidx > fl->ifl_cidx) + MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); + + DBG_COUNTER_INC(fl_refills); + if (n > 8) + DBG_COUNTER_INC(fl_refills_large); + + while (n--) { + /* + * We allocate an uninitialized mbuf + cluster, mbuf is + * initialized after rx. + * + * If the cluster is still set then we know a minimum sized packet was received + */ + if ((cl = rxsd->ifsd_cl) == NULL) { + if ((cl = rxsd->ifsd_cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) + break; +#if MEMORY_LOGGING + fl->ifl_cl_enqueued++; +#endif + } + if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { + break; + } +#if MEMORY_LOGGING + fl->ifl_m_enqueued++; +#endif + + DBG_COUNTER_INC(rx_allocs); +#ifdef notyet + if ((rxsd->ifsd_flags & RX_SW_DESC_MAP_CREATED) == 0) { + int err; + + if ((err = bus_dmamap_create(fl->ifl_ifdi->idi_tag, 0, &rxsd->ifsd_map))) { + log(LOG_WARNING, "bus_dmamap_create failed %d\n", err); + uma_zfree(fl->ifl_zone, cl); + n = 0; + goto done; + } + rxsd->ifsd_flags |= RX_SW_DESC_MAP_CREATED; + } +#endif +#if defined(__i386__) || defined(__amd64__) + if (!IS_DMAR(ctx)) { + bus_addr = pmap_kextract((vm_offset_t)cl); + } else +#endif + { + struct rxq_refill_cb_arg cb_arg; + iflib_rxq_t q; + + cb_arg.error = 0; + q = fl->ifl_rxq; + err = bus_dmamap_load(fl->ifl_desc_tag, rxsd->ifsd_map, + cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); + + if (err != 0 || cb_arg.error) { + /* + * !zone_pack ? + */ + if (fl->ifl_zone == zone_pack) + uma_zfree(fl->ifl_zone, cl); + m_free(m); + n = 0; + goto done; + } + bus_addr = cb_arg.seg.ds_addr; + } + rxsd->ifsd_flags |= RX_SW_DESC_INUSE; + + MPASS(rxsd->ifsd_m == NULL); + rxsd->ifsd_cl = cl; + rxsd->ifsd_m = m; + fl->ifl_bus_addrs[i] = bus_addr; + fl->ifl_vm_addrs[i] = cl; + rxsd++; + fl->ifl_credits++; + i++; + MPASS(fl->ifl_credits <= fl->ifl_size); + if (++fl->ifl_pidx == fl->ifl_size) { + fl->ifl_pidx = 0; + fl->ifl_gen = 1; + rxsd = fl->ifl_sds; + } + if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { + ctx->isc_rxd_refill(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx, + fl->ifl_bus_addrs, fl->ifl_vm_addrs, i); + i = 0; + pidx = fl->ifl_pidx; + } + } +done: + DBG_COUNTER_INC(rxd_flush); + if (fl->ifl_pidx == 0) + pidx = fl->ifl_size - 1; + else + pidx = fl->ifl_pidx - 1; + ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); +} + +static __inline void +__iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) +{ + /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ + int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; +#ifdef INVARIANTS + int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; +#endif + + MPASS(fl->ifl_credits <= fl->ifl_size); + MPASS(reclaimable == delta); + + if (reclaimable > 0) + _iflib_fl_refill(ctx, fl, min(max, reclaimable)); +} + +static void +iflib_fl_bufs_free(iflib_fl_t fl) +{ + iflib_dma_info_t idi = fl->ifl_ifdi; + uint32_t i; + + for (i = 0; i < fl->ifl_size; i++) { + iflib_rxsd_t d = &fl->ifl_sds[i]; + + if (d->ifsd_flags & RX_SW_DESC_INUSE) { + bus_dmamap_unload(fl->ifl_desc_tag, d->ifsd_map); + bus_dmamap_destroy(fl->ifl_desc_tag, d->ifsd_map); + if (d->ifsd_m != NULL) { + m_init(d->ifsd_m, M_NOWAIT, MT_DATA, 0); + uma_zfree(zone_mbuf, d->ifsd_m); + } + if (d->ifsd_cl != NULL) + uma_zfree(fl->ifl_zone, d->ifsd_cl); + d->ifsd_flags = 0; + } else { + MPASS(d->ifsd_cl == NULL); + MPASS(d->ifsd_m == NULL); + } +#if MEMORY_LOGGING + fl->ifl_m_dequeued++; + fl->ifl_cl_dequeued++; +#endif + d->ifsd_cl = NULL; + d->ifsd_m = NULL; + } + /* + * Reset free list values + */ + fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;; + bzero(idi->idi_vaddr, idi->idi_size); +} + +/********************************************************************* + * + * Initialize a receive ring and its buffers. + * + **********************************************************************/ +static int +iflib_fl_setup(iflib_fl_t fl) +{ + iflib_rxq_t rxq = fl->ifl_rxq; + if_ctx_t ctx = rxq->ifr_ctx; + if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; + + /* + ** Free current RX buffer structs and their mbufs + */ + iflib_fl_bufs_free(fl); + /* Now replenish the mbufs */ + MPASS(fl->ifl_credits == 0); + /* + * XXX don't set the max_frame_size to larger + * than the hardware can handle + */ + if (sctx->isc_max_frame_size <= 2048) + fl->ifl_buf_size = MCLBYTES; + else if (sctx->isc_max_frame_size <= 4096) + fl->ifl_buf_size = MJUMPAGESIZE; + else if (sctx->isc_max_frame_size <= 9216) + fl->ifl_buf_size = MJUM9BYTES; + else + fl->ifl_buf_size = MJUM16BYTES; + if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) + ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; + fl->ifl_cltype = m_gettype(fl->ifl_buf_size); + fl->ifl_zone = m_getzone(fl->ifl_buf_size); + + + /* avoid pre-allocating zillions of clusters to an idle card + * potentially speeding up attach + */ + _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); + MPASS(min(128, fl->ifl_size) == fl->ifl_credits); + if (min(128, fl->ifl_size) != fl->ifl_credits) + return (ENOBUFS); + /* + * handle failure + */ + MPASS(rxq != NULL); + MPASS(fl->ifl_ifdi != NULL); + bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + return (0); +} + +/********************************************************************* + * + * Free receive ring data structures + * + **********************************************************************/ +static void +iflib_rx_sds_free(iflib_rxq_t rxq) +{ + iflib_fl_t fl; + int i; + + if (rxq->ifr_fl != NULL) { + for (i = 0; i < rxq->ifr_nfl; i++) { + fl = &rxq->ifr_fl[i]; + if (fl->ifl_desc_tag != NULL) { + bus_dma_tag_destroy(fl->ifl_desc_tag); + fl->ifl_desc_tag = NULL; + } + } + if (rxq->ifr_fl->ifl_sds != NULL) + free(rxq->ifr_fl->ifl_sds, M_IFLIB); + + free(rxq->ifr_fl, M_IFLIB); + rxq->ifr_fl = NULL; + rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; + } +} + +/* + * MI independent logic + * + */ +static void +iflib_timer(void *arg) +{ + iflib_txq_t txq = arg; + if_ctx_t ctx = txq->ift_ctx; + if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; + + if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) + return; + /* + ** Check on the state of the TX queue(s), this + ** can be done without the lock because its RO + ** and the HUNG state will be static if set. + */ + IFDI_TIMER(ctx, txq->ift_id); + if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && + (ctx->ifc_pause_frames == 0)) + goto hung; + + if (TXQ_AVAIL(txq) <= 2*scctx->isc_tx_nsegments || + ifmp_ring_is_stalled(txq->ift_br[0])) + GROUPTASK_ENQUEUE(&txq->ift_task); + + ctx->ifc_pause_frames = 0; + if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) + callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); + return; +hung: + CTX_LOCK(ctx); + if_setdrvflagbits(ctx->ifc_ifp, 0, IFF_DRV_RUNNING); + device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", + txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); + + IFDI_WATCHDOG_RESET(ctx); + ctx->ifc_watchdog_events++; + ctx->ifc_pause_frames = 0; + + iflib_init_locked(ctx); + CTX_UNLOCK(ctx); +} + +static void +iflib_init_locked(if_ctx_t ctx) +{ + if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; + if_t ifp = ctx->ifc_ifp; + iflib_fl_t fl; + iflib_txq_t txq; + iflib_rxq_t rxq; + int i, j; + + + if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); + IFDI_INTR_DISABLE(ctx); + + /* Set hardware offload abilities */ + if_clearhwassist(ifp); + if (if_getcapenable(ifp) & IFCAP_TXCSUM) + if_sethwassistbits(ifp, CSUM_IP | CSUM_TCP | CSUM_UDP, 0); + if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) + if_sethwassistbits(ifp, (CSUM_TCP_IPV6 | CSUM_UDP_IPV6), 0); + if (if_getcapenable(ifp) & IFCAP_TSO4) + if_sethwassistbits(ifp, CSUM_IP_TSO, 0); + if (if_getcapenable(ifp) & IFCAP_TSO6) + if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); + + for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { + CALLOUT_LOCK(txq); + callout_stop(&txq->ift_timer); + callout_stop(&txq->ift_db_check); + CALLOUT_UNLOCK(txq); + iflib_netmap_txq_init(ctx, txq); + } + for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { + iflib_netmap_rxq_init(ctx, rxq); + } + IFDI_INIT(ctx); + for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { + for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { + if (iflib_fl_setup(fl)) { + device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); + goto done; + } + } + } + done: + if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); + IFDI_INTR_ENABLE(ctx); + txq = ctx->ifc_txqs; + for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) + callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, + txq->ift_timer.c_cpu); +} + +static int +iflib_media_change(if_t ifp) +{ + if_ctx_t ctx = if_getsoftc(ifp); + int err; + + CTX_LOCK(ctx); + if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) + iflib_init_locked(ctx); + CTX_UNLOCK(ctx); + return (err); +} + +static void +iflib_media_status(if_t ifp, struct ifmediareq *ifmr) +{ + if_ctx_t ctx = if_getsoftc(ifp); + + CTX_LOCK(ctx); + IFDI_UPDATE_ADMIN_STATUS(ctx); + IFDI_MEDIA_STATUS(ctx, ifmr); + CTX_UNLOCK(ctx); +} + +static void +iflib_stop(if_ctx_t ctx) +{ + iflib_txq_t txq = ctx->ifc_txqs; + iflib_rxq_t rxq = ctx->ifc_rxqs; + if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; + if_shared_ctx_t sctx = ctx->ifc_sctx; + iflib_dma_info_t di; + iflib_fl_t fl; + int i, j; + + /* Tell the stack that the interface is no longer active */ + if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); + + IFDI_INTR_DISABLE(ctx); + msleep(ctx, &ctx->ifc_mtx, PUSER, "iflib_init", hz); + + /* Wait for current tx queue users to exit to disarm watchdog timer. */ + for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { + /* make sure all transmitters have completed before proceeding XXX */ + + /* clean any enqueued buffers */ + iflib_txq_check_drain(txq, 0); + /* Free any existing tx buffers. */ + for (j = 0; j < sctx->isc_ntxd; j++) { + iflib_txsd_free(ctx, txq, j); + } + txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; + txq->ift_in_use = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; + txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; + txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; + txq->ift_pullups = 0; + ifmp_ring_reset_stats(txq->ift_br[0]); + for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) + bzero((void *)di->idi_vaddr, di->idi_size); + } + for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { + /* make sure all transmitters have completed before proceeding XXX */ + + for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) + bzero((void *)di->idi_vaddr, di->idi_size); + /* also resets the free lists pidx/cidx */ + for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) + iflib_fl_bufs_free(fl); + } + IFDI_STOP(ctx); +} + +static iflib_rxsd_t +rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int *cltype, int unload) +{ + int flid, cidx; + iflib_rxsd_t sd; + iflib_fl_t fl; + iflib_dma_info_t di; + + flid = irf->irf_flid; + cidx = irf->irf_idx; + fl = &rxq->ifr_fl[flid]; + fl->ifl_credits--; +#if MEMORY_LOGGING + fl->ifl_m_dequeued++; + if (cltype) + fl->ifl_cl_dequeued++; +#endif + sd = &fl->ifl_sds[cidx]; + di = fl->ifl_ifdi; + bus_dmamap_sync(di->idi_tag, di->idi_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + /* not valid assert if bxe really does SGE from non-contiguous elements */ + MPASS(fl->ifl_cidx == cidx); + if (unload) + bus_dmamap_unload(fl->ifl_desc_tag, sd->ifsd_map); + + if (__predict_false(++fl->ifl_cidx == fl->ifl_size)) { + fl->ifl_cidx = 0; + fl->ifl_gen = 0; + } + /* YES ick */ + if (cltype) + *cltype = fl->ifl_cltype; + return (sd); +} + +static struct mbuf * +assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri) +{ + int i, padlen , flags, cltype; + struct mbuf *m, *mh, *mt; + iflib_rxsd_t sd; + caddr_t cl; + + i = 0; + do { + sd = rxd_frag_to_sd(rxq, &ri->iri_frags[i], &cltype, TRUE); + + MPASS(sd->ifsd_cl != NULL); + MPASS(sd->ifsd_m != NULL); + m = sd->ifsd_m; + if (i == 0) { + flags = M_PKTHDR|M_EXT; + mh = mt = m; + padlen = ri->iri_pad; + } else { + flags = M_EXT; + mt->m_next = m; + mt = m; + /* assuming padding is only on the first fragment */ + padlen = 0; + } + sd->ifsd_m = NULL; + cl = sd->ifsd_cl; + sd->ifsd_cl = NULL; + + /* Can these two be made one ? */ + m_init(m, M_NOWAIT, MT_DATA, flags); + m_cljset(m, cl, cltype); + /* + * These must follow m_init and m_cljset + */ + m->m_data += padlen; + ri->iri_len -= padlen; + m->m_len = ri->iri_len; + } while (++i < ri->iri_nfrags); + + return (mh); +} + + + +/* + * Process one software descriptor + */ +static struct mbuf * +iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) +{ + struct mbuf *m; + iflib_rxsd_t sd; + + /* should I merge this back in now that the two paths are basically duplicated? */ + if (ri->iri_len <= IFLIB_RX_COPY_THRESH) { + sd = rxd_frag_to_sd(rxq, &ri->iri_frags[0], NULL, FALSE); + m = sd->ifsd_m; + sd->ifsd_m = NULL; + m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); + memcpy(m->m_data, sd->ifsd_cl, ri->iri_len); + m->m_len = ri->iri_len; + } else { + m = assemble_segments(rxq, ri); + } + m->m_pkthdr.len = ri->iri_len; + m->m_pkthdr.rcvif = ri->iri_ifp; + m->m_flags |= ri->iri_flags; + m->m_pkthdr.ether_vtag = ri->iri_vtag; + m->m_pkthdr.flowid = ri->iri_flowid; + M_HASHTYPE_SET(m, ri->iri_rsstype); + m->m_pkthdr.csum_flags = ri->iri_csum_flags; + m->m_pkthdr.csum_data = ri->iri_csum_data; + return (m); +} + +static bool +iflib_rxeof(iflib_rxq_t rxq, int budget) +{ + if_ctx_t ctx = rxq->ifr_ctx; + if_shared_ctx_t sctx = ctx->ifc_sctx; + int avail, i; + uint16_t *cidxp; + struct if_rxd_info ri; + int err, budget_left, rx_bytes, rx_pkts; + iflib_fl_t fl; + struct ifnet *ifp; + struct lro_entry *queued; + int lro_enabled; + /* + * XXX early demux data packets so that if_input processing only handles + * acks in interrupt context + */ + struct mbuf *m, *mh, *mt; + + if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &budget)) { + return (FALSE); + } + + mh = mt = NULL; + MPASS(budget > 0); + rx_pkts = rx_bytes = 0; + if (sctx->isc_flags & IFLIB_HAS_CQ) + cidxp = &rxq->ifr_cq_cidx; + else + cidxp = &rxq->ifr_fl[0].ifl_cidx; + if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp)) == 0) { + for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) + __iflib_fl_refill_lt(ctx, fl, budget + 8); + DBG_COUNTER_INC(rx_unavail); + return (false); + } + + for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { + if (__predict_false(!CTX_ACTIVE(ctx))) { + DBG_COUNTER_INC(rx_ctx_inactive); + break; + } + /* + * Reset client set fields to their default values + */ + bzero(&ri, sizeof(ri)); + ri.iri_qsidx = rxq->ifr_id; + ri.iri_cidx = *cidxp; + ri.iri_ifp = ctx->ifc_ifp; + ri.iri_frags = rxq->ifr_frags; + err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); + + /* in lieu of handling correctly - make sure it isn't being unhandled */ + MPASS(err == 0); + if (sctx->isc_flags & IFLIB_HAS_CQ) { + /* we know we consumed _one_ CQ entry */ + if (++rxq->ifr_cq_cidx == sctx->isc_nrxd) { + rxq->ifr_cq_cidx = 0; + rxq->ifr_cq_gen = 0; + } + /* was this only a completion queue message? */ + if (__predict_false(ri.iri_nfrags == 0)) + continue; + } + MPASS(ri.iri_nfrags != 0); + MPASS(ri.iri_len != 0); + + /* will advance the cidx on the corresponding free lists */ + m = iflib_rxd_pkt_get(rxq, &ri); + if (avail == 0 && budget_left) + avail = iflib_rxd_avail(ctx, rxq, *cidxp); + + if (__predict_false(m == NULL)) { + DBG_COUNTER_INC(rx_mbuf_null); + continue; + } + /* imm_pkt: -- cxgb */ + if (mh == NULL) + mh = mt = m; + else { + mt->m_nextpkt = m; + mt = m; + } + } + /* make sure that we can refill faster than drain */ + for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) + __iflib_fl_refill_lt(ctx, fl, budget + 8); + + ifp = ctx->ifc_ifp; + lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); + + while (mh != NULL) { + m = mh; + mh = mh->m_nextpkt; + m->m_nextpkt = NULL; + rx_bytes += m->m_pkthdr.len; + rx_pkts++; +#if defined(INET6) || defined(INET) + if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) + continue; +#endif + DBG_COUNTER_INC(rx_if_input); + ifp->if_input(ifp, m); + } + if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); + if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); + + /* + * Flush any outstanding LRO work + */ + while ((queued = LIST_FIRST(&rxq->ifr_lc.lro_active)) != NULL) { + LIST_REMOVE(queued, next); +#if defined(INET6) || defined(INET) + tcp_lro_flush(&rxq->ifr_lc, queued); +#endif + } + return (iflib_rxd_avail(ctx, rxq, *cidxp)); +} + +#define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) +#define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) +#define TXQ_MAX_DB_DEFERRED(ctx) (ctx->ifc_sctx->isc_ntxd >> 5) +#define TXQ_MAX_DB_CONSUMED(ctx) (ctx->ifc_sctx->isc_ntxd >> 4) + +static __inline void +iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring) +{ + uint32_t dbval; + + if (ring || txq->ift_db_pending >= TXQ_MAX_DB_DEFERRED(ctx)) { + + /* the lock will only ever be contended in the !min_latency case */ + if (!TXDB_TRYLOCK(txq)) + return; + dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; + ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); + txq->ift_db_pending = txq->ift_npending = 0; + TXDB_UNLOCK(txq); + } +} + +static void +iflib_txd_deferred_db_check(void * arg) +{ + iflib_txq_t txq = arg; + + /* simple non-zero boolean so use bitwise OR */ + if ((txq->ift_db_pending | txq->ift_npending) && + txq->ift_db_pending >= txq->ift_db_pending_queued) + iflib_txd_db_check(txq->ift_ctx, txq, TRUE); + txq->ift_db_pending_queued = 0; + if (ifmp_ring_is_stalled(txq->ift_br[0])) + iflib_txq_check_drain(txq, 4); +} + +#ifdef PKT_DEBUG +static void +print_pkt(if_pkt_info_t pi) +{ + printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", + pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); + printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", + pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); + printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", + pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); +} +#endif + +#define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) +#define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) + +static int +iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) +{ + struct ether_vlan_header *eh; + struct mbuf *m; + + m = *mp; + /* + * Determine where frame payload starts. + * Jump over vlan headers if already present, + * helpful for QinQ too. + */ + if (__predict_false(m->m_len < sizeof(*eh))) { + txq->ift_pullups++; + if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) + return (ENOMEM); + } + eh = mtod(m, struct ether_vlan_header *); + if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { + pi->ipi_etype = ntohs(eh->evl_proto); + pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; + } else { + pi->ipi_etype = ntohs(eh->evl_encap_proto); + pi->ipi_ehdrlen = ETHER_HDR_LEN; + } + + switch (pi->ipi_etype) { +#ifdef INET + case ETHERTYPE_IP: + { + struct ip *ip = NULL; + struct tcphdr *th = NULL; + struct mbuf *n; + int minthlen; + + minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); + if (__predict_false(m->m_len < minthlen)) { + /* + * if this code bloat is causing too much of a hit + * move it to a separate function and mark it noinline + */ + if (m->m_len == pi->ipi_ehdrlen) { + n = m->m_next; + MPASS(n); + if (n->m_len >= sizeof(*ip)) { + ip = (struct ip *)n->m_data; + if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) + th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); + } else { + txq->ift_pullups++; + if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) + return (ENOMEM); + ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); + } + } else { + txq->ift_pullups++; + if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) + return (ENOMEM); + ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); + if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) + th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); + } + } else { + ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); + if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) + th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); + } + pi->ipi_ip_hlen = ip->ip_hl << 2; + pi->ipi_ipproto = ip->ip_p; + pi->ipi_flags |= IPI_TX_IPV4; + + if (pi->ipi_csum_flags & CSUM_IP) + ip->ip_sum = 0; + + if (pi->ipi_ipproto == IPPROTO_TCP) { + if (__predict_false(th == NULL)) { + txq->ift_pullups++; + if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) + return (ENOMEM); + th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); + } + pi->ipi_tcp_hflags = th->th_flags; + pi->ipi_tcp_hlen = th->th_off << 2; + pi->ipi_tcp_seq = th->th_seq; + } + if (IS_TSO4(pi)) { + if (__predict_false(ip->ip_p != IPPROTO_TCP)) + return (ENXIO); + th->th_sum = in_pseudo(ip->ip_src.s_addr, + ip->ip_dst.s_addr, htons(IPPROTO_TCP)); + pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; + } + break; + } +#endif +#ifdef INET6 + case ETHERTYPE_IPV6: + { + struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); + struct tcphdr *th; + pi->ipi_ip_hlen = sizeof(struct ip6_hdr); + + if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { + if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) + return (ENOMEM); + } + th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); + + /* XXX-BZ this will go badly in case of ext hdrs. */ + pi->ipi_ipproto = ip6->ip6_nxt; + pi->ipi_flags |= IPI_TX_IPV6; + + if (pi->ipi_ipproto == IPPROTO_TCP) { + if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { + if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) + return (ENOMEM); + } + pi->ipi_tcp_hflags = th->th_flags; + pi->ipi_tcp_hlen = th->th_off << 2; + } + if (IS_TSO6(pi)) { + + if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) + return (ENXIO); + /* + * The corresponding flag is set by the stack in the IPv4 + * TSO case, but not in IPv6 (at least in FreeBSD 10.2). + * So, set it here because the rest of the flow requires it. + */ + pi->ipi_csum_flags |= CSUM_TCP_IPV6; + th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); + pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; + } + break; + } +#endif + default: + pi->ipi_csum_flags &= ~CSUM_OFFLOAD; + pi->ipi_ip_hlen = 0; + break; + } + *mp = m; + return (0); +} + + +static __noinline struct mbuf * +collapse_pkthdr(struct mbuf *m0) +{ + struct mbuf *m, *m_next, *tmp; + + m = m0; + m_next = m->m_next; + while (m_next != NULL && m_next->m_len == 0) { + m = m_next; + m->m_next = NULL; + m_free(m); + m_next = m_next->m_next; + } + m = m0; + m->m_next = m_next; + if ((m_next->m_flags & M_EXT) == 0) { + m = m_defrag(m, M_NOWAIT); + } else { + tmp = m_next->m_next; + memcpy(m_next, m, MPKTHSIZE); + m = m_next; + m->m_next = tmp; + } + return (m); +} + +/* + * If dodgy hardware rejects the scatter gather chain we've handed it + * we'll need to rebuild the mbuf chain before we can call m_defrag + */ +static __noinline struct mbuf * +iflib_rebuild_mbuf(iflib_txq_t txq) +{ + + int ntxd, mhlen, len, i, pidx; + struct mbuf *m, *mh, **ifsd_m; + if_shared_ctx_t sctx; + + pidx = txq->ift_pidx; + ifsd_m = txq->ift_sds.ifsd_m; + sctx = txq->ift_ctx->ifc_sctx; + ntxd = sctx->isc_ntxd; + mh = m = ifsd_m[pidx]; + ifsd_m[pidx] = NULL; +#if MEMORY_LOGGING + txq->ift_dequeued++; +#endif + len = m->m_len; + mhlen = m->m_pkthdr.len; + i = 1; + + while (len < mhlen && (m->m_next == NULL)) { + m->m_next = ifsd_m[(pidx + i) & (ntxd-1)]; + ifsd_m[(pidx + i) & (ntxd -1)] = NULL; +#if MEMORY_LOGGING + txq->ift_dequeued++; +#endif + m = m->m_next; + len += m->m_len; + i++; + } + return (mh); +} + +static int +iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, + struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, + int max_segs, int flags) +{ + if_ctx_t ctx; + if_shared_ctx_t sctx; + int i, next, pidx, mask, err, maxsegsz, ntxd, count; + struct mbuf *m, *tmp, **ifsd_m, **mp; + + m = *m0; + + /* + * Please don't ever do this + */ + if (__predict_false(m->m_len == 0)) + *m0 = m = collapse_pkthdr(m); + + ctx = txq->ift_ctx; + sctx = ctx->ifc_sctx; + ifsd_m = txq->ift_sds.ifsd_m; + ntxd = sctx->isc_ntxd; + pidx = txq->ift_pidx; + if (map != NULL) { + uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; + + err = bus_dmamap_load_mbuf_sg(tag, map, + *m0, segs, nsegs, BUS_DMA_NOWAIT); + if (err) + return (err); + ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; + i = 0; + next = pidx; + mask = (sctx->isc_ntxd-1); + m = *m0; + do { + mp = &ifsd_m[next]; + *mp = m; + m = m->m_next; + (*mp)->m_next = NULL; + if (__predict_false((*mp)->m_len == 0)) { + m_free(*mp); + *mp = NULL; + } else + next = (pidx + i) & (ntxd-1); + } while (m != NULL); + } else { + int buflen, sgsize, max_sgsize; + vm_offset_t vaddr; + vm_paddr_t curaddr; + + count = i = 0; + maxsegsz = sctx->isc_tx_maxsize; + m = *m0; + do { + if (__predict_false(m->m_len <= 0)) { + tmp = m; + m = m->m_next; + tmp->m_next = NULL; + m_free(tmp); + continue; + } + buflen = m->m_len; + vaddr = (vm_offset_t)m->m_data; + /* + * see if we can't be smarter about physically + * contiguous mappings + */ + next = (pidx + count) & (ntxd-1); + MPASS(ifsd_m[next] == NULL); +#if MEMORY_LOGGING + txq->ift_enqueued++; +#endif + ifsd_m[next] = m; + while (buflen > 0) { + max_sgsize = MIN(buflen, maxsegsz); + curaddr = pmap_kextract(vaddr); + sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); + sgsize = MIN(sgsize, max_sgsize); + segs[i].ds_addr = curaddr; + segs[i].ds_len = sgsize; + vaddr += sgsize; + buflen -= sgsize; + i++; + if (i >= max_segs) + goto err; + } + count++; + tmp = m; + m = m->m_next; + tmp->m_next = NULL; + } while (m != NULL); + *nsegs = i; + } + return (0); +err: + *m0 = iflib_rebuild_mbuf(txq); + return (EFBIG); +} + +static int +iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) +{ + if_ctx_t ctx; + if_shared_ctx_t sctx; + if_softc_ctx_t scctx; + bus_dma_segment_t *segs; + struct mbuf *m_head; + bus_dmamap_t map; + struct if_pkt_info pi; + int remap = 0; + int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; + bus_dma_tag_t desc_tag; + + segs = txq->ift_segs; + ctx = txq->ift_ctx; + sctx = ctx->ifc_sctx; + scctx = &ctx->ifc_softc_ctx; + segs = txq->ift_segs; + ntxd = sctx->isc_ntxd; + m_head = *m_headp; + map = NULL; + + /* + * If we're doing TSO the next descriptor to clean may be quite far ahead + */ + cidx = txq->ift_cidx; + pidx = txq->ift_pidx; + next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); + + /* prefetch the next cache line of mbuf pointers and flags */ + prefetch(&txq->ift_sds.ifsd_m[next]); + if (txq->ift_sds.ifsd_map != NULL) { + prefetch(&txq->ift_sds.ifsd_map[next]); + map = txq->ift_sds.ifsd_map[pidx]; + next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); + prefetch(&txq->ift_sds.ifsd_flags[next]); + } + + + if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { + desc_tag = txq->ift_tso_desc_tag; + max_segs = scctx->isc_tx_tso_segments_max; + } else { + desc_tag = txq->ift_desc_tag; + max_segs = scctx->isc_tx_nsegments; + } + m_head = *m_headp; + bzero(&pi, sizeof(pi)); + pi.ipi_len = m_head->m_pkthdr.len; + pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); + pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; + pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; + pi.ipi_pidx = pidx; + pi.ipi_qsidx = txq->ift_id; + + /* deliberate bitwise OR to make one condition */ + if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { + if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) + return (err); + m_head = *m_headp; + } + +retry: + err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); +defrag: + if (__predict_false(err)) { + switch (err) { + case EFBIG: + /* try collapse once and defrag once */ + if (remap == 0) + m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); + if (remap == 1) + m_head = m_defrag(*m_headp, M_NOWAIT); + remap++; + if (__predict_false(m_head == NULL)) + goto defrag_failed; + txq->ift_mbuf_defrag++; + *m_headp = m_head; + goto retry; + break; + case ENOMEM: + txq->ift_no_tx_dma_setup++; + break; + default: + txq->ift_no_tx_dma_setup++; + m_freem(*m_headp); + DBG_COUNTER_INC(tx_frees); + *m_headp = NULL; + break; + } + txq->ift_map_failed++; + DBG_COUNTER_INC(encap_load_mbuf_fail); + return (err); + } + + /* + * XXX assumes a 1 to 1 relationship between segments and + * descriptors - this does not hold true on all drivers, e.g. + * cxgb + */ + if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { + txq->ift_no_desc_avail++; + if (map != NULL) + bus_dmamap_unload(desc_tag, map); + DBG_COUNTER_INC(encap_txq_avail_fail); + if (txq->ift_task.gt_task.ta_pending == 0) + GROUPTASK_ENQUEUE(&txq->ift_task); + return (ENOBUFS); + } + pi.ipi_segs = segs; + pi.ipi_nsegs = nsegs; + + MPASS(pidx >= 0 && pidx < sctx->isc_ntxd); +#ifdef PKT_DEBUG + print_pkt(&pi); +#endif + if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { + bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + DBG_COUNTER_INC(tx_encap); + MPASS(pi.ipi_new_pidx >= 0 && pi.ipi_new_pidx < sctx->isc_ntxd); + + ndesc = pi.ipi_new_pidx - pi.ipi_pidx; + if (pi.ipi_new_pidx < pi.ipi_pidx) { + ndesc += sctx->isc_ntxd; + txq->ift_gen = 1; + } + MPASS(pi.ipi_new_pidx != pidx); + MPASS(ndesc > 0); + txq->ift_in_use += ndesc; + /* + * We update the last software descriptor again here because there may + * be a sentinel and/or there may be more mbufs than segments + */ + txq->ift_pidx = pi.ipi_new_pidx; + txq->ift_npending += pi.ipi_ndescs; + } else if (__predict_false(err == EFBIG && remap < 2)) { + *m_headp = m_head = iflib_rebuild_mbuf(txq); + remap = 1; + txq->ift_txd_encap_efbig++; + goto defrag; + } else + DBG_COUNTER_INC(encap_txd_encap_fail); + return (err); + +defrag_failed: + txq->ift_mbuf_defrag_failed++; + txq->ift_map_failed++; + m_freem(*m_headp); + DBG_COUNTER_INC(tx_frees); + *m_headp = NULL; + return (ENOMEM); +} + +/* forward compatibility for cxgb */ +#define FIRST_QSET(ctx) 0 + +#define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) +#define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) +#define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NRXQSETS(ctx)) + FIRST_QSET(ctx)) +#define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) +#define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) +#define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) + + + +/* if there are more than TXQ_MIN_OCCUPANCY packets pending we consider deferring + * doorbell writes + * + * ORing with 2 assures that min occupancy is never less than 2 without any conditional logic + */ +#define TXQ_MIN_OCCUPANCY(ctx) ((ctx->ifc_sctx->isc_ntxd >> 6)| 0x2) + +static inline int +iflib_txq_min_occupancy(iflib_txq_t txq) +{ + if_ctx_t ctx; + + ctx = txq->ift_ctx; + return (get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen) < TXQ_MIN_OCCUPANCY(ctx) + MAX_TX_DESC(ctx)); +} + +static void +iflib_tx_desc_free(iflib_txq_t txq, int n) +{ + int hasmap; + uint32_t qsize, cidx, mask, gen; + struct mbuf *m, **ifsd_m; + uint8_t *ifsd_flags; + bus_dmamap_t *ifsd_map; + + cidx = txq->ift_cidx; + gen = txq->ift_gen; + qsize = txq->ift_ctx->ifc_sctx->isc_ntxd; + mask = qsize-1; + hasmap = txq->ift_sds.ifsd_map != NULL; + ifsd_flags = txq->ift_sds.ifsd_flags; + ifsd_m = txq->ift_sds.ifsd_m; + ifsd_map = txq->ift_sds.ifsd_map; + + while (n--) { + prefetch(ifsd_m[(cidx + 3) & mask]); + prefetch(ifsd_m[(cidx + 4) & mask]); + + if (ifsd_m[cidx] != NULL) { + prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); + prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); + if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { + /* + * does it matter if it's not the TSO tag? If so we'll + * have to add the type to flags + */ + bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); + ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; + } + if ((m = ifsd_m[cidx]) != NULL) { + /* XXX we don't support any drivers that batch packets yet */ + MPASS(m->m_nextpkt == NULL); + + m_freem(m); + ifsd_m[cidx] = NULL; +#if MEMORY_LOGGING + txq->ift_dequeued++; +#endif + DBG_COUNTER_INC(tx_frees); + } + } + if (__predict_false(++cidx == qsize)) { + cidx = 0; + gen = 0; + } + } + txq->ift_cidx = cidx; + txq->ift_gen = gen; +} + +static __inline int +iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) +{ + int reclaim; + if_ctx_t ctx = txq->ift_ctx; + + KASSERT(thresh >= 0, ("invalid threshold to reclaim")); + MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); + + /* + * Need a rate-limiting check so that this isn't called every time + */ + iflib_tx_credits_update(ctx, txq); + reclaim = DESC_RECLAIMABLE(txq); + + if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { +#ifdef INVARIANTS + if (iflib_verbose_debug) { + printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, + txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, + reclaim, thresh); + + } +#endif + return (0); + } + iflib_tx_desc_free(txq, reclaim); + txq->ift_cleaned += reclaim; + txq->ift_in_use -= reclaim; + + if (txq->ift_active == FALSE) + txq->ift_active = TRUE; + + return (reclaim); +} + +static struct mbuf ** +_ring_peek_one(struct ifmp_ring *r, int cidx, int offset) +{ + + return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (r->size-1)])); +} + +static void +iflib_txq_check_drain(iflib_txq_t txq, int budget) +{ + + ifmp_ring_check_drainage(txq->ift_br[0], budget); +} + +static uint32_t +iflib_txq_can_drain(struct ifmp_ring *r) +{ + iflib_txq_t txq = r->cookie; + if_ctx_t ctx = txq->ift_ctx; + + return ((TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx)) || + ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, false)); +} + +static uint32_t +iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) +{ + iflib_txq_t txq = r->cookie; + if_ctx_t ctx = txq->ift_ctx; + if_t ifp = ctx->ifc_ifp; + struct mbuf **mp, *m; + int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail, err, in_use_prev, desc_used; + + if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || + !LINK_ACTIVE(ctx))) { + DBG_COUNTER_INC(txq_drain_notready); + return (0); + } + + avail = IDXDIFF(pidx, cidx, r->size); + if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { + DBG_COUNTER_INC(txq_drain_flushing); + for (i = 0; i < avail; i++) { + m_freem(r->items[(cidx + i) & (r->size-1)]); + r->items[(cidx + i) & (r->size-1)] = NULL; + } + return (avail); + } + iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); + if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { + txq->ift_qstatus = IFLIB_QUEUE_IDLE; + CALLOUT_LOCK(txq); + callout_stop(&txq->ift_timer); + callout_stop(&txq->ift_db_check); + CALLOUT_UNLOCK(txq); + DBG_COUNTER_INC(txq_drain_oactive); + return (0); + } + consumed = mcast_sent = bytes_sent = pkt_sent = 0; + count = MIN(avail, TX_BATCH_SIZE); + + for (desc_used = i = 0; i < count && TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2; i++) { + mp = _ring_peek_one(r, cidx, i); + in_use_prev = txq->ift_in_use; + err = iflib_encap(txq, mp); + /* + * What other errors should we bail out for? + */ + if (err == ENOBUFS) { + DBG_COUNTER_INC(txq_drain_encapfail); + break; + } + consumed++; + if (err) + continue; + + pkt_sent++; + m = *mp; + DBG_COUNTER_INC(tx_sent); + bytes_sent += m->m_pkthdr.len; + if (m->m_flags & M_MCAST) + mcast_sent++; + + txq->ift_db_pending += (txq->ift_in_use - in_use_prev); + desc_used += (txq->ift_in_use - in_use_prev); + iflib_txd_db_check(ctx, txq, FALSE); + ETHER_BPF_MTAP(ifp, m); + if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) + break; + + if (desc_used > TXQ_MAX_DB_CONSUMED(ctx)) + break; + } + + if ((iflib_min_tx_latency || iflib_txq_min_occupancy(txq)) && txq->ift_db_pending) + iflib_txd_db_check(ctx, txq, TRUE); + else if ((txq->ift_db_pending || TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)) && + (callout_pending(&txq->ift_db_check) == 0)) { + txq->ift_db_pending_queued = txq->ift_db_pending; + callout_reset_on(&txq->ift_db_check, 1, iflib_txd_deferred_db_check, + txq, txq->ift_db_check.c_cpu); + } + if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); + if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); + if (mcast_sent) + if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); + + return (consumed); +} + +static void +_task_fn_tx(void *context, int pending) +{ + iflib_txq_t txq = context; + if_ctx_t ctx = txq->ift_ctx; + + if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) + return; + ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE); +} + +static void +_task_fn_rx(void *context, int pending) +{ + iflib_rxq_t rxq = context; + if_ctx_t ctx = rxq->ifr_ctx; + bool more; + + DBG_COUNTER_INC(task_fn_rxs); + if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) + return; + + if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) { + if (ctx->ifc_flags & IFC_LEGACY) + IFDI_INTR_ENABLE(ctx); + else { + DBG_COUNTER_INC(rx_intr_enables); + IFDI_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); + } + } + if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) + return; + if (more) + GROUPTASK_ENQUEUE(&rxq->ifr_task); +} + +static void +_task_fn_admin(void *context, int pending) +{ + if_ctx_t ctx = context; + if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; + iflib_txq_t txq; + int i; + + if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) + return; + + CTX_LOCK(ctx); + for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { + CALLOUT_LOCK(txq); + callout_stop(&txq->ift_timer); + CALLOUT_UNLOCK(txq); + } + IFDI_UPDATE_ADMIN_STATUS(ctx); + for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) + callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); + IFDI_LINK_INTR_ENABLE(ctx); + CTX_UNLOCK(ctx); + + if (LINK_ACTIVE(ctx) == 0) + return; + for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) + iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); +} + + +static void +_task_fn_iov(void *context, int pending) +{ + if_ctx_t ctx = context; + + if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) + return; + + CTX_LOCK(ctx); + IFDI_VFLR_HANDLE(ctx); + CTX_UNLOCK(ctx); +} + +static int +iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) +{ + int err; + if_int_delay_info_t info; + if_ctx_t ctx; + + info = (if_int_delay_info_t)arg1; + ctx = info->iidi_ctx; + info->iidi_req = req; + info->iidi_oidp = oidp; + CTX_LOCK(ctx); + err = IFDI_SYSCTL_INT_DELAY(ctx, info); + CTX_UNLOCK(ctx); + return (err); +} + +/********************************************************************* + * + * IFNET FUNCTIONS + * + **********************************************************************/ + +static void +iflib_if_init_locked(if_ctx_t ctx) +{ + iflib_stop(ctx); + iflib_init_locked(ctx); +} + + +static void +iflib_if_init(void *arg) +{ + if_ctx_t ctx = arg; + + CTX_LOCK(ctx); + iflib_if_init_locked(ctx); + CTX_UNLOCK(ctx); +} + +static int +iflib_if_transmit(if_t ifp, struct mbuf *m) +{ + if_ctx_t ctx = if_getsoftc(ifp); + + iflib_txq_t txq; + struct mbuf *marr[8], **mp, *next; + int err, i, count, qidx; + + if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { + DBG_COUNTER_INC(tx_frees); + m_freem(m); + return (0); + } + + qidx = 0; + if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) + qidx = QIDX(ctx, m); + /* + * XXX calculate buf_ring based on flowid (divvy up bits?) + */ + txq = &ctx->ifc_txqs[qidx]; + +#ifdef DRIVER_BACKPRESSURE + if (txq->ift_closed) { + while (m != NULL) { + next = m->m_nextpkt; + m->m_nextpkt = NULL; + m_freem(m); + m = next; + } + return (ENOBUFS); + } +#endif + qidx = count = 0; + mp = marr; + next = m; + do { + count++; + next = next->m_nextpkt; + } while (next != NULL); + + if (count > 8) + if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { + /* XXX check nextpkt */ + m_freem(m); + /* XXX simplify for now */ + DBG_COUNTER_INC(tx_frees); + return (ENOBUFS); + } + for (next = m, i = 0; next != NULL; i++) { + mp[i] = next; + next = next->m_nextpkt; + mp[i]->m_nextpkt = NULL; + } + DBG_COUNTER_INC(tx_seen); + err = ifmp_ring_enqueue(txq->ift_br[0], (void **)mp, count, TX_BATCH_SIZE); + + if (iflib_txq_can_drain(txq->ift_br[0])) + GROUPTASK_ENQUEUE(&txq->ift_task); + if (err) { + /* support forthcoming later */ +#ifdef DRIVER_BACKPRESSURE + txq->ift_closed = TRUE; +#endif + for (i = 0; i < count; i++) + m_freem(mp[i]); + ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE); + } + if (count > 16) + free(mp, M_IFLIB); + + return (err); +} + +static void +iflib_if_qflush(if_t ifp) +{ + if_ctx_t ctx = if_getsoftc(ifp); + iflib_txq_t txq = ctx->ifc_txqs; + int i; + + CTX_LOCK(ctx); + ctx->ifc_flags |= IFC_QFLUSH; + CTX_UNLOCK(ctx); + for (i = 0; i < NTXQSETS(ctx); i++, txq++) + while (!(ifmp_ring_is_idle(txq->ift_br[0]) || ifmp_ring_is_stalled(txq->ift_br[0]))) + iflib_txq_check_drain(txq, 0); + CTX_LOCK(ctx); + ctx->ifc_flags &= ~IFC_QFLUSH; + CTX_UNLOCK(ctx); + + if_qflush(ifp); +} + +#define IFCAP_REINIT (IFCAP_HWCSUM|IFCAP_TSO4|IFCAP_TSO6|IFCAP_VLAN_HWTAGGING|IFCAP_VLAN_MTU | \ + IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) + +#define IFCAP_FLAGS (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ + IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \ + IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) + +static int +iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) +{ + if_ctx_t ctx = if_getsoftc(ifp); + struct ifreq *ifr = (struct ifreq *)data; +#if defined(INET) || defined(INET6) + struct ifaddr *ifa = (struct ifaddr *)data; +#endif + bool avoid_reset = FALSE; + int err = 0, reinit = 0, bits; + + switch (command) { + case SIOCSIFADDR: +#ifdef INET + if (ifa->ifa_addr->sa_family == AF_INET) + avoid_reset = TRUE; +#endif +#ifdef INET6 + if (ifa->ifa_addr->sa_family == AF_INET6) + avoid_reset = TRUE; +#endif + /* + ** Calling init results in link renegotiation, + ** so we avoid doing it when possible. + */ + if (avoid_reset) { + if_setflagbits(ifp, IFF_UP,0); + if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) + reinit = 1; +#ifdef INET + if (!(if_getflags(ifp) & IFF_NOARP)) + arp_ifinit(ifp, ifa); +#endif + } else + err = ether_ioctl(ifp, command, data); + break; + case SIOCSIFMTU: + CTX_LOCK(ctx); + if (ifr->ifr_mtu == if_getmtu(ifp)) { + CTX_UNLOCK(ctx); + break; + } + bits = if_getdrvflags(ifp); + /* stop the driver and free any clusters before proceeding */ + iflib_stop(ctx); + + if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { + if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) + ctx->ifc_flags |= IFC_MULTISEG; + else + ctx->ifc_flags &= ~IFC_MULTISEG; + err = if_setmtu(ifp, ifr->ifr_mtu); + } + iflib_init_locked(ctx); + if_setdrvflags(ifp, bits); + CTX_UNLOCK(ctx); + break; + case SIOCSIFFLAGS: + CTX_LOCK(ctx); + if (if_getflags(ifp) & IFF_UP) { + if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { + if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & + (IFF_PROMISC | IFF_ALLMULTI)) { + err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); + } + } else + reinit = 1; + } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { + iflib_stop(ctx); + } + ctx->ifc_if_flags = if_getflags(ifp); + CTX_UNLOCK(ctx); + break; + + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { + CTX_LOCK(ctx); + IFDI_INTR_DISABLE(ctx); + IFDI_MULTI_SET(ctx); + IFDI_INTR_ENABLE(ctx); + CTX_UNLOCK(ctx); + } + break; + case SIOCSIFMEDIA: + CTX_LOCK(ctx); + IFDI_MEDIA_SET(ctx); + CTX_UNLOCK(ctx); + /* falls thru */ + case SIOCGIFMEDIA: + err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); + break; + case SIOCGI2C: + { + struct ifi2creq i2c; + + err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); + if (err != 0) + break; + if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { + err = EINVAL; + break; + } + if (i2c.len > sizeof(i2c.data)) { + err = EINVAL; + break; + } + + if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) + err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); + break; + } + case SIOCSIFCAP: + { + int mask, setmask; + + mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); + setmask = 0; +#ifdef TCP_OFFLOAD + setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); +#endif + setmask |= (mask & IFCAP_FLAGS); + + if ((mask & IFCAP_WOL) && + (if_getcapabilities(ifp) & IFCAP_WOL) != 0) + setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); + if_vlancap(ifp); + /* + * want to ensure that traffic has stopped before we change any of the flags + */ + if (setmask) { + CTX_LOCK(ctx); + bits = if_getdrvflags(ifp); + if (setmask & IFCAP_REINIT) + iflib_stop(ctx); + if_togglecapenable(ifp, setmask); + if (setmask & IFCAP_REINIT) + iflib_init_locked(ctx); + if_setdrvflags(ifp, bits); + CTX_UNLOCK(ctx); + } + break; + } + case SIOCGPRIVATE_0: + case SIOCSDRVSPEC: + case SIOCGDRVSPEC: + CTX_LOCK(ctx); + err = IFDI_PRIV_IOCTL(ctx, command, data); + CTX_UNLOCK(ctx); + break; + default: + err = ether_ioctl(ifp, command, data); + break; + } + if (reinit) + iflib_if_init(ctx); + return (err); +} + +static uint64_t +iflib_if_get_counter(if_t ifp, ift_counter cnt) +{ + if_ctx_t ctx = if_getsoftc(ifp); + + return (IFDI_GET_COUNTER(ctx, cnt)); +} + +/********************************************************************* + * + * OTHER FUNCTIONS EXPORTED TO THE STACK + * + **********************************************************************/ + +static void +iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) +{ + if_ctx_t ctx = if_getsoftc(ifp); + + if ((void *)ctx != arg) + return; + + if ((vtag == 0) || (vtag > 4095)) + return; + + CTX_LOCK(ctx); + IFDI_VLAN_REGISTER(ctx, vtag); + /* Re-init to load the changes */ + if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) + iflib_init_locked(ctx); + CTX_UNLOCK(ctx); +} + +static void +iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) +{ + if_ctx_t ctx = if_getsoftc(ifp); + + if ((void *)ctx != arg) + return; + + if ((vtag == 0) || (vtag > 4095)) + return; + + CTX_LOCK(ctx); + IFDI_VLAN_UNREGISTER(ctx, vtag); + /* Re-init to load the changes */ + if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) + iflib_init_locked(ctx); + CTX_UNLOCK(ctx); +} + +static void +iflib_led_func(void *arg, int onoff) +{ + if_ctx_t ctx = arg; + + CTX_LOCK(ctx); + IFDI_LED_FUNC(ctx, onoff); + CTX_UNLOCK(ctx); +} + +/********************************************************************* + * + * BUS FUNCTION DEFINITIONS + * + **********************************************************************/ + +int +iflib_device_probe(device_t dev) +{ + pci_vendor_info_t *ent; + + uint16_t pci_vendor_id, pci_device_id; + uint16_t pci_subvendor_id, pci_subdevice_id; + uint16_t pci_rev_id; + if_shared_ctx_t sctx; + + if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) + return (ENOTSUP); + + pci_vendor_id = pci_get_vendor(dev); + pci_device_id = pci_get_device(dev); + pci_subvendor_id = pci_get_subvendor(dev); + pci_subdevice_id = pci_get_subdevice(dev); + pci_rev_id = pci_get_revid(dev); + if (sctx->isc_parse_devinfo != NULL) + sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); + + ent = sctx->isc_vendor_info; + while (ent->pvi_vendor_id != 0) { + if (pci_vendor_id != ent->pvi_vendor_id) { + ent++; + continue; + } + if ((pci_device_id == ent->pvi_device_id) && + ((pci_subvendor_id == ent->pvi_subvendor_id) || + (ent->pvi_subvendor_id == 0)) && + ((pci_subdevice_id == ent->pvi_subdevice_id) || + (ent->pvi_subdevice_id == 0)) && + ((pci_rev_id == ent->pvi_rev_id) || + (ent->pvi_rev_id == 0))) { + + device_set_desc_copy(dev, ent->pvi_name); + /* this needs to be changed to zero if the bus probing code + * ever stops re-probing on best match because the sctx + * may have its values over written by register calls + * in subsequent probes + */ + return (BUS_PROBE_DEFAULT); + } + ent++; + } + return (ENXIO); +} + +int +iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) +{ + int err, rid, msix, msix_bar; + if_ctx_t ctx; + if_t ifp; + if_softc_ctx_t scctx; + + + ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); + + if (sc == NULL) { + sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); + device_set_softc(dev, ctx); + } + + ctx->ifc_sctx = sctx; + ctx->ifc_dev = dev; + ctx->ifc_txrx = *sctx->isc_txrx; + ctx->ifc_softc = sc; + + if ((err = iflib_register(ctx)) != 0) { + device_printf(dev, "iflib_register failed %d\n", err); + return (err); + } + iflib_add_device_sysctl_pre(ctx); + if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { + device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); + return (err); + } +#ifdef ACPI_DMAR + if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) + ctx->ifc_flags |= IFC_DMAR; +#endif + + scctx = &ctx->ifc_softc_ctx; + msix_bar = scctx->isc_msix_bar; + + if (scctx->isc_tx_nsegments > sctx->isc_ntxd / MAX_SINGLE_PACKET_FRACTION) + scctx->isc_tx_nsegments = max(1, sctx->isc_ntxd / MAX_SINGLE_PACKET_FRACTION); + if (scctx->isc_tx_tso_segments_max > sctx->isc_ntxd / MAX_SINGLE_PACKET_FRACTION) + scctx->isc_tx_tso_segments_max = max(1, sctx->isc_ntxd / MAX_SINGLE_PACKET_FRACTION); + + ifp = ctx->ifc_ifp; + + /* + * XXX sanity check that ntxd & nrxd are a power of 2 + */ + + /* + * Protect the stack against modern hardware + */ + if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) + scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; + + /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ + ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; + ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; + ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; + if (scctx->isc_rss_table_size == 0) + scctx->isc_rss_table_size = 64; + scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1;; + /* + ** Now setup MSI or MSI/X, should + ** return us the number of supported + ** vectors. (Will be 1 for MSI) + */ + if (sctx->isc_flags & IFLIB_SKIP_MSIX) { + msix = scctx->isc_vectors; + } else if (scctx->isc_msix_bar != 0) + msix = iflib_msix_init(ctx); + else { + scctx->isc_vectors = 1; + scctx->isc_ntxqsets = 1; + scctx->isc_nrxqsets = 1; + scctx->isc_intr = IFLIB_INTR_LEGACY; + msix = 0; + } + /* Get memory for the station queues */ + if ((err = iflib_queues_alloc(ctx))) { + device_printf(dev, "Unable to allocate queue memory\n"); + goto fail; + } + + if ((err = iflib_qset_structures_setup(ctx))) { + device_printf(dev, "qset structure setup failed %d\n", err); + goto fail_queues; + } + + if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { + device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); + goto fail_intr_free; + } + if (msix <= 1) { + rid = 0; + if (scctx->isc_intr == IFLIB_INTR_MSI) { + MPASS(msix == 1); + rid = 1; + } + if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx, &rid, "irq0")) != 0) { + device_printf(dev, "iflib_legacy_setup failed %d\n", err); + goto fail_intr_free; + } + } + ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); + if ((err = IFDI_ATTACH_POST(ctx)) != 0) { + device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); + goto fail_detach; + } + if ((err = iflib_netmap_attach(ctx))) { + device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); + goto fail_detach; + } + *ctxp = ctx; + + iflib_add_device_sysctl_post(ctx); + return (0); +fail_detach: + ether_ifdetach(ctx->ifc_ifp); +fail_intr_free: + if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) + pci_release_msi(ctx->ifc_dev); +fail_queues: + /* XXX free queues */ +fail: + IFDI_DETACH(ctx); + return (err); +} + +int +iflib_device_attach(device_t dev) +{ + if_ctx_t ctx; + if_shared_ctx_t sctx; + + if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) + return (ENOTSUP); + + pci_enable_busmaster(dev); + + return (iflib_device_register(dev, NULL, sctx, &ctx)); +} + +int +iflib_device_deregister(if_ctx_t ctx) +{ + if_t ifp = ctx->ifc_ifp; + iflib_txq_t txq; + iflib_rxq_t rxq; + device_t dev = ctx->ifc_dev; + int i; + struct taskqgroup *tqg; + + /* Make sure VLANS are not using driver */ + if (if_vlantrunkinuse(ifp)) { + device_printf(dev,"Vlan in use, detach first\n"); + return (EBUSY); + } + + CTX_LOCK(ctx); + ctx->ifc_in_detach = 1; + iflib_stop(ctx); + CTX_UNLOCK(ctx); + + /* Unregister VLAN events */ + if (ctx->ifc_vlan_attach_event != NULL) + EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); + if (ctx->ifc_vlan_detach_event != NULL) + EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); + + iflib_netmap_detach(ifp); + ether_ifdetach(ifp); + /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ + CTX_LOCK_DESTROY(ctx); + if (ctx->ifc_led_dev != NULL) + led_destroy(ctx->ifc_led_dev); + /* XXX drain any dependent tasks */ + tqg = qgroup_if_io_tqg; + for (txq = ctx->ifc_txqs, i = 0, rxq = ctx->ifc_rxqs; i < NTXQSETS(ctx); i++, txq++) { + callout_drain(&txq->ift_timer); + callout_drain(&txq->ift_db_check); + if (txq->ift_task.gt_uniq != NULL) + taskqgroup_detach(tqg, &txq->ift_task); + } + for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { + if (rxq->ifr_task.gt_uniq != NULL) + taskqgroup_detach(tqg, &rxq->ifr_task); + } + tqg = qgroup_if_config_tqg; + if (ctx->ifc_admin_task.gt_uniq != NULL) + taskqgroup_detach(tqg, &ctx->ifc_admin_task); + if (ctx->ifc_vflr_task.gt_uniq != NULL) + taskqgroup_detach(tqg, &ctx->ifc_vflr_task); + + IFDI_DETACH(ctx); + if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { + pci_release_msi(dev); + } + if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { + iflib_irq_free(ctx, &ctx->ifc_legacy_irq); + } + if (ctx->ifc_msix_mem != NULL) { + bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, + ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); + ctx->ifc_msix_mem = NULL; + } + + bus_generic_detach(dev); + if_free(ifp); + + iflib_tx_structures_free(ctx); + iflib_rx_structures_free(ctx); + return (0); +} + + +int +iflib_device_detach(device_t dev) +{ + if_ctx_t ctx = device_get_softc(dev); + + return (iflib_device_deregister(ctx)); +} + +int +iflib_device_suspend(device_t dev) +{ + if_ctx_t ctx = device_get_softc(dev); + + CTX_LOCK(ctx); + IFDI_SUSPEND(ctx); + CTX_UNLOCK(ctx); + + return bus_generic_suspend(dev); +} +int +iflib_device_shutdown(device_t dev) +{ + if_ctx_t ctx = device_get_softc(dev); + + CTX_LOCK(ctx); + IFDI_SHUTDOWN(ctx); + CTX_UNLOCK(ctx); + + return bus_generic_suspend(dev); +} + + +int +iflib_device_resume(device_t dev) +{ + if_ctx_t ctx = device_get_softc(dev); + iflib_txq_t txq = ctx->ifc_txqs; + + CTX_LOCK(ctx); + IFDI_RESUME(ctx); + iflib_init_locked(ctx); + CTX_UNLOCK(ctx); + for (int i = 0; i < NTXQSETS(ctx); i++, txq++) + iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); + + return (bus_generic_resume(dev)); +} + +int +iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) +{ + int error; + if_ctx_t ctx = device_get_softc(dev); + + CTX_LOCK(ctx); + error = IFDI_IOV_INIT(ctx, num_vfs, params); + CTX_UNLOCK(ctx); + + return (error); +} + +void +iflib_device_iov_uninit(device_t dev) +{ + if_ctx_t ctx = device_get_softc(dev); + + CTX_LOCK(ctx); + IFDI_IOV_UNINIT(ctx); + CTX_UNLOCK(ctx); +} + +int +iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) +{ + int error; + if_ctx_t ctx = device_get_softc(dev); + + CTX_LOCK(ctx); + error = IFDI_IOV_VF_ADD(ctx, vfnum, params); + CTX_UNLOCK(ctx); + + return (error); +} + +/********************************************************************* + * + * MODULE FUNCTION DEFINITIONS + * + **********************************************************************/ + +/* + * - Start a fast taskqueue thread for each core + * - Start a taskqueue for control operations + */ +static int +iflib_module_init(void) +{ + return (0); +} + +static int +iflib_module_event_handler(module_t mod, int what, void *arg) +{ + int err; + + switch (what) { + case MOD_LOAD: + if ((err = iflib_module_init()) != 0) + return (err); + break; + case MOD_UNLOAD: + return (EBUSY); + default: + return (EOPNOTSUPP); + } + + return (0); +} + +/********************************************************************* + * + * PUBLIC FUNCTION DEFINITIONS + * ordered as in iflib.h + * + **********************************************************************/ + + +static void +_iflib_assert(if_shared_ctx_t sctx) +{ + MPASS(sctx->isc_tx_maxsize); + MPASS(sctx->isc_tx_maxsegsize); + + MPASS(sctx->isc_rx_maxsize); + MPASS(sctx->isc_rx_nsegments); + MPASS(sctx->isc_rx_maxsegsize); + + + MPASS(sctx->isc_txrx->ift_txd_encap); + MPASS(sctx->isc_txrx->ift_txd_flush); + MPASS(sctx->isc_txrx->ift_txd_credits_update); + MPASS(sctx->isc_txrx->ift_rxd_available); + MPASS(sctx->isc_txrx->ift_rxd_pkt_get); + MPASS(sctx->isc_txrx->ift_rxd_refill); + MPASS(sctx->isc_txrx->ift_rxd_flush); + MPASS(sctx->isc_nrxd); +} + +static int +iflib_register(if_ctx_t ctx) +{ + if_shared_ctx_t sctx = ctx->ifc_sctx; + driver_t *driver = sctx->isc_driver; + device_t dev = ctx->ifc_dev; + if_t ifp; + + _iflib_assert(sctx); + + CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); + MPASS(ctx->ifc_flags == 0); + + ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); + if (ifp == NULL) { + device_printf(dev, "can not allocate ifnet structure\n"); + return (ENOMEM); + } + + /* + * Initialize our context's device specific methods + */ + kobj_init((kobj_t) ctx, (kobj_class_t) driver); + kobj_class_compile((kobj_class_t) driver); + driver->refs++; + + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + if_setsoftc(ifp, ctx); + if_setdev(ifp, dev); + if_setinitfn(ifp, iflib_if_init); + if_setioctlfn(ifp, iflib_if_ioctl); + if_settransmitfn(ifp, iflib_if_transmit); + if_setqflushfn(ifp, iflib_if_qflush); + if_setgetcounterfn(ifp, iflib_if_get_counter); + if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); + + if_setcapabilities(ifp, 0); + if_setcapenable(ifp, 0); + + ctx->ifc_vlan_attach_event = + EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, + EVENTHANDLER_PRI_FIRST); + ctx->ifc_vlan_detach_event = + EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, + EVENTHANDLER_PRI_FIRST); + + ifmedia_init(&ctx->ifc_media, IFM_IMASK, + iflib_media_change, iflib_media_status); + + return (0); +} + + +static int +iflib_queues_alloc(if_ctx_t ctx) +{ + if_shared_ctx_t sctx = ctx->ifc_sctx; + device_t dev = ctx->ifc_dev; + int nrxqsets = ctx->ifc_softc_ctx.isc_nrxqsets; + int ntxqsets = ctx->ifc_softc_ctx.isc_ntxqsets; + iflib_txq_t txq; + iflib_rxq_t rxq; + iflib_fl_t fl = NULL; + int i, j, err, txconf, rxconf, fl_ifdi_offset; + iflib_dma_info_t ifdip; + uint32_t *rxqsizes = sctx->isc_rxqsizes; + uint32_t *txqsizes = sctx->isc_txqsizes; + uint8_t nrxqs = sctx->isc_nrxqs; + uint8_t ntxqs = sctx->isc_ntxqs; + int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; + caddr_t *vaddrs; + uint64_t *paddrs; + struct ifmp_ring **brscp; + int nbuf_rings = 1; /* XXX determine dynamically */ + + KASSERT(ntxqs > 0, ("number of queues must be at least 1")); + KASSERT(nrxqs > 0, ("number of queues must be at least 1")); + +/* Allocate the TX ring struct memory */ + if (!(txq = + (iflib_txq_t) malloc(sizeof(struct iflib_txq) * + ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { + device_printf(dev, "Unable to allocate TX ring memory\n"); + err = ENOMEM; + goto fail; + } + + /* Now allocate the RX */ + if (!(rxq = + (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * + nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { + device_printf(dev, "Unable to allocate RX ring memory\n"); + err = ENOMEM; + goto rx_fail; + } + if (!(brscp = malloc(sizeof(void *) * nbuf_rings * nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { + device_printf(dev, "Unable to buf_ring_sc * memory\n"); + err = ENOMEM; + goto rx_fail; + } + + ctx->ifc_txqs = txq; + ctx->ifc_rxqs = rxq; + + /* + * XXX handle allocation failure + */ + for (txconf = i = 0; i < ntxqsets; i++, txconf++, txq++) { + /* Set up some basics */ + + if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { + device_printf(dev, "failed to allocate iflib_dma_info\n"); + err = ENOMEM; + goto fail; + } + txq->ift_ifdi = ifdip; + for (j = 0; j < ntxqs; j++, ifdip++) { + if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { + device_printf(dev, "Unable to allocate Descriptor memory\n"); + err = ENOMEM; + goto err_tx_desc; + } + bzero((void *)ifdip->idi_vaddr, txqsizes[j]); + } + txq->ift_ctx = ctx; + txq->ift_id = i; + /* XXX fix this */ + txq->ift_timer.c_cpu = i % mp_ncpus; + txq->ift_db_check.c_cpu = i % mp_ncpus; + txq->ift_nbr = nbuf_rings; + + if (iflib_txsd_alloc(txq)) { + device_printf(dev, "Critical Failure setting up TX buffers\n"); + err = ENOMEM; + goto err_tx_desc; + } + + /* Initialize the TX lock */ + snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", + device_get_nameunit(dev), txq->ift_id); + mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); + callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); + callout_init_mtx(&txq->ift_db_check, &txq->ift_mtx, 0); + + snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", + device_get_nameunit(dev), txq->ift_id); + TXDB_LOCK_INIT(txq); + + txq->ift_br = brscp + i*nbuf_rings; + for (j = 0; j < nbuf_rings; j++) { + err = ifmp_ring_alloc(&txq->ift_br[j], 2048, txq, iflib_txq_drain, + iflib_txq_can_drain, M_IFLIB, M_WAITOK); + if (err) { + /* XXX free any allocated rings */ + device_printf(dev, "Unable to allocate buf_ring\n"); + goto fail; + } + } + } + + for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { + /* Set up some basics */ + + if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { + device_printf(dev, "failed to allocate iflib_dma_info\n"); + err = ENOMEM; + goto fail; + } + + rxq->ifr_ifdi = ifdip; + for (j = 0; j < nrxqs; j++, ifdip++) { + if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { + device_printf(dev, "Unable to allocate Descriptor memory\n"); + err = ENOMEM; + goto err_tx_desc; + } + bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); + } + rxq->ifr_ctx = ctx; + rxq->ifr_id = i; + if (sctx->isc_flags & IFLIB_HAS_CQ) { + fl_ifdi_offset = 1; + } else { + fl_ifdi_offset = 0; + } + rxq->ifr_nfl = nfree_lists; + if (!(fl = + (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { + device_printf(dev, "Unable to allocate free list memory\n"); + err = ENOMEM; + goto fail; + } + rxq->ifr_fl = fl; + for (j = 0; j < nfree_lists; j++) { + rxq->ifr_fl[j].ifl_rxq = rxq; + rxq->ifr_fl[j].ifl_id = j; + rxq->ifr_fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + fl_ifdi_offset]; + } + /* Allocate receive buffers for the ring*/ + if (iflib_rxsd_alloc(rxq)) { + device_printf(dev, + "Critical Failure setting up receive buffers\n"); + err = ENOMEM; + goto err_rx_desc; + } + } + + /* TXQs */ + vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); + paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); + for (i = 0; i < ntxqsets; i++) { + iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; + + for (j = 0; j < ntxqs; j++, di++) { + vaddrs[i*ntxqs + j] = di->idi_vaddr; + paddrs[i*ntxqs + j] = di->idi_paddr; + } + } + if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { + device_printf(ctx->ifc_dev, "device queue allocation failed\n"); + iflib_tx_structures_free(ctx); + free(vaddrs, M_IFLIB); + free(paddrs, M_IFLIB); + goto err_rx_desc; + } + free(vaddrs, M_IFLIB); + free(paddrs, M_IFLIB); + + /* RXQs */ + vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); + paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); + for (i = 0; i < nrxqsets; i++) { + iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; + + for (j = 0; j < nrxqs; j++, di++) { + vaddrs[i*nrxqs + j] = di->idi_vaddr; + paddrs[i*nrxqs + j] = di->idi_paddr; + } + } + if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { + device_printf(ctx->ifc_dev, "device queue allocation failed\n"); + iflib_tx_structures_free(ctx); + free(vaddrs, M_IFLIB); + free(paddrs, M_IFLIB); + goto err_rx_desc; + } + free(vaddrs, M_IFLIB); + free(paddrs, M_IFLIB); + + return (0); + +/* XXX handle allocation failure changes */ +err_rx_desc: +err_tx_desc: + if (ctx->ifc_rxqs != NULL) + free(ctx->ifc_rxqs, M_IFLIB); + ctx->ifc_rxqs = NULL; +rx_fail: + if (ctx->ifc_txqs != NULL) + free(ctx->ifc_txqs, M_IFLIB); + ctx->ifc_txqs = NULL; +fail: + return (err); +} + +static int +iflib_tx_structures_setup(if_ctx_t ctx) +{ + iflib_txq_t txq = ctx->ifc_txqs; + int i; + + for (i = 0; i < NTXQSETS(ctx); i++, txq++) + iflib_txq_setup(txq); + + return (0); +} + +static void +iflib_tx_structures_free(if_ctx_t ctx) +{ + iflib_txq_t txq = ctx->ifc_txqs; + int i, j; + + for (i = 0; i < NTXQSETS(ctx); i++, txq++) { + iflib_txq_destroy(txq); + for (j = 0; j < ctx->ifc_nhwtxqs; j++) + iflib_dma_free(&txq->ift_ifdi[j]); + } + free(ctx->ifc_txqs, M_IFLIB); + ctx->ifc_txqs = NULL; + IFDI_QUEUES_FREE(ctx); +} + +/********************************************************************* + * + * Initialize all receive rings. + * + **********************************************************************/ +static int +iflib_rx_structures_setup(if_ctx_t ctx) +{ + iflib_rxq_t rxq = ctx->ifc_rxqs; + int q; +#if defined(INET6) || defined(INET) + int i, err; +#endif + + for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { +#if defined(INET6) || defined(INET) + tcp_lro_free(&rxq->ifr_lc); + if ((err = tcp_lro_init(&rxq->ifr_lc)) != 0) { + device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); + goto fail; + } + rxq->ifr_lro_enabled = TRUE; + rxq->ifr_lc.ifp = ctx->ifc_ifp; +#endif + IFDI_RXQ_SETUP(ctx, rxq->ifr_id); + } + return (0); +#if defined(INET6) || defined(INET) +fail: + /* + * Free RX software descriptors allocated so far, we will only handle + * the rings that completed, the failing case will have + * cleaned up for itself. 'q' failed, so its the terminus. + */ + rxq = ctx->ifc_rxqs; + for (i = 0; i < q; ++i, rxq++) { + iflib_rx_sds_free(rxq); + rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; + } + return (err); +#endif +} + +/********************************************************************* + * + * Free all receive rings. + * + **********************************************************************/ +static void +iflib_rx_structures_free(if_ctx_t ctx) +{ + iflib_rxq_t rxq = ctx->ifc_rxqs; + + for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, rxq++) { + iflib_rx_sds_free(rxq); + } +} + +static int +iflib_qset_structures_setup(if_ctx_t ctx) +{ + int err; + + if ((err = iflib_tx_structures_setup(ctx)) != 0) + return (err); + + if ((err = iflib_rx_structures_setup(ctx)) != 0) { + device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); + iflib_tx_structures_free(ctx); + iflib_rx_structures_free(ctx); + } + return (err); +} + +int +iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, + driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) +{ + + return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); +} + +static void +find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) +{ + int i, cpuid; + + CPU_COPY(&ctx->ifc_cpus, cpus); + /* clear up to the qid'th bit */ + for (i = 0; i < qid; i++) { + cpuid = CPU_FFS(cpus); + CPU_CLR(cpuid, cpus); + } +} + +int +iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, + iflib_intr_type_t type, driver_filter_t *filter, + void *filter_arg, int qid, char *name) +{ + struct grouptask *gtask; + struct taskqgroup *tqg; + iflib_filter_info_t info; + cpuset_t cpus; + task_fn_t *fn; + int tqrid, err; + void *q; + + info = &ctx->ifc_filter_info; + + switch (type) { + /* XXX merge tx/rx for netmap? */ + case IFLIB_INTR_TX: + q = &ctx->ifc_txqs[qid]; + info = &ctx->ifc_txqs[qid].ift_filter_info; + gtask = &ctx->ifc_txqs[qid].ift_task; + tqg = qgroup_if_io_tqg; + tqrid = irq->ii_rid; + fn = _task_fn_tx; + break; + case IFLIB_INTR_RX: + q = &ctx->ifc_rxqs[qid]; + info = &ctx->ifc_rxqs[qid].ifr_filter_info; + gtask = &ctx->ifc_rxqs[qid].ifr_task; + tqg = qgroup_if_io_tqg; + tqrid = irq->ii_rid; + fn = _task_fn_rx; + break; + case IFLIB_INTR_ADMIN: + q = ctx; + info = &ctx->ifc_filter_info; + gtask = &ctx->ifc_admin_task; + tqg = qgroup_if_config_tqg; + tqrid = -1; + fn = _task_fn_admin; + break; + default: + panic("unknown net intr type"); + } + GROUPTASK_INIT(gtask, 0, fn, q); + + info->ifi_filter = filter; + info->ifi_filter_arg = filter_arg; + info->ifi_task = gtask; + + /* XXX query cpu that rid belongs to */ + + err = _iflib_irq_alloc(ctx, irq, rid, iflib_fast_intr, NULL, info, name); + if (err != 0) + return (err); + if (tqrid != -1) { + find_nth(ctx, &cpus, qid); + taskqgroup_attach_cpu(tqg, gtask, q, CPU_FFS(&cpus), irq->ii_rid, name); + } else + taskqgroup_attach(tqg, gtask, q, tqrid, name); + + + return (0); +} + +void +iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name) +{ + struct grouptask *gtask; + struct taskqgroup *tqg; + task_fn_t *fn; + void *q; + + switch (type) { + case IFLIB_INTR_TX: + q = &ctx->ifc_txqs[qid]; + gtask = &ctx->ifc_txqs[qid].ift_task; + tqg = qgroup_if_io_tqg; + fn = _task_fn_tx; + break; + case IFLIB_INTR_RX: + q = &ctx->ifc_rxqs[qid]; + gtask = &ctx->ifc_rxqs[qid].ifr_task; + tqg = qgroup_if_io_tqg; + fn = _task_fn_rx; + break; + case IFLIB_INTR_ADMIN: + q = ctx; + gtask = &ctx->ifc_admin_task; + tqg = qgroup_if_config_tqg; + rid = -1; + fn = _task_fn_admin; + break; + case IFLIB_INTR_IOV: + q = ctx; + gtask = &ctx->ifc_vflr_task; + tqg = qgroup_if_config_tqg; + rid = -1; + fn = _task_fn_iov; + break; + default: + panic("unknown net intr type"); + } + GROUPTASK_INIT(gtask, 0, fn, q); + taskqgroup_attach(tqg, gtask, q, rid, name); +} + +void +iflib_irq_free(if_ctx_t ctx, if_irq_t irq) +{ + if (irq->ii_tag) + bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); + + if (irq->ii_res) + bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); +} + +static int +iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) +{ + iflib_txq_t txq = ctx->ifc_txqs; + iflib_rxq_t rxq = ctx->ifc_rxqs; + if_irq_t irq = &ctx->ifc_legacy_irq; + iflib_filter_info_t info; + struct grouptask *gtask; + struct taskqgroup *tqg; + task_fn_t *fn; + int tqrid; + void *q; + int err; + + q = &ctx->ifc_rxqs[0]; + info = &rxq[0].ifr_filter_info; + gtask = &rxq[0].ifr_task; + tqg = qgroup_if_io_tqg; + tqrid = irq->ii_rid = *rid; + fn = _task_fn_rx; + + ctx->ifc_flags |= IFC_LEGACY; + info->ifi_filter = filter; + info->ifi_filter_arg = filter_arg; + info->ifi_task = gtask; + + /* We allocate a single interrupt resource */ + if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr, NULL, info, name)) != 0) + return (err); + GROUPTASK_INIT(gtask, 0, fn, q); + taskqgroup_attach(tqg, gtask, q, tqrid, name); + + GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); + taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); + GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); + taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin/link"); + + return (0); +} + +void +iflib_led_create(if_ctx_t ctx) +{ + + ctx->ifc_led_dev = led_create(iflib_led_func, ctx, + device_get_nameunit(ctx->ifc_dev)); +} + +void +iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) +{ + + GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); +} + +void +iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) +{ + + GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); +} + +void +iflib_admin_intr_deferred(if_ctx_t ctx) +{ + + GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); +} + +void +iflib_iov_intr_deferred(if_ctx_t ctx) +{ + + GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); +} + +void +iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) +{ + + taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); +} + +void +iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, task_fn_t *fn, + char *name) +{ + + GROUPTASK_INIT(gtask, 0, fn, ctx); + taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); +} + +void +iflib_link_state_change(if_ctx_t ctx, int link_state) +{ + if_t ifp = ctx->ifc_ifp; + iflib_txq_t txq = ctx->ifc_txqs; + +#if 0 + if_setbaudrate(ifp, baudrate); +#endif + /* If link down, disable watchdog */ + if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { + for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) + txq->ift_qstatus = IFLIB_QUEUE_IDLE; + } + ctx->ifc_link_state = link_state; + if_link_state_change(ifp, link_state); +} + +static int +iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) +{ + int credits; + + if (ctx->isc_txd_credits_update == NULL) + return (0); + + if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, true)) == 0) + return (0); + + txq->ift_processed += credits; + txq->ift_cidx_processed += credits; + + if (txq->ift_cidx_processed >= txq->ift_size) + txq->ift_cidx_processed -= txq->ift_size; + return (credits); +} + +static int +iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx) +{ + + return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx)); +} + +void +iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, + const char *description, if_int_delay_info_t info, + int offset, int value) +{ + info->iidi_ctx = ctx; + info->iidi_offset = offset; + info->iidi_value = value; + SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), + OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, + info, 0, iflib_sysctl_int_delay, "I", description); +} + +struct mtx * +iflib_ctx_lock_get(if_ctx_t ctx) +{ + + return (&ctx->ifc_mtx); +} + +static int +iflib_msix_init(if_ctx_t ctx) +{ + device_t dev = ctx->ifc_dev; + if_shared_ctx_t sctx = ctx->ifc_sctx; + if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; + int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; + int iflib_num_tx_queues, iflib_num_rx_queues; + int err, admincnt, bar; + + iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; + iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; + bar = ctx->ifc_softc_ctx.isc_msix_bar; + admincnt = sctx->isc_admin_intrcnt; + /* Override by tuneable */ + if (enable_msix == 0) + goto msi; + + /* + ** When used in a virtualized environment + ** PCI BUSMASTER capability may not be set + ** so explicity set it here and rewrite + ** the ENABLE in the MSIX control register + ** at this point to cause the host to + ** successfully initialize us. + */ + { + uint16_t pci_cmd_word; + int msix_ctrl, rid; + + rid = 0; + pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); + pci_cmd_word |= PCIM_CMD_BUSMASTEREN; + pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2); + pci_find_cap(dev, PCIY_MSIX, &rid); + rid += PCIR_MSIX_CTRL; + msix_ctrl = pci_read_config(dev, rid, 2); + msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; + pci_write_config(dev, rid, msix_ctrl, 2); + } + + /* + * bar == -1 => "trust me I know what I'm doing" + * https://www.youtube.com/watch?v=nnwWKkNau4I + * Some drivers are for hardware that is so shoddily + * documented that no one knows which bars are which + * so the developer has to map all bars. This hack + * allows shoddy garbage to use msix in this framework. + */ + if (bar != -1) { + ctx->ifc_msix_mem = bus_alloc_resource_any(dev, + SYS_RES_MEMORY, &bar, RF_ACTIVE); + if (ctx->ifc_msix_mem == NULL) { + /* May not be enabled */ + device_printf(dev, "Unable to map MSIX table \n"); + goto msi; + } + } + /* First try MSI/X */ + if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ + device_printf(dev, "System has MSIX disabled \n"); + bus_release_resource(dev, SYS_RES_MEMORY, + bar, ctx->ifc_msix_mem); + ctx->ifc_msix_mem = NULL; + goto msi; + } +#if IFLIB_DEBUG + /* use only 1 qset in debug mode */ + queuemsgs = min(msgs - admincnt, 1); +#else + queuemsgs = msgs - admincnt; +#endif + if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { +#ifdef RSS + queues = imin(queuemsgs, rss_getnumbuckets()); +#else + queues = queuemsgs; +#endif + queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); + device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", + CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); + } else { + device_printf(dev, "Unable to fetch CPU list\n"); + /* Figure out a reasonable auto config value */ + queues = min(queuemsgs, mp_ncpus); + } +#ifdef RSS + /* If we're doing RSS, clamp at the number of RSS buckets */ + if (queues > rss_getnumbuckets()) + queues = rss_getnumbuckets(); +#endif + if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queues) + queues = rx_queues = iflib_num_rx_queues; + else + rx_queues = queues; + if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) + tx_queues = iflib_num_tx_queues; + else + tx_queues = queues; + + device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); + + vectors = queues + admincnt; + if ((err = pci_alloc_msix(dev, &vectors)) == 0) { + device_printf(dev, + "Using MSIX interrupts with %d vectors\n", vectors); + scctx->isc_vectors = vectors; + scctx->isc_nrxqsets = rx_queues; + scctx->isc_ntxqsets = tx_queues; + scctx->isc_intr = IFLIB_INTR_MSIX; + return (vectors); + } else { + device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); + } +msi: + vectors = pci_msi_count(dev); + scctx->isc_nrxqsets = 1; + scctx->isc_ntxqsets = 1; + scctx->isc_vectors = vectors; + if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { + device_printf(dev,"Using an MSI interrupt\n"); + scctx->isc_intr = IFLIB_INTR_MSI; + } else { + device_printf(dev,"Using a Legacy interrupt\n"); + scctx->isc_intr = IFLIB_INTR_LEGACY; + } + + return (vectors); +} + +char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; + +static int +mp_ring_state_handler(SYSCTL_HANDLER_ARGS) +{ + int rc; + uint16_t *state = ((uint16_t *)oidp->oid_arg1); + struct sbuf *sb; + char *ring_state = "UNKNOWN"; + + /* XXX needed ? */ + rc = sysctl_wire_old_buffer(req, 0); + MPASS(rc == 0); + if (rc != 0) + return (rc); + sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); + MPASS(sb != NULL); + if (sb == NULL) + return (ENOMEM); + if (state[3] <= 3) + ring_state = ring_states[state[3]]; + + sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", + state[0], state[1], state[2], ring_state); + rc = sbuf_finish(sb); + sbuf_delete(sb); + return(rc); +} + + + +#define NAME_BUFLEN 32 +static void +iflib_add_device_sysctl_pre(if_ctx_t ctx) +{ + device_t dev = iflib_get_dev(ctx); + struct sysctl_oid_list *child, *oid_list; + struct sysctl_ctx_list *ctx_list; + struct sysctl_oid *node; + + ctx_list = device_get_sysctl_ctx(dev); + child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); + ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", + CTLFLAG_RD, NULL, "IFLIB fields"); + oid_list = SYSCTL_CHILDREN(node); + + SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", + CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, + "# of txqs to use, 0 => use default #"); + SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", + CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, + "# of txqs to use, 0 => use default #"); + SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxds", + CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxds, 0, + "# of tx descriptors to use, 0 => use default #"); + SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxds", + CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxds, 0, + "# of rx descriptors to use, 0 => use default #"); + +} + +static void +iflib_add_device_sysctl_post(if_ctx_t ctx) +{ + if_shared_ctx_t sctx = ctx->ifc_sctx; + if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; + device_t dev = iflib_get_dev(ctx); + struct sysctl_oid_list *child; + struct sysctl_ctx_list *ctx_list; + iflib_fl_t fl; + iflib_txq_t txq; + iflib_rxq_t rxq; + int i, j; + char namebuf[NAME_BUFLEN]; + char *qfmt; + struct sysctl_oid *queue_node, *fl_node, *node; + struct sysctl_oid_list *queue_list, *fl_list; + ctx_list = device_get_sysctl_ctx(dev); + + node = ctx->ifc_sysctl_node; + child = SYSCTL_CHILDREN(node); + + if (scctx->isc_ntxqsets > 100) + qfmt = "txq%03d"; + else if (scctx->isc_ntxqsets > 10) + qfmt = "txq%02d"; + else + qfmt = "txq%d"; + for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { + snprintf(namebuf, NAME_BUFLEN, qfmt, i); + queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, + CTLFLAG_RD, NULL, "Queue Name"); + queue_list = SYSCTL_CHILDREN(queue_node); +#if MEMORY_LOGGING + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", + CTLFLAG_RD, + &txq->ift_dequeued, "total mbufs freed"); + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", + CTLFLAG_RD, + &txq->ift_enqueued, "total mbufs enqueued"); +#endif + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", + CTLFLAG_RD, + &txq->ift_mbuf_defrag, "# of times m_defrag was called"); + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", + CTLFLAG_RD, + &txq->ift_pullups, "# of times m_pullup was called"); + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", + CTLFLAG_RD, + &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", + CTLFLAG_RD, + &txq->ift_mbuf_defrag_failed, "# of times no descriptors were available"); + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", + CTLFLAG_RD, + &txq->ift_map_failed, "# of times dma map failed"); + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", + CTLFLAG_RD, + &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", + CTLFLAG_RD, + &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); + SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", + CTLFLAG_RD, + &txq->ift_pidx, 1, "Producer Index"); + SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", + CTLFLAG_RD, + &txq->ift_cidx, 1, "Consumer Index"); + SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", + CTLFLAG_RD, + &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); + SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", + CTLFLAG_RD, + &txq->ift_in_use, 1, "descriptors in use"); + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", + CTLFLAG_RD, + &txq->ift_processed, "descriptors procesed for clean"); + SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", + CTLFLAG_RD, + &txq->ift_cleaned, "total cleaned"); + SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", + CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br[0]->state), + 0, mp_ring_state_handler, "A", "soft ring state"); + SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", + CTLFLAG_RD, &txq->ift_br[0]->enqueues, + "# of enqueues to the mp_ring for this queue"); + SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", + CTLFLAG_RD, &txq->ift_br[0]->drops, + "# of drops in the mp_ring for this queue"); + SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", + CTLFLAG_RD, &txq->ift_br[0]->starts, + "# of normal consumer starts in the mp_ring for this queue"); + SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", + CTLFLAG_RD, &txq->ift_br[0]->stalls, + "# of consumer stalls in the mp_ring for this queue"); + SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", + CTLFLAG_RD, &txq->ift_br[0]->restarts, + "# of consumer restarts in the mp_ring for this queue"); + SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", + CTLFLAG_RD, &txq->ift_br[0]->abdications, + "# of consumer abdications in the mp_ring for this queue"); + + } + + if (scctx->isc_nrxqsets > 100) + qfmt = "rxq%03d"; + else if (scctx->isc_nrxqsets > 10) + qfmt = "rxq%02d"; + else + qfmt = "rxq%d"; + for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { + snprintf(namebuf, NAME_BUFLEN, qfmt, i); + queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, + CTLFLAG_RD, NULL, "Queue Name"); + queue_list = SYSCTL_CHILDREN(queue_node); + if (sctx->isc_flags & IFLIB_HAS_CQ) { + SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", + CTLFLAG_RD, + &rxq->ifr_cq_pidx, 1, "Producer Index"); + SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", + CTLFLAG_RD, + &rxq->ifr_cq_cidx, 1, "Consumer Index"); + } + for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { + snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); + fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, + CTLFLAG_RD, NULL, "freelist Name"); + fl_list = SYSCTL_CHILDREN(fl_node); + SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", + CTLFLAG_RD, + &fl->ifl_pidx, 1, "Producer Index"); + SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", + CTLFLAG_RD, + &fl->ifl_cidx, 1, "Consumer Index"); + SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", + CTLFLAG_RD, + &fl->ifl_credits, 1, "credits available"); +#if MEMORY_LOGGING + SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", + CTLFLAG_RD, + &fl->ifl_m_enqueued, "mbufs allocated"); + SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", + CTLFLAG_RD, + &fl->ifl_m_dequeued, "mbufs freed"); + SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", + CTLFLAG_RD, + &fl->ifl_cl_enqueued, "clusters allocated"); + SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", + CTLFLAG_RD, + &fl->ifl_cl_dequeued, "clusters freed"); +#endif + + } + } + +} diff --git a/sys/net/iflib.h b/sys/net/iflib.h new file mode 100644 index 0000000..c301b91 --- /dev/null +++ b/sys/net/iflib.h @@ -0,0 +1,338 @@ +/*- + * Copyright (c) 2014-2015, Matthew Macy (mmacy@nextbsd.org) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Neither the name of Matthew Macy nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ +#ifndef __IFLIB_H_ +#define __IFLIB_H_ + +#include <sys/kobj.h> +#include <sys/bus.h> +#include <sys/cpuset.h> +#include <machine/bus.h> +#include <sys/bus_dma.h> +#include <sys/nv.h> + + +/* + * Most cards can handle much larger TSO requests + * but the FreeBSD TCP stack will break on larger + * values + */ +#define FREEBSD_TSO_SIZE_MAX 65518 + + +struct iflib_ctx; +typedef struct iflib_ctx *if_ctx_t; +struct if_shared_ctx; +typedef struct if_shared_ctx *if_shared_ctx_t; +struct if_int_delay_info; +typedef struct if_int_delay_info *if_int_delay_info_t; + +/* + * File organization: + * - public structures + * - iflib accessors + * - iflib utility functions + * - iflib core functions + */ + +typedef struct if_rxd_frag { + uint8_t irf_flid; + uint16_t irf_idx; +} *if_rxd_frag_t; + +typedef struct if_rxd_info { + /* set by iflib */ + uint16_t iri_qsidx; /* qset index */ + uint16_t iri_vtag; /* vlan tag - if flag set */ + uint16_t iri_len; /* packet length */ + uint16_t iri_cidx; /* consumer index of cq */ + struct ifnet *iri_ifp; /* some drivers >1 interface per softc */ + + /* updated by driver */ + uint16_t iri_flags; /* mbuf flags for packet */ + uint32_t iri_flowid; /* RSS hash for packet */ + uint32_t iri_csum_flags; /* m_pkthdr csum flags */ + uint32_t iri_csum_data; /* m_pkthdr csum data */ + uint8_t iri_nfrags; /* number of fragments in packet */ + uint8_t iri_rsstype; /* RSS hash type */ + uint8_t iri_pad; /* any padding in the received data */ + if_rxd_frag_t iri_frags; +} *if_rxd_info_t; + +#define IPI_TX_INTR 0x1 /* send an interrupt when this packet is sent */ +#define IPI_TX_IPV4 0x2 /* ethertype IPv4 */ +#define IPI_TX_IPV6 0x4 /* ethertype IPv6 */ + +typedef struct if_pkt_info { + uint32_t ipi_len; /* packet length */ + bus_dma_segment_t *ipi_segs; /* physical addresses */ + uint16_t ipi_qsidx; /* queue set index */ + uint16_t ipi_nsegs; /* number of segments */ + uint16_t ipi_ndescs; /* number of descriptors used by encap */ + uint16_t ipi_flags; /* iflib per-packet flags */ + uint32_t ipi_pidx; /* start pidx for encap */ + uint32_t ipi_new_pidx; /* next available pidx post-encap */ + /* offload handling */ + uint64_t ipi_csum_flags; /* packet checksum flags */ + uint16_t ipi_tso_segsz; /* tso segment size */ + uint16_t ipi_mflags; /* packet mbuf flags */ + uint16_t ipi_vtag; /* VLAN tag */ + uint16_t ipi_etype; /* ether header type */ + uint8_t ipi_ehdrlen; /* ether header length */ + uint8_t ipi_ip_hlen; /* ip header length */ + uint8_t ipi_tcp_hlen; /* tcp header length */ + uint8_t ipi_tcp_hflags; /* tcp header flags */ + uint8_t ipi_ipproto; /* ip protocol */ + /* implied padding */ + uint32_t ipi_tcp_seq; /* tcp seqno */ + uint32_t ipi_tcp_sum; /* tcp csum */ +} *if_pkt_info_t; + +typedef struct if_irq { + struct resource *ii_res; + int ii_rid; + void *ii_tag; +} *if_irq_t; + +struct if_int_delay_info { + if_ctx_t iidi_ctx; /* Back-pointer to the iflib ctx (softc) */ + int iidi_offset; /* Register offset to read/write */ + int iidi_value; /* Current value in usecs */ + struct sysctl_oid *iidi_oidp; + struct sysctl_req *iidi_req; +}; + +typedef enum { + IFLIB_INTR_LEGACY, + IFLIB_INTR_MSI, + IFLIB_INTR_MSIX +} iflib_intr_mode_t; + +/* + * This really belongs in pciio.h or some place more general + * but this is the only consumer for now. + */ +typedef struct pci_vendor_info { + uint32_t pvi_vendor_id; + uint32_t pvi_device_id; + uint32_t pvi_subvendor_id; + uint32_t pvi_subdevice_id; + uint32_t pvi_rev_id; + uint32_t pvi_class_mask; + caddr_t pvi_name; +} pci_vendor_info_t; + +#define PVID(vendor, devid, name) {vendor, devid, 0, 0, 0, 0, name} +#define PVID_OEM(vendor, devid, svid, sdevid, revid, name) {vendor, devid, svid, sdevid, revid, 0, name} +#define PVID_END {0, 0, 0, 0, 0, 0, NULL} + +typedef struct if_txrx { + int (*ift_txd_encap) (void *, if_pkt_info_t); + void (*ift_txd_flush) (void *, uint16_t, uint32_t); + int (*ift_txd_credits_update) (void *, uint16_t, uint32_t, bool); + + int (*ift_rxd_available) (void *, uint16_t qsidx, uint32_t pidx); + int (*ift_rxd_pkt_get) (void *, if_rxd_info_t ri); + void (*ift_rxd_refill) (void * , uint16_t qsidx, uint8_t flidx, uint32_t pidx, + uint64_t *paddrs, caddr_t *vaddrs, uint16_t count); + void (*ift_rxd_flush) (void *, uint16_t qsidx, uint8_t flidx, uint32_t pidx); + int (*ift_legacy_intr) (void *); +} *if_txrx_t; + +typedef struct if_softc_ctx { + int isc_vectors; + int isc_nrxqsets; + int isc_ntxqsets; + int isc_msix_bar; /* can be model specific - initialize in attach_pre */ + int isc_tx_nsegments; /* can be model specific - initialize in attach_pre */ + int isc_tx_tso_segments_max; + int isc_tx_tso_size_max; + int isc_tx_tso_segsize_max; + int isc_rss_table_size; + int isc_rss_table_mask; + + iflib_intr_mode_t isc_intr; + uint16_t isc_max_frame_size; /* set at init time by driver */ + pci_vendor_info_t isc_vendor_info; /* set by iflib prior to attach_pre */ +} *if_softc_ctx_t; + +/* + * Initialization values for device + */ +struct if_shared_ctx { + int isc_magic; + if_txrx_t isc_txrx; + driver_t *isc_driver; + int isc_ntxd; + int isc_nrxd; + int isc_nfl; + int isc_flags; + bus_size_t isc_q_align; + bus_size_t isc_tx_maxsize; + bus_size_t isc_tx_maxsegsize; + bus_size_t isc_rx_maxsize; + bus_size_t isc_rx_maxsegsize; + int isc_rx_nsegments; + int isc_rx_process_limit; + + + uint32_t isc_txqsizes[8]; + int isc_ntxqs; /* # of tx queues per tx qset - usually 1 */ + uint32_t isc_rxqsizes[8]; + int isc_nrxqs; /* # of rx queues per rx qset - intel 1, chelsio 2, broadcom 3 */ + int isc_admin_intrcnt; /* # of admin/link interrupts */ + + int isc_tx_reclaim_thresh; + + /* fields necessary for probe */ + pci_vendor_info_t *isc_vendor_info; + char *isc_driver_version; +/* optional function to transform the read values to match the table*/ + void (*isc_parse_devinfo) (uint16_t *device_id, uint16_t *subvendor_id, + uint16_t *subdevice_id, uint16_t *rev_id); +}; + +typedef struct iflib_dma_info { + bus_addr_t idi_paddr; + caddr_t idi_vaddr; + bus_dma_tag_t idi_tag; + bus_dmamap_t idi_map; + uint32_t idi_size; +} *iflib_dma_info_t; + +#define IFLIB_MAGIC 0xCAFEF00D + +typedef enum { + IFLIB_INTR_TX, + IFLIB_INTR_RX, + IFLIB_INTR_ADMIN, + IFLIB_INTR_IOV, +} iflib_intr_type_t; + +#ifndef ETH_ADDR_LEN +#define ETH_ADDR_LEN 6 +#endif + + +/* + * Interface has a separate command queue + */ +#define IFLIB_HAS_CQ 0x1 +/* + * Driver has already allocated vectors + */ +#define IFLIB_SKIP_MSIX 0x2 + +/* + * Interface is a virtual function + */ +#define IFLIB_IS_VF 0x4 + + +/* + * field accessors + */ +void *iflib_get_softc(if_ctx_t ctx); + +device_t iflib_get_dev(if_ctx_t ctx); + +if_t iflib_get_ifp(if_ctx_t ctx); + +struct ifmedia *iflib_get_media(if_ctx_t ctx); + +if_softc_ctx_t iflib_get_softc_ctx(if_ctx_t ctx); +if_shared_ctx_t iflib_get_sctx(if_ctx_t ctx); + +void iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]); + + + + +/* + * If the driver can plug cleanly in to newbus use these + */ +int iflib_device_probe(device_t); +int iflib_device_attach(device_t); +int iflib_device_detach(device_t); +int iflib_device_suspend(device_t); +int iflib_device_resume(device_t); +int iflib_device_shutdown(device_t); + + +int iflib_device_iov_init(device_t, uint16_t, const nvlist_t *); +void iflib_device_iov_uninit(device_t); +int iflib_device_iov_add_vf(device_t, uint16_t, const nvlist_t *); + +/* + * If the driver can't plug cleanly in to newbus + * use these + */ +int iflib_device_register(device_t dev, void *softc, if_shared_ctx_t sctx, if_ctx_t *ctxp); +int iflib_device_deregister(if_ctx_t); + + + +int iflib_irq_alloc(if_ctx_t, if_irq_t, int, driver_filter_t, void *filter_arg, driver_intr_t, void *arg, char *name); +int iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, + iflib_intr_type_t type, driver_filter_t *filter, + void *filter_arg, int qid, char *name); +void iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name); + +void iflib_irq_free(if_ctx_t ctx, if_irq_t irq); + +void iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name); + +void iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, + task_fn_t *fn, char *name); + + +void iflib_tx_intr_deferred(if_ctx_t ctx, int txqid); +void iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid); +void iflib_admin_intr_deferred(if_ctx_t ctx); +void iflib_iov_intr_deferred(if_ctx_t ctx); + + +void iflib_link_state_change(if_ctx_t ctx, int linkstate); + +int iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags); +void iflib_dma_free(iflib_dma_info_t dma); + +int iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count); + +void iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count); + + +struct mtx *iflib_ctx_lock_get(if_ctx_t); +struct mtx *iflib_qset_lock_get(if_ctx_t, uint16_t); + +void iflib_led_create(if_ctx_t ctx); + +void iflib_add_int_delay_sysctl(if_ctx_t, const char *, const char *, + if_int_delay_info_t, int, int); + +#endif /* __IFLIB_H_ */ diff --git a/sys/net/mp_ring.c b/sys/net/mp_ring.c new file mode 100644 index 0000000..1e17964 --- /dev/null +++ b/sys/net/mp_ring.c @@ -0,0 +1,544 @@ +/*- + * Copyright (c) 2014 Chelsio Communications, Inc. + * All rights reserved. + * Written by: Navdeep Parhar <np@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/types.h> +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/counter.h> +#include <sys/lock.h> +#include <sys/mutex.h> +#include <sys/malloc.h> +#include <machine/cpu.h> + +#if defined(__powerpc__) || defined(__mips__) +#define NO_64BIT_ATOMICS +#endif + +#if defined(__i386__) +#define atomic_cmpset_acq_64 atomic_cmpset_64 +#define atomic_cmpset_rel_64 atomic_cmpset_64 +#endif + +#include <net/mp_ring.h> + +union ring_state { + struct { + uint16_t pidx_head; + uint16_t pidx_tail; + uint16_t cidx; + uint16_t flags; + }; + uint64_t state; +}; + +enum { + IDLE = 0, /* consumer ran to completion, nothing more to do. */ + BUSY, /* consumer is running already, or will be shortly. */ + STALLED, /* consumer stopped due to lack of resources. */ + ABDICATED, /* consumer stopped even though there was work to be + done because it wants another thread to take over. */ +}; + +static inline uint16_t +space_available(struct ifmp_ring *r, union ring_state s) +{ + uint16_t x = r->size - 1; + + if (s.cidx == s.pidx_head) + return (x); + else if (s.cidx > s.pidx_head) + return (s.cidx - s.pidx_head - 1); + else + return (x - s.pidx_head + s.cidx); +} + +static inline uint16_t +increment_idx(struct ifmp_ring *r, uint16_t idx, uint16_t n) +{ + int x = r->size - idx; + + MPASS(x > 0); + return (x > n ? idx + n : n - x); +} + +/* Consumer is about to update the ring's state to s */ +static inline uint16_t +state_to_flags(union ring_state s, int abdicate) +{ + + if (s.cidx == s.pidx_tail) + return (IDLE); + else if (abdicate && s.pidx_tail != s.pidx_head) + return (ABDICATED); + + return (BUSY); +} + +#ifdef NO_64BIT_ATOMICS +static void +drain_ring_locked(struct ifmp_ring *r, union ring_state os, uint16_t prev, int budget) +{ + union ring_state ns; + int n, pending, total; + uint16_t cidx = os.cidx; + uint16_t pidx = os.pidx_tail; + + MPASS(os.flags == BUSY); + MPASS(cidx != pidx); + + if (prev == IDLE) + counter_u64_add(r->starts, 1); + pending = 0; + total = 0; + + while (cidx != pidx) { + + /* Items from cidx to pidx are available for consumption. */ + n = r->drain(r, cidx, pidx); + if (n == 0) { + os.state = ns.state = r->state; + ns.cidx = cidx; + ns.flags = STALLED; + r->state = ns.state; + if (prev != STALLED) + counter_u64_add(r->stalls, 1); + else if (total > 0) { + counter_u64_add(r->restarts, 1); + counter_u64_add(r->stalls, 1); + } + break; + } + cidx = increment_idx(r, cidx, n); + pending += n; + total += n; + + /* + * We update the cidx only if we've caught up with the pidx, the + * real cidx is getting too far ahead of the one visible to + * everyone else, or we have exceeded our budget. + */ + if (cidx != pidx && pending < 64 && total < budget) + continue; + + os.state = ns.state = r->state; + ns.cidx = cidx; + ns.flags = state_to_flags(ns, total >= budget); + r->state = ns.state; + + if (ns.flags == ABDICATED) + counter_u64_add(r->abdications, 1); + if (ns.flags != BUSY) { + /* Wrong loop exit if we're going to stall. */ + MPASS(ns.flags != STALLED); + if (prev == STALLED) { + MPASS(total > 0); + counter_u64_add(r->restarts, 1); + } + break; + } + + /* + * The acquire style atomic above guarantees visibility of items + * associated with any pidx change that we notice here. + */ + pidx = ns.pidx_tail; + pending = 0; + } +} +#else +/* + * Caller passes in a state, with a guarantee that there is work to do and that + * all items up to the pidx_tail in the state are visible. + */ +static void +drain_ring_lockless(struct ifmp_ring *r, union ring_state os, uint16_t prev, int budget) +{ + union ring_state ns; + int n, pending, total; + uint16_t cidx = os.cidx; + uint16_t pidx = os.pidx_tail; + + MPASS(os.flags == BUSY); + MPASS(cidx != pidx); + + if (prev == IDLE) + counter_u64_add(r->starts, 1); + pending = 0; + total = 0; + + while (cidx != pidx) { + + /* Items from cidx to pidx are available for consumption. */ + n = r->drain(r, cidx, pidx); + if (n == 0) { + critical_enter(); + do { + os.state = ns.state = r->state; + ns.cidx = cidx; + ns.flags = STALLED; + } while (atomic_cmpset_64(&r->state, os.state, + ns.state) == 0); + critical_exit(); + if (prev != STALLED) + counter_u64_add(r->stalls, 1); + else if (total > 0) { + counter_u64_add(r->restarts, 1); + counter_u64_add(r->stalls, 1); + } + break; + } + cidx = increment_idx(r, cidx, n); + pending += n; + total += n; + + /* + * We update the cidx only if we've caught up with the pidx, the + * real cidx is getting too far ahead of the one visible to + * everyone else, or we have exceeded our budget. + */ + if (cidx != pidx && pending < 64 && total < budget) + continue; + critical_enter(); + do { + os.state = ns.state = r->state; + ns.cidx = cidx; + ns.flags = state_to_flags(ns, total >= budget); + } while (atomic_cmpset_acq_64(&r->state, os.state, ns.state) == 0); + critical_exit(); + + if (ns.flags == ABDICATED) + counter_u64_add(r->abdications, 1); + if (ns.flags != BUSY) { + /* Wrong loop exit if we're going to stall. */ + MPASS(ns.flags != STALLED); + if (prev == STALLED) { + MPASS(total > 0); + counter_u64_add(r->restarts, 1); + } + break; + } + + /* + * The acquire style atomic above guarantees visibility of items + * associated with any pidx change that we notice here. + */ + pidx = ns.pidx_tail; + pending = 0; + } +} +#endif + +int +ifmp_ring_alloc(struct ifmp_ring **pr, int size, void *cookie, mp_ring_drain_t drain, + mp_ring_can_drain_t can_drain, struct malloc_type *mt, int flags) +{ + struct ifmp_ring *r; + + /* All idx are 16b so size can be 65536 at most */ + if (pr == NULL || size < 2 || size > 65536 || drain == NULL || + can_drain == NULL) + return (EINVAL); + *pr = NULL; + flags &= M_NOWAIT | M_WAITOK; + MPASS(flags != 0); + + r = malloc(__offsetof(struct ifmp_ring, items[size]), mt, flags | M_ZERO); + if (r == NULL) + return (ENOMEM); + r->size = size; + r->cookie = cookie; + r->mt = mt; + r->drain = drain; + r->can_drain = can_drain; + r->enqueues = counter_u64_alloc(flags); + r->drops = counter_u64_alloc(flags); + r->starts = counter_u64_alloc(flags); + r->stalls = counter_u64_alloc(flags); + r->restarts = counter_u64_alloc(flags); + r->abdications = counter_u64_alloc(flags); + if (r->enqueues == NULL || r->drops == NULL || r->starts == NULL || + r->stalls == NULL || r->restarts == NULL || + r->abdications == NULL) { + ifmp_ring_free(r); + return (ENOMEM); + } + + *pr = r; +#ifdef NO_64BIT_ATOMICS + mtx_init(&r->lock, "mp_ring lock", NULL, MTX_DEF); +#endif + return (0); +} + +void +ifmp_ring_free(struct ifmp_ring *r) +{ + + if (r == NULL) + return; + + if (r->enqueues != NULL) + counter_u64_free(r->enqueues); + if (r->drops != NULL) + counter_u64_free(r->drops); + if (r->starts != NULL) + counter_u64_free(r->starts); + if (r->stalls != NULL) + counter_u64_free(r->stalls); + if (r->restarts != NULL) + counter_u64_free(r->restarts); + if (r->abdications != NULL) + counter_u64_free(r->abdications); + + free(r, r->mt); +} + +/* + * Enqueue n items and maybe drain the ring for some time. + * + * Returns an errno. + */ +#ifdef NO_64BIT_ATOMICS +int +ifmp_ring_enqueue(struct ifmp_ring *r, void **items, int n, int budget) +{ + union ring_state os, ns; + uint16_t pidx_start, pidx_stop; + int i; + + MPASS(items != NULL); + MPASS(n > 0); + + mtx_lock(&r->lock); + /* + * Reserve room for the new items. Our reservation, if successful, is + * from 'pidx_start' to 'pidx_stop'. + */ + os.state = r->state; + if (n >= space_available(r, os)) { + counter_u64_add(r->drops, n); + MPASS(os.flags != IDLE); + if (os.flags == STALLED) + ifmp_ring_check_drainage(r, 0); + return (ENOBUFS); + } + ns.state = os.state; + ns.pidx_head = increment_idx(r, os.pidx_head, n); + r->state = ns.state; + pidx_start = os.pidx_head; + pidx_stop = ns.pidx_head; + + /* + * Wait for other producers who got in ahead of us to enqueue their + * items, one producer at a time. It is our turn when the ring's + * pidx_tail reaches the begining of our reservation (pidx_start). + */ + while (ns.pidx_tail != pidx_start) { + cpu_spinwait(); + ns.state = r->state; + } + + /* Now it is our turn to fill up the area we reserved earlier. */ + i = pidx_start; + do { + r->items[i] = *items++; + if (__predict_false(++i == r->size)) + i = 0; + } while (i != pidx_stop); + + /* + * Update the ring's pidx_tail. The release style atomic guarantees + * that the items are visible to any thread that sees the updated pidx. + */ + os.state = ns.state = r->state; + ns.pidx_tail = pidx_stop; + ns.flags = BUSY; + r->state = ns.state; + counter_u64_add(r->enqueues, n); + + /* + * Turn into a consumer if some other thread isn't active as a consumer + * already. + */ + if (os.flags != BUSY) + drain_ring_locked(r, ns, os.flags, budget); + + mtx_unlock(&r->lock); + return (0); +} + +#else +int +ifmp_ring_enqueue(struct ifmp_ring *r, void **items, int n, int budget) +{ + union ring_state os, ns; + uint16_t pidx_start, pidx_stop; + int i; + + MPASS(items != NULL); + MPASS(n > 0); + + /* + * Reserve room for the new items. Our reservation, if successful, is + * from 'pidx_start' to 'pidx_stop'. + */ + for (;;) { + os.state = r->state; + if (n >= space_available(r, os)) { + counter_u64_add(r->drops, n); + MPASS(os.flags != IDLE); + if (os.flags == STALLED) + ifmp_ring_check_drainage(r, 0); + return (ENOBUFS); + } + ns.state = os.state; + ns.pidx_head = increment_idx(r, os.pidx_head, n); + critical_enter(); + if (atomic_cmpset_64(&r->state, os.state, ns.state)) + break; + critical_exit(); + cpu_spinwait(); + } + pidx_start = os.pidx_head; + pidx_stop = ns.pidx_head; + + /* + * Wait for other producers who got in ahead of us to enqueue their + * items, one producer at a time. It is our turn when the ring's + * pidx_tail reaches the begining of our reservation (pidx_start). + */ + while (ns.pidx_tail != pidx_start) { + cpu_spinwait(); + ns.state = r->state; + } + + /* Now it is our turn to fill up the area we reserved earlier. */ + i = pidx_start; + do { + r->items[i] = *items++; + if (__predict_false(++i == r->size)) + i = 0; + } while (i != pidx_stop); + + /* + * Update the ring's pidx_tail. The release style atomic guarantees + * that the items are visible to any thread that sees the updated pidx. + */ + do { + os.state = ns.state = r->state; + ns.pidx_tail = pidx_stop; + ns.flags = BUSY; + } while (atomic_cmpset_rel_64(&r->state, os.state, ns.state) == 0); + critical_exit(); + counter_u64_add(r->enqueues, n); + + /* + * Turn into a consumer if some other thread isn't active as a consumer + * already. + */ + if (os.flags != BUSY) + drain_ring_lockless(r, ns, os.flags, budget); + + return (0); +} +#endif + +void +ifmp_ring_check_drainage(struct ifmp_ring *r, int budget) +{ + union ring_state os, ns; + + os.state = r->state; + if (os.flags != STALLED || os.pidx_head != os.pidx_tail || r->can_drain(r) == 0) + return; + + MPASS(os.cidx != os.pidx_tail); /* implied by STALLED */ + ns.state = os.state; + ns.flags = BUSY; + + +#ifdef NO_64BIT_ATOMICS + mtx_lock(&r->lock); + if (r->state != os.state) { + mtx_unlock(&r->lock); + return; + } + r->state = ns.state; + drain_ring_locked(r, ns, os.flags, budget); + mtx_unlock(&r->lock); +#else + /* + * The acquire style atomic guarantees visibility of items associated + * with the pidx that we read here. + */ + if (!atomic_cmpset_acq_64(&r->state, os.state, ns.state)) + return; + + + drain_ring_lockless(r, ns, os.flags, budget); +#endif +} + +void +ifmp_ring_reset_stats(struct ifmp_ring *r) +{ + + counter_u64_zero(r->enqueues); + counter_u64_zero(r->drops); + counter_u64_zero(r->starts); + counter_u64_zero(r->stalls); + counter_u64_zero(r->restarts); + counter_u64_zero(r->abdications); +} + +int +ifmp_ring_is_idle(struct ifmp_ring *r) +{ + union ring_state s; + + s.state = r->state; + if (s.pidx_head == s.pidx_tail && s.pidx_tail == s.cidx && + s.flags == IDLE) + return (1); + + return (0); +} + +int +ifmp_ring_is_stalled(struct ifmp_ring *r) +{ + union ring_state s; + + s.state = r->state; + if (s.pidx_head == s.pidx_tail && s.flags == STALLED) + return (1); + + return (0); +} diff --git a/sys/net/mp_ring.h b/sys/net/mp_ring.h new file mode 100644 index 0000000..350b668 --- /dev/null +++ b/sys/net/mp_ring.h @@ -0,0 +1,71 @@ +/*- + * Copyright (c) 2014 Chelsio Communications, Inc. + * All rights reserved. + * Written by: Navdeep Parhar <np@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#ifndef __NET_MP_RING_H +#define __NET_MP_RING_H + +#ifndef _KERNEL +#error "no user-serviceable parts inside" +#endif + +struct ifmp_ring; +typedef u_int (*mp_ring_drain_t)(struct ifmp_ring *, u_int, u_int); +typedef u_int (*mp_ring_can_drain_t)(struct ifmp_ring *); +typedef void (*mp_ring_serial_t)(struct ifmp_ring *); + +struct ifmp_ring { + volatile uint64_t state __aligned(CACHE_LINE_SIZE); + + int size __aligned(CACHE_LINE_SIZE); + void * cookie; + struct malloc_type * mt; + mp_ring_drain_t drain; + mp_ring_can_drain_t can_drain; /* cheap, may be unreliable */ + counter_u64_t enqueues; + counter_u64_t drops; + counter_u64_t starts; + counter_u64_t stalls; + counter_u64_t restarts; /* recovered after stalling */ + counter_u64_t abdications; +#ifdef NO_64BIT_ATOMICS + struct mtx lock; +#endif + void * volatile items[] __aligned(CACHE_LINE_SIZE); +}; + +int ifmp_ring_alloc(struct ifmp_ring **, int, void *, mp_ring_drain_t, + mp_ring_can_drain_t, struct malloc_type *, int); +void ifmp_ring_free(struct ifmp_ring *); +int ifmp_ring_enqueue(struct ifmp_ring *, void **, int, int); +void ifmp_ring_check_drainage(struct ifmp_ring *, int); +void ifmp_ring_reset_stats(struct ifmp_ring *); +int ifmp_ring_is_idle(struct ifmp_ring *); +int ifmp_ring_is_stalled(struct ifmp_ring *r); +#endif diff --git a/sys/net/vnet.c b/sys/net/vnet.c index 9c3d281..afb836a 100644 --- a/sys/net/vnet.c +++ b/sys/net/vnet.c @@ -233,6 +233,7 @@ vnet_alloc(void) SDT_PROBE1(vnet, functions, vnet_alloc, entry, __LINE__); vnet = malloc(sizeof(struct vnet), M_VNET, M_WAITOK | M_ZERO); vnet->vnet_magic_n = VNET_MAGIC_N; + vnet->vnet_state = 0; SDT_PROBE2(vnet, functions, vnet_alloc, alloc, __LINE__, vnet); /* @@ -268,7 +269,6 @@ vnet_alloc(void) void vnet_destroy(struct vnet *vnet) { - struct ifnet *ifp, *nifp; SDT_PROBE2(vnet, functions, vnet_destroy, entry, __LINE__, vnet); KASSERT(vnet->vnet_sockcnt == 0, @@ -279,13 +279,6 @@ vnet_destroy(struct vnet *vnet) VNET_LIST_WUNLOCK(); CURVNET_SET_QUIET(vnet); - - /* Return all inherited interfaces to their parent vnets. */ - TAILQ_FOREACH_SAFE(ifp, &V_ifnet, if_link, nifp) { - if (ifp->if_home_vnet != ifp->if_vnet) - if_vmove(ifp, ifp->if_home_vnet); - } - vnet_sysuninit(); CURVNET_RESTORE(); @@ -304,7 +297,7 @@ vnet_destroy(struct vnet *vnet) * Boot time initialization and allocation of virtual network stacks. */ static void -vnet_init_prelink(void *arg) +vnet_init_prelink(void *arg __unused) { rw_init(&vnet_rwlock, "vnet_rwlock"); @@ -316,7 +309,7 @@ SYSINIT(vnet_init_prelink, SI_SUB_VNET_PRELINK, SI_ORDER_FIRST, vnet_init_prelink, NULL); static void -vnet0_init(void *arg) +vnet0_init(void *arg __unused) { /* Warn people before take off - in case we crash early. */ @@ -333,7 +326,7 @@ vnet0_init(void *arg) SYSINIT(vnet0_init, SI_SUB_VNET, SI_ORDER_FIRST, vnet0_init, NULL); static void -vnet_init_done(void *unused) +vnet_init_done(void *unused __unused) { curvnet = NULL; @@ -358,6 +351,16 @@ vnet_data_startup(void *dummy __unused) } SYSINIT(vnet_data, SI_SUB_KLD, SI_ORDER_FIRST, vnet_data_startup, 0); +/* Dummy VNET_SYSINIT to make sure we always reach the final end state. */ +static void +vnet_sysinit_done(void *unused __unused) +{ + + return; +} +VNET_SYSINIT(vnet_sysinit_done, SI_SUB_VNET_DONE, SI_ORDER_ANY, + vnet_sysinit_done, NULL); + /* * When a module is loaded and requires storage for a virtualized global * variable, allocate space from the modspace free list. This interface @@ -571,6 +574,7 @@ vnet_sysinit(void) VNET_SYSINIT_RLOCK(); TAILQ_FOREACH(vs, &vnet_constructors, link) { + curvnet->vnet_state = vs->subsystem; vs->func(vs->arg); } VNET_SYSINIT_RUNLOCK(); @@ -589,6 +593,7 @@ vnet_sysuninit(void) VNET_SYSINIT_RLOCK(); TAILQ_FOREACH_REVERSE(vs, &vnet_destructors, vnet_sysuninit_head, link) { + curvnet->vnet_state = vs->subsystem; vs->func(vs->arg); } VNET_SYSINIT_RUNLOCK(); @@ -690,27 +695,46 @@ vnet_log_recursion(struct vnet *old_vnet, const char *old_fn, int line) * DDB(4). */ #ifdef DDB -DB_SHOW_COMMAND(vnets, db_show_vnets) +static void +db_vnet_print(struct vnet *vnet) +{ + + db_printf("vnet = %p\n", vnet); + db_printf(" vnet_magic_n = %#08x (%s, orig %#08x)\n", + vnet->vnet_magic_n, + (vnet->vnet_magic_n == VNET_MAGIC_N) ? + "ok" : "mismatch", VNET_MAGIC_N); + db_printf(" vnet_ifcnt = %u\n", vnet->vnet_ifcnt); + db_printf(" vnet_sockcnt = %u\n", vnet->vnet_sockcnt); + db_printf(" vnet_data_mem = %p\n", vnet->vnet_data_mem); + db_printf(" vnet_data_base = %#jx\n", + (uintmax_t)vnet->vnet_data_base); + db_printf(" vnet_state = %#08x\n", vnet->vnet_state); + db_printf("\n"); +} + +DB_SHOW_ALL_COMMAND(vnets, db_show_all_vnets) { VNET_ITERATOR_DECL(vnet_iter); VNET_FOREACH(vnet_iter) { - db_printf("vnet = %p\n", vnet_iter); - db_printf(" vnet_magic_n = 0x%x (%s, orig 0x%x)\n", - vnet_iter->vnet_magic_n, - (vnet_iter->vnet_magic_n == VNET_MAGIC_N) ? - "ok" : "mismatch", VNET_MAGIC_N); - db_printf(" vnet_ifcnt = %u\n", vnet_iter->vnet_ifcnt); - db_printf(" vnet_sockcnt = %u\n", vnet_iter->vnet_sockcnt); - db_printf(" vnet_data_mem = %p\n", vnet_iter->vnet_data_mem); - db_printf(" vnet_data_base = 0x%jx\n", - (uintmax_t)vnet_iter->vnet_data_base); - db_printf("\n"); + db_vnet_print(vnet_iter); if (db_pager_quit) break; } } +DB_SHOW_COMMAND(vnet, db_show_vnet) +{ + + if (!have_addr) { + db_printf("usage: show vnet <struct vnet *>\n"); + return; + } + + db_vnet_print((struct vnet *)addr); +} + static void db_show_vnet_print_vs(struct vnet_sysinit *vs, int ddb) { @@ -734,7 +758,7 @@ db_show_vnet_print_vs(struct vnet_sysinit *vs, int ddb) sym = db_search_symbol((vm_offset_t)vs->func, DB_STGY_PROC, &offset); db_symbol_values(sym, &funcname, NULL); xprint("%s(%p)\n", (vsname != NULL) ? vsname : "", vs); - xprint(" 0x%08x 0x%08x\n", vs->subsystem, vs->order); + xprint(" %#08x %#08x\n", vs->subsystem, vs->order); xprint(" %p(%s)(%p)\n", vs->func, (funcname != NULL) ? funcname : "", vs->arg); #undef xprint diff --git a/sys/net/vnet.h b/sys/net/vnet.h index 75bb728..cc23f87 100644 --- a/sys/net/vnet.h +++ b/sys/net/vnet.h @@ -70,6 +70,7 @@ struct vnet { u_int vnet_magic_n; u_int vnet_ifcnt; u_int vnet_sockcnt; + u_int vnet_state; /* SI_SUB_* */ void *vnet_data_mem; uintptr_t vnet_data_base; }; diff --git a/sys/net80211/ieee80211.c b/sys/net80211/ieee80211.c index d2b254a..453f119 100644 --- a/sys/net80211/ieee80211.c +++ b/sys/net80211/ieee80211.c @@ -406,6 +406,17 @@ ieee80211_find_com(const char *name) return (ic); } +void +ieee80211_iterate_coms(ieee80211_com_iter_func *f, void *arg) +{ + struct ieee80211com *ic; + + mtx_lock(&ic_list_mtx); + LIST_FOREACH(ic, &ic_head, ic_next) + (*f)(arg, ic); + mtx_unlock(&ic_list_mtx); +} + /* * Default reset method for use with the ioctl support. This * method is invoked after any state change in the 802.11 diff --git a/sys/net80211/ieee80211_ddb.c b/sys/net80211/ieee80211_ddb.c index de7a243..f758875 100644 --- a/sys/net80211/ieee80211_ddb.c +++ b/sys/net80211/ieee80211_ddb.c @@ -69,6 +69,8 @@ static void _db_show_vap(const struct ieee80211vap *, int, int); static void _db_show_com(const struct ieee80211com *, int showvaps, int showsta, int showmesh, int showprocs); +static void _db_show_all_vaps(void *, struct ieee80211com *); + static void _db_show_node_table(const char *tag, const struct ieee80211_node_table *); static void _db_show_channel(const char *tag, const struct ieee80211_channel *); @@ -161,8 +163,6 @@ DB_SHOW_COMMAND(com, db_show_com) DB_SHOW_ALL_COMMAND(vaps, db_show_all_vaps) { - VNET_ITERATOR_DECL(vnet_iter); - const struct ifnet *ifp; int i, showall = 0; for (i = 0; modif[i] != '\0'; i++) @@ -172,24 +172,7 @@ DB_SHOW_ALL_COMMAND(vaps, db_show_all_vaps) break; } - VNET_FOREACH(vnet_iter) { - TAILQ_FOREACH(ifp, &V_ifnet, if_list) - if (ifp->if_type == IFT_IEEE80211) { - const struct ieee80211com *ic = ifp->if_l2com; - - if (!showall) { - const struct ieee80211vap *vap; - db_printf("%s: com %p vaps:", - ifp->if_xname, ic); - TAILQ_FOREACH(vap, &ic->ic_vaps, - iv_next) - db_printf(" %s(%p)", - vap->iv_ifp->if_xname, vap); - db_printf("\n"); - } else - _db_show_com(ic, 1, 1, 1, 1); - } - } + ieee80211_iterate_coms(_db_show_all_vaps, &showall); } #ifdef IEEE80211_SUPPORT_MESH @@ -683,6 +666,21 @@ _db_show_com(const struct ieee80211com *ic, int showvaps, int showsta, } static void +_db_show_all_vaps(void *arg, struct ieee80211com *ic) +{ + int showall = *(int *)arg; + + if (!showall) { + const struct ieee80211vap *vap; + db_printf("%s: com %p vaps:", ic->ic_name, ic); + TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) + db_printf(" %s(%p)", vap->iv_ifp->if_xname, vap); + db_printf("\n"); + } else + _db_show_com(ic, 1, 1, 1, 1); +} + +static void _db_show_node_table(const char *tag, const struct ieee80211_node_table *nt) { int i; diff --git a/sys/net80211/ieee80211_var.h b/sys/net80211/ieee80211_var.h index f94a15a..3c33f0a 100644 --- a/sys/net80211/ieee80211_var.h +++ b/sys/net80211/ieee80211_var.h @@ -714,6 +714,8 @@ void ieee80211_drain(struct ieee80211com *); void ieee80211_chan_init(struct ieee80211com *); struct ieee80211com *ieee80211_find_vap(const uint8_t mac[IEEE80211_ADDR_LEN]); struct ieee80211com *ieee80211_find_com(const char *name); +typedef void ieee80211_com_iter_func(void *, struct ieee80211com *); +void ieee80211_iterate_coms(ieee80211_com_iter_func *, void *); int ieee80211_media_change(struct ifnet *); void ieee80211_media_status(struct ifnet *, struct ifmediareq *); int ieee80211_ioctl(struct ifnet *, u_long, caddr_t); diff --git a/sys/netinet/ip_fw.h b/sys/netinet/ip_fw.h index e46abf8..640025d 100644 --- a/sys/netinet/ip_fw.h +++ b/sys/netinet/ip_fw.h @@ -791,9 +791,9 @@ typedef struct _ipfw_obj_tlv { typedef struct _ipfw_obj_ntlv { ipfw_obj_tlv head; /* TLV header */ uint16_t idx; /* Name index */ - uint8_t spare; /* unused */ + uint8_t set; /* set, if applicable */ uint8_t type; /* object type, if applicable */ - uint32_t set; /* set, if applicable */ + uint32_t spare; /* unused */ char name[64]; /* Null-terminated name */ } ipfw_obj_ntlv; diff --git a/sys/netinet/tcp_input.c b/sys/netinet/tcp_input.c index cd400f5..330d305 100644 --- a/sys/netinet/tcp_input.c +++ b/sys/netinet/tcp_input.c @@ -250,7 +250,7 @@ static void tcp_vnet_init(const void *unused) { - COUNTER_ARRAY_ALLOC(VNET(tcps_states), TCP_NSTATES, M_WAITOK); + COUNTER_ARRAY_ALLOC(V_tcps_states, TCP_NSTATES, M_WAITOK); VNET_PCPUSTAT_ALLOC(tcpstat, M_WAITOK); } VNET_SYSINIT(tcp_vnet_init, SI_SUB_PROTO_IFATTACHDOMAIN, SI_ORDER_ANY, @@ -261,7 +261,7 @@ static void tcp_vnet_uninit(const void *unused) { - COUNTER_ARRAY_FREE(VNET(tcps_states), TCP_NSTATES); + COUNTER_ARRAY_FREE(V_tcps_states, TCP_NSTATES); VNET_PCPUSTAT_FREE(tcpstat); } VNET_SYSUNINIT(tcp_vnet_uninit, SI_SUB_PROTO_IFATTACHDOMAIN, SI_ORDER_ANY, diff --git a/sys/netinet/tcp_stacks/fastpath.c b/sys/netinet/tcp_stacks/fastpath.c index e7807bd..7d573c5 100644 --- a/sys/netinet/tcp_stacks/fastpath.c +++ b/sys/netinet/tcp_stacks/fastpath.c @@ -2375,34 +2375,17 @@ tcp_do_segment_fastack(struct mbuf *m, struct tcphdr *th, struct socket *so, } struct tcp_function_block __tcp_fastslow = { - "fastslow", - tcp_output, - tcp_do_segment_fastslow, - tcp_default_ctloutput, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - 0, - 0 - + .tfb_tcp_block_name = "fastslow", + .tfb_tcp_output = tcp_output, + .tfb_tcp_do_segment = tcp_do_segment_fastslow, + .tfb_tcp_ctloutput = tcp_default_ctloutput, }; struct tcp_function_block __tcp_fastack = { - "fastack", - tcp_output, - tcp_do_segment_fastack, - tcp_default_ctloutput, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - 0, - 0 + .tfb_tcp_block_name = "fastack", + .tfb_tcp_output = tcp_output, + .tfb_tcp_do_segment = tcp_do_segment_fastack, + .tfb_tcp_ctloutput = tcp_default_ctloutput }; static int diff --git a/sys/netinet/tcp_subr.c b/sys/netinet/tcp_subr.c index 64d7124..03526df 100644 --- a/sys/netinet/tcp_subr.c +++ b/sys/netinet/tcp_subr.c @@ -1642,7 +1642,7 @@ tcp_pcblist(SYSCTL_HANDLER_ARGS) */ if (req->oldptr == NULL) { n = V_tcbinfo.ipi_count + - counter_u64_fetch(VNET(tcps_states)[TCPS_SYN_RECEIVED]); + counter_u64_fetch(V_tcps_states[TCPS_SYN_RECEIVED]); n += imax(n / 8, 10); req->oldidx = 2 * (sizeof xig) + n * sizeof(struct xtcpcb); return (0); @@ -1659,7 +1659,7 @@ tcp_pcblist(SYSCTL_HANDLER_ARGS) n = V_tcbinfo.ipi_count; INP_LIST_RUNLOCK(&V_tcbinfo); - m = counter_u64_fetch(VNET(tcps_states)[TCPS_SYN_RECEIVED]); + m = counter_u64_fetch(V_tcps_states[TCPS_SYN_RECEIVED]); error = sysctl_wire_old_buffer(req, 2 * (sizeof xig) + (n + m) * sizeof(struct xtcpcb)); diff --git a/sys/netinet/tcp_timer.c b/sys/netinet/tcp_timer.c index 5925f42..837913e 100644 --- a/sys/netinet/tcp_timer.c +++ b/sys/netinet/tcp_timer.c @@ -604,6 +604,10 @@ tcp_timer_rexmt(void * xtp) KASSERT((tp->t_timers->tt_flags & TT_REXMT) != 0, ("%s: tp %p rexmt callout should be running", __func__, tp)); tcp_free_sackholes(tp); + if (tp->t_fb->tfb_tcp_rexmit_tmr) { + /* The stack has a timer action too. */ + (*tp->t_fb->tfb_tcp_rexmit_tmr)(tp); + } /* * Retransmission timer went off. Message has not * been acked within retransmit interval. Back off diff --git a/sys/netinet/tcp_var.h b/sys/netinet/tcp_var.h index f2c76a8..2bbd5e3 100644 --- a/sys/netinet/tcp_var.h +++ b/sys/netinet/tcp_var.h @@ -135,6 +135,7 @@ struct tcp_function_block { uint32_t, u_int); int (*tfb_tcp_timer_active)(struct tcpcb *, uint32_t); void (*tfb_tcp_timer_stop)(struct tcpcb *, uint32_t); + void (*tfb_tcp_rexmit_tmr)(struct tcpcb *); volatile uint32_t tfb_refcnt; uint32_t tfb_flags; }; @@ -628,8 +629,9 @@ void kmod_tcpstat_inc(int statnum); * Running TCP connection count by state. */ VNET_DECLARE(counter_u64_t, tcps_states[TCP_NSTATES]); -#define TCPSTATES_INC(state) counter_u64_add(VNET(tcps_states)[state], 1) -#define TCPSTATES_DEC(state) counter_u64_add(VNET(tcps_states)[state], -1) +#define V_tcps_states VNET(tcps_states) +#define TCPSTATES_INC(state) counter_u64_add(V_tcps_states[state], 1) +#define TCPSTATES_DEC(state) counter_u64_add(V_tcps_states[state], -1) /* * TCP specific helper hook point identifiers. diff --git a/sys/netinet6/ip6_output.c b/sys/netinet6/ip6_output.c index f64d305..1f780bd6 100644 --- a/sys/netinet6/ip6_output.c +++ b/sys/netinet6/ip6_output.c @@ -149,10 +149,10 @@ static int ip6_insertfraghdr(struct mbuf *, struct mbuf *, int, static int ip6_insert_jumboopt(struct ip6_exthdrs *, u_int32_t); static int ip6_splithdr(struct mbuf *, struct ip6_exthdrs *); static int ip6_getpmtu(struct route_in6 *, int, - struct ifnet *, struct in6_addr *, u_long *, int *, u_int); + struct ifnet *, const struct in6_addr *, u_long *, int *, u_int); static int ip6_calcmtu(struct ifnet *, const struct in6_addr *, u_long, u_long *, int *); -static int ip6_getpmtu_ctl(u_int, struct in6_addr *, u_long *); +static int ip6_getpmtu_ctl(u_int, const struct in6_addr *, u_long *); static int copypktopts(struct ip6_pktopts *, struct ip6_pktopts *, int); @@ -313,7 +313,7 @@ ip6_output(struct mbuf *m0, struct ip6_pktopts *opt, int alwaysfrag, dontfrag; u_int32_t optlen = 0, plen = 0, unfragpartlen = 0; struct ip6_exthdrs exthdrs; - struct in6_addr finaldst, src0, dst0; + struct in6_addr src0, dst0; u_int32_t zone; struct route_in6 *ro_pmtu = NULL; int hdrsplit = 0; @@ -338,7 +338,6 @@ ip6_output(struct mbuf *m0, struct ip6_pktopts *opt, } } - finaldst = ip6->ip6_dst; bzero(&exthdrs, sizeof(exthdrs)); if (opt) { /* Hop-by-Hop options header */ @@ -727,8 +726,8 @@ again: *ifpp = ifp; /* Determine path MTU. */ - if ((error = ip6_getpmtu(ro_pmtu, ro != ro_pmtu, ifp, &finaldst, &mtu, - &alwaysfrag, fibnum)) != 0) + if ((error = ip6_getpmtu(ro_pmtu, ro != ro_pmtu, ifp, &ip6->ip6_dst, + &mtu, &alwaysfrag, fibnum)) != 0) goto bad; /* @@ -826,8 +825,10 @@ again: #endif error = netisr_queue(NETISR_IPV6, m); goto done; - } else + } else { + RO_RTFREE(ro); needfiblookup = 1; /* Redo the routing table lookup. */ + } } /* See if fib was changed by packet filter. */ if (fibnum != M_GETFIB(m)) { @@ -1237,7 +1238,7 @@ ip6_insertfraghdr(struct mbuf *m0, struct mbuf *m, int hlen, * Returns 0 on success. */ static int -ip6_getpmtu_ctl(u_int fibnum, struct in6_addr *dst, u_long *mtup) +ip6_getpmtu_ctl(u_int fibnum, const struct in6_addr *dst, u_long *mtup) { struct nhop6_extended nh6; struct in6_addr kdst; @@ -1271,7 +1272,7 @@ ip6_getpmtu_ctl(u_int fibnum, struct in6_addr *dst, u_long *mtup) */ static int ip6_getpmtu(struct route_in6 *ro_pmtu, int do_lookup, - struct ifnet *ifp, struct in6_addr *dst, u_long *mtup, + struct ifnet *ifp, const struct in6_addr *dst, u_long *mtup, int *alwaysfragp, u_int fibnum) { struct nhop6_basic nh6; diff --git a/sys/netpfil/ipfw/ip_fw_dynamic.c b/sys/netpfil/ipfw/ip_fw_dynamic.c index 991de22..23e950d 100644 --- a/sys/netpfil/ipfw/ip_fw_dynamic.c +++ b/sys/netpfil/ipfw/ip_fw_dynamic.c @@ -319,77 +319,15 @@ print_dyn_rule_flags(struct ipfw_flow_id *id, int dyn_type, int log_flags, #define TIME_LEQ(a,b) ((int)((a)-(b)) <= 0) #define TIME_LE(a,b) ((int)((a)-(b)) < 0) -/* - * Lookup a dynamic rule, locked version. - */ -static ipfw_dyn_rule * -lookup_dyn_rule_locked(struct ipfw_flow_id *pkt, int i, int *match_direction, - struct tcphdr *tcp) +static void +dyn_update_proto_state(ipfw_dyn_rule *q, const struct ipfw_flow_id *id, + const struct tcphdr *tcp, int dir) { - /* - * Stateful ipfw extensions. - * Lookup into dynamic session queue. - */ -#define MATCH_REVERSE 0 -#define MATCH_FORWARD 1 -#define MATCH_NONE 2 -#define MATCH_UNKNOWN 3 - int dir = MATCH_NONE; - ipfw_dyn_rule *prev, *q = NULL; - - IPFW_BUCK_ASSERT(i); - - for (prev = NULL, q = V_ipfw_dyn_v[i].head; q; prev = q, q = q->next) { - if (q->dyn_type == O_LIMIT_PARENT && q->count) - continue; - - if (pkt->proto != q->id.proto || q->dyn_type == O_LIMIT_PARENT) - continue; - - if (IS_IP6_FLOW_ID(pkt)) { - if (IN6_ARE_ADDR_EQUAL(&pkt->src_ip6, &q->id.src_ip6) && - IN6_ARE_ADDR_EQUAL(&pkt->dst_ip6, &q->id.dst_ip6) && - pkt->src_port == q->id.src_port && - pkt->dst_port == q->id.dst_port) { - dir = MATCH_FORWARD; - break; - } - if (IN6_ARE_ADDR_EQUAL(&pkt->src_ip6, &q->id.dst_ip6) && - IN6_ARE_ADDR_EQUAL(&pkt->dst_ip6, &q->id.src_ip6) && - pkt->src_port == q->id.dst_port && - pkt->dst_port == q->id.src_port) { - dir = MATCH_REVERSE; - break; - } - } else { - if (pkt->src_ip == q->id.src_ip && - pkt->dst_ip == q->id.dst_ip && - pkt->src_port == q->id.src_port && - pkt->dst_port == q->id.dst_port) { - dir = MATCH_FORWARD; - break; - } - if (pkt->src_ip == q->id.dst_ip && - pkt->dst_ip == q->id.src_ip && - pkt->src_port == q->id.dst_port && - pkt->dst_port == q->id.src_port) { - dir = MATCH_REVERSE; - break; - } - } - } - if (q == NULL) - goto done; /* q = NULL, not found */ - - if (prev != NULL) { /* found and not in front */ - prev->next = q->next; - q->next = V_ipfw_dyn_v[i].head; - V_ipfw_dyn_v[i].head = q; - } - if (pkt->proto == IPPROTO_TCP) { /* update state according to flags */ - uint32_t ack; - u_char flags = pkt->_flags & (TH_FIN | TH_SYN | TH_RST); + uint32_t ack; + u_char flags; + if (id->proto == IPPROTO_TCP) { + flags = id->_flags & (TH_FIN | TH_SYN | TH_RST); #define BOTH_SYN (TH_SYN | (TH_SYN << 8)) #define BOTH_FIN (TH_FIN | (TH_FIN << 8)) #define TCP_FLAGS (TH_FLAGS | (TH_FLAGS << 8)) @@ -432,7 +370,8 @@ lookup_dyn_rule_locked(struct ipfw_flow_id *pkt, int i, int *match_direction, case BOTH_SYN | BOTH_FIN: /* both sides closed */ if (V_dyn_fin_lifetime >= V_dyn_keepalive_period) - V_dyn_fin_lifetime = V_dyn_keepalive_period - 1; + V_dyn_fin_lifetime = + V_dyn_keepalive_period - 1; q->expire = time_uptime + V_dyn_fin_lifetime; break; @@ -446,16 +385,86 @@ lookup_dyn_rule_locked(struct ipfw_flow_id *pkt, int i, int *match_direction, printf("invalid state: 0x%x\n", q->state); #endif if (V_dyn_rst_lifetime >= V_dyn_keepalive_period) - V_dyn_rst_lifetime = V_dyn_keepalive_period - 1; + V_dyn_rst_lifetime = + V_dyn_keepalive_period - 1; q->expire = time_uptime + V_dyn_rst_lifetime; break; } - } else if (pkt->proto == IPPROTO_UDP) { + } else if (id->proto == IPPROTO_UDP) { q->expire = time_uptime + V_dyn_udp_lifetime; } else { /* other protocols */ q->expire = time_uptime + V_dyn_short_lifetime; } +} + +/* + * Lookup a dynamic rule, locked version. + */ +static ipfw_dyn_rule * +lookup_dyn_rule_locked(struct ipfw_flow_id *pkt, int i, int *match_direction, + struct tcphdr *tcp) +{ + /* + * Stateful ipfw extensions. + * Lookup into dynamic session queue. + */ + ipfw_dyn_rule *prev, *q = NULL; + int dir; + + IPFW_BUCK_ASSERT(i); + + dir = MATCH_NONE; + for (prev = NULL, q = V_ipfw_dyn_v[i].head; q; prev = q, q = q->next) { + if (q->dyn_type == O_LIMIT_PARENT && q->count) + continue; + + if (pkt->proto != q->id.proto || q->dyn_type == O_LIMIT_PARENT) + continue; + + if (IS_IP6_FLOW_ID(pkt)) { + if (IN6_ARE_ADDR_EQUAL(&pkt->src_ip6, &q->id.src_ip6) && + IN6_ARE_ADDR_EQUAL(&pkt->dst_ip6, &q->id.dst_ip6) && + pkt->src_port == q->id.src_port && + pkt->dst_port == q->id.dst_port) { + dir = MATCH_FORWARD; + break; + } + if (IN6_ARE_ADDR_EQUAL(&pkt->src_ip6, &q->id.dst_ip6) && + IN6_ARE_ADDR_EQUAL(&pkt->dst_ip6, &q->id.src_ip6) && + pkt->src_port == q->id.dst_port && + pkt->dst_port == q->id.src_port) { + dir = MATCH_REVERSE; + break; + } + } else { + if (pkt->src_ip == q->id.src_ip && + pkt->dst_ip == q->id.dst_ip && + pkt->src_port == q->id.src_port && + pkt->dst_port == q->id.dst_port) { + dir = MATCH_FORWARD; + break; + } + if (pkt->src_ip == q->id.dst_ip && + pkt->dst_ip == q->id.src_ip && + pkt->src_port == q->id.dst_port && + pkt->dst_port == q->id.src_port) { + dir = MATCH_REVERSE; + break; + } + } + } + if (q == NULL) + goto done; /* q = NULL, not found */ + + if (prev != NULL) { /* found and not in front */ + prev->next = q->next; + q->next = V_ipfw_dyn_v[i].head; + V_ipfw_dyn_v[i].head = q; + } + + /* update state according to flags */ + dyn_update_proto_state(q, pkt, tcp, dir); done: if (match_direction != NULL) *match_direction = dir; @@ -678,7 +687,7 @@ ipfw_install_state(struct ip_fw_chain *chain, struct ip_fw *rule, ipfw_insn_limit *cmd, struct ip_fw_args *args, uint32_t tablearg) { ipfw_dyn_rule *q; - int i; + int i, dir; DEB(print_dyn_rule(&args->f_id, cmd->o.opcode, "install_state", "");) @@ -686,8 +695,7 @@ ipfw_install_state(struct ip_fw_chain *chain, struct ip_fw *rule, IPFW_BUCK_LOCK(i); - q = lookup_dyn_rule_locked(&args->f_id, i, NULL, NULL); - + q = lookup_dyn_rule_locked(&args->f_id, i, &dir, NULL); if (q != NULL) { /* should never occur */ DEB( if (last_log != time_uptime) { @@ -786,7 +794,8 @@ ipfw_install_state(struct ip_fw_chain *chain, struct ip_fw *rule, IPFW_BUCK_UNLOCK(pindex); IPFW_BUCK_LOCK(i); - q = add_dyn_rule(&args->f_id, i, O_LIMIT, (struct ip_fw *)parent); + q = add_dyn_rule(&args->f_id, i, O_LIMIT, + (struct ip_fw *)parent); if (q == NULL) { /* Decrement index and notify caller */ IPFW_BUCK_UNLOCK(i); @@ -807,9 +816,7 @@ ipfw_install_state(struct ip_fw_chain *chain, struct ip_fw *rule, return (1); /* Notify caller about failure */ } - /* XXX just set lifetime */ - lookup_dyn_rule_locked(&args->f_id, i, NULL, NULL); - + dyn_update_proto_state(q, &args->f_id, NULL, dir); IPFW_BUCK_UNLOCK(i); return (0); } diff --git a/sys/netpfil/ipfw/ip_fw_eaction.c b/sys/netpfil/ipfw/ip_fw_eaction.c index 09e0310..a9de696 100644 --- a/sys/netpfil/ipfw/ip_fw_eaction.c +++ b/sys/netpfil/ipfw/ip_fw_eaction.c @@ -137,10 +137,28 @@ static int eaction_findbyname(struct ip_fw_chain *ch, struct tid_info *ti, struct named_object **pno) { + ipfw_obj_ntlv *ntlv; - EACTION_DEBUG("uidx %u, type %u", ti->uidx, ti->type); - return (ipfw_objhash_find_type(CHAIN_TO_SRV(ch), ti, - IPFW_TLV_EACTION, pno)); + if (ti->tlvs == NULL) + return (EINVAL); + + /* Search ntlv in the buffer provided by user */ + ntlv = ipfw_find_name_tlv_type(ti->tlvs, ti->tlen, ti->uidx, + IPFW_TLV_EACTION); + if (ntlv == NULL) + return (EINVAL); + EACTION_DEBUG("name %s, uidx %u, type %u", ntlv->name, + ti->uidx, ti->type); + /* + * Search named object with corresponding name. + * Since eaction objects are global - ignore the set value + * and use zero instead. + */ + *pno = ipfw_objhash_lookup_name_type(CHAIN_TO_SRV(ch), + 0, IPFW_TLV_EACTION, ntlv->name); + if (*pno == NULL) + return (ESRCH); + return (0); } static struct named_object * diff --git a/sys/netpfil/ipfw/ip_fw_private.h b/sys/netpfil/ipfw/ip_fw_private.h index 52e8a76..e90781a 100644 --- a/sys/netpfil/ipfw/ip_fw_private.h +++ b/sys/netpfil/ipfw/ip_fw_private.h @@ -315,9 +315,10 @@ struct named_object { char *name; /* object name */ uint16_t etlv; /* Export TLV id */ uint8_t subtype;/* object subtype within class */ - uint8_t spare[3]; + uint8_t set; /* set object belongs to */ uint16_t kidx; /* object kernel index */ - uint32_t set; /* set object belongs to */ + uint16_t spare; + uint32_t ocnt; /* object counter for internal use */ uint32_t refcnt; /* number of references */ }; TAILQ_HEAD(namedobjects_head, named_object); @@ -571,6 +572,21 @@ typedef int (ipfw_obj_create_cb)(struct ip_fw_chain *ch, struct tid_info *ti, */ typedef void (ipfw_obj_destroy_cb)(struct ip_fw_chain *ch, struct named_object *no); +/* + * Sets handler callback. Handles moving and swaping set of named object. + * SWAP_ALL moves all named objects from set `set' to `new_set' and vise versa; + * TEST_ALL checks that there aren't any named object with conflicting names; + * MOVE_ALL moves all named objects from set `set' to `new_set'; + * COUNT_ONE used to count number of references used by object with kidx `set'; + * TEST_ONE checks that named object with kidx `set' can be moved to `new_set`; + * MOVE_ONE moves named object with kidx `set' to set `new_set'. + */ +enum ipfw_sets_cmd { + SWAP_ALL = 0, TEST_ALL, MOVE_ALL, COUNT_ONE, TEST_ONE, MOVE_ONE +}; +typedef int (ipfw_obj_sets_cb)(struct ip_fw_chain *ch, + uint16_t set, uint8_t new_set, enum ipfw_sets_cmd cmd); + struct opcode_obj_rewrite { uint32_t opcode; /* Opcode to act upon */ @@ -581,6 +597,7 @@ struct opcode_obj_rewrite { ipfw_obj_fidx_cb *find_bykidx; /* Find named object by kidx */ ipfw_obj_create_cb *create_object; /* Create named object */ ipfw_obj_destroy_cb *destroy_object;/* Destroy named object */ + ipfw_obj_sets_cb *manage_sets; /* Swap or move sets */ }; #define IPFW_ADD_OBJ_REWRITER(f, c) do { \ @@ -675,8 +692,11 @@ int ipfw_objhash_same_name(struct namedobj_instance *ni, struct named_object *a, void ipfw_objhash_add(struct namedobj_instance *ni, struct named_object *no); void ipfw_objhash_del(struct namedobj_instance *ni, struct named_object *no); uint32_t ipfw_objhash_count(struct namedobj_instance *ni); +uint32_t ipfw_objhash_count_type(struct namedobj_instance *ni, uint16_t type); int ipfw_objhash_foreach(struct namedobj_instance *ni, objhash_cb_t *f, void *arg); +int ipfw_objhash_foreach_type(struct namedobj_instance *ni, objhash_cb_t *f, + void *arg, uint16_t type); int ipfw_objhash_free_idx(struct namedobj_instance *ni, uint16_t idx); int ipfw_objhash_alloc_idx(void *n, uint16_t *pidx); void ipfw_objhash_set_funcs(struct namedobj_instance *ni, @@ -698,6 +718,8 @@ int classify_opcode_kidx(ipfw_insn *cmd, uint16_t *puidx); void ipfw_init_srv(struct ip_fw_chain *ch); void ipfw_destroy_srv(struct ip_fw_chain *ch); int ipfw_check_object_name_generic(const char *name); +int ipfw_obj_manage_sets(struct namedobj_instance *ni, uint16_t type, + uint16_t set, uint8_t new_set, enum ipfw_sets_cmd cmd); /* In ip_fw_eaction.c */ typedef int (ipfw_eaction_t)(struct ip_fw_chain *ch, struct ip_fw_args *args, diff --git a/sys/netpfil/ipfw/ip_fw_sockopt.c b/sys/netpfil/ipfw/ip_fw_sockopt.c index c183dfc..d186ba5 100644 --- a/sys/netpfil/ipfw/ip_fw_sockopt.c +++ b/sys/netpfil/ipfw/ip_fw_sockopt.c @@ -851,6 +851,113 @@ ipfw_match_range(struct ip_fw *rule, ipfw_range_tlv *rt) return (1); } +struct manage_sets_args { + uint16_t set; + uint8_t new_set; +}; + +static int +swap_sets_cb(struct namedobj_instance *ni, struct named_object *no, + void *arg) +{ + struct manage_sets_args *args; + + args = (struct manage_sets_args *)arg; + if (no->set == (uint8_t)args->set) + no->set = args->new_set; + else if (no->set == args->new_set) + no->set = (uint8_t)args->set; + return (0); +} + +static int +move_sets_cb(struct namedobj_instance *ni, struct named_object *no, + void *arg) +{ + struct manage_sets_args *args; + + args = (struct manage_sets_args *)arg; + if (no->set == (uint8_t)args->set) + no->set = args->new_set; + return (0); +} + +static int +test_sets_cb(struct namedobj_instance *ni, struct named_object *no, + void *arg) +{ + struct manage_sets_args *args; + + args = (struct manage_sets_args *)arg; + if (no->set != (uint8_t)args->set) + return (0); + if (ipfw_objhash_lookup_name_type(ni, args->new_set, + no->etlv, no->name) != NULL) + return (EEXIST); + return (0); +} + +/* + * Generic function to handler moving and swapping sets. + */ +int +ipfw_obj_manage_sets(struct namedobj_instance *ni, uint16_t type, + uint16_t set, uint8_t new_set, enum ipfw_sets_cmd cmd) +{ + struct manage_sets_args args; + struct named_object *no; + + args.set = set; + args.new_set = new_set; + switch (cmd) { + case SWAP_ALL: + return (ipfw_objhash_foreach_type(ni, swap_sets_cb, + &args, type)); + case TEST_ALL: + return (ipfw_objhash_foreach_type(ni, test_sets_cb, + &args, type)); + case MOVE_ALL: + return (ipfw_objhash_foreach_type(ni, move_sets_cb, + &args, type)); + case COUNT_ONE: + /* + * @set used to pass kidx. + * When @new_set is zero - reset object counter, + * otherwise increment it. + */ + no = ipfw_objhash_lookup_kidx(ni, set); + if (new_set != 0) + no->ocnt++; + else + no->ocnt = 0; + return (0); + case TEST_ONE: + /* @set used to pass kidx */ + no = ipfw_objhash_lookup_kidx(ni, set); + /* + * First check number of references: + * when it differs, this mean other rules are holding + * reference to given object, so it is not possible to + * change its set. Note that refcnt may account references + * to some going-to-be-added rules. Since we don't know + * their numbers (and even if they will be added) it is + * perfectly OK to return error here. + */ + if (no->ocnt != no->refcnt) + return (EBUSY); + if (ipfw_objhash_lookup_name_type(ni, new_set, type, + no->name) != NULL) + return (EEXIST); + return (0); + case MOVE_ONE: + /* @set used to pass kidx */ + no = ipfw_objhash_lookup_kidx(ni, set); + no->set = new_set; + return (0); + } + return (EINVAL); +} + /* * Delete rules matching range @rt. * Saves number of deleted rules in @ndel. @@ -935,7 +1042,89 @@ delete_range(struct ip_fw_chain *chain, ipfw_range_tlv *rt, int *ndel) return (0); } -/* +static int +move_objects(struct ip_fw_chain *ch, ipfw_range_tlv *rt) +{ + struct opcode_obj_rewrite *rw; + struct ip_fw *rule; + ipfw_insn *cmd; + int cmdlen, i, l, c; + uint16_t kidx; + + IPFW_UH_WLOCK_ASSERT(ch); + + /* Stage 1: count number of references by given rules */ + for (c = 0, i = 0; i < ch->n_rules - 1; i++) { + rule = ch->map[i]; + if (ipfw_match_range(rule, rt) == 0) + continue; + if (rule->set == rt->new_set) /* nothing to do */ + continue; + /* Search opcodes with named objects */ + for (l = rule->cmd_len, cmdlen = 0, cmd = rule->cmd; + l > 0; l -= cmdlen, cmd += cmdlen) { + cmdlen = F_LEN(cmd); + rw = find_op_rw(cmd, &kidx, NULL); + if (rw == NULL || rw->manage_sets == NULL) + continue; + /* + * When manage_sets() returns non-zero value to + * COUNT_ONE command, consider this as an object + * doesn't support sets (e.g. disabled with sysctl). + * So, skip checks for this object. + */ + if (rw->manage_sets(ch, kidx, 1, COUNT_ONE) != 0) + continue; + c++; + } + } + if (c == 0) /* No objects found */ + return (0); + /* Stage 2: verify "ownership" */ + for (c = 0, i = 0; (i < ch->n_rules - 1) && c == 0; i++) { + rule = ch->map[i]; + if (ipfw_match_range(rule, rt) == 0) + continue; + if (rule->set == rt->new_set) /* nothing to do */ + continue; + /* Search opcodes with named objects */ + for (l = rule->cmd_len, cmdlen = 0, cmd = rule->cmd; + l > 0 && c == 0; l -= cmdlen, cmd += cmdlen) { + cmdlen = F_LEN(cmd); + rw = find_op_rw(cmd, &kidx, NULL); + if (rw == NULL || rw->manage_sets == NULL) + continue; + /* Test for ownership and conflicting names */ + c = rw->manage_sets(ch, kidx, + (uint8_t)rt->new_set, TEST_ONE); + } + } + /* Stage 3: change set and cleanup */ + for (i = 0; i < ch->n_rules - 1; i++) { + rule = ch->map[i]; + if (ipfw_match_range(rule, rt) == 0) + continue; + if (rule->set == rt->new_set) /* nothing to do */ + continue; + /* Search opcodes with named objects */ + for (l = rule->cmd_len, cmdlen = 0, cmd = rule->cmd; + l > 0; l -= cmdlen, cmd += cmdlen) { + cmdlen = F_LEN(cmd); + rw = find_op_rw(cmd, &kidx, NULL); + if (rw == NULL || rw->manage_sets == NULL) + continue; + /* cleanup object counter */ + rw->manage_sets(ch, kidx, + 0 /* reset counter */, COUNT_ONE); + if (c != 0) + continue; + /* change set */ + rw->manage_sets(ch, kidx, + (uint8_t)rt->new_set, MOVE_ONE); + } + } + return (c); +}/* * Changes set of given rule rannge @rt * with each other. * @@ -956,11 +1145,9 @@ move_range(struct ip_fw_chain *chain, ipfw_range_tlv *rt) * by given rule subset only. Otherwise, we can't move * them to new set and have to return error. */ - if (V_fw_tables_sets != 0) { - if (ipfw_move_tables_sets(chain, rt, rt->new_set) != 0) { - IPFW_UH_WUNLOCK(chain); - return (EBUSY); - } + if ((i = move_objects(chain, rt)) != 0) { + IPFW_UH_WUNLOCK(chain); + return (i); } /* XXX: We have to do swap holding WLOCK */ @@ -1156,24 +1343,48 @@ enable_sets(struct ip_fw_chain *chain, ipfw_range_tlv *rt) IPFW_WUNLOCK(chain); } -static void +static int swap_sets(struct ip_fw_chain *chain, ipfw_range_tlv *rt, int mv) { + struct opcode_obj_rewrite *rw; struct ip_fw *rule; int i; IPFW_UH_WLOCK_ASSERT(chain); + if (rt->set == rt->new_set) /* nothing to do */ + return (0); + + if (mv != 0) { + /* + * Berfore moving the rules we need to check that + * there aren't any conflicting named objects. + */ + for (rw = ctl3_rewriters; + rw < ctl3_rewriters + ctl3_rsize; rw++) { + if (rw->manage_sets == NULL) + continue; + i = rw->manage_sets(chain, (uint8_t)rt->set, + (uint8_t)rt->new_set, TEST_ALL); + if (i != 0) + return (EEXIST); + } + } /* Swap or move two sets */ for (i = 0; i < chain->n_rules - 1; i++) { rule = chain->map[i]; - if (rule->set == rt->set) - rule->set = rt->new_set; - else if (rule->set == rt->new_set && mv == 0) - rule->set = rt->set; + if (rule->set == (uint8_t)rt->set) + rule->set = (uint8_t)rt->new_set; + else if (rule->set == (uint8_t)rt->new_set && mv == 0) + rule->set = (uint8_t)rt->set; + } + for (rw = ctl3_rewriters; rw < ctl3_rewriters + ctl3_rsize; rw++) { + if (rw->manage_sets == NULL) + continue; + rw->manage_sets(chain, (uint8_t)rt->set, + (uint8_t)rt->new_set, mv != 0 ? MOVE_ALL: SWAP_ALL); } - if (V_fw_tables_sets != 0) - ipfw_swap_tables_sets(chain, rt->set, rt->new_set, mv); + return (0); } /* @@ -1188,6 +1399,7 @@ manage_sets(struct ip_fw_chain *chain, ip_fw3_opheader *op3, struct sockopt_data *sd) { ipfw_range_header *rh; + int ret; if (sd->valsize != sizeof(*rh)) return (EINVAL); @@ -1196,12 +1408,17 @@ manage_sets(struct ip_fw_chain *chain, ip_fw3_opheader *op3, if (rh->range.head.length != sizeof(ipfw_range_tlv)) return (1); + if (rh->range.set >= IPFW_MAX_SETS || + rh->range.new_set >= IPFW_MAX_SETS) + return (EINVAL); + ret = 0; IPFW_UH_WLOCK(chain); switch (op3->opcode) { case IP_FW_SET_SWAP: case IP_FW_SET_MOVE: - swap_sets(chain, &rh->range, op3->opcode == IP_FW_SET_MOVE); + ret = swap_sets(chain, &rh->range, + op3->opcode == IP_FW_SET_MOVE); break; case IP_FW_SET_ENABLE: enable_sets(chain, &rh->range); @@ -1209,7 +1426,7 @@ manage_sets(struct ip_fw_chain *chain, ip_fw3_opheader *op3, } IPFW_UH_WUNLOCK(chain); - return (0); + return (ret); } /** @@ -1280,14 +1497,14 @@ del_entry(struct ip_fw_chain *chain, uint32_t arg) break; case 3: /* move rules from set "rulenum" to set "new_set" */ IPFW_UH_WLOCK(chain); - swap_sets(chain, &rt, 1); + error = swap_sets(chain, &rt, 1); IPFW_UH_WUNLOCK(chain); - return (0); + return (error); case 4: /* swap sets "rulenum" and "new_set" */ IPFW_UH_WLOCK(chain); - swap_sets(chain, &rt, 0); + error = swap_sets(chain, &rt, 0); IPFW_UH_WUNLOCK(chain); - return (0); + return (error); default: return (ENOTSUP); } @@ -2526,11 +2743,8 @@ rewrite_rule_uidx(struct ip_fw_chain *chain, struct rule_check_info *ci) type = 0; memset(&ti, 0, sizeof(ti)); - /* - * Use default set for looking up tables (old way) or - * use set rule is assigned to (new way). - */ - ti.set = (V_fw_tables_sets != 0) ? ci->krule->set : 0; + /* Use set rule is assigned to. */ + ti.set = ci->krule->set; if (ci->ctlv != NULL) { ti.tlvs = (void *)(ci->ctlv + 1); ti.tlen = ci->ctlv->head.length - sizeof(ipfw_obj_ctlv); @@ -4248,6 +4462,23 @@ ipfw_objhash_count(struct namedobj_instance *ni) return (ni->count); } +uint32_t +ipfw_objhash_count_type(struct namedobj_instance *ni, uint16_t type) +{ + struct named_object *no; + uint32_t count; + int i; + + count = 0; + for (i = 0; i < ni->nn_size; i++) { + TAILQ_FOREACH(no, &ni->names[i], nn_next) { + if (no->etlv == type) + count++; + } + } + return (count); +} + /* * Runs @func for each found named object. * It is safe to delete objects from callback @@ -4269,6 +4500,29 @@ ipfw_objhash_foreach(struct namedobj_instance *ni, objhash_cb_t *f, void *arg) } /* + * Runs @f for each found named object with type @type. + * It is safe to delete objects from callback + */ +int +ipfw_objhash_foreach_type(struct namedobj_instance *ni, objhash_cb_t *f, + void *arg, uint16_t type) +{ + struct named_object *no, *no_tmp; + int i, ret; + + for (i = 0; i < ni->nn_size; i++) { + TAILQ_FOREACH_SAFE(no, &ni->names[i], nn_next, no_tmp) { + if (no->etlv != type) + continue; + ret = f(ni, no, arg); + if (ret != 0) + return (ret); + } + } + return (0); +} + +/* * Removes index from given set. * Returns 0 on success. */ diff --git a/sys/netpfil/ipfw/ip_fw_table.c b/sys/netpfil/ipfw/ip_fw_table.c index 194be08..68225b3 100644 --- a/sys/netpfil/ipfw/ip_fw_table.c +++ b/sys/netpfil/ipfw/ip_fw_table.c @@ -1602,64 +1602,6 @@ ipfw_resize_tables(struct ip_fw_chain *ch, unsigned int ntables) } /* - * Switch between "set 0" and "rule's set" table binding, - * Check all ruleset bindings and permits changing - * IFF each binding has both rule AND table in default set (set 0). - * - * Returns 0 on success. - */ -int -ipfw_switch_tables_namespace(struct ip_fw_chain *ch, unsigned int sets) -{ - struct namedobj_instance *ni; - struct named_object *no; - struct ip_fw *rule; - ipfw_insn *cmd; - int cmdlen, i, l; - uint16_t kidx; - - IPFW_UH_WLOCK(ch); - - if (V_fw_tables_sets == sets) { - IPFW_UH_WUNLOCK(ch); - return (0); - } - - ni = CHAIN_TO_NI(ch); - - /* - * Scan all rules and examine tables opcodes. - */ - for (i = 0; i < ch->n_rules; i++) { - rule = ch->map[i]; - - l = rule->cmd_len; - cmd = rule->cmd; - cmdlen = 0; - for ( ; l > 0 ; l -= cmdlen, cmd += cmdlen) { - cmdlen = F_LEN(cmd); - - if (classify_opcode_kidx(cmd, &kidx) != 0) - continue; - - no = ipfw_objhash_lookup_kidx(ni, kidx); - - /* Check if both table object and rule has the set 0 */ - if (no->set != 0 || rule->set != 0) { - IPFW_UH_WUNLOCK(ch); - return (EBUSY); - } - - } - } - V_fw_tables_sets = sets; - - IPFW_UH_WUNLOCK(ch); - - return (0); -} - -/* * Lookup an IP @addr in table @tbl. * Stores found value in @val. * @@ -2875,39 +2817,190 @@ table_findbykidx(struct ip_fw_chain *ch, uint16_t idx) return (&tc->no); } +static int +table_manage_sets(struct ip_fw_chain *ch, uint16_t set, uint8_t new_set, + enum ipfw_sets_cmd cmd) +{ + + switch (cmd) { + case SWAP_ALL: + case TEST_ALL: + /* + * Return success for TEST_ALL, since nothing prevents + * move rules from one set to another. All tables are + * accessible from all sets when per-set tables sysctl + * is disabled. + */ + case MOVE_ALL: + case TEST_ONE: + case MOVE_ONE: + /* + * NOTE: we need to use ipfw_objhash_del/ipfw_objhash_add + * if set number will be used in hash function. Currently + * we can just use generic handler that replaces set value. + */ + if (V_fw_tables_sets == 0) + return (0); + break; + case COUNT_ONE: + /* + * Return EOPNOTSUPP for COUNT_ONE when per-set sysctl is + * disabled. This allow skip table's opcodes from additional + * checks when specific rules moved to another set. + */ + if (V_fw_tables_sets == 0) + return (EOPNOTSUPP); + } + /* Use generic sets handler when per-set sysctl is enabled. */ + return (ipfw_obj_manage_sets(CHAIN_TO_NI(ch), IPFW_TLV_TBL_NAME, + set, new_set, cmd)); +} + static struct opcode_obj_rewrite opcodes[] = { { - O_IP_SRC_LOOKUP, IPFW_TLV_TBL_NAME, - classify_srcdst, update_arg1, - table_findbyname, table_findbykidx, create_table_compat + .opcode = O_IP_SRC_LOOKUP, + .etlv = IPFW_TLV_TBL_NAME, + .classifier = classify_srcdst, + .update = update_arg1, + .find_byname = table_findbyname, + .find_bykidx = table_findbykidx, + .create_object = create_table_compat, + .manage_sets = table_manage_sets, }, { - O_IP_DST_LOOKUP, IPFW_TLV_TBL_NAME, - classify_srcdst, update_arg1, - table_findbyname, table_findbykidx, create_table_compat + .opcode = O_IP_DST_LOOKUP, + .etlv = IPFW_TLV_TBL_NAME, + .classifier = classify_srcdst, + .update = update_arg1, + .find_byname = table_findbyname, + .find_bykidx = table_findbykidx, + .create_object = create_table_compat, + .manage_sets = table_manage_sets, }, { - O_IP_FLOW_LOOKUP, IPFW_TLV_TBL_NAME, - classify_flow, update_arg1, - table_findbyname, table_findbykidx, create_table_compat + .opcode = O_IP_FLOW_LOOKUP, + .etlv = IPFW_TLV_TBL_NAME, + .classifier = classify_flow, + .update = update_arg1, + .find_byname = table_findbyname, + .find_bykidx = table_findbykidx, + .create_object = create_table_compat, + .manage_sets = table_manage_sets, }, { - O_XMIT, IPFW_TLV_TBL_NAME, - classify_via, update_via, - table_findbyname, table_findbykidx, create_table_compat + .opcode = O_XMIT, + .etlv = IPFW_TLV_TBL_NAME, + .classifier = classify_via, + .update = update_via, + .find_byname = table_findbyname, + .find_bykidx = table_findbykidx, + .create_object = create_table_compat, + .manage_sets = table_manage_sets, }, { - O_RECV, IPFW_TLV_TBL_NAME, - classify_via, update_via, - table_findbyname, table_findbykidx, create_table_compat + .opcode = O_RECV, + .etlv = IPFW_TLV_TBL_NAME, + .classifier = classify_via, + .update = update_via, + .find_byname = table_findbyname, + .find_bykidx = table_findbykidx, + .create_object = create_table_compat, + .manage_sets = table_manage_sets, }, { - O_VIA, IPFW_TLV_TBL_NAME, - classify_via, update_via, - table_findbyname, table_findbykidx, create_table_compat + .opcode = O_VIA, + .etlv = IPFW_TLV_TBL_NAME, + .classifier = classify_via, + .update = update_via, + .find_byname = table_findbyname, + .find_bykidx = table_findbykidx, + .create_object = create_table_compat, + .manage_sets = table_manage_sets, }, }; +static int +test_sets_cb(struct namedobj_instance *ni __unused, struct named_object *no, + void *arg __unused) +{ + + /* Check that there aren't any tables in not default set */ + if (no->set != 0) + return (EBUSY); + return (0); +} + +/* + * Switch between "set 0" and "rule's set" table binding, + * Check all ruleset bindings and permits changing + * IFF each binding has both rule AND table in default set (set 0). + * + * Returns 0 on success. + */ +int +ipfw_switch_tables_namespace(struct ip_fw_chain *ch, unsigned int sets) +{ + struct opcode_obj_rewrite *rw; + struct namedobj_instance *ni; + struct named_object *no; + struct ip_fw *rule; + ipfw_insn *cmd; + int cmdlen, i, l; + uint16_t kidx; + uint8_t subtype; + + IPFW_UH_WLOCK(ch); + + if (V_fw_tables_sets == sets) { + IPFW_UH_WUNLOCK(ch); + return (0); + } + ni = CHAIN_TO_NI(ch); + if (sets == 0) { + /* + * Prevent disabling sets support if we have some tables + * in not default sets. + */ + if (ipfw_objhash_foreach_type(ni, test_sets_cb, + NULL, IPFW_TLV_TBL_NAME) != 0) { + IPFW_UH_WUNLOCK(ch); + return (EBUSY); + } + } + /* + * Scan all rules and examine tables opcodes. + */ + for (i = 0; i < ch->n_rules; i++) { + rule = ch->map[i]; + + l = rule->cmd_len; + cmd = rule->cmd; + cmdlen = 0; + for ( ; l > 0 ; l -= cmdlen, cmd += cmdlen) { + cmdlen = F_LEN(cmd); + /* Check only tables opcodes */ + for (kidx = 0, rw = opcodes; + rw < opcodes + nitems(opcodes); rw++) { + if (rw->opcode != cmd->opcode) + continue; + if (rw->classifier(cmd, &kidx, &subtype) == 0) + break; + } + if (kidx == 0) + continue; + no = ipfw_objhash_lookup_kidx(ni, kidx); + /* Check if both table object and rule has the set 0 */ + if (no->set != 0 || rule->set != 0) { + IPFW_UH_WUNLOCK(ch); + return (EBUSY); + } + + } + } + V_fw_tables_sets = sets; + IPFW_UH_WUNLOCK(ch); + return (0); +} /* * Checks table name for validity. @@ -2954,7 +3047,7 @@ find_table_err(struct namedobj_instance *ni, struct tid_info *ti, * This is needed due to different sets behavior * controlled by V_fw_tables_sets. */ - set = ti->set; + set = (V_fw_tables_sets != 0) ? ti->set : 0; } else { snprintf(bname, sizeof(bname), "%d", ti->uidx); name = bname; @@ -3112,196 +3205,6 @@ unlink_table(struct ip_fw_chain *ch, struct table_config *tc) tc->ta->change_ti(tc->astate, NULL); } -struct swap_table_args { - int set; - int new_set; - int mv; -}; - -/* - * Change set for each matching table. - * - * Ensure we dispatch each table once by setting/checking ochange - * fields. - */ -static int -swap_table_set(struct namedobj_instance *ni, struct named_object *no, - void *arg) -{ - struct table_config *tc; - struct swap_table_args *sta; - - tc = (struct table_config *)no; - sta = (struct swap_table_args *)arg; - - if (no->set != sta->set && (no->set != sta->new_set || sta->mv != 0)) - return (0); - - if (tc->ochanged != 0) - return (0); - - tc->ochanged = 1; - ipfw_objhash_del(ni, no); - if (no->set == sta->set) - no->set = sta->new_set; - else - no->set = sta->set; - ipfw_objhash_add(ni, no); - return (0); -} - -/* - * Cleans up ochange field for all tables. - */ -static int -clean_table_set_data(struct namedobj_instance *ni, struct named_object *no, - void *arg) -{ - struct table_config *tc; - struct swap_table_args *sta; - - tc = (struct table_config *)no; - sta = (struct swap_table_args *)arg; - - tc->ochanged = 0; - return (0); -} - -/* - * Swaps tables within two sets. - */ -void -ipfw_swap_tables_sets(struct ip_fw_chain *ch, uint32_t set, - uint32_t new_set, int mv) -{ - struct swap_table_args sta; - - IPFW_UH_WLOCK_ASSERT(ch); - - sta.set = set; - sta.new_set = new_set; - sta.mv = mv; - - ipfw_objhash_foreach(CHAIN_TO_NI(ch), swap_table_set, &sta); - ipfw_objhash_foreach(CHAIN_TO_NI(ch), clean_table_set_data, &sta); -} - -/* - * Move all tables which are reference by rules in @rr to set @new_set. - * Makes sure that all relevant tables are referenced ONLLY by given rules. - * - * Returns 0 on success, - */ -int -ipfw_move_tables_sets(struct ip_fw_chain *ch, ipfw_range_tlv *rt, - uint32_t new_set) -{ - struct ip_fw *rule; - struct table_config *tc; - struct named_object *no; - struct namedobj_instance *ni; - int bad, i, l, cmdlen; - uint16_t kidx; - ipfw_insn *cmd; - - IPFW_UH_WLOCK_ASSERT(ch); - - ni = CHAIN_TO_NI(ch); - - /* Stage 1: count number of references by given rules */ - for (i = 0; i < ch->n_rules - 1; i++) { - rule = ch->map[i]; - if (ipfw_match_range(rule, rt) == 0) - continue; - - l = rule->cmd_len; - cmd = rule->cmd; - cmdlen = 0; - for ( ; l > 0 ; l -= cmdlen, cmd += cmdlen) { - cmdlen = F_LEN(cmd); - if (classify_opcode_kidx(cmd, &kidx) != 0) - continue; - no = ipfw_objhash_lookup_kidx(ni, kidx); - KASSERT(no != NULL, - ("objhash lookup failed on index %d", kidx)); - tc = (struct table_config *)no; - tc->ocount++; - } - - } - - /* Stage 2: verify "ownership" */ - bad = 0; - for (i = 0; i < ch->n_rules - 1; i++) { - rule = ch->map[i]; - if (ipfw_match_range(rule, rt) == 0) - continue; - - l = rule->cmd_len; - cmd = rule->cmd; - cmdlen = 0; - for ( ; l > 0 ; l -= cmdlen, cmd += cmdlen) { - cmdlen = F_LEN(cmd); - if (classify_opcode_kidx(cmd, &kidx) != 0) - continue; - no = ipfw_objhash_lookup_kidx(ni, kidx); - KASSERT(no != NULL, - ("objhash lookup failed on index %d", kidx)); - tc = (struct table_config *)no; - if (tc->no.refcnt != tc->ocount) { - - /* - * Number of references differ: - * Other rule(s) are holding reference to given - * table, so it is not possible to change its set. - * - * Note that refcnt may account - * references to some going-to-be-added rules. - * Since we don't know their numbers (and event - * if they will be added) it is perfectly OK - * to return error here. - */ - bad = 1; - break; - } - } - - if (bad != 0) - break; - } - - /* Stage 3: change set or cleanup */ - for (i = 0; i < ch->n_rules - 1; i++) { - rule = ch->map[i]; - if (ipfw_match_range(rule, rt) == 0) - continue; - - l = rule->cmd_len; - cmd = rule->cmd; - cmdlen = 0; - for ( ; l > 0 ; l -= cmdlen, cmd += cmdlen) { - cmdlen = F_LEN(cmd); - if (classify_opcode_kidx(cmd, &kidx) != 0) - continue; - no = ipfw_objhash_lookup_kidx(ni, kidx); - KASSERT(no != NULL, - ("objhash lookup failed on index %d", kidx)); - tc = (struct table_config *)no; - - tc->ocount = 0; - if (bad != 0) - continue; - - /* Actually change set. */ - ipfw_objhash_del(ni, no); - no->set = new_set; - ipfw_objhash_add(ni, no); - } - } - - return (bad); -} - static struct ipfw_sopt_handler scodes[] = { { IP_FW_TABLE_XCREATE, 0, HDIR_SET, create_table }, { IP_FW_TABLE_XDESTROY, 0, HDIR_SET, flush_table_v0 }, diff --git a/sys/ofed/drivers/infiniband/debug/memtrack.c b/sys/ofed/drivers/infiniband/debug/memtrack.c index 7082856..6c8d5df 100644 --- a/sys/ofed/drivers/infiniband/debug/memtrack.c +++ b/sys/ofed/drivers/infiniband/debug/memtrack.c @@ -510,7 +510,7 @@ EXPORT_SYMBOL(is_non_trackable_free_func); /* WA - In this function handles confirm - the the function name is + the function name is '__ib_umem_release' or 'ib_umem_get' In this case we won't track the memory there because the kernel diff --git a/sys/ofed/drivers/infiniband/debug/memtrack.h b/sys/ofed/drivers/infiniband/debug/memtrack.h index 76265ae..fb52f4b 100644 --- a/sys/ofed/drivers/infiniband/debug/memtrack.h +++ b/sys/ofed/drivers/infiniband/debug/memtrack.h @@ -64,7 +64,7 @@ int is_non_trackable_alloc_func(const char *func_name); int is_non_trackable_free_func(const char *func_name); /* WA - In this function handles confirm - the the function name is + the function name is '__ib_umem_release' or 'ib_umem_get' In this case we won't track the memory there because the kernel diff --git a/sys/ofed/drivers/net/mlx4/main.c b/sys/ofed/drivers/net/mlx4/main.c index 314a4ba..10ba359 100644 --- a/sys/ofed/drivers/net/mlx4/main.c +++ b/sys/ofed/drivers/net/mlx4/main.c @@ -164,7 +164,7 @@ MODULE_PARM_DESC(fast_drop, int mlx4_enable_64b_cqe_eqe = 1; module_param_named(enable_64b_cqe_eqe, mlx4_enable_64b_cqe_eqe, int, 0644); MODULE_PARM_DESC(enable_64b_cqe_eqe, - "Enable 64 byte CQEs/EQEs when the the FW supports this if non-zero (default: 1)"); + "Enable 64 byte CQEs/EQEs when the FW supports this if non-zero (default: 1)"); #define HCA_GLOBAL_CAP_MASK 0 diff --git a/sys/sparc64/central/central.c b/sys/sparc64/central/central.c index 9b16364..f768322 100644 --- a/sys/sparc64/central/central.c +++ b/sys/sparc64/central/central.c @@ -165,7 +165,7 @@ central_attach(device_t dev) resource_list_add(&cdi->cdi_rl, SYS_RES_MEMORY, i, reg[i].sbr_offset, reg[i].sbr_offset + reg[i].sbr_size, reg[i].sbr_size); - free(reg, M_OFWPROP); + OF_prop_free(reg); cdev = device_add_child(dev, NULL, -1); if (cdev == NULL) { device_printf(dev, "<%s>: device_add_child failed\n", diff --git a/sys/sparc64/ebus/ebus.c b/sys/sparc64/ebus/ebus.c index 55a90a3..b48dab6 100644 --- a/sys/sparc64/ebus/ebus.c +++ b/sys/sparc64/ebus/ebus.c @@ -376,7 +376,7 @@ ebus_pci_attach(device_t dev) } } free(sc->sc_rinfo, M_DEVBUF); - free(sc->sc_range, M_OFWPROP); + OF_prop_free(sc->sc_range); return (ENXIO); } @@ -670,7 +670,7 @@ ebus_setup_dinfo(device_t dev, struct ebus_softc *sc, phandle_t node) (void)resource_list_add(&edi->edi_rl, SYS_RES_MEMORY, i, start, start + regs[i].size - 1, regs[i].size); } - free(regs, M_OFWPROP); + OF_prop_free(regs); nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intrs), (void **)&intrs); @@ -701,7 +701,7 @@ ebus_setup_dinfo(device_t dev, struct ebus_softc *sc, phandle_t node) (void)resource_list_add(&edi->edi_rl, SYS_RES_IRQ, i, rintr, rintr, 1); } - free(intrs, M_OFWPROP); + OF_prop_free(intrs); return (edi); } diff --git a/sys/sparc64/fhc/fhc.c b/sys/sparc64/fhc/fhc.c index 85aa67d..417e32b 100644 --- a/sys/sparc64/fhc/fhc.c +++ b/sys/sparc64/fhc/fhc.c @@ -205,7 +205,7 @@ fhc_attach(device_t dev) device_printf(dev, "board %d, ", board); if (OF_getprop_alloc(node, "board-model", 1, (void **)&name) != -1) { printf("model %s\n", name); - free(name, M_OFWPROP); + OF_prop_free(name); } else printf("model unknown\n"); @@ -297,7 +297,7 @@ fhc_attach(device_t dev) resource_list_add(&fdi->fdi_rl, SYS_RES_MEMORY, j, reg[j].sbr_offset, reg[j].sbr_offset + reg[j].sbr_size, reg[j].sbr_size); - free(reg, M_OFWPROP); + OF_prop_free(reg); if (central == 1) { i = OF_getprop_alloc(child, "interrupts", sizeof(*intr), (void **)&intr); @@ -307,7 +307,7 @@ fhc_attach(device_t dev) resource_list_add(&fdi->fdi_rl, SYS_RES_IRQ, j, iv, iv, 1); } - free(intr, M_OFWPROP); + OF_prop_free(intr); } } cdev = device_add_child(dev, NULL, -1); diff --git a/sys/sparc64/isa/isa.c b/sys/sparc64/isa/isa.c index 74627c5..b583553 100644 --- a/sys/sparc64/isa/isa.c +++ b/sys/sparc64/isa/isa.c @@ -169,7 +169,7 @@ isa_setup_children(device_t dev, phandle_t parent) */ if (strcmp(name, "8042") == 0) { isa_setup_children(dev, node); - free(name, M_OFWPROP); + OF_prop_free(name); continue; } @@ -179,7 +179,7 @@ isa_setup_children(device_t dev, phandle_t parent) if (ofw_isa_pnp_map[i].name == NULL) { device_printf(dev, "no PnP map entry for node " "0x%lx: %s\n", (unsigned long)node, name); - free(name, M_OFWPROP); + OF_prop_free(name); continue; } @@ -230,10 +230,10 @@ isa_setup_children(device_t dev, phandle_t parent) } } if (regidx != NULL) - free(regidx, M_OFWPROP); + OF_prop_free(regidx); } if (regs != NULL) - free(regs, M_OFWPROP); + OF_prop_free(regs); nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intrs), (void **)&intrs); @@ -251,14 +251,14 @@ isa_setup_children(device_t dev, phandle_t parent) bus_set_resource(cdev, SYS_RES_IRQ, i, rintr, 1); } if (intrs != NULL) - free(intrs, M_OFWPROP); + OF_prop_free(intrs); ndrq = OF_getprop_alloc(node, "dma-channel", sizeof(*drqs), (void **)&drqs); for (i = 0; i < ndrq; i++) bus_set_resource(cdev, SYS_RES_DRQ, i, drqs[i], 1); if (drqs != NULL) - free(drqs, M_OFWPROP); + OF_prop_free(drqs); /* * Devices using DMA hang off of the `dma' node instead of @@ -267,7 +267,7 @@ isa_setup_children(device_t dev, phandle_t parent) if (strcmp(name, "dma") == 0) isa_setup_children(dev, node); - free(name, M_OFWPROP); + OF_prop_free(name); } } diff --git a/sys/sparc64/pci/ofw_pci.c b/sys/sparc64/pci/ofw_pci.c index 8babd49..9c8b46b 100644 --- a/sys/sparc64/pci/ofw_pci.c +++ b/sys/sparc64/pci/ofw_pci.c @@ -100,12 +100,12 @@ ofw_pci_attach_common(device_t dev, bus_dma_tag_t dmat, u_long iosize, if (sc->sc_pci_bh[j] != 0) { device_printf(dev, "duplicate range for space %d\n", j); - free(range, M_OFWPROP); + OF_prop_free(range); return (EINVAL); } sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); } - free(range, M_OFWPROP); + OF_prop_free(range); /* * Make sure that the expected ranges are actually present. diff --git a/sys/sparc64/sbus/dma_sbus.c b/sys/sparc64/sbus/dma_sbus.c index 4a83c92..217c5fb 100644 --- a/sys/sparc64/sbus/dma_sbus.c +++ b/sys/sparc64/sbus/dma_sbus.c @@ -216,7 +216,7 @@ dma_attach(device_t dev) csr &= ~E_TP_AUI; else csr |= E_TP_AUI; - free(cabletype, M_OFWPROP); + OF_prop_free(cabletype); } L64854_SCSR(lsc, csr); DELAY(20000); /* manual says we need a 20ms delay */ @@ -309,7 +309,7 @@ dma_setup_dinfo(device_t dev, struct dma_softc *dsc, phandle_t node) if (slot != -1 && slot != rslot) { device_printf(dev, "<%s>: multiple slots\n", ddi->ddi_obdinfo.obd_name); - free(reg, M_OFWPROP); + OF_prop_free(reg); goto fail; } slot = rslot; @@ -317,7 +317,7 @@ dma_setup_dinfo(device_t dev, struct dma_softc *dsc, phandle_t node) resource_list_add(&ddi->ddi_rl, SYS_RES_MEMORY, i, base, base + reg[i].sbr_size, reg[i].sbr_size); } - free(reg, M_OFWPROP); + OF_prop_free(reg); if (slot != dsc->sc_slot) { device_printf(dev, "<%s>: parent and child slot do not match\n", ddi->ddi_obdinfo.obd_name); @@ -343,7 +343,7 @@ dma_setup_dinfo(device_t dev, struct dma_softc *dsc, phandle_t node) resource_list_add(&ddi->ddi_rl, SYS_RES_IRQ, i, iv, iv, 1); } - free(intr, M_OFWPROP); + OF_prop_free(intr); } return (ddi); diff --git a/sys/sparc64/sbus/sbus.c b/sys/sparc64/sbus/sbus.c index 6d448f9..85ddf41 100644 --- a/sys/sparc64/sbus/sbus.c +++ b/sys/sparc64/sbus/sbus.c @@ -331,7 +331,7 @@ sbus_attach(device_t dev) sc->sc_rd[i].rd_pend = phys + size; sc->sc_rd[i].rd_res = res; } - free(range, M_OFWPROP); + OF_prop_free(range); /* * Get the SBus burst transfer size if burst transfers are supported. @@ -495,7 +495,7 @@ sbus_setup_dinfo(device_t dev, struct sbus_softc *sc, phandle_t node) if (slot != -1 && slot != rslot) { device_printf(dev, "<%s>: multiple slots\n", sdi->sdi_obdinfo.obd_name); - free(reg, M_OFWPROP); + OF_prop_free(reg); goto fail; } slot = rslot; @@ -503,7 +503,7 @@ sbus_setup_dinfo(device_t dev, struct sbus_softc *sc, phandle_t node) resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY, i, base, base + reg[i].sbr_size, reg[i].sbr_size); } - free(reg, M_OFWPROP); + OF_prop_free(reg); } sdi->sdi_slot = slot; @@ -525,7 +525,7 @@ sbus_setup_dinfo(device_t dev, struct sbus_softc *sc, phandle_t node) resource_list_add(&sdi->sdi_rl, SYS_RES_IRQ, i, iv, iv, 1); } - free(intr, M_OFWPROP); + OF_prop_free(intr); } if (OF_getprop(node, "burst-sizes", &sdi->sdi_burstsz, sizeof(sdi->sdi_burstsz)) == -1) diff --git a/sys/sparc64/sparc64/nexus.c b/sys/sparc64/sparc64/nexus.c index 3e72b6c..2c5ed92 100644 --- a/sys/sparc64/sparc64/nexus.c +++ b/sys/sparc64/sparc64/nexus.c @@ -559,7 +559,7 @@ nexus_setup_dinfo(device_t dev, phandle_t node) resource_list_add(&ndi->ndi_rl, SYS_RES_MEMORY, i, phys, phys + size - 1, size); } - free(reg, M_OFWPROP); + OF_prop_free(reg); nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intr), (void **)&intr); @@ -568,7 +568,7 @@ nexus_setup_dinfo(device_t dev, phandle_t node) "upa-portid" : "portid", &ign, sizeof(ign)) <= 0) { device_printf(dev, "<%s>: could not determine portid\n", ndi->ndi_obdinfo.obd_name); - free(intr, M_OFWPROP); + OF_prop_free(intr); goto fail; } @@ -579,7 +579,7 @@ nexus_setup_dinfo(device_t dev, phandle_t node) resource_list_add(&ndi->ndi_rl, SYS_RES_IRQ, i, intr[i], intr[i], 1); } - free(intr, M_OFWPROP); + OF_prop_free(intr); } return (ndi); diff --git a/sys/sparc64/sparc64/upa.c b/sys/sparc64/sparc64/upa.c index 34bc50f..e4699c4 100644 --- a/sys/sparc64/sparc64/upa.c +++ b/sys/sparc64/sparc64/upa.c @@ -560,7 +560,7 @@ upa_setup_dinfo(device_t dev, struct upa_softc *sc, phandle_t node, for (i = 0; i < nreg; i++) resource_list_add(&udi->udi_rl, SYS_RES_MEMORY, i, reg[i].phys, reg[i].phys + reg[i].size - 1, reg[i].size); - free(reg, M_OFWPROP); + OF_prop_free(reg); intr = INTMAP_VEC(sc->sc_ign, (UPA_INO_BASE + portid)); resource_list_add(&udi->udi_rl, SYS_RES_IRQ, 0, intr, intr, 1); diff --git a/sys/sys/_task.h b/sys/sys/_task.h index 11fd1bc..4cfa171 100644 --- a/sys/sys/_task.h +++ b/sys/sys/_task.h @@ -45,10 +45,21 @@ typedef void task_fn_t(void *context, int pending); struct task { STAILQ_ENTRY(task) ta_link; /* (q) link for queue */ - u_short ta_pending; /* (q) count times queued */ + uint8_t ta_pending; /* (q) count times queued */ + uint8_t ta_flags; /* (q) flags */ u_short ta_priority; /* (c) Priority */ task_fn_t *ta_func; /* (c) task handler */ void *ta_context; /* (c) argument for handler */ }; +struct grouptask { + struct task gt_task; + void *gt_taskqueue; + LIST_ENTRY(grouptask) gt_list; + void *gt_uniq; + char *gt_name; + int16_t gt_irq; + int16_t gt_cpu; +}; + #endif /* !_SYS__TASK_H_ */ diff --git a/sys/sys/_umtx.h b/sys/sys/_umtx.h index e8a400f..d94f86b 100644 --- a/sys/sys/_umtx.h +++ b/sys/sys/_umtx.h @@ -37,7 +37,11 @@ struct umutex { volatile __lwpid_t m_owner; /* Owner of the mutex */ __uint32_t m_flags; /* Flags of the mutex */ __uint32_t m_ceilings[2]; /* Priority protect ceiling */ - __uint32_t m_spare[4]; + __uintptr_t m_rb_lnk; /* Robust linkage */ +#ifndef __LP64__ + __uint32_t m_pad; +#endif + __uint32_t m_spare[2]; }; struct ucond { diff --git a/sys/sys/intr.h b/sys/sys/intr.h index 14267c4..3d75efd 100644 --- a/sys/sys/intr.h +++ b/sys/sys/intr.h @@ -110,7 +110,7 @@ bool intr_isrc_init_on_cpu(struct intr_irqsrc *isrc, u_int cpu); int intr_isrc_dispatch(struct intr_irqsrc *, struct trapframe *); u_int intr_irq_next_cpu(u_int current_cpu, cpuset_t *cpumask); -int intr_pic_register(device_t, intptr_t); +struct intr_pic *intr_pic_register(device_t, intptr_t); int intr_pic_deregister(device_t, intptr_t); int intr_pic_claim_root(device_t, intptr_t, intr_irq_filter_t *, void *, u_int); diff --git a/sys/sys/mbuf.h b/sys/sys/mbuf.h index 4a48d47..ca867ab 100644 --- a/sys/sys/mbuf.h +++ b/sys/sys/mbuf.h @@ -279,6 +279,8 @@ struct mbuf { #define M_PROTO11 0x00400000 /* protocol-specific */ #define M_PROTO12 0x00800000 /* protocol-specific */ +#define MB_DTOR_SKIP 0x1 /* don't pollute the cache by touching a freed mbuf */ + /* * Flags to purge when crossing layers. */ @@ -401,6 +403,7 @@ struct mbuf { */ #define EXT_FLAG_EMBREF 0x000001 /* embedded ext_count */ #define EXT_FLAG_EXTREF 0x000002 /* external ext_cnt, notyet */ + #define EXT_FLAG_NOFREE 0x000010 /* don't free mbuf to pool, notyet */ #define EXT_FLAG_VENDOR1 0x010000 /* for vendor-internal use */ diff --git a/sys/sys/proc.h b/sys/sys/proc.h index 35303fc..1cb34bf 100644 --- a/sys/sys/proc.h +++ b/sys/sys/proc.h @@ -282,6 +282,9 @@ struct thread { int td_no_sleeping; /* (k) Sleeping disabled count. */ int td_dom_rr_idx; /* (k) RR Numa domain selection. */ void *td_su; /* (k) FFS SU private */ + uintptr_t td_rb_list; /* (k) Robust list head. */ + uintptr_t td_rbp_list; /* (k) Robust priv list head. */ + uintptr_t td_rb_inact; /* (k) Current in-action mutex loc. */ #define td_endzero td_sigmask /* Copied during fork1() or create_thread(). */ diff --git a/sys/sys/socketvar.h b/sys/sys/socketvar.h index c675cfb..87b8a2a 100644 --- a/sys/sys/socketvar.h +++ b/sys/sys/socketvar.h @@ -335,7 +335,6 @@ struct uio; /* * From uipc_socket and friends */ -int sockargs(struct mbuf **mp, caddr_t buf, int buflen, int type); int getsockaddr(struct sockaddr **namp, caddr_t uaddr, size_t len); int getsock_cap(struct thread *td, int fd, cap_rights_t *rightsp, struct file **fpp, u_int *fflagp); diff --git a/sys/sys/taskqueue.h b/sys/sys/taskqueue.h index cfba472..432a75e 100644 --- a/sys/sys/taskqueue.h +++ b/sys/sys/taskqueue.h @@ -39,6 +39,7 @@ #include <sys/_cpuset.h> struct taskqueue; +struct taskqgroup; struct thread; struct timeout_task { @@ -96,6 +97,7 @@ void taskqueue_set_callback(struct taskqueue *queue, #define TASK_INITIALIZER(priority, func, context) \ { .ta_pending = 0, \ + .ta_flags = 0, \ .ta_priority = (priority), \ .ta_func = (func), \ .ta_context = (context) } @@ -111,6 +113,7 @@ void taskqueue_thread_enqueue(void *context); */ #define TASK_INIT(task, priority, func, context) do { \ (task)->ta_pending = 0; \ + (task)->ta_flags = 0; \ (task)->ta_priority = (priority); \ (task)->ta_func = (func); \ (task)->ta_context = (context); \ @@ -143,7 +146,7 @@ taskqueue_define_##name(void *arg) \ init; \ } \ \ -SYSINIT(taskqueue_##name, SI_SUB_CONFIGURE, SI_ORDER_SECOND, \ +SYSINIT(taskqueue_##name, SI_SUB_INIT_IF, SI_ORDER_SECOND, \ taskqueue_define_##name, NULL); \ \ struct __hack @@ -168,7 +171,7 @@ taskqueue_define_##name(void *arg) \ init; \ } \ \ -SYSINIT(taskqueue_##name, SI_SUB_CONFIGURE, SI_ORDER_SECOND, \ +SYSINIT(taskqueue_##name, SI_SUB_INIT_IF, SI_ORDER_SECOND, \ taskqueue_define_##name, NULL); \ \ struct __hack @@ -202,4 +205,63 @@ struct taskqueue *taskqueue_create_fast(const char *name, int mflags, taskqueue_enqueue_fn enqueue, void *context); +/* + * Taskqueue groups. Manages dynamic thread groups and irq binding for + * device and other tasks. + */ +int grouptaskqueue_enqueue(struct taskqueue *queue, struct task *task); +void taskqgroup_attach(struct taskqgroup *qgroup, struct grouptask *gtask, + void *uniq, int irq, char *name); +int taskqgroup_attach_cpu(struct taskqgroup *qgroup, struct grouptask *gtask, + void *uniq, int cpu, int irq, char *name); +void taskqgroup_detach(struct taskqgroup *qgroup, struct grouptask *gtask); +struct taskqgroup *taskqgroup_create(char *name); +void taskqgroup_destroy(struct taskqgroup *qgroup); +int taskqgroup_adjust(struct taskqgroup *qgroup, int cnt, int stride); + +#define TASK_SKIP_WAKEUP 0x1 + +#define GTASK_INIT(task, priority, func, context) do { \ + (task)->ta_pending = 0; \ + (task)->ta_flags = TASK_SKIP_WAKEUP; \ + (task)->ta_priority = (priority); \ + (task)->ta_func = (func); \ + (task)->ta_context = (context); \ +} while (0) + +#define GROUPTASK_INIT(gtask, priority, func, context) \ + GTASK_INIT(&(gtask)->gt_task, priority, func, context) + +#define GROUPTASK_ENQUEUE(gtask) \ + grouptaskqueue_enqueue((gtask)->gt_taskqueue, &(gtask)->gt_task) + +#define TASKQGROUP_DECLARE(name) \ +extern struct taskqgroup *qgroup_##name + +#define TASKQGROUP_DEFINE(name, cnt, stride) \ + \ +struct taskqgroup *qgroup_##name; \ + \ +static void \ +taskqgroup_define_##name(void *arg) \ +{ \ + qgroup_##name = taskqgroup_create(#name); \ +} \ + \ +SYSINIT(taskqgroup_##name, SI_SUB_INIT_IF, SI_ORDER_FIRST, \ + taskqgroup_define_##name, NULL); \ + \ +static void \ +taskqgroup_adjust_##name(void *arg) \ +{ \ + taskqgroup_adjust(qgroup_##name, (cnt), (stride)); \ +} \ + \ +SYSINIT(taskqgroup_adj_##name, SI_SUB_SMP, SI_ORDER_ANY, \ + taskqgroup_adjust_##name, NULL); \ + \ +struct __hack + +TASKQGROUP_DECLARE(net); + #endif /* !_SYS_TASKQUEUE_H_ */ diff --git a/sys/sys/umtx.h b/sys/sys/umtx.h index 325148c..d2ff5ac 100644 --- a/sys/sys/umtx.h +++ b/sys/sys/umtx.h @@ -32,13 +32,26 @@ #include <sys/_umtx.h> +/* Common lock flags */ #define USYNC_PROCESS_SHARED 0x0001 /* Process shared sync objs */ -#define UMUTEX_UNOWNED 0x0 -#define UMUTEX_CONTESTED 0x80000000U - +/* umutex flags */ #define UMUTEX_PRIO_INHERIT 0x0004 /* Priority inherited mutex */ #define UMUTEX_PRIO_PROTECT 0x0008 /* Priority protect mutex */ +#define UMUTEX_ROBUST 0x0010 /* Robust mutex */ +#define UMUTEX_NONCONSISTENT 0x0020 /* Robust locked but not consistent */ + +/* + * The umutex.m_lock values and bits. The m_owner is the word which + * serves as the lock. Its high bit is the contention indicator and + * rest of bits records the owner TID. TIDs values start with PID_MAX + * + 2 and end by INT32_MAX. The low range [1..PID_MAX] is guaranteed + * to be useable as the special markers. + */ +#define UMUTEX_UNOWNED 0x0 +#define UMUTEX_CONTESTED 0x80000000U +#define UMUTEX_RB_OWNERDEAD (UMUTEX_CONTESTED | 0x10) +#define UMUTEX_RB_NOTRECOV (UMUTEX_CONTESTED | 0x11) /* urwlock flags */ #define URWLOCK_PREFER_READER 0x0002 @@ -84,6 +97,7 @@ #define UMTX_OP_SEM2_WAIT 23 #define UMTX_OP_SEM2_WAKE 24 #define UMTX_OP_SHM 25 +#define UMTX_OP_ROBUST_LISTS 26 /* Flags for UMTX_OP_CV_WAIT */ #define CVWAIT_CHECK_UNPARKING 0x01 @@ -100,6 +114,12 @@ #define UMTX_SHM_DESTROY 0x0004 #define UMTX_SHM_ALIVE 0x0008 +struct umtx_robust_lists_params { + uintptr_t robust_list_offset; + uintptr_t robust_priv_list_offset; + uintptr_t robust_inact_offset; +}; + #ifndef _KERNEL int _umtx_op(void *obj, int op, u_long val, void *uaddr, void *uaddr2); @@ -122,6 +142,8 @@ enum { TYPE_RWLOCK, TYPE_FUTEX, TYPE_SHM, + TYPE_PI_ROBUST_UMUTEX, + TYPE_PP_ROBUST_UMUTEX, }; /* Key to represent a unique userland synchronous object */ diff --git a/sys/sys/vnode.h b/sys/sys/vnode.h index e82f6ee..41ec7f7 100644 --- a/sys/sys/vnode.h +++ b/sys/sys/vnode.h @@ -286,6 +286,7 @@ struct vattr { */ #define VA_UTIMES_NULL 0x01 /* utimes argument was NULL */ #define VA_EXCLUSIVE 0x02 /* exclusive create request */ +#define VA_SYNC 0x04 /* O_SYNC truncation */ /* * Flags for ioflag. (high 16 bits used to ask for read-ahead and diff --git a/sys/ufs/ffs/ffs_inode.c b/sys/ufs/ffs/ffs_inode.c index 0202820..50b456b 100644 --- a/sys/ufs/ffs/ffs_inode.c +++ b/sys/ufs/ffs/ffs_inode.c @@ -610,7 +610,7 @@ extclean: softdep_journal_freeblocks(ip, cred, length, IO_EXT); else softdep_setup_freeblocks(ip, length, IO_EXT); - return (ffs_update(vp, !DOINGASYNC(vp))); + return (ffs_update(vp, (flags & IO_SYNC) != 0 || !DOINGASYNC(vp))); } /* diff --git a/sys/ufs/ffs/ffs_vfsops.c b/sys/ufs/ffs/ffs_vfsops.c index c76683e..712fc21 100644 --- a/sys/ufs/ffs/ffs_vfsops.c +++ b/sys/ufs/ffs/ffs_vfsops.c @@ -512,7 +512,7 @@ ffs_mount(struct mount *mp) * We need the name for the mount point (also used for * "last mounted on") copied in. If an error occurs, * the mount point is discarded by the upper level code. - * Note that vfs_mount() populates f_mntonname for us. + * Note that vfs_mount_alloc() populates f_mntonname for us. */ if ((error = ffs_mountfs(devvp, mp, td)) != 0) { vrele(devvp); @@ -780,6 +780,8 @@ ffs_mountfs(devvp, mp, td) mp->mnt_iosize_max = MAXPHYS; devvp->v_bufobj.bo_ops = &ffs_ops; + if (devvp->v_type == VCHR) + devvp->v_rdev->si_mountpt = mp; fs = NULL; sblockloc = 0; @@ -1049,8 +1051,6 @@ ffs_mountfs(devvp, mp, td) ffs_flushfiles(mp, FORCECLOSE, td); goto out; } - if (devvp->v_type == VCHR && devvp->v_rdev != NULL) - devvp->v_rdev->si_mountpt = mp; if (fs->fs_snapinum[0] != 0) ffs_snapshot_mount(mp); fs->fs_fmod = 1; @@ -1058,7 +1058,7 @@ ffs_mountfs(devvp, mp, td) (void) ffs_sbupdate(ump, MNT_WAIT, 0); } /* - * Initialize filesystem stat information in mount struct. + * Initialize filesystem state information in mount struct. */ MNT_ILOCK(mp); mp->mnt_kern_flag |= MNTK_LOOKUP_SHARED | MNTK_EXTENDED_SHARED | @@ -1083,6 +1083,8 @@ ffs_mountfs(devvp, mp, td) out: if (bp) brelse(bp); + if (devvp->v_type == VCHR && devvp->v_rdev != NULL) + devvp->v_rdev->si_mountpt = NULL; if (cp != NULL) { DROP_GIANT(); g_topology_lock(); diff --git a/sys/ufs/ufs/ufs_lookup.c b/sys/ufs/ufs/ufs_lookup.c index c6769cd..53536ff 100644 --- a/sys/ufs/ufs/ufs_lookup.c +++ b/sys/ufs/ufs/ufs_lookup.c @@ -1131,9 +1131,9 @@ ufs_direnter(dvp, tvp, dirp, cnp, newdirbp, isrename) if (tvp != NULL) VOP_UNLOCK(tvp, 0); error = UFS_TRUNCATE(dvp, (off_t)dp->i_endoff, - IO_NORMAL | IO_SYNC, cr); + IO_NORMAL | (DOINGASYNC(dvp) ? 0 : IO_SYNC), cr); if (error != 0) - vprint("ufs_direnter: failted to truncate", dvp); + vprint("ufs_direnter: failed to truncate", dvp); #ifdef UFS_DIRHASH if (error == 0 && dp->i_dirhash != NULL) ufsdirhash_dirtrunc(dp, dp->i_endoff); diff --git a/sys/ufs/ufs/ufs_vnops.c b/sys/ufs/ufs/ufs_vnops.c index c0729f8..83df347 100644 --- a/sys/ufs/ufs/ufs_vnops.c +++ b/sys/ufs/ufs/ufs_vnops.c @@ -625,7 +625,8 @@ ufs_setattr(ap) */ return (0); } - if ((error = UFS_TRUNCATE(vp, vap->va_size, IO_NORMAL, + if ((error = UFS_TRUNCATE(vp, vap->va_size, IO_NORMAL | + ((vap->va_vaflags & VA_SYNC) != 0 ? IO_SYNC : 0), cred)) != 0) return (error); } diff --git a/sys/vm/vm_object.c b/sys/vm/vm_object.c index 4a0479b..cf6eda8 100644 --- a/sys/vm/vm_object.c +++ b/sys/vm/vm_object.c @@ -476,7 +476,7 @@ vm_object_vndeallocate(vm_object_t object) } #endif - if (object->ref_count == 1) + if (!umtx_shm_vnobj_persistent && object->ref_count == 1) umtx_shm_object_terminated(object); /* diff --git a/sys/vm/vm_object.h b/sys/vm/vm_object.h index c68fdce..cfc583b 100644 --- a/sys/vm/vm_object.h +++ b/sys/vm/vm_object.h @@ -300,6 +300,7 @@ vm_object_cache_is_empty(vm_object_t object) void umtx_shm_object_init(vm_object_t object); void umtx_shm_object_terminated(vm_object_t object); +extern int umtx_shm_vnobj_persistent; vm_object_t vm_object_allocate (objtype_t, vm_pindex_t); boolean_t vm_object_coalesce(vm_object_t, vm_ooffset_t, vm_size_t, vm_size_t, diff --git a/sys/vm/vnode_pager.c b/sys/vm/vnode_pager.c index f39afc2..cc43976 100644 --- a/sys/vm/vnode_pager.c +++ b/sys/vm/vnode_pager.c @@ -164,6 +164,7 @@ vnode_destroy_vobject(struct vnode *vp) return; ASSERT_VOP_ELOCKED(vp, "vnode_destroy_vobject"); VM_OBJECT_WLOCK(obj); + umtx_shm_object_terminated(obj); if (obj->ref_count == 0) { /* * don't double-terminate the object diff --git a/sys/xen/interface/io/blkif.h b/sys/xen/interface/io/blkif.h index 8f0f9a6..0d50d77 100644 --- a/sys/xen/interface/io/blkif.h +++ b/sys/xen/interface/io/blkif.h @@ -324,7 +324,7 @@ * access (even when it should be read-only). If the frontend hits the * maximum number of allowed persistently mapped grants, it can fallback * to non persistent mode. This will cause a performance degradation, - * since the the backend driver will still try to map those grants + * since the backend driver will still try to map those grants * persistently. Since the persistent grants protocol is compatible with * the previous protocol, a frontend driver can choose to work in * persistent mode even when the backend doesn't support it. diff --git a/targets/Makefile b/targets/Makefile index b5be7d2..8040953 100644 --- a/targets/Makefile +++ b/targets/Makefile @@ -1,6 +1,6 @@ # $FreeBSD$ -# This is the top-level makefile - derrived from the Junos version +# This is the top-level makefile - derived from the Junos version # # If a subdir that matches the requested target exists, we assume # a build target and initialize DIRDEPS, dirdeps.mk does the rest. diff --git a/tools/tools/nanobsd/defaults.sh b/tools/tools/nanobsd/defaults.sh index a69ad8b..44b64cd 100755 --- a/tools/tools/nanobsd/defaults.sh +++ b/tools/tools/nanobsd/defaults.sh @@ -195,7 +195,7 @@ NANO_DATADIR="" # in case they are stray in the build environment SRCCONF=/dev/null SRC_ENV_CONF=/dev/null - + ####################################################################### # # The functions which do the real work. @@ -319,7 +319,7 @@ make_conf_build ( ) ( # in addition to the user's global settings ( nano_global_make_env - echo "${CONF_WORLD}" + echo "${CONF_WORLD}" echo "${CONF_BUILD}" ) > ${NANO_MAKE_CONF_BUILD} ) @@ -429,7 +429,7 @@ install_kernel ( ) ( ( nano_make_install_env - nano_make_kernel_env + nano_make_kernel_env if [ "${NANO_MODULES}" != "default" ]; then MODULES_OVERRIDE="${NANO_MODULES}" @@ -465,7 +465,7 @@ run_early_customize() { pprint 2 "run early customize scripts" for c in $NANO_EARLY_CUSTOMIZE - do + do pprint 2 "early customize \"$c\"" pprint 3 "log: ${NANO_LOG}/_.early_cust.$c" pprint 4 "`type $c`" @@ -529,7 +529,7 @@ fixup_before_diskimage ( ) ( echo "/set uname=${NANO_DEF_UNAME} gname=${NANO_DEF_GNAME}" > ${NANO_METALOG} cat ${NANO_METALOG}.pre | ${NANO_TOOLS}/mtree-dedup.awk | \ sed -e 's/ size=[0-9][0-9]*//' | sort >> ${NANO_METALOG} - fi + fi ) setup_nanobsd ( ) ( @@ -603,11 +603,11 @@ setup_nanobsd_etc ( ) ( prune_usr ( ) ( - # Remove all empty directories in /usr + # Remove all empty directories in /usr find "${NANO_WORLDDIR}"/usr -type d -depth -print | while read d do - rmdir $d > /dev/null 2>&1 || true + rmdir $d > /dev/null 2>&1 || true done ) @@ -676,7 +676,7 @@ create_diskimage ( ) ( else print "g c" 1023 " h" $4 " s" $3 - if ($7 > 0) { + if ($7 > 0) { # size of data partition in full cylinders dsl = int (($7 + cs - 1) / cs) } else { @@ -697,7 +697,7 @@ create_diskimage ( ) ( print "p 1 165 " $3, isl * cs - $3 c = isl * cs; - # Second image partition (if any) also starts offset one + # Second image partition (if any) also starts offset one # track to keep them identical. if ($2 > 1) { print "p 2 165 " $3 + c, isl * cs - $3 @@ -780,7 +780,7 @@ create_diskimage ( ) ( tunefs -L ${NANO_LABEL}"${NANO_ALTROOT}" /dev/${MD}${NANO_ALTROOT} fi fi - + # Create Config slice populate_cfg_slice /dev/${MD}${NANO_SLICE_CFG} "${NANO_CFGDIR}" ${MNT} "${NANO_SLICE_CFG}" @@ -1018,10 +1018,11 @@ pprint ( ) ( usage ( ) { ( - echo "Usage: $0 [-bfiKknqvw] [-c config_file]" + echo "Usage: $0 [-bfhiKknqvwX] [-c config_file]" echo " -b suppress builds (both kernel and world)" echo " -c specify config file" echo " -f suppress code slice extraction" + echo " -h print this help summary page" echo " -i suppress disk image build" echo " -K suppress installkernel" echo " -k suppress buildkernel" @@ -1029,6 +1030,7 @@ usage ( ) { echo " -q make output more quiet" echo " -v make output more verbose" echo " -w suppress buildworld" + echo " -X make native-xtools" ) 1>&2 exit 2 } diff --git a/tools/tools/nanobsd/nanobsd.sh b/tools/tools/nanobsd/nanobsd.sh index f140a76..02c84cd 100755 --- a/tools/tools/nanobsd/nanobsd.sh +++ b/tools/tools/nanobsd/nanobsd.sh @@ -55,7 +55,7 @@ set -e set -- $args for i do - case "$i" + case "$i" in -K) do_installkernel=false diff --git a/usr.bin/chat/chat.c b/usr.bin/chat/chat.c index d62e47a..107d951 100644 --- a/usr.bin/chat/chat.c +++ b/usr.bin/chat/chat.c @@ -521,7 +521,7 @@ void terminate(int status) size_t rep_len; rep_len = strlen(report_buffer); - while (rep_len + 1 <= sizeof(report_buffer)) { + while (rep_len + 1 < sizeof(report_buffer)) { alarm(1); c = get_char(); alarm(0); diff --git a/usr.bin/kdump/kdump.c b/usr.bin/kdump/kdump.c index abda217..439b90c 100644 --- a/usr.bin/kdump/kdump.c +++ b/usr.bin/kdump/kdump.c @@ -298,8 +298,9 @@ main(int argc, char *argv[]) m = malloc(size = 1025); if (m == NULL) errx(1, "%s", strerror(ENOMEM)); - if (!freopen(tracefile, "r", stdin)) - err(1, "%s", tracefile); + if (strcmp(tracefile, "-") != 0) + if (!freopen(tracefile, "r", stdin)) + err(1, "%s", tracefile); strerror_init(); localtime_init(); diff --git a/usr.bin/ldd/ldd.c b/usr.bin/ldd/ldd.c index cc3a769..e1bebe0 100644 --- a/usr.bin/ldd/ldd.c +++ b/usr.bin/ldd/ldd.c @@ -88,7 +88,7 @@ static void usage(void); static int execldd32(char *file, char *fmt1, char *fmt2, int aflag, int vflag) { - char *argv[8]; + char *argv[9]; int i, rval, status; LDD_UNSETENV("TRACE_LOADED_OBJECTS"); diff --git a/usr.bin/ncal/ncal.c b/usr.bin/ncal/ncal.c index 48b8c1a..5a5cbc3 100644 --- a/usr.bin/ncal/ncal.c +++ b/usr.bin/ncal/ncal.c @@ -642,8 +642,8 @@ monthrangeb(int y, int m, int jd_flag, int before, int after) wprintf(L"%-*ls ", mw, wcenter(ws, year[i].name, mw)); else { - swprintf(ws, sizeof(ws), L"%-ls %d", - year[i].name, M2Y(m + i)); + swprintf(ws, sizeof(ws)/sizeof(ws[0]), + L"%-ls %d", year[i].name, M2Y(m + i)); wprintf(L"%-*ls ", mw, wcenter(ws1, ws, mw)); } printf("\n"); @@ -958,7 +958,7 @@ mkweekdays(struct weekdays *wds) for (i = 0; i != 7; i++) { tm.tm_wday = (i+1) % 7; - wcsftime(buf, sizeof(buf), L"%a", &tm); + wcsftime(buf, sizeof(buf)/sizeof(buf[0]), L"%a", &tm); for (len = 2; len > 0; --len) { if ((width = wcswidth(buf, len)) <= 2) break; diff --git a/usr.bin/numactl/numactl.1 b/usr.bin/numactl/numactl.1 index 750e23b..15c50d7 100644 --- a/usr.bin/numactl/numactl.1 +++ b/usr.bin/numactl/numactl.1 @@ -83,7 +83,7 @@ The options are as follows: .Bl -tag -width ".Fl -cpudomain Ar domain" .It Fl -cpudomain Ar domain , Fl c Ar domain Set the given CPU scheduling policy. -Constrain the the object (tid, pid, command) to run on CPUs +Constrain the object (tid, pid, command) to run on CPUs that belong to the given domain. .It Fl -get , Fl g Retrieve the NUMA policy for the given thread or process id. diff --git a/usr.bin/xinstall/tests/install_test.sh b/usr.bin/xinstall/tests/install_test.sh index 9a9c69f..24a8a4d 100755 --- a/usr.bin/xinstall/tests/install_test.sh +++ b/usr.bin/xinstall/tests/install_test.sh @@ -64,12 +64,6 @@ copy_to_nonexistent_backup_safe_body() { copy_to_nonexistent_with_opts -b -B.bak -S } -atf_test_case copy_to_nonexistent_preserving -copy_to_nonexistent_preserving_body() { - copy_to_nonexistent_with_opts -p - [ ! testf -ot copyf ] || atf_fail "bad timestamp 2" -} - copy_self_with_opts() { printf 'test\n123\r456\r\n789\0z' >testf printf 'test\n123\r456\r\n789\0z' >testf2 @@ -313,7 +307,6 @@ atf_init_test_cases() { atf_add_test_case copy_to_nonexistent_safe_comparing atf_add_test_case copy_to_nonexistent_backup atf_add_test_case copy_to_nonexistent_backup_safe - atf_add_test_case copy_to_nonexistent_preserving atf_add_test_case copy_self atf_add_test_case copy_self_safe atf_add_test_case copy_self_comparing diff --git a/usr.bin/xinstall/xinstall.c b/usr.bin/xinstall/xinstall.c index 5e05ba8..1121cff 100644 --- a/usr.bin/xinstall/xinstall.c +++ b/usr.bin/xinstall/xinstall.c @@ -131,7 +131,7 @@ static void do_symlink(const char *, const char *, const struct stat *); static void makelink(const char *, const char *, const struct stat *); static void install(const char *, const char *, u_long, u_int); static void install_dir(char *); -static void metadata_log(const char *, const char *, struct timespec *, +static void metadata_log(const char *, const char *, struct timeval *, const char *, const char *, off_t); static int parseid(const char *, id_t *); static void strip(const char *); @@ -722,7 +722,7 @@ static void install(const char *from_name, const char *to_name, u_long fset, u_int flags) { struct stat from_sb, temp_sb, to_sb; - struct timespec tsb[2]; + struct timeval tvb[2]; int devnull, files_match, from_fd, serrno, target; int tempcopy, temp_fd, to_fd; char backup[MAXPATHLEN], *p, pathbuf[MAXPATHLEN], tempfile[MAXPATHLEN]; @@ -857,9 +857,11 @@ install(const char *from_name, const char *to_name, u_long fset, u_int flags) * Need to preserve target file times, though. */ if (to_sb.st_nlink != 1) { - tsb[0] = to_sb.st_atim; - tsb[1] = to_sb.st_mtim; - (void)utimensat(AT_FDCWD, tempfile, tsb, 0); + tvb[0].tv_sec = to_sb.st_atime; + tvb[0].tv_usec = 0; + tvb[1].tv_sec = to_sb.st_mtime; + tvb[1].tv_usec = 0; + (void)utimes(tempfile, tvb); } else { files_match = 1; (void)unlink(tempfile); @@ -914,9 +916,11 @@ install(const char *from_name, const char *to_name, u_long fset, u_int flags) * Preserve the timestamp of the source file if necessary. */ if (dopreserve && !files_match && !devnull) { - tsb[0] = from_sb.st_atim; - tsb[1] = from_sb.st_mtim; - (void)utimensat(AT_FDCWD, to_name, tsb, 0); + tvb[0].tv_sec = from_sb.st_atime; + tvb[0].tv_usec = 0; + tvb[1].tv_sec = from_sb.st_mtime; + tvb[1].tv_usec = 0; + (void)utimes(to_name, tvb); } if (fstat(to_fd, &to_sb) == -1) { @@ -985,7 +989,7 @@ install(const char *from_name, const char *to_name, u_long fset, u_int flags) if (!devnull) (void)close(from_fd); - metadata_log(to_name, "file", tsb, NULL, digestresult, to_sb.st_size); + metadata_log(to_name, "file", tvb, NULL, digestresult, to_sb.st_size); free(digestresult); } @@ -1297,7 +1301,7 @@ again: * or to allow integrity checks to be performed. */ static void -metadata_log(const char *path, const char *type, struct timespec *ts, +metadata_log(const char *path, const char *type, struct timeval *tv, const char *slink, const char *digestresult, off_t size) { static const char extra[] = { ' ', '\t', '\n', '\\', '#', '\0' }; @@ -1351,9 +1355,9 @@ metadata_log(const char *path, const char *type, struct timespec *ts, } if (*type == 'f') /* type=file */ fprintf(metafp, " size=%lld", (long long)size); - if (ts != NULL && dopreserve) - fprintf(metafp, " time=%lld.%09ld", - (long long)ts[1].tv_sec, ts[1].tv_nsec); + if (tv != NULL && dopreserve) + fprintf(metafp, " time=%lld.%ld", + (long long)tv[1].tv_sec, (long)tv[1].tv_usec); if (digestresult && digest) fprintf(metafp, " %s=%s", digest, digestresult); if (fflags) diff --git a/usr.sbin/bsdconfig/share/dialog.subr b/usr.sbin/bsdconfig/share/dialog.subr index 17e7b4a..a802efe 100644 --- a/usr.sbin/bsdconfig/share/dialog.subr +++ b/usr.sbin/bsdconfig/share/dialog.subr @@ -1815,7 +1815,7 @@ f_dialog_inputstr_fetch() # f_dialog_input $var_to_set $prompt [$init [$hline]] # # Prompt the user with a dialog(1) inputbox to enter some value. The inputbox -# remains until the the user presses ENTER or ESC, or otherwise ends the +# remains until the user presses ENTER or ESC, or otherwise ends the # editing session (by selecting `Cancel' for example). # # If the user presses ENTER, the exit status is zero (success), otherwise if diff --git a/usr.sbin/bsnmpd/bsnmpd/Makefile b/usr.sbin/bsnmpd/bsnmpd/Makefile index 1cf4a8b..e4106e0 100644 --- a/usr.sbin/bsnmpd/bsnmpd/Makefile +++ b/usr.sbin/bsnmpd/bsnmpd/Makefile @@ -47,6 +47,7 @@ MANFILTER= sed -e 's%@MODPATH@%${LIBDIR}/%g' \ -e 's%@DEFPATH@%${DEFSDIR}/%g' \ -e 's%@MIBSPATH@%${BMIBSDIR}/%g' +NO_WCAST_ALIGN= yes WARNS?= 6 .include <bsd.prog.mk> diff --git a/usr.sbin/iscsid/login.c b/usr.sbin/iscsid/login.c index ed0b9bf..6abb9d6 100644 --- a/usr.sbin/iscsid/login.c +++ b/usr.sbin/iscsid/login.c @@ -422,8 +422,38 @@ login_negotiate_key(struct connection *conn, const char *name, /* Ignore */ } else if (strcmp(name, "IFMarker") == 0) { /* Ignore */ + } else if (strcmp(name, "RDMAExtensions") == 0) { + if (conn->conn_conf.isc_iser == 1 && + strcmp(value, "Yes") != 0) { + log_errx(1, "received unsupported RDMAExtensions"); + } + } else if (strcmp(name, "InitiatorRecvDataSegmentLength") == 0) { + tmp = strtoul(value, NULL, 10); + if (tmp <= 0) + log_errx(1, "received invalid " + "InitiatorRecvDataSegmentLength"); + if ((size_t)tmp > conn->conn_limits.isl_max_data_segment_length) { + log_debugx("capping InitiatorRecvDataSegmentLength " + "from %d to %zd", tmp, + conn->conn_limits.isl_max_data_segment_length); + tmp = conn->conn_limits.isl_max_data_segment_length; + } + conn->conn_max_data_segment_length = tmp; } else if (strcmp(name, "TargetPortalGroupTag") == 0) { /* Ignore */ + } else if (strcmp(name, "TargetRecvDataSegmentLength") == 0) { + tmp = strtoul(value, NULL, 10); + if (tmp <= 0) { + log_errx(1, + "received invalid TargetRecvDataSegmentLength"); + } + if ((size_t)tmp > conn->conn_limits.isl_max_data_segment_length) { + log_debugx("capping TargetRecvDataSegmentLength " + "from %d to %zd", tmp, + conn->conn_limits.isl_max_data_segment_length); + tmp = conn->conn_limits.isl_max_data_segment_length; + } + conn->conn_max_data_segment_length = tmp; } else { log_debugx("unknown key \"%s\"; ignoring", name); } @@ -465,13 +495,23 @@ login_negotiate(struct connection *conn) conn->conn_limits.isl_max_data_segment_length); keys_add(request_keys, "InitialR2T", "Yes"); keys_add(request_keys, "MaxOutstandingR2T", "1"); + if (conn->conn_conf.isc_iser == 1) { + keys_add_int(request_keys, "InitiatorRecvDataSegmentLength", + conn->conn_limits.isl_max_data_segment_length); + keys_add_int(request_keys, "TargetRecvDataSegmentLength", + conn->conn_limits.isl_max_data_segment_length); + keys_add(request_keys, "RDMAExtensions", "Yes"); + } else { + keys_add_int(request_keys, "MaxRecvDataSegmentLength", + conn->conn_limits.isl_max_data_segment_length); + } } else { keys_add(request_keys, "HeaderDigest", "None"); keys_add(request_keys, "DataDigest", "None"); + keys_add_int(request_keys, "MaxRecvDataSegmentLength", + conn->conn_limits.isl_max_data_segment_length); } - keys_add_int(request_keys, "MaxRecvDataSegmentLength", - conn->conn_limits.isl_max_data_segment_length); keys_add(request_keys, "DefaultTime2Wait", "0"); keys_add(request_keys, "DefaultTime2Retain", "0"); keys_add(request_keys, "ErrorRecoveryLevel", "0"); diff --git a/usr.sbin/makefs/cd9660.c b/usr.sbin/makefs/cd9660.c index e05e52a..3f55b8d 100644 --- a/usr.sbin/makefs/cd9660.c +++ b/usr.sbin/makefs/cd9660.c @@ -685,6 +685,9 @@ cd9660_finalize_PVD(void) cd9660_time_8426( (unsigned char *)diskStructure.primaryDescriptor.effective_date, tim); + /* make this sane */ + cd9660_time_915(diskStructure.rootNode->dot_record->isoDirRecord->date, + tim); } static void @@ -774,7 +777,7 @@ cd9660_setup_volume_descriptors(void) temp->next = t; memset(t->volumeDescriptorData, 0, 2048); t->volumeDescriptorData[0] = ISO_VOLUME_DESCRIPTOR_TERMINATOR; - t->next = 0; + t->next = NULL; t->volumeDescriptorData[6] = 1; t->sector = sector; memcpy(t->volumeDescriptorData + 1, @@ -1403,7 +1406,7 @@ cd9660_convert_structure(fsnode *root, cd9660node *parent_node, int level, this_node->level = working_level - 1; if (cd9660_rrip_move_directory( - this_node) == 0) { + this_node) == NULL) { warnx("Failure in " "cd9660_rrip_" "move_directory" @@ -1416,7 +1419,7 @@ cd9660_convert_structure(fsnode *root, cd9660node *parent_node, int level, } /* Do the recursive call on the children */ - if (iterator->child != 0) { + if (iterator->child != NULL) { cd9660_convert_structure( iterator->child, this_node, working_level, @@ -1445,7 +1448,7 @@ cd9660_convert_structure(fsnode *root, cd9660node *parent_node, int level, } /*Allocate new temp_node */ - if (iterator->next != 0) { + if (iterator->next != NULL) { this_node = cd9660_allocate_cd9660node(); if (this_node == NULL) CD9660_MEM_ALLOC_ERROR(__func__); @@ -1733,7 +1736,7 @@ cd9660_convert_filename(const char *oldname, char *newname, int is_file) { assert(1 <= diskStructure.isoLevel && diskStructure.isoLevel <= 2); /* NEW */ - cd9660_filename_conversion_functor conversion_function = 0; + cd9660_filename_conversion_functor conversion_function = NULL; if (diskStructure.isoLevel == 1) conversion_function = &cd9660_level1_convert_filename; else if (diskStructure.isoLevel == 2) diff --git a/usr.sbin/makefs/ffs.c b/usr.sbin/makefs/ffs.c index dd97c01..dc749dc 100644 --- a/usr.sbin/makefs/ffs.c +++ b/usr.sbin/makefs/ffs.c @@ -1125,9 +1125,13 @@ ffs_write_inode(union dinode *dp, uint32_t ino, const fsinfo_t *fsopts) initediblk < ufs_rw32(cgp->cg_niblk, fsopts->needswap)) { memset(buf, 0, fs->fs_bsize); dip = (struct ufs2_dinode *)buf; + /* + * XXX: Time-based seeds should be avoided for + * reproduceable builds. + */ srandom(time(NULL)); for (i = 0; i < INOPB(fs); i++) { - dip->di_gen = random() / 2 + 1; + dip->di_gen = random(); dip++; } ffs_wtfs(fsbtodb(fs, ino_to_fsba(fs, diff --git a/usr.sbin/makefs/mtree.c b/usr.sbin/makefs/mtree.c index 8a687bf..532b9e4 100644 --- a/usr.sbin/makefs/mtree.c +++ b/usr.sbin/makefs/mtree.c @@ -150,7 +150,7 @@ mtree_file_path(fsnode *node) depth = 0; rp[depth] = node->name; - for (pnode = node->parent; pnode && depth < MAKEFS_MAX_TREE_DEPTH; + for (pnode = node->parent; pnode && depth < MAKEFS_MAX_TREE_DEPTH - 1; pnode = pnode->parent) { if (strcmp(pnode->name, ".") == 0) break; diff --git a/usr.sbin/pciconf/pciconf.8 b/usr.sbin/pciconf/pciconf.8 index 705b594..f0f47b8 100644 --- a/usr.sbin/pciconf/pciconf.8 +++ b/usr.sbin/pciconf/pciconf.8 @@ -237,7 +237,7 @@ prefix indicates if the keyword is read-only or read-write .Dq rw . The second string provides the keyword name. -The text after the the equals sign lists the value of the keyword which is +The text after the equals sign lists the value of the keyword which is usually an ASCII string. .Pp If the optional diff --git a/usr.sbin/ppp/link.c b/usr.sbin/ppp/link.c index dc5507d..f802b95 100644 --- a/usr.sbin/ppp/link.c +++ b/usr.sbin/ppp/link.c @@ -209,7 +209,7 @@ static struct protostatheader { { PROTO_LQR, "LQR" }, { PROTO_CHAP, "CHAP" }, { PROTO_MP, "MULTILINK" }, - { 0, "Others" } + { 0, "Others" } /* must be last */ }; void @@ -218,13 +218,13 @@ link_ProtocolRecord(struct link *l, u_short proto, int type) int i; for (i = 0; i < NPROTOSTAT; i++) - if (ProtocolStat[i].number == proto) + if (ProtocolStat[i].number == proto || ProtocolStat[i].number == 0) { + if (type == PROTO_IN) + l->proto_in[i]++; + else + l->proto_out[i]++; break; - - if (type == PROTO_IN) - l->proto_in[i]++; - else - l->proto_out[i]++; + } } void diff --git a/usr.sbin/rarpd/rarpd.c b/usr.sbin/rarpd/rarpd.c index 74f7940..2bb333c 100644 --- a/usr.sbin/rarpd/rarpd.c +++ b/usr.sbin/rarpd/rarpd.c @@ -739,7 +739,7 @@ update_arptab(u_char *ep, in_addr_t ipaddr) /* Get the type and interface index */ rt = &rtmsg.rthdr; - bzero(rt, sizeof(rtmsg)); + bzero(&rtmsg, sizeof(rtmsg)); rt->rtm_version = RTM_VERSION; rt->rtm_addrs = RTA_DST; rt->rtm_type = RTM_GET; diff --git a/usr.sbin/rpc.lockd/lock_proc.c b/usr.sbin/rpc.lockd/lock_proc.c index 8884ad9..595d625 100644 --- a/usr.sbin/rpc.lockd/lock_proc.c +++ b/usr.sbin/rpc.lockd/lock_proc.c @@ -112,7 +112,7 @@ log_netobj(netobj *obj) } /* Prevent the security hazard from the buffer overflow */ maxlen = (obj->n_len < MAX_NETOBJ_SZ ? obj->n_len : MAX_NETOBJ_SZ); - for (i=0, tmp1 = objvalbuffer, tmp2 = objascbuffer; i < obj->n_len; + for (i=0, tmp1 = objvalbuffer, tmp2 = objascbuffer; i < maxlen; i++, tmp1 +=2, tmp2 +=1) { sprintf(tmp1,"%02X",*(obj->n_bytes+i)); sprintf(tmp2,"%c",*(obj->n_bytes+i)); diff --git a/usr.sbin/rpc.statd/file.c b/usr.sbin/rpc.statd/file.c index 0625e30..beef0e4 100644 --- a/usr.sbin/rpc.statd/file.c +++ b/usr.sbin/rpc.statd/file.c @@ -82,6 +82,7 @@ HostInfo *find_host(char *hostname, int create) struct addrinfo *ai1, *ai2; int i; + ai2 = NULL; if (getaddrinfo(hostname, NULL, NULL, &ai1) != 0) ai1 = NULL; for (i = 0, hp = status_info->hosts; i < status_info->noOfHosts; i++, hp++) @@ -91,7 +92,7 @@ HostInfo *find_host(char *hostname, int create) result = hp; break; } - if (hp->hostname[0] && + if (hp->hostname[0] != '\0' && getaddrinfo(hp->hostname, NULL, NULL, &ai2) != 0) ai2 = NULL; if (ai1 && ai2) @@ -113,8 +114,10 @@ HostInfo *find_host(char *hostname, int create) if (result) break; } - if (ai2) + if (ai2) { freeaddrinfo(ai2); + ai2 = NULL; + } if (!spare_slot && !hp->monList && !hp->notifyReqd) spare_slot = hp; } @@ -134,9 +137,8 @@ HostInfo *find_host(char *hostname, int create) if (desired_size > status_file_len) { /* Extend file by writing 1 byte of junk at the desired end pos */ - lseek(status_fd, desired_size - 1, SEEK_SET); - i = write(status_fd, &i, 1); - if (i < 1) + if (lseek(status_fd, desired_size - 1, SEEK_SET) == -1 || + write(status_fd, "\0", 1) < 0) { syslog(LOG_ERR, "Unable to extend status file"); return (NULL); |
