diff options
| -rw-r--r-- | sys/dev/aic7xxx/aic7xxx.seq | 19 | ||||
| -rw-r--r-- | sys/dev/aic7xxx/aic7xxx_reg.h | 12 |
2 files changed, 21 insertions, 10 deletions
diff --git a/sys/dev/aic7xxx/aic7xxx.seq b/sys/dev/aic7xxx/aic7xxx.seq index 1aa154c..d9c1365 100644 --- a/sys/dev/aic7xxx/aic7xxx.seq +++ b/sys/dev/aic7xxx/aic7xxx.seq @@ -41,7 +41,7 @@ * *-M************************************************************************/ -VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.24 1995/11/07 05:31:28 gibbs Exp $" +VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.26 1996/01/05 16:11:49 gibbs Exp $" #include "../../dev/aic7xxx/aic7xxx_reg.h" @@ -507,13 +507,18 @@ p_mesgout_start: * a MESSAGE REJECT. */ p_mesgout_loop: + test SSTAT1,PHASEMIS jnz p_mesgout_phasemis test SSTAT0,SPIORDY jz p_mesgout_loop cmp DINDEX,1 jne p_mesgout_outb /* last byte? */ mvi CLRSINT1,CLRATNO /* drop ATN */ p_mesgout_outb: - test SSTAT1,PHASEMIS jnz p_mesgout_phasemis + or SXFRCTL0, CLRSTCNT + mvi STCNT0, 1 dec DINDEX mov SCSIDATL,SINDIR +p_mesgout_outb_wait: + test SSTAT0,SDONE jz p_mesgout_outb_wait + p_mesgout4: test DINDEX,0xff jnz p_mesgout_loop @@ -881,23 +886,19 @@ mk_mesg1: inb_next: call inb_last -inb_next_wait: - test SSTAT1,PHASEMIS jnz mesgin_phasemis - test SSTAT0,SPIORDY jz inb_next_wait /* wait for next byte */ inb_first: + test SSTAT1,PHASEMIS jnz mesgin_phasemis + test SSTAT0,SPIORDY jz inb_first /* wait for next byte */ mov DINDEX,SINDEX mov DINDIR,SCSIBUSL ret /*read byte directly from bus*/ inb_last: - clr STCNT2 - clr STCNT1 + or SXFRCTL0,CLRSTCNT mvi STCNT0,0x01 mov NONE,SCSIDATL /*dummy read from latch to ACK*/ inb_last_wait: test SSTAT0,SDONE jz inb_last_wait /* Wait for completion */ ret - - mesgin_phasemis: /* * We expected to receive another byte, but the target changed phase diff --git a/sys/dev/aic7xxx/aic7xxx_reg.h b/sys/dev/aic7xxx/aic7xxx_reg.h index 5dae1dd..bbe2b5a 100644 --- a/sys/dev/aic7xxx/aic7xxx_reg.h +++ b/sys/dev/aic7xxx/aic7xxx_reg.h @@ -18,7 +18,7 @@ * 4. Modifications may be freely made to this file if the above conditions * are met. * - * $Id: aic7xxx_reg.h,v 1.1 1995/11/05 04:37:25 gibbs Exp $ + * $Id: aic7xxx_reg.h,v 1.2 1996/01/03 06:25:32 gibbs Exp $ */ /* @@ -356,6 +356,16 @@ #define ENABLE 0x01 /* + * On the aic78X0 chips, Board Control is replaced by the DSCommand + * register (p. 4-64) + */ +#define DSCOMMAND 0x084 +#define CACHETHEN 0x80 /* Cache Threshold enable */ +#define DPARCKEN 0x40 /* Data Parity Check Enable */ +#define MPARCKEN 0x20 /* Memory Parity Check Enable */ +#define EXTREQLCK 0x10 /* External Request Lock */ + +/* * Bus On/Off Time (p. 3-44) */ #define BUSTIME 0x085 |
