diff options
| -rw-r--r-- | sys/riscv/riscv/timer.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/sys/riscv/riscv/timer.c b/sys/riscv/riscv/timer.c index e3f3f22..fbef1a1 100644 --- a/sys/riscv/riscv/timer.c +++ b/sys/riscv/riscv/timer.c @@ -145,8 +145,9 @@ riscv_tmr_intr(void *arg) /* * Clear interrupt pending bit. - * Note sip register is unimplemented in Spike simulator, - * so use machine command to clear in mip. + * Note: SIP_STIP bit is not implemented in sip register + * in Spike simulator, so use machine command to clear + * interrupt pending bit in mip. */ machine_command(ECALL_CLEAR_PENDING, 0); |
