diff options
36 files changed, 972 insertions, 659 deletions
diff --git a/contrib/gcc/ChangeLog b/contrib/gcc/ChangeLog index f664314..783f3d1 100644 --- a/contrib/gcc/ChangeLog +++ b/contrib/gcc/ChangeLog @@ -1,7 +1,172 @@ +2002-09-14 Stephane Carrez <stcarrez@nerim.fr> + + * config/m68hc11/m68hc11.md ("movdi_internal"): Allow any offsetable + memory operand when source is 0 (K constraint). + ("movsi_internal"): Likewise. + ("movdf_internal"): Likewise. + ("movsf_internal"): Likewise. + +2002-09-14 Alan Modra <amodra@bigpond.net.au> + + Merge from mainline. + 2002-09-14 Alan Modra <amodra@bigpond.net.au> + * doc/tm.texi (DBX_OUTPUT_NFUN): Describe. + * dbxout.c (dbxout_function_end): Use DBX_OUTPUT_NFUN. + * config/rs6000/linux64.h (DBX_OUTPUT_NFUN): Define. + + 2002-08-27 David Edelsohn <edelsohn@gnu.org> + * config/rs6000/linux64.h (ADJUST_FIELD_ALIGN): Undef before define. + + 2002-08-02 Alan Modra <amodra@bigpond.net.au> + * config/rs6000/linux64.h (DBX_OUTPUT_BRAC): Define. + (DBX_OUTPUT_LBRAC, DBX_OUTPUT_RBRAC): Define. + * config/rs6000/rs6000.c (output_toc): Don't use lshift_double when + HOST_BITS_PER_WIDE_INT == 64. + + 2002-07-27 Alan Modra <amodra@bigpond.net.au> + * config/rs6000/rs6000.c (output_profile_hook): Don't generate profile + label reference when NO_PROFILE_COUNTERS. + + 2002-07-11 Alan Modra <amodra@bigpond.net.au> + * config/rs6000/linux64.h (ASM_SPEC): Define. + +2002-09-13 Alan Modra <amodra@bigpond.net.au> + + Merge from mainline. + 2002-07-24 Alan Modra <amodra@bigpond.net.au> + PR c/7150, target/7380 + * config/rs6000/rs6000.md: Remove scratch reg on insns using + addze and similar (plus (comparison r1 r2) r3) insns. Add + missing scratch reg in one case. Formatting fixes. + + 2002-07-18 Alan Modra <amodra@bigpond.net.au> + PR other/7114, target/5967 + * config/rs6000/rs6000.c (first_reg_to_save): Remove bogus + adjustments to first_reg for profiling case. + (output_function_profiler): Correct lr save slot for ABI_AIX_NODESC. + Disable profiling for 64 bit code on both ABI_V4 and ABI_AIX_NODESC. + Save static chain reg to sp + 12 on ABI_AIX_NODESC. + * config/rs6000/sysv4.h (ASM_OUTPUT_REG_PUSH): Define. + (ASM_OUTPUT_REG_POP): Define. + * config/rs6000/linux64.h (ASM_OUTPUT_REG_PUSH): Undef. + (ASM_OUTPUT_REG_POP): Undef. + + 2002-06-30 Alan Modra <amodra@bigpond.net.au> + PR optimization/7120 + * unroll.c (loop_iterations): Handle EQ loops. + +2002-09-13 Alan Modra <amodra@bigpond.net.au> + + * config/rs6000/rs6000.c (rs6000_emit_load_toc_table): Remove "if" + nesting. Correct test for non-PowerPC64 ELF ABI_AIX. + * config/rs6000/rs6000.md (load_toc_v4_PIC*): Disable when ABI_AIX. + +2002-09-12 Janis Johnson <janis187@us.ibm.com> + + * doc/compat.texi: New file with new chapter, Binary Compatibility. + +2002-09-12 Jason Merrill <jason@redhat.com> + + * calls.c (store_one_arg): Use size_in_bytes to determine the + amount of space to push. + +2002-09-12 Jakub Jelinek <jakub@redhat.com> + + * config/sparc/linux64.h (STARTFILE_SPEC32): Fix a typo. + +2002-09-12 Alan Modra <amodra@bigpond.net.au> + + * emit-rtl.c (set_mem_size): New function. + * expr.h (set_mem_size): Declare. + * config/rs6000/rs6000.c (expand_block_move_mem): Exterminate. + (expand_block_move): Instead, use adjust_address and + replace_equiv_address to generate proper aliasing info. + Move common code out of conditionals. Localize vars. + +2002-09-11 Alexander Kabaev <kan@FreeBSD.ORG> + + Wed Apr 24 13:48:25 CEST 2002 Jan Hubicka <jh@suse.cz> + * loop.c (canonicalize_condition): Use gen_int_mode. + +2002-09-11 Janis Johnson <janis187@us.ibm.com> + + * Makefile.in (TEXI_GCC_FILES): Add compat.texi. + * doc/gcc.texi (Top): Add new chapter, Binary Compatibility, and + include its file, compat.texi. + * doc/trouble.texi (Interoperation): Update information about C++ ABI + issues. + * doc/invoke.texi (-fshort-wchar): Move to Code Generation Options. + (-fpcc-struct-return, -freg-struct-return, -fshort-enums, + -fshort-double, -fshort-wchar, -fpack-struct, -fleading-underscore): + Warn that these options can break ABI compatibility. + (Many places): Fix overfull hboxes. + + * doc/extend.texi: Fix a broken link; fix overfull hboxes. + * doc/install.texi: Fix a typo, some formatting directives, and + overfull hboxes. + * doc/c-tree.texi: Fix overfull hboxes. + * doc/cppopts.texi: Ditto. + * doc/makefile.texi: Ditto. + * doc/rtl.texi: Ditto. + * doc/standards.texi: Ditto. + * doc/tm.texi: Ditto. + +2002-09-08 Alan Modra <amodra@bigpond.net.au> + + * reload.c (find_reloads <p constraint>): Pass operand_mode to + find_reloads_address. + +2002-09-07 Scott Snyder <snyder@fnal.gov> + + PR target/7374 + * config/alpha/alpha.md (abstf2): Fix typo: 'neg' for 'abs'. + +2002-09-07 Glen Nakamura <glen@imodulo.com> + + PR opt/7814 + * sched-deps.c (sched_analyze_insn): Make sure to add insn + to reg_last->sets after flushing the dependency lists to guarantee + that subsequent clobbers will be dependent on it. + +2002-09-07 Alan Modra <amodra@bigpond.net.au> + + * config/rs6000/linux64.h (ASM_PREFERRED_EH_DATA_FORMAT): Define. + +2002-09-06 Jakub Jelinek <jakub@redhat.com> + + * configure.in (HAVE_AS_OFFSETABLE_LO10): Use -xarch=v9 + unconditionally when gcc_cv_as_flags64 checks are gone. + * configure: Rebuilt. + +2002-09-04 Eric Botcazou <ebotcazou@multimania.com> + + PR c/7102 + * optabs.c (expand_binop): Convert CONST_INTs in all cases. + +2002-09-04 Jason Thorpe <thorpej@wasabisystems.com> + + * config/sparc/t-netbsd64: Disable multilib for now. + +2002-09-01 Alexandre Oliva <aoliva@redhat.com> + + * c-tree.h (skip_evaluation): Move declaration... + * c-common.h: ... here. + * c-typeck.c (build_external_ref): Don't assemble_external nor + mark a tree as used if skip_evaluation is set. + * c-parse.in (typeof): New non-terminal to set skip_evaluation + around TYPEOF. + (typespec_nonreserved_nonattr): Use it. + +2002-09-01 Marek Michalkiewicz <marekm@amelek.gda.pl> + + 2002-08-13 Denis Chertykov <denisc@overta.ru> + * config/avr/avr.md: Call CC_STATUS_INIT in all peepnoles + which can change CC0. + 2002-08-29 Rodney Brown <rbrown64@csc.com.au> - * doc/install.texi (Specific, alpha*-dec-osf*): Add "virtual - memory exhausted" workarounds. + * doc/install.texi (Specific, alpha*-dec-osf*): Add "virtual + memory exhausted" workarounds. 2002-08-29 John David Anglin <dave@hiauly1.hia.nrc.ca> @@ -23,10 +188,10 @@ 2002-08-23 David Edelsohn <edelsohn@gnu.org> - * config/rs6000/rs6000.c (rs6000_select_section): Treat - DEFAULT_ABI == ABI_AIX like PIC. Test PIC & reloc for readonly - default. - (rs6000_unique_section): Likewise. + * config/rs6000/rs6000.c (rs6000_select_section): Treat + DEFAULT_ABI == ABI_AIX like PIC. Test PIC & reloc for readonly + default. + (rs6000_unique_section): Likewise. 2002-08-22 Jason Merrill <jason@redhat.com> diff --git a/contrib/gcc/c-parse.in b/contrib/gcc/c-parse.in index 9740aa3..c7cbb16 100644 --- a/contrib/gcc/c-parse.in +++ b/contrib/gcc/c-parse.in @@ -534,6 +534,10 @@ alignof: ALIGNOF { skip_evaluation++; } ; +typeof: + TYPEOF { skip_evaluation++; } + ; + cast_expr: unary_expr | '(' typename ')' cast_expr %prec UNARY @@ -1376,10 +1380,10 @@ ifobjc | non_empty_protocolrefs { $$ = get_object_reference ($1); } end ifobjc - | TYPEOF '(' expr ')' - { $$ = TREE_TYPE ($3); } - | TYPEOF '(' typename ')' - { $$ = groktypename ($3); } + | typeof '(' expr ')' + { skip_evaluation--; $$ = TREE_TYPE ($3); } + | typeof '(' typename ')' + { skip_evaluation--; $$ = groktypename ($3); } ; /* typespec_nonreserved_attr does not exist. */ diff --git a/contrib/gcc/c-typeck.c b/contrib/gcc/c-typeck.c index b21cac0..d400f39 100644 --- a/contrib/gcc/c-typeck.c +++ b/contrib/gcc/c-typeck.c @@ -1493,7 +1493,8 @@ build_external_ref (id, fun) if (TREE_TYPE (ref) == error_mark_node) return error_mark_node; - assemble_external (ref); + if (!skip_evaluation) + assemble_external (ref); TREE_USED (ref) = 1; if (TREE_CODE (ref) == CONST_DECL) diff --git a/contrib/gcc/calls.c b/contrib/gcc/calls.c index 6cb2956..c0a73e7 100644 --- a/contrib/gcc/calls.c +++ b/contrib/gcc/calls.c @@ -4491,7 +4491,8 @@ store_one_arg (arg, argblock, flags, variable_size, reg_parm_stack_space) emit_push_insn for BLKmode is careful to avoid it. */ excess = (arg->size.constant - int_size_in_bytes (TREE_TYPE (pval)) + partial * UNITS_PER_WORD); - size_rtx = expr_size (pval); + size_rtx = expand_expr (size_in_bytes (TREE_TYPE (pval)), + NULL_RTX, TYPE_MODE (sizetype), 0); } if ((flags & ECF_SIBCALL) && GET_CODE (arg->value) == MEM) diff --git a/contrib/gcc/config/alpha/alpha.md b/contrib/gcc/config/alpha/alpha.md index 785a61d..1875b80 100644 --- a/contrib/gcc/config/alpha/alpha.md +++ b/contrib/gcc/config/alpha/alpha.md @@ -2374,7 +2374,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_expand "abstf2" [(parallel [(set (match_operand:TF 0 "register_operand" "") - (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" ""))) + (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" ""))) (use (match_dup 2))])] "TARGET_HAS_XFLOATING_LIBS" { diff --git a/contrib/gcc/config/rs6000/linux64.h b/contrib/gcc/config/rs6000/linux64.h index f84e1e3..ce8f7ac 100644 --- a/contrib/gcc/config/rs6000/linux64.h +++ b/contrib/gcc/config/rs6000/linux64.h @@ -37,6 +37,12 @@ Boston, MA 02111-1307, USA. */ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc64" +#undef ASM_SPEC +#define ASM_SPEC "%{.s: %{mregnames} %{mno-regnames}} \ +%{.S: %{mregnames} %{mno-regnames}} \ +%{mlittle} %{mlittle-endian} %{mbig} %{mbig-endian} \ +%{v:-V} %{Qy:} %{!Qn:-Qy} -a64 %(asm_cpu) %{Wa,*:%*}" + /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_NO_TOC #define TARGET_NO_TOC 0 @@ -65,6 +71,7 @@ Boston, MA 02111-1307, USA. */ #define USER_LABEL_PREFIX "" /* AIX word-aligns FP doubles but doubleword-aligns 64-bit ints. */ +#undef ADJUST_FIELD_ALIGN #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ (TYPE_MODE (TREE_CODE (TREE_TYPE (FIELD)) == ARRAY_TYPE \ ? get_inner_array_type (FIELD) \ @@ -327,3 +334,49 @@ do \ sym_lineno += 1; \ } \ while (0) + +/* Similarly, we want the function code label here. */ +#define DBX_OUTPUT_BRAC(FILE, NAME, BRAC) \ + do \ + { \ + const char *flab; \ + fprintf (FILE, "%s%d,0,0,", ASM_STABN_OP, BRAC); \ + assemble_name (FILE, NAME); \ + putc ('-', FILE); \ + if (current_function_func_begin_label != NULL_TREE) \ + flab = IDENTIFIER_POINTER (current_function_func_begin_label); \ + else \ + { \ + putc ('.', FILE); \ + flab = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \ + } \ + assemble_name (FILE, flab); \ + putc ('\n', FILE); \ + } \ + while (0) + +#define DBX_OUTPUT_LBRAC(FILE, NAME) DBX_OUTPUT_BRAC (FILE, NAME, N_LBRAC) +#define DBX_OUTPUT_RBRAC(FILE, NAME) DBX_OUTPUT_BRAC (FILE, NAME, N_RBRAC) + +/* Another case where we want the dot name. */ +#define DBX_OUTPUT_NFUN(FILE, LSCOPE, DECL) \ + do \ + { \ + fprintf (FILE, "%s\"\",%d,0,0,", ASM_STABS_OP, N_FUN); \ + assemble_name (FILE, LSCOPE); \ + fputs ("-.", FILE); \ + assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \ + putc ('\n', FILE); \ + } \ + while (0) + +/* Override sysv4.h as these are ABI_V4 only. */ +#undef ASM_OUTPUT_REG_PUSH +#undef ASM_OUTPUT_REG_POP + +/* Select a format to encode pointers in exception handling data. CODE + is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is + true if the symbol may be affected by dynamic relocations. */ +#undef ASM_PREFERRED_EH_DATA_FORMAT +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ + (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_udata8) diff --git a/contrib/gcc/config/rs6000/rs6000.c b/contrib/gcc/config/rs6000/rs6000.c index 92b1d64..ad9df44 100644 --- a/contrib/gcc/config/rs6000/rs6000.c +++ b/contrib/gcc/config/rs6000/rs6000.c @@ -120,7 +120,6 @@ static int rs6000_sr_alias_set; static void rs6000_add_gc_roots PARAMS ((void)); static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); -static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); static void validate_condition_mode PARAMS ((enum rtx_code, enum machine_mode)); static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); @@ -4909,21 +4908,6 @@ altivec_init_builtins (void) } -/* Generate a memory reference for expand_block_move, copying volatile, - and other bits from an original memory reference. */ - -static rtx -expand_block_move_mem (mode, addr, orig_mem) - enum machine_mode mode; - rtx addr; - rtx orig_mem; -{ - rtx mem = gen_rtx_MEM (mode, addr); - - MEM_COPY_ATTRIBUTES (mem, orig_mem); - return mem; -} - /* Expand a block move operation, and return 1 if successful. Return 0 if we should let the compiler generate normal code. @@ -4946,14 +4930,6 @@ expand_block_move (operands) int align; int bytes; int offset; - int num_reg; - int i; - rtx src_reg; - rtx dest_reg; - rtx src_addr; - rtx dest_addr; - rtx tmp_reg; - rtx stores[MAX_MOVE_REG]; int move_bytes; /* If this is not a fixed size move, just call memcpy */ @@ -4975,14 +4951,17 @@ expand_block_move (operands) if (bytes > (TARGET_POWERPC64 ? 64 : 32)) return 0; - /* Move the address into scratch registers. */ - dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); - src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); - if (TARGET_STRING) /* string instructions are available */ { - for ( ; bytes > 0; bytes -= move_bytes) + for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) { + union { + rtx (*movstrsi) PARAMS ((rtx, rtx, rtx, rtx)); + rtx (*mov) PARAMS ((rtx, rtx)); + } gen_func; + enum machine_mode mode = BLKmode; + rtx src, dest; + if (bytes > 24 /* move up to 32 bytes at a time */ && ! fixed_regs[5] && ! fixed_regs[6] @@ -4994,15 +4973,7 @@ expand_block_move (operands) && ! fixed_regs[12]) { move_bytes = (bytes > 32) ? 32 : bytes; - emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT ((move_bytes == 32) - ? 0 : move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_8reg; } else if (bytes > 16 /* move up to 24 bytes at a time */ && ! fixed_regs[5] @@ -5013,14 +4984,7 @@ expand_block_move (operands) && ! fixed_regs[10]) { move_bytes = (bytes > 24) ? 24 : bytes; - emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT (move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_6reg; } else if (bytes > 8 /* move up to 16 bytes at a time */ && ! fixed_regs[5] @@ -5029,14 +4993,7 @@ expand_block_move (operands) && ! fixed_regs[8]) { move_bytes = (bytes > 16) ? 16 : bytes; - emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT (move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_4reg; } else if (bytes >= 8 && TARGET_POWERPC64 /* 64-bit loads and stores require word-aligned @@ -5044,108 +5001,84 @@ expand_block_move (operands) && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) { move_bytes = 8; - tmp_reg = gen_reg_rtx (DImode); - emit_move_insn (tmp_reg, - expand_block_move_mem (DImode, - src_reg, orig_src)); - emit_move_insn (expand_block_move_mem (DImode, - dest_reg, orig_dest), - tmp_reg); + mode = DImode; + gen_func.mov = gen_movdi; } else if (bytes > 4 && !TARGET_POWERPC64) { /* move up to 8 bytes at a time */ move_bytes = (bytes > 8) ? 8 : bytes; - emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT (move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_2reg; } else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) { /* move 4 bytes */ move_bytes = 4; - tmp_reg = gen_reg_rtx (SImode); - emit_move_insn (tmp_reg, - expand_block_move_mem (SImode, - src_reg, orig_src)); - emit_move_insn (expand_block_move_mem (SImode, - dest_reg, orig_dest), - tmp_reg); + mode = SImode; + gen_func.mov = gen_movsi; } else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) { /* move 2 bytes */ move_bytes = 2; - tmp_reg = gen_reg_rtx (HImode); - emit_move_insn (tmp_reg, - expand_block_move_mem (HImode, - src_reg, orig_src)); - emit_move_insn (expand_block_move_mem (HImode, - dest_reg, orig_dest), - tmp_reg); + mode = HImode; + gen_func.mov = gen_movhi; } else if (bytes == 1) /* move 1 byte */ { move_bytes = 1; - tmp_reg = gen_reg_rtx (QImode); - emit_move_insn (tmp_reg, - expand_block_move_mem (QImode, - src_reg, orig_src)); - emit_move_insn (expand_block_move_mem (QImode, - dest_reg, orig_dest), - tmp_reg); + mode = QImode; + gen_func.mov = gen_movqi; } else { /* move up to 4 bytes at a time */ move_bytes = (bytes > 4) ? 4 : bytes; - emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT (move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_1reg; } - if (bytes > move_bytes) + src = adjust_address (orig_src, mode, offset); + dest = adjust_address (orig_dest, mode, offset); + + if (mode == BLKmode) { - if (! TARGET_POWERPC64) + /* Move the address into scratch registers. The movstrsi + patterns require zero offset. */ + if (!REG_P (XEXP (src, 0))) { - emit_insn (gen_addsi3 (src_reg, src_reg, - GEN_INT (move_bytes))); - emit_insn (gen_addsi3 (dest_reg, dest_reg, - GEN_INT (move_bytes))); + rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); + src = replace_equiv_address (src, src_reg); } - else + set_mem_size (src, GEN_INT (move_bytes)); + + if (!REG_P (XEXP (dest, 0))) { - emit_insn (gen_adddi3 (src_reg, src_reg, - GEN_INT (move_bytes))); - emit_insn (gen_adddi3 (dest_reg, dest_reg, - GEN_INT (move_bytes))); + rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); + dest = replace_equiv_address (dest, dest_reg); } + set_mem_size (dest, GEN_INT (move_bytes)); + + emit_insn ((*gen_func.movstrsi) (dest, src, + GEN_INT (move_bytes & 31), + align_rtx)); + } + else + { + rtx tmp_reg = gen_reg_rtx (mode); + + emit_insn ((*gen_func.mov) (tmp_reg, src)); + emit_insn ((*gen_func.mov) (dest, tmp_reg)); } } } else /* string instructions not available */ { - num_reg = offset = 0; - for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) + rtx stores[MAX_MOVE_REG]; + int num_reg = 0; + int i; + + for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) { - /* Calculate the correct offset for src/dest */ - if (offset == 0) - { - src_addr = src_reg; - dest_addr = dest_reg; - } - else - { - src_addr = plus_constant (src_reg, offset); - dest_addr = plus_constant (dest_reg, offset); - } + rtx (*gen_mov_func) PARAMS ((rtx, rtx)); + enum machine_mode mode; + rtx src, dest, tmp_reg; /* Generate the appropriate load and store, saving the stores for later. */ @@ -5155,56 +5088,35 @@ expand_block_move (operands) && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) { move_bytes = 8; - tmp_reg = gen_reg_rtx (DImode); - emit_insn (gen_movdi (tmp_reg, - expand_block_move_mem (DImode, - src_addr, - orig_src))); - stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, - dest_addr, - orig_dest), - tmp_reg); + mode = DImode; + gen_mov_func = gen_movdi; } else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) { move_bytes = 4; - tmp_reg = gen_reg_rtx (SImode); - emit_insn (gen_movsi (tmp_reg, - expand_block_move_mem (SImode, - src_addr, - orig_src))); - stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, - dest_addr, - orig_dest), - tmp_reg); + mode = SImode; + gen_mov_func = gen_movsi; } else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) { move_bytes = 2; - tmp_reg = gen_reg_rtx (HImode); - emit_insn (gen_movhi (tmp_reg, - expand_block_move_mem (HImode, - src_addr, - orig_src))); - stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, - dest_addr, - orig_dest), - tmp_reg); + mode = HImode; + gen_mov_func = gen_movhi; } else { move_bytes = 1; - tmp_reg = gen_reg_rtx (QImode); - emit_insn (gen_movqi (tmp_reg, - expand_block_move_mem (QImode, - src_addr, - orig_src))); - stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, - dest_addr, - orig_dest), - tmp_reg); + mode = QImode; + gen_mov_func = gen_movqi; } + src = adjust_address (orig_src, mode, offset); + dest = adjust_address (orig_dest, mode, offset); + tmp_reg = gen_reg_rtx (mode); + + emit_insn ((*gen_mov_func) (tmp_reg, src)); + stores[num_reg++] = (*gen_mov_func) (dest, tmp_reg); + if (num_reg >= MAX_MOVE_REG) { for (i = 0; i < num_reg; i++) @@ -7434,53 +7346,6 @@ first_reg_to_save () || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) break; - if (current_function_profile) - { - /* AIX must save/restore every register that contains a parameter - before/after the .__mcount call plus an additional register - for the static chain, if needed; use registers from 30 down to 22 - to do this. */ - if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) - { - int last_parm_reg, profile_first_reg; - - /* Figure out last used parameter register. The proper thing - to do is to walk incoming args of the function. A function - might have live parameter registers even if it has no - incoming args. */ - for (last_parm_reg = 10; - last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; - last_parm_reg--) - ; - - /* Calculate first reg for saving parameter registers - and static chain. - Skip reg 31 which may contain the frame pointer. */ - profile_first_reg = (33 - last_parm_reg - - (current_function_needs_context ? 1 : 0)); -#if TARGET_MACHO - /* Need to skip another reg to account for R31 being PICBASE - (when flag_pic is set) or R30 being used as the frame - pointer (when flag_pic is not set). */ - --profile_first_reg; -#endif - /* Do not save frame pointer if no parameters needs to be saved. */ - if (profile_first_reg == 31) - profile_first_reg = 32; - - if (first_reg > profile_first_reg) - first_reg = profile_first_reg; - } - - /* SVR4 may need one register to preserve the static chain. */ - else if (current_function_needs_context) - { - /* Skip reg 31 which may contain the frame pointer. */ - if (first_reg > 30) - first_reg = 30; - } - } - #if TARGET_MACHO if (flag_pic && current_function_uses_pic_offset_table && (first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)) @@ -8124,91 +7989,88 @@ rs6000_emit_load_toc_table (fromprolog) rtx dest; dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); - if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) + if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) + { + rtx temp = (fromprolog + ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) + : gen_reg_rtx (Pmode)); + rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); + rs6000_maybe_dead (emit_move_insn (dest, temp)); + } + else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) { - if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) + char buf[30]; + rtx tempLR = (fromprolog + ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) + : gen_reg_rtx (Pmode)); + rtx temp0 = (fromprolog + ? gen_rtx_REG (Pmode, 0) + : gen_reg_rtx (Pmode)); + rtx symF; + + /* possibly create the toc section */ + if (! toc_initialized) { - rtx temp = (fromprolog - ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) - : gen_reg_rtx (Pmode)); - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); - rs6000_maybe_dead (emit_move_insn (dest, temp)); + toc_section (); + function_section (current_function_decl); } - else if (flag_pic == 2) - { - char buf[30]; - rtx tempLR = (fromprolog - ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) - : gen_reg_rtx (Pmode)); - rtx temp0 = (fromprolog - ? gen_rtx_REG (Pmode, 0) - : gen_reg_rtx (Pmode)); - rtx symF; - - /* possibly create the toc section */ - if (! toc_initialized) - { - toc_section (); - function_section (current_function_decl); - } - - if (fromprolog) - { - rtx symL; - - ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); - symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - - ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); - symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, - symF))); - rs6000_maybe_dead (emit_move_insn (dest, tempLR)); - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, - symL, - symF))); - } - else - { - rtx tocsym; - static int reload_toc_labelno = 0; - tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); + if (fromprolog) + { + rtx symL; - ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); - symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); + ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); + symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, - symF, - tocsym))); - rs6000_maybe_dead (emit_move_insn (dest, tempLR)); - rs6000_maybe_dead (emit_move_insn (temp0, - gen_rtx_MEM (Pmode, dest))); - } - rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); - } - else if (flag_pic == 0 && TARGET_MINIMAL_TOC) - { - /* This is for AIX code running in non-PIC ELF. */ - char buf[30]; - rtx realsym; - ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); - realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - - rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); - rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); + ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); + symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); + + rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, + symF))); + rs6000_maybe_dead (emit_move_insn (dest, tempLR)); + rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, + symL, + symF))); } else - abort (); + { + rtx tocsym; + static int reload_toc_labelno = 0; + + tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); + + ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); + symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); + + rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, + symF, + tocsym))); + rs6000_maybe_dead (emit_move_insn (dest, tempLR)); + rs6000_maybe_dead (emit_move_insn (temp0, + gen_rtx_MEM (Pmode, dest))); + } + rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); } - else + else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) + { + /* This is for AIX code running in non-PIC ELF32. */ + char buf[30]; + rtx realsym; + ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); + realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); + + rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); + rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); + } + else if (DEFAULT_ABI == ABI_AIX) { if (TARGET_32BIT) - rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); + rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); else - rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); + rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); } + else + abort (); } int @@ -10238,8 +10100,17 @@ output_toc (file, x, labelno, mode) abort ();/* It would be easy to make this work, but it doesn't now. */ if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) - lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), - POINTER_SIZE, &low, &high, 0); + { +#if HOST_BITS_PER_WIDE_INT == 32 + lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), + POINTER_SIZE, &low, &high, 0); +#else + low |= high << 32; + low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); + high = (HOST_WIDE_INT) low >> 32; + low &= 0xffffffff; +#endif + } if (TARGET_64BIT) { @@ -10457,10 +10328,13 @@ rs6000_gen_section_name (buf, filename, section_desc) void output_profile_hook (labelno) - int labelno; + int labelno ATTRIBUTE_UNUSED; { if (DEFAULT_ABI == ABI_AIX) { +#ifdef NO_PROFILE_COUNTERS + emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); +#else char buf[30]; const char *label_name; rtx fun; @@ -10471,6 +10345,7 @@ output_profile_hook (labelno) emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, fun, Pmode); +#endif } else if (DEFAULT_ABI == ABI_DARWIN) { @@ -10504,6 +10379,7 @@ output_function_profiler (file, labelno) int labelno; { char buf[100]; + int save_lr = 8; ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); switch (DEFAULT_ABI) @@ -10512,13 +10388,21 @@ output_function_profiler (file, labelno) abort (); case ABI_V4: + save_lr = 4; + /* Fall through. */ + case ABI_AIX_NODESC: + if (!TARGET_32BIT) + { + warning ("no profiling of 64-bit code for this ABI"); + return; + } fprintf (file, "\tmflr %s\n", reg_names[0]); if (flag_pic == 1) { fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", - reg_names[0], reg_names[1]); + asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", + reg_names[0], save_lr, reg_names[1]); asm_fprintf (file, "\tmflr %s\n", reg_names[12]); asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); assemble_name (file, buf); @@ -10526,8 +10410,8 @@ output_function_profiler (file, labelno) } else if (flag_pic > 1) { - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", - reg_names[0], reg_names[1]); + asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", + reg_names[0], save_lr, reg_names[1]); /* Now, we need to get the address of the label. */ fputs ("\tbl 1f\n\t.long ", file); assemble_name (file, buf); @@ -10543,27 +10427,32 @@ output_function_profiler (file, labelno) asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); assemble_name (file, buf); fputs ("@ha\n", file); - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", - reg_names[0], reg_names[1]); + asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", + reg_names[0], save_lr, reg_names[1]); asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); assemble_name (file, buf); asm_fprintf (file, "@l(%s)\n", reg_names[12]); } - if (current_function_needs_context) - asm_fprintf (file, "\tmr %s,%s\n", - reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); - fprintf (file, "\tbl %s\n", RS6000_MCOUNT); - if (current_function_needs_context) - asm_fprintf (file, "\tmr %s,%s\n", - reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); + if (current_function_needs_context && DEFAULT_ABI == ABI_AIX_NODESC) + { + asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", + reg_names[STATIC_CHAIN_REGNUM], + 12, reg_names[1]); + fprintf (file, "\tbl %s\n", RS6000_MCOUNT); + asm_fprintf (file, "\t{l|lwz} %s,%d(%s)\n", + reg_names[STATIC_CHAIN_REGNUM], + 12, reg_names[1]); + } + else + /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ + fprintf (file, "\tbl %s\n", RS6000_MCOUNT); break; case ABI_AIX: case ABI_DARWIN: /* Don't do anything, done in output_profile_hook (). */ break; - } } diff --git a/contrib/gcc/config/rs6000/rs6000.md b/contrib/gcc/config/rs6000/rs6000.md index 5188ce5..f032bfd 100644 --- a/contrib/gcc/config/rs6000/rs6000.md +++ b/contrib/gcc/config/rs6000/rs6000.md @@ -9641,7 +9641,7 @@ [(set (match_operand:SI 0 "register_operand" "=l") (match_operand:SI 1 "immediate_operand" "s")) (unspec [(match_dup 1)] 7)] - "TARGET_ELF && flag_pic == 2" + "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" "bl %1\\n%1:" [(set_attr "type" "branch") (set_attr "length" "4")]) @@ -9650,7 +9650,7 @@ [(set (match_operand:SI 0 "register_operand" "=l") (match_operand:SI 1 "immediate_operand" "s")) (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] - "TARGET_ELF && flag_pic == 2" + "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" "bl %1\\n\\t.long %2-%1+4\\n%1:" [(set_attr "type" "branch") (set_attr "length" "8")]) @@ -9660,7 +9660,7 @@ (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") (minus:SI (match_operand:SI 2 "immediate_operand" "s") (match_operand:SI 3 "immediate_operand" "s")))))] - "TARGET_ELF && flag_pic == 2" + "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" "{l|lwz} %0,%2-%3(%1)" [(set_attr "type" "load")]) @@ -11253,15 +11253,14 @@ "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) - (match_operand:SI 3 "gpc_reg_operand" "r,r"))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r,r")))] "TARGET_POWER" "@ - doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" + doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 + {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -11292,46 +11291,43 @@ "TARGET_POWER && reload_completed" [(set (match_dup 4) (plus:SI (le:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 + doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 + {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11481,37 +11477,34 @@ "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 + {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "8,12")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11525,14 +11518,13 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (and:SI (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "! TARGET_POWERPC64" - "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" + "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" [(set_attr "length" "12")]) (define_insn "" @@ -11562,34 +11554,32 @@ (clobber (match_scratch:SI 4 ""))] "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) - (and:SI (neg:SI (leu:SI (match_dup 1) - (match_dup 2))) - (match_dup 3))) + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:SI (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 + {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (and:SI (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -11597,13 +11587,12 @@ (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) - (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + [(set (match_dup 0) + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) + (match_dup 3))) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11648,13 +11637,12 @@ "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_POWER" - "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" + "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -11683,44 +11671,41 @@ "TARGET_POWER && reload_completed" [(set (match_dup 4) (plus:SI (lt:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 + doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11815,46 +11800,43 @@ "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_neg_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11905,21 +11887,20 @@ (clobber (match_scratch:SI 3 ""))] "TARGET_POWER && reload_completed" [(parallel [(set (match_dup 0) - (ge:SI (match_dup 1) (match_dup 2))) - (clobber (match_dup 3))]) + (ge:SI (match_dup 1) (match_dup 2))) + (clobber (match_dup 3))]) (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_POWER" - "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" + "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -11948,44 +11929,41 @@ "TARGET_POWER && reload_completed" [(set (match_dup 4) (plus:SI (ge:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 + doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12130,39 +12108,36 @@ "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 - {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3 + {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 + {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "8,8,12,12")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_neg_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12178,16 +12153,15 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") (and:SI (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gpc_reg_operand" "r,r"))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r,r")))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" [(set_attr "length" "12")]) (define_insn "" @@ -12219,36 +12193,34 @@ (clobber (match_scratch:SI 4 ""))] "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) - (and:SI (neg:SI (geu:SI (match_dup 1) - (match_dup 2))) - (match_dup 3))) + (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (and:SI (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 # #" [(set_attr "type" "compare") (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (and:SI (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -12256,13 +12228,11 @@ (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12394,13 +12364,12 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:DI 2 "gpc_reg_operand" "r"))) - (clobber (match_scratch:DI 3 "=&r"))] + (match_operand:DI 2 "gpc_reg_operand" "r")))] "TARGET_POWERPC64" - "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2" + "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" [(set_attr "length" "12")]) (define_insn "" @@ -12461,92 +12430,85 @@ "TARGET_POWERPC64 && reload_completed" [(set (match_dup 3) (plus:DI (gt:DI (match_dup 1) (const_int 0)) - (match_dup 2))) + (match_dup 2))) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (const_int 0)) (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:SI 3 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] "! TARGET_POWERPC64" "@ - {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2 + {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int 0)) (match_operand:SI 2 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:SI 3 ""))] + (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_dup 3))]) - (set (match_dup 4) + (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (const_int 0)) (match_operand:DI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:DI 3 "=&r,&r"))] + (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") + (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] "TARGET_POWERPC64" "@ - addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2 + addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") (const_int 0)) (match_operand:DI 2 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") - (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:DI 3 ""))] + (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_dup 3))]) - (set (match_dup 4) + (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_POWER" - "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" + "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -12574,45 +12536,41 @@ (clobber (match_scratch:SI 4 ""))] "TARGET_POWER && reload_completed" [(set (match_dup 4) - (plus:SI (gt:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,r")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 + doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12731,15 +12689,14 @@ [(set_attr "length" "8,12")]) (define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:DI 2 "reg_or_short_operand" "I,rI")) - (match_operand:DI 3 "reg_or_short_operand" "r,rI"))) - (clobber (match_scratch:DI 4 "=&r,&r"))] + (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] "TARGET_POWERPC64" "@ - addic %4,%1,%k2\;addze %0,%3 - subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3" + addic %0,%1,%k2\;addze %0,%3 + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" [(set_attr "length" "8,12")]) (define_insn "" @@ -12770,7 +12727,7 @@ "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] @@ -12811,77 +12768,71 @@ "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 + {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 + {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "8,12,12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] + (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWERPC64" "@ - addic %4,%1,%k2\;addze. %0,%3 - subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3 + addic %0,%1,%k2\;addze. %0,%3 + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "8,12,12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "reg_or_short_operand" "")) (match_operand:DI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") - (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:DI 4 ""))] + (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") diff --git a/contrib/gcc/config/rs6000/sysv4.h b/contrib/gcc/config/rs6000/sysv4.h index 9274d8f..635e926 100644 --- a/contrib/gcc/config/rs6000/sysv4.h +++ b/contrib/gcc/config/rs6000/sysv4.h @@ -770,6 +770,38 @@ do { \ ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ } while (0) +/* This is how to output code to push a register on the stack. + It need not be very fast code. + + On the rs6000, we must keep the backchain up to date. In order + to simplify things, always allocate 16 bytes for a push (System V + wants to keep stack aligned to a 16 byte boundary). */ + +#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ +do { \ + if (DEFAULT_ABI == ABI_V4) \ + asm_fprintf (FILE, \ + (TARGET_32BIT \ + ? "\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,12(%s)\n" \ + : "\tstdu %s,-32(%s)\n\tstd %s,24(%s)\n"), \ + reg_names[1], reg_names[1], reg_names[REGNO], \ + reg_names[1]); \ +} while (0) + +/* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ +do { \ + if (DEFAULT_ABI == ABI_V4) \ + asm_fprintf (FILE, \ + (TARGET_32BIT \ + ? "\t{l|lwz} %s,12(%s)\n\t{ai|addic} %s,%s,16\n" \ + : "\tld %s,24(%s)\n\t{ai|addic} %s,%s,32\n"), \ + reg_names[REGNO], reg_names[1], reg_names[1], \ + reg_names[1]); \ +} while (0) + /* Switch Recognition by gcc.c. Add -G xx support. */ /* Override svr4.h definition. */ diff --git a/contrib/gcc/config/sparc/linux64.h b/contrib/gcc/config/sparc/linux64.h index 33c3f54..1dfd97f 100644 --- a/contrib/gcc/config/sparc/linux64.h +++ b/contrib/gcc/config/sparc/linux64.h @@ -58,7 +58,7 @@ Boston, MA 02111-1307, USA. */ #define STARTFILE_SPEC32 \ "%{!shared: \ - %{pg:/usr/lib/gcrt1.o%s} %{!pg:%{/usr/lib/p:gcrt1.o%s} %{!p:/usr/lib/crt1.o%s}}}\ + %{pg:/usr/lib/gcrt1.o%s} %{!pg:%{p:/usr/lib/gcrt1.o%s} %{!p:/usr/lib/crt1.o%s}}}\ /usr/lib/crti.o%s %{static:crtbeginT.o%s}\ %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" diff --git a/contrib/gcc/config/sparc/t-netbsd64 b/contrib/gcc/config/sparc/t-netbsd64 index 1292b86..0fddb0f 100644 --- a/contrib/gcc/config/sparc/t-netbsd64 +++ b/contrib/gcc/config/sparc/t-netbsd64 @@ -1,6 +1,8 @@ -MULTILIB_OPTIONS = m32/m64 -MULTILIB_DIRNAMES = 32 64 -MULTILIB_MATCHES = +# Disable multilib fow now, as NetBSD/sparc64 does not ship with +# a 32-bit environment. +#MULTILIB_OPTIONS = m32/m64 +#MULTILIB_DIRNAMES = 32 64 +#MULTILIB_MATCHES = -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib +#LIBGCC = stmp-multilib +#INSTALL_LIBGCC = install-multilib diff --git a/contrib/gcc/configure.in b/contrib/gcc/configure.in index 9cacc4a..69545a4 100644 --- a/contrib/gcc/configure.in +++ b/contrib/gcc/configure.in @@ -1846,33 +1846,31 @@ EOF [Define if your assembler and linker support unaligned PC relative relocs against hidden symbols.]) fi - if test "x$gcc_cv_as_flags64" != xno; then - AC_CACHE_CHECK([for assembler offsetable %lo() support], - gcc_cv_as_offsetable_lo10, [ - gcc_cv_as_offsetable_lo10=unknown - if test "x$gcc_cv_as" != x; then - # Check if assembler has offsetable %lo() - echo "or %g1, %lo(ab) + 12, %g1" > conftest.s - echo "or %g1, %lo(ab + 12), %g1" > conftest1.s - if $gcc_cv_as $gcc_cv_as_flags64 -o conftest.o conftest.s \ - > /dev/null 2>&1 && - $gcc_cv_as $gcc_cv_as_flags64 -o conftest1.o conftest1.s \ - > /dev/null 2>&1; then - if cmp conftest.o conftest1.o > /dev/null 2>&1; then - gcc_cv_as_offsetable_lo10=no - else - gcc_cv_as_offsetable_lo10=yes - fi - else + AC_CACHE_CHECK([for assembler offsetable %lo() support], + gcc_cv_as_offsetable_lo10, [ + gcc_cv_as_offsetable_lo10=unknown + if test "x$gcc_cv_as" != x; then + # Check if assembler has offsetable %lo() + echo "or %g1, %lo(ab) + 12, %g1" > conftest.s + echo "or %g1, %lo(ab + 12), %g1" > conftest1.s + if $gcc_cv_as -xarch=v9 -o conftest.o conftest.s \ + > /dev/null 2>&1 && + $gcc_cv_as -xarch=v9 -o conftest1.o conftest1.s \ + > /dev/null 2>&1; then + if cmp conftest.o conftest1.o > /dev/null 2>&1; then gcc_cv_as_offsetable_lo10=no + else + gcc_cv_as_offsetable_lo10=yes fi - rm -f conftest.s conftest.o conftest1.s conftest1.o + else + gcc_cv_as_offsetable_lo10=no fi - ]) - if test "x$gcc_cv_as_offsetable_lo10" = xyes; then - AC_DEFINE(HAVE_AS_OFFSETABLE_LO10, 1, - [Define if your assembler supports offsetable %lo().]) + rm -f conftest.s conftest.o conftest1.s conftest1.o fi + ]) + if test "x$gcc_cv_as_offsetable_lo10" = xyes; then + AC_DEFINE(HAVE_AS_OFFSETABLE_LO10, 1, + [Define if your assembler supports offsetable %lo().]) fi ;; diff --git a/contrib/gcc/cp/ChangeLog b/contrib/gcc/cp/ChangeLog index e7c5b8c..f75f91f 100644 --- a/contrib/gcc/cp/ChangeLog +++ b/contrib/gcc/cp/ChangeLog @@ -1,3 +1,20 @@ +2002-09-04 Jakub Jelinek <jakub@redhat.com> + + * decl.c (start_cleanup_fn): Clear interface_only before + start_function, restore it afterwards. + +2002-09-01 Alexandre Oliva <aoliva@redhat.com> + + * parse.y (sizeof, alignof, typeof): New non-terminals to + increment skip_evaluation. Replace terminals with them and + decrement skip_evaluation at the end of rules using them. + * decl2.c (mark_used): Don't assemble_external if + skipping evaluation. + +2002-08-31 Jason Merrill <jason@redhat.com> + + * cp-lang.c (cp_expr_size): Don't abort. + 2002-08-27 Mark Mitchell <mark@codesourcery.com> * cp-tree.h (warn_abi): Declare it. diff --git a/contrib/gcc/cp/cp-lang.c b/contrib/gcc/cp/cp-lang.c index 7b1d860..b573cce 100644 --- a/contrib/gcc/cp/cp-lang.c +++ b/contrib/gcc/cp/cp-lang.c @@ -122,14 +122,8 @@ cp_expr_size (exp) { if (CLASS_TYPE_P (TREE_TYPE (exp))) { - /* The backend should not be interested in the size of an expression - of a type with both of these set; all copies of such types must go - through a constructor or assignment op. */ - if (TYPE_HAS_COMPLEX_INIT_REF (TREE_TYPE (exp)) - && TYPE_HAS_COMPLEX_ASSIGN_REF (TREE_TYPE (exp))) - abort (); - /* This would be wrong for a type with virtual bases, but they are - caught by the abort above. */ + /* This would be wrong for a type with virtual bases, but they should + not get here. */ return CLASSTYPE_SIZE_UNIT (TREE_TYPE (exp)); } else diff --git a/contrib/gcc/cp/decl2.c b/contrib/gcc/cp/decl2.c index 09a30f4..0eb4799 100644 --- a/contrib/gcc/cp/decl2.c +++ b/contrib/gcc/cp/decl2.c @@ -5186,7 +5186,8 @@ mark_used (decl) TREE_USED (decl) = 1; if (processing_template_decl) return; - assemble_external (decl); + if (!skip_evaluation) + assemble_external (decl); /* Is it a synthesized method that needs to be synthesized? */ if (TREE_CODE (decl) == FUNCTION_DECL diff --git a/contrib/gcc/cp/parse.y b/contrib/gcc/cp/parse.y index d1e3761..6782621 100644 --- a/contrib/gcc/cp/parse.y +++ b/contrib/gcc/cp/parse.y @@ -1255,16 +1255,20 @@ unary_expr: /* Refer to the address of a label as a pointer. */ | ANDAND identifier { $$ = finish_label_address_expr ($2); } - | SIZEOF unary_expr %prec UNARY - { $$ = finish_sizeof ($2); } - | SIZEOF '(' type_id ')' %prec HYPERUNARY + | sizeof unary_expr %prec UNARY + { $$ = finish_sizeof ($2); + skip_evaluation--; } + | sizeof '(' type_id ')' %prec HYPERUNARY { $$ = finish_sizeof (groktypename ($3.t)); - check_for_new_type ("sizeof", $3); } - | ALIGNOF unary_expr %prec UNARY - { $$ = finish_alignof ($2); } - | ALIGNOF '(' type_id ')' %prec HYPERUNARY + check_for_new_type ("sizeof", $3); + skip_evaluation--; } + | alignof unary_expr %prec UNARY + { $$ = finish_alignof ($2); + skip_evaluation--; } + | alignof '(' type_id ')' %prec HYPERUNARY { $$ = finish_alignof (groktypename ($3.t)); - check_for_new_type ("alignof", $3); } + check_for_new_type ("alignof", $3); + skip_evaluation--; } /* The %prec EMPTY's here are required by the = init initializer syntax extension; see below. */ @@ -1989,6 +1993,18 @@ reserved_typespecquals: { $$ = tree_cons ($1, NULL_TREE, NULL_TREE); } ; +sizeof: + SIZEOF { skip_evaluation++; } + ; + +alignof: + ALIGNOF { skip_evaluation++; } + ; + +typeof: + TYPEOF { skip_evaluation++; } + ; + /* A typespec (but not a type qualifier). Once we have seen one of these in a declaration, if a typedef name appears then it is being redeclared. */ @@ -2000,12 +2016,14 @@ typespec: { $$.t = $1; $$.new_type_flag = 0; $$.lookups = NULL_TREE; } | complete_type_name { $$.t = $1; $$.new_type_flag = 0; $$.lookups = NULL_TREE; } - | TYPEOF '(' expr ')' + | typeof '(' expr ')' { $$.t = finish_typeof ($3); - $$.new_type_flag = 0; $$.lookups = NULL_TREE; } - | TYPEOF '(' type_id ')' + $$.new_type_flag = 0; $$.lookups = NULL_TREE; + skip_evaluation--; } + | typeof '(' type_id ')' { $$.t = groktypename ($3.t); - $$.new_type_flag = 0; $$.lookups = NULL_TREE; } + $$.new_type_flag = 0; $$.lookups = NULL_TREE; + skip_evaluation--; } | SIGOF '(' expr ')' { tree type = TREE_TYPE ($3); diff --git a/contrib/gcc/doc/c-tree.texi b/contrib/gcc/doc/c-tree.texi index 0e821e5..35da90a 100644 --- a/contrib/gcc/doc/c-tree.texi +++ b/contrib/gcc/doc/c-tree.texi @@ -1203,11 +1203,11 @@ Then, if @code{THUNK_VCALL_OFFSET} (an @code{INTEGER_CST}) is nonzero the adjusted @code{this} pointer must be adjusted again. The complete calculation is given by the following pseudo-code: -@example +@smallexample this += THUNK_DELTA if (THUNK_VCALL_OFFSET) this += (*((ptrdiff_t **) this))[THUNK_VCALL_OFFSET] -@end example +@end smallexample Finally, the thunk should jump to the location given by @code{DECL_INITIAL}; this will always be an expression for the diff --git a/contrib/gcc/doc/compat.texi b/contrib/gcc/doc/compat.texi new file mode 100644 index 0000000..3e4ef89 --- /dev/null +++ b/contrib/gcc/doc/compat.texi @@ -0,0 +1,115 @@ +@c Copyright (C) 2002 Free Software Foundation, Inc. +@c This is part of the GCC manual. +@c For copying conditions, see the file gcc.texi. + +@node Compatibility +@chapter Binary Compatibility +@cindex binary compatibility +@cindex ABI +@cindex application binary interface + +Binary compatibility encompasses several related concepts: + +@table @dfn +@item application binary interface (ABI) +The set of runtime conventions followed by all of the tools that deal +with binary representations of a program, including compilers, assemblers, +linkers, and language runtime support. +Some ABIs are formal with a written specification, possibly designed +by multiple interested parties. Others are simply the way things are +actually done by a particular set of tools. + +@item ABI conformance +A compiler conforms to an ABI if it generates code that follows all of +the specifications enumerated by that ABI@. +A library conforms to an ABI if it is implemented according to that ABI@. +An application conforms to an ABI if it is built using tools that conform +to that ABI and does not contain source code that specifically changes +behavior specified by the ABI@. + +@item calling conventions +Calling conventions are a subset of an ABI that specify of how arguments +are passed and function results are returned. + +@item interoperability +Different sets of tools are interoperable if they generate files that +can be used in the same program. The set of tools includes compilers, +assemblers, linkers, libraries, header files, startup files, and debuggers. +Binaries produced by different sets of tools are not interoperable unless +they implement the same ABI@. This applies to different versions of the +same tools as well as tools from different vendors. + +@item intercallability +Whether a function in a binary built by one set of tools can call a +function in a binary built by a different set of tools is a subset +of interoperability. + +@item implementation-defined features +Language standards include lists of implementation-defined features whose +behavior can vary from one implementation to another. Some of these +features are normally covered by a platform's ABI and others are not. +The features that are not covered by an ABI generally affect how a +program behaves, but not intercallability. + +@item compatibility +Conformance to the same ABI and the same behavior of implementation-defined +features are both relevant for compatibility. +@end table + +The application binary interface implemented by a C or C++ compiler +affects code generation and runtime support for: + +@itemize @bullet +@item +size and alignment of data types +@item +layout of structured types +@item +calling conventions +@item +register usage conventions +@item +interfaces for runtime arithmetic support +@item +object file formats +@end itemize + +In addition, the application binary interface implemented by a C++ compiler +affects code generation and runtime support for: +@itemize @bullet +@item +name mangling +@item +exception handling +@item +invoking constructors and destructors +@item +layout, alignment, and padding of classes +@item +layout and alignment of virtual tables +@end itemize + +Some GCC compilation options cause the compiler to generate code that +does not conform to the platform's default ABI@. Other options cause +different program behavior for implementation-defined features that are +not covered by an ABI@. These options are provided for consistency with +other compilers that do not follow the platform's default ABI or the +usual behavior of implementation-defined features for the platform. +Be very careful about using such options. + +Most platforms have a well-defined ABI that covers C code, but ABIs +that cover C++ functionality are not yet common. + +Starting with GCC 3.2, GCC binary conventions for C++ are based on a +written, vendor-neutral C++ ABI that was designed to be specific to +64-bit Itanium but also includes generic specifications that apply to +any platform. +This C++ ABI is also implemented by other compiler vendors on some +platforms, notably GNU/Linux and BSD systems. +We have tried hard to provide a stable ABI that will be compatible with +future GCC releases, but it is possible that we will encounter problems +that make this difficult. Such problems could include different +interpretations of the C++ ABI by different vendors, bugs in the ABI, or +bugs in the implementation of the ABI in different compilers. +GCC's @code{-Wabi} switch warns when G++ generates code that is +probably not compatible with the C++ ABI@. diff --git a/contrib/gcc/doc/cppopts.texi b/contrib/gcc/doc/cppopts.texi index 463403e..308e989 100644 --- a/contrib/gcc/doc/cppopts.texi +++ b/contrib/gcc/doc/cppopts.texi @@ -541,10 +541,10 @@ standard-conforming modes it converts them. See the @option{-std} and The nine trigraphs and their replacements are -@example +@smallexample Trigraph: ??( ??) ??< ??> ??= ??/ ??' ??! ??- Replacement: [ ] @{ @} # \ ^ | ~ -@end example +@end smallexample @end ifclear @item -remap diff --git a/contrib/gcc/doc/extend.texi b/contrib/gcc/doc/extend.texi index 4a33eea..79eea70 100644 --- a/contrib/gcc/doc/extend.texi +++ b/contrib/gcc/doc/extend.texi @@ -739,7 +739,7 @@ GCC implements taking the address of a nested function using a technique called @dfn{trampolines}. A paper describing them is available as @noindent -@uref{http://people.debian.org/~karlheg/Usenix88-lexic.pdf}. +@uref{http://people.debian.org/~aaronl/Usenix88-lexic.pdf}. A nested function can jump to a label inherited from a containing function, provided the label was explicitly declared in the containing @@ -1396,9 +1396,9 @@ variable number of arguments much as a function can. The syntax for defining the macro is similar to that of a function. Here is an example: -@example +@smallexample #define debug(format, ...) fprintf (stderr, format, __VA_ARGS__) -@end example +@end smallexample Here @samp{@dots{}} is a @dfn{variable argument}. In the invocation of such a macro, it represents the zero or more tokens until the closing @@ -1437,9 +1437,9 @@ string. To help solve this problem, CPP behaves specially for variable arguments used with the token paste operator, @samp{##}. If instead you write -@example +@smallexample #define debug(format, ...) fprintf (stderr, format, ## __VA_ARGS__) -@end example +@end smallexample and if the variable arguments are omitted or empty, the @samp{##} operator causes the preprocessor to remove the comma before it. If you @@ -1749,9 +1749,9 @@ nested subobject to initialize; the list is taken relative to the subobject corresponding to the closest surrounding brace pair. For example, with the @samp{struct point} declaration above: -@example +@smallexample struct point ptarray[10] = @{ [2].y = yv2, [2].x = xv2, [0].x = xv0 @}; -@end example +@end smallexample @noindent If the same field is initialized multiple times, it will have value from @@ -6749,10 +6749,10 @@ inclusive. Lower numbers indicate a higher priority. In the following example, @code{A} would normally be created before @code{B}, but the @code{init_priority} attribute has reversed that order: -@example +@smallexample Some_Class A __attribute__ ((init_priority (2000))); Some_Class B __attribute__ ((init_priority (543))); -@end example +@end smallexample @noindent Note that the particular values of @var{priority} do not matter; only their @@ -6778,7 +6778,7 @@ appropriately. However, if C++ code only needs to execute destructors when Java exceptions are thrown through it, GCC will guess incorrectly. Sample problematic code is: -@example +@smallexample struct S @{ ~S(); @}; extern void bar(); // is written in Java, and may throw exceptions void foo() @@ -6786,7 +6786,7 @@ Sample problematic code is: S s; bar(); @} -@end example +@end smallexample @noindent The usual effect of an incorrect guess is a link failure, complaining of diff --git a/contrib/gcc/doc/gcc.texi b/contrib/gcc/doc/gcc.texi index 4af8694..fe51216 100644 --- a/contrib/gcc/doc/gcc.texi +++ b/contrib/gcc/doc/gcc.texi @@ -164,6 +164,7 @@ Introduction, gccint, GNU Compiler Collection (GCC) Internals}. * C Extensions:: GNU extensions to the C language family. * C++ Extensions:: GNU extensions to the C++ language. * Objective-C:: GNU Objective-C runtime features. +* Compatibility:: Binary Compatibility * Gcov:: gcov: a GCC test coverage program. * Trouble:: If you have trouble using GCC. * Bugs:: How, why and where to report bugs. @@ -188,6 +189,7 @@ Introduction, gccint, GNU Compiler Collection (GCC) Internals}. @include invoke.texi @include extend.texi @include objc.texi +@include compat.texi @include gcov.texi @include trouble.texi @include bugreport.texi diff --git a/contrib/gcc/doc/invoke.texi b/contrib/gcc/doc/invoke.texi index a3b53ed..d60d6fc 100644 --- a/contrib/gcc/doc/invoke.texi +++ b/contrib/gcc/doc/invoke.texi @@ -169,7 +169,7 @@ in the following sections. -fallow-single-precision -fcond-mismatch @gol -fsigned-bitfields -fsigned-char @gol -funsigned-bitfields -funsigned-char @gol --fwritable-strings -fshort-wchar} +-fwritable-strings} @item C++ Language Options @xref{C++ Dialect Options,,Options Controlling C++ Dialect}. @@ -279,8 +279,8 @@ in the following sections. -frerun-cse-after-loop -frerun-loop-opt @gol -fschedule-insns -fschedule-insns2 @gol -fsingle-precision-constant -fssa -fssa-ccp -fssa-dce @gol --fstrength-reduce -fstrict-aliasing -fthread-jumps -ftrapv @gol --funroll-all-loops -funroll-loops @gol +-fstrength-reduce -fstrict-aliasing -fthread-jumps @gol +-ftrapv -funroll-all-loops -funroll-loops @gol --param @var{name}=@var{value} -O -O0 -O1 -O2 -O3 -Os} @@ -444,7 +444,7 @@ in the following sections. -mno-relocatable -mrelocatable-lib -mno-relocatable-lib @gol -mtoc -mno-toc -mlittle -mlittle-endian -mbig -mbig-endian @gol -mcall-aix -mcall-sysv -mcall-netbsd @gol --maix-struct-return -msvr4-struct-return +-maix-struct-return -msvr4-struct-return @gol -mabi=altivec -mabi=no-altivec @gol -mprototype -mno-prototype @gol -msim -mmvme -mads -myellowknife -memb -msdata @gol @@ -610,8 +610,8 @@ in the following sections. @emph{D30V Options} @gccoptlist{ --mextmem -mextmemory -monchip -mno-asm-optimize -masm-optimize @gol --mbranch-cost=@var{n} -mcond-exec=@var{n}} +-mextmem -mextmemory -monchip -mno-asm-optimize @gol +-masm-optimize -mbranch-cost=@var{n} -mcond-exec=@var{n}} @emph{S/390 and zSeries Options} @gccoptlist{ @@ -670,7 +670,7 @@ in the following sections. -fno-common -fno-ident -fno-gnu-linker @gol -fpcc-struct-return -fpic -fPIC @gol -freg-struct-return -fshared-data -fshort-enums @gol --fshort-double -fvolatile @gol +-fshort-double -fshort-wchar -fvolatile @gol -fvolatile-global -fvolatile-static @gol -fverbose-asm -fpack-struct -fstack-check @gol -fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol @@ -1297,12 +1297,6 @@ than double precision. If you must use @option{-traditional}, but want to use single precision operations when the operands are single precision, use this option. This option has no effect when compiling with ISO or GNU C conventions (the default). - -@item -fshort-wchar -@opindex fshort-wchar -Override the underlying type for @samp{wchar_t} to be @samp{short -unsigned int} instead of the default for the target. This option is -useful for building programs to run under WINE@. @end table @node C++ Dialect Options @@ -9716,7 +9710,8 @@ unwinding from asynchronous events (such as debugger or garbage collector). Return ``short'' @code{struct} and @code{union} values in memory like longer ones, rather than in registers. This convention is less efficient, but it has the advantage of allowing intercallability between -GCC-compiled files and files compiled with other compilers. +GCC-compiled files and files compiled with other compilers, particularly +the Portable C Compiler (pcc). The precise convention for returning structures in memory depends on the target configuration macros. @@ -9724,6 +9719,11 @@ on the target configuration macros. Short structures and unions are those whose size and alignment match that of some integer type. +@strong{Warning:} code compiled with the @option{-fpcc-struct-return} +switch is not binary compatible with code compiled with the +@option{-freg-struct-return} switch. +Use it to conform to a non-default application binary interface. + @item -freg-struct-return @opindex freg-struct-return Return @code{struct} and @code{union} values in registers when possible. @@ -9737,16 +9737,39 @@ defaults to @option{-fpcc-struct-return}, except on targets where GCC is the principal compiler. In those cases, we can choose the standard, and we chose the more efficient register return alternative. +@strong{Warning:} code compiled with the @option{-freg-struct-return} +switch is not binary compatible with code compiled with the +@option{-fpcc-struct-return} switch. +Use it to conform to a non-default application binary interface. + @item -fshort-enums @opindex fshort-enums Allocate to an @code{enum} type only as many bytes as it needs for the declared range of possible values. Specifically, the @code{enum} type will be equivalent to the smallest integer type which has enough room. +@strong{Warning:} the @option{-fshort-enums} switch causes GCC to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. + @item -fshort-double @opindex fshort-double Use the same size for @code{double} as for @code{float}. +@strong{Warning:} the @option{-fshort-double} switch causes GCC to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. + +@item -fshort-wchar +@opindex fshort-wchar +Override the underlying type for @samp{wchar_t} to be @samp{short +unsigned int} instead of the default for the target. This option is +useful for building programs to run under WINE@. + +@strong{Warning:} the @option{-fshort-wchar} switch causes GCC to generate +code that is not binary compatible with code generated without that switch. +Use it to conform to a non-default application binary interface. + @item -fshared-data @opindex fshared-data Requests that the data and non-@code{const} variables of this @@ -9888,9 +9911,12 @@ three-way choice. @item -fpack-struct @opindex fpack-struct -Pack all structure members together without holes. Usually you would -not want to use this option, since it makes the code suboptimal, and -the offsets of structure members won't agree with system libraries. +Pack all structure members together without holes. + +@strong{Warning:} the @option{-fpack-struct} switch causes GCC to generate +code that is not binary compatible with code generated without that switch. +Additionally, it makes the code suboptimial. +Use it to conform to a non-default application binary interface. @item -finstrument-functions @opindex finstrument-functions @@ -9987,8 +10013,10 @@ This option and its counterpart, @option{-fno-leading-underscore}, forcibly change the way C symbols are represented in the object file. One use is to help link with legacy assembly code. -Be warned that you should know what you are doing when invoking this -option, and that not all targets provide complete support for it. +@strong{Warning:} the @option{-fleading-underscore} switch causes GCC to +generate code that is not binary compatible with code generated without that +switch. Use it to conform to a non-default application binary interface. +Not all targets provide complete support for this switch. @end table @c man end diff --git a/contrib/gcc/doc/makefile.texi b/contrib/gcc/doc/makefile.texi index 69d621b..6d6b025 100644 --- a/contrib/gcc/doc/makefile.texi +++ b/contrib/gcc/doc/makefile.texi @@ -48,9 +48,9 @@ You can specify specific tests by setting RUNTESTFLAGS to be the name of the @file{.exp} file, optionally followed by (for some tests) an equals and a file wildcard, like: -@example +@smallexample make check-gcc RUNTESTFLAGS="execute.exp=19980413-*" -@end example +@end smallexample Note that running the testsuite may require additional tools be installed, such as TCL or dejagnu. diff --git a/contrib/gcc/doc/rtl.texi b/contrib/gcc/doc/rtl.texi index 2151047..56a02d3 100644 --- a/contrib/gcc/doc/rtl.texi +++ b/contrib/gcc/doc/rtl.texi @@ -2316,11 +2316,11 @@ An hypothetical example might be a pattern for an addition that can either wrap around or use saturating addition depending on the value of a special control register: -@example +@smallexample (parallel [(set (reg:SI 2) (unspec:SI [(reg:SI 3) (reg:SI 4)] 0)) (use (reg:SI 1))]) -@end example +@end smallexample @noindent @@ -2552,10 +2552,10 @@ where @var{z} is an index register and @var{i} is a constant. Here is an example of its use: -@example +@smallexample (mem:SF (post_modify:SI (reg:SI 42) (plus (reg:SI 42) (reg:SI 48)))) -@end example +@end smallexample This says to modify pseudo register 42 by adding the contents of pseudo register 48 to it, after the use of what ever 42 points to. diff --git a/contrib/gcc/doc/standards.texi b/contrib/gcc/doc/standards.texi index 25fbb45..b3e8b18 100644 --- a/contrib/gcc/doc/standards.texi +++ b/contrib/gcc/doc/standards.texi @@ -168,11 +168,19 @@ information concerning the history of C that is available online, see There is no formal written standard for Objective-C@. The most authoritative manual is ``Object-Oriented Programming and the -Objective-C Language'', available at a number of web sites; -@uref{http://developer.apple.com/techpubs/macosx/Cocoa/ObjectiveC/} has a -recent version, while @uref{http://www.toodarkpark.org/computers/objc/} -is an older example. @uref{http://www.gnustep.org} includes useful -information as well. +Objective-C Language'', available at a number of web sites + +@itemize +@item +@uref{http://developer.apple.com/techpubs/macosx/Cocoa/ObjectiveC/} +is a recent version +@item +@uref{http://www.toodarkpark.org/computers/objc/} +is an older example +@item +@uref{http://www.gnustep.org} +has additional useful information +@end itemize @xref{Top, GNAT Reference Manual, About This Guide, gnat_rm, GNAT Reference Manual}, for information on standard diff --git a/contrib/gcc/doc/tm.texi b/contrib/gcc/doc/tm.texi index 2e3ad05..d8821c5 100644 --- a/contrib/gcc/doc/tm.texi +++ b/contrib/gcc/doc/tm.texi @@ -156,11 +156,11 @@ such as one option that enables many options, some of which select multilibs. Example nonsensical definition, where @code{-malt-abi}, @code{-EB}, and @code{-mspoo} cause different multilibs to be chosen: -@example +@smallexample #define TARGET_OPTION_TRANSLATE_TABLE \ @{ "-fast", "-march=fast-foo -malt-abi -I/usr/fast-foo" @}, \ @{ "-compat", "-EB -malign=4 -mspoo" @} -@end example +@end smallexample @findex CPP_SPEC @item CPP_SPEC @@ -7423,6 +7423,11 @@ argument @var{name} is the name of an assembler symbol (for use with @item DBX_OUTPUT_RBRAC (@var{stream}, @var{name}) Like @code{DBX_OUTPUT_LBRAC}, but for the end of a scope level. +@findex DBX_OUTPUT_NFUN +@item DBX_OUTPUT_NFUN (@var{stream}, @var{lscope_label}, @var{decl}) +Define this macro if the target machine requires special handling to +output an @code{N_FUN} entry for the function @var{decl}. + @findex DBX_OUTPUT_ENUM @item DBX_OUTPUT_ENUM (@var{stream}, @var{type}) Define this macro if the target machine requires special handling to diff --git a/contrib/gcc/doc/trouble.texi b/contrib/gcc/doc/trouble.texi index 09026fe..4cfef9f 100644 --- a/contrib/gcc/doc/trouble.texi +++ b/contrib/gcc/doc/trouble.texi @@ -105,11 +105,13 @@ libraries and debuggers on certain systems. @itemize @bullet @item -G++ does not do name mangling in the same way as other C++ -compilers. This means that object files compiled with one compiler -cannot be used with another. +On many platforms, GCC supports a different ABI for C++ than do other +compilers, so the object files compiled by GCC cannot be used with object +files generated by another C++ compiler. -This effect is intentional, to protect you from more subtle problems. +An area where the difference is most apparent is name mangling. The use +of different name mangling is intentional, to protect you from more subtle +problems. Compilers differ as to many internal details of C++ implementation, including: how class instances are laid out, how multiple inheritance is implemented, and how virtual function calls are handled. If the name diff --git a/contrib/gcc/expr.h b/contrib/gcc/expr.h index 97d734b..4658a50 100644 --- a/contrib/gcc/expr.h +++ b/contrib/gcc/expr.h @@ -612,6 +612,9 @@ extern void set_mem_expr PARAMS ((rtx, tree)); /* Set the offset for MEM to OFFSET. */ extern void set_mem_offset PARAMS ((rtx, rtx)); +/* Set the size for MEM to SIZE. */ +extern void set_mem_size PARAMS ((rtx, rtx)); + /* Return a memory reference like MEMREF, but with its mode changed to MODE and its address changed to ADDR. (VOIDmode means don't change the mode. diff --git a/contrib/gcc/f/ChangeLog b/contrib/gcc/f/ChangeLog index 498e64d..3f3b286 100644 --- a/contrib/gcc/f/ChangeLog +++ b/contrib/gcc/f/ChangeLog @@ -1,3 +1,14 @@ +2002-09-14 Hans-Peter Nilsson <hp@bitrange.com> + + * target.c (ffetarget_memcpy_): Don't test nonexistent + HOST_BYTES_BIG_ENDIAN, HOST_BITS_BIG_ENDIAN. Check + HOST_WORDS_BIG_ENDIAN against both WORDS_BIG_ENDIAN and + BYTES_BIG_ENDIAN. + +2002-09-07 Jan Hubicka <jh@suse.cz> + + * com.c (ffe_type_for_mode): Handle long double. + 2002-08-30 Alan Modra <amodra@bigpond.net.au> * target.h (FFETARGET_32bit_longs): Don't define for powerpc64 or @@ -60,7 +71,7 @@ Mon Apr 15 10:59:14 2002 Mark Mitchell <mark@codesourcery.com> * Make-lang.in (f/target.o): Depend on diagnostic.h. * target.c: Include diagnostic.h. - (ffetarget_memcpy_): Call sorry if host and target endians are + (ffetarget_memcpy_): Call sorry if host and target endians are not matching. 2002-04-13 Toon Moene <toon@moene.indiv.nluug.nl> @@ -112,7 +123,7 @@ Mon Mar 18 18:43:22 CET 2002 Jan Hubicka <jh@suse.cz> * intrin.def: Use 'N' constraints in table of intrinsics. * intdoc.c: Document this constraint. * intdoc.texi: Regenerated. - + 2002-02-04 Philipp Thomas <pthomas@suse.de> * implic.c lex.c stb.c ste.c stu.c: Update copyright dates. diff --git a/contrib/gcc/f/com.c b/contrib/gcc/f/com.c index a915139..13de981 100644 --- a/contrib/gcc/f/com.c +++ b/contrib/gcc/f/com.c @@ -15014,7 +15014,10 @@ type_for_mode (mode, unsignedp) if (mode == TYPE_MODE (double_type_node)) return double_type_node; - if (mode == TYPE_MODE (build_pointer_type (char_type_node))) + if (mode == TYPE_MODE (long_double_type_node)) + return long_double_type_node; + + if (mode == TYPE_MODE (build_pointer_type (char_type_node))) return build_pointer_type (char_type_node); if (mode == TYPE_MODE (build_pointer_type (integer_type_node))) diff --git a/contrib/gcc/f/target.c b/contrib/gcc/f/target.c index f934a8f..086faed 100644 --- a/contrib/gcc/f/target.c +++ b/contrib/gcc/f/target.c @@ -2521,6 +2521,9 @@ void * ffetarget_memcpy_ (void *dst, void *src, size_t len) { #ifdef CROSS_COMPILE + /* HOST_WORDS_BIG_ENDIAN corresponds to both WORDS_BIG_ENDIAN and + BYTES_BIG_ENDIAN (i.e. there are no HOST_ macros to represent a + difference in the two latter). */ int host_words_big_endian = #ifndef HOST_WORDS_BIG_ENDIAN 0 @@ -2529,22 +2532,6 @@ ffetarget_memcpy_ (void *dst, void *src, size_t len) #endif ; - int host_bytes_big_endian = -#ifndef HOST_BYTES_BIG_ENDIAN - 0 -#else - HOST_BYTES_BIG_ENDIAN -#endif - ; - - int host_bits_big_endian = -#ifndef HOST_BITS_BIG_ENDIAN - 0 -#else - HOST_BITS_BIG_ENDIAN -#endif - ; - /* This is just hands thrown up in the air over bits coming through this function representing a number being memcpy:d as-is from host to target. We can't generally adjust endianness here since we don't @@ -2555,8 +2542,7 @@ ffetarget_memcpy_ (void *dst, void *src, size_t len) for instance in g77.f-torture/execute/980628-[4-6].f and alpha2.f. Still, we compile *some* code. FIXME: Rewrite handling of numbers. */ if (!WORDS_BIG_ENDIAN != !host_words_big_endian - || !BYTES_BIG_ENDIAN != !host_bytes_big_endian - || !BITS_BIG_ENDIAN != !host_bits_big_endian) + || !BYTES_BIG_ENDIAN != !host_words_big_endian) sorry ("data initializer on host with different endianness"); #endif /* CROSS_COMPILE */ diff --git a/contrib/gcc/f/version.c b/contrib/gcc/f/version.c index bfda27c..b9dc05c 100644 --- a/contrib/gcc/f/version.c +++ b/contrib/gcc/f/version.c @@ -1,4 +1,4 @@ #include "ansidecl.h" #include "f/version.h" -const char *const ffe_version_string = "3.2.1 20020831 (prerelease)"; +const char *const ffe_version_string = "3.2.1 20020916 (prerelease)"; diff --git a/contrib/gcc/loop.c b/contrib/gcc/loop.c index 4045ced..4450845 100644 --- a/contrib/gcc/loop.c +++ b/contrib/gcc/loop.c @@ -9264,7 +9264,7 @@ canonicalize_condition (insn, cond, reverse, earliest, want_reg) { case LE: if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1) - code = LT, op1 = GEN_INT (const_val + 1); + code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0)); break; /* When cross-compiling, const_val might be sign-extended from @@ -9273,17 +9273,17 @@ canonicalize_condition (insn, cond, reverse, earliest, want_reg) if ((HOST_WIDE_INT) (const_val & max_val) != (((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) - code = GT, op1 = GEN_INT (const_val - 1); + code = GT, op1 = gen_int_mode (const_val - 1, GET_MODE (op0)); break; case LEU: if (uconst_val < max_val) - code = LTU, op1 = GEN_INT (uconst_val + 1); + code = LTU, op1 = gen_int_mode (uconst_val + 1, GET_MODE (op0)); break; case GEU: if (uconst_val != 0) - code = GTU, op1 = GEN_INT (uconst_val - 1); + code = GTU, op1 = gen_int_mode (uconst_val - 1, GET_MODE (op0)); break; default: diff --git a/contrib/gcc/optabs.c b/contrib/gcc/optabs.c index d228e58..1cf2803 100644 --- a/contrib/gcc/optabs.c +++ b/contrib/gcc/optabs.c @@ -752,23 +752,18 @@ expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods) } /* In case the insn wants input operands in modes different from - the result, convert the operands. It would seem that we - don't need to convert CONST_INTs, but we do, so that they're - a properly sign-extended for their modes; we choose the - widest mode between mode and mode[01], so that, in a widening - operation, we call convert_modes with different FROM and TO - modes, which ensures the value is sign-extended. Shift - operations are an exception, because the second operand needs - not be extended to the mode of the result. */ + those of the actual operands, convert the operands. It would + seem that we don't need to convert CONST_INTs, but we do, so + that they're properly zero-extended or sign-extended for their + modes; shift operations are an exception, because the second + operand needs not be extended to the mode of the result. */ if (GET_MODE (op0) != mode0 && mode0 != VOIDmode) xop0 = convert_modes (mode0, GET_MODE (op0) != VOIDmode ? GET_MODE (op0) - : GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode0) - ? mode - : mode0, + : mode, xop0, unsignedp); if (GET_MODE (xop1) != mode1 @@ -776,8 +771,7 @@ expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods) xop1 = convert_modes (mode1, GET_MODE (op1) != VOIDmode ? GET_MODE (op1) - : (GET_MODE_SIZE (mode) > GET_MODE_SIZE (mode1) - && ! shift_op) + : ! shift_op ? mode : mode1, xop1, unsignedp); diff --git a/contrib/gcc/sched-deps.c b/contrib/gcc/sched-deps.c index 5904f91..f2f64d3 100644 --- a/contrib/gcc/sched-deps.c +++ b/contrib/gcc/sched-deps.c @@ -1118,8 +1118,6 @@ sched_analyze_insn (deps, x, insn, loop_notes) EXECUTE_IF_SET_IN_REG_SET (reg_pending_clobbers, 0, i, { struct deps_reg *reg_last = &deps->reg_last[i]; - add_dependence_list (insn, reg_last->sets, REG_DEP_OUTPUT); - add_dependence_list (insn, reg_last->uses, REG_DEP_ANTI); if (reg_last->uses_length > MAX_PENDING_LIST_LENGTH || reg_last->clobbers_length > MAX_PENDING_LIST_LENGTH) { @@ -1129,6 +1127,7 @@ sched_analyze_insn (deps, x, insn, loop_notes) REG_DEP_ANTI); add_dependence_list_and_free (insn, ®_last->clobbers, REG_DEP_OUTPUT); + reg_last->sets = alloc_INSN_LIST (insn, reg_last->sets); reg_last->clobbers_length = 0; reg_last->uses_length = 0; } diff --git a/contrib/gcc/unroll.c b/contrib/gcc/unroll.c index 6be951e..032d675 100644 --- a/contrib/gcc/unroll.c +++ b/contrib/gcc/unroll.c @@ -3997,12 +3997,6 @@ loop_iterations (loop) } return 0; } - else if (comparison_code == EQ) - { - if (loop_dump_stream) - fprintf (loop_dump_stream, "Loop iterations: EQ comparison loop.\n"); - return 0; - } else if (GET_CODE (final_value) != CONST_INT) { if (loop_dump_stream) @@ -4014,6 +4008,43 @@ loop_iterations (loop) } return 0; } + else if (comparison_code == EQ) + { + rtx inc_once; + + if (loop_dump_stream) + fprintf (loop_dump_stream, "Loop iterations: EQ comparison loop.\n"); + + inc_once = gen_int_mode (INTVAL (initial_value) + INTVAL (increment), + GET_MODE (iteration_var)); + + if (inc_once == final_value) + { + /* The iterator value once through the loop is equal to the + comparision value. Either we have an infinite loop, or + we'll loop twice. */ + if (increment == const0_rtx) + return 0; + loop_info->n_iterations = 2; + } + else + loop_info->n_iterations = 1; + + if (GET_CODE (loop_info->initial_value) == CONST_INT) + loop_info->final_value + = gen_int_mode ((INTVAL (loop_info->initial_value) + + loop_info->n_iterations * INTVAL (increment)), + GET_MODE (iteration_var)); + else + loop_info->final_value + = plus_constant (loop_info->initial_value, + loop_info->n_iterations * INTVAL (increment)); + loop_info->final_equiv_value + = gen_int_mode ((INTVAL (initial_value) + + loop_info->n_iterations * INTVAL (increment)), + GET_MODE (iteration_var)); + return loop_info->n_iterations; + } /* Final_larger is 1 if final larger, 0 if they are equal, otherwise -1. */ if (unsigned_p) |
