diff options
| -rw-r--r-- | sys/dev/bge/if_bge.c | 9 | ||||
| -rw-r--r-- | sys/dev/bge/if_bgereg.h | 3 |
2 files changed, 8 insertions, 4 deletions
diff --git a/sys/dev/bge/if_bge.c b/sys/dev/bge/if_bge.c index 2077c8c3..1bfd509 100644 --- a/sys/dev/bge/if_bge.c +++ b/sys/dev/bge/if_bge.c @@ -1295,8 +1295,7 @@ bge_stop_fw(sc) } /* - * Do endian, PCI and DMA initialization. Also check the on-board ROM - * self-test results. + * Do endian, PCI and DMA initialization. */ static int bge_chipinit(struct bge_softc *sc) @@ -1404,9 +1403,11 @@ bge_chipinit(struct bge_softc *sc) /* * Disable memory write invalidate. Apparently it is not supported - * properly by these devices. + * properly by these devices. Also ensure that INTx isn't disabled, + * as these chips need it even when using MSI. */ - PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); + PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, + PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); /* Set the timer prescaler (always 66Mhz) */ CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); diff --git a/sys/dev/bge/if_bgereg.h b/sys/dev/bge/if_bgereg.h index b38e77d..66e36b5 100644 --- a/sys/dev/bge/if_bgereg.h +++ b/sys/dev/bge/if_bgereg.h @@ -404,6 +404,9 @@ #ifndef PCIM_CMD_MWIEN #define PCIM_CMD_MWIEN 0x0010 #endif +#ifndef PCIM_CMD_INTxDIS +#define PCIM_CMD_INTxDIS 0x0400 +#endif /* * High priority mailbox registers |
