diff options
| -rw-r--r-- | sys/dev/ath/ath_hal/ar9002/ar9002phy.h | 7 | ||||
| -rw-r--r-- | sys/dev/ath/ath_hal/ar9002/ar9285_reset.c | 38 |
2 files changed, 44 insertions, 1 deletions
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9002phy.h b/sys/dev/ath/ath_hal/ar9002/ar9002phy.h index 1ff69d9..3d837cf 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9002phy.h +++ b/sys/dev/ath/ath_hal/ar9002/ar9002phy.h @@ -42,9 +42,16 @@ #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 +#define AR_PHY_TX_PWRCTRL8 0xa278 +#define AR_PHY_TX_PWRCTRL10 0xa394 #define AR_PHY_TX_GAIN_TBL1 0xa300 #define AR_PHY_TX_GAIN 0x0007F000 #define AR_PHY_TX_GAIN_S 12 +#define AR_PHY_CH0_TX_PWRCTRL11 0xa398 +#define AR_PHY_CH1_TX_PWRCTRL11 0xb398 +#define AR_PHY_CH0_TX_PWRCTRL12 0xa3dc +#define AR_PHY_CH0_TX_PWRCTRL13 0xa3e0 + #endif diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c b/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c index 33ef422..fd69de6 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c @@ -35,7 +35,7 @@ #include "ar5416/ar5416.h" #include "ar5416/ar5416reg.h" #include "ar5416/ar5416phy.h" - +#include "ar9002/ar9002phy.h" #include "ar9002/ar9285phy.h" /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ @@ -415,6 +415,42 @@ ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); } + /* + * Program the CCK TX gain factor appropriately if needed. + * The AR9285/AR9271 has a non-constant PA tx gain behaviour + * for CCK versus OFDM rates; other chips deal with this + * differently. + * + * The mask/shift/multiply hackery is done so place the same + * value (bb_desired_scale) into multiple 5-bit fields. + * For example, AR_PHY_TX_PWRCTRL9 has bb_desired_scale written + * to three fields: (0..4), (5..9) and (10..14). + */ + if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) { + uint8_t bb_desired_scale = (pModal->bb_scale_smrt_antenna & EEP_4K_BB_DESIRED_SCALE_MASK); + if ((eep->baseEepHeader.txGainType == 0) && (bb_desired_scale != 0)) { + uint32_t pwrctrl, mask, clr; + + mask = (1<<0) | (1<<5) | (1<<10) | (1<<15) | (1<<20) | (1<<25); + pwrctrl = mask * bb_desired_scale; + clr = mask * 0x1f; + OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); + OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); + OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); + + mask = (1<<0) | (1<<5) | (1<<15); + pwrctrl = mask * bb_desired_scale; + clr = mask * 0x1f; + OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); + + mask = (1<<0) | (1<<5); + pwrctrl = mask * bb_desired_scale; + clr = mask * 0x1f; + OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); + OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); + } + } + return AH_TRUE; } |
