diff options
| -rw-r--r-- | sys/dev/sfxge/common/efx.h | 2 | ||||
| -rw-r--r-- | sys/dev/sfxge/common/efx_impl.h | 14 | ||||
| -rw-r--r-- | sys/dev/sfxge/common/siena_nic.c | 3 | ||||
| -rw-r--r-- | sys/dev/sfxge/common/siena_sram.c | 7 |
4 files changed, 20 insertions, 6 deletions
diff --git a/sys/dev/sfxge/common/efx.h b/sys/dev/sfxge/common/efx.h index 92e271d..51e13f4 100644 --- a/sys/dev/sfxge/common/efx.h +++ b/sys/dev/sfxge/common/efx.h @@ -1622,6 +1622,7 @@ efx_rx_scale_toeplitz_ipv6_key_set( #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) +#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) typedef enum efx_rxq_type_e { EFX_RXQ_TYPE_DEFAULT, @@ -1708,6 +1709,7 @@ efx_tx_fini( #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) +#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize) extern __checkReturn int efx_tx_qcreate( diff --git a/sys/dev/sfxge/common/efx_impl.h b/sys/dev/sfxge/common/efx_impl.h index 31681f2..6202276 100644 --- a/sys/dev/sfxge/common/efx_impl.h +++ b/sys/dev/sfxge/common/efx_impl.h @@ -200,8 +200,18 @@ typedef struct efx_nic_ops_s { void (*eno_unprobe)(efx_nic_t *); } efx_nic_ops_t; -#define EFX_TXQ_LIMIT_TARGET 259 -#define EFX_RXQ_LIMIT_TARGET 768 +#ifndef EFX_TXQ_LIMIT_TARGET +# define EFX_TXQ_LIMIT_TARGET 259 +#endif +#ifndef EFX_RXQ_LIMIT_TARGET +# define EFX_RXQ_LIMIT_TARGET 768 +#endif +#ifndef EFX_TXQ_DC_SIZE +#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */ +#endif +#ifndef EFX_RXQ_DC_SIZE +#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */ +#endif #if EFSYS_OPT_FILTER diff --git a/sys/dev/sfxge/common/siena_nic.c b/sys/dev/sfxge/common/siena_nic.c index 9df2c02..8595bb8 100644 --- a/sys/dev/sfxge/common/siena_nic.c +++ b/sys/dev/sfxge/common/siena_nic.c @@ -365,7 +365,8 @@ siena_board_cfg( } encp->enc_buftbl_limit = SIENA_SRAM_ROWS - - (encp->enc_txq_limit * 16) - (encp->enc_rxq_limit * 64); + (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) - + (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE)); return (0); diff --git a/sys/dev/sfxge/common/siena_sram.c b/sys/dev/sfxge/common/siena_sram.c index 9c13e1d..3137e5b 100644 --- a/sys/dev/sfxge/common/siena_sram.c +++ b/sys/dev/sfxge/common/siena_sram.c @@ -44,20 +44,21 @@ siena_sram_init( EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); rx_base = encp->enc_buftbl_limit; - tx_base = rx_base + (encp->enc_rxq_limit * 64); + tx_base = rx_base + (encp->enc_rxq_limit * + EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE)); /* Initialize the transmit descriptor cache */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base); EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword); - EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, 1); /* 16 descriptors */ + EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE); EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword); /* Initialize the receive descriptor cache */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base); EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword); - EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, 3); /* 64 descriptors */ + EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE); EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword); /* Set receive descriptor pre-fetch low water mark */ |
