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-rw-r--r--sys/dev/ic/i8251.h103
-rw-r--r--sys/dev/ic/i8255.h46
-rw-r--r--sys/pc98/cbus/sio.c66
3 files changed, 133 insertions, 82 deletions
diff --git a/sys/dev/ic/i8251.h b/sys/dev/ic/i8251.h
index fab1ea4..162ab29 100644
--- a/sys/dev/ic/i8251.h
+++ b/sys/dev/ic/i8251.h
@@ -32,13 +32,25 @@
/*
* modified for PC9801 by M.Ishii
* Kyoto University Microcomputer Club (KMC)
- */
-
-/*
+ *
* modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
*/
-/* define command and status code */
+/* i8251 mode register */
+#define MOD8251_5BITS 0x00
+#define MOD8251_6BITS 0x04
+#define MOD8251_7BITS 0x08
+#define MOD8251_8BITS 0x0c
+#define MOD8251_PENAB 0x10 /* parity enable */
+#define MOD8251_PEVEN 0x20 /* parity even */
+#define MOD8251_STOP1 0x40 /* 1 stop bit */
+#define MOD8251_STOP15 0x80 /* 1.5 stop bit */
+#define MOD8251_STOP2 0xc0 /* 2 stop bit */
+#define MOD8251_CLKx1 0x01 /* x1 */
+#define MOD8251_CLKx16 0x02 /* x16 */
+#define MOD8251_CLKx64 0x03 /* x64 */
+
+/* i8251 command register */
#define CMD8251_TxEN 0x01 /* transmit enable */
#define CMD8251_DTR 0x02 /* assert DTR */
#define CMD8251_RxEN 0x04 /* receive enable */
@@ -46,59 +58,54 @@
#define CMD8251_ER 0x10 /* error reset */
#define CMD8251_RTS 0x20 /* assert RTS */
#define CMD8251_RESET 0x40 /* internal reset */
-#define CMD8251_EH 0x80 /* enter hunt mode (only synchronous mode)*/
+#define CMD8251_EH 0x80 /* enter hunt mode */
+/* i8251 status register */
#define STS8251_TxRDY 0x01 /* transmit READY */
#define STS8251_RxRDY 0x02 /* data exists in receive buffer */
#define STS8251_TxEMP 0x04 /* transmit buffer EMPTY */
#define STS8251_PE 0x08 /* perity error */
#define STS8251_OE 0x10 /* overrun error */
#define STS8251_FE 0x20 /* framing error */
-#define STS8251_BD_SD 0x40 /* break detect (async) / sync detect (sync) */
+#define STS8251_BI 0x40 /* break detect */
#define STS8251_DSR 0x80 /* DSR is asserted */
-#define STS8251F_TxEMP 0x01 /* transmit buffer EMPTY */
-#define STS8251F_TxRDY 0x02 /* transmit READY */
-#define STS8251F_RxRDY 0x04 /* data exists in receive buffer */
-#define STS8251F_OE 0x10 /* overrun error */
-#define STS8251F_PE 0x20 /* perity error */
-#define STS8251F_BD_SD 0x80 /* break detect (async) / sync detect (sync) */
-
-#define INTR8251F_DTCT 0x60 /* FIFO detection mask */
-#define INTR8251F_INTRV 0x0e /* interrupt event */
-#define INTR8251F_TO 0x0c /* receive timeout */
-#define INTR8251F_LSTS 0x06 /* line status */
-#define INTR8251F_RxRDY 0x04 /* receive READY */
-#define INTR8251F_TxRDY 0x02 /* transmit READY */
-#define INTR8251F_ISEV 0x01 /* event occured */
-#define INTR8251F_MSTS 0x00 /* modem status */
-
-#define CTRL8251F_ENABLE 0x01 /* enable FIFO */
-#define CTRL8251F_RCV_RST 0x02 /* reset receive FIFO */
-#define CTRL8251F_XMT_RST 0x04 /* reset transmit FIFO */
-
-#define MOD8251_5BITS 0x00
-#define MOD8251_6BITS 0x04
-#define MOD8251_7BITS 0x08
-#define MOD8251_8BITS 0x0c
-#define MOD8251_PDISAB 0x00 /* parity disable */
-#define MOD8251_PODD 0x10 /* parity odd */
-#define MOD8251_PEVEN 0x30 /* parity even */
-#define MOD8251_STOP1 0x40 /* stop bit len = 1bit */
-#define MOD8251_STOP2 0xc0 /* stop bit len = 2bit */
-#define MOD8251_CLKX16 0x02 /* x16 */
-#define MOD8251_CLKX1 0x01 /* x1 */
+/* i8251F line status register */
+#define FLSR_TxEMP 0x01 /* transmit buffer EMPTY */
+#define FLSR_TxRDY 0x02 /* transmit READY */
+#define FLSR_RxRDY 0x04 /* data exists in receive buffer */
+#define FLSR_OE 0x10 /* overrun error */
+#define FLSR_PE 0x20 /* perity error */
+#define FLSR_BI 0x80 /* break detect */
-#define CICSCD_CD 0x20 /* CD */
-#define CICSCD_CS 0x40 /* CS */
-#define CICSCD_CI 0x80 /* CI */
+/* i8251F modem status register */
+#define MSR_DCD 0x80 /* Current Data Carrier Detect */
+#define MSR_RI 0x40 /* Current Ring Indicator */
+#define MSR_DSR 0x20 /* Current Data Set Ready */
+#define MSR_CTS 0x10 /* Current Clear to Send */
+#define MSR_DDCD 0x08 /* DCD has changed state */
+#define MSR_TERI 0x04 /* RI has toggled low to high */
+#define MSR_DDSR 0x02 /* DSR has changed state */
+#define MSR_DCTS 0x01 /* CTS has changed state */
-#define CICSCDF_CS 0x10 /* CS */
-#define CICSCDF_DR 0x20 /* DR */
-#define CICSCDF_CI 0x40 /* CI */
-#define CICSCDF_CD 0x80 /* CD */
+/* i8251F interrupt identification register */
+#define IIR_FIFO_CK1 0x40
+#define IIR_FIFO_CK2 0x20
+#define IIR_IMASK 0x0f
+#define IIR_RXTOUT 0x0c /* Receiver timeout */
+#define IIR_RLS 0x06 /* Line status change */
+#define IIR_RXRDY 0x04 /* Receiver ready */
+#define IIR_TXRDY 0x02 /* Transmitter ready */
+#define IIR_NOPEND 0x01 /* Transmitter ready */
+#define IIR_MLSC 0x00 /* Modem status */
-/* interrupt mask control */
-#define IEN_Rx 0x01
-#define IEN_TxEMP 0x02
-#define IEN_Tx 0x04
+/* i8251F fifo control register */
+#define FIFO_ENABLE 0x01 /* Turn the FIFO on */
+#define FIFO_RCV_RST 0x02 /* Reset RX FIFO */
+#define FIFO_XMT_RST 0x04 /* Reset TX FIFO */
+#define FIFO_LSR_EN 0x08
+#define FIFO_MSR_EN 0x10
+#define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */
+#define FIFO_TRIGGER_4 0x40 /* ibid 4 */
+#define FIFO_TRIGGER_8 0x80 /* ibid 8 */
+#define FIFO_TRIGGER_14 0xc0 /* ibid 14 */
diff --git a/sys/dev/ic/i8255.h b/sys/dev/ic/i8255.h
new file mode 100644
index 0000000..1ecfe50
--- /dev/null
+++ b/sys/dev/ic/i8255.h
@@ -0,0 +1,46 @@
+/*-
+ * Copyright (c) 2008 TAKAHASHI Yoshihiro
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _DEV_IC_I8255_H_
+#define _DEV_IC_I8255_H_
+
+/*
+ * modem status via SYSTM_PORTB
+ */
+#define CICSCD_CD 0x20 /* CD */
+#define CICSCD_CS 0x40 /* CS */
+#define CICSCD_CI 0x80 /* CI */
+
+/*
+ * control intrline via SYSTM_PORTC
+ */
+#define IEN_Rx 0x01
+#define IEN_TxEMP 0x02
+#define IEN_Tx 0x04
+
+#endif /* _DEV_IC_I8255_H_ */
diff --git a/sys/pc98/cbus/sio.c b/sys/pc98/cbus/sio.c
index 7089578..0bd4bd8 100644
--- a/sys/pc98/cbus/sio.c
+++ b/sys/pc98/cbus/sio.c
@@ -121,6 +121,7 @@
#include <dev/ic/ns16550.h>
#ifdef PC98
#include <dev/ic/i8251.h>
+#include <dev/ic/i8255.h>
#include <dev/ic/rsa.h>
#endif
@@ -1784,8 +1785,8 @@ comopen(struct tty *tp, struct cdev *dev)
pc98_msrint_start(dev);
if (com->pc98_8251fifo) {
com->pc98_8251fifo_enable = 1;
- outb(I8251F_fcr, CTRL8251F_ENABLE |
- CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
+ outb(I8251F_fcr,
+ FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST);
}
}
#endif
@@ -1803,8 +1804,7 @@ comopen(struct tty *tp, struct cdev *dev)
*/
for (i = 0; i < 500; i++) {
sio_setreg(com, com_fifo,
- FIFO_RCV_RST | FIFO_XMT_RST
- | com->fifo_image);
+ FIFO_RCV_RST | FIFO_XMT_RST | com->fifo_image);
#ifdef PC98
if (com->pc98_if_type == COM_IF_RSA98III)
outb(com->rsabase + rsa_frr , 0x00);
@@ -1955,7 +1955,7 @@ comclose(tp)
#ifdef PC98
if (com->pc98_8251fifo) {
if (com->pc98_8251fifo_enable)
- outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
+ outb(I8251F_fcr, FIFO_XMT_RST | FIFO_RCV_RST);
com->pc98_8251fifo_enable = 0;
}
#endif
@@ -1997,8 +1997,8 @@ siobusycheck(chan)
#ifdef PC98
else if ((IS_8251(com->pc98_if_type) &&
((com->pc98_8251fifo_enable &&
- (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP))
- == (STS8251F_TxRDY | STS8251F_TxEMP)) ||
+ (inb(I8251F_lsr) & (FLSR_TxRDY | FLSR_TxEMP))
+ == (FLSR_TxRDY | FLSR_TxEMP)) ||
(!com->pc98_8251fifo_enable &&
(inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
== (STS8251_TxRDY | STS8251_TxEMP)))) ||
@@ -2298,12 +2298,12 @@ status_read:;
more_intr:
line_status = 0;
if (com->pc98_8251fifo_enable) {
- if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY;
- if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY;
- if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE;
- if (tmp & STS8251F_PE) line_status |= LSR_PE;
- if (tmp & STS8251F_OE) line_status |= LSR_OE;
- if (tmp & STS8251F_BD_SD) line_status |= LSR_BI;
+ if (tmp & FLSR_TxRDY) line_status |= LSR_TXRDY;
+ if (tmp & FLSR_RxRDY) line_status |= LSR_RXRDY;
+ if (tmp & FLSR_TxEMP) line_status |= LSR_TSRE;
+ if (tmp & FLSR_PE) line_status |= LSR_PE;
+ if (tmp & FLSR_OE) line_status |= LSR_OE;
+ if (tmp & FLSR_BI) line_status |= LSR_BI;
} else {
if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
@@ -2311,7 +2311,7 @@ more_intr:
if (tmp & STS8251_PE) line_status |= LSR_PE;
if (tmp & STS8251_OE) line_status |= LSR_OE;
if (tmp & STS8251_FE) line_status |= LSR_FE;
- if (tmp & STS8251_BD_SD) line_status |= LSR_BI;
+ if (tmp & STS8251_BI) line_status |= LSR_BI;
}
} else {
#endif /* PC98 */
@@ -2345,15 +2345,15 @@ more_intr:
if (IS_8251(com->pc98_if_type)) {
if (com->pc98_8251fifo_enable) {
recv_data = inb(I8251F_data);
- if (tmp & (STS8251F_PE | STS8251F_OE |
- STS8251F_BD_SD)) {
+ if (tmp &
+ (FLSR_PE | FLSR_OE | FLSR_BI)) {
pc98_i8251_or_cmd(com, CMD8251_ER);
recv_data = 0;
}
} else {
recv_data = inb(com->data_port);
if (tmp & (STS8251_PE | STS8251_OE |
- STS8251_FE | STS8251_BD_SD)) {
+ STS8251_FE | STS8251_BI)) {
pc98_i8251_or_cmd(com, CMD8251_ER);
recv_data = 0;
}
@@ -2626,7 +2626,7 @@ txrdy:
}
if (IS_8251(com->pc98_if_type)) {
if (com->pc98_8251fifo_enable) {
- if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY)
+ if ((tmp = inb(I8251F_lsr)) & FLSR_RxRDY)
goto more_intr;
} else {
if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
@@ -3874,10 +3874,10 @@ pc98_get_modem_status(struct com_s *com)
int stat2;
stat2 = inb(I8251F_msr);
- if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR;
- if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI;
- if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR;
- if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS;
+ if ( stat2 & MSR_DCD ) msr |= TIOCM_CAR;
+ if ( stat2 & MSR_RI ) msr |= TIOCM_RI;
+ if ( stat2 & MSR_DSR ) msr |= TIOCM_DSR;
+ if ( stat2 & MSR_CTS ) msr |= TIOCM_CTS;
#if COM_CARRIER_DETECT_EMULATE
if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
msr |= TIOCM_CAR;
@@ -4005,7 +4005,7 @@ pc98_i8251_clear_cmd(struct com_s *com, int x)
outb(com->cmd_port, tmp);
com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
if (com->pc98_8251fifo_enable)
- outb(I8251F_fcr, CTRL8251F_ENABLE);
+ outb(I8251F_fcr, FIFO_ENABLE);
COM_INT_ENABLE
}
@@ -4021,7 +4021,7 @@ pc98_i8251_or_cmd(struct com_s *com, int x)
outb(com->cmd_port, tmp);
com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
if (com->pc98_8251fifo_enable)
- outb(I8251F_fcr, CTRL8251F_ENABLE);
+ outb(I8251F_fcr, FIFO_ENABLE);
COM_INT_ENABLE
}
@@ -4037,7 +4037,7 @@ pc98_i8251_set_cmd(struct com_s *com, int x)
outb(com->cmd_port, tmp);
com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
if (com->pc98_8251fifo_enable)
- outb(I8251F_fcr, CTRL8251F_ENABLE);
+ outb(I8251F_fcr, FIFO_ENABLE);
COM_INT_ENABLE
}
@@ -4053,7 +4053,7 @@ pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
outb(com->cmd_port, tmp);
com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
if (com->pc98_8251fifo_enable)
- outb(I8251F_fcr, CTRL8251F_ENABLE);
+ outb(I8251F_fcr, FIFO_ENABLE);
COM_INT_ENABLE
}
@@ -4088,8 +4088,7 @@ pc98_i8251_reset(struct com_s *com, int mode, int command)
pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
DELAY(10);
if (com->pc98_8251fifo_enable)
- outb(I8251F_fcr, CTRL8251F_ENABLE |
- CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
+ outb(I8251F_fcr, FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST);
}
static void
@@ -4131,11 +4130,10 @@ com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
}
if ( cflag&PARENB ) {
if ( cflag&PARODD )
- cfcr |= MOD8251_PODD;
+ cfcr |= MOD8251_PENAB;
else
- cfcr |= MOD8251_PEVEN;
- } else
- cfcr |= MOD8251_PDISAB;
+ cfcr |= MOD8251_PENAB | MOD8251_PEVEN;
+ }
if ( cflag&CSTOPB )
cfcr |= MOD8251_STOP2;
@@ -4143,9 +4141,9 @@ com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
cfcr |= MOD8251_STOP1;
if ( count & 0x10000 )
- cfcr |= MOD8251_CLKX1;
+ cfcr |= MOD8251_CLKx1;
else
- cfcr |= MOD8251_CLKX16;
+ cfcr |= MOD8251_CLKx16;
while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
;
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