diff options
| -rw-r--r-- | lib/libpmc/libpmc.c | 63 | ||||
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_armv7.c | 90 | ||||
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_armv7.h | 5 | ||||
| -rw-r--r-- | sys/dev/hwpmc/pmc_events.h | 369 | ||||
| -rw-r--r-- | sys/sys/pmc.h | 7 |
5 files changed, 424 insertions, 110 deletions
diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c index d9d7902..9305618 100644 --- a/lib/libpmc/libpmc.c +++ b/lib/libpmc/libpmc.c @@ -268,6 +268,16 @@ static const struct pmc_event_descr westmereuc_event_table[] = __PMC_EV_ALIAS_WESTMEREUC() }; +static const struct pmc_event_descr cortex_a8_event_table[] = +{ + __PMC_EV_ALIAS_ARMV7_CORTEX_A8() +}; + +static const struct pmc_event_descr cortex_a9_event_table[] = +{ + __PMC_EV_ALIAS_ARMV7_CORTEX_A9() +}; + static const struct pmc_event_descr cortex_a53_event_table[] = { __PMC_EV_ALIAS_ARMV8_CORTEX_A53() @@ -308,7 +318,8 @@ PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); -PMC_MDEP_TABLE(armv7, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); +PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); +PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); @@ -377,7 +388,8 @@ PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); #if defined(__XSCALE__) PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); #endif -PMC_CLASS_TABLE_DESC(armv7, ARMV7, armv7, armv7); +PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a9, armv7); +PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7); #endif #if defined(__aarch64__) PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64); @@ -2436,12 +2448,20 @@ xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, } #endif -static struct pmc_event_alias armv7_aliases[] = { +static struct pmc_event_alias cortex_a8_aliases[] = { EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), EV_ALIAS("instructions", "INSTR_EXECUTED"), EV_ALIAS(NULL, NULL) }; + +static struct pmc_event_alias cortex_a9_aliases[] = { + EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"), + EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"), + EV_ALIAS("instructions", "INSTR_EXECUTED"), + EV_ALIAS(NULL, NULL) +}; + static int armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, struct pmc_op_pmcallocate *pmc_config __unused) @@ -2981,8 +3001,17 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, count = PMC_EVENT_TABLE_SIZE(xscale); break; case PMC_CLASS_ARMV7: - ev = armv7_event_table; - count = PMC_EVENT_TABLE_SIZE(armv7); + switch (cpu_info.pm_cputype) { + default: + case PMC_CPU_ARMV7_CORTEX_A8: + ev = cortex_a8_event_table; + count = PMC_EVENT_TABLE_SIZE(cortex_a8); + break; + case PMC_CPU_ARMV7_CORTEX_A9: + ev = cortex_a9_event_table; + count = PMC_EVENT_TABLE_SIZE(cortex_a9); + break; + } break; case PMC_CLASS_ARMV8: switch (cpu_info.pm_cputype) { @@ -3289,9 +3318,13 @@ pmc_init(void) pmc_class_table[n] = &xscale_class_table_descr; break; #endif - case PMC_CPU_ARMV7: - PMC_MDEP_INIT(armv7); - pmc_class_table[n] = &armv7_class_table_descr; + case PMC_CPU_ARMV7_CORTEX_A8: + PMC_MDEP_INIT(cortex_a8); + pmc_class_table[n] = &cortex_a8_class_table_descr; + break; + case PMC_CPU_ARMV7_CORTEX_A9: + PMC_MDEP_INIT(cortex_a9); + pmc_class_table[n] = &cortex_a9_class_table_descr; break; #endif #if defined(__aarch64__) @@ -3515,8 +3548,18 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) ev = xscale_event_table; evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { - ev = armv7_event_table; - evfence = armv7_event_table + PMC_EVENT_TABLE_SIZE(armv7); + switch (cpu) { + case PMC_CPU_ARMV7_CORTEX_A8: + ev = cortex_a8_event_table; + evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8); + break; + case PMC_CPU_ARMV7_CORTEX_A9: + ev = cortex_a9_event_table; + evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9); + break; + default: /* Unknown CPU type. */ + break; + } } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) { switch (cpu) { case PMC_CPU_ARMV8_CORTEX_A53: diff --git a/sys/dev/hwpmc/hwpmc_armv7.c b/sys/dev/hwpmc/hwpmc_armv7.c index 66d4971..469eca8 100644 --- a/sys/dev/hwpmc/hwpmc_armv7.c +++ b/sys/dev/hwpmc/hwpmc_armv7.c @@ -39,9 +39,6 @@ __FBSDID("$FreeBSD$"); #include <machine/pmc_mdep.h> #include <machine/cpu.h> -#define CPU_ID_CORTEX_VER_MASK 0xff -#define CPU_ID_CORTEX_VER_SHIFT 4 - static int armv7_npmcs; struct armv7_event_code_map { @@ -49,49 +46,11 @@ struct armv7_event_code_map { uint8_t pe_code; }; -const struct armv7_event_code_map armv7_event_codes[] = { - { PMC_EV_ARMV7_PMNC_SW_INCR, 0x00 }, - { PMC_EV_ARMV7_L1_ICACHE_REFILL, 0x01 }, - { PMC_EV_ARMV7_ITLB_REFILL, 0x02 }, - { PMC_EV_ARMV7_L1_DCACHE_REFILL, 0x03 }, - { PMC_EV_ARMV7_L1_DCACHE_ACCESS, 0x04 }, - { PMC_EV_ARMV7_DTLB_REFILL, 0x05 }, - { PMC_EV_ARMV7_MEM_READ, 0x06 }, - { PMC_EV_ARMV7_MEM_WRITE, 0x07 }, - { PMC_EV_ARMV7_INSTR_EXECUTED, 0x08 }, - { PMC_EV_ARMV7_EXC_TAKEN, 0x09 }, - { PMC_EV_ARMV7_EXC_EXECUTED, 0x0A }, - { PMC_EV_ARMV7_CID_WRITE, 0x0B }, - { PMC_EV_ARMV7_PC_WRITE, 0x0C }, - { PMC_EV_ARMV7_PC_IMM_BRANCH, 0x0D }, - { PMC_EV_ARMV7_PC_PROC_RETURN, 0x0E }, - { PMC_EV_ARMV7_MEM_UNALIGNED_ACCESS, 0x0F }, - { PMC_EV_ARMV7_PC_BRANCH_MIS_PRED, 0x10 }, - { PMC_EV_ARMV7_CLOCK_CYCLES, 0x11 }, - { PMC_EV_ARMV7_PC_BRANCH_PRED, 0x12 }, - { PMC_EV_ARMV7_MEM_ACCESS, 0x13 }, - { PMC_EV_ARMV7_L1_ICACHE_ACCESS, 0x14 }, - { PMC_EV_ARMV7_L1_DCACHE_WB, 0x15 }, - { PMC_EV_ARMV7_L2_CACHE_ACCESS, 0x16 }, - { PMC_EV_ARMV7_L2_CACHE_REFILL, 0x17 }, - { PMC_EV_ARMV7_L2_CACHE_WB, 0x18 }, - { PMC_EV_ARMV7_BUS_ACCESS, 0x19 }, - { PMC_EV_ARMV7_MEM_ERROR, 0x1A }, - { PMC_EV_ARMV7_INSTR_SPEC, 0x1B }, - { PMC_EV_ARMV7_TTBR_WRITE, 0x1C }, - { PMC_EV_ARMV7_BUS_CYCLES, 0x1D }, - { PMC_EV_ARMV7_CPU_CYCLES, 0xFF }, -}; - -const int armv7_event_codes_size = - sizeof(armv7_event_codes) / sizeof(armv7_event_codes[0]); - /* * Per-processor information. */ struct armv7_cpu { struct pmc_hw *pc_armv7pmcs; - int cortex_ver; }; static struct armv7_cpu **armv7_pcpu; @@ -173,10 +132,10 @@ static int armv7_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { - uint32_t caps, config; struct armv7_cpu *pac; enum pmc_event pe; - int i; + uint32_t config; + uint32_t caps; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); @@ -190,18 +149,10 @@ armv7_allocate_pmc(int cpu, int ri, struct pmc *pm, return (EINVAL); pe = a->pm_ev; - for (i = 0; i < armv7_event_codes_size; i++) { - if (armv7_event_codes[i].pe_ev == pe) { - config = armv7_event_codes[i].pe_code; - break; - } - } - if (i == armv7_event_codes_size) - return EINVAL; - + config = (pe & EVENT_ID_MASK); pm->pm_md.pm_armv7.pm_armv7_evsel = config; - PMCDBG2(MDP,ALL,2,"armv7-allocate ri=%d -> config=0x%x", ri, config); + PMCDBG2(MDP, ALL, 2, "armv7-allocate ri=%d -> config=0x%x", ri, config); return 0; } @@ -225,7 +176,7 @@ armv7_read_pmc(int cpu, int ri, pmc_value_t *v) else tmp = armv7_pmcn_read(ri); - PMCDBG2(MDP,REA,2,"armv7-read id=%d -> %jd", ri, tmp); + PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) *v = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); else @@ -249,7 +200,7 @@ armv7_write_pmc(int cpu, int ri, pmc_value_t v) if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) v = ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(v); - PMCDBG3(MDP,WRI,1,"armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v); + PMCDBG3(MDP, WRI, 1, "armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v); if (pm->pm_md.pm_armv7.pm_armv7_evsel == 0xFF) cp15_pmccntr_set(v); @@ -264,7 +215,7 @@ armv7_config_pmc(int cpu, int ri, struct pmc *pm) { struct pmc_hw *phw; - PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); + PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); @@ -457,20 +408,15 @@ armv7_pcpu_init(struct pmc_mdep *md, int cpu) struct pmc_cpu *pc; uint32_t pmnc; int first_ri; - int cpuid; int i; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[armv7,%d] wrong cpu number %d", __LINE__, cpu)); - PMCDBG1(MDP,INI,1,"armv7-init cpu=%d", cpu); + PMCDBG1(MDP, INI, 1, "armv7-init cpu=%d", cpu); armv7_pcpu[cpu] = pac = malloc(sizeof(struct armv7_cpu), M_PMC, M_WAITOK|M_ZERO); - cpuid = cpu_ident(); - pac->cortex_ver = (cpuid >> CPU_ID_CORTEX_VER_SHIFT) & \ - CPU_ID_CORTEX_VER_MASK; - pac->pc_armv7pmcs = malloc(sizeof(struct pmc_hw) * armv7_npmcs, M_PMC, M_WAITOK|M_ZERO); pc = pmc_pcpu[cpu]; @@ -509,14 +455,15 @@ pmc_armv7_initialize() { struct pmc_mdep *pmc_mdep; struct pmc_classdep *pcd; + int idcode; int reg; reg = cp15_pmcr_get(); - armv7_npmcs = (reg >> ARMV7_PMNC_N_SHIFT) & \ ARMV7_PMNC_N_MASK; + idcode = (reg & ARMV7_IDCODE_MASK) >> ARMV7_IDCODE_SHIFT; - PMCDBG1(MDP,INI,1,"armv7-init npmcs=%d", armv7_npmcs); + PMCDBG1(MDP, INI, 1, "armv7-init npmcs=%d", armv7_npmcs); /* * Allocate space for pointers to PMC HW descriptors and for @@ -527,7 +474,20 @@ pmc_armv7_initialize() /* Just one class */ pmc_mdep = pmc_mdep_alloc(1); - pmc_mdep->pmd_cputype = PMC_CPU_ARMV7; + + switch (idcode) { + case ARMV7_IDCODE_CORTEX_A9: + pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A9; + break; + default: + case ARMV7_IDCODE_CORTEX_A8: + /* + * On A8 we implemented common events only, + * so use it for the rest of machines. + */ + pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A8; + break; + } pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7]; pcd->pcd_caps = ARMV7_PMC_CAPS; diff --git a/sys/dev/hwpmc/hwpmc_armv7.h b/sys/dev/hwpmc/hwpmc_armv7.h index 35f7d5b..5282345f 100644 --- a/sys/dev/hwpmc/hwpmc_armv7.h +++ b/sys/dev/hwpmc/hwpmc_armv7.h @@ -48,9 +48,14 @@ #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters implemented */ #define ARMV7_PMNC_N_MASK 0x1f #define ARMV7_PMNC_MASK 0x3f /* Writable bits */ +#define ARMV7_IDCODE_SHIFT 16 /* Identification code */ +#define ARMV7_IDCODE_MASK (0xff << ARMV7_IDCODE_SHIFT) +#define ARMV7_IDCODE_CORTEX_A9 9 +#define ARMV7_IDCODE_CORTEX_A8 8 #define ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R)) #define ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) +#define EVENT_ID_MASK 0xFF #ifdef _KERNEL /* MD extension for 'struct pmc' */ diff --git a/sys/dev/hwpmc/pmc_events.h b/sys/dev/hwpmc/pmc_events.h index 467367f..96dc900 100644 --- a/sys/dev/hwpmc/pmc_events.h +++ b/sys/dev/hwpmc/pmc_events.h @@ -4766,41 +4766,342 @@ __PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_84H_01H) * ARMv7 Events */ -#define __PMC_EV_ARMV7() \ - __PMC_EV(ARMV7, PMNC_SW_INCR) \ - __PMC_EV(ARMV7, L1_ICACHE_REFILL) \ - __PMC_EV(ARMV7, ITLB_REFILL) \ - __PMC_EV(ARMV7, L1_DCACHE_REFILL) \ - __PMC_EV(ARMV7, L1_DCACHE_ACCESS) \ - __PMC_EV(ARMV7, DTLB_REFILL) \ - __PMC_EV(ARMV7, MEM_READ) \ - __PMC_EV(ARMV7, MEM_WRITE) \ - __PMC_EV(ARMV7, INSTR_EXECUTED) \ - __PMC_EV(ARMV7, EXC_TAKEN) \ - __PMC_EV(ARMV7, EXC_EXECUTED) \ - __PMC_EV(ARMV7, CID_WRITE) \ - __PMC_EV(ARMV7, PC_WRITE) \ - __PMC_EV(ARMV7, PC_IMM_BRANCH) \ - __PMC_EV(ARMV7, PC_PROC_RETURN) \ - __PMC_EV(ARMV7, MEM_UNALIGNED_ACCESS) \ - __PMC_EV(ARMV7, PC_BRANCH_MIS_PRED) \ - __PMC_EV(ARMV7, CLOCK_CYCLES) \ - __PMC_EV(ARMV7, PC_BRANCH_PRED) \ - __PMC_EV(ARMV7, MEM_ACCESS) \ - __PMC_EV(ARMV7, L1_ICACHE_ACCESS) \ - __PMC_EV(ARMV7, L1_DCACHE_WB) \ - __PMC_EV(ARMV7, L2_CACHE_ACCESS) \ - __PMC_EV(ARMV7, L2_CACHE_REFILL) \ - __PMC_EV(ARMV7, L2_CACHE_WB) \ - __PMC_EV(ARMV7, BUS_ACCESS) \ - __PMC_EV(ARMV7, MEM_ERROR) \ - __PMC_EV(ARMV7, INSTR_SPEC) \ - __PMC_EV(ARMV7, TTBR_WRITE) \ - __PMC_EV(ARMV7, BUS_CYCLES) \ - __PMC_EV(ARMV7, CPU_CYCLES) +#define __PMC_EV_ARMV7() \ + __PMC_EV(ARMV7, EVENT_00H) \ + __PMC_EV(ARMV7, EVENT_01H) \ + __PMC_EV(ARMV7, EVENT_02H) \ + __PMC_EV(ARMV7, EVENT_03H) \ + __PMC_EV(ARMV7, EVENT_04H) \ + __PMC_EV(ARMV7, EVENT_05H) \ + __PMC_EV(ARMV7, EVENT_06H) \ + __PMC_EV(ARMV7, EVENT_07H) \ + __PMC_EV(ARMV7, EVENT_08H) \ + __PMC_EV(ARMV7, EVENT_09H) \ + __PMC_EV(ARMV7, EVENT_0AH) \ + __PMC_EV(ARMV7, EVENT_0BH) \ + __PMC_EV(ARMV7, EVENT_0CH) \ + __PMC_EV(ARMV7, EVENT_0DH) \ + __PMC_EV(ARMV7, EVENT_0EH) \ + __PMC_EV(ARMV7, EVENT_0FH) \ + __PMC_EV(ARMV7, EVENT_10H) \ + __PMC_EV(ARMV7, EVENT_11H) \ + __PMC_EV(ARMV7, EVENT_12H) \ + __PMC_EV(ARMV7, EVENT_13H) \ + __PMC_EV(ARMV7, EVENT_14H) \ + __PMC_EV(ARMV7, EVENT_15H) \ + __PMC_EV(ARMV7, EVENT_16H) \ + __PMC_EV(ARMV7, EVENT_17H) \ + __PMC_EV(ARMV7, EVENT_18H) \ + __PMC_EV(ARMV7, EVENT_19H) \ + __PMC_EV(ARMV7, EVENT_1AH) \ + __PMC_EV(ARMV7, EVENT_1BH) \ + __PMC_EV(ARMV7, EVENT_1CH) \ + __PMC_EV(ARMV7, EVENT_1DH) \ + __PMC_EV(ARMV7, EVENT_1EH) \ + __PMC_EV(ARMV7, EVENT_1FH) \ + __PMC_EV(ARMV7, EVENT_20H) \ + __PMC_EV(ARMV7, EVENT_21H) \ + __PMC_EV(ARMV7, EVENT_22H) \ + __PMC_EV(ARMV7, EVENT_23H) \ + __PMC_EV(ARMV7, EVENT_24H) \ + __PMC_EV(ARMV7, EVENT_25H) \ + __PMC_EV(ARMV7, EVENT_26H) \ + __PMC_EV(ARMV7, EVENT_27H) \ + __PMC_EV(ARMV7, EVENT_28H) \ + __PMC_EV(ARMV7, EVENT_29H) \ + __PMC_EV(ARMV7, EVENT_2AH) \ + __PMC_EV(ARMV7, EVENT_2BH) \ + __PMC_EV(ARMV7, EVENT_2CH) \ + __PMC_EV(ARMV7, EVENT_2DH) \ + __PMC_EV(ARMV7, EVENT_2EH) \ + __PMC_EV(ARMV7, EVENT_2FH) \ + __PMC_EV(ARMV7, EVENT_30H) \ + __PMC_EV(ARMV7, EVENT_31H) \ + __PMC_EV(ARMV7, EVENT_32H) \ + __PMC_EV(ARMV7, EVENT_33H) \ + __PMC_EV(ARMV7, EVENT_34H) \ + __PMC_EV(ARMV7, EVENT_35H) \ + __PMC_EV(ARMV7, EVENT_36H) \ + __PMC_EV(ARMV7, EVENT_37H) \ + __PMC_EV(ARMV7, EVENT_38H) \ + __PMC_EV(ARMV7, EVENT_39H) \ + __PMC_EV(ARMV7, EVENT_3AH) \ + __PMC_EV(ARMV7, EVENT_3BH) \ + __PMC_EV(ARMV7, EVENT_3CH) \ + __PMC_EV(ARMV7, EVENT_3DH) \ + __PMC_EV(ARMV7, EVENT_3EH) \ + __PMC_EV(ARMV7, EVENT_3FH) \ + __PMC_EV(ARMV7, EVENT_40H) \ + __PMC_EV(ARMV7, EVENT_41H) \ + __PMC_EV(ARMV7, EVENT_42H) \ + __PMC_EV(ARMV7, EVENT_43H) \ + __PMC_EV(ARMV7, EVENT_44H) \ + __PMC_EV(ARMV7, EVENT_45H) \ + __PMC_EV(ARMV7, EVENT_46H) \ + __PMC_EV(ARMV7, EVENT_47H) \ + __PMC_EV(ARMV7, EVENT_48H) \ + __PMC_EV(ARMV7, EVENT_49H) \ + __PMC_EV(ARMV7, EVENT_4AH) \ + __PMC_EV(ARMV7, EVENT_4BH) \ + __PMC_EV(ARMV7, EVENT_4CH) \ + __PMC_EV(ARMV7, EVENT_4DH) \ + __PMC_EV(ARMV7, EVENT_4EH) \ + __PMC_EV(ARMV7, EVENT_4FH) \ + __PMC_EV(ARMV7, EVENT_50H) \ + __PMC_EV(ARMV7, EVENT_51H) \ + __PMC_EV(ARMV7, EVENT_52H) \ + __PMC_EV(ARMV7, EVENT_53H) \ + __PMC_EV(ARMV7, EVENT_54H) \ + __PMC_EV(ARMV7, EVENT_55H) \ + __PMC_EV(ARMV7, EVENT_56H) \ + __PMC_EV(ARMV7, EVENT_57H) \ + __PMC_EV(ARMV7, EVENT_58H) \ + __PMC_EV(ARMV7, EVENT_59H) \ + __PMC_EV(ARMV7, EVENT_5AH) \ + __PMC_EV(ARMV7, EVENT_5BH) \ + __PMC_EV(ARMV7, EVENT_5CH) \ + __PMC_EV(ARMV7, EVENT_5DH) \ + __PMC_EV(ARMV7, EVENT_5EH) \ + __PMC_EV(ARMV7, EVENT_5FH) \ + __PMC_EV(ARMV7, EVENT_60H) \ + __PMC_EV(ARMV7, EVENT_61H) \ + __PMC_EV(ARMV7, EVENT_62H) \ + __PMC_EV(ARMV7, EVENT_63H) \ + __PMC_EV(ARMV7, EVENT_64H) \ + __PMC_EV(ARMV7, EVENT_65H) \ + __PMC_EV(ARMV7, EVENT_66H) \ + __PMC_EV(ARMV7, EVENT_67H) \ + __PMC_EV(ARMV7, EVENT_68H) \ + __PMC_EV(ARMV7, EVENT_69H) \ + __PMC_EV(ARMV7, EVENT_6AH) \ + __PMC_EV(ARMV7, EVENT_6BH) \ + __PMC_EV(ARMV7, EVENT_6CH) \ + __PMC_EV(ARMV7, EVENT_6DH) \ + __PMC_EV(ARMV7, EVENT_6EH) \ + __PMC_EV(ARMV7, EVENT_6FH) \ + __PMC_EV(ARMV7, EVENT_70H) \ + __PMC_EV(ARMV7, EVENT_71H) \ + __PMC_EV(ARMV7, EVENT_72H) \ + __PMC_EV(ARMV7, EVENT_73H) \ + __PMC_EV(ARMV7, EVENT_74H) \ + __PMC_EV(ARMV7, EVENT_75H) \ + __PMC_EV(ARMV7, EVENT_76H) \ + __PMC_EV(ARMV7, EVENT_77H) \ + __PMC_EV(ARMV7, EVENT_78H) \ + __PMC_EV(ARMV7, EVENT_79H) \ + __PMC_EV(ARMV7, EVENT_7AH) \ + __PMC_EV(ARMV7, EVENT_7BH) \ + __PMC_EV(ARMV7, EVENT_7CH) \ + __PMC_EV(ARMV7, EVENT_7DH) \ + __PMC_EV(ARMV7, EVENT_7EH) \ + __PMC_EV(ARMV7, EVENT_7FH) \ + __PMC_EV(ARMV7, EVENT_80H) \ + __PMC_EV(ARMV7, EVENT_81H) \ + __PMC_EV(ARMV7, EVENT_82H) \ + __PMC_EV(ARMV7, EVENT_83H) \ + __PMC_EV(ARMV7, EVENT_84H) \ + __PMC_EV(ARMV7, EVENT_85H) \ + __PMC_EV(ARMV7, EVENT_86H) \ + __PMC_EV(ARMV7, EVENT_87H) \ + __PMC_EV(ARMV7, EVENT_88H) \ + __PMC_EV(ARMV7, EVENT_89H) \ + __PMC_EV(ARMV7, EVENT_8AH) \ + __PMC_EV(ARMV7, EVENT_8BH) \ + __PMC_EV(ARMV7, EVENT_8CH) \ + __PMC_EV(ARMV7, EVENT_8DH) \ + __PMC_EV(ARMV7, EVENT_8EH) \ + __PMC_EV(ARMV7, EVENT_8FH) \ + __PMC_EV(ARMV7, EVENT_90H) \ + __PMC_EV(ARMV7, EVENT_91H) \ + __PMC_EV(ARMV7, EVENT_92H) \ + __PMC_EV(ARMV7, EVENT_93H) \ + __PMC_EV(ARMV7, EVENT_94H) \ + __PMC_EV(ARMV7, EVENT_95H) \ + __PMC_EV(ARMV7, EVENT_96H) \ + __PMC_EV(ARMV7, EVENT_97H) \ + __PMC_EV(ARMV7, EVENT_98H) \ + __PMC_EV(ARMV7, EVENT_99H) \ + __PMC_EV(ARMV7, EVENT_9AH) \ + __PMC_EV(ARMV7, EVENT_9BH) \ + __PMC_EV(ARMV7, EVENT_9CH) \ + __PMC_EV(ARMV7, EVENT_9DH) \ + __PMC_EV(ARMV7, EVENT_9EH) \ + __PMC_EV(ARMV7, EVENT_9FH) \ + __PMC_EV(ARMV7, EVENT_A0H) \ + __PMC_EV(ARMV7, EVENT_A1H) \ + __PMC_EV(ARMV7, EVENT_A2H) \ + __PMC_EV(ARMV7, EVENT_A3H) \ + __PMC_EV(ARMV7, EVENT_A4H) \ + __PMC_EV(ARMV7, EVENT_A5H) \ + __PMC_EV(ARMV7, EVENT_A6H) \ + __PMC_EV(ARMV7, EVENT_A7H) \ + __PMC_EV(ARMV7, EVENT_A8H) \ + __PMC_EV(ARMV7, EVENT_A9H) \ + __PMC_EV(ARMV7, EVENT_AAH) \ + __PMC_EV(ARMV7, EVENT_ABH) \ + __PMC_EV(ARMV7, EVENT_ACH) \ + __PMC_EV(ARMV7, EVENT_ADH) \ + __PMC_EV(ARMV7, EVENT_AEH) \ + __PMC_EV(ARMV7, EVENT_AFH) \ + __PMC_EV(ARMV7, EVENT_B0H) \ + __PMC_EV(ARMV7, EVENT_B1H) \ + __PMC_EV(ARMV7, EVENT_B2H) \ + __PMC_EV(ARMV7, EVENT_B3H) \ + __PMC_EV(ARMV7, EVENT_B4H) \ + __PMC_EV(ARMV7, EVENT_B5H) \ + __PMC_EV(ARMV7, EVENT_B6H) \ + __PMC_EV(ARMV7, EVENT_B7H) \ + __PMC_EV(ARMV7, EVENT_B8H) \ + __PMC_EV(ARMV7, EVENT_B9H) \ + __PMC_EV(ARMV7, EVENT_BAH) \ + __PMC_EV(ARMV7, EVENT_BBH) \ + __PMC_EV(ARMV7, EVENT_BCH) \ + __PMC_EV(ARMV7, EVENT_BDH) \ + __PMC_EV(ARMV7, EVENT_BEH) \ + __PMC_EV(ARMV7, EVENT_BFH) \ + __PMC_EV(ARMV7, EVENT_C0H) \ + __PMC_EV(ARMV7, EVENT_C1H) \ + __PMC_EV(ARMV7, EVENT_C2H) \ + __PMC_EV(ARMV7, EVENT_C3H) \ + __PMC_EV(ARMV7, EVENT_C4H) \ + __PMC_EV(ARMV7, EVENT_C5H) \ + __PMC_EV(ARMV7, EVENT_C6H) \ + __PMC_EV(ARMV7, EVENT_C7H) \ + __PMC_EV(ARMV7, EVENT_C8H) \ + __PMC_EV(ARMV7, EVENT_C9H) \ + __PMC_EV(ARMV7, EVENT_CAH) \ + __PMC_EV(ARMV7, EVENT_CBH) \ + __PMC_EV(ARMV7, EVENT_CCH) \ + __PMC_EV(ARMV7, EVENT_CDH) \ + __PMC_EV(ARMV7, EVENT_CEH) \ + __PMC_EV(ARMV7, EVENT_CFH) \ + __PMC_EV(ARMV7, EVENT_D0H) \ + __PMC_EV(ARMV7, EVENT_D1H) \ + __PMC_EV(ARMV7, EVENT_D2H) \ + __PMC_EV(ARMV7, EVENT_D3H) \ + __PMC_EV(ARMV7, EVENT_D4H) \ + __PMC_EV(ARMV7, EVENT_D5H) \ + __PMC_EV(ARMV7, EVENT_D6H) \ + __PMC_EV(ARMV7, EVENT_D7H) \ + __PMC_EV(ARMV7, EVENT_D8H) \ + __PMC_EV(ARMV7, EVENT_D9H) \ + __PMC_EV(ARMV7, EVENT_DAH) \ + __PMC_EV(ARMV7, EVENT_DBH) \ + __PMC_EV(ARMV7, EVENT_DCH) \ + __PMC_EV(ARMV7, EVENT_DDH) \ + __PMC_EV(ARMV7, EVENT_DEH) \ + __PMC_EV(ARMV7, EVENT_DFH) \ + __PMC_EV(ARMV7, EVENT_E0H) \ + __PMC_EV(ARMV7, EVENT_E1H) \ + __PMC_EV(ARMV7, EVENT_E2H) \ + __PMC_EV(ARMV7, EVENT_E3H) \ + __PMC_EV(ARMV7, EVENT_E4H) \ + __PMC_EV(ARMV7, EVENT_E5H) \ + __PMC_EV(ARMV7, EVENT_E6H) \ + __PMC_EV(ARMV7, EVENT_E7H) \ + __PMC_EV(ARMV7, EVENT_E8H) \ + __PMC_EV(ARMV7, EVENT_E9H) \ + __PMC_EV(ARMV7, EVENT_EAH) \ + __PMC_EV(ARMV7, EVENT_EBH) \ + __PMC_EV(ARMV7, EVENT_ECH) \ + __PMC_EV(ARMV7, EVENT_EDH) \ + __PMC_EV(ARMV7, EVENT_EEH) \ + __PMC_EV(ARMV7, EVENT_EFH) \ + __PMC_EV(ARMV7, EVENT_F0H) \ + __PMC_EV(ARMV7, EVENT_F1H) \ + __PMC_EV(ARMV7, EVENT_F2H) \ + __PMC_EV(ARMV7, EVENT_F3H) \ + __PMC_EV(ARMV7, EVENT_F4H) \ + __PMC_EV(ARMV7, EVENT_F5H) \ + __PMC_EV(ARMV7, EVENT_F6H) \ + __PMC_EV(ARMV7, EVENT_F7H) \ + __PMC_EV(ARMV7, EVENT_F8H) \ + __PMC_EV(ARMV7, EVENT_F9H) \ + __PMC_EV(ARMV7, EVENT_FAH) \ + __PMC_EV(ARMV7, EVENT_FBH) \ + __PMC_EV(ARMV7, EVENT_FCH) \ + __PMC_EV(ARMV7, EVENT_FDH) \ + __PMC_EV(ARMV7, EVENT_FEH) \ + __PMC_EV(ARMV7, EVENT_FFH) -#define PMC_EV_ARMV7_FIRST PMC_EV_ARMV7_PMNC_SW_INCR -#define PMC_EV_ARMV7_LAST PMC_EV_ARMV7_CPU_CYCLES +#define PMC_EV_ARMV7_FIRST PMC_EV_ARMV7_EVENT_00H +#define PMC_EV_ARMV7_LAST PMC_EV_ARMV7_EVENT_FFH + +#define __PMC_EV_ALIAS_ARMV7_COMMON() \ + __PMC_EV_ALIAS("PMNC_SW_INCR", ARMV7_EVENT_00H) \ + __PMC_EV_ALIAS("L1_ICACHE_REFILL", ARMV7_EVENT_01H) \ + __PMC_EV_ALIAS("ITLB_REFILL", ARMV7_EVENT_02H) \ + __PMC_EV_ALIAS("L1_DCACHE_REFILL", ARMV7_EVENT_03H) \ + __PMC_EV_ALIAS("L1_DCACHE_ACCESS", ARMV7_EVENT_04H) \ + __PMC_EV_ALIAS("DTLB_REFILL", ARMV7_EVENT_05H) \ + __PMC_EV_ALIAS("MEM_READ", ARMV7_EVENT_06H) \ + __PMC_EV_ALIAS("MEM_WRITE", ARMV7_EVENT_07H) \ + __PMC_EV_ALIAS("INSTR_EXECUTED", ARMV7_EVENT_08H) \ + __PMC_EV_ALIAS("EXC_TAKEN", ARMV7_EVENT_09H) \ + __PMC_EV_ALIAS("EXC_EXECUTED", ARMV7_EVENT_0AH) \ + __PMC_EV_ALIAS("CID_WRITE", ARMV7_EVENT_0BH) \ + __PMC_EV_ALIAS("PC_WRITE", ARMV7_EVENT_0CH) \ + __PMC_EV_ALIAS("PC_IMM_BRANCH", ARMV7_EVENT_0DH) \ + __PMC_EV_ALIAS("PC_PROC_RETURN", ARMV7_EVENT_0EH) \ + __PMC_EV_ALIAS("MEM_UNALIGNED_ACCESS", ARMV7_EVENT_0FH) \ + __PMC_EV_ALIAS("PC_BRANCH_MIS_PRED", ARMV7_EVENT_10H) \ + __PMC_EV_ALIAS("CLOCK_CYCLES", ARMV7_EVENT_11H) \ + __PMC_EV_ALIAS("PC_BRANCH_PRED", ARMV7_EVENT_12H) \ + __PMC_EV_ALIAS("MEM_ACCESS", ARMV7_EVENT_13H) \ + __PMC_EV_ALIAS("L1_ICACHE_ACCESS", ARMV7_EVENT_14H) \ + __PMC_EV_ALIAS("L1_DCACHE_WB", ARMV7_EVENT_15H) \ + __PMC_EV_ALIAS("L2_CACHE_ACCESS", ARMV7_EVENT_16H) \ + __PMC_EV_ALIAS("L2_CACHE_REFILL", ARMV7_EVENT_17H) \ + __PMC_EV_ALIAS("L2_CACHE_WB", ARMV7_EVENT_18H) \ + __PMC_EV_ALIAS("BUS_ACCESS", ARMV7_EVENT_19H) \ + __PMC_EV_ALIAS("MEM_ERROR", ARMV7_EVENT_1AH) \ + __PMC_EV_ALIAS("INSTR_SPEC", ARMV7_EVENT_1BH) \ + __PMC_EV_ALIAS("TTBR_WRITE", ARMV7_EVENT_1CH) \ + __PMC_EV_ALIAS("BUS_CYCLES", ARMV7_EVENT_1DH) \ + __PMC_EV_ALIAS("CPU_CYCLES", ARMV7_EVENT_FFH) + +#define __PMC_EV_ALIAS_ARMV7_CORTEX_A8() \ + __PMC_EV_ALIAS_ARMV7_COMMON() + +#define __PMC_EV_ALIAS_ARMV7_CORTEX_A9() \ + __PMC_EV_ALIAS_ARMV7_COMMON() \ + __PMC_EV_ALIAS("JAVA_BYTECODE", ARMV7_EVENT_40H) \ + __PMC_EV_ALIAS("SOFTWARE_JAVA_BYTECODE", ARMV7_EVENT_41H) \ + __PMC_EV_ALIAS("JAZELLE_BACKWARD_BRANCH", ARMV7_EVENT_42H) \ + __PMC_EV_ALIAS("COHERENT_LINEFILL_MISSC", ARMV7_EVENT_50H) \ + __PMC_EV_ALIAS("COHERENT_LINEFILL_HITC", ARMV7_EVENT_51H) \ + __PMC_EV_ALIAS("INSTR_CACHE_DEPENDENT_STALL", ARMV7_EVENT_60H) \ + __PMC_EV_ALIAS("DATA_CACHE_DEPENDENT_STALL", ARMV7_EVENT_61H) \ + __PMC_EV_ALIAS("MAIN_TLB_MISS_STALL", ARMV7_EVENT_62H) \ + __PMC_EV_ALIAS("STREX_PASSED", ARMV7_EVENT_63H) \ + __PMC_EV_ALIAS("STREX_FAILED", ARMV7_EVENT_64H) \ + __PMC_EV_ALIAS("DATA_EVICTION", ARMV7_EVENT_65H) \ + __PMC_EV_ALIAS("ISSUE_DNOT_DISPATCH_ANY_INSTR", ARMV7_EVENT_66H) \ + __PMC_EV_ALIAS("ISSUE_IS_EMPTY", ARMV7_EVENT_67H) \ + __PMC_EV_ALIAS("MAIN_EXECUTION_UNIT_PIPE", ARMV7_EVENT_70H) \ + __PMC_EV_ALIAS("SECOND_EXECUTION_UNIT_PIPE", ARMV7_EVENT_71H) \ + __PMC_EV_ALIAS("LOAD_STORE_PIPE", ARMV7_EVENT_72H) \ + __PMC_EV_ALIAS("FLOATING_POINT_INSTR_RENAMED", ARMV7_EVENT_73H) \ + __PMC_EV_ALIAS("NEON_INSTRS_RENAMED", ARMV7_EVENT_74H) \ + __PMC_EV_ALIAS("PLD_STALL", ARMV7_EVENT_80H) \ + __PMC_EV_ALIAS("WRITE_STALL", ARMV7_EVENT_81H) \ + __PMC_EV_ALIAS("INSTR_MAIN_TLB_MISS_STALL", ARMV7_EVENT_82H) \ + __PMC_EV_ALIAS("DATA_MAIN_TLB_MISS_STALL", ARMV7_EVENT_83H) \ + __PMC_EV_ALIAS("INSTR_MICRO_TLB_MISS_STALL", ARMV7_EVENT_84H) \ + __PMC_EV_ALIAS("DATA_MICRO_TLB_MISS_STALL", ARMV7_EVENT_85H) \ + __PMC_EV_ALIAS("DMB_STALL", ARMV7_EVENT_86H) \ + __PMC_EV_ALIAS("INTEGER_CORE_CLOCK_ENABLED", ARMV7_EVENT_8AH) \ + __PMC_EV_ALIAS("DATA_ENGINE_CLOCK_ENABLED", ARMV7_EVENT_8BH) \ + __PMC_EV_ALIAS("ISB", ARMV7_EVENT_90H) \ + __PMC_EV_ALIAS("DSB", ARMV7_EVENT_91H) \ + __PMC_EV_ALIAS("DMB", ARMV7_EVENT_92H) \ + __PMC_EV_ALIAS("EXTERNAL_INTERRUPT", ARMV7_EVENT_93H) \ + __PMC_EV_ALIAS("PLE_CACHE_LINE_REQ_COMPLETED", ARMV7_EVENT_A0H) \ + __PMC_EV_ALIAS("PLE_CACHE_LINE_REQ_SKIPPED", ARMV7_EVENT_A1H) \ + __PMC_EV_ALIAS("PLE_FIFO_FLUSH", ARMV7_EVENT_A2H) \ + __PMC_EV_ALIAS("PLE_REQUEST_COMPLETED", ARMV7_EVENT_A3H) \ + __PMC_EV_ALIAS("PLE_FIFO_OVERFLOW", ARMV7_EVENT_A4H) \ + __PMC_EV_ALIAS("PLE_REQUEST_PROGRAMMED", ARMV7_EVENT_A5H) /* * ARMv8 Events diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index f4d46b2..e0e7fcb 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -105,7 +105,12 @@ __PMC_CPU(PPC_MPC85XX, 0x340, "Freescale PowerPC MPC85XX") \ __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ __PMC_CPU(GENERIC, 0x400, "Generic") \ - __PMC_CPU(ARMV7, 0x500, "ARMv7") \ + __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ + __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ + __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ + __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ + __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ + __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") |
