diff options
| -rw-r--r-- | sys/arm/mv/common.c | 1 | ||||
| -rw-r--r-- | sys/arm/mv/discovery/db78xxx.c | 1 | ||||
| -rw-r--r-- | sys/arm/mv/discovery/discovery.c | 1 | ||||
| -rw-r--r-- | sys/arm/mv/kirkwood/db88f6xxx.c | 1 | ||||
| -rw-r--r-- | sys/arm/mv/kirkwood/kirkwood.c | 1 | ||||
| -rw-r--r-- | sys/arm/mv/mvreg.h | 245 | ||||
| -rw-r--r-- | sys/arm/mv/mvwin.h | 279 | ||||
| -rw-r--r-- | sys/arm/mv/orion/db88f5xxx.c | 2 | ||||
| -rw-r--r-- | sys/arm/mv/orion/orion.c | 1 | ||||
| -rw-r--r-- | sys/dev/uart/uart_cpu_mv.c | 1 | ||||
| -rw-r--r-- | sys/dev/usb/controller/ehci_mbus.c | 5 |
11 files changed, 292 insertions, 246 deletions
diff --git a/sys/arm/mv/common.c b/sys/arm/mv/common.c index 53ad91e..b2d13dd 100644 --- a/sys/arm/mv/common.c +++ b/sys/arm/mv/common.c @@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$"); #include <arm/mv/mvreg.h> #include <arm/mv/mvvar.h> +#include <arm/mv/mvwin.h> static int win_eth_can_remap(int i); diff --git a/sys/arm/mv/discovery/db78xxx.c b/sys/arm/mv/discovery/db78xxx.c index 52db6b6..98b2dff 100644 --- a/sys/arm/mv/discovery/db78xxx.c +++ b/sys/arm/mv/discovery/db78xxx.c @@ -47,6 +47,7 @@ __FBSDID("$FreeBSD$"); #include <arm/mv/mvreg.h> #include <arm/mv/mvvar.h> +#include <arm/mv/mvwin.h> /* * Virtual address space layout: diff --git a/sys/arm/mv/discovery/discovery.c b/sys/arm/mv/discovery/discovery.c index ce35e99..dddc448 100644 --- a/sys/arm/mv/discovery/discovery.c +++ b/sys/arm/mv/discovery/discovery.c @@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$"); #include <arm/mv/mvreg.h> #include <arm/mv/mvvar.h> +#include <arm/mv/mvwin.h> #define _MV_PCIE_MAX_PORT 8 diff --git a/sys/arm/mv/kirkwood/db88f6xxx.c b/sys/arm/mv/kirkwood/db88f6xxx.c index 8ff4f61..5f89010 100644 --- a/sys/arm/mv/kirkwood/db88f6xxx.c +++ b/sys/arm/mv/kirkwood/db88f6xxx.c @@ -47,6 +47,7 @@ __FBSDID("$FreeBSD$"); #include <arm/mv/mvreg.h> #include <arm/mv/mvvar.h> +#include <arm/mv/mvwin.h> /* * Virtual address space layout: diff --git a/sys/arm/mv/kirkwood/kirkwood.c b/sys/arm/mv/kirkwood/kirkwood.c index a2d41a6..675e79f 100644 --- a/sys/arm/mv/kirkwood/kirkwood.c +++ b/sys/arm/mv/kirkwood/kirkwood.c @@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$"); #include <arm/mv/mvreg.h> #include <arm/mv/mvvar.h> +#include <arm/mv/mvwin.h> struct obio_device obio_devices[] = { { "ic", MV_IC_BASE, MV_IC_SIZE, diff --git a/sys/arm/mv/mvreg.h b/sys/arm/mv/mvreg.h index 2551b1b..b91a672 100644 --- a/sys/arm/mv/mvreg.h +++ b/sys/arm/mv/mvreg.h @@ -34,120 +34,6 @@ #ifndef _MVREG_H_ #define _MVREG_H_ -#include <machine/intr.h> - -/* - * Physical addresses of integrated SoC peripherals - */ -#define MV_PHYS_BASE 0xF1000000 -#define MV_SIZE 0x100000 - -/* - * Decode windows addresses (physical) - */ -#define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) -#define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE -#define MV_PCIE_IO_SIZE (1024 * 1024) -#define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) -#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE -#define MV_PCI_IO_SIZE (1024 * 1024) - -#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) -#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE -#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) -#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) -#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE -#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) - -/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ - -/* 512KB NOR FLASH */ -#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) -#define MV_DEV_BOOT_SIZE (512 * 1024) -/* CS0: 7-seg LED */ -#define MV_DEV_CS0_PHYS_BASE 0xFA000000 -#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ -/* CS1: 32MB NOR FLASH */ -#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) -#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) -/* CS2: 32MB NAND FLASH */ -#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) -#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ - -#define MV_CESA_SRAM_PHYS_BASE 0xFD000000 -#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */ -#define MV_CESA_SRAM_SIZE (1024 * 1024) - -/* XXX this is probably not robust against wraparounds... */ -#if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF) -#error Devices memory layout overlaps reset vectors range! -#endif - -/* - * Integrated SoC peripherals addresses - */ -#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ -#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) -#define MV_MPP_BASE (MV_BASE + 0x10000) -#define MV_GPIO_BASE (MV_BASE + 0x10100) -#define MV_GPIO_SIZE 0x20 -#define MV_RTC_BASE (MV_BASE + 0x10300) -#define MV_RTC_SIZE 0x08 -#define MV_TWSI_BASE (MV_BASE + 0x11000) -#define MV_TWSI_SIZE 0x20 -#define MV_UART0_BASE (MV_BASE + 0x12000) -#define MV_UART1_BASE (MV_BASE + 0x12100) -#define MV_UART_SIZE 0x20 -#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) -#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) -#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) -#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) -#define MV_IC_SIZE 0x3C -#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300) -#define MV_TIMERS_SIZE 0x30 -#define MV_PCI_BASE (MV_BASE + 0x30000) -#define MV_PCI_SIZE 0x2000 -#if defined (SOC_MV_KIRKWOOD) -#define MV_CESA_BASE (MV_BASE + 0x30000) /* CESA,PCI don't coexist */ -#elif defined (SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) -#define MV_CESA_BASE (MV_BASE + 0x90000) -#endif -#define MV_CESA_SIZE 0x10000 -#define MV_PCIE_BASE (MV_BASE + 0x40000) -#define MV_PCIE_SIZE 0x2000 - -#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) -#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) -#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) -#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) -#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) -#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) -#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) -#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) - -#define MV_USB0_BASE (MV_BASE + 0x50000) -#define MV_USB1_BASE (MV_USB0_BASE + 0x1000) -#define MV_USB2_BASE (MV_USB0_BASE + 0x2000) -#define MV_USB_SIZE 0x1000 -#define MV_USB_HOST_OFST 0x0100 /* EHCI HC regs start at this offset within USB range */ -#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320) -#define MV_IDMA_BASE (MV_BASE + 0x60000) -#define MV_IDMA_SIZE 0x1000 -#define MV_XOR_BASE (MV_BASE + 0x60000) -#define MV_XOR_SIZE 0x1000 -#define MV_ETH0_BASE (MV_BASE + 0x72000) -#define MV_ETH1_BASE (MV_BASE + 0x76000) -#define MV_ETH_SIZE 0x2000 -#if defined(SOC_MV_ORION) || defined(SOC_MV_KIRKWOOD) -#define MV_SATAHC_BASE (MV_BASE + 0x80000) -#define MV_SATAHC_SIZE 0x6000 -#elif defined(SOC_MV_DISCOVERY) -#define MV_SATAHC_BASE (MV_BASE + 0xA0000) -#define MV_SATAHC_SIZE 0x6000 -#endif - -#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE - /* * Interrupt sources */ @@ -478,135 +364,4 @@ #define MV_DEV_MV78100_Z0 0x6381 #define MV_DEV_MV78100 0x7810 -/* - * Decode windows definitions and macros - */ -#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) -#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) -#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) -#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) -#if defined(SOC_MV_DISCOVERY) -#define MV_WIN_CPU_MAX 14 -#else -#define MV_WIN_CPU_MAX 8 -#endif - -#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) -#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) -#define MV_WIN_DDR_MAX 4 - -#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04) -#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) -#define MV_WIN_CESA_MAX 4 - -#define MV_WIN_USB_CTRL(n, m) (0x10 * (n) + (m) * 0x1000 + 0x0) -#define MV_WIN_USB_BASE(n, m) (0x10 * (n) + (m) * 0x1000 + 0x4) -#define MV_WIN_USB_MAX 4 - -#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) -#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) -#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) -#define MV_WIN_ETH_MAX 6 - -#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) -#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) -#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) -#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) -#define MV_WIN_IDMA_MAX 8 -#define MV_IDMA_CHAN_MAX 4 - -#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) -#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) -#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) -#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) -#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) -#define MV_WIN_XOR_MAX 8 -#define MV_XOR_CHAN_MAX 2 -#define MV_XOR_NON_REMAP 4 - -#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ - (n) + 1) + 0x1820) -#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ - (n) + 1) + 0x1824) -#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ - (n) + 1) + 0x182C) -#define MV_WIN_PCIE_MAX 6 - -#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) -#define MV_PCIE_BAR_MAX 3 - -#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) -#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) -#define MV_WIN_SATA_MAX 4 - -#define WIN_REG_IDX_RD(pre,reg,off,base) \ - static __inline uint32_t \ - pre ## _ ## reg ## _read(int i) \ - { \ - return (bus_space_read_4(obio_tag, base, off(i))); \ - } - -#define WIN_REG_IDX_RD2(pre,reg,off,base) \ - static __inline uint32_t \ - pre ## _ ## reg ## _read(int i, int j) \ - { \ - return (bus_space_read_4(obio_tag, base, off(i, j))); \ - } \ - -#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ - static __inline uint32_t \ - pre ## _ ## reg ## _read(uint32_t base, int i) \ - { \ - return (bus_space_read_4(obio_tag, base, off(i))); \ - } - -#define WIN_REG_IDX_WR(pre,reg,off,base) \ - static __inline void \ - pre ## _ ## reg ## _write(int i, uint32_t val) \ - { \ - bus_space_write_4(obio_tag, base, off(i), val); \ - } - -#define WIN_REG_IDX_WR2(pre,reg,off,base) \ - static __inline void \ - pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ - { \ - bus_space_write_4(obio_tag, base, off(i, j), val); \ - } - -#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ - static __inline void \ - pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ - { \ - bus_space_write_4(obio_tag, base, off(i), val); \ - } - -#define WIN_REG_RD(pre,reg,off,base) \ - static __inline uint32_t \ - pre ## _ ## reg ## _read(void) \ - { \ - return (bus_space_read_4(obio_tag, base, off)); \ - } - -#define WIN_REG_BASE_RD(pre,reg,off) \ - static __inline uint32_t \ - pre ## _ ## reg ## _read(uint32_t base) \ - { \ - return (bus_space_read_4(obio_tag, base, off)); \ - } - -#define WIN_REG_WR(pre,reg,off,base) \ - static __inline void \ - pre ## _ ## reg ## _write(uint32_t val) \ - { \ - bus_space_write_4(obio_tag, base, off, val); \ - } - -#define WIN_REG_BASE_WR(pre,reg,off) \ - static __inline void \ - pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ - { \ - bus_space_write_4(obio_tag, base, off, val); \ - } - #endif /* _MVREG_H_ */ diff --git a/sys/arm/mv/mvwin.h b/sys/arm/mv/mvwin.h new file mode 100644 index 0000000..1aaec28 --- /dev/null +++ b/sys/arm/mv/mvwin.h @@ -0,0 +1,279 @@ +/*- + * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. + * All rights reserved. + * + * Developed by Semihalf. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of MARVELL nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MVWIN_H_ +#define _MVWIN_H_ + +/* + * Physical addresses of integrated SoC peripherals + */ +#define MV_PHYS_BASE 0xF1000000 +#define MV_SIZE 0x100000 + +/* + * Decode windows addresses (physical) + */ +#define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) +#define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE +#define MV_PCIE_IO_SIZE (1024 * 1024) +#define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) +#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE +#define MV_PCI_IO_SIZE (1024 * 1024) + +#define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) +#define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE +#define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) +#define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) +#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE +#define MV_PCI_MEM_SIZE (64 * 1024 * 1024) + +/* XXX DEV_BOOT, CSx are board specific, should be defined per platform */ + +/* 512KB NOR FLASH */ +#define MV_DEV_BOOT_PHYS_BASE (MV_PCI_MEM_PHYS_BASE + MV_PCI_MEM_SIZE) +#define MV_DEV_BOOT_SIZE (512 * 1024) +/* CS0: 7-seg LED */ +#define MV_DEV_CS0_PHYS_BASE 0xFA000000 +#define MV_DEV_CS0_SIZE (1024 * 1024) /* XXX u-boot has 2MB */ +/* CS1: 32MB NOR FLASH */ +#define MV_DEV_CS1_PHYS_BASE (MV_DEV_CS0_PHYS_BASE + MV_DEV_CS0_SIZE) +#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) +/* CS2: 32MB NAND FLASH */ +#define MV_DEV_CS2_PHYS_BASE (MV_DEV_CS1_PHYS_BASE + MV_DEV_CS1_SIZE) +#define MV_DEV_CS2_SIZE 1024 /* XXX u-boot has 1MB */ + +#define MV_CESA_SRAM_PHYS_BASE 0xFD000000 +#define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */ +#define MV_CESA_SRAM_SIZE (1024 * 1024) + +/* XXX this is probably not robust against wraparounds... */ +#if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF) +#error Devices memory layout overlaps reset vectors range! +#endif + +/* + * Integrated SoC peripherals addresses + */ +#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ +#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) +#define MV_MPP_BASE (MV_BASE + 0x10000) +#define MV_GPIO_BASE (MV_BASE + 0x10100) +#define MV_GPIO_SIZE 0x20 +#define MV_RTC_BASE (MV_BASE + 0x10300) +#define MV_RTC_SIZE 0x08 +#define MV_TWSI_BASE (MV_BASE + 0x11000) +#define MV_TWSI_SIZE 0x20 +#define MV_UART0_BASE (MV_BASE + 0x12000) +#define MV_UART1_BASE (MV_BASE + 0x12100) +#define MV_UART_SIZE 0x20 +#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) +#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) +#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) +#define MV_IC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) +#define MV_IC_SIZE 0x3C +#define MV_TIMERS_BASE (MV_MBUS_BRIDGE_BASE + 0x300) +#define MV_TIMERS_SIZE 0x30 +#define MV_PCI_BASE (MV_BASE + 0x30000) +#define MV_PCI_SIZE 0x2000 +#if defined (SOC_MV_KIRKWOOD) +#define MV_CESA_BASE (MV_BASE + 0x30000) /* CESA,PCI don't coexist */ +#elif defined (SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) +#define MV_CESA_BASE (MV_BASE + 0x90000) +#endif +#define MV_CESA_SIZE 0x10000 +#define MV_PCIE_BASE (MV_BASE + 0x40000) +#define MV_PCIE_SIZE 0x2000 + +#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) +#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) +#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) +#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) +#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) +#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) +#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) +#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) + +#define MV_USB0_BASE (MV_BASE + 0x50000) +#define MV_USB1_BASE (MV_USB0_BASE + 0x1000) +#define MV_USB2_BASE (MV_USB0_BASE + 0x2000) +#define MV_USB_SIZE 0x1000 +#define MV_USB_AWR_BASE (MV_USB0_BASE + 0x320) +#define MV_IDMA_BASE (MV_BASE + 0x60000) +#define MV_IDMA_SIZE 0x1000 +#define MV_XOR_BASE (MV_BASE + 0x60000) +#define MV_XOR_SIZE 0x1000 +#define MV_ETH0_BASE (MV_BASE + 0x72000) +#define MV_ETH1_BASE (MV_BASE + 0x76000) +#define MV_ETH_SIZE 0x2000 +#if defined(SOC_MV_ORION) || defined(SOC_MV_KIRKWOOD) +#define MV_SATAHC_BASE (MV_BASE + 0x80000) +#define MV_SATAHC_SIZE 0x6000 +#elif defined(SOC_MV_DISCOVERY) +#define MV_SATAHC_BASE (MV_BASE + 0xA0000) +#define MV_SATAHC_SIZE 0x6000 +#endif + +#define MV_DEV_CS0_BASE MV_DEV_CS0_PHYS_BASE + +/* + * Decode windows definitions and macros + */ +#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) +#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) +#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) +#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) +#if defined(SOC_MV_DISCOVERY) +#define MV_WIN_CPU_MAX 14 +#else +#define MV_WIN_CPU_MAX 8 +#endif + +#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) +#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) +#define MV_WIN_DDR_MAX 4 + +#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04) +#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) +#define MV_WIN_CESA_MAX 4 + +#define MV_WIN_USB_CTRL(n, m) (0x10 * (n) + (m) * 0x1000 + 0x0) +#define MV_WIN_USB_BASE(n, m) (0x10 * (n) + (m) * 0x1000 + 0x4) +#define MV_WIN_USB_MAX 4 + +#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) +#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) +#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) +#define MV_WIN_ETH_MAX 6 + +#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) +#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) +#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) +#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) +#define MV_WIN_IDMA_MAX 8 +#define MV_IDMA_CHAN_MAX 4 + +#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) +#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) +#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) +#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) +#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) +#define MV_WIN_XOR_MAX 8 +#define MV_XOR_CHAN_MAX 2 +#define MV_XOR_NON_REMAP 4 + +#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ + (n) + 1) + 0x1820) +#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ + (n) + 1) + 0x1824) +#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ + (n) + 1) + 0x182C) +#define MV_WIN_PCIE_MAX 6 + +#define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) +#define MV_PCIE_BAR_MAX 3 + +#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) +#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) +#define MV_WIN_SATA_MAX 4 + +#define WIN_REG_IDX_RD(pre,reg,off,base) \ + static __inline uint32_t \ + pre ## _ ## reg ## _read(int i) \ + { \ + return (bus_space_read_4(obio_tag, base, off(i))); \ + } + +#define WIN_REG_IDX_RD2(pre,reg,off,base) \ + static __inline uint32_t \ + pre ## _ ## reg ## _read(int i, int j) \ + { \ + return (bus_space_read_4(obio_tag, base, off(i, j))); \ + } \ + +#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ + static __inline uint32_t \ + pre ## _ ## reg ## _read(uint32_t base, int i) \ + { \ + return (bus_space_read_4(obio_tag, base, off(i))); \ + } + +#define WIN_REG_IDX_WR(pre,reg,off,base) \ + static __inline void \ + pre ## _ ## reg ## _write(int i, uint32_t val) \ + { \ + bus_space_write_4(obio_tag, base, off(i), val); \ + } + +#define WIN_REG_IDX_WR2(pre,reg,off,base) \ + static __inline void \ + pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ + { \ + bus_space_write_4(obio_tag, base, off(i, j), val); \ + } + +#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ + static __inline void \ + pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ + { \ + bus_space_write_4(obio_tag, base, off(i), val); \ + } + +#define WIN_REG_RD(pre,reg,off,base) \ + static __inline uint32_t \ + pre ## _ ## reg ## _read(void) \ + { \ + return (bus_space_read_4(obio_tag, base, off)); \ + } + +#define WIN_REG_BASE_RD(pre,reg,off) \ + static __inline uint32_t \ + pre ## _ ## reg ## _read(uint32_t base) \ + { \ + return (bus_space_read_4(obio_tag, base, off)); \ + } + +#define WIN_REG_WR(pre,reg,off,base) \ + static __inline void \ + pre ## _ ## reg ## _write(uint32_t val) \ + { \ + bus_space_write_4(obio_tag, base, off, val); \ + } + +#define WIN_REG_BASE_WR(pre,reg,off) \ + static __inline void \ + pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ + { \ + bus_space_write_4(obio_tag, base, off, val); \ + } + +#endif /* _MVWIN_H_ */ diff --git a/sys/arm/mv/orion/db88f5xxx.c b/sys/arm/mv/orion/db88f5xxx.c index 5a5f283..8b40f54 100644 --- a/sys/arm/mv/orion/db88f5xxx.c +++ b/sys/arm/mv/orion/db88f5xxx.c @@ -41,12 +41,14 @@ __FBSDID("$FreeBSD$"); #include <vm/pmap.h> #include <machine/bus.h> +#include <machine/intr.h> #include <machine/pte.h> #include <machine/pmap.h> #include <machine/vmparam.h> #include <arm/mv/mvreg.h> #include <arm/mv/mvvar.h> +#include <arm/mv/mvwin.h> /* * Virtual address space layout: diff --git a/sys/arm/mv/orion/orion.c b/sys/arm/mv/orion/orion.c index e1852c1..7730a59 100644 --- a/sys/arm/mv/orion/orion.c +++ b/sys/arm/mv/orion/orion.c @@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$"); #include <arm/mv/mvreg.h> #include <arm/mv/mvvar.h> +#include <arm/mv/mvwin.h> extern const struct obio_pci_irq_map pci_irq_map[]; diff --git a/sys/dev/uart/uart_cpu_mv.c b/sys/dev/uart/uart_cpu_mv.c index 067f5dc..8c7188e 100644 --- a/sys/dev/uart/uart_cpu_mv.c +++ b/sys/dev/uart/uart_cpu_mv.c @@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$"); #include <arm/mv/mvreg.h> #include <arm/mv/mvvar.h> +#include <arm/mv/mvwin.h> bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; diff --git a/sys/dev/usb/controller/ehci_mbus.c b/sys/dev/usb/controller/ehci_mbus.c index c508269..eb9c101 100644 --- a/sys/dev/usb/controller/ehci_mbus.c +++ b/sys/dev/usb/controller/ehci_mbus.c @@ -67,6 +67,9 @@ static int err_intr(void *arg); static struct resource *irq_err; static void *ih_err; +/* EHCI HC regs start at this offset within USB range */ +#define MV_USB_HOST_OFST 0x0100 + #define USB_BRIDGE_INTR_CAUSE 0x210 #define USB_BRIDGE_INTR_MASK 0x214 @@ -152,7 +155,7 @@ ehci_mbus_attach(device_t self) } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); bsh = rman_get_bushandle(sc->sc_io_res); - sc->sc_io_size = MV_USB_SIZE - MV_USB_HOST_OFST; + sc->sc_io_size = rman_get_size(sc->sc_io_res) - MV_USB_HOST_OFST; /* * Marvell EHCI host controller registers start at certain offset within |
