diff options
| -rw-r--r-- | sys/conf/NOTES | 9 | ||||
| -rw-r--r-- | sys/conf/options | 1 | ||||
| -rw-r--r-- | sys/dev/ath/ath_hal/ar5212/ar5212_reset.c | 8 |
3 files changed, 18 insertions, 0 deletions
diff --git a/sys/conf/NOTES b/sys/conf/NOTES index f0cc9a0..cc1964d 100644 --- a/sys/conf/NOTES +++ b/sys/conf/NOTES @@ -2091,6 +2091,15 @@ device ath_hal # pci/cardbus chip support #device ath_rf5413 #device ath_ar5416 # AR5416 chips options AH_SUPPORT_AR5416 # enable AR5416 tx/rx descriptors +# All of the AR5212 parts have a problem when paired with the AR71xx +# CPUS. These parts have a bug that triggers a fatal bus error on the AR71xx +# only. Details of the exact nature of the bug are sketchy, but some can be +# found at https://forum.openwrt.org/viewtopic.php?pid=70060 on pages 4, 5 and +# 6. This option enables this workaround. There is a performance penalty +# for this work around, but without it things don't work at all. The DMA +# from the card usually bursts 128 bytes, but on the affected CPUs, only +# 4 are safe. +options AH_RXCFG_SDMAMW_4BYTES #device ath_ar9160 # AR9160 chips #device ath_ar9280 # AR9280 chips #device ath_ar9285 # AR9285 chips diff --git a/sys/conf/options b/sys/conf/options index fabc0bf..8f1dcaa 100644 --- a/sys/conf/options +++ b/sys/conf/options @@ -771,6 +771,7 @@ AH_PRIVATE_DIAG opt_ah.h AH_NEED_DESC_SWAP opt_ah.h AH_USE_INIPDGAIN opt_ah.h AH_MAXCHAN opt_ah.h +AH_RXCFG_SDMAMW_4BYTES opt_ah.h # options for the Broadcom BCM43xx driver (bwi) BWI_DEBUG opt_bwi.h diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c b/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c index fc937ea..8e6341a 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c @@ -283,6 +283,14 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0); regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange, regWrites); +#ifdef AH_RXCFG_SDMAMW_4BYTES + /* + * Nala doesn't work with 128 byte bursts on pb42(hydra) (ar71xx), + * use 4 instead. Enabling it on all platforms would hurt performance, + * so we only enable it on the ones that are affected by it. + */ + OS_REG_WRITE(ah, AR_RXCFG, 0); +#endif ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); |
