diff options
| -rw-r--r-- | sys/powerpc/mpc85xx/mpc85xx.c | 27 | ||||
| -rw-r--r-- | sys/powerpc/mpc85xx/ocpbus.h | 5 |
2 files changed, 25 insertions, 7 deletions
diff --git a/sys/powerpc/mpc85xx/mpc85xx.c b/sys/powerpc/mpc85xx/mpc85xx.c index d5831ee..144867e 100644 --- a/sys/powerpc/mpc85xx/mpc85xx.c +++ b/sys/powerpc/mpc85xx/mpc85xx.c @@ -33,10 +33,16 @@ __FBSDID("$FreeBSD$"); #include <sys/param.h> #include <sys/systm.h> +#include <vm/vm.h> +#include <vm/vm_param.h> + #include <machine/cpu.h> #include <machine/cpufunc.h> +#include <machine/pio.h> #include <machine/spr.h> +#include <powerpc/mpc85xx/ocpbus.h> + /* * MPC85xx system specific routines */ @@ -44,16 +50,23 @@ __FBSDID("$FreeBSD$"); void cpu_reset() { + uint32_t svr = mfsvr(); + + if (svr == SVR_MPC8572E || svr == SVR_MPC8572) + /* Systems with dedicated reset register */ + out32(OCP85XX_RSTCR, 2); + else { + /* Clear DBCR0, disables debug interrupts and events. */ + mtspr(SPR_DBCR0, 0); + __asm volatile("isync"); - /* Clear DBCR0, disables debug interrupts and events. */ - mtspr(SPR_DBCR0, 0); - __asm volatile("isync"); + /* Enable Debug Interrupts in MSR. */ + mtmsr(mfmsr() | PSL_DE); - /* Enable Debug Interrupts in MSR. */ - mtmsr(mfmsr() | PSL_DE); + /* Enable debug interrupts and issue reset. */ + mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); + } - /* Enable debug interrupts and issue reset. */ - mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); printf("Reset failed...\n"); while (1); } diff --git a/sys/powerpc/mpc85xx/ocpbus.h b/sys/powerpc/mpc85xx/ocpbus.h index 3e2c575..2c63804 100644 --- a/sys/powerpc/mpc85xx/ocpbus.h +++ b/sys/powerpc/mpc85xx/ocpbus.h @@ -52,6 +52,11 @@ #define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014) /* + * Status Registers. + */ +#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0) + +/* * OCP Bus Definitions */ #define OCP85XX_I2C0_OFF 0x03000 |
