diff options
| -rw-r--r-- | sys/dev/acpica/acpi_hpet.c | 42 | ||||
| -rw-r--r-- | sys/dev/acpica/acpi_hpet.h | 65 |
2 files changed, 84 insertions, 23 deletions
diff --git a/sys/dev/acpica/acpi_hpet.c b/sys/dev/acpica/acpi_hpet.c index 32c0530..77c6a7d 100644 --- a/sys/dev/acpica/acpi_hpet.c +++ b/sys/dev/acpica/acpi_hpet.c @@ -38,6 +38,7 @@ __FBSDID("$FreeBSD$"); #include <contrib/dev/acpica/acpi.h> #include <dev/acpica/acpivar.h> +#include <dev/acpica/acpi_hpet.h> ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); @@ -58,12 +59,6 @@ static void acpi_hpet_test(struct acpi_hpet_softc *sc); static char *hpet_ids[] = { "PNP0103", NULL }; -#define HPET_MEM_WIDTH 0x400 /* Expected memory region size */ -#define HPET_OFFSET_INFO 0 /* Location of info in region */ -#define HPET_OFFSET_PERIOD 4 /* Location of period (1/hz) */ -#define HPET_OFFSET_ENABLE 0x10 /* Location of enable word */ -#define HPET_OFFSET_VALUE 0xf0 /* Location of actual timer value */ - #define DEV_HPET(x) (acpi_get_magic(x) == (uintptr_t)&acpi_hpet_devclass) struct timecounter hpet_timecounter = { @@ -79,25 +74,25 @@ hpet_get_timecount(struct timecounter *tc) struct acpi_hpet_softc *sc; sc = tc->tc_priv; - return (bus_read_4(sc->mem_res, HPET_OFFSET_VALUE)); + return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); } static void hpet_enable(struct acpi_hpet_softc *sc) { uint32_t val; - - val = bus_read_4(sc->mem_res, HPET_OFFSET_ENABLE); - bus_write_4(sc->mem_res, HPET_OFFSET_ENABLE, val | 1); + + val = bus_read_4(sc->mem_res, HPET_CONFIG); + bus_write_4(sc->mem_res, HPET_CONFIG, val | HPET_CNF_ENABLE); } static void hpet_disable(struct acpi_hpet_softc *sc) { uint32_t val; - - val = bus_read_4(sc->mem_res, HPET_OFFSET_ENABLE); - bus_write_4(sc->mem_res, HPET_OFFSET_ENABLE, val & ~1); + + val = bus_read_4(sc->mem_res, HPET_CONFIG); + bus_write_4(sc->mem_res, HPET_CONFIG, val & ~HPET_CNF_ENABLE); } /* Discover the HPET via the ACPI table of the same name. */ @@ -187,7 +182,7 @@ acpi_hpet_attach(device_t dev) hpet_enable(sc); /* Read basic statistics about the timer. */ - val = bus_read_4(sc->mem_res, HPET_OFFSET_PERIOD); + val = bus_read_4(sc->mem_res, HPET_PERIOD); if (val == 0) { device_printf(dev, "invalid period\n"); hpet_disable(sc); @@ -197,12 +192,13 @@ acpi_hpet_attach(device_t dev) freq = (1000000000000000LL + val / 2) / val; if (bootverbose) { - val = bus_read_4(sc->mem_res, HPET_OFFSET_INFO); + val = bus_read_4(sc->mem_res, HPET_CAPABILITIES); device_printf(dev, "vend: 0x%x rev: 0x%x num: %d hz: %jd opts:%s%s\n", - val >> 16, val & 0xff, (val >> 18) & 0xf, freq, - ((val >> 15) & 1) ? " leg_route" : "", - ((val >> 13) & 1) ? " count_size" : ""); + val >> 16, val & HPET_CAP_REV_ID, + (val & HPET_CAP_NUM_TIM) >> 8, freq, + (val & HPET_CAP_LEG_RT) ? " legacy_route" : "", + (val & HPET_CAP_COUNT_SIZE) ? " 64-bit" : ""); } if (testenv("debug.acpi.hpet_test")) @@ -212,9 +208,9 @@ acpi_hpet_attach(device_t dev) * Don't attach if the timer never increments. Since the spec * requires it to be at least 10 MHz, it has to change in 1 us. */ - val = bus_read_4(sc->mem_res, HPET_OFFSET_VALUE); + val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); DELAY(1); - val2 = bus_read_4(sc->mem_res, HPET_OFFSET_VALUE); + val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); if (val == val2) { device_printf(dev, "HPET never increments, disabling\n"); hpet_disable(sc); @@ -278,11 +274,11 @@ acpi_hpet_test(struct acpi_hpet_softc *sc) binuptime(&b0); binuptime(&b0); binuptime(&b1); - u1 = bus_read_4(sc->mem_res, HPET_OFFSET_VALUE); + u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); for (i = 1; i < 1000; i++) - u2 = bus_read_4(sc->mem_res, HPET_OFFSET_VALUE); + u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); binuptime(&b2); - u2 = bus_read_4(sc->mem_res, HPET_OFFSET_VALUE); + u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); bintime_sub(&b2, &b1); bintime_sub(&b1, &b0); diff --git a/sys/dev/acpica/acpi_hpet.h b/sys/dev/acpica/acpi_hpet.h new file mode 100644 index 0000000..11372e1 --- /dev/null +++ b/sys/dev/acpica/acpi_hpet.h @@ -0,0 +1,65 @@ +/*- + * Copyright (c) 2005 Poul-Henning Kamp + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __ACPI_HPET_H__ +#define __ACPI_HPET_H__ + +#define HPET_MEM_WIDTH 0x400 /* Expected memory region size */ + +/* General registers */ +#define HPET_CAPABILITIES 0x0 /* General capabilities and ID */ +#define HPET_CAP_VENDOR_ID 0xffff0000 +#define HPET_CAP_LEG_RT 0x00008000 +#define HPET_CAP_COUNT_SIZE 0x00002000 /* 1 = 64-bit, 0 = 32-bit */ +#define HPET_CAP_NUM_TIM 0x00001f00 +#define HPET_CAP_REV_ID 0x000000ff +#define HPET_PERIOD 0x4 /* Period (1/hz) of timer */ +#define HPET_CONFIG 0x10 /* General configuration register */ +#define HPET_CNF_LEG_RT 0x00000002 +#define HPET_CNF_ENABLE 0x00000001 +#define HPET_ISR 0x20 /* General interrupt status register */ +#define HPET_MAIN_COUNTER 0xf0 /* Main counter register */ + +/* Timer registers */ +#define HPET_TIMER_CAP_CNF(x) ((x) * 0x20 + 0x100) +#define HPET_TCAP_INT_ROUTE 0xffffffff00000000 +#define HPET_TCAP_FSB_INT_DEL 0x00008000 +#define HPET_TCNF_FSB_EN 0x00004000 +#define HPET_TCNF_INT_ROUTE 0x00003e00 +#define HPET_TCNF_32MODE 0x00000100 +#define HPET_TCNF_VAL_SET 0x00000040 +#define HPET_TCAP_SIZE 0x00000020 /* 1 = 64-bit, 0 = 32-bit */ +#define HPET_TCAP_PER_INT 0x00000010 /* Supports periodic interrupts */ +#define HPET_TCNF_TYPE 0x00000008 /* 1 = periodic, 0 = one-shot */ +#define HPET_TCNF_INT_ENB 0x00000004 +#define HPET_TCNT_INT_TYPE 0x00000002 /* 1 = level triggered, 0 = edge */ +#define HPET_TIMER_COMPARATOR(x) ((x) * 0x20 + 0x108) +#define HPET_TIMER_FSB_VAL(x) ((x) * 0x20 + 0x110) +#define HPET_TIMER_FSB_ADDR(x) ((x) * 0x20 + 0x114) + +#endif /* !__ACPI_HPET_H__ */ |
