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-rw-r--r--release/sysinstall/devices.c1
-rw-r--r--release/texts/i386/HARDWARE.TXT5
-rw-r--r--release/texts/i386/RELNOTES.TXT8
-rw-r--r--share/man/man4/dm.4150
-rw-r--r--share/man/man4/man4.i386/Makefile5
-rw-r--r--share/man/man4/man4.i386/dm.4150
-rw-r--r--sys/alpha/conf/GENERIC1
-rw-r--r--sys/alpha/conf/NOTES1
-rw-r--r--sys/amd64/conf/GENERIC1
-rw-r--r--sys/conf/NOTES5
-rw-r--r--sys/conf/files1
-rw-r--r--sys/i386/conf/GENERIC1
-rw-r--r--sys/i386/conf/LINT5
-rw-r--r--sys/i386/conf/NOTES5
-rw-r--r--sys/i386/i386/userconfig.c1
-rw-r--r--sys/modules/Makefile2
-rw-r--r--sys/modules/dm/Makefile33
-rw-r--r--sys/pci/if_dm.c1714
-rw-r--r--sys/pci/if_dmreg.h419
-rw-r--r--usr.sbin/sade/devices.c1
-rw-r--r--usr.sbin/sysinstall/devices.c1
21 files changed, 2507 insertions, 3 deletions
diff --git a/release/sysinstall/devices.c b/release/sysinstall/devices.c
index 878e4e8..7269b69 100644
--- a/release/sysinstall/devices.c
+++ b/release/sysinstall/devices.c
@@ -89,6 +89,7 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "cc3i", "SDL HSSI sync serial PCI card" },
{ DEVICE_TYPE_NETWORK, "en", "Efficient Networks ATM PCI card" },
{ DEVICE_TYPE_NETWORK, "de", "DEC DE435 PCI NIC or other DC21040-AA based card" },
+ { DEVICE_TYPE_NETWORK, "dm", "Davicom DM9100/DM9102 PCI fast ethernet card" },
{ DEVICE_TYPE_NETWORK, "fxp", "Intel EtherExpress Pro/100B PCI Fast Ethernet card" },
{ DEVICE_TYPE_NETWORK, "ed", "Novell NE1000/2000; 3C503; NE2000-compatible PCMCIA" },
{ DEVICE_TYPE_NETWORK, "ep", "3Com 3C509 ethernet card/3C589 PCMCIA" },
diff --git a/release/texts/i386/HARDWARE.TXT b/release/texts/i386/HARDWARE.TXT
index 5911f7a..5d0919f 100644
--- a/release/texts/i386/HARDWARE.TXT
+++ b/release/texts/i386/HARDWARE.TXT
@@ -90,6 +90,7 @@ al0 dyn dyn n/a dyn ADMtek AL981 PCI based cards
ax0 dyn dyn n/a dyn ASIX AX88140A PCI based cards
de0 n/a n/a n/a n/a DEC DC21x40 PCI based cards
(including 21140 100bT cards)
+dm0 n/a n/a n/a n/a Davicom DM9100/DM9102 PCI based cards
ed0 280 10 dyn d8000 WD & SMC 80xx; Novell NE1000 &
NE2000; 3Com 3C503; HP PC Lan+
eg0 310 5 dyn dyn 3Com 3C505
@@ -514,6 +515,10 @@ DEC EtherWORKS II NICs (DE200, DE201, DE202, and DE422)
DEC DC21040, DC21041, or DC21140 based NICs (SMC Etherpower 8432T, DE245, etc)
DEC FDDI (DEFPA/DEFEA) NICs
+Davicom DM9100 and DM9102 PCI fast ethernet NICs, including the
+following:
+ Jaton Corporation XPressNet
+
Efficient ENI-155p ATM PCI
FORE PCA-200E ATM PCI
diff --git a/release/texts/i386/RELNOTES.TXT b/release/texts/i386/RELNOTES.TXT
index 1f5b82b..1c32f85 100644
--- a/release/texts/i386/RELNOTES.TXT
+++ b/release/texts/i386/RELNOTES.TXT
@@ -98,6 +98,10 @@ syslog(3) to log all messages to /var/log/security.
Driver support has been added for PCI fast ethernet adapters based on
the Silicon Integrated Systems SiS 900 and SiS 7016 ethernet controllers.
+Driver support has been added for PCI fast ethernet adapters based on
+the Davicom DM9100 and DM9102 ethernet controllers, including the Jaton
+Corporation XpressNet.
+
1.2. SECURITY FIXES
-------------------
@@ -334,6 +338,10 @@ DEC EtherWORKS II NICs (DE200, DE201, DE202, and DE422)
DEC DC21040, DC21041, or DC21140 based NICs (SMC Etherpower 8432T, DE245, etc)
DEC FDDI (DEFPA/DEFEA) NICs
+Davicom DM9100 and DM9102 PCI fast ethernet NICs, including the
+following:
+ Jaton Corporation XpressNet
+
Fujitsu MB86960A/MB86965A
HP PC Lan+ cards (model numbers: 27247B and 27252A).
diff --git a/share/man/man4/dm.4 b/share/man/man4/dm.4
new file mode 100644
index 0000000..b095c80
--- /dev/null
+++ b/share/man/man4/dm.4
@@ -0,0 +1,150 @@
+.\" Copyright (c) 1997, 1998, 1999
+.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\" 3. All advertising materials mentioning features or use of this software
+.\" must display the following acknowledgement:
+.\" This product includes software developed by Bill Paul.
+.\" 4. Neither the name of the author nor the names of any co-contributors
+.\" may be used to endorse or promote products derived from this software
+.\" without specific prior written permission.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+.\" THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd September 4, 1999
+.Dt DM 4 i386
+.Os FreeBSD
+.Sh NAME
+.Nm dm
+.Nd
+Davicom DM9100/DM9102 fast ethernet device driver
+.Sh SYNOPSIS
+.Cd "controller miibus0"
+.Cd "device dm0"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for PCI ethernet adapters and embedded
+controllers based on the Davicom DM9100 and DM9102 PCI
+fast ethernet controller chips including the Jaton Corporation
+XPressNet.
+.Pp
+The DM9100 and DM9102 are designed to be DEC 21x4x workalikes. The
+register layout, DMA descriptor scheme and receive filter programming
+are identical to the DEC part. The DM9102
+is a 100Mbps ethernet MAC and MII-compliant transceiver
+in a single package. The DM9100 is similar to the DM9102 except
+that it has no internal PHY, requiring instead an external transceiver
+to be attached to its MII interface.
+.Pp
+The
+.Nm
+driver supports the following media types:
+.Pp
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It autoselect
+Enable autoselection of the media type and options.
+The user can manually override
+the autoselected mode by adding media options to the
+.Pa /etc/rc.conf
+fine.
+.It 10baseT/UTP
+Set 10Mbps operation. The
+.Ar mediaopt
+option can also be used to select either
+.Ar full-duplex
+or
+.Ar half-duplex modes.
+.It 100baseTX
+Set 100Mbps (fast ethernet) operation. The
+.Ar mediaopt
+option can also be used to select either
+.Ar full-duplex
+or
+.Ar half-duplex
+modes.
+.El
+.Pp
+The
+.Nm
+driver supports the following media options:
+.Pp
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It full-duplex
+Force full duplex operation
+.It half-duplex
+Force half duplex operation.
+.El
+.Pp
+For more information on configuring this device, see
+.Xr ifconfig 8 .
+.Sh DIAGNOSTICS
+.Bl -diag
+.It "dm%d: couldn't map ports/memory"
+A fatal initialization error has occurred.
+.It "dm%d: couldn't map interrupt"
+A fatal initialization error has occurred.
+.It "dm%d: watchdog timeout"
+The device has stopped responding to the network, or there is a problem with
+the network connection (cable).
+.It "dm%d: no memory for rx list"
+The driver failed to allocate an mbuf for the receiver ring.
+.It "dm%d: no memory for tx list"
+The driver failed to allocate an mbuf for the transmitter ring when
+allocating a pad buffer or collapsing an mbuf chain into a cludmr.
+.It "dm%d: chip is in D3 power state -- setting to D0"
+This message applies only to adapters which support power
+management. Some operating sydmms place the controller in low power
+mode when shutting down, and some PCI BIOSes fail to bring the chip
+out of this state before configuring it. The controller loses all of
+its PCI configuration in the D3 state, so if the BIOS does not set
+it back to full power mode in time, it won't be able to configure it
+correctly. The driver tries to detect this condition and bring
+the adapter back to the D0 (full power) state, but this may not be
+enough to return the driver to a fully operational condition. If
+you see this message at boot time and the driver fails to attach
+the device as a network interface, you will have to perform second
+warm boot to have the device properly configured.
+.Pp
+Note that this condition only occurs when warm booting from another
+operating sydmm. If you power down your sydmm prior to booting
+.Fx ,
+the card should be configured correctly.
+.El
+.Sh SEE ALSO
+.Xr arp 4 ,
+.Xr netintro 4 ,
+.Xr ifconfig 8
+.Rs
+.%T Davicom DM9102 datasheet
+.%O http://www.davicom8.com
+.Re
+.Sh HISTORY
+The
+.Nm
+device driver first appeared in
+.Fx 3.0 .
+.Sh AUTHORS
+The
+.Nm
+driver was written by
+.An Bill Paul Aq wpaul@ee.columbia.edu .
diff --git a/share/man/man4/man4.i386/Makefile b/share/man/man4/man4.i386/Makefile
index e05baf4..a2fcbb7 100644
--- a/share/man/man4/man4.i386/Makefile
+++ b/share/man/man4/man4.i386/Makefile
@@ -2,8 +2,8 @@
MAN4= adv.4 adw.4 aha.4 ahb.4 ahc.4 aic.4 al.4 alpm.4 apm.4 ar.4 asc.4 \
atkbd.4 atkbdc.4 ax.4 bktr.4 bt.4 cs.4 cx.4 cy.4 de.4 \
- dgb.4 dpt.4 ed.4 el.4 en.4 ep.4 ex.4 fdc.4 fe.4 fxp.4 gsc.4 ie.4 \
- io.4 joy.4 keyboard.4 labpc.4 le.4 lnc.4 matcd.4 mcd.4 \
+ dgb.4 dm.4 dpt.4 ed.4 el.4 en.4 ep.4 ex.4 fdc.4 fe.4 fxp.4 gsc.4 \
+ ie.4 io.4 joy.4 keyboard.4 labpc.4 le.4 lnc.4 matcd.4 mcd.4 \
mem.4 meteor.4 mouse.4 mse.4 mtio.4 mx.4 ncr.4 npx.4 \
ohci.4 pcf.4 pcm.4 pcvt.4 perfmon.4 pn.4 pnp.4 ppc.4 psm.4 \
rdp.4 rl.4 sb.4 scd.4 screen.4 sf.4 si.4 sio.4 sis.4 sk.4 \
@@ -32,6 +32,7 @@ MLINKS+= cx.4 ../cx.4
MLINKS+= cy.4 ../cy.4
MLINKS+= de.4 ../de.4
MLINKS+= dgb.4 ../dgb.4
+MLINKS+= dm.4 ../dm.4
MLINKS+= dpt.4 ../dpt.4
MLINKS+= ed.4 ../ed.4
MLINKS+= el.4 ../el.4
diff --git a/share/man/man4/man4.i386/dm.4 b/share/man/man4/man4.i386/dm.4
new file mode 100644
index 0000000..b095c80
--- /dev/null
+++ b/share/man/man4/man4.i386/dm.4
@@ -0,0 +1,150 @@
+.\" Copyright (c) 1997, 1998, 1999
+.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\" 3. All advertising materials mentioning features or use of this software
+.\" must display the following acknowledgement:
+.\" This product includes software developed by Bill Paul.
+.\" 4. Neither the name of the author nor the names of any co-contributors
+.\" may be used to endorse or promote products derived from this software
+.\" without specific prior written permission.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+.\" THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd September 4, 1999
+.Dt DM 4 i386
+.Os FreeBSD
+.Sh NAME
+.Nm dm
+.Nd
+Davicom DM9100/DM9102 fast ethernet device driver
+.Sh SYNOPSIS
+.Cd "controller miibus0"
+.Cd "device dm0"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for PCI ethernet adapters and embedded
+controllers based on the Davicom DM9100 and DM9102 PCI
+fast ethernet controller chips including the Jaton Corporation
+XPressNet.
+.Pp
+The DM9100 and DM9102 are designed to be DEC 21x4x workalikes. The
+register layout, DMA descriptor scheme and receive filter programming
+are identical to the DEC part. The DM9102
+is a 100Mbps ethernet MAC and MII-compliant transceiver
+in a single package. The DM9100 is similar to the DM9102 except
+that it has no internal PHY, requiring instead an external transceiver
+to be attached to its MII interface.
+.Pp
+The
+.Nm
+driver supports the following media types:
+.Pp
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It autoselect
+Enable autoselection of the media type and options.
+The user can manually override
+the autoselected mode by adding media options to the
+.Pa /etc/rc.conf
+fine.
+.It 10baseT/UTP
+Set 10Mbps operation. The
+.Ar mediaopt
+option can also be used to select either
+.Ar full-duplex
+or
+.Ar half-duplex modes.
+.It 100baseTX
+Set 100Mbps (fast ethernet) operation. The
+.Ar mediaopt
+option can also be used to select either
+.Ar full-duplex
+or
+.Ar half-duplex
+modes.
+.El
+.Pp
+The
+.Nm
+driver supports the following media options:
+.Pp
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It full-duplex
+Force full duplex operation
+.It half-duplex
+Force half duplex operation.
+.El
+.Pp
+For more information on configuring this device, see
+.Xr ifconfig 8 .
+.Sh DIAGNOSTICS
+.Bl -diag
+.It "dm%d: couldn't map ports/memory"
+A fatal initialization error has occurred.
+.It "dm%d: couldn't map interrupt"
+A fatal initialization error has occurred.
+.It "dm%d: watchdog timeout"
+The device has stopped responding to the network, or there is a problem with
+the network connection (cable).
+.It "dm%d: no memory for rx list"
+The driver failed to allocate an mbuf for the receiver ring.
+.It "dm%d: no memory for tx list"
+The driver failed to allocate an mbuf for the transmitter ring when
+allocating a pad buffer or collapsing an mbuf chain into a cludmr.
+.It "dm%d: chip is in D3 power state -- setting to D0"
+This message applies only to adapters which support power
+management. Some operating sydmms place the controller in low power
+mode when shutting down, and some PCI BIOSes fail to bring the chip
+out of this state before configuring it. The controller loses all of
+its PCI configuration in the D3 state, so if the BIOS does not set
+it back to full power mode in time, it won't be able to configure it
+correctly. The driver tries to detect this condition and bring
+the adapter back to the D0 (full power) state, but this may not be
+enough to return the driver to a fully operational condition. If
+you see this message at boot time and the driver fails to attach
+the device as a network interface, you will have to perform second
+warm boot to have the device properly configured.
+.Pp
+Note that this condition only occurs when warm booting from another
+operating sydmm. If you power down your sydmm prior to booting
+.Fx ,
+the card should be configured correctly.
+.El
+.Sh SEE ALSO
+.Xr arp 4 ,
+.Xr netintro 4 ,
+.Xr ifconfig 8
+.Rs
+.%T Davicom DM9102 datasheet
+.%O http://www.davicom8.com
+.Re
+.Sh HISTORY
+The
+.Nm
+device driver first appeared in
+.Fx 3.0 .
+.Sh AUTHORS
+The
+.Nm
+driver was written by
+.An Bill Paul Aq wpaul@ee.columbia.edu .
diff --git a/sys/alpha/conf/GENERIC b/sys/alpha/conf/GENERIC
index daa3307..8275c4c 100644
--- a/sys/alpha/conf/GENERIC
+++ b/sys/alpha/conf/GENERIC
@@ -115,6 +115,7 @@ controller miibus0
device al0
device ax0
device de0
+device dm0
device fxp0
device le0
device mx0
diff --git a/sys/alpha/conf/NOTES b/sys/alpha/conf/NOTES
index daa3307..8275c4c 100644
--- a/sys/alpha/conf/NOTES
+++ b/sys/alpha/conf/NOTES
@@ -115,6 +115,7 @@ controller miibus0
device al0
device ax0
device de0
+device dm0
device fxp0
device le0
device mx0
diff --git a/sys/amd64/conf/GENERIC b/sys/amd64/conf/GENERIC
index c07286a..c0e66db 100644
--- a/sys/amd64/conf/GENERIC
+++ b/sys/amd64/conf/GENERIC
@@ -162,6 +162,7 @@ controller miibus0
device al0 # ADMtek AL981 (``Comet'')
device ax0 # ASIX AX88140A
device de0 # DEC/Intel DC21x4x (``Tulip'')
+device dm0 # Davicom DM9100/DM9102
device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
device pn0 # Lite-On 82c168/82c169 (``PNIC'')
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index 05298f4..2294be6 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -1542,6 +1542,10 @@ controller miibus0
# The `de' device provides support for the Digital Equipment DC21040
# self-contained Ethernet adapter.
#
+# The `dm' device provides support for PCI fast ethernet adapters
+# based on the the Davicom DM9100 and DM9102 controller chips, including
+# the Jaton Corporation XPressNet.
+#
# The `fxp' device provides support for the Intel EtherExpress Pro/100B
# PCI Fast Ethernet adapters.
#
@@ -1721,6 +1725,7 @@ options SCSI_ISP_FCDUPLEX=0x4 # isp2 is a Fibre Channel card
device al0
device ax0
device de0
+device dm0
device fxp0
device mx0
device pn0
diff --git a/sys/conf/files b/sys/conf/files
index 961d932..713c267 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -626,6 +626,7 @@ pci/ida_pci.c optional ida pci
pci/if_al.c optional al
pci/if_ax.c optional ax
pci/if_de.c optional de
+pci/if_dm.c optional dm
pci/if_ed_p.c optional ed pci
pci/if_en_pci.c optional en pci
pci/if_fxp.c optional fxp
diff --git a/sys/i386/conf/GENERIC b/sys/i386/conf/GENERIC
index c07286a..c0e66db 100644
--- a/sys/i386/conf/GENERIC
+++ b/sys/i386/conf/GENERIC
@@ -162,6 +162,7 @@ controller miibus0
device al0 # ADMtek AL981 (``Comet'')
device ax0 # ASIX AX88140A
device de0 # DEC/Intel DC21x4x (``Tulip'')
+device dm0 # Davicom DM9100/DM9102
device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
device pn0 # Lite-On 82c168/82c169 (``PNIC'')
diff --git a/sys/i386/conf/LINT b/sys/i386/conf/LINT
index 05298f4..2294be6 100644
--- a/sys/i386/conf/LINT
+++ b/sys/i386/conf/LINT
@@ -1542,6 +1542,10 @@ controller miibus0
# The `de' device provides support for the Digital Equipment DC21040
# self-contained Ethernet adapter.
#
+# The `dm' device provides support for PCI fast ethernet adapters
+# based on the the Davicom DM9100 and DM9102 controller chips, including
+# the Jaton Corporation XPressNet.
+#
# The `fxp' device provides support for the Intel EtherExpress Pro/100B
# PCI Fast Ethernet adapters.
#
@@ -1721,6 +1725,7 @@ options SCSI_ISP_FCDUPLEX=0x4 # isp2 is a Fibre Channel card
device al0
device ax0
device de0
+device dm0
device fxp0
device mx0
device pn0
diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES
index 05298f4..2294be6 100644
--- a/sys/i386/conf/NOTES
+++ b/sys/i386/conf/NOTES
@@ -1542,6 +1542,10 @@ controller miibus0
# The `de' device provides support for the Digital Equipment DC21040
# self-contained Ethernet adapter.
#
+# The `dm' device provides support for PCI fast ethernet adapters
+# based on the the Davicom DM9100 and DM9102 controller chips, including
+# the Jaton Corporation XPressNet.
+#
# The `fxp' device provides support for the Intel EtherExpress Pro/100B
# PCI Fast Ethernet adapters.
#
@@ -1721,6 +1725,7 @@ options SCSI_ISP_FCDUPLEX=0x4 # isp2 is a Fibre Channel card
device al0
device ax0
device de0
+device dm0
device fxp0
device mx0
device pn0
diff --git a/sys/i386/i386/userconfig.c b/sys/i386/i386/userconfig.c
index 14bbdd5..11bfbc5 100644
--- a/sys/i386/i386/userconfig.c
+++ b/sys/i386/i386/userconfig.c
@@ -404,6 +404,7 @@ static DEV_INFO device_info[] = {
{"al", "ADMtek AL981 ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"ax", "ASIX AX88140A ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"de", "DEC DC21040 Ethernet adapter", FLG_FIXED, CLS_NETWORK},
+{"dm", "Davicom DM910x Ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"fpa", "DEC DEFPA PCI FDDI adapter", FLG_FIXED, CLS_NETWORK},
{"rl", "RealTek 8129/8139 ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"mx", "Macronix PMAC ethernet adapter", FLG_FIXED, CLS_NETWORK},
diff --git a/sys/modules/Makefile b/sys/modules/Makefile
index 28cdb34..68f208d 100644
--- a/sys/modules/Makefile
+++ b/sys/modules/Makefile
@@ -2,7 +2,7 @@
# XXX present but broken: atapi ip_mroute_mod joy pcic
-SUBDIR= ax ccd cd9660 coda fdesc fxp if_disc if_ppp if_sl if_tun ipfw \
+SUBDIR= ax ccd cd9660 coda dm fdesc fxp if_disc if_ppp if_sl if_tun ipfw \
kernfs mfs mii msdos mx nfs ntfs nullfs pn portal procfs sf \
sis sk ste ti tl umapfs union vn vr wb xl
diff --git a/sys/modules/dm/Makefile b/sys/modules/dm/Makefile
new file mode 100644
index 0000000..bd96130
--- /dev/null
+++ b/sys/modules/dm/Makefile
@@ -0,0 +1,33 @@
+# $FreeBSD$
+
+S = ${.CURDIR}/../..
+.PATH: $S/pci
+KMOD = dm
+SRCS = if_dm.c dm.h bpf.h opt_bdg.h device_if.h bus_if.h pci_if.h
+SRCS += miibus_if.h
+CLEANFILES += dm.h bpf.h opt_bdg.h device_if.h bus_if.h pci_if.h
+CLEANFILES += miibus_if.h
+CFLAGS += ${DEBUG_FLAGS}
+
+dm.h:
+ echo "#define NDM 1" > dm.h
+
+bpf.h:
+ echo "#define NBPF 1" > bpf.h
+
+opt_bdg.h:
+ touch opt_bdg.h
+
+device_if.h: $S/kern/makedevops.pl $S/kern/device_if.m
+ perl $S/kern/makedevops.pl -h $S/kern/device_if.m
+
+bus_if.h: $S/kern/makedevops.pl $S/kern/bus_if.m
+ perl $S/kern/makedevops.pl -h $S/kern/bus_if.m
+
+pci_if.h: $S/kern/makedevops.pl $S/pci/pci_if.m
+ perl $S/kern/makedevops.pl -h $S/pci/pci_if.m
+
+miibus_if.h: $S/kern/makedevops.pl $S/dev/mii/miibus_if.m
+ perl $S/kern/makedevops.pl -h $S/dev/mii/miibus_if.m
+
+.include <bsd.kmod.mk>
diff --git a/sys/pci/if_dm.c b/sys/pci/if_dm.c
new file mode 100644
index 0000000..d033d1f
--- /dev/null
+++ b/sys/pci/if_dm.c
@@ -0,0 +1,1714 @@
+/*
+ * Copyright (c) 1997, 1998, 1999
+ * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $Id: if_dm.c,v 1.3 1999/09/06 04:35:06 wpaul Exp $
+ */
+
+/*
+ * Davicom DM9102 fast ethernet PCI NIC driver.
+ *
+ * Written by Bill Paul <wpaul@ee.columbia.edu>
+ * Electrical Engineering Department
+ * Columbia University, New York City
+ */
+
+/*
+ * The Davicom DM9102 is yet another DEC 21x4x clone. This one is actually
+ * a pretty faithful copy. Same RX filter programming, same SROM layout,
+ * same everything. Datasheets available from www.davicom8.com. Only
+ * MII-based transceivers are supported.
+ *
+ * The DM9102's DMA engine seems pretty weak. Multi-fragment transmits
+ * don't seem to work well, and on slow machines you get lots of RX
+ * underruns.
+ */
+
+#include "bpf.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#if NBPF > 0
+#include <net/bpf.h>
+#endif
+
+#include <vm/vm.h> /* for vtophys */
+#include <vm/pmap.h> /* for vtophys */
+#include <machine/clock.h> /* for DELAY */
+#include <machine/bus_pio.h>
+#include <machine/bus_memio.h>
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+
+#define DM_USEIOSPACE
+
+#include <pci/if_dmreg.h>
+
+#include "miibus_if.h"
+
+#ifndef lint
+static const char rcsid[] =
+ "$FreeBSD$";
+#endif
+
+/*
+ * Various supported device vendors/types and their names.
+ */
+static struct dm_type dm_devs[] = {
+ { DM_VENDORID, DM_DEVICEID_DM9100, "Davicom DM9100 10/100BaseTX" },
+ { DM_VENDORID, DM_DEVICEID_DM9102, "Davicom DM9102 10/100BaseTX" },
+ { 0, 0, NULL }
+};
+
+static int dm_probe __P((device_t));
+static int dm_attach __P((device_t));
+static int dm_detach __P((device_t));
+
+static int dm_newbuf __P((struct dm_softc *,
+ struct dm_desc *,
+ struct mbuf *));
+static int dm_encap __P((struct dm_softc *,
+ struct mbuf **, u_int32_t *));
+
+static void dm_rxeof __P((struct dm_softc *));
+static void dm_rxeoc __P((struct dm_softc *));
+static void dm_txeof __P((struct dm_softc *));
+static void dm_intr __P((void *));
+static void dm_tick __P((void *));
+static void dm_start __P((struct ifnet *));
+static int dm_ioctl __P((struct ifnet *, u_long, caddr_t));
+static void dm_init __P((void *));
+static void dm_stop __P((struct dm_softc *));
+static void dm_watchdog __P((struct ifnet *));
+static void dm_shutdown __P((device_t));
+static int dm_ifmedia_upd __P((struct ifnet *));
+static void dm_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
+
+static void dm_delay __P((struct dm_softc *));
+static void dm_eeprom_idle __P((struct dm_softc *));
+static void dm_eeprom_putbyte __P((struct dm_softc *, int));
+static void dm_eeprom_getword __P((struct dm_softc *, int, u_int16_t *));
+static void dm_read_eeprom __P((struct dm_softc *, caddr_t, int,
+ int, int));
+
+static void dm_mii_writebit __P((struct dm_softc *, int));
+static int dm_mii_readbit __P((struct dm_softc *));
+static void dm_mii_sync __P((struct dm_softc *));
+static void dm_mii_send __P((struct dm_softc *, u_int32_t, int));
+static int dm_mii_readreg __P((struct dm_softc *, struct dm_mii_frame *));
+static int dm_mii_writereg __P((struct dm_softc *, struct dm_mii_frame *));
+static int dm_miibus_readreg __P((device_t, int, int));
+static int dm_miibus_writereg __P((device_t, int, int, int));
+static void dm_miibus_statchg __P((device_t));
+
+static u_int32_t dm_calchash __P((caddr_t));
+static void dm_setfilt __P((struct dm_softc *));
+static void dm_reset __P((struct dm_softc *));
+static int dm_list_rx_init __P((struct dm_softc *));
+static int dm_list_tx_init __P((struct dm_softc *));
+
+#ifdef DM_USEIOSPACE
+#define DM_RES SYS_RES_IOPORT
+#define DM_RID DM_PCI_LOIO
+#else
+#define DM_RES SYS_RES_IOPORT
+#define DM_RID DM_PCI_LOIO
+#endif
+
+static device_method_t dm_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, dm_probe),
+ DEVMETHOD(device_attach, dm_attach),
+ DEVMETHOD(device_detach, dm_detach),
+ DEVMETHOD(device_shutdown, dm_shutdown),
+
+ /* bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_driver_added, bus_generic_driver_added),
+
+ /* MII interface */
+ DEVMETHOD(miibus_readreg, dm_miibus_readreg),
+ DEVMETHOD(miibus_writereg, dm_miibus_writereg),
+ DEVMETHOD(miibus_statchg, dm_miibus_statchg),
+
+ { 0, 0 }
+};
+
+static driver_t dm_driver = {
+ "dm",
+ dm_methods,
+ sizeof(struct dm_softc)
+};
+
+static devclass_t dm_devclass;
+
+DRIVER_MODULE(dm, pci, dm_driver, dm_devclass, 0, 0);
+DRIVER_MODULE(miibus, dm, miibus_driver, miibus_devclass, 0, 0);
+
+#define DM_SETBIT(sc, reg, x) \
+ CSR_WRITE_4(sc, reg, \
+ CSR_READ_4(sc, reg) | x)
+
+#define DM_CLRBIT(sc, reg, x) \
+ CSR_WRITE_4(sc, reg, \
+ CSR_READ_4(sc, reg) & ~x)
+
+#define SIO_SET(x) \
+ CSR_WRITE_4(sc, DM_SIO, \
+ CSR_READ_4(sc, DM_SIO) | x)
+
+#define SIO_CLR(x) \
+ CSR_WRITE_4(sc, DM_SIO, \
+ CSR_READ_4(sc, DM_SIO) & ~x)
+
+static void dm_delay(sc)
+ struct dm_softc *sc;
+{
+ int idx;
+
+ for (idx = (300 / 33) + 1; idx > 0; idx--)
+ CSR_READ_4(sc, DM_BUSCTL);
+}
+
+static void dm_eeprom_idle(sc)
+ struct dm_softc *sc;
+{
+ register int i;
+
+ CSR_WRITE_4(sc, DM_SIO, DM_SIO_EESEL);
+ dm_delay(sc);
+ DM_SETBIT(sc, DM_SIO, DM_SIO_ROMCTL_READ);
+ dm_delay(sc);
+ DM_SETBIT(sc, DM_SIO, DM_SIO_EE_CS);
+ dm_delay(sc);
+ DM_SETBIT(sc, DM_SIO, DM_SIO_EE_CLK);
+ dm_delay(sc);
+
+ for (i = 0; i < 25; i++) {
+ DM_CLRBIT(sc, DM_SIO, DM_SIO_EE_CLK);
+ dm_delay(sc);
+ DM_SETBIT(sc, DM_SIO, DM_SIO_EE_CLK);
+ dm_delay(sc);
+ }
+
+ DM_CLRBIT(sc, DM_SIO, DM_SIO_EE_CLK);
+ dm_delay(sc);
+ DM_CLRBIT(sc, DM_SIO, DM_SIO_EE_CS);
+ dm_delay(sc);
+ CSR_WRITE_4(sc, DM_SIO, 0x00000000);
+
+ return;
+}
+
+/*
+ * Send a read command and address to the EEPROM, check for ACK.
+ */
+static void dm_eeprom_putbyte(sc, addr)
+ struct dm_softc *sc;
+ int addr;
+{
+ register int d, i;
+
+ d = addr | DM_EECMD_READ;
+
+ /*
+ * Feed in each bit and stobe the clock.
+ */
+ for (i = 0x400; i; i >>= 1) {
+ if (d & i) {
+ SIO_SET(DM_SIO_EE_DATAIN);
+ } else {
+ SIO_CLR(DM_SIO_EE_DATAIN);
+ }
+ dm_delay(sc);
+ SIO_SET(DM_SIO_EE_CLK);
+ dm_delay(sc);
+ SIO_CLR(DM_SIO_EE_CLK);
+ dm_delay(sc);
+ }
+
+ return;
+}
+
+/*
+ * Read a word of data stored in the EEPROM at address 'addr.'
+ */
+static void dm_eeprom_getword(sc, addr, dest)
+ struct dm_softc *sc;
+ int addr;
+ u_int16_t *dest;
+{
+ register int i;
+ u_int16_t word = 0;
+
+ /* Force EEPROM to idle state. */
+ dm_eeprom_idle(sc);
+
+ /* Enter EEPROM access mode. */
+ CSR_WRITE_4(sc, DM_SIO, DM_SIO_EESEL);
+ dm_delay(sc);
+ DM_SETBIT(sc, DM_SIO, DM_SIO_ROMCTL_READ);
+ dm_delay(sc);
+ DM_SETBIT(sc, DM_SIO, DM_SIO_EE_CS);
+ dm_delay(sc);
+ DM_SETBIT(sc, DM_SIO, DM_SIO_EE_CLK);
+ dm_delay(sc);
+
+ /*
+ * Send address of word we want to read.
+ */
+ dm_eeprom_putbyte(sc, addr);
+
+ /*
+ * Start reading bits from EEPROM.
+ */
+ for (i = 0x8000; i; i >>= 1) {
+ SIO_SET(DM_SIO_EE_CLK);
+ dm_delay(sc);
+ if (CSR_READ_4(sc, DM_SIO) & DM_SIO_EE_DATAOUT)
+ word |= i;
+ dm_delay(sc);
+ SIO_CLR(DM_SIO_EE_CLK);
+ dm_delay(sc);
+ }
+
+ /* Turn off EEPROM access mode. */
+ dm_eeprom_idle(sc);
+
+ *dest = word;
+
+ return;
+}
+
+/*
+ * Read a sequence of words from the EEPROM.
+ */
+static void dm_read_eeprom(sc, dest, off, cnt, swap)
+ struct dm_softc *sc;
+ caddr_t dest;
+ int off;
+ int cnt;
+ int swap;
+{
+ int i;
+ u_int16_t word = 0, *ptr;
+
+ for (i = 0; i < cnt; i++) {
+ dm_eeprom_getword(sc, off + i, &word);
+ ptr = (u_int16_t *)(dest + (i * 2));
+ if (swap)
+ *ptr = ntohs(word);
+ else
+ *ptr = word;
+ }
+
+ return;
+}
+
+/*
+ * Write a bit to the MII bus.
+ */
+static void dm_mii_writebit(sc, bit)
+ struct dm_softc *sc;
+ int bit;
+{
+ if (bit)
+ CSR_WRITE_4(sc, DM_SIO, DM_SIO_ROMCTL_WRITE|DM_SIO_MII_DATAOUT);
+ else
+ CSR_WRITE_4(sc, DM_SIO, DM_SIO_ROMCTL_WRITE);
+
+ DM_SETBIT(sc, DM_SIO, DM_SIO_MII_CLK);
+ DM_CLRBIT(sc, DM_SIO, DM_SIO_MII_CLK);
+
+ return;
+}
+
+/*
+ * Read a bit from the MII bus.
+ */
+static int dm_mii_readbit(sc)
+ struct dm_softc *sc;
+{
+ CSR_WRITE_4(sc, DM_SIO, DM_SIO_ROMCTL_READ|DM_SIO_MII_DIR);
+ CSR_READ_4(sc, DM_SIO);
+ DM_SETBIT(sc, DM_SIO, DM_SIO_MII_CLK);
+ DM_CLRBIT(sc, DM_SIO, DM_SIO_MII_CLK);
+ if (CSR_READ_4(sc, DM_SIO) & DM_SIO_MII_DATAIN)
+ return(1);
+
+ return(0);
+}
+
+/*
+ * Sync the PHYs by setting data bit and strobing the clock 32 times.
+ */
+static void dm_mii_sync(sc)
+ struct dm_softc *sc;
+{
+ register int i;
+
+ CSR_WRITE_4(sc, DM_SIO, DM_SIO_ROMCTL_WRITE);
+
+ for (i = 0; i < 32; i++)
+ dm_mii_writebit(sc, 1);
+
+ return;
+}
+
+/*
+ * Clock a series of bits through the MII.
+ */
+static void dm_mii_send(sc, bits, cnt)
+ struct dm_softc *sc;
+ u_int32_t bits;
+ int cnt;
+{
+ int i;
+
+ for (i = (0x1 << (cnt - 1)); i; i >>= 1)
+ dm_mii_writebit(sc, bits & i);
+}
+
+/*
+ * Read an PHY register through the MII.
+ */
+static int dm_mii_readreg(sc, frame)
+ struct dm_softc *sc;
+ struct dm_mii_frame *frame;
+
+{
+ int i, ack, s;
+
+ s = splimp();
+
+ /*
+ * Set up frame for RX.
+ */
+ frame->mii_stdelim = DM_MII_STARTDELIM;
+ frame->mii_opcode = DM_MII_READOP;
+ frame->mii_turnaround = 0;
+ frame->mii_data = 0;
+
+ /*
+ * Sync the PHYs.
+ */
+ dm_mii_sync(sc);
+
+ /*
+ * Send command/address info.
+ */
+ dm_mii_send(sc, frame->mii_stdelim, 2);
+ dm_mii_send(sc, frame->mii_opcode, 2);
+ dm_mii_send(sc, frame->mii_phyaddr, 5);
+ dm_mii_send(sc, frame->mii_regaddr, 5);
+
+#ifdef notdef
+ /* Idle bit */
+ dm_mii_writebit(sc, 1);
+ dm_mii_writebit(sc, 0);
+#endif
+
+ /* Check for ack */
+ ack = dm_mii_readbit(sc);
+
+ /*
+ * Now try reading data bits. If the ack failed, we still
+ * need to clock through 16 cycles to keep the PHY(s) in sync.
+ */
+ if (ack) {
+ for(i = 0; i < 16; i++) {
+ dm_mii_readbit(sc);
+ }
+ goto fail;
+ }
+
+ for (i = 0x8000; i; i >>= 1) {
+ if (!ack) {
+ if (dm_mii_readbit(sc))
+ frame->mii_data |= i;
+ }
+ }
+
+fail:
+
+ dm_mii_writebit(sc, 0);
+ dm_mii_writebit(sc, 0);
+
+ splx(s);
+
+ if (ack)
+ return(1);
+ return(0);
+}
+
+/*
+ * Write to a PHY register through the MII.
+ */
+static int dm_mii_writereg(sc, frame)
+ struct dm_softc *sc;
+ struct dm_mii_frame *frame;
+
+{
+ int s;
+
+ s = splimp();
+ /*
+ * Set up frame for TX.
+ */
+
+ frame->mii_stdelim = DM_MII_STARTDELIM;
+ frame->mii_opcode = DM_MII_WRITEOP;
+ frame->mii_turnaround = DM_MII_TURNAROUND;
+
+ /*
+ * Sync the PHYs.
+ */
+ dm_mii_sync(sc);
+
+ dm_mii_send(sc, frame->mii_stdelim, 2);
+ dm_mii_send(sc, frame->mii_opcode, 2);
+ dm_mii_send(sc, frame->mii_phyaddr, 5);
+ dm_mii_send(sc, frame->mii_regaddr, 5);
+ dm_mii_send(sc, frame->mii_turnaround, 2);
+ dm_mii_send(sc, frame->mii_data, 16);
+
+ /* Idle bit. */
+ dm_mii_writebit(sc, 0);
+ dm_mii_writebit(sc, 0);
+
+ splx(s);
+
+ return(0);
+}
+
+static int dm_miibus_readreg(dev, phy, reg)
+ device_t dev;
+ int phy, reg;
+{
+ struct dm_softc *sc;
+ struct dm_mii_frame frame;
+
+ sc = device_get_softc(dev);
+ bzero((char *)&frame, sizeof(frame));
+
+ frame.mii_phyaddr = phy;
+ frame.mii_regaddr = reg;
+ dm_mii_readreg(sc, &frame);
+
+ return(frame.mii_data);
+}
+
+static int dm_miibus_writereg(dev, phy, reg, data)
+ device_t dev;
+ int phy, reg, data;
+{
+ struct dm_softc *sc;
+ struct dm_mii_frame frame;
+
+ sc = device_get_softc(dev);
+ bzero((char *)&frame, sizeof(frame));
+
+ frame.mii_phyaddr = phy;
+ frame.mii_regaddr = reg;
+ frame.mii_data = data;
+
+ dm_mii_writereg(sc, &frame);
+
+ return(0);
+}
+
+static void dm_miibus_statchg(dev)
+ device_t dev;
+{
+ struct dm_softc *sc;
+ struct mii_data *mii;
+
+ sc = device_get_softc(dev);
+ mii = device_get_softc(sc->dm_miibus);
+
+ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_SPEEDSEL);
+ else
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_SPEEDSEL);
+
+ if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_FULLDUPLEX);
+ else
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_FULLDUPLEX);
+
+ return;
+}
+
+#define DM_POLY 0xEDB88320
+#define DM_BITS 9
+
+static u_int32_t dm_calchash(addr)
+ caddr_t addr;
+{
+ u_int32_t idx, bit, data, crc;
+
+ /* Compute CRC for the address value. */
+ crc = 0xFFFFFFFF; /* initial value */
+
+ for (idx = 0; idx < 6; idx++) {
+ for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
+ crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DM_POLY : 0);
+ }
+
+ return (crc & ((1 << DM_BITS) - 1));
+}
+
+void dm_setfilt(sc)
+ struct dm_softc *sc;
+{
+ struct dm_desc *sframe;
+ u_int32_t h, *sp;
+ struct ifmultiaddr *ifma;
+ struct ifnet *ifp;
+ int i;
+
+ ifp = &sc->arpcom.ac_if;
+
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_TX_ON);
+ DM_SETBIT(sc, DM_ISR, DM_ISR_TX_IDLE);
+
+ sframe = &sc->dm_ldata->dm_sframe;
+ sp = (u_int32_t *)&sc->dm_cdata.dm_sbuf;
+ bzero((char *)sp, DM_SFRAME_LEN);
+
+ sframe->dm_next = vtophys(&sc->dm_ldata->dm_tx_list[0]);
+ sframe->dm_data = vtophys(&sc->dm_cdata.dm_sbuf);
+ sframe->dm_ctl = DM_SFRAME_LEN | DM_TXCTL_TLINK |
+ DM_TXCTL_SETUP | DM_FILTER_HASHPERF;
+
+ /* If we want promiscuous mode, set the allframes bit. */
+ if (ifp->if_flags & IFF_PROMISC)
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_RX_PROMISC);
+ else
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_RX_PROMISC);
+
+ if (ifp->if_flags & IFF_ALLMULTI)
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_RX_ALLMULTI);
+
+ for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
+ ifma = ifma->ifma_link.le_next) {
+ if (ifma->ifma_addr->sa_family != AF_LINK)
+ continue;
+ h = dm_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
+ sp[h >> 4] |= 1 << (h & 0xF);
+ }
+
+ if (ifp->if_flags & IFF_BROADCAST) {
+ h = dm_calchash((caddr_t)&etherbroadcastaddr);
+ sp[h >> 4] |= 1 << (h & 0xF);
+ }
+
+ sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
+ sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
+ sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
+
+ CSR_WRITE_4(sc, DM_TXADDR, vtophys(sframe));
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_TX_ON);
+ sframe->dm_status = DM_TXSTAT_OWN;
+ CSR_WRITE_4(sc, DM_TXSTART, 0xFFFFFFFF);
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_TX_ON);
+
+ /*
+ * Wait for chip to clear the 'own' bit.
+ */
+ for (i = 0; i < DM_TIMEOUT; i++) {
+ DELAY(10);
+ if (sframe->dm_status != DM_TXSTAT_OWN)
+ break;
+ }
+
+ if (i == DM_TIMEOUT)
+ printf("dm%d: failed to send setup frame\n", sc->dm_unit);
+
+ DM_SETBIT(sc, DM_ISR, DM_ISR_TX_NOBUF|DM_ISR_TX_IDLE);
+
+ return;
+}
+
+static void dm_reset(sc)
+ struct dm_softc *sc;
+{
+ register int i;
+
+ DM_SETBIT(sc, DM_BUSCTL, DM_BUSCTL_RESET);
+
+ for (i = 0; i < DM_TIMEOUT; i++) {
+ DELAY(10);
+ if (!(CSR_READ_4(sc, DM_BUSCTL) & DM_BUSCTL_RESET))
+ break;
+ }
+
+ if (i == DM_TIMEOUT)
+ printf("dm%d: reset never completed!\n", sc->dm_unit);
+
+ CSR_WRITE_4(sc, DM_BUSCTL, 0);
+
+ /* Wait a little while for the chip to get its brains in order. */
+ DELAY(1000);
+ return;
+}
+
+/*
+ * Probe for an Davicom chip. Check the PCI vendor and device
+ * IDs against our list and return a device name if we find a match.
+ */
+static int dm_probe(dev)
+ device_t dev;
+{
+ struct dm_type *t;
+
+ t = dm_devs;
+
+ while(t->dm_name != NULL) {
+ if ((pci_get_vendor(dev) == t->dm_vid) &&
+ (pci_get_device(dev) == t->dm_did)) {
+ device_set_desc(dev, t->dm_name);
+ return(0);
+ }
+ t++;
+ }
+
+ return(ENXIO);
+}
+
+/*
+ * Attach the interface. Allocate softc structures, do ifmedia
+ * setup and ethernet/BPF attach.
+ */
+static int dm_attach(dev)
+ device_t dev;
+{
+ int s;
+ u_char eaddr[ETHER_ADDR_LEN];
+ u_int32_t command;
+ struct dm_softc *sc;
+ struct ifnet *ifp;
+ int unit, error = 0, rid;
+
+ s = splimp();
+
+ sc = device_get_softc(dev);
+ unit = device_get_unit(dev);
+ bzero(sc, sizeof(struct dm_softc));
+
+ /*
+ * Handle power management nonsense.
+ */
+
+ command = pci_read_config(dev, DM_PCI_CAPID, 4) & 0x000000FF;
+ if (command == 0x01) {
+
+ command = pci_read_config(dev, DM_PCI_PWRMGMTCTRL, 4);
+ if (command & DM_PSTATE_MASK) {
+ u_int32_t iobase, membase, irq;
+
+ /* Save important PCI config data. */
+ iobase = pci_read_config(dev, DM_PCI_LOIO, 4);
+ membase = pci_read_config(dev, DM_PCI_LOMEM, 4);
+ irq = pci_read_config(dev, DM_PCI_INTLINE, 4);
+
+ /* Reset the power state. */
+ printf("dm%d: chip is in D%d power mode "
+ "-- setting to D0\n", unit, command & DM_PSTATE_MASK);
+ command &= 0xFFFFFFFC;
+ pci_write_config(dev, DM_PCI_PWRMGMTCTRL, command, 4);
+
+ /* Restore PCI config data. */
+ pci_write_config(dev, DM_PCI_LOIO, iobase, 4);
+ pci_write_config(dev, DM_PCI_LOMEM, membase, 4);
+ pci_write_config(dev, DM_PCI_INTLINE, irq, 4);
+ }
+ }
+
+ /*
+ * Map control/status registers.
+ */
+ command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
+ command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
+ pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4);
+ command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
+
+#ifdef DM_USEIOSPACE
+ if (!(command & PCIM_CMD_PORTEN)) {
+ printf("dm%d: failed to enable I/O ports!\n", unit);
+ error = ENXIO;;
+ goto fail;
+ }
+#else
+ if (!(command & PCIM_CMD_MEMEN)) {
+ printf("dm%d: failed to enable memory mapping!\n", unit);
+ error = ENXIO;;
+ goto fail;
+ }
+#endif
+
+ rid = DM_RID;
+ sc->dm_res = bus_alloc_resource(dev, DM_RES, &rid,
+ 0, ~0, 1, RF_ACTIVE);
+
+ if (sc->dm_res == NULL) {
+ printf("dm%d: couldn't map ports/memory\n", unit);
+ error = ENXIO;
+ goto fail;
+ }
+
+ sc->dm_btag = rman_get_bustag(sc->dm_res);
+ sc->dm_bhandle = rman_get_bushandle(sc->dm_res);
+
+ /* Allocate interrupt */
+ rid = 0;
+ sc->dm_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
+ RF_SHAREABLE | RF_ACTIVE);
+
+ if (sc->dm_irq == NULL) {
+ printf("dm%d: couldn't map interrupt\n", unit);
+ bus_release_resource(dev, DM_RES, DM_RID, sc->dm_res);
+ error = ENXIO;
+ goto fail;
+ }
+
+ error = bus_setup_intr(dev, sc->dm_irq, INTR_TYPE_NET,
+ dm_intr, sc, &sc->dm_intrhand);
+
+ if (error) {
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dm_res);
+ bus_release_resource(dev, DM_RES, DM_RID, sc->dm_res);
+ printf("dm%d: couldn't set up irq\n", unit);
+ goto fail;
+ }
+
+ /* Save the cache line size. */
+ sc->dm_cachesize = pci_read_config(dev, DM_PCI_CACHELEN, 4) & 0xFF;
+
+ /* Reset the adapter. */
+ dm_reset(sc);
+
+ /*
+ * Get station address from the EEPROM.
+ */
+ dm_read_eeprom(sc, (caddr_t)&eaddr, DM_EE_NODEADDR, 3, 0);
+
+ /*
+ * A Davicom chip was detected. Inform the world.
+ */
+ printf("dm%d: Ethernet address: %6D\n", unit, eaddr, ":");
+
+ sc->dm_unit = unit;
+ callout_handle_init(&sc->dm_stat_ch);
+ bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
+
+ sc->dm_ldata = contigmalloc(sizeof(struct dm_list_data), M_DEVBUF,
+ M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
+
+ if (sc->dm_ldata == NULL) {
+ printf("dm%d: no memory for list buffers!\n", unit);
+ bus_teardown_intr(dev, sc->dm_irq, sc->dm_intrhand);
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dm_irq);
+ bus_release_resource(dev, DM_RES, DM_RID, sc->dm_res);
+ error = ENXIO;
+ goto fail;
+ }
+ bzero(sc->dm_ldata, sizeof(struct dm_list_data));
+
+ ifp = &sc->arpcom.ac_if;
+ ifp->if_softc = sc;
+ ifp->if_unit = unit;
+ ifp->if_name = "dm";
+ ifp->if_mtu = ETHERMTU;
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = dm_ioctl;
+ ifp->if_output = ether_output;
+ ifp->if_start = dm_start;
+ ifp->if_watchdog = dm_watchdog;
+ ifp->if_init = dm_init;
+ ifp->if_baudrate = 10000000;
+ ifp->if_snd.ifq_maxlen = DM_TX_LIST_CNT - 1;
+
+ /*
+ * Do MII setup.
+ */
+ if (mii_phy_probe(dev, &sc->dm_miibus,
+ dm_ifmedia_upd, dm_ifmedia_sts)) {
+ printf("dm%d: MII without any PHY!\n", sc->dm_unit);
+ bus_teardown_intr(dev, sc->dm_irq, sc->dm_intrhand);
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dm_irq);
+ bus_release_resource(dev, DM_RES, DM_RID, sc->dm_res);
+ error = ENXIO;
+ goto fail;
+ }
+
+ /*
+ * Call MI attach routines.
+ */
+ if_attach(ifp);
+ ether_ifattach(ifp);
+
+#if NBPF > 0
+ bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
+#endif
+
+fail:
+ splx(s);
+ return(error);
+}
+
+static int dm_detach(dev)
+ device_t dev;
+{
+ struct dm_softc *sc;
+ struct ifnet *ifp;
+ int s;
+
+ s = splimp();
+
+ sc = device_get_softc(dev);
+ ifp = &sc->arpcom.ac_if;
+
+ dm_reset(sc);
+ dm_stop(sc);
+ if_detach(ifp);
+
+ bus_generic_detach(dev);
+ device_delete_child(dev, sc->dm_miibus);
+
+ bus_teardown_intr(dev, sc->dm_irq, sc->dm_intrhand);
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dm_irq);
+ bus_release_resource(dev, DM_RES, DM_RID, sc->dm_res);
+
+ contigfree(sc->dm_ldata, sizeof(struct dm_list_data), M_DEVBUF);
+
+ splx(s);
+
+ return(0);
+}
+
+/*
+ * Initialize the transmit descriptors.
+ */
+static int dm_list_tx_init(sc)
+ struct dm_softc *sc;
+{
+ struct dm_chain_data *cd;
+ struct dm_list_data *ld;
+ int i;
+
+ cd = &sc->dm_cdata;
+ ld = sc->dm_ldata;
+ for (i = 0; i < DM_TX_LIST_CNT; i++) {
+ if (i == (DM_TX_LIST_CNT - 1)) {
+ ld->dm_tx_list[i].dm_nextdesc =
+ &ld->dm_tx_list[0];
+ ld->dm_tx_list[i].dm_next =
+ vtophys(&ld->dm_tx_list[0]);
+ } else {
+ ld->dm_tx_list[i].dm_nextdesc =
+ &ld->dm_tx_list[i + 1];
+ ld->dm_tx_list[i].dm_next =
+ vtophys(&ld->dm_tx_list[i + 1]);
+ }
+ ld->dm_tx_list[i].dm_mbuf = NULL;
+ ld->dm_tx_list[i].dm_data = 0;
+ ld->dm_tx_list[i].dm_ctl = 0;
+ }
+
+ cd->dm_tx_prod = cd->dm_tx_cons = cd->dm_tx_cnt = 0;
+
+ return(0);
+}
+
+
+/*
+ * Initialize the RX descriptors and allocate mbufs for them. Note that
+ * we arrange the descriptors in a closed ring, so that the last descriptor
+ * points back to the first.
+ */
+static int dm_list_rx_init(sc)
+ struct dm_softc *sc;
+{
+ struct dm_chain_data *cd;
+ struct dm_list_data *ld;
+ int i;
+
+ cd = &sc->dm_cdata;
+ ld = sc->dm_ldata;
+
+ for (i = 0; i < DM_RX_LIST_CNT; i++) {
+ if (dm_newbuf(sc, &ld->dm_rx_list[i], NULL) == ENOBUFS)
+ return(ENOBUFS);
+ if (i == (DM_RX_LIST_CNT - 1)) {
+ ld->dm_rx_list[i].dm_nextdesc =
+ &ld->dm_rx_list[0];
+ ld->dm_rx_list[i].dm_next =
+ vtophys(&ld->dm_rx_list[0]);
+ } else {
+ ld->dm_rx_list[i].dm_nextdesc =
+ &ld->dm_rx_list[i + 1];
+ ld->dm_rx_list[i].dm_next =
+ vtophys(&ld->dm_rx_list[i + 1]);
+ }
+ }
+
+ cd->dm_rx_prod = 0;
+
+ return(0);
+}
+
+/*
+ * Initialize an RX descriptor and attach an MBUF cluster.
+ * Note: the length fields are only 11 bits wide, which means the
+ * largest size we can specify is 2047. This is important because
+ * MCLBYTES is 2048, so we have to subtract one otherwise we'll
+ * overflow the field and make a mess.
+ */
+static int dm_newbuf(sc, c, m)
+ struct dm_softc *sc;
+ struct dm_desc *c;
+ struct mbuf *m;
+{
+ struct mbuf *m_new = NULL;
+
+ if (m == NULL) {
+ MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+ if (m_new == NULL) {
+ printf("dm%d: no memory for rx list "
+ "-- packet dropped!\n", sc->dm_unit);
+ return(ENOBUFS);
+ }
+
+ MCLGET(m_new, M_DONTWAIT);
+ if (!(m_new->m_flags & M_EXT)) {
+ printf("dm%d: no memory for rx list "
+ "-- packet dropped!\n", sc->dm_unit);
+ m_freem(m_new);
+ return(ENOBUFS);
+ }
+ m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
+ } else {
+ m_new = m;
+ m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
+ m_new->m_data = m_new->m_ext.ext_buf;
+ }
+
+ m_adj(m_new, sizeof(u_int64_t));
+
+ c->dm_mbuf = m_new;
+ c->dm_data = vtophys(mtod(m_new, caddr_t));
+ c->dm_ctl = DM_RXCTL_RLINK | DM_RXLEN;
+ c->dm_status = DM_RXSTAT_OWN;
+
+ return(0);
+}
+
+/*
+ * A frame has been uploaded: pass the resulting mbuf chain up to
+ * the higher level protocols.
+ */
+static void dm_rxeof(sc)
+ struct dm_softc *sc;
+{
+ struct ether_header *eh;
+ struct mbuf *m;
+ struct ifnet *ifp;
+ struct dm_desc *cur_rx;
+ int i, total_len = 0;
+ u_int32_t rxstat;
+
+ ifp = &sc->arpcom.ac_if;
+ i = sc->dm_cdata.dm_rx_prod;
+
+ while(!(sc->dm_ldata->dm_rx_list[i].dm_status & DM_RXSTAT_OWN)) {
+ struct mbuf *m0 = NULL;
+
+ cur_rx = &sc->dm_ldata->dm_rx_list[i];
+ rxstat = cur_rx->dm_status;
+ m = cur_rx->dm_mbuf;
+ cur_rx->dm_mbuf = NULL;
+ total_len = DM_RXBYTES(rxstat);
+ DM_INC(i, DM_RX_LIST_CNT);
+
+ /*
+ * If an error occurs, update stats, clear the
+ * status word and leave the mbuf cluster in place:
+ * it should simply get re-used next time this descriptor
+ * comes up in the ring.
+ */
+ if (rxstat & DM_RXSTAT_RXERR) {
+ ifp->if_ierrors++;
+ if (rxstat & DM_RXSTAT_COLLSEEN)
+ ifp->if_collisions++;
+ dm_newbuf(sc, cur_rx, m);
+ dm_init(sc);
+ return;
+ }
+
+ /* No errors; receive the packet. */
+ total_len -= ETHER_CRC_LEN;
+
+ m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
+ total_len + ETHER_ALIGN, 0, ifp, NULL);
+ dm_newbuf(sc, cur_rx, m);
+ if (m0 == NULL) {
+ ifp->if_ierrors++;
+ continue;
+ }
+ m_adj(m0, ETHER_ALIGN);
+ m = m0;
+
+ ifp->if_ipackets++;
+ eh = mtod(m, struct ether_header *);
+#if NBPF > 0
+ /*
+ * Handle BPF listeners. Let the BPF user see the packet, but
+ * don't pass it up to the ether_input() layer unless it's
+ * a broadcast packet, multicast packet, matches our ethernet
+ * address or the interface is in promiscuous mode.
+ */
+ if (ifp->if_bpf) {
+ bpf_mtap(ifp, m);
+ if (ifp->if_flags & IFF_PROMISC &&
+ (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
+ ETHER_ADDR_LEN) &&
+ (eh->ether_dhost[0] & 1) == 0)) {
+ m_freem(m);
+ continue;
+ }
+ }
+#endif
+ /* Remove header from mbuf and pass it on. */
+ m_adj(m, sizeof(struct ether_header));
+ ether_input(ifp, eh, m);
+ }
+
+ sc->dm_cdata.dm_rx_prod = i;
+
+ return;
+}
+
+void dm_rxeoc(sc)
+ struct dm_softc *sc;
+{
+ dm_rxeof(sc);
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_RX_ON);
+ CSR_WRITE_4(sc, DM_RXSTART, 0xFFFFFFFF);
+ return;
+}
+
+/*
+ * A frame was downloaded to the chip. It's safe for us to clean up
+ * the list buffers.
+ */
+
+static void dm_txeof(sc)
+ struct dm_softc *sc;
+{
+ struct dm_desc *cur_tx = NULL;
+ struct ifnet *ifp;
+ int idx;
+
+ ifp = &sc->arpcom.ac_if;
+
+ /* Clear the timeout timer. */
+ ifp->if_timer = 0;
+
+ /*
+ * Go through our tx list and free mbufs for those
+ * frames that have been transmitted.
+ */
+ idx = sc->dm_cdata.dm_tx_cons;
+ while(idx != sc->dm_cdata.dm_tx_prod) {
+ u_int32_t txstat;
+
+ cur_tx = &sc->dm_ldata->dm_tx_list[idx];
+ txstat = cur_tx->dm_status;
+
+ if (txstat & DM_TXSTAT_OWN)
+ break;
+
+ if (!(cur_tx->dm_ctl & DM_TXCTL_LASTFRAG)) {
+ sc->dm_cdata.dm_tx_cnt--;
+ DM_INC(idx, DM_TX_LIST_CNT);
+ continue;
+ }
+
+ if (txstat & DM_TXSTAT_ERRSUM) {
+ ifp->if_oerrors++;
+ if (txstat & DM_TXSTAT_EXCESSCOLL)
+ ifp->if_collisions++;
+ if (txstat & DM_TXSTAT_LATECOLL)
+ ifp->if_collisions++;
+ dm_init(sc);
+ return;
+ }
+
+ ifp->if_collisions += (txstat & DM_TXSTAT_COLLCNT) >> 3;
+
+ ifp->if_opackets++;
+ if (cur_tx->dm_mbuf != NULL) {
+ m_freem(cur_tx->dm_mbuf);
+ cur_tx->dm_mbuf = NULL;
+ }
+
+ sc->dm_cdata.dm_tx_cnt--;
+ DM_INC(idx, DM_TX_LIST_CNT);
+ ifp->if_timer = 0;
+ }
+
+ sc->dm_cdata.dm_tx_cons = idx;
+
+ if (cur_tx != NULL)
+ ifp->if_flags &= ~IFF_OACTIVE;
+
+ return;
+}
+
+static void dm_tick(xsc)
+ void *xsc;
+{
+ struct dm_softc *sc;
+ struct mii_data *mii;
+ int s;
+
+ s = splimp();
+
+ sc = xsc;
+ mii = device_get_softc(sc->dm_miibus);
+ mii_tick(mii);
+
+ splx(s);
+
+ return;
+}
+
+static void dm_intr(arg)
+ void *arg;
+{
+ struct dm_softc *sc;
+ struct ifnet *ifp;
+ u_int32_t status;
+
+ sc = arg;
+ ifp = &sc->arpcom.ac_if;
+
+ /* Supress unwanted interrupts */
+ if (!(ifp->if_flags & IFF_UP)) {
+ dm_stop(sc);
+ return;
+ }
+
+ /* Disable interrupts. */
+ CSR_WRITE_4(sc, DM_IMR, 0x00000000);
+
+ for (;;) {
+ status = CSR_READ_4(sc, DM_ISR);
+ if (status)
+ CSR_WRITE_4(sc, DM_ISR, status);
+
+ if ((status & DM_INTRS) == 0)
+ break;
+
+ if ((status & DM_ISR_TX_OK) || (status & DM_ISR_TX_EARLY))
+ dm_txeof(sc);
+
+ if (status & DM_ISR_TX_NOBUF)
+ dm_txeof(sc);
+
+ if (status & DM_ISR_TX_IDLE) {
+ dm_txeof(sc);
+ if (sc->dm_cdata.dm_tx_cnt) {
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_TX_ON);
+ CSR_WRITE_4(sc, DM_TXSTART, 0xFFFFFFFF);
+ }
+ }
+
+ if (status & DM_ISR_TX_UNDERRUN) {
+ u_int32_t cfg;
+ cfg = CSR_READ_4(sc, DM_NETCFG);
+ if ((cfg & DM_NETCFG_TX_THRESH) == DM_TXTHRESH_160BYTES)
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_STORENFWD);
+ else
+ CSR_WRITE_4(sc, DM_NETCFG, cfg + 0x4000);
+ }
+
+ if (status & DM_ISR_RX_OK) {
+ dm_rxeof(sc);
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_RX_ON);
+ CSR_WRITE_4(sc, DM_RXSTART, 0xFFFFFFFF);
+ }
+
+ if ((status & DM_ISR_RX_WATDOGTIMEO)
+ || (status & DM_ISR_RX_NOBUF))
+ dm_rxeoc(sc);
+
+ if (status & DM_ISR_BUS_ERR) {
+ dm_reset(sc);
+ dm_init(sc);
+ }
+ }
+
+ /* Re-enable interrupts. */
+ CSR_WRITE_4(sc, DM_IMR, DM_INTRS);
+
+ if (ifp->if_snd.ifq_head != NULL)
+ dm_start(ifp);
+
+ return;
+}
+
+/*
+ * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
+ * pointers to the fragment pointers.
+ */
+static int dm_encap(sc, m_head, txidx)
+ struct dm_softc *sc;
+ struct mbuf **m_head;
+ u_int32_t *txidx;
+{
+ struct dm_desc *f = NULL;
+ struct mbuf *m;
+ int frag, cur, cnt = 0;
+ struct mbuf *m_new = NULL;
+
+ m = *m_head;
+ MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+ if (m_new == NULL) {
+ printf("dm%d: no memory for tx list", sc->dm_unit);
+ return(ENOBUFS);
+ }
+ if (m->m_pkthdr.len > MHLEN) {
+ MCLGET(m_new, M_DONTWAIT);
+ if (!(m_new->m_flags & M_EXT)) {
+ m_freem(m_new);
+ printf("dm%d: no memory for tx list", sc->dm_unit);
+ return(ENOBUFS);
+ }
+ }
+ m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
+ m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
+ m_freem(m);
+ *m_head = m_new;
+
+ /*
+ * Start packing the mbufs in this chain into
+ * the fragment pointers. Stop when we run out
+ * of fragments or hit the end of the mbuf chain.
+ */
+ cur = frag = *txidx;
+
+ for (m = m_new; m != NULL; m = m->m_next) {
+ if (m->m_len != 0) {
+ if ((DM_RX_LIST_CNT -
+ (sc->dm_cdata.dm_tx_cnt + cnt)) < 2)
+ return(ENOBUFS);
+ f = &sc->dm_ldata->dm_tx_list[frag];
+ f->dm_ctl = DM_TXCTL_TLINK | m->m_len;
+ if (cnt == 0) {
+ f->dm_status = 0;
+ f->dm_ctl |= DM_TXCTL_FIRSTFRAG;
+ } else
+ f->dm_status = DM_TXSTAT_OWN;
+ f->dm_data = vtophys(mtod(m, vm_offset_t));
+ cur = frag;
+ DM_INC(frag, DM_TX_LIST_CNT);
+ cnt++;
+ }
+ }
+
+ if (m != NULL)
+ return(ENOBUFS);
+
+ sc->dm_ldata->dm_tx_list[cur].dm_mbuf = *m_head;
+ sc->dm_ldata->dm_tx_list[cur].dm_ctl |=
+ DM_TXCTL_LASTFRAG|DM_TXCTL_FINT;
+ sc->dm_ldata->dm_tx_list[*txidx].dm_status |= DM_TXSTAT_OWN;
+ sc->dm_cdata.dm_tx_cnt += cnt;
+ *txidx = frag;
+
+ return(0);
+}
+
+/*
+ * Main transmit routine. To avoid having to do mbuf copies, we put pointers
+ * to the mbuf data regions directly in the transmit lists. We also save a
+ * copy of the pointers since the transmit list fragment pointers are
+ * physical addresses.
+ */
+
+static void dm_start(ifp)
+ struct ifnet *ifp;
+{
+ struct dm_softc *sc;
+ struct mbuf *m_head = NULL;
+ u_int32_t idx;
+
+ sc = ifp->if_softc;
+
+ if (ifp->if_flags & IFF_OACTIVE)
+ return;
+
+ idx = sc->dm_cdata.dm_tx_prod;
+
+ while(sc->dm_ldata->dm_tx_list[idx].dm_mbuf == NULL) {
+ IF_DEQUEUE(&ifp->if_snd, m_head);
+ if (m_head == NULL)
+ break;
+
+ if (dm_encap(sc, &m_head, &idx)) {
+ IF_PREPEND(&ifp->if_snd, m_head);
+ ifp->if_flags |= IFF_OACTIVE;
+ break;
+ }
+
+#if NBPF > 0
+ /*
+ * If there's a BPF listener, bounce a copy of this frame
+ * to him.
+ */
+ if (ifp->if_bpf)
+ bpf_mtap(ifp, m_head);
+#endif
+ }
+
+ sc->dm_cdata.dm_tx_prod = idx;
+ CSR_WRITE_4(sc, DM_TXSTART, 0xFFFFFFFF);
+
+ /*
+ * Set a timeout in case the chip goes out to lunch.
+ */
+ ifp->if_timer = 5;
+
+ return;
+}
+
+static void dm_init(xsc)
+ void *xsc;
+{
+ struct dm_softc *sc = xsc;
+ struct ifnet *ifp = &sc->arpcom.ac_if;
+ struct mii_data *mii;
+ int s;
+
+ s = splimp();
+
+ /*
+ * Cancel pending I/O and free all RX/TX buffers.
+ */
+ dm_stop(sc);
+ dm_reset(sc);
+
+ mii = device_get_softc(sc->dm_miibus);
+
+ /*
+ * Set cache alignment and burst length.
+ */
+ CSR_WRITE_4(sc, DM_BUSCTL, DM_BURSTLEN_32LONG);
+ switch(sc->dm_cachesize) {
+ case 32:
+ DM_SETBIT(sc, DM_BUSCTL, DM_CACHEALIGN_32LONG);
+ break;
+ case 16:
+ DM_SETBIT(sc, DM_BUSCTL, DM_CACHEALIGN_16LONG);
+ break;
+ case 8:
+ DM_SETBIT(sc, DM_BUSCTL, DM_CACHEALIGN_8LONG);
+ break;
+ case 0:
+ default:
+ DM_SETBIT(sc, DM_BUSCTL, DM_CACHEALIGN_NONE);
+ break;
+ }
+
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_HEARTBEAT);
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_STORENFWD);
+
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_TX_THRESH);
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_SPEEDSEL);
+
+ if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_10_T)
+ DM_SETBIT(sc, DM_NETCFG, DM_TXTHRESH_160BYTES);
+ else
+ DM_SETBIT(sc, DM_NETCFG, DM_TXTHRESH_72BYTES);
+
+ /* Init circular RX list. */
+ if (dm_list_rx_init(sc) == ENOBUFS) {
+ printf("dm%d: initialization failed: no "
+ "memory for rx buffers\n", sc->dm_unit);
+ dm_stop(sc);
+ (void)splx(s);
+ return;
+ }
+
+ /*
+ * Init tx descriptors.
+ */
+ dm_list_tx_init(sc);
+
+ /* If we want promiscuous mode, set the allframes bit. */
+ if (ifp->if_flags & IFF_PROMISC) {
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_RX_PROMISC);
+ } else {
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_RX_PROMISC);
+ }
+
+ /*
+ * Set the capture broadcast bit to capture broadcast frames.
+ */
+ if (ifp->if_flags & IFF_BROADCAST) {
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_RX_BROAD);
+ } else {
+ DM_CLRBIT(sc, DM_NETCFG, DM_NETCFG_RX_BROAD);
+ }
+
+ /*
+ * Load the RX/multicast filter.
+ */
+ dm_setfilt(sc);
+
+ /*
+ * Load the address of the RX and TX lists.
+ */
+ CSR_WRITE_4(sc, DM_RXADDR, vtophys(&sc->dm_ldata->dm_rx_list[0]));
+ /*CSR_WRITE_4(sc, DM_TXADDR, vtophys(&sc->dm_ldata->dm_tx_list[0]));*/
+
+ /*
+ * Enable interrupts.
+ */
+ CSR_WRITE_4(sc, DM_IMR, DM_INTRS);
+ CSR_WRITE_4(sc, DM_ISR, 0xFFFFFFFF);
+
+ /* Enable receiver and transmitter. */
+ DM_SETBIT(sc, DM_NETCFG, DM_NETCFG_TX_ON|DM_NETCFG_RX_ON);
+ CSR_WRITE_4(sc, DM_RXSTART, 0xFFFFFFFF);
+
+ mii_mediachg(mii);
+
+ ifp->if_flags |= IFF_RUNNING;
+ ifp->if_flags &= ~IFF_OACTIVE;
+
+ (void)splx(s);
+
+ sc->dm_stat_ch = timeout(dm_tick, sc, hz);
+
+ return;
+}
+
+/*
+ * Set media options.
+ */
+static int dm_ifmedia_upd(ifp)
+ struct ifnet *ifp;
+{
+ struct dm_softc *sc;
+
+ sc = ifp->if_softc;
+
+ if (ifp->if_flags & IFF_UP)
+ dm_init(sc);
+
+ return(0);
+}
+
+/*
+ * Report current media status.
+ */
+static void dm_ifmedia_sts(ifp, ifmr)
+ struct ifnet *ifp;
+ struct ifmediareq *ifmr;
+{
+ struct dm_softc *sc;
+ struct mii_data *mii;
+
+ sc = ifp->if_softc;
+
+ mii = device_get_softc(sc->dm_miibus);
+ mii_pollstat(mii);
+ ifmr->ifm_active = mii->mii_media_active;
+ ifmr->ifm_status = mii->mii_media_status;
+
+ return;
+}
+
+static int dm_ioctl(ifp, command, data)
+ struct ifnet *ifp;
+ u_long command;
+ caddr_t data;
+{
+ struct dm_softc *sc = ifp->if_softc;
+ struct ifreq *ifr = (struct ifreq *) data;
+ struct mii_data *mii;
+ int s, error = 0;
+
+ s = splimp();
+
+ switch(command) {
+ case SIOCSIFADDR:
+ case SIOCGIFADDR:
+ case SIOCSIFMTU:
+ error = ether_ioctl(ifp, command, data);
+ break;
+ case SIOCSIFFLAGS:
+ if (ifp->if_flags & IFF_UP) {
+ dm_init(sc);
+ } else {
+ if (ifp->if_flags & IFF_RUNNING)
+ dm_stop(sc);
+ }
+ error = 0;
+ break;
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+ dm_init(sc);
+ error = 0;
+ break;
+ case SIOCGIFMEDIA:
+ case SIOCSIFMEDIA:
+ mii = device_get_softc(sc->dm_miibus);
+ error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
+ break;
+ default:
+ error = EINVAL;
+ break;
+ }
+
+ (void)splx(s);
+
+ return(error);
+}
+
+static void dm_watchdog(ifp)
+ struct ifnet *ifp;
+{
+ struct dm_softc *sc;
+
+ sc = ifp->if_softc;
+
+ ifp->if_oerrors++;
+ printf("dm%d: watchdog timeout\n", sc->dm_unit);
+
+ dm_stop(sc);
+ dm_reset(sc);
+ dm_init(sc);
+
+ if (ifp->if_snd.ifq_head != NULL)
+ dm_start(ifp);
+
+ return;
+}
+
+/*
+ * Stop the adapter and free any mbufs allocated to the
+ * RX and TX lists.
+ */
+static void dm_stop(sc)
+ struct dm_softc *sc;
+{
+ register int i;
+ struct ifnet *ifp;
+
+ ifp = &sc->arpcom.ac_if;
+ ifp->if_timer = 0;
+
+ untimeout(dm_tick, sc, sc->dm_stat_ch);
+
+ DM_CLRBIT(sc, DM_NETCFG, (DM_NETCFG_RX_ON|DM_NETCFG_TX_ON));
+ CSR_WRITE_4(sc, DM_IMR, 0x00000000);
+ CSR_WRITE_4(sc, DM_TXADDR, 0x00000000);
+ CSR_WRITE_4(sc, DM_RXADDR, 0x00000000);
+
+ /*
+ * Free data in the RX lists.
+ */
+ for (i = 0; i < DM_RX_LIST_CNT; i++) {
+ if (sc->dm_ldata->dm_rx_list[i].dm_mbuf != NULL) {
+ m_freem(sc->dm_ldata->dm_rx_list[i].dm_mbuf);
+ sc->dm_ldata->dm_rx_list[i].dm_mbuf = NULL;
+ }
+ }
+ bzero((char *)&sc->dm_ldata->dm_rx_list,
+ sizeof(sc->dm_ldata->dm_rx_list));
+
+ /*
+ * Free the TX list buffers.
+ */
+ for (i = 0; i < DM_TX_LIST_CNT; i++) {
+ if (sc->dm_ldata->dm_tx_list[i].dm_mbuf != NULL) {
+ m_freem(sc->dm_ldata->dm_tx_list[i].dm_mbuf);
+ sc->dm_ldata->dm_tx_list[i].dm_mbuf = NULL;
+ }
+ }
+
+ bzero((char *)&sc->dm_ldata->dm_tx_list,
+ sizeof(sc->dm_ldata->dm_tx_list));
+
+ ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+
+ return;
+}
+
+/*
+ * Stop all chip I/O so that the kernel's probe routines don't
+ * get confused by errant DMAs when rebooting.
+ */
+static void dm_shutdown(dev)
+ device_t dev;
+{
+ struct dm_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ dm_reset(sc);
+ dm_stop(sc);
+
+ return;
+}
diff --git a/sys/pci/if_dmreg.h b/sys/pci/if_dmreg.h
new file mode 100644
index 0000000..2d79ebb
--- /dev/null
+++ b/sys/pci/if_dmreg.h
@@ -0,0 +1,419 @@
+/*
+ * Copyright (c) 1997, 1998, 1999
+ * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * Davicom register definitions.
+ */
+
+#define DM_BUSCTL 0x00 /* bus control */
+#define DM_TXSTART 0x08 /* tx start demand */
+#define DM_RXSTART 0x10 /* rx start demand */
+#define DM_RXADDR 0x18 /* rx descriptor list start addr */
+#define DM_TXADDR 0x20 /* tx descriptor list start addr */
+#define DM_ISR 0x28 /* interrupt status register */
+#define DM_NETCFG 0x30 /* network config register */
+#define DM_IMR 0x38 /* interrupt mask */
+#define DM_FRAMESDISCARDED 0x40 /* # of discarded frames */
+#define DM_SIO 0x48 /* MII and ROM/EEPROM access */
+#define DM_RESERVED 0x50
+#define DM_GENTIMER 0x58 /* general timer */
+#define DM_GENPORT 0x60 /* general purpose port */
+
+/*
+ * Bus control bits.
+ */
+#define DM_BUSCTL_RESET 0x00000001
+#define DM_BUSCTL_ARBITRATION 0x00000002
+#define WB_BUSCTL_SKIPLEN 0x0000007C
+#define DM_BUSCTL_BIGENDIAN 0x00000080
+#define DM_BUSCTL_BURSTLEN 0x00003F00
+#define DM_BUSCTL_CACHEALIGN 0x0000C000
+#define DM_BUSCTL_BUF_BIGENDIAN 0x00100000
+#define DM_BUSCTL_READMULTI 0x00200000
+
+#define DM_SKIPLEN_1LONG 0x00000004
+#define DM_SKIPLEN_2LONG 0x00000008
+#define DM_SKIPLEN_3LONG 0x00000010
+#define DM_SKIPLEN_4LONG 0x00000020
+#define DM_SKIPLEN_5LONG 0x00000040
+
+#define DM_CACHEALIGN_NONE 0x00000000
+#define DM_CACHEALIGN_8LONG 0x00004000
+#define DM_CACHEALIGN_16LONG 0x00008000
+#define DM_CACHEALIGN_32LONG 0x0000C000
+
+#define DM_BURSTLEN_UNLIMIT 0x00000000
+#define DM_BURSTLEN_1LONG 0x00000100
+#define DM_BURSTLEN_2LONG 0x00000200
+#define DM_BURSTLEN_4LONG 0x00000400
+#define DM_BURSTLEN_8LONG 0x00000800
+#define DM_BURSTLEN_16LONG 0x00001000
+#define DM_BURSTLEN_32LONG 0x00002000
+
+/*
+ * Interrupt status bits.
+ */
+#define DM_ISR_TX_OK 0x00000001
+#define DM_ISR_TX_IDLE 0x00000002
+#define DM_ISR_TX_NOBUF 0x00000004
+#define DM_ISR_TX_JABBERTIMEO 0x00000008
+#define DM_ISR_TX_UNDERRUN 0x00000020
+#define DM_ISR_RX_OK 0x00000040
+#define DM_ISR_RX_NOBUF 0x00000080
+#define DM_ISR_RX_IDLE 0x00000100
+#define DM_ISR_RX_WATDOGTIMEO 0x00000200
+#define DM_ISR_TX_EARLY 0x00000400
+#define DM_ISR_TIMER_EXPIRED 0x00000800
+#define DM_ISR_BUS_ERR 0x00002000
+#define DM_ISR_ABNORMAL 0x00008000
+#define DM_ISR_NORMAL 0x00010000
+#define DM_ISR_RX_STATE 0x000E0000
+#define DM_ISR_TX_STATE 0x00700000
+#define DM_ISR_BUSERRTYPE 0x03800000
+
+#define DM_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
+#define DM_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
+#define DM_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
+#define DM_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
+#define DM_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
+#define DM_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
+#define DM_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
+#define DM_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
+
+#define DM_TXSTATE_RESET 0x00000000 /* 000 - reset */
+#define DM_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
+#define DM_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
+#define DM_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
+#define DM_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
+#define DM_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
+#define DM_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
+#define DM_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
+
+/*
+ * Network config bits.
+ */
+#define DM_NETCFG_LINKSTAT_PCS 0x00000001
+#define DM_NETCFG_RX_ON 0x00000002
+#define DM_NETCFG_RX_BADFRAMES 0x00000008
+#define DM_NETCFG_RX_PROMISC 0x00000040
+#define DM_NETCFG_RX_ALLMULTI 0x00000080
+#define DM_NETCFG_RX_BROAD 0x00000100
+#define DM_NETCFG_FULLDUPLEX 0x00000200
+#define DM_NETCFG_LOOPBACK 0x00000C00
+#define DM_NETCFG_FORCECOLL 0x00001000
+#define DM_NETCFG_TX_ON 0x00002000
+#define DM_NETCFG_TX_THRESH 0x0000C000
+#define DM_NETCFG_PORTSEL 0x00040000 /* 0 == SRL, 1 == MII/SYM */
+#define DM_NETCFG_HEARTBEAT 0x00080000 /* 0 == ON, 1 == OFF */
+#define DM_NETCFG_STORENFWD 0x00200000
+#define DM_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
+#define DM_NETCFG_PCS 0x00800000
+#define DM_NETCFG_SCRAMBLER 0x01000000
+#define DM_NETCFG_RX_ALL 0x40000000
+
+#define DM_OPMODE_NORM 0x00000000
+#define DM_OPMODE_INTLOOP 0x00000400
+#define DM_OPMODE_EXTLOOP 0x00000800
+
+#define DM_TXTHRESH_72BYTES 0x00000000
+#define DM_TXTHRESH_96BYTES 0x00004000
+#define DM_TXTHRESH_128BYTES 0x00008000
+#define DM_TXTHRESH_160BYTES 0x0000C000
+
+/*
+ * Interrupt mask bits.
+ */
+#define DM_IMR_TX_OK 0x00000001
+#define DM_IMR_TX_IDLE 0x00000002
+#define DM_IMR_TX_NOBUF 0x00000004
+#define DM_IMR_TX_JABBERTIMEO 0x00000008
+#define DM_IMR_TX_UNDERRUN 0x00000020
+#define DM_IMR_RX_OK 0x00000040
+#define DM_IMR_RX_NOBUF 0x00000080
+#define DM_IMR_RX_IDLE 0x00000100
+#define DM_IMR_RX_WATDOGTIMEO 0x00000200
+#define DM_IMR_TX_EARLY 0x00000400
+#define DM_IMR_TIMER_EXPIRED 0x00000800
+#define DM_IMR_BUS_ERR 0x00002000
+#define DM_IMR_RX_EARLY 0x00004000
+#define DM_IMR_ABNORMAL 0x00008000
+#define DM_IMR_NORMAL 0x00010000
+
+#define DM_INTRS \
+ (DM_IMR_RX_OK|DM_IMR_TX_OK|DM_IMR_RX_NOBUF|DM_IMR_RX_WATDOGTIMEO|\
+ DM_IMR_TX_NOBUF|DM_IMR_TX_UNDERRUN|DM_IMR_BUS_ERR| \
+ DM_IMR_ABNORMAL|DM_IMR_NORMAL|/*DM_IMR_TX_EARLY*/ \
+ DM_IMR_TX_IDLE|DM_IMR_RX_IDLE)
+
+/*
+ * Serial I/O (EEPROM/ROM) bits.
+ */
+#define DM_SIO_EE_CS 0x00000001 /* EEPROM chip select */
+#define DM_SIO_EE_CLK 0x00000002 /* EEPROM clock */
+#define DM_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
+#define DM_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
+#define DM_SIO_EESEL 0x00000800
+#define DM_SIO_ROMSEL 0x00001000
+#define DM_SIO_ROMCTL_WRITE 0x00002000
+#define DM_SIO_ROMCTL_READ 0x00004000
+#define DM_SIO_MII_CLK 0x00010000 /* MDIO clock */
+#define DM_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
+#define DM_SIO_MII_DIR 0x00040000 /* MDIO dir */
+#define DM_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
+
+#define DM_EECMD_WRITE 0x140
+#define DM_EECMD_READ 0x180
+#define DM_EECMD_ERASE 0x1c0
+
+#define DM_EE_NODEADDR_OFFSET 0x70
+#define DM_EE_NODEADDR 10
+
+/*
+ * General purpose timer register
+ */
+#define DM_TIMER_VALUE 0x0000FFFF
+#define DM_TIMER_CONTINUOUS 0x00010000
+
+/*
+ * Size of a setup frame.
+ */
+#define DM_SFRAME_LEN 192
+
+/*
+ * Davicom TX/RX list structure.
+ */
+
+struct dm_desc {
+ u_int32_t dm_status;
+ u_int32_t dm_ctl;
+ u_int32_t dm_ptr1;
+ u_int32_t dm_ptr2;
+ struct mbuf *dm_mbuf;
+ struct dm_desc *dm_nextdesc;
+};
+
+#define dm_data dm_ptr1
+#define dm_next dm_ptr2
+
+#define DM_RXSTAT_FIFOOFLOW 0x00000001
+#define DM_RXSTAT_CRCERR 0x00000002
+#define DM_RXSTAT_DRIBBLE 0x00000004
+#define DM_RXSTAT_WATCHDOG 0x00000010
+#define DM_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
+#define DM_RXSTAT_COLLSEEN 0x00000040
+#define DM_RXSTAT_GIANT 0x00000080
+#define DM_RXSTAT_LASTFRAG 0x00000100
+#define DM_RXSTAT_FIRSTFRAG 0x00000200
+#define DM_RXSTAT_MULTICAST 0x00000400
+#define DM_RXSTAT_RUNT 0x00000800
+#define DM_RXSTAT_RXTYPE 0x00003000
+#define DM_RXSTAT_RXERR 0x00008000
+#define DM_RXSTAT_RXLEN 0x3FFF0000
+#define DM_RXSTAT_OWN 0x80000000
+
+#define DM_RXBYTES(x) ((x & DM_RXSTAT_RXLEN) >> 16)
+#define DM_RXSTAT (DM_RXSTAT_FIRSTFRAG|DM_RXSTAT_LASTFRAG|DM_RXSTAT_OWN)
+
+#define DM_RXCTL_BUFLEN1 0x00000FFF
+#define DM_RXCTL_BUFLEN2 0x00FFF000
+#define DM_RXCTL_RLINK 0x01000000
+#define DM_RXCTL_RLAST 0x02000000
+
+#define DM_TXSTAT_DEFER 0x00000001
+#define DM_TXSTAT_UNDERRUN 0x00000002
+#define DM_TXSTAT_LINKFAIL 0x00000003
+#define DM_TXSTAT_COLLCNT 0x00000078
+#define DM_TXSTAT_SQE 0x00000080
+#define DM_TXSTAT_EXCESSCOLL 0x00000100
+#define DM_TXSTAT_LATECOLL 0x00000200
+#define DM_TXSTAT_NOCARRIER 0x00000400
+#define DM_TXSTAT_CARRLOST 0x00000800
+#define DM_TXSTAT_JABTIMEO 0x00004000
+#define DM_TXSTAT_ERRSUM 0x00008000
+#define DM_TXSTAT_OWN 0x80000000
+
+#define DM_TXCTL_BUFLEN1 0x000007FF
+#define DM_TXCTL_BUFLEN2 0x003FF800
+#define DM_TXCTL_FILTTYPE0 0x00400000
+#define DM_TXCTL_PAD 0x00800000
+#define DM_TXCTL_TLINK 0x01000000
+#define DM_TXCTL_TLAST 0x02000000
+#define DM_TXCTL_NOCRC 0x04000000
+#define DM_TXCTL_SETUP 0x08000000
+#define DM_TXCTL_FILTTYPE1 0x10000000
+#define DM_TXCTL_FIRSTFRAG 0x20000000
+#define DM_TXCTL_LASTFRAG 0x40000000
+#define DM_TXCTL_FINT 0x80000000
+
+#define DM_FILTER_PERFECT 0x00000000
+#define DM_FILTER_HASHPERF 0x00400000
+#define DM_FILTER_INVERSE 0x10000000
+#define DM_FILTER_HASHONLY 0x10400000
+
+#define DM_MAXFRAGS 16
+#define DM_RX_LIST_CNT 64
+#define DM_TX_LIST_CNT 128
+#define DM_MIN_FRAMELEN 60
+#define DM_RXLEN 1536
+
+#define DM_INC(x, y) (x) = (x + 1) % y
+
+struct dm_list_data {
+ struct dm_desc dm_rx_list[DM_RX_LIST_CNT];
+ struct dm_desc dm_tx_list[DM_TX_LIST_CNT];
+ struct dm_desc dm_sframe;
+};
+
+struct dm_chain_data {
+ u_int32_t dm_sbuf[DM_SFRAME_LEN/sizeof(u_int32_t)];
+ u_int8_t dm_pad[DM_MIN_FRAMELEN];
+ int dm_tx_prod;
+ int dm_tx_cons;
+ int dm_tx_cnt;
+ int dm_rx_prod;
+};
+
+struct dm_type {
+ u_int16_t dm_vid;
+ u_int16_t dm_did;
+ char *dm_name;
+};
+
+struct dm_mii_frame {
+ u_int8_t mii_stdelim;
+ u_int8_t mii_opcode;
+ u_int8_t mii_phyaddr;
+ u_int8_t mii_regaddr;
+ u_int8_t mii_turnaround;
+ u_int16_t mii_data;
+};
+
+/*
+ * MII constants
+ */
+#define DM_MII_STARTDELIM 0x01
+#define DM_MII_READOP 0x02
+#define DM_MII_WRITEOP 0x01
+#define DM_MII_TURNAROUND 0x02
+
+struct dm_softc {
+ struct arpcom arpcom; /* interface info */
+ bus_space_handle_t dm_bhandle; /* bus space handle */
+ bus_space_tag_t dm_btag; /* bus space tag */
+ void *dm_intrhand;
+ struct resource *dm_irq;
+ struct resource *dm_res;
+ device_t dm_miibus;
+ u_int8_t dm_unit; /* interface number */
+ int dm_cachesize;
+ struct dm_list_data *dm_ldata;
+ struct dm_chain_data dm_cdata;
+ struct callout_handle dm_stat_ch;
+};
+
+/*
+ * register space access macros
+ */
+#define CSR_WRITE_4(sc, reg, val) \
+ bus_space_write_4(sc->dm_btag, sc->dm_bhandle, reg, val)
+#define CSR_WRITE_2(sc, reg, val) \
+ bus_space_write_2(sc->dm_btag, sc->dm_bbhandle, reg, val)
+#define CSR_WRITE_1(sc, reg, val) \
+ bus_space_write_1(sc->dm_btag, sc->dm_bhandle, reg, val)
+
+#define CSR_READ_4(sc, reg) \
+ bus_space_read_4(sc->dm_btag, sc->dm_bhandle, reg)
+#define CSR_READ_2(sc, reg) \
+ bus_space_read_2(sc->dm_btag, sc->dm_bhandle, reg)
+#define CSR_READ_1(sc, reg) \
+ bus_space_read_1(sc->dm_btag, sc->dm_bhandle, reg)
+
+#define DM_TIMEOUT 1000
+#define ETHER_ALIGN 2
+
+/*
+ * General constants that are fun to know.
+ *
+ * Davicom PCI vendor ID
+ */
+#define DM_VENDORID 0x1282
+
+/*
+ * Davicom DM9102 device ID.
+ */
+#define DM_DEVICEID_DM9102 0x9102
+#define DM_DEVICEID_DM9100 0x9100
+
+/*
+ * PCI low memory base and low I/O base register, and
+ * other PCI registers.
+ */
+
+#define DM_PCI_VENDOR_ID 0x00
+#define DM_PCI_DEVICE_ID 0x02
+#define DM_PCI_COMMAND 0x04
+#define DM_PCI_STATUS 0x06
+#define DM_PCI_REVID 0x08
+#define DM_PCI_CLASSCODE 0x09
+#define DM_PCI_CACHELEN 0x0C
+#define DM_PCI_LATENCY_TIMER 0x0D
+#define DM_PCI_HEADER_TYPE 0x0E
+#define DM_PCI_LOIO 0x10
+#define DM_PCI_LOMEM 0x14
+#define DM_PCI_BIOSROM 0x30
+#define DM_PCI_INTLINE 0x3C
+#define DM_PCI_INTPIN 0x3D
+#define DM_PCI_MINGNT 0x3E
+#define DM_PCI_MINLAT 0x0F
+#define DM_PCI_RESETOPT 0x48
+#define DM_PCI_EEPROM_DATA 0x4C
+
+/* power management registers */
+#define DM_PCI_CAPID 0x50 /* 8 bits */
+#define DM_PCI_NEXTPTR 0x51 /* 8 bits */
+#define DM_PCI_PWRMGMTCAP 0x52 /* 16 bits */
+#define DM_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
+
+#define DM_PSTATE_MASK 0x0003
+#define DM_PSTATE_D0 0x0000
+#define DM_PSTATE_D1 0x0001
+#define DM_PSTATE_D2 0x0002
+#define DM_PSTATE_D3 0x0003
+#define DM_PME_EN 0x0010
+#define DM_PME_STATUS 0x8000
+
+#ifdef __alpha__
+#undef vtophys
+#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
+#endif
diff --git a/usr.sbin/sade/devices.c b/usr.sbin/sade/devices.c
index 878e4e8..7269b69 100644
--- a/usr.sbin/sade/devices.c
+++ b/usr.sbin/sade/devices.c
@@ -89,6 +89,7 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "cc3i", "SDL HSSI sync serial PCI card" },
{ DEVICE_TYPE_NETWORK, "en", "Efficient Networks ATM PCI card" },
{ DEVICE_TYPE_NETWORK, "de", "DEC DE435 PCI NIC or other DC21040-AA based card" },
+ { DEVICE_TYPE_NETWORK, "dm", "Davicom DM9100/DM9102 PCI fast ethernet card" },
{ DEVICE_TYPE_NETWORK, "fxp", "Intel EtherExpress Pro/100B PCI Fast Ethernet card" },
{ DEVICE_TYPE_NETWORK, "ed", "Novell NE1000/2000; 3C503; NE2000-compatible PCMCIA" },
{ DEVICE_TYPE_NETWORK, "ep", "3Com 3C509 ethernet card/3C589 PCMCIA" },
diff --git a/usr.sbin/sysinstall/devices.c b/usr.sbin/sysinstall/devices.c
index 878e4e8..7269b69 100644
--- a/usr.sbin/sysinstall/devices.c
+++ b/usr.sbin/sysinstall/devices.c
@@ -89,6 +89,7 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "cc3i", "SDL HSSI sync serial PCI card" },
{ DEVICE_TYPE_NETWORK, "en", "Efficient Networks ATM PCI card" },
{ DEVICE_TYPE_NETWORK, "de", "DEC DE435 PCI NIC or other DC21040-AA based card" },
+ { DEVICE_TYPE_NETWORK, "dm", "Davicom DM9100/DM9102 PCI fast ethernet card" },
{ DEVICE_TYPE_NETWORK, "fxp", "Intel EtherExpress Pro/100B PCI Fast Ethernet card" },
{ DEVICE_TYPE_NETWORK, "ed", "Novell NE1000/2000; 3C503; NE2000-compatible PCMCIA" },
{ DEVICE_TYPE_NETWORK, "ep", "3Com 3C509 ethernet card/3C589 PCMCIA" },
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