diff options
| -rw-r--r-- | sys/mips/atheros/ar71xx_machdep.c | 11 | ||||
| -rw-r--r-- | sys/mips/atheros/ar71xxreg.h | 54 | ||||
| -rw-r--r-- | sys/mips/atheros/uart_bus_ar71xx.c | 13 | ||||
| -rw-r--r-- | sys/mips/atheros/uart_cpu_ar71xx.c | 13 |
4 files changed, 53 insertions, 38 deletions
diff --git a/sys/mips/atheros/ar71xx_machdep.c b/sys/mips/atheros/ar71xx_machdep.c index a120959..6ca395a 100644 --- a/sys/mips/atheros/ar71xx_machdep.c +++ b/sys/mips/atheros/ar71xx_machdep.c @@ -100,8 +100,8 @@ platform_start(__register_t a0 __unused, __register_t a1 __unused, __register_t a2 __unused, __register_t a3 __unused) { vm_offset_t kernend; - uint64_t platform_counter_freq, freq; - uint32_t reg, div, pll_config; + uint64_t platform_counter_freq; + uint32_t reg; int argc, i, count = 0; char **argv, **envp; @@ -151,12 +151,7 @@ platform_start(__register_t a0 __unused, __register_t a1 __unused, * should be called first. */ init_param1(); - pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG); - div = ((pll_config >> PLL_FB_SHIFT) & PLL_FB_MASK) + 1; - freq = div * AR71XX_BASE_FREQ; - div = ((pll_config >> PLL_CPU_DIV_SEL_SHIFT) & PLL_CPU_DIV_SEL_MASK) - + 1; - platform_counter_freq = freq / div; + platform_counter_freq = ar71xx_cpu_freq(); mips_timer_init_params(platform_counter_freq, 1); cninit(); diff --git a/sys/mips/atheros/ar71xxreg.h b/sys/mips/atheros/ar71xxreg.h index 33ae55c..cc331d4 100644 --- a/sys/mips/atheros/ar71xxreg.h +++ b/sys/mips/atheros/ar71xxreg.h @@ -26,12 +26,6 @@ #ifndef _AR71XX_REG_H_ #define _AR71XX_REG_H_ -#define ATH_READ_REG(reg) \ - *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) - -#define ATH_WRITE_REG(reg, val) \ - *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val) - /* PCI region */ #define AR71XX_PCI_MEM_BASE 0x10000000 /* @@ -174,6 +168,15 @@ #define AR71XX_PLL_ETH_EXT_CLK 0x18050018 #define AR71XX_PLL_PCI_CLK 0x1805001C +#define AR71XX_RST_WDOG_CONTROL 0x18060008 +#define RST_WDOG_LAST (1 << 31) +#define RST_WDOG_ACTION_MASK 3 +#define RST_WDOG_ACTION_RESET 3 +#define RST_WDOG_ACTION_NMI 2 +#define RST_WDOG_ACTION_GP_INTR 1 +#define RST_WDOG_ACTION_NOACTION 0 + +#define AR71XX_RST_WDOG_TIMER 0x1806000C /* * APB interrupt status and mask register and interrupt bit numbers for */ @@ -419,4 +422,43 @@ #define SPI_IO_CTRL_DO 1 #define AR71XX_SPI_RDS 0x0C +#define ATH_READ_REG(reg) \ + *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) + +#define ATH_WRITE_REG(reg, val) \ + *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val) + +static inline uint64_t +ar71xx_cpu_freq(void) +{ + uint32_t pll_config, div; + uint64_t freq; + + /* PLL freq */ + pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG); + div = ((pll_config >> PLL_FB_SHIFT) & PLL_FB_MASK) + 1; + freq = div * AR71XX_BASE_FREQ; + /* CPU freq */ + div = ((pll_config >> PLL_CPU_DIV_SEL_SHIFT) & PLL_CPU_DIV_SEL_MASK) + + 1; + freq = freq / div; + + return (freq); +} + +static inline uint64_t +ar71xx_ahb_freq(void) +{ + uint32_t pll_config, div; + uint64_t freq; + + /* PLL freq */ + pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG); + /* AHB freq */ + div = (((pll_config >> PLL_AHB_DIV_SHIFT) & PLL_AHB_DIV_MASK) + 1) * 2; + freq = ar71xx_cpu_freq() / div; + return (freq); +} + + #endif /* _AR71XX_REG_H_ */ diff --git a/sys/mips/atheros/uart_bus_ar71xx.c b/sys/mips/atheros/uart_bus_ar71xx.c index 380c3da..8d83291 100644 --- a/sys/mips/atheros/uart_bus_ar71xx.c +++ b/sys/mips/atheros/uart_bus_ar71xx.c @@ -67,20 +67,9 @@ static int uart_ar71xx_probe(device_t dev) { struct uart_softc *sc; - uint32_t pll_config, div; uint64_t freq; - /* PLL freq */ - pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG); - div = ((pll_config >> PLL_FB_SHIFT) & PLL_FB_MASK) + 1; - freq = div * AR71XX_BASE_FREQ; - /* CPU freq */ - div = ((pll_config >> PLL_CPU_DIV_SEL_SHIFT) & PLL_CPU_DIV_SEL_MASK) - + 1; - freq = freq / div; - /* AHB freq */ - div = (((pll_config >> PLL_AHB_DIV_SHIFT) & PLL_AHB_DIV_MASK) + 1) * 2; - freq = freq / div; + freq = ar71xx_ahb_freq(); sc = device_get_softc(dev); sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); diff --git a/sys/mips/atheros/uart_cpu_ar71xx.c b/sys/mips/atheros/uart_cpu_ar71xx.c index 67b5d98..4528ac6 100644 --- a/sys/mips/atheros/uart_cpu_ar71xx.c +++ b/sys/mips/atheros/uart_cpu_ar71xx.c @@ -53,20 +53,9 @@ uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) int uart_cpu_getdev(int devtype, struct uart_devinfo *di) { - uint32_t pll_config, div; uint64_t freq; - /* PLL freq */ - pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG); - div = ((pll_config >> PLL_FB_SHIFT) & PLL_FB_MASK) + 1; - freq = div * AR71XX_BASE_FREQ; - /* CPU freq */ - div = ((pll_config >> PLL_CPU_DIV_SEL_SHIFT) & PLL_CPU_DIV_SEL_MASK) - + 1; - freq = freq / div; - /* AHB freq */ - div = (((pll_config >> PLL_AHB_DIV_SHIFT) & PLL_AHB_DIV_MASK) + 1) * 2; - freq = freq / div; + freq = ar71xx_ahb_freq(); di->ops = uart_getops(&uart_ns8250_class); di->bas.chan = 0; |
